Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 10:54:00.406238 lava-dispatcher, installed at version: 2023.05.1
2 10:54:00.406437 start: 0 validate
3 10:54:00.406558 Start time: 2023-06-05 10:54:00.406550+00:00 (UTC)
4 10:54:00.406675 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:54:00.406806 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:54:00.690566 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:54:00.691314 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:54:00.988079 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:54:00.988848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:54:01.278212 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:54:01.278937 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:54:01.578279 validate duration: 1.17
14 10:54:01.578552 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:54:01.578651 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:54:01.578741 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:54:01.578875 Not decompressing ramdisk as can be used compressed.
18 10:54:01.578965 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 10:54:01.579032 saving as /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/ramdisk/rootfs.cpio.gz
20 10:54:01.579096 total size: 8186575 (7MB)
21 10:54:01.580114 progress 0% (0MB)
22 10:54:01.582303 progress 5% (0MB)
23 10:54:01.584296 progress 10% (0MB)
24 10:54:01.586447 progress 15% (1MB)
25 10:54:01.588433 progress 20% (1MB)
26 10:54:01.590578 progress 25% (1MB)
27 10:54:01.592557 progress 30% (2MB)
28 10:54:01.594701 progress 35% (2MB)
29 10:54:01.596674 progress 40% (3MB)
30 10:54:01.598846 progress 45% (3MB)
31 10:54:01.600833 progress 50% (3MB)
32 10:54:01.602952 progress 55% (4MB)
33 10:54:01.604904 progress 60% (4MB)
34 10:54:01.607006 progress 65% (5MB)
35 10:54:01.608957 progress 70% (5MB)
36 10:54:01.611049 progress 75% (5MB)
37 10:54:01.613031 progress 80% (6MB)
38 10:54:01.615121 progress 85% (6MB)
39 10:54:01.617068 progress 90% (7MB)
40 10:54:01.619166 progress 95% (7MB)
41 10:54:01.621131 progress 100% (7MB)
42 10:54:01.621340 7MB downloaded in 0.04s (184.83MB/s)
43 10:54:01.621483 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:54:01.621722 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:54:01.621808 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:54:01.621892 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:54:01.622020 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:54:01.622094 saving as /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/kernel/Image
50 10:54:01.622154 total size: 45746688 (43MB)
51 10:54:01.622214 No compression specified
52 10:54:01.623300 progress 0% (0MB)
53 10:54:01.634460 progress 5% (2MB)
54 10:54:01.645847 progress 10% (4MB)
55 10:54:01.657273 progress 15% (6MB)
56 10:54:01.668619 progress 20% (8MB)
57 10:54:01.679841 progress 25% (10MB)
58 10:54:01.690822 progress 30% (13MB)
59 10:54:01.701920 progress 35% (15MB)
60 10:54:01.713048 progress 40% (17MB)
61 10:54:01.724155 progress 45% (19MB)
62 10:54:01.735295 progress 50% (21MB)
63 10:54:01.746365 progress 55% (24MB)
64 10:54:01.757857 progress 60% (26MB)
65 10:54:01.769191 progress 65% (28MB)
66 10:54:01.780385 progress 70% (30MB)
67 10:54:01.791503 progress 75% (32MB)
68 10:54:01.802494 progress 80% (34MB)
69 10:54:01.813616 progress 85% (37MB)
70 10:54:01.824681 progress 90% (39MB)
71 10:54:01.835677 progress 95% (41MB)
72 10:54:01.846618 progress 100% (43MB)
73 10:54:01.846731 43MB downloaded in 0.22s (194.27MB/s)
74 10:54:01.846876 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:54:01.847109 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:54:01.847204 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:54:01.847300 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:54:01.847440 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:54:01.847512 saving as /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/dtb/mt8192-asurada-spherion-r0.dtb
81 10:54:01.847574 total size: 46924 (0MB)
82 10:54:01.847634 No compression specified
83 10:54:01.848759 progress 69% (0MB)
84 10:54:01.849073 progress 100% (0MB)
85 10:54:01.849258 0MB downloaded in 0.00s (26.63MB/s)
86 10:54:01.849392 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:54:01.849615 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:54:01.849700 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:54:01.849785 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:54:01.849895 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:54:01.849969 saving as /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/modules/modules.tar
93 10:54:01.850030 total size: 8542412 (8MB)
94 10:54:01.850090 Using unxz to decompress xz
95 10:54:01.853614 progress 0% (0MB)
96 10:54:01.874709 progress 5% (0MB)
97 10:54:01.898857 progress 10% (0MB)
98 10:54:01.923965 progress 15% (1MB)
99 10:54:01.947669 progress 20% (1MB)
100 10:54:01.973027 progress 25% (2MB)
101 10:54:01.997332 progress 30% (2MB)
102 10:54:02.021360 progress 35% (2MB)
103 10:54:02.045033 progress 40% (3MB)
104 10:54:02.069520 progress 45% (3MB)
105 10:54:02.092933 progress 50% (4MB)
106 10:54:02.115205 progress 55% (4MB)
107 10:54:02.139055 progress 60% (4MB)
108 10:54:02.163258 progress 65% (5MB)
109 10:54:02.187592 progress 70% (5MB)
110 10:54:02.213814 progress 75% (6MB)
111 10:54:02.242078 progress 80% (6MB)
112 10:54:02.263905 progress 85% (6MB)
113 10:54:02.287980 progress 90% (7MB)
114 10:54:02.310652 progress 95% (7MB)
115 10:54:02.333759 progress 100% (8MB)
116 10:54:02.339227 8MB downloaded in 0.49s (16.65MB/s)
117 10:54:02.339495 end: 1.4.1 http-download (duration 00:00:00) [common]
119 10:54:02.339754 end: 1.4 download-retry (duration 00:00:00) [common]
120 10:54:02.339848 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:54:02.339945 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:54:02.340026 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:54:02.340114 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:54:02.340335 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy
125 10:54:02.340468 makedir: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin
126 10:54:02.340576 makedir: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/tests
127 10:54:02.340675 makedir: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/results
128 10:54:02.340793 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-add-keys
129 10:54:02.340942 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-add-sources
130 10:54:02.341070 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-background-process-start
131 10:54:02.341201 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-background-process-stop
132 10:54:02.341325 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-common-functions
133 10:54:02.341449 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-echo-ipv4
134 10:54:02.341574 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-install-packages
135 10:54:02.341696 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-installed-packages
136 10:54:02.341818 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-os-build
137 10:54:02.341940 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-probe-channel
138 10:54:02.342061 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-probe-ip
139 10:54:02.342182 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-target-ip
140 10:54:02.342301 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-target-mac
141 10:54:02.342421 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-target-storage
142 10:54:02.342545 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-case
143 10:54:02.342665 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-event
144 10:54:02.342786 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-feedback
145 10:54:02.342906 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-raise
146 10:54:02.343028 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-reference
147 10:54:02.343149 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-runner
148 10:54:02.343270 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-set
149 10:54:02.343391 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-test-shell
150 10:54:02.343514 Updating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-install-packages (oe)
151 10:54:02.343665 Updating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/bin/lava-installed-packages (oe)
152 10:54:02.343787 Creating /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/environment
153 10:54:02.343886 LAVA metadata
154 10:54:02.343959 - LAVA_JOB_ID=10591035
155 10:54:02.344024 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:54:02.344125 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:54:02.344194 skipped lava-vland-overlay
158 10:54:02.344269 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:54:02.344352 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:54:02.344417 skipped lava-multinode-overlay
161 10:54:02.344497 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:54:02.344589 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:54:02.344664 Loading test definitions
164 10:54:02.344755 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:54:02.344875 Using /lava-10591035 at stage 0
166 10:54:02.345193 uuid=10591035_1.5.2.3.1 testdef=None
167 10:54:02.345282 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:54:02.345367 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:54:02.345892 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:54:02.346116 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:54:02.346766 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:54:02.346999 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:54:02.347613 runner path: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/0/tests/0_dmesg test_uuid 10591035_1.5.2.3.1
176 10:54:02.347772 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:54:02.348014 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 10:54:02.348087 Using /lava-10591035 at stage 1
180 10:54:02.348396 uuid=10591035_1.5.2.3.5 testdef=None
181 10:54:02.348486 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 10:54:02.348570 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 10:54:02.349087 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 10:54:02.349303 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 10:54:02.350478 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 10:54:02.350709 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 10:54:02.351327 runner path: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/1/tests/1_bootrr test_uuid 10591035_1.5.2.3.5
190 10:54:02.351478 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 10:54:02.351685 Creating lava-test-runner.conf files
193 10:54:02.351750 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/0 for stage 0
194 10:54:02.351839 - 0_dmesg
195 10:54:02.351920 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591035/lava-overlay-owd0cmpy/lava-10591035/1 for stage 1
196 10:54:02.352069 - 1_bootrr
197 10:54:02.352163 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 10:54:02.352249 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 10:54:02.360011 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 10:54:02.360116 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 10:54:02.360203 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 10:54:02.360290 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 10:54:02.360375 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 10:54:02.586325 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 10:54:02.586681 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 10:54:02.586800 extracting modules file /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591035/extract-overlay-ramdisk-qa9dkaob/ramdisk
207 10:54:02.785819 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 10:54:02.785991 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 10:54:02.786092 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591035/compress-overlay-fllpwbpy/overlay-1.5.2.4.tar.gz to ramdisk
210 10:54:02.786164 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591035/compress-overlay-fllpwbpy/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591035/extract-overlay-ramdisk-qa9dkaob/ramdisk
211 10:54:02.794032 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 10:54:02.794164 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 10:54:02.794300 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 10:54:02.794387 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 10:54:02.794469 Building ramdisk /var/lib/lava/dispatcher/tmp/10591035/extract-overlay-ramdisk-qa9dkaob/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591035/extract-overlay-ramdisk-qa9dkaob/ramdisk
216 10:54:03.150853 >> 143713 blocks
217 10:54:05.352727 rename /var/lib/lava/dispatcher/tmp/10591035/extract-overlay-ramdisk-qa9dkaob/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/ramdisk/ramdisk.cpio.gz
218 10:54:05.353193 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 10:54:05.353319 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 10:54:05.353421 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 10:54:05.353529 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/kernel/Image'
222 10:54:16.412217 Returned 0 in 11 seconds
223 10:54:16.513086 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/kernel/image.itb
224 10:54:16.918524 output: FIT description: Kernel Image image with one or more FDT blobs
225 10:54:16.918862 output: Created: Mon Jun 5 11:54:16 2023
226 10:54:16.918936 output: Image 0 (kernel-1)
227 10:54:16.919004 output: Description:
228 10:54:16.919068 output: Created: Mon Jun 5 11:54:16 2023
229 10:54:16.919132 output: Type: Kernel Image
230 10:54:16.919194 output: Compression: lzma compressed
231 10:54:16.919254 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
232 10:54:16.919315 output: Architecture: AArch64
233 10:54:16.919375 output: OS: Linux
234 10:54:16.919429 output: Load Address: 0x00000000
235 10:54:16.919505 output: Entry Point: 0x00000000
236 10:54:16.919575 output: Hash algo: crc32
237 10:54:16.919629 output: Hash value: 8ce42972
238 10:54:16.919682 output: Image 1 (fdt-1)
239 10:54:16.919736 output: Description: mt8192-asurada-spherion-r0
240 10:54:16.919789 output: Created: Mon Jun 5 11:54:16 2023
241 10:54:16.919843 output: Type: Flat Device Tree
242 10:54:16.919896 output: Compression: uncompressed
243 10:54:16.919949 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 10:54:16.920003 output: Architecture: AArch64
245 10:54:16.920056 output: Hash algo: crc32
246 10:54:16.920109 output: Hash value: 1df858fa
247 10:54:16.920163 output: Image 2 (ramdisk-1)
248 10:54:16.920216 output: Description: unavailable
249 10:54:16.920269 output: Created: Mon Jun 5 11:54:16 2023
250 10:54:16.920322 output: Type: RAMDisk Image
251 10:54:16.920376 output: Compression: Unknown Compression
252 10:54:16.920429 output: Data Size: 21229014 Bytes = 20731.46 KiB = 20.25 MiB
253 10:54:16.920483 output: Architecture: AArch64
254 10:54:16.920536 output: OS: Linux
255 10:54:16.920590 output: Load Address: unavailable
256 10:54:16.920643 output: Entry Point: unavailable
257 10:54:16.920696 output: Hash algo: crc32
258 10:54:16.920749 output: Hash value: ae4847ff
259 10:54:16.920840 output: Default Configuration: 'conf-1'
260 10:54:16.920894 output: Configuration 0 (conf-1)
261 10:54:16.920947 output: Description: mt8192-asurada-spherion-r0
262 10:54:16.921000 output: Kernel: kernel-1
263 10:54:16.921053 output: Init Ramdisk: ramdisk-1
264 10:54:16.921106 output: FDT: fdt-1
265 10:54:16.921159 output: Loadables: kernel-1
266 10:54:16.921211 output:
267 10:54:16.921397 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 10:54:16.921554 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 10:54:16.921659 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
270 10:54:16.921751 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:45) [common]
271 10:54:16.921831 No LXC device requested
272 10:54:16.921908 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 10:54:16.921995 start: 1.7 deploy-device-env (timeout 00:09:45) [common]
274 10:54:16.922072 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 10:54:16.922138 Checking files for TFTP limit of 4294967296 bytes.
276 10:54:16.922630 end: 1 tftp-deploy (duration 00:00:15) [common]
277 10:54:16.922739 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 10:54:16.922834 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 10:54:16.922959 substitutions:
280 10:54:16.923026 - {DTB}: 10591035/tftp-deploy-zdi7ijol/dtb/mt8192-asurada-spherion-r0.dtb
281 10:54:16.923089 - {INITRD}: 10591035/tftp-deploy-zdi7ijol/ramdisk/ramdisk.cpio.gz
282 10:54:16.923148 - {KERNEL}: 10591035/tftp-deploy-zdi7ijol/kernel/Image
283 10:54:16.923206 - {LAVA_MAC}: None
284 10:54:16.923262 - {PRESEED_CONFIG}: None
285 10:54:16.923318 - {PRESEED_LOCAL}: None
286 10:54:16.923388 - {RAMDISK}: 10591035/tftp-deploy-zdi7ijol/ramdisk/ramdisk.cpio.gz
287 10:54:16.923457 - {ROOT_PART}: None
288 10:54:16.923528 - {ROOT}: None
289 10:54:16.923595 - {SERVER_IP}: 192.168.201.1
290 10:54:16.923649 - {TEE}: None
291 10:54:16.923705 Parsed boot commands:
292 10:54:16.923759 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 10:54:16.923930 Parsed boot commands: tftpboot 192.168.201.1 10591035/tftp-deploy-zdi7ijol/kernel/image.itb 10591035/tftp-deploy-zdi7ijol/kernel/cmdline
294 10:54:16.924019 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 10:54:16.924109 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 10:54:16.924200 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 10:54:16.924286 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 10:54:16.924365 Not connected, no need to disconnect.
299 10:54:16.924442 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 10:54:16.924532 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 10:54:16.924606 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
302 10:54:16.928250 Setting prompt string to ['lava-test: # ']
303 10:54:16.928770 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 10:54:16.928901 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 10:54:16.928998 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 10:54:16.929114 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 10:54:16.929316 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 10:54:22.076433 >> Command sent successfully.
309 10:54:22.082745 Returned 0 in 5 seconds
310 10:54:22.183494 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 10:54:22.185356 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 10:54:22.185897 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 10:54:22.186382 Setting prompt string to 'Starting depthcharge on Spherion...'
315 10:54:22.186769 Changing prompt to 'Starting depthcharge on Spherion...'
316 10:54:22.187264 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 10:54:22.188485 [Enter `^Ec?' for help]
318 10:54:22.353785
319 10:54:22.354382
320 10:54:22.354848 F0: 102B 0000
321 10:54:22.355193
322 10:54:22.355540 F3: 1001 0000 [0200]
323 10:54:22.357337
324 10:54:22.357773 F3: 1001 0000
325 10:54:22.358151
326 10:54:22.358545 F7: 102D 0000
327 10:54:22.358869
328 10:54:22.360336 F1: 0000 0000
329 10:54:22.360804
330 10:54:22.361165 V0: 0000 0000 [0001]
331 10:54:22.361529
332 10:54:22.363861 00: 0007 8000
333 10:54:22.364317
334 10:54:22.364665 01: 0000 0000
335 10:54:22.365026
336 10:54:22.367229 BP: 0C00 0209 [0000]
337 10:54:22.367666
338 10:54:22.368012 G0: 1182 0000
339 10:54:22.368337
340 10:54:22.370852 EC: 0000 0021 [4000]
341 10:54:22.371290
342 10:54:22.371636 S7: 0000 0000 [0000]
343 10:54:22.371958
344 10:54:22.374489 CC: 0000 0000 [0001]
345 10:54:22.375044
346 10:54:22.375405 T0: 0000 0040 [010F]
347 10:54:22.375737
348 10:54:22.376085 Jump to BL
349 10:54:22.377260
350 10:54:22.400930
351 10:54:22.401451
352 10:54:22.401801
353 10:54:22.407811 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 10:54:22.411224 ARM64: Exception handlers installed.
355 10:54:22.414373 ARM64: Testing exception
356 10:54:22.417871 ARM64: Done test exception
357 10:54:22.424057 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 10:54:22.434279 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 10:54:22.441109 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 10:54:22.451905 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 10:54:22.458560 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 10:54:22.468946 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 10:54:22.478799 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 10:54:22.485688 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 10:54:22.503481 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 10:54:22.506881 WDT: Last reset was cold boot
367 10:54:22.510241 SPI1(PAD0) initialized at 2873684 Hz
368 10:54:22.513405 SPI5(PAD0) initialized at 992727 Hz
369 10:54:22.516679 VBOOT: Loading verstage.
370 10:54:22.523568 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 10:54:22.527157 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 10:54:22.530543 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 10:54:22.533527 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 10:54:22.540931 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 10:54:22.548213 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 10:54:22.558572 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 10:54:22.559016
378 10:54:22.559359
379 10:54:22.568691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 10:54:22.571862 ARM64: Exception handlers installed.
381 10:54:22.575263 ARM64: Testing exception
382 10:54:22.578860 ARM64: Done test exception
383 10:54:22.582000 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 10:54:22.585414 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 10:54:22.599878 Probing TPM: . done!
386 10:54:22.600419 TPM ready after 0 ms
387 10:54:22.606326 Connected to device vid:did:rid of 1ae0:0028:00
388 10:54:22.613497 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 10:54:22.671466 Initialized TPM device CR50 revision 0
390 10:54:22.683626 tlcl_send_startup: Startup return code is 0
391 10:54:22.684101 TPM: setup succeeded
392 10:54:22.695131 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 10:54:22.703771 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 10:54:22.711248 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 10:54:22.722929 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 10:54:22.726498 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 10:54:22.733411 in-header: 03 07 00 00 08 00 00 00
398 10:54:22.736937 in-data: aa e4 47 04 13 02 00 00
399 10:54:22.740622 Chrome EC: UHEPI supported
400 10:54:22.747394 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 10:54:22.751197 in-header: 03 ad 00 00 08 00 00 00
402 10:54:22.755019 in-data: 00 20 20 08 00 00 00 00
403 10:54:22.755454 Phase 1
404 10:54:22.758724 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 10:54:22.765943 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 10:54:22.769816 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 10:54:22.773287 Recovery requested (1009000e)
408 10:54:22.785070 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 10:54:22.789255 tlcl_extend: response is 0
410 10:54:22.798453 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 10:54:22.804390 tlcl_extend: response is 0
412 10:54:22.811226 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 10:54:22.831602 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 10:54:22.838598 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 10:54:22.839052
416 10:54:22.839396
417 10:54:22.849056 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 10:54:22.851465 ARM64: Exception handlers installed.
419 10:54:22.855176 ARM64: Testing exception
420 10:54:22.855793 ARM64: Done test exception
421 10:54:22.876925 pmic_efuse_setting: Set efuses in 11 msecs
422 10:54:22.880528 pmwrap_interface_init: Select PMIF_VLD_RDY
423 10:54:22.887639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 10:54:22.890268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 10:54:22.897098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 10:54:22.900816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 10:54:22.904825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 10:54:22.911743 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 10:54:22.914980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 10:54:22.918502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 10:54:22.925458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 10:54:22.928982 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 10:54:22.932876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 10:54:22.939426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 10:54:22.943428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 10:54:22.949680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 10:54:22.956287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 10:54:22.959587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 10:54:22.967297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 10:54:22.970934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 10:54:22.977571 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 10:54:22.984245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 10:54:22.988053 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 10:54:22.995515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 10:54:22.998670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 10:54:23.005233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 10:54:23.011989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 10:54:23.015826 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 10:54:23.021900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 10:54:23.025326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 10:54:23.031735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 10:54:23.035274 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 10:54:23.041747 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 10:54:23.045143 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 10:54:23.051430 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 10:54:23.055427 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 10:54:23.061601 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 10:54:23.065446 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 10:54:23.071553 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 10:54:23.074882 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 10:54:23.081951 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 10:54:23.085591 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 10:54:23.089066 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 10:54:23.092410 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 10:54:23.099164 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 10:54:23.102681 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 10:54:23.105755 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 10:54:23.112113 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 10:54:23.115472 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 10:54:23.119485 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 10:54:23.125389 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 10:54:23.128943 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 10:54:23.131852 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 10:54:23.138959 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 10:54:23.148702 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 10:54:23.152327 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 10:54:23.162024 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 10:54:23.168309 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 10:54:23.175087 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 10:54:23.178415 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 10:54:23.181529 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 10:54:23.189674 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
483 10:54:23.196358 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 10:54:23.199676 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 10:54:23.206035 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 10:54:23.214415 [RTC]rtc_get_frequency_meter,154: input=15, output=772
487 10:54:23.223727 [RTC]rtc_get_frequency_meter,154: input=23, output=958
488 10:54:23.233102 [RTC]rtc_get_frequency_meter,154: input=19, output=863
489 10:54:23.242689 [RTC]rtc_get_frequency_meter,154: input=17, output=818
490 10:54:23.252301 [RTC]rtc_get_frequency_meter,154: input=16, output=795
491 10:54:23.255561 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 10:54:23.262442 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 10:54:23.266094 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
494 10:54:23.268944 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 10:54:23.271921 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
496 10:54:23.275490 ADC[4]: Raw value=902139 ID=7
497 10:54:23.278796 ADC[3]: Raw value=213179 ID=1
498 10:54:23.281788 RAM Code: 0x71
499 10:54:23.285357 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 10:54:23.288453 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 10:54:23.299161 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 10:54:23.305724 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 10:54:23.308661 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 10:54:23.311766 in-header: 03 07 00 00 08 00 00 00
505 10:54:23.315248 in-data: aa e4 47 04 13 02 00 00
506 10:54:23.318538 Chrome EC: UHEPI supported
507 10:54:23.325280 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 10:54:23.328189 in-header: 03 ed 00 00 08 00 00 00
509 10:54:23.331472 in-data: 80 20 60 08 00 00 00 00
510 10:54:23.334936 MRC: failed to locate region type 0.
511 10:54:23.342217 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 10:54:23.345282 DRAM-K: Running full calibration
513 10:54:23.351726 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 10:54:23.352193 header.status = 0x0
515 10:54:23.354782 header.version = 0x6 (expected: 0x6)
516 10:54:23.358202 header.size = 0xd00 (expected: 0xd00)
517 10:54:23.361938 header.flags = 0x0
518 10:54:23.368444 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 10:54:23.384264 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
520 10:54:23.390864 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 10:54:23.394231 dram_init: ddr_geometry: 2
522 10:54:23.397996 [EMI] MDL number = 2
523 10:54:23.398538 [EMI] Get MDL freq = 0
524 10:54:23.401099 dram_init: ddr_type: 0
525 10:54:23.401626 is_discrete_lpddr4: 1
526 10:54:23.404239 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 10:54:23.404817
528 10:54:23.405251
529 10:54:23.407713 [Bian_co] ETT version 0.0.0.1
530 10:54:23.414183 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 10:54:23.414623
532 10:54:23.417301 dramc_set_vcore_voltage set vcore to 650000
533 10:54:23.421399 Read voltage for 800, 4
534 10:54:23.421938 Vio18 = 0
535 10:54:23.422292 Vcore = 650000
536 10:54:23.424452 Vdram = 0
537 10:54:23.425143 Vddq = 0
538 10:54:23.425562 Vmddr = 0
539 10:54:23.427466 dram_init: config_dvfs: 1
540 10:54:23.430962 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 10:54:23.438284 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 10:54:23.441743 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
543 10:54:23.444878 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
544 10:54:23.448030 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 10:54:23.451653 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 10:54:23.455484 MEM_TYPE=3, freq_sel=18
547 10:54:23.459018 sv_algorithm_assistance_LP4_1600
548 10:54:23.462747 ============ PULL DRAM RESETB DOWN ============
549 10:54:23.466720 ========== PULL DRAM RESETB DOWN end =========
550 10:54:23.469492 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 10:54:23.473550 ===================================
552 10:54:23.477547 LPDDR4 DRAM CONFIGURATION
553 10:54:23.480690 ===================================
554 10:54:23.481221 EX_ROW_EN[0] = 0x0
555 10:54:23.484352 EX_ROW_EN[1] = 0x0
556 10:54:23.484817 LP4Y_EN = 0x0
557 10:54:23.488215 WORK_FSP = 0x0
558 10:54:23.488885 WL = 0x2
559 10:54:23.491673 RL = 0x2
560 10:54:23.492148 BL = 0x2
561 10:54:23.495249 RPST = 0x0
562 10:54:23.495845 RD_PRE = 0x0
563 10:54:23.498802 WR_PRE = 0x1
564 10:54:23.499228 WR_PST = 0x0
565 10:54:23.502773 DBI_WR = 0x0
566 10:54:23.503316 DBI_RD = 0x0
567 10:54:23.505442 OTF = 0x1
568 10:54:23.508906 ===================================
569 10:54:23.511678 ===================================
570 10:54:23.512381 ANA top config
571 10:54:23.515077 ===================================
572 10:54:23.518703 DLL_ASYNC_EN = 0
573 10:54:23.522394 ALL_SLAVE_EN = 1
574 10:54:23.522949 NEW_RANK_MODE = 1
575 10:54:23.525358 DLL_IDLE_MODE = 1
576 10:54:23.528913 LP45_APHY_COMB_EN = 1
577 10:54:23.532205 TX_ODT_DIS = 1
578 10:54:23.532762 NEW_8X_MODE = 1
579 10:54:23.535875 ===================================
580 10:54:23.539009 ===================================
581 10:54:23.542053 data_rate = 1600
582 10:54:23.545385 CKR = 1
583 10:54:23.549078 DQ_P2S_RATIO = 8
584 10:54:23.552583 ===================================
585 10:54:23.556250 CA_P2S_RATIO = 8
586 10:54:23.556691 DQ_CA_OPEN = 0
587 10:54:23.559942 DQ_SEMI_OPEN = 0
588 10:54:23.563729 CA_SEMI_OPEN = 0
589 10:54:23.567390 CA_FULL_RATE = 0
590 10:54:23.567887 DQ_CKDIV4_EN = 1
591 10:54:23.570875 CA_CKDIV4_EN = 1
592 10:54:23.574449 CA_PREDIV_EN = 0
593 10:54:23.577792 PH8_DLY = 0
594 10:54:23.578230 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 10:54:23.581277 DQ_AAMCK_DIV = 4
596 10:54:23.584294 CA_AAMCK_DIV = 4
597 10:54:23.587653 CA_ADMCK_DIV = 4
598 10:54:23.591355 DQ_TRACK_CA_EN = 0
599 10:54:23.594271 CA_PICK = 800
600 10:54:23.597630 CA_MCKIO = 800
601 10:54:23.598075 MCKIO_SEMI = 0
602 10:54:23.601285 PLL_FREQ = 3068
603 10:54:23.604354 DQ_UI_PI_RATIO = 32
604 10:54:23.607490 CA_UI_PI_RATIO = 0
605 10:54:23.610781 ===================================
606 10:54:23.614454 ===================================
607 10:54:23.617579 memory_type:LPDDR4
608 10:54:23.618060 GP_NUM : 10
609 10:54:23.620761 SRAM_EN : 1
610 10:54:23.624436 MD32_EN : 0
611 10:54:23.624966 ===================================
612 10:54:23.627506 [ANA_INIT] >>>>>>>>>>>>>>
613 10:54:23.631315 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 10:54:23.635159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 10:54:23.638670 ===================================
616 10:54:23.642492 data_rate = 1600,PCW = 0X7600
617 10:54:23.642921 ===================================
618 10:54:23.645645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 10:54:23.653273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 10:54:23.656900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 10:54:23.664351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 10:54:23.667560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 10:54:23.670910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 10:54:23.671343 [ANA_INIT] flow start
625 10:54:23.674056 [ANA_INIT] PLL >>>>>>>>
626 10:54:23.677458 [ANA_INIT] PLL <<<<<<<<
627 10:54:23.677890 [ANA_INIT] MIDPI >>>>>>>>
628 10:54:23.680847 [ANA_INIT] MIDPI <<<<<<<<
629 10:54:23.684157 [ANA_INIT] DLL >>>>>>>>
630 10:54:23.684590 [ANA_INIT] flow end
631 10:54:23.691041 ============ LP4 DIFF to SE enter ============
632 10:54:23.694390 ============ LP4 DIFF to SE exit ============
633 10:54:23.697548 [ANA_INIT] <<<<<<<<<<<<<
634 10:54:23.700805 [Flow] Enable top DCM control >>>>>
635 10:54:23.704039 [Flow] Enable top DCM control <<<<<
636 10:54:23.704524 Enable DLL master slave shuffle
637 10:54:23.711162 ==============================================================
638 10:54:23.714226 Gating Mode config
639 10:54:23.717769 ==============================================================
640 10:54:23.721035 Config description:
641 10:54:23.731051 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 10:54:23.738153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 10:54:23.740942 SELPH_MODE 0: By rank 1: By Phase
644 10:54:23.747922 ==============================================================
645 10:54:23.750804 GAT_TRACK_EN = 1
646 10:54:23.754538 RX_GATING_MODE = 2
647 10:54:23.755057 RX_GATING_TRACK_MODE = 2
648 10:54:23.757929 SELPH_MODE = 1
649 10:54:23.761052 PICG_EARLY_EN = 1
650 10:54:23.764829 VALID_LAT_VALUE = 1
651 10:54:23.771146 ==============================================================
652 10:54:23.774164 Enter into Gating configuration >>>>
653 10:54:23.778003 Exit from Gating configuration <<<<
654 10:54:23.781300 Enter into DVFS_PRE_config >>>>>
655 10:54:23.790693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 10:54:23.794328 Exit from DVFS_PRE_config <<<<<
657 10:54:23.797344 Enter into PICG configuration >>>>
658 10:54:23.800635 Exit from PICG configuration <<<<
659 10:54:23.804109 [RX_INPUT] configuration >>>>>
660 10:54:23.807780 [RX_INPUT] configuration <<<<<
661 10:54:23.810976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 10:54:23.817552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 10:54:23.824298 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 10:54:23.830979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 10:54:23.834071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 10:54:23.840643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 10:54:23.844209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 10:54:23.850971 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 10:54:23.854923 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 10:54:23.858404 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 10:54:23.861425 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 10:54:23.868123 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 10:54:23.871771 ===================================
674 10:54:23.872202 LPDDR4 DRAM CONFIGURATION
675 10:54:23.874930 ===================================
676 10:54:23.878162 EX_ROW_EN[0] = 0x0
677 10:54:23.878590 EX_ROW_EN[1] = 0x0
678 10:54:23.881324 LP4Y_EN = 0x0
679 10:54:23.881752 WORK_FSP = 0x0
680 10:54:23.884588 WL = 0x2
681 10:54:23.885132 RL = 0x2
682 10:54:23.888589 BL = 0x2
683 10:54:23.891517 RPST = 0x0
684 10:54:23.892063 RD_PRE = 0x0
685 10:54:23.894949 WR_PRE = 0x1
686 10:54:23.895479 WR_PST = 0x0
687 10:54:23.898253 DBI_WR = 0x0
688 10:54:23.898681 DBI_RD = 0x0
689 10:54:23.901575 OTF = 0x1
690 10:54:23.904834 ===================================
691 10:54:23.908234 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 10:54:23.911363 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 10:54:23.914811 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 10:54:23.918047 ===================================
695 10:54:23.921065 LPDDR4 DRAM CONFIGURATION
696 10:54:23.924830 ===================================
697 10:54:23.927852 EX_ROW_EN[0] = 0x10
698 10:54:23.928358 EX_ROW_EN[1] = 0x0
699 10:54:23.931054 LP4Y_EN = 0x0
700 10:54:23.931494 WORK_FSP = 0x0
701 10:54:23.934161 WL = 0x2
702 10:54:23.934590 RL = 0x2
703 10:54:23.937738 BL = 0x2
704 10:54:23.938165 RPST = 0x0
705 10:54:23.941261 RD_PRE = 0x0
706 10:54:23.941688 WR_PRE = 0x1
707 10:54:23.944584 WR_PST = 0x0
708 10:54:23.945124 DBI_WR = 0x0
709 10:54:23.947913 DBI_RD = 0x0
710 10:54:23.951151 OTF = 0x1
711 10:54:23.951731 ===================================
712 10:54:23.957790 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 10:54:23.962967 nWR fixed to 40
714 10:54:23.966060 [ModeRegInit_LP4] CH0 RK0
715 10:54:23.966531 [ModeRegInit_LP4] CH0 RK1
716 10:54:23.969716 [ModeRegInit_LP4] CH1 RK0
717 10:54:23.972795 [ModeRegInit_LP4] CH1 RK1
718 10:54:23.973225 match AC timing 13
719 10:54:23.979460 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 10:54:23.982638 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 10:54:23.986380 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 10:54:23.993157 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 10:54:23.996479 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 10:54:23.997044 [EMI DOE] emi_dcm 0
725 10:54:24.002991 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 10:54:24.003516 ==
727 10:54:24.006522 Dram Type= 6, Freq= 0, CH_0, rank 0
728 10:54:24.009652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 10:54:24.010186 ==
730 10:54:24.016077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 10:54:24.022739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 10:54:24.030421 [CA 0] Center 38 (7~69) winsize 63
733 10:54:24.033835 [CA 1] Center 38 (7~69) winsize 63
734 10:54:24.036751 [CA 2] Center 35 (5~66) winsize 62
735 10:54:24.039903 [CA 3] Center 35 (4~66) winsize 63
736 10:54:24.043500 [CA 4] Center 34 (4~65) winsize 62
737 10:54:24.047153 [CA 5] Center 33 (3~64) winsize 62
738 10:54:24.047688
739 10:54:24.050502 [CmdBusTrainingLP45] Vref(ca) range 1: 32
740 10:54:24.051059
741 10:54:24.053642 [CATrainingPosCal] consider 1 rank data
742 10:54:24.056908 u2DelayCellTimex100 = 270/100 ps
743 10:54:24.060089 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
744 10:54:24.067181 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
745 10:54:24.069997 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
746 10:54:24.073428 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
747 10:54:24.077001 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
748 10:54:24.080025 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
749 10:54:24.080513
750 10:54:24.083312 CA PerBit enable=1, Macro0, CA PI delay=33
751 10:54:24.083741
752 10:54:24.086812 [CBTSetCACLKResult] CA Dly = 33
753 10:54:24.090080 CS Dly: 6 (0~37)
754 10:54:24.090584 ==
755 10:54:24.093400 Dram Type= 6, Freq= 0, CH_0, rank 1
756 10:54:24.097214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 10:54:24.097690 ==
758 10:54:24.100337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 10:54:24.107099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 10:54:24.117476 [CA 0] Center 38 (7~69) winsize 63
761 10:54:24.121002 [CA 1] Center 38 (7~69) winsize 63
762 10:54:24.124373 [CA 2] Center 36 (6~67) winsize 62
763 10:54:24.128358 [CA 3] Center 35 (5~66) winsize 62
764 10:54:24.131789 [CA 4] Center 35 (4~66) winsize 63
765 10:54:24.135498 [CA 5] Center 34 (4~65) winsize 62
766 10:54:24.136107
767 10:54:24.139059 [CmdBusTrainingLP45] Vref(ca) range 1: 32
768 10:54:24.139686
769 10:54:24.142832 [CATrainingPosCal] consider 2 rank data
770 10:54:24.143276 u2DelayCellTimex100 = 270/100 ps
771 10:54:24.146535 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
772 10:54:24.150360 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
773 10:54:24.157475 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
774 10:54:24.157913 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 10:54:24.161203 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
776 10:54:24.164938 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 10:54:24.165373
778 10:54:24.168815 CA PerBit enable=1, Macro0, CA PI delay=34
779 10:54:24.172239
780 10:54:24.172758 [CBTSetCACLKResult] CA Dly = 34
781 10:54:24.176080 CS Dly: 6 (0~38)
782 10:54:24.176578
783 10:54:24.179893 ----->DramcWriteLeveling(PI) begin...
784 10:54:24.180333 ==
785 10:54:24.183351 Dram Type= 6, Freq= 0, CH_0, rank 0
786 10:54:24.187488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 10:54:24.188080 ==
788 10:54:24.191482 Write leveling (Byte 0): 32 => 32
789 10:54:24.192064 Write leveling (Byte 1): 31 => 31
790 10:54:24.194914 DramcWriteLeveling(PI) end<-----
791 10:54:24.195391
792 10:54:24.195939 ==
793 10:54:24.198856 Dram Type= 6, Freq= 0, CH_0, rank 0
794 10:54:24.202321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 10:54:24.202767 ==
796 10:54:24.205608 [Gating] SW mode calibration
797 10:54:24.213431 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 10:54:24.217035 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 10:54:24.224282 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
800 10:54:24.228231 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
801 10:54:24.231484 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 10:54:24.235293 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:54:24.238904 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:54:24.246151 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 10:54:24.249794 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:54:24.253830 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:54:24.257592 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:54:24.260945 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:54:24.268520 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:54:24.272750 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:54:24.275958 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:54:24.279724 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 10:54:24.283472 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 10:54:24.287771 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 10:54:24.294543 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 10:54:24.298672 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
817 10:54:24.302098 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
818 10:54:24.306175 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 10:54:24.309396 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 10:54:24.316463 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 10:54:24.320146 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 10:54:24.324007 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:54:24.327463 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:54:24.331230 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:54:24.338162 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
826 10:54:24.341773 0 9 12 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
827 10:54:24.345850 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 10:54:24.349516 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 10:54:24.353181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 10:54:24.360735 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 10:54:24.364537 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 10:54:24.367800 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
833 10:54:24.371804 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
834 10:54:24.375842 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
835 10:54:24.382702 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 10:54:24.386678 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 10:54:24.390679 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 10:54:24.394016 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 10:54:24.398306 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 10:54:24.401248 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
841 10:54:24.408626 0 11 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
842 10:54:24.412390 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
843 10:54:24.415866 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 10:54:24.419517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 10:54:24.426681 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 10:54:24.430035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 10:54:24.433374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
848 10:54:24.439733 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 10:54:24.442867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
850 10:54:24.446462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:54:24.449992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:54:24.456711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 10:54:24.459669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 10:54:24.462885 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 10:54:24.469732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 10:54:24.473624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 10:54:24.476517 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 10:54:24.483292 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 10:54:24.486714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 10:54:24.490394 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 10:54:24.496803 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 10:54:24.500155 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 10:54:24.503400 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 10:54:24.509533 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
865 10:54:24.512711 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
866 10:54:24.516203 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 10:54:24.519409 Total UI for P1: 0, mck2ui 16
868 10:54:24.522980 best dqsien dly found for B0: ( 0, 14, 6)
869 10:54:24.526164 Total UI for P1: 0, mck2ui 16
870 10:54:24.529297 best dqsien dly found for B1: ( 0, 14, 10)
871 10:54:24.532633 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
872 10:54:24.535979 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
873 10:54:24.536413
874 10:54:24.542330 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
875 10:54:24.545843 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
876 10:54:24.545928 [Gating] SW calibration Done
877 10:54:24.548788 ==
878 10:54:24.548886 Dram Type= 6, Freq= 0, CH_0, rank 0
879 10:54:24.555783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
880 10:54:24.555868 ==
881 10:54:24.555936 RX Vref Scan: 0
882 10:54:24.555999
883 10:54:24.559004 RX Vref 0 -> 0, step: 1
884 10:54:24.559094
885 10:54:24.562439 RX Delay -130 -> 252, step: 16
886 10:54:24.565607 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
887 10:54:24.569236 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
888 10:54:24.575430 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
889 10:54:24.579155 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
890 10:54:24.582417 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
891 10:54:24.585704 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
892 10:54:24.588791 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
893 10:54:24.595554 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
894 10:54:24.598638 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
895 10:54:24.601988 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
896 10:54:24.605519 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
897 10:54:24.608870 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
898 10:54:24.615432 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
899 10:54:24.618586 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
900 10:54:24.622647 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
901 10:54:24.625443 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
902 10:54:24.626036 ==
903 10:54:24.628637 Dram Type= 6, Freq= 0, CH_0, rank 0
904 10:54:24.635199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 10:54:24.635759 ==
906 10:54:24.636292 DQS Delay:
907 10:54:24.638860 DQS0 = 0, DQS1 = 0
908 10:54:24.639461 DQM Delay:
909 10:54:24.639988 DQM0 = 90, DQM1 = 79
910 10:54:24.641942 DQ Delay:
911 10:54:24.645200 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
912 10:54:24.648423 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
913 10:54:24.652245 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
914 10:54:24.655509 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
915 10:54:24.655998
916 10:54:24.656508
917 10:54:24.657068 ==
918 10:54:24.658916 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:54:24.662235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:54:24.662739 ==
921 10:54:24.663149
922 10:54:24.663631
923 10:54:24.664952 TX Vref Scan disable
924 10:54:24.665505 == TX Byte 0 ==
925 10:54:24.671956 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
926 10:54:24.675167 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
927 10:54:24.675601 == TX Byte 1 ==
928 10:54:24.681702 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
929 10:54:24.685486 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
930 10:54:24.686059 ==
931 10:54:24.688554 Dram Type= 6, Freq= 0, CH_0, rank 0
932 10:54:24.691762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 10:54:24.691874 ==
934 10:54:24.705719 TX Vref=22, minBit 6, minWin=27, winSum=439
935 10:54:24.709374 TX Vref=24, minBit 6, minWin=27, winSum=442
936 10:54:24.712403 TX Vref=26, minBit 8, minWin=27, winSum=447
937 10:54:24.715868 TX Vref=28, minBit 8, minWin=27, winSum=451
938 10:54:24.719041 TX Vref=30, minBit 10, minWin=27, winSum=456
939 10:54:24.725492 TX Vref=32, minBit 9, minWin=27, winSum=455
940 10:54:24.728804 [TxChooseVref] Worse bit 10, Min win 27, Win sum 456, Final Vref 30
941 10:54:24.728892
942 10:54:24.732401 Final TX Range 1 Vref 30
943 10:54:24.732500
944 10:54:24.732594 ==
945 10:54:24.735604 Dram Type= 6, Freq= 0, CH_0, rank 0
946 10:54:24.738749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
947 10:54:24.738848 ==
948 10:54:24.742097
949 10:54:24.742197
950 10:54:24.742288 TX Vref Scan disable
951 10:54:24.745757 == TX Byte 0 ==
952 10:54:24.748999 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
953 10:54:24.756088 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
954 10:54:24.756191 == TX Byte 1 ==
955 10:54:24.758853 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
956 10:54:24.765689 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
957 10:54:24.765766
958 10:54:24.765842 [DATLAT]
959 10:54:24.765902 Freq=800, CH0 RK0
960 10:54:24.765961
961 10:54:24.769083 DATLAT Default: 0xa
962 10:54:24.769154 0, 0xFFFF, sum = 0
963 10:54:24.772002 1, 0xFFFF, sum = 0
964 10:54:24.775377 2, 0xFFFF, sum = 0
965 10:54:24.775480 3, 0xFFFF, sum = 0
966 10:54:24.778820 4, 0xFFFF, sum = 0
967 10:54:24.778923 5, 0xFFFF, sum = 0
968 10:54:24.782092 6, 0xFFFF, sum = 0
969 10:54:24.782166 7, 0xFFFF, sum = 0
970 10:54:24.785552 8, 0xFFFF, sum = 0
971 10:54:24.785624 9, 0x0, sum = 1
972 10:54:24.789005 10, 0x0, sum = 2
973 10:54:24.789078 11, 0x0, sum = 3
974 10:54:24.789146 12, 0x0, sum = 4
975 10:54:24.792184 best_step = 10
976 10:54:24.792251
977 10:54:24.792312 ==
978 10:54:24.795468 Dram Type= 6, Freq= 0, CH_0, rank 0
979 10:54:24.798606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 10:54:24.798706 ==
981 10:54:24.801931 RX Vref Scan: 1
982 10:54:24.802007
983 10:54:24.805528 Set Vref Range= 32 -> 127
984 10:54:24.805596
985 10:54:24.805666 RX Vref 32 -> 127, step: 1
986 10:54:24.805726
987 10:54:24.808586 RX Delay -95 -> 252, step: 8
988 10:54:24.808680
989 10:54:24.812047 Set Vref, RX VrefLevel [Byte0]: 32
990 10:54:24.815235 [Byte1]: 32
991 10:54:24.815330
992 10:54:24.818558 Set Vref, RX VrefLevel [Byte0]: 33
993 10:54:24.822103 [Byte1]: 33
994 10:54:24.825915
995 10:54:24.825992 Set Vref, RX VrefLevel [Byte0]: 34
996 10:54:24.829392 [Byte1]: 34
997 10:54:24.833466
998 10:54:24.833563 Set Vref, RX VrefLevel [Byte0]: 35
999 10:54:24.836907 [Byte1]: 35
1000 10:54:24.841626
1001 10:54:24.841724 Set Vref, RX VrefLevel [Byte0]: 36
1002 10:54:24.844700 [Byte1]: 36
1003 10:54:24.848757
1004 10:54:24.848842 Set Vref, RX VrefLevel [Byte0]: 37
1005 10:54:24.851999 [Byte1]: 37
1006 10:54:24.856472
1007 10:54:24.856545 Set Vref, RX VrefLevel [Byte0]: 38
1008 10:54:24.859806 [Byte1]: 38
1009 10:54:24.864162
1010 10:54:24.864238 Set Vref, RX VrefLevel [Byte0]: 39
1011 10:54:24.867264 [Byte1]: 39
1012 10:54:24.871555
1013 10:54:24.871626 Set Vref, RX VrefLevel [Byte0]: 40
1014 10:54:24.875009 [Byte1]: 40
1015 10:54:24.879642
1016 10:54:24.879746 Set Vref, RX VrefLevel [Byte0]: 41
1017 10:54:24.882803 [Byte1]: 41
1018 10:54:24.887362
1019 10:54:24.887444 Set Vref, RX VrefLevel [Byte0]: 42
1020 10:54:24.890562 [Byte1]: 42
1021 10:54:24.894768
1022 10:54:24.894841 Set Vref, RX VrefLevel [Byte0]: 43
1023 10:54:24.898027 [Byte1]: 43
1024 10:54:24.902048
1025 10:54:24.902125 Set Vref, RX VrefLevel [Byte0]: 44
1026 10:54:24.905693 [Byte1]: 44
1027 10:54:24.909578
1028 10:54:24.909649 Set Vref, RX VrefLevel [Byte0]: 45
1029 10:54:24.912977 [Byte1]: 45
1030 10:54:24.917184
1031 10:54:24.917280 Set Vref, RX VrefLevel [Byte0]: 46
1032 10:54:24.920362 [Byte1]: 46
1033 10:54:24.924956
1034 10:54:24.925030 Set Vref, RX VrefLevel [Byte0]: 47
1035 10:54:24.928287 [Byte1]: 47
1036 10:54:24.932384
1037 10:54:24.932482 Set Vref, RX VrefLevel [Byte0]: 48
1038 10:54:24.935877 [Byte1]: 48
1039 10:54:24.940095
1040 10:54:24.940195 Set Vref, RX VrefLevel [Byte0]: 49
1041 10:54:24.943387 [Byte1]: 49
1042 10:54:24.947831
1043 10:54:24.947942 Set Vref, RX VrefLevel [Byte0]: 50
1044 10:54:24.950983 [Byte1]: 50
1045 10:54:24.955230
1046 10:54:24.955333 Set Vref, RX VrefLevel [Byte0]: 51
1047 10:54:24.958311 [Byte1]: 51
1048 10:54:24.962567
1049 10:54:24.966203 Set Vref, RX VrefLevel [Byte0]: 52
1050 10:54:24.966311 [Byte1]: 52
1051 10:54:24.970361
1052 10:54:24.970463 Set Vref, RX VrefLevel [Byte0]: 53
1053 10:54:24.973542 [Byte1]: 53
1054 10:54:24.978120
1055 10:54:24.978196 Set Vref, RX VrefLevel [Byte0]: 54
1056 10:54:24.981194 [Byte1]: 54
1057 10:54:24.985771
1058 10:54:24.985879 Set Vref, RX VrefLevel [Byte0]: 55
1059 10:54:24.988965 [Byte1]: 55
1060 10:54:24.993112
1061 10:54:24.993213 Set Vref, RX VrefLevel [Byte0]: 56
1062 10:54:24.996447 [Byte1]: 56
1063 10:54:25.000676
1064 10:54:25.000780 Set Vref, RX VrefLevel [Byte0]: 57
1065 10:54:25.004318 [Byte1]: 57
1066 10:54:25.008318
1067 10:54:25.008416 Set Vref, RX VrefLevel [Byte0]: 58
1068 10:54:25.011848 [Byte1]: 58
1069 10:54:25.015980
1070 10:54:25.016078 Set Vref, RX VrefLevel [Byte0]: 59
1071 10:54:25.019297 [Byte1]: 59
1072 10:54:25.023646
1073 10:54:25.023751 Set Vref, RX VrefLevel [Byte0]: 60
1074 10:54:25.027112 [Byte1]: 60
1075 10:54:25.031060
1076 10:54:25.031144 Set Vref, RX VrefLevel [Byte0]: 61
1077 10:54:25.034359 [Byte1]: 61
1078 10:54:25.038896
1079 10:54:25.039000 Set Vref, RX VrefLevel [Byte0]: 62
1080 10:54:25.042289 [Byte1]: 62
1081 10:54:25.046695
1082 10:54:25.046797 Set Vref, RX VrefLevel [Byte0]: 63
1083 10:54:25.049809 [Byte1]: 63
1084 10:54:25.053937
1085 10:54:25.054039 Set Vref, RX VrefLevel [Byte0]: 64
1086 10:54:25.057191 [Byte1]: 64
1087 10:54:25.061639
1088 10:54:25.061744 Set Vref, RX VrefLevel [Byte0]: 65
1089 10:54:25.064845 [Byte1]: 65
1090 10:54:25.069010
1091 10:54:25.069090 Set Vref, RX VrefLevel [Byte0]: 66
1092 10:54:25.072656 [Byte1]: 66
1093 10:54:25.076656
1094 10:54:25.076768 Set Vref, RX VrefLevel [Byte0]: 67
1095 10:54:25.080346 [Byte1]: 67
1096 10:54:25.084462
1097 10:54:25.084565 Set Vref, RX VrefLevel [Byte0]: 68
1098 10:54:25.087459 [Byte1]: 68
1099 10:54:25.091995
1100 10:54:25.092080 Set Vref, RX VrefLevel [Byte0]: 69
1101 10:54:25.098246 [Byte1]: 69
1102 10:54:25.098346
1103 10:54:25.101857 Set Vref, RX VrefLevel [Byte0]: 70
1104 10:54:25.105189 [Byte1]: 70
1105 10:54:25.105261
1106 10:54:25.108735 Set Vref, RX VrefLevel [Byte0]: 71
1107 10:54:25.111874 [Byte1]: 71
1108 10:54:25.111971
1109 10:54:25.115004 Set Vref, RX VrefLevel [Byte0]: 72
1110 10:54:25.118390 [Byte1]: 72
1111 10:54:25.122394
1112 10:54:25.122488 Set Vref, RX VrefLevel [Byte0]: 73
1113 10:54:25.125684 [Byte1]: 73
1114 10:54:25.129800
1115 10:54:25.129882 Set Vref, RX VrefLevel [Byte0]: 74
1116 10:54:25.133533 [Byte1]: 74
1117 10:54:25.137731
1118 10:54:25.137813 Set Vref, RX VrefLevel [Byte0]: 75
1119 10:54:25.140895 [Byte1]: 75
1120 10:54:25.144979
1121 10:54:25.145060 Set Vref, RX VrefLevel [Byte0]: 76
1122 10:54:25.148265 [Byte1]: 76
1123 10:54:25.152692
1124 10:54:25.152807 Set Vref, RX VrefLevel [Byte0]: 77
1125 10:54:25.155823 [Byte1]: 77
1126 10:54:25.160170
1127 10:54:25.160271 Set Vref, RX VrefLevel [Byte0]: 78
1128 10:54:25.163855 [Byte1]: 78
1129 10:54:25.167875
1130 10:54:25.167974 Set Vref, RX VrefLevel [Byte0]: 79
1131 10:54:25.171563 [Byte1]: 79
1132 10:54:25.175638
1133 10:54:25.175744 Final RX Vref Byte 0 = 61 to rank0
1134 10:54:25.178863 Final RX Vref Byte 1 = 62 to rank0
1135 10:54:25.182363 Final RX Vref Byte 0 = 61 to rank1
1136 10:54:25.185676 Final RX Vref Byte 1 = 62 to rank1==
1137 10:54:25.189083 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 10:54:25.195443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 10:54:25.195531 ==
1140 10:54:25.195594 DQS Delay:
1141 10:54:25.195679 DQS0 = 0, DQS1 = 0
1142 10:54:25.198727 DQM Delay:
1143 10:54:25.198825 DQM0 = 93, DQM1 = 82
1144 10:54:25.202413 DQ Delay:
1145 10:54:25.205501 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1146 10:54:25.208792 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1147 10:54:25.212016 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1148 10:54:25.215402 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1149 10:54:25.215485
1150 10:54:25.215550
1151 10:54:25.222075 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1152 10:54:25.225778 CH0 RK0: MR19=606, MR18=3D39
1153 10:54:25.232445 CH0_RK0: MR19=0x606, MR18=0x3D39, DQSOSC=394, MR23=63, INC=95, DEC=63
1154 10:54:25.232529
1155 10:54:25.235373 ----->DramcWriteLeveling(PI) begin...
1156 10:54:25.235457 ==
1157 10:54:25.238924 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 10:54:25.242176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 10:54:25.242260 ==
1160 10:54:25.245361 Write leveling (Byte 0): 33 => 33
1161 10:54:25.249017 Write leveling (Byte 1): 25 => 25
1162 10:54:25.252284 DramcWriteLeveling(PI) end<-----
1163 10:54:25.252392
1164 10:54:25.252460 ==
1165 10:54:25.255509 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 10:54:25.258717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 10:54:25.258800 ==
1168 10:54:25.262142 [Gating] SW mode calibration
1169 10:54:25.268657 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 10:54:25.275437 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 10:54:25.319605 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1172 10:54:25.319900 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1173 10:54:25.319973 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:54:25.320446 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:54:25.320718 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:54:25.320840 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:54:25.321184 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:54:25.321271 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:54:25.321527 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:54:25.321596 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:54:25.363643 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:54:25.364164 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:54:25.364248 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:54:25.364511 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:54:25.364580 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:54:25.365210 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:54:25.365477 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:54:25.365554 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1189 10:54:25.365676 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:54:25.365742 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:54:25.369233 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:54:25.372187 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:54:25.375638 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 10:54:25.378730 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 10:54:25.385738 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:54:25.388884 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:54:25.392110 0 9 8 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (1 1)
1198 10:54:25.398790 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 10:54:25.401805 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 10:54:25.405586 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 10:54:25.412061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 10:54:25.415712 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 10:54:25.418760 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 10:54:25.425340 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1205 10:54:25.428404 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
1206 10:54:25.431955 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 10:54:25.438530 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 10:54:25.441699 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 10:54:25.445300 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 10:54:25.451690 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 10:54:25.455326 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 10:54:25.458420 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1213 10:54:25.462337 0 11 8 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
1214 10:54:25.469483 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 10:54:25.472968 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 10:54:25.476253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 10:54:25.482743 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 10:54:25.486355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 10:54:25.490105 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 10:54:25.493268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 10:54:25.499809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:54:25.503372 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:54:25.506678 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:54:25.513144 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 10:54:25.516565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 10:54:25.519763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 10:54:25.526340 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 10:54:25.529942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 10:54:25.533185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 10:54:25.539547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 10:54:25.542890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 10:54:25.546483 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 10:54:25.553313 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 10:54:25.556416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 10:54:25.559626 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 10:54:25.562957 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1237 10:54:25.569860 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1238 10:54:25.572950 Total UI for P1: 0, mck2ui 16
1239 10:54:25.576102 best dqsien dly found for B1: ( 0, 14, 4)
1240 10:54:25.579812 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 10:54:25.583083 Total UI for P1: 0, mck2ui 16
1242 10:54:25.586277 best dqsien dly found for B0: ( 0, 14, 6)
1243 10:54:25.589851 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1244 10:54:25.593009 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1245 10:54:25.593094
1246 10:54:25.596260 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1247 10:54:25.599488 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1248 10:54:25.602964 [Gating] SW calibration Done
1249 10:54:25.603067 ==
1250 10:54:25.605921 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 10:54:25.612918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 10:54:25.613005 ==
1253 10:54:25.613072 RX Vref Scan: 0
1254 10:54:25.613144
1255 10:54:25.616064 RX Vref 0 -> 0, step: 1
1256 10:54:25.616138
1257 10:54:25.619252 RX Delay -130 -> 252, step: 16
1258 10:54:25.622620 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1259 10:54:25.625662 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1260 10:54:25.629128 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1261 10:54:25.635666 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1262 10:54:25.638915 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1263 10:54:25.642282 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1264 10:54:25.645635 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1265 10:54:25.649062 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1266 10:54:25.655595 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1267 10:54:25.659214 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1268 10:54:25.662317 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1269 10:54:25.666069 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1270 10:54:25.668997 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1271 10:54:25.675619 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1272 10:54:25.678955 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1273 10:54:25.682599 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1274 10:54:25.682680 ==
1275 10:54:25.685845 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 10:54:25.689046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 10:54:25.689120 ==
1278 10:54:25.692339 DQS Delay:
1279 10:54:25.692411 DQS0 = 0, DQS1 = 0
1280 10:54:25.695743 DQM Delay:
1281 10:54:25.695815 DQM0 = 90, DQM1 = 79
1282 10:54:25.695942 DQ Delay:
1283 10:54:25.699149 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1284 10:54:25.702180 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1285 10:54:25.705837 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1286 10:54:25.708880 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1287 10:54:25.708956
1288 10:54:25.709020
1289 10:54:25.712107 ==
1290 10:54:25.715790 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 10:54:25.718719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 10:54:25.718798 ==
1293 10:54:25.718860
1294 10:54:25.718927
1295 10:54:25.722439 TX Vref Scan disable
1296 10:54:25.722532 == TX Byte 0 ==
1297 10:54:25.729178 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1298 10:54:25.732284 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1299 10:54:25.732356 == TX Byte 1 ==
1300 10:54:25.738586 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1301 10:54:25.742417 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1302 10:54:25.742502 ==
1303 10:54:25.745773 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 10:54:25.748508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 10:54:25.748592 ==
1306 10:54:25.763335 TX Vref=22, minBit 1, minWin=27, winSum=446
1307 10:54:25.766987 TX Vref=24, minBit 2, minWin=28, winSum=453
1308 10:54:25.770249 TX Vref=26, minBit 3, minWin=28, winSum=454
1309 10:54:25.773205 TX Vref=28, minBit 3, minWin=28, winSum=455
1310 10:54:25.776528 TX Vref=30, minBit 8, minWin=28, winSum=460
1311 10:54:25.780116 TX Vref=32, minBit 8, minWin=28, winSum=461
1312 10:54:25.786460 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 32
1313 10:54:25.786553
1314 10:54:25.790397 Final TX Range 1 Vref 32
1315 10:54:25.790490
1316 10:54:25.790566 ==
1317 10:54:25.793532 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 10:54:25.796633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 10:54:25.796796 ==
1320 10:54:25.799923
1321 10:54:25.800022
1322 10:54:25.800127 TX Vref Scan disable
1323 10:54:25.803611 == TX Byte 0 ==
1324 10:54:25.806639 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1325 10:54:25.813216 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1326 10:54:25.813302 == TX Byte 1 ==
1327 10:54:25.816550 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1328 10:54:25.823192 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1329 10:54:25.823268
1330 10:54:25.823329 [DATLAT]
1331 10:54:25.823390 Freq=800, CH0 RK1
1332 10:54:25.823446
1333 10:54:25.826787 DATLAT Default: 0xa
1334 10:54:25.826869 0, 0xFFFF, sum = 0
1335 10:54:25.830005 1, 0xFFFF, sum = 0
1336 10:54:25.830076 2, 0xFFFF, sum = 0
1337 10:54:25.833162 3, 0xFFFF, sum = 0
1338 10:54:25.836789 4, 0xFFFF, sum = 0
1339 10:54:25.836894 5, 0xFFFF, sum = 0
1340 10:54:25.839870 6, 0xFFFF, sum = 0
1341 10:54:25.839951 7, 0xFFFF, sum = 0
1342 10:54:25.843087 8, 0xFFFF, sum = 0
1343 10:54:25.843188 9, 0x0, sum = 1
1344 10:54:25.843280 10, 0x0, sum = 2
1345 10:54:25.846505 11, 0x0, sum = 3
1346 10:54:25.846577 12, 0x0, sum = 4
1347 10:54:25.849761 best_step = 10
1348 10:54:25.849840
1349 10:54:25.849900 ==
1350 10:54:25.853200 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 10:54:25.856430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 10:54:25.856530 ==
1353 10:54:25.859601 RX Vref Scan: 0
1354 10:54:25.859714
1355 10:54:25.859818 RX Vref 0 -> 0, step: 1
1356 10:54:25.863214
1357 10:54:25.863310 RX Delay -79 -> 252, step: 8
1358 10:54:25.870232 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1359 10:54:25.873571 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1360 10:54:25.876434 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1361 10:54:25.880046 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1362 10:54:25.883190 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1363 10:54:25.890015 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1364 10:54:25.893386 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1365 10:54:25.896958 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1366 10:54:25.900050 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1367 10:54:25.903264 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1368 10:54:25.909784 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1369 10:54:25.913466 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1370 10:54:25.916349 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1371 10:54:25.919933 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1372 10:54:25.923140 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1373 10:54:25.929869 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1374 10:54:25.929973 ==
1375 10:54:25.933479 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 10:54:25.936616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 10:54:25.936715 ==
1378 10:54:25.936841 DQS Delay:
1379 10:54:25.939814 DQS0 = 0, DQS1 = 0
1380 10:54:25.939884 DQM Delay:
1381 10:54:25.943239 DQM0 = 91, DQM1 = 82
1382 10:54:25.943336 DQ Delay:
1383 10:54:25.946624 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1384 10:54:25.949766 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1385 10:54:25.953099 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1386 10:54:25.956858 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1387 10:54:25.956935
1388 10:54:25.957027
1389 10:54:25.966570 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1390 10:54:25.966660 CH0 RK1: MR19=606, MR18=411B
1391 10:54:25.973081 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1392 10:54:25.976658 [RxdqsGatingPostProcess] freq 800
1393 10:54:25.983134 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1394 10:54:25.986792 Pre-setting of DQS Precalculation
1395 10:54:25.989957 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1396 10:54:25.990031 ==
1397 10:54:25.993369 Dram Type= 6, Freq= 0, CH_1, rank 0
1398 10:54:25.996479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 10:54:25.999846 ==
1400 10:54:26.003321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 10:54:26.009759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 10:54:26.018390 [CA 0] Center 36 (6~67) winsize 62
1403 10:54:26.021867 [CA 1] Center 36 (6~67) winsize 62
1404 10:54:26.025071 [CA 2] Center 35 (5~65) winsize 61
1405 10:54:26.028378 [CA 3] Center 34 (3~65) winsize 63
1406 10:54:26.031453 [CA 4] Center 34 (4~65) winsize 62
1407 10:54:26.034929 [CA 5] Center 34 (3~65) winsize 63
1408 10:54:26.035029
1409 10:54:26.038396 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1410 10:54:26.038479
1411 10:54:26.041394 [CATrainingPosCal] consider 1 rank data
1412 10:54:26.044950 u2DelayCellTimex100 = 270/100 ps
1413 10:54:26.048177 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 10:54:26.054661 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 10:54:26.057987 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1416 10:54:26.061318 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1417 10:54:26.064600 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 10:54:26.068332 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1419 10:54:26.068431
1420 10:54:26.070958 CA PerBit enable=1, Macro0, CA PI delay=34
1421 10:54:26.071054
1422 10:54:26.074546 [CBTSetCACLKResult] CA Dly = 34
1423 10:54:26.077725 CS Dly: 5 (0~36)
1424 10:54:26.077855 ==
1425 10:54:26.081004 Dram Type= 6, Freq= 0, CH_1, rank 1
1426 10:54:26.084218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 10:54:26.084303 ==
1428 10:54:26.091090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 10:54:26.094497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 10:54:26.104508 [CA 0] Center 36 (6~67) winsize 62
1431 10:54:26.107976 [CA 1] Center 37 (6~68) winsize 63
1432 10:54:26.111170 [CA 2] Center 35 (5~66) winsize 62
1433 10:54:26.114458 [CA 3] Center 34 (4~65) winsize 62
1434 10:54:26.117999 [CA 4] Center 35 (5~65) winsize 61
1435 10:54:26.121371 [CA 5] Center 34 (4~65) winsize 62
1436 10:54:26.121454
1437 10:54:26.124711 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1438 10:54:26.124855
1439 10:54:26.127822 [CATrainingPosCal] consider 2 rank data
1440 10:54:26.131650 u2DelayCellTimex100 = 270/100 ps
1441 10:54:26.135197 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1442 10:54:26.139083 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 10:54:26.142955 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1444 10:54:26.146270 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1445 10:54:26.149843 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1446 10:54:26.153317 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 10:54:26.153419
1448 10:54:26.157160 CA PerBit enable=1, Macro0, CA PI delay=34
1449 10:54:26.157254
1450 10:54:26.160284 [CBTSetCACLKResult] CA Dly = 34
1451 10:54:26.164114 CS Dly: 6 (0~38)
1452 10:54:26.164228
1453 10:54:26.167169 ----->DramcWriteLeveling(PI) begin...
1454 10:54:26.167276 ==
1455 10:54:26.170542 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 10:54:26.173875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 10:54:26.173959 ==
1458 10:54:26.176973 Write leveling (Byte 0): 25 => 25
1459 10:54:26.180316 Write leveling (Byte 1): 26 => 26
1460 10:54:26.184121 DramcWriteLeveling(PI) end<-----
1461 10:54:26.184230
1462 10:54:26.184326 ==
1463 10:54:26.187311 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 10:54:26.190845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 10:54:26.190929 ==
1466 10:54:26.193540 [Gating] SW mode calibration
1467 10:54:26.200219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1468 10:54:26.206646 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1469 10:54:26.210286 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1470 10:54:26.213633 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1471 10:54:26.220032 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:54:26.223659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:54:26.226676 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:54:26.233334 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:54:26.236922 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:54:26.240195 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:54:26.246997 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:54:26.250290 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:54:26.253374 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:54:26.259708 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:54:26.263240 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:54:26.266352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:54:26.273292 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:54:26.276231 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:54:26.279701 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1486 10:54:26.286501 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1487 10:54:26.289769 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1488 10:54:26.292934 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:54:26.299571 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:54:26.302799 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:54:26.306623 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:54:26.312810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 10:54:26.316273 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:54:26.319548 0 9 4 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1495 10:54:26.326473 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1496 10:54:26.329800 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 10:54:26.332733 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 10:54:26.336272 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 10:54:26.342749 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 10:54:26.346368 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 10:54:26.349390 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 10:54:26.356225 0 10 4 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (0 0)
1503 10:54:26.359392 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 10:54:26.362903 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 10:54:26.369470 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 10:54:26.373005 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 10:54:26.375874 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 10:54:26.382647 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 10:54:26.385861 0 11 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1510 10:54:26.389506 0 11 4 | B1->B0 | 3434 3939 | 0 0 | (0 0) (1 1)
1511 10:54:26.396124 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 10:54:26.399278 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 10:54:26.402715 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 10:54:26.409326 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 10:54:26.412654 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 10:54:26.415820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 10:54:26.422711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1518 10:54:26.425840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1519 10:54:26.429168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1520 10:54:26.435806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:54:26.439163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 10:54:26.442753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 10:54:26.449142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 10:54:26.452718 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 10:54:26.456219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 10:54:26.462487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 10:54:26.465925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 10:54:26.468993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 10:54:26.476031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 10:54:26.479031 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 10:54:26.482236 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 10:54:26.489003 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 10:54:26.492204 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 10:54:26.495526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1535 10:54:26.498887 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 10:54:26.502437 Total UI for P1: 0, mck2ui 16
1537 10:54:26.505470 best dqsien dly found for B0: ( 0, 14, 4)
1538 10:54:26.508625 Total UI for P1: 0, mck2ui 16
1539 10:54:26.511999 best dqsien dly found for B1: ( 0, 14, 4)
1540 10:54:26.515446 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1541 10:54:26.518622 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1542 10:54:26.522361
1543 10:54:26.525731 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1544 10:54:26.528655 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1545 10:54:26.531972 [Gating] SW calibration Done
1546 10:54:26.532081 ==
1547 10:54:26.535142 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 10:54:26.538692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 10:54:26.538777 ==
1550 10:54:26.538844 RX Vref Scan: 0
1551 10:54:26.538911
1552 10:54:26.541728 RX Vref 0 -> 0, step: 1
1553 10:54:26.541837
1554 10:54:26.545401 RX Delay -130 -> 252, step: 16
1555 10:54:26.548411 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1556 10:54:26.552014 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1557 10:54:26.558391 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1558 10:54:26.562162 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1559 10:54:26.565417 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1560 10:54:26.568431 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1561 10:54:26.571837 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1562 10:54:26.578366 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1563 10:54:26.582008 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1564 10:54:26.584741 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1565 10:54:26.588456 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1566 10:54:26.594893 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1567 10:54:26.598144 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1568 10:54:26.601990 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1569 10:54:26.604659 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1570 10:54:26.608180 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1571 10:54:26.608305 ==
1572 10:54:26.611467 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 10:54:26.618212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 10:54:26.618360 ==
1575 10:54:26.618489 DQS Delay:
1576 10:54:26.621482 DQS0 = 0, DQS1 = 0
1577 10:54:26.621657 DQM Delay:
1578 10:54:26.624823 DQM0 = 87, DQM1 = 80
1579 10:54:26.624947 DQ Delay:
1580 10:54:26.628040 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1581 10:54:26.631329 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1582 10:54:26.635119 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1583 10:54:26.638436 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1584 10:54:26.638664
1585 10:54:26.638861
1586 10:54:26.639048 ==
1587 10:54:26.641602 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 10:54:26.644564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 10:54:26.644869 ==
1590 10:54:26.645042
1591 10:54:26.645196
1592 10:54:26.648140 TX Vref Scan disable
1593 10:54:26.651386 == TX Byte 0 ==
1594 10:54:26.654669 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1595 10:54:26.658255 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1596 10:54:26.661453 == TX Byte 1 ==
1597 10:54:26.664537 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1598 10:54:26.668360 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1599 10:54:26.668900 ==
1600 10:54:26.671757 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 10:54:26.674732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 10:54:26.678276 ==
1603 10:54:26.689299 TX Vref=22, minBit 10, minWin=27, winSum=453
1604 10:54:26.692631 TX Vref=24, minBit 15, minWin=27, winSum=457
1605 10:54:26.695750 TX Vref=26, minBit 9, minWin=28, winSum=463
1606 10:54:26.699504 TX Vref=28, minBit 13, minWin=28, winSum=463
1607 10:54:26.702833 TX Vref=30, minBit 9, minWin=28, winSum=463
1608 10:54:26.706780 TX Vref=32, minBit 12, minWin=27, winSum=457
1609 10:54:26.713242 [TxChooseVref] Worse bit 9, Min win 28, Win sum 463, Final Vref 26
1610 10:54:26.713810
1611 10:54:26.716603 Final TX Range 1 Vref 26
1612 10:54:26.717164
1613 10:54:26.717638 ==
1614 10:54:26.719740 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 10:54:26.723337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 10:54:26.723833 ==
1617 10:54:26.724288
1618 10:54:26.724804
1619 10:54:26.726505 TX Vref Scan disable
1620 10:54:26.729947 == TX Byte 0 ==
1621 10:54:26.733411 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1622 10:54:26.736453 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1623 10:54:26.740084 == TX Byte 1 ==
1624 10:54:26.743004 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1625 10:54:26.746781 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1626 10:54:26.747320
1627 10:54:26.749732 [DATLAT]
1628 10:54:26.750247 Freq=800, CH1 RK0
1629 10:54:26.750718
1630 10:54:26.753214 DATLAT Default: 0xa
1631 10:54:26.753709 0, 0xFFFF, sum = 0
1632 10:54:26.756460 1, 0xFFFF, sum = 0
1633 10:54:26.756992 2, 0xFFFF, sum = 0
1634 10:54:26.759963 3, 0xFFFF, sum = 0
1635 10:54:26.760558 4, 0xFFFF, sum = 0
1636 10:54:26.763198 5, 0xFFFF, sum = 0
1637 10:54:26.763854 6, 0xFFFF, sum = 0
1638 10:54:26.766261 7, 0xFFFF, sum = 0
1639 10:54:26.766653 8, 0xFFFF, sum = 0
1640 10:54:26.770128 9, 0x0, sum = 1
1641 10:54:26.770707 10, 0x0, sum = 2
1642 10:54:26.773214 11, 0x0, sum = 3
1643 10:54:26.773672 12, 0x0, sum = 4
1644 10:54:26.776526 best_step = 10
1645 10:54:26.777053
1646 10:54:26.777436 ==
1647 10:54:26.779877 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 10:54:26.783112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 10:54:26.783661 ==
1650 10:54:26.786718 RX Vref Scan: 1
1651 10:54:26.787290
1652 10:54:26.787779 Set Vref Range= 32 -> 127
1653 10:54:26.788249
1654 10:54:26.790043 RX Vref 32 -> 127, step: 1
1655 10:54:26.790478
1656 10:54:26.792942 RX Delay -95 -> 252, step: 8
1657 10:54:26.793398
1658 10:54:26.796516 Set Vref, RX VrefLevel [Byte0]: 32
1659 10:54:26.799733 [Byte1]: 32
1660 10:54:26.800389
1661 10:54:26.802955 Set Vref, RX VrefLevel [Byte0]: 33
1662 10:54:26.806352 [Byte1]: 33
1663 10:54:26.809820
1664 10:54:26.810416 Set Vref, RX VrefLevel [Byte0]: 34
1665 10:54:26.813253 [Byte1]: 34
1666 10:54:26.817464
1667 10:54:26.817985 Set Vref, RX VrefLevel [Byte0]: 35
1668 10:54:26.820818 [Byte1]: 35
1669 10:54:26.824818
1670 10:54:26.825380 Set Vref, RX VrefLevel [Byte0]: 36
1671 10:54:26.828309 [Byte1]: 36
1672 10:54:26.832702
1673 10:54:26.833312 Set Vref, RX VrefLevel [Byte0]: 37
1674 10:54:26.835907 [Byte1]: 37
1675 10:54:26.840125
1676 10:54:26.840717 Set Vref, RX VrefLevel [Byte0]: 38
1677 10:54:26.843618 [Byte1]: 38
1678 10:54:26.847746
1679 10:54:26.848303 Set Vref, RX VrefLevel [Byte0]: 39
1680 10:54:26.851226 [Byte1]: 39
1681 10:54:26.855184
1682 10:54:26.855749 Set Vref, RX VrefLevel [Byte0]: 40
1683 10:54:26.858841 [Byte1]: 40
1684 10:54:26.862914
1685 10:54:26.863346 Set Vref, RX VrefLevel [Byte0]: 41
1686 10:54:26.866357 [Byte1]: 41
1687 10:54:26.870534
1688 10:54:26.871121 Set Vref, RX VrefLevel [Byte0]: 42
1689 10:54:26.873931 [Byte1]: 42
1690 10:54:26.877966
1691 10:54:26.878605 Set Vref, RX VrefLevel [Byte0]: 43
1692 10:54:26.881685 [Byte1]: 43
1693 10:54:26.885949
1694 10:54:26.886413 Set Vref, RX VrefLevel [Byte0]: 44
1695 10:54:26.889188 [Byte1]: 44
1696 10:54:26.893290
1697 10:54:26.893716 Set Vref, RX VrefLevel [Byte0]: 45
1698 10:54:26.896679 [Byte1]: 45
1699 10:54:26.901018
1700 10:54:26.901444 Set Vref, RX VrefLevel [Byte0]: 46
1701 10:54:26.904220 [Byte1]: 46
1702 10:54:26.908479
1703 10:54:26.909086 Set Vref, RX VrefLevel [Byte0]: 47
1704 10:54:26.912024 [Byte1]: 47
1705 10:54:26.915939
1706 10:54:26.916567 Set Vref, RX VrefLevel [Byte0]: 48
1707 10:54:26.919418 [Byte1]: 48
1708 10:54:26.923544
1709 10:54:26.924100 Set Vref, RX VrefLevel [Byte0]: 49
1710 10:54:26.926809 [Byte1]: 49
1711 10:54:26.931160
1712 10:54:26.931802 Set Vref, RX VrefLevel [Byte0]: 50
1713 10:54:26.934826 [Byte1]: 50
1714 10:54:26.938797
1715 10:54:26.939304 Set Vref, RX VrefLevel [Byte0]: 51
1716 10:54:26.942353 [Byte1]: 51
1717 10:54:26.946412
1718 10:54:26.946838 Set Vref, RX VrefLevel [Byte0]: 52
1719 10:54:26.949919 [Byte1]: 52
1720 10:54:26.954046
1721 10:54:26.954606 Set Vref, RX VrefLevel [Byte0]: 53
1722 10:54:26.957419 [Byte1]: 53
1723 10:54:26.961855
1724 10:54:26.962281 Set Vref, RX VrefLevel [Byte0]: 54
1725 10:54:26.965081 [Byte1]: 54
1726 10:54:26.969181
1727 10:54:26.969692 Set Vref, RX VrefLevel [Byte0]: 55
1728 10:54:26.972849 [Byte1]: 55
1729 10:54:26.976834
1730 10:54:26.977390 Set Vref, RX VrefLevel [Byte0]: 56
1731 10:54:26.980084 [Byte1]: 56
1732 10:54:26.984403
1733 10:54:26.985086 Set Vref, RX VrefLevel [Byte0]: 57
1734 10:54:26.987769 [Byte1]: 57
1735 10:54:26.992003
1736 10:54:26.992563 Set Vref, RX VrefLevel [Byte0]: 58
1737 10:54:26.995706 [Byte1]: 58
1738 10:54:26.999364
1739 10:54:26.999923 Set Vref, RX VrefLevel [Byte0]: 59
1740 10:54:27.002781 [Byte1]: 59
1741 10:54:27.007562
1742 10:54:27.008154 Set Vref, RX VrefLevel [Byte0]: 60
1743 10:54:27.010411 [Byte1]: 60
1744 10:54:27.014851
1745 10:54:27.015466 Set Vref, RX VrefLevel [Byte0]: 61
1746 10:54:27.018506 [Byte1]: 61
1747 10:54:27.022790
1748 10:54:27.025443 Set Vref, RX VrefLevel [Byte0]: 62
1749 10:54:27.028675 [Byte1]: 62
1750 10:54:27.029274
1751 10:54:27.032502 Set Vref, RX VrefLevel [Byte0]: 63
1752 10:54:27.035567 [Byte1]: 63
1753 10:54:27.036152
1754 10:54:27.038824 Set Vref, RX VrefLevel [Byte0]: 64
1755 10:54:27.042409 [Byte1]: 64
1756 10:54:27.042835
1757 10:54:27.045165 Set Vref, RX VrefLevel [Byte0]: 65
1758 10:54:27.048325 [Byte1]: 65
1759 10:54:27.052450
1760 10:54:27.052565 Set Vref, RX VrefLevel [Byte0]: 66
1761 10:54:27.056099 [Byte1]: 66
1762 10:54:27.060226
1763 10:54:27.060310 Set Vref, RX VrefLevel [Byte0]: 67
1764 10:54:27.063257 [Byte1]: 67
1765 10:54:27.067773
1766 10:54:27.067870 Set Vref, RX VrefLevel [Byte0]: 68
1767 10:54:27.071076 [Byte1]: 68
1768 10:54:27.075344
1769 10:54:27.075418 Set Vref, RX VrefLevel [Byte0]: 69
1770 10:54:27.078574 [Byte1]: 69
1771 10:54:27.082843
1772 10:54:27.082932 Set Vref, RX VrefLevel [Byte0]: 70
1773 10:54:27.086586 [Byte1]: 70
1774 10:54:27.090835
1775 10:54:27.090931 Set Vref, RX VrefLevel [Byte0]: 71
1776 10:54:27.094108 [Byte1]: 71
1777 10:54:27.098139
1778 10:54:27.098225 Set Vref, RX VrefLevel [Byte0]: 72
1779 10:54:27.101423 [Byte1]: 72
1780 10:54:27.105650
1781 10:54:27.105740 Set Vref, RX VrefLevel [Byte0]: 73
1782 10:54:27.109421 [Byte1]: 73
1783 10:54:27.113254
1784 10:54:27.113359 Set Vref, RX VrefLevel [Byte0]: 74
1785 10:54:27.116628 [Byte1]: 74
1786 10:54:27.121041
1787 10:54:27.121121 Set Vref, RX VrefLevel [Byte0]: 75
1788 10:54:27.124222 [Byte1]: 75
1789 10:54:27.128330
1790 10:54:27.128409 Set Vref, RX VrefLevel [Byte0]: 76
1791 10:54:27.131767 [Byte1]: 76
1792 10:54:27.135945
1793 10:54:27.136046 Set Vref, RX VrefLevel [Byte0]: 77
1794 10:54:27.139657 [Byte1]: 77
1795 10:54:27.143891
1796 10:54:27.143966 Set Vref, RX VrefLevel [Byte0]: 78
1797 10:54:27.146863 [Byte1]: 78
1798 10:54:27.151171
1799 10:54:27.151248 Set Vref, RX VrefLevel [Byte0]: 79
1800 10:54:27.154846 [Byte1]: 79
1801 10:54:27.159072
1802 10:54:27.159154 Set Vref, RX VrefLevel [Byte0]: 80
1803 10:54:27.162108 [Byte1]: 80
1804 10:54:27.166595
1805 10:54:27.166670 Final RX Vref Byte 0 = 53 to rank0
1806 10:54:27.169699 Final RX Vref Byte 1 = 62 to rank0
1807 10:54:27.172862 Final RX Vref Byte 0 = 53 to rank1
1808 10:54:27.176611 Final RX Vref Byte 1 = 62 to rank1==
1809 10:54:27.179557 Dram Type= 6, Freq= 0, CH_1, rank 0
1810 10:54:27.186372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 10:54:27.186474 ==
1812 10:54:27.186568 DQS Delay:
1813 10:54:27.189680 DQS0 = 0, DQS1 = 0
1814 10:54:27.189754 DQM Delay:
1815 10:54:27.189817 DQM0 = 92, DQM1 = 82
1816 10:54:27.192890 DQ Delay:
1817 10:54:27.195937 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1818 10:54:27.199488 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =88
1819 10:54:27.202823 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1820 10:54:27.206132 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1821 10:54:27.206217
1822 10:54:27.206284
1823 10:54:27.212630 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 399 ps
1824 10:54:27.215952 CH1 RK0: MR19=606, MR18=2A48
1825 10:54:27.222925 CH1_RK0: MR19=0x606, MR18=0x2A48, DQSOSC=391, MR23=63, INC=96, DEC=64
1826 10:54:27.223008
1827 10:54:27.226251 ----->DramcWriteLeveling(PI) begin...
1828 10:54:27.226332 ==
1829 10:54:27.229224 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 10:54:27.232577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 10:54:27.232650 ==
1832 10:54:27.235955 Write leveling (Byte 0): 29 => 29
1833 10:54:27.239201 Write leveling (Byte 1): 30 => 30
1834 10:54:27.242553 DramcWriteLeveling(PI) end<-----
1835 10:54:27.242628
1836 10:54:27.242691 ==
1837 10:54:27.246209 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 10:54:27.249273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 10:54:27.249346 ==
1840 10:54:27.252528 [Gating] SW mode calibration
1841 10:54:27.259200 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1842 10:54:27.266002 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1843 10:54:27.269174 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1844 10:54:27.275836 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1845 10:54:27.278939 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:54:27.282218 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:54:27.289143 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:54:27.292336 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:54:27.295900 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 10:54:27.302515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 10:54:27.305807 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 10:54:27.309004 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 10:54:27.312507 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:54:27.319228 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 10:54:27.322439 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 10:54:27.325654 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 10:54:27.332130 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:54:27.335882 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:54:27.338890 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1860 10:54:27.345752 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1861 10:54:27.349002 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1862 10:54:27.352327 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 10:54:27.358774 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 10:54:27.362130 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 10:54:27.365247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 10:54:27.372043 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 10:54:27.375298 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 10:54:27.378787 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
1869 10:54:27.385342 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 10:54:27.388799 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 10:54:27.391985 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 10:54:27.398311 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 10:54:27.401957 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 10:54:27.405264 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 10:54:27.411857 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1876 10:54:27.414979 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
1877 10:54:27.418525 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:54:27.424627 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:54:27.428451 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:54:27.431637 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:54:27.438253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:54:27.441701 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:54:27.444652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:54:27.451283 0 11 4 | B1->B0 | 3131 3030 | 0 0 | (0 0) (1 1)
1885 10:54:27.454828 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1886 10:54:27.457996 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 10:54:27.464552 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 10:54:27.468008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 10:54:27.471791 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 10:54:27.477826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 10:54:27.481487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1892 10:54:27.484278 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1893 10:54:27.491005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 10:54:27.494583 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 10:54:27.497762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 10:54:27.504274 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 10:54:27.507776 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 10:54:27.510832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 10:54:27.517822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 10:54:27.520923 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 10:54:27.524104 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 10:54:27.530970 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 10:54:27.534354 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 10:54:27.537486 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 10:54:27.540796 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 10:54:27.547677 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 10:54:27.550856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 10:54:27.553897 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1909 10:54:27.561005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 10:54:27.564083 Total UI for P1: 0, mck2ui 16
1911 10:54:27.567363 best dqsien dly found for B0: ( 0, 14, 6)
1912 10:54:27.570553 Total UI for P1: 0, mck2ui 16
1913 10:54:27.573906 best dqsien dly found for B1: ( 0, 14, 4)
1914 10:54:27.577238 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1915 10:54:27.580321 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1916 10:54:27.580433
1917 10:54:27.583602 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1918 10:54:27.587373 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 10:54:27.590172 [Gating] SW calibration Done
1920 10:54:27.590246 ==
1921 10:54:27.593745 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 10:54:27.596900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 10:54:27.596977 ==
1924 10:54:27.600062 RX Vref Scan: 0
1925 10:54:27.600144
1926 10:54:27.603378 RX Vref 0 -> 0, step: 1
1927 10:54:27.603459
1928 10:54:27.603524 RX Delay -130 -> 252, step: 16
1929 10:54:27.610677 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1930 10:54:27.613558 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1931 10:54:27.617029 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1932 10:54:27.620416 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1933 10:54:27.623347 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1934 10:54:27.629936 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1935 10:54:27.633632 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1936 10:54:27.636790 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1937 10:54:27.640155 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1938 10:54:27.643306 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1939 10:54:27.649770 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1940 10:54:27.653453 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1941 10:54:27.656554 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1942 10:54:27.659690 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1943 10:54:27.666762 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1944 10:54:27.669791 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1945 10:54:27.669865 ==
1946 10:54:27.673213 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 10:54:27.676357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 10:54:27.676433 ==
1949 10:54:27.676503 DQS Delay:
1950 10:54:27.679774 DQS0 = 0, DQS1 = 0
1951 10:54:27.679847 DQM Delay:
1952 10:54:27.683021 DQM0 = 91, DQM1 = 84
1953 10:54:27.683093 DQ Delay:
1954 10:54:27.686319 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1955 10:54:27.689533 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1956 10:54:27.692866 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1957 10:54:27.696172 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1958 10:54:27.696249
1959 10:54:27.696326
1960 10:54:27.696388 ==
1961 10:54:27.699642 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 10:54:27.706334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 10:54:27.706412 ==
1964 10:54:27.706476
1965 10:54:27.706546
1966 10:54:27.706607 TX Vref Scan disable
1967 10:54:27.709308 == TX Byte 0 ==
1968 10:54:27.712728 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 10:54:27.719469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 10:54:27.719559 == TX Byte 1 ==
1971 10:54:27.722851 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1972 10:54:27.729495 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1973 10:54:27.729573 ==
1974 10:54:27.732919 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 10:54:27.736091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 10:54:27.736164 ==
1977 10:54:27.748626 TX Vref=22, minBit 13, minWin=27, winSum=451
1978 10:54:27.751707 TX Vref=24, minBit 13, minWin=27, winSum=453
1979 10:54:27.755052 TX Vref=26, minBit 9, minWin=28, winSum=460
1980 10:54:27.758298 TX Vref=28, minBit 13, minWin=27, winSum=456
1981 10:54:27.761585 TX Vref=30, minBit 8, minWin=28, winSum=460
1982 10:54:27.768138 TX Vref=32, minBit 8, minWin=28, winSum=457
1983 10:54:27.771667 [TxChooseVref] Worse bit 9, Min win 28, Win sum 460, Final Vref 26
1984 10:54:27.771750
1985 10:54:27.775111 Final TX Range 1 Vref 26
1986 10:54:27.775197
1987 10:54:27.775331 ==
1988 10:54:27.778080 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 10:54:27.781792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 10:54:27.785000 ==
1991 10:54:27.785082
1992 10:54:27.785146
1993 10:54:27.785206 TX Vref Scan disable
1994 10:54:27.788714 == TX Byte 0 ==
1995 10:54:27.792179 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1996 10:54:27.798562 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1997 10:54:27.798645 == TX Byte 1 ==
1998 10:54:27.801758 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1999 10:54:27.808143 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2000 10:54:27.808221
2001 10:54:27.808284 [DATLAT]
2002 10:54:27.808343 Freq=800, CH1 RK1
2003 10:54:27.808401
2004 10:54:27.811887 DATLAT Default: 0xa
2005 10:54:27.811970 0, 0xFFFF, sum = 0
2006 10:54:27.815077 1, 0xFFFF, sum = 0
2007 10:54:27.815160 2, 0xFFFF, sum = 0
2008 10:54:27.818253 3, 0xFFFF, sum = 0
2009 10:54:27.821876 4, 0xFFFF, sum = 0
2010 10:54:27.822009 5, 0xFFFF, sum = 0
2011 10:54:27.825150 6, 0xFFFF, sum = 0
2012 10:54:27.825238 7, 0xFFFF, sum = 0
2013 10:54:27.828523 8, 0xFFFF, sum = 0
2014 10:54:27.828609 9, 0x0, sum = 1
2015 10:54:27.828731 10, 0x0, sum = 2
2016 10:54:27.831535 11, 0x0, sum = 3
2017 10:54:27.831621 12, 0x0, sum = 4
2018 10:54:27.835035 best_step = 10
2019 10:54:27.835144
2020 10:54:27.835242 ==
2021 10:54:27.838539 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 10:54:27.841711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 10:54:27.841795 ==
2024 10:54:27.845232 RX Vref Scan: 0
2025 10:54:27.845315
2026 10:54:27.845381 RX Vref 0 -> 0, step: 1
2027 10:54:27.845442
2028 10:54:27.848528 RX Delay -95 -> 252, step: 8
2029 10:54:27.855049 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2030 10:54:27.858331 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2031 10:54:27.862087 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2032 10:54:27.865223 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2033 10:54:27.868396 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2034 10:54:27.874921 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2035 10:54:27.878223 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2036 10:54:27.881407 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2037 10:54:27.884747 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2038 10:54:27.888390 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2039 10:54:27.894817 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2040 10:54:27.898331 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2041 10:54:27.901951 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2042 10:54:27.905133 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2043 10:54:27.908541 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2044 10:54:27.914685 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2045 10:54:27.914769 ==
2046 10:54:27.918181 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 10:54:27.921396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 10:54:27.921473 ==
2049 10:54:27.921537 DQS Delay:
2050 10:54:27.924627 DQS0 = 0, DQS1 = 0
2051 10:54:27.924726 DQM Delay:
2052 10:54:27.928201 DQM0 = 91, DQM1 = 84
2053 10:54:27.928288 DQ Delay:
2054 10:54:27.931312 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2055 10:54:27.935051 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2056 10:54:27.938155 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2057 10:54:27.941673 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2058 10:54:27.941757
2059 10:54:27.941823
2060 10:54:27.951555 [DQSOSCAuto] RK1, (LSB)MR18= 0x360c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
2061 10:54:27.951638 CH1 RK1: MR19=606, MR18=360C
2062 10:54:27.957934 CH1_RK1: MR19=0x606, MR18=0x360C, DQSOSC=396, MR23=63, INC=94, DEC=62
2063 10:54:27.961636 [RxdqsGatingPostProcess] freq 800
2064 10:54:27.968149 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 10:54:27.971357 Pre-setting of DQS Precalculation
2066 10:54:27.974692 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 10:54:27.981574 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 10:54:27.988032 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 10:54:27.991625
2070 10:54:27.992156
2071 10:54:27.992588 [Calibration Summary] 1600 Mbps
2072 10:54:27.994726 CH 0, Rank 0
2073 10:54:27.995169 SW Impedance : PASS
2074 10:54:27.998334 DUTY Scan : NO K
2075 10:54:28.001489 ZQ Calibration : PASS
2076 10:54:28.001913 Jitter Meter : NO K
2077 10:54:28.004690 CBT Training : PASS
2078 10:54:28.008008 Write leveling : PASS
2079 10:54:28.008464 RX DQS gating : PASS
2080 10:54:28.011267 RX DQ/DQS(RDDQC) : PASS
2081 10:54:28.014586 TX DQ/DQS : PASS
2082 10:54:28.015121 RX DATLAT : PASS
2083 10:54:28.018205 RX DQ/DQS(Engine): PASS
2084 10:54:28.021080 TX OE : NO K
2085 10:54:28.021605 All Pass.
2086 10:54:28.021946
2087 10:54:28.022284 CH 0, Rank 1
2088 10:54:28.024599 SW Impedance : PASS
2089 10:54:28.028051 DUTY Scan : NO K
2090 10:54:28.028508 ZQ Calibration : PASS
2091 10:54:28.031295 Jitter Meter : NO K
2092 10:54:28.034588 CBT Training : PASS
2093 10:54:28.035010 Write leveling : PASS
2094 10:54:28.037817 RX DQS gating : PASS
2095 10:54:28.040922 RX DQ/DQS(RDDQC) : PASS
2096 10:54:28.041439 TX DQ/DQS : PASS
2097 10:54:28.044437 RX DATLAT : PASS
2098 10:54:28.047682 RX DQ/DQS(Engine): PASS
2099 10:54:28.048262 TX OE : NO K
2100 10:54:28.051048 All Pass.
2101 10:54:28.051593
2102 10:54:28.052062 CH 1, Rank 0
2103 10:54:28.054317 SW Impedance : PASS
2104 10:54:28.054810 DUTY Scan : NO K
2105 10:54:28.057524 ZQ Calibration : PASS
2106 10:54:28.060730 Jitter Meter : NO K
2107 10:54:28.061172 CBT Training : PASS
2108 10:54:28.064360 Write leveling : PASS
2109 10:54:28.064937 RX DQS gating : PASS
2110 10:54:28.067855 RX DQ/DQS(RDDQC) : PASS
2111 10:54:28.071100 TX DQ/DQS : PASS
2112 10:54:28.071706 RX DATLAT : PASS
2113 10:54:28.074320 RX DQ/DQS(Engine): PASS
2114 10:54:28.077528 TX OE : NO K
2115 10:54:28.078035 All Pass.
2116 10:54:28.078548
2117 10:54:28.079064 CH 1, Rank 1
2118 10:54:28.080682 SW Impedance : PASS
2119 10:54:28.083869 DUTY Scan : NO K
2120 10:54:28.084522 ZQ Calibration : PASS
2121 10:54:28.087574 Jitter Meter : NO K
2122 10:54:28.090616 CBT Training : PASS
2123 10:54:28.091259 Write leveling : PASS
2124 10:54:28.094174 RX DQS gating : PASS
2125 10:54:28.097404 RX DQ/DQS(RDDQC) : PASS
2126 10:54:28.097824 TX DQ/DQS : PASS
2127 10:54:28.100625 RX DATLAT : PASS
2128 10:54:28.103764 RX DQ/DQS(Engine): PASS
2129 10:54:28.104182 TX OE : NO K
2130 10:54:28.104517 All Pass.
2131 10:54:28.107486
2132 10:54:28.107901 DramC Write-DBI off
2133 10:54:28.110641 PER_BANK_REFRESH: Hybrid Mode
2134 10:54:28.111058 TX_TRACKING: ON
2135 10:54:28.113997 [GetDramInforAfterCalByMRR] Vendor 6.
2136 10:54:28.120269 [GetDramInforAfterCalByMRR] Revision 606.
2137 10:54:28.123751 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 10:54:28.124223 MR0 0x3b3b
2139 10:54:28.124798 MR8 0x5151
2140 10:54:28.127487 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 10:54:28.127910
2142 10:54:28.130757 MR0 0x3b3b
2143 10:54:28.131203 MR8 0x5151
2144 10:54:28.133954 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 10:54:28.134460
2146 10:54:28.143541 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 10:54:28.146920 [FAST_K] Save calibration result to emmc
2148 10:54:28.150422 [FAST_K] Save calibration result to emmc
2149 10:54:28.154060 dram_init: config_dvfs: 1
2150 10:54:28.156929 dramc_set_vcore_voltage set vcore to 662500
2151 10:54:28.160245 Read voltage for 1200, 2
2152 10:54:28.160861 Vio18 = 0
2153 10:54:28.161364 Vcore = 662500
2154 10:54:28.163782 Vdram = 0
2155 10:54:28.164288 Vddq = 0
2156 10:54:28.164787 Vmddr = 0
2157 10:54:28.170642 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 10:54:28.173747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 10:54:28.177546 MEM_TYPE=3, freq_sel=15
2160 10:54:28.180719 sv_algorithm_assistance_LP4_1600
2161 10:54:28.183662 ============ PULL DRAM RESETB DOWN ============
2162 10:54:28.186965 ========== PULL DRAM RESETB DOWN end =========
2163 10:54:28.193596 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 10:54:28.197012 ===================================
2165 10:54:28.197705 LPDDR4 DRAM CONFIGURATION
2166 10:54:28.200239 ===================================
2167 10:54:28.203583 EX_ROW_EN[0] = 0x0
2168 10:54:28.207246 EX_ROW_EN[1] = 0x0
2169 10:54:28.207904 LP4Y_EN = 0x0
2170 10:54:28.210553 WORK_FSP = 0x0
2171 10:54:28.211162 WL = 0x4
2172 10:54:28.213667 RL = 0x4
2173 10:54:28.214295 BL = 0x2
2174 10:54:28.217265 RPST = 0x0
2175 10:54:28.217895 RD_PRE = 0x0
2176 10:54:28.220361 WR_PRE = 0x1
2177 10:54:28.220968 WR_PST = 0x0
2178 10:54:28.223668 DBI_WR = 0x0
2179 10:54:28.224318 DBI_RD = 0x0
2180 10:54:28.226743 OTF = 0x1
2181 10:54:28.230021 ===================================
2182 10:54:28.233591 ===================================
2183 10:54:28.234085 ANA top config
2184 10:54:28.236988 ===================================
2185 10:54:28.240004 DLL_ASYNC_EN = 0
2186 10:54:28.243421 ALL_SLAVE_EN = 0
2187 10:54:28.243877 NEW_RANK_MODE = 1
2188 10:54:28.247288 DLL_IDLE_MODE = 1
2189 10:54:28.250384 LP45_APHY_COMB_EN = 1
2190 10:54:28.253715 TX_ODT_DIS = 1
2191 10:54:28.257047 NEW_8X_MODE = 1
2192 10:54:28.260168 ===================================
2193 10:54:28.263304 ===================================
2194 10:54:28.263747 data_rate = 2400
2195 10:54:28.266715 CKR = 1
2196 10:54:28.270013 DQ_P2S_RATIO = 8
2197 10:54:28.273351 ===================================
2198 10:54:28.276867 CA_P2S_RATIO = 8
2199 10:54:28.279974 DQ_CA_OPEN = 0
2200 10:54:28.283359 DQ_SEMI_OPEN = 0
2201 10:54:28.283875 CA_SEMI_OPEN = 0
2202 10:54:28.287122 CA_FULL_RATE = 0
2203 10:54:28.289888 DQ_CKDIV4_EN = 0
2204 10:54:28.293926 CA_CKDIV4_EN = 0
2205 10:54:28.296859 CA_PREDIV_EN = 0
2206 10:54:28.300362 PH8_DLY = 17
2207 10:54:28.300898 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 10:54:28.303135 DQ_AAMCK_DIV = 4
2209 10:54:28.306805 CA_AAMCK_DIV = 4
2210 10:54:28.309883 CA_ADMCK_DIV = 4
2211 10:54:28.313182 DQ_TRACK_CA_EN = 0
2212 10:54:28.316916 CA_PICK = 1200
2213 10:54:28.320045 CA_MCKIO = 1200
2214 10:54:28.320560 MCKIO_SEMI = 0
2215 10:54:28.323059 PLL_FREQ = 2366
2216 10:54:28.326576 DQ_UI_PI_RATIO = 32
2217 10:54:28.329746 CA_UI_PI_RATIO = 0
2218 10:54:28.333095 ===================================
2219 10:54:28.336301 ===================================
2220 10:54:28.339719 memory_type:LPDDR4
2221 10:54:28.340267 GP_NUM : 10
2222 10:54:28.343192 SRAM_EN : 1
2223 10:54:28.346398 MD32_EN : 0
2224 10:54:28.349942 ===================================
2225 10:54:28.350586 [ANA_INIT] >>>>>>>>>>>>>>
2226 10:54:28.352883 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 10:54:28.356475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 10:54:28.359987 ===================================
2229 10:54:28.363216 data_rate = 2400,PCW = 0X5b00
2230 10:54:28.366608 ===================================
2231 10:54:28.369583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 10:54:28.376604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 10:54:28.379620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 10:54:28.386180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 10:54:28.389722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 10:54:28.393071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 10:54:28.393795 [ANA_INIT] flow start
2238 10:54:28.396170 [ANA_INIT] PLL >>>>>>>>
2239 10:54:28.399476 [ANA_INIT] PLL <<<<<<<<
2240 10:54:28.400014 [ANA_INIT] MIDPI >>>>>>>>
2241 10:54:28.403107 [ANA_INIT] MIDPI <<<<<<<<
2242 10:54:28.406558 [ANA_INIT] DLL >>>>>>>>
2243 10:54:28.409737 [ANA_INIT] DLL <<<<<<<<
2244 10:54:28.410291 [ANA_INIT] flow end
2245 10:54:28.412866 ============ LP4 DIFF to SE enter ============
2246 10:54:28.419686 ============ LP4 DIFF to SE exit ============
2247 10:54:28.420112 [ANA_INIT] <<<<<<<<<<<<<
2248 10:54:28.422909 [Flow] Enable top DCM control >>>>>
2249 10:54:28.426201 [Flow] Enable top DCM control <<<<<
2250 10:54:28.429910 Enable DLL master slave shuffle
2251 10:54:28.436313 ==============================================================
2252 10:54:28.436840 Gating Mode config
2253 10:54:28.442850 ==============================================================
2254 10:54:28.446263 Config description:
2255 10:54:28.452954 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 10:54:28.459369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 10:54:28.466290 SELPH_MODE 0: By rank 1: By Phase
2258 10:54:28.472820 ==============================================================
2259 10:54:28.473351 GAT_TRACK_EN = 1
2260 10:54:28.476166 RX_GATING_MODE = 2
2261 10:54:28.479322 RX_GATING_TRACK_MODE = 2
2262 10:54:28.482628 SELPH_MODE = 1
2263 10:54:28.486071 PICG_EARLY_EN = 1
2264 10:54:28.489584 VALID_LAT_VALUE = 1
2265 10:54:28.496030 ==============================================================
2266 10:54:28.499630 Enter into Gating configuration >>>>
2267 10:54:28.502607 Exit from Gating configuration <<<<
2268 10:54:28.505981 Enter into DVFS_PRE_config >>>>>
2269 10:54:28.515960 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 10:54:28.519221 Exit from DVFS_PRE_config <<<<<
2271 10:54:28.522515 Enter into PICG configuration >>>>
2272 10:54:28.525860 Exit from PICG configuration <<<<
2273 10:54:28.529215 [RX_INPUT] configuration >>>>>
2274 10:54:28.529698 [RX_INPUT] configuration <<<<<
2275 10:54:28.535642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 10:54:28.542853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 10:54:28.549408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 10:54:28.552388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 10:54:28.558894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 10:54:28.565809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 10:54:28.568933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 10:54:28.572463 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 10:54:28.578808 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 10:54:28.582708 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 10:54:28.585580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 10:54:28.591999 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 10:54:28.595761 ===================================
2288 10:54:28.596245 LPDDR4 DRAM CONFIGURATION
2289 10:54:28.598724 ===================================
2290 10:54:28.602076 EX_ROW_EN[0] = 0x0
2291 10:54:28.602667 EX_ROW_EN[1] = 0x0
2292 10:54:28.605609 LP4Y_EN = 0x0
2293 10:54:28.608865 WORK_FSP = 0x0
2294 10:54:28.609450 WL = 0x4
2295 10:54:28.612033 RL = 0x4
2296 10:54:28.612497 BL = 0x2
2297 10:54:28.615807 RPST = 0x0
2298 10:54:28.616286 RD_PRE = 0x0
2299 10:54:28.618698 WR_PRE = 0x1
2300 10:54:28.619269 WR_PST = 0x0
2301 10:54:28.622216 DBI_WR = 0x0
2302 10:54:28.622764 DBI_RD = 0x0
2303 10:54:28.625514 OTF = 0x1
2304 10:54:28.628690 ===================================
2305 10:54:28.631908 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 10:54:28.635733 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 10:54:28.642291 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 10:54:28.645344 ===================================
2309 10:54:28.645891 LPDDR4 DRAM CONFIGURATION
2310 10:54:28.648744 ===================================
2311 10:54:28.652356 EX_ROW_EN[0] = 0x10
2312 10:54:28.652918 EX_ROW_EN[1] = 0x0
2313 10:54:28.655052 LP4Y_EN = 0x0
2314 10:54:28.655599 WORK_FSP = 0x0
2315 10:54:28.658495 WL = 0x4
2316 10:54:28.662049 RL = 0x4
2317 10:54:28.662466 BL = 0x2
2318 10:54:28.665065 RPST = 0x0
2319 10:54:28.665660 RD_PRE = 0x0
2320 10:54:28.668419 WR_PRE = 0x1
2321 10:54:28.668854 WR_PST = 0x0
2322 10:54:28.671818 DBI_WR = 0x0
2323 10:54:28.672380 DBI_RD = 0x0
2324 10:54:28.674889 OTF = 0x1
2325 10:54:28.678524 ===================================
2326 10:54:28.685123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 10:54:28.685577 ==
2328 10:54:28.688517 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 10:54:28.691517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 10:54:28.692161 ==
2331 10:54:28.695192 [Duty_Offset_Calibration]
2332 10:54:28.695635 B0:2 B1:0 CA:1
2333 10:54:28.695958
2334 10:54:28.698531 [DutyScan_Calibration_Flow] k_type=0
2335 10:54:28.707239
2336 10:54:28.707644 ==CLK 0==
2337 10:54:28.710792 Final CLK duty delay cell = -4
2338 10:54:28.713919 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2339 10:54:28.717571 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2340 10:54:28.720320 [-4] AVG Duty = 4953%(X100)
2341 10:54:28.720826
2342 10:54:28.723591 CH0 CLK Duty spec in!! Max-Min= 156%
2343 10:54:28.727049 [DutyScan_Calibration_Flow] ====Done====
2344 10:54:28.727461
2345 10:54:28.730311 [DutyScan_Calibration_Flow] k_type=1
2346 10:54:28.746209
2347 10:54:28.746611 ==DQS 0 ==
2348 10:54:28.749615 Final DQS duty delay cell = 0
2349 10:54:28.752946 [0] MAX Duty = 5187%(X100), DQS PI = 30
2350 10:54:28.756028 [0] MIN Duty = 4938%(X100), DQS PI = 2
2351 10:54:28.756572 [0] AVG Duty = 5062%(X100)
2352 10:54:28.759347
2353 10:54:28.759912 ==DQS 1 ==
2354 10:54:28.762804 Final DQS duty delay cell = -4
2355 10:54:28.766042 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2356 10:54:28.769434 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2357 10:54:28.773139 [-4] AVG Duty = 5031%(X100)
2358 10:54:28.773693
2359 10:54:28.776265 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2360 10:54:28.776850
2361 10:54:28.779858 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2362 10:54:28.782767 [DutyScan_Calibration_Flow] ====Done====
2363 10:54:28.783238
2364 10:54:28.786260 [DutyScan_Calibration_Flow] k_type=3
2365 10:54:28.802849
2366 10:54:28.803427 ==DQM 0 ==
2367 10:54:28.806416 Final DQM duty delay cell = 0
2368 10:54:28.809793 [0] MAX Duty = 5062%(X100), DQS PI = 26
2369 10:54:28.812797 [0] MIN Duty = 4875%(X100), DQS PI = 0
2370 10:54:28.813362 [0] AVG Duty = 4968%(X100)
2371 10:54:28.816104
2372 10:54:28.816535 ==DQM 1 ==
2373 10:54:28.819657 Final DQM duty delay cell = 0
2374 10:54:28.823097 [0] MAX Duty = 5187%(X100), DQS PI = 46
2375 10:54:28.826099 [0] MIN Duty = 5000%(X100), DQS PI = 22
2376 10:54:28.829569 [0] AVG Duty = 5093%(X100)
2377 10:54:28.829994
2378 10:54:28.833013 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2379 10:54:28.833623
2380 10:54:28.835947 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2381 10:54:28.839731 [DutyScan_Calibration_Flow] ====Done====
2382 10:54:28.840285
2383 10:54:28.842699 [DutyScan_Calibration_Flow] k_type=2
2384 10:54:28.859766
2385 10:54:28.860329 ==DQ 0 ==
2386 10:54:28.862876 Final DQ duty delay cell = -4
2387 10:54:28.865840 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2388 10:54:28.869425 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2389 10:54:28.872734 [-4] AVG Duty = 4953%(X100)
2390 10:54:28.873308
2391 10:54:28.873658 ==DQ 1 ==
2392 10:54:28.876393 Final DQ duty delay cell = 4
2393 10:54:28.879725 [4] MAX Duty = 5093%(X100), DQS PI = 4
2394 10:54:28.882606 [4] MIN Duty = 5031%(X100), DQS PI = 0
2395 10:54:28.883034 [4] AVG Duty = 5062%(X100)
2396 10:54:28.886184
2397 10:54:28.889297 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2398 10:54:28.889854
2399 10:54:28.892913 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2400 10:54:28.896058 [DutyScan_Calibration_Flow] ====Done====
2401 10:54:28.896602 ==
2402 10:54:28.899336 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 10:54:28.902919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 10:54:28.903526 ==
2405 10:54:28.906143 [Duty_Offset_Calibration]
2406 10:54:28.906718 B0:0 B1:-1 CA:2
2407 10:54:28.907198
2408 10:54:28.909513 [DutyScan_Calibration_Flow] k_type=0
2409 10:54:28.919499
2410 10:54:28.920054 ==CLK 0==
2411 10:54:28.922951 Final CLK duty delay cell = 0
2412 10:54:28.926338 [0] MAX Duty = 5156%(X100), DQS PI = 16
2413 10:54:28.929642 [0] MIN Duty = 4938%(X100), DQS PI = 44
2414 10:54:28.930183 [0] AVG Duty = 5047%(X100)
2415 10:54:28.933011
2416 10:54:28.936033 CH1 CLK Duty spec in!! Max-Min= 218%
2417 10:54:28.939724 [DutyScan_Calibration_Flow] ====Done====
2418 10:54:28.940225
2419 10:54:28.942889 [DutyScan_Calibration_Flow] k_type=1
2420 10:54:28.959357
2421 10:54:28.959928 ==DQS 0 ==
2422 10:54:28.962218 Final DQS duty delay cell = 0
2423 10:54:28.965654 [0] MAX Duty = 5093%(X100), DQS PI = 24
2424 10:54:28.969136 [0] MIN Duty = 4969%(X100), DQS PI = 0
2425 10:54:28.969749 [0] AVG Duty = 5031%(X100)
2426 10:54:28.972259
2427 10:54:28.972814 ==DQS 1 ==
2428 10:54:28.975674 Final DQS duty delay cell = 0
2429 10:54:28.979039 [0] MAX Duty = 5156%(X100), DQS PI = 0
2430 10:54:28.982237 [0] MIN Duty = 4844%(X100), DQS PI = 36
2431 10:54:28.982788 [0] AVG Duty = 5000%(X100)
2432 10:54:28.985829
2433 10:54:28.989194 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2434 10:54:28.989655
2435 10:54:28.992617 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2436 10:54:28.995714 [DutyScan_Calibration_Flow] ====Done====
2437 10:54:28.996192
2438 10:54:28.998933 [DutyScan_Calibration_Flow] k_type=3
2439 10:54:29.015690
2440 10:54:29.016259 ==DQM 0 ==
2441 10:54:29.018844 Final DQM duty delay cell = 4
2442 10:54:29.021889 [4] MAX Duty = 5093%(X100), DQS PI = 4
2443 10:54:29.025153 [4] MIN Duty = 4938%(X100), DQS PI = 48
2444 10:54:29.028758 [4] AVG Duty = 5015%(X100)
2445 10:54:29.029240
2446 10:54:29.029774 ==DQM 1 ==
2447 10:54:29.032019 Final DQM duty delay cell = -4
2448 10:54:29.035129 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2449 10:54:29.038521 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2450 10:54:29.041770 [-4] AVG Duty = 4875%(X100)
2451 10:54:29.042255
2452 10:54:29.045011 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2453 10:54:29.045460
2454 10:54:29.048274 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2455 10:54:29.051889 [DutyScan_Calibration_Flow] ====Done====
2456 10:54:29.052329
2457 10:54:29.055076 [DutyScan_Calibration_Flow] k_type=2
2458 10:54:29.072215
2459 10:54:29.072309 ==DQ 0 ==
2460 10:54:29.075199 Final DQ duty delay cell = 0
2461 10:54:29.078653 [0] MAX Duty = 5062%(X100), DQS PI = 20
2462 10:54:29.081668 [0] MIN Duty = 4938%(X100), DQS PI = 44
2463 10:54:29.084882 [0] AVG Duty = 5000%(X100)
2464 10:54:29.084964
2465 10:54:29.085030 ==DQ 1 ==
2466 10:54:29.088621 Final DQ duty delay cell = 0
2467 10:54:29.091882 [0] MAX Duty = 5031%(X100), DQS PI = 2
2468 10:54:29.095024 [0] MIN Duty = 4813%(X100), DQS PI = 36
2469 10:54:29.095107 [0] AVG Duty = 4922%(X100)
2470 10:54:29.098263
2471 10:54:29.101489 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2472 10:54:29.101572
2473 10:54:29.104679 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2474 10:54:29.107895 [DutyScan_Calibration_Flow] ====Done====
2475 10:54:29.111351 nWR fixed to 30
2476 10:54:29.114524 [ModeRegInit_LP4] CH0 RK0
2477 10:54:29.114607 [ModeRegInit_LP4] CH0 RK1
2478 10:54:29.118339 [ModeRegInit_LP4] CH1 RK0
2479 10:54:29.121319 [ModeRegInit_LP4] CH1 RK1
2480 10:54:29.121402 match AC timing 7
2481 10:54:29.127784 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 10:54:29.131253 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 10:54:29.134434 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 10:54:29.140910 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 10:54:29.144388 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 10:54:29.144470 ==
2487 10:54:29.147769 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 10:54:29.150961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 10:54:29.151045 ==
2490 10:54:29.157326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 10:54:29.164003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 10:54:29.171594 [CA 0] Center 38 (7~69) winsize 63
2493 10:54:29.175408 [CA 1] Center 38 (8~69) winsize 62
2494 10:54:29.178316 [CA 2] Center 35 (4~66) winsize 63
2495 10:54:29.181766 [CA 3] Center 35 (4~66) winsize 63
2496 10:54:29.184859 [CA 4] Center 34 (4~65) winsize 62
2497 10:54:29.188404 [CA 5] Center 33 (3~63) winsize 61
2498 10:54:29.188482
2499 10:54:29.191462 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 10:54:29.191538
2501 10:54:29.195058 [CATrainingPosCal] consider 1 rank data
2502 10:54:29.198359 u2DelayCellTimex100 = 270/100 ps
2503 10:54:29.201483 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2504 10:54:29.208163 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2505 10:54:29.211632 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2506 10:54:29.214920 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2507 10:54:29.218302 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2508 10:54:29.221430 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 10:54:29.221534
2510 10:54:29.224995 CA PerBit enable=1, Macro0, CA PI delay=33
2511 10:54:29.225099
2512 10:54:29.228179 [CBTSetCACLKResult] CA Dly = 33
2513 10:54:29.228291 CS Dly: 6 (0~37)
2514 10:54:29.231372 ==
2515 10:54:29.235180 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 10:54:29.238421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 10:54:29.238558 ==
2518 10:54:29.241772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 10:54:29.248247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 10:54:29.257928 [CA 0] Center 39 (8~70) winsize 63
2521 10:54:29.261404 [CA 1] Center 38 (8~69) winsize 62
2522 10:54:29.264665 [CA 2] Center 35 (5~66) winsize 62
2523 10:54:29.267966 [CA 3] Center 35 (5~66) winsize 62
2524 10:54:29.271357 [CA 4] Center 34 (4~65) winsize 62
2525 10:54:29.274831 [CA 5] Center 34 (4~64) winsize 61
2526 10:54:29.275259
2527 10:54:29.278145 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2528 10:54:29.278594
2529 10:54:29.281077 [CATrainingPosCal] consider 2 rank data
2530 10:54:29.284640 u2DelayCellTimex100 = 270/100 ps
2531 10:54:29.287938 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2532 10:54:29.291086 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2533 10:54:29.297796 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 10:54:29.301205 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 10:54:29.304220 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 10:54:29.307602 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2537 10:54:29.308081
2538 10:54:29.310883 CA PerBit enable=1, Macro0, CA PI delay=33
2539 10:54:29.311305
2540 10:54:29.314480 [CBTSetCACLKResult] CA Dly = 33
2541 10:54:29.314905 CS Dly: 7 (0~39)
2542 10:54:29.315276
2543 10:54:29.317419 ----->DramcWriteLeveling(PI) begin...
2544 10:54:29.320911 ==
2545 10:54:29.324202 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 10:54:29.327484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 10:54:29.327904 ==
2548 10:54:29.330902 Write leveling (Byte 0): 33 => 33
2549 10:54:29.334395 Write leveling (Byte 1): 30 => 30
2550 10:54:29.337574 DramcWriteLeveling(PI) end<-----
2551 10:54:29.337989
2552 10:54:29.338322 ==
2553 10:54:29.340693 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 10:54:29.344239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 10:54:29.344661 ==
2556 10:54:29.347534 [Gating] SW mode calibration
2557 10:54:29.354018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 10:54:29.360896 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 10:54:29.363994 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2560 10:54:29.367422 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2561 10:54:29.374171 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 10:54:29.377372 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 10:54:29.380583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 10:54:29.384154 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 10:54:29.390655 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2566 10:54:29.394185 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2567 10:54:29.397753 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2568 10:54:29.404007 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 10:54:29.407131 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 10:54:29.410866 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 10:54:29.417386 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 10:54:29.420533 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 10:54:29.424218 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2574 10:54:29.430646 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2575 10:54:29.434051 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
2576 10:54:29.437183 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 10:54:29.443841 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 10:54:29.447118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 10:54:29.450332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 10:54:29.457188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 10:54:29.460502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 10:54:29.463940 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 10:54:29.470747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2584 10:54:29.473808 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 10:54:29.477371 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 10:54:29.484093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 10:54:29.487144 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 10:54:29.490822 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 10:54:29.497101 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 10:54:29.500235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 10:54:29.503633 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 10:54:29.510026 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 10:54:29.513568 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 10:54:29.516862 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 10:54:29.520171 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 10:54:29.526614 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 10:54:29.530222 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2598 10:54:29.533758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 10:54:29.540146 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2600 10:54:29.543441 Total UI for P1: 0, mck2ui 16
2601 10:54:29.546924 best dqsien dly found for B0: ( 1, 3, 26)
2602 10:54:29.550197 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 10:54:29.553424 Total UI for P1: 0, mck2ui 16
2604 10:54:29.556564 best dqsien dly found for B1: ( 1, 4, 0)
2605 10:54:29.559848 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2606 10:54:29.563536 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2607 10:54:29.563958
2608 10:54:29.566622 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2609 10:54:29.570059 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2610 10:54:29.573368 [Gating] SW calibration Done
2611 10:54:29.573792 ==
2612 10:54:29.576832 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 10:54:29.583381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 10:54:29.583803 ==
2615 10:54:29.584136 RX Vref Scan: 0
2616 10:54:29.584448
2617 10:54:29.586712 RX Vref 0 -> 0, step: 1
2618 10:54:29.587133
2619 10:54:29.590092 RX Delay -40 -> 252, step: 8
2620 10:54:29.593037 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2621 10:54:29.596417 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2622 10:54:29.599916 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2623 10:54:29.603156 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2624 10:54:29.609813 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2625 10:54:29.613093 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2626 10:54:29.616203 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2627 10:54:29.620052 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2628 10:54:29.623126 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2629 10:54:29.629917 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2630 10:54:29.632863 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2631 10:54:29.636140 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2632 10:54:29.639461 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2633 10:54:29.642980 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2634 10:54:29.649672 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2635 10:54:29.652862 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2636 10:54:29.653267 ==
2637 10:54:29.656344 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 10:54:29.659519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 10:54:29.659961 ==
2640 10:54:29.662885 DQS Delay:
2641 10:54:29.663264 DQS0 = 0, DQS1 = 0
2642 10:54:29.663585 DQM Delay:
2643 10:54:29.666051 DQM0 = 123, DQM1 = 111
2644 10:54:29.666487 DQ Delay:
2645 10:54:29.669222 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2646 10:54:29.672835 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2647 10:54:29.679427 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2648 10:54:29.682797 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2649 10:54:29.683272
2650 10:54:29.683614
2651 10:54:29.683973 ==
2652 10:54:29.686173 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 10:54:29.689223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 10:54:29.689800 ==
2655 10:54:29.690148
2656 10:54:29.690483
2657 10:54:29.692846 TX Vref Scan disable
2658 10:54:29.696046 == TX Byte 0 ==
2659 10:54:29.699304 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2660 10:54:29.702586 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2661 10:54:29.705788 == TX Byte 1 ==
2662 10:54:29.709332 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2663 10:54:29.712650 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2664 10:54:29.713239 ==
2665 10:54:29.716159 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 10:54:29.719368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 10:54:29.719796 ==
2668 10:54:29.732347 TX Vref=22, minBit 1, minWin=24, winSum=407
2669 10:54:29.735551 TX Vref=24, minBit 1, minWin=24, winSum=416
2670 10:54:29.739079 TX Vref=26, minBit 0, minWin=24, winSum=417
2671 10:54:29.742438 TX Vref=28, minBit 4, minWin=25, winSum=426
2672 10:54:29.745669 TX Vref=30, minBit 7, minWin=25, winSum=427
2673 10:54:29.749048 TX Vref=32, minBit 1, minWin=25, winSum=422
2674 10:54:29.755846 [TxChooseVref] Worse bit 7, Min win 25, Win sum 427, Final Vref 30
2675 10:54:29.756416
2676 10:54:29.758838 Final TX Range 1 Vref 30
2677 10:54:29.759363
2678 10:54:29.759880 ==
2679 10:54:29.762277 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 10:54:29.765479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 10:54:29.766047 ==
2682 10:54:29.768719
2683 10:54:29.769367
2684 10:54:29.769985 TX Vref Scan disable
2685 10:54:29.771880 == TX Byte 0 ==
2686 10:54:29.775024 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2687 10:54:29.778246 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2688 10:54:29.781857 == TX Byte 1 ==
2689 10:54:29.785053 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2690 10:54:29.791638 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2691 10:54:29.791748
2692 10:54:29.791833 [DATLAT]
2693 10:54:29.791912 Freq=1200, CH0 RK0
2694 10:54:29.791991
2695 10:54:29.795058 DATLAT Default: 0xd
2696 10:54:29.795172 0, 0xFFFF, sum = 0
2697 10:54:29.798336 1, 0xFFFF, sum = 0
2698 10:54:29.798454 2, 0xFFFF, sum = 0
2699 10:54:29.801806 3, 0xFFFF, sum = 0
2700 10:54:29.804899 4, 0xFFFF, sum = 0
2701 10:54:29.804986 5, 0xFFFF, sum = 0
2702 10:54:29.808223 6, 0xFFFF, sum = 0
2703 10:54:29.808337 7, 0xFFFF, sum = 0
2704 10:54:29.811348 8, 0xFFFF, sum = 0
2705 10:54:29.811467 9, 0xFFFF, sum = 0
2706 10:54:29.815042 10, 0xFFFF, sum = 0
2707 10:54:29.815146 11, 0xFFFF, sum = 0
2708 10:54:29.818359 12, 0x0, sum = 1
2709 10:54:29.818449 13, 0x0, sum = 2
2710 10:54:29.821513 14, 0x0, sum = 3
2711 10:54:29.821621 15, 0x0, sum = 4
2712 10:54:29.821726 best_step = 13
2713 10:54:29.824802
2714 10:54:29.824929 ==
2715 10:54:29.828331 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 10:54:29.831784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 10:54:29.831900 ==
2718 10:54:29.831977 RX Vref Scan: 1
2719 10:54:29.832040
2720 10:54:29.834736 Set Vref Range= 32 -> 127
2721 10:54:29.834846
2722 10:54:29.838434 RX Vref 32 -> 127, step: 1
2723 10:54:29.838543
2724 10:54:29.841428 RX Delay -13 -> 252, step: 4
2725 10:54:29.841514
2726 10:54:29.844974 Set Vref, RX VrefLevel [Byte0]: 32
2727 10:54:29.848205 [Byte1]: 32
2728 10:54:29.848308
2729 10:54:29.851788 Set Vref, RX VrefLevel [Byte0]: 33
2730 10:54:29.854820 [Byte1]: 33
2731 10:54:29.858618
2732 10:54:29.859176 Set Vref, RX VrefLevel [Byte0]: 34
2733 10:54:29.861832 [Byte1]: 34
2734 10:54:29.866517
2735 10:54:29.869646 Set Vref, RX VrefLevel [Byte0]: 35
2736 10:54:29.870170 [Byte1]: 35
2737 10:54:29.874101
2738 10:54:29.874637 Set Vref, RX VrefLevel [Byte0]: 36
2739 10:54:29.877852 [Byte1]: 36
2740 10:54:29.882381
2741 10:54:29.882823 Set Vref, RX VrefLevel [Byte0]: 37
2742 10:54:29.885509 [Byte1]: 37
2743 10:54:29.890080
2744 10:54:29.890653 Set Vref, RX VrefLevel [Byte0]: 38
2745 10:54:29.893523 [Byte1]: 38
2746 10:54:29.897724
2747 10:54:29.898287 Set Vref, RX VrefLevel [Byte0]: 39
2748 10:54:29.901397 [Byte1]: 39
2749 10:54:29.905848
2750 10:54:29.906436 Set Vref, RX VrefLevel [Byte0]: 40
2751 10:54:29.909235 [Byte1]: 40
2752 10:54:29.913871
2753 10:54:29.914319 Set Vref, RX VrefLevel [Byte0]: 41
2754 10:54:29.916923 [Byte1]: 41
2755 10:54:29.921606
2756 10:54:29.922214 Set Vref, RX VrefLevel [Byte0]: 42
2757 10:54:29.924620 [Byte1]: 42
2758 10:54:29.929522
2759 10:54:29.930087 Set Vref, RX VrefLevel [Byte0]: 43
2760 10:54:29.932595 [Byte1]: 43
2761 10:54:29.937171
2762 10:54:29.937638 Set Vref, RX VrefLevel [Byte0]: 44
2763 10:54:29.940721 [Byte1]: 44
2764 10:54:29.945044
2765 10:54:29.945471 Set Vref, RX VrefLevel [Byte0]: 45
2766 10:54:29.948824 [Byte1]: 45
2767 10:54:29.952969
2768 10:54:29.953397 Set Vref, RX VrefLevel [Byte0]: 46
2769 10:54:29.956461 [Byte1]: 46
2770 10:54:29.961080
2771 10:54:29.961507 Set Vref, RX VrefLevel [Byte0]: 47
2772 10:54:29.964084 [Byte1]: 47
2773 10:54:29.968924
2774 10:54:29.969352 Set Vref, RX VrefLevel [Byte0]: 48
2775 10:54:29.971993 [Byte1]: 48
2776 10:54:29.977072
2777 10:54:29.977504 Set Vref, RX VrefLevel [Byte0]: 49
2778 10:54:29.980111 [Byte1]: 49
2779 10:54:29.984503
2780 10:54:29.985116 Set Vref, RX VrefLevel [Byte0]: 50
2781 10:54:29.988318 [Byte1]: 50
2782 10:54:29.992630
2783 10:54:29.993214 Set Vref, RX VrefLevel [Byte0]: 51
2784 10:54:29.995711 [Byte1]: 51
2785 10:54:30.000732
2786 10:54:30.001310 Set Vref, RX VrefLevel [Byte0]: 52
2787 10:54:30.003954 [Byte1]: 52
2788 10:54:30.008506
2789 10:54:30.008984 Set Vref, RX VrefLevel [Byte0]: 53
2790 10:54:30.011445 [Byte1]: 53
2791 10:54:30.015992
2792 10:54:30.016103 Set Vref, RX VrefLevel [Byte0]: 54
2793 10:54:30.019261 [Byte1]: 54
2794 10:54:30.023766
2795 10:54:30.023876 Set Vref, RX VrefLevel [Byte0]: 55
2796 10:54:30.026978 [Byte1]: 55
2797 10:54:30.031902
2798 10:54:30.032013 Set Vref, RX VrefLevel [Byte0]: 56
2799 10:54:30.034963 [Byte1]: 56
2800 10:54:30.039423
2801 10:54:30.039535 Set Vref, RX VrefLevel [Byte0]: 57
2802 10:54:30.042953 [Byte1]: 57
2803 10:54:30.047356
2804 10:54:30.047465 Set Vref, RX VrefLevel [Byte0]: 58
2805 10:54:30.050864 [Byte1]: 58
2806 10:54:30.055408
2807 10:54:30.055483 Set Vref, RX VrefLevel [Byte0]: 59
2808 10:54:30.058470 [Byte1]: 59
2809 10:54:30.063381
2810 10:54:30.063453 Set Vref, RX VrefLevel [Byte0]: 60
2811 10:54:30.066800 [Byte1]: 60
2812 10:54:30.071458
2813 10:54:30.071581 Set Vref, RX VrefLevel [Byte0]: 61
2814 10:54:30.074660 [Byte1]: 61
2815 10:54:30.079116
2816 10:54:30.079250 Set Vref, RX VrefLevel [Byte0]: 62
2817 10:54:30.082370 [Byte1]: 62
2818 10:54:30.087352
2819 10:54:30.087502 Set Vref, RX VrefLevel [Byte0]: 63
2820 10:54:30.090290 [Byte1]: 63
2821 10:54:30.094727
2822 10:54:30.094899 Set Vref, RX VrefLevel [Byte0]: 64
2823 10:54:30.098257 [Byte1]: 64
2824 10:54:30.102778
2825 10:54:30.102998 Set Vref, RX VrefLevel [Byte0]: 65
2826 10:54:30.106047 [Byte1]: 65
2827 10:54:30.111047
2828 10:54:30.111388 Set Vref, RX VrefLevel [Byte0]: 66
2829 10:54:30.114239 [Byte1]: 66
2830 10:54:30.118636
2831 10:54:30.119058 Set Vref, RX VrefLevel [Byte0]: 67
2832 10:54:30.122421 [Byte1]: 67
2833 10:54:30.126881
2834 10:54:30.127410 Set Vref, RX VrefLevel [Byte0]: 68
2835 10:54:30.129904 [Byte1]: 68
2836 10:54:30.134845
2837 10:54:30.135474 Set Vref, RX VrefLevel [Byte0]: 69
2838 10:54:30.137845 [Byte1]: 69
2839 10:54:30.142550
2840 10:54:30.142980 Set Vref, RX VrefLevel [Byte0]: 70
2841 10:54:30.145626 [Byte1]: 70
2842 10:54:30.150422
2843 10:54:30.150949 Final RX Vref Byte 0 = 60 to rank0
2844 10:54:30.153611 Final RX Vref Byte 1 = 49 to rank0
2845 10:54:30.157217 Final RX Vref Byte 0 = 60 to rank1
2846 10:54:30.160416 Final RX Vref Byte 1 = 49 to rank1==
2847 10:54:30.163799 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 10:54:30.170864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 10:54:30.171319 ==
2850 10:54:30.171655 DQS Delay:
2851 10:54:30.171965 DQS0 = 0, DQS1 = 0
2852 10:54:30.173897 DQM Delay:
2853 10:54:30.174437 DQM0 = 123, DQM1 = 109
2854 10:54:30.176891 DQ Delay:
2855 10:54:30.180092 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2856 10:54:30.183600 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2857 10:54:30.187207 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2858 10:54:30.190327 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2859 10:54:30.190812
2860 10:54:30.191412
2861 10:54:30.200331 [DQSOSCAuto] RK0, (LSB)MR18= 0x704, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2862 10:54:30.200916 CH0 RK0: MR19=404, MR18=704
2863 10:54:30.206746 CH0_RK0: MR19=0x404, MR18=0x704, DQSOSC=407, MR23=63, INC=39, DEC=26
2864 10:54:30.207457
2865 10:54:30.210146 ----->DramcWriteLeveling(PI) begin...
2866 10:54:30.210527 ==
2867 10:54:30.213849 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 10:54:30.217155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 10:54:30.219990 ==
2870 10:54:30.220553 Write leveling (Byte 0): 34 => 34
2871 10:54:30.223547 Write leveling (Byte 1): 31 => 31
2872 10:54:30.226808 DramcWriteLeveling(PI) end<-----
2873 10:54:30.227228
2874 10:54:30.227562 ==
2875 10:54:30.229920 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 10:54:30.236709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 10:54:30.237443 ==
2878 10:54:30.240300 [Gating] SW mode calibration
2879 10:54:30.246342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 10:54:30.249849 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 10:54:30.256485 0 15 0 | B1->B0 | 3030 3434 | 0 0 | (1 1) (0 0)
2882 10:54:30.259750 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 10:54:30.263030 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 10:54:30.269484 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 10:54:30.272869 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 10:54:30.276220 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 10:54:30.283105 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 10:54:30.286263 0 15 28 | B1->B0 | 3232 3232 | 1 0 | (1 0) (0 1)
2889 10:54:30.289421 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 10:54:30.295956 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 10:54:30.299540 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 10:54:30.302787 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 10:54:30.310500 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 10:54:30.312507 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 10:54:30.316210 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 10:54:30.319298 1 0 28 | B1->B0 | 3636 4242 | 0 1 | (0 0) (0 0)
2897 10:54:30.326024 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 10:54:30.329088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 10:54:30.332491 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 10:54:30.339063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 10:54:30.342428 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 10:54:30.346207 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 10:54:30.352322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 10:54:30.355402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 10:54:30.358717 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:54:30.365315 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:54:30.368797 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 10:54:30.371791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 10:54:30.378859 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 10:54:30.382017 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 10:54:30.385595 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 10:54:30.392130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 10:54:30.395365 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 10:54:30.398554 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 10:54:30.405474 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 10:54:30.408705 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 10:54:30.412361 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 10:54:30.418815 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 10:54:30.422131 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2920 10:54:30.425259 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2921 10:54:30.432123 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 10:54:30.432553 Total UI for P1: 0, mck2ui 16
2923 10:54:30.439033 best dqsien dly found for B0: ( 1, 3, 26)
2924 10:54:30.439462 Total UI for P1: 0, mck2ui 16
2925 10:54:30.442204 best dqsien dly found for B1: ( 1, 3, 30)
2926 10:54:30.448631 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2927 10:54:30.452054 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2928 10:54:30.452482
2929 10:54:30.455668 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2930 10:54:30.458789 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2931 10:54:30.462277 [Gating] SW calibration Done
2932 10:54:30.462703 ==
2933 10:54:30.465386 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 10:54:30.468482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 10:54:30.468941 ==
2936 10:54:30.472111 RX Vref Scan: 0
2937 10:54:30.472536
2938 10:54:30.472900 RX Vref 0 -> 0, step: 1
2939 10:54:30.473223
2940 10:54:30.475116 RX Delay -40 -> 252, step: 8
2941 10:54:30.478721 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2942 10:54:30.485533 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 10:54:30.488329 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2944 10:54:30.491976 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2945 10:54:30.495278 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2946 10:54:30.498701 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2947 10:54:30.505255 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 10:54:30.508438 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2949 10:54:30.512094 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2950 10:54:30.515097 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2951 10:54:30.518536 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2952 10:54:30.521698 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2953 10:54:30.528601 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2954 10:54:30.531841 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2955 10:54:30.535198 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2956 10:54:30.538454 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2957 10:54:30.538877 ==
2958 10:54:30.541706 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 10:54:30.548508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 10:54:30.548974 ==
2961 10:54:30.549314 DQS Delay:
2962 10:54:30.551812 DQS0 = 0, DQS1 = 0
2963 10:54:30.552234 DQM Delay:
2964 10:54:30.555203 DQM0 = 120, DQM1 = 108
2965 10:54:30.555624 DQ Delay:
2966 10:54:30.558543 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2967 10:54:30.561926 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2968 10:54:30.565368 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2969 10:54:30.568650 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2970 10:54:30.569150
2971 10:54:30.569496
2972 10:54:30.569905 ==
2973 10:54:30.571770 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 10:54:30.575334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 10:54:30.578520 ==
2976 10:54:30.578952
2977 10:54:30.579291
2978 10:54:30.579602 TX Vref Scan disable
2979 10:54:30.581601 == TX Byte 0 ==
2980 10:54:30.585208 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2981 10:54:30.588147 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2982 10:54:30.591751 == TX Byte 1 ==
2983 10:54:30.595039 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2984 10:54:30.598687 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2985 10:54:30.601825 ==
2986 10:54:30.602285 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 10:54:30.608508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 10:54:30.609100 ==
2989 10:54:30.619286 TX Vref=22, minBit 0, minWin=25, winSum=414
2990 10:54:30.623095 TX Vref=24, minBit 7, minWin=24, winSum=417
2991 10:54:30.625963 TX Vref=26, minBit 2, minWin=25, winSum=417
2992 10:54:30.629684 TX Vref=28, minBit 7, minWin=24, winSum=418
2993 10:54:30.632964 TX Vref=30, minBit 5, minWin=25, winSum=425
2994 10:54:30.636225 TX Vref=32, minBit 2, minWin=25, winSum=423
2995 10:54:30.642758 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
2996 10:54:30.643341
2997 10:54:30.645906 Final TX Range 1 Vref 30
2998 10:54:30.646378
2999 10:54:30.646864 ==
3000 10:54:30.649156 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 10:54:30.652701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 10:54:30.653099 ==
3003 10:54:30.655918
3004 10:54:30.656405
3005 10:54:30.656937 TX Vref Scan disable
3006 10:54:30.659276 == TX Byte 0 ==
3007 10:54:30.662379 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3008 10:54:30.665765 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3009 10:54:30.669306 == TX Byte 1 ==
3010 10:54:30.672157 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3011 10:54:30.679118 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3012 10:54:30.679756
3013 10:54:30.680273 [DATLAT]
3014 10:54:30.680812 Freq=1200, CH0 RK1
3015 10:54:30.681154
3016 10:54:30.682606 DATLAT Default: 0xd
3017 10:54:30.683031 0, 0xFFFF, sum = 0
3018 10:54:30.685836 1, 0xFFFF, sum = 0
3019 10:54:30.686430 2, 0xFFFF, sum = 0
3020 10:54:30.689133 3, 0xFFFF, sum = 0
3021 10:54:30.692430 4, 0xFFFF, sum = 0
3022 10:54:30.693164 5, 0xFFFF, sum = 0
3023 10:54:30.696066 6, 0xFFFF, sum = 0
3024 10:54:30.696532 7, 0xFFFF, sum = 0
3025 10:54:30.699090 8, 0xFFFF, sum = 0
3026 10:54:30.699707 9, 0xFFFF, sum = 0
3027 10:54:30.702476 10, 0xFFFF, sum = 0
3028 10:54:30.703080 11, 0xFFFF, sum = 0
3029 10:54:30.705571 12, 0x0, sum = 1
3030 10:54:30.705961 13, 0x0, sum = 2
3031 10:54:30.709046 14, 0x0, sum = 3
3032 10:54:30.709447 15, 0x0, sum = 4
3033 10:54:30.709836 best_step = 13
3034 10:54:30.712453
3035 10:54:30.712894 ==
3036 10:54:30.715727 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 10:54:30.719132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 10:54:30.719614 ==
3039 10:54:30.719998 RX Vref Scan: 0
3040 10:54:30.720412
3041 10:54:30.722225 RX Vref 0 -> 0, step: 1
3042 10:54:30.722719
3043 10:54:30.725871 RX Delay -21 -> 252, step: 4
3044 10:54:30.728891 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3045 10:54:30.735593 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3046 10:54:30.739250 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3047 10:54:30.742300 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3048 10:54:30.745660 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3049 10:54:30.749057 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3050 10:54:30.755507 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3051 10:54:30.759149 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3052 10:54:30.762089 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3053 10:54:30.765349 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3054 10:54:30.768606 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3055 10:54:30.775478 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3056 10:54:30.778541 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3057 10:54:30.782158 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3058 10:54:30.785067 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3059 10:54:30.788474 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3060 10:54:30.791769 ==
3061 10:54:30.795196 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 10:54:30.798639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 10:54:30.799079 ==
3064 10:54:30.799416 DQS Delay:
3065 10:54:30.801653 DQS0 = 0, DQS1 = 0
3066 10:54:30.802078 DQM Delay:
3067 10:54:30.805189 DQM0 = 119, DQM1 = 107
3068 10:54:30.805613 DQ Delay:
3069 10:54:30.808736 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3070 10:54:30.811655 DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =126
3071 10:54:30.815120 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3072 10:54:30.818691 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3073 10:54:30.819113
3074 10:54:30.819446
3075 10:54:30.828142 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
3076 10:54:30.828570 CH0 RK1: MR19=403, MR18=AF2
3077 10:54:30.834740 CH0_RK1: MR19=0x403, MR18=0xAF2, DQSOSC=406, MR23=63, INC=39, DEC=26
3078 10:54:30.838342 [RxdqsGatingPostProcess] freq 1200
3079 10:54:30.845225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 10:54:30.848063 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 10:54:30.851679 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 10:54:30.854981 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 10:54:30.858179 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 10:54:30.861863 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 10:54:30.865030 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 10:54:30.868320 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 10:54:30.871471 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 10:54:30.871921 Pre-setting of DQS Precalculation
3089 10:54:30.877935 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 10:54:30.878367 ==
3091 10:54:30.881534 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 10:54:30.884696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 10:54:30.885196 ==
3094 10:54:30.891627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 10:54:30.897819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3096 10:54:30.905219 [CA 0] Center 37 (7~68) winsize 62
3097 10:54:30.908694 [CA 1] Center 37 (7~68) winsize 62
3098 10:54:30.911871 [CA 2] Center 35 (5~65) winsize 61
3099 10:54:30.915207 [CA 3] Center 34 (4~65) winsize 62
3100 10:54:30.918778 [CA 4] Center 34 (4~65) winsize 62
3101 10:54:30.922187 [CA 5] Center 33 (3~64) winsize 62
3102 10:54:30.922638
3103 10:54:30.925059 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3104 10:54:30.925513
3105 10:54:30.928183 [CATrainingPosCal] consider 1 rank data
3106 10:54:30.931674 u2DelayCellTimex100 = 270/100 ps
3107 10:54:30.935275 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 10:54:30.941842 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 10:54:30.945016 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 10:54:30.948168 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3111 10:54:30.951530 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3112 10:54:30.955190 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 10:54:30.955659
3114 10:54:30.958525 CA PerBit enable=1, Macro0, CA PI delay=33
3115 10:54:30.958972
3116 10:54:30.961745 [CBTSetCACLKResult] CA Dly = 33
3117 10:54:30.964719 CS Dly: 5 (0~36)
3118 10:54:30.965385 ==
3119 10:54:30.968121 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 10:54:30.971363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 10:54:30.971893 ==
3122 10:54:30.977807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 10:54:30.981397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3124 10:54:30.990732 [CA 0] Center 38 (8~68) winsize 61
3125 10:54:30.994385 [CA 1] Center 38 (7~69) winsize 63
3126 10:54:30.997700 [CA 2] Center 35 (5~66) winsize 62
3127 10:54:31.001187 [CA 3] Center 35 (5~65) winsize 61
3128 10:54:31.004359 [CA 4] Center 35 (5~65) winsize 61
3129 10:54:31.007516 [CA 5] Center 34 (4~64) winsize 61
3130 10:54:31.008189
3131 10:54:31.010919 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 10:54:31.011308
3133 10:54:31.014209 [CATrainingPosCal] consider 2 rank data
3134 10:54:31.017780 u2DelayCellTimex100 = 270/100 ps
3135 10:54:31.020927 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3136 10:54:31.027327 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3137 10:54:31.030593 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3138 10:54:31.034050 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3139 10:54:31.037185 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3140 10:54:31.040710 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3141 10:54:31.041215
3142 10:54:31.043832 CA PerBit enable=1, Macro0, CA PI delay=34
3143 10:54:31.044208
3144 10:54:31.047479 [CBTSetCACLKResult] CA Dly = 34
3145 10:54:31.047933 CS Dly: 6 (0~39)
3146 10:54:31.050732
3147 10:54:31.053898 ----->DramcWriteLeveling(PI) begin...
3148 10:54:31.054357 ==
3149 10:54:31.056874 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 10:54:31.060320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 10:54:31.060872 ==
3152 10:54:31.063660 Write leveling (Byte 0): 27 => 27
3153 10:54:31.067171 Write leveling (Byte 1): 28 => 28
3154 10:54:31.070360 DramcWriteLeveling(PI) end<-----
3155 10:54:31.070972
3156 10:54:31.071364 ==
3157 10:54:31.073575 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 10:54:31.076922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 10:54:31.077402 ==
3160 10:54:31.080511 [Gating] SW mode calibration
3161 10:54:31.087022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 10:54:31.093416 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 10:54:31.096742 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 10:54:31.099841 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 10:54:31.106658 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 10:54:31.109916 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 10:54:31.113716 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 10:54:31.120094 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3169 10:54:31.123178 0 15 24 | B1->B0 | 2929 2626 | 1 1 | (1 1) (1 0)
3170 10:54:31.126729 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3171 10:54:31.133193 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 10:54:31.136794 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 10:54:31.140331 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 10:54:31.146485 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 10:54:31.150170 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 10:54:31.153185 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3177 10:54:31.159644 1 0 24 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
3178 10:54:31.163232 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 10:54:31.166533 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 10:54:31.173191 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 10:54:31.176519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 10:54:31.179617 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 10:54:31.186181 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 10:54:31.189527 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3185 10:54:31.192881 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3186 10:54:31.199498 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3187 10:54:31.202896 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:54:31.205949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:54:31.212822 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 10:54:31.216161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 10:54:31.218932 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 10:54:31.225768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 10:54:31.229179 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 10:54:31.232752 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 10:54:31.239152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 10:54:31.242277 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 10:54:31.245922 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 10:54:31.249052 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 10:54:31.255531 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 10:54:31.259079 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3201 10:54:31.262341 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3202 10:54:31.269117 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 10:54:31.272689 Total UI for P1: 0, mck2ui 16
3204 10:54:31.275806 best dqsien dly found for B0: ( 1, 3, 22)
3205 10:54:31.276228 Total UI for P1: 0, mck2ui 16
3206 10:54:31.282667 best dqsien dly found for B1: ( 1, 3, 24)
3207 10:54:31.285727 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3208 10:54:31.288870 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3209 10:54:31.289415
3210 10:54:31.292060 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3211 10:54:31.295565 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3212 10:54:31.298528 [Gating] SW calibration Done
3213 10:54:31.299103 ==
3214 10:54:31.301801 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 10:54:31.305466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 10:54:31.305885 ==
3217 10:54:31.308869 RX Vref Scan: 0
3218 10:54:31.309400
3219 10:54:31.309758 RX Vref 0 -> 0, step: 1
3220 10:54:31.311855
3221 10:54:31.312406 RX Delay -40 -> 252, step: 8
3222 10:54:31.318507 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3223 10:54:31.322055 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3224 10:54:31.325231 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3225 10:54:31.328789 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3226 10:54:31.332163 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3227 10:54:31.338683 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3228 10:54:31.341753 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3229 10:54:31.344916 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3230 10:54:31.348341 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3231 10:54:31.351683 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3232 10:54:31.358260 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3233 10:54:31.361785 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3234 10:54:31.364906 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3235 10:54:31.368092 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3236 10:54:31.371606 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3237 10:54:31.378517 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3238 10:54:31.378941 ==
3239 10:54:31.381709 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 10:54:31.384899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 10:54:31.385293 ==
3242 10:54:31.385714 DQS Delay:
3243 10:54:31.388041 DQS0 = 0, DQS1 = 0
3244 10:54:31.388535 DQM Delay:
3245 10:54:31.391247 DQM0 = 119, DQM1 = 112
3246 10:54:31.391807 DQ Delay:
3247 10:54:31.394566 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3248 10:54:31.398253 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3249 10:54:31.401660 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3250 10:54:31.404674 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3251 10:54:31.405173
3252 10:54:31.405266
3253 10:54:31.407901 ==
3254 10:54:31.411034 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 10:54:31.414396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 10:54:31.414506 ==
3257 10:54:31.414600
3258 10:54:31.414692
3259 10:54:31.417410 TX Vref Scan disable
3260 10:54:31.417519 == TX Byte 0 ==
3261 10:54:31.421173 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 10:54:31.427396 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 10:54:31.427517 == TX Byte 1 ==
3264 10:54:31.431017 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3265 10:54:31.437730 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3266 10:54:31.437841 ==
3267 10:54:31.441133 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 10:54:31.444428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 10:54:31.444536 ==
3270 10:54:31.456250 TX Vref=22, minBit 9, minWin=24, winSum=406
3271 10:54:31.459607 TX Vref=24, minBit 1, minWin=24, winSum=410
3272 10:54:31.463101 TX Vref=26, minBit 8, minWin=25, winSum=417
3273 10:54:31.466247 TX Vref=28, minBit 10, minWin=25, winSum=418
3274 10:54:31.470028 TX Vref=30, minBit 11, minWin=25, winSum=421
3275 10:54:31.476490 TX Vref=32, minBit 1, minWin=26, winSum=423
3276 10:54:31.479645 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 32
3277 10:54:31.480068
3278 10:54:31.482963 Final TX Range 1 Vref 32
3279 10:54:31.483388
3280 10:54:31.483722 ==
3281 10:54:31.486285 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 10:54:31.489710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 10:54:31.490150 ==
3284 10:54:31.493063
3285 10:54:31.493491
3286 10:54:31.493921 TX Vref Scan disable
3287 10:54:31.496313 == TX Byte 0 ==
3288 10:54:31.499501 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 10:54:31.503140 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 10:54:31.506360 == TX Byte 1 ==
3291 10:54:31.509551 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 10:54:31.512821 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 10:54:31.516057
3294 10:54:31.516483 [DATLAT]
3295 10:54:31.517000 Freq=1200, CH1 RK0
3296 10:54:31.517412
3297 10:54:31.519496 DATLAT Default: 0xd
3298 10:54:31.519927 0, 0xFFFF, sum = 0
3299 10:54:31.522990 1, 0xFFFF, sum = 0
3300 10:54:31.523427 2, 0xFFFF, sum = 0
3301 10:54:31.526106 3, 0xFFFF, sum = 0
3302 10:54:31.529409 4, 0xFFFF, sum = 0
3303 10:54:31.529838 5, 0xFFFF, sum = 0
3304 10:54:31.532733 6, 0xFFFF, sum = 0
3305 10:54:31.533184 7, 0xFFFF, sum = 0
3306 10:54:31.536110 8, 0xFFFF, sum = 0
3307 10:54:31.536537 9, 0xFFFF, sum = 0
3308 10:54:31.539401 10, 0xFFFF, sum = 0
3309 10:54:31.539846 11, 0xFFFF, sum = 0
3310 10:54:31.542888 12, 0x0, sum = 1
3311 10:54:31.543309 13, 0x0, sum = 2
3312 10:54:31.546098 14, 0x0, sum = 3
3313 10:54:31.546515 15, 0x0, sum = 4
3314 10:54:31.549288 best_step = 13
3315 10:54:31.549700
3316 10:54:31.550027 ==
3317 10:54:31.552760 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 10:54:31.555819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 10:54:31.556233 ==
3320 10:54:31.556559 RX Vref Scan: 1
3321 10:54:31.556900
3322 10:54:31.559380 Set Vref Range= 32 -> 127
3323 10:54:31.559671
3324 10:54:31.562447 RX Vref 32 -> 127, step: 1
3325 10:54:31.562737
3326 10:54:31.565981 RX Delay -13 -> 252, step: 4
3327 10:54:31.566274
3328 10:54:31.568974 Set Vref, RX VrefLevel [Byte0]: 32
3329 10:54:31.572425 [Byte1]: 32
3330 10:54:31.572505
3331 10:54:31.575879 Set Vref, RX VrefLevel [Byte0]: 33
3332 10:54:31.578663 [Byte1]: 33
3333 10:54:31.582269
3334 10:54:31.582349 Set Vref, RX VrefLevel [Byte0]: 34
3335 10:54:31.585443 [Byte1]: 34
3336 10:54:31.590169
3337 10:54:31.590248 Set Vref, RX VrefLevel [Byte0]: 35
3338 10:54:31.593449 [Byte1]: 35
3339 10:54:31.597991
3340 10:54:31.598072 Set Vref, RX VrefLevel [Byte0]: 36
3341 10:54:31.601383 [Byte1]: 36
3342 10:54:31.606257
3343 10:54:31.606337 Set Vref, RX VrefLevel [Byte0]: 37
3344 10:54:31.609343 [Byte1]: 37
3345 10:54:31.613898
3346 10:54:31.613978 Set Vref, RX VrefLevel [Byte0]: 38
3347 10:54:31.617029 [Byte1]: 38
3348 10:54:31.621916
3349 10:54:31.621996 Set Vref, RX VrefLevel [Byte0]: 39
3350 10:54:31.625203 [Byte1]: 39
3351 10:54:31.629747
3352 10:54:31.629826 Set Vref, RX VrefLevel [Byte0]: 40
3353 10:54:31.633215 [Byte1]: 40
3354 10:54:31.637692
3355 10:54:31.637772 Set Vref, RX VrefLevel [Byte0]: 41
3356 10:54:31.640623 [Byte1]: 41
3357 10:54:31.645534
3358 10:54:31.645614 Set Vref, RX VrefLevel [Byte0]: 42
3359 10:54:31.648923 [Byte1]: 42
3360 10:54:31.653343
3361 10:54:31.653423 Set Vref, RX VrefLevel [Byte0]: 43
3362 10:54:31.656522 [Byte1]: 43
3363 10:54:31.661186
3364 10:54:31.661266 Set Vref, RX VrefLevel [Byte0]: 44
3365 10:54:31.664703 [Byte1]: 44
3366 10:54:31.669030
3367 10:54:31.669110 Set Vref, RX VrefLevel [Byte0]: 45
3368 10:54:31.672167 [Byte1]: 45
3369 10:54:31.677153
3370 10:54:31.677237 Set Vref, RX VrefLevel [Byte0]: 46
3371 10:54:31.680287 [Byte1]: 46
3372 10:54:31.684537
3373 10:54:31.688104 Set Vref, RX VrefLevel [Byte0]: 47
3374 10:54:31.691190 [Byte1]: 47
3375 10:54:31.691270
3376 10:54:31.694765 Set Vref, RX VrefLevel [Byte0]: 48
3377 10:54:31.698036 [Byte1]: 48
3378 10:54:31.698117
3379 10:54:31.701351 Set Vref, RX VrefLevel [Byte0]: 49
3380 10:54:31.704586 [Byte1]: 49
3381 10:54:31.708627
3382 10:54:31.708707 Set Vref, RX VrefLevel [Byte0]: 50
3383 10:54:31.711870 [Byte1]: 50
3384 10:54:31.716493
3385 10:54:31.716573 Set Vref, RX VrefLevel [Byte0]: 51
3386 10:54:31.719751 [Byte1]: 51
3387 10:54:31.724262
3388 10:54:31.724342 Set Vref, RX VrefLevel [Byte0]: 52
3389 10:54:31.727416 [Byte1]: 52
3390 10:54:31.732177
3391 10:54:31.732257 Set Vref, RX VrefLevel [Byte0]: 53
3392 10:54:31.735843 [Byte1]: 53
3393 10:54:31.740244
3394 10:54:31.740325 Set Vref, RX VrefLevel [Byte0]: 54
3395 10:54:31.743414 [Byte1]: 54
3396 10:54:31.747934
3397 10:54:31.748014 Set Vref, RX VrefLevel [Byte0]: 55
3398 10:54:31.751292 [Byte1]: 55
3399 10:54:31.755807
3400 10:54:31.755887 Set Vref, RX VrefLevel [Byte0]: 56
3401 10:54:31.759105 [Byte1]: 56
3402 10:54:31.763817
3403 10:54:31.763897 Set Vref, RX VrefLevel [Byte0]: 57
3404 10:54:31.767114 [Byte1]: 57
3405 10:54:31.771438
3406 10:54:31.771530 Set Vref, RX VrefLevel [Byte0]: 58
3407 10:54:31.775026 [Byte1]: 58
3408 10:54:31.779683
3409 10:54:31.779792 Set Vref, RX VrefLevel [Byte0]: 59
3410 10:54:31.782794 [Byte1]: 59
3411 10:54:31.787806
3412 10:54:31.787925 Set Vref, RX VrefLevel [Byte0]: 60
3413 10:54:31.790949 [Byte1]: 60
3414 10:54:31.795686
3415 10:54:31.796094 Set Vref, RX VrefLevel [Byte0]: 61
3416 10:54:31.798925 [Byte1]: 61
3417 10:54:31.803582
3418 10:54:31.803991 Set Vref, RX VrefLevel [Byte0]: 62
3419 10:54:31.806617 [Byte1]: 62
3420 10:54:31.811043
3421 10:54:31.811118 Set Vref, RX VrefLevel [Byte0]: 63
3422 10:54:31.814662 [Byte1]: 63
3423 10:54:31.818947
3424 10:54:31.819027 Set Vref, RX VrefLevel [Byte0]: 64
3425 10:54:31.822053 [Byte1]: 64
3426 10:54:31.826747
3427 10:54:31.826847 Set Vref, RX VrefLevel [Byte0]: 65
3428 10:54:31.829921 [Byte1]: 65
3429 10:54:31.834535
3430 10:54:31.834645 Set Vref, RX VrefLevel [Byte0]: 66
3431 10:54:31.838101 [Byte1]: 66
3432 10:54:31.842700
3433 10:54:31.842841 Set Vref, RX VrefLevel [Byte0]: 67
3434 10:54:31.846112 [Byte1]: 67
3435 10:54:31.850939
3436 10:54:31.853950 Set Vref, RX VrefLevel [Byte0]: 68
3437 10:54:31.857009 [Byte1]: 68
3438 10:54:31.857425
3439 10:54:31.860424 Final RX Vref Byte 0 = 51 to rank0
3440 10:54:31.863688 Final RX Vref Byte 1 = 53 to rank0
3441 10:54:31.867070 Final RX Vref Byte 0 = 51 to rank1
3442 10:54:31.870334 Final RX Vref Byte 1 = 53 to rank1==
3443 10:54:31.873889 Dram Type= 6, Freq= 0, CH_1, rank 0
3444 10:54:31.877231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 10:54:31.877675 ==
3446 10:54:31.878011 DQS Delay:
3447 10:54:31.880330 DQS0 = 0, DQS1 = 0
3448 10:54:31.880746 DQM Delay:
3449 10:54:31.883721 DQM0 = 119, DQM1 = 112
3450 10:54:31.884137 DQ Delay:
3451 10:54:31.886966 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3452 10:54:31.890001 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3453 10:54:31.893442 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3454 10:54:31.897087 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3455 10:54:31.900347
3456 10:54:31.900760
3457 10:54:31.906871 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3458 10:54:31.910620 CH1 RK0: MR19=404, MR18=417
3459 10:54:31.916745 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3460 10:54:31.917202
3461 10:54:31.919896 ----->DramcWriteLeveling(PI) begin...
3462 10:54:31.920319 ==
3463 10:54:31.923682 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 10:54:31.926879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 10:54:31.927301 ==
3466 10:54:31.930287 Write leveling (Byte 0): 25 => 25
3467 10:54:31.933314 Write leveling (Byte 1): 29 => 29
3468 10:54:31.936533 DramcWriteLeveling(PI) end<-----
3469 10:54:31.936990
3470 10:54:31.937328 ==
3471 10:54:31.939939 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 10:54:31.943121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 10:54:31.943545 ==
3474 10:54:31.946534 [Gating] SW mode calibration
3475 10:54:31.953122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3476 10:54:31.959481 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3477 10:54:31.963048 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 10:54:31.966429 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 10:54:31.972920 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 10:54:31.976314 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 10:54:31.979504 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 10:54:31.986007 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 10:54:31.989867 0 15 24 | B1->B0 | 2929 3333 | 1 1 | (1 0) (1 0)
3484 10:54:31.992833 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3485 10:54:31.999343 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 10:54:32.002627 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 10:54:32.006206 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 10:54:32.012701 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 10:54:32.016223 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 10:54:32.019226 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 10:54:32.025793 1 0 24 | B1->B0 | 3e3e 2a2a | 1 1 | (0 0) (0 0)
3492 10:54:32.029239 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3493 10:54:32.032458 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 10:54:32.038981 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 10:54:32.042309 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 10:54:32.045748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 10:54:32.052037 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 10:54:32.055853 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 10:54:32.058604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3500 10:54:32.065569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3501 10:54:32.068613 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 10:54:32.071782 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 10:54:32.078575 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 10:54:32.081900 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 10:54:32.085298 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 10:54:32.091844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 10:54:32.095121 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 10:54:32.098281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 10:54:32.104787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:54:32.108108 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:54:32.111420 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 10:54:32.118305 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 10:54:32.121569 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 10:54:32.124719 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 10:54:32.131135 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3516 10:54:32.134464 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3517 10:54:32.138122 Total UI for P1: 0, mck2ui 16
3518 10:54:32.141339 best dqsien dly found for B0: ( 1, 3, 24)
3519 10:54:32.144717 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 10:54:32.147817 Total UI for P1: 0, mck2ui 16
3521 10:54:32.150842 best dqsien dly found for B1: ( 1, 3, 26)
3522 10:54:32.154711 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3523 10:54:32.157656 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3524 10:54:32.160804
3525 10:54:32.163936 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3526 10:54:32.167543 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3527 10:54:32.170676 [Gating] SW calibration Done
3528 10:54:32.171111 ==
3529 10:54:32.173864 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 10:54:32.177139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 10:54:32.177567 ==
3532 10:54:32.180557 RX Vref Scan: 0
3533 10:54:32.181004
3534 10:54:32.181343 RX Vref 0 -> 0, step: 1
3535 10:54:32.181660
3536 10:54:32.183626 RX Delay -40 -> 252, step: 8
3537 10:54:32.186898 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3538 10:54:32.193670 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3539 10:54:32.196969 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3540 10:54:32.200136 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3541 10:54:32.203788 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3542 10:54:32.206842 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3543 10:54:32.213672 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3544 10:54:32.216864 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3545 10:54:32.220143 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3546 10:54:32.223440 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3547 10:54:32.226976 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3548 10:54:32.233483 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3549 10:54:32.236673 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3550 10:54:32.239811 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3551 10:54:32.243640 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3552 10:54:32.246703 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3553 10:54:32.250101 ==
3554 10:54:32.250525 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 10:54:32.256756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 10:54:32.257215 ==
3557 10:54:32.257554 DQS Delay:
3558 10:54:32.260390 DQS0 = 0, DQS1 = 0
3559 10:54:32.260975 DQM Delay:
3560 10:54:32.263091 DQM0 = 119, DQM1 = 113
3561 10:54:32.263614 DQ Delay:
3562 10:54:32.266509 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3563 10:54:32.269897 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3564 10:54:32.273511 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3565 10:54:32.276424 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3566 10:54:32.276956
3567 10:54:32.277296
3568 10:54:32.277654 ==
3569 10:54:32.279942 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 10:54:32.286528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 10:54:32.286956 ==
3572 10:54:32.287292
3573 10:54:32.287604
3574 10:54:32.287904 TX Vref Scan disable
3575 10:54:32.289715 == TX Byte 0 ==
3576 10:54:32.293017 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 10:54:32.299690 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 10:54:32.300114 == TX Byte 1 ==
3579 10:54:32.303023 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3580 10:54:32.309907 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3581 10:54:32.310377 ==
3582 10:54:32.312955 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 10:54:32.315916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 10:54:32.315998 ==
3585 10:54:32.327392 TX Vref=22, minBit 1, minWin=25, winSum=418
3586 10:54:32.330967 TX Vref=24, minBit 1, minWin=25, winSum=422
3587 10:54:32.334263 TX Vref=26, minBit 3, minWin=25, winSum=427
3588 10:54:32.337566 TX Vref=28, minBit 3, minWin=25, winSum=425
3589 10:54:32.340717 TX Vref=30, minBit 9, minWin=26, winSum=427
3590 10:54:32.347107 TX Vref=32, minBit 0, minWin=26, winSum=427
3591 10:54:32.350869 [TxChooseVref] Worse bit 9, Min win 26, Win sum 427, Final Vref 30
3592 10:54:32.350957
3593 10:54:32.353983 Final TX Range 1 Vref 30
3594 10:54:32.354078
3595 10:54:32.354153 ==
3596 10:54:32.357215 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 10:54:32.360885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 10:54:32.360989 ==
3599 10:54:32.363982
3600 10:54:32.364404
3601 10:54:32.364741 TX Vref Scan disable
3602 10:54:32.367682 == TX Byte 0 ==
3603 10:54:32.370975 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3604 10:54:32.377423 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3605 10:54:32.377847 == TX Byte 1 ==
3606 10:54:32.381060 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3607 10:54:32.387455 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3608 10:54:32.387878
3609 10:54:32.388243 [DATLAT]
3610 10:54:32.388558 Freq=1200, CH1 RK1
3611 10:54:32.388888
3612 10:54:32.390477 DATLAT Default: 0xd
3613 10:54:32.394156 0, 0xFFFF, sum = 0
3614 10:54:32.394585 1, 0xFFFF, sum = 0
3615 10:54:32.397203 2, 0xFFFF, sum = 0
3616 10:54:32.397629 3, 0xFFFF, sum = 0
3617 10:54:32.400383 4, 0xFFFF, sum = 0
3618 10:54:32.400837 5, 0xFFFF, sum = 0
3619 10:54:32.403697 6, 0xFFFF, sum = 0
3620 10:54:32.404126 7, 0xFFFF, sum = 0
3621 10:54:32.407268 8, 0xFFFF, sum = 0
3622 10:54:32.407695 9, 0xFFFF, sum = 0
3623 10:54:32.410335 10, 0xFFFF, sum = 0
3624 10:54:32.410793 11, 0xFFFF, sum = 0
3625 10:54:32.413796 12, 0x0, sum = 1
3626 10:54:32.414296 13, 0x0, sum = 2
3627 10:54:32.416988 14, 0x0, sum = 3
3628 10:54:32.417416 15, 0x0, sum = 4
3629 10:54:32.420500 best_step = 13
3630 10:54:32.420961
3631 10:54:32.421300 ==
3632 10:54:32.423771 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 10:54:32.427140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 10:54:32.427567 ==
3635 10:54:32.430250 RX Vref Scan: 0
3636 10:54:32.430674
3637 10:54:32.431010 RX Vref 0 -> 0, step: 1
3638 10:54:32.431391
3639 10:54:32.433610 RX Delay -13 -> 252, step: 4
3640 10:54:32.440534 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3641 10:54:32.443242 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3642 10:54:32.446866 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3643 10:54:32.450077 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3644 10:54:32.453426 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3645 10:54:32.460312 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3646 10:54:32.463479 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3647 10:54:32.466819 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3648 10:54:32.470141 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3649 10:54:32.473114 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3650 10:54:32.480181 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3651 10:54:32.483097 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3652 10:54:32.486606 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3653 10:54:32.489951 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3654 10:54:32.496226 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3655 10:54:32.499601 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3656 10:54:32.500025 ==
3657 10:54:32.502844 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 10:54:32.506405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 10:54:32.506993 ==
3660 10:54:32.507348 DQS Delay:
3661 10:54:32.509511 DQS0 = 0, DQS1 = 0
3662 10:54:32.509929 DQM Delay:
3663 10:54:32.512885 DQM0 = 119, DQM1 = 113
3664 10:54:32.513304 DQ Delay:
3665 10:54:32.516185 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3666 10:54:32.519540 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3667 10:54:32.522764 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3668 10:54:32.529402 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3669 10:54:32.529951
3670 10:54:32.530445
3671 10:54:32.535668 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3672 10:54:32.538990 CH1 RK1: MR19=403, MR18=6E9
3673 10:54:32.545998 CH1_RK1: MR19=0x403, MR18=0x6E9, DQSOSC=407, MR23=63, INC=39, DEC=26
3674 10:54:32.549203 [RxdqsGatingPostProcess] freq 1200
3675 10:54:32.552368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3676 10:54:32.555641 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 10:54:32.559114 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 10:54:32.562116 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 10:54:32.565452 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 10:54:32.568886 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 10:54:32.572130 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 10:54:32.575542 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 10:54:32.578720 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 10:54:32.581902 Pre-setting of DQS Precalculation
3685 10:54:32.585445 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3686 10:54:32.595140 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3687 10:54:32.601992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3688 10:54:32.602414
3689 10:54:32.602748
3690 10:54:32.605282 [Calibration Summary] 2400 Mbps
3691 10:54:32.605705 CH 0, Rank 0
3692 10:54:32.608697 SW Impedance : PASS
3693 10:54:32.609147 DUTY Scan : NO K
3694 10:54:32.611723 ZQ Calibration : PASS
3695 10:54:32.615096 Jitter Meter : NO K
3696 10:54:32.615519 CBT Training : PASS
3697 10:54:32.618377 Write leveling : PASS
3698 10:54:32.621751 RX DQS gating : PASS
3699 10:54:32.622175 RX DQ/DQS(RDDQC) : PASS
3700 10:54:32.625048 TX DQ/DQS : PASS
3701 10:54:32.628316 RX DATLAT : PASS
3702 10:54:32.628738 RX DQ/DQS(Engine): PASS
3703 10:54:32.631582 TX OE : NO K
3704 10:54:32.632004 All Pass.
3705 10:54:32.632338
3706 10:54:32.634773 CH 0, Rank 1
3707 10:54:32.635195 SW Impedance : PASS
3708 10:54:32.637936 DUTY Scan : NO K
3709 10:54:32.641213 ZQ Calibration : PASS
3710 10:54:32.641635 Jitter Meter : NO K
3711 10:54:32.644497 CBT Training : PASS
3712 10:54:32.647952 Write leveling : PASS
3713 10:54:32.648374 RX DQS gating : PASS
3714 10:54:32.651266 RX DQ/DQS(RDDQC) : PASS
3715 10:54:32.654452 TX DQ/DQS : PASS
3716 10:54:32.654874 RX DATLAT : PASS
3717 10:54:32.658056 RX DQ/DQS(Engine): PASS
3718 10:54:32.658481 TX OE : NO K
3719 10:54:32.661453 All Pass.
3720 10:54:32.661871
3721 10:54:32.662204 CH 1, Rank 0
3722 10:54:32.664608 SW Impedance : PASS
3723 10:54:32.665069 DUTY Scan : NO K
3724 10:54:32.667717 ZQ Calibration : PASS
3725 10:54:32.670990 Jitter Meter : NO K
3726 10:54:32.671411 CBT Training : PASS
3727 10:54:32.674271 Write leveling : PASS
3728 10:54:32.678067 RX DQS gating : PASS
3729 10:54:32.678491 RX DQ/DQS(RDDQC) : PASS
3730 10:54:32.681187 TX DQ/DQS : PASS
3731 10:54:32.684431 RX DATLAT : PASS
3732 10:54:32.684896 RX DQ/DQS(Engine): PASS
3733 10:54:32.687662 TX OE : NO K
3734 10:54:32.688085 All Pass.
3735 10:54:32.688420
3736 10:54:32.690912 CH 1, Rank 1
3737 10:54:32.691380 SW Impedance : PASS
3738 10:54:32.693989 DUTY Scan : NO K
3739 10:54:32.697407 ZQ Calibration : PASS
3740 10:54:32.697831 Jitter Meter : NO K
3741 10:54:32.701044 CBT Training : PASS
3742 10:54:32.704007 Write leveling : PASS
3743 10:54:32.704432 RX DQS gating : PASS
3744 10:54:32.707651 RX DQ/DQS(RDDQC) : PASS
3745 10:54:32.710733 TX DQ/DQS : PASS
3746 10:54:32.711161 RX DATLAT : PASS
3747 10:54:32.713905 RX DQ/DQS(Engine): PASS
3748 10:54:32.717192 TX OE : NO K
3749 10:54:32.717619 All Pass.
3750 10:54:32.717952
3751 10:54:32.718262 DramC Write-DBI off
3752 10:54:32.720613 PER_BANK_REFRESH: Hybrid Mode
3753 10:54:32.723877 TX_TRACKING: ON
3754 10:54:32.730685 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3755 10:54:32.736799 [FAST_K] Save calibration result to emmc
3756 10:54:32.740218 dramc_set_vcore_voltage set vcore to 650000
3757 10:54:32.740859 Read voltage for 600, 5
3758 10:54:32.743727 Vio18 = 0
3759 10:54:32.744162 Vcore = 650000
3760 10:54:32.744555 Vdram = 0
3761 10:54:32.747279 Vddq = 0
3762 10:54:32.747938 Vmddr = 0
3763 10:54:32.750094 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3764 10:54:32.756665 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3765 10:54:32.759915 MEM_TYPE=3, freq_sel=19
3766 10:54:32.763378 sv_algorithm_assistance_LP4_1600
3767 10:54:32.766676 ============ PULL DRAM RESETB DOWN ============
3768 10:54:32.770351 ========== PULL DRAM RESETB DOWN end =========
3769 10:54:32.776833 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3770 10:54:32.779786 ===================================
3771 10:54:32.780211 LPDDR4 DRAM CONFIGURATION
3772 10:54:32.783155 ===================================
3773 10:54:32.786459 EX_ROW_EN[0] = 0x0
3774 10:54:32.786890 EX_ROW_EN[1] = 0x0
3775 10:54:32.789537 LP4Y_EN = 0x0
3776 10:54:32.793284 WORK_FSP = 0x0
3777 10:54:32.793712 WL = 0x2
3778 10:54:32.796732 RL = 0x2
3779 10:54:32.797196 BL = 0x2
3780 10:54:32.799561 RPST = 0x0
3781 10:54:32.799991 RD_PRE = 0x0
3782 10:54:32.802909 WR_PRE = 0x1
3783 10:54:32.803337 WR_PST = 0x0
3784 10:54:32.806103 DBI_WR = 0x0
3785 10:54:32.806528 DBI_RD = 0x0
3786 10:54:32.809443 OTF = 0x1
3787 10:54:32.812623 ===================================
3788 10:54:32.816131 ===================================
3789 10:54:32.816568 ANA top config
3790 10:54:32.819309 ===================================
3791 10:54:32.822606 DLL_ASYNC_EN = 0
3792 10:54:32.825945 ALL_SLAVE_EN = 1
3793 10:54:32.829191 NEW_RANK_MODE = 1
3794 10:54:32.829621 DLL_IDLE_MODE = 1
3795 10:54:32.832416 LP45_APHY_COMB_EN = 1
3796 10:54:32.835960 TX_ODT_DIS = 1
3797 10:54:32.838915 NEW_8X_MODE = 1
3798 10:54:32.842111 ===================================
3799 10:54:32.845783 ===================================
3800 10:54:32.849030 data_rate = 1200
3801 10:54:32.849460 CKR = 1
3802 10:54:32.852167 DQ_P2S_RATIO = 8
3803 10:54:32.855344 ===================================
3804 10:54:32.858789 CA_P2S_RATIO = 8
3805 10:54:32.861771 DQ_CA_OPEN = 0
3806 10:54:32.865643 DQ_SEMI_OPEN = 0
3807 10:54:32.868667 CA_SEMI_OPEN = 0
3808 10:54:32.869148 CA_FULL_RATE = 0
3809 10:54:32.871971 DQ_CKDIV4_EN = 1
3810 10:54:32.875171 CA_CKDIV4_EN = 1
3811 10:54:32.878531 CA_PREDIV_EN = 0
3812 10:54:32.881893 PH8_DLY = 0
3813 10:54:32.884901 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3814 10:54:32.888523 DQ_AAMCK_DIV = 4
3815 10:54:32.888976 CA_AAMCK_DIV = 4
3816 10:54:32.891746 CA_ADMCK_DIV = 4
3817 10:54:32.895044 DQ_TRACK_CA_EN = 0
3818 10:54:32.898267 CA_PICK = 600
3819 10:54:32.901783 CA_MCKIO = 600
3820 10:54:32.904557 MCKIO_SEMI = 0
3821 10:54:32.908135 PLL_FREQ = 2288
3822 10:54:32.908565 DQ_UI_PI_RATIO = 32
3823 10:54:32.911437 CA_UI_PI_RATIO = 0
3824 10:54:32.914870 ===================================
3825 10:54:32.918128 ===================================
3826 10:54:32.921544 memory_type:LPDDR4
3827 10:54:32.924748 GP_NUM : 10
3828 10:54:32.925209 SRAM_EN : 1
3829 10:54:32.928064 MD32_EN : 0
3830 10:54:32.931211 ===================================
3831 10:54:32.931636 [ANA_INIT] >>>>>>>>>>>>>>
3832 10:54:32.934702 <<<<<< [CONFIGURE PHASE]: ANA_TX
3833 10:54:32.938420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3834 10:54:32.941080 ===================================
3835 10:54:32.944707 data_rate = 1200,PCW = 0X5800
3836 10:54:32.947561 ===================================
3837 10:54:32.951297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3838 10:54:32.957763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 10:54:32.964634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 10:54:32.968094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3841 10:54:32.971074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3842 10:54:32.974483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3843 10:54:32.977756 [ANA_INIT] flow start
3844 10:54:32.978196 [ANA_INIT] PLL >>>>>>>>
3845 10:54:32.980759 [ANA_INIT] PLL <<<<<<<<
3846 10:54:32.984285 [ANA_INIT] MIDPI >>>>>>>>
3847 10:54:32.984711 [ANA_INIT] MIDPI <<<<<<<<
3848 10:54:32.987394 [ANA_INIT] DLL >>>>>>>>
3849 10:54:32.990532 [ANA_INIT] flow end
3850 10:54:32.994208 ============ LP4 DIFF to SE enter ============
3851 10:54:32.997563 ============ LP4 DIFF to SE exit ============
3852 10:54:33.000691 [ANA_INIT] <<<<<<<<<<<<<
3853 10:54:33.004390 [Flow] Enable top DCM control >>>>>
3854 10:54:33.007409 [Flow] Enable top DCM control <<<<<
3855 10:54:33.010760 Enable DLL master slave shuffle
3856 10:54:33.013974 ==============================================================
3857 10:54:33.017003 Gating Mode config
3858 10:54:33.023956 ==============================================================
3859 10:54:33.024386 Config description:
3860 10:54:33.033668 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3861 10:54:33.040120 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3862 10:54:33.047026 SELPH_MODE 0: By rank 1: By Phase
3863 10:54:33.050107 ==============================================================
3864 10:54:33.053492 GAT_TRACK_EN = 1
3865 10:54:33.056697 RX_GATING_MODE = 2
3866 10:54:33.060169 RX_GATING_TRACK_MODE = 2
3867 10:54:33.063548 SELPH_MODE = 1
3868 10:54:33.066595 PICG_EARLY_EN = 1
3869 10:54:33.069887 VALID_LAT_VALUE = 1
3870 10:54:33.076883 ==============================================================
3871 10:54:33.079637 Enter into Gating configuration >>>>
3872 10:54:33.083243 Exit from Gating configuration <<<<
3873 10:54:33.083667 Enter into DVFS_PRE_config >>>>>
3874 10:54:33.096625 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3875 10:54:33.099455 Exit from DVFS_PRE_config <<<<<
3876 10:54:33.103153 Enter into PICG configuration >>>>
3877 10:54:33.106499 Exit from PICG configuration <<<<
3878 10:54:33.109592 [RX_INPUT] configuration >>>>>
3879 10:54:33.110052 [RX_INPUT] configuration <<<<<
3880 10:54:33.116017 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3881 10:54:33.122397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3882 10:54:33.126244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 10:54:33.132529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 10:54:33.139057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 10:54:33.145519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 10:54:33.149192 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3887 10:54:33.152224 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3888 10:54:33.158917 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3889 10:54:33.162176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3890 10:54:33.165295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3891 10:54:33.172627 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 10:54:33.175568 ===================================
3893 10:54:33.176013 LPDDR4 DRAM CONFIGURATION
3894 10:54:33.178995 ===================================
3895 10:54:33.182060 EX_ROW_EN[0] = 0x0
3896 10:54:33.185346 EX_ROW_EN[1] = 0x0
3897 10:54:33.185770 LP4Y_EN = 0x0
3898 10:54:33.188998 WORK_FSP = 0x0
3899 10:54:33.189422 WL = 0x2
3900 10:54:33.191975 RL = 0x2
3901 10:54:33.192395 BL = 0x2
3902 10:54:33.195563 RPST = 0x0
3903 10:54:33.195983 RD_PRE = 0x0
3904 10:54:33.198717 WR_PRE = 0x1
3905 10:54:33.199138 WR_PST = 0x0
3906 10:54:33.201967 DBI_WR = 0x0
3907 10:54:33.202389 DBI_RD = 0x0
3908 10:54:33.205257 OTF = 0x1
3909 10:54:33.208542 ===================================
3910 10:54:33.211663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3911 10:54:33.214864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3912 10:54:33.221599 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 10:54:33.225031 ===================================
3914 10:54:33.225459 LPDDR4 DRAM CONFIGURATION
3915 10:54:33.228089 ===================================
3916 10:54:33.231742 EX_ROW_EN[0] = 0x10
3917 10:54:33.234898 EX_ROW_EN[1] = 0x0
3918 10:54:33.235323 LP4Y_EN = 0x0
3919 10:54:33.238117 WORK_FSP = 0x0
3920 10:54:33.238546 WL = 0x2
3921 10:54:33.241275 RL = 0x2
3922 10:54:33.241705 BL = 0x2
3923 10:54:33.244992 RPST = 0x0
3924 10:54:33.245417 RD_PRE = 0x0
3925 10:54:33.248144 WR_PRE = 0x1
3926 10:54:33.248573 WR_PST = 0x0
3927 10:54:33.251420 DBI_WR = 0x0
3928 10:54:33.251846 DBI_RD = 0x0
3929 10:54:33.254448 OTF = 0x1
3930 10:54:33.257985 ===================================
3931 10:54:33.264405 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3932 10:54:33.267692 nWR fixed to 30
3933 10:54:33.268121 [ModeRegInit_LP4] CH0 RK0
3934 10:54:33.271210 [ModeRegInit_LP4] CH0 RK1
3935 10:54:33.274428 [ModeRegInit_LP4] CH1 RK0
3936 10:54:33.278037 [ModeRegInit_LP4] CH1 RK1
3937 10:54:33.278464 match AC timing 17
3938 10:54:33.284570 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3939 10:54:33.287794 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3940 10:54:33.291093 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3941 10:54:33.297420 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3942 10:54:33.300904 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3943 10:54:33.301332 ==
3944 10:54:33.304117 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 10:54:33.307445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 10:54:33.307877 ==
3947 10:54:33.314251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 10:54:33.321064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3949 10:54:33.323987 [CA 0] Center 36 (6~67) winsize 62
3950 10:54:33.327230 [CA 1] Center 36 (6~67) winsize 62
3951 10:54:33.330847 [CA 2] Center 34 (4~65) winsize 62
3952 10:54:33.333916 [CA 3] Center 34 (4~65) winsize 62
3953 10:54:33.337338 [CA 4] Center 34 (3~65) winsize 63
3954 10:54:33.340543 [CA 5] Center 33 (3~64) winsize 62
3955 10:54:33.341144
3956 10:54:33.344053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3957 10:54:33.344567
3958 10:54:33.347073 [CATrainingPosCal] consider 1 rank data
3959 10:54:33.350453 u2DelayCellTimex100 = 270/100 ps
3960 10:54:33.353619 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3961 10:54:33.356893 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3962 10:54:33.360069 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 10:54:33.363784 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 10:54:33.366708 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3965 10:54:33.373631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 10:54:33.374053
3967 10:54:33.376725 CA PerBit enable=1, Macro0, CA PI delay=33
3968 10:54:33.377190
3969 10:54:33.380193 [CBTSetCACLKResult] CA Dly = 33
3970 10:54:33.380617 CS Dly: 4 (0~35)
3971 10:54:33.381000 ==
3972 10:54:33.383689 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 10:54:33.386879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 10:54:33.390083 ==
3975 10:54:33.393311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 10:54:33.400080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3977 10:54:33.403289 [CA 0] Center 36 (6~67) winsize 62
3978 10:54:33.406612 [CA 1] Center 36 (6~67) winsize 62
3979 10:54:33.409623 [CA 2] Center 35 (4~66) winsize 63
3980 10:54:33.412882 [CA 3] Center 34 (4~65) winsize 62
3981 10:54:33.416193 [CA 4] Center 34 (3~65) winsize 63
3982 10:54:33.419642 [CA 5] Center 34 (3~65) winsize 63
3983 10:54:33.420065
3984 10:54:33.423121 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3985 10:54:33.423545
3986 10:54:33.426313 [CATrainingPosCal] consider 2 rank data
3987 10:54:33.429871 u2DelayCellTimex100 = 270/100 ps
3988 10:54:33.432936 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3989 10:54:33.436196 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3990 10:54:33.439476 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 10:54:33.446372 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 10:54:33.449360 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3993 10:54:33.452887 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 10:54:33.453313
3995 10:54:33.455852 CA PerBit enable=1, Macro0, CA PI delay=33
3996 10:54:33.456273
3997 10:54:33.459589 [CBTSetCACLKResult] CA Dly = 33
3998 10:54:33.460011 CS Dly: 5 (0~37)
3999 10:54:33.460344
4000 10:54:33.462918 ----->DramcWriteLeveling(PI) begin...
4001 10:54:33.466073 ==
4002 10:54:33.466498 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 10:54:33.472481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 10:54:33.472977 ==
4005 10:54:33.475742 Write leveling (Byte 0): 36 => 36
4006 10:54:33.479317 Write leveling (Byte 1): 31 => 31
4007 10:54:33.482698 DramcWriteLeveling(PI) end<-----
4008 10:54:33.483149
4009 10:54:33.483801 ==
4010 10:54:33.485974 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 10:54:33.489349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 10:54:33.489942 ==
4013 10:54:33.492591 [Gating] SW mode calibration
4014 10:54:33.499546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4015 10:54:33.505782 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4016 10:54:33.509234 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 10:54:33.512280 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 10:54:33.518808 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 10:54:33.522135 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
4020 10:54:33.525096 0 9 16 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
4021 10:54:33.528875 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 10:54:33.535457 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 10:54:33.538786 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 10:54:33.541798 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 10:54:33.548395 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 10:54:33.551620 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4027 10:54:33.554890 0 10 12 | B1->B0 | 2323 3838 | 1 0 | (0 0) (0 0)
4028 10:54:33.561477 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4029 10:54:33.564879 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 10:54:33.568219 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 10:54:33.574778 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 10:54:33.578443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 10:54:33.581361 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 10:54:33.588452 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 10:54:33.591343 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4036 10:54:33.595009 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4037 10:54:33.601492 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 10:54:33.604561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 10:54:33.607759 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 10:54:33.614480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 10:54:33.617999 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 10:54:33.621082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 10:54:33.627800 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 10:54:33.630962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 10:54:33.634266 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:54:33.640774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:54:33.644054 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:54:33.647750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 10:54:33.654027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 10:54:33.657238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4051 10:54:33.660643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 10:54:33.667377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4053 10:54:33.670564 Total UI for P1: 0, mck2ui 16
4054 10:54:33.674344 best dqsien dly found for B0: ( 0, 13, 14)
4055 10:54:33.677542 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 10:54:33.680686 Total UI for P1: 0, mck2ui 16
4057 10:54:33.684321 best dqsien dly found for B1: ( 0, 13, 16)
4058 10:54:33.687303 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4059 10:54:33.690779 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4060 10:54:33.691204
4061 10:54:33.694046 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4062 10:54:33.700563 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4063 10:54:33.701154 [Gating] SW calibration Done
4064 10:54:33.701634 ==
4065 10:54:33.704113 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 10:54:33.710687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 10:54:33.711111 ==
4068 10:54:33.711446 RX Vref Scan: 0
4069 10:54:33.711800
4070 10:54:33.713599 RX Vref 0 -> 0, step: 1
4071 10:54:33.714023
4072 10:54:33.717283 RX Delay -230 -> 252, step: 16
4073 10:54:33.720740 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4074 10:54:33.723840 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4075 10:54:33.726984 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4076 10:54:33.733965 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4077 10:54:33.736667 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4078 10:54:33.740317 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4079 10:54:33.743573 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4080 10:54:33.750184 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4081 10:54:33.753571 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4082 10:54:33.756689 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4083 10:54:33.760306 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4084 10:54:33.766633 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4085 10:54:33.770069 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4086 10:54:33.773646 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4087 10:54:33.776665 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4088 10:54:33.784015 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4089 10:54:33.784441 ==
4090 10:54:33.786855 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 10:54:33.790474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 10:54:33.790899 ==
4093 10:54:33.791237 DQS Delay:
4094 10:54:33.793527 DQS0 = 0, DQS1 = 0
4095 10:54:33.793946 DQM Delay:
4096 10:54:33.796651 DQM0 = 51, DQM1 = 39
4097 10:54:33.797133 DQ Delay:
4098 10:54:33.800140 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4099 10:54:33.803350 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4100 10:54:33.806780 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4101 10:54:33.809889 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4102 10:54:33.810310
4103 10:54:33.810641
4104 10:54:33.810950 ==
4105 10:54:33.813201 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 10:54:33.816405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 10:54:33.816864 ==
4108 10:54:33.817207
4109 10:54:33.817520
4110 10:54:33.819611 TX Vref Scan disable
4111 10:54:33.822954 == TX Byte 0 ==
4112 10:54:33.826392 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4113 10:54:33.829807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4114 10:54:33.832983 == TX Byte 1 ==
4115 10:54:33.835942 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4116 10:54:33.839276 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4117 10:54:33.839359 ==
4118 10:54:33.842552 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 10:54:33.849131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 10:54:33.849215 ==
4121 10:54:33.849280
4122 10:54:33.849379
4123 10:54:33.852164 TX Vref Scan disable
4124 10:54:33.852247 == TX Byte 0 ==
4125 10:54:33.858967 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4126 10:54:33.862174 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4127 10:54:33.862257 == TX Byte 1 ==
4128 10:54:33.868661 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4129 10:54:33.872368 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4130 10:54:33.872452
4131 10:54:33.872516 [DATLAT]
4132 10:54:33.875278 Freq=600, CH0 RK0
4133 10:54:33.875361
4134 10:54:33.875426 DATLAT Default: 0x9
4135 10:54:33.878782 0, 0xFFFF, sum = 0
4136 10:54:33.878866 1, 0xFFFF, sum = 0
4137 10:54:33.882099 2, 0xFFFF, sum = 0
4138 10:54:33.885459 3, 0xFFFF, sum = 0
4139 10:54:33.885543 4, 0xFFFF, sum = 0
4140 10:54:33.888722 5, 0xFFFF, sum = 0
4141 10:54:33.888851 6, 0xFFFF, sum = 0
4142 10:54:33.891988 7, 0xFFFF, sum = 0
4143 10:54:33.892073 8, 0x0, sum = 1
4144 10:54:33.892139 9, 0x0, sum = 2
4145 10:54:33.895422 10, 0x0, sum = 3
4146 10:54:33.895505 11, 0x0, sum = 4
4147 10:54:33.898425 best_step = 9
4148 10:54:33.898536
4149 10:54:33.898604 ==
4150 10:54:33.901858 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 10:54:33.905246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 10:54:33.905359 ==
4153 10:54:33.908423 RX Vref Scan: 1
4154 10:54:33.908524
4155 10:54:33.908616 RX Vref 0 -> 0, step: 1
4156 10:54:33.908704
4157 10:54:33.911806 RX Delay -179 -> 252, step: 8
4158 10:54:33.911889
4159 10:54:33.914994 Set Vref, RX VrefLevel [Byte0]: 60
4160 10:54:33.918326 [Byte1]: 49
4161 10:54:33.922491
4162 10:54:33.922585 Final RX Vref Byte 0 = 60 to rank0
4163 10:54:33.926362 Final RX Vref Byte 1 = 49 to rank0
4164 10:54:33.929541 Final RX Vref Byte 0 = 60 to rank1
4165 10:54:33.932845 Final RX Vref Byte 1 = 49 to rank1==
4166 10:54:33.936027 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 10:54:33.942950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 10:54:33.943373 ==
4169 10:54:33.943708 DQS Delay:
4170 10:54:33.946089 DQS0 = 0, DQS1 = 0
4171 10:54:33.946509 DQM Delay:
4172 10:54:33.946848 DQM0 = 47, DQM1 = 39
4173 10:54:33.949095 DQ Delay:
4174 10:54:33.952581 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =44
4175 10:54:33.955741 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4176 10:54:33.958928 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4177 10:54:33.962187 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4178 10:54:33.962610
4179 10:54:33.962948
4180 10:54:33.968998 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4181 10:54:33.972264 CH0 RK0: MR19=808, MR18=5B55
4182 10:54:33.978664 CH0_RK0: MR19=0x808, MR18=0x5B55, DQSOSC=392, MR23=63, INC=170, DEC=113
4183 10:54:33.979126
4184 10:54:33.982035 ----->DramcWriteLeveling(PI) begin...
4185 10:54:33.982461 ==
4186 10:54:33.985671 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 10:54:33.988743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 10:54:33.989208 ==
4189 10:54:33.991863 Write leveling (Byte 0): 34 => 34
4190 10:54:33.995122 Write leveling (Byte 1): 30 => 30
4191 10:54:33.998180 DramcWriteLeveling(PI) end<-----
4192 10:54:33.998613
4193 10:54:33.998971 ==
4194 10:54:34.001793 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 10:54:34.008076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 10:54:34.008501 ==
4197 10:54:34.011502 [Gating] SW mode calibration
4198 10:54:34.018441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4199 10:54:34.021555 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4200 10:54:34.027842 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 10:54:34.031642 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 10:54:34.034738 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 10:54:34.041242 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 1)
4204 10:54:34.044380 0 9 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
4205 10:54:34.048029 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 10:54:34.051262 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 10:54:34.057727 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 10:54:34.061390 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 10:54:34.064401 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 10:54:34.070820 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 10:54:34.074120 0 10 12 | B1->B0 | 2727 3434 | 1 0 | (1 1) (0 0)
4212 10:54:34.080592 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4213 10:54:34.083878 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 10:54:34.087374 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 10:54:34.094118 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 10:54:34.096863 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 10:54:34.100410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 10:54:34.106942 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 10:54:34.110271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4220 10:54:34.113600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 10:54:34.120209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 10:54:34.123594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 10:54:34.126676 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 10:54:34.133592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 10:54:34.136950 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 10:54:34.139987 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 10:54:34.146545 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 10:54:34.149772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:54:34.153107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:54:34.156514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:54:34.163252 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 10:54:34.166352 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 10:54:34.169446 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 10:54:34.176027 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 10:54:34.179670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4236 10:54:34.182861 Total UI for P1: 0, mck2ui 16
4237 10:54:34.186135 best dqsien dly found for B0: ( 0, 13, 10)
4238 10:54:34.189330 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 10:54:34.192747 Total UI for P1: 0, mck2ui 16
4240 10:54:34.196438 best dqsien dly found for B1: ( 0, 13, 12)
4241 10:54:34.199332 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4242 10:54:34.205996 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4243 10:54:34.206081
4244 10:54:34.209146 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4245 10:54:34.212484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4246 10:54:34.216171 [Gating] SW calibration Done
4247 10:54:34.216728 ==
4248 10:54:34.219790 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 10:54:34.222334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 10:54:34.222425 ==
4251 10:54:34.225726 RX Vref Scan: 0
4252 10:54:34.225809
4253 10:54:34.225876 RX Vref 0 -> 0, step: 1
4254 10:54:34.225938
4255 10:54:34.228822 RX Delay -230 -> 252, step: 16
4256 10:54:34.232465 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4257 10:54:34.239132 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4258 10:54:34.242111 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4259 10:54:34.245375 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4260 10:54:34.248598 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4261 10:54:34.255301 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4262 10:54:34.259050 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4263 10:54:34.262016 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4264 10:54:34.265099 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4265 10:54:34.268713 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4266 10:54:34.274960 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4267 10:54:34.278591 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4268 10:54:34.282206 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4269 10:54:34.285380 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4270 10:54:34.291807 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4271 10:54:34.295448 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4272 10:54:34.295877 ==
4273 10:54:34.298433 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 10:54:34.301706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 10:54:34.302151 ==
4276 10:54:34.305405 DQS Delay:
4277 10:54:34.305916 DQS0 = 0, DQS1 = 0
4278 10:54:34.308561 DQM Delay:
4279 10:54:34.309082 DQM0 = 48, DQM1 = 42
4280 10:54:34.309428 DQ Delay:
4281 10:54:34.311873 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4282 10:54:34.315096 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4283 10:54:34.318540 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4284 10:54:34.322105 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4285 10:54:34.322546
4286 10:54:34.322887
4287 10:54:34.324855 ==
4288 10:54:34.328275 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 10:54:34.331657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 10:54:34.332244 ==
4291 10:54:34.332823
4292 10:54:34.333308
4293 10:54:34.334814 TX Vref Scan disable
4294 10:54:34.335238 == TX Byte 0 ==
4295 10:54:34.341603 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4296 10:54:34.344836 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4297 10:54:34.345264 == TX Byte 1 ==
4298 10:54:34.351336 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4299 10:54:34.355014 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4300 10:54:34.355520 ==
4301 10:54:34.358251 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 10:54:34.361304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 10:54:34.361733 ==
4304 10:54:34.362069
4305 10:54:34.362386
4306 10:54:34.364857 TX Vref Scan disable
4307 10:54:34.367735 == TX Byte 0 ==
4308 10:54:34.371442 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4309 10:54:34.374611 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4310 10:54:34.377919 == TX Byte 1 ==
4311 10:54:34.381006 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4312 10:54:34.387953 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4313 10:54:34.388406
4314 10:54:34.388937 [DATLAT]
4315 10:54:34.389272 Freq=600, CH0 RK1
4316 10:54:34.389577
4317 10:54:34.391003 DATLAT Default: 0x9
4318 10:54:34.391416 0, 0xFFFF, sum = 0
4319 10:54:34.394134 1, 0xFFFF, sum = 0
4320 10:54:34.394568 2, 0xFFFF, sum = 0
4321 10:54:34.397906 3, 0xFFFF, sum = 0
4322 10:54:34.400655 4, 0xFFFF, sum = 0
4323 10:54:34.401113 5, 0xFFFF, sum = 0
4324 10:54:34.403865 6, 0xFFFF, sum = 0
4325 10:54:34.403974 7, 0xFFFF, sum = 0
4326 10:54:34.407040 8, 0x0, sum = 1
4327 10:54:34.407123 9, 0x0, sum = 2
4328 10:54:34.407189 10, 0x0, sum = 3
4329 10:54:34.410583 11, 0x0, sum = 4
4330 10:54:34.410665 best_step = 9
4331 10:54:34.410730
4332 10:54:34.410789 ==
4333 10:54:34.414149 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 10:54:34.420187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 10:54:34.420273 ==
4336 10:54:34.420339 RX Vref Scan: 0
4337 10:54:34.420411
4338 10:54:34.423721 RX Vref 0 -> 0, step: 1
4339 10:54:34.423802
4340 10:54:34.427161 RX Delay -179 -> 252, step: 8
4341 10:54:34.430808 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4342 10:54:34.437416 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4343 10:54:34.440671 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4344 10:54:34.443979 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4345 10:54:34.447353 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4346 10:54:34.450548 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4347 10:54:34.457053 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4348 10:54:34.460404 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4349 10:54:34.463961 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4350 10:54:34.466740 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4351 10:54:34.473687 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4352 10:54:34.477034 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4353 10:54:34.480103 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4354 10:54:34.483656 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4355 10:54:34.490151 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4356 10:54:34.493296 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4357 10:54:34.493713 ==
4358 10:54:34.496573 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 10:54:34.500111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 10:54:34.500547 ==
4361 10:54:34.500914 DQS Delay:
4362 10:54:34.503331 DQS0 = 0, DQS1 = 0
4363 10:54:34.503730 DQM Delay:
4364 10:54:34.506511 DQM0 = 48, DQM1 = 40
4365 10:54:34.507058 DQ Delay:
4366 10:54:34.510121 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4367 10:54:34.513194 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4368 10:54:34.516313 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4369 10:54:34.519955 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =48
4370 10:54:34.520392
4371 10:54:34.520742
4372 10:54:34.529579 [DQSOSCAuto] RK1, (LSB)MR18= 0x6534, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4373 10:54:34.530030 CH0 RK1: MR19=808, MR18=6534
4374 10:54:34.536586 CH0_RK1: MR19=0x808, MR18=0x6534, DQSOSC=390, MR23=63, INC=172, DEC=114
4375 10:54:34.539526 [RxdqsGatingPostProcess] freq 600
4376 10:54:34.546026 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4377 10:54:34.549532 Pre-setting of DQS Precalculation
4378 10:54:34.552625 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4379 10:54:34.553080 ==
4380 10:54:34.556023 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 10:54:34.562918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 10:54:34.563334 ==
4383 10:54:34.566180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 10:54:34.572453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4385 10:54:34.575636 [CA 0] Center 35 (5~66) winsize 62
4386 10:54:34.578898 [CA 1] Center 35 (5~66) winsize 62
4387 10:54:34.582764 [CA 2] Center 34 (4~65) winsize 62
4388 10:54:34.585719 [CA 3] Center 33 (3~64) winsize 62
4389 10:54:34.588946 [CA 4] Center 34 (3~65) winsize 63
4390 10:54:34.592277 [CA 5] Center 33 (3~64) winsize 62
4391 10:54:34.592686
4392 10:54:34.595478 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4393 10:54:34.595923
4394 10:54:34.598630 [CATrainingPosCal] consider 1 rank data
4395 10:54:34.602222 u2DelayCellTimex100 = 270/100 ps
4396 10:54:34.605354 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 10:54:34.612122 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 10:54:34.615350 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 10:54:34.618476 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 10:54:34.621955 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4401 10:54:34.625352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 10:54:34.625763
4403 10:54:34.628701 CA PerBit enable=1, Macro0, CA PI delay=33
4404 10:54:34.629173
4405 10:54:34.631689 [CBTSetCACLKResult] CA Dly = 33
4406 10:54:34.635182 CS Dly: 4 (0~35)
4407 10:54:34.635595 ==
4408 10:54:34.638375 Dram Type= 6, Freq= 0, CH_1, rank 1
4409 10:54:34.641879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 10:54:34.642297 ==
4411 10:54:34.648129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 10:54:34.651400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4413 10:54:34.656011 [CA 0] Center 35 (5~66) winsize 62
4414 10:54:34.659240 [CA 1] Center 35 (5~66) winsize 62
4415 10:54:34.662523 [CA 2] Center 34 (4~65) winsize 62
4416 10:54:34.665626 [CA 3] Center 34 (4~65) winsize 62
4417 10:54:34.668916 [CA 4] Center 34 (4~65) winsize 62
4418 10:54:34.672322 [CA 5] Center 33 (3~64) winsize 62
4419 10:54:34.672808
4420 10:54:34.675949 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4421 10:54:34.676359
4422 10:54:34.679036 [CATrainingPosCal] consider 2 rank data
4423 10:54:34.682427 u2DelayCellTimex100 = 270/100 ps
4424 10:54:34.685496 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 10:54:34.692235 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 10:54:34.695308 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4427 10:54:34.698780 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4428 10:54:34.701960 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 10:54:34.705529 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 10:54:34.705968
4431 10:54:34.708757 CA PerBit enable=1, Macro0, CA PI delay=33
4432 10:54:34.709270
4433 10:54:34.711745 [CBTSetCACLKResult] CA Dly = 33
4434 10:54:34.715561 CS Dly: 4 (0~36)
4435 10:54:34.716126
4436 10:54:34.718675 ----->DramcWriteLeveling(PI) begin...
4437 10:54:34.719135 ==
4438 10:54:34.721977 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 10:54:34.725088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 10:54:34.725513 ==
4441 10:54:34.728503 Write leveling (Byte 0): 30 => 30
4442 10:54:34.731518 Write leveling (Byte 1): 30 => 30
4443 10:54:34.734889 DramcWriteLeveling(PI) end<-----
4444 10:54:34.735354
4445 10:54:34.735754 ==
4446 10:54:34.738177 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 10:54:34.741830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 10:54:34.742256 ==
4449 10:54:34.744920 [Gating] SW mode calibration
4450 10:54:34.751468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4451 10:54:34.758073 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4452 10:54:34.761255 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 10:54:34.764812 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 10:54:34.771337 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 10:54:34.774774 0 9 12 | B1->B0 | 2e2e 2e2e | 0 1 | (0 1) (1 0)
4456 10:54:34.777815 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 10:54:34.784627 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 10:54:34.787951 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 10:54:34.791304 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 10:54:34.797545 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 10:54:34.800836 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 10:54:34.803982 0 10 8 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4463 10:54:34.810920 0 10 12 | B1->B0 | 3838 4242 | 1 0 | (0 0) (0 0)
4464 10:54:34.813816 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 10:54:34.817021 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 10:54:34.824204 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 10:54:34.827094 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 10:54:34.830466 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 10:54:34.837261 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 10:54:34.840308 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 10:54:34.843839 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4472 10:54:34.850590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 10:54:34.853350 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 10:54:34.856862 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 10:54:34.863473 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:54:34.866790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 10:54:34.870014 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 10:54:34.876511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:54:34.879947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:54:34.883318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:54:34.890214 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:54:34.893095 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:54:34.896575 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:54:34.903164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 10:54:34.906349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 10:54:34.909674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4487 10:54:34.916372 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4488 10:54:34.919445 Total UI for P1: 0, mck2ui 16
4489 10:54:34.923127 best dqsien dly found for B0: ( 0, 13, 8)
4490 10:54:34.926657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 10:54:34.929640 Total UI for P1: 0, mck2ui 16
4492 10:54:34.932905 best dqsien dly found for B1: ( 0, 13, 12)
4493 10:54:34.936149 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4494 10:54:34.939460 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4495 10:54:34.940073
4496 10:54:34.942724 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4497 10:54:34.949527 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4498 10:54:34.950118 [Gating] SW calibration Done
4499 10:54:34.950670 ==
4500 10:54:34.952730 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 10:54:34.958947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 10:54:34.959499 ==
4503 10:54:34.960025 RX Vref Scan: 0
4504 10:54:34.960535
4505 10:54:34.962306 RX Vref 0 -> 0, step: 1
4506 10:54:34.962812
4507 10:54:34.966165 RX Delay -230 -> 252, step: 16
4508 10:54:34.968892 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4509 10:54:34.972051 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4510 10:54:34.975715 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4511 10:54:34.982130 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4512 10:54:34.985416 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4513 10:54:34.988852 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4514 10:54:34.992015 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4515 10:54:34.998683 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4516 10:54:35.002433 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4517 10:54:35.005734 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4518 10:54:35.008868 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4519 10:54:35.015607 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4520 10:54:35.018749 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4521 10:54:35.021913 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4522 10:54:35.025280 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4523 10:54:35.032063 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4524 10:54:35.032486 ==
4525 10:54:35.035445 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 10:54:35.038676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 10:54:35.039102 ==
4528 10:54:35.039439 DQS Delay:
4529 10:54:35.041776 DQS0 = 0, DQS1 = 0
4530 10:54:35.042198 DQM Delay:
4531 10:54:35.045159 DQM0 = 52, DQM1 = 43
4532 10:54:35.045656 DQ Delay:
4533 10:54:35.048229 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4534 10:54:35.051423 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4535 10:54:35.054776 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4536 10:54:35.058559 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4537 10:54:35.058994
4538 10:54:35.059331
4539 10:54:35.059643 ==
4540 10:54:35.061767 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 10:54:35.065010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 10:54:35.065453 ==
4543 10:54:35.065816
4544 10:54:35.067922
4545 10:54:35.068368 TX Vref Scan disable
4546 10:54:35.071556 == TX Byte 0 ==
4547 10:54:35.074879 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4548 10:54:35.078091 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4549 10:54:35.081444 == TX Byte 1 ==
4550 10:54:35.084486 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4551 10:54:35.087723 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4552 10:54:35.088117 ==
4553 10:54:35.091342 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 10:54:35.097729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 10:54:35.098159 ==
4556 10:54:35.098499
4557 10:54:35.098853
4558 10:54:35.099197 TX Vref Scan disable
4559 10:54:35.102393 == TX Byte 0 ==
4560 10:54:35.105730 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 10:54:35.112215 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 10:54:35.112723 == TX Byte 1 ==
4563 10:54:35.115450 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4564 10:54:35.122090 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4565 10:54:35.122566
4566 10:54:35.122912 [DATLAT]
4567 10:54:35.123230 Freq=600, CH1 RK0
4568 10:54:35.123535
4569 10:54:35.125536 DATLAT Default: 0x9
4570 10:54:35.129019 0, 0xFFFF, sum = 0
4571 10:54:35.129424 1, 0xFFFF, sum = 0
4572 10:54:35.131911 2, 0xFFFF, sum = 0
4573 10:54:35.132383 3, 0xFFFF, sum = 0
4574 10:54:35.135242 4, 0xFFFF, sum = 0
4575 10:54:35.135630 5, 0xFFFF, sum = 0
4576 10:54:35.138838 6, 0xFFFF, sum = 0
4577 10:54:35.139271 7, 0xFFFF, sum = 0
4578 10:54:35.142122 8, 0x0, sum = 1
4579 10:54:35.142556 9, 0x0, sum = 2
4580 10:54:35.145202 10, 0x0, sum = 3
4581 10:54:35.145611 11, 0x0, sum = 4
4582 10:54:35.146040 best_step = 9
4583 10:54:35.146358
4584 10:54:35.148482 ==
4585 10:54:35.148905 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 10:54:35.155316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 10:54:35.155843 ==
4588 10:54:35.156250 RX Vref Scan: 1
4589 10:54:35.156978
4590 10:54:35.158603 RX Vref 0 -> 0, step: 1
4591 10:54:35.159045
4592 10:54:35.161805 RX Delay -179 -> 252, step: 8
4593 10:54:35.162389
4594 10:54:35.164889 Set Vref, RX VrefLevel [Byte0]: 51
4595 10:54:35.168686 [Byte1]: 53
4596 10:54:35.169165
4597 10:54:35.171497 Final RX Vref Byte 0 = 51 to rank0
4598 10:54:35.175050 Final RX Vref Byte 1 = 53 to rank0
4599 10:54:35.178255 Final RX Vref Byte 0 = 51 to rank1
4600 10:54:35.181909 Final RX Vref Byte 1 = 53 to rank1==
4601 10:54:35.184589 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 10:54:35.191040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 10:54:35.191498 ==
4604 10:54:35.191840 DQS Delay:
4605 10:54:35.192158 DQS0 = 0, DQS1 = 0
4606 10:54:35.194665 DQM Delay:
4607 10:54:35.195109 DQM0 = 49, DQM1 = 40
4608 10:54:35.197683 DQ Delay:
4609 10:54:35.200833 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4610 10:54:35.204462 DQ4 =52, DQ5 =60, DQ6 =56, DQ7 =44
4611 10:54:35.207542 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4612 10:54:35.210843 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4613 10:54:35.211319
4614 10:54:35.211660
4615 10:54:35.217397 [DQSOSCAuto] RK0, (LSB)MR18= 0x466d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4616 10:54:35.220535 CH1 RK0: MR19=808, MR18=466D
4617 10:54:35.227436 CH1_RK0: MR19=0x808, MR18=0x466D, DQSOSC=389, MR23=63, INC=173, DEC=115
4618 10:54:35.227862
4619 10:54:35.230681 ----->DramcWriteLeveling(PI) begin...
4620 10:54:35.231111 ==
4621 10:54:35.233892 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 10:54:35.237495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 10:54:35.238009 ==
4624 10:54:35.240281 Write leveling (Byte 0): 29 => 29
4625 10:54:35.243794 Write leveling (Byte 1): 29 => 29
4626 10:54:35.247091 DramcWriteLeveling(PI) end<-----
4627 10:54:35.247515
4628 10:54:35.247847 ==
4629 10:54:35.250246 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 10:54:35.253746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 10:54:35.256886 ==
4632 10:54:35.257309 [Gating] SW mode calibration
4633 10:54:35.263840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4634 10:54:35.270520 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4635 10:54:35.273854 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 10:54:35.280083 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 10:54:35.283411 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4638 10:54:35.286986 0 9 12 | B1->B0 | 2a2a 2f2f | 0 0 | (1 1) (0 0)
4639 10:54:35.293611 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4640 10:54:35.296565 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 10:54:35.300012 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 10:54:35.306504 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 10:54:35.309809 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 10:54:35.313094 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 10:54:35.319939 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 10:54:35.323027 0 10 12 | B1->B0 | 3d3d 3030 | 0 0 | (0 0) (0 0)
4647 10:54:35.326609 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 10:54:35.332914 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 10:54:35.336474 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 10:54:35.339926 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 10:54:35.346306 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 10:54:35.349696 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 10:54:35.352753 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 10:54:35.359145 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4655 10:54:35.362331 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 10:54:35.365869 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 10:54:35.372420 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 10:54:35.375551 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 10:54:35.378795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 10:54:35.385684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 10:54:35.388973 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 10:54:35.392075 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:54:35.398879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:54:35.402293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:54:35.405483 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:54:35.411965 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:54:35.414976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 10:54:35.418297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 10:54:35.424775 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4670 10:54:35.428204 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4671 10:54:35.431274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 10:54:35.434933 Total UI for P1: 0, mck2ui 16
4673 10:54:35.437857 best dqsien dly found for B0: ( 0, 13, 10)
4674 10:54:35.441190 Total UI for P1: 0, mck2ui 16
4675 10:54:35.444721 best dqsien dly found for B1: ( 0, 13, 12)
4676 10:54:35.448001 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4677 10:54:35.450962 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4678 10:54:35.454608
4679 10:54:35.457589 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4680 10:54:35.461081 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4681 10:54:35.464285 [Gating] SW calibration Done
4682 10:54:35.464387 ==
4683 10:54:35.467639 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 10:54:35.470975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 10:54:35.471094 ==
4686 10:54:35.474093 RX Vref Scan: 0
4687 10:54:35.474217
4688 10:54:35.474328 RX Vref 0 -> 0, step: 1
4689 10:54:35.474431
4690 10:54:35.477515 RX Delay -230 -> 252, step: 16
4691 10:54:35.481112 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4692 10:54:35.487607 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4693 10:54:35.490811 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4694 10:54:35.494117 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4695 10:54:35.497311 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4696 10:54:35.500717 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4697 10:54:35.507860 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4698 10:54:35.510888 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4699 10:54:35.513976 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4700 10:54:35.517066 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4701 10:54:35.523893 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4702 10:54:35.527188 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4703 10:54:35.530613 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4704 10:54:35.533608 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4705 10:54:35.540741 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4706 10:54:35.544121 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4707 10:54:35.544644 ==
4708 10:54:35.547349 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 10:54:35.550635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 10:54:35.551181 ==
4711 10:54:35.553924 DQS Delay:
4712 10:54:35.554541 DQS0 = 0, DQS1 = 0
4713 10:54:35.555099 DQM Delay:
4714 10:54:35.557267 DQM0 = 51, DQM1 = 46
4715 10:54:35.557694 DQ Delay:
4716 10:54:35.560545 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4717 10:54:35.563870 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4718 10:54:35.567247 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4719 10:54:35.570457 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4720 10:54:35.571036
4721 10:54:35.571530
4722 10:54:35.572004 ==
4723 10:54:35.573596 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 10:54:35.580069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 10:54:35.580624 ==
4726 10:54:35.581156
4727 10:54:35.581631
4728 10:54:35.582103 TX Vref Scan disable
4729 10:54:35.583809 == TX Byte 0 ==
4730 10:54:35.587340 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4731 10:54:35.593585 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4732 10:54:35.594059 == TX Byte 1 ==
4733 10:54:35.597072 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4734 10:54:35.603538 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4735 10:54:35.604025 ==
4736 10:54:35.606574 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 10:54:35.609943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 10:54:35.610027 ==
4739 10:54:35.610094
4740 10:54:35.610154
4741 10:54:35.613157 TX Vref Scan disable
4742 10:54:35.616329 == TX Byte 0 ==
4743 10:54:35.619718 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4744 10:54:35.623486 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4745 10:54:35.626812 == TX Byte 1 ==
4746 10:54:35.629954 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4747 10:54:35.633162 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4748 10:54:35.633697
4749 10:54:35.634203 [DATLAT]
4750 10:54:35.636710 Freq=600, CH1 RK1
4751 10:54:35.637207
4752 10:54:35.640172 DATLAT Default: 0x9
4753 10:54:35.640675 0, 0xFFFF, sum = 0
4754 10:54:35.643173 1, 0xFFFF, sum = 0
4755 10:54:35.643870 2, 0xFFFF, sum = 0
4756 10:54:35.646245 3, 0xFFFF, sum = 0
4757 10:54:35.646811 4, 0xFFFF, sum = 0
4758 10:54:35.650005 5, 0xFFFF, sum = 0
4759 10:54:35.650602 6, 0xFFFF, sum = 0
4760 10:54:35.653171 7, 0xFFFF, sum = 0
4761 10:54:35.653692 8, 0x0, sum = 1
4762 10:54:35.656363 9, 0x0, sum = 2
4763 10:54:35.656999 10, 0x0, sum = 3
4764 10:54:35.659544 11, 0x0, sum = 4
4765 10:54:35.660084 best_step = 9
4766 10:54:35.660586
4767 10:54:35.661098 ==
4768 10:54:35.663238 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 10:54:35.666169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 10:54:35.666686 ==
4771 10:54:35.669826 RX Vref Scan: 0
4772 10:54:35.670383
4773 10:54:35.672889 RX Vref 0 -> 0, step: 1
4774 10:54:35.673269
4775 10:54:35.673593 RX Delay -163 -> 252, step: 8
4776 10:54:35.680837 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4777 10:54:35.683765 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4778 10:54:35.687157 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4779 10:54:35.690563 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4780 10:54:35.697257 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4781 10:54:35.700400 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4782 10:54:35.703296 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4783 10:54:35.706626 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4784 10:54:35.709839 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4785 10:54:35.716543 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4786 10:54:35.719535 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4787 10:54:35.723015 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4788 10:54:35.726507 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4789 10:54:35.733173 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4790 10:54:35.736141 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4791 10:54:35.739770 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4792 10:54:35.739879 ==
4793 10:54:35.742961 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 10:54:35.746270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 10:54:35.746377 ==
4796 10:54:35.749195 DQS Delay:
4797 10:54:35.749304 DQS0 = 0, DQS1 = 0
4798 10:54:35.752485 DQM Delay:
4799 10:54:35.752596 DQM0 = 49, DQM1 = 43
4800 10:54:35.756227 DQ Delay:
4801 10:54:35.756342 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4802 10:54:35.759269 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4803 10:54:35.762427 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4804 10:54:35.765765 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4805 10:54:35.765881
4806 10:54:35.769354
4807 10:54:35.775801 [DQSOSCAuto] RK1, (LSB)MR18= 0x5319, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4808 10:54:35.779243 CH1 RK1: MR19=808, MR18=5319
4809 10:54:35.785314 CH1_RK1: MR19=0x808, MR18=0x5319, DQSOSC=394, MR23=63, INC=168, DEC=112
4810 10:54:35.789039 [RxdqsGatingPostProcess] freq 600
4811 10:54:35.792102 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4812 10:54:35.795252 Pre-setting of DQS Precalculation
4813 10:54:35.801817 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4814 10:54:35.808530 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4815 10:54:35.815170 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4816 10:54:35.815282
4817 10:54:35.815379
4818 10:54:35.818410 [Calibration Summary] 1200 Mbps
4819 10:54:35.818521 CH 0, Rank 0
4820 10:54:35.821885 SW Impedance : PASS
4821 10:54:35.825393 DUTY Scan : NO K
4822 10:54:35.825515 ZQ Calibration : PASS
4823 10:54:35.828454 Jitter Meter : NO K
4824 10:54:35.831744 CBT Training : PASS
4825 10:54:35.831867 Write leveling : PASS
4826 10:54:35.835302 RX DQS gating : PASS
4827 10:54:35.838290 RX DQ/DQS(RDDQC) : PASS
4828 10:54:35.838405 TX DQ/DQS : PASS
4829 10:54:35.841792 RX DATLAT : PASS
4830 10:54:35.844935 RX DQ/DQS(Engine): PASS
4831 10:54:35.845039 TX OE : NO K
4832 10:54:35.845134 All Pass.
4833 10:54:35.848164
4834 10:54:35.848264 CH 0, Rank 1
4835 10:54:35.851174 SW Impedance : PASS
4836 10:54:35.851287 DUTY Scan : NO K
4837 10:54:35.854704 ZQ Calibration : PASS
4838 10:54:35.858278 Jitter Meter : NO K
4839 10:54:35.858380 CBT Training : PASS
4840 10:54:35.861239 Write leveling : PASS
4841 10:54:35.861349 RX DQS gating : PASS
4842 10:54:35.864949 RX DQ/DQS(RDDQC) : PASS
4843 10:54:35.867996 TX DQ/DQS : PASS
4844 10:54:35.868112 RX DATLAT : PASS
4845 10:54:35.871561 RX DQ/DQS(Engine): PASS
4846 10:54:35.874706 TX OE : NO K
4847 10:54:35.874811 All Pass.
4848 10:54:35.874903
4849 10:54:35.874992 CH 1, Rank 0
4850 10:54:35.878526 SW Impedance : PASS
4851 10:54:35.881558 DUTY Scan : NO K
4852 10:54:35.882179 ZQ Calibration : PASS
4853 10:54:35.884825 Jitter Meter : NO K
4854 10:54:35.888174 CBT Training : PASS
4855 10:54:35.888743 Write leveling : PASS
4856 10:54:35.891395 RX DQS gating : PASS
4857 10:54:35.894668 RX DQ/DQS(RDDQC) : PASS
4858 10:54:35.895273 TX DQ/DQS : PASS
4859 10:54:35.898124 RX DATLAT : PASS
4860 10:54:35.901330 RX DQ/DQS(Engine): PASS
4861 10:54:35.901756 TX OE : NO K
4862 10:54:35.904821 All Pass.
4863 10:54:35.905372
4864 10:54:35.905856 CH 1, Rank 1
4865 10:54:35.908060 SW Impedance : PASS
4866 10:54:35.908640 DUTY Scan : NO K
4867 10:54:35.911505 ZQ Calibration : PASS
4868 10:54:35.914895 Jitter Meter : NO K
4869 10:54:35.915587 CBT Training : PASS
4870 10:54:35.917929 Write leveling : PASS
4871 10:54:35.918567 RX DQS gating : PASS
4872 10:54:35.921172 RX DQ/DQS(RDDQC) : PASS
4873 10:54:35.924316 TX DQ/DQS : PASS
4874 10:54:35.924879 RX DATLAT : PASS
4875 10:54:35.928111 RX DQ/DQS(Engine): PASS
4876 10:54:35.931267 TX OE : NO K
4877 10:54:35.931797 All Pass.
4878 10:54:35.932303
4879 10:54:35.934430 DramC Write-DBI off
4880 10:54:35.934927 PER_BANK_REFRESH: Hybrid Mode
4881 10:54:35.937675 TX_TRACKING: ON
4882 10:54:35.947761 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4883 10:54:35.950750 [FAST_K] Save calibration result to emmc
4884 10:54:35.954235 dramc_set_vcore_voltage set vcore to 662500
4885 10:54:35.957453 Read voltage for 933, 3
4886 10:54:35.957875 Vio18 = 0
4887 10:54:35.958210 Vcore = 662500
4888 10:54:35.958526 Vdram = 0
4889 10:54:35.960719 Vddq = 0
4890 10:54:35.961175 Vmddr = 0
4891 10:54:35.967514 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4892 10:54:35.970550 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4893 10:54:35.973714 MEM_TYPE=3, freq_sel=17
4894 10:54:35.977424 sv_algorithm_assistance_LP4_1600
4895 10:54:35.980597 ============ PULL DRAM RESETB DOWN ============
4896 10:54:35.983888 ========== PULL DRAM RESETB DOWN end =========
4897 10:54:35.990531 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4898 10:54:35.993615 ===================================
4899 10:54:35.994043 LPDDR4 DRAM CONFIGURATION
4900 10:54:35.996757 ===================================
4901 10:54:36.000250 EX_ROW_EN[0] = 0x0
4902 10:54:36.003523 EX_ROW_EN[1] = 0x0
4903 10:54:36.003946 LP4Y_EN = 0x0
4904 10:54:36.006720 WORK_FSP = 0x0
4905 10:54:36.007144 WL = 0x3
4906 10:54:36.010160 RL = 0x3
4907 10:54:36.010583 BL = 0x2
4908 10:54:36.013666 RPST = 0x0
4909 10:54:36.014131 RD_PRE = 0x0
4910 10:54:36.016868 WR_PRE = 0x1
4911 10:54:36.017289 WR_PST = 0x0
4912 10:54:36.020040 DBI_WR = 0x0
4913 10:54:36.020462 DBI_RD = 0x0
4914 10:54:36.023590 OTF = 0x1
4915 10:54:36.026742 ===================================
4916 10:54:36.030092 ===================================
4917 10:54:36.030536 ANA top config
4918 10:54:36.033282 ===================================
4919 10:54:36.036916 DLL_ASYNC_EN = 0
4920 10:54:36.039874 ALL_SLAVE_EN = 1
4921 10:54:36.043182 NEW_RANK_MODE = 1
4922 10:54:36.043609 DLL_IDLE_MODE = 1
4923 10:54:36.046482 LP45_APHY_COMB_EN = 1
4924 10:54:36.049874 TX_ODT_DIS = 1
4925 10:54:36.052988 NEW_8X_MODE = 1
4926 10:54:36.056457 ===================================
4927 10:54:36.060089 ===================================
4928 10:54:36.063626 data_rate = 1866
4929 10:54:36.064048 CKR = 1
4930 10:54:36.066380 DQ_P2S_RATIO = 8
4931 10:54:36.069857 ===================================
4932 10:54:36.073056 CA_P2S_RATIO = 8
4933 10:54:36.076381 DQ_CA_OPEN = 0
4934 10:54:36.079789 DQ_SEMI_OPEN = 0
4935 10:54:36.083174 CA_SEMI_OPEN = 0
4936 10:54:36.083611 CA_FULL_RATE = 0
4937 10:54:36.086469 DQ_CKDIV4_EN = 1
4938 10:54:36.089644 CA_CKDIV4_EN = 1
4939 10:54:36.092832 CA_PREDIV_EN = 0
4940 10:54:36.096472 PH8_DLY = 0
4941 10:54:36.099537 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4942 10:54:36.099959 DQ_AAMCK_DIV = 4
4943 10:54:36.102818 CA_AAMCK_DIV = 4
4944 10:54:36.106309 CA_ADMCK_DIV = 4
4945 10:54:36.109721 DQ_TRACK_CA_EN = 0
4946 10:54:36.112811 CA_PICK = 933
4947 10:54:36.115961 CA_MCKIO = 933
4948 10:54:36.119675 MCKIO_SEMI = 0
4949 10:54:36.120098 PLL_FREQ = 3732
4950 10:54:36.122885 DQ_UI_PI_RATIO = 32
4951 10:54:36.126149 CA_UI_PI_RATIO = 0
4952 10:54:36.129277 ===================================
4953 10:54:36.132871 ===================================
4954 10:54:36.136270 memory_type:LPDDR4
4955 10:54:36.136692 GP_NUM : 10
4956 10:54:36.139421 SRAM_EN : 1
4957 10:54:36.142513 MD32_EN : 0
4958 10:54:36.145874 ===================================
4959 10:54:36.146298 [ANA_INIT] >>>>>>>>>>>>>>
4960 10:54:36.149085 <<<<<< [CONFIGURE PHASE]: ANA_TX
4961 10:54:36.152502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4962 10:54:36.155670 ===================================
4963 10:54:36.159139 data_rate = 1866,PCW = 0X8f00
4964 10:54:36.162569 ===================================
4965 10:54:36.165957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4966 10:54:36.172252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 10:54:36.175617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 10:54:36.182117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4969 10:54:36.185421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4970 10:54:36.188911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4971 10:54:36.192033 [ANA_INIT] flow start
4972 10:54:36.192455 [ANA_INIT] PLL >>>>>>>>
4973 10:54:36.195281 [ANA_INIT] PLL <<<<<<<<
4974 10:54:36.198528 [ANA_INIT] MIDPI >>>>>>>>
4975 10:54:36.198973 [ANA_INIT] MIDPI <<<<<<<<
4976 10:54:36.202088 [ANA_INIT] DLL >>>>>>>>
4977 10:54:36.205567 [ANA_INIT] flow end
4978 10:54:36.208297 ============ LP4 DIFF to SE enter ============
4979 10:54:36.211983 ============ LP4 DIFF to SE exit ============
4980 10:54:36.215312 [ANA_INIT] <<<<<<<<<<<<<
4981 10:54:36.218463 [Flow] Enable top DCM control >>>>>
4982 10:54:36.221793 [Flow] Enable top DCM control <<<<<
4983 10:54:36.225237 Enable DLL master slave shuffle
4984 10:54:36.228215 ==============================================================
4985 10:54:36.231482 Gating Mode config
4986 10:54:36.238557 ==============================================================
4987 10:54:36.238982 Config description:
4988 10:54:36.248016 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4989 10:54:36.254957 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4990 10:54:36.261239 SELPH_MODE 0: By rank 1: By Phase
4991 10:54:36.264596 ==============================================================
4992 10:54:36.268166 GAT_TRACK_EN = 1
4993 10:54:36.271403 RX_GATING_MODE = 2
4994 10:54:36.274633 RX_GATING_TRACK_MODE = 2
4995 10:54:36.277735 SELPH_MODE = 1
4996 10:54:36.281578 PICG_EARLY_EN = 1
4997 10:54:36.284442 VALID_LAT_VALUE = 1
4998 10:54:36.287702 ==============================================================
4999 10:54:36.294171 Enter into Gating configuration >>>>
5000 10:54:36.297760 Exit from Gating configuration <<<<
5001 10:54:36.298185 Enter into DVFS_PRE_config >>>>>
5002 10:54:36.310704 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5003 10:54:36.313903 Exit from DVFS_PRE_config <<<<<
5004 10:54:36.317455 Enter into PICG configuration >>>>
5005 10:54:36.320402 Exit from PICG configuration <<<<
5006 10:54:36.323951 [RX_INPUT] configuration >>>>>
5007 10:54:36.324374 [RX_INPUT] configuration <<<<<
5008 10:54:36.330352 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5009 10:54:36.337123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5010 10:54:36.340334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 10:54:36.346922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 10:54:36.353409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 10:54:36.360189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 10:54:36.363279 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5015 10:54:36.366951 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5016 10:54:36.373253 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5017 10:54:36.376834 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5018 10:54:36.380227 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5019 10:54:36.386973 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 10:54:36.389798 ===================================
5021 10:54:36.390224 LPDDR4 DRAM CONFIGURATION
5022 10:54:36.393066 ===================================
5023 10:54:36.396502 EX_ROW_EN[0] = 0x0
5024 10:54:36.399722 EX_ROW_EN[1] = 0x0
5025 10:54:36.400145 LP4Y_EN = 0x0
5026 10:54:36.403045 WORK_FSP = 0x0
5027 10:54:36.403463 WL = 0x3
5028 10:54:36.406144 RL = 0x3
5029 10:54:36.406572 BL = 0x2
5030 10:54:36.409530 RPST = 0x0
5031 10:54:36.409949 RD_PRE = 0x0
5032 10:54:36.412951 WR_PRE = 0x1
5033 10:54:36.413370 WR_PST = 0x0
5034 10:54:36.416001 DBI_WR = 0x0
5035 10:54:36.416427 DBI_RD = 0x0
5036 10:54:36.419474 OTF = 0x1
5037 10:54:36.422737 ===================================
5038 10:54:36.426003 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5039 10:54:36.429478 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5040 10:54:36.435923 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 10:54:36.439151 ===================================
5042 10:54:36.439576 LPDDR4 DRAM CONFIGURATION
5043 10:54:36.442904 ===================================
5044 10:54:36.445964 EX_ROW_EN[0] = 0x10
5045 10:54:36.448999 EX_ROW_EN[1] = 0x0
5046 10:54:36.449426 LP4Y_EN = 0x0
5047 10:54:36.452821 WORK_FSP = 0x0
5048 10:54:36.453247 WL = 0x3
5049 10:54:36.455761 RL = 0x3
5050 10:54:36.456210 BL = 0x2
5051 10:54:36.458758 RPST = 0x0
5052 10:54:36.459183 RD_PRE = 0x0
5053 10:54:36.462301 WR_PRE = 0x1
5054 10:54:36.462724 WR_PST = 0x0
5055 10:54:36.465688 DBI_WR = 0x0
5056 10:54:36.466114 DBI_RD = 0x0
5057 10:54:36.469074 OTF = 0x1
5058 10:54:36.472180 ===================================
5059 10:54:36.478749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5060 10:54:36.482260 nWR fixed to 30
5061 10:54:36.485446 [ModeRegInit_LP4] CH0 RK0
5062 10:54:36.485867 [ModeRegInit_LP4] CH0 RK1
5063 10:54:36.488921 [ModeRegInit_LP4] CH1 RK0
5064 10:54:36.492002 [ModeRegInit_LP4] CH1 RK1
5065 10:54:36.492519 match AC timing 9
5066 10:54:36.498772 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5067 10:54:36.502060 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5068 10:54:36.505296 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5069 10:54:36.512057 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5070 10:54:36.515105 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5071 10:54:36.515529 ==
5072 10:54:36.518527 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 10:54:36.521947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 10:54:36.522370 ==
5075 10:54:36.528480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 10:54:36.535287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5077 10:54:36.538558 [CA 0] Center 38 (7~69) winsize 63
5078 10:54:36.541802 [CA 1] Center 38 (8~69) winsize 62
5079 10:54:36.544963 [CA 2] Center 35 (5~66) winsize 62
5080 10:54:36.548124 [CA 3] Center 34 (4~65) winsize 62
5081 10:54:36.551466 [CA 4] Center 34 (4~65) winsize 62
5082 10:54:36.554637 [CA 5] Center 33 (3~64) winsize 62
5083 10:54:36.555057
5084 10:54:36.557930 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5085 10:54:36.558375
5086 10:54:36.561409 [CATrainingPosCal] consider 1 rank data
5087 10:54:36.564534 u2DelayCellTimex100 = 270/100 ps
5088 10:54:36.567974 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5089 10:54:36.571108 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5090 10:54:36.574501 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5091 10:54:36.577839 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5092 10:54:36.580984 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5093 10:54:36.587763 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 10:54:36.588178
5095 10:54:36.590992 CA PerBit enable=1, Macro0, CA PI delay=33
5096 10:54:36.591426
5097 10:54:36.594453 [CBTSetCACLKResult] CA Dly = 33
5098 10:54:36.594963 CS Dly: 7 (0~38)
5099 10:54:36.595299 ==
5100 10:54:36.597660 Dram Type= 6, Freq= 0, CH_0, rank 1
5101 10:54:36.601363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 10:54:36.604103 ==
5103 10:54:36.607892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 10:54:36.614154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5105 10:54:36.617699 [CA 0] Center 38 (8~69) winsize 62
5106 10:54:36.620665 [CA 1] Center 38 (8~69) winsize 62
5107 10:54:36.624238 [CA 2] Center 36 (6~66) winsize 61
5108 10:54:36.627246 [CA 3] Center 35 (5~66) winsize 62
5109 10:54:36.630965 [CA 4] Center 34 (4~65) winsize 62
5110 10:54:36.634111 [CA 5] Center 34 (4~65) winsize 62
5111 10:54:36.634531
5112 10:54:36.637116 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5113 10:54:36.637553
5114 10:54:36.640596 [CATrainingPosCal] consider 2 rank data
5115 10:54:36.644069 u2DelayCellTimex100 = 270/100 ps
5116 10:54:36.647073 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5117 10:54:36.650357 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5118 10:54:36.657281 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5119 10:54:36.660522 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5120 10:54:36.663768 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5121 10:54:36.666833 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5122 10:54:36.667268
5123 10:54:36.670227 CA PerBit enable=1, Macro0, CA PI delay=34
5124 10:54:36.670669
5125 10:54:36.673581 [CBTSetCACLKResult] CA Dly = 34
5126 10:54:36.674004 CS Dly: 7 (0~39)
5127 10:54:36.674340
5128 10:54:36.676594 ----->DramcWriteLeveling(PI) begin...
5129 10:54:36.680385 ==
5130 10:54:36.683405 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 10:54:36.686574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 10:54:36.687004 ==
5133 10:54:36.689963 Write leveling (Byte 0): 34 => 34
5134 10:54:36.693099 Write leveling (Byte 1): 31 => 31
5135 10:54:36.696708 DramcWriteLeveling(PI) end<-----
5136 10:54:36.697163
5137 10:54:36.697506 ==
5138 10:54:36.700029 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 10:54:36.703271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 10:54:36.703703 ==
5141 10:54:36.706480 [Gating] SW mode calibration
5142 10:54:36.713148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5143 10:54:36.719462 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5144 10:54:36.722976 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5145 10:54:36.726507 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 10:54:36.733136 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 10:54:36.736131 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 10:54:36.739603 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 10:54:36.746191 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 10:54:36.749428 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5151 10:54:36.752541 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
5152 10:54:36.759433 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5153 10:54:36.762711 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 10:54:36.765869 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 10:54:36.772347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 10:54:36.775511 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 10:54:36.778991 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 10:54:36.785627 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5159 10:54:36.788728 0 15 28 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
5160 10:54:36.791967 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5161 10:54:36.798891 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 10:54:36.801878 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 10:54:36.805125 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 10:54:36.811458 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 10:54:36.814996 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 10:54:36.818507 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5167 10:54:36.824982 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5168 10:54:36.828270 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5169 10:54:36.831148 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 10:54:36.837996 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 10:54:36.841095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 10:54:36.844381 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 10:54:36.851282 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 10:54:36.854518 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 10:54:36.857820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:54:36.864656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:54:36.867766 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:54:36.871223 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:54:36.877714 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:54:36.880990 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 10:54:36.884297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 10:54:36.890929 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 10:54:36.894318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 10:54:36.897402 Total UI for P1: 0, mck2ui 16
5185 10:54:36.900667 best dqsien dly found for B0: ( 1, 2, 26)
5186 10:54:36.904145 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 10:54:36.907345 Total UI for P1: 0, mck2ui 16
5188 10:54:36.910674 best dqsien dly found for B1: ( 1, 2, 28)
5189 10:54:36.914051 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5190 10:54:36.917807 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5191 10:54:36.918230
5192 10:54:36.924274 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5193 10:54:36.927280 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5194 10:54:36.927778 [Gating] SW calibration Done
5195 10:54:36.930575 ==
5196 10:54:36.933739 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 10:54:36.937124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 10:54:36.937690 ==
5199 10:54:36.938009 RX Vref Scan: 0
5200 10:54:36.938103
5201 10:54:36.940272 RX Vref 0 -> 0, step: 1
5202 10:54:36.940387
5203 10:54:36.943510 RX Delay -80 -> 252, step: 8
5204 10:54:36.946818 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5205 10:54:36.950080 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5206 10:54:36.956592 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5207 10:54:36.960273 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5208 10:54:36.963314 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5209 10:54:36.966456 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5210 10:54:36.970145 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5211 10:54:36.973245 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5212 10:54:36.979594 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5213 10:54:36.983073 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5214 10:54:36.986875 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5215 10:54:36.989882 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5216 10:54:36.992952 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5217 10:54:36.996481 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5218 10:54:37.003058 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5219 10:54:37.006101 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5220 10:54:37.006214 ==
5221 10:54:37.009688 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 10:54:37.012682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 10:54:37.012812 ==
5224 10:54:37.016260 DQS Delay:
5225 10:54:37.016343 DQS0 = 0, DQS1 = 0
5226 10:54:37.016408 DQM Delay:
5227 10:54:37.019459 DQM0 = 105, DQM1 = 90
5228 10:54:37.019542 DQ Delay:
5229 10:54:37.022732 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5230 10:54:37.025770 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5231 10:54:37.029393 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5232 10:54:37.032687 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5233 10:54:37.032821
5234 10:54:37.032904
5235 10:54:37.035727 ==
5236 10:54:37.039149 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 10:54:37.042350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 10:54:37.042473 ==
5239 10:54:37.042572
5240 10:54:37.042662
5241 10:54:37.045747 TX Vref Scan disable
5242 10:54:37.045883 == TX Byte 0 ==
5243 10:54:37.049160 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5244 10:54:37.056000 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5245 10:54:37.056536 == TX Byte 1 ==
5246 10:54:37.062499 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5247 10:54:37.065666 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5248 10:54:37.066133 ==
5249 10:54:37.069090 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 10:54:37.072865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 10:54:37.073375 ==
5252 10:54:37.073718
5253 10:54:37.074133
5254 10:54:37.075779 TX Vref Scan disable
5255 10:54:37.078930 == TX Byte 0 ==
5256 10:54:37.082565 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5257 10:54:37.085643 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5258 10:54:37.088862 == TX Byte 1 ==
5259 10:54:37.092352 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5260 10:54:37.095504 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5261 10:54:37.096086
5262 10:54:37.099048 [DATLAT]
5263 10:54:37.099522 Freq=933, CH0 RK0
5264 10:54:37.099935
5265 10:54:37.102193 DATLAT Default: 0xd
5266 10:54:37.102574 0, 0xFFFF, sum = 0
5267 10:54:37.105712 1, 0xFFFF, sum = 0
5268 10:54:37.106241 2, 0xFFFF, sum = 0
5269 10:54:37.108549 3, 0xFFFF, sum = 0
5270 10:54:37.109148 4, 0xFFFF, sum = 0
5271 10:54:37.112126 5, 0xFFFF, sum = 0
5272 10:54:37.112547 6, 0xFFFF, sum = 0
5273 10:54:37.115370 7, 0xFFFF, sum = 0
5274 10:54:37.115837 8, 0xFFFF, sum = 0
5275 10:54:37.118659 9, 0xFFFF, sum = 0
5276 10:54:37.119216 10, 0x0, sum = 1
5277 10:54:37.121971 11, 0x0, sum = 2
5278 10:54:37.122430 12, 0x0, sum = 3
5279 10:54:37.125208 13, 0x0, sum = 4
5280 10:54:37.125633 best_step = 11
5281 10:54:37.125969
5282 10:54:37.126280 ==
5283 10:54:37.128842 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 10:54:37.135051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 10:54:37.135568 ==
5286 10:54:37.135911 RX Vref Scan: 1
5287 10:54:37.136259
5288 10:54:37.138320 RX Vref 0 -> 0, step: 1
5289 10:54:37.138746
5290 10:54:37.141757 RX Delay -53 -> 252, step: 4
5291 10:54:37.142175
5292 10:54:37.145042 Set Vref, RX VrefLevel [Byte0]: 60
5293 10:54:37.148278 [Byte1]: 49
5294 10:54:37.148904
5295 10:54:37.151532 Final RX Vref Byte 0 = 60 to rank0
5296 10:54:37.154626 Final RX Vref Byte 1 = 49 to rank0
5297 10:54:37.158060 Final RX Vref Byte 0 = 60 to rank1
5298 10:54:37.161403 Final RX Vref Byte 1 = 49 to rank1==
5299 10:54:37.164750 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 10:54:37.168090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 10:54:37.168515 ==
5302 10:54:37.171346 DQS Delay:
5303 10:54:37.171769 DQS0 = 0, DQS1 = 0
5304 10:54:37.174866 DQM Delay:
5305 10:54:37.175288 DQM0 = 107, DQM1 = 92
5306 10:54:37.175623 DQ Delay:
5307 10:54:37.178186 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5308 10:54:37.184749 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =116
5309 10:54:37.187672 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5310 10:54:37.191395 DQ12 =94, DQ13 =96, DQ14 =102, DQ15 =100
5311 10:54:37.191907
5312 10:54:37.192394
5313 10:54:37.198003 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5314 10:54:37.200975 CH0 RK0: MR19=505, MR18=211D
5315 10:54:37.207853 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5316 10:54:37.208361
5317 10:54:37.211247 ----->DramcWriteLeveling(PI) begin...
5318 10:54:37.211683 ==
5319 10:54:37.214536 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 10:54:37.217657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 10:54:37.218183 ==
5322 10:54:37.221147 Write leveling (Byte 0): 29 => 29
5323 10:54:37.224177 Write leveling (Byte 1): 29 => 29
5324 10:54:37.227886 DramcWriteLeveling(PI) end<-----
5325 10:54:37.228296
5326 10:54:37.228623 ==
5327 10:54:37.230785 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 10:54:37.234258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 10:54:37.234696 ==
5330 10:54:37.237598 [Gating] SW mode calibration
5331 10:54:37.244195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5332 10:54:37.250561 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5333 10:54:37.253969 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 10:54:37.260222 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 10:54:37.263674 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 10:54:37.266853 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 10:54:37.273539 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 10:54:37.276787 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 10:54:37.279986 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5340 10:54:37.286865 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5341 10:54:37.290376 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 10:54:37.293643 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 10:54:37.300170 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 10:54:37.303219 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 10:54:37.306659 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 10:54:37.313310 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 10:54:37.316485 0 15 24 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
5348 10:54:37.319798 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5349 10:54:37.326436 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 10:54:37.329994 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 10:54:37.333179 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 10:54:37.339511 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 10:54:37.343110 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 10:54:37.346411 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 10:54:37.352688 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 10:54:37.356151 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5357 10:54:37.359768 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 10:54:37.366084 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 10:54:37.369902 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 10:54:37.372549 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 10:54:37.379339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 10:54:37.382718 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 10:54:37.386091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 10:54:37.392502 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 10:54:37.395564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:54:37.398844 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:54:37.405589 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:54:37.409130 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:54:37.412646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:54:37.419043 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 10:54:37.422232 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 10:54:37.425248 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5373 10:54:37.428573 Total UI for P1: 0, mck2ui 16
5374 10:54:37.431992 best dqsien dly found for B1: ( 1, 2, 26)
5375 10:54:37.438517 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 10:54:37.438943 Total UI for P1: 0, mck2ui 16
5377 10:54:37.445130 best dqsien dly found for B0: ( 1, 2, 28)
5378 10:54:37.448866 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5379 10:54:37.451777 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5380 10:54:37.452197
5381 10:54:37.455036 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5382 10:54:37.458688 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5383 10:54:37.461793 [Gating] SW calibration Done
5384 10:54:37.462331 ==
5385 10:54:37.465250 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 10:54:37.468673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 10:54:37.469132 ==
5388 10:54:37.471849 RX Vref Scan: 0
5389 10:54:37.472271
5390 10:54:37.472606 RX Vref 0 -> 0, step: 1
5391 10:54:37.473026
5392 10:54:37.474991 RX Delay -80 -> 252, step: 8
5393 10:54:37.478174 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5394 10:54:37.485156 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5395 10:54:37.488427 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5396 10:54:37.491802 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5397 10:54:37.495031 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5398 10:54:37.498166 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5399 10:54:37.504357 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5400 10:54:37.508067 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5401 10:54:37.511177 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5402 10:54:37.514695 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5403 10:54:37.517760 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5404 10:54:37.521046 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5405 10:54:37.527586 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5406 10:54:37.530912 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5407 10:54:37.534116 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5408 10:54:37.537600 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5409 10:54:37.538030 ==
5410 10:54:37.540697 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 10:54:37.547182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 10:54:37.547613 ==
5413 10:54:37.547955 DQS Delay:
5414 10:54:37.548270 DQS0 = 0, DQS1 = 0
5415 10:54:37.550327 DQM Delay:
5416 10:54:37.550757 DQM0 = 104, DQM1 = 90
5417 10:54:37.553950 DQ Delay:
5418 10:54:37.557164 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5419 10:54:37.560744 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5420 10:54:37.563837 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5421 10:54:37.567240 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5422 10:54:37.567668
5423 10:54:37.568008
5424 10:54:37.568322 ==
5425 10:54:37.570281 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 10:54:37.573510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 10:54:37.573941 ==
5428 10:54:37.574281
5429 10:54:37.574597
5430 10:54:37.577074 TX Vref Scan disable
5431 10:54:37.580109 == TX Byte 0 ==
5432 10:54:37.583697 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5433 10:54:37.587271 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5434 10:54:37.590178 == TX Byte 1 ==
5435 10:54:37.593737 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5436 10:54:37.597064 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5437 10:54:37.597490 ==
5438 10:54:37.600146 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 10:54:37.603896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 10:54:37.606920 ==
5441 10:54:37.607346
5442 10:54:37.607684
5443 10:54:37.607996 TX Vref Scan disable
5444 10:54:37.610274 == TX Byte 0 ==
5445 10:54:37.613935 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5446 10:54:37.620512 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5447 10:54:37.620984 == TX Byte 1 ==
5448 10:54:37.623566 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5449 10:54:37.630476 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5450 10:54:37.630902
5451 10:54:37.631241 [DATLAT]
5452 10:54:37.631555 Freq=933, CH0 RK1
5453 10:54:37.631861
5454 10:54:37.633473 DATLAT Default: 0xb
5455 10:54:37.633900 0, 0xFFFF, sum = 0
5456 10:54:37.636758 1, 0xFFFF, sum = 0
5457 10:54:37.640320 2, 0xFFFF, sum = 0
5458 10:54:37.640837 3, 0xFFFF, sum = 0
5459 10:54:37.643398 4, 0xFFFF, sum = 0
5460 10:54:37.643831 5, 0xFFFF, sum = 0
5461 10:54:37.646684 6, 0xFFFF, sum = 0
5462 10:54:37.647141 7, 0xFFFF, sum = 0
5463 10:54:37.650190 8, 0xFFFF, sum = 0
5464 10:54:37.650645 9, 0xFFFF, sum = 0
5465 10:54:37.653458 10, 0x0, sum = 1
5466 10:54:37.653929 11, 0x0, sum = 2
5467 10:54:37.656583 12, 0x0, sum = 3
5468 10:54:37.657060 13, 0x0, sum = 4
5469 10:54:37.657413 best_step = 11
5470 10:54:37.659749
5471 10:54:37.660232 ==
5472 10:54:37.663294 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 10:54:37.666685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 10:54:37.667115 ==
5475 10:54:37.667449 RX Vref Scan: 0
5476 10:54:37.669675
5477 10:54:37.670101 RX Vref 0 -> 0, step: 1
5478 10:54:37.670438
5479 10:54:37.673051 RX Delay -53 -> 252, step: 4
5480 10:54:37.679535 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5481 10:54:37.682666 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5482 10:54:37.686127 iDelay=203, Bit 2, Center 100 (15 ~ 186) 172
5483 10:54:37.689079 iDelay=203, Bit 3, Center 100 (15 ~ 186) 172
5484 10:54:37.692946 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5485 10:54:37.699261 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5486 10:54:37.702695 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5487 10:54:37.705753 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5488 10:54:37.709039 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5489 10:54:37.712670 iDelay=203, Bit 9, Center 78 (-5 ~ 162) 168
5490 10:54:37.718853 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5491 10:54:37.722868 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5492 10:54:37.725710 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5493 10:54:37.728879 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5494 10:54:37.732684 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5495 10:54:37.739221 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5496 10:54:37.739672 ==
5497 10:54:37.742257 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 10:54:37.745541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 10:54:37.746003 ==
5500 10:54:37.746415 DQS Delay:
5501 10:54:37.748718 DQS0 = 0, DQS1 = 0
5502 10:54:37.749175 DQM Delay:
5503 10:54:37.752072 DQM0 = 104, DQM1 = 92
5504 10:54:37.752527 DQ Delay:
5505 10:54:37.755718 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5506 10:54:37.758875 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5507 10:54:37.762144 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =92
5508 10:54:37.765040 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5509 10:54:37.765471
5510 10:54:37.765840
5511 10:54:37.775158 [DQSOSCAuto] RK1, (LSB)MR18= 0x2809, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5512 10:54:37.778874 CH0 RK1: MR19=505, MR18=2809
5513 10:54:37.782056 CH0_RK1: MR19=0x505, MR18=0x2809, DQSOSC=409, MR23=63, INC=64, DEC=43
5514 10:54:37.785082 [RxdqsGatingPostProcess] freq 933
5515 10:54:37.791642 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 10:54:37.795077 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 10:54:37.798238 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 10:54:37.801741 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 10:54:37.805122 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 10:54:37.808121 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 10:54:37.811549 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 10:54:37.814889 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 10:54:37.817981 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 10:54:37.821437 Pre-setting of DQS Precalculation
5525 10:54:37.825175 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 10:54:37.825601 ==
5527 10:54:37.828143 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 10:54:37.831624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 10:54:37.832055 ==
5530 10:54:37.837983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 10:54:37.844985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5532 10:54:37.848098 [CA 0] Center 37 (7~68) winsize 62
5533 10:54:37.851177 [CA 1] Center 37 (7~68) winsize 62
5534 10:54:37.855212 [CA 2] Center 36 (6~66) winsize 61
5535 10:54:37.858112 [CA 3] Center 35 (5~65) winsize 61
5536 10:54:37.861405 [CA 4] Center 35 (5~66) winsize 62
5537 10:54:37.864633 [CA 5] Center 34 (5~64) winsize 60
5538 10:54:37.865159
5539 10:54:37.868058 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5540 10:54:37.868632
5541 10:54:37.870841 [CATrainingPosCal] consider 1 rank data
5542 10:54:37.874258 u2DelayCellTimex100 = 270/100 ps
5543 10:54:37.877648 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5544 10:54:37.881157 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5545 10:54:37.884528 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5546 10:54:37.887797 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5547 10:54:37.894344 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5548 10:54:37.897527 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5549 10:54:37.897997
5550 10:54:37.901067 CA PerBit enable=1, Macro0, CA PI delay=34
5551 10:54:37.901631
5552 10:54:37.904027 [CBTSetCACLKResult] CA Dly = 34
5553 10:54:37.904492 CS Dly: 6 (0~37)
5554 10:54:37.904893 ==
5555 10:54:37.907672 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 10:54:37.913837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 10:54:37.914556 ==
5558 10:54:37.917441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 10:54:37.924091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 10:54:37.927273 [CA 0] Center 37 (7~68) winsize 62
5561 10:54:37.930425 [CA 1] Center 38 (8~69) winsize 62
5562 10:54:37.933701 [CA 2] Center 36 (6~66) winsize 61
5563 10:54:37.936877 [CA 3] Center 35 (5~65) winsize 61
5564 10:54:37.940924 [CA 4] Center 35 (5~65) winsize 61
5565 10:54:37.944060 [CA 5] Center 35 (5~65) winsize 61
5566 10:54:37.944620
5567 10:54:37.947360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 10:54:37.947924
5569 10:54:37.950435 [CATrainingPosCal] consider 2 rank data
5570 10:54:37.954041 u2DelayCellTimex100 = 270/100 ps
5571 10:54:37.957019 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5572 10:54:37.960463 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5573 10:54:37.967303 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5574 10:54:37.970673 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5575 10:54:37.973387 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5576 10:54:37.976993 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5577 10:54:37.977563
5578 10:54:37.980674 CA PerBit enable=1, Macro0, CA PI delay=34
5579 10:54:37.981311
5580 10:54:37.983535 [CBTSetCACLKResult] CA Dly = 34
5581 10:54:37.984185 CS Dly: 7 (0~39)
5582 10:54:37.986764
5583 10:54:37.989871 ----->DramcWriteLeveling(PI) begin...
5584 10:54:37.990409 ==
5585 10:54:37.993429 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 10:54:37.996982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 10:54:37.997544 ==
5588 10:54:38.000342 Write leveling (Byte 0): 27 => 27
5589 10:54:38.003146 Write leveling (Byte 1): 30 => 30
5590 10:54:38.006583 DramcWriteLeveling(PI) end<-----
5591 10:54:38.007144
5592 10:54:38.007516 ==
5593 10:54:38.010241 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 10:54:38.013331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 10:54:38.013900 ==
5596 10:54:38.016930 [Gating] SW mode calibration
5597 10:54:38.024177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 10:54:38.029869 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 10:54:38.033351 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 10:54:38.036593 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 10:54:38.043223 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 10:54:38.046507 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 10:54:38.050049 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 10:54:38.056512 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5605 10:54:38.059970 0 14 24 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
5606 10:54:38.062959 0 14 28 | B1->B0 | 2727 2525 | 1 0 | (0 0) (0 0)
5607 10:54:38.069676 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 10:54:38.073272 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 10:54:38.076332 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 10:54:38.082940 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 10:54:38.086367 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 10:54:38.089654 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 10:54:38.096646 0 15 24 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
5614 10:54:38.099575 0 15 28 | B1->B0 | 3939 4444 | 0 1 | (0 0) (0 0)
5615 10:54:38.102652 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 10:54:38.109691 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 10:54:38.112751 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 10:54:38.116067 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 10:54:38.122647 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 10:54:38.126267 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 10:54:38.129437 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5622 10:54:38.135488 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5623 10:54:38.138913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 10:54:38.142344 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 10:54:38.148971 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 10:54:38.152498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 10:54:38.155564 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 10:54:38.158946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 10:54:38.165061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 10:54:38.169014 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 10:54:38.171876 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:54:38.178856 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:54:38.181804 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:54:38.185418 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:54:38.191941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:54:38.195359 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:54:38.198735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5638 10:54:38.204963 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5639 10:54:38.208522 Total UI for P1: 0, mck2ui 16
5640 10:54:38.211988 best dqsien dly found for B0: ( 1, 2, 24)
5641 10:54:38.214971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 10:54:38.218545 Total UI for P1: 0, mck2ui 16
5643 10:54:38.221859 best dqsien dly found for B1: ( 1, 2, 26)
5644 10:54:38.225045 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5645 10:54:38.228269 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5646 10:54:38.228850
5647 10:54:38.231834 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5648 10:54:38.235123 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5649 10:54:38.238024 [Gating] SW calibration Done
5650 10:54:38.238493 ==
5651 10:54:38.241493 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 10:54:38.248205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 10:54:38.248860 ==
5654 10:54:38.249269 RX Vref Scan: 0
5655 10:54:38.249619
5656 10:54:38.251321 RX Vref 0 -> 0, step: 1
5657 10:54:38.251786
5658 10:54:38.254925 RX Delay -80 -> 252, step: 8
5659 10:54:38.257832 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5660 10:54:38.261528 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5661 10:54:38.264669 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5662 10:54:38.267697 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5663 10:54:38.274425 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5664 10:54:38.277674 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5665 10:54:38.281325 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5666 10:54:38.284574 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5667 10:54:38.287947 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5668 10:54:38.294427 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5669 10:54:38.297666 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5670 10:54:38.300933 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5671 10:54:38.304287 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5672 10:54:38.307851 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5673 10:54:38.314089 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5674 10:54:38.317667 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5675 10:54:38.318133 ==
5676 10:54:38.321224 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 10:54:38.323860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 10:54:38.324389 ==
5679 10:54:38.324788 DQS Delay:
5680 10:54:38.327168 DQS0 = 0, DQS1 = 0
5681 10:54:38.327629 DQM Delay:
5682 10:54:38.330777 DQM0 = 102, DQM1 = 96
5683 10:54:38.331241 DQ Delay:
5684 10:54:38.334015 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5685 10:54:38.337192 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5686 10:54:38.341197 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5687 10:54:38.344090 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =99
5688 10:54:38.344654
5689 10:54:38.345060
5690 10:54:38.347257 ==
5691 10:54:38.350461 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 10:54:38.354247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 10:54:38.354773 ==
5694 10:54:38.355117
5695 10:54:38.355429
5696 10:54:38.356946 TX Vref Scan disable
5697 10:54:38.357372 == TX Byte 0 ==
5698 10:54:38.363282 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5699 10:54:38.366732 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5700 10:54:38.367174 == TX Byte 1 ==
5701 10:54:38.373706 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5702 10:54:38.376891 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5703 10:54:38.377372 ==
5704 10:54:38.380087 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 10:54:38.383912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 10:54:38.384502 ==
5707 10:54:38.384926
5708 10:54:38.385280
5709 10:54:38.386601 TX Vref Scan disable
5710 10:54:38.390050 == TX Byte 0 ==
5711 10:54:38.393662 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 10:54:38.396762 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 10:54:38.400456 == TX Byte 1 ==
5714 10:54:38.403169 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5715 10:54:38.406644 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5716 10:54:38.407115
5717 10:54:38.410021 [DATLAT]
5718 10:54:38.410587 Freq=933, CH1 RK0
5719 10:54:38.410959
5720 10:54:38.413079 DATLAT Default: 0xd
5721 10:54:38.413547 0, 0xFFFF, sum = 0
5722 10:54:38.416972 1, 0xFFFF, sum = 0
5723 10:54:38.417542 2, 0xFFFF, sum = 0
5724 10:54:38.419993 3, 0xFFFF, sum = 0
5725 10:54:38.420570 4, 0xFFFF, sum = 0
5726 10:54:38.423106 5, 0xFFFF, sum = 0
5727 10:54:38.423699 6, 0xFFFF, sum = 0
5728 10:54:38.426803 7, 0xFFFF, sum = 0
5729 10:54:38.427380 8, 0xFFFF, sum = 0
5730 10:54:38.429745 9, 0xFFFF, sum = 0
5731 10:54:38.430221 10, 0x0, sum = 1
5732 10:54:38.433076 11, 0x0, sum = 2
5733 10:54:38.433549 12, 0x0, sum = 3
5734 10:54:38.436233 13, 0x0, sum = 4
5735 10:54:38.436661 best_step = 11
5736 10:54:38.437023
5737 10:54:38.437334 ==
5738 10:54:38.439479 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 10:54:38.446660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 10:54:38.447196 ==
5741 10:54:38.447538 RX Vref Scan: 1
5742 10:54:38.447852
5743 10:54:38.449345 RX Vref 0 -> 0, step: 1
5744 10:54:38.449767
5745 10:54:38.453076 RX Delay -53 -> 252, step: 4
5746 10:54:38.453613
5747 10:54:38.456525 Set Vref, RX VrefLevel [Byte0]: 51
5748 10:54:38.459319 [Byte1]: 53
5749 10:54:38.459812
5750 10:54:38.462430 Final RX Vref Byte 0 = 51 to rank0
5751 10:54:38.465957 Final RX Vref Byte 1 = 53 to rank0
5752 10:54:38.469187 Final RX Vref Byte 0 = 51 to rank1
5753 10:54:38.472568 Final RX Vref Byte 1 = 53 to rank1==
5754 10:54:38.475961 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 10:54:38.478922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 10:54:38.479348 ==
5757 10:54:38.482439 DQS Delay:
5758 10:54:38.482862 DQS0 = 0, DQS1 = 0
5759 10:54:38.485923 DQM Delay:
5760 10:54:38.486453 DQM0 = 104, DQM1 = 98
5761 10:54:38.486795 DQ Delay:
5762 10:54:38.489321 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5763 10:54:38.492671 DQ4 =104, DQ5 =112, DQ6 =116, DQ7 =100
5764 10:54:38.495729 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =92
5765 10:54:38.502413 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =102
5766 10:54:38.502939
5767 10:54:38.503278
5768 10:54:38.509342 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5769 10:54:38.512203 CH1 RK0: MR19=505, MR18=172F
5770 10:54:38.519316 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5771 10:54:38.519843
5772 10:54:38.522350 ----->DramcWriteLeveling(PI) begin...
5773 10:54:38.522914 ==
5774 10:54:38.526090 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 10:54:38.528873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 10:54:38.529316 ==
5777 10:54:38.532252 Write leveling (Byte 0): 29 => 29
5778 10:54:38.536055 Write leveling (Byte 1): 29 => 29
5779 10:54:38.539198 DramcWriteLeveling(PI) end<-----
5780 10:54:38.539720
5781 10:54:38.540060 ==
5782 10:54:38.542608 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 10:54:38.545448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 10:54:38.545878 ==
5785 10:54:38.549018 [Gating] SW mode calibration
5786 10:54:38.555577 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 10:54:38.562064 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 10:54:38.565088 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5789 10:54:38.572034 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 10:54:38.575070 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 10:54:38.578468 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 10:54:38.585071 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 10:54:38.588470 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 10:54:38.591606 0 14 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
5795 10:54:38.598355 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 0)
5796 10:54:38.602025 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5797 10:54:38.604884 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 10:54:38.611915 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 10:54:38.614717 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 10:54:38.618454 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 10:54:38.624683 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 10:54:38.628156 0 15 24 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
5803 10:54:38.631160 0 15 28 | B1->B0 | 4141 3737 | 0 0 | (0 0) (0 0)
5804 10:54:38.638204 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 10:54:38.641443 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 10:54:38.644925 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 10:54:38.651383 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 10:54:38.654553 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 10:54:38.658410 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 10:54:38.661389 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5811 10:54:38.667986 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5812 10:54:38.671244 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 10:54:38.678012 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 10:54:38.680912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 10:54:38.684614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 10:54:38.690749 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 10:54:38.694468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 10:54:38.697208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 10:54:38.704279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:54:38.707562 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:54:38.710615 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:54:38.717366 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:54:38.720601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:54:38.723842 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 10:54:38.730286 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 10:54:38.734257 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5827 10:54:38.736851 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5828 10:54:38.740535 Total UI for P1: 0, mck2ui 16
5829 10:54:38.743915 best dqsien dly found for B1: ( 1, 2, 24)
5830 10:54:38.746968 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 10:54:38.750398 Total UI for P1: 0, mck2ui 16
5832 10:54:38.753630 best dqsien dly found for B0: ( 1, 2, 28)
5833 10:54:38.756908 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5834 10:54:38.763378 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5835 10:54:38.763948
5836 10:54:38.766453 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5837 10:54:38.770294 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5838 10:54:38.773290 [Gating] SW calibration Done
5839 10:54:38.773783 ==
5840 10:54:38.776528 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 10:54:38.780018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 10:54:38.780491 ==
5843 10:54:38.783290 RX Vref Scan: 0
5844 10:54:38.783860
5845 10:54:38.784235 RX Vref 0 -> 0, step: 1
5846 10:54:38.784591
5847 10:54:38.786426 RX Delay -80 -> 252, step: 8
5848 10:54:38.789799 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5849 10:54:38.796999 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5850 10:54:38.799771 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5851 10:54:38.803285 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5852 10:54:38.806243 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5853 10:54:38.809903 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5854 10:54:38.812997 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5855 10:54:38.819928 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5856 10:54:38.823077 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5857 10:54:38.825762 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5858 10:54:38.829687 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5859 10:54:38.832983 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5860 10:54:38.839307 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5861 10:54:38.842626 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5862 10:54:38.846153 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5863 10:54:38.849307 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5864 10:54:38.849880 ==
5865 10:54:38.853013 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 10:54:38.859304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 10:54:38.859830 ==
5868 10:54:38.860219 DQS Delay:
5869 10:54:38.860569 DQS0 = 0, DQS1 = 0
5870 10:54:38.862608 DQM Delay:
5871 10:54:38.863077 DQM0 = 102, DQM1 = 95
5872 10:54:38.865896 DQ Delay:
5873 10:54:38.869120 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5874 10:54:38.872524 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5875 10:54:38.875984 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5876 10:54:38.878847 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5877 10:54:38.879445
5878 10:54:38.879821
5879 10:54:38.880161 ==
5880 10:54:38.882268 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 10:54:38.885256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 10:54:38.885683 ==
5883 10:54:38.886022
5884 10:54:38.886330
5885 10:54:38.888455 TX Vref Scan disable
5886 10:54:38.892261 == TX Byte 0 ==
5887 10:54:38.895672 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5888 10:54:38.898394 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5889 10:54:38.901875 == TX Byte 1 ==
5890 10:54:38.905384 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5891 10:54:38.908296 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5892 10:54:38.908854 ==
5893 10:54:38.911563 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 10:54:38.918247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 10:54:38.918780 ==
5896 10:54:38.919121
5897 10:54:38.919434
5898 10:54:38.919730 TX Vref Scan disable
5899 10:54:38.922741 == TX Byte 0 ==
5900 10:54:38.925593 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5901 10:54:38.932668 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5902 10:54:38.933225 == TX Byte 1 ==
5903 10:54:38.935865 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5904 10:54:38.942507 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5905 10:54:38.943072
5906 10:54:38.943434 [DATLAT]
5907 10:54:38.943759 Freq=933, CH1 RK1
5908 10:54:38.944070
5909 10:54:38.945853 DATLAT Default: 0xb
5910 10:54:38.946371 0, 0xFFFF, sum = 0
5911 10:54:38.949149 1, 0xFFFF, sum = 0
5912 10:54:38.952297 2, 0xFFFF, sum = 0
5913 10:54:38.952870 3, 0xFFFF, sum = 0
5914 10:54:38.955635 4, 0xFFFF, sum = 0
5915 10:54:38.956172 5, 0xFFFF, sum = 0
5916 10:54:38.959123 6, 0xFFFF, sum = 0
5917 10:54:38.959667 7, 0xFFFF, sum = 0
5918 10:54:38.962111 8, 0xFFFF, sum = 0
5919 10:54:38.962648 9, 0xFFFF, sum = 0
5920 10:54:38.965139 10, 0x0, sum = 1
5921 10:54:38.965568 11, 0x0, sum = 2
5922 10:54:38.968452 12, 0x0, sum = 3
5923 10:54:38.968919 13, 0x0, sum = 4
5924 10:54:38.971683 best_step = 11
5925 10:54:38.972101
5926 10:54:38.972434 ==
5927 10:54:38.974969 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 10:54:38.978617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 10:54:38.979155 ==
5930 10:54:38.979500 RX Vref Scan: 0
5931 10:54:38.981685
5932 10:54:38.982196 RX Vref 0 -> 0, step: 1
5933 10:54:38.982540
5934 10:54:38.984740 RX Delay -53 -> 252, step: 4
5935 10:54:38.991508 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5936 10:54:38.994816 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5937 10:54:38.998562 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5938 10:54:39.001443 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5939 10:54:39.004516 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5940 10:54:39.011467 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5941 10:54:39.014759 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5942 10:54:39.018289 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5943 10:54:39.021408 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5944 10:54:39.024942 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5945 10:54:39.031501 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5946 10:54:39.034660 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5947 10:54:39.037461 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5948 10:54:39.041316 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5949 10:54:39.044443 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5950 10:54:39.050921 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5951 10:54:39.051436 ==
5952 10:54:39.054674 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 10:54:39.057651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 10:54:39.058186 ==
5955 10:54:39.058532 DQS Delay:
5956 10:54:39.061130 DQS0 = 0, DQS1 = 0
5957 10:54:39.061658 DQM Delay:
5958 10:54:39.064292 DQM0 = 105, DQM1 = 97
5959 10:54:39.064853 DQ Delay:
5960 10:54:39.067385 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =104
5961 10:54:39.071014 DQ4 =104, DQ5 =116, DQ6 =112, DQ7 =104
5962 10:54:39.074104 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5963 10:54:39.077357 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5964 10:54:39.077781
5965 10:54:39.078118
5966 10:54:39.087580 [DQSOSCAuto] RK1, (LSB)MR18= 0x1df9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 412 ps
5967 10:54:39.090581 CH1 RK1: MR19=504, MR18=1DF9
5968 10:54:39.093746 CH1_RK1: MR19=0x504, MR18=0x1DF9, DQSOSC=412, MR23=63, INC=63, DEC=42
5969 10:54:39.097648 [RxdqsGatingPostProcess] freq 933
5970 10:54:39.104073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 10:54:39.107423 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 10:54:39.110745 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 10:54:39.113959 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 10:54:39.117623 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 10:54:39.120672 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 10:54:39.124465 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 10:54:39.127339 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 10:54:39.130854 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 10:54:39.133722 Pre-setting of DQS Precalculation
5980 10:54:39.137684 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 10:54:39.144100 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 10:54:39.150566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 10:54:39.151320
5984 10:54:39.153542
5985 10:54:39.153961 [Calibration Summary] 1866 Mbps
5986 10:54:39.157426 CH 0, Rank 0
5987 10:54:39.157955 SW Impedance : PASS
5988 10:54:39.160341 DUTY Scan : NO K
5989 10:54:39.163859 ZQ Calibration : PASS
5990 10:54:39.164433 Jitter Meter : NO K
5991 10:54:39.167104 CBT Training : PASS
5992 10:54:39.170064 Write leveling : PASS
5993 10:54:39.170500 RX DQS gating : PASS
5994 10:54:39.173296 RX DQ/DQS(RDDQC) : PASS
5995 10:54:39.177200 TX DQ/DQS : PASS
5996 10:54:39.177739 RX DATLAT : PASS
5997 10:54:39.180159 RX DQ/DQS(Engine): PASS
5998 10:54:39.183403 TX OE : NO K
5999 10:54:39.183942 All Pass.
6000 10:54:39.184283
6001 10:54:39.184596 CH 0, Rank 1
6002 10:54:39.186767 SW Impedance : PASS
6003 10:54:39.189921 DUTY Scan : NO K
6004 10:54:39.190450 ZQ Calibration : PASS
6005 10:54:39.193054 Jitter Meter : NO K
6006 10:54:39.196864 CBT Training : PASS
6007 10:54:39.197389 Write leveling : PASS
6008 10:54:39.200046 RX DQS gating : PASS
6009 10:54:39.200580 RX DQ/DQS(RDDQC) : PASS
6010 10:54:39.203577 TX DQ/DQS : PASS
6011 10:54:39.206466 RX DATLAT : PASS
6012 10:54:39.206887 RX DQ/DQS(Engine): PASS
6013 10:54:39.209686 TX OE : NO K
6014 10:54:39.210111 All Pass.
6015 10:54:39.210445
6016 10:54:39.213438 CH 1, Rank 0
6017 10:54:39.214010 SW Impedance : PASS
6018 10:54:39.216165 DUTY Scan : NO K
6019 10:54:39.219863 ZQ Calibration : PASS
6020 10:54:39.220388 Jitter Meter : NO K
6021 10:54:39.223076 CBT Training : PASS
6022 10:54:39.226274 Write leveling : PASS
6023 10:54:39.226798 RX DQS gating : PASS
6024 10:54:39.229664 RX DQ/DQS(RDDQC) : PASS
6025 10:54:39.233178 TX DQ/DQS : PASS
6026 10:54:39.233710 RX DATLAT : PASS
6027 10:54:39.236290 RX DQ/DQS(Engine): PASS
6028 10:54:39.239657 TX OE : NO K
6029 10:54:39.240185 All Pass.
6030 10:54:39.240525
6031 10:54:39.240870 CH 1, Rank 1
6032 10:54:39.242915 SW Impedance : PASS
6033 10:54:39.246151 DUTY Scan : NO K
6034 10:54:39.246764 ZQ Calibration : PASS
6035 10:54:39.249016 Jitter Meter : NO K
6036 10:54:39.252637 CBT Training : PASS
6037 10:54:39.253101 Write leveling : PASS
6038 10:54:39.255722 RX DQS gating : PASS
6039 10:54:39.259252 RX DQ/DQS(RDDQC) : PASS
6040 10:54:39.259673 TX DQ/DQS : PASS
6041 10:54:39.262667 RX DATLAT : PASS
6042 10:54:39.263087 RX DQ/DQS(Engine): PASS
6043 10:54:39.265848 TX OE : NO K
6044 10:54:39.266269 All Pass.
6045 10:54:39.266606
6046 10:54:39.269357 DramC Write-DBI off
6047 10:54:39.272380 PER_BANK_REFRESH: Hybrid Mode
6048 10:54:39.272818 TX_TRACKING: ON
6049 10:54:39.283190 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 10:54:39.285563 [FAST_K] Save calibration result to emmc
6051 10:54:39.289445 dramc_set_vcore_voltage set vcore to 650000
6052 10:54:39.292947 Read voltage for 400, 6
6053 10:54:39.293472 Vio18 = 0
6054 10:54:39.295945 Vcore = 650000
6055 10:54:39.296472 Vdram = 0
6056 10:54:39.296866 Vddq = 0
6057 10:54:39.297194 Vmddr = 0
6058 10:54:39.302777 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 10:54:39.308953 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 10:54:39.309379 MEM_TYPE=3, freq_sel=20
6061 10:54:39.312510 sv_algorithm_assistance_LP4_800
6062 10:54:39.315489 ============ PULL DRAM RESETB DOWN ============
6063 10:54:39.321727 ========== PULL DRAM RESETB DOWN end =========
6064 10:54:39.325579 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 10:54:39.328925 ===================================
6066 10:54:39.332119 LPDDR4 DRAM CONFIGURATION
6067 10:54:39.335204 ===================================
6068 10:54:39.335732 EX_ROW_EN[0] = 0x0
6069 10:54:39.338437 EX_ROW_EN[1] = 0x0
6070 10:54:39.341930 LP4Y_EN = 0x0
6071 10:54:39.342472 WORK_FSP = 0x0
6072 10:54:39.344815 WL = 0x2
6073 10:54:39.345240 RL = 0x2
6074 10:54:39.348969 BL = 0x2
6075 10:54:39.349510 RPST = 0x0
6076 10:54:39.351885 RD_PRE = 0x0
6077 10:54:39.352320 WR_PRE = 0x1
6078 10:54:39.354741 WR_PST = 0x0
6079 10:54:39.355167 DBI_WR = 0x0
6080 10:54:39.358320 DBI_RD = 0x0
6081 10:54:39.358843 OTF = 0x1
6082 10:54:39.361466 ===================================
6083 10:54:39.364851 ===================================
6084 10:54:39.367976 ANA top config
6085 10:54:39.371415 ===================================
6086 10:54:39.371899 DLL_ASYNC_EN = 0
6087 10:54:39.375040 ALL_SLAVE_EN = 1
6088 10:54:39.378060 NEW_RANK_MODE = 1
6089 10:54:39.381329 DLL_IDLE_MODE = 1
6090 10:54:39.384430 LP45_APHY_COMB_EN = 1
6091 10:54:39.384873 TX_ODT_DIS = 1
6092 10:54:39.388051 NEW_8X_MODE = 1
6093 10:54:39.391393 ===================================
6094 10:54:39.394736 ===================================
6095 10:54:39.397638 data_rate = 800
6096 10:54:39.401244 CKR = 1
6097 10:54:39.404915 DQ_P2S_RATIO = 4
6098 10:54:39.407521 ===================================
6099 10:54:39.411414 CA_P2S_RATIO = 4
6100 10:54:39.411991 DQ_CA_OPEN = 0
6101 10:54:39.414334 DQ_SEMI_OPEN = 1
6102 10:54:39.417651 CA_SEMI_OPEN = 1
6103 10:54:39.420830 CA_FULL_RATE = 0
6104 10:54:39.424725 DQ_CKDIV4_EN = 0
6105 10:54:39.427882 CA_CKDIV4_EN = 1
6106 10:54:39.428410 CA_PREDIV_EN = 0
6107 10:54:39.431129 PH8_DLY = 0
6108 10:54:39.434661 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 10:54:39.437654 DQ_AAMCK_DIV = 0
6110 10:54:39.441026 CA_AAMCK_DIV = 0
6111 10:54:39.444309 CA_ADMCK_DIV = 4
6112 10:54:39.444869 DQ_TRACK_CA_EN = 0
6113 10:54:39.447841 CA_PICK = 800
6114 10:54:39.451259 CA_MCKIO = 400
6115 10:54:39.454580 MCKIO_SEMI = 400
6116 10:54:39.457377 PLL_FREQ = 3016
6117 10:54:39.461103 DQ_UI_PI_RATIO = 32
6118 10:54:39.464109 CA_UI_PI_RATIO = 32
6119 10:54:39.467313 ===================================
6120 10:54:39.470358 ===================================
6121 10:54:39.470783 memory_type:LPDDR4
6122 10:54:39.473632 GP_NUM : 10
6123 10:54:39.477087 SRAM_EN : 1
6124 10:54:39.477536 MD32_EN : 0
6125 10:54:39.480337 ===================================
6126 10:54:39.483827 [ANA_INIT] >>>>>>>>>>>>>>
6127 10:54:39.487611 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 10:54:39.490381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 10:54:39.493924 ===================================
6130 10:54:39.497261 data_rate = 800,PCW = 0X7400
6131 10:54:39.500200 ===================================
6132 10:54:39.503699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 10:54:39.506676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 10:54:39.520350 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 10:54:39.523852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 10:54:39.526563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 10:54:39.530061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 10:54:39.533365 [ANA_INIT] flow start
6139 10:54:39.537253 [ANA_INIT] PLL >>>>>>>>
6140 10:54:39.537779 [ANA_INIT] PLL <<<<<<<<
6141 10:54:39.539644 [ANA_INIT] MIDPI >>>>>>>>
6142 10:54:39.542959 [ANA_INIT] MIDPI <<<<<<<<
6143 10:54:39.543485 [ANA_INIT] DLL >>>>>>>>
6144 10:54:39.546507 [ANA_INIT] flow end
6145 10:54:39.549708 ============ LP4 DIFF to SE enter ============
6146 10:54:39.556500 ============ LP4 DIFF to SE exit ============
6147 10:54:39.557067 [ANA_INIT] <<<<<<<<<<<<<
6148 10:54:39.560023 [Flow] Enable top DCM control >>>>>
6149 10:54:39.562910 [Flow] Enable top DCM control <<<<<
6150 10:54:39.566382 Enable DLL master slave shuffle
6151 10:54:39.572626 ==============================================================
6152 10:54:39.573268 Gating Mode config
6153 10:54:39.579357 ==============================================================
6154 10:54:39.582690 Config description:
6155 10:54:39.589590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 10:54:39.596147 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 10:54:39.602947 SELPH_MODE 0: By rank 1: By Phase
6158 10:54:39.609241 ==============================================================
6159 10:54:39.612718 GAT_TRACK_EN = 0
6160 10:54:39.613276 RX_GATING_MODE = 2
6161 10:54:39.616265 RX_GATING_TRACK_MODE = 2
6162 10:54:39.619350 SELPH_MODE = 1
6163 10:54:39.622952 PICG_EARLY_EN = 1
6164 10:54:39.625796 VALID_LAT_VALUE = 1
6165 10:54:39.632881 ==============================================================
6166 10:54:39.635869 Enter into Gating configuration >>>>
6167 10:54:39.639012 Exit from Gating configuration <<<<
6168 10:54:39.642575 Enter into DVFS_PRE_config >>>>>
6169 10:54:39.652209 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 10:54:39.655831 Exit from DVFS_PRE_config <<<<<
6171 10:54:39.659503 Enter into PICG configuration >>>>
6172 10:54:39.662523 Exit from PICG configuration <<<<
6173 10:54:39.665395 [RX_INPUT] configuration >>>>>
6174 10:54:39.669278 [RX_INPUT] configuration <<<<<
6175 10:54:39.671993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 10:54:39.678765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 10:54:39.685307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 10:54:39.688896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 10:54:39.695040 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 10:54:39.701998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 10:54:39.705653 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 10:54:39.711837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 10:54:39.715294 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 10:54:39.718961 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 10:54:39.722048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 10:54:39.728544 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 10:54:39.731954 ===================================
6188 10:54:39.732477 LPDDR4 DRAM CONFIGURATION
6189 10:54:39.734797 ===================================
6190 10:54:39.738636 EX_ROW_EN[0] = 0x0
6191 10:54:39.741570 EX_ROW_EN[1] = 0x0
6192 10:54:39.742000 LP4Y_EN = 0x0
6193 10:54:39.745004 WORK_FSP = 0x0
6194 10:54:39.745523 WL = 0x2
6195 10:54:39.748691 RL = 0x2
6196 10:54:39.749248 BL = 0x2
6197 10:54:39.751784 RPST = 0x0
6198 10:54:39.752307 RD_PRE = 0x0
6199 10:54:39.754950 WR_PRE = 0x1
6200 10:54:39.755473 WR_PST = 0x0
6201 10:54:39.758016 DBI_WR = 0x0
6202 10:54:39.758438 DBI_RD = 0x0
6203 10:54:39.761630 OTF = 0x1
6204 10:54:39.764687 ===================================
6205 10:54:39.767974 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 10:54:39.771249 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 10:54:39.778143 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 10:54:39.781001 ===================================
6209 10:54:39.781461 LPDDR4 DRAM CONFIGURATION
6210 10:54:39.784651 ===================================
6211 10:54:39.787746 EX_ROW_EN[0] = 0x10
6212 10:54:39.791649 EX_ROW_EN[1] = 0x0
6213 10:54:39.792172 LP4Y_EN = 0x0
6214 10:54:39.794662 WORK_FSP = 0x0
6215 10:54:39.795085 WL = 0x2
6216 10:54:39.797535 RL = 0x2
6217 10:54:39.797960 BL = 0x2
6218 10:54:39.801109 RPST = 0x0
6219 10:54:39.801653 RD_PRE = 0x0
6220 10:54:39.804156 WR_PRE = 0x1
6221 10:54:39.804680 WR_PST = 0x0
6222 10:54:39.807911 DBI_WR = 0x0
6223 10:54:39.808329 DBI_RD = 0x0
6224 10:54:39.811456 OTF = 0x1
6225 10:54:39.814076 ===================================
6226 10:54:39.820981 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 10:54:39.824611 nWR fixed to 30
6228 10:54:39.827382 [ModeRegInit_LP4] CH0 RK0
6229 10:54:39.827804 [ModeRegInit_LP4] CH0 RK1
6230 10:54:39.830973 [ModeRegInit_LP4] CH1 RK0
6231 10:54:39.834581 [ModeRegInit_LP4] CH1 RK1
6232 10:54:39.835100 match AC timing 19
6233 10:54:39.840982 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 10:54:39.844356 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 10:54:39.847416 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 10:54:39.854271 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 10:54:39.857389 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 10:54:39.857911 ==
6239 10:54:39.860734 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 10:54:39.864489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 10:54:39.865059 ==
6242 10:54:39.870333 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 10:54:39.876924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 10:54:39.880213 [CA 0] Center 36 (8~64) winsize 57
6245 10:54:39.884083 [CA 1] Center 36 (8~64) winsize 57
6246 10:54:39.887444 [CA 2] Center 36 (8~64) winsize 57
6247 10:54:39.888023 [CA 3] Center 36 (8~64) winsize 57
6248 10:54:39.890148 [CA 4] Center 36 (8~64) winsize 57
6249 10:54:39.893479 [CA 5] Center 36 (8~64) winsize 57
6250 10:54:39.894083
6251 10:54:39.900704 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 10:54:39.901253
6253 10:54:39.903351 [CATrainingPosCal] consider 1 rank data
6254 10:54:39.906834 u2DelayCellTimex100 = 270/100 ps
6255 10:54:39.910161 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 10:54:39.913518 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 10:54:39.916663 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 10:54:39.920430 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 10:54:39.923540 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 10:54:39.926538 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 10:54:39.926965
6262 10:54:39.930119 CA PerBit enable=1, Macro0, CA PI delay=36
6263 10:54:39.930651
6264 10:54:39.933312 [CBTSetCACLKResult] CA Dly = 36
6265 10:54:39.936938 CS Dly: 1 (0~32)
6266 10:54:39.937460 ==
6267 10:54:39.940012 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 10:54:39.943129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 10:54:39.943556 ==
6270 10:54:39.949765 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 10:54:39.956417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6272 10:54:39.960201 [CA 0] Center 36 (8~64) winsize 57
6273 10:54:39.960735 [CA 1] Center 36 (8~64) winsize 57
6274 10:54:39.963239 [CA 2] Center 36 (8~64) winsize 57
6275 10:54:39.966320 [CA 3] Center 36 (8~64) winsize 57
6276 10:54:39.969424 [CA 4] Center 36 (8~64) winsize 57
6277 10:54:39.972753 [CA 5] Center 36 (8~64) winsize 57
6278 10:54:39.973207
6279 10:54:39.975883 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6280 10:54:39.976307
6281 10:54:39.983148 [CATrainingPosCal] consider 2 rank data
6282 10:54:39.983677 u2DelayCellTimex100 = 270/100 ps
6283 10:54:39.989564 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 10:54:39.992832 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 10:54:39.995951 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 10:54:39.999115 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 10:54:40.002342 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 10:54:40.005958 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 10:54:40.006634
6290 10:54:40.008826 CA PerBit enable=1, Macro0, CA PI delay=36
6291 10:54:40.009333
6292 10:54:40.012841 [CBTSetCACLKResult] CA Dly = 36
6293 10:54:40.015507 CS Dly: 1 (0~32)
6294 10:54:40.015937
6295 10:54:40.018690 ----->DramcWriteLeveling(PI) begin...
6296 10:54:40.019121 ==
6297 10:54:40.022325 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 10:54:40.025090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 10:54:40.025519 ==
6300 10:54:40.028722 Write leveling (Byte 0): 40 => 8
6301 10:54:40.032412 Write leveling (Byte 1): 32 => 0
6302 10:54:40.035338 DramcWriteLeveling(PI) end<-----
6303 10:54:40.035875
6304 10:54:40.036222 ==
6305 10:54:40.038643 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 10:54:40.042127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 10:54:40.042656 ==
6308 10:54:40.044988 [Gating] SW mode calibration
6309 10:54:40.051650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 10:54:40.058665 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 10:54:40.061589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 10:54:40.065027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 10:54:40.071817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 10:54:40.074580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 10:54:40.077848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 10:54:40.084514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 10:54:40.088227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 10:54:40.091633 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 10:54:40.098107 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 10:54:40.101071 Total UI for P1: 0, mck2ui 16
6321 10:54:40.104514 best dqsien dly found for B0: ( 0, 14, 24)
6322 10:54:40.107706 Total UI for P1: 0, mck2ui 16
6323 10:54:40.111410 best dqsien dly found for B1: ( 0, 14, 24)
6324 10:54:40.114968 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 10:54:40.117700 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 10:54:40.118124
6327 10:54:40.121226 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 10:54:40.124444 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 10:54:40.127840 [Gating] SW calibration Done
6330 10:54:40.128253 ==
6331 10:54:40.131463 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 10:54:40.134606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 10:54:40.135049 ==
6334 10:54:40.137889 RX Vref Scan: 0
6335 10:54:40.138425
6336 10:54:40.140989 RX Vref 0 -> 0, step: 1
6337 10:54:40.141406
6338 10:54:40.141737 RX Delay -410 -> 252, step: 16
6339 10:54:40.147560 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6340 10:54:40.151348 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6341 10:54:40.154236 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6342 10:54:40.161200 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6343 10:54:40.164313 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6344 10:54:40.167712 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6345 10:54:40.171355 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6346 10:54:40.174379 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6347 10:54:40.180432 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6348 10:54:40.183742 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6349 10:54:40.187886 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6350 10:54:40.193919 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6351 10:54:40.197249 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6352 10:54:40.200913 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6353 10:54:40.203755 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6354 10:54:40.210080 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6355 10:54:40.210541 ==
6356 10:54:40.213418 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 10:54:40.217016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 10:54:40.217444 ==
6359 10:54:40.217831 DQS Delay:
6360 10:54:40.220117 DQS0 = 19, DQS1 = 43
6361 10:54:40.220590 DQM Delay:
6362 10:54:40.223411 DQM0 = 6, DQM1 = 14
6363 10:54:40.223928 DQ Delay:
6364 10:54:40.226890 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6365 10:54:40.229976 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6366 10:54:40.233823 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6367 10:54:40.236805 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6368 10:54:40.237233
6369 10:54:40.237670
6370 10:54:40.238010 ==
6371 10:54:40.240195 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 10:54:40.243706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 10:54:40.244140 ==
6374 10:54:40.244473
6375 10:54:40.244969
6376 10:54:40.246978 TX Vref Scan disable
6377 10:54:40.250160 == TX Byte 0 ==
6378 10:54:40.253357 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 10:54:40.256960 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 10:54:40.257479 == TX Byte 1 ==
6381 10:54:40.263365 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 10:54:40.266965 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 10:54:40.267492 ==
6384 10:54:40.270154 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 10:54:40.273172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 10:54:40.273766 ==
6387 10:54:40.274184
6388 10:54:40.276626
6389 10:54:40.277075 TX Vref Scan disable
6390 10:54:40.279860 == TX Byte 0 ==
6391 10:54:40.283625 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 10:54:40.286438 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 10:54:40.290217 == TX Byte 1 ==
6394 10:54:40.292911 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 10:54:40.296486 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 10:54:40.296941
6397 10:54:40.299974 [DATLAT]
6398 10:54:40.300498 Freq=400, CH0 RK0
6399 10:54:40.300991
6400 10:54:40.302968 DATLAT Default: 0xf
6401 10:54:40.303394 0, 0xFFFF, sum = 0
6402 10:54:40.306283 1, 0xFFFF, sum = 0
6403 10:54:40.306718 2, 0xFFFF, sum = 0
6404 10:54:40.309316 3, 0xFFFF, sum = 0
6405 10:54:40.309753 4, 0xFFFF, sum = 0
6406 10:54:40.312942 5, 0xFFFF, sum = 0
6407 10:54:40.313376 6, 0xFFFF, sum = 0
6408 10:54:40.316176 7, 0xFFFF, sum = 0
6409 10:54:40.316600 8, 0xFFFF, sum = 0
6410 10:54:40.319555 9, 0xFFFF, sum = 0
6411 10:54:40.319991 10, 0xFFFF, sum = 0
6412 10:54:40.322645 11, 0xFFFF, sum = 0
6413 10:54:40.323073 12, 0xFFFF, sum = 0
6414 10:54:40.325841 13, 0x0, sum = 1
6415 10:54:40.326317 14, 0x0, sum = 2
6416 10:54:40.329379 15, 0x0, sum = 3
6417 10:54:40.329806 16, 0x0, sum = 4
6418 10:54:40.332990 best_step = 14
6419 10:54:40.333560
6420 10:54:40.334049 ==
6421 10:54:40.335850 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 10:54:40.339576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:54:40.340252 ==
6424 10:54:40.342338 RX Vref Scan: 1
6425 10:54:40.342761
6426 10:54:40.343100 RX Vref 0 -> 0, step: 1
6427 10:54:40.343418
6428 10:54:40.346195 RX Delay -327 -> 252, step: 8
6429 10:54:40.346731
6430 10:54:40.349093 Set Vref, RX VrefLevel [Byte0]: 60
6431 10:54:40.352341 [Byte1]: 49
6432 10:54:40.357130
6433 10:54:40.357556 Final RX Vref Byte 0 = 60 to rank0
6434 10:54:40.361072 Final RX Vref Byte 1 = 49 to rank0
6435 10:54:40.364152 Final RX Vref Byte 0 = 60 to rank1
6436 10:54:40.367272 Final RX Vref Byte 1 = 49 to rank1==
6437 10:54:40.370546 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 10:54:40.376758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 10:54:40.377237 ==
6440 10:54:40.377577 DQS Delay:
6441 10:54:40.380318 DQS0 = 28, DQS1 = 48
6442 10:54:40.380883 DQM Delay:
6443 10:54:40.381251 DQM0 = 12, DQM1 = 14
6444 10:54:40.383957 DQ Delay:
6445 10:54:40.387106 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6446 10:54:40.390492 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6447 10:54:40.391016 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6448 10:54:40.396959 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6449 10:54:40.397384
6450 10:54:40.397722
6451 10:54:40.403783 [DQSOSCAuto] RK0, (LSB)MR18= 0xada5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6452 10:54:40.406861 CH0 RK0: MR19=C0C, MR18=ADA5
6453 10:54:40.413396 CH0_RK0: MR19=0xC0C, MR18=0xADA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6454 10:54:40.413924 ==
6455 10:54:40.416901 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 10:54:40.420585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 10:54:40.421161 ==
6458 10:54:40.423688 [Gating] SW mode calibration
6459 10:54:40.430164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 10:54:40.436995 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 10:54:40.440351 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 10:54:40.443380 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 10:54:40.450056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 10:54:40.453171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 10:54:40.456563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 10:54:40.463450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 10:54:40.466499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 10:54:40.469678 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 10:54:40.476473 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 10:54:40.477045 Total UI for P1: 0, mck2ui 16
6471 10:54:40.480036 best dqsien dly found for B0: ( 0, 14, 24)
6472 10:54:40.483131 Total UI for P1: 0, mck2ui 16
6473 10:54:40.486222 best dqsien dly found for B1: ( 0, 14, 24)
6474 10:54:40.493101 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 10:54:40.496526 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 10:54:40.496979
6477 10:54:40.499843 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 10:54:40.502610 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 10:54:40.506474 [Gating] SW calibration Done
6480 10:54:40.506897 ==
6481 10:54:40.509688 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 10:54:40.512565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 10:54:40.513337 ==
6484 10:54:40.516086 RX Vref Scan: 0
6485 10:54:40.516611
6486 10:54:40.517002 RX Vref 0 -> 0, step: 1
6487 10:54:40.517327
6488 10:54:40.519405 RX Delay -410 -> 252, step: 16
6489 10:54:40.525879 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6490 10:54:40.529053 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6491 10:54:40.532736 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6492 10:54:40.535579 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6493 10:54:40.542605 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6494 10:54:40.545956 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6495 10:54:40.548985 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6496 10:54:40.552058 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6497 10:54:40.559071 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6498 10:54:40.562198 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6499 10:54:40.565662 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6500 10:54:40.568606 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6501 10:54:40.575533 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6502 10:54:40.578460 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6503 10:54:40.582098 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6504 10:54:40.588830 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6505 10:54:40.589255 ==
6506 10:54:40.592192 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 10:54:40.595523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 10:54:40.595952 ==
6509 10:54:40.596295 DQS Delay:
6510 10:54:40.598538 DQS0 = 27, DQS1 = 43
6511 10:54:40.598962 DQM Delay:
6512 10:54:40.601678 DQM0 = 9, DQM1 = 15
6513 10:54:40.602107 DQ Delay:
6514 10:54:40.605178 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6515 10:54:40.608292 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6516 10:54:40.611530 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6517 10:54:40.615401 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6518 10:54:40.615928
6519 10:54:40.616273
6520 10:54:40.616584 ==
6521 10:54:40.618183 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 10:54:40.621650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 10:54:40.622088 ==
6524 10:54:40.622427
6525 10:54:40.622738
6526 10:54:40.625325 TX Vref Scan disable
6527 10:54:40.625853 == TX Byte 0 ==
6528 10:54:40.631477 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6529 10:54:40.635009 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6530 10:54:40.635515 == TX Byte 1 ==
6531 10:54:40.641544 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6532 10:54:40.644963 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6533 10:54:40.645474 ==
6534 10:54:40.648084 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 10:54:40.651497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 10:54:40.652021 ==
6537 10:54:40.652368
6538 10:54:40.652680
6539 10:54:40.654893 TX Vref Scan disable
6540 10:54:40.657831 == TX Byte 0 ==
6541 10:54:40.661495 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6542 10:54:40.664358 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6543 10:54:40.668005 == TX Byte 1 ==
6544 10:54:40.671190 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6545 10:54:40.674846 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6546 10:54:40.675386
6547 10:54:40.675736 [DATLAT]
6548 10:54:40.677776 Freq=400, CH0 RK1
6549 10:54:40.678375
6550 10:54:40.678730 DATLAT Default: 0xe
6551 10:54:40.680958 0, 0xFFFF, sum = 0
6552 10:54:40.681390 1, 0xFFFF, sum = 0
6553 10:54:40.684307 2, 0xFFFF, sum = 0
6554 10:54:40.687435 3, 0xFFFF, sum = 0
6555 10:54:40.687868 4, 0xFFFF, sum = 0
6556 10:54:40.691228 5, 0xFFFF, sum = 0
6557 10:54:40.691773 6, 0xFFFF, sum = 0
6558 10:54:40.694300 7, 0xFFFF, sum = 0
6559 10:54:40.694844 8, 0xFFFF, sum = 0
6560 10:54:40.697694 9, 0xFFFF, sum = 0
6561 10:54:40.698125 10, 0xFFFF, sum = 0
6562 10:54:40.700623 11, 0xFFFF, sum = 0
6563 10:54:40.701081 12, 0xFFFF, sum = 0
6564 10:54:40.704273 13, 0x0, sum = 1
6565 10:54:40.704703 14, 0x0, sum = 2
6566 10:54:40.707344 15, 0x0, sum = 3
6567 10:54:40.707788 16, 0x0, sum = 4
6568 10:54:40.711004 best_step = 14
6569 10:54:40.711523
6570 10:54:40.711881 ==
6571 10:54:40.714159 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 10:54:40.717596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 10:54:40.718223 ==
6574 10:54:40.720792 RX Vref Scan: 0
6575 10:54:40.721239
6576 10:54:40.721577 RX Vref 0 -> 0, step: 1
6577 10:54:40.721894
6578 10:54:40.724397 RX Delay -327 -> 252, step: 8
6579 10:54:40.731585 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6580 10:54:40.734650 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6581 10:54:40.738180 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6582 10:54:40.744588 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6583 10:54:40.748191 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6584 10:54:40.751434 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6585 10:54:40.754518 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6586 10:54:40.757829 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6587 10:54:40.764458 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6588 10:54:40.767968 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6589 10:54:40.771137 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6590 10:54:40.777475 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6591 10:54:40.781038 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6592 10:54:40.784516 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6593 10:54:40.787382 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6594 10:54:40.794014 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6595 10:54:40.794437 ==
6596 10:54:40.797234 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 10:54:40.800812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 10:54:40.801237 ==
6599 10:54:40.801578 DQS Delay:
6600 10:54:40.804423 DQS0 = 28, DQS1 = 44
6601 10:54:40.804881 DQM Delay:
6602 10:54:40.807500 DQM0 = 9, DQM1 = 15
6603 10:54:40.807925 DQ Delay:
6604 10:54:40.810648 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6605 10:54:40.814038 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6606 10:54:40.817319 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6607 10:54:40.820789 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6608 10:54:40.821220
6609 10:54:40.821557
6610 10:54:40.827085 [DQSOSCAuto] RK1, (LSB)MR18= 0xb66a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6611 10:54:40.830623 CH0 RK1: MR19=C0C, MR18=B66A
6612 10:54:40.837436 CH0_RK1: MR19=0xC0C, MR18=0xB66A, DQSOSC=387, MR23=63, INC=394, DEC=262
6613 10:54:40.840705 [RxdqsGatingPostProcess] freq 400
6614 10:54:40.847033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 10:54:40.850419 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 10:54:40.853730 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 10:54:40.856833 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 10:54:40.859983 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 10:54:40.860405 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 10:54:40.863756 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 10:54:40.867063 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 10:54:40.870080 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 10:54:40.873273 Pre-setting of DQS Precalculation
6624 10:54:40.880304 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 10:54:40.880730 ==
6626 10:54:40.883517 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 10:54:40.886544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 10:54:40.887018 ==
6629 10:54:40.893237 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 10:54:40.899769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6631 10:54:40.903338 [CA 0] Center 36 (8~64) winsize 57
6632 10:54:40.903762 [CA 1] Center 36 (8~64) winsize 57
6633 10:54:40.906428 [CA 2] Center 36 (8~64) winsize 57
6634 10:54:40.910025 [CA 3] Center 36 (8~64) winsize 57
6635 10:54:40.913060 [CA 4] Center 36 (8~64) winsize 57
6636 10:54:40.916587 [CA 5] Center 36 (8~64) winsize 57
6637 10:54:40.917049
6638 10:54:40.919683 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6639 10:54:40.920106
6640 10:54:40.926194 [CATrainingPosCal] consider 1 rank data
6641 10:54:40.926615 u2DelayCellTimex100 = 270/100 ps
6642 10:54:40.933227 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 10:54:40.936436 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 10:54:40.939724 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 10:54:40.943078 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 10:54:40.946257 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 10:54:40.949655 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 10:54:40.950083
6649 10:54:40.952432 CA PerBit enable=1, Macro0, CA PI delay=36
6650 10:54:40.952516
6651 10:54:40.955898 [CBTSetCACLKResult] CA Dly = 36
6652 10:54:40.955982 CS Dly: 1 (0~32)
6653 10:54:40.959221 ==
6654 10:54:40.962332 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 10:54:40.965669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 10:54:40.965753 ==
6657 10:54:40.972530 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 10:54:40.975955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6659 10:54:40.978855 [CA 0] Center 36 (8~64) winsize 57
6660 10:54:40.982210 [CA 1] Center 36 (8~64) winsize 57
6661 10:54:40.985726 [CA 2] Center 36 (8~64) winsize 57
6662 10:54:40.988749 [CA 3] Center 36 (8~64) winsize 57
6663 10:54:40.992221 [CA 4] Center 36 (8~64) winsize 57
6664 10:54:40.995496 [CA 5] Center 36 (8~64) winsize 57
6665 10:54:40.995579
6666 10:54:40.998680 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6667 10:54:40.998764
6668 10:54:41.001858 [CATrainingPosCal] consider 2 rank data
6669 10:54:41.005375 u2DelayCellTimex100 = 270/100 ps
6670 10:54:41.008547 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 10:54:41.011660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 10:54:41.018287 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 10:54:41.021943 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 10:54:41.024984 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 10:54:41.028407 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 10:54:41.028526
6677 10:54:41.031561 CA PerBit enable=1, Macro0, CA PI delay=36
6678 10:54:41.031643
6679 10:54:41.034836 [CBTSetCACLKResult] CA Dly = 36
6680 10:54:41.034919 CS Dly: 1 (0~32)
6681 10:54:41.034984
6682 10:54:41.038375 ----->DramcWriteLeveling(PI) begin...
6683 10:54:41.041683 ==
6684 10:54:41.044771 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 10:54:41.048190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 10:54:41.048272 ==
6687 10:54:41.051313 Write leveling (Byte 0): 40 => 8
6688 10:54:41.054431 Write leveling (Byte 1): 32 => 0
6689 10:54:41.058071 DramcWriteLeveling(PI) end<-----
6690 10:54:41.058154
6691 10:54:41.058219 ==
6692 10:54:41.061350 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 10:54:41.064356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 10:54:41.064440 ==
6695 10:54:41.067723 [Gating] SW mode calibration
6696 10:54:41.074424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 10:54:41.080983 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 10:54:41.084162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 10:54:41.087506 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 10:54:41.094339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 10:54:41.097677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 10:54:41.100821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 10:54:41.107852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 10:54:41.110634 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 10:54:41.113938 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 10:54:41.120802 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 10:54:41.120886 Total UI for P1: 0, mck2ui 16
6708 10:54:41.127586 best dqsien dly found for B0: ( 0, 14, 24)
6709 10:54:41.127670 Total UI for P1: 0, mck2ui 16
6710 10:54:41.130439 best dqsien dly found for B1: ( 0, 14, 24)
6711 10:54:41.137300 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 10:54:41.140537 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 10:54:41.140620
6714 10:54:41.143777 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 10:54:41.146943 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 10:54:41.150597 [Gating] SW calibration Done
6717 10:54:41.150680 ==
6718 10:54:41.153612 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 10:54:41.156882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 10:54:41.156966 ==
6721 10:54:41.160067 RX Vref Scan: 0
6722 10:54:41.160149
6723 10:54:41.160216 RX Vref 0 -> 0, step: 1
6724 10:54:41.160278
6725 10:54:41.163559 RX Delay -410 -> 252, step: 16
6726 10:54:41.169985 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6727 10:54:41.173555 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6728 10:54:41.176697 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6729 10:54:41.179971 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6730 10:54:41.186984 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6731 10:54:41.190082 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6732 10:54:41.193308 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6733 10:54:41.196454 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6734 10:54:41.203201 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6735 10:54:41.206309 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6736 10:54:41.209891 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6737 10:54:41.213043 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6738 10:54:41.219789 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6739 10:54:41.223200 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6740 10:54:41.226119 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6741 10:54:41.233032 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6742 10:54:41.233114 ==
6743 10:54:41.236078 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 10:54:41.239416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 10:54:41.239498 ==
6746 10:54:41.239564 DQS Delay:
6747 10:54:41.242837 DQS0 = 27, DQS1 = 43
6748 10:54:41.242919 DQM Delay:
6749 10:54:41.246114 DQM0 = 7, DQM1 = 17
6750 10:54:41.246196 DQ Delay:
6751 10:54:41.249706 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6752 10:54:41.252943 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6753 10:54:41.255792 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6754 10:54:41.259104 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6755 10:54:41.259186
6756 10:54:41.259250
6757 10:54:41.259310 ==
6758 10:54:41.262711 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 10:54:41.265776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 10:54:41.265859 ==
6761 10:54:41.265924
6762 10:54:41.265984
6763 10:54:41.268996 TX Vref Scan disable
6764 10:54:41.272619 == TX Byte 0 ==
6765 10:54:41.275779 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 10:54:41.278886 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 10:54:41.282066 == TX Byte 1 ==
6768 10:54:41.285767 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6769 10:54:41.289039 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6770 10:54:41.289121 ==
6771 10:54:41.292223 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 10:54:41.295511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 10:54:41.295594 ==
6774 10:54:41.298568
6775 10:54:41.298650
6776 10:54:41.298715 TX Vref Scan disable
6777 10:54:41.302010 == TX Byte 0 ==
6778 10:54:41.305264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 10:54:41.308921 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 10:54:41.311730 == TX Byte 1 ==
6781 10:54:41.315190 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6782 10:54:41.318905 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6783 10:54:41.319004
6784 10:54:41.321731 [DATLAT]
6785 10:54:41.321813 Freq=400, CH1 RK0
6786 10:54:41.321879
6787 10:54:41.325152 DATLAT Default: 0xf
6788 10:54:41.325234 0, 0xFFFF, sum = 0
6789 10:54:41.328237 1, 0xFFFF, sum = 0
6790 10:54:41.328320 2, 0xFFFF, sum = 0
6791 10:54:41.331786 3, 0xFFFF, sum = 0
6792 10:54:41.331870 4, 0xFFFF, sum = 0
6793 10:54:41.335117 5, 0xFFFF, sum = 0
6794 10:54:41.335200 6, 0xFFFF, sum = 0
6795 10:54:41.338732 7, 0xFFFF, sum = 0
6796 10:54:41.338816 8, 0xFFFF, sum = 0
6797 10:54:41.341474 9, 0xFFFF, sum = 0
6798 10:54:41.341558 10, 0xFFFF, sum = 0
6799 10:54:41.345092 11, 0xFFFF, sum = 0
6800 10:54:41.345175 12, 0xFFFF, sum = 0
6801 10:54:41.348304 13, 0x0, sum = 1
6802 10:54:41.348387 14, 0x0, sum = 2
6803 10:54:41.351411 15, 0x0, sum = 3
6804 10:54:41.351494 16, 0x0, sum = 4
6805 10:54:41.354754 best_step = 14
6806 10:54:41.354849
6807 10:54:41.354941 ==
6808 10:54:41.357942 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 10:54:41.361443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:54:41.361525 ==
6811 10:54:41.364680 RX Vref Scan: 1
6812 10:54:41.364812
6813 10:54:41.364909 RX Vref 0 -> 0, step: 1
6814 10:54:41.364970
6815 10:54:41.368246 RX Delay -327 -> 252, step: 8
6816 10:54:41.368328
6817 10:54:41.371362 Set Vref, RX VrefLevel [Byte0]: 51
6818 10:54:41.374484 [Byte1]: 53
6819 10:54:41.379405
6820 10:54:41.379487 Final RX Vref Byte 0 = 51 to rank0
6821 10:54:41.382674 Final RX Vref Byte 1 = 53 to rank0
6822 10:54:41.386363 Final RX Vref Byte 0 = 51 to rank1
6823 10:54:41.389443 Final RX Vref Byte 1 = 53 to rank1==
6824 10:54:41.392922 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 10:54:41.399336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 10:54:41.399419 ==
6827 10:54:41.399484 DQS Delay:
6828 10:54:41.402937 DQS0 = 32, DQS1 = 40
6829 10:54:41.403019 DQM Delay:
6830 10:54:41.403085 DQM0 = 11, DQM1 = 12
6831 10:54:41.405968 DQ Delay:
6832 10:54:41.409544 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6833 10:54:41.409626 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6834 10:54:41.412711 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6835 10:54:41.416466 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6836 10:54:41.416572
6837 10:54:41.416650
6838 10:54:41.426077 [DQSOSCAuto] RK0, (LSB)MR18= 0x95d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6839 10:54:41.429233 CH1 RK0: MR19=C0C, MR18=95D0
6840 10:54:41.435960 CH1_RK0: MR19=0xC0C, MR18=0x95D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6841 10:54:41.436042 ==
6842 10:54:41.439405 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 10:54:41.442468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 10:54:41.442587 ==
6845 10:54:41.445838 [Gating] SW mode calibration
6846 10:54:41.452388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 10:54:41.459388 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 10:54:41.462335 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 10:54:41.465923 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 10:54:41.472291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 10:54:41.475381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 10:54:41.479016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 10:54:41.485389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 10:54:41.488680 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 10:54:41.491865 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 10:54:41.498542 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 10:54:41.498624 Total UI for P1: 0, mck2ui 16
6858 10:54:41.504987 best dqsien dly found for B0: ( 0, 14, 24)
6859 10:54:41.505069 Total UI for P1: 0, mck2ui 16
6860 10:54:41.508645 best dqsien dly found for B1: ( 0, 14, 24)
6861 10:54:41.515138 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 10:54:41.518288 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 10:54:41.518370
6864 10:54:41.521522 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 10:54:41.524933 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 10:54:41.528595 [Gating] SW calibration Done
6867 10:54:41.528726 ==
6868 10:54:41.531728 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 10:54:41.534797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 10:54:41.534879 ==
6871 10:54:41.538774 RX Vref Scan: 0
6872 10:54:41.538856
6873 10:54:41.538921 RX Vref 0 -> 0, step: 1
6874 10:54:41.538981
6875 10:54:41.541572 RX Delay -410 -> 252, step: 16
6876 10:54:41.548100 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6877 10:54:41.551193 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6878 10:54:41.554840 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6879 10:54:41.557888 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6880 10:54:41.564630 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6881 10:54:41.568163 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6882 10:54:41.571339 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6883 10:54:41.574618 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6884 10:54:41.581335 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6885 10:54:41.584459 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6886 10:54:41.587973 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6887 10:54:41.591215 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6888 10:54:41.597827 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6889 10:54:41.601088 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6890 10:54:41.604228 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6891 10:54:41.611059 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6892 10:54:41.611141 ==
6893 10:54:41.614200 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 10:54:41.617729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 10:54:41.617811 ==
6896 10:54:41.617877 DQS Delay:
6897 10:54:41.620706 DQS0 = 35, DQS1 = 43
6898 10:54:41.620822 DQM Delay:
6899 10:54:41.624409 DQM0 = 16, DQM1 = 19
6900 10:54:41.624491 DQ Delay:
6901 10:54:41.627286 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6902 10:54:41.630978 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6903 10:54:41.634109 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6904 10:54:41.637292 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6905 10:54:41.637402
6906 10:54:41.637467
6907 10:54:41.637527 ==
6908 10:54:41.640959 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 10:54:41.644304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 10:54:41.644412 ==
6911 10:54:41.644504
6912 10:54:41.644591
6913 10:54:41.647157 TX Vref Scan disable
6914 10:54:41.650836 == TX Byte 0 ==
6915 10:54:41.653946 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6916 10:54:41.656958 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6917 10:54:41.660739 == TX Byte 1 ==
6918 10:54:41.663664 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 10:54:41.667067 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 10:54:41.667150 ==
6921 10:54:41.670250 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 10:54:41.673713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 10:54:41.673795 ==
6924 10:54:41.677085
6925 10:54:41.677166
6926 10:54:41.677232 TX Vref Scan disable
6927 10:54:41.680217 == TX Byte 0 ==
6928 10:54:41.683351 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6929 10:54:41.686653 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6930 10:54:41.690233 == TX Byte 1 ==
6931 10:54:41.693357 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6932 10:54:41.696607 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6933 10:54:41.696716
6934 10:54:41.696851 [DATLAT]
6935 10:54:41.699755 Freq=400, CH1 RK1
6936 10:54:41.699838
6937 10:54:41.703385 DATLAT Default: 0xe
6938 10:54:41.703467 0, 0xFFFF, sum = 0
6939 10:54:41.706707 1, 0xFFFF, sum = 0
6940 10:54:41.706792 2, 0xFFFF, sum = 0
6941 10:54:41.710097 3, 0xFFFF, sum = 0
6942 10:54:41.710182 4, 0xFFFF, sum = 0
6943 10:54:41.713348 5, 0xFFFF, sum = 0
6944 10:54:41.713433 6, 0xFFFF, sum = 0
6945 10:54:41.716479 7, 0xFFFF, sum = 0
6946 10:54:41.716591 8, 0xFFFF, sum = 0
6947 10:54:41.719845 9, 0xFFFF, sum = 0
6948 10:54:41.719930 10, 0xFFFF, sum = 0
6949 10:54:41.723662 11, 0xFFFF, sum = 0
6950 10:54:41.724095 12, 0xFFFF, sum = 0
6951 10:54:41.727079 13, 0x0, sum = 1
6952 10:54:41.727511 14, 0x0, sum = 2
6953 10:54:41.730223 15, 0x0, sum = 3
6954 10:54:41.730658 16, 0x0, sum = 4
6955 10:54:41.733508 best_step = 14
6956 10:54:41.733934
6957 10:54:41.734273 ==
6958 10:54:41.737038 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 10:54:41.740155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 10:54:41.740691 ==
6961 10:54:41.743474 RX Vref Scan: 0
6962 10:54:41.744000
6963 10:54:41.744343 RX Vref 0 -> 0, step: 1
6964 10:54:41.744662
6965 10:54:41.746839 RX Delay -327 -> 252, step: 8
6966 10:54:41.754817 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6967 10:54:41.757842 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6968 10:54:41.761165 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6969 10:54:41.768146 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6970 10:54:41.771111 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6971 10:54:41.774135 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6972 10:54:41.777731 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6973 10:54:41.784076 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6974 10:54:41.787965 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6975 10:54:41.790710 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6976 10:54:41.794609 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6977 10:54:41.800791 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6978 10:54:41.804401 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6979 10:54:41.807824 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6980 10:54:41.810574 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6981 10:54:41.817670 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6982 10:54:41.818208 ==
6983 10:54:41.820511 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 10:54:41.823959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 10:54:41.824495 ==
6986 10:54:41.824870 DQS Delay:
6987 10:54:41.826958 DQS0 = 32, DQS1 = 40
6988 10:54:41.827384 DQM Delay:
6989 10:54:41.830994 DQM0 = 12, DQM1 = 15
6990 10:54:41.831528 DQ Delay:
6991 10:54:41.833932 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6992 10:54:41.837340 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
6993 10:54:41.840824 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6994 10:54:41.843774 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =28
6995 10:54:41.844305
6996 10:54:41.844651
6997 10:54:41.850595 [DQSOSCAuto] RK1, (LSB)MR18= 0xa951, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6998 10:54:41.854183 CH1 RK1: MR19=C0C, MR18=A951
6999 10:54:41.860523 CH1_RK1: MR19=0xC0C, MR18=0xA951, DQSOSC=388, MR23=63, INC=392, DEC=261
7000 10:54:41.864038 [RxdqsGatingPostProcess] freq 400
7001 10:54:41.870527 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 10:54:41.873988 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 10:54:41.876867 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 10:54:41.880167 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 10:54:41.883829 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 10:54:41.886607 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 10:54:41.887086 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 10:54:41.890077 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 10:54:41.893711 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 10:54:41.896876 Pre-setting of DQS Precalculation
7011 10:54:41.903675 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 10:54:41.909961 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 10:54:41.916912 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 10:54:41.917430
7015 10:54:41.917774
7016 10:54:41.919827 [Calibration Summary] 800 Mbps
7017 10:54:41.920256 CH 0, Rank 0
7018 10:54:41.923346 SW Impedance : PASS
7019 10:54:41.926718 DUTY Scan : NO K
7020 10:54:41.927241 ZQ Calibration : PASS
7021 10:54:41.929978 Jitter Meter : NO K
7022 10:54:41.933192 CBT Training : PASS
7023 10:54:41.933618 Write leveling : PASS
7024 10:54:41.936603 RX DQS gating : PASS
7025 10:54:41.939801 RX DQ/DQS(RDDQC) : PASS
7026 10:54:41.940318 TX DQ/DQS : PASS
7027 10:54:41.943009 RX DATLAT : PASS
7028 10:54:41.946349 RX DQ/DQS(Engine): PASS
7029 10:54:41.946864 TX OE : NO K
7030 10:54:41.949623 All Pass.
7031 10:54:41.950140
7032 10:54:41.950477 CH 0, Rank 1
7033 10:54:41.952845 SW Impedance : PASS
7034 10:54:41.953358 DUTY Scan : NO K
7035 10:54:41.955980 ZQ Calibration : PASS
7036 10:54:41.959848 Jitter Meter : NO K
7037 10:54:41.960365 CBT Training : PASS
7038 10:54:41.962848 Write leveling : NO K
7039 10:54:41.965837 RX DQS gating : PASS
7040 10:54:41.966354 RX DQ/DQS(RDDQC) : PASS
7041 10:54:41.969286 TX DQ/DQS : PASS
7042 10:54:41.972680 RX DATLAT : PASS
7043 10:54:41.973231 RX DQ/DQS(Engine): PASS
7044 10:54:41.976442 TX OE : NO K
7045 10:54:41.977002 All Pass.
7046 10:54:41.977356
7047 10:54:41.979227 CH 1, Rank 0
7048 10:54:41.979653 SW Impedance : PASS
7049 10:54:41.982486 DUTY Scan : NO K
7050 10:54:41.982924 ZQ Calibration : PASS
7051 10:54:41.985670 Jitter Meter : NO K
7052 10:54:41.989422 CBT Training : PASS
7053 10:54:41.989845 Write leveling : PASS
7054 10:54:41.992619 RX DQS gating : PASS
7055 10:54:41.995879 RX DQ/DQS(RDDQC) : PASS
7056 10:54:41.996311 TX DQ/DQS : PASS
7057 10:54:41.999156 RX DATLAT : PASS
7058 10:54:42.002887 RX DQ/DQS(Engine): PASS
7059 10:54:42.003413 TX OE : NO K
7060 10:54:42.005699 All Pass.
7061 10:54:42.006138
7062 10:54:42.006469 CH 1, Rank 1
7063 10:54:42.009374 SW Impedance : PASS
7064 10:54:42.009939 DUTY Scan : NO K
7065 10:54:42.012158 ZQ Calibration : PASS
7066 10:54:42.016144 Jitter Meter : NO K
7067 10:54:42.016670 CBT Training : PASS
7068 10:54:42.018905 Write leveling : NO K
7069 10:54:42.022438 RX DQS gating : PASS
7070 10:54:42.022858 RX DQ/DQS(RDDQC) : PASS
7071 10:54:42.025634 TX DQ/DQS : PASS
7072 10:54:42.028933 RX DATLAT : PASS
7073 10:54:42.029453 RX DQ/DQS(Engine): PASS
7074 10:54:42.031906 TX OE : NO K
7075 10:54:42.032334 All Pass.
7076 10:54:42.032673
7077 10:54:42.035077 DramC Write-DBI off
7078 10:54:42.039243 PER_BANK_REFRESH: Hybrid Mode
7079 10:54:42.039775 TX_TRACKING: ON
7080 10:54:42.048808 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 10:54:42.052195 [FAST_K] Save calibration result to emmc
7082 10:54:42.055798 dramc_set_vcore_voltage set vcore to 725000
7083 10:54:42.058632 Read voltage for 1600, 0
7084 10:54:42.059223 Vio18 = 0
7085 10:54:42.059605 Vcore = 725000
7086 10:54:42.061572 Vdram = 0
7087 10:54:42.062000 Vddq = 0
7088 10:54:42.062341 Vmddr = 0
7089 10:54:42.068409 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 10:54:42.071900 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 10:54:42.075327 MEM_TYPE=3, freq_sel=13
7092 10:54:42.078454 sv_algorithm_assistance_LP4_3733
7093 10:54:42.081318 ============ PULL DRAM RESETB DOWN ============
7094 10:54:42.088171 ========== PULL DRAM RESETB DOWN end =========
7095 10:54:42.092061 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 10:54:42.095220 ===================================
7097 10:54:42.097686 LPDDR4 DRAM CONFIGURATION
7098 10:54:42.101485 ===================================
7099 10:54:42.101943 EX_ROW_EN[0] = 0x0
7100 10:54:42.104463 EX_ROW_EN[1] = 0x0
7101 10:54:42.105027 LP4Y_EN = 0x0
7102 10:54:42.108038 WORK_FSP = 0x1
7103 10:54:42.108574 WL = 0x5
7104 10:54:42.111131 RL = 0x5
7105 10:54:42.111558 BL = 0x2
7106 10:54:42.114394 RPST = 0x0
7107 10:54:42.114820 RD_PRE = 0x0
7108 10:54:42.117717 WR_PRE = 0x1
7109 10:54:42.120859 WR_PST = 0x1
7110 10:54:42.121286 DBI_WR = 0x0
7111 10:54:42.124244 DBI_RD = 0x0
7112 10:54:42.124817 OTF = 0x1
7113 10:54:42.128018 ===================================
7114 10:54:42.131158 ===================================
7115 10:54:42.131697 ANA top config
7116 10:54:42.134065 ===================================
7117 10:54:42.137571 DLL_ASYNC_EN = 0
7118 10:54:42.141004 ALL_SLAVE_EN = 0
7119 10:54:42.144625 NEW_RANK_MODE = 1
7120 10:54:42.148055 DLL_IDLE_MODE = 1
7121 10:54:42.148591 LP45_APHY_COMB_EN = 1
7122 10:54:42.150978 TX_ODT_DIS = 0
7123 10:54:42.154159 NEW_8X_MODE = 1
7124 10:54:42.157453 ===================================
7125 10:54:42.161296 ===================================
7126 10:54:42.164355 data_rate = 3200
7127 10:54:42.167567 CKR = 1
7128 10:54:42.170863 DQ_P2S_RATIO = 8
7129 10:54:42.171397 ===================================
7130 10:54:42.174035 CA_P2S_RATIO = 8
7131 10:54:42.177333 DQ_CA_OPEN = 0
7132 10:54:42.180810 DQ_SEMI_OPEN = 0
7133 10:54:42.183701 CA_SEMI_OPEN = 0
7134 10:54:42.187431 CA_FULL_RATE = 0
7135 10:54:42.190284 DQ_CKDIV4_EN = 0
7136 10:54:42.190712 CA_CKDIV4_EN = 0
7137 10:54:42.193741 CA_PREDIV_EN = 0
7138 10:54:42.196898 PH8_DLY = 12
7139 10:54:42.200107 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 10:54:42.203621 DQ_AAMCK_DIV = 4
7141 10:54:42.206672 CA_AAMCK_DIV = 4
7142 10:54:42.207246 CA_ADMCK_DIV = 4
7143 10:54:42.210114 DQ_TRACK_CA_EN = 0
7144 10:54:42.213261 CA_PICK = 1600
7145 10:54:42.216967 CA_MCKIO = 1600
7146 10:54:42.220262 MCKIO_SEMI = 0
7147 10:54:42.223138 PLL_FREQ = 3068
7148 10:54:42.226677 DQ_UI_PI_RATIO = 32
7149 10:54:42.229858 CA_UI_PI_RATIO = 0
7150 10:54:42.233509 ===================================
7151 10:54:42.236463 ===================================
7152 10:54:42.237070 memory_type:LPDDR4
7153 10:54:42.240217 GP_NUM : 10
7154 10:54:42.243495 SRAM_EN : 1
7155 10:54:42.244065 MD32_EN : 0
7156 10:54:42.246532 ===================================
7157 10:54:42.249646 [ANA_INIT] >>>>>>>>>>>>>>
7158 10:54:42.252966 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 10:54:42.256365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 10:54:42.259846 ===================================
7161 10:54:42.263521 data_rate = 3200,PCW = 0X7600
7162 10:54:42.266531 ===================================
7163 10:54:42.269312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 10:54:42.272707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 10:54:42.279473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 10:54:42.282561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 10:54:42.285922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 10:54:42.289446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 10:54:42.292823 [ANA_INIT] flow start
7170 10:54:42.295953 [ANA_INIT] PLL >>>>>>>>
7171 10:54:42.296515 [ANA_INIT] PLL <<<<<<<<
7172 10:54:42.298959 [ANA_INIT] MIDPI >>>>>>>>
7173 10:54:42.302882 [ANA_INIT] MIDPI <<<<<<<<
7174 10:54:42.305728 [ANA_INIT] DLL >>>>>>>>
7175 10:54:42.306204 [ANA_INIT] DLL <<<<<<<<
7176 10:54:42.308921 [ANA_INIT] flow end
7177 10:54:42.312320 ============ LP4 DIFF to SE enter ============
7178 10:54:42.315913 ============ LP4 DIFF to SE exit ============
7179 10:54:42.318822 [ANA_INIT] <<<<<<<<<<<<<
7180 10:54:42.322511 [Flow] Enable top DCM control >>>>>
7181 10:54:42.325595 [Flow] Enable top DCM control <<<<<
7182 10:54:42.329026 Enable DLL master slave shuffle
7183 10:54:42.335757 ==============================================================
7184 10:54:42.336281 Gating Mode config
7185 10:54:42.342557 ==============================================================
7186 10:54:42.343084 Config description:
7187 10:54:42.352290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 10:54:42.358960 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 10:54:42.365348 SELPH_MODE 0: By rank 1: By Phase
7190 10:54:42.369134 ==============================================================
7191 10:54:42.372000 GAT_TRACK_EN = 1
7192 10:54:42.375337 RX_GATING_MODE = 2
7193 10:54:42.378581 RX_GATING_TRACK_MODE = 2
7194 10:54:42.381651 SELPH_MODE = 1
7195 10:54:42.384920 PICG_EARLY_EN = 1
7196 10:54:42.388851 VALID_LAT_VALUE = 1
7197 10:54:42.395349 ==============================================================
7198 10:54:42.398168 Enter into Gating configuration >>>>
7199 10:54:42.401452 Exit from Gating configuration <<<<
7200 10:54:42.404939 Enter into DVFS_PRE_config >>>>>
7201 10:54:42.414710 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 10:54:42.417926 Exit from DVFS_PRE_config <<<<<
7203 10:54:42.421382 Enter into PICG configuration >>>>
7204 10:54:42.424666 Exit from PICG configuration <<<<
7205 10:54:42.427528 [RX_INPUT] configuration >>>>>
7206 10:54:42.427957 [RX_INPUT] configuration <<<<<
7207 10:54:42.434447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 10:54:42.441448 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 10:54:42.447441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 10:54:42.451086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 10:54:42.457314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 10:54:42.464135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 10:54:42.467724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 10:54:42.473925 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 10:54:42.477661 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 10:54:42.480963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 10:54:42.484069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 10:54:42.490785 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 10:54:42.494029 ===================================
7220 10:54:42.494556 LPDDR4 DRAM CONFIGURATION
7221 10:54:42.497438 ===================================
7222 10:54:42.500491 EX_ROW_EN[0] = 0x0
7223 10:54:42.503731 EX_ROW_EN[1] = 0x0
7224 10:54:42.504254 LP4Y_EN = 0x0
7225 10:54:42.507390 WORK_FSP = 0x1
7226 10:54:42.507914 WL = 0x5
7227 10:54:42.510494 RL = 0x5
7228 10:54:42.510921 BL = 0x2
7229 10:54:42.513405 RPST = 0x0
7230 10:54:42.513832 RD_PRE = 0x0
7231 10:54:42.517001 WR_PRE = 0x1
7232 10:54:42.517532 WR_PST = 0x1
7233 10:54:42.520359 DBI_WR = 0x0
7234 10:54:42.520900 DBI_RD = 0x0
7235 10:54:42.523088 OTF = 0x1
7236 10:54:42.526682 ===================================
7237 10:54:42.529951 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 10:54:42.533184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 10:54:42.539664 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 10:54:42.543299 ===================================
7241 10:54:42.543828 LPDDR4 DRAM CONFIGURATION
7242 10:54:42.546317 ===================================
7243 10:54:42.549630 EX_ROW_EN[0] = 0x10
7244 10:54:42.553293 EX_ROW_EN[1] = 0x0
7245 10:54:42.553819 LP4Y_EN = 0x0
7246 10:54:42.556375 WORK_FSP = 0x1
7247 10:54:42.556816 WL = 0x5
7248 10:54:42.559823 RL = 0x5
7249 10:54:42.560348 BL = 0x2
7250 10:54:42.563004 RPST = 0x0
7251 10:54:42.563528 RD_PRE = 0x0
7252 10:54:42.566625 WR_PRE = 0x1
7253 10:54:42.567148 WR_PST = 0x1
7254 10:54:42.569760 DBI_WR = 0x0
7255 10:54:42.570277 DBI_RD = 0x0
7256 10:54:42.573144 OTF = 0x1
7257 10:54:42.576348 ===================================
7258 10:54:42.582615 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 10:54:42.583138 ==
7260 10:54:42.585853 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 10:54:42.589667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 10:54:42.590208 ==
7263 10:54:42.592721 [Duty_Offset_Calibration]
7264 10:54:42.593279 B0:2 B1:0 CA:1
7265 10:54:42.593624
7266 10:54:42.596004 [DutyScan_Calibration_Flow] k_type=0
7267 10:54:42.606276
7268 10:54:42.606792 ==CLK 0==
7269 10:54:42.609660 Final CLK duty delay cell = -4
7270 10:54:42.612632 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7271 10:54:42.616314 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7272 10:54:42.619539 [-4] AVG Duty = 4922%(X100)
7273 10:54:42.620063
7274 10:54:42.622247 CH0 CLK Duty spec in!! Max-Min= 218%
7275 10:54:42.626282 [DutyScan_Calibration_Flow] ====Done====
7276 10:54:42.626803
7277 10:54:42.629643 [DutyScan_Calibration_Flow] k_type=1
7278 10:54:42.645699
7279 10:54:42.646215 ==DQS 0 ==
7280 10:54:42.649182 Final DQS duty delay cell = 0
7281 10:54:42.652134 [0] MAX Duty = 5249%(X100), DQS PI = 32
7282 10:54:42.655658 [0] MIN Duty = 4969%(X100), DQS PI = 0
7283 10:54:42.658667 [0] AVG Duty = 5109%(X100)
7284 10:54:42.659090
7285 10:54:42.659427 ==DQS 1 ==
7286 10:54:42.662508 Final DQS duty delay cell = -4
7287 10:54:42.665400 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7288 10:54:42.668903 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7289 10:54:42.672254 [-4] AVG Duty = 5000%(X100)
7290 10:54:42.672805
7291 10:54:42.675156 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7292 10:54:42.675674
7293 10:54:42.678675 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7294 10:54:42.681791 [DutyScan_Calibration_Flow] ====Done====
7295 10:54:42.682354
7296 10:54:42.684708 [DutyScan_Calibration_Flow] k_type=3
7297 10:54:42.703012
7298 10:54:42.703536 ==DQM 0 ==
7299 10:54:42.706334 Final DQM duty delay cell = 0
7300 10:54:42.709926 [0] MAX Duty = 5093%(X100), DQS PI = 26
7301 10:54:42.712876 [0] MIN Duty = 4813%(X100), DQS PI = 50
7302 10:54:42.716355 [0] AVG Duty = 4953%(X100)
7303 10:54:42.716913
7304 10:54:42.717264 ==DQM 1 ==
7305 10:54:42.719566 Final DQM duty delay cell = 0
7306 10:54:42.723045 [0] MAX Duty = 5249%(X100), DQS PI = 30
7307 10:54:42.726420 [0] MIN Duty = 5000%(X100), DQS PI = 22
7308 10:54:42.729242 [0] AVG Duty = 5124%(X100)
7309 10:54:42.729659
7310 10:54:42.732654 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7311 10:54:42.733100
7312 10:54:42.736051 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7313 10:54:42.739225 [DutyScan_Calibration_Flow] ====Done====
7314 10:54:42.739635
7315 10:54:42.742200 [DutyScan_Calibration_Flow] k_type=2
7316 10:54:42.760115
7317 10:54:42.760638 ==DQ 0 ==
7318 10:54:42.763779 Final DQ duty delay cell = 0
7319 10:54:42.766994 [0] MAX Duty = 5124%(X100), DQS PI = 32
7320 10:54:42.770247 [0] MIN Duty = 5000%(X100), DQS PI = 16
7321 10:54:42.770785 [0] AVG Duty = 5062%(X100)
7322 10:54:42.773235
7323 10:54:42.773746 ==DQ 1 ==
7324 10:54:42.776874 Final DQ duty delay cell = 0
7325 10:54:42.779690 [0] MAX Duty = 4969%(X100), DQS PI = 44
7326 10:54:42.783343 [0] MIN Duty = 4875%(X100), DQS PI = 10
7327 10:54:42.783860 [0] AVG Duty = 4922%(X100)
7328 10:54:42.786391
7329 10:54:42.789742 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7330 10:54:42.790154
7331 10:54:42.793039 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7332 10:54:42.796519 [DutyScan_Calibration_Flow] ====Done====
7333 10:54:42.797079 ==
7334 10:54:42.799483 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 10:54:42.803356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 10:54:42.803880 ==
7337 10:54:42.806237 [Duty_Offset_Calibration]
7338 10:54:42.806645 B0:0 B1:-1 CA:2
7339 10:54:42.806971
7340 10:54:42.809608 [DutyScan_Calibration_Flow] k_type=0
7341 10:54:42.820570
7342 10:54:42.821121 ==CLK 0==
7343 10:54:42.823731 Final CLK duty delay cell = 0
7344 10:54:42.827043 [0] MAX Duty = 5156%(X100), DQS PI = 10
7345 10:54:42.830384 [0] MIN Duty = 4906%(X100), DQS PI = 46
7346 10:54:42.833638 [0] AVG Duty = 5031%(X100)
7347 10:54:42.834146
7348 10:54:42.836904 CH1 CLK Duty spec in!! Max-Min= 250%
7349 10:54:42.840441 [DutyScan_Calibration_Flow] ====Done====
7350 10:54:42.840990
7351 10:54:42.843513 [DutyScan_Calibration_Flow] k_type=1
7352 10:54:42.860026
7353 10:54:42.860533 ==DQS 0 ==
7354 10:54:42.863816 Final DQS duty delay cell = 0
7355 10:54:42.866707 [0] MAX Duty = 5124%(X100), DQS PI = 26
7356 10:54:42.870293 [0] MIN Duty = 5000%(X100), DQS PI = 0
7357 10:54:42.872960 [0] AVG Duty = 5062%(X100)
7358 10:54:42.873489
7359 10:54:42.873964 ==DQS 1 ==
7360 10:54:42.876853 Final DQS duty delay cell = 0
7361 10:54:42.879581 [0] MAX Duty = 5187%(X100), DQS PI = 0
7362 10:54:42.883307 [0] MIN Duty = 4844%(X100), DQS PI = 32
7363 10:54:42.886515 [0] AVG Duty = 5015%(X100)
7364 10:54:42.886925
7365 10:54:42.889724 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7366 10:54:42.890135
7367 10:54:42.892840 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7368 10:54:42.896391 [DutyScan_Calibration_Flow] ====Done====
7369 10:54:42.897034
7370 10:54:42.899227 [DutyScan_Calibration_Flow] k_type=3
7371 10:54:42.917687
7372 10:54:42.918204 ==DQM 0 ==
7373 10:54:42.920942 Final DQM duty delay cell = 4
7374 10:54:42.924708 [4] MAX Duty = 5125%(X100), DQS PI = 8
7375 10:54:42.927776 [4] MIN Duty = 4969%(X100), DQS PI = 48
7376 10:54:42.931047 [4] AVG Duty = 5047%(X100)
7377 10:54:42.931566
7378 10:54:42.931903 ==DQM 1 ==
7379 10:54:42.933923 Final DQM duty delay cell = 0
7380 10:54:42.937562 [0] MAX Duty = 5281%(X100), DQS PI = 58
7381 10:54:42.940796 [0] MIN Duty = 4876%(X100), DQS PI = 34
7382 10:54:42.944269 [0] AVG Duty = 5078%(X100)
7383 10:54:42.944824
7384 10:54:42.947176 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7385 10:54:42.947628
7386 10:54:42.951066 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7387 10:54:42.954047 [DutyScan_Calibration_Flow] ====Done====
7388 10:54:42.954476
7389 10:54:42.957484 [DutyScan_Calibration_Flow] k_type=2
7390 10:54:42.974569
7391 10:54:42.975104 ==DQ 0 ==
7392 10:54:42.977694 Final DQ duty delay cell = 0
7393 10:54:42.980861 [0] MAX Duty = 5093%(X100), DQS PI = 20
7394 10:54:42.984597 [0] MIN Duty = 4969%(X100), DQS PI = 46
7395 10:54:42.985059 [0] AVG Duty = 5031%(X100)
7396 10:54:42.987740
7397 10:54:42.988204 ==DQ 1 ==
7398 10:54:42.990770 Final DQ duty delay cell = 0
7399 10:54:42.994547 [0] MAX Duty = 5062%(X100), DQS PI = 2
7400 10:54:42.997417 [0] MIN Duty = 4813%(X100), DQS PI = 34
7401 10:54:42.997840 [0] AVG Duty = 4937%(X100)
7402 10:54:43.000737
7403 10:54:43.004282 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7404 10:54:43.004843
7405 10:54:43.007528 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7406 10:54:43.010934 [DutyScan_Calibration_Flow] ====Done====
7407 10:54:43.014246 nWR fixed to 30
7408 10:54:43.014670 [ModeRegInit_LP4] CH0 RK0
7409 10:54:43.017629 [ModeRegInit_LP4] CH0 RK1
7410 10:54:43.020905 [ModeRegInit_LP4] CH1 RK0
7411 10:54:43.023897 [ModeRegInit_LP4] CH1 RK1
7412 10:54:43.024419 match AC timing 5
7413 10:54:43.031096 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 10:54:43.034416 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 10:54:43.037635 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 10:54:43.044486 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 10:54:43.047751 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 10:54:43.048275 [MiockJmeterHQA]
7419 10:54:43.048611
7420 10:54:43.050361 [DramcMiockJmeter] u1RxGatingPI = 0
7421 10:54:43.054281 0 : 4365, 4140
7422 10:54:43.054860 4 : 4368, 4138
7423 10:54:43.057288 8 : 4371, 4142
7424 10:54:43.057818 12 : 4368, 4140
7425 10:54:43.058164 16 : 4368, 4140
7426 10:54:43.060405 20 : 4252, 4027
7427 10:54:43.060967 24 : 4255, 4029
7428 10:54:43.064022 28 : 4255, 4030
7429 10:54:43.064556 32 : 4253, 4026
7430 10:54:43.066993 36 : 4255, 4029
7431 10:54:43.067419 40 : 4363, 4137
7432 10:54:43.070346 44 : 4253, 4026
7433 10:54:43.070770 48 : 4253, 4026
7434 10:54:43.071110 52 : 4255, 4030
7435 10:54:43.073626 56 : 4257, 4032
7436 10:54:43.074183 60 : 4252, 4026
7437 10:54:43.076915 64 : 4363, 4137
7438 10:54:43.077438 68 : 4363, 4138
7439 10:54:43.080436 72 : 4250, 4027
7440 10:54:43.080998 76 : 4250, 4026
7441 10:54:43.083343 80 : 4250, 4026
7442 10:54:43.083765 84 : 4250, 4026
7443 10:54:43.084101 88 : 4253, 3352
7444 10:54:43.086771 92 : 4360, 0
7445 10:54:43.087197 96 : 4250, 0
7446 10:54:43.090210 100 : 4360, 0
7447 10:54:43.090806 104 : 4360, 0
7448 10:54:43.091154 108 : 4250, 0
7449 10:54:43.093374 112 : 4250, 0
7450 10:54:43.093799 116 : 4250, 0
7451 10:54:43.096704 120 : 4250, 0
7452 10:54:43.097295 124 : 4250, 0
7453 10:54:43.097643 128 : 4252, 0
7454 10:54:43.100081 132 : 4250, 0
7455 10:54:43.100607 136 : 4361, 0
7456 10:54:43.103450 140 : 4250, 0
7457 10:54:43.103988 144 : 4363, 0
7458 10:54:43.104332 148 : 4361, 0
7459 10:54:43.106456 152 : 4363, 0
7460 10:54:43.106887 156 : 4360, 0
7461 10:54:43.107229 160 : 4252, 0
7462 10:54:43.109887 164 : 4255, 0
7463 10:54:43.110322 168 : 4250, 0
7464 10:54:43.113205 172 : 4250, 0
7465 10:54:43.113718 176 : 4254, 0
7466 10:54:43.114121 180 : 4250, 0
7467 10:54:43.116336 184 : 4250, 0
7468 10:54:43.116795 188 : 4255, 0
7469 10:54:43.119752 192 : 4254, 0
7470 10:54:43.120184 196 : 4250, 0
7471 10:54:43.120533 200 : 4361, 10
7472 10:54:43.123344 204 : 4252, 2410
7473 10:54:43.123878 208 : 4250, 4027
7474 10:54:43.126387 212 : 4361, 4138
7475 10:54:43.126822 216 : 4250, 4026
7476 10:54:43.129794 220 : 4252, 4029
7477 10:54:43.130335 224 : 4360, 4138
7478 10:54:43.132940 228 : 4361, 4138
7479 10:54:43.133481 232 : 4250, 4026
7480 10:54:43.136518 236 : 4250, 4026
7481 10:54:43.137091 240 : 4250, 4026
7482 10:54:43.139340 244 : 4250, 4027
7483 10:54:43.139774 248 : 4250, 4026
7484 10:54:43.142965 252 : 4250, 4027
7485 10:54:43.143578 256 : 4250, 4026
7486 10:54:43.143933 260 : 4250, 4027
7487 10:54:43.146210 264 : 4361, 4137
7488 10:54:43.146745 268 : 4360, 4138
7489 10:54:43.149293 272 : 4248, 4024
7490 10:54:43.149728 276 : 4365, 4142
7491 10:54:43.152593 280 : 4250, 4026
7492 10:54:43.153064 284 : 4250, 4027
7493 10:54:43.156207 288 : 4250, 4027
7494 10:54:43.156640 292 : 4252, 4030
7495 10:54:43.159246 296 : 4250, 4027
7496 10:54:43.159717 300 : 4250, 4026
7497 10:54:43.162754 304 : 4250, 4027
7498 10:54:43.163290 308 : 4252, 4030
7499 10:54:43.166060 312 : 4250, 3845
7500 10:54:43.166496 316 : 4361, 2017
7501 10:54:43.166842
7502 10:54:43.169702 MIOCK jitter meter ch=0
7503 10:54:43.170238
7504 10:54:43.173123 1T = (316-92) = 224 dly cells
7505 10:54:43.176230 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7506 10:54:43.176762 ==
7507 10:54:43.179464 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 10:54:43.185628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 10:54:43.186061 ==
7510 10:54:43.188949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 10:54:43.195960 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 10:54:43.199132 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 10:54:43.205468 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 10:54:43.213454 [CA 0] Center 43 (13~73) winsize 61
7515 10:54:43.216579 [CA 1] Center 43 (13~73) winsize 61
7516 10:54:43.220086 [CA 2] Center 38 (8~68) winsize 61
7517 10:54:43.223113 [CA 3] Center 37 (8~67) winsize 60
7518 10:54:43.227152 [CA 4] Center 36 (6~66) winsize 61
7519 10:54:43.230323 [CA 5] Center 35 (5~65) winsize 61
7520 10:54:43.230863
7521 10:54:43.233294 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 10:54:43.233826
7523 10:54:43.239916 [CATrainingPosCal] consider 1 rank data
7524 10:54:43.240450 u2DelayCellTimex100 = 290/100 ps
7525 10:54:43.246265 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7526 10:54:43.249837 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7527 10:54:43.253361 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7528 10:54:43.256403 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7529 10:54:43.259604 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7530 10:54:43.262829 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7531 10:54:43.263363
7532 10:54:43.266212 CA PerBit enable=1, Macro0, CA PI delay=35
7533 10:54:43.266781
7534 10:54:43.269380 [CBTSetCACLKResult] CA Dly = 35
7535 10:54:43.272933 CS Dly: 9 (0~40)
7536 10:54:43.276624 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 10:54:43.279779 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 10:54:43.280316 ==
7539 10:54:43.283005 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 10:54:43.289158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 10:54:43.289622 ==
7542 10:54:43.292593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 10:54:43.299307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 10:54:43.302650 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 10:54:43.308747 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 10:54:43.319931 [CA 0] Center 43 (13~73) winsize 61
7547 10:54:43.320488 [CA 1] Center 43 (13~73) winsize 61
7548 10:54:43.323285 [CA 2] Center 38 (8~68) winsize 61
7549 10:54:43.326302 [CA 3] Center 38 (8~68) winsize 61
7550 10:54:43.330189 [CA 4] Center 36 (6~66) winsize 61
7551 10:54:43.333296 [CA 5] Center 36 (6~66) winsize 61
7552 10:54:43.333831
7553 10:54:43.336529 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 10:54:43.337100
7555 10:54:43.343049 [CATrainingPosCal] consider 2 rank data
7556 10:54:43.343587 u2DelayCellTimex100 = 290/100 ps
7557 10:54:43.349674 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7558 10:54:43.353179 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7559 10:54:43.355979 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7560 10:54:43.359458 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7561 10:54:43.363176 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7562 10:54:43.366482 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7563 10:54:43.367017
7564 10:54:43.369641 CA PerBit enable=1, Macro0, CA PI delay=35
7565 10:54:43.370175
7566 10:54:43.372569 [CBTSetCACLKResult] CA Dly = 35
7567 10:54:43.376096 CS Dly: 10 (0~43)
7568 10:54:43.379346 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 10:54:43.382784 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 10:54:43.383259
7571 10:54:43.385985 ----->DramcWriteLeveling(PI) begin...
7572 10:54:43.388964 ==
7573 10:54:43.392583 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 10:54:43.395684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 10:54:43.396203 ==
7576 10:54:43.398961 Write leveling (Byte 0): 36 => 36
7577 10:54:43.402696 Write leveling (Byte 1): 32 => 32
7578 10:54:43.405658 DramcWriteLeveling(PI) end<-----
7579 10:54:43.406087
7580 10:54:43.406417 ==
7581 10:54:43.408730 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 10:54:43.412253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 10:54:43.412721 ==
7584 10:54:43.415571 [Gating] SW mode calibration
7585 10:54:43.422307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 10:54:43.428705 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 10:54:43.432104 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 10:54:43.435561 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 10:54:43.442324 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7590 10:54:43.445710 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7591 10:54:43.448872 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7592 10:54:43.455269 1 4 20 | B1->B0 | 3231 3434 | 1 1 | (1 1) (1 1)
7593 10:54:43.458656 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 10:54:43.461695 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 10:54:43.468960 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 10:54:43.471905 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 10:54:43.475025 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7598 10:54:43.481753 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7599 10:54:43.484806 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7600 10:54:43.488453 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7601 10:54:43.491566 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 10:54:43.498223 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 10:54:43.501443 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 10:54:43.504604 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 10:54:43.511725 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7606 10:54:43.514810 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7607 10:54:43.517818 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7608 10:54:43.524572 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7609 10:54:43.527901 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 10:54:43.531153 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 10:54:43.537559 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 10:54:43.541499 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 10:54:43.544559 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7614 10:54:43.551099 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 10:54:43.554263 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7616 10:54:43.557778 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7617 10:54:43.564019 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7618 10:54:43.567743 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 10:54:43.570786 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 10:54:43.577594 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 10:54:43.580820 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:54:43.583950 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:54:43.590641 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:54:43.593940 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:54:43.597201 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:54:43.603586 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 10:54:43.607169 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:54:43.610645 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 10:54:43.616867 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 10:54:43.620182 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 10:54:43.623355 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 10:54:43.627100 Total UI for P1: 0, mck2ui 16
7633 10:54:43.630304 best dqsien dly found for B0: ( 1, 9, 10)
7634 10:54:43.636694 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 10:54:43.640243 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 10:54:43.643353 Total UI for P1: 0, mck2ui 16
7637 10:54:43.646414 best dqsien dly found for B1: ( 1, 9, 18)
7638 10:54:43.649838 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7639 10:54:43.653121 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7640 10:54:43.653615
7641 10:54:43.656434 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7642 10:54:43.663002 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7643 10:54:43.663507 [Gating] SW calibration Done
7644 10:54:43.663850 ==
7645 10:54:43.666403 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 10:54:43.673333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 10:54:43.673763 ==
7648 10:54:43.674101 RX Vref Scan: 0
7649 10:54:43.674417
7650 10:54:43.676422 RX Vref 0 -> 0, step: 1
7651 10:54:43.676954
7652 10:54:43.679950 RX Delay 0 -> 252, step: 8
7653 10:54:43.682979 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7654 10:54:43.686571 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7655 10:54:43.689698 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7656 10:54:43.692954 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7657 10:54:43.699301 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7658 10:54:43.702999 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7659 10:54:43.706120 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7660 10:54:43.709479 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7661 10:54:43.712339 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7662 10:54:43.719134 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7663 10:54:43.722464 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7664 10:54:43.725522 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7665 10:54:43.729119 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7666 10:54:43.735795 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7667 10:54:43.738621 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7668 10:54:43.742227 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7669 10:54:43.742897 ==
7670 10:54:43.745638 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 10:54:43.749246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 10:54:43.749674 ==
7673 10:54:43.752005 DQS Delay:
7674 10:54:43.752429 DQS0 = 0, DQS1 = 0
7675 10:54:43.755846 DQM Delay:
7676 10:54:43.756394 DQM0 = 137, DQM1 = 127
7677 10:54:43.756754 DQ Delay:
7678 10:54:43.761972 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7679 10:54:43.765308 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7680 10:54:43.768870 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7681 10:54:43.772042 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7682 10:54:43.772471
7683 10:54:43.772841
7684 10:54:43.773161 ==
7685 10:54:43.775076 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 10:54:43.778795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 10:54:43.779321 ==
7688 10:54:43.779661
7689 10:54:43.779977
7690 10:54:43.781770 TX Vref Scan disable
7691 10:54:43.785132 == TX Byte 0 ==
7692 10:54:43.788410 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7693 10:54:43.791522 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 10:54:43.794773 == TX Byte 1 ==
7695 10:54:43.798527 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7696 10:54:43.801686 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7697 10:54:43.802145 ==
7698 10:54:43.804801 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 10:54:43.811736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 10:54:43.812247 ==
7701 10:54:43.824193
7702 10:54:43.828052 TX Vref early break, caculate TX vref
7703 10:54:43.831263 TX Vref=16, minBit 7, minWin=22, winSum=374
7704 10:54:43.834180 TX Vref=18, minBit 2, minWin=23, winSum=382
7705 10:54:43.837689 TX Vref=20, minBit 0, minWin=24, winSum=395
7706 10:54:43.841271 TX Vref=22, minBit 7, minWin=24, winSum=409
7707 10:54:43.844424 TX Vref=24, minBit 6, minWin=25, winSum=417
7708 10:54:43.850855 TX Vref=26, minBit 12, minWin=25, winSum=425
7709 10:54:43.854229 TX Vref=28, minBit 2, minWin=26, winSum=429
7710 10:54:43.857379 TX Vref=30, minBit 0, minWin=25, winSum=421
7711 10:54:43.860737 TX Vref=32, minBit 0, minWin=25, winSum=413
7712 10:54:43.864119 TX Vref=34, minBit 0, minWin=25, winSum=408
7713 10:54:43.870758 TX Vref=36, minBit 0, minWin=24, winSum=391
7714 10:54:43.873930 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
7715 10:54:43.874451
7716 10:54:43.877228 Final TX Range 0 Vref 28
7717 10:54:43.877781
7718 10:54:43.878126 ==
7719 10:54:43.880096 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 10:54:43.884007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 10:54:43.887369 ==
7722 10:54:43.887888
7723 10:54:43.888234
7724 10:54:43.888552 TX Vref Scan disable
7725 10:54:43.893701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7726 10:54:43.894130 == TX Byte 0 ==
7727 10:54:43.896832 u2DelayCellOfst[0]=13 cells (4 PI)
7728 10:54:43.900120 u2DelayCellOfst[1]=16 cells (5 PI)
7729 10:54:43.903832 u2DelayCellOfst[2]=10 cells (3 PI)
7730 10:54:43.906819 u2DelayCellOfst[3]=10 cells (3 PI)
7731 10:54:43.910276 u2DelayCellOfst[4]=6 cells (2 PI)
7732 10:54:43.913314 u2DelayCellOfst[5]=0 cells (0 PI)
7733 10:54:43.917099 u2DelayCellOfst[6]=16 cells (5 PI)
7734 10:54:43.920256 u2DelayCellOfst[7]=16 cells (5 PI)
7735 10:54:43.923605 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7736 10:54:43.927201 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7737 10:54:43.930529 == TX Byte 1 ==
7738 10:54:43.933036 u2DelayCellOfst[8]=0 cells (0 PI)
7739 10:54:43.936733 u2DelayCellOfst[9]=0 cells (0 PI)
7740 10:54:43.940123 u2DelayCellOfst[10]=6 cells (2 PI)
7741 10:54:43.943312 u2DelayCellOfst[11]=0 cells (0 PI)
7742 10:54:43.946589 u2DelayCellOfst[12]=10 cells (3 PI)
7743 10:54:43.949924 u2DelayCellOfst[13]=10 cells (3 PI)
7744 10:54:43.950369 u2DelayCellOfst[14]=10 cells (3 PI)
7745 10:54:43.953015 u2DelayCellOfst[15]=6 cells (2 PI)
7746 10:54:43.959665 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7747 10:54:43.963171 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7748 10:54:43.966249 DramC Write-DBI on
7749 10:54:43.966683 ==
7750 10:54:43.969438 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 10:54:43.972921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 10:54:43.973474 ==
7753 10:54:43.973866
7754 10:54:43.974244
7755 10:54:43.975846 TX Vref Scan disable
7756 10:54:43.976290 == TX Byte 0 ==
7757 10:54:43.983004 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7758 10:54:43.983548 == TX Byte 1 ==
7759 10:54:43.986164 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7760 10:54:43.989566 DramC Write-DBI off
7761 10:54:43.989991
7762 10:54:43.990331 [DATLAT]
7763 10:54:43.992588 Freq=1600, CH0 RK0
7764 10:54:43.993106
7765 10:54:43.993444 DATLAT Default: 0xf
7766 10:54:43.996038 0, 0xFFFF, sum = 0
7767 10:54:43.996561 1, 0xFFFF, sum = 0
7768 10:54:43.999128 2, 0xFFFF, sum = 0
7769 10:54:44.002647 3, 0xFFFF, sum = 0
7770 10:54:44.003126 4, 0xFFFF, sum = 0
7771 10:54:44.005768 5, 0xFFFF, sum = 0
7772 10:54:44.006299 6, 0xFFFF, sum = 0
7773 10:54:44.008843 7, 0xFFFF, sum = 0
7774 10:54:44.009329 8, 0xFFFF, sum = 0
7775 10:54:44.012459 9, 0xFFFF, sum = 0
7776 10:54:44.012996 10, 0xFFFF, sum = 0
7777 10:54:44.015625 11, 0xFFFF, sum = 0
7778 10:54:44.016110 12, 0xFFFF, sum = 0
7779 10:54:44.018925 13, 0xFFFF, sum = 0
7780 10:54:44.019426 14, 0x0, sum = 1
7781 10:54:44.022504 15, 0x0, sum = 2
7782 10:54:44.022927 16, 0x0, sum = 3
7783 10:54:44.025808 17, 0x0, sum = 4
7784 10:54:44.026251 best_step = 15
7785 10:54:44.026587
7786 10:54:44.026900 ==
7787 10:54:44.028919 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 10:54:44.035407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 10:54:44.035960 ==
7790 10:54:44.036363 RX Vref Scan: 1
7791 10:54:44.036685
7792 10:54:44.039180 Set Vref Range= 24 -> 127
7793 10:54:44.039705
7794 10:54:44.042152 RX Vref 24 -> 127, step: 1
7795 10:54:44.042644
7796 10:54:44.042993 RX Delay 19 -> 252, step: 4
7797 10:54:44.043310
7798 10:54:44.045459 Set Vref, RX VrefLevel [Byte0]: 24
7799 10:54:44.048724 [Byte1]: 24
7800 10:54:44.052694
7801 10:54:44.053269 Set Vref, RX VrefLevel [Byte0]: 25
7802 10:54:44.055987 [Byte1]: 25
7803 10:54:44.060412
7804 10:54:44.060861 Set Vref, RX VrefLevel [Byte0]: 26
7805 10:54:44.063570 [Byte1]: 26
7806 10:54:44.068201
7807 10:54:44.068732 Set Vref, RX VrefLevel [Byte0]: 27
7808 10:54:44.071306 [Byte1]: 27
7809 10:54:44.075931
7810 10:54:44.076562 Set Vref, RX VrefLevel [Byte0]: 28
7811 10:54:44.078842 [Byte1]: 28
7812 10:54:44.083258
7813 10:54:44.083761 Set Vref, RX VrefLevel [Byte0]: 29
7814 10:54:44.086176 [Byte1]: 29
7815 10:54:44.090578
7816 10:54:44.091083 Set Vref, RX VrefLevel [Byte0]: 30
7817 10:54:44.093616 [Byte1]: 30
7818 10:54:44.098438
7819 10:54:44.098860 Set Vref, RX VrefLevel [Byte0]: 31
7820 10:54:44.101521 [Byte1]: 31
7821 10:54:44.105472
7822 10:54:44.105897 Set Vref, RX VrefLevel [Byte0]: 32
7823 10:54:44.108927 [Byte1]: 32
7824 10:54:44.113077
7825 10:54:44.113564 Set Vref, RX VrefLevel [Byte0]: 33
7826 10:54:44.116925 [Byte1]: 33
7827 10:54:44.120963
7828 10:54:44.121477 Set Vref, RX VrefLevel [Byte0]: 34
7829 10:54:44.124000 [Byte1]: 34
7830 10:54:44.128561
7831 10:54:44.129217 Set Vref, RX VrefLevel [Byte0]: 35
7832 10:54:44.131890 [Byte1]: 35
7833 10:54:44.135851
7834 10:54:44.136277 Set Vref, RX VrefLevel [Byte0]: 36
7835 10:54:44.139210 [Byte1]: 36
7836 10:54:44.143593
7837 10:54:44.144017 Set Vref, RX VrefLevel [Byte0]: 37
7838 10:54:44.146726 [Byte1]: 37
7839 10:54:44.151608
7840 10:54:44.152165 Set Vref, RX VrefLevel [Byte0]: 38
7841 10:54:44.154547 [Byte1]: 38
7842 10:54:44.158608
7843 10:54:44.159032 Set Vref, RX VrefLevel [Byte0]: 39
7844 10:54:44.162200 [Byte1]: 39
7845 10:54:44.166409
7846 10:54:44.166830 Set Vref, RX VrefLevel [Byte0]: 40
7847 10:54:44.169591 [Byte1]: 40
7848 10:54:44.173713
7849 10:54:44.174135 Set Vref, RX VrefLevel [Byte0]: 41
7850 10:54:44.176869 [Byte1]: 41
7851 10:54:44.181157
7852 10:54:44.181577 Set Vref, RX VrefLevel [Byte0]: 42
7853 10:54:44.184406 [Byte1]: 42
7854 10:54:44.189031
7855 10:54:44.189457 Set Vref, RX VrefLevel [Byte0]: 43
7856 10:54:44.192166 [Byte1]: 43
7857 10:54:44.196678
7858 10:54:44.197139 Set Vref, RX VrefLevel [Byte0]: 44
7859 10:54:44.199907 [Byte1]: 44
7860 10:54:44.203881
7861 10:54:44.204300 Set Vref, RX VrefLevel [Byte0]: 45
7862 10:54:44.207592 [Byte1]: 45
7863 10:54:44.211594
7864 10:54:44.212016 Set Vref, RX VrefLevel [Byte0]: 46
7865 10:54:44.215075 [Byte1]: 46
7866 10:54:44.219038
7867 10:54:44.219459 Set Vref, RX VrefLevel [Byte0]: 47
7868 10:54:44.222837 [Byte1]: 47
7869 10:54:44.226981
7870 10:54:44.227401 Set Vref, RX VrefLevel [Byte0]: 48
7871 10:54:44.230146 [Byte1]: 48
7872 10:54:44.234333
7873 10:54:44.234784 Set Vref, RX VrefLevel [Byte0]: 49
7874 10:54:44.237682 [Byte1]: 49
7875 10:54:44.242317
7876 10:54:44.242751 Set Vref, RX VrefLevel [Byte0]: 50
7877 10:54:44.245485 [Byte1]: 50
7878 10:54:44.249660
7879 10:54:44.250093 Set Vref, RX VrefLevel [Byte0]: 51
7880 10:54:44.252711 [Byte1]: 51
7881 10:54:44.256958
7882 10:54:44.257390 Set Vref, RX VrefLevel [Byte0]: 52
7883 10:54:44.260633 [Byte1]: 52
7884 10:54:44.264534
7885 10:54:44.265016 Set Vref, RX VrefLevel [Byte0]: 53
7886 10:54:44.267870 [Byte1]: 53
7887 10:54:44.271995
7888 10:54:44.272427 Set Vref, RX VrefLevel [Byte0]: 54
7889 10:54:44.275576 [Byte1]: 54
7890 10:54:44.279815
7891 10:54:44.280212 Set Vref, RX VrefLevel [Byte0]: 55
7892 10:54:44.283251 [Byte1]: 55
7893 10:54:44.287398
7894 10:54:44.287804 Set Vref, RX VrefLevel [Byte0]: 56
7895 10:54:44.290641 [Byte1]: 56
7896 10:54:44.295453
7897 10:54:44.295884 Set Vref, RX VrefLevel [Byte0]: 57
7898 10:54:44.298089 [Byte1]: 57
7899 10:54:44.302693
7900 10:54:44.303127 Set Vref, RX VrefLevel [Byte0]: 58
7901 10:54:44.305667 [Byte1]: 58
7902 10:54:44.310122
7903 10:54:44.310556 Set Vref, RX VrefLevel [Byte0]: 59
7904 10:54:44.313211 [Byte1]: 59
7905 10:54:44.317581
7906 10:54:44.318014 Set Vref, RX VrefLevel [Byte0]: 60
7907 10:54:44.320795 [Byte1]: 60
7908 10:54:44.325201
7909 10:54:44.325636 Set Vref, RX VrefLevel [Byte0]: 61
7910 10:54:44.328505 [Byte1]: 61
7911 10:54:44.332823
7912 10:54:44.333251 Set Vref, RX VrefLevel [Byte0]: 62
7913 10:54:44.336107 [Byte1]: 62
7914 10:54:44.340298
7915 10:54:44.340729 Set Vref, RX VrefLevel [Byte0]: 63
7916 10:54:44.343545 [Byte1]: 63
7917 10:54:44.347829
7918 10:54:44.348262 Set Vref, RX VrefLevel [Byte0]: 64
7919 10:54:44.351578 [Byte1]: 64
7920 10:54:44.355514
7921 10:54:44.355949 Set Vref, RX VrefLevel [Byte0]: 65
7922 10:54:44.359244 [Byte1]: 65
7923 10:54:44.363142
7924 10:54:44.363575 Set Vref, RX VrefLevel [Byte0]: 66
7925 10:54:44.366307 [Byte1]: 66
7926 10:54:44.370734
7927 10:54:44.371180 Set Vref, RX VrefLevel [Byte0]: 67
7928 10:54:44.377045 [Byte1]: 67
7929 10:54:44.377479
7930 10:54:44.380744 Set Vref, RX VrefLevel [Byte0]: 68
7931 10:54:44.383814 [Byte1]: 68
7932 10:54:44.384213
7933 10:54:44.386970 Set Vref, RX VrefLevel [Byte0]: 69
7934 10:54:44.390588 [Byte1]: 69
7935 10:54:44.390985
7936 10:54:44.393788 Set Vref, RX VrefLevel [Byte0]: 70
7937 10:54:44.396858 [Byte1]: 70
7938 10:54:44.400982
7939 10:54:44.401370 Set Vref, RX VrefLevel [Byte0]: 71
7940 10:54:44.403955 [Byte1]: 71
7941 10:54:44.408422
7942 10:54:44.408843 Set Vref, RX VrefLevel [Byte0]: 72
7943 10:54:44.411599 [Byte1]: 72
7944 10:54:44.416607
7945 10:54:44.417083 Set Vref, RX VrefLevel [Byte0]: 73
7946 10:54:44.419391 [Byte1]: 73
7947 10:54:44.423405
7948 10:54:44.423841 Set Vref, RX VrefLevel [Byte0]: 74
7949 10:54:44.426799 [Byte1]: 74
7950 10:54:44.431044
7951 10:54:44.431477 Set Vref, RX VrefLevel [Byte0]: 75
7952 10:54:44.434668 [Byte1]: 75
7953 10:54:44.438981
7954 10:54:44.439404 Set Vref, RX VrefLevel [Byte0]: 76
7955 10:54:44.442225 [Byte1]: 76
7956 10:54:44.446339
7957 10:54:44.446763 Set Vref, RX VrefLevel [Byte0]: 77
7958 10:54:44.449438 [Byte1]: 77
7959 10:54:44.454026
7960 10:54:44.454455 Set Vref, RX VrefLevel [Byte0]: 78
7961 10:54:44.457056 [Byte1]: 78
7962 10:54:44.461540
7963 10:54:44.461960 Set Vref, RX VrefLevel [Byte0]: 79
7964 10:54:44.464812 [Byte1]: 79
7965 10:54:44.469203
7966 10:54:44.469623 Set Vref, RX VrefLevel [Byte0]: 80
7967 10:54:44.472047 [Byte1]: 80
7968 10:54:44.476383
7969 10:54:44.476830 Set Vref, RX VrefLevel [Byte0]: 81
7970 10:54:44.480009 [Byte1]: 81
7971 10:54:44.484211
7972 10:54:44.484632 Final RX Vref Byte 0 = 61 to rank0
7973 10:54:44.487319 Final RX Vref Byte 1 = 61 to rank0
7974 10:54:44.490986 Final RX Vref Byte 0 = 61 to rank1
7975 10:54:44.494390 Final RX Vref Byte 1 = 61 to rank1==
7976 10:54:44.497480 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 10:54:44.504697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 10:54:44.505216 ==
7979 10:54:44.505559 DQS Delay:
7980 10:54:44.505878 DQS0 = 0, DQS1 = 0
7981 10:54:44.507705 DQM Delay:
7982 10:54:44.508127 DQM0 = 136, DQM1 = 124
7983 10:54:44.510848 DQ Delay:
7984 10:54:44.513910 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7985 10:54:44.517906 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7986 10:54:44.520719 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7987 10:54:44.524139 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7988 10:54:44.524561
7989 10:54:44.524937
7990 10:54:44.525252
7991 10:54:44.526816 [DramC_TX_OE_Calibration] TA2
7992 10:54:44.530321 Original DQ_B0 (3 6) =30, OEN = 27
7993 10:54:44.533611 Original DQ_B1 (3 6) =30, OEN = 27
7994 10:54:44.536614 24, 0x0, End_B0=24 End_B1=24
7995 10:54:44.536725 25, 0x0, End_B0=25 End_B1=25
7996 10:54:44.540190 26, 0x0, End_B0=26 End_B1=26
7997 10:54:44.543388 27, 0x0, End_B0=27 End_B1=27
7998 10:54:44.546558 28, 0x0, End_B0=28 End_B1=28
7999 10:54:44.550091 29, 0x0, End_B0=29 End_B1=29
8000 10:54:44.550176 30, 0x0, End_B0=30 End_B1=30
8001 10:54:44.553055 31, 0x4141, End_B0=30 End_B1=30
8002 10:54:44.556391 Byte0 end_step=30 best_step=27
8003 10:54:44.559819 Byte1 end_step=30 best_step=27
8004 10:54:44.562969 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 10:54:44.566227 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 10:54:44.566310
8007 10:54:44.566376
8008 10:54:44.573171 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8009 10:54:44.576267 CH0 RK0: MR19=303, MR18=1E1C
8010 10:54:44.582881 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8011 10:54:44.582965
8012 10:54:44.586163 ----->DramcWriteLeveling(PI) begin...
8013 10:54:44.586248 ==
8014 10:54:44.589280 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 10:54:44.593081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 10:54:44.593165 ==
8017 10:54:44.596146 Write leveling (Byte 0): 38 => 38
8018 10:54:44.599135 Write leveling (Byte 1): 30 => 30
8019 10:54:44.602734 DramcWriteLeveling(PI) end<-----
8020 10:54:44.602816
8021 10:54:44.602882 ==
8022 10:54:44.606043 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 10:54:44.609212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 10:54:44.612568 ==
8025 10:54:44.612677 [Gating] SW mode calibration
8026 10:54:44.622438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 10:54:44.625543 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 10:54:44.629341 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 10:54:44.635453 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 10:54:44.638644 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 10:54:44.642274 1 4 12 | B1->B0 | 2424 3131 | 1 0 | (1 1) (1 1)
8032 10:54:44.648799 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8033 10:54:44.652020 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 10:54:44.655465 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 10:54:44.661790 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 10:54:44.664983 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 10:54:44.668427 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 10:54:44.674803 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 10:54:44.678592 1 5 12 | B1->B0 | 3434 2828 | 0 0 | (0 1) (0 1)
8040 10:54:44.681706 1 5 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8041 10:54:44.688317 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 10:54:44.691445 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 10:54:44.694803 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 10:54:44.701074 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 10:54:44.704489 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 10:54:44.707851 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8047 10:54:44.714526 1 6 12 | B1->B0 | 2b2b 403f | 0 1 | (0 0) (0 0)
8048 10:54:44.718038 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 10:54:44.721217 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 10:54:44.727517 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 10:54:44.730943 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 10:54:44.734279 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 10:54:44.740846 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 10:54:44.744190 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 10:54:44.747592 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8056 10:54:44.754203 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8057 10:54:44.757260 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 10:54:44.760706 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:54:44.767131 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:54:44.770757 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:54:44.773694 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 10:54:44.780647 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 10:54:44.783708 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 10:54:44.786927 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 10:54:44.793474 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 10:54:44.797116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 10:54:44.800166 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 10:54:44.806718 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 10:54:44.810047 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 10:54:44.813347 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 10:54:44.820296 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8072 10:54:44.823522 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8073 10:54:44.826795 Total UI for P1: 0, mck2ui 16
8074 10:54:44.829868 best dqsien dly found for B0: ( 1, 9, 10)
8075 10:54:44.833447 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 10:54:44.836242 Total UI for P1: 0, mck2ui 16
8077 10:54:44.839491 best dqsien dly found for B1: ( 1, 9, 14)
8078 10:54:44.842974 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8079 10:54:44.849435 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8080 10:54:44.849516
8081 10:54:44.852750 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8082 10:54:44.856229 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 10:54:44.859319 [Gating] SW calibration Done
8084 10:54:44.859400 ==
8085 10:54:44.862956 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 10:54:44.866498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 10:54:44.866580 ==
8088 10:54:44.869474 RX Vref Scan: 0
8089 10:54:44.869555
8090 10:54:44.869620 RX Vref 0 -> 0, step: 1
8091 10:54:44.869680
8092 10:54:44.872760 RX Delay 0 -> 252, step: 8
8093 10:54:44.875884 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8094 10:54:44.882698 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8095 10:54:44.885674 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8096 10:54:44.888903 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8097 10:54:44.892347 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8098 10:54:44.895407 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8099 10:54:44.901924 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8100 10:54:44.905715 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8101 10:54:44.908613 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8102 10:54:44.912187 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8103 10:54:44.915443 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8104 10:54:44.921989 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8105 10:54:44.925210 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8106 10:54:44.928570 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8107 10:54:44.931907 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8108 10:54:44.938524 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8109 10:54:44.938619 ==
8110 10:54:44.942157 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 10:54:44.945489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 10:54:44.945675 ==
8113 10:54:44.945774 DQS Delay:
8114 10:54:44.948428 DQS0 = 0, DQS1 = 0
8115 10:54:44.948615 DQM Delay:
8116 10:54:44.951670 DQM0 = 136, DQM1 = 125
8117 10:54:44.951842 DQ Delay:
8118 10:54:44.955260 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8119 10:54:44.958701 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8120 10:54:44.961617 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8121 10:54:44.964987 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8122 10:54:44.965244
8123 10:54:44.968069
8124 10:54:44.968328 ==
8125 10:54:44.971331 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 10:54:44.975335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 10:54:44.975660 ==
8128 10:54:44.975865
8129 10:54:44.976052
8130 10:54:44.978476 TX Vref Scan disable
8131 10:54:44.978800 == TX Byte 0 ==
8132 10:54:44.985076 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8133 10:54:44.988172 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8134 10:54:44.988652 == TX Byte 1 ==
8135 10:54:44.994830 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8136 10:54:44.997877 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8137 10:54:44.998404 ==
8138 10:54:45.001458 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 10:54:45.004664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 10:54:45.005237 ==
8141 10:54:45.020590
8142 10:54:45.023827 TX Vref early break, caculate TX vref
8143 10:54:45.027406 TX Vref=16, minBit 0, minWin=23, winSum=390
8144 10:54:45.030774 TX Vref=18, minBit 8, minWin=23, winSum=396
8145 10:54:45.033901 TX Vref=20, minBit 8, minWin=24, winSum=406
8146 10:54:45.037381 TX Vref=22, minBit 8, minWin=24, winSum=413
8147 10:54:45.040510 TX Vref=24, minBit 1, minWin=25, winSum=420
8148 10:54:45.047258 TX Vref=26, minBit 0, minWin=26, winSum=432
8149 10:54:45.050473 TX Vref=28, minBit 0, minWin=26, winSum=431
8150 10:54:45.053632 TX Vref=30, minBit 0, minWin=26, winSum=426
8151 10:54:45.057516 TX Vref=32, minBit 2, minWin=25, winSum=419
8152 10:54:45.060170 TX Vref=34, minBit 0, minWin=25, winSum=410
8153 10:54:45.063674 TX Vref=36, minBit 2, minWin=24, winSum=400
8154 10:54:45.070289 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8155 10:54:45.070805
8156 10:54:45.073576 Final TX Range 0 Vref 26
8157 10:54:45.074102
8158 10:54:45.074447 ==
8159 10:54:45.077262 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 10:54:45.080334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 10:54:45.080885 ==
8162 10:54:45.081230
8163 10:54:45.081544
8164 10:54:45.083979 TX Vref Scan disable
8165 10:54:45.090056 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8166 10:54:45.090481 == TX Byte 0 ==
8167 10:54:45.093617 u2DelayCellOfst[0]=13 cells (4 PI)
8168 10:54:45.096368 u2DelayCellOfst[1]=20 cells (6 PI)
8169 10:54:45.100094 u2DelayCellOfst[2]=13 cells (4 PI)
8170 10:54:45.102942 u2DelayCellOfst[3]=13 cells (4 PI)
8171 10:54:45.106653 u2DelayCellOfst[4]=10 cells (3 PI)
8172 10:54:45.110232 u2DelayCellOfst[5]=0 cells (0 PI)
8173 10:54:45.113613 u2DelayCellOfst[6]=20 cells (6 PI)
8174 10:54:45.116442 u2DelayCellOfst[7]=20 cells (6 PI)
8175 10:54:45.119918 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8176 10:54:45.123345 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8177 10:54:45.126290 == TX Byte 1 ==
8178 10:54:45.129628 u2DelayCellOfst[8]=0 cells (0 PI)
8179 10:54:45.133380 u2DelayCellOfst[9]=3 cells (1 PI)
8180 10:54:45.136300 u2DelayCellOfst[10]=6 cells (2 PI)
8181 10:54:45.139627 u2DelayCellOfst[11]=3 cells (1 PI)
8182 10:54:45.142807 u2DelayCellOfst[12]=13 cells (4 PI)
8183 10:54:45.143330 u2DelayCellOfst[13]=10 cells (3 PI)
8184 10:54:45.146536 u2DelayCellOfst[14]=16 cells (5 PI)
8185 10:54:45.149906 u2DelayCellOfst[15]=13 cells (4 PI)
8186 10:54:45.156009 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8187 10:54:45.159616 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8188 10:54:45.162603 DramC Write-DBI on
8189 10:54:45.163030 ==
8190 10:54:45.165888 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 10:54:45.169344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 10:54:45.169890 ==
8193 10:54:45.170237
8194 10:54:45.170546
8195 10:54:45.172409 TX Vref Scan disable
8196 10:54:45.172954 == TX Byte 0 ==
8197 10:54:45.178752 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8198 10:54:45.179274 == TX Byte 1 ==
8199 10:54:45.182574 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8200 10:54:45.185506 DramC Write-DBI off
8201 10:54:45.186030
8202 10:54:45.186365 [DATLAT]
8203 10:54:45.188982 Freq=1600, CH0 RK1
8204 10:54:45.189507
8205 10:54:45.189848 DATLAT Default: 0xf
8206 10:54:45.191908 0, 0xFFFF, sum = 0
8207 10:54:45.195745 1, 0xFFFF, sum = 0
8208 10:54:45.196196 2, 0xFFFF, sum = 0
8209 10:54:45.199141 3, 0xFFFF, sum = 0
8210 10:54:45.199677 4, 0xFFFF, sum = 0
8211 10:54:45.202041 5, 0xFFFF, sum = 0
8212 10:54:45.202471 6, 0xFFFF, sum = 0
8213 10:54:45.205197 7, 0xFFFF, sum = 0
8214 10:54:45.205626 8, 0xFFFF, sum = 0
8215 10:54:45.208818 9, 0xFFFF, sum = 0
8216 10:54:45.209250 10, 0xFFFF, sum = 0
8217 10:54:45.212351 11, 0xFFFF, sum = 0
8218 10:54:45.212933 12, 0xFFFF, sum = 0
8219 10:54:45.215430 13, 0xFFFF, sum = 0
8220 10:54:45.215860 14, 0x0, sum = 1
8221 10:54:45.218413 15, 0x0, sum = 2
8222 10:54:45.218862 16, 0x0, sum = 3
8223 10:54:45.221935 17, 0x0, sum = 4
8224 10:54:45.222472 best_step = 15
8225 10:54:45.222813
8226 10:54:45.223127 ==
8227 10:54:45.225136 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 10:54:45.231925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 10:54:45.232465 ==
8230 10:54:45.232849 RX Vref Scan: 0
8231 10:54:45.233182
8232 10:54:45.235265 RX Vref 0 -> 0, step: 1
8233 10:54:45.235797
8234 10:54:45.238528 RX Delay 11 -> 252, step: 4
8235 10:54:45.241693 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8236 10:54:45.244746 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8237 10:54:45.248347 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8238 10:54:45.254993 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8239 10:54:45.258295 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8240 10:54:45.261805 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8241 10:54:45.265337 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8242 10:54:45.268173 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8243 10:54:45.274853 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8244 10:54:45.277681 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8245 10:54:45.281359 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8246 10:54:45.284445 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8247 10:54:45.291144 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8248 10:54:45.294199 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8249 10:54:45.297394 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8250 10:54:45.301275 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8251 10:54:45.301696 ==
8252 10:54:45.304501 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 10:54:45.310842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 10:54:45.311431 ==
8255 10:54:45.311900 DQS Delay:
8256 10:54:45.312285 DQS0 = 0, DQS1 = 0
8257 10:54:45.314142 DQM Delay:
8258 10:54:45.314558 DQM0 = 132, DQM1 = 123
8259 10:54:45.317319 DQ Delay:
8260 10:54:45.320608 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8261 10:54:45.324118 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8262 10:54:45.327576 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8263 10:54:45.330541 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8264 10:54:45.330961
8265 10:54:45.331292
8266 10:54:45.331599
8267 10:54:45.333965 [DramC_TX_OE_Calibration] TA2
8268 10:54:45.336875 Original DQ_B0 (3 6) =30, OEN = 27
8269 10:54:45.340365 Original DQ_B1 (3 6) =30, OEN = 27
8270 10:54:45.344187 24, 0x0, End_B0=24 End_B1=24
8271 10:54:45.347358 25, 0x0, End_B0=25 End_B1=25
8272 10:54:45.347886 26, 0x0, End_B0=26 End_B1=26
8273 10:54:45.350203 27, 0x0, End_B0=27 End_B1=27
8274 10:54:45.353698 28, 0x0, End_B0=28 End_B1=28
8275 10:54:45.356814 29, 0x0, End_B0=29 End_B1=29
8276 10:54:45.357336 30, 0x0, End_B0=30 End_B1=30
8277 10:54:45.360740 31, 0x5151, End_B0=30 End_B1=30
8278 10:54:45.363617 Byte0 end_step=30 best_step=27
8279 10:54:45.367093 Byte1 end_step=30 best_step=27
8280 10:54:45.370024 Byte0 TX OE(2T, 0.5T) = (3, 3)
8281 10:54:45.373672 Byte1 TX OE(2T, 0.5T) = (3, 3)
8282 10:54:45.374196
8283 10:54:45.374532
8284 10:54:45.380058 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8285 10:54:45.383553 CH0 RK1: MR19=303, MR18=1F0C
8286 10:54:45.389984 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8287 10:54:45.393401 [RxdqsGatingPostProcess] freq 1600
8288 10:54:45.399611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8289 10:54:45.400042 best DQS0 dly(2T, 0.5T) = (1, 1)
8290 10:54:45.403205 best DQS1 dly(2T, 0.5T) = (1, 1)
8291 10:54:45.406167 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8292 10:54:45.409865 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8293 10:54:45.413119 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 10:54:45.416300 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 10:54:45.419483 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 10:54:45.423056 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 10:54:45.426310 Pre-setting of DQS Precalculation
8298 10:54:45.429305 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8299 10:54:45.429841 ==
8300 10:54:45.432943 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 10:54:45.439675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 10:54:45.440211 ==
8303 10:54:45.442917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8304 10:54:45.449698 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8305 10:54:45.452957 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8306 10:54:45.459498 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8307 10:54:45.466949 [CA 0] Center 40 (11~70) winsize 60
8308 10:54:45.470351 [CA 1] Center 41 (12~71) winsize 60
8309 10:54:45.473573 [CA 2] Center 37 (8~67) winsize 60
8310 10:54:45.476638 [CA 3] Center 36 (7~66) winsize 60
8311 10:54:45.479977 [CA 4] Center 37 (7~67) winsize 61
8312 10:54:45.483326 [CA 5] Center 36 (6~66) winsize 61
8313 10:54:45.483739
8314 10:54:45.486569 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8315 10:54:45.486985
8316 10:54:45.490148 [CATrainingPosCal] consider 1 rank data
8317 10:54:45.493708 u2DelayCellTimex100 = 290/100 ps
8318 10:54:45.496661 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8319 10:54:45.503492 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8320 10:54:45.506673 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8321 10:54:45.510129 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8322 10:54:45.513398 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8323 10:54:45.516430 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8324 10:54:45.516871
8325 10:54:45.519631 CA PerBit enable=1, Macro0, CA PI delay=36
8326 10:54:45.520043
8327 10:54:45.523641 [CBTSetCACLKResult] CA Dly = 36
8328 10:54:45.526601 CS Dly: 9 (0~40)
8329 10:54:45.530137 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8330 10:54:45.533058 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8331 10:54:45.533531 ==
8332 10:54:45.536519 Dram Type= 6, Freq= 0, CH_1, rank 1
8333 10:54:45.540180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 10:54:45.543086 ==
8335 10:54:45.546621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 10:54:45.549648 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 10:54:45.556154 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 10:54:45.563020 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 10:54:45.570545 [CA 0] Center 42 (12~72) winsize 61
8340 10:54:45.573714 [CA 1] Center 41 (12~71) winsize 60
8341 10:54:45.577114 [CA 2] Center 37 (8~67) winsize 60
8342 10:54:45.580287 [CA 3] Center 37 (8~66) winsize 59
8343 10:54:45.583418 [CA 4] Center 37 (8~67) winsize 60
8344 10:54:45.586741 [CA 5] Center 36 (7~66) winsize 60
8345 10:54:45.587259
8346 10:54:45.589671 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 10:54:45.590087
8348 10:54:45.593188 [CATrainingPosCal] consider 2 rank data
8349 10:54:45.596199 u2DelayCellTimex100 = 290/100 ps
8350 10:54:45.602825 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8351 10:54:45.606141 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8352 10:54:45.609483 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8353 10:54:45.612754 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8354 10:54:45.616028 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8355 10:54:45.619660 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8356 10:54:45.620072
8357 10:54:45.622852 CA PerBit enable=1, Macro0, CA PI delay=36
8358 10:54:45.623369
8359 10:54:45.626017 [CBTSetCACLKResult] CA Dly = 36
8360 10:54:45.629296 CS Dly: 10 (0~42)
8361 10:54:45.632887 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 10:54:45.636031 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 10:54:45.636546
8364 10:54:45.638992 ----->DramcWriteLeveling(PI) begin...
8365 10:54:45.639414 ==
8366 10:54:45.642607 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 10:54:45.649084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 10:54:45.649599 ==
8369 10:54:45.652439 Write leveling (Byte 0): 26 => 26
8370 10:54:45.655803 Write leveling (Byte 1): 27 => 27
8371 10:54:45.656324 DramcWriteLeveling(PI) end<-----
8372 10:54:45.659224
8373 10:54:45.659738 ==
8374 10:54:45.662044 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 10:54:45.665397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 10:54:45.665819 ==
8377 10:54:45.669383 [Gating] SW mode calibration
8378 10:54:45.675809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8379 10:54:45.678971 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8380 10:54:45.685480 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 10:54:45.688954 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 10:54:45.692293 1 4 8 | B1->B0 | 2727 2e2e | 1 1 | (0 0) (0 0)
8383 10:54:45.698839 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 10:54:45.702294 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 10:54:45.705179 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 10:54:45.711832 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 10:54:45.715116 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 10:54:45.718751 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 10:54:45.725311 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8390 10:54:45.728550 1 5 8 | B1->B0 | 2a2a 2626 | 0 0 | (0 1) (1 0)
8391 10:54:45.732086 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8392 10:54:45.738463 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 10:54:45.741655 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 10:54:45.745344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 10:54:45.751738 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 10:54:45.755228 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 10:54:45.758647 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 10:54:45.765035 1 6 8 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
8399 10:54:45.768470 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 10:54:45.771831 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 10:54:45.778084 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 10:54:45.781178 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 10:54:45.784605 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 10:54:45.791478 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 10:54:45.794629 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 10:54:45.797642 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 10:54:45.804440 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8408 10:54:45.807570 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8409 10:54:45.810984 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:54:45.817789 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:54:45.820497 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:54:45.824144 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:54:45.830556 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:54:45.833809 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 10:54:45.837333 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 10:54:45.844184 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 10:54:45.847588 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 10:54:45.850865 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 10:54:45.857091 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 10:54:45.860915 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 10:54:45.864041 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8422 10:54:45.870928 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8423 10:54:45.874090 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8424 10:54:45.877099 Total UI for P1: 0, mck2ui 16
8425 10:54:45.880718 best dqsien dly found for B0: ( 1, 9, 6)
8426 10:54:45.884012 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 10:54:45.887068 Total UI for P1: 0, mck2ui 16
8428 10:54:45.890027 best dqsien dly found for B1: ( 1, 9, 10)
8429 10:54:45.893654 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8430 10:54:45.896717 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8431 10:54:45.897298
8432 10:54:45.903747 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8433 10:54:45.906355 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8434 10:54:45.909614 [Gating] SW calibration Done
8435 10:54:45.910045 ==
8436 10:54:45.912996 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 10:54:45.916864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 10:54:45.917389 ==
8439 10:54:45.917733 RX Vref Scan: 0
8440 10:54:45.918055
8441 10:54:45.919705 RX Vref 0 -> 0, step: 1
8442 10:54:45.920134
8443 10:54:45.923342 RX Delay 0 -> 252, step: 8
8444 10:54:45.926466 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8445 10:54:45.929809 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8446 10:54:45.936341 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8447 10:54:45.939658 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8448 10:54:45.942805 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8449 10:54:45.946132 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8450 10:54:45.949183 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8451 10:54:45.956223 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8452 10:54:45.959487 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8453 10:54:45.962843 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8454 10:54:45.965669 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8455 10:54:45.969295 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8456 10:54:45.976288 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8457 10:54:45.979357 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8458 10:54:45.982695 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8459 10:54:45.985536 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8460 10:54:45.985962 ==
8461 10:54:45.988951 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 10:54:45.996016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 10:54:45.996547 ==
8464 10:54:45.996920 DQS Delay:
8465 10:54:45.997236 DQS0 = 0, DQS1 = 0
8466 10:54:45.998850 DQM Delay:
8467 10:54:45.999273 DQM0 = 138, DQM1 = 130
8468 10:54:46.002099 DQ Delay:
8469 10:54:46.005495 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8470 10:54:46.008873 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8471 10:54:46.011987 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8472 10:54:46.015735 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8473 10:54:46.016257
8474 10:54:46.016599
8475 10:54:46.016963 ==
8476 10:54:46.018876 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 10:54:46.022080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 10:54:46.025430 ==
8479 10:54:46.025951
8480 10:54:46.026296
8481 10:54:46.026609 TX Vref Scan disable
8482 10:54:46.028372 == TX Byte 0 ==
8483 10:54:46.031848 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8484 10:54:46.035035 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8485 10:54:46.038286 == TX Byte 1 ==
8486 10:54:46.041852 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8487 10:54:46.044972 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8488 10:54:46.048186 ==
8489 10:54:46.051835 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 10:54:46.055229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 10:54:46.055771 ==
8492 10:54:46.068267
8493 10:54:46.071738 TX Vref early break, caculate TX vref
8494 10:54:46.074993 TX Vref=16, minBit 0, minWin=22, winSum=372
8495 10:54:46.078233 TX Vref=18, minBit 5, minWin=23, winSum=379
8496 10:54:46.081213 TX Vref=20, minBit 10, minWin=23, winSum=393
8497 10:54:46.084670 TX Vref=22, minBit 0, minWin=24, winSum=404
8498 10:54:46.088121 TX Vref=24, minBit 5, minWin=24, winSum=406
8499 10:54:46.094252 TX Vref=26, minBit 10, minWin=24, winSum=418
8500 10:54:46.097417 TX Vref=28, minBit 12, minWin=25, winSum=421
8501 10:54:46.100794 TX Vref=30, minBit 14, minWin=24, winSum=415
8502 10:54:46.104409 TX Vref=32, minBit 9, minWin=24, winSum=409
8503 10:54:46.107714 TX Vref=34, minBit 9, minWin=24, winSum=401
8504 10:54:46.114563 TX Vref=36, minBit 10, minWin=23, winSum=390
8505 10:54:46.117564 [TxChooseVref] Worse bit 12, Min win 25, Win sum 421, Final Vref 28
8506 10:54:46.118112
8507 10:54:46.120636 Final TX Range 0 Vref 28
8508 10:54:46.121272
8509 10:54:46.121765 ==
8510 10:54:46.124553 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 10:54:46.130438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 10:54:46.131050 ==
8513 10:54:46.131429
8514 10:54:46.131777
8515 10:54:46.132085 TX Vref Scan disable
8516 10:54:46.137544 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8517 10:54:46.138101 == TX Byte 0 ==
8518 10:54:46.140689 u2DelayCellOfst[0]=13 cells (4 PI)
8519 10:54:46.144115 u2DelayCellOfst[1]=10 cells (3 PI)
8520 10:54:46.147782 u2DelayCellOfst[2]=0 cells (0 PI)
8521 10:54:46.150851 u2DelayCellOfst[3]=6 cells (2 PI)
8522 10:54:46.154150 u2DelayCellOfst[4]=6 cells (2 PI)
8523 10:54:46.157232 u2DelayCellOfst[5]=16 cells (5 PI)
8524 10:54:46.160682 u2DelayCellOfst[6]=16 cells (5 PI)
8525 10:54:46.164017 u2DelayCellOfst[7]=3 cells (1 PI)
8526 10:54:46.167141 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8527 10:54:46.170645 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8528 10:54:46.174023 == TX Byte 1 ==
8529 10:54:46.177012 u2DelayCellOfst[8]=0 cells (0 PI)
8530 10:54:46.180497 u2DelayCellOfst[9]=3 cells (1 PI)
8531 10:54:46.183557 u2DelayCellOfst[10]=10 cells (3 PI)
8532 10:54:46.186894 u2DelayCellOfst[11]=3 cells (1 PI)
8533 10:54:46.190504 u2DelayCellOfst[12]=13 cells (4 PI)
8534 10:54:46.193822 u2DelayCellOfst[13]=16 cells (5 PI)
8535 10:54:46.197076 u2DelayCellOfst[14]=20 cells (6 PI)
8536 10:54:46.197500 u2DelayCellOfst[15]=16 cells (5 PI)
8537 10:54:46.203670 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8538 10:54:46.206802 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8539 10:54:46.210026 DramC Write-DBI on
8540 10:54:46.210449 ==
8541 10:54:46.213185 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 10:54:46.216565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 10:54:46.217033 ==
8544 10:54:46.217372
8545 10:54:46.217684
8546 10:54:46.219900 TX Vref Scan disable
8547 10:54:46.220322 == TX Byte 0 ==
8548 10:54:46.226379 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8549 10:54:46.226805 == TX Byte 1 ==
8550 10:54:46.229993 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8551 10:54:46.233275 DramC Write-DBI off
8552 10:54:46.233698
8553 10:54:46.234034 [DATLAT]
8554 10:54:46.236567 Freq=1600, CH1 RK0
8555 10:54:46.237037
8556 10:54:46.237373 DATLAT Default: 0xf
8557 10:54:46.239715 0, 0xFFFF, sum = 0
8558 10:54:46.240145 1, 0xFFFF, sum = 0
8559 10:54:46.242952 2, 0xFFFF, sum = 0
8560 10:54:46.246358 3, 0xFFFF, sum = 0
8561 10:54:46.246788 4, 0xFFFF, sum = 0
8562 10:54:46.249581 5, 0xFFFF, sum = 0
8563 10:54:46.250010 6, 0xFFFF, sum = 0
8564 10:54:46.253142 7, 0xFFFF, sum = 0
8565 10:54:46.253572 8, 0xFFFF, sum = 0
8566 10:54:46.256208 9, 0xFFFF, sum = 0
8567 10:54:46.256709 10, 0xFFFF, sum = 0
8568 10:54:46.259606 11, 0xFFFF, sum = 0
8569 10:54:46.260035 12, 0xFFFF, sum = 0
8570 10:54:46.262784 13, 0xFFFF, sum = 0
8571 10:54:46.263216 14, 0x0, sum = 1
8572 10:54:46.266138 15, 0x0, sum = 2
8573 10:54:46.266569 16, 0x0, sum = 3
8574 10:54:46.269586 17, 0x0, sum = 4
8575 10:54:46.270015 best_step = 15
8576 10:54:46.270349
8577 10:54:46.270661 ==
8578 10:54:46.272830 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 10:54:46.279655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 10:54:46.280084 ==
8581 10:54:46.280422 RX Vref Scan: 1
8582 10:54:46.280742
8583 10:54:46.282697 Set Vref Range= 24 -> 127
8584 10:54:46.283123
8585 10:54:46.286312 RX Vref 24 -> 127, step: 1
8586 10:54:46.286738
8587 10:54:46.287073 RX Delay 19 -> 252, step: 4
8588 10:54:46.287388
8589 10:54:46.289220 Set Vref, RX VrefLevel [Byte0]: 24
8590 10:54:46.292474 [Byte1]: 24
8591 10:54:46.296623
8592 10:54:46.297081 Set Vref, RX VrefLevel [Byte0]: 25
8593 10:54:46.299753 [Byte1]: 25
8594 10:54:46.304077
8595 10:54:46.304497 Set Vref, RX VrefLevel [Byte0]: 26
8596 10:54:46.307239 [Byte1]: 26
8597 10:54:46.311970
8598 10:54:46.312394 Set Vref, RX VrefLevel [Byte0]: 27
8599 10:54:46.315082 [Byte1]: 27
8600 10:54:46.319410
8601 10:54:46.319832 Set Vref, RX VrefLevel [Byte0]: 28
8602 10:54:46.322474 [Byte1]: 28
8603 10:54:46.326757
8604 10:54:46.327179 Set Vref, RX VrefLevel [Byte0]: 29
8605 10:54:46.330211 [Byte1]: 29
8606 10:54:46.334411
8607 10:54:46.334835 Set Vref, RX VrefLevel [Byte0]: 30
8608 10:54:46.337903 [Byte1]: 30
8609 10:54:46.341936
8610 10:54:46.342358 Set Vref, RX VrefLevel [Byte0]: 31
8611 10:54:46.345657 [Byte1]: 31
8612 10:54:46.349779
8613 10:54:46.350396 Set Vref, RX VrefLevel [Byte0]: 32
8614 10:54:46.352801 [Byte1]: 32
8615 10:54:46.357514
8616 10:54:46.357935 Set Vref, RX VrefLevel [Byte0]: 33
8617 10:54:46.360284 [Byte1]: 33
8618 10:54:46.365056
8619 10:54:46.365554 Set Vref, RX VrefLevel [Byte0]: 34
8620 10:54:46.368351 [Byte1]: 34
8621 10:54:46.372324
8622 10:54:46.372928 Set Vref, RX VrefLevel [Byte0]: 35
8623 10:54:46.375734 [Byte1]: 35
8624 10:54:46.379806
8625 10:54:46.380283 Set Vref, RX VrefLevel [Byte0]: 36
8626 10:54:46.382992 [Byte1]: 36
8627 10:54:46.387462
8628 10:54:46.388019 Set Vref, RX VrefLevel [Byte0]: 37
8629 10:54:46.390682 [Byte1]: 37
8630 10:54:46.395039
8631 10:54:46.395647 Set Vref, RX VrefLevel [Byte0]: 38
8632 10:54:46.398320 [Byte1]: 38
8633 10:54:46.402460
8634 10:54:46.402887 Set Vref, RX VrefLevel [Byte0]: 39
8635 10:54:46.406095 [Byte1]: 39
8636 10:54:46.410266
8637 10:54:46.410684 Set Vref, RX VrefLevel [Byte0]: 40
8638 10:54:46.413552 [Byte1]: 40
8639 10:54:46.417578
8640 10:54:46.417992 Set Vref, RX VrefLevel [Byte0]: 41
8641 10:54:46.421221 [Byte1]: 41
8642 10:54:46.425352
8643 10:54:46.425769 Set Vref, RX VrefLevel [Byte0]: 42
8644 10:54:46.428586 [Byte1]: 42
8645 10:54:46.432998
8646 10:54:46.433420 Set Vref, RX VrefLevel [Byte0]: 43
8647 10:54:46.436299 [Byte1]: 43
8648 10:54:46.440244
8649 10:54:46.440663 Set Vref, RX VrefLevel [Byte0]: 44
8650 10:54:46.444000 [Byte1]: 44
8651 10:54:46.448228
8652 10:54:46.448648 Set Vref, RX VrefLevel [Byte0]: 45
8653 10:54:46.451550 [Byte1]: 45
8654 10:54:46.455703
8655 10:54:46.456124 Set Vref, RX VrefLevel [Byte0]: 46
8656 10:54:46.458871 [Byte1]: 46
8657 10:54:46.463139
8658 10:54:46.463579 Set Vref, RX VrefLevel [Byte0]: 47
8659 10:54:46.466374 [Byte1]: 47
8660 10:54:46.470606
8661 10:54:46.471024 Set Vref, RX VrefLevel [Byte0]: 48
8662 10:54:46.474070 [Byte1]: 48
8663 10:54:46.478601
8664 10:54:46.479048 Set Vref, RX VrefLevel [Byte0]: 49
8665 10:54:46.481640 [Byte1]: 49
8666 10:54:46.485985
8667 10:54:46.486413 Set Vref, RX VrefLevel [Byte0]: 50
8668 10:54:46.489199 [Byte1]: 50
8669 10:54:46.493372
8670 10:54:46.493937 Set Vref, RX VrefLevel [Byte0]: 51
8671 10:54:46.496969 [Byte1]: 51
8672 10:54:46.501029
8673 10:54:46.501599 Set Vref, RX VrefLevel [Byte0]: 52
8674 10:54:46.504508 [Byte1]: 52
8675 10:54:46.508741
8676 10:54:46.509217 Set Vref, RX VrefLevel [Byte0]: 53
8677 10:54:46.511872 [Byte1]: 53
8678 10:54:46.516213
8679 10:54:46.516849 Set Vref, RX VrefLevel [Byte0]: 54
8680 10:54:46.519583 [Byte1]: 54
8681 10:54:46.523717
8682 10:54:46.524141 Set Vref, RX VrefLevel [Byte0]: 55
8683 10:54:46.527183 [Byte1]: 55
8684 10:54:46.531418
8685 10:54:46.531848 Set Vref, RX VrefLevel [Byte0]: 56
8686 10:54:46.534750 [Byte1]: 56
8687 10:54:46.538731
8688 10:54:46.539234 Set Vref, RX VrefLevel [Byte0]: 57
8689 10:54:46.542125 [Byte1]: 57
8690 10:54:46.546761
8691 10:54:46.547187 Set Vref, RX VrefLevel [Byte0]: 58
8692 10:54:46.549805 [Byte1]: 58
8693 10:54:46.553913
8694 10:54:46.556747 Set Vref, RX VrefLevel [Byte0]: 59
8695 10:54:46.560106 [Byte1]: 59
8696 10:54:46.560215
8697 10:54:46.563425 Set Vref, RX VrefLevel [Byte0]: 60
8698 10:54:46.567093 [Byte1]: 60
8699 10:54:46.567177
8700 10:54:46.570290 Set Vref, RX VrefLevel [Byte0]: 61
8701 10:54:46.573547 [Byte1]: 61
8702 10:54:46.573631
8703 10:54:46.576889 Set Vref, RX VrefLevel [Byte0]: 62
8704 10:54:46.580306 [Byte1]: 62
8705 10:54:46.583896
8706 10:54:46.583993 Set Vref, RX VrefLevel [Byte0]: 63
8707 10:54:46.587398 [Byte1]: 63
8708 10:54:46.591671
8709 10:54:46.591754 Set Vref, RX VrefLevel [Byte0]: 64
8710 10:54:46.595055 [Byte1]: 64
8711 10:54:46.598942
8712 10:54:46.599043 Set Vref, RX VrefLevel [Byte0]: 65
8713 10:54:46.602238 [Byte1]: 65
8714 10:54:46.606451
8715 10:54:46.606535 Set Vref, RX VrefLevel [Byte0]: 66
8716 10:54:46.609945 [Byte1]: 66
8717 10:54:46.614177
8718 10:54:46.614261 Set Vref, RX VrefLevel [Byte0]: 67
8719 10:54:46.617453 [Byte1]: 67
8720 10:54:46.621980
8721 10:54:46.622062 Set Vref, RX VrefLevel [Byte0]: 68
8722 10:54:46.625187 [Byte1]: 68
8723 10:54:46.629370
8724 10:54:46.629455 Set Vref, RX VrefLevel [Byte0]: 69
8725 10:54:46.632851 [Byte1]: 69
8726 10:54:46.637402
8727 10:54:46.637565 Set Vref, RX VrefLevel [Byte0]: 70
8728 10:54:46.640683 [Byte1]: 70
8729 10:54:46.644592
8730 10:54:46.644782 Set Vref, RX VrefLevel [Byte0]: 71
8731 10:54:46.647860 [Byte1]: 71
8732 10:54:46.652375
8733 10:54:46.652537 Set Vref, RX VrefLevel [Byte0]: 72
8734 10:54:46.655401 [Byte1]: 72
8735 10:54:46.660144
8736 10:54:46.660288 Final RX Vref Byte 0 = 55 to rank0
8737 10:54:46.662919 Final RX Vref Byte 1 = 61 to rank0
8738 10:54:46.666629 Final RX Vref Byte 0 = 55 to rank1
8739 10:54:46.669585 Final RX Vref Byte 1 = 61 to rank1==
8740 10:54:46.672742 Dram Type= 6, Freq= 0, CH_1, rank 0
8741 10:54:46.679385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 10:54:46.679473 ==
8743 10:54:46.679540 DQS Delay:
8744 10:54:46.682508 DQS0 = 0, DQS1 = 0
8745 10:54:46.682592 DQM Delay:
8746 10:54:46.682658 DQM0 = 133, DQM1 = 129
8747 10:54:46.685767 DQ Delay:
8748 10:54:46.688923 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8749 10:54:46.692296 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8750 10:54:46.695373 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8751 10:54:46.698881 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8752 10:54:46.698965
8753 10:54:46.699031
8754 10:54:46.699092
8755 10:54:46.702361 [DramC_TX_OE_Calibration] TA2
8756 10:54:46.705399 Original DQ_B0 (3 6) =30, OEN = 27
8757 10:54:46.708803 Original DQ_B1 (3 6) =30, OEN = 27
8758 10:54:46.712285 24, 0x0, End_B0=24 End_B1=24
8759 10:54:46.715389 25, 0x0, End_B0=25 End_B1=25
8760 10:54:46.715474 26, 0x0, End_B0=26 End_B1=26
8761 10:54:46.718601 27, 0x0, End_B0=27 End_B1=27
8762 10:54:46.722203 28, 0x0, End_B0=28 End_B1=28
8763 10:54:46.725365 29, 0x0, End_B0=29 End_B1=29
8764 10:54:46.728613 30, 0x0, End_B0=30 End_B1=30
8765 10:54:46.728697 31, 0x4141, End_B0=30 End_B1=30
8766 10:54:46.731754 Byte0 end_step=30 best_step=27
8767 10:54:46.735208 Byte1 end_step=30 best_step=27
8768 10:54:46.738307 Byte0 TX OE(2T, 0.5T) = (3, 3)
8769 10:54:46.741818 Byte1 TX OE(2T, 0.5T) = (3, 3)
8770 10:54:46.741902
8771 10:54:46.741967
8772 10:54:46.748372 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8773 10:54:46.751616 CH1 RK0: MR19=303, MR18=1927
8774 10:54:46.758404 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8775 10:54:46.758488
8776 10:54:46.761693 ----->DramcWriteLeveling(PI) begin...
8777 10:54:46.761777 ==
8778 10:54:46.764823 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 10:54:46.767912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 10:54:46.771218 ==
8781 10:54:46.771301 Write leveling (Byte 0): 24 => 24
8782 10:54:46.774393 Write leveling (Byte 1): 28 => 28
8783 10:54:46.777990 DramcWriteLeveling(PI) end<-----
8784 10:54:46.778073
8785 10:54:46.778138 ==
8786 10:54:46.781184 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 10:54:46.787863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 10:54:46.787947 ==
8789 10:54:46.791064 [Gating] SW mode calibration
8790 10:54:46.797707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8791 10:54:46.800962 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8792 10:54:46.807592 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 10:54:46.810883 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 10:54:46.814217 1 4 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8795 10:54:46.820745 1 4 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8796 10:54:46.824064 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 10:54:46.827200 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 10:54:46.834109 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 10:54:46.837194 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 10:54:46.840865 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 10:54:46.847130 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 10:54:46.850372 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8803 10:54:46.853555 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8804 10:54:46.860520 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 10:54:46.863698 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 10:54:46.866879 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 10:54:46.873793 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 10:54:46.877005 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 10:54:46.880290 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8810 10:54:46.886762 1 6 8 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8811 10:54:46.889941 1 6 12 | B1->B0 | 4646 3939 | 0 0 | (0 0) (0 0)
8812 10:54:46.893336 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 10:54:46.899884 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 10:54:46.902910 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 10:54:46.906413 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 10:54:46.912947 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 10:54:46.916392 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8818 10:54:46.919788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8819 10:54:46.926356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8820 10:54:46.929695 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:54:46.932935 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 10:54:46.939793 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 10:54:46.942933 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 10:54:46.946284 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 10:54:46.952469 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 10:54:46.955753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 10:54:46.959453 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 10:54:46.965900 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 10:54:46.969201 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 10:54:46.972241 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 10:54:46.979061 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 10:54:46.982346 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 10:54:46.985526 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 10:54:46.992410 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8835 10:54:46.995549 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8836 10:54:46.998883 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 10:54:47.002433 Total UI for P1: 0, mck2ui 16
8838 10:54:47.005406 best dqsien dly found for B0: ( 1, 9, 10)
8839 10:54:47.008482 Total UI for P1: 0, mck2ui 16
8840 10:54:47.011970 best dqsien dly found for B1: ( 1, 9, 10)
8841 10:54:47.015145 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8842 10:54:47.018629 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8843 10:54:47.018738
8844 10:54:47.025227 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8845 10:54:47.028600 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8846 10:54:47.031588 [Gating] SW calibration Done
8847 10:54:47.031719 ==
8848 10:54:47.034967 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 10:54:47.038102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 10:54:47.038274 ==
8851 10:54:47.038405 RX Vref Scan: 0
8852 10:54:47.038528
8853 10:54:47.041699 RX Vref 0 -> 0, step: 1
8854 10:54:47.041866
8855 10:54:47.044820 RX Delay 0 -> 252, step: 8
8856 10:54:47.048484 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8857 10:54:47.051886 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8858 10:54:47.055161 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8859 10:54:47.061788 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8860 10:54:47.064961 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8861 10:54:47.068151 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8862 10:54:47.071721 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8863 10:54:47.075044 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8864 10:54:47.081578 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8865 10:54:47.084706 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8866 10:54:47.088570 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8867 10:54:47.091273 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8868 10:54:47.098220 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8869 10:54:47.101487 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8870 10:54:47.104884 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8871 10:54:47.107942 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8872 10:54:47.108364 ==
8873 10:54:47.111244 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 10:54:47.117907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 10:54:47.118335 ==
8876 10:54:47.118672 DQS Delay:
8877 10:54:47.118986 DQS0 = 0, DQS1 = 0
8878 10:54:47.121027 DQM Delay:
8879 10:54:47.121484 DQM0 = 137, DQM1 = 130
8880 10:54:47.124253 DQ Delay:
8881 10:54:47.128014 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8882 10:54:47.130910 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8883 10:54:47.134328 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8884 10:54:47.137547 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8885 10:54:47.137969
8886 10:54:47.138302
8887 10:54:47.138612 ==
8888 10:54:47.140992 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 10:54:47.144435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 10:54:47.147500 ==
8891 10:54:47.147920
8892 10:54:47.148299
8893 10:54:47.148637 TX Vref Scan disable
8894 10:54:47.151061 == TX Byte 0 ==
8895 10:54:47.154445 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8896 10:54:47.157572 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8897 10:54:47.160856 == TX Byte 1 ==
8898 10:54:47.164501 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 10:54:47.167517 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 10:54:47.170935 ==
8901 10:54:47.171327 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 10:54:47.177227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 10:54:47.177682 ==
8904 10:54:47.190562
8905 10:54:47.193481 TX Vref early break, caculate TX vref
8906 10:54:47.196726 TX Vref=16, minBit 10, minWin=22, winSum=380
8907 10:54:47.200310 TX Vref=18, minBit 9, minWin=22, winSum=390
8908 10:54:47.203408 TX Vref=20, minBit 8, minWin=23, winSum=395
8909 10:54:47.206939 TX Vref=22, minBit 9, minWin=23, winSum=406
8910 10:54:47.213304 TX Vref=24, minBit 11, minWin=24, winSum=416
8911 10:54:47.216553 TX Vref=26, minBit 9, minWin=25, winSum=423
8912 10:54:47.219778 TX Vref=28, minBit 0, minWin=25, winSum=421
8913 10:54:47.223034 TX Vref=30, minBit 10, minWin=24, winSum=418
8914 10:54:47.226333 TX Vref=32, minBit 10, minWin=24, winSum=408
8915 10:54:47.229738 TX Vref=34, minBit 0, minWin=24, winSum=401
8916 10:54:47.236319 TX Vref=36, minBit 9, minWin=22, winSum=389
8917 10:54:47.239757 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 26
8918 10:54:47.239831
8919 10:54:47.243061 Final TX Range 0 Vref 26
8920 10:54:47.243164
8921 10:54:47.243248 ==
8922 10:54:47.246330 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 10:54:47.249508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 10:54:47.252852 ==
8925 10:54:47.252933
8926 10:54:47.252997
8927 10:54:47.253056 TX Vref Scan disable
8928 10:54:47.259807 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8929 10:54:47.259901 == TX Byte 0 ==
8930 10:54:47.263301 u2DelayCellOfst[0]=13 cells (4 PI)
8931 10:54:47.266526 u2DelayCellOfst[1]=6 cells (2 PI)
8932 10:54:47.269660 u2DelayCellOfst[2]=0 cells (0 PI)
8933 10:54:47.272954 u2DelayCellOfst[3]=6 cells (2 PI)
8934 10:54:47.276458 u2DelayCellOfst[4]=6 cells (2 PI)
8935 10:54:47.279655 u2DelayCellOfst[5]=16 cells (5 PI)
8936 10:54:47.282996 u2DelayCellOfst[6]=16 cells (5 PI)
8937 10:54:47.286094 u2DelayCellOfst[7]=3 cells (1 PI)
8938 10:54:47.289482 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8939 10:54:47.292940 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 10:54:47.296319 == TX Byte 1 ==
8941 10:54:47.299580 u2DelayCellOfst[8]=0 cells (0 PI)
8942 10:54:47.302877 u2DelayCellOfst[9]=6 cells (2 PI)
8943 10:54:47.306003 u2DelayCellOfst[10]=10 cells (3 PI)
8944 10:54:47.309641 u2DelayCellOfst[11]=3 cells (1 PI)
8945 10:54:47.312361 u2DelayCellOfst[12]=13 cells (4 PI)
8946 10:54:47.315581 u2DelayCellOfst[13]=16 cells (5 PI)
8947 10:54:47.318841 u2DelayCellOfst[14]=20 cells (6 PI)
8948 10:54:47.322460 u2DelayCellOfst[15]=20 cells (6 PI)
8949 10:54:47.325337 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8950 10:54:47.328725 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8951 10:54:47.332051 DramC Write-DBI on
8952 10:54:47.332133 ==
8953 10:54:47.335682 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 10:54:47.338702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 10:54:47.338790 ==
8956 10:54:47.338860
8957 10:54:47.338924
8958 10:54:47.342115 TX Vref Scan disable
8959 10:54:47.342221 == TX Byte 0 ==
8960 10:54:47.348957 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8961 10:54:47.349126 == TX Byte 1 ==
8962 10:54:47.352475 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8963 10:54:47.355293 DramC Write-DBI off
8964 10:54:47.355494
8965 10:54:47.355616 [DATLAT]
8966 10:54:47.358419 Freq=1600, CH1 RK1
8967 10:54:47.358579
8968 10:54:47.358692 DATLAT Default: 0xf
8969 10:54:47.361887 0, 0xFFFF, sum = 0
8970 10:54:47.365282 1, 0xFFFF, sum = 0
8971 10:54:47.365483 2, 0xFFFF, sum = 0
8972 10:54:47.368583 3, 0xFFFF, sum = 0
8973 10:54:47.368788 4, 0xFFFF, sum = 0
8974 10:54:47.371850 5, 0xFFFF, sum = 0
8975 10:54:47.372097 6, 0xFFFF, sum = 0
8976 10:54:47.375394 7, 0xFFFF, sum = 0
8977 10:54:47.375655 8, 0xFFFF, sum = 0
8978 10:54:47.378819 9, 0xFFFF, sum = 0
8979 10:54:47.379114 10, 0xFFFF, sum = 0
8980 10:54:47.381886 11, 0xFFFF, sum = 0
8981 10:54:47.382223 12, 0xFFFF, sum = 0
8982 10:54:47.385564 13, 0xFFFF, sum = 0
8983 10:54:47.385900 14, 0x0, sum = 1
8984 10:54:47.388950 15, 0x0, sum = 2
8985 10:54:47.389346 16, 0x0, sum = 3
8986 10:54:47.392304 17, 0x0, sum = 4
8987 10:54:47.392825 best_step = 15
8988 10:54:47.393145
8989 10:54:47.393430 ==
8990 10:54:47.395521 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 10:54:47.402080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 10:54:47.402692 ==
8993 10:54:47.403095 RX Vref Scan: 0
8994 10:54:47.403440
8995 10:54:47.405554 RX Vref 0 -> 0, step: 1
8996 10:54:47.405973
8997 10:54:47.408862 RX Delay 19 -> 252, step: 4
8998 10:54:47.412002 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8999 10:54:47.415228 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9000 10:54:47.418563 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9001 10:54:47.425197 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9002 10:54:47.428451 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9003 10:54:47.432163 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9004 10:54:47.434684 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9005 10:54:47.438310 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9006 10:54:47.441488 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9007 10:54:47.448189 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9008 10:54:47.451779 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9009 10:54:47.454753 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9010 10:54:47.458134 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9011 10:54:47.464583 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9012 10:54:47.468334 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9013 10:54:47.471868 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9014 10:54:47.472439 ==
9015 10:54:47.474808 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 10:54:47.477883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 10:54:47.478423 ==
9018 10:54:47.481602 DQS Delay:
9019 10:54:47.482182 DQS0 = 0, DQS1 = 0
9020 10:54:47.484932 DQM Delay:
9021 10:54:47.485506 DQM0 = 134, DQM1 = 130
9022 10:54:47.485885 DQ Delay:
9023 10:54:47.491553 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
9024 10:54:47.494862 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9025 10:54:47.498054 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9026 10:54:47.501618 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9027 10:54:47.502195
9028 10:54:47.502829
9029 10:54:47.503221
9030 10:54:47.504580 [DramC_TX_OE_Calibration] TA2
9031 10:54:47.508027 Original DQ_B0 (3 6) =30, OEN = 27
9032 10:54:47.511103 Original DQ_B1 (3 6) =30, OEN = 27
9033 10:54:47.511671 24, 0x0, End_B0=24 End_B1=24
9034 10:54:47.514554 25, 0x0, End_B0=25 End_B1=25
9035 10:54:47.517819 26, 0x0, End_B0=26 End_B1=26
9036 10:54:47.520909 27, 0x0, End_B0=27 End_B1=27
9037 10:54:47.524183 28, 0x0, End_B0=28 End_B1=28
9038 10:54:47.524761 29, 0x0, End_B0=29 End_B1=29
9039 10:54:47.527517 30, 0x0, End_B0=30 End_B1=30
9040 10:54:47.531173 31, 0x4141, End_B0=30 End_B1=30
9041 10:54:47.534082 Byte0 end_step=30 best_step=27
9042 10:54:47.537475 Byte1 end_step=30 best_step=27
9043 10:54:47.541220 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 10:54:47.541784 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 10:54:47.542154
9046 10:54:47.542492
9047 10:54:47.550875 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9048 10:54:47.553923 CH1 RK1: MR19=303, MR18=1C06
9049 10:54:47.560647 CH1_RK1: MR19=0x303, MR18=0x1C06, DQSOSC=395, MR23=63, INC=23, DEC=15
9050 10:54:47.561335 [RxdqsGatingPostProcess] freq 1600
9051 10:54:47.567274 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 10:54:47.571033 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 10:54:47.573997 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 10:54:47.577331 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 10:54:47.580264 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 10:54:47.583962 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 10:54:47.587533 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 10:54:47.590692 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 10:54:47.594238 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 10:54:47.594813 Pre-setting of DQS Precalculation
9061 10:54:47.600963 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 10:54:47.606940 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 10:54:47.613626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 10:54:47.614182
9065 10:54:47.614554
9066 10:54:47.616830 [Calibration Summary] 3200 Mbps
9067 10:54:47.620328 CH 0, Rank 0
9068 10:54:47.620939 SW Impedance : PASS
9069 10:54:47.623836 DUTY Scan : NO K
9070 10:54:47.626618 ZQ Calibration : PASS
9071 10:54:47.627187 Jitter Meter : NO K
9072 10:54:47.630090 CBT Training : PASS
9073 10:54:47.633532 Write leveling : PASS
9074 10:54:47.634191 RX DQS gating : PASS
9075 10:54:47.637013 RX DQ/DQS(RDDQC) : PASS
9076 10:54:47.640047 TX DQ/DQS : PASS
9077 10:54:47.640622 RX DATLAT : PASS
9078 10:54:47.643872 RX DQ/DQS(Engine): PASS
9079 10:54:47.646667 TX OE : PASS
9080 10:54:47.647202 All Pass.
9081 10:54:47.647541
9082 10:54:47.647849 CH 0, Rank 1
9083 10:54:47.650016 SW Impedance : PASS
9084 10:54:47.653297 DUTY Scan : NO K
9085 10:54:47.653864 ZQ Calibration : PASS
9086 10:54:47.656382 Jitter Meter : NO K
9087 10:54:47.656919 CBT Training : PASS
9088 10:54:47.659663 Write leveling : PASS
9089 10:54:47.662832 RX DQS gating : PASS
9090 10:54:47.663257 RX DQ/DQS(RDDQC) : PASS
9091 10:54:47.666462 TX DQ/DQS : PASS
9092 10:54:47.669808 RX DATLAT : PASS
9093 10:54:47.670326 RX DQ/DQS(Engine): PASS
9094 10:54:47.672894 TX OE : PASS
9095 10:54:47.673415 All Pass.
9096 10:54:47.673856
9097 10:54:47.675858 CH 1, Rank 0
9098 10:54:47.675940 SW Impedance : PASS
9099 10:54:47.679270 DUTY Scan : NO K
9100 10:54:47.682523 ZQ Calibration : PASS
9101 10:54:47.682610 Jitter Meter : NO K
9102 10:54:47.685939 CBT Training : PASS
9103 10:54:47.689491 Write leveling : PASS
9104 10:54:47.689671 RX DQS gating : PASS
9105 10:54:47.692659 RX DQ/DQS(RDDQC) : PASS
9106 10:54:47.696158 TX DQ/DQS : PASS
9107 10:54:47.696357 RX DATLAT : PASS
9108 10:54:47.699263 RX DQ/DQS(Engine): PASS
9109 10:54:47.702241 TX OE : PASS
9110 10:54:47.702438 All Pass.
9111 10:54:47.702543
9112 10:54:47.702638 CH 1, Rank 1
9113 10:54:47.705625 SW Impedance : PASS
9114 10:54:47.709286 DUTY Scan : NO K
9115 10:54:47.709516 ZQ Calibration : PASS
9116 10:54:47.712706 Jitter Meter : NO K
9117 10:54:47.715808 CBT Training : PASS
9118 10:54:47.716056 Write leveling : PASS
9119 10:54:47.719307 RX DQS gating : PASS
9120 10:54:47.722313 RX DQ/DQS(RDDQC) : PASS
9121 10:54:47.722552 TX DQ/DQS : PASS
9122 10:54:47.725688 RX DATLAT : PASS
9123 10:54:47.726003 RX DQ/DQS(Engine): PASS
9124 10:54:47.729150 TX OE : PASS
9125 10:54:47.729522 All Pass.
9126 10:54:47.729762
9127 10:54:47.732332 DramC Write-DBI on
9128 10:54:47.735799 PER_BANK_REFRESH: Hybrid Mode
9129 10:54:47.736260 TX_TRACKING: ON
9130 10:54:47.746020 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 10:54:47.752503 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 10:54:47.762248 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 10:54:47.765456 [FAST_K] Save calibration result to emmc
9134 10:54:47.768912 sync common calibartion params.
9135 10:54:47.769339 sync cbt_mode0:1, 1:1
9136 10:54:47.772242 dram_init: ddr_geometry: 2
9137 10:54:47.775910 dram_init: ddr_geometry: 2
9138 10:54:47.776440 dram_init: ddr_geometry: 2
9139 10:54:47.778770 0:dram_rank_size:100000000
9140 10:54:47.782216 1:dram_rank_size:100000000
9141 10:54:47.785334 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 10:54:47.788738 DFS_SHUFFLE_HW_MODE: ON
9143 10:54:47.792113 dramc_set_vcore_voltage set vcore to 725000
9144 10:54:47.795594 Read voltage for 1600, 0
9145 10:54:47.796118 Vio18 = 0
9146 10:54:47.798880 Vcore = 725000
9147 10:54:47.799403 Vdram = 0
9148 10:54:47.799743 Vddq = 0
9149 10:54:47.800055 Vmddr = 0
9150 10:54:47.801882 switch to 3200 Mbps bootup
9151 10:54:47.805187 [DramcRunTimeConfig]
9152 10:54:47.805608 PHYPLL
9153 10:54:47.808826 DPM_CONTROL_AFTERK: ON
9154 10:54:47.809248 PER_BANK_REFRESH: ON
9155 10:54:47.812247 REFRESH_OVERHEAD_REDUCTION: ON
9156 10:54:47.815624 CMD_PICG_NEW_MODE: OFF
9157 10:54:47.816144 XRTWTW_NEW_MODE: ON
9158 10:54:47.818876 XRTRTR_NEW_MODE: ON
9159 10:54:47.819405 TX_TRACKING: ON
9160 10:54:47.822282 RDSEL_TRACKING: OFF
9161 10:54:47.825440 DQS Precalculation for DVFS: ON
9162 10:54:47.825864 RX_TRACKING: OFF
9163 10:54:47.828652 HW_GATING DBG: ON
9164 10:54:47.829119 ZQCS_ENABLE_LP4: ON
9165 10:54:47.831890 RX_PICG_NEW_MODE: ON
9166 10:54:47.832381 TX_PICG_NEW_MODE: ON
9167 10:54:47.835322 ENABLE_RX_DCM_DPHY: ON
9168 10:54:47.839016 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 10:54:47.841910 DUMMY_READ_FOR_TRACKING: OFF
9170 10:54:47.842336 !!! SPM_CONTROL_AFTERK: OFF
9171 10:54:47.845622 !!! SPM could not control APHY
9172 10:54:47.848492 IMPEDANCE_TRACKING: ON
9173 10:54:47.849046 TEMP_SENSOR: ON
9174 10:54:47.851906 HW_SAVE_FOR_SR: OFF
9175 10:54:47.854989 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 10:54:47.858453 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 10:54:47.858976 Read ODT Tracking: ON
9178 10:54:47.862057 Refresh Rate DeBounce: ON
9179 10:54:47.865103 DFS_NO_QUEUE_FLUSH: ON
9180 10:54:47.868349 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 10:54:47.868808 ENABLE_DFS_RUNTIME_MRW: OFF
9182 10:54:47.871256 DDR_RESERVE_NEW_MODE: ON
9183 10:54:47.874866 MR_CBT_SWITCH_FREQ: ON
9184 10:54:47.875411 =========================
9185 10:54:47.895152 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 10:54:47.898753 dram_init: ddr_geometry: 2
9187 10:54:47.916673 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 10:54:47.920047 dram_init: dram init end (result: 0)
9189 10:54:47.926955 DRAM-K: Full calibration passed in 24570 msecs
9190 10:54:47.929721 MRC: failed to locate region type 0.
9191 10:54:47.930146 DRAM rank0 size:0x100000000,
9192 10:54:47.933145 DRAM rank1 size=0x100000000
9193 10:54:47.943266 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 10:54:47.949759 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 10:54:47.956190 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 10:54:47.966451 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 10:54:47.966980 DRAM rank0 size:0x100000000,
9198 10:54:47.969645 DRAM rank1 size=0x100000000
9199 10:54:47.970185 CBMEM:
9200 10:54:47.973201 IMD: root @ 0xfffff000 254 entries.
9201 10:54:47.975957 IMD: root @ 0xffffec00 62 entries.
9202 10:54:47.979299 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 10:54:47.986220 WARNING: RO_VPD is uninitialized or empty.
9204 10:54:47.988969 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 10:54:47.996708 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 10:54:48.009290 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9207 10:54:48.020960 BS: romstage times (exec / console): total (unknown) / 24058 ms
9208 10:54:48.021521
9209 10:54:48.021894
9210 10:54:48.030843 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 10:54:48.033815 ARM64: Exception handlers installed.
9212 10:54:48.037662 ARM64: Testing exception
9213 10:54:48.040614 ARM64: Done test exception
9214 10:54:48.041217 Enumerating buses...
9215 10:54:48.044130 Show all devs... Before device enumeration.
9216 10:54:48.047436 Root Device: enabled 1
9217 10:54:48.050457 CPU_CLUSTER: 0: enabled 1
9218 10:54:48.051027 CPU: 00: enabled 1
9219 10:54:48.054196 Compare with tree...
9220 10:54:48.054757 Root Device: enabled 1
9221 10:54:48.057376 CPU_CLUSTER: 0: enabled 1
9222 10:54:48.060647 CPU: 00: enabled 1
9223 10:54:48.061242 Root Device scanning...
9224 10:54:48.063759 scan_static_bus for Root Device
9225 10:54:48.067248 CPU_CLUSTER: 0 enabled
9226 10:54:48.070512 scan_static_bus for Root Device done
9227 10:54:48.073827 scan_bus: bus Root Device finished in 8 msecs
9228 10:54:48.074349 done
9229 10:54:48.080645 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 10:54:48.083726 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 10:54:48.090152 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 10:54:48.093945 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 10:54:48.096941 Allocating resources...
9234 10:54:48.100183 Reading resources...
9235 10:54:48.103577 Root Device read_resources bus 0 link: 0
9236 10:54:48.103997 DRAM rank0 size:0x100000000,
9237 10:54:48.106859 DRAM rank1 size=0x100000000
9238 10:54:48.110094 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 10:54:48.113294 CPU: 00 missing read_resources
9240 10:54:48.120226 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 10:54:48.123285 Root Device read_resources bus 0 link: 0 done
9242 10:54:48.123705 Done reading resources.
9243 10:54:48.130189 Show resources in subtree (Root Device)...After reading.
9244 10:54:48.133125 Root Device child on link 0 CPU_CLUSTER: 0
9245 10:54:48.136378 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 10:54:48.146163 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 10:54:48.146699 CPU: 00
9248 10:54:48.149640 Root Device assign_resources, bus 0 link: 0
9249 10:54:48.152615 CPU_CLUSTER: 0 missing set_resources
9250 10:54:48.159519 Root Device assign_resources, bus 0 link: 0 done
9251 10:54:48.160055 Done setting resources.
9252 10:54:48.166305 Show resources in subtree (Root Device)...After assigning values.
9253 10:54:48.169553 Root Device child on link 0 CPU_CLUSTER: 0
9254 10:54:48.172937 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 10:54:48.182371 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 10:54:48.182890 CPU: 00
9257 10:54:48.185846 Done allocating resources.
9258 10:54:48.192415 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 10:54:48.192970 Enabling resources...
9260 10:54:48.195736 done.
9261 10:54:48.199068 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 10:54:48.202392 Initializing devices...
9263 10:54:48.202970 Root Device init
9264 10:54:48.205585 init hardware done!
9265 10:54:48.206180 0x00000018: ctrlr->caps
9266 10:54:48.208666 52.000 MHz: ctrlr->f_max
9267 10:54:48.212056 0.400 MHz: ctrlr->f_min
9268 10:54:48.212533 0x40ff8080: ctrlr->voltages
9269 10:54:48.215205 sclk: 390625
9270 10:54:48.215628 Bus Width = 1
9271 10:54:48.218723 sclk: 390625
9272 10:54:48.219250 Bus Width = 1
9273 10:54:48.221690 Early init status = 3
9274 10:54:48.225522 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 10:54:48.228488 in-header: 03 fc 00 00 01 00 00 00
9276 10:54:48.232360 in-data: 00
9277 10:54:48.235536 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9278 10:54:48.239589 in-header: 03 fd 00 00 00 00 00 00
9279 10:54:48.242994 in-data:
9280 10:54:48.245749 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9281 10:54:48.250110 in-header: 03 fc 00 00 01 00 00 00
9282 10:54:48.253414 in-data: 00
9283 10:54:48.256434 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9284 10:54:48.261584 in-header: 03 fd 00 00 00 00 00 00
9285 10:54:48.264978 in-data:
9286 10:54:48.268270 [SSUSB] Setting up USB HOST controller...
9287 10:54:48.271812 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9288 10:54:48.274927 [SSUSB] phy power-on done.
9289 10:54:48.278318 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9290 10:54:48.284895 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9291 10:54:48.288102 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9292 10:54:48.294881 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9293 10:54:48.301274 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9294 10:54:48.307995 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9295 10:54:48.314674 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9296 10:54:48.321309 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9297 10:54:48.324540 SPM: binary array size = 0x9dc
9298 10:54:48.328054 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9299 10:54:48.334434 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9300 10:54:48.341418 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9301 10:54:48.347599 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9302 10:54:48.350800 configure_display: Starting display init
9303 10:54:48.384922 anx7625_power_on_init: Init interface.
9304 10:54:48.388531 anx7625_disable_pd_protocol: Disabled PD feature.
9305 10:54:48.392146 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9306 10:54:48.419555 anx7625_start_dp_work: Secure OCM version=00
9307 10:54:48.422437 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9308 10:54:48.437480 sp_tx_get_edid_block: EDID Block = 1
9309 10:54:48.540158 Extracted contents:
9310 10:54:48.543355 header: 00 ff ff ff ff ff ff 00
9311 10:54:48.546500 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9312 10:54:48.550151 version: 01 04
9313 10:54:48.552922 basic params: 95 1f 11 78 0a
9314 10:54:48.556808 chroma info: 76 90 94 55 54 90 27 21 50 54
9315 10:54:48.559854 established: 00 00 00
9316 10:54:48.566261 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9317 10:54:48.572863 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9318 10:54:48.576759 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9319 10:54:48.583058 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9320 10:54:48.589516 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9321 10:54:48.592864 extensions: 00
9322 10:54:48.593370 checksum: fb
9323 10:54:48.593705
9324 10:54:48.599424 Manufacturer: IVO Model 57d Serial Number 0
9325 10:54:48.599942 Made week 0 of 2020
9326 10:54:48.602301 EDID version: 1.4
9327 10:54:48.602815 Digital display
9328 10:54:48.606188 6 bits per primary color channel
9329 10:54:48.608986 DisplayPort interface
9330 10:54:48.609478 Maximum image size: 31 cm x 17 cm
9331 10:54:48.612491 Gamma: 220%
9332 10:54:48.613125 Check DPMS levels
9333 10:54:48.619520 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9334 10:54:48.622316 First detailed timing is preferred timing
9335 10:54:48.622734 Established timings supported:
9336 10:54:48.625491 Standard timings supported:
9337 10:54:48.629087 Detailed timings
9338 10:54:48.632486 Hex of detail: 383680a07038204018303c0035ae10000019
9339 10:54:48.638819 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9340 10:54:48.642301 0780 0798 07c8 0820 hborder 0
9341 10:54:48.645575 0438 043b 0447 0458 vborder 0
9342 10:54:48.648798 -hsync -vsync
9343 10:54:48.649213 Did detailed timing
9344 10:54:48.655617 Hex of detail: 000000000000000000000000000000000000
9345 10:54:48.658819 Manufacturer-specified data, tag 0
9346 10:54:48.662024 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9347 10:54:48.665451 ASCII string: InfoVision
9348 10:54:48.668428 Hex of detail: 000000fe00523134304e574635205248200a
9349 10:54:48.672106 ASCII string: R140NWF5 RH
9350 10:54:48.672652 Checksum
9351 10:54:48.675493 Checksum: 0xfb (valid)
9352 10:54:48.678519 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9353 10:54:48.681787 DSI data_rate: 832800000 bps
9354 10:54:48.688601 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9355 10:54:48.691841 anx7625_parse_edid: pixelclock(138800).
9356 10:54:48.695039 hactive(1920), hsync(48), hfp(24), hbp(88)
9357 10:54:48.698260 vactive(1080), vsync(12), vfp(3), vbp(17)
9358 10:54:48.702002 anx7625_dsi_config: config dsi.
9359 10:54:48.708408 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9360 10:54:48.721842 anx7625_dsi_config: success to config DSI
9361 10:54:48.725197 anx7625_dp_start: MIPI phy setup OK.
9362 10:54:48.728395 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9363 10:54:48.731959 mtk_ddp_mode_set invalid vrefresh 60
9364 10:54:48.735302 main_disp_path_setup
9365 10:54:48.735836 ovl_layer_smi_id_en
9366 10:54:48.738723 ovl_layer_smi_id_en
9367 10:54:48.739146 ccorr_config
9368 10:54:48.739483 aal_config
9369 10:54:48.741638 gamma_config
9370 10:54:48.742081 postmask_config
9371 10:54:48.744893 dither_config
9372 10:54:48.748559 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9373 10:54:48.755149 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9374 10:54:48.758056 Root Device init finished in 552 msecs
9375 10:54:48.761710 CPU_CLUSTER: 0 init
9376 10:54:48.768099 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9377 10:54:48.774820 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9378 10:54:48.775336 APU_MBOX 0x190000b0 = 0x10001
9379 10:54:48.778187 APU_MBOX 0x190001b0 = 0x10001
9380 10:54:48.781490 APU_MBOX 0x190005b0 = 0x10001
9381 10:54:48.784793 APU_MBOX 0x190006b0 = 0x10001
9382 10:54:48.791652 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9383 10:54:48.801114 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9384 10:54:48.813212 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9385 10:54:48.820079 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9386 10:54:48.832022 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9387 10:54:48.840896 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9388 10:54:48.844101 CPU_CLUSTER: 0 init finished in 81 msecs
9389 10:54:48.847462 Devices initialized
9390 10:54:48.850919 Show all devs... After init.
9391 10:54:48.851445 Root Device: enabled 1
9392 10:54:48.854106 CPU_CLUSTER: 0: enabled 1
9393 10:54:48.856962 CPU: 00: enabled 1
9394 10:54:48.860572 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9395 10:54:48.863962 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9396 10:54:48.867284 ELOG: NV offset 0x57f000 size 0x1000
9397 10:54:48.874064 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9398 10:54:48.880276 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9399 10:54:48.883893 ELOG: Event(17) added with size 13 at 2023-06-05 10:54:46 UTC
9400 10:54:48.890075 out: cmd=0x121: 03 db 21 01 00 00 00 00
9401 10:54:48.893799 in-header: 03 e9 00 00 2c 00 00 00
9402 10:54:48.903803 in-data: 76 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 10:54:48.910221 ELOG: Event(A1) added with size 10 at 2023-06-05 10:54:46 UTC
9404 10:54:48.916621 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9405 10:54:48.923422 ELOG: Event(A0) added with size 9 at 2023-06-05 10:54:46 UTC
9406 10:54:48.926698 elog_add_boot_reason: Logged dev mode boot
9407 10:54:48.933326 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9408 10:54:48.933863 Finalize devices...
9409 10:54:48.936197 Devices finalized
9410 10:54:48.940063 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9411 10:54:48.943347 Writing coreboot table at 0xffe64000
9412 10:54:48.946551 0. 000000000010a000-0000000000113fff: RAMSTAGE
9413 10:54:48.952996 1. 0000000040000000-00000000400fffff: RAM
9414 10:54:48.956685 2. 0000000040100000-000000004032afff: RAMSTAGE
9415 10:54:48.959864 3. 000000004032b000-00000000545fffff: RAM
9416 10:54:48.962843 4. 0000000054600000-000000005465ffff: BL31
9417 10:54:48.966181 5. 0000000054660000-00000000ffe63fff: RAM
9418 10:54:48.972836 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9419 10:54:48.976322 7. 0000000100000000-000000023fffffff: RAM
9420 10:54:48.979362 Passing 5 GPIOs to payload:
9421 10:54:48.982749 NAME | PORT | POLARITY | VALUE
9422 10:54:48.989526 EC in RW | 0x000000aa | low | undefined
9423 10:54:48.992856 EC interrupt | 0x00000005 | low | undefined
9424 10:54:48.996114 TPM interrupt | 0x000000ab | high | undefined
9425 10:54:49.002641 SD card detect | 0x00000011 | high | undefined
9426 10:54:49.006123 speaker enable | 0x00000093 | high | undefined
9427 10:54:49.009502 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9428 10:54:49.012364 in-header: 03 f9 00 00 02 00 00 00
9429 10:54:49.016262 in-data: 02 00
9430 10:54:49.018962 ADC[4]: Raw value=901770 ID=7
9431 10:54:49.019388 ADC[3]: Raw value=213179 ID=1
9432 10:54:49.022122 RAM Code: 0x71
9433 10:54:49.025645 ADC[6]: Raw value=74502 ID=0
9434 10:54:49.026074 ADC[5]: Raw value=212441 ID=1
9435 10:54:49.028582 SKU Code: 0x1
9436 10:54:49.035420 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9437 10:54:49.035590 coreboot table: 964 bytes.
9438 10:54:49.038434 IMD ROOT 0. 0xfffff000 0x00001000
9439 10:54:49.042047 IMD SMALL 1. 0xffffe000 0x00001000
9440 10:54:49.045297 RO MCACHE 2. 0xffffc000 0x00001104
9441 10:54:49.048551 CONSOLE 3. 0xfff7c000 0x00080000
9442 10:54:49.051980 FMAP 4. 0xfff7b000 0x00000452
9443 10:54:49.055657 TIME STAMP 5. 0xfff7a000 0x00000910
9444 10:54:49.058800 VBOOT WORK 6. 0xfff66000 0x00014000
9445 10:54:49.061804 RAMOOPS 7. 0xffe66000 0x00100000
9446 10:54:49.065158 COREBOOT 8. 0xffe64000 0x00002000
9447 10:54:49.068387 IMD small region:
9448 10:54:49.071729 IMD ROOT 0. 0xffffec00 0x00000400
9449 10:54:49.075275 VPD 1. 0xffffeba0 0x0000004c
9450 10:54:49.079099 MMC STATUS 2. 0xffffeb80 0x00000004
9451 10:54:49.082006 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9452 10:54:49.085190 Probing TPM: done!
9453 10:54:49.089281 Connected to device vid:did:rid of 1ae0:0028:00
9454 10:54:49.099759 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9455 10:54:49.102941 Initialized TPM device CR50 revision 0
9456 10:54:49.106165 Checking cr50 for pending updates
9457 10:54:49.110555 Reading cr50 TPM mode
9458 10:54:49.118976 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9459 10:54:49.125694 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9460 10:54:49.165865 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9461 10:54:49.169196 Checking segment from ROM address 0x40100000
9462 10:54:49.172484 Checking segment from ROM address 0x4010001c
9463 10:54:49.179312 Loading segment from ROM address 0x40100000
9464 10:54:49.179862 code (compression=0)
9465 10:54:49.189141 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9466 10:54:49.195739 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9467 10:54:49.196263 it's not compressed!
9468 10:54:49.202290 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9469 10:54:49.208502 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9470 10:54:49.226477 Loading segment from ROM address 0x4010001c
9471 10:54:49.227009 Entry Point 0x80000000
9472 10:54:49.229126 Loaded segments
9473 10:54:49.232633 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9474 10:54:49.239013 Jumping to boot code at 0x80000000(0xffe64000)
9475 10:54:49.245999 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9476 10:54:49.252825 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9477 10:54:49.261020 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9478 10:54:49.264248 Checking segment from ROM address 0x40100000
9479 10:54:49.267389 Checking segment from ROM address 0x4010001c
9480 10:54:49.274189 Loading segment from ROM address 0x40100000
9481 10:54:49.274725 code (compression=1)
9482 10:54:49.280864 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9483 10:54:49.290858 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9484 10:54:49.291396 using LZMA
9485 10:54:49.298751 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9486 10:54:49.305214 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9487 10:54:49.308795 Loading segment from ROM address 0x4010001c
9488 10:54:49.309346 Entry Point 0x54601000
9489 10:54:49.311999 Loaded segments
9490 10:54:49.315044 NOTICE: MT8192 bl31_setup
9491 10:54:49.322626 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9492 10:54:49.325724 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9493 10:54:49.329170 WARNING: region 0:
9494 10:54:49.332836 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 10:54:49.333452 WARNING: region 1:
9496 10:54:49.338974 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9497 10:54:49.342477 WARNING: region 2:
9498 10:54:49.345961 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9499 10:54:49.349364 WARNING: region 3:
9500 10:54:49.352462 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 10:54:49.355784 WARNING: region 4:
9502 10:54:49.362493 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 10:54:49.363036 WARNING: region 5:
9504 10:54:49.365607 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 10:54:49.369185 WARNING: region 6:
9506 10:54:49.372445 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 10:54:49.375551 WARNING: region 7:
9508 10:54:49.378892 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 10:54:49.385630 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9510 10:54:49.388759 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9511 10:54:49.392243 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9512 10:54:49.398731 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9513 10:54:49.401571 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9514 10:54:49.408319 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9515 10:54:49.411863 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9516 10:54:49.415443 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9517 10:54:49.421672 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9518 10:54:49.424964 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9519 10:54:49.431741 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9520 10:54:49.434741 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9521 10:54:49.438178 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9522 10:54:49.445099 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9523 10:54:49.448023 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9524 10:54:49.451672 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9525 10:54:49.458151 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9526 10:54:49.461228 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9527 10:54:49.467884 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9528 10:54:49.471529 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9529 10:54:49.474606 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9530 10:54:49.481360 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9531 10:54:49.484530 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9532 10:54:49.487920 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9533 10:54:49.494514 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9534 10:54:49.497637 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9535 10:54:49.504156 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9536 10:54:49.507391 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9537 10:54:49.514296 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9538 10:54:49.517455 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9539 10:54:49.520726 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9540 10:54:49.527172 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9541 10:54:49.530657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9542 10:54:49.533690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9543 10:54:49.540458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9544 10:54:49.543776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9545 10:54:49.546911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9546 10:54:49.550490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9547 10:54:49.557184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9548 10:54:49.560196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9549 10:54:49.563630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9550 10:54:49.567372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9551 10:54:49.573688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9552 10:54:49.577073 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9553 10:54:49.580525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9554 10:54:49.583615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9555 10:54:49.590963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9556 10:54:49.593920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9557 10:54:49.597190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9558 10:54:49.603628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9559 10:54:49.606753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9560 10:54:49.613303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9561 10:54:49.616734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9562 10:54:49.623402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9563 10:54:49.627001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9564 10:54:49.629783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9565 10:54:49.636738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9566 10:54:49.640182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9567 10:54:49.647057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9568 10:54:49.650296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9569 10:54:49.656516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9570 10:54:49.659989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9571 10:54:49.666507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9572 10:54:49.669603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9573 10:54:49.673347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9574 10:54:49.680129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9575 10:54:49.682930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9576 10:54:49.690228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9577 10:54:49.693255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9578 10:54:49.699920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9579 10:54:49.702981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9580 10:54:49.706611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9581 10:54:49.713318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9582 10:54:49.716362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9583 10:54:49.722875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9584 10:54:49.726140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9585 10:54:49.733369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9586 10:54:49.736593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9587 10:54:49.742956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9588 10:54:49.746300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9589 10:54:49.749463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9590 10:54:49.756051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9591 10:54:49.759491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9592 10:54:49.766002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9593 10:54:49.769380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9594 10:54:49.776508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9595 10:54:49.779830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9596 10:54:49.782843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9597 10:54:49.789585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9598 10:54:49.792803 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9599 10:54:49.799279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9600 10:54:49.802885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9601 10:54:49.809295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9602 10:54:49.812589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9603 10:54:49.819088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9604 10:54:49.822705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9605 10:54:49.825662 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9606 10:54:49.829363 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9607 10:54:49.836005 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9608 10:54:49.839049 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9609 10:54:49.842895 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9610 10:54:49.848985 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9611 10:54:49.852274 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9612 10:54:49.855954 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9613 10:54:49.862361 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9614 10:54:49.865666 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9615 10:54:49.872263 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9616 10:54:49.876051 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9617 10:54:49.882410 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9618 10:54:49.885405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9619 10:54:49.889429 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9620 10:54:49.895655 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9621 10:54:49.899150 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9622 10:54:49.902572 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9623 10:54:49.908757 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9624 10:54:49.912335 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9625 10:54:49.915612 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9626 10:54:49.922570 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9627 10:54:49.925508 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9628 10:54:49.929055 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9629 10:54:49.935690 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9630 10:54:49.938586 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9631 10:54:49.942334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9632 10:54:49.945760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9633 10:54:49.952340 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9634 10:54:49.955569 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9635 10:54:49.962194 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9636 10:54:49.965330 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9637 10:54:49.968426 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9638 10:54:49.975348 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9639 10:54:49.978774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9640 10:54:49.985132 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9641 10:54:49.988678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9642 10:54:49.992043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9643 10:54:49.998981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9644 10:54:50.001765 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9645 10:54:50.008484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9646 10:54:50.011734 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9647 10:54:50.015094 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9648 10:54:50.021619 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9649 10:54:50.024721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9650 10:54:50.031880 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9651 10:54:50.034529 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9652 10:54:50.038213 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9653 10:54:50.044676 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9654 10:54:50.048089 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9655 10:54:50.054858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9656 10:54:50.057873 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9657 10:54:50.061224 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9658 10:54:50.067657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9659 10:54:50.071054 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9660 10:54:50.077588 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9661 10:54:50.080952 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9662 10:54:50.084250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9663 10:54:50.091023 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9664 10:54:50.094406 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9665 10:54:50.100910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9666 10:54:50.104219 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9667 10:54:50.107765 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9668 10:54:50.114489 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9669 10:54:50.117472 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9670 10:54:50.120556 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9671 10:54:50.127099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9672 10:54:50.130107 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9673 10:54:50.137175 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9674 10:54:50.140374 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9675 10:54:50.143876 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9676 10:54:50.150216 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9677 10:54:50.153553 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9678 10:54:50.160116 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9679 10:54:50.163307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9680 10:54:50.170051 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9681 10:54:50.173424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9682 10:54:50.176815 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9683 10:54:50.183462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9684 10:54:50.186643 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9685 10:54:50.192301 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9686 10:54:50.195601 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9687 10:54:50.199272 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9688 10:54:50.205722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9689 10:54:50.209145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9690 10:54:50.215598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9691 10:54:50.218604 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9692 10:54:50.222291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9693 10:54:50.228604 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9694 10:54:50.231915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9695 10:54:50.238512 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9696 10:54:50.241638 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9697 10:54:50.245268 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9698 10:54:50.251567 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9699 10:54:50.255172 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9700 10:54:50.261734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9701 10:54:50.264805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9702 10:54:50.271399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9703 10:54:50.274835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9704 10:54:50.277659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9705 10:54:50.284527 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9706 10:54:50.287832 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9707 10:54:50.294238 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9708 10:54:50.297446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9709 10:54:50.304344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9710 10:54:50.307769 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9711 10:54:50.310856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9712 10:54:50.317734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9713 10:54:50.320901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9714 10:54:50.327428 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9715 10:54:50.330487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9716 10:54:50.337419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9717 10:54:50.340491 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9718 10:54:50.343737 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9719 10:54:50.350418 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9720 10:54:50.354000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9721 10:54:50.360684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9722 10:54:50.363886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9723 10:54:50.366997 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9724 10:54:50.373934 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9725 10:54:50.377122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9726 10:54:50.383605 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9727 10:54:50.386910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9728 10:54:50.393475 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9729 10:54:50.397082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9730 10:54:50.400298 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9731 10:54:50.406830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9732 10:54:50.410011 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9733 10:54:50.416982 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9734 10:54:50.420242 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9735 10:54:50.426503 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9736 10:54:50.429848 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9737 10:54:50.433576 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9738 10:54:50.439759 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9739 10:54:50.443317 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9740 10:54:50.446415 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9741 10:54:50.449565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9742 10:54:50.456532 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9743 10:54:50.459640 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9744 10:54:50.463155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9745 10:54:50.469514 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9746 10:54:50.473139 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9747 10:54:50.476312 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9748 10:54:50.482907 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9749 10:54:50.486043 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9750 10:54:50.492777 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9751 10:54:50.496104 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9752 10:54:50.499254 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9753 10:54:50.505685 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9754 10:54:50.509240 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9755 10:54:50.512280 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9756 10:54:50.519249 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9757 10:54:50.522352 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9758 10:54:50.529109 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9759 10:54:50.532369 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9760 10:54:50.535474 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9761 10:54:50.541845 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9762 10:54:50.545155 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9763 10:54:50.548695 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9764 10:54:50.555263 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9765 10:54:50.558333 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9766 10:54:50.565021 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9767 10:54:50.568561 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9768 10:54:50.571740 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9769 10:54:50.578166 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9770 10:54:50.581861 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9771 10:54:50.588144 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9772 10:54:50.591281 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9773 10:54:50.594727 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9774 10:54:50.601802 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9775 10:54:50.604743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9776 10:54:50.608020 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9777 10:54:50.614647 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9778 10:54:50.617841 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9779 10:54:50.621352 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9780 10:54:50.624542 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9781 10:54:50.631154 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9782 10:54:50.634466 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9783 10:54:50.637891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9784 10:54:50.641183 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9785 10:54:50.644555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9786 10:54:50.651110 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9787 10:54:50.654424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9788 10:54:50.657562 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9789 10:54:50.664446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9790 10:54:50.667817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9791 10:54:50.671096 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9792 10:54:50.677579 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9793 10:54:50.681192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9794 10:54:50.687544 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9795 10:54:50.690817 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9796 10:54:50.694232 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9797 10:54:50.700584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9798 10:54:50.704290 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9799 10:54:50.710495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9800 10:54:50.713694 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9801 10:54:50.717331 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9802 10:54:50.724005 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9803 10:54:50.727087 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9804 10:54:50.733713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9805 10:54:50.736989 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9806 10:54:50.743503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9807 10:54:50.747102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9808 10:54:50.750345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9809 10:54:50.757117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9810 10:54:50.760427 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9811 10:54:50.766734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9812 10:54:50.770466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9813 10:54:50.776684 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9814 10:54:50.779899 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9815 10:54:50.783230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9816 10:54:50.790072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9817 10:54:50.793421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9818 10:54:50.799955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9819 10:54:50.803130 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9820 10:54:50.806221 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9821 10:54:50.812736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9822 10:54:50.816319 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9823 10:54:50.822739 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9824 10:54:50.826102 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9825 10:54:50.829249 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9826 10:54:50.835737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9827 10:54:50.839204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9828 10:54:50.845875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9829 10:54:50.849076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9830 10:54:50.856121 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9831 10:54:50.859110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9832 10:54:50.862199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9833 10:54:50.868942 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9834 10:54:50.872240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9835 10:54:50.879147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9836 10:54:50.882190 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9837 10:54:50.888681 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9838 10:54:50.892303 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9839 10:54:50.895663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9840 10:54:50.901944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9841 10:54:50.905069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9842 10:54:50.911983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9843 10:54:50.914964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9844 10:54:50.918709 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9845 10:54:50.924938 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9846 10:54:50.928560 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9847 10:54:50.934960 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9848 10:54:50.938189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9849 10:54:50.941752 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9850 10:54:50.948498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9851 10:54:50.951614 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9852 10:54:50.958664 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9853 10:54:50.961829 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9854 10:54:50.965118 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9855 10:54:50.971753 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9856 10:54:50.975291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9857 10:54:50.981548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9858 10:54:50.985163 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9859 10:54:50.991710 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9860 10:54:50.994983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9861 10:54:51.001780 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9862 10:54:51.005270 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9863 10:54:51.008449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9864 10:54:51.015009 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9865 10:54:51.018149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9866 10:54:51.024807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9867 10:54:51.028218 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9868 10:54:51.034576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9869 10:54:51.037929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9870 10:54:51.041152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9871 10:54:51.047673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9872 10:54:51.050995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9873 10:54:51.057376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9874 10:54:51.060756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9875 10:54:51.067987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9876 10:54:51.070833 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9877 10:54:51.077613 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9878 10:54:51.081187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9879 10:54:51.084108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9880 10:54:51.090649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9881 10:54:51.094388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9882 10:54:51.100813 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9883 10:54:51.103725 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9884 10:54:51.110993 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9885 10:54:51.114115 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9886 10:54:51.117055 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9887 10:54:51.123461 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9888 10:54:51.127039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9889 10:54:51.133874 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9890 10:54:51.136950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9891 10:54:51.143667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9892 10:54:51.146938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9893 10:54:51.153392 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9894 10:54:51.157223 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9895 10:54:51.159932 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9896 10:54:51.167224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9897 10:54:51.169768 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9898 10:54:51.176536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9899 10:54:51.179906 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9900 10:54:51.186875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9901 10:54:51.189958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9902 10:54:51.196741 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9903 10:54:51.199775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9904 10:54:51.202957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9905 10:54:51.209803 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9906 10:54:51.213281 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9907 10:54:51.219593 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9908 10:54:51.222927 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9909 10:54:51.229539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9910 10:54:51.232873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9911 10:54:51.236347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9912 10:54:51.242563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9913 10:54:51.245829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9914 10:54:51.252685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9915 10:54:51.255812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9916 10:54:51.262247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9917 10:54:51.265786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9918 10:54:51.272533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9919 10:54:51.275957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9920 10:54:51.282351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9921 10:54:51.285590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9922 10:54:51.292525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9923 10:54:51.295543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9924 10:54:51.301911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9925 10:54:51.305411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9926 10:54:51.311975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9927 10:54:51.315356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9928 10:54:51.321614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9929 10:54:51.325246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9930 10:54:51.331914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9931 10:54:51.335212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9932 10:54:51.341665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9933 10:54:51.345134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9934 10:54:51.351436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9935 10:54:51.354682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9936 10:54:51.361344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9937 10:54:51.364709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9938 10:54:51.371386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9939 10:54:51.374156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9940 10:54:51.381377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9941 10:54:51.384433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9942 10:54:51.391268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9943 10:54:51.394371 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9944 10:54:51.397662 INFO: [APUAPC] vio 0
9945 10:54:51.400482 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9946 10:54:51.407040 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9947 10:54:51.410573 INFO: [APUAPC] D0_APC_0: 0x400510
9948 10:54:51.413810 INFO: [APUAPC] D0_APC_1: 0x0
9949 10:54:51.414340 INFO: [APUAPC] D0_APC_2: 0x1540
9950 10:54:51.417478 INFO: [APUAPC] D0_APC_3: 0x0
9951 10:54:51.420584 INFO: [APUAPC] D1_APC_0: 0xffffffff
9952 10:54:51.423739 INFO: [APUAPC] D1_APC_1: 0xffffffff
9953 10:54:51.427389 INFO: [APUAPC] D1_APC_2: 0x3fffff
9954 10:54:51.430520 INFO: [APUAPC] D1_APC_3: 0x0
9955 10:54:51.433474 INFO: [APUAPC] D2_APC_0: 0xffffffff
9956 10:54:51.437021 INFO: [APUAPC] D2_APC_1: 0xffffffff
9957 10:54:51.440383 INFO: [APUAPC] D2_APC_2: 0x3fffff
9958 10:54:51.443656 INFO: [APUAPC] D2_APC_3: 0x0
9959 10:54:51.446864 INFO: [APUAPC] D3_APC_0: 0xffffffff
9960 10:54:51.450055 INFO: [APUAPC] D3_APC_1: 0xffffffff
9961 10:54:51.453341 INFO: [APUAPC] D3_APC_2: 0x3fffff
9962 10:54:51.456582 INFO: [APUAPC] D3_APC_3: 0x0
9963 10:54:51.459940 INFO: [APUAPC] D4_APC_0: 0xffffffff
9964 10:54:51.463053 INFO: [APUAPC] D4_APC_1: 0xffffffff
9965 10:54:51.466345 INFO: [APUAPC] D4_APC_2: 0x3fffff
9966 10:54:51.469567 INFO: [APUAPC] D4_APC_3: 0x0
9967 10:54:51.473486 INFO: [APUAPC] D5_APC_0: 0xffffffff
9968 10:54:51.476321 INFO: [APUAPC] D5_APC_1: 0xffffffff
9969 10:54:51.479598 INFO: [APUAPC] D5_APC_2: 0x3fffff
9970 10:54:51.483043 INFO: [APUAPC] D5_APC_3: 0x0
9971 10:54:51.486336 INFO: [APUAPC] D6_APC_0: 0xffffffff
9972 10:54:51.489339 INFO: [APUAPC] D6_APC_1: 0xffffffff
9973 10:54:51.492928 INFO: [APUAPC] D6_APC_2: 0x3fffff
9974 10:54:51.496355 INFO: [APUAPC] D6_APC_3: 0x0
9975 10:54:51.499536 INFO: [APUAPC] D7_APC_0: 0xffffffff
9976 10:54:51.502395 INFO: [APUAPC] D7_APC_1: 0xffffffff
9977 10:54:51.506178 INFO: [APUAPC] D7_APC_2: 0x3fffff
9978 10:54:51.509462 INFO: [APUAPC] D7_APC_3: 0x0
9979 10:54:51.512540 INFO: [APUAPC] D8_APC_0: 0xffffffff
9980 10:54:51.515679 INFO: [APUAPC] D8_APC_1: 0xffffffff
9981 10:54:51.519302 INFO: [APUAPC] D8_APC_2: 0x3fffff
9982 10:54:51.522697 INFO: [APUAPC] D8_APC_3: 0x0
9983 10:54:51.525863 INFO: [APUAPC] D9_APC_0: 0xffffffff
9984 10:54:51.529113 INFO: [APUAPC] D9_APC_1: 0xffffffff
9985 10:54:51.532466 INFO: [APUAPC] D9_APC_2: 0x3fffff
9986 10:54:51.535581 INFO: [APUAPC] D9_APC_3: 0x0
9987 10:54:51.539315 INFO: [APUAPC] D10_APC_0: 0xffffffff
9988 10:54:51.542564 INFO: [APUAPC] D10_APC_1: 0xffffffff
9989 10:54:51.545568 INFO: [APUAPC] D10_APC_2: 0x3fffff
9990 10:54:51.548966 INFO: [APUAPC] D10_APC_3: 0x0
9991 10:54:51.552513 INFO: [APUAPC] D11_APC_0: 0xffffffff
9992 10:54:51.555769 INFO: [APUAPC] D11_APC_1: 0xffffffff
9993 10:54:51.558862 INFO: [APUAPC] D11_APC_2: 0x3fffff
9994 10:54:51.561720 INFO: [APUAPC] D11_APC_3: 0x0
9995 10:54:51.564928 INFO: [APUAPC] D12_APC_0: 0xffffffff
9996 10:54:51.568583 INFO: [APUAPC] D12_APC_1: 0xffffffff
9997 10:54:51.571493 INFO: [APUAPC] D12_APC_2: 0x3fffff
9998 10:54:51.575205 INFO: [APUAPC] D12_APC_3: 0x0
9999 10:54:51.578537 INFO: [APUAPC] D13_APC_0: 0xffffffff
10000 10:54:51.581949 INFO: [APUAPC] D13_APC_1: 0xffffffff
10001 10:54:51.584608 INFO: [APUAPC] D13_APC_2: 0x3fffff
10002 10:54:51.588246 INFO: [APUAPC] D13_APC_3: 0x0
10003 10:54:51.591360 INFO: [APUAPC] D14_APC_0: 0xffffffff
10004 10:54:51.594871 INFO: [APUAPC] D14_APC_1: 0xffffffff
10005 10:54:51.598288 INFO: [APUAPC] D14_APC_2: 0x3fffff
10006 10:54:51.601345 INFO: [APUAPC] D14_APC_3: 0x0
10007 10:54:51.604810 INFO: [APUAPC] D15_APC_0: 0xffffffff
10008 10:54:51.608061 INFO: [APUAPC] D15_APC_1: 0xffffffff
10009 10:54:51.611656 INFO: [APUAPC] D15_APC_2: 0x3fffff
10010 10:54:51.614796 INFO: [APUAPC] D15_APC_3: 0x0
10011 10:54:51.617795 INFO: [APUAPC] APC_CON: 0x4
10012 10:54:51.621186 INFO: [NOCDAPC] D0_APC_0: 0x0
10013 10:54:51.624634 INFO: [NOCDAPC] D0_APC_1: 0x0
10014 10:54:51.627349 INFO: [NOCDAPC] D1_APC_0: 0x0
10015 10:54:51.630948 INFO: [NOCDAPC] D1_APC_1: 0xfff
10016 10:54:51.634632 INFO: [NOCDAPC] D2_APC_0: 0x0
10017 10:54:51.637646 INFO: [NOCDAPC] D2_APC_1: 0xfff
10018 10:54:51.638172 INFO: [NOCDAPC] D3_APC_0: 0x0
10019 10:54:51.640970 INFO: [NOCDAPC] D3_APC_1: 0xfff
10020 10:54:51.644485 INFO: [NOCDAPC] D4_APC_0: 0x0
10021 10:54:51.647789 INFO: [NOCDAPC] D4_APC_1: 0xfff
10022 10:54:51.651477 INFO: [NOCDAPC] D5_APC_0: 0x0
10023 10:54:51.654517 INFO: [NOCDAPC] D5_APC_1: 0xfff
10024 10:54:51.657561 INFO: [NOCDAPC] D6_APC_0: 0x0
10025 10:54:51.660980 INFO: [NOCDAPC] D6_APC_1: 0xfff
10026 10:54:51.663868 INFO: [NOCDAPC] D7_APC_0: 0x0
10027 10:54:51.667189 INFO: [NOCDAPC] D7_APC_1: 0xfff
10028 10:54:51.670799 INFO: [NOCDAPC] D8_APC_0: 0x0
10029 10:54:51.674523 INFO: [NOCDAPC] D8_APC_1: 0xfff
10030 10:54:51.675054 INFO: [NOCDAPC] D9_APC_0: 0x0
10031 10:54:51.677460 INFO: [NOCDAPC] D9_APC_1: 0xfff
10032 10:54:51.680417 INFO: [NOCDAPC] D10_APC_0: 0x0
10033 10:54:51.684393 INFO: [NOCDAPC] D10_APC_1: 0xfff
10034 10:54:51.687447 INFO: [NOCDAPC] D11_APC_0: 0x0
10035 10:54:51.690364 INFO: [NOCDAPC] D11_APC_1: 0xfff
10036 10:54:51.693531 INFO: [NOCDAPC] D12_APC_0: 0x0
10037 10:54:51.696976 INFO: [NOCDAPC] D12_APC_1: 0xfff
10038 10:54:51.700466 INFO: [NOCDAPC] D13_APC_0: 0x0
10039 10:54:51.703686 INFO: [NOCDAPC] D13_APC_1: 0xfff
10040 10:54:51.706961 INFO: [NOCDAPC] D14_APC_0: 0x0
10041 10:54:51.710012 INFO: [NOCDAPC] D14_APC_1: 0xfff
10042 10:54:51.713610 INFO: [NOCDAPC] D15_APC_0: 0x0
10043 10:54:51.717016 INFO: [NOCDAPC] D15_APC_1: 0xfff
10044 10:54:51.719976 INFO: [NOCDAPC] APC_CON: 0x4
10045 10:54:51.723214 INFO: [APUAPC] set_apusys_apc done
10046 10:54:51.723644 INFO: [DEVAPC] devapc_init done
10047 10:54:51.730079 INFO: GICv3 without legacy support detected.
10048 10:54:51.733494 INFO: ARM GICv3 driver initialized in EL3
10049 10:54:51.736748 INFO: Maximum SPI INTID supported: 639
10050 10:54:51.739901 INFO: BL31: Initializing runtime services
10051 10:54:51.746435 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10052 10:54:51.749811 INFO: SPM: enable CPC mode
10053 10:54:51.753340 INFO: mcdi ready for mcusys-off-idle and system suspend
10054 10:54:51.760041 INFO: BL31: Preparing for EL3 exit to normal world
10055 10:54:51.763460 INFO: Entry point address = 0x80000000
10056 10:54:51.766220 INFO: SPSR = 0x8
10057 10:54:51.770783
10058 10:54:51.771355
10059 10:54:51.771729
10060 10:54:51.773583 Starting depthcharge on Spherion...
10061 10:54:51.774054
10062 10:54:51.774421 Wipe memory regions:
10063 10:54:51.774767
10064 10:54:51.777031 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10065 10:54:51.777542 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10066 10:54:51.777966 Setting prompt string to ['asurada:']
10067 10:54:51.778344 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10068 10:54:51.779005 [0x00000040000000, 0x00000054600000)
10069 10:54:51.899342
10070 10:54:51.899908 [0x00000054660000, 0x00000080000000)
10071 10:54:52.160472
10072 10:54:52.161040 [0x000000821a7280, 0x000000ffe64000)
10073 10:54:52.904869
10074 10:54:52.905383 [0x00000100000000, 0x00000240000000)
10075 10:54:54.795612
10076 10:54:54.798647 Initializing XHCI USB controller at 0x11200000.
10077 10:54:55.837012
10078 10:54:55.839958 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10079 10:54:55.840501
10080 10:54:55.840884
10081 10:54:55.841205
10082 10:54:55.841938 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 10:54:55.943160 asurada: tftpboot 192.168.201.1 10591035/tftp-deploy-zdi7ijol/kernel/image.itb 10591035/tftp-deploy-zdi7ijol/kernel/cmdline
10085 10:54:55.943868 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 10:54:55.944382 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10087 10:54:55.949025 tftpboot 192.168.201.1 10591035/tftp-deploy-zdi7ijol/kernel/image.itp-deploy-zdi7ijol/kernel/cmdline
10088 10:54:55.949462
10089 10:54:55.949800 Waiting for link
10090 10:54:56.109639
10091 10:54:56.110177 R8152: Initializing
10092 10:54:56.110523
10093 10:54:56.112854 Version 9 (ocp_data = 6010)
10094 10:54:56.113390
10095 10:54:56.115924 R8152: Done initializing
10096 10:54:56.116471
10097 10:54:56.116853 Adding net device
10098 10:54:58.058089
10099 10:54:58.058589 done.
10100 10:54:58.058928
10101 10:54:58.059242 MAC: 00:e0:4c:72:2d:d6
10102 10:54:58.059554
10103 10:54:58.061466 Sending DHCP discover... done.
10104 10:54:58.061918
10105 10:55:08.425183 Waiting for reply... R8152: Bulk read error 0xffffffbf
10106 10:55:08.425716
10107 10:55:08.428687 Receive failed.
10108 10:55:08.429131
10109 10:55:08.429456 done.
10110 10:55:08.429786
10111 10:55:08.431951 Sending DHCP request... done.
10112 10:55:08.432504
10113 10:55:08.434870 Waiting for reply... done.
10114 10:55:08.435306
10115 10:55:08.438403 My ip is 192.168.201.21
10116 10:55:08.438817
10117 10:55:08.439171 The DHCP server ip is 192.168.201.1
10118 10:55:08.442011
10119 10:55:08.444980 TFTP server IP predefined by user: 192.168.201.1
10120 10:55:08.445425
10121 10:55:08.451399 Bootfile predefined by user: 10591035/tftp-deploy-zdi7ijol/kernel/image.itb
10122 10:55:08.451958
10123 10:55:08.454698 Sending tftp read request... done.
10124 10:55:08.455214
10125 10:55:08.459850 Waiting for the transfer...
10126 10:55:08.460360
10127 10:55:08.759945 00000000 ################################################################
10128 10:55:08.760109
10129 10:55:09.023538 00080000 ################################################################
10130 10:55:09.023674
10131 10:55:09.272856 00100000 ################################################################
10132 10:55:09.272992
10133 10:55:09.520609 00180000 ################################################################
10134 10:55:09.520744
10135 10:55:09.768976 00200000 ################################################################
10136 10:55:09.769110
10137 10:55:10.045739 00280000 ################################################################
10138 10:55:10.045904
10139 10:55:10.295323 00300000 ################################################################
10140 10:55:10.295515
10141 10:55:10.543212 00380000 ################################################################
10142 10:55:10.543350
10143 10:55:10.788724 00400000 ################################################################
10144 10:55:10.788873
10145 10:55:11.040156 00480000 ################################################################
10146 10:55:11.040289
10147 10:55:11.285120 00500000 ################################################################
10148 10:55:11.285273
10149 10:55:11.530128 00580000 ################################################################
10150 10:55:11.530262
10151 10:55:11.774969 00600000 ################################################################
10152 10:55:11.775103
10153 10:55:12.025201 00680000 ################################################################
10154 10:55:12.025329
10155 10:55:12.280247 00700000 ################################################################
10156 10:55:12.280403
10157 10:55:12.538251 00780000 ################################################################
10158 10:55:12.538377
10159 10:55:12.790953 00800000 ################################################################
10160 10:55:12.791127
10161 10:55:13.045432 00880000 ################################################################
10162 10:55:13.045564
10163 10:55:13.295438 00900000 ################################################################
10164 10:55:13.295571
10165 10:55:13.543941 00980000 ################################################################
10166 10:55:13.544077
10167 10:55:13.792195 00a00000 ################################################################
10168 10:55:13.792341
10169 10:55:14.052041 00a80000 ################################################################
10170 10:55:14.052175
10171 10:55:14.316072 00b00000 ################################################################
10172 10:55:14.316205
10173 10:55:14.575804 00b80000 ################################################################
10174 10:55:14.575934
10175 10:55:14.830979 00c00000 ################################################################
10176 10:55:14.831144
10177 10:55:15.078447 00c80000 ################################################################
10178 10:55:15.078605
10179 10:55:15.327553 00d00000 ################################################################
10180 10:55:15.327688
10181 10:55:15.583141 00d80000 ################################################################
10182 10:55:15.583298
10183 10:55:15.844172 00e00000 ################################################################
10184 10:55:15.844369
10185 10:55:16.104993 00e80000 ################################################################
10186 10:55:16.105123
10187 10:55:16.383902 00f00000 ################################################################
10188 10:55:16.384030
10189 10:55:16.660127 00f80000 ################################################################
10190 10:55:16.660256
10191 10:55:16.949775 01000000 ################################################################
10192 10:55:16.949906
10193 10:55:17.210523 01080000 ################################################################
10194 10:55:17.210677
10195 10:55:17.474375 01100000 ################################################################
10196 10:55:17.474502
10197 10:55:17.722996 01180000 ################################################################
10198 10:55:17.723122
10199 10:55:17.983684 01200000 ################################################################
10200 10:55:17.983811
10201 10:55:18.280060 01280000 ################################################################
10202 10:55:18.280187
10203 10:55:18.545827 01300000 ################################################################
10204 10:55:18.545954
10205 10:55:18.794941 01380000 ################################################################
10206 10:55:18.795072
10207 10:55:19.074313 01400000 ################################################################
10208 10:55:19.074438
10209 10:55:19.370484 01480000 ################################################################
10210 10:55:19.370614
10211 10:55:19.653365 01500000 ################################################################
10212 10:55:19.653495
10213 10:55:19.903245 01580000 ################################################################
10214 10:55:19.903376
10215 10:55:20.187571 01600000 ################################################################
10216 10:55:20.187703
10217 10:55:20.484650 01680000 ################################################################
10218 10:55:20.484784
10219 10:55:20.746934 01700000 ################################################################
10220 10:55:20.747064
10221 10:55:21.027935 01780000 ################################################################
10222 10:55:21.028067
10223 10:55:21.292506 01800000 ################################################################
10224 10:55:21.292639
10225 10:55:21.574000 01880000 ################################################################
10226 10:55:21.574131
10227 10:55:21.859449 01900000 ################################################################
10228 10:55:21.859582
10229 10:55:22.152296 01980000 ################################################################
10230 10:55:22.152426
10231 10:55:22.441795 01a00000 ################################################################
10232 10:55:22.441923
10233 10:55:22.719745 01a80000 ################################################################
10234 10:55:22.719900
10235 10:55:23.010513 01b00000 ################################################################
10236 10:55:23.010637
10237 10:55:23.302339 01b80000 ################################################################
10238 10:55:23.302461
10239 10:55:23.594859 01c00000 ################################################################
10240 10:55:23.594986
10241 10:55:23.890004 01c80000 ################################################################
10242 10:55:23.890138
10243 10:55:24.177603 01d00000 ################################################################
10244 10:55:24.177733
10245 10:55:24.398926 01d80000 ##################################################### done.
10246 10:55:24.399069
10247 10:55:24.402351 The bootfile was 31359910 bytes long.
10248 10:55:24.402443
10249 10:55:24.405518 Sending tftp read request... done.
10250 10:55:24.405614
10251 10:55:24.408669 Waiting for the transfer...
10252 10:55:24.408801
10253 10:55:24.408898 00000000 # done.
10254 10:55:24.408979
10255 10:55:24.415692 Command line loaded dynamically from TFTP file: 10591035/tftp-deploy-zdi7ijol/kernel/cmdline
10256 10:55:24.418489
10257 10:55:24.428406 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10258 10:55:24.428630
10259 10:55:24.428759 Loading FIT.
10260 10:55:24.428920
10261 10:55:24.431565 Image ramdisk-1 has 21229014 bytes.
10262 10:55:24.431737
10263 10:55:24.434692 Image fdt-1 has 46924 bytes.
10264 10:55:24.434848
10265 10:55:24.438187 Image kernel-1 has 10081937 bytes.
10266 10:55:24.438451
10267 10:55:24.448406 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 10:55:24.448742
10269 10:55:24.464944 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 10:55:24.465539
10271 10:55:24.471897 Choosing best match conf-1 for compat google,spherion-rev2.
10272 10:55:24.472464
10273 10:55:24.478272 Connected to device vid:did:rid of 1ae0:0028:00
10274 10:55:24.486109
10275 10:55:24.489717 tpm_get_response: command 0x17b, return code 0x0
10276 10:55:24.490288
10277 10:55:24.492988 ec_init: CrosEC protocol v3 supported (256, 248)
10278 10:55:24.496606
10279 10:55:24.499823 tpm_cleanup: add release locality here.
10280 10:55:24.500421
10281 10:55:24.500841 Shutting down all USB controllers.
10282 10:55:24.503124
10283 10:55:24.503597 Removing current net device
10284 10:55:24.503975
10285 10:55:24.509763 Exiting depthcharge with code 4 at timestamp: 62105480
10286 10:55:24.510235
10287 10:55:24.513263 LZMA decompressing kernel-1 to 0x821a6718
10288 10:55:24.513836
10289 10:55:24.516479 LZMA decompressing kernel-1 to 0x40000000
10290 10:55:25.782416
10291 10:55:25.782631 jumping to kernel
10292 10:55:25.783186 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10293 10:55:25.783350 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10294 10:55:25.783477 Setting prompt string to ['Linux version [0-9]']
10295 10:55:25.783587 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 10:55:25.783697 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 10:55:25.865239
10298 10:55:25.868349 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 10:55:25.872212 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10300 10:55:25.872846 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 10:55:25.873409 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10302 10:55:25.873848 Using line separator: #'\n'#
10303 10:55:25.874200 No login prompt set.
10304 10:55:25.874552 Parsing kernel messages
10305 10:55:25.874861 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10306 10:55:25.875378 [login-action] Waiting for messages, (timeout 00:03:51)
10307 10:55:25.891082 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10308 10:55:25.894608 [ 0.000000] random: crng init done
10309 10:55:25.901415 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10310 10:55:25.904650 [ 0.000000] efi: UEFI not found.
10311 10:55:25.910887 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10312 10:55:25.917608 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10313 10:55:25.928076 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10314 10:55:25.937680 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10315 10:55:25.944462 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 10:55:25.950831 [ 0.000000] printk: bootconsole [mtk8250] enabled
10317 10:55:25.957769 [ 0.000000] NUMA: No NUMA configuration found
10318 10:55:25.964040 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 10:55:25.967633 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10320 10:55:25.970483 [ 0.000000] Zone ranges:
10321 10:55:25.977243 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 10:55:25.980362 [ 0.000000] DMA32 empty
10323 10:55:25.986826 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 10:55:25.990340 [ 0.000000] Movable zone start for each node
10325 10:55:25.993568 [ 0.000000] Early memory node ranges
10326 10:55:25.999797 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 10:55:26.006615 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 10:55:26.013026 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 10:55:26.019838 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 10:55:26.026347 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 10:55:26.032474 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 10:55:26.088272 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 10:55:26.094774 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 10:55:26.101317 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10335 10:55:26.104677 [ 0.000000] psci: probing for conduit method from DT.
10336 10:55:26.111195 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 10:55:26.114890 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 10:55:26.120949 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 10:55:26.124415 [ 0.000000] psci: SMC Calling Convention v1.2
10340 10:55:26.130885 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10341 10:55:26.134245 [ 0.000000] Detected VIPT I-cache on CPU0
10342 10:55:26.140918 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 10:55:26.147391 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 10:55:26.154297 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 10:55:26.160692 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 10:55:26.170584 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10347 10:55:26.177606 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10348 10:55:26.181098 [ 0.000000] alternatives: applying boot alternatives
10349 10:55:26.187405 [ 0.000000] Fallback order for Node 0: 0
10350 10:55:26.194006 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10351 10:55:26.197014 [ 0.000000] Policy zone: Normal
10352 10:55:26.207184 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10353 10:55:26.220153 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10354 10:55:26.230447 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10355 10:55:26.240577 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10356 10:55:26.246868 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10357 10:55:26.250203 <6>[ 0.000000] software IO TLB: area num 8.
10358 10:55:26.307263 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10359 10:55:26.456144 <6>[ 0.000000] Memory: 7952212K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400556K reserved, 32768K cma-reserved)
10360 10:55:26.462857 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10361 10:55:26.469678 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10362 10:55:26.473046 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10363 10:55:26.479616 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10364 10:55:26.486138 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10365 10:55:26.489244 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10366 10:55:26.499346 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10367 10:55:26.505749 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10368 10:55:26.511790 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10369 10:55:26.518813 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10370 10:55:26.522037 <6>[ 0.000000] GICv3: 608 SPIs implemented
10371 10:55:26.525199 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10372 10:55:26.532313 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10373 10:55:26.535198 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10374 10:55:26.542335 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10375 10:55:26.555202 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10376 10:55:26.568035 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10377 10:55:26.574966 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10378 10:55:26.582659 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10379 10:55:26.596245 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10380 10:55:26.602477 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10381 10:55:26.609382 <6>[ 0.009179] Console: colour dummy device 80x25
10382 10:55:26.619047 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10383 10:55:26.625695 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10384 10:55:26.628873 <6>[ 0.029316] LSM: Security Framework initializing
10385 10:55:26.635651 <6>[ 0.034256] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 10:55:26.645821 <6>[ 0.042071] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 10:55:26.655811 <6>[ 0.051551] cblist_init_generic: Setting adjustable number of callback queues.
10388 10:55:26.659303 <6>[ 0.059049] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 10:55:26.665580 <6>[ 0.065387] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 10:55:26.671790 <6>[ 0.071796] rcu: Hierarchical SRCU implementation.
10391 10:55:26.678741 <6>[ 0.076810] rcu: Max phase no-delay instances is 1000.
10392 10:55:26.685179 <6>[ 0.083834] EFI services will not be available.
10393 10:55:26.688339 <6>[ 0.088806] smp: Bringing up secondary CPUs ...
10394 10:55:26.696247 <6>[ 0.093861] Detected VIPT I-cache on CPU1
10395 10:55:26.703193 <6>[ 0.093932] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10396 10:55:26.709463 <6>[ 0.093963] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10397 10:55:26.712704 <6>[ 0.094299] Detected VIPT I-cache on CPU2
10398 10:55:26.723243 <6>[ 0.094351] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10399 10:55:26.729611 <6>[ 0.094368] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10400 10:55:26.732574 <6>[ 0.094628] Detected VIPT I-cache on CPU3
10401 10:55:26.739130 <6>[ 0.094676] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10402 10:55:26.746530 <6>[ 0.094690] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10403 10:55:26.749494 <6>[ 0.094998] CPU features: detected: Spectre-v4
10404 10:55:26.756017 <6>[ 0.095004] CPU features: detected: Spectre-BHB
10405 10:55:26.759338 <6>[ 0.095010] Detected PIPT I-cache on CPU4
10406 10:55:26.765828 <6>[ 0.095069] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10407 10:55:26.772125 <6>[ 0.095086] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10408 10:55:26.778752 <6>[ 0.095383] Detected PIPT I-cache on CPU5
10409 10:55:26.785638 <6>[ 0.095447] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10410 10:55:26.792011 <6>[ 0.095463] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10411 10:55:26.795168 <6>[ 0.095746] Detected PIPT I-cache on CPU6
10412 10:55:26.801879 <6>[ 0.095811] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10413 10:55:26.808518 <6>[ 0.095827] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10414 10:55:26.815011 <6>[ 0.096130] Detected PIPT I-cache on CPU7
10415 10:55:26.821741 <6>[ 0.096195] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10416 10:55:26.828640 <6>[ 0.096212] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10417 10:55:26.831941 <6>[ 0.096260] smp: Brought up 1 node, 8 CPUs
10418 10:55:26.838342 <6>[ 0.237529] SMP: Total of 8 processors activated.
10419 10:55:26.841530 <6>[ 0.242449] CPU features: detected: 32-bit EL0 Support
10420 10:55:26.851706 <6>[ 0.247845] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 10:55:26.858386 <6>[ 0.256700] CPU features: detected: Common not Private translations
10422 10:55:26.865009 <6>[ 0.263175] CPU features: detected: CRC32 instructions
10423 10:55:26.871375 <6>[ 0.268559] CPU features: detected: RCpc load-acquire (LDAPR)
10424 10:55:26.874445 <6>[ 0.274519] CPU features: detected: LSE atomic instructions
10425 10:55:26.881393 <6>[ 0.280336] CPU features: detected: Privileged Access Never
10426 10:55:26.887690 <6>[ 0.286115] CPU features: detected: RAS Extension Support
10427 10:55:26.894683 <6>[ 0.291724] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 10:55:26.897732 <6>[ 0.298945] CPU: All CPU(s) started at EL2
10429 10:55:26.904245 <6>[ 0.303261] alternatives: applying system-wide alternatives
10430 10:55:26.913976 <6>[ 0.313929] devtmpfs: initialized
10431 10:55:26.929321 <6>[ 0.322716] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10432 10:55:26.936323 <6>[ 0.332679] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10433 10:55:26.942402 <6>[ 0.340901] pinctrl core: initialized pinctrl subsystem
10434 10:55:26.946248 <6>[ 0.347554] DMI not present or invalid.
10435 10:55:26.952106 <6>[ 0.351960] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10436 10:55:26.962296 <6>[ 0.358838] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10437 10:55:26.968692 <6>[ 0.366418] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10438 10:55:26.978484 <6>[ 0.374645] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10439 10:55:26.985023 <6>[ 0.382889] audit: initializing netlink subsys (disabled)
10440 10:55:26.991725 <5>[ 0.388585] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10441 10:55:26.998170 <6>[ 0.389299] thermal_sys: Registered thermal governor 'step_wise'
10442 10:55:27.004872 <6>[ 0.396550] thermal_sys: Registered thermal governor 'power_allocator'
10443 10:55:27.008389 <6>[ 0.402806] cpuidle: using governor menu
10444 10:55:27.014625 <6>[ 0.413762] NET: Registered PF_QIPCRTR protocol family
10445 10:55:27.021651 <6>[ 0.419238] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10446 10:55:27.028176 <6>[ 0.426340] ASID allocator initialised with 32768 entries
10447 10:55:27.031364 <6>[ 0.432913] Serial: AMBA PL011 UART driver
10448 10:55:27.041845 <4>[ 0.441601] Trying to register duplicate clock ID: 134
10449 10:55:27.095312 <6>[ 0.498813] KASLR enabled
10450 10:55:27.109806 <6>[ 0.506491] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10451 10:55:27.116434 <6>[ 0.513502] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10452 10:55:27.122962 <6>[ 0.519993] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10453 10:55:27.129621 <6>[ 0.526998] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10454 10:55:27.136333 <6>[ 0.533485] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10455 10:55:27.143172 <6>[ 0.540487] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10456 10:55:27.149605 <6>[ 0.546975] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10457 10:55:27.156296 <6>[ 0.553979] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10458 10:55:27.159744 <6>[ 0.561346] ACPI: Interpreter disabled.
10459 10:55:27.167908 <6>[ 0.567766] iommu: Default domain type: Translated
10460 10:55:27.174510 <6>[ 0.572877] iommu: DMA domain TLB invalidation policy: strict mode
10461 10:55:27.177627 <5>[ 0.579536] SCSI subsystem initialized
10462 10:55:27.184433 <6>[ 0.583775] usbcore: registered new interface driver usbfs
10463 10:55:27.191605 <6>[ 0.589504] usbcore: registered new interface driver hub
10464 10:55:27.194580 <6>[ 0.595058] usbcore: registered new device driver usb
10465 10:55:27.201201 <6>[ 0.601155] pps_core: LinuxPPS API ver. 1 registered
10466 10:55:27.210882 <6>[ 0.606349] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10467 10:55:27.214246 <6>[ 0.615693] PTP clock support registered
10468 10:55:27.217583 <6>[ 0.619931] EDAC MC: Ver: 3.0.0
10469 10:55:27.225332 <6>[ 0.625115] FPGA manager framework
10470 10:55:27.231783 <6>[ 0.628790] Advanced Linux Sound Architecture Driver Initialized.
10471 10:55:27.234858 <6>[ 0.635554] vgaarb: loaded
10472 10:55:27.241402 <6>[ 0.638715] clocksource: Switched to clocksource arch_sys_counter
10473 10:55:27.244696 <5>[ 0.645165] VFS: Disk quotas dquot_6.6.0
10474 10:55:27.251533 <6>[ 0.649354] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10475 10:55:27.254842 <6>[ 0.656543] pnp: PnP ACPI: disabled
10476 10:55:27.263557 <6>[ 0.663252] NET: Registered PF_INET protocol family
10477 10:55:27.273118 <6>[ 0.668856] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10478 10:55:27.284858 <6>[ 0.681152] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10479 10:55:27.294550 <6>[ 0.689966] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10480 10:55:27.301404 <6>[ 0.697936] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10481 10:55:27.307811 <6>[ 0.706634] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10482 10:55:27.319672 <6>[ 0.716372] TCP: Hash tables configured (established 65536 bind 65536)
10483 10:55:27.326355 <6>[ 0.723229] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 10:55:27.333224 <6>[ 0.730427] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 10:55:27.339580 <6>[ 0.738127] NET: Registered PF_UNIX/PF_LOCAL protocol family
10486 10:55:27.345930 <6>[ 0.744296] RPC: Registered named UNIX socket transport module.
10487 10:55:27.349717 <6>[ 0.750451] RPC: Registered udp transport module.
10488 10:55:27.355927 <6>[ 0.755383] RPC: Registered tcp transport module.
10489 10:55:27.362571 <6>[ 0.760313] RPC: Registered tcp NFSv4.1 backchannel transport module.
10490 10:55:27.365868 <6>[ 0.766983] PCI: CLS 0 bytes, default 64
10491 10:55:27.369362 <6>[ 0.771373] Unpacking initramfs...
10492 10:55:27.378848 <6>[ 0.775202] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10493 10:55:27.385724 <6>[ 0.783858] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10494 10:55:27.392718 <6>[ 0.792693] kvm [1]: IPA Size Limit: 40 bits
10495 10:55:27.395881 <6>[ 0.797218] kvm [1]: GICv3: no GICV resource entry
10496 10:55:27.402553 <6>[ 0.802237] kvm [1]: disabling GICv2 emulation
10497 10:55:27.409425 <6>[ 0.806920] kvm [1]: GIC system register CPU interface enabled
10498 10:55:27.412599 <6>[ 0.813086] kvm [1]: vgic interrupt IRQ18
10499 10:55:27.419063 <6>[ 0.817445] kvm [1]: VHE mode initialized successfully
10500 10:55:27.422724 <5>[ 0.823867] Initialise system trusted keyrings
10501 10:55:27.428930 <6>[ 0.828652] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10502 10:55:27.438731 <6>[ 0.838588] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10503 10:55:27.444982 <5>[ 0.844963] NFS: Registering the id_resolver key type
10504 10:55:27.448672 <5>[ 0.850263] Key type id_resolver registered
10505 10:55:27.454777 <5>[ 0.854677] Key type id_legacy registered
10506 10:55:27.461599 <6>[ 0.858969] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10507 10:55:27.468298 <6>[ 0.865891] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10508 10:55:27.474791 <6>[ 0.873588] 9p: Installing v9fs 9p2000 file system support
10509 10:55:27.511888 <5>[ 0.912172] Key type asymmetric registered
10510 10:55:27.515192 <5>[ 0.916503] Asymmetric key parser 'x509' registered
10511 10:55:27.525314 <6>[ 0.921635] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10512 10:55:27.528226 <6>[ 0.929246] io scheduler mq-deadline registered
10513 10:55:27.531646 <6>[ 0.934009] io scheduler kyber registered
10514 10:55:27.550852 <6>[ 0.950939] EINJ: ACPI disabled.
10515 10:55:27.582140 <4>[ 0.976153] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 10:55:27.592035 <4>[ 0.986799] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 10:55:27.606738 <6>[ 1.007206] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10518 10:55:27.614434 <6>[ 1.015042] printk: console [ttyS0] disabled
10519 10:55:27.642396 <6>[ 1.039685] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10520 10:55:27.648951 <6>[ 1.049157] printk: console [ttyS0] enabled
10521 10:55:27.652305 <6>[ 1.049157] printk: console [ttyS0] enabled
10522 10:55:27.658810 <6>[ 1.058054] printk: bootconsole [mtk8250] disabled
10523 10:55:27.662423 <6>[ 1.058054] printk: bootconsole [mtk8250] disabled
10524 10:55:27.669213 <6>[ 1.069044] SuperH (H)SCI(F) driver initialized
10525 10:55:27.672048 <6>[ 1.074311] msm_serial: driver initialized
10526 10:55:27.685894 <6>[ 1.083153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10527 10:55:27.695834 <6>[ 1.091697] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10528 10:55:27.702547 <6>[ 1.100238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10529 10:55:27.712047 <6>[ 1.108871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10530 10:55:27.722000 <6>[ 1.117577] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10531 10:55:27.728987 <6>[ 1.126289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10532 10:55:27.738683 <6>[ 1.134828] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10533 10:55:27.745456 <6>[ 1.143619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10534 10:55:27.755142 <6>[ 1.152161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10535 10:55:27.766874 <6>[ 1.167381] loop: module loaded
10536 10:55:27.773586 <6>[ 1.173363] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10537 10:55:27.796314 <4>[ 1.196670] mtk-pmic-keys: Failed to locate of_node [id: -1]
10538 10:55:27.802879 <6>[ 1.203377] megasas: 07.719.03.00-rc1
10539 10:55:27.812514 <6>[ 1.212959] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10540 10:55:27.821748 <6>[ 1.222096] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10541 10:55:27.838758 <6>[ 1.238680] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10542 10:55:27.899239 <6>[ 1.292547] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10543 10:55:28.262830 <6>[ 1.662561] Freeing initrd memory: 20724K
10544 10:55:28.278445 <6>[ 1.678040] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10545 10:55:28.289035 <6>[ 1.689128] tun: Universal TUN/TAP device driver, 1.6
10546 10:55:28.292616 <6>[ 1.695198] thunder_xcv, ver 1.0
10547 10:55:28.295971 <6>[ 1.698693] thunder_bgx, ver 1.0
10548 10:55:28.299265 <6>[ 1.702196] nicpf, ver 1.0
10549 10:55:28.309620 <6>[ 1.706208] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10550 10:55:28.313328 <6>[ 1.713684] hns3: Copyright (c) 2017 Huawei Corporation.
10551 10:55:28.316449 <6>[ 1.719275] hclge is initializing
10552 10:55:28.323059 <6>[ 1.722856] e1000: Intel(R) PRO/1000 Network Driver
10553 10:55:28.329849 <6>[ 1.727984] e1000: Copyright (c) 1999-2006 Intel Corporation.
10554 10:55:28.332637 <6>[ 1.733996] e1000e: Intel(R) PRO/1000 Network Driver
10555 10:55:28.339201 <6>[ 1.739211] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10556 10:55:28.345782 <6>[ 1.745394] igb: Intel(R) Gigabit Ethernet Network Driver
10557 10:55:28.352789 <6>[ 1.751044] igb: Copyright (c) 2007-2014 Intel Corporation.
10558 10:55:28.359676 <6>[ 1.756880] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10559 10:55:28.365840 <6>[ 1.763398] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10560 10:55:28.369017 <6>[ 1.769860] sky2: driver version 1.30
10561 10:55:28.375712 <6>[ 1.774841] VFIO - User Level meta-driver version: 0.3
10562 10:55:28.382985 <6>[ 1.782996] usbcore: registered new interface driver usb-storage
10563 10:55:28.389416 <6>[ 1.789436] usbcore: registered new device driver onboard-usb-hub
10564 10:55:28.398489 <6>[ 1.798516] mt6397-rtc mt6359-rtc: registered as rtc0
10565 10:55:28.408697 <6>[ 1.803981] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:55:25 UTC (1685962525)
10566 10:55:28.412239 <6>[ 1.813541] i2c_dev: i2c /dev entries driver
10567 10:55:28.428542 <6>[ 1.825258] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10568 10:55:28.435351 <6>[ 1.835254] sdhci: Secure Digital Host Controller Interface driver
10569 10:55:28.442222 <6>[ 1.841692] sdhci: Copyright(c) Pierre Ossman
10570 10:55:28.448554 <6>[ 1.847092] Synopsys Designware Multimedia Card Interface Driver
10571 10:55:28.451984 <6>[ 1.853703] mmc0: CQHCI version 5.10
10572 10:55:28.458105 <6>[ 1.854235] sdhci-pltfm: SDHCI platform and OF driver helper
10573 10:55:28.465317 <6>[ 1.865553] ledtrig-cpu: registered to indicate activity on CPUs
10574 10:55:28.476113 <6>[ 1.872913] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10575 10:55:28.479836 <6>[ 1.880300] usbcore: registered new interface driver usbhid
10576 10:55:28.486034 <6>[ 1.886127] usbhid: USB HID core driver
10577 10:55:28.492831 <6>[ 1.890373] spi_master spi0: will run message pump with realtime priority
10578 10:55:28.538581 <6>[ 1.932129] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10579 10:55:28.558096 <6>[ 1.947829] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10580 10:55:28.561230 <6>[ 1.961396] mmc0: Command Queue Engine enabled
10581 10:55:28.568501 <6>[ 1.962748] cros-ec-spi spi0.0: Chrome EC device registered
10582 10:55:28.575283 <6>[ 1.966133] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10583 10:55:28.578197 <6>[ 1.979443] mmcblk0: mmc0:0001 DA4128 116 GiB
10584 10:55:28.589200 <6>[ 1.989262] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10585 10:55:28.599329 <6>[ 1.989508] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10586 10:55:28.605754 <6>[ 1.996620] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10587 10:55:28.609197 <6>[ 2.006631] NET: Registered PF_PACKET protocol family
10588 10:55:28.616205 <6>[ 2.010381] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10589 10:55:28.619330 <6>[ 2.015156] 9pnet: Installing 9P2000 support
10590 10:55:28.625591 <6>[ 2.020906] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10591 10:55:28.632512 <5>[ 2.024829] Key type dns_resolver registered
10592 10:55:28.636051 <6>[ 2.036273] registered taskstats version 1
10593 10:55:28.642535 <5>[ 2.040727] Loading compiled-in X.509 certificates
10594 10:55:28.678415 <4>[ 2.071667] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 10:55:28.688462 <4>[ 2.082357] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10596 10:55:28.698302 <3>[ 2.095093] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10597 10:55:28.711159 <6>[ 2.110516] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10598 10:55:28.717411 <6>[ 2.117381] xhci-mtk 11200000.usb: xHCI Host Controller
10599 10:55:28.724024 <6>[ 2.122893] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10600 10:55:28.733941 <6>[ 2.130838] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10601 10:55:28.740932 <6>[ 2.140286] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10602 10:55:28.747632 <6>[ 2.146378] xhci-mtk 11200000.usb: xHCI Host Controller
10603 10:55:28.754324 <6>[ 2.151862] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10604 10:55:28.760625 <6>[ 2.159516] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10605 10:55:28.767363 <6>[ 2.167435] hub 1-0:1.0: USB hub found
10606 10:55:28.770550 <6>[ 2.171499] hub 1-0:1.0: 1 port detected
10607 10:55:28.780902 <6>[ 2.175849] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10608 10:55:28.784186 <6>[ 2.184669] hub 2-0:1.0: USB hub found
10609 10:55:28.787684 <6>[ 2.188704] hub 2-0:1.0: 1 port detected
10610 10:55:28.796327 <6>[ 2.195970] mtk-msdc 11f70000.mmc: Got CD GPIO
10611 10:55:28.813889 <6>[ 2.210273] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10612 10:55:28.820426 <6>[ 2.218321] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10613 10:55:28.830230 <4>[ 2.226302] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10614 10:55:28.840077 <6>[ 2.235967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10615 10:55:28.846591 <6>[ 2.244049] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10616 10:55:28.853553 <6>[ 2.252094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10617 10:55:28.863749 <6>[ 2.260012] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10618 10:55:28.870104 <6>[ 2.267833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10619 10:55:28.880461 <6>[ 2.275655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10620 10:55:28.889833 <6>[ 2.286426] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10621 10:55:28.896466 <6>[ 2.294793] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10622 10:55:28.906160 <6>[ 2.303151] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10623 10:55:28.916451 <6>[ 2.311494] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10624 10:55:28.923401 <6>[ 2.319837] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10625 10:55:28.932828 <6>[ 2.328179] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10626 10:55:28.939628 <6>[ 2.336523] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10627 10:55:28.949704 <6>[ 2.344865] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10628 10:55:28.955876 <6>[ 2.353208] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10629 10:55:28.965932 <6>[ 2.361550] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10630 10:55:28.972330 <6>[ 2.369893] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10631 10:55:28.982488 <6>[ 2.378236] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10632 10:55:28.989097 <6>[ 2.386583] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10633 10:55:28.998880 <6>[ 2.394927] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10634 10:55:29.005327 <6>[ 2.403272] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10635 10:55:29.012283 <6>[ 2.412159] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10636 10:55:29.019731 <6>[ 2.419594] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10637 10:55:29.026710 <6>[ 2.426667] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10638 10:55:29.037222 <6>[ 2.433804] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10639 10:55:29.043632 <6>[ 2.441120] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10640 10:55:29.053627 <6>[ 2.448082] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10641 10:55:29.060351 <6>[ 2.457234] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10642 10:55:29.069803 <6>[ 2.466361] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10643 10:55:29.079846 <6>[ 2.475662] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10644 10:55:29.089642 <6>[ 2.485136] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10645 10:55:29.099433 <6>[ 2.494611] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10646 10:55:29.109552 <6>[ 2.503748] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10647 10:55:29.116447 <6>[ 2.513224] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10648 10:55:29.126565 <6>[ 2.522353] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10649 10:55:29.136808 <6>[ 2.531656] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10650 10:55:29.146071 <6>[ 2.541821] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10651 10:55:29.157273 <6>[ 2.553727] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10652 10:55:29.178416 <6>[ 2.575096] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10653 10:55:29.207019 <6>[ 2.606978] hub 2-1:1.0: USB hub found
10654 10:55:29.210135 <6>[ 2.611488] hub 2-1:1.0: 3 ports detected
10655 10:55:29.329828 <6>[ 2.726956] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10656 10:55:29.483639 <6>[ 2.883332] hub 1-1:1.0: USB hub found
10657 10:55:29.486669 <6>[ 2.887704] hub 1-1:1.0: 4 ports detected
10658 10:55:29.561880 <6>[ 2.959227] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10659 10:55:29.806018 <6>[ 3.202955] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10660 10:55:29.937144 <6>[ 3.337531] hub 1-1.4:1.0: USB hub found
10661 10:55:29.940375 <6>[ 3.342063] hub 1-1.4:1.0: 2 ports detected
10662 10:55:30.237951 <6>[ 3.634953] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10663 10:55:30.421735 <6>[ 3.818955] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10664 10:55:41.454366 <6>[ 14.859573] ALSA device list:
10665 10:55:41.460739 <6>[ 14.862826] No soundcards found.
10666 10:55:41.473214 <6>[ 14.875232] Freeing unused kernel memory: 8384K
10667 10:55:41.476359 <6>[ 14.880161] Run /init as init process
10668 10:55:41.503737 Starting syslogd: OK
10669 10:55:41.507925 Starting klogd: OK
10670 10:55:41.517058 Running sysctl: OK
10671 10:55:41.526944 Populating /dev using udev: <30>[ 14.927663] udevd[194]: starting version 3.2.9
10672 10:55:41.533735 <27>[ 14.935555] udevd[194]: specified user 'tss' unknown
10673 10:55:41.540213 <27>[ 14.941063] udevd[194]: specified group 'tss' unknown
10674 10:55:41.546782 <30>[ 14.947541] udevd[195]: starting eudev-3.2.9
10675 10:55:41.575499 <27>[ 14.977710] udevd[195]: specified user 'tss' unknown
10676 10:55:41.582597 <27>[ 14.983105] udevd[195]: specified group 'tss' unknown
10677 10:55:41.780714 <6>[ 15.178984] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10678 10:55:41.795623 <6>[ 15.197088] remoteproc remoteproc0: scp is available
10679 10:55:41.805316 <4>[ 15.202467] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10680 10:55:41.811972 <6>[ 15.212328] remoteproc remoteproc0: powering up scp
10681 10:55:41.821612 <4>[ 15.217485] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10682 10:55:41.828229 <3>[ 15.227316] remoteproc remoteproc0: request_firmware failed: -2
10683 10:55:41.834796 <6>[ 15.229735] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10684 10:55:41.844824 <6>[ 15.241416] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10685 10:55:41.851131 <6>[ 15.250209] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10686 10:55:41.862082 <3>[ 15.260457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 10:55:41.868911 <4>[ 15.263802] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10688 10:55:41.875326 <6>[ 15.267059] mc: Linux media interface: v0.10
10689 10:55:41.881881 <3>[ 15.268621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 10:55:41.888751 <3>[ 15.268631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 10:55:41.898546 <3>[ 15.279192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 10:55:41.905323 <4>[ 15.280686] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10693 10:55:41.914919 <3>[ 15.288598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 10:55:41.917979 <6>[ 15.299718] usbcore: registered new interface driver r8152
10695 10:55:41.928226 <3>[ 15.304760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 10:55:41.934739 <3>[ 15.304770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 10:55:41.944530 <6>[ 15.313410] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10698 10:55:41.951143 <3>[ 15.320460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 10:55:41.958641 <4>[ 15.335899] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10700 10:55:41.965035 <4>[ 15.335899] Fallback method does not support PEC.
10701 10:55:41.971658 <3>[ 15.342255] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 10:55:41.978561 <6>[ 15.342964] videodev: Linux video capture interface: v2.00
10703 10:55:41.988611 <3>[ 15.365748] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 10:55:41.995421 <3>[ 15.371671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 10:55:42.005296 <6>[ 15.379423] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 10:55:42.015333 <6>[ 15.380801] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10707 10:55:42.021749 <6>[ 15.380807] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10708 10:55:42.028641 <6>[ 15.380815] pci_bus 0000:00: root bus resource [bus 00-ff]
10709 10:55:42.035028 <6>[ 15.380823] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10710 10:55:42.045301 <6>[ 15.380829] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10711 10:55:42.051680 <6>[ 15.380875] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10712 10:55:42.058145 <6>[ 15.380895] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10713 10:55:42.061918 <6>[ 15.380973] pci 0000:00:00.0: supports D1 D2
10714 10:55:42.068244 <6>[ 15.380976] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10715 10:55:42.078010 <6>[ 15.382987] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10716 10:55:42.084547 <6>[ 15.383094] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10717 10:55:42.091581 <6>[ 15.383124] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10718 10:55:42.098277 <6>[ 15.383145] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10719 10:55:42.107704 <6>[ 15.383163] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10720 10:55:42.111099 <6>[ 15.383276] pci 0000:01:00.0: supports D1 D2
10721 10:55:42.117815 <6>[ 15.383279] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 10:55:42.124522 <3>[ 15.385455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 10:55:42.134256 <3>[ 15.385462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 10:55:42.140673 <6>[ 15.390978] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10725 10:55:42.147240 <6>[ 15.398807] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10726 10:55:42.154400 <3>[ 15.398986] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10727 10:55:42.163934 <3>[ 15.400424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 10:55:42.170333 <3>[ 15.402380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 10:55:42.180374 <6>[ 15.412430] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10730 10:55:42.186637 <4>[ 15.418451] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10731 10:55:42.196716 <4>[ 15.418462] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10732 10:55:42.203210 <3>[ 15.421430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 10:55:42.213098 <3>[ 15.421437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 10:55:42.219874 <6>[ 15.428301] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10735 10:55:42.230000 <3>[ 15.434037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 10:55:42.236224 <6>[ 15.441170] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10737 10:55:42.242774 <3>[ 15.451062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 10:55:42.252513 <6>[ 15.457330] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10739 10:55:42.259145 <3>[ 15.464850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 10:55:42.269486 <6>[ 15.469325] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 10:55:42.272877 <6>[ 15.478986] r8152 2-1.3:1.0 eth0: v1.12.13
10742 10:55:42.279176 <6>[ 15.484445] pci 0000:00:00.0: PCI bridge to [bus 01]
10743 10:55:42.286071 <6>[ 15.484453] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10744 10:55:42.292491 <3>[ 15.507154] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10745 10:55:42.299079 <6>[ 15.513305] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10746 10:55:42.305701 <3>[ 15.622987] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10747 10:55:42.312288 <6>[ 15.628180] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10748 10:55:42.319207 <3>[ 15.635703] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10749 10:55:42.325575 <6>[ 15.644059] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10750 10:55:42.332376 <6>[ 15.651636] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10751 10:55:42.355387 <6>[ 15.756876] usbcore: registered new interface driver cdc_ether
10752 10:55:42.362771 <6>[ 15.764435] Bluetooth: Core ver 2.22
10753 10:55:42.366071 <6>[ 15.768418] NET: Registered PF_BLUETOOTH protocol family
10754 10:55:42.372455 <6>[ 15.769757] usbcore: registered new interface driver r8153_ecm
10755 10:55:42.379056 <6>[ 15.770569] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10756 10:55:42.388923 <5>[ 15.771539] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10757 10:55:42.402389 <6>[ 15.772144] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10758 10:55:42.405711 <6>[ 15.772306] usbcore: registered new interface driver uvcvideo
10759 10:55:42.412153 <6>[ 15.773999] Bluetooth: HCI device and connection manager initialized
10760 10:55:42.418826 <6>[ 15.796368] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10761 10:55:42.425750 <5>[ 15.796966] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10762 10:55:42.435775 <4>[ 15.797095] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10763 10:55:42.442247 <6>[ 15.797103] cfg80211: failed to load regulatory.db
10764 10:55:42.445607 <6>[ 15.807581] Bluetooth: HCI socket layer initialized
10765 10:55:42.452032 <6>[ 15.819308] remoteproc remoteproc0: powering up scp
10766 10:55:42.455153 <6>[ 15.820191] Bluetooth: L2CAP socket layer initialized
10767 10:55:42.465296 <4>[ 15.826758] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10768 10:55:42.471870 <6>[ 15.833495] Bluetooth: SCO socket layer initialized
10769 10:55:42.478461 <3>[ 15.842359] remoteproc remoteproc0: request_firmware failed: -2
10770 10:55:42.484801 <3>[ 15.884334] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10771 10:55:42.495043 <6>[ 15.896619] usbcore: registered new interface driver btusb
10772 10:55:42.504722 <4>[ 15.897751] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10773 10:55:42.514586 <6>[ 15.901422] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10774 10:55:42.521295 <6>[ 15.901535] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10775 10:55:42.524587 <6>[ 15.918907] mt7921e 0000:01:00.0: ASIC revision: 79610010
10776 10:55:42.531234 <3>[ 15.920342] Bluetooth: hci0: Failed to load firmware file (-2)
10777 10:55:42.537518 <3>[ 15.938331] Bluetooth: hci0: Failed to set up firmware (-2)
10778 10:55:42.547778 <4>[ 15.944162] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10779 10:55:42.627053 <4>[ 16.022444] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 10:55:42.627340 done
10781 10:55:42.647407 Saving random seed: OK
10782 10:55:42.663149 Starting network: OK
10783 10:55:42.700975 Starting dropbear sshd: <6>[ 16.102476] NET: Registered PF_INET6 protocol family
10784 10:55:42.707559 <6>[ 16.109351] Segment Routing with IPv6
10785 10:55:42.710450 <6>[ 16.113312] In-situ OAM (IOAM) with IPv6
10786 10:55:42.714255 OK
10787 10:55:42.727589 /bin/sh: can't access tty; job control turned off
10788 10:55:42.728510 Matched prompt #10: / #
10790 10:55:42.729529 Setting prompt string to ['/ #']
10791 10:55:42.729907 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10793 10:55:42.730736 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10794 10:55:42.731118 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10795 10:55:42.731521 Setting prompt string to ['/ #']
10796 10:55:42.731894 Forcing a shell prompt, looking for ['/ #']
10798 10:55:42.783012 / #
10799 10:55:42.783672 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10800 10:55:42.784205 Waiting using forced prompt support (timeout 00:02:30)
10801 10:55:42.784735 <4>[ 16.137858] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 10:55:42.789924
10803 10:55:42.790955 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10804 10:55:42.791560 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10805 10:55:42.792083 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10806 10:55:42.792571 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10807 10:55:42.793099 end: 2 depthcharge-action (duration 00:01:26) [common]
10808 10:55:42.793587 start: 3 lava-test-retry (timeout 00:01:00) [common]
10809 10:55:42.794074 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10810 10:55:42.794488 Using namespace: common
10812 10:55:42.895664 / # #
10813 10:55:42.896420 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10814 10:55:42.897167 #<4>[ 16.256787] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 10:55:42.902128
10816 10:55:42.902996 Using /lava-10591035
10818 10:55:43.004324 / # export SHELL=/bin/sh
10819 10:55:43.005142 export SHELL=/bin/sh<4>[ 16.373437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 10:55:43.011071
10822 10:55:43.112831 / # . /lava-10591035/environment
10823 10:55:43.113625 . /lava-10591035/environment<4>[ 16.493026] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 10:55:43.119666
10826 10:55:43.221385 / # /lava-10591035/bin/lava-test-runner /lava-10591035/0
10827 10:55:43.222022 Test shell timeout: 10s (minimum of the action and connection timeout)
10828 10:55:43.223655 /lava-10591035/bin/lava-test-runner /lava-10591035/0<4>[ 16.609212] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 10:55:43.228626
10830 10:55:43.273265 + export 'TESTRUN_ID=0_dmesg'
10831 10:55:43.273857 +<8>[ 16.654990] <LAVA_SIGNAL_STARTRUN 0_dmesg 10591035_1.5.2.3.1>
10832 10:55:43.274318 cd /lava-10591035/0/tests/0_dmesg
10833 10:55:43.274676 + cat uuid
10834 10:55:43.275023 + UUID=10591035_1.5.2.3.1
10835 10:55:43.275357 + set +x
10836 10:55:43.275685 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10837 10:55:43.276284 Received signal: <STARTRUN> 0_dmesg 10591035_1.5.2.3.1
10838 10:55:43.276666 Starting test lava.0_dmesg (10591035_1.5.2.3.1)
10839 10:55:43.277156 Skipping test definition patterns.
10840 10:55:43.277733 <8>[ 16.674678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10841 10:55:43.278372 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10843 10:55:43.297217 <8>[ 16.695205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10844 10:55:43.298104 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10846 10:55:43.318214 <8>[ 16.716478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10847 10:55:43.319045 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10849 10:55:43.322222 + set +x
10850 10:55:43.325812 Received signal: <ENDRUN> 0_dmesg 10591035_1.5.2.3.1
10851 10:55:43.326328 Ending use of test pattern.
10852 10:55:43.326697 Ending test lava.0_dmesg (10591035_1.5.2.3.1), duration 0.05
10854 10:55:43.329155 <8>[ 16.727566] <LAVA_SIGNAL_ENDRUN 0_dmesg 10591035_1.5.2.3.1>
10855 10:55:43.338842 <4>[ 16.729456] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 10:55:43.342023 <LAVA_TEST_RUNNER EXIT>
10857 10:55:43.342754 ok: lava_test_shell seems to have completed
10858 10:55:43.343452 alert: pass
crit: pass
emerg: pass
10859 10:55:43.343949 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10860 10:55:43.344443 end: 3 lava-test-retry (duration 00:00:01) [common]
10861 10:55:43.344947 start: 4 lava-test-retry (timeout 00:01:00) [common]
10862 10:55:43.345426 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10863 10:55:43.345793 Using namespace: common
10865 10:55:43.446936 / # #
10866 10:55:43.447548 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10867 10:55:43.448090 Using /lava-10591035
10869 10:55:43.549231 export SHELL=/bin/sh
10870 10:55:43.550214 #<4>[ 16.853055] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10871 10:55:43.550836
10873 10:55:43.652396 / # export SHELL=/bin/sh. /lava-10591035/environment
10874 10:55:43.653315
10875 10:55:43.653772 / # <4>[ 16.973544] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10877 10:55:43.755213 . /lava-10591035/environment/lava-10591035/bin/lava-test-runner /lava-10591035/1
10878 10:55:43.755829 Test shell timeout: 10s (minimum of the action and connection timeout)
10879 10:55:43.756401
10880 10:55:43.756984 / # <4>[ 17.093229] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10881 10:55:43.764512 /lava-10591035/bin/lava-test-runner /lava-10591035/1
10882 10:55:43.805276 + export 'TESTRUN_ID=1_bootrr'
10883 10:55:43.805843 <8>[ 17.186001] <LAVA_SIGNAL_STARTRUN 1_bootrr 10591035_1.5.2.3.5>
10884 10:55:43.806226 + cd /lava-10591035/1/tests/1_bootrr
10885 10:55:43.806580 + cat uuid
10886 10:55:43.806918 + UUID=10591035_1.5.2.3.5
10887 10:55:43.807248 + set +x
10888 10:55:43.807843 Received signal: <STARTRUN> 1_bootrr 10591035_1.5.2.3.5
10889 10:55:43.808195 Starting test lava.1_bootrr (10591035_1.5.2.3.5)
10890 10:55:43.808602 Skipping test definition patterns.
10891 10:55:43.809168 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10591035/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10892 10:55:43.809538 + cd /opt/bootrr/libexec/bootrr
10893 10:55:43.812216 + sh helpers/b<3>[ 17.213210] mt7921e 0000:01:00.0: hardware init failed
10894 10:55:43.816007 ootrr-auto
10895 10:55:43.825220 /lava-10591035/1/../bin/lava-test-ca<8>[ 17.223514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10896 10:55:43.825652 se
10897 10:55:43.826356 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10899 10:55:43.838012 /lava-10591035/1/../bin/lava-test-case
10900 10:55:43.844243 <8>[ 17.242751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10901 10:55:43.845116 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10903 10:55:43.849296 /usr/bin/tpm2_getcap
10904 10:55:43.884714 /lava-10591035/1/../bin/lava-test-case
10905 10:55:43.891075 <8>[ 17.290508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10906 10:55:43.891613 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10908 10:55:43.907193 /lava-10591035/1/../bin/lava-test-case
10909 10:55:43.913827 <8>[ 17.313134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10910 10:55:43.914128 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10912 10:55:43.925945 /lava-10591035/1/../bin/lava-test-case
10913 10:55:43.932410 <8>[ 17.331086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10914 10:55:43.932675 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10916 10:55:43.944248 /lava-10591035/1/../bin/lava-test-case
10917 10:55:43.950729 <8>[ 17.349799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10918 10:55:43.951003 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10920 10:55:43.962729 /lava-10591035/1/../bin/lava-test-case
10921 10:55:43.969199 <8>[ 17.367984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10922 10:55:43.969465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10924 10:55:43.981387 /lava-10591035/1/../bin/lava-test-case
10925 10:55:43.988082 <8>[ 17.386845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10926 10:55:43.988342 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10928 10:55:43.998112 /lava-10591035/1/../bin/lava-test-case
10929 10:55:44.004549 <8>[ 17.403270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10930 10:55:44.004802 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10932 10:55:44.017100 /lava-10591035/1/../bin/lava-test-case
10933 10:55:44.023829 <8>[ 17.422430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10934 10:55:44.024088 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10936 10:55:44.033139 /lava-10591035/1/../bin/lava-test-case
10937 10:55:44.039685 <8>[ 17.438870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10938 10:55:44.039938 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10940 10:55:44.052761 /lava-10591035/1/../bin/lava-test-case
10941 10:55:44.059462 <8>[ 17.457987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10942 10:55:44.059718 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10944 10:55:44.071034 /lava-10591035/1/../bin/lava-test-case
10945 10:55:44.078060 <8>[ 17.477118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10946 10:55:44.078317 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10948 10:55:44.090129 /lava-10591035/1/../bin/lava-test-case
10949 10:55:44.096570 <8>[ 17.495779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10950 10:55:44.096808 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10952 10:55:44.108216 /lava-10591035/1/../bin/lava-test-case
10953 10:55:44.114879 <8>[ 17.514183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10954 10:55:44.115139 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10956 10:55:44.125193 /lava-10591035/1/../bin/lava-test-case
10957 10:55:44.131710 <8>[ 17.530535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10958 10:55:44.131969 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10960 10:55:44.143889 /lava-10591035/1/../bin/lava-test-case
10961 10:55:44.150203 <8>[ 17.549245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10962 10:55:44.150462 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10964 10:55:44.159261 /lava-10591035/1/../bin/lava-test-case
10965 10:55:44.165757 <8>[ 17.564758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10966 10:55:44.166016 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10968 10:55:44.178145 /lava-10591035/1/../bin/lava-test-case
10969 10:55:44.184868 <8>[ 17.583862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10970 10:55:44.185127 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10972 10:55:44.194527 /lava-10591035/1/../bin/lava-test-case
10973 10:55:44.200933 <8>[ 17.599560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10974 10:55:44.201189 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10976 10:55:44.212660 /lava-10591035/1/../bin/lava-test-case
10977 10:55:44.219021 <8>[ 17.617833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10978 10:55:44.219278 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10980 10:55:44.227350 /lava-10591035/1/../bin/lava-test-case
10981 10:55:44.233903 <8>[ 17.632816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10982 10:55:44.234162 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10984 10:55:44.246463 /lava-10591035/1/../bin/lava-test-case
10985 10:55:44.253033 <8>[ 17.651855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10986 10:55:44.253293 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10988 10:55:44.261762 /lava-10591035/1/../bin/lava-test-case
10989 10:55:44.268456 <8>[ 17.667366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10990 10:55:44.268720 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10992 10:55:44.280817 /lava-10591035/1/../bin/lava-test-case
10993 10:55:44.287035 <8>[ 17.686603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10994 10:55:44.287296 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10996 10:55:44.298927 /lava-10591035/1/../bin/lava-test-case
10997 10:55:44.305262 <8>[ 17.704850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10998 10:55:44.305523 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11000 10:55:44.314522 /lava-10591035/1/../bin/lava-test-case
11001 10:55:44.321158 <8>[ 17.720500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11002 10:55:44.321417 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11004 10:55:44.332674 /lava-10591035/1/../bin/lava-test-case
11005 10:55:44.339609 <8>[ 17.739063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11006 10:55:44.339870 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11008 10:55:44.349029 /lava-10591035/1/../bin/lava-test-case
11009 10:55:44.355653 <8>[ 17.754348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11010 10:55:44.355915 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11012 10:55:44.367748 /lava-10591035/1/../bin/lava-test-case
11013 10:55:44.374781 <8>[ 17.773025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11014 10:55:44.375041 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11016 10:55:44.385235 /lava-10591035/1/../bin/lava-test-case
11017 10:55:44.391379 <8>[ 17.790452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11018 10:55:44.391642 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11020 10:55:44.403672 /lava-10591035/1/../bin/lava-test-case
11021 10:55:44.410200 <8>[ 17.808914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11022 10:55:44.410461 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11024 10:55:44.421388 /lava-10591035/1/../bin/lava-test-case
11025 10:55:44.427938 <8>[ 17.826586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11026 10:55:44.428196 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11028 10:55:44.437768 /lava-10591035/1/../bin/lava-test-case
11029 10:55:44.443986 <8>[ 17.843094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11030 10:55:44.444253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11032 10:55:44.455579 /lava-10591035/1/../bin/lava-test-case
11033 10:55:44.462343 <8>[ 17.861176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11034 10:55:44.462602 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11036 10:55:44.473800 /lava-10591035/1/../bin/lava-test-case
11037 10:55:44.480378 <8>[ 17.879284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11038 10:55:44.480636 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11040 10:55:44.489078 /lava-10591035/1/../bin/lava-test-case
11041 10:55:44.495796 <8>[ 17.894907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11042 10:55:44.496057 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11044 10:55:44.508248 /lava-10591035/1/../bin/lava-test-case
11045 10:55:44.514117 <8>[ 17.912882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11046 10:55:44.514465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11048 10:55:44.523457 /lava-10591035/1/../bin/lava-test-case
11049 10:55:44.529970 <8>[ 17.928919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11050 10:55:44.530309 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11052 10:55:44.541545 /lava-10591035/1/../bin/lava-test-case
11053 10:55:44.547898 <8>[ 17.946608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11054 10:55:44.548267 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11056 10:55:44.556572 /lava-10591035/1/../bin/lava-test-case
11057 10:55:44.563383 <8>[ 17.962443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11058 10:55:44.563798 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11060 10:55:44.575568 /lava-10591035/1/../bin/lava-test-case
11061 10:55:44.582372 <8>[ 17.980723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11062 10:55:44.582878 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11064 10:55:44.591407 /lava-10591035/1/../bin/lava-test-case
11065 10:55:44.597912 <8>[ 17.996649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11066 10:55:44.598678 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11068 10:55:44.610315 /lava-10591035/1/../bin/lava-test-case
11069 10:55:44.616706 <8>[ 18.015268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11070 10:55:44.617446 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11072 10:55:44.626137 /lava-10591035/1/../bin/lava-test-case
11073 10:55:44.632458 <8>[ 18.031968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11074 10:55:44.632745 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11076 10:55:44.644950 /lava-10591035/1/../bin/lava-test-case
11077 10:55:44.652055 <8>[ 18.050451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11078 10:55:44.652404 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11080 10:55:44.661149 /lava-10591035/1/../bin/lava-test-case
11081 10:55:44.667399 <8>[ 18.066011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11082 10:55:44.667759 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11084 10:55:44.678841 /lava-10591035/1/../bin/lava-test-case
11085 10:55:44.685233 <8>[ 18.083790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11086 10:55:44.685609 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11088 10:55:44.694076 /lava-10591035/1/../bin/lava-test-case
11089 10:55:44.700453 <8>[ 18.099329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11090 10:55:44.700911 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11092 10:55:44.711883 /lava-10591035/1/../bin/lava-test-case
11093 10:55:44.718734 <8>[ 18.117140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11094 10:55:44.719280 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11096 10:55:44.730685 /lava-10591035/1/../bin/lava-test-case
11097 10:55:44.737411 <8>[ 18.135381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11098 10:55:44.738203 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11100 10:55:45.747628 /lava-10591035/1/../bin/lava-test-case
11101 10:55:45.754366 <8>[ 19.153232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11102 10:55:45.755161 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11104 10:55:46.766219 /lava-10591035/1/../bin/lava-test-case
11105 10:55:46.772416 <8>[ 20.172619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11106 10:55:46.772673 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11107 10:55:46.772759 Bad test result: blocked
11108 10:55:46.782710 /lava-10591035/1/../bin/lava-test-case
11109 10:55:46.789179 <8>[ 20.188309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11110 10:55:46.789509 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11112 10:55:46.801384 /lava-10591035/1/../bin/lava-test-case
11113 10:55:46.808429 <8>[ 20.206928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11114 10:55:46.809287 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11116 10:55:46.818588 /lava-10591035/1/../bin/lava-test-case
11117 10:55:46.825041 <8>[ 20.223872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11118 10:55:46.825777 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11120 10:55:46.836250 /lava-10591035/1/../bin/lava-test-case
11121 10:55:46.842928 <8>[ 20.241339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11122 10:55:46.843715 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11124 10:55:46.854431 /lava-10591035/1/../bin/lava-test-case
11125 10:55:46.861162 <8>[ 20.259588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11126 10:55:46.861942 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11128 10:55:46.871629 /lava-10591035/1/../bin/lava-test-case
11129 10:55:46.877963 <8>[ 20.276740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11130 10:55:46.878744 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11132 10:55:46.887170 /lava-10591035/1/../bin/lava-test-case
11133 10:55:46.893491 <8>[ 20.292526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11134 10:55:46.894170 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11136 10:55:46.905723 /lava-10591035/1/../bin/lava-test-case
11137 10:55:46.912323 <8>[ 20.311020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11138 10:55:46.913121 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11140 10:55:46.923071 /lava-10591035/1/../bin/lava-test-case
11141 10:55:46.930122 <8>[ 20.328785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11142 10:55:46.930898 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11144 10:55:46.939227 /lava-10591035/1/../bin/lava-test-case
11145 10:55:46.945324 <8>[ 20.344635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11146 10:55:46.946117 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11148 10:55:46.957905 /lava-10591035/1/../bin/lava-test-case
11149 10:55:46.964637 <8>[ 20.363263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11150 10:55:46.965446 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11152 10:55:46.973459 /lava-10591035/1/../bin/lava-test-case
11153 10:55:46.980301 <8>[ 20.378599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11154 10:55:46.981109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11156 10:55:46.991818 /lava-10591035/1/../bin/lava-test-case
11157 10:55:46.998529 <8>[ 20.397710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11158 10:55:46.999308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11160 10:55:47.007749 /lava-10591035/1/../bin/lava-test-case
11161 10:55:47.014161 <8>[ 20.413446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11162 10:55:47.014945 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11164 10:55:47.025810 /lava-10591035/1/../bin/lava-test-case
11165 10:55:47.032554 <8>[ 20.431494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11166 10:55:47.033378 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11168 10:55:47.043831 /lava-10591035/1/../bin/lava-test-case
11169 10:55:47.049825 <8>[ 20.449295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11170 10:55:47.050625 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11172 10:55:47.061359 /lava-10591035/1/../bin/lava-test-case
11173 10:55:47.068048 <8>[ 20.466842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11174 10:55:47.068852 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11176 10:55:47.078670 /lava-10591035/1/../bin/lava-test-case
11177 10:55:47.085046 <8>[ 20.484104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11178 10:55:47.085823 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11180 10:55:47.096953 /lava-10591035/1/../bin/lava-test-case
11181 10:55:47.103625 <8>[ 20.502019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11182 10:55:47.104414 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11184 10:55:47.114251 /lava-10591035/1/../bin/lava-test-case
11185 10:55:47.120407 <8>[ 20.519953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11186 10:55:47.121369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11188 10:55:47.131914 /lava-10591035/1/../bin/lava-test-case
11189 10:55:47.138218 <8>[ 20.536818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11190 10:55:47.139000 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11192 10:55:47.148885 /lava-10591035/1/../bin/lava-test-case
11193 10:55:47.155456 <8>[ 20.554646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11194 10:55:47.156278 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11196 10:55:47.166033 /lava-10591035/1/../bin/lava-test-case
11197 10:55:47.172843 <8>[ 20.572166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11198 10:55:47.173657 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11200 10:55:47.183914 /lava-10591035/1/../bin/lava-test-case
11201 10:55:47.190699 <8>[ 20.589448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11202 10:55:47.191492 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11204 10:55:47.201835 /lava-10591035/1/../bin/lava-test-case
11205 10:55:47.208511 <8>[ 20.607783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11206 10:55:47.209345 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11208 10:55:47.220455 /lava-10591035/1/../bin/lava-test-case
11209 10:55:47.226737 <8>[ 20.626162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11210 10:55:47.227480 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11212 10:55:47.238329 /lava-10591035/1/../bin/lava-test-case
11213 10:55:47.245101 <8>[ 20.643710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11214 10:55:47.245890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11216 10:55:47.256288 /lava-10591035/1/../bin/lava-test-case
11217 10:55:47.262701 <8>[ 20.661428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11218 10:55:47.263383 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11220 10:55:47.274502 /lava-10591035/1/../bin/lava-test-case
11221 10:55:47.281239 <8>[ 20.679573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11222 10:55:47.282028 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11224 10:55:47.289526 /lava-10591035/1/../bin/lava-test-case
11225 10:55:47.296388 <8>[ 20.695113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11226 10:55:47.297182 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11228 10:55:47.307433 /lava-10591035/1/../bin/lava-test-case
11229 10:55:47.314132 <8>[ 20.712727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11230 10:55:47.314931 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11232 10:55:47.323382 /lava-10591035/1/../bin/lava-test-case
11233 10:55:47.329774 <8>[ 20.728527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11234 10:55:47.330600 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11236 10:55:47.341038 /lava-10591035/1/../bin/lava-test-case
11237 10:55:47.347471 <8>[ 20.746732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11238 10:55:47.348271 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11240 10:55:47.356383 /lava-10591035/1/../bin/lava-test-case
11241 10:55:47.362780 <8>[ 20.762172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11242 10:55:47.363596 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11244 10:55:47.375341 /lava-10591035/1/../bin/lava-test-case
11245 10:55:47.381602 <8>[ 20.780249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11246 10:55:47.382406 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11248 10:55:47.391665 /lava-10591035/1/../bin/lava-test-case
11249 10:55:47.398180 <8>[ 20.796794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11250 10:55:47.398999 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11252 10:55:47.409618 /lava-10591035/1/../bin/lava-test-case
11253 10:55:47.416573 <8>[ 20.814996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11254 10:55:47.417422 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11256 10:55:47.425456 /lava-10591035/1/../bin/lava-test-case
11257 10:55:47.431886 <8>[ 20.830456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11258 10:55:47.432738 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11260 10:55:47.443910 /lava-10591035/1/../bin/lava-test-case
11261 10:55:47.449993 <8>[ 20.849094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11262 10:55:47.450898 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11264 10:55:47.458841 /lava-10591035/1/../bin/lava-test-case
11265 10:55:47.465188 <8>[ 20.864261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11266 10:55:47.465890 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11268 10:55:47.477946 /lava-10591035/1/../bin/lava-test-case
11269 10:55:47.484469 <8>[ 20.883685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11270 10:55:47.485361 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11272 10:55:47.495715 /lava-10591035/1/../bin/lava-test-case
11273 10:55:47.501968 <8>[ 20.901481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11274 10:55:47.502728 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11276 10:55:47.512492 /lava-10591035/1/../bin/lava-test-case
11277 10:55:47.518652 <8>[ 20.917459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11278 10:55:47.519435 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11280 10:55:47.529835 /lava-10591035/1/../bin/lava-test-case
11281 10:55:47.536862 <8>[ 20.935406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11282 10:55:47.537653 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11284 10:55:47.545517 /lava-10591035/1/../bin/lava-test-case
11285 10:55:47.551812 <8>[ 20.951013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11286 10:55:47.552631 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11288 10:55:47.562861 /lava-10591035/1/../bin/lava-test-case
11289 10:55:47.569624 <8>[ 20.968106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11290 10:55:47.570401 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11292 10:55:47.578385 /lava-10591035/1/../bin/lava-test-case
11293 10:55:47.584957 <8>[ 20.983608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11294 10:55:47.585792 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11296 10:55:48.597308 /lava-10591035/1/../bin/lava-test-case
11297 10:55:48.604025 <8>[ 22.003865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11298 10:55:48.604885 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11300 10:55:48.613270 /lava-10591035/1/../bin/lava-test-case
11301 10:55:48.620040 <8>[ 22.019090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11302 10:55:48.620922 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11304 10:55:49.634110 /lava-10591035/1/../bin/lava-test-case
11305 10:55:49.640552 <8>[ 23.040663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11306 10:55:49.641374 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11308 10:55:49.650112 /lava-10591035/1/../bin/lava-test-case
11309 10:55:49.657002 <8>[ 23.055816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11310 10:55:49.657924 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11312 10:55:50.670978 /lava-10591035/1/../bin/lava-test-case
11313 10:55:50.677544 <8>[ 24.077642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11314 10:55:50.678240 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11316 10:55:50.687232 /lava-10591035/1/../bin/lava-test-case
11317 10:55:50.693585 <8>[ 24.093607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11318 10:55:50.694292 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11320 10:55:51.707470 /lava-10591035/1/../bin/lava-test-case
11321 10:55:51.714176 <8>[ 25.114091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11322 10:55:51.714974 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11324 10:55:51.722656 /lava-10591035/1/../bin/lava-test-case
11325 10:55:51.729425 <8>[ 25.129178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11326 10:55:51.730215 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11328 10:55:52.742863 /lava-10591035/1/../bin/lava-test-case
11329 10:55:52.749254 <8>[ 26.150064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11330 10:55:52.749990 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11332 10:55:52.758744 /lava-10591035/1/../bin/lava-test-case
11333 10:55:52.765326 <8>[ 26.165419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11334 10:55:52.766004 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11336 10:55:53.780384 /lava-10591035/1/../bin/lava-test-case
11337 10:55:53.786880 <8>[ 27.187067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11338 10:55:53.787680 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11340 10:55:53.796931 /lava-10591035/1/../bin/lava-test-case
11341 10:55:53.803054 <8>[ 27.202453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11342 10:55:53.803843 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11344 10:55:54.817213 /lava-10591035/1/../bin/lava-test-case
11345 10:55:54.823795 <8>[ 28.224991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11346 10:55:54.824584 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11348 10:55:54.834177 /lava-10591035/1/../bin/lava-test-case
11349 10:55:54.841052 <8>[ 28.240772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11350 10:55:54.841842 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11352 10:55:54.851308 /lava-10591035/1/../bin/lava-test-case
11353 10:55:54.857421 <8>[ 28.257490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11354 10:55:54.858210 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11356 10:55:55.872466 /lava-10591035/1/../bin/lava-test-case
11357 10:55:55.878503 <8>[ 29.279685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11358 10:55:55.879291 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11360 10:55:55.889303 /lava-10591035/1/../bin/lava-test-case
11361 10:55:55.895696 <8>[ 29.296054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11362 10:55:55.896536 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11364 10:55:55.908494 /lava-10591035/1/../bin/lava-test-case
11365 10:55:55.914968 <8>[ 29.315195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11366 10:55:55.915760 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11368 10:55:55.924312 /lava-10591035/1/../bin/lava-test-case
11369 10:55:55.930773 <8>[ 29.331340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11370 10:55:55.931550 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11372 10:55:55.944468 /lava-10591035/1/../bin/lava-test-case
11373 10:55:55.950664 <8>[ 29.350933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11374 10:55:55.951457 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11376 10:55:55.962500 /lava-10591035/1/../bin/lava-test-case
11377 10:55:55.968912 <8>[ 29.368900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11378 10:55:55.969685 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11380 10:55:55.980850 /lava-10591035/1/../bin/lava-test-case
11381 10:55:55.986991 <8>[ 29.387021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11382 10:55:55.987674 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11384 10:55:55.996483 /lava-10591035/1/../bin/lava-test-case
11385 10:55:56.003077 <8>[ 29.403202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11386 10:55:56.003772 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11388 10:55:56.015058 /lava-10591035/1/../bin/lava-test-case
11389 10:55:56.021605 <8>[ 29.421798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11390 10:55:56.022383 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11392 10:55:56.033881 /lava-10591035/1/../bin/lava-test-case
11393 10:55:56.040626 <8>[ 29.440182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11394 10:55:56.041457 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11396 10:55:56.050595 /lava-10591035/1/../bin/lava-test-case
11397 10:55:56.056616 <8>[ 29.456447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11398 10:55:56.057446 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11400 10:55:56.069428 /lava-10591035/1/../bin/lava-test-case
11401 10:55:56.076278 <8>[ 29.476052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11402 10:55:56.077117 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11404 10:55:56.086424 /lava-10591035/1/../bin/lava-test-case
11405 10:55:56.092545 <8>[ 29.492424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11406 10:55:56.093457 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11408 10:55:56.105326 /lava-10591035/1/../bin/lava-test-case
11409 10:55:56.112275 <8>[ 29.511673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11410 10:55:56.113094 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11412 10:55:56.122055 /lava-10591035/1/../bin/lava-test-case
11413 10:55:56.128409 <8>[ 29.528605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11414 10:55:56.129227 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11416 10:55:56.141271 /lava-10591035/1/../bin/lava-test-case
11417 10:55:56.147932 <8>[ 29.547720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11418 10:55:56.148711 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11420 10:55:56.157147 /lava-10591035/1/../bin/lava-test-case
11421 10:55:56.163858 <8>[ 29.564029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11422 10:55:56.164728 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11424 10:55:56.176671 /lava-10591035/1/../bin/lava-test-case
11425 10:55:56.183196 <8>[ 29.583271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11426 10:55:56.183954 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11428 10:55:56.193188 /lava-10591035/1/../bin/lava-test-case
11429 10:55:56.199771 <8>[ 29.599395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11430 10:55:56.200555 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11432 10:55:56.212136 /lava-10591035/1/../bin/lava-test-case
11433 10:55:56.218714 <8>[ 29.618432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11434 10:55:56.219392 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11436 10:55:56.227573 /lava-10591035/1/../bin/lava-test-case
11437 10:55:56.234266 <8>[ 29.633648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11438 10:55:56.235054 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11440 10:55:57.248025 /lava-10591035/1/../bin/lava-test-case
11441 10:55:57.254619 <8>[ 30.654688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11442 10:55:57.255406 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11444 10:55:58.267595 /lava-10591035/1/../bin/lava-test-case
11445 10:55:58.274446 <8>[ 31.675425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11446 10:55:58.275263 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11448 10:55:58.284002 /lava-10591035/1/../bin/lava-test-case
11449 10:55:58.290165 <8>[ 31.691398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11450 10:55:58.290988 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11452 10:55:58.302961 /lava-10591035/1/../bin/lava-test-case
11453 10:55:58.309344 <8>[ 31.709243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11454 10:55:58.310139 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11456 10:55:58.318213 /lava-10591035/1/../bin/lava-test-case
11457 10:55:58.324429 <8>[ 31.725075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11458 10:55:58.325344 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11460 10:55:58.336214 /lava-10591035/1/../bin/lava-test-case
11461 10:55:58.342885 <8>[ 31.742670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11462 10:55:58.343681 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11464 10:55:58.352249 /lava-10591035/1/../bin/lava-test-case
11465 10:55:58.358344 <8>[ 31.758582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11466 10:55:58.359039 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11468 10:55:58.369270 /lava-10591035/1/../bin/lava-test-case
11469 10:55:58.375770 <8>[ 31.775911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11470 10:55:58.376442 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11472 10:55:58.384511 /lava-10591035/1/../bin/lava-test-case
11473 10:55:58.391119 <8>[ 31.791704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11474 10:55:58.391904 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11476 10:55:58.402319 /lava-10591035/1/../bin/lava-test-case
11477 10:55:58.409623 <8>[ 31.809578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11478 10:55:58.410402 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11480 10:55:58.418256 /lava-10591035/1/../bin/lava-test-case
11481 10:55:58.424845 <8>[ 31.824996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11482 10:55:58.425623 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11484 10:55:58.436529 /lava-10591035/1/../bin/lava-test-case
11485 10:55:58.442738 <8>[ 31.842448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11486 10:55:58.443520 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11488 10:55:58.450956 /lava-10591035/1/../bin/lava-test-case
11489 10:55:58.457596 <8>[ 31.858052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11490 10:55:58.458379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11492 10:55:58.469232 /lava-10591035/1/../bin/lava-test-case
11493 10:55:58.475944 <8>[ 31.875990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11494 10:55:58.476715 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11496 10:55:58.484520 /lava-10591035/1/../bin/lava-test-case
11497 10:55:58.491919 <8>[ 31.891237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11498 10:55:58.492679 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11500 10:55:58.502288 /lava-10591035/1/../bin/lava-test-case
11501 10:55:58.508525 <8>[ 31.908965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11502 10:55:58.509293 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11504 10:55:58.517501 /lava-10591035/1/../bin/lava-test-case
11505 10:55:58.524589 <8>[ 31.924490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11506 10:55:58.525400 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11508 10:55:58.535880 /lava-10591035/1/../bin/lava-test-case
11509 10:55:58.542817 <8>[ 31.942921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11510 10:55:58.543549 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11512 10:55:58.550848 /lava-10591035/1/../bin/lava-test-case
11513 10:55:58.557318 <8>[ 31.957851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11514 10:55:58.558092 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11516 10:55:58.568932 /lava-10591035/1/../bin/lava-test-case
11517 10:55:58.575083 <8>[ 31.975232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11518 10:55:58.575854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11520 10:55:58.583962 /lava-10591035/1/../bin/lava-test-case
11521 10:55:58.590695 <8>[ 31.990951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11522 10:55:58.591459 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11524 10:55:58.602176 /lava-10591035/1/../bin/lava-test-case
11525 10:55:58.608478 <8>[ 32.009729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11526 10:55:58.609184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11528 10:55:59.620643 /lava-10591035/1/../bin/lava-test-case
11529 10:55:59.627243 <8>[ 33.028050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11530 10:55:59.628002 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11532 10:56:00.640264 /lava-10591035/1/../bin/lava-test-case
11533 10:56:00.646994 <8>[ 34.048551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11534 10:56:00.647773 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11535 10:56:00.648166 Bad test result: blocked
11536 10:56:00.657345 /lava-10591035/1/../bin/lava-test-case
11537 10:56:00.663744 <8>[ 34.064394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11538 10:56:00.664488 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11540 10:56:01.678023 /lava-10591035/1/../bin/lava-test-case
11541 10:56:01.684653 <8>[ 35.086412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11542 10:56:01.685450 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11544 10:56:01.694222 /lava-10591035/1/../bin/lava-test-case
11545 10:56:01.701070 <8>[ 35.101975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11546 10:56:01.701850 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11548 10:56:01.712278 /lava-10591035/1/../bin/lava-test-case
11549 10:56:01.719106 <8>[ 35.119713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11550 10:56:01.719864 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11552 10:56:01.730395 /lava-10591035/1/../bin/lava-test-case
11553 10:56:01.736818 <8>[ 35.137247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11554 10:56:01.737598 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11556 10:56:01.745377 /lava-10591035/1/../bin/lava-test-case
11557 10:56:01.752423 <8>[ 35.152648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11558 10:56:01.753251 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11560 10:56:01.763763 /lava-10591035/1/../bin/lava-test-case
11561 10:56:01.770020 <8>[ 35.171346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11562 10:56:01.770778 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11564 10:56:01.778951 /lava-10591035/1/../bin/lava-test-case
11565 10:56:01.785507 <8>[ 35.186543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11566 10:56:01.786279 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11568 10:56:02.799923 /lava-10591035/1/../bin/lava-test-case
11569 10:56:02.806193 <8>[ 36.208549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11570 10:56:02.806868 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11572 10:56:02.816511 /lava-10591035/1/../bin/lava-test-case
11573 10:56:02.823124 <8>[ 36.224274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11574 10:56:02.823917 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11576 10:56:03.836043 /lava-10591035/1/../bin/lava-test-case
11577 10:56:03.843229 <8>[ 37.244791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11578 10:56:03.844024 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11580 10:56:03.852395 /lava-10591035/1/../bin/lava-test-case
11581 10:56:03.858708 <8>[ 37.259811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11582 10:56:03.859463 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11584 10:56:04.872215 /lava-10591035/1/../bin/lava-test-case
11585 10:56:04.879057 <8>[ 38.280688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11586 10:56:04.879840 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11588 10:56:04.887965 /lava-10591035/1/../bin/lava-test-case
11589 10:56:04.894414 <8>[ 38.295750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11590 10:56:04.895182 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11592 10:56:05.908108 /lava-10591035/1/../bin/lava-test-case
11593 10:56:05.915361 <8>[ 39.316748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11594 10:56:05.916134 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11596 10:56:05.924861 /lava-10591035/1/../bin/lava-test-case
11597 10:56:05.931058 <8>[ 39.332903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11598 10:56:05.931797 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11600 10:56:05.942482 /lava-10591035/1/../bin/lava-test-case
11601 10:56:05.948948 <8>[ 39.349738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11602 10:56:05.949717 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11604 10:56:05.959813 /lava-10591035/1/../bin/lava-test-case
11605 10:56:05.966316 <8>[ 39.367274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11606 10:56:05.967048 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11608 10:56:05.974896 /lava-10591035/1/../bin/lava-test-case
11609 10:56:05.981313 <8>[ 39.382142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11610 10:56:05.982111 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11612 10:56:05.992459 /lava-10591035/1/../bin/lava-test-case
11613 10:56:05.999064 <8>[ 39.399907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11614 10:56:05.999802 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11616 10:56:06.007184 /lava-10591035/1/../bin/lava-test-case
11617 10:56:06.014157 <8>[ 39.415191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11618 10:56:06.014954 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11620 10:56:06.025373 /lava-10591035/1/../bin/lava-test-case
11621 10:56:06.032038 <8>[ 39.433392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11622 10:56:06.032828 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11624 10:56:06.041516 /lava-10591035/1/../bin/lava-test-case
11625 10:56:06.048008 <8>[ 39.449267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11626 10:56:06.048852 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11628 10:56:07.061662 /lava-10591035/1/../bin/lava-test-case
11629 10:56:07.067748 <8>[ 40.470000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11630 10:56:07.068577 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11632 10:56:07.072470 + set +x
11633 10:56:07.075803 Received signal: <ENDRUN> 1_bootrr 10591035_1.5.2.3.5
11634 10:56:07.076368 Ending use of test pattern.
11635 10:56:07.076829 Ending test lava.1_bootrr (10591035_1.5.2.3.5), duration 23.27
11637 10:56:07.078619 <8>[ 40.480075] <LAVA_SIGNAL_ENDRUN 1_bootrr 10591035_1.5.2.3.5>
11638 10:56:07.079262 ok: lava_test_shell seems to have completed
11639 10:56:07.084438 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11640 10:56:07.085225 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11641 10:56:07.085749 end: 4 lava-test-retry (duration 00:00:24) [common]
11642 10:56:07.086294 start: 5 finalize (timeout 00:07:54) [common]
11643 10:56:07.086827 start: 5.1 power-off (timeout 00:00:30) [common]
11644 10:56:07.087725 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11645 10:56:07.171988 >> Command sent successfully.
11646 10:56:07.176635 Returned 0 in 0 seconds
11647 10:56:07.277585 end: 5.1 power-off (duration 00:00:00) [common]
11649 10:56:07.279165 start: 5.2 read-feedback (timeout 00:07:54) [common]
11651 10:56:07.281225 Listened to connection for namespace 'common' for up to 1s
11652 10:56:08.281079 Finalising connection for namespace 'common'
11653 10:56:08.281697 Disconnecting from shell: Finalise
11654 10:56:08.282132 / #
11655 10:56:08.383131 end: 5.2 read-feedback (duration 00:00:01) [common]
11656 10:56:08.383832 end: 5 finalize (duration 00:00:01) [common]
11657 10:56:08.384469 Cleaning after the job
11658 10:56:08.385069 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/ramdisk
11659 10:56:08.396108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/kernel
11660 10:56:08.417070 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/dtb
11661 10:56:08.417543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591035/tftp-deploy-zdi7ijol/modules
11662 10:56:08.427439 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591035
11663 10:56:08.469589 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591035
11664 10:56:08.469762 Job finished correctly