Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 10:50:23.841162 lava-dispatcher, installed at version: 2023.05.1
2 10:50:23.841356 start: 0 validate
3 10:50:23.841481 Start time: 2023-06-05 10:50:23.841474+00:00 (UTC)
4 10:50:23.841601 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:50:23.841726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:50:24.136696 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:50:24.137417 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:50:24.435701 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:50:24.436397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:50:52.544267 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:50:52.544431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:50:53.125878 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:50:53.126153 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:50:53.422229 validate duration: 29.58
16 10:50:53.422482 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:50:53.422578 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:50:53.422664 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:50:53.422784 Not decompressing ramdisk as can be used compressed.
20 10:50:53.422863 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 10:50:53.422924 saving as /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/ramdisk/initrd.cpio.gz
22 10:50:53.422983 total size: 4665395 (4MB)
23 10:51:14.352584 progress 0% (0MB)
24 10:51:14.353991 progress 5% (0MB)
25 10:51:14.355237 progress 10% (0MB)
26 10:51:14.356466 progress 15% (0MB)
27 10:51:14.357670 progress 20% (0MB)
28 10:51:14.358868 progress 25% (1MB)
29 10:51:14.360072 progress 30% (1MB)
30 10:51:14.361268 progress 35% (1MB)
31 10:51:14.362487 progress 40% (1MB)
32 10:51:14.363837 progress 45% (2MB)
33 10:51:14.365036 progress 50% (2MB)
34 10:51:14.366233 progress 55% (2MB)
35 10:51:14.367464 progress 60% (2MB)
36 10:51:14.368650 progress 65% (2MB)
37 10:51:14.369848 progress 70% (3MB)
38 10:51:14.371035 progress 75% (3MB)
39 10:51:14.372257 progress 80% (3MB)
40 10:51:14.373608 progress 85% (3MB)
41 10:51:14.374805 progress 90% (4MB)
42 10:51:14.376041 progress 95% (4MB)
43 10:51:14.377248 progress 100% (4MB)
44 10:51:14.377396 4MB downloaded in 20.95s (0.21MB/s)
45 10:51:14.377539 end: 1.1.1 http-download (duration 00:00:21) [common]
47 10:51:14.377774 end: 1.1 download-retry (duration 00:00:21) [common]
48 10:51:14.377861 start: 1.2 download-retry (timeout 00:09:39) [common]
49 10:51:14.377945 start: 1.2.1 http-download (timeout 00:09:39) [common]
50 10:51:14.378079 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:51:14.378150 saving as /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/kernel/Image
52 10:51:14.378209 total size: 45746688 (43MB)
53 10:51:14.378268 No compression specified
54 10:51:14.670628 progress 0% (0MB)
55 10:51:14.682012 progress 5% (2MB)
56 10:51:14.693574 progress 10% (4MB)
57 10:51:14.704976 progress 15% (6MB)
58 10:51:14.716418 progress 20% (8MB)
59 10:51:14.728181 progress 25% (10MB)
60 10:51:14.739543 progress 30% (13MB)
61 10:51:14.751156 progress 35% (15MB)
62 10:51:14.762632 progress 40% (17MB)
63 10:51:14.774153 progress 45% (19MB)
64 10:51:14.785563 progress 50% (21MB)
65 10:51:14.796882 progress 55% (24MB)
66 10:51:14.808291 progress 60% (26MB)
67 10:51:14.819806 progress 65% (28MB)
68 10:51:14.831357 progress 70% (30MB)
69 10:51:14.843097 progress 75% (32MB)
70 10:51:14.854803 progress 80% (34MB)
71 10:51:14.866521 progress 85% (37MB)
72 10:51:14.878171 progress 90% (39MB)
73 10:51:14.889701 progress 95% (41MB)
74 10:51:14.901642 progress 100% (43MB)
75 10:51:14.901849 43MB downloaded in 0.52s (83.32MB/s)
76 10:51:14.902018 end: 1.2.1 http-download (duration 00:00:01) [common]
78 10:51:14.902316 end: 1.2 download-retry (duration 00:00:01) [common]
79 10:51:14.902404 start: 1.3 download-retry (timeout 00:09:39) [common]
80 10:51:14.902521 start: 1.3.1 http-download (timeout 00:09:39) [common]
81 10:51:14.902684 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:51:14.902754 saving as /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/dtb/mt8192-asurada-spherion-r0.dtb
83 10:51:14.902827 total size: 46924 (0MB)
84 10:51:14.902899 No compression specified
85 10:51:15.188750 progress 69% (0MB)
86 10:51:15.189079 progress 100% (0MB)
87 10:51:15.189246 0MB downloaded in 0.29s (0.16MB/s)
88 10:51:15.189387 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:51:15.189617 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:51:15.189707 start: 1.4 download-retry (timeout 00:09:38) [common]
92 10:51:15.189796 start: 1.4.1 http-download (timeout 00:09:38) [common]
93 10:51:15.189932 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 10:51:15.189999 saving as /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/nfsrootfs/full.rootfs.tar
95 10:51:15.190059 total size: 125267308 (119MB)
96 10:51:15.190118 Using unxz to decompress xz
97 10:51:15.478580 progress 0% (0MB)
98 10:51:15.792425 progress 5% (6MB)
99 10:51:16.120303 progress 10% (11MB)
100 10:51:16.441645 progress 15% (17MB)
101 10:51:16.621875 progress 20% (23MB)
102 10:51:16.795422 progress 25% (29MB)
103 10:51:17.137701 progress 30% (35MB)
104 10:51:17.483454 progress 35% (41MB)
105 10:51:17.862131 progress 40% (47MB)
106 10:51:18.236788 progress 45% (53MB)
107 10:51:18.620547 progress 50% (59MB)
108 10:51:18.974431 progress 55% (65MB)
109 10:51:19.336930 progress 60% (71MB)
110 10:51:19.676526 progress 65% (77MB)
111 10:51:20.039888 progress 70% (83MB)
112 10:51:20.414339 progress 75% (89MB)
113 10:51:20.823585 progress 80% (95MB)
114 10:51:21.233805 progress 85% (101MB)
115 10:51:21.469478 progress 90% (107MB)
116 10:51:21.799132 progress 95% (113MB)
117 10:51:22.164283 progress 100% (119MB)
118 10:51:22.170418 119MB downloaded in 6.98s (17.11MB/s)
119 10:51:22.170708 end: 1.4.1 http-download (duration 00:00:07) [common]
121 10:51:22.170973 end: 1.4 download-retry (duration 00:00:07) [common]
122 10:51:22.171065 start: 1.5 download-retry (timeout 00:09:31) [common]
123 10:51:22.171159 start: 1.5.1 http-download (timeout 00:09:31) [common]
124 10:51:22.171330 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:51:22.171433 saving as /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/modules/modules.tar
126 10:51:22.171499 total size: 8542412 (8MB)
127 10:51:22.171560 Using unxz to decompress xz
128 10:51:22.175075 progress 0% (0MB)
129 10:51:22.196286 progress 5% (0MB)
130 10:51:22.221134 progress 10% (0MB)
131 10:51:22.246979 progress 15% (1MB)
132 10:51:22.271716 progress 20% (1MB)
133 10:51:22.296794 progress 25% (2MB)
134 10:51:22.321788 progress 30% (2MB)
135 10:51:22.347929 progress 35% (2MB)
136 10:51:22.372464 progress 40% (3MB)
137 10:51:22.397283 progress 45% (3MB)
138 10:51:22.420892 progress 50% (4MB)
139 10:51:22.443750 progress 55% (4MB)
140 10:51:22.469579 progress 60% (4MB)
141 10:51:22.495313 progress 65% (5MB)
142 10:51:22.520758 progress 70% (5MB)
143 10:51:22.547430 progress 75% (6MB)
144 10:51:22.576562 progress 80% (6MB)
145 10:51:22.598943 progress 85% (6MB)
146 10:51:22.623795 progress 90% (7MB)
147 10:51:22.646952 progress 95% (7MB)
148 10:51:22.670500 progress 100% (8MB)
149 10:51:22.676093 8MB downloaded in 0.50s (16.15MB/s)
150 10:51:22.676385 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:51:22.676654 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:51:22.676757 start: 1.6 prepare-tftp-overlay (timeout 00:09:31) [common]
154 10:51:22.676851 start: 1.6.1 extract-nfsrootfs (timeout 00:09:31) [common]
155 10:51:24.902534 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g
156 10:51:24.902740 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 10:51:24.902841 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
158 10:51:24.903005 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem
159 10:51:24.903137 makedir: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin
160 10:51:24.903238 makedir: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/tests
161 10:51:24.903333 makedir: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/results
162 10:51:24.903664 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-add-keys
163 10:51:24.903802 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-add-sources
164 10:51:24.903928 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-background-process-start
165 10:51:24.904068 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-background-process-stop
166 10:51:24.904206 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-common-functions
167 10:51:24.904324 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-echo-ipv4
168 10:51:24.904442 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-install-packages
169 10:51:24.904559 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-installed-packages
170 10:51:24.904673 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-os-build
171 10:51:24.904789 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-probe-channel
172 10:51:24.904904 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-probe-ip
173 10:51:24.905019 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-target-ip
174 10:51:24.905134 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-target-mac
175 10:51:24.905249 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-target-storage
176 10:51:24.905367 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-case
177 10:51:24.905483 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-event
178 10:51:24.905598 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-feedback
179 10:51:24.905715 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-raise
180 10:51:24.905834 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-reference
181 10:51:24.905951 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-runner
182 10:51:24.906067 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-set
183 10:51:24.906183 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-test-shell
184 10:51:24.906301 Updating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-install-packages (oe)
185 10:51:24.906442 Updating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/bin/lava-installed-packages (oe)
186 10:51:24.906565 Creating /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/environment
187 10:51:24.906662 LAVA metadata
188 10:51:24.906730 - LAVA_JOB_ID=10591012
189 10:51:24.906791 - LAVA_DISPATCHER_IP=192.168.201.1
190 10:51:24.906888 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:29) [common]
191 10:51:24.906955 skipped lava-vland-overlay
192 10:51:24.907028 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 10:51:24.907105 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:29) [common]
194 10:51:24.907164 skipped lava-multinode-overlay
195 10:51:24.907235 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 10:51:24.907311 start: 1.6.2.3 test-definition (timeout 00:09:29) [common]
197 10:51:24.907421 Loading test definitions
198 10:51:24.907510 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:29) [common]
199 10:51:24.907580 Using /lava-10591012 at stage 0
200 10:51:24.907869 uuid=10591012_1.6.2.3.1 testdef=None
201 10:51:24.907955 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 10:51:24.908039 start: 1.6.2.3.2 test-overlay (timeout 00:09:29) [common]
203 10:51:24.908561 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 10:51:24.908780 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:29) [common]
206 10:51:24.909392 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 10:51:24.909616 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:29) [common]
209 10:51:24.910217 runner path: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/0/tests/0_dmesg test_uuid 10591012_1.6.2.3.1
210 10:51:24.910366 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 10:51:24.910613 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:29) [common]
213 10:51:24.910683 Using /lava-10591012 at stage 1
214 10:51:24.910968 uuid=10591012_1.6.2.3.5 testdef=None
215 10:51:24.911053 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 10:51:24.911135 start: 1.6.2.3.6 test-overlay (timeout 00:09:29) [common]
217 10:51:24.911613 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 10:51:24.911823 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:29) [common]
220 10:51:24.912443 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 10:51:24.912665 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:29) [common]
223 10:51:24.913269 runner path: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/1/tests/1_bootrr test_uuid 10591012_1.6.2.3.5
224 10:51:24.913414 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 10:51:24.913612 Creating lava-test-runner.conf files
227 10:51:24.913673 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/0 for stage 0
228 10:51:24.913757 - 0_dmesg
229 10:51:24.913832 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591012/lava-overlay-f6ilyiem/lava-10591012/1 for stage 1
230 10:51:24.913917 - 1_bootrr
231 10:51:24.914007 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 10:51:24.914089 start: 1.6.2.4 compress-overlay (timeout 00:09:29) [common]
233 10:51:24.921251 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 10:51:24.921352 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:29) [common]
235 10:51:24.921435 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 10:51:24.921518 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 10:51:24.921600 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:29) [common]
238 10:51:25.036337 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 10:51:25.036701 start: 1.6.4 extract-modules (timeout 00:09:28) [common]
240 10:51:25.036818 extracting modules file /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g
241 10:51:25.236413 extracting modules file /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591012/extract-overlay-ramdisk-wac3489b/ramdisk
242 10:51:25.441752 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 10:51:25.441917 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
244 10:51:25.442017 [common] Applying overlay to NFS
245 10:51:25.442087 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591012/compress-overlay-bm86ww00/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g
246 10:51:25.449763 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 10:51:25.449873 start: 1.6.6 configure-preseed-file (timeout 00:09:28) [common]
248 10:51:25.449964 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 10:51:25.450053 start: 1.6.7 compress-ramdisk (timeout 00:09:28) [common]
250 10:51:25.450134 Building ramdisk /var/lib/lava/dispatcher/tmp/10591012/extract-overlay-ramdisk-wac3489b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591012/extract-overlay-ramdisk-wac3489b/ramdisk
251 10:51:25.720099 >> 117801 blocks
252 10:51:27.609051 rename /var/lib/lava/dispatcher/tmp/10591012/extract-overlay-ramdisk-wac3489b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/ramdisk/ramdisk.cpio.gz
253 10:51:27.609470 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 10:51:27.609597 start: 1.6.8 prepare-kernel (timeout 00:09:26) [common]
255 10:51:27.609699 start: 1.6.8.1 prepare-fit (timeout 00:09:26) [common]
256 10:51:27.609805 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/kernel/Image'
257 10:51:39.756327 Returned 0 in 12 seconds
258 10:51:39.856939 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/kernel/image.itb
259 10:51:40.168668 output: FIT description: Kernel Image image with one or more FDT blobs
260 10:51:40.169020 output: Created: Mon Jun 5 11:51:40 2023
261 10:51:40.169097 output: Image 0 (kernel-1)
262 10:51:40.169164 output: Description:
263 10:51:40.169228 output: Created: Mon Jun 5 11:51:40 2023
264 10:51:40.169287 output: Type: Kernel Image
265 10:51:40.169347 output: Compression: lzma compressed
266 10:51:40.169405 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
267 10:51:40.169461 output: Architecture: AArch64
268 10:51:40.169518 output: OS: Linux
269 10:51:40.169574 output: Load Address: 0x00000000
270 10:51:40.169630 output: Entry Point: 0x00000000
271 10:51:40.169690 output: Hash algo: crc32
272 10:51:40.169742 output: Hash value: 8ce42972
273 10:51:40.169794 output: Image 1 (fdt-1)
274 10:51:40.169846 output: Description: mt8192-asurada-spherion-r0
275 10:51:40.169899 output: Created: Mon Jun 5 11:51:40 2023
276 10:51:40.169951 output: Type: Flat Device Tree
277 10:51:40.170004 output: Compression: uncompressed
278 10:51:40.170056 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 10:51:40.170108 output: Architecture: AArch64
280 10:51:40.170161 output: Hash algo: crc32
281 10:51:40.170213 output: Hash value: 1df858fa
282 10:51:40.170265 output: Image 2 (ramdisk-1)
283 10:51:40.170317 output: Description: unavailable
284 10:51:40.170369 output: Created: Mon Jun 5 11:51:40 2023
285 10:51:40.170420 output: Type: RAMDisk Image
286 10:51:40.170472 output: Compression: Unknown Compression
287 10:51:40.170524 output: Data Size: 17637731 Bytes = 17224.35 KiB = 16.82 MiB
288 10:51:40.170577 output: Architecture: AArch64
289 10:51:40.170629 output: OS: Linux
290 10:51:40.170680 output: Load Address: unavailable
291 10:51:40.170732 output: Entry Point: unavailable
292 10:51:40.170783 output: Hash algo: crc32
293 10:51:40.170835 output: Hash value: ea9a2feb
294 10:51:40.170886 output: Default Configuration: 'conf-1'
295 10:51:40.170938 output: Configuration 0 (conf-1)
296 10:51:40.170990 output: Description: mt8192-asurada-spherion-r0
297 10:51:40.171043 output: Kernel: kernel-1
298 10:51:40.171095 output: Init Ramdisk: ramdisk-1
299 10:51:40.171147 output: FDT: fdt-1
300 10:51:40.171198 output: Loadables: kernel-1
301 10:51:40.171249 output:
302 10:51:40.171480 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 10:51:40.171579 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 10:51:40.171683 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
305 10:51:40.171775 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
306 10:51:40.171853 No LXC device requested
307 10:51:40.171930 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 10:51:40.172017 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
309 10:51:40.172093 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 10:51:40.172161 Checking files for TFTP limit of 4294967296 bytes.
311 10:51:40.172653 end: 1 tftp-deploy (duration 00:00:47) [common]
312 10:51:40.172758 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 10:51:40.172856 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 10:51:40.172983 substitutions:
315 10:51:40.173051 - {DTB}: 10591012/tftp-deploy-70bw0c7d/dtb/mt8192-asurada-spherion-r0.dtb
316 10:51:40.173116 - {INITRD}: 10591012/tftp-deploy-70bw0c7d/ramdisk/ramdisk.cpio.gz
317 10:51:40.173175 - {KERNEL}: 10591012/tftp-deploy-70bw0c7d/kernel/Image
318 10:51:40.173233 - {LAVA_MAC}: None
319 10:51:40.173290 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g
320 10:51:40.173346 - {NFS_SERVER_IP}: 192.168.201.1
321 10:51:40.173402 - {PRESEED_CONFIG}: None
322 10:51:40.173456 - {PRESEED_LOCAL}: None
323 10:51:40.173510 - {RAMDISK}: 10591012/tftp-deploy-70bw0c7d/ramdisk/ramdisk.cpio.gz
324 10:51:40.173566 - {ROOT_PART}: None
325 10:51:40.173620 - {ROOT}: None
326 10:51:40.173674 - {SERVER_IP}: 192.168.201.1
327 10:51:40.173727 - {TEE}: None
328 10:51:40.173781 Parsed boot commands:
329 10:51:40.173834 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 10:51:40.174009 Parsed boot commands: tftpboot 192.168.201.1 10591012/tftp-deploy-70bw0c7d/kernel/image.itb 10591012/tftp-deploy-70bw0c7d/kernel/cmdline
331 10:51:40.174097 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 10:51:40.174181 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 10:51:40.174275 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 10:51:40.174362 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 10:51:40.174434 Not connected, no need to disconnect.
336 10:51:40.174510 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 10:51:40.174592 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 10:51:40.174659 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
339 10:51:40.178000 Setting prompt string to ['lava-test: # ']
340 10:51:40.178360 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 10:51:40.178474 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 10:51:40.178576 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 10:51:40.178668 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 10:51:40.178867 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
345 10:51:45.310242 >> Command sent successfully.
346 10:51:45.312758 Returned 0 in 5 seconds
347 10:51:45.413148 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 10:51:45.413533 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 10:51:45.413649 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 10:51:45.413792 Setting prompt string to 'Starting depthcharge on Spherion...'
352 10:51:45.413858 Changing prompt to 'Starting depthcharge on Spherion...'
353 10:51:45.413984 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 10:51:45.414301 [Enter `^Ec?' for help]
355 10:51:45.587815
356 10:51:45.587960
357 10:51:45.588033 F0: 102B 0000
358 10:51:45.588095
359 10:51:45.588155 F3: 1001 0000 [0200]
360 10:51:45.588213
361 10:51:45.591028 F3: 1001 0000
362 10:51:45.591111
363 10:51:45.591176 F7: 102D 0000
364 10:51:45.591237
365 10:51:45.595001 F1: 0000 0000
366 10:51:45.595085
367 10:51:45.595150 V0: 0000 0000 [0001]
368 10:51:45.595211
369 10:51:45.595269 00: 0007 8000
370 10:51:45.595330
371 10:51:45.597873 01: 0000 0000
372 10:51:45.597957
373 10:51:45.598021 BP: 0C00 0209 [0000]
374 10:51:45.598082
375 10:51:45.601710 G0: 1182 0000
376 10:51:45.601792
377 10:51:45.601857 EC: 0000 0021 [4000]
378 10:51:45.601917
379 10:51:45.605064 S7: 0000 0000 [0000]
380 10:51:45.605146
381 10:51:45.605211 CC: 0000 0000 [0001]
382 10:51:45.605270
383 10:51:45.607962 T0: 0000 0040 [010F]
384 10:51:45.608044
385 10:51:45.608108 Jump to BL
386 10:51:45.608166
387 10:51:45.634583
388 10:51:45.634672
389 10:51:45.634737
390 10:51:45.642009 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 10:51:45.645887 ARM64: Exception handlers installed.
392 10:51:45.649397 ARM64: Testing exception
393 10:51:45.653200 ARM64: Done test exception
394 10:51:45.660639 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 10:51:45.667660 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 10:51:45.674282 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 10:51:45.685380 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 10:51:45.691871 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 10:51:45.701912 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 10:51:45.712576 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 10:51:45.719387 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 10:51:45.737229 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 10:51:45.741012 WDT: Last reset was cold boot
404 10:51:45.743938 SPI1(PAD0) initialized at 2873684 Hz
405 10:51:45.747346 SPI5(PAD0) initialized at 992727 Hz
406 10:51:45.750744 VBOOT: Loading verstage.
407 10:51:45.756995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 10:51:45.760389 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 10:51:45.763938 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 10:51:45.767264 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 10:51:45.775002 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 10:51:45.781577 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 10:51:45.792516 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
414 10:51:45.792599
415 10:51:45.792665
416 10:51:45.802445 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 10:51:45.805410 ARM64: Exception handlers installed.
418 10:51:45.808882 ARM64: Testing exception
419 10:51:45.808965 ARM64: Done test exception
420 10:51:45.815850 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 10:51:45.819116 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:51:45.833083 Probing TPM: . done!
423 10:51:45.833165 TPM ready after 0 ms
424 10:51:45.840117 Connected to device vid:did:rid of 1ae0:0028:00
425 10:51:45.847539 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 10:51:45.906501 Initialized TPM device CR50 revision 0
427 10:51:45.918300 tlcl_send_startup: Startup return code is 0
428 10:51:45.918392 TPM: setup succeeded
429 10:51:45.929558 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 10:51:45.938616 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 10:51:45.950545 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 10:51:45.960475 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 10:51:45.963816 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 10:51:45.968744 in-header: 03 07 00 00 08 00 00 00
435 10:51:45.972169 in-data: aa e4 47 04 13 02 00 00
436 10:51:45.975681 Chrome EC: UHEPI supported
437 10:51:45.983487 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 10:51:45.986816 in-header: 03 ad 00 00 08 00 00 00
439 10:51:45.990380 in-data: 00 20 20 08 00 00 00 00
440 10:51:45.990546 Phase 1
441 10:51:45.994007 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 10:51:46.001046 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 10:51:46.004947 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 10:51:46.008414 Recovery requested (1009000e)
445 10:51:46.018114 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 10:51:46.024285 tlcl_extend: response is 0
447 10:51:46.034613 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 10:51:46.040379 tlcl_extend: response is 0
449 10:51:46.046582 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 10:51:46.066828 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
451 10:51:46.073314 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 10:51:46.073399
453 10:51:46.073463
454 10:51:46.083670 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 10:51:46.087886 ARM64: Exception handlers installed.
456 10:51:46.087970 ARM64: Testing exception
457 10:51:46.090880 ARM64: Done test exception
458 10:51:46.112831 pmic_efuse_setting: Set efuses in 11 msecs
459 10:51:46.116213 pmwrap_interface_init: Select PMIF_VLD_RDY
460 10:51:46.122521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 10:51:46.125764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 10:51:46.132780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 10:51:46.136366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 10:51:46.140074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 10:51:46.147265 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 10:51:46.151663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 10:51:46.155011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 10:51:46.158659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 10:51:46.166145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 10:51:46.169722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 10:51:46.173561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 10:51:46.176717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 10:51:46.184544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 10:51:46.192183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 10:51:46.195766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 10:51:46.203272 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 10:51:46.207124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 10:51:46.213785 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 10:51:46.217554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 10:51:46.225250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 10:51:46.229147 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 10:51:46.236449 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 10:51:46.240030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 10:51:46.247990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 10:51:46.251143 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 10:51:46.254822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 10:51:46.262019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 10:51:46.266072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 10:51:46.269667 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 10:51:46.276777 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 10:51:46.280529 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 10:51:46.287992 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 10:51:46.291501 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 10:51:46.295129 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 10:51:46.302840 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 10:51:46.306284 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 10:51:46.313181 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 10:51:46.317385 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 10:51:46.321482 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 10:51:46.324650 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 10:51:46.328005 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 10:51:46.332033 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 10:51:46.338816 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 10:51:46.342394 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 10:51:46.345900 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 10:51:46.349505 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 10:51:46.353055 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 10:51:46.360673 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 10:51:46.364256 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 10:51:46.368177 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 10:51:46.375325 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 10:51:46.382596 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 10:51:46.386488 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 10:51:46.398086 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 10:51:46.405192 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 10:51:46.408370 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 10:51:46.412266 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 10:51:46.419710 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 10:51:46.426882 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
520 10:51:46.430321 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 10:51:46.433969 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 10:51:46.441906 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 10:51:46.449677 [RTC]rtc_get_frequency_meter,154: input=15, output=790
524 10:51:46.459190 [RTC]rtc_get_frequency_meter,154: input=23, output=977
525 10:51:46.468902 [RTC]rtc_get_frequency_meter,154: input=19, output=885
526 10:51:46.478049 [RTC]rtc_get_frequency_meter,154: input=17, output=837
527 10:51:46.487769 [RTC]rtc_get_frequency_meter,154: input=16, output=814
528 10:51:46.497237 [RTC]rtc_get_frequency_meter,154: input=15, output=789
529 10:51:46.507785 [RTC]rtc_get_frequency_meter,154: input=16, output=814
530 10:51:46.510488 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
531 10:51:46.517823 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
532 10:51:46.521959 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 10:51:46.525235 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 10:51:46.528910 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 10:51:46.532261 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 10:51:46.536262 ADC[4]: Raw value=901328 ID=7
537 10:51:46.539595 ADC[3]: Raw value=213336 ID=1
538 10:51:46.539666 RAM Code: 0x71
539 10:51:46.543453 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 10:51:46.550951 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 10:51:46.558446 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 10:51:46.565461 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 10:51:46.569464 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 10:51:46.572808 in-header: 03 07 00 00 08 00 00 00
545 10:51:46.572877 in-data: aa e4 47 04 13 02 00 00
546 10:51:46.577089 Chrome EC: UHEPI supported
547 10:51:46.583796 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 10:51:46.587267 in-header: 03 ed 00 00 08 00 00 00
549 10:51:46.590920 in-data: 80 20 60 08 00 00 00 00
550 10:51:46.594849 MRC: failed to locate region type 0.
551 10:51:46.602270 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 10:51:46.605807 DRAM-K: Running full calibration
553 10:51:46.610277 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 10:51:46.613013 header.status = 0x0
555 10:51:46.617295 header.version = 0x6 (expected: 0x6)
556 10:51:46.620777 header.size = 0xd00 (expected: 0xd00)
557 10:51:46.620848 header.flags = 0x0
558 10:51:46.627760 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 10:51:46.644749 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
560 10:51:46.652245 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 10:51:46.656321 dram_init: ddr_geometry: 2
562 10:51:46.656398 [EMI] MDL number = 2
563 10:51:46.660026 [EMI] Get MDL freq = 0
564 10:51:46.660094 dram_init: ddr_type: 0
565 10:51:46.663621 is_discrete_lpddr4: 1
566 10:51:46.667074 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 10:51:46.667141
568 10:51:46.667202
569 10:51:46.667260 [Bian_co] ETT version 0.0.0.1
570 10:51:46.674203 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 10:51:46.674276
572 10:51:46.678152 dramc_set_vcore_voltage set vcore to 650000
573 10:51:46.678222 Read voltage for 800, 4
574 10:51:46.681450 Vio18 = 0
575 10:51:46.681517 Vcore = 650000
576 10:51:46.681578 Vdram = 0
577 10:51:46.685463 Vddq = 0
578 10:51:46.685531 Vmddr = 0
579 10:51:46.688175 dram_init: config_dvfs: 1
580 10:51:46.692012 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 10:51:46.698606 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 10:51:46.702175 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
583 10:51:46.705459 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
584 10:51:46.708479 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
585 10:51:46.712132 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
586 10:51:46.714964 MEM_TYPE=3, freq_sel=18
587 10:51:46.718613 sv_algorithm_assistance_LP4_1600
588 10:51:46.722053 ============ PULL DRAM RESETB DOWN ============
589 10:51:46.725546 ========== PULL DRAM RESETB DOWN end =========
590 10:51:46.731801 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 10:51:46.735335 ===================================
592 10:51:46.735418 LPDDR4 DRAM CONFIGURATION
593 10:51:46.738522 ===================================
594 10:51:46.741887 EX_ROW_EN[0] = 0x0
595 10:51:46.741962 EX_ROW_EN[1] = 0x0
596 10:51:46.745146 LP4Y_EN = 0x0
597 10:51:46.748524 WORK_FSP = 0x0
598 10:51:46.748594 WL = 0x2
599 10:51:46.752231 RL = 0x2
600 10:51:46.752298 BL = 0x2
601 10:51:46.755403 RPST = 0x0
602 10:51:46.755472 RD_PRE = 0x0
603 10:51:46.759277 WR_PRE = 0x1
604 10:51:46.759414 WR_PST = 0x0
605 10:51:46.762414 DBI_WR = 0x0
606 10:51:46.762480 DBI_RD = 0x0
607 10:51:46.765282 OTF = 0x1
608 10:51:46.768765 ===================================
609 10:51:46.772653 ===================================
610 10:51:46.772723 ANA top config
611 10:51:46.775360 ===================================
612 10:51:46.778929 DLL_ASYNC_EN = 0
613 10:51:46.782353 ALL_SLAVE_EN = 1
614 10:51:46.782420 NEW_RANK_MODE = 1
615 10:51:46.785990 DLL_IDLE_MODE = 1
616 10:51:46.788814 LP45_APHY_COMB_EN = 1
617 10:51:46.792082 TX_ODT_DIS = 1
618 10:51:46.792155 NEW_8X_MODE = 1
619 10:51:46.795430 ===================================
620 10:51:46.798721 ===================================
621 10:51:46.802181 data_rate = 1600
622 10:51:46.805678 CKR = 1
623 10:51:46.808979 DQ_P2S_RATIO = 8
624 10:51:46.812527 ===================================
625 10:51:46.815974 CA_P2S_RATIO = 8
626 10:51:46.818795 DQ_CA_OPEN = 0
627 10:51:46.818862 DQ_SEMI_OPEN = 0
628 10:51:46.822416 CA_SEMI_OPEN = 0
629 10:51:46.825786 CA_FULL_RATE = 0
630 10:51:46.828747 DQ_CKDIV4_EN = 1
631 10:51:46.832355 CA_CKDIV4_EN = 1
632 10:51:46.835618 CA_PREDIV_EN = 0
633 10:51:46.835689 PH8_DLY = 0
634 10:51:46.839115 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 10:51:46.842354 DQ_AAMCK_DIV = 4
636 10:51:46.845738 CA_AAMCK_DIV = 4
637 10:51:46.848776 CA_ADMCK_DIV = 4
638 10:51:46.852408 DQ_TRACK_CA_EN = 0
639 10:51:46.852477 CA_PICK = 800
640 10:51:46.855758 CA_MCKIO = 800
641 10:51:46.858689 MCKIO_SEMI = 0
642 10:51:46.862827 PLL_FREQ = 3068
643 10:51:46.865745 DQ_UI_PI_RATIO = 32
644 10:51:46.869838 CA_UI_PI_RATIO = 0
645 10:51:46.869911 ===================================
646 10:51:46.873372 ===================================
647 10:51:46.877527 memory_type:LPDDR4
648 10:51:46.880978 GP_NUM : 10
649 10:51:46.881051 SRAM_EN : 1
650 10:51:46.884445 MD32_EN : 0
651 10:51:46.884515 ===================================
652 10:51:46.888379 [ANA_INIT] >>>>>>>>>>>>>>
653 10:51:46.892035 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 10:51:46.895719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 10:51:46.899018 ===================================
656 10:51:46.902297 data_rate = 1600,PCW = 0X7600
657 10:51:46.905564 ===================================
658 10:51:46.908924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 10:51:46.912484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 10:51:46.919218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 10:51:46.923394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 10:51:46.926221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 10:51:46.929199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 10:51:46.932549 [ANA_INIT] flow start
665 10:51:46.935952 [ANA_INIT] PLL >>>>>>>>
666 10:51:46.936400 [ANA_INIT] PLL <<<<<<<<
667 10:51:46.939731 [ANA_INIT] MIDPI >>>>>>>>
668 10:51:46.942365 [ANA_INIT] MIDPI <<<<<<<<
669 10:51:46.942816 [ANA_INIT] DLL >>>>>>>>
670 10:51:46.946080 [ANA_INIT] flow end
671 10:51:46.949673 ============ LP4 DIFF to SE enter ============
672 10:51:46.952853 ============ LP4 DIFF to SE exit ============
673 10:51:46.956533 [ANA_INIT] <<<<<<<<<<<<<
674 10:51:46.959266 [Flow] Enable top DCM control >>>>>
675 10:51:46.962501 [Flow] Enable top DCM control <<<<<
676 10:51:46.966012 Enable DLL master slave shuffle
677 10:51:46.972874 ==============================================================
678 10:51:46.972964 Gating Mode config
679 10:51:46.979097 ==============================================================
680 10:51:46.979200 Config description:
681 10:51:46.989083 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 10:51:46.996016 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 10:51:47.002366 SELPH_MODE 0: By rank 1: By Phase
684 10:51:47.005643 ==============================================================
685 10:51:47.009109 GAT_TRACK_EN = 1
686 10:51:47.012526 RX_GATING_MODE = 2
687 10:51:47.015592 RX_GATING_TRACK_MODE = 2
688 10:51:47.019017 SELPH_MODE = 1
689 10:51:47.022460 PICG_EARLY_EN = 1
690 10:51:47.026030 VALID_LAT_VALUE = 1
691 10:51:47.029092 ==============================================================
692 10:51:47.032692 Enter into Gating configuration >>>>
693 10:51:47.036220 Exit from Gating configuration <<<<
694 10:51:47.038971 Enter into DVFS_PRE_config >>>>>
695 10:51:47.052404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 10:51:47.055788 Exit from DVFS_PRE_config <<<<<
697 10:51:47.058865 Enter into PICG configuration >>>>
698 10:51:47.058971 Exit from PICG configuration <<<<
699 10:51:47.062213 [RX_INPUT] configuration >>>>>
700 10:51:47.066153 [RX_INPUT] configuration <<<<<
701 10:51:47.072566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 10:51:47.075621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 10:51:47.083327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 10:51:47.089819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 10:51:47.096588 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 10:51:47.103592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 10:51:47.106243 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 10:51:47.109636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 10:51:47.113042 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 10:51:47.119863 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 10:51:47.123280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 10:51:47.126790 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 10:51:47.129852 ===================================
714 10:51:47.133202 LPDDR4 DRAM CONFIGURATION
715 10:51:47.136702 ===================================
716 10:51:47.136785 EX_ROW_EN[0] = 0x0
717 10:51:47.140191 EX_ROW_EN[1] = 0x0
718 10:51:47.140274 LP4Y_EN = 0x0
719 10:51:47.143272 WORK_FSP = 0x0
720 10:51:47.143361 WL = 0x2
721 10:51:47.146908 RL = 0x2
722 10:51:47.146990 BL = 0x2
723 10:51:47.149565 RPST = 0x0
724 10:51:47.153128 RD_PRE = 0x0
725 10:51:47.153211 WR_PRE = 0x1
726 10:51:47.156484 WR_PST = 0x0
727 10:51:47.156566 DBI_WR = 0x0
728 10:51:47.159974 DBI_RD = 0x0
729 10:51:47.160056 OTF = 0x1
730 10:51:47.163200 ===================================
731 10:51:47.166583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 10:51:47.169918 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 10:51:47.176870 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 10:51:47.179730 ===================================
735 10:51:47.183231 LPDDR4 DRAM CONFIGURATION
736 10:51:47.186875 ===================================
737 10:51:47.186958 EX_ROW_EN[0] = 0x10
738 10:51:47.190073 EX_ROW_EN[1] = 0x0
739 10:51:47.190156 LP4Y_EN = 0x0
740 10:51:47.193242 WORK_FSP = 0x0
741 10:51:47.193326 WL = 0x2
742 10:51:47.196519 RL = 0x2
743 10:51:47.196602 BL = 0x2
744 10:51:47.199761 RPST = 0x0
745 10:51:47.199844 RD_PRE = 0x0
746 10:51:47.203093 WR_PRE = 0x1
747 10:51:47.203176 WR_PST = 0x0
748 10:51:47.206697 DBI_WR = 0x0
749 10:51:47.206780 DBI_RD = 0x0
750 10:51:47.209589 OTF = 0x1
751 10:51:47.213040 ===================================
752 10:51:47.220119 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 10:51:47.223024 nWR fixed to 40
754 10:51:47.227234 [ModeRegInit_LP4] CH0 RK0
755 10:51:47.227317 [ModeRegInit_LP4] CH0 RK1
756 10:51:47.229946 [ModeRegInit_LP4] CH1 RK0
757 10:51:47.233585 [ModeRegInit_LP4] CH1 RK1
758 10:51:47.233668 match AC timing 13
759 10:51:47.240088 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 10:51:47.243154 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 10:51:47.246925 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 10:51:47.253541 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 10:51:47.256815 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 10:51:47.256899 [EMI DOE] emi_dcm 0
765 10:51:47.263368 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 10:51:47.263515 ==
767 10:51:47.266883 Dram Type= 6, Freq= 0, CH_0, rank 0
768 10:51:47.270239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 10:51:47.270325 ==
770 10:51:47.276574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 10:51:47.280072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 10:51:47.290523 [CA 0] Center 37 (6~68) winsize 63
773 10:51:47.294267 [CA 1] Center 37 (6~68) winsize 63
774 10:51:47.297593 [CA 2] Center 35 (4~66) winsize 63
775 10:51:47.300486 [CA 3] Center 34 (4~65) winsize 62
776 10:51:47.303866 [CA 4] Center 34 (3~65) winsize 63
777 10:51:47.307212 [CA 5] Center 33 (3~64) winsize 62
778 10:51:47.307296
779 10:51:47.310649 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 10:51:47.310732
781 10:51:47.313520 [CATrainingPosCal] consider 1 rank data
782 10:51:47.316903 u2DelayCellTimex100 = 270/100 ps
783 10:51:47.320849 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
784 10:51:47.323887 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 10:51:47.330642 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
786 10:51:47.333670 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 10:51:47.337138 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
788 10:51:47.340375 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 10:51:47.340458
790 10:51:47.343832 CA PerBit enable=1, Macro0, CA PI delay=33
791 10:51:47.343916
792 10:51:47.347330 [CBTSetCACLKResult] CA Dly = 33
793 10:51:47.347454 CS Dly: 5 (0~36)
794 10:51:47.350349 ==
795 10:51:47.350423 Dram Type= 6, Freq= 0, CH_0, rank 1
796 10:51:47.356764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 10:51:47.356845 ==
798 10:51:47.360245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 10:51:47.366960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 10:51:47.376512 [CA 0] Center 37 (6~68) winsize 63
801 10:51:47.380804 [CA 1] Center 37 (6~68) winsize 63
802 10:51:47.383613 [CA 2] Center 35 (4~66) winsize 63
803 10:51:47.386578 [CA 3] Center 35 (4~66) winsize 63
804 10:51:47.390184 [CA 4] Center 34 (3~65) winsize 63
805 10:51:47.393746 [CA 5] Center 33 (3~64) winsize 62
806 10:51:47.393829
807 10:51:47.396745 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 10:51:47.396827
809 10:51:47.400081 [CATrainingPosCal] consider 2 rank data
810 10:51:47.403694 u2DelayCellTimex100 = 270/100 ps
811 10:51:47.406478 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
812 10:51:47.413098 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
813 10:51:47.416758 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
814 10:51:47.420143 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 10:51:47.423703 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
816 10:51:47.426785 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 10:51:47.426867
818 10:51:47.430166 CA PerBit enable=1, Macro0, CA PI delay=33
819 10:51:47.430248
820 10:51:47.432997 [CBTSetCACLKResult] CA Dly = 33
821 10:51:47.433080 CS Dly: 5 (0~37)
822 10:51:47.436490
823 10:51:47.440055 ----->DramcWriteLeveling(PI) begin...
824 10:51:47.440139 ==
825 10:51:47.443076 Dram Type= 6, Freq= 0, CH_0, rank 0
826 10:51:47.447062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 10:51:47.447148 ==
828 10:51:47.450538 Write leveling (Byte 0): 31 => 31
829 10:51:47.454253 Write leveling (Byte 1): 30 => 30
830 10:51:47.454336 DramcWriteLeveling(PI) end<-----
831 10:51:47.454401
832 10:51:47.454460 ==
833 10:51:47.457894 Dram Type= 6, Freq= 0, CH_0, rank 0
834 10:51:47.464454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 10:51:47.464537 ==
836 10:51:47.464603 [Gating] SW mode calibration
837 10:51:47.471718 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 10:51:47.478030 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 10:51:47.481316 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 10:51:47.488111 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 10:51:47.491697 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 10:51:47.495189 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 10:51:47.501620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:51:47.505274 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 10:51:47.508120 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 10:51:47.515467 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 10:51:47.518018 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 10:51:47.521648 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 10:51:47.525115 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 10:51:47.531560 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 10:51:47.534784 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 10:51:47.538335 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 10:51:47.544632 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:51:47.548463 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:51:47.551791 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:51:47.558260 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 10:51:47.561605 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
858 10:51:47.565257 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:51:47.571666 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:51:47.574826 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:51:47.578309 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:51:47.585347 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:51:47.588601 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:51:47.591563 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:51:47.598476 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:51:47.601736 0 9 12 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
867 10:51:47.605532 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 10:51:47.608537 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 10:51:47.614916 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 10:51:47.618428 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 10:51:47.621996 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 10:51:47.628705 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
873 10:51:47.632085 0 10 8 | B1->B0 | 3232 3030 | 1 0 | (1 0) (1 1)
874 10:51:47.635173 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
875 10:51:47.641975 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:51:47.645554 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:51:47.648984 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:51:47.655476 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:51:47.658969 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 10:51:47.661875 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 10:51:47.668882 0 11 8 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 1)
882 10:51:47.672373 0 11 12 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
883 10:51:47.675741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 10:51:47.678490 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 10:51:47.685504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 10:51:47.688455 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 10:51:47.691947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 10:51:47.698544 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 10:51:47.702023 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 10:51:47.705623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 10:51:47.712012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 10:51:47.715630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 10:51:47.718543 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 10:51:47.725351 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 10:51:47.728856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 10:51:47.731859 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 10:51:47.738968 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 10:51:47.742131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 10:51:47.745388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 10:51:47.752060 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 10:51:47.755761 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:51:47.758761 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:51:47.762120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:51:47.769249 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:51:47.772012 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 10:51:47.775467 Total UI for P1: 0, mck2ui 16
907 10:51:47.778783 best dqsien dly found for B0: ( 0, 14, 6)
908 10:51:47.782083 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 10:51:47.785563 Total UI for P1: 0, mck2ui 16
910 10:51:47.788757 best dqsien dly found for B1: ( 0, 14, 8)
911 10:51:47.792331 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
912 10:51:47.795605 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 10:51:47.795686
914 10:51:47.802420 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 10:51:47.805604 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 10:51:47.805687 [Gating] SW calibration Done
917 10:51:47.809186 ==
918 10:51:47.812454 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:51:47.815339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:51:47.815426 ==
921 10:51:47.815492 RX Vref Scan: 0
922 10:51:47.815551
923 10:51:47.818935 RX Vref 0 -> 0, step: 1
924 10:51:47.819017
925 10:51:47.821924 RX Delay -130 -> 252, step: 16
926 10:51:47.825540 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
927 10:51:47.829029 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
928 10:51:47.835472 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
929 10:51:47.838807 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
930 10:51:47.842346 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
931 10:51:47.845275 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
932 10:51:47.848568 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
933 10:51:47.852130 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
934 10:51:47.858778 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
935 10:51:47.862806 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
936 10:51:47.865719 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
937 10:51:47.868789 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
938 10:51:47.872370 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
939 10:51:47.878579 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
940 10:51:47.881923 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
941 10:51:47.885374 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
942 10:51:47.885456 ==
943 10:51:47.888611 Dram Type= 6, Freq= 0, CH_0, rank 0
944 10:51:47.892192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 10:51:47.895591 ==
946 10:51:47.895673 DQS Delay:
947 10:51:47.895738 DQS0 = 0, DQS1 = 0
948 10:51:47.898948 DQM Delay:
949 10:51:47.899030 DQM0 = 83, DQM1 = 79
950 10:51:47.902355 DQ Delay:
951 10:51:47.902437 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 10:51:47.905226 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
953 10:51:47.908777 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
954 10:51:47.911725 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 10:51:47.911807
956 10:51:47.915221
957 10:51:47.915302 ==
958 10:51:47.918864 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:51:47.921779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:51:47.921862 ==
961 10:51:47.921927
962 10:51:47.921986
963 10:51:47.925232 TX Vref Scan disable
964 10:51:47.925314 == TX Byte 0 ==
965 10:51:47.932091 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
966 10:51:47.935332 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
967 10:51:47.935453 == TX Byte 1 ==
968 10:51:47.941900 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
969 10:51:47.945591 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
970 10:51:47.945673 ==
971 10:51:47.948953 Dram Type= 6, Freq= 0, CH_0, rank 0
972 10:51:47.952320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 10:51:47.952437 ==
974 10:51:47.966069 TX Vref=22, minBit 5, minWin=27, winSum=443
975 10:51:47.968997 TX Vref=24, minBit 5, minWin=27, winSum=446
976 10:51:47.972612 TX Vref=26, minBit 5, minWin=27, winSum=448
977 10:51:47.975559 TX Vref=28, minBit 12, minWin=27, winSum=453
978 10:51:47.978952 TX Vref=30, minBit 3, minWin=28, winSum=457
979 10:51:47.985741 TX Vref=32, minBit 12, minWin=27, winSum=457
980 10:51:47.989246 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
981 10:51:47.989330
982 10:51:47.992637 Final TX Range 1 Vref 30
983 10:51:47.992720
984 10:51:47.992785 ==
985 10:51:47.995510 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:51:47.998902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:51:47.998985 ==
988 10:51:48.002161
989 10:51:48.002242
990 10:51:48.002306 TX Vref Scan disable
991 10:51:48.005424 == TX Byte 0 ==
992 10:51:48.009184 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
993 10:51:48.015501 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
994 10:51:48.015583 == TX Byte 1 ==
995 10:51:48.018799 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
996 10:51:48.025789 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
997 10:51:48.025872
998 10:51:48.025936 [DATLAT]
999 10:51:48.025996 Freq=800, CH0 RK0
1000 10:51:48.026055
1001 10:51:48.028785 DATLAT Default: 0xa
1002 10:51:48.028867 0, 0xFFFF, sum = 0
1003 10:51:48.032557 1, 0xFFFF, sum = 0
1004 10:51:48.032640 2, 0xFFFF, sum = 0
1005 10:51:48.035868 3, 0xFFFF, sum = 0
1006 10:51:48.035951 4, 0xFFFF, sum = 0
1007 10:51:48.038893 5, 0xFFFF, sum = 0
1008 10:51:48.042455 6, 0xFFFF, sum = 0
1009 10:51:48.042539 7, 0xFFFF, sum = 0
1010 10:51:48.045869 8, 0xFFFF, sum = 0
1011 10:51:48.045952 9, 0x0, sum = 1
1012 10:51:48.046019 10, 0x0, sum = 2
1013 10:51:48.048663 11, 0x0, sum = 3
1014 10:51:48.048745 12, 0x0, sum = 4
1015 10:51:48.052542 best_step = 10
1016 10:51:48.052672
1017 10:51:48.052741 ==
1018 10:51:48.055344 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 10:51:48.058708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 10:51:48.058817 ==
1021 10:51:48.062100 RX Vref Scan: 1
1022 10:51:48.062216
1023 10:51:48.062313 Set Vref Range= 32 -> 127
1024 10:51:48.065517
1025 10:51:48.065630 RX Vref 32 -> 127, step: 1
1026 10:51:48.065736
1027 10:51:48.068883 RX Delay -95 -> 252, step: 8
1028 10:51:48.069005
1029 10:51:48.072169 Set Vref, RX VrefLevel [Byte0]: 32
1030 10:51:48.075715 [Byte1]: 32
1031 10:51:48.075796
1032 10:51:48.078705 Set Vref, RX VrefLevel [Byte0]: 33
1033 10:51:48.082077 [Byte1]: 33
1034 10:51:48.086090
1035 10:51:48.086201 Set Vref, RX VrefLevel [Byte0]: 34
1036 10:51:48.089494 [Byte1]: 34
1037 10:51:48.093848
1038 10:51:48.093930 Set Vref, RX VrefLevel [Byte0]: 35
1039 10:51:48.096784 [Byte1]: 35
1040 10:51:48.101376
1041 10:51:48.101477 Set Vref, RX VrefLevel [Byte0]: 36
1042 10:51:48.104767 [Byte1]: 36
1043 10:51:48.109128
1044 10:51:48.109201 Set Vref, RX VrefLevel [Byte0]: 37
1045 10:51:48.111897 [Byte1]: 37
1046 10:51:48.116673
1047 10:51:48.116781 Set Vref, RX VrefLevel [Byte0]: 38
1048 10:51:48.120125 [Byte1]: 38
1049 10:51:48.124452
1050 10:51:48.124549 Set Vref, RX VrefLevel [Byte0]: 39
1051 10:51:48.127680 [Byte1]: 39
1052 10:51:48.131935
1053 10:51:48.132005 Set Vref, RX VrefLevel [Byte0]: 40
1054 10:51:48.135361 [Byte1]: 40
1055 10:51:48.139156
1056 10:51:48.139267 Set Vref, RX VrefLevel [Byte0]: 41
1057 10:51:48.142511 [Byte1]: 41
1058 10:51:48.146667
1059 10:51:48.146772 Set Vref, RX VrefLevel [Byte0]: 42
1060 10:51:48.149952 [Byte1]: 42
1061 10:51:48.154373
1062 10:51:48.154447 Set Vref, RX VrefLevel [Byte0]: 43
1063 10:51:48.157552 [Byte1]: 43
1064 10:51:48.161760
1065 10:51:48.161840 Set Vref, RX VrefLevel [Byte0]: 44
1066 10:51:48.165095 [Byte1]: 44
1067 10:51:48.169242
1068 10:51:48.169323 Set Vref, RX VrefLevel [Byte0]: 45
1069 10:51:48.172731 [Byte1]: 45
1070 10:51:48.177436
1071 10:51:48.177517 Set Vref, RX VrefLevel [Byte0]: 46
1072 10:51:48.180336 [Byte1]: 46
1073 10:51:48.184901
1074 10:51:48.184982 Set Vref, RX VrefLevel [Byte0]: 47
1075 10:51:48.188255 [Byte1]: 47
1076 10:51:48.192432
1077 10:51:48.192512 Set Vref, RX VrefLevel [Byte0]: 48
1078 10:51:48.195680 [Byte1]: 48
1079 10:51:48.200107
1080 10:51:48.200188 Set Vref, RX VrefLevel [Byte0]: 49
1081 10:51:48.203412 [Byte1]: 49
1082 10:51:48.207490
1083 10:51:48.207571 Set Vref, RX VrefLevel [Byte0]: 50
1084 10:51:48.210785 [Byte1]: 50
1085 10:51:48.215256
1086 10:51:48.215387 Set Vref, RX VrefLevel [Byte0]: 51
1087 10:51:48.218723 [Byte1]: 51
1088 10:51:48.222909
1089 10:51:48.222990 Set Vref, RX VrefLevel [Byte0]: 52
1090 10:51:48.225905 [Byte1]: 52
1091 10:51:48.230543
1092 10:51:48.230624 Set Vref, RX VrefLevel [Byte0]: 53
1093 10:51:48.233664 [Byte1]: 53
1094 10:51:48.237740
1095 10:51:48.237821 Set Vref, RX VrefLevel [Byte0]: 54
1096 10:51:48.241287 [Byte1]: 54
1097 10:51:48.245742
1098 10:51:48.245823 Set Vref, RX VrefLevel [Byte0]: 55
1099 10:51:48.248602 [Byte1]: 55
1100 10:51:48.253358
1101 10:51:48.253438 Set Vref, RX VrefLevel [Byte0]: 56
1102 10:51:48.256667 [Byte1]: 56
1103 10:51:48.260907
1104 10:51:48.261008 Set Vref, RX VrefLevel [Byte0]: 57
1105 10:51:48.263839 [Byte1]: 57
1106 10:51:48.268165
1107 10:51:48.268246 Set Vref, RX VrefLevel [Byte0]: 58
1108 10:51:48.271627 [Byte1]: 58
1109 10:51:48.275842
1110 10:51:48.275918 Set Vref, RX VrefLevel [Byte0]: 59
1111 10:51:48.279370 [Byte1]: 59
1112 10:51:48.283370
1113 10:51:48.283465 Set Vref, RX VrefLevel [Byte0]: 60
1114 10:51:48.287064 [Byte1]: 60
1115 10:51:48.291106
1116 10:51:48.291186 Set Vref, RX VrefLevel [Byte0]: 61
1117 10:51:48.294447 [Byte1]: 61
1118 10:51:48.298507
1119 10:51:48.298587 Set Vref, RX VrefLevel [Byte0]: 62
1120 10:51:48.301950 [Byte1]: 62
1121 10:51:48.306489
1122 10:51:48.306572 Set Vref, RX VrefLevel [Byte0]: 63
1123 10:51:48.309938 [Byte1]: 63
1124 10:51:48.313752
1125 10:51:48.313833 Set Vref, RX VrefLevel [Byte0]: 64
1126 10:51:48.317086 [Byte1]: 64
1127 10:51:48.321350
1128 10:51:48.321431 Set Vref, RX VrefLevel [Byte0]: 65
1129 10:51:48.324952 [Byte1]: 65
1130 10:51:48.329174
1131 10:51:48.329257 Set Vref, RX VrefLevel [Byte0]: 66
1132 10:51:48.332053 [Byte1]: 66
1133 10:51:48.336726
1134 10:51:48.336807 Set Vref, RX VrefLevel [Byte0]: 67
1135 10:51:48.339685 [Byte1]: 67
1136 10:51:48.344292
1137 10:51:48.344373 Set Vref, RX VrefLevel [Byte0]: 68
1138 10:51:48.347664 [Byte1]: 68
1139 10:51:48.351795
1140 10:51:48.351875 Set Vref, RX VrefLevel [Byte0]: 69
1141 10:51:48.354904 [Byte1]: 69
1142 10:51:48.359432
1143 10:51:48.359512 Set Vref, RX VrefLevel [Byte0]: 70
1144 10:51:48.362723 [Byte1]: 70
1145 10:51:48.367104
1146 10:51:48.367198 Set Vref, RX VrefLevel [Byte0]: 71
1147 10:51:48.370360 [Byte1]: 71
1148 10:51:48.374287
1149 10:51:48.374367 Set Vref, RX VrefLevel [Byte0]: 72
1150 10:51:48.377935 [Byte1]: 72
1151 10:51:48.381990
1152 10:51:48.382071 Set Vref, RX VrefLevel [Byte0]: 73
1153 10:51:48.385530 [Byte1]: 73
1154 10:51:48.389781
1155 10:51:48.389861 Set Vref, RX VrefLevel [Byte0]: 74
1156 10:51:48.393342 [Byte1]: 74
1157 10:51:48.397373
1158 10:51:48.397454 Set Vref, RX VrefLevel [Byte0]: 75
1159 10:51:48.400718 [Byte1]: 75
1160 10:51:48.405142
1161 10:51:48.405222 Set Vref, RX VrefLevel [Byte0]: 76
1162 10:51:48.408129 [Byte1]: 76
1163 10:51:48.412788
1164 10:51:48.412869 Set Vref, RX VrefLevel [Byte0]: 77
1165 10:51:48.415955 [Byte1]: 77
1166 10:51:48.420065
1167 10:51:48.420145 Final RX Vref Byte 0 = 61 to rank0
1168 10:51:48.423316 Final RX Vref Byte 1 = 57 to rank0
1169 10:51:48.426756 Final RX Vref Byte 0 = 61 to rank1
1170 10:51:48.429982 Final RX Vref Byte 1 = 57 to rank1==
1171 10:51:48.433219 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 10:51:48.436794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 10:51:48.440327 ==
1174 10:51:48.440410 DQS Delay:
1175 10:51:48.440475 DQS0 = 0, DQS1 = 0
1176 10:51:48.443406 DQM Delay:
1177 10:51:48.443501 DQM0 = 87, DQM1 = 79
1178 10:51:48.446925 DQ Delay:
1179 10:51:48.450235 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1180 10:51:48.450317 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1181 10:51:48.453654 DQ8 =68, DQ9 =64, DQ10 =84, DQ11 =76
1182 10:51:48.456730 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1183 10:51:48.456811
1184 10:51:48.460379
1185 10:51:48.466769 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1186 10:51:48.470348 CH0 RK0: MR19=606, MR18=2B11
1187 10:51:48.476927 CH0_RK0: MR19=0x606, MR18=0x2B11, DQSOSC=398, MR23=63, INC=93, DEC=62
1188 10:51:48.477010
1189 10:51:48.480552 ----->DramcWriteLeveling(PI) begin...
1190 10:51:48.480634 ==
1191 10:51:48.483461 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 10:51:48.487001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 10:51:48.487083 ==
1194 10:51:48.490103 Write leveling (Byte 0): 31 => 31
1195 10:51:48.493684 Write leveling (Byte 1): 29 => 29
1196 10:51:48.496947 DramcWriteLeveling(PI) end<-----
1197 10:51:48.497027
1198 10:51:48.497090 ==
1199 10:51:48.499967 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 10:51:48.503361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 10:51:48.503443 ==
1202 10:51:48.506937 [Gating] SW mode calibration
1203 10:51:48.513385 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 10:51:48.519997 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 10:51:48.564158 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 10:51:48.564261 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1207 10:51:48.564328 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1208 10:51:48.564573 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 10:51:48.564819 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 10:51:48.564945 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 10:51:48.565188 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 10:51:48.565252 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 10:51:48.565489 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 10:51:48.565560 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 10:51:48.608592 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 10:51:48.608873 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 10:51:48.608942 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 10:51:48.609185 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:51:48.609253 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:51:48.609747 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:51:48.610326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:51:48.610409 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1223 10:51:48.610653 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1224 10:51:48.610911 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 10:51:48.621231 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:51:48.621873 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:51:48.621956 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:51:48.624667 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:51:48.627509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:51:48.634210 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:51:48.637762 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1232 10:51:48.641310 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
1233 10:51:48.647925 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 10:51:48.650903 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 10:51:48.654474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 10:51:48.661215 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 10:51:48.664624 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 10:51:48.668185 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1239 10:51:48.671611 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1240 10:51:48.678401 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:51:48.681306 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:51:48.684556 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:51:48.691643 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:51:48.695147 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:51:48.698859 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:51:48.702245 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1247 10:51:48.709000 0 11 8 | B1->B0 | 2929 4040 | 0 0 | (0 0) (0 0)
1248 10:51:48.712478 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1249 10:51:48.715461 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 10:51:48.723467 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 10:51:48.726602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 10:51:48.729982 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 10:51:48.733417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 10:51:48.739858 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1255 10:51:48.742970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1256 10:51:48.746619 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1257 10:51:48.753113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 10:51:48.756719 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 10:51:48.759582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 10:51:48.766329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 10:51:48.769777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 10:51:48.773355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 10:51:48.780460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 10:51:48.783536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 10:51:48.786485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 10:51:48.793138 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:51:48.796248 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:51:48.799828 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:51:48.803203 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1270 10:51:48.809733 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1271 10:51:48.812911 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1272 10:51:48.816556 Total UI for P1: 0, mck2ui 16
1273 10:51:48.819581 best dqsien dly found for B0: ( 0, 14, 2)
1274 10:51:48.823109 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 10:51:48.826154 Total UI for P1: 0, mck2ui 16
1276 10:51:48.829796 best dqsien dly found for B1: ( 0, 14, 8)
1277 10:51:48.832970 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1278 10:51:48.836408 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1279 10:51:48.839644
1280 10:51:48.843178 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1281 10:51:48.846149 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 10:51:48.849976 [Gating] SW calibration Done
1283 10:51:48.850046 ==
1284 10:51:48.852838 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 10:51:48.856376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 10:51:48.856448 ==
1287 10:51:48.856514 RX Vref Scan: 0
1288 10:51:48.856574
1289 10:51:48.859284 RX Vref 0 -> 0, step: 1
1290 10:51:48.859405
1291 10:51:48.862748 RX Delay -130 -> 252, step: 16
1292 10:51:48.866195 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1293 10:51:48.869648 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 10:51:48.876247 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1295 10:51:48.879705 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1296 10:51:48.882986 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1297 10:51:48.886194 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1298 10:51:48.889489 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1299 10:51:48.895914 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1300 10:51:48.899383 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1301 10:51:48.903001 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1302 10:51:48.905873 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1303 10:51:48.909275 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1304 10:51:48.916133 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1305 10:51:48.919752 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1306 10:51:48.922584 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1307 10:51:48.925991 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1308 10:51:48.926065 ==
1309 10:51:48.929459 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 10:51:48.936014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 10:51:48.936099 ==
1312 10:51:48.936163 DQS Delay:
1313 10:51:48.936223 DQS0 = 0, DQS1 = 0
1314 10:51:48.939233 DQM Delay:
1315 10:51:48.939308 DQM0 = 86, DQM1 = 77
1316 10:51:48.942748 DQ Delay:
1317 10:51:48.945728 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1318 10:51:48.949207 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1319 10:51:48.952836 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1320 10:51:48.955845 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1321 10:51:48.955927
1322 10:51:48.956027
1323 10:51:48.956085 ==
1324 10:51:48.959573 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 10:51:48.962494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 10:51:48.962575 ==
1327 10:51:48.962642
1328 10:51:48.962701
1329 10:51:48.965877 TX Vref Scan disable
1330 10:51:48.965958 == TX Byte 0 ==
1331 10:51:48.972675 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1332 10:51:48.976413 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1333 10:51:48.976495 == TX Byte 1 ==
1334 10:51:48.982598 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1335 10:51:48.985757 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1336 10:51:48.985838 ==
1337 10:51:48.989339 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 10:51:48.992500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 10:51:48.992582 ==
1340 10:51:49.006963 TX Vref=22, minBit 8, minWin=27, winSum=443
1341 10:51:49.010003 TX Vref=24, minBit 8, minWin=27, winSum=447
1342 10:51:49.013599 TX Vref=26, minBit 9, minWin=27, winSum=451
1343 10:51:49.016527 TX Vref=28, minBit 9, minWin=27, winSum=451
1344 10:51:49.019815 TX Vref=30, minBit 2, minWin=28, winSum=457
1345 10:51:49.023287 TX Vref=32, minBit 2, minWin=28, winSum=455
1346 10:51:49.030131 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
1347 10:51:49.030218
1348 10:51:49.033553 Final TX Range 1 Vref 30
1349 10:51:49.033633
1350 10:51:49.033695 ==
1351 10:51:49.037050 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 10:51:49.039797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 10:51:49.039878 ==
1354 10:51:49.039941
1355 10:51:49.043168
1356 10:51:49.043246 TX Vref Scan disable
1357 10:51:49.046537 == TX Byte 0 ==
1358 10:51:49.050445 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1359 10:51:49.056841 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1360 10:51:49.056937 == TX Byte 1 ==
1361 10:51:49.059877 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1362 10:51:49.066508 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1363 10:51:49.066588
1364 10:51:49.066650 [DATLAT]
1365 10:51:49.066708 Freq=800, CH0 RK1
1366 10:51:49.066764
1367 10:51:49.070075 DATLAT Default: 0xa
1368 10:51:49.070155 0, 0xFFFF, sum = 0
1369 10:51:49.073502 1, 0xFFFF, sum = 0
1370 10:51:49.073584 2, 0xFFFF, sum = 0
1371 10:51:49.076428 3, 0xFFFF, sum = 0
1372 10:51:49.079929 4, 0xFFFF, sum = 0
1373 10:51:49.080010 5, 0xFFFF, sum = 0
1374 10:51:49.083429 6, 0xFFFF, sum = 0
1375 10:51:49.083509 7, 0xFFFF, sum = 0
1376 10:51:49.086470 8, 0xFFFF, sum = 0
1377 10:51:49.086551 9, 0x0, sum = 1
1378 10:51:49.086614 10, 0x0, sum = 2
1379 10:51:49.090068 11, 0x0, sum = 3
1380 10:51:49.090148 12, 0x0, sum = 4
1381 10:51:49.093434 best_step = 10
1382 10:51:49.093513
1383 10:51:49.093574 ==
1384 10:51:49.096740 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 10:51:49.100558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 10:51:49.100638 ==
1387 10:51:49.103702 RX Vref Scan: 0
1388 10:51:49.103781
1389 10:51:49.103842 RX Vref 0 -> 0, step: 1
1390 10:51:49.103902
1391 10:51:49.106267 RX Delay -95 -> 252, step: 8
1392 10:51:49.113391 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1393 10:51:49.116393 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1394 10:51:49.119844 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1395 10:51:49.122937 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1396 10:51:49.126622 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1397 10:51:49.133000 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1398 10:51:49.136345 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1399 10:51:49.139800 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1400 10:51:49.143092 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1401 10:51:49.146354 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1402 10:51:49.152981 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1403 10:51:49.156570 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1404 10:51:49.160237 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1405 10:51:49.163100 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1406 10:51:49.169911 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1407 10:51:49.173433 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1408 10:51:49.173512 ==
1409 10:51:49.176548 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 10:51:49.179870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 10:51:49.179950 ==
1412 10:51:49.180012 DQS Delay:
1413 10:51:49.182755 DQS0 = 0, DQS1 = 0
1414 10:51:49.182834 DQM Delay:
1415 10:51:49.186530 DQM0 = 87, DQM1 = 78
1416 10:51:49.186609 DQ Delay:
1417 10:51:49.189988 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1418 10:51:49.192797 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1419 10:51:49.196638 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1420 10:51:49.199735 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1421 10:51:49.199815
1422 10:51:49.199879
1423 10:51:49.210047 [DQSOSCAuto] RK1, (LSB)MR18= 0x321b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1424 10:51:49.210130 CH0 RK1: MR19=606, MR18=321B
1425 10:51:49.216453 CH0_RK1: MR19=0x606, MR18=0x321B, DQSOSC=397, MR23=63, INC=93, DEC=62
1426 10:51:49.220037 [RxdqsGatingPostProcess] freq 800
1427 10:51:49.226547 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 10:51:49.230058 Pre-setting of DQS Precalculation
1429 10:51:49.233053 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 10:51:49.233135 ==
1431 10:51:49.236345 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 10:51:49.240074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 10:51:49.240156 ==
1434 10:51:49.246812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 10:51:49.253277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 10:51:49.261486 [CA 0] Center 36 (6~67) winsize 62
1437 10:51:49.265026 [CA 1] Center 36 (6~67) winsize 62
1438 10:51:49.268077 [CA 2] Center 34 (4~64) winsize 61
1439 10:51:49.271454 [CA 3] Center 33 (3~64) winsize 62
1440 10:51:49.275145 [CA 4] Center 34 (3~65) winsize 63
1441 10:51:49.278067 [CA 5] Center 33 (3~64) winsize 62
1442 10:51:49.278148
1443 10:51:49.281277 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1444 10:51:49.281358
1445 10:51:49.285001 [CATrainingPosCal] consider 1 rank data
1446 10:51:49.288266 u2DelayCellTimex100 = 270/100 ps
1447 10:51:49.291455 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1448 10:51:49.294958 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1449 10:51:49.301564 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1450 10:51:49.305311 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1451 10:51:49.308442 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1452 10:51:49.311442 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1453 10:51:49.311524
1454 10:51:49.315088 CA PerBit enable=1, Macro0, CA PI delay=33
1455 10:51:49.315170
1456 10:51:49.318101 [CBTSetCACLKResult] CA Dly = 33
1457 10:51:49.318181 CS Dly: 4 (0~35)
1458 10:51:49.318245 ==
1459 10:51:49.321642 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 10:51:49.327889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 10:51:49.327974 ==
1462 10:51:49.331548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 10:51:49.338414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 10:51:49.347515 [CA 0] Center 36 (5~67) winsize 63
1465 10:51:49.351169 [CA 1] Center 36 (5~67) winsize 63
1466 10:51:49.354626 [CA 2] Center 34 (4~64) winsize 61
1467 10:51:49.357360 [CA 3] Center 33 (3~64) winsize 62
1468 10:51:49.361494 [CA 4] Center 34 (3~65) winsize 63
1469 10:51:49.364700 [CA 5] Center 33 (3~64) winsize 62
1470 10:51:49.364796
1471 10:51:49.368495 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1472 10:51:49.368577
1473 10:51:49.372382 [CATrainingPosCal] consider 2 rank data
1474 10:51:49.376236 u2DelayCellTimex100 = 270/100 ps
1475 10:51:49.379495 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1476 10:51:49.383040 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1477 10:51:49.386991 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1478 10:51:49.390545 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1479 10:51:49.394566 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1480 10:51:49.397546 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1481 10:51:49.397656
1482 10:51:49.400923 CA PerBit enable=1, Macro0, CA PI delay=33
1483 10:51:49.401005
1484 10:51:49.404569 [CBTSetCACLKResult] CA Dly = 33
1485 10:51:49.404651 CS Dly: 5 (0~38)
1486 10:51:49.404715
1487 10:51:49.407624 ----->DramcWriteLeveling(PI) begin...
1488 10:51:49.407708 ==
1489 10:51:49.411160 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 10:51:49.418017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 10:51:49.418118 ==
1492 10:51:49.420927 Write leveling (Byte 0): 27 => 27
1493 10:51:49.424489 Write leveling (Byte 1): 30 => 30
1494 10:51:49.424561 DramcWriteLeveling(PI) end<-----
1495 10:51:49.427808
1496 10:51:49.427879 ==
1497 10:51:49.431286 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 10:51:49.434411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 10:51:49.434507 ==
1500 10:51:49.437702 [Gating] SW mode calibration
1501 10:51:49.444371 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 10:51:49.447990 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 10:51:49.454720 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 10:51:49.457678 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 10:51:49.460971 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1506 10:51:49.468009 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 10:51:49.471188 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 10:51:49.474025 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 10:51:49.481185 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 10:51:49.484191 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 10:51:49.487744 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 10:51:49.494649 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 10:51:49.497557 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 10:51:49.501465 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 10:51:49.504188 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:51:49.511116 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:51:49.514659 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:51:49.518373 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:51:49.524301 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:51:49.527621 0 8 4 | B1->B0 | 2322 2323 | 1 0 | (0 1) (0 0)
1521 10:51:49.531239 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 10:51:49.537856 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:51:49.541250 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:51:49.544518 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:51:49.551260 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:51:49.554750 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:51:49.558106 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:51:49.564472 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:51:49.567938 0 9 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1530 10:51:49.571041 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1531 10:51:49.577648 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 10:51:49.580951 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 10:51:49.584553 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 10:51:49.591053 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 10:51:49.594336 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 10:51:49.598271 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
1537 10:51:49.601258 0 10 8 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (0 0)
1538 10:51:49.608201 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 10:51:49.611018 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:51:49.614804 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:51:49.621169 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:51:49.624581 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:51:49.628170 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:51:49.635056 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:51:49.638233 0 11 8 | B1->B0 | 3737 3333 | 1 0 | (0 0) (0 0)
1546 10:51:49.641487 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 10:51:49.647978 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 10:51:49.651316 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 10:51:49.654427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 10:51:49.661125 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 10:51:49.664943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 10:51:49.667906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 10:51:49.674581 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 10:51:49.678122 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 10:51:49.681788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 10:51:49.684768 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 10:51:49.691283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 10:51:49.694901 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 10:51:49.698187 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 10:51:49.704637 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 10:51:49.708092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 10:51:49.711521 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 10:51:49.718167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:51:49.721454 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:51:49.724690 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:51:49.731590 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:51:49.734920 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:51:49.737815 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:51:49.744834 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 10:51:49.744942 Total UI for P1: 0, mck2ui 16
1571 10:51:49.751308 best dqsien dly found for B0: ( 0, 14, 6)
1572 10:51:49.751452 Total UI for P1: 0, mck2ui 16
1573 10:51:49.754742 best dqsien dly found for B1: ( 0, 14, 6)
1574 10:51:49.761584 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1575 10:51:49.764536 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1576 10:51:49.764624
1577 10:51:49.767824 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1578 10:51:49.771341 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1579 10:51:49.774633 [Gating] SW calibration Done
1580 10:51:49.774758 ==
1581 10:51:49.778529 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 10:51:49.781142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 10:51:49.781247 ==
1584 10:51:49.781347 RX Vref Scan: 0
1585 10:51:49.784590
1586 10:51:49.784674 RX Vref 0 -> 0, step: 1
1587 10:51:49.784767
1588 10:51:49.787635 RX Delay -130 -> 252, step: 16
1589 10:51:49.791123 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1590 10:51:49.798282 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1591 10:51:49.801136 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1592 10:51:49.804596 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1593 10:51:49.807767 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1594 10:51:49.811267 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1595 10:51:49.814861 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1596 10:51:49.821051 iDelay=222, Bit 7, Center 69 (-50 ~ 189) 240
1597 10:51:49.824580 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1598 10:51:49.827937 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1599 10:51:49.831023 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1600 10:51:49.838052 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1601 10:51:49.840995 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1602 10:51:49.844561 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1603 10:51:49.847542 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1604 10:51:49.850951 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1605 10:51:49.851025 ==
1606 10:51:49.854454 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 10:51:49.860835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 10:51:49.860938 ==
1609 10:51:49.861040 DQS Delay:
1610 10:51:49.864341 DQS0 = 0, DQS1 = 0
1611 10:51:49.864449 DQM Delay:
1612 10:51:49.864550 DQM0 = 81, DQM1 = 76
1613 10:51:49.867680 DQ Delay:
1614 10:51:49.871048 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1615 10:51:49.874370 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1616 10:51:49.877632 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1617 10:51:49.881014 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1618 10:51:49.881097
1619 10:51:49.881167
1620 10:51:49.881226 ==
1621 10:51:49.884320 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 10:51:49.887835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 10:51:49.887934 ==
1624 10:51:49.888033
1625 10:51:49.888095
1626 10:51:49.891222 TX Vref Scan disable
1627 10:51:49.894800 == TX Byte 0 ==
1628 10:51:49.897694 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1629 10:51:49.901328 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1630 10:51:49.904761 == TX Byte 1 ==
1631 10:51:49.907443 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1632 10:51:49.911378 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1633 10:51:49.911482 ==
1634 10:51:49.914349 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 10:51:49.917835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 10:51:49.917933 ==
1637 10:51:49.932072 TX Vref=22, minBit 0, minWin=27, winSum=436
1638 10:51:49.935547 TX Vref=24, minBit 0, minWin=27, winSum=439
1639 10:51:49.938807 TX Vref=26, minBit 2, minWin=27, winSum=443
1640 10:51:49.942686 TX Vref=28, minBit 10, minWin=27, winSum=450
1641 10:51:49.946265 TX Vref=30, minBit 6, minWin=28, winSum=456
1642 10:51:49.949296 TX Vref=32, minBit 1, minWin=28, winSum=456
1643 10:51:49.956363 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 30
1644 10:51:49.956442
1645 10:51:49.959796 Final TX Range 1 Vref 30
1646 10:51:49.959895
1647 10:51:49.959992 ==
1648 10:51:49.962750 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 10:51:49.966055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 10:51:49.966135 ==
1651 10:51:49.966233
1652 10:51:49.966330
1653 10:51:49.969491 TX Vref Scan disable
1654 10:51:49.972970 == TX Byte 0 ==
1655 10:51:49.976421 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1656 10:51:49.979303 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1657 10:51:49.983255 == TX Byte 1 ==
1658 10:51:49.985946 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1659 10:51:49.989789 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1660 10:51:49.989915
1661 10:51:49.993101 [DATLAT]
1662 10:51:49.993274 Freq=800, CH1 RK0
1663 10:51:49.993383
1664 10:51:49.996236 DATLAT Default: 0xa
1665 10:51:49.996318 0, 0xFFFF, sum = 0
1666 10:51:49.999774 1, 0xFFFF, sum = 0
1667 10:51:49.999859 2, 0xFFFF, sum = 0
1668 10:51:50.002750 3, 0xFFFF, sum = 0
1669 10:51:50.002849 4, 0xFFFF, sum = 0
1670 10:51:50.006328 5, 0xFFFF, sum = 0
1671 10:51:50.006437 6, 0xFFFF, sum = 0
1672 10:51:50.009281 7, 0xFFFF, sum = 0
1673 10:51:50.009405 8, 0xFFFF, sum = 0
1674 10:51:50.012757 9, 0x0, sum = 1
1675 10:51:50.012870 10, 0x0, sum = 2
1676 10:51:50.016146 11, 0x0, sum = 3
1677 10:51:50.016259 12, 0x0, sum = 4
1678 10:51:50.019628 best_step = 10
1679 10:51:50.019715
1680 10:51:50.019803 ==
1681 10:51:50.022726 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 10:51:50.026210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 10:51:50.026317 ==
1684 10:51:50.026380 RX Vref Scan: 1
1685 10:51:50.026453
1686 10:51:50.029453 Set Vref Range= 32 -> 127
1687 10:51:50.029558
1688 10:51:50.032966 RX Vref 32 -> 127, step: 1
1689 10:51:50.033065
1690 10:51:50.036301 RX Delay -111 -> 252, step: 8
1691 10:51:50.036396
1692 10:51:50.039786 Set Vref, RX VrefLevel [Byte0]: 32
1693 10:51:50.042649 [Byte1]: 32
1694 10:51:50.042729
1695 10:51:50.046626 Set Vref, RX VrefLevel [Byte0]: 33
1696 10:51:50.049649 [Byte1]: 33
1697 10:51:50.049729
1698 10:51:50.053341 Set Vref, RX VrefLevel [Byte0]: 34
1699 10:51:50.056147 [Byte1]: 34
1700 10:51:50.060254
1701 10:51:50.060334 Set Vref, RX VrefLevel [Byte0]: 35
1702 10:51:50.063697 [Byte1]: 35
1703 10:51:50.068256
1704 10:51:50.068335 Set Vref, RX VrefLevel [Byte0]: 36
1705 10:51:50.070950 [Byte1]: 36
1706 10:51:50.075379
1707 10:51:50.075472 Set Vref, RX VrefLevel [Byte0]: 37
1708 10:51:50.078893 [Byte1]: 37
1709 10:51:50.083111
1710 10:51:50.083199 Set Vref, RX VrefLevel [Byte0]: 38
1711 10:51:50.086394 [Byte1]: 38
1712 10:51:50.090650
1713 10:51:50.090731 Set Vref, RX VrefLevel [Byte0]: 39
1714 10:51:50.093962 [Byte1]: 39
1715 10:51:50.098429
1716 10:51:50.098499 Set Vref, RX VrefLevel [Byte0]: 40
1717 10:51:50.101971 [Byte1]: 40
1718 10:51:50.106115
1719 10:51:50.106190 Set Vref, RX VrefLevel [Byte0]: 41
1720 10:51:50.109152 [Byte1]: 41
1721 10:51:50.113752
1722 10:51:50.113824 Set Vref, RX VrefLevel [Byte0]: 42
1723 10:51:50.116725 [Byte1]: 42
1724 10:51:50.121384
1725 10:51:50.121468 Set Vref, RX VrefLevel [Byte0]: 43
1726 10:51:50.124790 [Byte1]: 43
1727 10:51:50.129039
1728 10:51:50.129121 Set Vref, RX VrefLevel [Byte0]: 44
1729 10:51:50.132249 [Byte1]: 44
1730 10:51:50.136819
1731 10:51:50.136900 Set Vref, RX VrefLevel [Byte0]: 45
1732 10:51:50.140164 [Byte1]: 45
1733 10:51:50.144553
1734 10:51:50.144652 Set Vref, RX VrefLevel [Byte0]: 46
1735 10:51:50.147602 [Byte1]: 46
1736 10:51:50.151982
1737 10:51:50.152061 Set Vref, RX VrefLevel [Byte0]: 47
1738 10:51:50.155448 [Byte1]: 47
1739 10:51:50.159586
1740 10:51:50.159662 Set Vref, RX VrefLevel [Byte0]: 48
1741 10:51:50.163180 [Byte1]: 48
1742 10:51:50.167053
1743 10:51:50.167128 Set Vref, RX VrefLevel [Byte0]: 49
1744 10:51:50.170490 [Byte1]: 49
1745 10:51:50.175085
1746 10:51:50.175163 Set Vref, RX VrefLevel [Byte0]: 50
1747 10:51:50.178237 [Byte1]: 50
1748 10:51:50.182767
1749 10:51:50.182842 Set Vref, RX VrefLevel [Byte0]: 51
1750 10:51:50.185999 [Byte1]: 51
1751 10:51:50.190011
1752 10:51:50.190088 Set Vref, RX VrefLevel [Byte0]: 52
1753 10:51:50.193388 [Byte1]: 52
1754 10:51:50.197853
1755 10:51:50.197929 Set Vref, RX VrefLevel [Byte0]: 53
1756 10:51:50.201270 [Byte1]: 53
1757 10:51:50.205255
1758 10:51:50.205322 Set Vref, RX VrefLevel [Byte0]: 54
1759 10:51:50.208755 [Byte1]: 54
1760 10:51:50.212900
1761 10:51:50.212972 Set Vref, RX VrefLevel [Byte0]: 55
1762 10:51:50.216476 [Byte1]: 55
1763 10:51:50.220879
1764 10:51:50.220953 Set Vref, RX VrefLevel [Byte0]: 56
1765 10:51:50.223852 [Byte1]: 56
1766 10:51:50.228687
1767 10:51:50.228762 Set Vref, RX VrefLevel [Byte0]: 57
1768 10:51:50.231669 [Byte1]: 57
1769 10:51:50.236198
1770 10:51:50.236273 Set Vref, RX VrefLevel [Byte0]: 58
1771 10:51:50.239632 [Byte1]: 58
1772 10:51:50.243916
1773 10:51:50.243991 Set Vref, RX VrefLevel [Byte0]: 59
1774 10:51:50.246762 [Byte1]: 59
1775 10:51:50.251674
1776 10:51:50.251755 Set Vref, RX VrefLevel [Byte0]: 60
1777 10:51:50.254946 [Byte1]: 60
1778 10:51:50.258837
1779 10:51:50.258919 Set Vref, RX VrefLevel [Byte0]: 61
1780 10:51:50.262439 [Byte1]: 61
1781 10:51:50.266603
1782 10:51:50.266684 Set Vref, RX VrefLevel [Byte0]: 62
1783 10:51:50.270276 [Byte1]: 62
1784 10:51:50.274389
1785 10:51:50.274470 Set Vref, RX VrefLevel [Byte0]: 63
1786 10:51:50.277896 [Byte1]: 63
1787 10:51:50.281735
1788 10:51:50.281816 Set Vref, RX VrefLevel [Byte0]: 64
1789 10:51:50.285676 [Byte1]: 64
1790 10:51:50.289677
1791 10:51:50.289758 Set Vref, RX VrefLevel [Byte0]: 65
1792 10:51:50.293085 [Byte1]: 65
1793 10:51:50.297104
1794 10:51:50.297201 Set Vref, RX VrefLevel [Byte0]: 66
1795 10:51:50.300491 [Byte1]: 66
1796 10:51:50.304981
1797 10:51:50.305063 Set Vref, RX VrefLevel [Byte0]: 67
1798 10:51:50.308609 [Byte1]: 67
1799 10:51:50.312362
1800 10:51:50.312443 Set Vref, RX VrefLevel [Byte0]: 68
1801 10:51:50.319321 [Byte1]: 68
1802 10:51:50.319442
1803 10:51:50.322330 Set Vref, RX VrefLevel [Byte0]: 69
1804 10:51:50.325535 [Byte1]: 69
1805 10:51:50.325618
1806 10:51:50.329081 Set Vref, RX VrefLevel [Byte0]: 70
1807 10:51:50.332154 [Byte1]: 70
1808 10:51:50.335733
1809 10:51:50.335813 Set Vref, RX VrefLevel [Byte0]: 71
1810 10:51:50.339123 [Byte1]: 71
1811 10:51:50.343373
1812 10:51:50.343468 Set Vref, RX VrefLevel [Byte0]: 72
1813 10:51:50.346880 [Byte1]: 72
1814 10:51:50.350729
1815 10:51:50.350810 Set Vref, RX VrefLevel [Byte0]: 73
1816 10:51:50.354052 [Byte1]: 73
1817 10:51:50.358321
1818 10:51:50.358402 Set Vref, RX VrefLevel [Byte0]: 74
1819 10:51:50.362082 [Byte1]: 74
1820 10:51:50.366323
1821 10:51:50.366419 Set Vref, RX VrefLevel [Byte0]: 75
1822 10:51:50.369633 [Byte1]: 75
1823 10:51:50.373948
1824 10:51:50.374050 Set Vref, RX VrefLevel [Byte0]: 76
1825 10:51:50.376784 [Byte1]: 76
1826 10:51:50.381381
1827 10:51:50.381484 Set Vref, RX VrefLevel [Byte0]: 77
1828 10:51:50.384677 [Byte1]: 77
1829 10:51:50.389033
1830 10:51:50.389105 Set Vref, RX VrefLevel [Byte0]: 78
1831 10:51:50.391969 [Byte1]: 78
1832 10:51:50.396608
1833 10:51:50.396685 Final RX Vref Byte 0 = 62 to rank0
1834 10:51:50.399960 Final RX Vref Byte 1 = 57 to rank0
1835 10:51:50.403543 Final RX Vref Byte 0 = 62 to rank1
1836 10:51:50.406902 Final RX Vref Byte 1 = 57 to rank1==
1837 10:51:50.409695 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 10:51:50.416685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 10:51:50.416767 ==
1840 10:51:50.416832 DQS Delay:
1841 10:51:50.416892 DQS0 = 0, DQS1 = 0
1842 10:51:50.419881 DQM Delay:
1843 10:51:50.419961 DQM0 = 83, DQM1 = 74
1844 10:51:50.423511 DQ Delay:
1845 10:51:50.427026 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1846 10:51:50.427108 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1847 10:51:50.429843 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1848 10:51:50.433297 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1849 10:51:50.436823
1850 10:51:50.436903
1851 10:51:50.443340 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fa, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1852 10:51:50.446597 CH1 RK0: MR19=605, MR18=26FA
1853 10:51:50.453401 CH1_RK0: MR19=0x605, MR18=0x26FA, DQSOSC=400, MR23=63, INC=92, DEC=61
1854 10:51:50.453496
1855 10:51:50.456760 ----->DramcWriteLeveling(PI) begin...
1856 10:51:50.456844 ==
1857 10:51:50.460229 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 10:51:50.463525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 10:51:50.463617 ==
1860 10:51:50.466682 Write leveling (Byte 0): 31 => 31
1861 10:51:50.470047 Write leveling (Byte 1): 30 => 30
1862 10:51:50.473658 DramcWriteLeveling(PI) end<-----
1863 10:51:50.473739
1864 10:51:50.473803 ==
1865 10:51:50.476640 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 10:51:50.480101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 10:51:50.480183 ==
1868 10:51:50.483521 [Gating] SW mode calibration
1869 10:51:50.489882 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 10:51:50.496519 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 10:51:50.500093 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 10:51:50.503499 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1873 10:51:50.509683 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1874 10:51:50.513068 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:51:50.516465 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:51:50.523281 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:51:50.526535 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:51:50.530058 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:51:50.536881 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:51:50.539898 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:51:50.543362 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:51:50.546951 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:51:50.553780 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:51:50.556737 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:51:50.560035 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:51:50.566835 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:51:50.570253 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1888 10:51:50.573739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1889 10:51:50.580368 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:51:50.583827 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:51:50.586787 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:51:50.593688 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 10:51:50.597165 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 10:51:50.600429 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 10:51:50.606721 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 10:51:50.610195 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1897 10:51:50.613634 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1898 10:51:50.620419 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 10:51:50.623300 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 10:51:50.627103 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 10:51:50.633419 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 10:51:50.637006 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 10:51:50.640395 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1904 10:51:50.643722 0 10 4 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (0 0)
1905 10:51:50.649815 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1906 10:51:50.653296 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:51:50.656821 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:51:50.663495 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 10:51:50.666817 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:51:50.669993 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 10:51:50.676710 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1912 10:51:50.680295 0 11 4 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
1913 10:51:50.683932 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1914 10:51:50.690218 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 10:51:50.693558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 10:51:50.696785 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 10:51:50.703461 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 10:51:50.706978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 10:51:50.709969 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1920 10:51:50.716628 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1921 10:51:50.719991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:51:50.723274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:51:50.730233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:51:50.733278 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:51:50.736625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:51:50.740149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:51:50.746709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:51:50.750073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:51:50.753636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:51:50.759953 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:51:50.763411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 10:51:50.767082 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 10:51:50.773080 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 10:51:50.776438 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 10:51:50.779874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 10:51:50.787252 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1937 10:51:50.789887 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1938 10:51:50.793431 Total UI for P1: 0, mck2ui 16
1939 10:51:50.796811 best dqsien dly found for B0: ( 0, 14, 4)
1940 10:51:50.800154 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 10:51:50.803545 Total UI for P1: 0, mck2ui 16
1942 10:51:50.806914 best dqsien dly found for B1: ( 0, 14, 6)
1943 10:51:50.810066 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1944 10:51:50.813449 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1945 10:51:50.813522
1946 10:51:50.817146 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 10:51:50.823387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1948 10:51:50.823478 [Gating] SW calibration Done
1949 10:51:50.823543 ==
1950 10:51:50.826885 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 10:51:50.833367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 10:51:50.833445 ==
1953 10:51:50.833509 RX Vref Scan: 0
1954 10:51:50.833567
1955 10:51:50.836909 RX Vref 0 -> 0, step: 1
1956 10:51:50.836979
1957 10:51:50.839887 RX Delay -130 -> 252, step: 16
1958 10:51:50.843324 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1959 10:51:50.846871 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1960 10:51:50.850389 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1961 10:51:50.856696 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1962 10:51:50.860296 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1963 10:51:50.863651 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1964 10:51:50.866569 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1965 10:51:50.870196 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1966 10:51:50.873290 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1967 10:51:50.879862 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1968 10:51:50.883356 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1969 10:51:50.886946 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1970 10:51:50.889854 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1971 10:51:50.897049 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1972 10:51:50.900001 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1973 10:51:50.903230 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1974 10:51:50.903334 ==
1975 10:51:50.906667 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 10:51:50.910033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 10:51:50.910108 ==
1978 10:51:50.913478 DQS Delay:
1979 10:51:50.913550 DQS0 = 0, DQS1 = 0
1980 10:51:50.916366 DQM Delay:
1981 10:51:50.916439 DQM0 = 81, DQM1 = 76
1982 10:51:50.916499 DQ Delay:
1983 10:51:50.920156 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1984 10:51:50.923235 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1985 10:51:50.927158 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1986 10:51:50.930155 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1987 10:51:50.930227
1988 10:51:50.930288
1989 10:51:50.932975 ==
1990 10:51:50.933044 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 10:51:50.940112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 10:51:50.940190 ==
1993 10:51:50.940252
1994 10:51:50.940309
1995 10:51:50.940368 TX Vref Scan disable
1996 10:51:50.943530 == TX Byte 0 ==
1997 10:51:50.946967 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1998 10:51:50.953910 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1999 10:51:50.953985 == TX Byte 1 ==
2000 10:51:50.956868 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 10:51:50.963445 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 10:51:50.963522 ==
2003 10:51:50.967091 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 10:51:50.970144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 10:51:50.970220 ==
2006 10:51:50.982475 TX Vref=22, minBit 9, minWin=27, winSum=444
2007 10:51:50.985840 TX Vref=24, minBit 10, minWin=27, winSum=449
2008 10:51:50.989425 TX Vref=26, minBit 13, minWin=27, winSum=449
2009 10:51:50.992577 TX Vref=28, minBit 15, minWin=27, winSum=454
2010 10:51:50.995976 TX Vref=30, minBit 3, minWin=28, winSum=456
2011 10:51:51.002949 TX Vref=32, minBit 3, minWin=28, winSum=455
2012 10:51:51.005828 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 30
2013 10:51:51.005902
2014 10:51:51.009205 Final TX Range 1 Vref 30
2015 10:51:51.009286
2016 10:51:51.009350 ==
2017 10:51:51.012602 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 10:51:51.015981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 10:51:51.019588 ==
2020 10:51:51.019668
2021 10:51:51.019730
2022 10:51:51.019789 TX Vref Scan disable
2023 10:51:51.022983 == TX Byte 0 ==
2024 10:51:51.026098 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2025 10:51:51.032898 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2026 10:51:51.032978 == TX Byte 1 ==
2027 10:51:51.036211 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 10:51:51.042936 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 10:51:51.043041
2030 10:51:51.043135 [DATLAT]
2031 10:51:51.043229 Freq=800, CH1 RK1
2032 10:51:51.043315
2033 10:51:51.046609 DATLAT Default: 0xa
2034 10:51:51.046689 0, 0xFFFF, sum = 0
2035 10:51:51.049427 1, 0xFFFF, sum = 0
2036 10:51:51.049509 2, 0xFFFF, sum = 0
2037 10:51:51.052831 3, 0xFFFF, sum = 0
2038 10:51:51.056296 4, 0xFFFF, sum = 0
2039 10:51:51.056377 5, 0xFFFF, sum = 0
2040 10:51:51.059267 6, 0xFFFF, sum = 0
2041 10:51:51.059378 7, 0xFFFF, sum = 0
2042 10:51:51.062861 8, 0xFFFF, sum = 0
2043 10:51:51.062943 9, 0x0, sum = 1
2044 10:51:51.063007 10, 0x0, sum = 2
2045 10:51:51.066405 11, 0x0, sum = 3
2046 10:51:51.066486 12, 0x0, sum = 4
2047 10:51:51.069465 best_step = 10
2048 10:51:51.069544
2049 10:51:51.069607 ==
2050 10:51:51.072824 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 10:51:51.076209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 10:51:51.076289 ==
2053 10:51:51.079554 RX Vref Scan: 0
2054 10:51:51.079636
2055 10:51:51.079699 RX Vref 0 -> 0, step: 1
2056 10:51:51.079757
2057 10:51:51.083030 RX Delay -111 -> 252, step: 8
2058 10:51:51.089896 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2059 10:51:51.093302 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2060 10:51:51.096354 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2061 10:51:51.099990 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2062 10:51:51.103027 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2063 10:51:51.109943 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2064 10:51:51.113277 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2065 10:51:51.116666 iDelay=209, Bit 7, Center 80 (-31 ~ 192) 224
2066 10:51:51.120094 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2067 10:51:51.123768 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2068 10:51:51.129900 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2069 10:51:51.133238 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2070 10:51:51.136580 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2071 10:51:51.139974 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2072 10:51:51.143384 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2073 10:51:51.149856 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2074 10:51:51.149938 ==
2075 10:51:51.152826 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 10:51:51.156157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 10:51:51.156239 ==
2078 10:51:51.156303 DQS Delay:
2079 10:51:51.159520 DQS0 = 0, DQS1 = 0
2080 10:51:51.159601 DQM Delay:
2081 10:51:51.163078 DQM0 = 81, DQM1 = 75
2082 10:51:51.163159 DQ Delay:
2083 10:51:51.166682 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2084 10:51:51.169676 DQ4 =84, DQ5 =88, DQ6 =92, DQ7 =80
2085 10:51:51.173322 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2086 10:51:51.176642 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2087 10:51:51.176724
2088 10:51:51.176787
2089 10:51:51.186487 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2090 10:51:51.186574 CH1 RK1: MR19=606, MR18=1C27
2091 10:51:51.192622 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2092 10:51:51.196054 [RxdqsGatingPostProcess] freq 800
2093 10:51:51.202917 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 10:51:51.205932 Pre-setting of DQS Precalculation
2095 10:51:51.209756 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 10:51:51.216104 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 10:51:51.225683 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 10:51:51.225794
2099 10:51:51.225887
2100 10:51:51.225976 [Calibration Summary] 1600 Mbps
2101 10:51:51.229268 CH 0, Rank 0
2102 10:51:51.232734 SW Impedance : PASS
2103 10:51:51.232834 DUTY Scan : NO K
2104 10:51:51.235627 ZQ Calibration : PASS
2105 10:51:51.235713 Jitter Meter : NO K
2106 10:51:51.238986 CBT Training : PASS
2107 10:51:51.242425 Write leveling : PASS
2108 10:51:51.242517 RX DQS gating : PASS
2109 10:51:51.245750 RX DQ/DQS(RDDQC) : PASS
2110 10:51:51.249150 TX DQ/DQS : PASS
2111 10:51:51.249245 RX DATLAT : PASS
2112 10:51:51.252211 RX DQ/DQS(Engine): PASS
2113 10:51:51.255602 TX OE : NO K
2114 10:51:51.255702 All Pass.
2115 10:51:51.255812
2116 10:51:51.255944 CH 0, Rank 1
2117 10:51:51.259199 SW Impedance : PASS
2118 10:51:51.262322 DUTY Scan : NO K
2119 10:51:51.262437 ZQ Calibration : PASS
2120 10:51:51.265651 Jitter Meter : NO K
2121 10:51:51.269357 CBT Training : PASS
2122 10:51:51.269457 Write leveling : PASS
2123 10:51:51.272266 RX DQS gating : PASS
2124 10:51:51.275816 RX DQ/DQS(RDDQC) : PASS
2125 10:51:51.275893 TX DQ/DQS : PASS
2126 10:51:51.278847 RX DATLAT : PASS
2127 10:51:51.278939 RX DQ/DQS(Engine): PASS
2128 10:51:51.282274 TX OE : NO K
2129 10:51:51.282392 All Pass.
2130 10:51:51.282482
2131 10:51:51.285436 CH 1, Rank 0
2132 10:51:51.285543 SW Impedance : PASS
2133 10:51:51.288715 DUTY Scan : NO K
2134 10:51:51.292292 ZQ Calibration : PASS
2135 10:51:51.292389 Jitter Meter : NO K
2136 10:51:51.295201 CBT Training : PASS
2137 10:51:51.298996 Write leveling : PASS
2138 10:51:51.299110 RX DQS gating : PASS
2139 10:51:51.302081 RX DQ/DQS(RDDQC) : PASS
2140 10:51:51.305455 TX DQ/DQS : PASS
2141 10:51:51.305560 RX DATLAT : PASS
2142 10:51:51.308848 RX DQ/DQS(Engine): PASS
2143 10:51:51.311967 TX OE : NO K
2144 10:51:51.312048 All Pass.
2145 10:51:51.312113
2146 10:51:51.312172 CH 1, Rank 1
2147 10:51:51.315487 SW Impedance : PASS
2148 10:51:51.318771 DUTY Scan : NO K
2149 10:51:51.318870 ZQ Calibration : PASS
2150 10:51:51.322348 Jitter Meter : NO K
2151 10:51:51.325901 CBT Training : PASS
2152 10:51:51.326002 Write leveling : PASS
2153 10:51:51.329042 RX DQS gating : PASS
2154 10:51:51.329138 RX DQ/DQS(RDDQC) : PASS
2155 10:51:51.332043 TX DQ/DQS : PASS
2156 10:51:51.335286 RX DATLAT : PASS
2157 10:51:51.335422 RX DQ/DQS(Engine): PASS
2158 10:51:51.338860 TX OE : NO K
2159 10:51:51.338964 All Pass.
2160 10:51:51.339056
2161 10:51:51.342341 DramC Write-DBI off
2162 10:51:51.345301 PER_BANK_REFRESH: Hybrid Mode
2163 10:51:51.345449 TX_TRACKING: ON
2164 10:51:51.349126 [GetDramInforAfterCalByMRR] Vendor 6.
2165 10:51:51.352012 [GetDramInforAfterCalByMRR] Revision 606.
2166 10:51:51.355683 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 10:51:51.358322 MR0 0x3b3b
2168 10:51:51.358414 MR8 0x5151
2169 10:51:51.361911 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 10:51:51.361984
2171 10:51:51.365380 MR0 0x3b3b
2172 10:51:51.365478 MR8 0x5151
2173 10:51:51.368546 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 10:51:51.368617
2175 10:51:51.378459 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 10:51:51.381888 [FAST_K] Save calibration result to emmc
2177 10:51:51.385301 [FAST_K] Save calibration result to emmc
2178 10:51:51.388863 dram_init: config_dvfs: 1
2179 10:51:51.391468 dramc_set_vcore_voltage set vcore to 662500
2180 10:51:51.391543 Read voltage for 1200, 2
2181 10:51:51.395208 Vio18 = 0
2182 10:51:51.395290 Vcore = 662500
2183 10:51:51.395378 Vdram = 0
2184 10:51:51.399036 Vddq = 0
2185 10:51:51.399116 Vmddr = 0
2186 10:51:51.401876 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 10:51:51.408499 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 10:51:51.411821 MEM_TYPE=3, freq_sel=15
2189 10:51:51.414893 sv_algorithm_assistance_LP4_1600
2190 10:51:51.418458 ============ PULL DRAM RESETB DOWN ============
2191 10:51:51.421501 ========== PULL DRAM RESETB DOWN end =========
2192 10:51:51.428227 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 10:51:51.431566 ===================================
2194 10:51:51.431647 LPDDR4 DRAM CONFIGURATION
2195 10:51:51.435004 ===================================
2196 10:51:51.438433 EX_ROW_EN[0] = 0x0
2197 10:51:51.438540 EX_ROW_EN[1] = 0x0
2198 10:51:51.441738 LP4Y_EN = 0x0
2199 10:51:51.441816 WORK_FSP = 0x0
2200 10:51:51.444699 WL = 0x4
2201 10:51:51.448161 RL = 0x4
2202 10:51:51.448265 BL = 0x2
2203 10:51:51.451580 RPST = 0x0
2204 10:51:51.451660 RD_PRE = 0x0
2205 10:51:51.454804 WR_PRE = 0x1
2206 10:51:51.454884 WR_PST = 0x0
2207 10:51:51.458292 DBI_WR = 0x0
2208 10:51:51.458372 DBI_RD = 0x0
2209 10:51:51.461763 OTF = 0x1
2210 10:51:51.465351 ===================================
2211 10:51:51.468342 ===================================
2212 10:51:51.468424 ANA top config
2213 10:51:51.472070 ===================================
2214 10:51:51.475550 DLL_ASYNC_EN = 0
2215 10:51:51.478101 ALL_SLAVE_EN = 0
2216 10:51:51.478182 NEW_RANK_MODE = 1
2217 10:51:51.481738 DLL_IDLE_MODE = 1
2218 10:51:51.484737 LP45_APHY_COMB_EN = 1
2219 10:51:51.488217 TX_ODT_DIS = 1
2220 10:51:51.491738 NEW_8X_MODE = 1
2221 10:51:51.494454 ===================================
2222 10:51:51.494536 ===================================
2223 10:51:51.498197 data_rate = 2400
2224 10:51:51.501220 CKR = 1
2225 10:51:51.505011 DQ_P2S_RATIO = 8
2226 10:51:51.507863 ===================================
2227 10:51:51.511226 CA_P2S_RATIO = 8
2228 10:51:51.514701 DQ_CA_OPEN = 0
2229 10:51:51.518032 DQ_SEMI_OPEN = 0
2230 10:51:51.518107 CA_SEMI_OPEN = 0
2231 10:51:51.521030 CA_FULL_RATE = 0
2232 10:51:51.524484 DQ_CKDIV4_EN = 0
2233 10:51:51.528006 CA_CKDIV4_EN = 0
2234 10:51:51.531237 CA_PREDIV_EN = 0
2235 10:51:51.534424 PH8_DLY = 17
2236 10:51:51.534499 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 10:51:51.537846 DQ_AAMCK_DIV = 4
2238 10:51:51.541297 CA_AAMCK_DIV = 4
2239 10:51:51.544289 CA_ADMCK_DIV = 4
2240 10:51:51.547670 DQ_TRACK_CA_EN = 0
2241 10:51:51.551181 CA_PICK = 1200
2242 10:51:51.554696 CA_MCKIO = 1200
2243 10:51:51.554768 MCKIO_SEMI = 0
2244 10:51:51.557909 PLL_FREQ = 2366
2245 10:51:51.560897 DQ_UI_PI_RATIO = 32
2246 10:51:51.564374 CA_UI_PI_RATIO = 0
2247 10:51:51.567842 ===================================
2248 10:51:51.571424 ===================================
2249 10:51:51.574277 memory_type:LPDDR4
2250 10:51:51.574352 GP_NUM : 10
2251 10:51:51.578036 SRAM_EN : 1
2252 10:51:51.578108 MD32_EN : 0
2253 10:51:51.581170 ===================================
2254 10:51:51.584278 [ANA_INIT] >>>>>>>>>>>>>>
2255 10:51:51.587796 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 10:51:51.591291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 10:51:51.594224 ===================================
2258 10:51:51.597572 data_rate = 2400,PCW = 0X5b00
2259 10:51:51.600841 ===================================
2260 10:51:51.604191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 10:51:51.611016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 10:51:51.614078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 10:51:51.620854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 10:51:51.624503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 10:51:51.627312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 10:51:51.627433 [ANA_INIT] flow start
2267 10:51:51.630977 [ANA_INIT] PLL >>>>>>>>
2268 10:51:51.633899 [ANA_INIT] PLL <<<<<<<<
2269 10:51:51.633980 [ANA_INIT] MIDPI >>>>>>>>
2270 10:51:51.637713 [ANA_INIT] MIDPI <<<<<<<<
2271 10:51:51.640690 [ANA_INIT] DLL >>>>>>>>
2272 10:51:51.640771 [ANA_INIT] DLL <<<<<<<<
2273 10:51:51.643879 [ANA_INIT] flow end
2274 10:51:51.647311 ============ LP4 DIFF to SE enter ============
2275 10:51:51.654618 ============ LP4 DIFF to SE exit ============
2276 10:51:51.654706 [ANA_INIT] <<<<<<<<<<<<<
2277 10:51:51.657331 [Flow] Enable top DCM control >>>>>
2278 10:51:51.661027 [Flow] Enable top DCM control <<<<<
2279 10:51:51.664048 Enable DLL master slave shuffle
2280 10:51:51.671083 ==============================================================
2281 10:51:51.671165 Gating Mode config
2282 10:51:51.677799 ==============================================================
2283 10:51:51.680590 Config description:
2284 10:51:51.687038 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 10:51:51.693949 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 10:51:51.700483 SELPH_MODE 0: By rank 1: By Phase
2287 10:51:51.707152 ==============================================================
2288 10:51:51.707270 GAT_TRACK_EN = 1
2289 10:51:51.710858 RX_GATING_MODE = 2
2290 10:51:51.714125 RX_GATING_TRACK_MODE = 2
2291 10:51:51.716868 SELPH_MODE = 1
2292 10:51:51.720860 PICG_EARLY_EN = 1
2293 10:51:51.723786 VALID_LAT_VALUE = 1
2294 10:51:51.730437 ==============================================================
2295 10:51:51.733840 Enter into Gating configuration >>>>
2296 10:51:51.737198 Exit from Gating configuration <<<<
2297 10:51:51.740544 Enter into DVFS_PRE_config >>>>>
2298 10:51:51.750116 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 10:51:51.754207 Exit from DVFS_PRE_config <<<<<
2300 10:51:51.756810 Enter into PICG configuration >>>>
2301 10:51:51.760344 Exit from PICG configuration <<<<
2302 10:51:51.763786 [RX_INPUT] configuration >>>>>
2303 10:51:51.763868 [RX_INPUT] configuration <<<<<
2304 10:51:51.770608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 10:51:51.776949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 10:51:51.780402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 10:51:51.787293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 10:51:51.793514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 10:51:51.800148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 10:51:51.803234 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 10:51:51.807019 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 10:51:51.813711 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 10:51:51.816545 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 10:51:51.819904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 10:51:51.826662 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 10:51:51.829702 ===================================
2317 10:51:51.829785 LPDDR4 DRAM CONFIGURATION
2318 10:51:51.833153 ===================================
2319 10:51:51.836954 EX_ROW_EN[0] = 0x0
2320 10:51:51.837036 EX_ROW_EN[1] = 0x0
2321 10:51:51.839829 LP4Y_EN = 0x0
2322 10:51:51.843024 WORK_FSP = 0x0
2323 10:51:51.843106 WL = 0x4
2324 10:51:51.846331 RL = 0x4
2325 10:51:51.846413 BL = 0x2
2326 10:51:51.849650 RPST = 0x0
2327 10:51:51.849733 RD_PRE = 0x0
2328 10:51:51.853042 WR_PRE = 0x1
2329 10:51:51.853124 WR_PST = 0x0
2330 10:51:51.856336 DBI_WR = 0x0
2331 10:51:51.856417 DBI_RD = 0x0
2332 10:51:51.859739 OTF = 0x1
2333 10:51:51.863057 ===================================
2334 10:51:51.866267 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 10:51:51.869704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 10:51:51.876782 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 10:51:51.879977 ===================================
2338 10:51:51.880059 LPDDR4 DRAM CONFIGURATION
2339 10:51:51.883289 ===================================
2340 10:51:51.886289 EX_ROW_EN[0] = 0x10
2341 10:51:51.886372 EX_ROW_EN[1] = 0x0
2342 10:51:51.889763 LP4Y_EN = 0x0
2343 10:51:51.889845 WORK_FSP = 0x0
2344 10:51:51.892859 WL = 0x4
2345 10:51:51.892941 RL = 0x4
2346 10:51:51.896113 BL = 0x2
2347 10:51:51.899919 RPST = 0x0
2348 10:51:51.899999 RD_PRE = 0x0
2349 10:51:51.903212 WR_PRE = 0x1
2350 10:51:51.903292 WR_PST = 0x0
2351 10:51:51.906316 DBI_WR = 0x0
2352 10:51:51.906395 DBI_RD = 0x0
2353 10:51:51.909388 OTF = 0x1
2354 10:51:51.913402 ===================================
2355 10:51:51.916222 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 10:51:51.919377 ==
2357 10:51:51.923043 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 10:51:51.926050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 10:51:51.926149 ==
2360 10:51:51.929661 [Duty_Offset_Calibration]
2361 10:51:51.929740 B0:2 B1:-1 CA:1
2362 10:51:51.929819
2363 10:51:51.932853 [DutyScan_Calibration_Flow] k_type=0
2364 10:51:51.942011
2365 10:51:51.942090 ==CLK 0==
2366 10:51:51.944763 Final CLK duty delay cell = -4
2367 10:51:51.948087 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2368 10:51:51.952236 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2369 10:51:51.954745 [-4] AVG Duty = 4953%(X100)
2370 10:51:51.954824
2371 10:51:51.958318 CH0 CLK Duty spec in!! Max-Min= 156%
2372 10:51:51.961712 [DutyScan_Calibration_Flow] ====Done====
2373 10:51:51.961790
2374 10:51:51.964671 [DutyScan_Calibration_Flow] k_type=1
2375 10:51:51.979696
2376 10:51:51.979776 ==DQS 0 ==
2377 10:51:51.983114 Final DQS duty delay cell = -4
2378 10:51:51.986710 [-4] MAX Duty = 5000%(X100), DQS PI = 42
2379 10:51:51.990116 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2380 10:51:51.993234 [-4] AVG Duty = 4938%(X100)
2381 10:51:51.993313
2382 10:51:51.993374 ==DQS 1 ==
2383 10:51:51.996564 Final DQS duty delay cell = -4
2384 10:51:51.999907 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2385 10:51:52.003265 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2386 10:51:52.006841 [-4] AVG Duty = 5062%(X100)
2387 10:51:52.006920
2388 10:51:52.009768 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2389 10:51:52.009849
2390 10:51:52.013092 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2391 10:51:52.016793 [DutyScan_Calibration_Flow] ====Done====
2392 10:51:52.016872
2393 10:51:52.019771 [DutyScan_Calibration_Flow] k_type=3
2394 10:51:52.037231
2395 10:51:52.037310 ==DQM 0 ==
2396 10:51:52.040185 Final DQM duty delay cell = 0
2397 10:51:52.043769 [0] MAX Duty = 5031%(X100), DQS PI = 54
2398 10:51:52.047221 [0] MIN Duty = 4907%(X100), DQS PI = 2
2399 10:51:52.047327 [0] AVG Duty = 4969%(X100)
2400 10:51:52.049991
2401 10:51:52.050070 ==DQM 1 ==
2402 10:51:52.054026 Final DQM duty delay cell = 0
2403 10:51:52.057325 [0] MAX Duty = 5156%(X100), DQS PI = 62
2404 10:51:52.060477 [0] MIN Duty = 4969%(X100), DQS PI = 10
2405 10:51:52.060556 [0] AVG Duty = 5062%(X100)
2406 10:51:52.063485
2407 10:51:52.067435 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2408 10:51:52.067517
2409 10:51:52.070410 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2410 10:51:52.073694 [DutyScan_Calibration_Flow] ====Done====
2411 10:51:52.073775
2412 10:51:52.077276 [DutyScan_Calibration_Flow] k_type=2
2413 10:51:52.092449
2414 10:51:52.092529 ==DQ 0 ==
2415 10:51:52.095855 Final DQ duty delay cell = -4
2416 10:51:52.099559 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2417 10:51:52.102400 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2418 10:51:52.105847 [-4] AVG Duty = 4984%(X100)
2419 10:51:52.105930
2420 10:51:52.105994 ==DQ 1 ==
2421 10:51:52.108955 Final DQ duty delay cell = 0
2422 10:51:52.112469 [0] MAX Duty = 5031%(X100), DQS PI = 18
2423 10:51:52.115886 [0] MIN Duty = 4907%(X100), DQS PI = 46
2424 10:51:52.119405 [0] AVG Duty = 4969%(X100)
2425 10:51:52.119485
2426 10:51:52.122817 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2427 10:51:52.122899
2428 10:51:52.126156 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2429 10:51:52.129569 [DutyScan_Calibration_Flow] ====Done====
2430 10:51:52.129671 ==
2431 10:51:52.132930 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 10:51:52.136137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 10:51:52.136218 ==
2434 10:51:52.139698 [Duty_Offset_Calibration]
2435 10:51:52.139778 B0:1 B1:1 CA:2
2436 10:51:52.139842
2437 10:51:52.142684 [DutyScan_Calibration_Flow] k_type=0
2438 10:51:52.153266
2439 10:51:52.153350 ==CLK 0==
2440 10:51:52.155975 Final CLK duty delay cell = 0
2441 10:51:52.159719 [0] MAX Duty = 5156%(X100), DQS PI = 24
2442 10:51:52.163200 [0] MIN Duty = 4938%(X100), DQS PI = 46
2443 10:51:52.163282 [0] AVG Duty = 5047%(X100)
2444 10:51:52.165972
2445 10:51:52.169534 CH1 CLK Duty spec in!! Max-Min= 218%
2446 10:51:52.172960 [DutyScan_Calibration_Flow] ====Done====
2447 10:51:52.173041
2448 10:51:52.175881 [DutyScan_Calibration_Flow] k_type=1
2449 10:51:52.192168
2450 10:51:52.192249 ==DQS 0 ==
2451 10:51:52.195727 Final DQS duty delay cell = 0
2452 10:51:52.198729 [0] MAX Duty = 5031%(X100), DQS PI = 18
2453 10:51:52.202263 [0] MIN Duty = 4844%(X100), DQS PI = 48
2454 10:51:52.205524 [0] AVG Duty = 4937%(X100)
2455 10:51:52.205605
2456 10:51:52.205669 ==DQS 1 ==
2457 10:51:52.208694 Final DQS duty delay cell = 0
2458 10:51:52.212118 [0] MAX Duty = 5031%(X100), DQS PI = 20
2459 10:51:52.215255 [0] MIN Duty = 4907%(X100), DQS PI = 0
2460 10:51:52.219007 [0] AVG Duty = 4969%(X100)
2461 10:51:52.219088
2462 10:51:52.222330 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2463 10:51:52.222412
2464 10:51:52.225483 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2465 10:51:52.229137 [DutyScan_Calibration_Flow] ====Done====
2466 10:51:52.229220
2467 10:51:52.232538 [DutyScan_Calibration_Flow] k_type=3
2468 10:51:52.249081
2469 10:51:52.249190 ==DQM 0 ==
2470 10:51:52.252038 Final DQM duty delay cell = 0
2471 10:51:52.255496 [0] MAX Duty = 5093%(X100), DQS PI = 16
2472 10:51:52.258916 [0] MIN Duty = 4907%(X100), DQS PI = 48
2473 10:51:52.261823 [0] AVG Duty = 5000%(X100)
2474 10:51:52.261934
2475 10:51:52.262027 ==DQM 1 ==
2476 10:51:52.265201 Final DQM duty delay cell = 0
2477 10:51:52.268993 [0] MAX Duty = 5156%(X100), DQS PI = 62
2478 10:51:52.272322 [0] MIN Duty = 4938%(X100), DQS PI = 24
2479 10:51:52.275785 [0] AVG Duty = 5047%(X100)
2480 10:51:52.275900
2481 10:51:52.279278 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2482 10:51:52.279403
2483 10:51:52.282302 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2484 10:51:52.285543 [DutyScan_Calibration_Flow] ====Done====
2485 10:51:52.285625
2486 10:51:52.288876 [DutyScan_Calibration_Flow] k_type=2
2487 10:51:52.305784
2488 10:51:52.305873 ==DQ 0 ==
2489 10:51:52.308743 Final DQ duty delay cell = 0
2490 10:51:52.312190 [0] MAX Duty = 5124%(X100), DQS PI = 18
2491 10:51:52.315476 [0] MIN Duty = 4907%(X100), DQS PI = 50
2492 10:51:52.315558 [0] AVG Duty = 5015%(X100)
2493 10:51:52.315622
2494 10:51:52.318922 ==DQ 1 ==
2495 10:51:52.322506 Final DQ duty delay cell = 0
2496 10:51:52.325135 [0] MAX Duty = 5124%(X100), DQS PI = 58
2497 10:51:52.328979 [0] MIN Duty = 5031%(X100), DQS PI = 2
2498 10:51:52.329084 [0] AVG Duty = 5077%(X100)
2499 10:51:52.329176
2500 10:51:52.332174 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2501 10:51:52.332247
2502 10:51:52.335402 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2503 10:51:52.342154 [DutyScan_Calibration_Flow] ====Done====
2504 10:51:52.345008 nWR fixed to 30
2505 10:51:52.345106 [ModeRegInit_LP4] CH0 RK0
2506 10:51:52.348421 [ModeRegInit_LP4] CH0 RK1
2507 10:51:52.351952 [ModeRegInit_LP4] CH1 RK0
2508 10:51:52.352046 [ModeRegInit_LP4] CH1 RK1
2509 10:51:52.355461 match AC timing 7
2510 10:51:52.358857 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 10:51:52.361753 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 10:51:52.368818 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 10:51:52.372198 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 10:51:52.379150 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 10:51:52.379255 ==
2516 10:51:52.382457 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 10:51:52.385441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 10:51:52.385545 ==
2519 10:51:52.392305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 10:51:52.395575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 10:51:52.405048 [CA 0] Center 40 (10~71) winsize 62
2522 10:51:52.408585 [CA 1] Center 39 (9~70) winsize 62
2523 10:51:52.412193 [CA 2] Center 36 (6~67) winsize 62
2524 10:51:52.415283 [CA 3] Center 36 (5~67) winsize 63
2525 10:51:52.418720 [CA 4] Center 35 (5~65) winsize 61
2526 10:51:52.421933 [CA 5] Center 34 (4~65) winsize 62
2527 10:51:52.422035
2528 10:51:52.425306 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2529 10:51:52.425401
2530 10:51:52.428621 [CATrainingPosCal] consider 1 rank data
2531 10:51:52.431984 u2DelayCellTimex100 = 270/100 ps
2532 10:51:52.435225 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2533 10:51:52.439005 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2534 10:51:52.445269 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2535 10:51:52.449019 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2536 10:51:52.452218 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2537 10:51:52.455127 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2538 10:51:52.455222
2539 10:51:52.458852 CA PerBit enable=1, Macro0, CA PI delay=34
2540 10:51:52.458947
2541 10:51:52.461843 [CBTSetCACLKResult] CA Dly = 34
2542 10:51:52.461913 CS Dly: 7 (0~38)
2543 10:51:52.461973 ==
2544 10:51:52.465536 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 10:51:52.472166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 10:51:52.472240 ==
2547 10:51:52.475434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 10:51:52.482232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 10:51:52.491529 [CA 0] Center 39 (9~70) winsize 62
2550 10:51:52.494459 [CA 1] Center 39 (9~70) winsize 62
2551 10:51:52.497781 [CA 2] Center 36 (6~67) winsize 62
2552 10:51:52.501216 [CA 3] Center 35 (5~66) winsize 62
2553 10:51:52.504759 [CA 4] Center 34 (4~65) winsize 62
2554 10:51:52.507630 [CA 5] Center 34 (4~64) winsize 61
2555 10:51:52.507707
2556 10:51:52.511354 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2557 10:51:52.511446
2558 10:51:52.514250 [CATrainingPosCal] consider 2 rank data
2559 10:51:52.517728 u2DelayCellTimex100 = 270/100 ps
2560 10:51:52.521329 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2561 10:51:52.524652 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2562 10:51:52.531420 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2563 10:51:52.534211 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2564 10:51:52.537691 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2565 10:51:52.540989 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2566 10:51:52.541084
2567 10:51:52.544303 CA PerBit enable=1, Macro0, CA PI delay=34
2568 10:51:52.544375
2569 10:51:52.547698 [CBTSetCACLKResult] CA Dly = 34
2570 10:51:52.547768 CS Dly: 8 (0~41)
2571 10:51:52.547829
2572 10:51:52.551205 ----->DramcWriteLeveling(PI) begin...
2573 10:51:52.554642 ==
2574 10:51:52.557658 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 10:51:52.561320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 10:51:52.561412 ==
2577 10:51:52.564281 Write leveling (Byte 0): 31 => 31
2578 10:51:52.567709 Write leveling (Byte 1): 31 => 31
2579 10:51:52.570802 DramcWriteLeveling(PI) end<-----
2580 10:51:52.570896
2581 10:51:52.570983 ==
2582 10:51:52.574502 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 10:51:52.577786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 10:51:52.577882 ==
2585 10:51:52.581046 [Gating] SW mode calibration
2586 10:51:52.587916 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 10:51:52.591497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 10:51:52.597985 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 10:51:52.601431 0 15 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2590 10:51:52.604858 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2591 10:51:52.611049 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 10:51:52.614411 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 10:51:52.618087 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 10:51:52.624370 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 10:51:52.627831 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 10:51:52.631472 1 0 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
2597 10:51:52.637777 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2598 10:51:52.641297 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 10:51:52.644539 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 10:51:52.651208 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 10:51:52.654682 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 10:51:52.658131 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 10:51:52.664466 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 10:51:52.667820 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2605 10:51:52.671246 1 1 4 | B1->B0 | 3535 4040 | 0 0 | (0 0) (1 1)
2606 10:51:52.677682 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 10:51:52.680977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 10:51:52.684412 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 10:51:52.687731 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 10:51:52.694698 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 10:51:52.697570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 10:51:52.701422 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2613 10:51:52.708530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 10:51:52.711136 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:51:52.714691 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:51:52.721369 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:51:52.724133 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:51:52.727739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:51:52.734575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:51:52.737934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:51:52.740876 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 10:51:52.748204 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 10:51:52.750797 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 10:51:52.754379 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 10:51:52.761398 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 10:51:52.764379 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 10:51:52.768233 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 10:51:52.774457 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2629 10:51:52.778001 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2630 10:51:52.781379 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 10:51:52.784697 Total UI for P1: 0, mck2ui 16
2632 10:51:52.788033 best dqsien dly found for B0: ( 1, 4, 2)
2633 10:51:52.791086 Total UI for P1: 0, mck2ui 16
2634 10:51:52.794343 best dqsien dly found for B1: ( 1, 4, 2)
2635 10:51:52.797753 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2636 10:51:52.800750 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2637 10:51:52.800831
2638 10:51:52.804209 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2639 10:51:52.807688 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2640 10:51:52.810839 [Gating] SW calibration Done
2641 10:51:52.810920 ==
2642 10:51:52.814505 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 10:51:52.820908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 10:51:52.820989 ==
2645 10:51:52.821053 RX Vref Scan: 0
2646 10:51:52.821111
2647 10:51:52.824476 RX Vref 0 -> 0, step: 1
2648 10:51:52.824556
2649 10:51:52.827438 RX Delay -40 -> 252, step: 8
2650 10:51:52.830806 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2651 10:51:52.834360 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2652 10:51:52.837738 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2653 10:51:52.840895 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2654 10:51:52.847989 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2655 10:51:52.850860 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2656 10:51:52.854375 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2657 10:51:52.857706 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2658 10:51:52.861276 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2659 10:51:52.864097 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2660 10:51:52.871183 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2661 10:51:52.874659 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2662 10:51:52.877552 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2663 10:51:52.880972 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2664 10:51:52.887659 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2665 10:51:52.891457 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2666 10:51:52.891541 ==
2667 10:51:52.894644 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 10:51:52.898046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 10:51:52.898127 ==
2670 10:51:52.898191 DQS Delay:
2671 10:51:52.900772 DQS0 = 0, DQS1 = 0
2672 10:51:52.900853 DQM Delay:
2673 10:51:52.904301 DQM0 = 116, DQM1 = 107
2674 10:51:52.904381 DQ Delay:
2675 10:51:52.907800 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2676 10:51:52.911370 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2677 10:51:52.914605 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2678 10:51:52.917920 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2679 10:51:52.918000
2680 10:51:52.918063
2681 10:51:52.920912 ==
2682 10:51:52.924492 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 10:51:52.927545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 10:51:52.927626 ==
2685 10:51:52.927690
2686 10:51:52.927749
2687 10:51:52.931027 TX Vref Scan disable
2688 10:51:52.931107 == TX Byte 0 ==
2689 10:51:52.934482 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2690 10:51:52.941381 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2691 10:51:52.941462 == TX Byte 1 ==
2692 10:51:52.944145 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2693 10:51:52.951195 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2694 10:51:52.951275 ==
2695 10:51:52.954780 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 10:51:52.957647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 10:51:52.957728 ==
2698 10:51:52.969493 TX Vref=22, minBit 1, minWin=24, winSum=411
2699 10:51:52.972931 TX Vref=24, minBit 7, minWin=24, winSum=417
2700 10:51:52.976289 TX Vref=26, minBit 5, minWin=25, winSum=419
2701 10:51:52.979305 TX Vref=28, minBit 0, minWin=26, winSum=424
2702 10:51:52.983065 TX Vref=30, minBit 0, minWin=26, winSum=429
2703 10:51:52.989486 TX Vref=32, minBit 3, minWin=26, winSum=427
2704 10:51:52.992792 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
2705 10:51:52.992873
2706 10:51:52.996486 Final TX Range 1 Vref 30
2707 10:51:52.996568
2708 10:51:52.996631 ==
2709 10:51:52.999975 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 10:51:53.002893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 10:51:53.002974 ==
2712 10:51:53.003038
2713 10:51:53.006252
2714 10:51:53.006332 TX Vref Scan disable
2715 10:51:53.009472 == TX Byte 0 ==
2716 10:51:53.012934 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2717 10:51:53.016094 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2718 10:51:53.019557 == TX Byte 1 ==
2719 10:51:53.022626 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2720 10:51:53.026271 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2721 10:51:53.026355
2722 10:51:53.029609 [DATLAT]
2723 10:51:53.029690 Freq=1200, CH0 RK0
2724 10:51:53.029754
2725 10:51:53.032580 DATLAT Default: 0xd
2726 10:51:53.032661 0, 0xFFFF, sum = 0
2727 10:51:53.036115 1, 0xFFFF, sum = 0
2728 10:51:53.036227 2, 0xFFFF, sum = 0
2729 10:51:53.039130 3, 0xFFFF, sum = 0
2730 10:51:53.039207 4, 0xFFFF, sum = 0
2731 10:51:53.042604 5, 0xFFFF, sum = 0
2732 10:51:53.042697 6, 0xFFFF, sum = 0
2733 10:51:53.046024 7, 0xFFFF, sum = 0
2734 10:51:53.049220 8, 0xFFFF, sum = 0
2735 10:51:53.049310 9, 0xFFFF, sum = 0
2736 10:51:53.052539 10, 0xFFFF, sum = 0
2737 10:51:53.052617 11, 0xFFFF, sum = 0
2738 10:51:53.055853 12, 0x0, sum = 1
2739 10:51:53.055932 13, 0x0, sum = 2
2740 10:51:53.059261 14, 0x0, sum = 3
2741 10:51:53.059404 15, 0x0, sum = 4
2742 10:51:53.059469 best_step = 13
2743 10:51:53.059528
2744 10:51:53.062756 ==
2745 10:51:53.066184 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 10:51:53.069071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 10:51:53.069150 ==
2748 10:51:53.069214 RX Vref Scan: 1
2749 10:51:53.069275
2750 10:51:53.072576 Set Vref Range= 32 -> 127
2751 10:51:53.072654
2752 10:51:53.075933 RX Vref 32 -> 127, step: 1
2753 10:51:53.076008
2754 10:51:53.079440 RX Delay -21 -> 252, step: 4
2755 10:51:53.079519
2756 10:51:53.082993 Set Vref, RX VrefLevel [Byte0]: 32
2757 10:51:53.085838 [Byte1]: 32
2758 10:51:53.085916
2759 10:51:53.089413 Set Vref, RX VrefLevel [Byte0]: 33
2760 10:51:53.092922 [Byte1]: 33
2761 10:51:53.092996
2762 10:51:53.096078 Set Vref, RX VrefLevel [Byte0]: 34
2763 10:51:53.099584 [Byte1]: 34
2764 10:51:53.103633
2765 10:51:53.106989 Set Vref, RX VrefLevel [Byte0]: 35
2766 10:51:53.107063 [Byte1]: 35
2767 10:51:53.111565
2768 10:51:53.111643 Set Vref, RX VrefLevel [Byte0]: 36
2769 10:51:53.114631 [Byte1]: 36
2770 10:51:53.119690
2771 10:51:53.119764 Set Vref, RX VrefLevel [Byte0]: 37
2772 10:51:53.122726 [Byte1]: 37
2773 10:51:53.127436
2774 10:51:53.127510 Set Vref, RX VrefLevel [Byte0]: 38
2775 10:51:53.130500 [Byte1]: 38
2776 10:51:53.135480
2777 10:51:53.135556 Set Vref, RX VrefLevel [Byte0]: 39
2778 10:51:53.138700 [Byte1]: 39
2779 10:51:53.143397
2780 10:51:53.143482 Set Vref, RX VrefLevel [Byte0]: 40
2781 10:51:53.146783 [Byte1]: 40
2782 10:51:53.150980
2783 10:51:53.151063 Set Vref, RX VrefLevel [Byte0]: 41
2784 10:51:53.154918 [Byte1]: 41
2785 10:51:53.159006
2786 10:51:53.159083 Set Vref, RX VrefLevel [Byte0]: 42
2787 10:51:53.162678 [Byte1]: 42
2788 10:51:53.167243
2789 10:51:53.167371 Set Vref, RX VrefLevel [Byte0]: 43
2790 10:51:53.173273 [Byte1]: 43
2791 10:51:53.173356
2792 10:51:53.176630 Set Vref, RX VrefLevel [Byte0]: 44
2793 10:51:53.180025 [Byte1]: 44
2794 10:51:53.180108
2795 10:51:53.183455 Set Vref, RX VrefLevel [Byte0]: 45
2796 10:51:53.186985 [Byte1]: 45
2797 10:51:53.191137
2798 10:51:53.191220 Set Vref, RX VrefLevel [Byte0]: 46
2799 10:51:53.194099 [Byte1]: 46
2800 10:51:53.198516
2801 10:51:53.198598 Set Vref, RX VrefLevel [Byte0]: 47
2802 10:51:53.202066 [Byte1]: 47
2803 10:51:53.206476
2804 10:51:53.206558 Set Vref, RX VrefLevel [Byte0]: 48
2805 10:51:53.210080 [Byte1]: 48
2806 10:51:53.214658
2807 10:51:53.214742 Set Vref, RX VrefLevel [Byte0]: 49
2808 10:51:53.217632 [Byte1]: 49
2809 10:51:53.222825
2810 10:51:53.222908 Set Vref, RX VrefLevel [Byte0]: 50
2811 10:51:53.225600 [Byte1]: 50
2812 10:51:53.230274
2813 10:51:53.230357 Set Vref, RX VrefLevel [Byte0]: 51
2814 10:51:53.233813 [Byte1]: 51
2815 10:51:53.238646
2816 10:51:53.238728 Set Vref, RX VrefLevel [Byte0]: 52
2817 10:51:53.241480 [Byte1]: 52
2818 10:51:53.246471
2819 10:51:53.246554 Set Vref, RX VrefLevel [Byte0]: 53
2820 10:51:53.249733 [Byte1]: 53
2821 10:51:53.253987
2822 10:51:53.254070 Set Vref, RX VrefLevel [Byte0]: 54
2823 10:51:53.257265 [Byte1]: 54
2824 10:51:53.262475
2825 10:51:53.262558 Set Vref, RX VrefLevel [Byte0]: 55
2826 10:51:53.265579 [Byte1]: 55
2827 10:51:53.270127
2828 10:51:53.272983 Set Vref, RX VrefLevel [Byte0]: 56
2829 10:51:53.276415 [Byte1]: 56
2830 10:51:53.276499
2831 10:51:53.279787 Set Vref, RX VrefLevel [Byte0]: 57
2832 10:51:53.283245 [Byte1]: 57
2833 10:51:53.283328
2834 10:51:53.286700 Set Vref, RX VrefLevel [Byte0]: 58
2835 10:51:53.289773 [Byte1]: 58
2836 10:51:53.293972
2837 10:51:53.294055 Set Vref, RX VrefLevel [Byte0]: 59
2838 10:51:53.297000 [Byte1]: 59
2839 10:51:53.301661
2840 10:51:53.301743 Set Vref, RX VrefLevel [Byte0]: 60
2841 10:51:53.304883 [Byte1]: 60
2842 10:51:53.309459
2843 10:51:53.309542 Set Vref, RX VrefLevel [Byte0]: 61
2844 10:51:53.312713 [Byte1]: 61
2845 10:51:53.317943
2846 10:51:53.318026 Set Vref, RX VrefLevel [Byte0]: 62
2847 10:51:53.321006 [Byte1]: 62
2848 10:51:53.325846
2849 10:51:53.325929 Set Vref, RX VrefLevel [Byte0]: 63
2850 10:51:53.328827 [Byte1]: 63
2851 10:51:53.333334
2852 10:51:53.333415 Set Vref, RX VrefLevel [Byte0]: 64
2853 10:51:53.339790 [Byte1]: 64
2854 10:51:53.339872
2855 10:51:53.343261 Set Vref, RX VrefLevel [Byte0]: 65
2856 10:51:53.346323 [Byte1]: 65
2857 10:51:53.346403
2858 10:51:53.349814 Set Vref, RX VrefLevel [Byte0]: 66
2859 10:51:53.353072 [Byte1]: 66
2860 10:51:53.357434
2861 10:51:53.357516 Set Vref, RX VrefLevel [Byte0]: 67
2862 10:51:53.360907 [Byte1]: 67
2863 10:51:53.364936
2864 10:51:53.365020 Set Vref, RX VrefLevel [Byte0]: 68
2865 10:51:53.368487 [Byte1]: 68
2866 10:51:53.373581
2867 10:51:53.373661 Final RX Vref Byte 0 = 51 to rank0
2868 10:51:53.376596 Final RX Vref Byte 1 = 51 to rank0
2869 10:51:53.380106 Final RX Vref Byte 0 = 51 to rank1
2870 10:51:53.383041 Final RX Vref Byte 1 = 51 to rank1==
2871 10:51:53.386838 Dram Type= 6, Freq= 0, CH_0, rank 0
2872 10:51:53.389606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 10:51:53.393251 ==
2874 10:51:53.393323 DQS Delay:
2875 10:51:53.393390 DQS0 = 0, DQS1 = 0
2876 10:51:53.396869 DQM Delay:
2877 10:51:53.396935 DQM0 = 115, DQM1 = 105
2878 10:51:53.399754 DQ Delay:
2879 10:51:53.403336 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
2880 10:51:53.406607 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2881 10:51:53.409933 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2882 10:51:53.413195 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2883 10:51:53.413267
2884 10:51:53.413328
2885 10:51:53.419965 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2886 10:51:53.423518 CH0 RK0: MR19=303, MR18=FCEC
2887 10:51:53.430093 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2888 10:51:53.430169
2889 10:51:53.433792 ----->DramcWriteLeveling(PI) begin...
2890 10:51:53.433864 ==
2891 10:51:53.436566 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 10:51:53.439932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 10:51:53.440002 ==
2894 10:51:53.443578 Write leveling (Byte 0): 32 => 32
2895 10:51:53.446698 Write leveling (Byte 1): 28 => 28
2896 10:51:53.449935 DramcWriteLeveling(PI) end<-----
2897 10:51:53.450004
2898 10:51:53.450071 ==
2899 10:51:53.453342 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 10:51:53.457213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 10:51:53.460266 ==
2902 10:51:53.460340 [Gating] SW mode calibration
2903 10:51:53.466987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2904 10:51:53.473600 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2905 10:51:53.476612 0 15 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
2906 10:51:53.483313 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2907 10:51:53.487014 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 10:51:53.490046 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 10:51:53.496593 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 10:51:53.500241 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 10:51:53.503672 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 10:51:53.510000 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
2913 10:51:53.513387 1 0 0 | B1->B0 | 2f2f 2727 | 1 0 | (1 1) (0 0)
2914 10:51:53.516801 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2915 10:51:53.523647 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 10:51:53.527027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 10:51:53.530322 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 10:51:53.533441 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 10:51:53.540249 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2920 10:51:53.543534 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2921 10:51:53.546860 1 1 0 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (0 0)
2922 10:51:53.553433 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2923 10:51:53.556534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 10:51:53.559972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 10:51:53.566459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 10:51:53.569832 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 10:51:53.572913 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 10:51:53.579925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2929 10:51:53.582969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2930 10:51:53.586293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2931 10:51:53.593150 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:51:53.596494 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:51:53.600288 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 10:51:53.606596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:51:53.609675 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:51:53.613098 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 10:51:53.619869 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 10:51:53.623187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 10:51:53.626599 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 10:51:53.632995 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 10:51:53.636113 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 10:51:53.639646 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 10:51:53.646345 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 10:51:53.649577 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2945 10:51:53.652938 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2946 10:51:53.656024 Total UI for P1: 0, mck2ui 16
2947 10:51:53.659954 best dqsien dly found for B0: ( 1, 3, 28)
2948 10:51:53.663280 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 10:51:53.666168 Total UI for P1: 0, mck2ui 16
2950 10:51:53.669763 best dqsien dly found for B1: ( 1, 4, 0)
2951 10:51:53.673141 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2952 10:51:53.675968 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2953 10:51:53.679924
2954 10:51:53.683181 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2955 10:51:53.686317 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2956 10:51:53.689591 [Gating] SW calibration Done
2957 10:51:53.689673 ==
2958 10:51:53.693071 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 10:51:53.696632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 10:51:53.696702 ==
2961 10:51:53.696771 RX Vref Scan: 0
2962 10:51:53.696828
2963 10:51:53.699362 RX Vref 0 -> 0, step: 1
2964 10:51:53.699432
2965 10:51:53.702944 RX Delay -40 -> 252, step: 8
2966 10:51:53.706294 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2967 10:51:53.709419 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2968 10:51:53.716827 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2969 10:51:53.719978 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2970 10:51:53.723225 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2971 10:51:53.726544 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2972 10:51:53.729459 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2973 10:51:53.732809 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2974 10:51:53.740026 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2975 10:51:53.742888 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2976 10:51:53.746276 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2977 10:51:53.749676 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2978 10:51:53.753005 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2979 10:51:53.759577 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2980 10:51:53.763660 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2981 10:51:53.766531 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2982 10:51:53.766638 ==
2983 10:51:53.770181 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 10:51:53.773086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 10:51:53.773161 ==
2986 10:51:53.776396 DQS Delay:
2987 10:51:53.776521 DQS0 = 0, DQS1 = 0
2988 10:51:53.780033 DQM Delay:
2989 10:51:53.780108 DQM0 = 115, DQM1 = 106
2990 10:51:53.783221 DQ Delay:
2991 10:51:53.786108 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2992 10:51:53.789795 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2993 10:51:53.793171 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2994 10:51:53.796812 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2995 10:51:53.796909
2996 10:51:53.797000
2997 10:51:53.797086 ==
2998 10:51:53.799849 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 10:51:53.803212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 10:51:53.803305 ==
3001 10:51:53.803426
3002 10:51:53.803485
3003 10:51:53.806062 TX Vref Scan disable
3004 10:51:53.809370 == TX Byte 0 ==
3005 10:51:53.813194 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3006 10:51:53.816184 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3007 10:51:53.819746 == TX Byte 1 ==
3008 10:51:53.823143 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3009 10:51:53.826539 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3010 10:51:53.826634 ==
3011 10:51:53.829759 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 10:51:53.832856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 10:51:53.832929 ==
3014 10:51:53.846701 TX Vref=22, minBit 3, minWin=25, winSum=422
3015 10:51:53.849580 TX Vref=24, minBit 3, minWin=25, winSum=428
3016 10:51:53.853098 TX Vref=26, minBit 14, minWin=26, winSum=435
3017 10:51:53.856308 TX Vref=28, minBit 12, minWin=26, winSum=437
3018 10:51:53.859908 TX Vref=30, minBit 13, minWin=26, winSum=436
3019 10:51:53.866476 TX Vref=32, minBit 12, minWin=26, winSum=439
3020 10:51:53.869886 [TxChooseVref] Worse bit 12, Min win 26, Win sum 439, Final Vref 32
3021 10:51:53.869960
3022 10:51:53.872858 Final TX Range 1 Vref 32
3023 10:51:53.872928
3024 10:51:53.872992 ==
3025 10:51:53.876204 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 10:51:53.879954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 10:51:53.883110 ==
3028 10:51:53.883205
3029 10:51:53.883291
3030 10:51:53.883413 TX Vref Scan disable
3031 10:51:53.886443 == TX Byte 0 ==
3032 10:51:53.890027 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3033 10:51:53.896659 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3034 10:51:53.896757 == TX Byte 1 ==
3035 10:51:53.900026 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3036 10:51:53.902960 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3037 10:51:53.906431
3038 10:51:53.906505 [DATLAT]
3039 10:51:53.906569 Freq=1200, CH0 RK1
3040 10:51:53.906627
3041 10:51:53.909833 DATLAT Default: 0xd
3042 10:51:53.909925 0, 0xFFFF, sum = 0
3043 10:51:53.913546 1, 0xFFFF, sum = 0
3044 10:51:53.913650 2, 0xFFFF, sum = 0
3045 10:51:53.916704 3, 0xFFFF, sum = 0
3046 10:51:53.916801 4, 0xFFFF, sum = 0
3047 10:51:53.920373 5, 0xFFFF, sum = 0
3048 10:51:53.923234 6, 0xFFFF, sum = 0
3049 10:51:53.923329 7, 0xFFFF, sum = 0
3050 10:51:53.926667 8, 0xFFFF, sum = 0
3051 10:51:53.926736 9, 0xFFFF, sum = 0
3052 10:51:53.929960 10, 0xFFFF, sum = 0
3053 10:51:53.930054 11, 0xFFFF, sum = 0
3054 10:51:53.933392 12, 0x0, sum = 1
3055 10:51:53.933464 13, 0x0, sum = 2
3056 10:51:53.937142 14, 0x0, sum = 3
3057 10:51:53.937238 15, 0x0, sum = 4
3058 10:51:53.937326 best_step = 13
3059 10:51:53.937410
3060 10:51:53.940013 ==
3061 10:51:53.943212 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 10:51:53.946562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 10:51:53.946662 ==
3064 10:51:53.946750 RX Vref Scan: 0
3065 10:51:53.946838
3066 10:51:53.949553 RX Vref 0 -> 0, step: 1
3067 10:51:53.949646
3068 10:51:53.953091 RX Delay -21 -> 252, step: 4
3069 10:51:53.956399 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3070 10:51:53.963244 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3071 10:51:53.966486 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3072 10:51:53.969829 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3073 10:51:53.973468 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3074 10:51:53.976349 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3075 10:51:53.983434 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3076 10:51:53.986818 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3077 10:51:53.989677 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3078 10:51:53.993050 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3079 10:51:53.996598 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3080 10:51:54.000002 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3081 10:51:54.006867 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3082 10:51:54.009799 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3083 10:51:54.012931 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3084 10:51:54.016626 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3085 10:51:54.016725 ==
3086 10:51:54.020212 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 10:51:54.026232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 10:51:54.026327 ==
3089 10:51:54.026416 DQS Delay:
3090 10:51:54.029736 DQS0 = 0, DQS1 = 0
3091 10:51:54.029829 DQM Delay:
3092 10:51:54.029915 DQM0 = 114, DQM1 = 104
3093 10:51:54.033171 DQ Delay:
3094 10:51:54.036512 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3095 10:51:54.039773 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3096 10:51:54.043224 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3097 10:51:54.046792 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
3098 10:51:54.046861
3099 10:51:54.046920
3100 10:51:54.056504 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3101 10:51:54.056585 CH0 RK1: MR19=303, MR18=FFF1
3102 10:51:54.063261 CH0_RK1: MR19=0x303, MR18=0xFFF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3103 10:51:54.066158 [RxdqsGatingPostProcess] freq 1200
3104 10:51:54.073212 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 10:51:54.076767 best DQS0 dly(2T, 0.5T) = (0, 12)
3106 10:51:54.079636 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 10:51:54.083220 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3108 10:51:54.086192 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 10:51:54.086300 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 10:51:54.089767 best DQS1 dly(2T, 0.5T) = (0, 12)
3111 10:51:54.093053 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 10:51:54.096520 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3113 10:51:54.099422 Pre-setting of DQS Precalculation
3114 10:51:54.106050 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 10:51:54.106145 ==
3116 10:51:54.109445 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 10:51:54.113369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 10:51:54.113471 ==
3119 10:51:54.119591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 10:51:54.122547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 10:51:54.132650 [CA 0] Center 38 (8~68) winsize 61
3122 10:51:54.136003 [CA 1] Center 38 (8~68) winsize 61
3123 10:51:54.139327 [CA 2] Center 35 (5~65) winsize 61
3124 10:51:54.142298 [CA 3] Center 34 (4~65) winsize 62
3125 10:51:54.146113 [CA 4] Center 34 (4~65) winsize 62
3126 10:51:54.149526 [CA 5] Center 34 (4~64) winsize 61
3127 10:51:54.149601
3128 10:51:54.152643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 10:51:54.152716
3130 10:51:54.156067 [CATrainingPosCal] consider 1 rank data
3131 10:51:54.159060 u2DelayCellTimex100 = 270/100 ps
3132 10:51:54.162564 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3133 10:51:54.166007 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3134 10:51:54.172341 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3135 10:51:54.175761 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3136 10:51:54.179273 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3137 10:51:54.182834 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3138 10:51:54.182914
3139 10:51:54.185788 CA PerBit enable=1, Macro0, CA PI delay=34
3140 10:51:54.185896
3141 10:51:54.189079 [CBTSetCACLKResult] CA Dly = 34
3142 10:51:54.189161 CS Dly: 6 (0~37)
3143 10:51:54.189228 ==
3144 10:51:54.192896 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 10:51:54.199163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 10:51:54.199245 ==
3147 10:51:54.202751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 10:51:54.209093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3149 10:51:54.218489 [CA 0] Center 38 (8~68) winsize 61
3150 10:51:54.221255 [CA 1] Center 38 (8~68) winsize 61
3151 10:51:54.224680 [CA 2] Center 34 (4~65) winsize 62
3152 10:51:54.228183 [CA 3] Center 34 (4~65) winsize 62
3153 10:51:54.231956 [CA 4] Center 34 (4~65) winsize 62
3154 10:51:54.234816 [CA 5] Center 33 (4~63) winsize 60
3155 10:51:54.234922
3156 10:51:54.238552 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3157 10:51:54.238635
3158 10:51:54.241710 [CATrainingPosCal] consider 2 rank data
3159 10:51:54.244739 u2DelayCellTimex100 = 270/100 ps
3160 10:51:54.248655 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3161 10:51:54.251939 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3162 10:51:54.258932 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 10:51:54.261466 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3164 10:51:54.264940 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3165 10:51:54.268355 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 10:51:54.268428
3167 10:51:54.271728 CA PerBit enable=1, Macro0, CA PI delay=33
3168 10:51:54.271798
3169 10:51:54.275104 [CBTSetCACLKResult] CA Dly = 33
3170 10:51:54.275172 CS Dly: 7 (0~40)
3171 10:51:54.275231
3172 10:51:54.278518 ----->DramcWriteLeveling(PI) begin...
3173 10:51:54.278600 ==
3174 10:51:54.281984 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 10:51:54.288522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 10:51:54.288600 ==
3177 10:51:54.292002 Write leveling (Byte 0): 26 => 26
3178 10:51:54.295320 Write leveling (Byte 1): 28 => 28
3179 10:51:54.295457 DramcWriteLeveling(PI) end<-----
3180 10:51:54.295548
3181 10:51:54.298488 ==
3182 10:51:54.301846 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 10:51:54.305361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 10:51:54.305463 ==
3185 10:51:54.308925 [Gating] SW mode calibration
3186 10:51:54.315241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 10:51:54.318616 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 10:51:54.325525 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3189 10:51:54.328666 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 10:51:54.332055 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 10:51:54.338394 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 10:51:54.341943 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 10:51:54.345145 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 10:51:54.351967 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3195 10:51:54.355248 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3196 10:51:54.358290 1 0 0 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 1)
3197 10:51:54.365404 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 10:51:54.368745 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 10:51:54.372529 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3200 10:51:54.375110 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 10:51:54.381853 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 10:51:54.385432 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 10:51:54.388856 1 0 28 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
3204 10:51:54.395271 1 1 0 | B1->B0 | 3b3b 3030 | 1 0 | (0 0) (1 1)
3205 10:51:54.398720 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 10:51:54.401986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 10:51:54.408534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 10:51:54.412303 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 10:51:54.414751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 10:51:54.421548 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 10:51:54.425050 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3212 10:51:54.428525 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3213 10:51:54.435725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:51:54.438577 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:51:54.441618 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:51:54.448493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:51:54.451657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:51:54.455192 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 10:51:54.461601 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 10:51:54.464820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 10:51:54.468595 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 10:51:54.474939 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 10:51:54.478169 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 10:51:54.481619 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 10:51:54.488653 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 10:51:54.491981 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 10:51:54.494954 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3228 10:51:54.498941 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3229 10:51:54.501552 Total UI for P1: 0, mck2ui 16
3230 10:51:54.505077 best dqsien dly found for B0: ( 1, 3, 28)
3231 10:51:54.511335 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 10:51:54.514878 Total UI for P1: 0, mck2ui 16
3233 10:51:54.518427 best dqsien dly found for B1: ( 1, 4, 0)
3234 10:51:54.521969 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3235 10:51:54.524714 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3236 10:51:54.524788
3237 10:51:54.528041 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3238 10:51:54.531612 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3239 10:51:54.535036 [Gating] SW calibration Done
3240 10:51:54.535110 ==
3241 10:51:54.538477 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 10:51:54.541526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 10:51:54.541602 ==
3244 10:51:54.545211 RX Vref Scan: 0
3245 10:51:54.545280
3246 10:51:54.545339 RX Vref 0 -> 0, step: 1
3247 10:51:54.545396
3248 10:51:54.548180 RX Delay -40 -> 252, step: 8
3249 10:51:54.551766 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3250 10:51:54.558357 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3251 10:51:54.561497 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3252 10:51:54.565294 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3253 10:51:54.568227 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3254 10:51:54.571951 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3255 10:51:54.578103 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3256 10:51:54.581594 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3257 10:51:54.585068 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3258 10:51:54.587908 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3259 10:51:54.591178 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3260 10:51:54.598465 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3261 10:51:54.601201 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3262 10:51:54.604558 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3263 10:51:54.608354 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3264 10:51:54.611158 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3265 10:51:54.614632 ==
3266 10:51:54.614713 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 10:51:54.621710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 10:51:54.621818 ==
3269 10:51:54.621910 DQS Delay:
3270 10:51:54.625094 DQS0 = 0, DQS1 = 0
3271 10:51:54.625175 DQM Delay:
3272 10:51:54.628429 DQM0 = 116, DQM1 = 109
3273 10:51:54.628510 DQ Delay:
3274 10:51:54.631740 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3275 10:51:54.634710 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3276 10:51:54.638025 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3277 10:51:54.641470 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3278 10:51:54.641550
3279 10:51:54.641614
3280 10:51:54.641672 ==
3281 10:51:54.644518 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 10:51:54.651577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 10:51:54.651658 ==
3284 10:51:54.651722
3285 10:51:54.651781
3286 10:51:54.651838 TX Vref Scan disable
3287 10:51:54.654545 == TX Byte 0 ==
3288 10:51:54.657915 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3289 10:51:54.661211 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3290 10:51:54.664563 == TX Byte 1 ==
3291 10:51:54.668154 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3292 10:51:54.674711 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3293 10:51:54.674792 ==
3294 10:51:54.678152 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 10:51:54.681084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 10:51:54.681166 ==
3297 10:51:54.692303 TX Vref=22, minBit 0, minWin=25, winSum=411
3298 10:51:54.695990 TX Vref=24, minBit 0, minWin=25, winSum=416
3299 10:51:54.699021 TX Vref=26, minBit 1, minWin=25, winSum=420
3300 10:51:54.702471 TX Vref=28, minBit 9, minWin=25, winSum=423
3301 10:51:54.705980 TX Vref=30, minBit 0, minWin=26, winSum=428
3302 10:51:54.712559 TX Vref=32, minBit 1, minWin=26, winSum=431
3303 10:51:54.716034 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 32
3304 10:51:54.716117
3305 10:51:54.719264 Final TX Range 1 Vref 32
3306 10:51:54.719392
3307 10:51:54.719458 ==
3308 10:51:54.722266 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 10:51:54.725775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 10:51:54.725857 ==
3311 10:51:54.728838
3312 10:51:54.728907
3313 10:51:54.728967 TX Vref Scan disable
3314 10:51:54.732702 == TX Byte 0 ==
3315 10:51:54.735360 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 10:51:54.738987 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 10:51:54.742054 == TX Byte 1 ==
3318 10:51:54.746073 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3319 10:51:54.748961 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3320 10:51:54.752361
3321 10:51:54.752441 [DATLAT]
3322 10:51:54.752504 Freq=1200, CH1 RK0
3323 10:51:54.752563
3324 10:51:54.755642 DATLAT Default: 0xd
3325 10:51:54.755722 0, 0xFFFF, sum = 0
3326 10:51:54.759152 1, 0xFFFF, sum = 0
3327 10:51:54.759234 2, 0xFFFF, sum = 0
3328 10:51:54.762492 3, 0xFFFF, sum = 0
3329 10:51:54.762574 4, 0xFFFF, sum = 0
3330 10:51:54.765878 5, 0xFFFF, sum = 0
3331 10:51:54.765960 6, 0xFFFF, sum = 0
3332 10:51:54.769030 7, 0xFFFF, sum = 0
3333 10:51:54.772525 8, 0xFFFF, sum = 0
3334 10:51:54.772607 9, 0xFFFF, sum = 0
3335 10:51:54.775402 10, 0xFFFF, sum = 0
3336 10:51:54.775483 11, 0xFFFF, sum = 0
3337 10:51:54.779201 12, 0x0, sum = 1
3338 10:51:54.779282 13, 0x0, sum = 2
3339 10:51:54.782631 14, 0x0, sum = 3
3340 10:51:54.782713 15, 0x0, sum = 4
3341 10:51:54.782777 best_step = 13
3342 10:51:54.782835
3343 10:51:54.786204 ==
3344 10:51:54.788746 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 10:51:54.792470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 10:51:54.792549 ==
3347 10:51:54.792611 RX Vref Scan: 1
3348 10:51:54.792668
3349 10:51:54.795685 Set Vref Range= 32 -> 127
3350 10:51:54.795764
3351 10:51:54.798747 RX Vref 32 -> 127, step: 1
3352 10:51:54.798826
3353 10:51:54.802301 RX Delay -21 -> 252, step: 4
3354 10:51:54.802379
3355 10:51:54.805235 Set Vref, RX VrefLevel [Byte0]: 32
3356 10:51:54.808769 [Byte1]: 32
3357 10:51:54.808848
3358 10:51:54.812091 Set Vref, RX VrefLevel [Byte0]: 33
3359 10:51:54.815449 [Byte1]: 33
3360 10:51:54.815530
3361 10:51:54.818921 Set Vref, RX VrefLevel [Byte0]: 34
3362 10:51:54.822515 [Byte1]: 34
3363 10:51:54.826378
3364 10:51:54.826455 Set Vref, RX VrefLevel [Byte0]: 35
3365 10:51:54.829990 [Byte1]: 35
3366 10:51:54.834413
3367 10:51:54.834505 Set Vref, RX VrefLevel [Byte0]: 36
3368 10:51:54.837898 [Byte1]: 36
3369 10:51:54.842514
3370 10:51:54.842594 Set Vref, RX VrefLevel [Byte0]: 37
3371 10:51:54.846016 [Byte1]: 37
3372 10:51:54.850553
3373 10:51:54.850631 Set Vref, RX VrefLevel [Byte0]: 38
3374 10:51:54.853647 [Byte1]: 38
3375 10:51:54.858212
3376 10:51:54.858290 Set Vref, RX VrefLevel [Byte0]: 39
3377 10:51:54.861728 [Byte1]: 39
3378 10:51:54.866286
3379 10:51:54.866364 Set Vref, RX VrefLevel [Byte0]: 40
3380 10:51:54.869452 [Byte1]: 40
3381 10:51:54.874636
3382 10:51:54.874715 Set Vref, RX VrefLevel [Byte0]: 41
3383 10:51:54.877339 [Byte1]: 41
3384 10:51:54.881981
3385 10:51:54.882059 Set Vref, RX VrefLevel [Byte0]: 42
3386 10:51:54.885335 [Byte1]: 42
3387 10:51:54.890227
3388 10:51:54.890306 Set Vref, RX VrefLevel [Byte0]: 43
3389 10:51:54.892961 [Byte1]: 43
3390 10:51:54.897807
3391 10:51:54.897885 Set Vref, RX VrefLevel [Byte0]: 44
3392 10:51:54.901065 [Byte1]: 44
3393 10:51:54.905542
3394 10:51:54.905620 Set Vref, RX VrefLevel [Byte0]: 45
3395 10:51:54.909126 [Byte1]: 45
3396 10:51:54.913873
3397 10:51:54.913952 Set Vref, RX VrefLevel [Byte0]: 46
3398 10:51:54.917400 [Byte1]: 46
3399 10:51:54.921466
3400 10:51:54.921544 Set Vref, RX VrefLevel [Byte0]: 47
3401 10:51:54.925016 [Byte1]: 47
3402 10:51:54.929515
3403 10:51:54.929593 Set Vref, RX VrefLevel [Byte0]: 48
3404 10:51:54.933070 [Byte1]: 48
3405 10:51:54.937723
3406 10:51:54.937801 Set Vref, RX VrefLevel [Byte0]: 49
3407 10:51:54.940755 [Byte1]: 49
3408 10:51:54.945206
3409 10:51:54.945284 Set Vref, RX VrefLevel [Byte0]: 50
3410 10:51:54.948768 [Byte1]: 50
3411 10:51:54.953386
3412 10:51:54.953464 Set Vref, RX VrefLevel [Byte0]: 51
3413 10:51:54.956439 [Byte1]: 51
3414 10:51:54.961461
3415 10:51:54.961540 Set Vref, RX VrefLevel [Byte0]: 52
3416 10:51:54.964741 [Byte1]: 52
3417 10:51:54.968971
3418 10:51:54.969049 Set Vref, RX VrefLevel [Byte0]: 53
3419 10:51:54.972652 [Byte1]: 53
3420 10:51:54.977101
3421 10:51:54.977179 Set Vref, RX VrefLevel [Byte0]: 54
3422 10:51:54.980489 [Byte1]: 54
3423 10:51:54.985118
3424 10:51:54.985197 Set Vref, RX VrefLevel [Byte0]: 55
3425 10:51:54.987950 [Byte1]: 55
3426 10:51:54.992570
3427 10:51:54.992648 Set Vref, RX VrefLevel [Byte0]: 56
3428 10:51:54.995991 [Byte1]: 56
3429 10:51:55.000594
3430 10:51:55.000672 Set Vref, RX VrefLevel [Byte0]: 57
3431 10:51:55.003936 [Byte1]: 57
3432 10:51:55.008672
3433 10:51:55.008754 Set Vref, RX VrefLevel [Byte0]: 58
3434 10:51:55.012215 [Byte1]: 58
3435 10:51:55.016391
3436 10:51:55.016469 Set Vref, RX VrefLevel [Byte0]: 59
3437 10:51:55.020005 [Byte1]: 59
3438 10:51:55.024616
3439 10:51:55.024694 Set Vref, RX VrefLevel [Byte0]: 60
3440 10:51:55.027572 [Byte1]: 60
3441 10:51:55.032515
3442 10:51:55.032598 Set Vref, RX VrefLevel [Byte0]: 61
3443 10:51:55.035983 [Byte1]: 61
3444 10:51:55.040836
3445 10:51:55.040919 Set Vref, RX VrefLevel [Byte0]: 62
3446 10:51:55.043566 [Byte1]: 62
3447 10:51:55.048775
3448 10:51:55.048862 Set Vref, RX VrefLevel [Byte0]: 63
3449 10:51:55.051572 [Byte1]: 63
3450 10:51:55.056041
3451 10:51:55.056124 Set Vref, RX VrefLevel [Byte0]: 64
3452 10:51:55.059511 [Byte1]: 64
3453 10:51:55.064743
3454 10:51:55.064827 Set Vref, RX VrefLevel [Byte0]: 65
3455 10:51:55.067761 [Byte1]: 65
3456 10:51:55.072366
3457 10:51:55.072456 Set Vref, RX VrefLevel [Byte0]: 66
3458 10:51:55.075040 [Byte1]: 66
3459 10:51:55.079681
3460 10:51:55.079764 Set Vref, RX VrefLevel [Byte0]: 67
3461 10:51:55.083083 [Byte1]: 67
3462 10:51:55.088021
3463 10:51:55.088104 Set Vref, RX VrefLevel [Byte0]: 68
3464 10:51:55.091228 [Byte1]: 68
3465 10:51:55.096037
3466 10:51:55.096120 Set Vref, RX VrefLevel [Byte0]: 69
3467 10:51:55.099383 [Byte1]: 69
3468 10:51:55.103917
3469 10:51:55.104000 Final RX Vref Byte 0 = 54 to rank0
3470 10:51:55.106820 Final RX Vref Byte 1 = 53 to rank0
3471 10:51:55.110242 Final RX Vref Byte 0 = 54 to rank1
3472 10:51:55.113641 Final RX Vref Byte 1 = 53 to rank1==
3473 10:51:55.117551 Dram Type= 6, Freq= 0, CH_1, rank 0
3474 10:51:55.123441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 10:51:55.123525 ==
3476 10:51:55.123610 DQS Delay:
3477 10:51:55.123689 DQS0 = 0, DQS1 = 0
3478 10:51:55.127145 DQM Delay:
3479 10:51:55.127228 DQM0 = 115, DQM1 = 109
3480 10:51:55.130116 DQ Delay:
3481 10:51:55.133665 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3482 10:51:55.136834 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3483 10:51:55.140367 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3484 10:51:55.143419 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3485 10:51:55.143502
3486 10:51:55.143586
3487 10:51:55.150164 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbdf, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3488 10:51:55.153767 CH1 RK0: MR19=303, MR18=FBDF
3489 10:51:55.160565 CH1_RK0: MR19=0x303, MR18=0xFBDF, DQSOSC=412, MR23=63, INC=38, DEC=25
3490 10:51:55.160650
3491 10:51:55.164147 ----->DramcWriteLeveling(PI) begin...
3492 10:51:55.164232 ==
3493 10:51:55.167039 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 10:51:55.170485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 10:51:55.174120 ==
3496 10:51:55.174203 Write leveling (Byte 0): 28 => 28
3497 10:51:55.176872 Write leveling (Byte 1): 30 => 30
3498 10:51:55.180259 DramcWriteLeveling(PI) end<-----
3499 10:51:55.180342
3500 10:51:55.180442 ==
3501 10:51:55.183665 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 10:51:55.190794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 10:51:55.190884 ==
3504 10:51:55.190973 [Gating] SW mode calibration
3505 10:51:55.200802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3506 10:51:55.204268 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3507 10:51:55.207388 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3508 10:51:55.213812 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 10:51:55.217493 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 10:51:55.220427 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 10:51:55.227302 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 10:51:55.230603 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3513 10:51:55.234286 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
3514 10:51:55.240435 0 15 28 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (1 0)
3515 10:51:55.243871 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 10:51:55.247267 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 10:51:55.253965 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 10:51:55.257450 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 10:51:55.260671 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 10:51:55.267079 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3521 10:51:55.270425 1 0 24 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (1 1)
3522 10:51:55.273917 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3523 10:51:55.280338 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 10:51:55.283752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 10:51:55.287020 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 10:51:55.290301 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 10:51:55.297414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 10:51:55.300626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 10:51:55.304089 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3530 10:51:55.310233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3531 10:51:55.313503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 10:51:55.316925 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 10:51:55.323494 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 10:51:55.327025 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:51:55.330262 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 10:51:55.337100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 10:51:55.340511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 10:51:55.343630 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 10:51:55.350541 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 10:51:55.353462 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 10:51:55.357026 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 10:51:55.363840 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 10:51:55.367389 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 10:51:55.370090 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 10:51:55.377026 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3546 10:51:55.380069 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3547 10:51:55.383621 Total UI for P1: 0, mck2ui 16
3548 10:51:55.386623 best dqsien dly found for B0: ( 1, 3, 24)
3549 10:51:55.389880 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 10:51:55.393800 Total UI for P1: 0, mck2ui 16
3551 10:51:55.396856 best dqsien dly found for B1: ( 1, 3, 28)
3552 10:51:55.400287 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3553 10:51:55.403925 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3554 10:51:55.404006
3555 10:51:55.406689 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3556 10:51:55.414185 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3557 10:51:55.414268 [Gating] SW calibration Done
3558 10:51:55.414332 ==
3559 10:51:55.416522 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 10:51:55.423043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 10:51:55.423125 ==
3562 10:51:55.423190 RX Vref Scan: 0
3563 10:51:55.423250
3564 10:51:55.426586 RX Vref 0 -> 0, step: 1
3565 10:51:55.426667
3566 10:51:55.429977 RX Delay -40 -> 252, step: 8
3567 10:51:55.433526 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3568 10:51:55.436846 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3569 10:51:55.439769 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3570 10:51:55.446736 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3571 10:51:55.450145 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3572 10:51:55.453152 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3573 10:51:55.456902 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3574 10:51:55.460181 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3575 10:51:55.466278 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3576 10:51:55.469801 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3577 10:51:55.473077 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3578 10:51:55.476175 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3579 10:51:55.479612 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3580 10:51:55.486152 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3581 10:51:55.489504 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3582 10:51:55.492843 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3583 10:51:55.492991 ==
3584 10:51:55.496267 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 10:51:55.499765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 10:51:55.502892 ==
3587 10:51:55.503025 DQS Delay:
3588 10:51:55.503146 DQS0 = 0, DQS1 = 0
3589 10:51:55.505809 DQM Delay:
3590 10:51:55.505911 DQM0 = 113, DQM1 = 110
3591 10:51:55.509295 DQ Delay:
3592 10:51:55.512664 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3593 10:51:55.516130 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3594 10:51:55.519580 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3595 10:51:55.522496 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3596 10:51:55.522576
3597 10:51:55.522639
3598 10:51:55.522698 ==
3599 10:51:55.525915 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 10:51:55.529402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 10:51:55.529483 ==
3602 10:51:55.529547
3603 10:51:55.529605
3604 10:51:55.532839 TX Vref Scan disable
3605 10:51:55.535891 == TX Byte 0 ==
3606 10:51:55.539258 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3607 10:51:55.542824 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3608 10:51:55.545676 == TX Byte 1 ==
3609 10:51:55.549033 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3610 10:51:55.552560 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3611 10:51:55.552673 ==
3612 10:51:55.556428 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 10:51:55.562371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 10:51:55.562452 ==
3615 10:51:55.572570 TX Vref=22, minBit 1, minWin=25, winSum=419
3616 10:51:55.575928 TX Vref=24, minBit 15, minWin=25, winSum=424
3617 10:51:55.579360 TX Vref=26, minBit 1, minWin=26, winSum=427
3618 10:51:55.582347 TX Vref=28, minBit 2, minWin=26, winSum=430
3619 10:51:55.585931 TX Vref=30, minBit 3, minWin=26, winSum=436
3620 10:51:55.592419 TX Vref=32, minBit 2, minWin=26, winSum=434
3621 10:51:55.596481 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 30
3622 10:51:55.596587
3623 10:51:55.599214 Final TX Range 1 Vref 30
3624 10:51:55.599310
3625 10:51:55.599429 ==
3626 10:51:55.602668 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 10:51:55.606053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 10:51:55.606159 ==
3629 10:51:55.606253
3630 10:51:55.609336
3631 10:51:55.609444 TX Vref Scan disable
3632 10:51:55.612777 == TX Byte 0 ==
3633 10:51:55.615740 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3634 10:51:55.619111 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3635 10:51:55.622458 == TX Byte 1 ==
3636 10:51:55.625707 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3637 10:51:55.629115 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3638 10:51:55.632522
3639 10:51:55.632623 [DATLAT]
3640 10:51:55.632713 Freq=1200, CH1 RK1
3641 10:51:55.632801
3642 10:51:55.636279 DATLAT Default: 0xd
3643 10:51:55.636384 0, 0xFFFF, sum = 0
3644 10:51:55.639019 1, 0xFFFF, sum = 0
3645 10:51:55.639118 2, 0xFFFF, sum = 0
3646 10:51:55.642569 3, 0xFFFF, sum = 0
3647 10:51:55.642650 4, 0xFFFF, sum = 0
3648 10:51:55.645788 5, 0xFFFF, sum = 0
3649 10:51:55.648954 6, 0xFFFF, sum = 0
3650 10:51:55.649058 7, 0xFFFF, sum = 0
3651 10:51:55.652530 8, 0xFFFF, sum = 0
3652 10:51:55.652663 9, 0xFFFF, sum = 0
3653 10:51:55.655521 10, 0xFFFF, sum = 0
3654 10:51:55.655658 11, 0xFFFF, sum = 0
3655 10:51:55.659283 12, 0x0, sum = 1
3656 10:51:55.659449 13, 0x0, sum = 2
3657 10:51:55.662189 14, 0x0, sum = 3
3658 10:51:55.662331 15, 0x0, sum = 4
3659 10:51:55.662456 best_step = 13
3660 10:51:55.665761
3661 10:51:55.665894 ==
3662 10:51:55.668677 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 10:51:55.672483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 10:51:55.672614 ==
3665 10:51:55.672731 RX Vref Scan: 0
3666 10:51:55.672842
3667 10:51:55.675469 RX Vref 0 -> 0, step: 1
3668 10:51:55.675595
3669 10:51:55.678903 RX Delay -21 -> 252, step: 4
3670 10:51:55.682372 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3671 10:51:55.688887 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3672 10:51:55.692396 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3673 10:51:55.695424 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3674 10:51:55.698756 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3675 10:51:55.702105 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3676 10:51:55.708991 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3677 10:51:55.711827 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3678 10:51:55.715387 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3679 10:51:55.718888 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3680 10:51:55.722330 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3681 10:51:55.729147 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3682 10:51:55.732307 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3683 10:51:55.735502 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3684 10:51:55.738567 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3685 10:51:55.742116 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3686 10:51:55.745761 ==
3687 10:51:55.748441 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 10:51:55.751973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 10:51:55.752055 ==
3690 10:51:55.752120 DQS Delay:
3691 10:51:55.755541 DQS0 = 0, DQS1 = 0
3692 10:51:55.755623 DQM Delay:
3693 10:51:55.758942 DQM0 = 113, DQM1 = 109
3694 10:51:55.759022 DQ Delay:
3695 10:51:55.761723 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3696 10:51:55.765027 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3697 10:51:55.768589 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3698 10:51:55.772051 DQ12 =116, DQ13 =120, DQ14 =116, DQ15 =118
3699 10:51:55.772133
3700 10:51:55.772197
3701 10:51:55.781826 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3702 10:51:55.781912 CH1 RK1: MR19=303, MR18=F6FC
3703 10:51:55.788684 CH1_RK1: MR19=0x303, MR18=0xF6FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3704 10:51:55.791539 [RxdqsGatingPostProcess] freq 1200
3705 10:51:55.798455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3706 10:51:55.801990 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 10:51:55.805179 best DQS1 dly(2T, 0.5T) = (0, 12)
3708 10:51:55.808183 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 10:51:55.811661 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3710 10:51:55.815045 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 10:51:55.818568 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 10:51:55.818682 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 10:51:55.821990 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 10:51:55.824967 Pre-setting of DQS Precalculation
3715 10:51:55.831952 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3716 10:51:55.838512 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3717 10:51:55.845094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3718 10:51:55.845176
3719 10:51:55.845242
3720 10:51:55.847952 [Calibration Summary] 2400 Mbps
3721 10:51:55.851261 CH 0, Rank 0
3722 10:51:55.851343 SW Impedance : PASS
3723 10:51:55.854857 DUTY Scan : NO K
3724 10:51:55.857875 ZQ Calibration : PASS
3725 10:51:55.857956 Jitter Meter : NO K
3726 10:51:55.861334 CBT Training : PASS
3727 10:51:55.861416 Write leveling : PASS
3728 10:51:55.865410 RX DQS gating : PASS
3729 10:51:55.868025 RX DQ/DQS(RDDQC) : PASS
3730 10:51:55.868116 TX DQ/DQS : PASS
3731 10:51:55.871480 RX DATLAT : PASS
3732 10:51:55.874484 RX DQ/DQS(Engine): PASS
3733 10:51:55.874565 TX OE : NO K
3734 10:51:55.878334 All Pass.
3735 10:51:55.878415
3736 10:51:55.878478 CH 0, Rank 1
3737 10:51:55.881197 SW Impedance : PASS
3738 10:51:55.881278 DUTY Scan : NO K
3739 10:51:55.884754 ZQ Calibration : PASS
3740 10:51:55.888062 Jitter Meter : NO K
3741 10:51:55.888143 CBT Training : PASS
3742 10:51:55.891144 Write leveling : PASS
3743 10:51:55.894784 RX DQS gating : PASS
3744 10:51:55.894866 RX DQ/DQS(RDDQC) : PASS
3745 10:51:55.897999 TX DQ/DQS : PASS
3746 10:51:55.901168 RX DATLAT : PASS
3747 10:51:55.901250 RX DQ/DQS(Engine): PASS
3748 10:51:55.904621 TX OE : NO K
3749 10:51:55.904703 All Pass.
3750 10:51:55.904767
3751 10:51:55.907983 CH 1, Rank 0
3752 10:51:55.908065 SW Impedance : PASS
3753 10:51:55.911353 DUTY Scan : NO K
3754 10:51:55.914265 ZQ Calibration : PASS
3755 10:51:55.914347 Jitter Meter : NO K
3756 10:51:55.917965 CBT Training : PASS
3757 10:51:55.920880 Write leveling : PASS
3758 10:51:55.920962 RX DQS gating : PASS
3759 10:51:55.924311 RX DQ/DQS(RDDQC) : PASS
3760 10:51:55.924392 TX DQ/DQS : PASS
3761 10:51:55.927815 RX DATLAT : PASS
3762 10:51:55.930727 RX DQ/DQS(Engine): PASS
3763 10:51:55.930809 TX OE : NO K
3764 10:51:55.934116 All Pass.
3765 10:51:55.934198
3766 10:51:55.934261 CH 1, Rank 1
3767 10:51:55.937696 SW Impedance : PASS
3768 10:51:55.937777 DUTY Scan : NO K
3769 10:51:55.940956 ZQ Calibration : PASS
3770 10:51:55.944436 Jitter Meter : NO K
3771 10:51:55.944526 CBT Training : PASS
3772 10:51:55.947784 Write leveling : PASS
3773 10:51:55.950800 RX DQS gating : PASS
3774 10:51:55.950882 RX DQ/DQS(RDDQC) : PASS
3775 10:51:55.954317 TX DQ/DQS : PASS
3776 10:51:55.957310 RX DATLAT : PASS
3777 10:51:55.957392 RX DQ/DQS(Engine): PASS
3778 10:51:55.960865 TX OE : NO K
3779 10:51:55.960947 All Pass.
3780 10:51:55.961012
3781 10:51:55.964635 DramC Write-DBI off
3782 10:51:55.967667 PER_BANK_REFRESH: Hybrid Mode
3783 10:51:55.967748 TX_TRACKING: ON
3784 10:51:55.977180 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3785 10:51:55.980737 [FAST_K] Save calibration result to emmc
3786 10:51:55.983970 dramc_set_vcore_voltage set vcore to 650000
3787 10:51:55.987278 Read voltage for 600, 5
3788 10:51:55.987384 Vio18 = 0
3789 10:51:55.987463 Vcore = 650000
3790 10:51:55.990850 Vdram = 0
3791 10:51:55.990931 Vddq = 0
3792 10:51:55.990996 Vmddr = 0
3793 10:51:55.997260 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3794 10:51:56.000716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3795 10:51:56.003805 MEM_TYPE=3, freq_sel=19
3796 10:51:56.007196 sv_algorithm_assistance_LP4_1600
3797 10:51:56.010799 ============ PULL DRAM RESETB DOWN ============
3798 10:51:56.013725 ========== PULL DRAM RESETB DOWN end =========
3799 10:51:56.020379 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3800 10:51:56.023711 ===================================
3801 10:51:56.023792 LPDDR4 DRAM CONFIGURATION
3802 10:51:56.027305 ===================================
3803 10:51:56.030454 EX_ROW_EN[0] = 0x0
3804 10:51:56.033451 EX_ROW_EN[1] = 0x0
3805 10:51:56.033533 LP4Y_EN = 0x0
3806 10:51:56.037486 WORK_FSP = 0x0
3807 10:51:56.037572 WL = 0x2
3808 10:51:56.040436 RL = 0x2
3809 10:51:56.040518 BL = 0x2
3810 10:51:56.043961 RPST = 0x0
3811 10:51:56.044042 RD_PRE = 0x0
3812 10:51:56.047233 WR_PRE = 0x1
3813 10:51:56.047342 WR_PST = 0x0
3814 10:51:56.050738 DBI_WR = 0x0
3815 10:51:56.050823 DBI_RD = 0x0
3816 10:51:56.053941 OTF = 0x1
3817 10:51:56.056755 ===================================
3818 10:51:56.060145 ===================================
3819 10:51:56.060227 ANA top config
3820 10:51:56.063826 ===================================
3821 10:51:56.066798 DLL_ASYNC_EN = 0
3822 10:51:56.070451 ALL_SLAVE_EN = 1
3823 10:51:56.073799 NEW_RANK_MODE = 1
3824 10:51:56.073882 DLL_IDLE_MODE = 1
3825 10:51:56.076830 LP45_APHY_COMB_EN = 1
3826 10:51:56.080245 TX_ODT_DIS = 1
3827 10:51:56.083755 NEW_8X_MODE = 1
3828 10:51:56.087016 ===================================
3829 10:51:56.090483 ===================================
3830 10:51:56.093407 data_rate = 1200
3831 10:51:56.093489 CKR = 1
3832 10:51:56.096845 DQ_P2S_RATIO = 8
3833 10:51:56.099953 ===================================
3834 10:51:56.103386 CA_P2S_RATIO = 8
3835 10:51:56.106922 DQ_CA_OPEN = 0
3836 10:51:56.109957 DQ_SEMI_OPEN = 0
3837 10:51:56.113293 CA_SEMI_OPEN = 0
3838 10:51:56.113375 CA_FULL_RATE = 0
3839 10:51:56.116997 DQ_CKDIV4_EN = 1
3840 10:51:56.119844 CA_CKDIV4_EN = 1
3841 10:51:56.123142 CA_PREDIV_EN = 0
3842 10:51:56.126535 PH8_DLY = 0
3843 10:51:56.130089 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3844 10:51:56.130171 DQ_AAMCK_DIV = 4
3845 10:51:56.133485 CA_AAMCK_DIV = 4
3846 10:51:56.136468 CA_ADMCK_DIV = 4
3847 10:51:56.139709 DQ_TRACK_CA_EN = 0
3848 10:51:56.143928 CA_PICK = 600
3849 10:51:56.146586 CA_MCKIO = 600
3850 10:51:56.149751 MCKIO_SEMI = 0
3851 10:51:56.149836 PLL_FREQ = 2288
3852 10:51:56.152909 DQ_UI_PI_RATIO = 32
3853 10:51:56.156508 CA_UI_PI_RATIO = 0
3854 10:51:56.159536 ===================================
3855 10:51:56.163110 ===================================
3856 10:51:56.166161 memory_type:LPDDR4
3857 10:51:56.169471 GP_NUM : 10
3858 10:51:56.169553 SRAM_EN : 1
3859 10:51:56.172957 MD32_EN : 0
3860 10:51:56.175977 ===================================
3861 10:51:56.176059 [ANA_INIT] >>>>>>>>>>>>>>
3862 10:51:56.179378 <<<<<< [CONFIGURE PHASE]: ANA_TX
3863 10:51:56.182861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3864 10:51:56.186451 ===================================
3865 10:51:56.189364 data_rate = 1200,PCW = 0X5800
3866 10:51:56.192690 ===================================
3867 10:51:56.196020 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3868 10:51:56.202953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 10:51:56.205979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 10:51:56.212709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3871 10:51:56.216542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3872 10:51:56.219472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3873 10:51:56.222494 [ANA_INIT] flow start
3874 10:51:56.222576 [ANA_INIT] PLL >>>>>>>>
3875 10:51:56.225964 [ANA_INIT] PLL <<<<<<<<
3876 10:51:56.229455 [ANA_INIT] MIDPI >>>>>>>>
3877 10:51:56.229538 [ANA_INIT] MIDPI <<<<<<<<
3878 10:51:56.232890 [ANA_INIT] DLL >>>>>>>>
3879 10:51:56.235834 [ANA_INIT] flow end
3880 10:51:56.239158 ============ LP4 DIFF to SE enter ============
3881 10:51:56.242739 ============ LP4 DIFF to SE exit ============
3882 10:51:56.245675 [ANA_INIT] <<<<<<<<<<<<<
3883 10:51:56.249184 [Flow] Enable top DCM control >>>>>
3884 10:51:56.252571 [Flow] Enable top DCM control <<<<<
3885 10:51:56.255884 Enable DLL master slave shuffle
3886 10:51:56.259205 ==============================================================
3887 10:51:56.262167 Gating Mode config
3888 10:51:56.269129 ==============================================================
3889 10:51:56.269212 Config description:
3890 10:51:56.279303 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3891 10:51:56.285943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3892 10:51:56.289217 SELPH_MODE 0: By rank 1: By Phase
3893 10:51:56.295929 ==============================================================
3894 10:51:56.298663 GAT_TRACK_EN = 1
3895 10:51:56.302311 RX_GATING_MODE = 2
3896 10:51:56.305577 RX_GATING_TRACK_MODE = 2
3897 10:51:56.309060 SELPH_MODE = 1
3898 10:51:56.312030 PICG_EARLY_EN = 1
3899 10:51:56.315642 VALID_LAT_VALUE = 1
3900 10:51:56.319333 ==============================================================
3901 10:51:56.322709 Enter into Gating configuration >>>>
3902 10:51:56.325490 Exit from Gating configuration <<<<
3903 10:51:56.328825 Enter into DVFS_PRE_config >>>>>
3904 10:51:56.342252 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3905 10:51:56.342337 Exit from DVFS_PRE_config <<<<<
3906 10:51:56.345535 Enter into PICG configuration >>>>
3907 10:51:56.348384 Exit from PICG configuration <<<<
3908 10:51:56.351713 [RX_INPUT] configuration >>>>>
3909 10:51:56.354875 [RX_INPUT] configuration <<<<<
3910 10:51:56.362093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3911 10:51:56.365234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3912 10:51:56.371930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 10:51:56.378167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 10:51:56.385284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 10:51:56.391612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 10:51:56.395205 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3917 10:51:56.398393 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3918 10:51:56.401675 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3919 10:51:56.408187 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3920 10:51:56.411736 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3921 10:51:56.415236 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 10:51:56.418216 ===================================
3923 10:51:56.421755 LPDDR4 DRAM CONFIGURATION
3924 10:51:56.424883 ===================================
3925 10:51:56.428141 EX_ROW_EN[0] = 0x0
3926 10:51:56.428222 EX_ROW_EN[1] = 0x0
3927 10:51:56.431269 LP4Y_EN = 0x0
3928 10:51:56.431401 WORK_FSP = 0x0
3929 10:51:56.434864 WL = 0x2
3930 10:51:56.434971 RL = 0x2
3931 10:51:56.437949 BL = 0x2
3932 10:51:56.438030 RPST = 0x0
3933 10:51:56.441367 RD_PRE = 0x0
3934 10:51:56.441449 WR_PRE = 0x1
3935 10:51:56.444545 WR_PST = 0x0
3936 10:51:56.444652 DBI_WR = 0x0
3937 10:51:56.448088 DBI_RD = 0x0
3938 10:51:56.448169 OTF = 0x1
3939 10:51:56.451665 ===================================
3940 10:51:56.454440 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3941 10:51:56.461250 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3942 10:51:56.464887 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 10:51:56.468165 ===================================
3944 10:51:56.471445 LPDDR4 DRAM CONFIGURATION
3945 10:51:56.474501 ===================================
3946 10:51:56.474582 EX_ROW_EN[0] = 0x10
3947 10:51:56.477991 EX_ROW_EN[1] = 0x0
3948 10:51:56.481008 LP4Y_EN = 0x0
3949 10:51:56.481089 WORK_FSP = 0x0
3950 10:51:56.484516 WL = 0x2
3951 10:51:56.484597 RL = 0x2
3952 10:51:56.488041 BL = 0x2
3953 10:51:56.488122 RPST = 0x0
3954 10:51:56.490925 RD_PRE = 0x0
3955 10:51:56.491007 WR_PRE = 0x1
3956 10:51:56.494308 WR_PST = 0x0
3957 10:51:56.494390 DBI_WR = 0x0
3958 10:51:56.497759 DBI_RD = 0x0
3959 10:51:56.497840 OTF = 0x1
3960 10:51:56.501301 ===================================
3961 10:51:56.507891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3962 10:51:56.511849 nWR fixed to 30
3963 10:51:56.515282 [ModeRegInit_LP4] CH0 RK0
3964 10:51:56.515370 [ModeRegInit_LP4] CH0 RK1
3965 10:51:56.518438 [ModeRegInit_LP4] CH1 RK0
3966 10:51:56.522058 [ModeRegInit_LP4] CH1 RK1
3967 10:51:56.522140 match AC timing 17
3968 10:51:56.528630 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3969 10:51:56.531889 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3970 10:51:56.535166 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3971 10:51:56.541892 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3972 10:51:56.545393 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3973 10:51:56.545475 ==
3974 10:51:56.548482 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 10:51:56.552260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 10:51:56.552362 ==
3977 10:51:56.558801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 10:51:56.564771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3979 10:51:56.568971 [CA 0] Center 36 (6~66) winsize 61
3980 10:51:56.571752 [CA 1] Center 35 (5~66) winsize 62
3981 10:51:56.574761 [CA 2] Center 34 (4~65) winsize 62
3982 10:51:56.578335 [CA 3] Center 34 (4~65) winsize 62
3983 10:51:56.581270 [CA 4] Center 34 (4~64) winsize 61
3984 10:51:56.585155 [CA 5] Center 33 (3~64) winsize 62
3985 10:51:56.585236
3986 10:51:56.588002 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3987 10:51:56.588114
3988 10:51:56.591652 [CATrainingPosCal] consider 1 rank data
3989 10:51:56.594516 u2DelayCellTimex100 = 270/100 ps
3990 10:51:56.597796 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 10:51:56.601380 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3992 10:51:56.604794 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3993 10:51:56.608114 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 10:51:56.614861 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3995 10:51:56.617699 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 10:51:56.617780
3997 10:51:56.621330 CA PerBit enable=1, Macro0, CA PI delay=33
3998 10:51:56.621411
3999 10:51:56.624317 [CBTSetCACLKResult] CA Dly = 33
4000 10:51:56.624398 CS Dly: 4 (0~35)
4001 10:51:56.624469 ==
4002 10:51:56.627760 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 10:51:56.634708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 10:51:56.634790 ==
4005 10:51:56.637516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 10:51:56.643985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4007 10:51:56.648005 [CA 0] Center 36 (6~66) winsize 61
4008 10:51:56.650710 [CA 1] Center 36 (6~66) winsize 61
4009 10:51:56.654166 [CA 2] Center 34 (4~64) winsize 61
4010 10:51:56.657708 [CA 3] Center 34 (4~64) winsize 61
4011 10:51:56.660663 [CA 4] Center 33 (3~64) winsize 62
4012 10:51:56.664208 [CA 5] Center 33 (3~64) winsize 62
4013 10:51:56.664289
4014 10:51:56.667376 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4015 10:51:56.667457
4016 10:51:56.670707 [CATrainingPosCal] consider 2 rank data
4017 10:51:56.673795 u2DelayCellTimex100 = 270/100 ps
4018 10:51:56.677891 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 10:51:56.680692 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4020 10:51:56.687211 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4021 10:51:56.690858 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4022 10:51:56.693799 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4023 10:51:56.697321 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 10:51:56.697402
4025 10:51:56.700771 CA PerBit enable=1, Macro0, CA PI delay=33
4026 10:51:56.700852
4027 10:51:56.704226 [CBTSetCACLKResult] CA Dly = 33
4028 10:51:56.704307 CS Dly: 4 (0~36)
4029 10:51:56.704370
4030 10:51:56.707148 ----->DramcWriteLeveling(PI) begin...
4031 10:51:56.710430 ==
4032 10:51:56.713740 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 10:51:56.717424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 10:51:56.717506 ==
4035 10:51:56.720547 Write leveling (Byte 0): 33 => 33
4036 10:51:56.723463 Write leveling (Byte 1): 29 => 29
4037 10:51:56.727057 DramcWriteLeveling(PI) end<-----
4038 10:51:56.727137
4039 10:51:56.727200 ==
4040 10:51:56.730672 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 10:51:56.733452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 10:51:56.733533 ==
4043 10:51:56.737164 [Gating] SW mode calibration
4044 10:51:56.743251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4045 10:51:56.750047 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4046 10:51:56.753653 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 10:51:56.756831 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 10:51:56.763217 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 10:51:56.766429 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4050 10:51:56.770050 0 9 16 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (0 0)
4051 10:51:56.776939 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4052 10:51:56.779981 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 10:51:56.783257 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 10:51:56.786977 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 10:51:56.793271 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 10:51:56.796757 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 10:51:56.800257 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 10:51:56.806470 0 10 16 | B1->B0 | 3131 3b3b | 0 1 | (0 0) (0 0)
4059 10:51:56.810040 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 10:51:56.812908 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 10:51:56.819971 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 10:51:56.822976 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 10:51:56.826284 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 10:51:56.833531 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 10:51:56.836420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 10:51:56.839934 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 10:51:56.846359 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4068 10:51:56.849735 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 10:51:56.853112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 10:51:56.859866 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 10:51:56.862884 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:51:56.866248 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 10:51:56.872938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 10:51:56.876284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 10:51:56.879700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 10:51:56.886552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 10:51:56.889419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 10:51:56.892808 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 10:51:56.899892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 10:51:56.902726 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 10:51:56.906460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 10:51:56.912778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4083 10:51:56.916233 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 10:51:56.919621 Total UI for P1: 0, mck2ui 16
4085 10:51:56.922880 best dqsien dly found for B0: ( 0, 13, 16)
4086 10:51:56.926491 Total UI for P1: 0, mck2ui 16
4087 10:51:56.929286 best dqsien dly found for B1: ( 0, 13, 16)
4088 10:51:56.932637 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4089 10:51:56.935946 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4090 10:51:56.936052
4091 10:51:56.939288 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4092 10:51:56.942886 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4093 10:51:56.945723 [Gating] SW calibration Done
4094 10:51:56.945829 ==
4095 10:51:56.949265 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 10:51:56.952835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 10:51:56.952945 ==
4098 10:51:56.956199 RX Vref Scan: 0
4099 10:51:56.956272
4100 10:51:56.959459 RX Vref 0 -> 0, step: 1
4101 10:51:56.959539
4102 10:51:56.962774 RX Delay -230 -> 252, step: 16
4103 10:51:56.965720 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4104 10:51:56.969134 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4105 10:51:56.972527 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4106 10:51:56.976044 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4107 10:51:56.982291 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4108 10:51:56.985596 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4109 10:51:56.989235 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4110 10:51:56.992477 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4111 10:51:56.999514 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4112 10:51:57.002398 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4113 10:51:57.005972 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4114 10:51:57.008870 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4115 10:51:57.015789 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4116 10:51:57.018736 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4117 10:51:57.022139 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4118 10:51:57.025540 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4119 10:51:57.025636 ==
4120 10:51:57.029057 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 10:51:57.035660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 10:51:57.035764 ==
4123 10:51:57.035863 DQS Delay:
4124 10:51:57.038706 DQS0 = 0, DQS1 = 0
4125 10:51:57.038810 DQM Delay:
4126 10:51:57.038898 DQM0 = 40, DQM1 = 34
4127 10:51:57.042200 DQ Delay:
4128 10:51:57.045567 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4129 10:51:57.049165 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4130 10:51:57.052039 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4131 10:51:57.055810 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4132 10:51:57.055894
4133 10:51:57.055955
4134 10:51:57.056048 ==
4135 10:51:57.058961 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 10:51:57.062183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 10:51:57.062281 ==
4138 10:51:57.062383
4139 10:51:57.062468
4140 10:51:57.065516 TX Vref Scan disable
4141 10:51:57.065592 == TX Byte 0 ==
4142 10:51:57.072306 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4143 10:51:57.075505 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4144 10:51:57.075592 == TX Byte 1 ==
4145 10:51:57.081753 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4146 10:51:57.085303 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4147 10:51:57.085381 ==
4148 10:51:57.088638 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 10:51:57.092106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 10:51:57.092177 ==
4151 10:51:57.092237
4152 10:51:57.095451
4153 10:51:57.095525 TX Vref Scan disable
4154 10:51:57.099128 == TX Byte 0 ==
4155 10:51:57.101993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4156 10:51:57.108448 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4157 10:51:57.108521 == TX Byte 1 ==
4158 10:51:57.112050 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4159 10:51:57.118443 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4160 10:51:57.118543
4161 10:51:57.118636 [DATLAT]
4162 10:51:57.118723 Freq=600, CH0 RK0
4163 10:51:57.118812
4164 10:51:57.122126 DATLAT Default: 0x9
4165 10:51:57.122220 0, 0xFFFF, sum = 0
4166 10:51:57.125349 1, 0xFFFF, sum = 0
4167 10:51:57.128640 2, 0xFFFF, sum = 0
4168 10:51:57.128710 3, 0xFFFF, sum = 0
4169 10:51:57.132009 4, 0xFFFF, sum = 0
4170 10:51:57.132083 5, 0xFFFF, sum = 0
4171 10:51:57.135016 6, 0xFFFF, sum = 0
4172 10:51:57.135113 7, 0xFFFF, sum = 0
4173 10:51:57.138342 8, 0x0, sum = 1
4174 10:51:57.138430 9, 0x0, sum = 2
4175 10:51:57.138492 10, 0x0, sum = 3
4176 10:51:57.141644 11, 0x0, sum = 4
4177 10:51:57.141750 best_step = 9
4178 10:51:57.141854
4179 10:51:57.141944 ==
4180 10:51:57.144889 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 10:51:57.152041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 10:51:57.152115 ==
4183 10:51:57.152176 RX Vref Scan: 1
4184 10:51:57.152240
4185 10:51:57.154875 RX Vref 0 -> 0, step: 1
4186 10:51:57.154968
4187 10:51:57.158371 RX Delay -195 -> 252, step: 8
4188 10:51:57.158464
4189 10:51:57.161753 Set Vref, RX VrefLevel [Byte0]: 51
4190 10:51:57.165156 [Byte1]: 51
4191 10:51:57.165251
4192 10:51:57.168309 Final RX Vref Byte 0 = 51 to rank0
4193 10:51:57.171504 Final RX Vref Byte 1 = 51 to rank0
4194 10:51:57.174939 Final RX Vref Byte 0 = 51 to rank1
4195 10:51:57.178357 Final RX Vref Byte 1 = 51 to rank1==
4196 10:51:57.181535 Dram Type= 6, Freq= 0, CH_0, rank 0
4197 10:51:57.185282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 10:51:57.185362 ==
4199 10:51:57.188220 DQS Delay:
4200 10:51:57.188300 DQS0 = 0, DQS1 = 0
4201 10:51:57.191734 DQM Delay:
4202 10:51:57.191814 DQM0 = 42, DQM1 = 33
4203 10:51:57.191877 DQ Delay:
4204 10:51:57.194934 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4205 10:51:57.198239 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4206 10:51:57.201697 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4207 10:51:57.204957 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4208 10:51:57.205037
4209 10:51:57.205100
4210 10:51:57.214712 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4211 10:51:57.218240 CH0 RK0: MR19=808, MR18=4120
4212 10:51:57.225228 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4213 10:51:57.225309
4214 10:51:57.228118 ----->DramcWriteLeveling(PI) begin...
4215 10:51:57.228199 ==
4216 10:51:57.231652 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 10:51:57.234808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 10:51:57.234889 ==
4219 10:51:57.238233 Write leveling (Byte 0): 33 => 33
4220 10:51:57.240984 Write leveling (Byte 1): 29 => 29
4221 10:51:57.244905 DramcWriteLeveling(PI) end<-----
4222 10:51:57.244986
4223 10:51:57.245049 ==
4224 10:51:57.247753 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 10:51:57.251159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 10:51:57.251240 ==
4227 10:51:57.254822 [Gating] SW mode calibration
4228 10:51:57.261175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 10:51:57.268011 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4230 10:51:57.271040 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 10:51:57.274296 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 10:51:57.281229 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 10:51:57.284708 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
4234 10:51:57.287702 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4235 10:51:57.294668 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 10:51:57.297487 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 10:51:57.300837 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 10:51:57.308007 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 10:51:57.310883 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 10:51:57.314434 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 10:51:57.320916 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
4242 10:51:57.324365 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
4243 10:51:57.327948 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 10:51:57.334451 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 10:51:57.337779 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 10:51:57.341001 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 10:51:57.347342 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 10:51:57.350840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 10:51:57.354246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4250 10:51:57.361060 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4251 10:51:57.363904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:51:57.367431 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 10:51:57.370879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 10:51:57.377332 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:51:57.380808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:51:57.383677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 10:51:57.390313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 10:51:57.393839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 10:51:57.397187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 10:51:57.404027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 10:51:57.407481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 10:51:57.410492 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 10:51:57.416893 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 10:51:57.420353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4265 10:51:57.423703 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 10:51:57.429994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 10:51:57.433671 Total UI for P1: 0, mck2ui 16
4268 10:51:57.437365 best dqsien dly found for B0: ( 0, 13, 14)
4269 10:51:57.437447 Total UI for P1: 0, mck2ui 16
4270 10:51:57.443734 best dqsien dly found for B1: ( 0, 13, 14)
4271 10:51:57.447253 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4272 10:51:57.450391 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4273 10:51:57.450473
4274 10:51:57.453712 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4275 10:51:57.457017 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4276 10:51:57.460401 [Gating] SW calibration Done
4277 10:51:57.460483 ==
4278 10:51:57.463923 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 10:51:57.466964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 10:51:57.467047 ==
4281 10:51:57.469927 RX Vref Scan: 0
4282 10:51:57.470009
4283 10:51:57.470073 RX Vref 0 -> 0, step: 1
4284 10:51:57.473239
4285 10:51:57.473320 RX Delay -230 -> 252, step: 16
4286 10:51:57.479862 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4287 10:51:57.483161 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4288 10:51:57.486648 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4289 10:51:57.490113 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4290 10:51:57.496565 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4291 10:51:57.499946 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4292 10:51:57.503430 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4293 10:51:57.506831 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4294 10:51:57.510325 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4295 10:51:57.516955 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4296 10:51:57.519899 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4297 10:51:57.522937 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4298 10:51:57.526377 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4299 10:51:57.533416 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4300 10:51:57.536366 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4301 10:51:57.539952 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4302 10:51:57.540044 ==
4303 10:51:57.543242 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 10:51:57.546175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 10:51:57.549497 ==
4306 10:51:57.549589 DQS Delay:
4307 10:51:57.549680 DQS0 = 0, DQS1 = 0
4308 10:51:57.552936 DQM Delay:
4309 10:51:57.553002 DQM0 = 42, DQM1 = 35
4310 10:51:57.556438 DQ Delay:
4311 10:51:57.556529 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4312 10:51:57.559973 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4313 10:51:57.562935 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4314 10:51:57.566348 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4315 10:51:57.569695
4316 10:51:57.569792
4317 10:51:57.569882 ==
4318 10:51:57.572822 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 10:51:57.576547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 10:51:57.576616 ==
4321 10:51:57.576677
4322 10:51:57.576738
4323 10:51:57.579784 TX Vref Scan disable
4324 10:51:57.579853 == TX Byte 0 ==
4325 10:51:57.586405 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4326 10:51:57.589435 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4327 10:51:57.589528 == TX Byte 1 ==
4328 10:51:57.596106 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4329 10:51:57.599414 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4330 10:51:57.599485 ==
4331 10:51:57.602911 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 10:51:57.605780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 10:51:57.605876 ==
4334 10:51:57.605965
4335 10:51:57.606050
4336 10:51:57.609278 TX Vref Scan disable
4337 10:51:57.612432 == TX Byte 0 ==
4338 10:51:57.616103 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4339 10:51:57.618975 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4340 10:51:57.622619 == TX Byte 1 ==
4341 10:51:57.626114 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4342 10:51:57.629098 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4343 10:51:57.632220
4344 10:51:57.632286 [DATLAT]
4345 10:51:57.632346 Freq=600, CH0 RK1
4346 10:51:57.632403
4347 10:51:57.635639 DATLAT Default: 0x9
4348 10:51:57.635704 0, 0xFFFF, sum = 0
4349 10:51:57.639109 1, 0xFFFF, sum = 0
4350 10:51:57.639203 2, 0xFFFF, sum = 0
4351 10:51:57.642698 3, 0xFFFF, sum = 0
4352 10:51:57.642763 4, 0xFFFF, sum = 0
4353 10:51:57.645817 5, 0xFFFF, sum = 0
4354 10:51:57.648855 6, 0xFFFF, sum = 0
4355 10:51:57.648921 7, 0xFFFF, sum = 0
4356 10:51:57.648979 8, 0x0, sum = 1
4357 10:51:57.652401 9, 0x0, sum = 2
4358 10:51:57.652466 10, 0x0, sum = 3
4359 10:51:57.655336 11, 0x0, sum = 4
4360 10:51:57.655433 best_step = 9
4361 10:51:57.655520
4362 10:51:57.655603 ==
4363 10:51:57.658897 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 10:51:57.666005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 10:51:57.666105 ==
4366 10:51:57.666195 RX Vref Scan: 0
4367 10:51:57.666286
4368 10:51:57.668768 RX Vref 0 -> 0, step: 1
4369 10:51:57.668868
4370 10:51:57.672362 RX Delay -195 -> 252, step: 8
4371 10:51:57.675928 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4372 10:51:57.682155 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4373 10:51:57.685678 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4374 10:51:57.688913 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4375 10:51:57.692220 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4376 10:51:57.699089 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4377 10:51:57.702334 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4378 10:51:57.705307 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4379 10:51:57.708685 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4380 10:51:57.712228 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4381 10:51:57.718971 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4382 10:51:57.721900 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4383 10:51:57.725476 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4384 10:51:57.729079 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4385 10:51:57.735447 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4386 10:51:57.739064 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4387 10:51:57.739156 ==
4388 10:51:57.741797 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 10:51:57.745061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 10:51:57.745153 ==
4391 10:51:57.748683 DQS Delay:
4392 10:51:57.748752 DQS0 = 0, DQS1 = 0
4393 10:51:57.748809 DQM Delay:
4394 10:51:57.752161 DQM0 = 39, DQM1 = 33
4395 10:51:57.752238 DQ Delay:
4396 10:51:57.755374 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4397 10:51:57.758575 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4398 10:51:57.761636 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4399 10:51:57.765092 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4400 10:51:57.765187
4401 10:51:57.765272
4402 10:51:57.774917 [DQSOSCAuto] RK1, (LSB)MR18= 0x492c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4403 10:51:57.775002 CH0 RK1: MR19=808, MR18=492C
4404 10:51:57.781974 CH0_RK1: MR19=0x808, MR18=0x492C, DQSOSC=396, MR23=63, INC=167, DEC=111
4405 10:51:57.785516 [RxdqsGatingPostProcess] freq 600
4406 10:51:57.791580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 10:51:57.794881 Pre-setting of DQS Precalculation
4408 10:51:57.798362 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4409 10:51:57.798444 ==
4410 10:51:57.801680 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 10:51:57.808598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 10:51:57.808680 ==
4413 10:51:57.811497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 10:51:57.818404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 10:51:57.821658 [CA 0] Center 35 (5~65) winsize 61
4416 10:51:57.825250 [CA 1] Center 35 (5~66) winsize 62
4417 10:51:57.828150 [CA 2] Center 33 (3~64) winsize 62
4418 10:51:57.831825 [CA 3] Center 33 (3~64) winsize 62
4419 10:51:57.835403 [CA 4] Center 33 (3~64) winsize 62
4420 10:51:57.838691 [CA 5] Center 33 (3~64) winsize 62
4421 10:51:57.838767
4422 10:51:57.841738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 10:51:57.841835
4424 10:51:57.845369 [CATrainingPosCal] consider 1 rank data
4425 10:51:57.848641 u2DelayCellTimex100 = 270/100 ps
4426 10:51:57.851961 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4427 10:51:57.854950 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 10:51:57.858346 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 10:51:57.865069 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 10:51:57.868602 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 10:51:57.871871 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 10:51:57.871947
4433 10:51:57.874799 CA PerBit enable=1, Macro0, CA PI delay=33
4434 10:51:57.874900
4435 10:51:57.878358 [CBTSetCACLKResult] CA Dly = 33
4436 10:51:57.878459 CS Dly: 5 (0~36)
4437 10:51:57.878555 ==
4438 10:51:57.881738 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 10:51:57.888283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 10:51:57.888362 ==
4441 10:51:57.891552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 10:51:57.898342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4443 10:51:57.901548 [CA 0] Center 35 (5~66) winsize 62
4444 10:51:57.905059 [CA 1] Center 35 (5~66) winsize 62
4445 10:51:57.908466 [CA 2] Center 34 (4~65) winsize 62
4446 10:51:57.911278 [CA 3] Center 34 (3~65) winsize 63
4447 10:51:57.914955 [CA 4] Center 34 (4~65) winsize 62
4448 10:51:57.917980 [CA 5] Center 33 (3~64) winsize 62
4449 10:51:57.918060
4450 10:51:57.921459 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4451 10:51:57.921539
4452 10:51:57.925302 [CATrainingPosCal] consider 2 rank data
4453 10:51:57.928450 u2DelayCellTimex100 = 270/100 ps
4454 10:51:57.931582 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4455 10:51:57.934673 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 10:51:57.941167 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4457 10:51:57.944648 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 10:51:57.948116 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4459 10:51:57.951336 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 10:51:57.951437
4461 10:51:57.955131 CA PerBit enable=1, Macro0, CA PI delay=33
4462 10:51:57.955212
4463 10:51:57.957965 [CBTSetCACLKResult] CA Dly = 33
4464 10:51:57.958045 CS Dly: 5 (0~36)
4465 10:51:57.958108
4466 10:51:57.964725 ----->DramcWriteLeveling(PI) begin...
4467 10:51:57.964807 ==
4468 10:51:57.967705 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 10:51:57.971534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 10:51:57.971616 ==
4471 10:51:57.974460 Write leveling (Byte 0): 29 => 29
4472 10:51:57.977853 Write leveling (Byte 1): 30 => 30
4473 10:51:57.981250 DramcWriteLeveling(PI) end<-----
4474 10:51:57.981330
4475 10:51:57.981393 ==
4476 10:51:57.984246 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 10:51:57.987675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 10:51:57.987756 ==
4479 10:51:57.991124 [Gating] SW mode calibration
4480 10:51:57.997596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4481 10:51:58.004298 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4482 10:51:58.007411 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 10:51:58.010889 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 10:51:58.017498 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 10:51:58.021002 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
4486 10:51:58.024267 0 9 16 | B1->B0 | 2929 2727 | 1 1 | (1 1) (0 0)
4487 10:51:58.031152 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 10:51:58.034081 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 10:51:58.037316 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 10:51:58.043951 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 10:51:58.047558 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 10:51:58.050520 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 10:51:58.057589 0 10 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4494 10:51:58.060258 0 10 16 | B1->B0 | 4141 4040 | 0 0 | (0 0) (0 0)
4495 10:51:58.064193 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 10:51:58.070637 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 10:51:58.073849 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 10:51:58.077361 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 10:51:58.080534 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 10:51:58.087256 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 10:51:58.090854 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 10:51:58.093687 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 10:51:58.100686 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 10:51:58.103954 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 10:51:58.107265 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 10:51:58.113421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 10:51:58.116865 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 10:51:58.120413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 10:51:58.127080 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 10:51:58.130404 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 10:51:58.133777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 10:51:58.140274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 10:51:58.143869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 10:51:58.146782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 10:51:58.153836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 10:51:58.157045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 10:51:58.160033 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 10:51:58.166910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4519 10:51:58.166992 Total UI for P1: 0, mck2ui 16
4520 10:51:58.173896 best dqsien dly found for B0: ( 0, 13, 14)
4521 10:51:58.177870 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 10:51:58.179983 Total UI for P1: 0, mck2ui 16
4523 10:51:58.183470 best dqsien dly found for B1: ( 0, 13, 16)
4524 10:51:58.186798 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4525 10:51:58.189719 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4526 10:51:58.189800
4527 10:51:58.193054 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4528 10:51:58.196676 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4529 10:51:58.199677 [Gating] SW calibration Done
4530 10:51:58.199758 ==
4531 10:51:58.203246 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 10:51:58.209782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 10:51:58.209864 ==
4534 10:51:58.209929 RX Vref Scan: 0
4535 10:51:58.209988
4536 10:51:58.213229 RX Vref 0 -> 0, step: 1
4537 10:51:58.213310
4538 10:51:58.216200 RX Delay -230 -> 252, step: 16
4539 10:51:58.219810 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4540 10:51:58.222900 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4541 10:51:58.226367 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4542 10:51:58.232691 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4543 10:51:58.236051 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4544 10:51:58.239673 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4545 10:51:58.243451 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4546 10:51:58.246367 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4547 10:51:58.252776 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4548 10:51:58.256320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4549 10:51:58.259456 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4550 10:51:58.262914 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4551 10:51:58.269743 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4552 10:51:58.273120 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4553 10:51:58.275903 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4554 10:51:58.279605 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4555 10:51:58.279690 ==
4556 10:51:58.282711 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 10:51:58.289533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 10:51:58.289614 ==
4559 10:51:58.289677 DQS Delay:
4560 10:51:58.292316 DQS0 = 0, DQS1 = 0
4561 10:51:58.292396 DQM Delay:
4562 10:51:58.295811 DQM0 = 43, DQM1 = 34
4563 10:51:58.295891 DQ Delay:
4564 10:51:58.299401 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4565 10:51:58.302446 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4566 10:51:58.305938 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4567 10:51:58.309469 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4568 10:51:58.309549
4569 10:51:58.309613
4570 10:51:58.309671 ==
4571 10:51:58.312719 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 10:51:58.315565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 10:51:58.315646 ==
4574 10:51:58.315710
4575 10:51:58.315770
4576 10:51:58.318776 TX Vref Scan disable
4577 10:51:58.322413 == TX Byte 0 ==
4578 10:51:58.325395 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 10:51:58.329462 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 10:51:58.332073 == TX Byte 1 ==
4581 10:51:58.335442 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 10:51:58.339214 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 10:51:58.339317 ==
4584 10:51:58.342011 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 10:51:58.348523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 10:51:58.348604 ==
4587 10:51:58.348669
4588 10:51:58.348727
4589 10:51:58.348785 TX Vref Scan disable
4590 10:51:58.352815 == TX Byte 0 ==
4591 10:51:58.356135 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4592 10:51:58.359670 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4593 10:51:58.362698 == TX Byte 1 ==
4594 10:51:58.366132 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 10:51:58.369501 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 10:51:58.373126
4597 10:51:58.373201 [DATLAT]
4598 10:51:58.373263 Freq=600, CH1 RK0
4599 10:51:58.373325
4600 10:51:58.376501 DATLAT Default: 0x9
4601 10:51:58.376570 0, 0xFFFF, sum = 0
4602 10:51:58.379565 1, 0xFFFF, sum = 0
4603 10:51:58.379636 2, 0xFFFF, sum = 0
4604 10:51:58.382775 3, 0xFFFF, sum = 0
4605 10:51:58.386018 4, 0xFFFF, sum = 0
4606 10:51:58.386088 5, 0xFFFF, sum = 0
4607 10:51:58.389515 6, 0xFFFF, sum = 0
4608 10:51:58.389584 7, 0xFFFF, sum = 0
4609 10:51:58.392880 8, 0x0, sum = 1
4610 10:51:58.392955 9, 0x0, sum = 2
4611 10:51:58.393018 10, 0x0, sum = 3
4612 10:51:58.396218 11, 0x0, sum = 4
4613 10:51:58.396288 best_step = 9
4614 10:51:58.396348
4615 10:51:58.396405 ==
4616 10:51:58.399110 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 10:51:58.406349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 10:51:58.406432 ==
4619 10:51:58.406497 RX Vref Scan: 1
4620 10:51:58.406556
4621 10:51:58.409170 RX Vref 0 -> 0, step: 1
4622 10:51:58.409250
4623 10:51:58.412632 RX Delay -195 -> 252, step: 8
4624 10:51:58.412713
4625 10:51:58.416065 Set Vref, RX VrefLevel [Byte0]: 54
4626 10:51:58.419282 [Byte1]: 53
4627 10:51:58.419419
4628 10:51:58.422530 Final RX Vref Byte 0 = 54 to rank0
4629 10:51:58.425914 Final RX Vref Byte 1 = 53 to rank0
4630 10:51:58.429429 Final RX Vref Byte 0 = 54 to rank1
4631 10:51:58.432733 Final RX Vref Byte 1 = 53 to rank1==
4632 10:51:58.435596 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 10:51:58.439128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 10:51:58.439209 ==
4635 10:51:58.442644 DQS Delay:
4636 10:51:58.442725 DQS0 = 0, DQS1 = 0
4637 10:51:58.445453 DQM Delay:
4638 10:51:58.445533 DQM0 = 41, DQM1 = 33
4639 10:51:58.445597 DQ Delay:
4640 10:51:58.448679 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4641 10:51:58.452279 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4642 10:51:58.455967 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4643 10:51:58.458791 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4644 10:51:58.458870
4645 10:51:58.458934
4646 10:51:58.468943 [DQSOSCAuto] RK0, (LSB)MR18= 0x4005, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
4647 10:51:58.471882 CH1 RK0: MR19=808, MR18=4005
4648 10:51:58.478776 CH1_RK0: MR19=0x808, MR18=0x4005, DQSOSC=397, MR23=63, INC=166, DEC=110
4649 10:51:58.478858
4650 10:51:58.482220 ----->DramcWriteLeveling(PI) begin...
4651 10:51:58.482301 ==
4652 10:51:58.485352 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 10:51:58.488872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 10:51:58.488953 ==
4655 10:51:58.492340 Write leveling (Byte 0): 29 => 29
4656 10:51:58.495354 Write leveling (Byte 1): 32 => 32
4657 10:51:58.498702 DramcWriteLeveling(PI) end<-----
4658 10:51:58.498782
4659 10:51:58.498844 ==
4660 10:51:58.502206 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 10:51:58.505185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 10:51:58.505266 ==
4663 10:51:58.508598 [Gating] SW mode calibration
4664 10:51:58.515147 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4665 10:51:58.521709 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4666 10:51:58.525532 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 10:51:58.528248 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4668 10:51:58.535487 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 10:51:58.538260 0 9 12 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
4670 10:51:58.541871 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4671 10:51:58.548739 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 10:51:58.552199 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 10:51:58.554952 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 10:51:58.561429 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 10:51:58.564910 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 10:51:58.568439 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4677 10:51:58.574896 0 10 12 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
4678 10:51:58.578021 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4679 10:51:58.581393 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 10:51:58.588041 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 10:51:58.591257 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 10:51:58.594984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 10:51:58.601554 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 10:51:58.604714 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 10:51:58.608013 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4686 10:51:58.614725 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 10:51:58.617728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 10:51:58.621474 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 10:51:58.627582 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:51:58.630999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 10:51:58.634484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 10:51:58.637821 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 10:51:58.644763 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 10:51:58.647727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 10:51:58.651219 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 10:51:58.657577 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 10:51:58.661161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 10:51:58.664081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 10:51:58.670835 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 10:51:58.674220 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4701 10:51:58.677793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4702 10:51:58.681127 Total UI for P1: 0, mck2ui 16
4703 10:51:58.684044 best dqsien dly found for B0: ( 0, 13, 8)
4704 10:51:58.690781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 10:51:58.690864 Total UI for P1: 0, mck2ui 16
4706 10:51:58.697690 best dqsien dly found for B1: ( 0, 13, 12)
4707 10:51:58.700888 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4708 10:51:58.704382 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4709 10:51:58.704465
4710 10:51:58.707895 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4711 10:51:58.710725 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4712 10:51:58.714330 [Gating] SW calibration Done
4713 10:51:58.714411 ==
4714 10:51:58.717142 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 10:51:58.720700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 10:51:58.720782 ==
4717 10:51:58.724125 RX Vref Scan: 0
4718 10:51:58.724206
4719 10:51:58.724270 RX Vref 0 -> 0, step: 1
4720 10:51:58.727313
4721 10:51:58.727437 RX Delay -230 -> 252, step: 16
4722 10:51:58.733843 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4723 10:51:58.737433 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4724 10:51:58.740418 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4725 10:51:58.743874 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4726 10:51:58.750216 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4727 10:51:58.753846 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4728 10:51:58.757223 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4729 10:51:58.760415 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4730 10:51:58.763317 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4731 10:51:58.770569 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4732 10:51:58.773480 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4733 10:51:58.776999 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4734 10:51:58.780515 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4735 10:51:58.787103 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4736 10:51:58.790538 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4737 10:51:58.793603 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4738 10:51:58.793685 ==
4739 10:51:58.796904 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 10:51:58.800340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 10:51:58.803307 ==
4742 10:51:58.803429 DQS Delay:
4743 10:51:58.803494 DQS0 = 0, DQS1 = 0
4744 10:51:58.806695 DQM Delay:
4745 10:51:58.806776 DQM0 = 42, DQM1 = 37
4746 10:51:58.810249 DQ Delay:
4747 10:51:58.810330 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4748 10:51:58.813627 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4749 10:51:58.816485 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4750 10:51:58.820174 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4751 10:51:58.820255
4752 10:51:58.822997
4753 10:51:58.823078 ==
4754 10:51:58.826532 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 10:51:58.829796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 10:51:58.829876 ==
4757 10:51:58.829941
4758 10:51:58.829999
4759 10:51:58.833380 TX Vref Scan disable
4760 10:51:58.833460 == TX Byte 0 ==
4761 10:51:58.839922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 10:51:58.843266 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 10:51:58.843355 == TX Byte 1 ==
4764 10:51:58.850357 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 10:51:58.853012 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 10:51:58.853093 ==
4767 10:51:58.856517 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 10:51:58.860078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 10:51:58.860159 ==
4770 10:51:58.860223
4771 10:51:58.860282
4772 10:51:58.863456 TX Vref Scan disable
4773 10:51:58.866348 == TX Byte 0 ==
4774 10:51:58.869679 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4775 10:51:58.872877 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4776 10:51:58.876561 == TX Byte 1 ==
4777 10:51:58.879765 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4778 10:51:58.882776 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4779 10:51:58.886316
4780 10:51:58.886397 [DATLAT]
4781 10:51:58.886460 Freq=600, CH1 RK1
4782 10:51:58.886521
4783 10:51:58.889703 DATLAT Default: 0x9
4784 10:51:58.889783 0, 0xFFFF, sum = 0
4785 10:51:58.893118 1, 0xFFFF, sum = 0
4786 10:51:58.893201 2, 0xFFFF, sum = 0
4787 10:51:58.896114 3, 0xFFFF, sum = 0
4788 10:51:58.896197 4, 0xFFFF, sum = 0
4789 10:51:58.899521 5, 0xFFFF, sum = 0
4790 10:51:58.902699 6, 0xFFFF, sum = 0
4791 10:51:58.902780 7, 0xFFFF, sum = 0
4792 10:51:58.902844 8, 0x0, sum = 1
4793 10:51:58.905969 9, 0x0, sum = 2
4794 10:51:58.906050 10, 0x0, sum = 3
4795 10:51:58.909187 11, 0x0, sum = 4
4796 10:51:58.909269 best_step = 9
4797 10:51:58.909332
4798 10:51:58.909391 ==
4799 10:51:58.912743 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 10:51:58.919468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 10:51:58.919550 ==
4802 10:51:58.919614 RX Vref Scan: 0
4803 10:51:58.919674
4804 10:51:58.922493 RX Vref 0 -> 0, step: 1
4805 10:51:58.922574
4806 10:51:58.925897 RX Delay -179 -> 252, step: 8
4807 10:51:58.929530 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4808 10:51:58.935890 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4809 10:51:58.939335 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4810 10:51:58.942754 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4811 10:51:58.945943 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4812 10:51:58.952434 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4813 10:51:58.956028 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4814 10:51:58.958914 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4815 10:51:58.962538 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4816 10:51:58.966125 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4817 10:51:58.972446 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4818 10:51:58.975931 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4819 10:51:58.979533 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4820 10:51:58.982415 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4821 10:51:58.989587 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4822 10:51:58.992420 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4823 10:51:58.992779 ==
4824 10:51:58.995878 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 10:51:58.999456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 10:51:58.999704 ==
4827 10:51:59.002760 DQS Delay:
4828 10:51:59.002994 DQS0 = 0, DQS1 = 0
4829 10:51:59.003179 DQM Delay:
4830 10:51:59.006122 DQM0 = 38, DQM1 = 33
4831 10:51:59.006356 DQ Delay:
4832 10:51:59.009694 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4833 10:51:59.012969 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4834 10:51:59.015930 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4835 10:51:59.018883 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4836 10:51:59.019171
4837 10:51:59.019541
4838 10:51:59.029176 [DQSOSCAuto] RK1, (LSB)MR18= 0x3140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4839 10:51:59.029505 CH1 RK1: MR19=808, MR18=3140
4840 10:51:59.035755 CH1_RK1: MR19=0x808, MR18=0x3140, DQSOSC=397, MR23=63, INC=166, DEC=110
4841 10:51:59.038968 [RxdqsGatingPostProcess] freq 600
4842 10:51:59.045387 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4843 10:51:59.049292 Pre-setting of DQS Precalculation
4844 10:51:59.051948 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4845 10:51:59.058586 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4846 10:51:59.068992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4847 10:51:59.069073
4848 10:51:59.069137
4849 10:51:59.072437 [Calibration Summary] 1200 Mbps
4850 10:51:59.072519 CH 0, Rank 0
4851 10:51:59.075266 SW Impedance : PASS
4852 10:51:59.075372 DUTY Scan : NO K
4853 10:51:59.078815 ZQ Calibration : PASS
4854 10:51:59.082449 Jitter Meter : NO K
4855 10:51:59.082530 CBT Training : PASS
4856 10:51:59.085391 Write leveling : PASS
4857 10:51:59.085472 RX DQS gating : PASS
4858 10:51:59.088772 RX DQ/DQS(RDDQC) : PASS
4859 10:51:59.092381 TX DQ/DQS : PASS
4860 10:51:59.092463 RX DATLAT : PASS
4861 10:51:59.095375 RX DQ/DQS(Engine): PASS
4862 10:51:59.098664 TX OE : NO K
4863 10:51:59.098746 All Pass.
4864 10:51:59.098810
4865 10:51:59.098870 CH 0, Rank 1
4866 10:51:59.101972 SW Impedance : PASS
4867 10:51:59.104974 DUTY Scan : NO K
4868 10:51:59.105056 ZQ Calibration : PASS
4869 10:51:59.108470 Jitter Meter : NO K
4870 10:51:59.111550 CBT Training : PASS
4871 10:51:59.111631 Write leveling : PASS
4872 10:51:59.114977 RX DQS gating : PASS
4873 10:51:59.118581 RX DQ/DQS(RDDQC) : PASS
4874 10:51:59.118663 TX DQ/DQS : PASS
4875 10:51:59.121833 RX DATLAT : PASS
4876 10:51:59.125265 RX DQ/DQS(Engine): PASS
4877 10:51:59.125347 TX OE : NO K
4878 10:51:59.128149 All Pass.
4879 10:51:59.128231
4880 10:51:59.128294 CH 1, Rank 0
4881 10:51:59.131867 SW Impedance : PASS
4882 10:51:59.131948 DUTY Scan : NO K
4883 10:51:59.134684 ZQ Calibration : PASS
4884 10:51:59.138175 Jitter Meter : NO K
4885 10:51:59.138257 CBT Training : PASS
4886 10:51:59.141572 Write leveling : PASS
4887 10:51:59.141653 RX DQS gating : PASS
4888 10:51:59.144756 RX DQ/DQS(RDDQC) : PASS
4889 10:51:59.148136 TX DQ/DQS : PASS
4890 10:51:59.148218 RX DATLAT : PASS
4891 10:51:59.151551 RX DQ/DQS(Engine): PASS
4892 10:51:59.154677 TX OE : NO K
4893 10:51:59.154754 All Pass.
4894 10:51:59.154816
4895 10:51:59.154874 CH 1, Rank 1
4896 10:51:59.158150 SW Impedance : PASS
4897 10:51:59.161536 DUTY Scan : NO K
4898 10:51:59.161608 ZQ Calibration : PASS
4899 10:51:59.164948 Jitter Meter : NO K
4900 10:51:59.167950 CBT Training : PASS
4901 10:51:59.168018 Write leveling : PASS
4902 10:51:59.171457 RX DQS gating : PASS
4903 10:51:59.174909 RX DQ/DQS(RDDQC) : PASS
4904 10:51:59.174975 TX DQ/DQS : PASS
4905 10:51:59.177836 RX DATLAT : PASS
4906 10:51:59.181266 RX DQ/DQS(Engine): PASS
4907 10:51:59.181334 TX OE : NO K
4908 10:51:59.184767 All Pass.
4909 10:51:59.184832
4910 10:51:59.184893 DramC Write-DBI off
4911 10:51:59.188071 PER_BANK_REFRESH: Hybrid Mode
4912 10:51:59.188138 TX_TRACKING: ON
4913 10:51:59.197828 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4914 10:51:59.201368 [FAST_K] Save calibration result to emmc
4915 10:51:59.204478 dramc_set_vcore_voltage set vcore to 662500
4916 10:51:59.207881 Read voltage for 933, 3
4917 10:51:59.207959 Vio18 = 0
4918 10:51:59.211336 Vcore = 662500
4919 10:51:59.211452 Vdram = 0
4920 10:51:59.211513 Vddq = 0
4921 10:51:59.211571 Vmddr = 0
4922 10:51:59.217835 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4923 10:51:59.224478 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4924 10:51:59.224560 MEM_TYPE=3, freq_sel=17
4925 10:51:59.228078 sv_algorithm_assistance_LP4_1600
4926 10:51:59.231303 ============ PULL DRAM RESETB DOWN ============
4927 10:51:59.237852 ========== PULL DRAM RESETB DOWN end =========
4928 10:51:59.241034 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4929 10:51:59.244337 ===================================
4930 10:51:59.247810 LPDDR4 DRAM CONFIGURATION
4931 10:51:59.251142 ===================================
4932 10:51:59.251223 EX_ROW_EN[0] = 0x0
4933 10:51:59.254144 EX_ROW_EN[1] = 0x0
4934 10:51:59.254225 LP4Y_EN = 0x0
4935 10:51:59.257448 WORK_FSP = 0x0
4936 10:51:59.260869 WL = 0x3
4937 10:51:59.260950 RL = 0x3
4938 10:51:59.264738 BL = 0x2
4939 10:51:59.264819 RPST = 0x0
4940 10:51:59.267580 RD_PRE = 0x0
4941 10:51:59.267660 WR_PRE = 0x1
4942 10:51:59.271233 WR_PST = 0x0
4943 10:51:59.271339 DBI_WR = 0x0
4944 10:51:59.274095 DBI_RD = 0x0
4945 10:51:59.274175 OTF = 0x1
4946 10:51:59.277556 ===================================
4947 10:51:59.280883 ===================================
4948 10:51:59.284107 ANA top config
4949 10:51:59.287602 ===================================
4950 10:51:59.287683 DLL_ASYNC_EN = 0
4951 10:51:59.291146 ALL_SLAVE_EN = 1
4952 10:51:59.294831 NEW_RANK_MODE = 1
4953 10:51:59.297688 DLL_IDLE_MODE = 1
4954 10:51:59.297769 LP45_APHY_COMB_EN = 1
4955 10:51:59.300812 TX_ODT_DIS = 1
4956 10:51:59.304364 NEW_8X_MODE = 1
4957 10:51:59.307651 ===================================
4958 10:51:59.310905 ===================================
4959 10:51:59.314436 data_rate = 1866
4960 10:51:59.317787 CKR = 1
4961 10:51:59.317867 DQ_P2S_RATIO = 8
4962 10:51:59.321043 ===================================
4963 10:51:59.324222 CA_P2S_RATIO = 8
4964 10:51:59.327764 DQ_CA_OPEN = 0
4965 10:51:59.331345 DQ_SEMI_OPEN = 0
4966 10:51:59.334081 CA_SEMI_OPEN = 0
4967 10:51:59.337743 CA_FULL_RATE = 0
4968 10:51:59.337823 DQ_CKDIV4_EN = 1
4969 10:51:59.341187 CA_CKDIV4_EN = 1
4970 10:51:59.344165 CA_PREDIV_EN = 0
4971 10:51:59.347636 PH8_DLY = 0
4972 10:51:59.350944 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4973 10:51:59.354254 DQ_AAMCK_DIV = 4
4974 10:51:59.354334 CA_AAMCK_DIV = 4
4975 10:51:59.357733 CA_ADMCK_DIV = 4
4976 10:51:59.361188 DQ_TRACK_CA_EN = 0
4977 10:51:59.364299 CA_PICK = 933
4978 10:51:59.367555 CA_MCKIO = 933
4979 10:51:59.371022 MCKIO_SEMI = 0
4980 10:51:59.374007 PLL_FREQ = 3732
4981 10:51:59.374088 DQ_UI_PI_RATIO = 32
4982 10:51:59.377575 CA_UI_PI_RATIO = 0
4983 10:51:59.380992 ===================================
4984 10:51:59.384277 ===================================
4985 10:51:59.387741 memory_type:LPDDR4
4986 10:51:59.390650 GP_NUM : 10
4987 10:51:59.390730 SRAM_EN : 1
4988 10:51:59.394163 MD32_EN : 0
4989 10:51:59.398065 ===================================
4990 10:51:59.400777 [ANA_INIT] >>>>>>>>>>>>>>
4991 10:51:59.400858 <<<<<< [CONFIGURE PHASE]: ANA_TX
4992 10:51:59.404182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4993 10:51:59.407736 ===================================
4994 10:51:59.410718 data_rate = 1866,PCW = 0X8f00
4995 10:51:59.414109 ===================================
4996 10:51:59.417767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4997 10:51:59.424274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 10:51:59.430885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 10:51:59.433983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5000 10:51:59.437275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5001 10:51:59.440577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5002 10:51:59.444273 [ANA_INIT] flow start
5003 10:51:59.444353 [ANA_INIT] PLL >>>>>>>>
5004 10:51:59.447700 [ANA_INIT] PLL <<<<<<<<
5005 10:51:59.450461 [ANA_INIT] MIDPI >>>>>>>>
5006 10:51:59.450542 [ANA_INIT] MIDPI <<<<<<<<
5007 10:51:59.454258 [ANA_INIT] DLL >>>>>>>>
5008 10:51:59.457198 [ANA_INIT] flow end
5009 10:51:59.460645 ============ LP4 DIFF to SE enter ============
5010 10:51:59.464214 ============ LP4 DIFF to SE exit ============
5011 10:51:59.467163 [ANA_INIT] <<<<<<<<<<<<<
5012 10:51:59.470448 [Flow] Enable top DCM control >>>>>
5013 10:51:59.473760 [Flow] Enable top DCM control <<<<<
5014 10:51:59.477411 Enable DLL master slave shuffle
5015 10:51:59.480885 ==============================================================
5016 10:51:59.483789 Gating Mode config
5017 10:51:59.490621 ==============================================================
5018 10:51:59.490702 Config description:
5019 10:51:59.500707 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5020 10:51:59.507078 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5021 10:51:59.510664 SELPH_MODE 0: By rank 1: By Phase
5022 10:51:59.517225 ==============================================================
5023 10:51:59.520483 GAT_TRACK_EN = 1
5024 10:51:59.523944 RX_GATING_MODE = 2
5025 10:51:59.526927 RX_GATING_TRACK_MODE = 2
5026 10:51:59.530007 SELPH_MODE = 1
5027 10:51:59.533479 PICG_EARLY_EN = 1
5028 10:51:59.536821 VALID_LAT_VALUE = 1
5029 10:51:59.540452 ==============================================================
5030 10:51:59.543911 Enter into Gating configuration >>>>
5031 10:51:59.546755 Exit from Gating configuration <<<<
5032 10:51:59.550321 Enter into DVFS_PRE_config >>>>>
5033 10:51:59.563524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5034 10:51:59.563608 Exit from DVFS_PRE_config <<<<<
5035 10:51:59.566795 Enter into PICG configuration >>>>
5036 10:51:59.570536 Exit from PICG configuration <<<<
5037 10:51:59.573363 [RX_INPUT] configuration >>>>>
5038 10:51:59.577133 [RX_INPUT] configuration <<<<<
5039 10:51:59.583455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5040 10:51:59.586496 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5041 10:51:59.593451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 10:51:59.599879 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 10:51:59.606392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 10:51:59.613045 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 10:51:59.616777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5046 10:51:59.619600 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5047 10:51:59.622973 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5048 10:51:59.629821 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5049 10:51:59.633297 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5050 10:51:59.636567 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 10:51:59.640017 ===================================
5052 10:51:59.643154 LPDDR4 DRAM CONFIGURATION
5053 10:51:59.646468 ===================================
5054 10:51:59.649761 EX_ROW_EN[0] = 0x0
5055 10:51:59.649835 EX_ROW_EN[1] = 0x0
5056 10:51:59.652702 LP4Y_EN = 0x0
5057 10:51:59.652798 WORK_FSP = 0x0
5058 10:51:59.656148 WL = 0x3
5059 10:51:59.656221 RL = 0x3
5060 10:51:59.660133 BL = 0x2
5061 10:51:59.660200 RPST = 0x0
5062 10:51:59.663094 RD_PRE = 0x0
5063 10:51:59.663160 WR_PRE = 0x1
5064 10:51:59.666510 WR_PST = 0x0
5065 10:51:59.666577 DBI_WR = 0x0
5066 10:51:59.669705 DBI_RD = 0x0
5067 10:51:59.669780 OTF = 0x1
5068 10:51:59.673013 ===================================
5069 10:51:59.675998 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5070 10:51:59.682923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5071 10:51:59.686255 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 10:51:59.689335 ===================================
5073 10:51:59.692805 LPDDR4 DRAM CONFIGURATION
5074 10:51:59.696174 ===================================
5075 10:51:59.696282 EX_ROW_EN[0] = 0x10
5076 10:51:59.699440 EX_ROW_EN[1] = 0x0
5077 10:51:59.702964 LP4Y_EN = 0x0
5078 10:51:59.703033 WORK_FSP = 0x0
5079 10:51:59.705827 WL = 0x3
5080 10:51:59.705894 RL = 0x3
5081 10:51:59.709356 BL = 0x2
5082 10:51:59.709456 RPST = 0x0
5083 10:51:59.712913 RD_PRE = 0x0
5084 10:51:59.712983 WR_PRE = 0x1
5085 10:51:59.715857 WR_PST = 0x0
5086 10:51:59.715925 DBI_WR = 0x0
5087 10:51:59.718997 DBI_RD = 0x0
5088 10:51:59.719066 OTF = 0x1
5089 10:51:59.722405 ===================================
5090 10:51:59.729152 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5091 10:51:59.733500 nWR fixed to 30
5092 10:51:59.736723 [ModeRegInit_LP4] CH0 RK0
5093 10:51:59.736798 [ModeRegInit_LP4] CH0 RK1
5094 10:51:59.740304 [ModeRegInit_LP4] CH1 RK0
5095 10:51:59.743575 [ModeRegInit_LP4] CH1 RK1
5096 10:51:59.743656 match AC timing 9
5097 10:51:59.749991 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5098 10:51:59.753874 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5099 10:51:59.756759 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5100 10:51:59.763385 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5101 10:51:59.766859 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5102 10:51:59.766940 ==
5103 10:51:59.770098 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 10:51:59.773424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 10:51:59.773505 ==
5106 10:51:59.780596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 10:51:59.786929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5108 10:51:59.790251 [CA 0] Center 38 (8~69) winsize 62
5109 10:51:59.793339 [CA 1] Center 38 (8~69) winsize 62
5110 10:51:59.796763 [CA 2] Center 35 (5~66) winsize 62
5111 10:51:59.800216 [CA 3] Center 34 (4~65) winsize 62
5112 10:51:59.803022 [CA 4] Center 34 (4~64) winsize 61
5113 10:51:59.806563 [CA 5] Center 34 (4~64) winsize 61
5114 10:51:59.806645
5115 10:51:59.810175 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5116 10:51:59.810255
5117 10:51:59.813058 [CATrainingPosCal] consider 1 rank data
5118 10:51:59.816544 u2DelayCellTimex100 = 270/100 ps
5119 10:51:59.820115 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5120 10:51:59.823005 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5121 10:51:59.826432 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5122 10:51:59.829384 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5123 10:51:59.832799 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5124 10:51:59.839547 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5125 10:51:59.839628
5126 10:51:59.842943 CA PerBit enable=1, Macro0, CA PI delay=34
5127 10:51:59.843025
5128 10:51:59.846287 [CBTSetCACLKResult] CA Dly = 34
5129 10:51:59.846369 CS Dly: 6 (0~37)
5130 10:51:59.846433 ==
5131 10:51:59.849823 Dram Type= 6, Freq= 0, CH_0, rank 1
5132 10:51:59.852747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 10:51:59.856226 ==
5134 10:51:59.859290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 10:51:59.866154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5136 10:51:59.869439 [CA 0] Center 38 (8~69) winsize 62
5137 10:51:59.872599 [CA 1] Center 38 (8~69) winsize 62
5138 10:51:59.875835 [CA 2] Center 35 (5~66) winsize 62
5139 10:51:59.879137 [CA 3] Center 35 (5~65) winsize 61
5140 10:51:59.882668 [CA 4] Center 33 (3~64) winsize 62
5141 10:51:59.885958 [CA 5] Center 33 (3~64) winsize 62
5142 10:51:59.886039
5143 10:51:59.889577 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5144 10:51:59.889658
5145 10:51:59.892786 [CATrainingPosCal] consider 2 rank data
5146 10:51:59.896262 u2DelayCellTimex100 = 270/100 ps
5147 10:51:59.899173 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5148 10:51:59.902581 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5149 10:51:59.905948 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5150 10:51:59.909722 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5151 10:51:59.915932 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 10:51:59.919521 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5153 10:51:59.919602
5154 10:51:59.922466 CA PerBit enable=1, Macro0, CA PI delay=34
5155 10:51:59.922547
5156 10:51:59.926058 [CBTSetCACLKResult] CA Dly = 34
5157 10:51:59.926139 CS Dly: 7 (0~39)
5158 10:51:59.926203
5159 10:51:59.929051 ----->DramcWriteLeveling(PI) begin...
5160 10:51:59.929133 ==
5161 10:51:59.932498 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 10:51:59.938768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 10:51:59.938849 ==
5164 10:51:59.942552 Write leveling (Byte 0): 34 => 34
5165 10:51:59.945379 Write leveling (Byte 1): 24 => 24
5166 10:51:59.945460 DramcWriteLeveling(PI) end<-----
5167 10:51:59.945524
5168 10:51:59.948676 ==
5169 10:51:59.952115 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 10:51:59.955911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 10:51:59.955992 ==
5172 10:51:59.958519 [Gating] SW mode calibration
5173 10:51:59.965691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5174 10:51:59.968678 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5175 10:51:59.975040 0 14 0 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (1 1)
5176 10:51:59.978770 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5177 10:51:59.982298 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 10:51:59.988953 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 10:51:59.992018 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 10:51:59.995391 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 10:52:00.001939 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 10:52:00.005277 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5183 10:52:00.008724 0 15 0 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
5184 10:52:00.015531 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5185 10:52:00.018470 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 10:52:00.021768 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 10:52:00.028171 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 10:52:00.031589 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 10:52:00.035099 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 10:52:00.041971 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5191 10:52:00.044678 1 0 0 | B1->B0 | 3232 4343 | 0 0 | (0 0) (0 0)
5192 10:52:00.048143 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 10:52:00.054972 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 10:52:00.057810 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 10:52:00.061684 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 10:52:00.068506 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 10:52:00.070952 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 10:52:00.074527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 10:52:00.081048 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5200 10:52:00.084336 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5201 10:52:00.087697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 10:52:00.094497 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 10:52:00.097902 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 10:52:00.101184 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 10:52:00.107507 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 10:52:00.110960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 10:52:00.114783 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 10:52:00.120777 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 10:52:00.124487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 10:52:00.127323 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 10:52:00.134041 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 10:52:00.137429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 10:52:00.141276 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 10:52:00.147404 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5215 10:52:00.150907 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5216 10:52:00.154165 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5217 10:52:00.157632 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 10:52:00.160415 Total UI for P1: 0, mck2ui 16
5219 10:52:00.164147 best dqsien dly found for B0: ( 1, 3, 0)
5220 10:52:00.167417 Total UI for P1: 0, mck2ui 16
5221 10:52:00.170473 best dqsien dly found for B1: ( 1, 3, 0)
5222 10:52:00.173905 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5223 10:52:00.177393 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5224 10:52:00.180339
5225 10:52:00.183792 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5226 10:52:00.187250 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5227 10:52:00.190386 [Gating] SW calibration Done
5228 10:52:00.190467 ==
5229 10:52:00.193953 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 10:52:00.197300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 10:52:00.197383 ==
5232 10:52:00.197447 RX Vref Scan: 0
5233 10:52:00.197507
5234 10:52:00.200445 RX Vref 0 -> 0, step: 1
5235 10:52:00.200526
5236 10:52:00.203939 RX Delay -80 -> 252, step: 8
5237 10:52:00.207151 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5238 10:52:00.210492 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5239 10:52:00.214051 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5240 10:52:00.220455 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5241 10:52:00.223592 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5242 10:52:00.227115 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5243 10:52:00.230803 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5244 10:52:00.234267 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5245 10:52:00.240730 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5246 10:52:00.243398 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5247 10:52:00.246975 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5248 10:52:00.250298 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5249 10:52:00.253893 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5250 10:52:00.256826 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5251 10:52:00.263406 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5252 10:52:00.267341 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5253 10:52:00.267461 ==
5254 10:52:00.269941 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 10:52:00.273507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 10:52:00.273588 ==
5257 10:52:00.276869 DQS Delay:
5258 10:52:00.276960 DQS0 = 0, DQS1 = 0
5259 10:52:00.277024 DQM Delay:
5260 10:52:00.279827 DQM0 = 99, DQM1 = 87
5261 10:52:00.279907 DQ Delay:
5262 10:52:00.283610 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5263 10:52:00.286531 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5264 10:52:00.289984 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5265 10:52:00.293425 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5266 10:52:00.293506
5267 10:52:00.293570
5268 10:52:00.293630 ==
5269 10:52:00.296967 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 10:52:00.303439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 10:52:00.303521 ==
5272 10:52:00.303586
5273 10:52:00.303644
5274 10:52:00.303700 TX Vref Scan disable
5275 10:52:00.306822 == TX Byte 0 ==
5276 10:52:00.310243 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5277 10:52:00.317213 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5278 10:52:00.317294 == TX Byte 1 ==
5279 10:52:00.320080 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5280 10:52:00.326784 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5281 10:52:00.326866 ==
5282 10:52:00.330399 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 10:52:00.333885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 10:52:00.333966 ==
5285 10:52:00.334030
5286 10:52:00.334092
5287 10:52:00.336639 TX Vref Scan disable
5288 10:52:00.340117 == TX Byte 0 ==
5289 10:52:00.343604 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5290 10:52:00.346479 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5291 10:52:00.350030 == TX Byte 1 ==
5292 10:52:00.353469 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5293 10:52:00.356889 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5294 10:52:00.356970
5295 10:52:00.357034 [DATLAT]
5296 10:52:00.359753 Freq=933, CH0 RK0
5297 10:52:00.359835
5298 10:52:00.363241 DATLAT Default: 0xd
5299 10:52:00.363322 0, 0xFFFF, sum = 0
5300 10:52:00.366678 1, 0xFFFF, sum = 0
5301 10:52:00.366760 2, 0xFFFF, sum = 0
5302 10:52:00.370171 3, 0xFFFF, sum = 0
5303 10:52:00.370254 4, 0xFFFF, sum = 0
5304 10:52:00.373276 5, 0xFFFF, sum = 0
5305 10:52:00.373359 6, 0xFFFF, sum = 0
5306 10:52:00.376613 7, 0xFFFF, sum = 0
5307 10:52:00.376696 8, 0xFFFF, sum = 0
5308 10:52:00.379947 9, 0xFFFF, sum = 0
5309 10:52:00.380047 10, 0x0, sum = 1
5310 10:52:00.383280 11, 0x0, sum = 2
5311 10:52:00.383421 12, 0x0, sum = 3
5312 10:52:00.386782 13, 0x0, sum = 4
5313 10:52:00.386863 best_step = 11
5314 10:52:00.386926
5315 10:52:00.386984 ==
5316 10:52:00.389596 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 10:52:00.393013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 10:52:00.393094 ==
5319 10:52:00.396491 RX Vref Scan: 1
5320 10:52:00.396571
5321 10:52:00.399827 RX Vref 0 -> 0, step: 1
5322 10:52:00.399912
5323 10:52:00.399976 RX Delay -61 -> 252, step: 4
5324 10:52:00.400035
5325 10:52:00.402813 Set Vref, RX VrefLevel [Byte0]: 51
5326 10:52:00.406511 [Byte1]: 51
5327 10:52:00.411246
5328 10:52:00.411342 Final RX Vref Byte 0 = 51 to rank0
5329 10:52:00.414418 Final RX Vref Byte 1 = 51 to rank0
5330 10:52:00.418277 Final RX Vref Byte 0 = 51 to rank1
5331 10:52:00.420964 Final RX Vref Byte 1 = 51 to rank1==
5332 10:52:00.424461 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 10:52:00.431492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 10:52:00.431573 ==
5335 10:52:00.431638 DQS Delay:
5336 10:52:00.431696 DQS0 = 0, DQS1 = 0
5337 10:52:00.434691 DQM Delay:
5338 10:52:00.434772 DQM0 = 97, DQM1 = 89
5339 10:52:00.437929 DQ Delay:
5340 10:52:00.441358 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5341 10:52:00.444835 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5342 10:52:00.447691 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5343 10:52:00.451329 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5344 10:52:00.451450
5345 10:52:00.451514
5346 10:52:00.457612 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5347 10:52:00.461105 CH0 RK0: MR19=505, MR18=1400
5348 10:52:00.467884 CH0_RK0: MR19=0x505, MR18=0x1400, DQSOSC=415, MR23=63, INC=62, DEC=41
5349 10:52:00.467982
5350 10:52:00.471327 ----->DramcWriteLeveling(PI) begin...
5351 10:52:00.471433 ==
5352 10:52:00.474142 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 10:52:00.477819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 10:52:00.477916 ==
5355 10:52:00.481265 Write leveling (Byte 0): 31 => 31
5356 10:52:00.484475 Write leveling (Byte 1): 29 => 29
5357 10:52:00.487732 DramcWriteLeveling(PI) end<-----
5358 10:52:00.487809
5359 10:52:00.487871 ==
5360 10:52:00.490845 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 10:52:00.494310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 10:52:00.494390 ==
5363 10:52:00.497849 [Gating] SW mode calibration
5364 10:52:00.504278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 10:52:00.510946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5366 10:52:00.514312 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5367 10:52:00.520792 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5368 10:52:00.524413 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 10:52:00.527291 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 10:52:00.533969 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 10:52:00.537431 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 10:52:00.540915 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5373 10:52:00.543921 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
5374 10:52:00.550960 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5375 10:52:00.553781 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 10:52:00.557360 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 10:52:00.563904 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 10:52:00.567228 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 10:52:00.570568 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 10:52:00.577340 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 10:52:00.580224 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5382 10:52:00.583852 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5383 10:52:00.590525 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 10:52:00.593517 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 10:52:00.597229 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 10:52:00.603573 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 10:52:00.607039 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 10:52:00.610553 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 10:52:00.617127 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5390 10:52:00.620060 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5391 10:52:00.623265 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 10:52:00.629988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 10:52:00.633693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 10:52:00.636928 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 10:52:00.643469 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 10:52:00.646951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 10:52:00.650365 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 10:52:00.656735 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 10:52:00.660486 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 10:52:00.663264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 10:52:00.670294 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 10:52:00.673249 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 10:52:00.676561 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 10:52:00.680564 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 10:52:00.686915 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5406 10:52:00.690407 Total UI for P1: 0, mck2ui 16
5407 10:52:00.693647 best dqsien dly found for B0: ( 1, 2, 26)
5408 10:52:00.696902 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5409 10:52:00.699765 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5410 10:52:00.706972 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 10:52:00.709920 Total UI for P1: 0, mck2ui 16
5412 10:52:00.713310 best dqsien dly found for B1: ( 1, 3, 0)
5413 10:52:00.716784 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5414 10:52:00.720058 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5415 10:52:00.720139
5416 10:52:00.723576 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5417 10:52:00.726348 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5418 10:52:00.729755 [Gating] SW calibration Done
5419 10:52:00.729837 ==
5420 10:52:00.733337 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 10:52:00.736640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 10:52:00.736722 ==
5423 10:52:00.739829 RX Vref Scan: 0
5424 10:52:00.739909
5425 10:52:00.739974 RX Vref 0 -> 0, step: 1
5426 10:52:00.740032
5427 10:52:00.743306 RX Delay -80 -> 252, step: 8
5428 10:52:00.749681 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5429 10:52:00.753056 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5430 10:52:00.756495 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5431 10:52:00.759494 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5432 10:52:00.763144 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5433 10:52:00.766426 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5434 10:52:00.769996 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5435 10:52:00.776197 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5436 10:52:00.779575 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5437 10:52:00.783053 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5438 10:52:00.786509 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5439 10:52:00.789364 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5440 10:52:00.796370 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5441 10:52:00.799635 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5442 10:52:00.802952 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5443 10:52:00.806228 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5444 10:52:00.806310 ==
5445 10:52:00.809471 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 10:52:00.812905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 10:52:00.812987 ==
5448 10:52:00.816375 DQS Delay:
5449 10:52:00.816459 DQS0 = 0, DQS1 = 0
5450 10:52:00.819231 DQM Delay:
5451 10:52:00.819311 DQM0 = 96, DQM1 = 88
5452 10:52:00.819417 DQ Delay:
5453 10:52:00.822670 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5454 10:52:00.826147 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5455 10:52:00.829491 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5456 10:52:00.832652 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5457 10:52:00.832734
5458 10:52:00.832797
5459 10:52:00.836169 ==
5460 10:52:00.839511 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 10:52:00.842849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 10:52:00.842930 ==
5463 10:52:00.842994
5464 10:52:00.843051
5465 10:52:00.845853 TX Vref Scan disable
5466 10:52:00.845933 == TX Byte 0 ==
5467 10:52:00.852369 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5468 10:52:00.855895 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5469 10:52:00.855976 == TX Byte 1 ==
5470 10:52:00.862623 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5471 10:52:00.865905 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5472 10:52:00.865986 ==
5473 10:52:00.868879 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 10:52:00.872598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 10:52:00.872680 ==
5476 10:52:00.872743
5477 10:52:00.872801
5478 10:52:00.875979 TX Vref Scan disable
5479 10:52:00.878755 == TX Byte 0 ==
5480 10:52:00.882295 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5481 10:52:00.885541 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5482 10:52:00.888975 == TX Byte 1 ==
5483 10:52:00.892358 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5484 10:52:00.895601 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5485 10:52:00.895682
5486 10:52:00.898814 [DATLAT]
5487 10:52:00.898895 Freq=933, CH0 RK1
5488 10:52:00.898959
5489 10:52:00.902603 DATLAT Default: 0xb
5490 10:52:00.902683 0, 0xFFFF, sum = 0
5491 10:52:00.906274 1, 0xFFFF, sum = 0
5492 10:52:00.906356 2, 0xFFFF, sum = 0
5493 10:52:00.908820 3, 0xFFFF, sum = 0
5494 10:52:00.908902 4, 0xFFFF, sum = 0
5495 10:52:00.912220 5, 0xFFFF, sum = 0
5496 10:52:00.912302 6, 0xFFFF, sum = 0
5497 10:52:00.915849 7, 0xFFFF, sum = 0
5498 10:52:00.915930 8, 0xFFFF, sum = 0
5499 10:52:00.918823 9, 0xFFFF, sum = 0
5500 10:52:00.918905 10, 0x0, sum = 1
5501 10:52:00.922129 11, 0x0, sum = 2
5502 10:52:00.922211 12, 0x0, sum = 3
5503 10:52:00.925551 13, 0x0, sum = 4
5504 10:52:00.925678 best_step = 11
5505 10:52:00.925770
5506 10:52:00.925833 ==
5507 10:52:00.928829 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 10:52:00.935684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 10:52:00.935765 ==
5510 10:52:00.935829 RX Vref Scan: 0
5511 10:52:00.935887
5512 10:52:00.938618 RX Vref 0 -> 0, step: 1
5513 10:52:00.938698
5514 10:52:00.942245 RX Delay -61 -> 252, step: 4
5515 10:52:00.945681 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5516 10:52:00.948954 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5517 10:52:00.952217 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5518 10:52:00.958857 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5519 10:52:00.961886 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5520 10:52:00.965331 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5521 10:52:00.968457 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5522 10:52:00.972007 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5523 10:52:00.978489 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5524 10:52:00.981789 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5525 10:52:00.985305 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5526 10:52:00.988796 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5527 10:52:00.991840 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5528 10:52:00.995239 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5529 10:52:01.001782 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5530 10:52:01.004877 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5531 10:52:01.004959 ==
5532 10:52:01.008486 Dram Type= 6, Freq= 0, CH_0, rank 1
5533 10:52:01.011868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 10:52:01.011951 ==
5535 10:52:01.014989 DQS Delay:
5536 10:52:01.015070 DQS0 = 0, DQS1 = 0
5537 10:52:01.015135 DQM Delay:
5538 10:52:01.018612 DQM0 = 95, DQM1 = 87
5539 10:52:01.018694 DQ Delay:
5540 10:52:01.021779 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5541 10:52:01.024710 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5542 10:52:01.028460 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5543 10:52:01.031397 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5544 10:52:01.031479
5545 10:52:01.031543
5546 10:52:01.041484 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5547 10:52:01.045023 CH0 RK1: MR19=505, MR18=1B08
5548 10:52:01.047992 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5549 10:52:01.051372 [RxdqsGatingPostProcess] freq 933
5550 10:52:01.058347 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5551 10:52:01.061333 best DQS0 dly(2T, 0.5T) = (0, 11)
5552 10:52:01.064903 best DQS1 dly(2T, 0.5T) = (0, 11)
5553 10:52:01.067898 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5554 10:52:01.071377 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5555 10:52:01.074887 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 10:52:01.078022 best DQS1 dly(2T, 0.5T) = (0, 11)
5557 10:52:01.081453 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 10:52:01.084361 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5559 10:52:01.084443 Pre-setting of DQS Precalculation
5560 10:52:01.091241 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5561 10:52:01.091322 ==
5562 10:52:01.094257 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 10:52:01.097961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 10:52:01.098043 ==
5565 10:52:01.104606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 10:52:01.111115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5567 10:52:01.114589 [CA 0] Center 36 (6~67) winsize 62
5568 10:52:01.117486 [CA 1] Center 36 (6~67) winsize 62
5569 10:52:01.120979 [CA 2] Center 34 (4~64) winsize 61
5570 10:52:01.124095 [CA 3] Center 33 (3~64) winsize 62
5571 10:52:01.127463 [CA 4] Center 34 (4~64) winsize 61
5572 10:52:01.130835 [CA 5] Center 33 (3~63) winsize 61
5573 10:52:01.130915
5574 10:52:01.134692 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5575 10:52:01.134773
5576 10:52:01.137552 [CATrainingPosCal] consider 1 rank data
5577 10:52:01.140927 u2DelayCellTimex100 = 270/100 ps
5578 10:52:01.144335 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 10:52:01.148038 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 10:52:01.151177 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 10:52:01.153924 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 10:52:01.157293 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 10:52:01.160718 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5584 10:52:01.160800
5585 10:52:01.167409 CA PerBit enable=1, Macro0, CA PI delay=33
5586 10:52:01.167491
5587 10:52:01.170973 [CBTSetCACLKResult] CA Dly = 33
5588 10:52:01.171053 CS Dly: 4 (0~35)
5589 10:52:01.171117 ==
5590 10:52:01.173918 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 10:52:01.177577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 10:52:01.177659 ==
5593 10:52:01.184212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 10:52:01.190980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5595 10:52:01.193689 [CA 0] Center 36 (6~67) winsize 62
5596 10:52:01.197247 [CA 1] Center 36 (6~67) winsize 62
5597 10:52:01.200721 [CA 2] Center 34 (4~64) winsize 61
5598 10:52:01.204019 [CA 3] Center 33 (3~64) winsize 62
5599 10:52:01.207236 [CA 4] Center 34 (4~65) winsize 62
5600 10:52:01.210237 [CA 5] Center 33 (3~63) winsize 61
5601 10:52:01.210319
5602 10:52:01.213779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5603 10:52:01.213860
5604 10:52:01.217314 [CATrainingPosCal] consider 2 rank data
5605 10:52:01.220679 u2DelayCellTimex100 = 270/100 ps
5606 10:52:01.223639 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 10:52:01.227156 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 10:52:01.230414 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 10:52:01.233568 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 10:52:01.237026 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 10:52:01.244130 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5612 10:52:01.244214
5613 10:52:01.246906 CA PerBit enable=1, Macro0, CA PI delay=33
5614 10:52:01.246987
5615 10:52:01.250364 [CBTSetCACLKResult] CA Dly = 33
5616 10:52:01.250445 CS Dly: 5 (0~38)
5617 10:52:01.250509
5618 10:52:01.254270 ----->DramcWriteLeveling(PI) begin...
5619 10:52:01.254351 ==
5620 10:52:01.257001 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 10:52:01.263770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 10:52:01.263852 ==
5623 10:52:01.267268 Write leveling (Byte 0): 28 => 28
5624 10:52:01.267370 Write leveling (Byte 1): 29 => 29
5625 10:52:01.270354 DramcWriteLeveling(PI) end<-----
5626 10:52:01.270513
5627 10:52:01.273365 ==
5628 10:52:01.273445 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 10:52:01.280024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 10:52:01.280135 ==
5631 10:52:01.283524 [Gating] SW mode calibration
5632 10:52:01.289937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5633 10:52:01.293322 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5634 10:52:01.300057 0 14 0 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (0 0)
5635 10:52:01.303264 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 10:52:01.306578 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 10:52:01.313247 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 10:52:01.316904 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 10:52:01.320308 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 10:52:01.326782 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5641 10:52:01.330264 0 14 28 | B1->B0 | 3131 3030 | 1 1 | (0 0) (1 0)
5642 10:52:01.333316 0 15 0 | B1->B0 | 2626 2a2a | 0 0 | (1 1) (1 1)
5643 10:52:01.339701 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 10:52:01.343215 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 10:52:01.346606 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 10:52:01.349953 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 10:52:01.356764 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 10:52:01.359602 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 10:52:01.363166 0 15 28 | B1->B0 | 3535 2d2d | 0 0 | (0 0) (0 0)
5650 10:52:01.369682 1 0 0 | B1->B0 | 4343 4040 | 0 0 | (0 0) (0 0)
5651 10:52:01.373389 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 10:52:01.376466 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 10:52:01.382920 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 10:52:01.386508 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 10:52:01.389544 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 10:52:01.396586 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 10:52:01.400051 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5658 10:52:01.402847 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 10:52:01.409749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 10:52:01.412720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 10:52:01.415904 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 10:52:01.422769 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 10:52:01.425750 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 10:52:01.429077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 10:52:01.436303 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 10:52:01.439140 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 10:52:01.442631 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 10:52:01.449243 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 10:52:01.452589 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 10:52:01.456098 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 10:52:01.462324 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 10:52:01.465897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 10:52:01.469344 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5674 10:52:01.475891 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 10:52:01.479537 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 10:52:01.482391 Total UI for P1: 0, mck2ui 16
5677 10:52:01.486077 best dqsien dly found for B0: ( 1, 2, 30)
5678 10:52:01.488908 Total UI for P1: 0, mck2ui 16
5679 10:52:01.492587 best dqsien dly found for B1: ( 1, 2, 30)
5680 10:52:01.496128 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5681 10:52:01.499120 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5682 10:52:01.499201
5683 10:52:01.502681 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5684 10:52:01.505846 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5685 10:52:01.509352 [Gating] SW calibration Done
5686 10:52:01.509433 ==
5687 10:52:01.512722 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 10:52:01.515972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 10:52:01.516052 ==
5690 10:52:01.518825 RX Vref Scan: 0
5691 10:52:01.518905
5692 10:52:01.522251 RX Vref 0 -> 0, step: 1
5693 10:52:01.522332
5694 10:52:01.522396 RX Delay -80 -> 252, step: 8
5695 10:52:01.529251 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5696 10:52:01.532441 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5697 10:52:01.535827 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5698 10:52:01.538888 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5699 10:52:01.542365 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5700 10:52:01.546113 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5701 10:52:01.552223 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5702 10:52:01.555633 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5703 10:52:01.559007 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5704 10:52:01.562628 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5705 10:52:01.565424 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5706 10:52:01.571927 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5707 10:52:01.575829 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5708 10:52:01.578775 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5709 10:52:01.582069 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5710 10:52:01.585649 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5711 10:52:01.585730 ==
5712 10:52:01.589253 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 10:52:01.592339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 10:52:01.595704 ==
5715 10:52:01.595784 DQS Delay:
5716 10:52:01.595848 DQS0 = 0, DQS1 = 0
5717 10:52:01.598605 DQM Delay:
5718 10:52:01.598686 DQM0 = 96, DQM1 = 88
5719 10:52:01.602233 DQ Delay:
5720 10:52:01.605591 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5721 10:52:01.608983 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5722 10:52:01.612082 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5723 10:52:01.615598 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5724 10:52:01.615679
5725 10:52:01.615742
5726 10:52:01.615800 ==
5727 10:52:01.619191 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 10:52:01.621958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 10:52:01.622040 ==
5730 10:52:01.622104
5731 10:52:01.622162
5732 10:52:01.625265 TX Vref Scan disable
5733 10:52:01.625346 == TX Byte 0 ==
5734 10:52:01.631812 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5735 10:52:01.635212 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5736 10:52:01.635293 == TX Byte 1 ==
5737 10:52:01.642371 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5738 10:52:01.645193 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5739 10:52:01.645275 ==
5740 10:52:01.648662 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 10:52:01.652036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 10:52:01.652117 ==
5743 10:52:01.652181
5744 10:52:01.652239
5745 10:52:01.655246 TX Vref Scan disable
5746 10:52:01.659116 == TX Byte 0 ==
5747 10:52:01.661772 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5748 10:52:01.665131 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5749 10:52:01.668668 == TX Byte 1 ==
5750 10:52:01.672389 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 10:52:01.675238 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 10:52:01.675344
5753 10:52:01.678654 [DATLAT]
5754 10:52:01.678734 Freq=933, CH1 RK0
5755 10:52:01.678798
5756 10:52:01.681919 DATLAT Default: 0xd
5757 10:52:01.682000 0, 0xFFFF, sum = 0
5758 10:52:01.685189 1, 0xFFFF, sum = 0
5759 10:52:01.685272 2, 0xFFFF, sum = 0
5760 10:52:01.688972 3, 0xFFFF, sum = 0
5761 10:52:01.689055 4, 0xFFFF, sum = 0
5762 10:52:01.691748 5, 0xFFFF, sum = 0
5763 10:52:01.691830 6, 0xFFFF, sum = 0
5764 10:52:01.695241 7, 0xFFFF, sum = 0
5765 10:52:01.695356 8, 0xFFFF, sum = 0
5766 10:52:01.698791 9, 0xFFFF, sum = 0
5767 10:52:01.698874 10, 0x0, sum = 1
5768 10:52:01.701949 11, 0x0, sum = 2
5769 10:52:01.702032 12, 0x0, sum = 3
5770 10:52:01.705301 13, 0x0, sum = 4
5771 10:52:01.705382 best_step = 11
5772 10:52:01.705446
5773 10:52:01.705503 ==
5774 10:52:01.708474 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 10:52:01.715177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 10:52:01.715258 ==
5777 10:52:01.715324 RX Vref Scan: 1
5778 10:52:01.715424
5779 10:52:01.718444 RX Vref 0 -> 0, step: 1
5780 10:52:01.718525
5781 10:52:01.721432 RX Delay -61 -> 252, step: 4
5782 10:52:01.721514
5783 10:52:01.725379 Set Vref, RX VrefLevel [Byte0]: 54
5784 10:52:01.728245 [Byte1]: 53
5785 10:52:01.728326
5786 10:52:01.731784 Final RX Vref Byte 0 = 54 to rank0
5787 10:52:01.734677 Final RX Vref Byte 1 = 53 to rank0
5788 10:52:01.738053 Final RX Vref Byte 0 = 54 to rank1
5789 10:52:01.741852 Final RX Vref Byte 1 = 53 to rank1==
5790 10:52:01.744643 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 10:52:01.748147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 10:52:01.748229 ==
5793 10:52:01.751878 DQS Delay:
5794 10:52:01.751958 DQS0 = 0, DQS1 = 0
5795 10:52:01.752039 DQM Delay:
5796 10:52:01.755067 DQM0 = 98, DQM1 = 89
5797 10:52:01.755147 DQ Delay:
5798 10:52:01.758379 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5799 10:52:01.761674 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5800 10:52:01.765119 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =88
5801 10:52:01.768331 DQ12 =98, DQ13 =98, DQ14 =94, DQ15 =96
5802 10:52:01.768411
5803 10:52:01.768473
5804 10:52:01.778270 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5805 10:52:01.781445 CH1 RK0: MR19=504, MR18=12EE
5806 10:52:01.787860 CH1_RK0: MR19=0x504, MR18=0x12EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5807 10:52:01.787942
5808 10:52:01.791327 ----->DramcWriteLeveling(PI) begin...
5809 10:52:01.791418 ==
5810 10:52:01.794795 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 10:52:01.797825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 10:52:01.797907 ==
5813 10:52:01.801671 Write leveling (Byte 0): 26 => 26
5814 10:52:01.804305 Write leveling (Byte 1): 30 => 30
5815 10:52:01.807779 DramcWriteLeveling(PI) end<-----
5816 10:52:01.807859
5817 10:52:01.807923 ==
5818 10:52:01.811225 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 10:52:01.814202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 10:52:01.814283 ==
5821 10:52:01.817736 [Gating] SW mode calibration
5822 10:52:01.824414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 10:52:01.831048 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 10:52:01.834611 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5825 10:52:01.837702 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 10:52:01.844373 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 10:52:01.847457 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 10:52:01.850990 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 10:52:01.857472 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5830 10:52:01.860882 0 14 24 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)
5831 10:52:01.864272 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5832 10:52:01.870528 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 10:52:01.874038 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5834 10:52:01.877287 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 10:52:01.883804 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 10:52:01.887216 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 10:52:01.890921 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5838 10:52:01.897448 0 15 24 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
5839 10:52:01.901041 0 15 28 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
5840 10:52:01.904206 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 10:52:01.910897 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 10:52:01.914251 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 10:52:01.917700 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 10:52:01.920745 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 10:52:01.927703 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 10:52:01.930521 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5847 10:52:01.933742 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5848 10:52:01.940393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 10:52:01.944002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 10:52:01.947282 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 10:52:01.953836 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 10:52:01.956776 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 10:52:01.960369 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 10:52:01.966845 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 10:52:01.970286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 10:52:01.973582 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 10:52:01.980244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 10:52:01.983735 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 10:52:01.987522 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 10:52:01.994416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 10:52:01.996846 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 10:52:02.000755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5863 10:52:02.007039 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5864 10:52:02.007120 Total UI for P1: 0, mck2ui 16
5865 10:52:02.013625 best dqsien dly found for B0: ( 1, 2, 24)
5866 10:52:02.016743 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5867 10:52:02.020351 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 10:52:02.023713 Total UI for P1: 0, mck2ui 16
5869 10:52:02.026730 best dqsien dly found for B1: ( 1, 2, 30)
5870 10:52:02.030542 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5871 10:52:02.033545 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5872 10:52:02.033627
5873 10:52:02.036673 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 10:52:02.043639 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5875 10:52:02.043747 [Gating] SW calibration Done
5876 10:52:02.046686 ==
5877 10:52:02.046766 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 10:52:02.053927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 10:52:02.054008 ==
5880 10:52:02.054072 RX Vref Scan: 0
5881 10:52:02.054130
5882 10:52:02.056808 RX Vref 0 -> 0, step: 1
5883 10:52:02.056888
5884 10:52:02.060243 RX Delay -80 -> 252, step: 8
5885 10:52:02.063232 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5886 10:52:02.066694 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5887 10:52:02.070044 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5888 10:52:02.076815 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5889 10:52:02.079655 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5890 10:52:02.083087 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5891 10:52:02.086333 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5892 10:52:02.089484 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5893 10:52:02.092757 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5894 10:52:02.099518 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5895 10:52:02.103141 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5896 10:52:02.106173 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5897 10:52:02.109498 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5898 10:52:02.113084 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5899 10:52:02.116387 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5900 10:52:02.122825 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5901 10:52:02.122908 ==
5902 10:52:02.126158 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 10:52:02.129571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 10:52:02.129654 ==
5905 10:52:02.129719 DQS Delay:
5906 10:52:02.133099 DQS0 = 0, DQS1 = 0
5907 10:52:02.133180 DQM Delay:
5908 10:52:02.136642 DQM0 = 94, DQM1 = 89
5909 10:52:02.136723 DQ Delay:
5910 10:52:02.139490 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5911 10:52:02.142725 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5912 10:52:02.146555 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5913 10:52:02.149199 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5914 10:52:02.149280
5915 10:52:02.149343
5916 10:52:02.149401 ==
5917 10:52:02.152770 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 10:52:02.155847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 10:52:02.159586 ==
5920 10:52:02.159667
5921 10:52:02.159730
5922 10:52:02.159787 TX Vref Scan disable
5923 10:52:02.162792 == TX Byte 0 ==
5924 10:52:02.165712 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 10:52:02.169357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 10:52:02.172709 == TX Byte 1 ==
5927 10:52:02.176330 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5928 10:52:02.179265 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5929 10:52:02.182541 ==
5930 10:52:02.182622 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 10:52:02.189267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 10:52:02.189348 ==
5933 10:52:02.189412
5934 10:52:02.189470
5935 10:52:02.192318 TX Vref Scan disable
5936 10:52:02.192399 == TX Byte 0 ==
5937 10:52:02.199191 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5938 10:52:02.202438 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5939 10:52:02.202520 == TX Byte 1 ==
5940 10:52:02.208949 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5941 10:52:02.212457 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5942 10:52:02.212539
5943 10:52:02.212601 [DATLAT]
5944 10:52:02.215490 Freq=933, CH1 RK1
5945 10:52:02.215572
5946 10:52:02.215635 DATLAT Default: 0xb
5947 10:52:02.219023 0, 0xFFFF, sum = 0
5948 10:52:02.219104 1, 0xFFFF, sum = 0
5949 10:52:02.222756 2, 0xFFFF, sum = 0
5950 10:52:02.222838 3, 0xFFFF, sum = 0
5951 10:52:02.225700 4, 0xFFFF, sum = 0
5952 10:52:02.225782 5, 0xFFFF, sum = 0
5953 10:52:02.229023 6, 0xFFFF, sum = 0
5954 10:52:02.229105 7, 0xFFFF, sum = 0
5955 10:52:02.233076 8, 0xFFFF, sum = 0
5956 10:52:02.233161 9, 0xFFFF, sum = 0
5957 10:52:02.235587 10, 0x0, sum = 1
5958 10:52:02.235669 11, 0x0, sum = 2
5959 10:52:02.239208 12, 0x0, sum = 3
5960 10:52:02.239289 13, 0x0, sum = 4
5961 10:52:02.242668 best_step = 11
5962 10:52:02.242749
5963 10:52:02.242812 ==
5964 10:52:02.245828 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 10:52:02.249134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 10:52:02.249215 ==
5967 10:52:02.252214 RX Vref Scan: 0
5968 10:52:02.252294
5969 10:52:02.252358 RX Vref 0 -> 0, step: 1
5970 10:52:02.252417
5971 10:52:02.255764 RX Delay -61 -> 252, step: 4
5972 10:52:02.262805 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5973 10:52:02.265799 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5974 10:52:02.269295 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5975 10:52:02.272982 iDelay=199, Bit 3, Center 90 (-1 ~ 182) 184
5976 10:52:02.275945 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5977 10:52:02.282815 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5978 10:52:02.286086 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5979 10:52:02.288954 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5980 10:52:02.292787 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5981 10:52:02.295691 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5982 10:52:02.299698 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5983 10:52:02.305693 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5984 10:52:02.309147 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5985 10:52:02.312689 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5986 10:52:02.315556 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5987 10:52:02.319155 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5988 10:52:02.319237 ==
5989 10:52:02.322560 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 10:52:02.328904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 10:52:02.328986 ==
5992 10:52:02.329048 DQS Delay:
5993 10:52:02.332260 DQS0 = 0, DQS1 = 0
5994 10:52:02.332341 DQM Delay:
5995 10:52:02.332405 DQM0 = 94, DQM1 = 90
5996 10:52:02.335738 DQ Delay:
5997 10:52:02.338833 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =90
5998 10:52:02.342168 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =90
5999 10:52:02.345639 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =82
6000 10:52:02.348640 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6001 10:52:02.348721
6002 10:52:02.348809
6003 10:52:02.355650 [DQSOSCAuto] RK1, (LSB)MR18= 0xd17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6004 10:52:02.358517 CH1 RK1: MR19=505, MR18=D17
6005 10:52:02.365328 CH1_RK1: MR19=0x505, MR18=0xD17, DQSOSC=414, MR23=63, INC=63, DEC=42
6006 10:52:02.368841 [RxdqsGatingPostProcess] freq 933
6007 10:52:02.371789 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 10:52:02.375239 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 10:52:02.378955 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 10:52:02.381711 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 10:52:02.385163 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 10:52:02.388476 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 10:52:02.391953 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 10:52:02.395203 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 10:52:02.398518 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 10:52:02.401983 Pre-setting of DQS Precalculation
6017 10:52:02.405441 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 10:52:02.415074 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 10:52:02.422229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 10:52:02.422313
6021 10:52:02.422377
6022 10:52:02.424994 [Calibration Summary] 1866 Mbps
6023 10:52:02.425077 CH 0, Rank 0
6024 10:52:02.428590 SW Impedance : PASS
6025 10:52:02.428671 DUTY Scan : NO K
6026 10:52:02.431943 ZQ Calibration : PASS
6027 10:52:02.434864 Jitter Meter : NO K
6028 10:52:02.434945 CBT Training : PASS
6029 10:52:02.438494 Write leveling : PASS
6030 10:52:02.441352 RX DQS gating : PASS
6031 10:52:02.441432 RX DQ/DQS(RDDQC) : PASS
6032 10:52:02.445146 TX DQ/DQS : PASS
6033 10:52:02.448047 RX DATLAT : PASS
6034 10:52:02.448129 RX DQ/DQS(Engine): PASS
6035 10:52:02.451738 TX OE : NO K
6036 10:52:02.451819 All Pass.
6037 10:52:02.451884
6038 10:52:02.454869 CH 0, Rank 1
6039 10:52:02.454950 SW Impedance : PASS
6040 10:52:02.458381 DUTY Scan : NO K
6041 10:52:02.458492 ZQ Calibration : PASS
6042 10:52:02.461659 Jitter Meter : NO K
6043 10:52:02.465111 CBT Training : PASS
6044 10:52:02.465192 Write leveling : PASS
6045 10:52:02.468505 RX DQS gating : PASS
6046 10:52:02.471643 RX DQ/DQS(RDDQC) : PASS
6047 10:52:02.471724 TX DQ/DQS : PASS
6048 10:52:02.474885 RX DATLAT : PASS
6049 10:52:02.478459 RX DQ/DQS(Engine): PASS
6050 10:52:02.478540 TX OE : NO K
6051 10:52:02.481479 All Pass.
6052 10:52:02.481560
6053 10:52:02.481623 CH 1, Rank 0
6054 10:52:02.484990 SW Impedance : PASS
6055 10:52:02.485072 DUTY Scan : NO K
6056 10:52:02.488353 ZQ Calibration : PASS
6057 10:52:02.491233 Jitter Meter : NO K
6058 10:52:02.491342 CBT Training : PASS
6059 10:52:02.494680 Write leveling : PASS
6060 10:52:02.498430 RX DQS gating : PASS
6061 10:52:02.498510 RX DQ/DQS(RDDQC) : PASS
6062 10:52:02.501672 TX DQ/DQS : PASS
6063 10:52:02.504533 RX DATLAT : PASS
6064 10:52:02.504614 RX DQ/DQS(Engine): PASS
6065 10:52:02.507952 TX OE : NO K
6066 10:52:02.508033 All Pass.
6067 10:52:02.508097
6068 10:52:02.511222 CH 1, Rank 1
6069 10:52:02.511305 SW Impedance : PASS
6070 10:52:02.514246 DUTY Scan : NO K
6071 10:52:02.518207 ZQ Calibration : PASS
6072 10:52:02.518289 Jitter Meter : NO K
6073 10:52:02.521063 CBT Training : PASS
6074 10:52:02.521143 Write leveling : PASS
6075 10:52:02.524166 RX DQS gating : PASS
6076 10:52:02.527648 RX DQ/DQS(RDDQC) : PASS
6077 10:52:02.527728 TX DQ/DQS : PASS
6078 10:52:02.530957 RX DATLAT : PASS
6079 10:52:02.534492 RX DQ/DQS(Engine): PASS
6080 10:52:02.534573 TX OE : NO K
6081 10:52:02.537503 All Pass.
6082 10:52:02.537583
6083 10:52:02.537647 DramC Write-DBI off
6084 10:52:02.541039 PER_BANK_REFRESH: Hybrid Mode
6085 10:52:02.544602 TX_TRACKING: ON
6086 10:52:02.550760 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 10:52:02.554308 [FAST_K] Save calibration result to emmc
6088 10:52:02.557618 dramc_set_vcore_voltage set vcore to 650000
6089 10:52:02.560747 Read voltage for 400, 6
6090 10:52:02.560828 Vio18 = 0
6091 10:52:02.564197 Vcore = 650000
6092 10:52:02.564278 Vdram = 0
6093 10:52:02.564342 Vddq = 0
6094 10:52:02.567358 Vmddr = 0
6095 10:52:02.570736 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 10:52:02.577761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 10:52:02.577860 MEM_TYPE=3, freq_sel=20
6098 10:52:02.580642 sv_algorithm_assistance_LP4_800
6099 10:52:02.587234 ============ PULL DRAM RESETB DOWN ============
6100 10:52:02.591095 ========== PULL DRAM RESETB DOWN end =========
6101 10:52:02.593973 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 10:52:02.597416 ===================================
6103 10:52:02.600790 LPDDR4 DRAM CONFIGURATION
6104 10:52:02.603980 ===================================
6105 10:52:02.606871 EX_ROW_EN[0] = 0x0
6106 10:52:02.606952 EX_ROW_EN[1] = 0x0
6107 10:52:02.610816 LP4Y_EN = 0x0
6108 10:52:02.610897 WORK_FSP = 0x0
6109 10:52:02.613874 WL = 0x2
6110 10:52:02.613955 RL = 0x2
6111 10:52:02.617292 BL = 0x2
6112 10:52:02.617372 RPST = 0x0
6113 10:52:02.620551 RD_PRE = 0x0
6114 10:52:02.620631 WR_PRE = 0x1
6115 10:52:02.623940 WR_PST = 0x0
6116 10:52:02.624021 DBI_WR = 0x0
6117 10:52:02.626838 DBI_RD = 0x0
6118 10:52:02.626918 OTF = 0x1
6119 10:52:02.630210 ===================================
6120 10:52:02.633847 ===================================
6121 10:52:02.636755 ANA top config
6122 10:52:02.640411 ===================================
6123 10:52:02.643375 DLL_ASYNC_EN = 0
6124 10:52:02.643469 ALL_SLAVE_EN = 1
6125 10:52:02.646998 NEW_RANK_MODE = 1
6126 10:52:02.650450 DLL_IDLE_MODE = 1
6127 10:52:02.653828 LP45_APHY_COMB_EN = 1
6128 10:52:02.653962 TX_ODT_DIS = 1
6129 10:52:02.657060 NEW_8X_MODE = 1
6130 10:52:02.660043 ===================================
6131 10:52:02.663557 ===================================
6132 10:52:02.666967 data_rate = 800
6133 10:52:02.670303 CKR = 1
6134 10:52:02.674130 DQ_P2S_RATIO = 4
6135 10:52:02.676738 ===================================
6136 10:52:02.680520 CA_P2S_RATIO = 4
6137 10:52:02.680601 DQ_CA_OPEN = 0
6138 10:52:02.683784 DQ_SEMI_OPEN = 1
6139 10:52:02.686732 CA_SEMI_OPEN = 1
6140 10:52:02.690209 CA_FULL_RATE = 0
6141 10:52:02.693775 DQ_CKDIV4_EN = 0
6142 10:52:02.693856 CA_CKDIV4_EN = 1
6143 10:52:02.697129 CA_PREDIV_EN = 0
6144 10:52:02.700419 PH8_DLY = 0
6145 10:52:02.703233 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 10:52:02.706622 DQ_AAMCK_DIV = 0
6147 10:52:02.710537 CA_AAMCK_DIV = 0
6148 10:52:02.710619 CA_ADMCK_DIV = 4
6149 10:52:02.713391 DQ_TRACK_CA_EN = 0
6150 10:52:02.716951 CA_PICK = 800
6151 10:52:02.720423 CA_MCKIO = 400
6152 10:52:02.723759 MCKIO_SEMI = 400
6153 10:52:02.726663 PLL_FREQ = 3016
6154 10:52:02.730508 DQ_UI_PI_RATIO = 32
6155 10:52:02.733403 CA_UI_PI_RATIO = 32
6156 10:52:02.736795 ===================================
6157 10:52:02.740358 ===================================
6158 10:52:02.740440 memory_type:LPDDR4
6159 10:52:02.743257 GP_NUM : 10
6160 10:52:02.746720 SRAM_EN : 1
6161 10:52:02.746816 MD32_EN : 0
6162 10:52:02.750189 ===================================
6163 10:52:02.753202 [ANA_INIT] >>>>>>>>>>>>>>
6164 10:52:02.756783 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 10:52:02.760059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 10:52:02.763626 ===================================
6167 10:52:02.766741 data_rate = 800,PCW = 0X7400
6168 10:52:02.769786 ===================================
6169 10:52:02.772926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 10:52:02.776585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 10:52:02.790378 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 10:52:02.792894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 10:52:02.796460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 10:52:02.799928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 10:52:02.802738 [ANA_INIT] flow start
6176 10:52:02.802818 [ANA_INIT] PLL >>>>>>>>
6177 10:52:02.806557 [ANA_INIT] PLL <<<<<<<<
6178 10:52:02.809626 [ANA_INIT] MIDPI >>>>>>>>
6179 10:52:02.812847 [ANA_INIT] MIDPI <<<<<<<<
6180 10:52:02.812929 [ANA_INIT] DLL >>>>>>>>
6181 10:52:02.816363 [ANA_INIT] flow end
6182 10:52:02.819833 ============ LP4 DIFF to SE enter ============
6183 10:52:02.823116 ============ LP4 DIFF to SE exit ============
6184 10:52:02.825929 [ANA_INIT] <<<<<<<<<<<<<
6185 10:52:02.829630 [Flow] Enable top DCM control >>>>>
6186 10:52:02.832986 [Flow] Enable top DCM control <<<<<
6187 10:52:02.836810 Enable DLL master slave shuffle
6188 10:52:02.842945 ==============================================================
6189 10:52:02.843027 Gating Mode config
6190 10:52:02.849579 ==============================================================
6191 10:52:02.849660 Config description:
6192 10:52:02.859144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 10:52:02.866166 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 10:52:02.872892 SELPH_MODE 0: By rank 1: By Phase
6195 10:52:02.876414 ==============================================================
6196 10:52:02.879354 GAT_TRACK_EN = 0
6197 10:52:02.882852 RX_GATING_MODE = 2
6198 10:52:02.886192 RX_GATING_TRACK_MODE = 2
6199 10:52:02.889277 SELPH_MODE = 1
6200 10:52:02.892521 PICG_EARLY_EN = 1
6201 10:52:02.896006 VALID_LAT_VALUE = 1
6202 10:52:02.902421 ==============================================================
6203 10:52:02.905894 Enter into Gating configuration >>>>
6204 10:52:02.909228 Exit from Gating configuration <<<<
6205 10:52:02.909309 Enter into DVFS_PRE_config >>>>>
6206 10:52:02.922392 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 10:52:02.925742 Exit from DVFS_PRE_config <<<<<
6208 10:52:02.929222 Enter into PICG configuration >>>>
6209 10:52:02.932258 Exit from PICG configuration <<<<
6210 10:52:02.932351 [RX_INPUT] configuration >>>>>
6211 10:52:02.935708 [RX_INPUT] configuration <<<<<
6212 10:52:02.942472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 10:52:02.945389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 10:52:02.952339 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 10:52:02.959010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 10:52:02.965412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 10:52:02.972082 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 10:52:02.975527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 10:52:02.979073 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 10:52:02.985776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 10:52:02.988971 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 10:52:02.992592 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 10:52:02.995492 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 10:52:02.998976 ===================================
6225 10:52:03.001936 LPDDR4 DRAM CONFIGURATION
6226 10:52:03.005502 ===================================
6227 10:52:03.008933 EX_ROW_EN[0] = 0x0
6228 10:52:03.009051 EX_ROW_EN[1] = 0x0
6229 10:52:03.011937 LP4Y_EN = 0x0
6230 10:52:03.012006 WORK_FSP = 0x0
6231 10:52:03.015717 WL = 0x2
6232 10:52:03.015816 RL = 0x2
6233 10:52:03.018460 BL = 0x2
6234 10:52:03.018559 RPST = 0x0
6235 10:52:03.022083 RD_PRE = 0x0
6236 10:52:03.022155 WR_PRE = 0x1
6237 10:52:03.025685 WR_PST = 0x0
6238 10:52:03.025755 DBI_WR = 0x0
6239 10:52:03.029150 DBI_RD = 0x0
6240 10:52:03.029221 OTF = 0x1
6241 10:52:03.032092 ===================================
6242 10:52:03.038638 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 10:52:03.042029 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 10:52:03.045193 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 10:52:03.048714 ===================================
6246 10:52:03.051781 LPDDR4 DRAM CONFIGURATION
6247 10:52:03.055082 ===================================
6248 10:52:03.058745 EX_ROW_EN[0] = 0x10
6249 10:52:03.058825 EX_ROW_EN[1] = 0x0
6250 10:52:03.061749 LP4Y_EN = 0x0
6251 10:52:03.061837 WORK_FSP = 0x0
6252 10:52:03.065226 WL = 0x2
6253 10:52:03.065294 RL = 0x2
6254 10:52:03.068650 BL = 0x2
6255 10:52:03.068717 RPST = 0x0
6256 10:52:03.071557 RD_PRE = 0x0
6257 10:52:03.071634 WR_PRE = 0x1
6258 10:52:03.074898 WR_PST = 0x0
6259 10:52:03.074975 DBI_WR = 0x0
6260 10:52:03.078707 DBI_RD = 0x0
6261 10:52:03.078793 OTF = 0x1
6262 10:52:03.082038 ===================================
6263 10:52:03.088269 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 10:52:03.093019 nWR fixed to 30
6265 10:52:03.096253 [ModeRegInit_LP4] CH0 RK0
6266 10:52:03.096325 [ModeRegInit_LP4] CH0 RK1
6267 10:52:03.099703 [ModeRegInit_LP4] CH1 RK0
6268 10:52:03.103206 [ModeRegInit_LP4] CH1 RK1
6269 10:52:03.103305 match AC timing 19
6270 10:52:03.109798 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 10:52:03.113197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 10:52:03.116002 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 10:52:03.122651 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 10:52:03.126042 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 10:52:03.126144 ==
6276 10:52:03.129418 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 10:52:03.132885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 10:52:03.132965 ==
6279 10:52:03.139130 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 10:52:03.146149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 10:52:03.149672 [CA 0] Center 36 (8~64) winsize 57
6282 10:52:03.153023 [CA 1] Center 36 (8~64) winsize 57
6283 10:52:03.155877 [CA 2] Center 36 (8~64) winsize 57
6284 10:52:03.159053 [CA 3] Center 36 (8~64) winsize 57
6285 10:52:03.159133 [CA 4] Center 36 (8~64) winsize 57
6286 10:52:03.162685 [CA 5] Center 36 (8~64) winsize 57
6287 10:52:03.162766
6288 10:52:03.169689 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 10:52:03.169770
6290 10:52:03.172648 [CATrainingPosCal] consider 1 rank data
6291 10:52:03.176078 u2DelayCellTimex100 = 270/100 ps
6292 10:52:03.179612 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:52:03.182794 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 10:52:03.185874 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 10:52:03.189355 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 10:52:03.192902 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 10:52:03.195813 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 10:52:03.195893
6299 10:52:03.199475 CA PerBit enable=1, Macro0, CA PI delay=36
6300 10:52:03.199556
6301 10:52:03.202485 [CBTSetCACLKResult] CA Dly = 36
6302 10:52:03.206055 CS Dly: 1 (0~32)
6303 10:52:03.206135 ==
6304 10:52:03.209062 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 10:52:03.212648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 10:52:03.212730 ==
6307 10:52:03.218799 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 10:52:03.222599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6309 10:52:03.225706 [CA 0] Center 36 (8~64) winsize 57
6310 10:52:03.229156 [CA 1] Center 36 (8~64) winsize 57
6311 10:52:03.232183 [CA 2] Center 36 (8~64) winsize 57
6312 10:52:03.235640 [CA 3] Center 36 (8~64) winsize 57
6313 10:52:03.239113 [CA 4] Center 36 (8~64) winsize 57
6314 10:52:03.242284 [CA 5] Center 36 (8~64) winsize 57
6315 10:52:03.242365
6316 10:52:03.245681 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6317 10:52:03.245763
6318 10:52:03.249171 [CATrainingPosCal] consider 2 rank data
6319 10:52:03.252266 u2DelayCellTimex100 = 270/100 ps
6320 10:52:03.255628 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 10:52:03.259060 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 10:52:03.265740 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 10:52:03.269317 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 10:52:03.272377 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 10:52:03.275728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 10:52:03.275809
6327 10:52:03.279017 CA PerBit enable=1, Macro0, CA PI delay=36
6328 10:52:03.279098
6329 10:52:03.282730 [CBTSetCACLKResult] CA Dly = 36
6330 10:52:03.282811 CS Dly: 1 (0~32)
6331 10:52:03.282874
6332 10:52:03.285964 ----->DramcWriteLeveling(PI) begin...
6333 10:52:03.289214 ==
6334 10:52:03.289295 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 10:52:03.295327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 10:52:03.295417 ==
6337 10:52:03.298871 Write leveling (Byte 0): 40 => 8
6338 10:52:03.302227 Write leveling (Byte 1): 32 => 0
6339 10:52:03.302309 DramcWriteLeveling(PI) end<-----
6340 10:52:03.305539
6341 10:52:03.305618 ==
6342 10:52:03.309623 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 10:52:03.312519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 10:52:03.312600 ==
6345 10:52:03.315519 [Gating] SW mode calibration
6346 10:52:03.321908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 10:52:03.325797 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 10:52:03.332346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 10:52:03.335237 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 10:52:03.338639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 10:52:03.345327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 10:52:03.348896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 10:52:03.351953 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 10:52:03.358839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 10:52:03.362638 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 10:52:03.365549 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 10:52:03.368614 Total UI for P1: 0, mck2ui 16
6358 10:52:03.372048 best dqsien dly found for B0: ( 0, 14, 24)
6359 10:52:03.375463 Total UI for P1: 0, mck2ui 16
6360 10:52:03.378414 best dqsien dly found for B1: ( 0, 14, 24)
6361 10:52:03.382047 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 10:52:03.385276 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 10:52:03.385384
6364 10:52:03.391639 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 10:52:03.394960 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 10:52:03.398293 [Gating] SW calibration Done
6367 10:52:03.398372 ==
6368 10:52:03.401563 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 10:52:03.405675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 10:52:03.405756 ==
6371 10:52:03.405818 RX Vref Scan: 0
6372 10:52:03.405876
6373 10:52:03.408185 RX Vref 0 -> 0, step: 1
6374 10:52:03.408264
6375 10:52:03.412318 RX Delay -410 -> 252, step: 16
6376 10:52:03.415052 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6377 10:52:03.422033 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6378 10:52:03.425079 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6379 10:52:03.428404 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6380 10:52:03.431837 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6381 10:52:03.438070 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6382 10:52:03.441478 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6383 10:52:03.444784 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6384 10:52:03.448340 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6385 10:52:03.454704 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6386 10:52:03.458065 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6387 10:52:03.461476 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6388 10:52:03.464660 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6389 10:52:03.471492 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6390 10:52:03.474991 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6391 10:52:03.478138 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6392 10:52:03.478218 ==
6393 10:52:03.481664 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:52:03.484699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:52:03.487920 ==
6396 10:52:03.487998 DQS Delay:
6397 10:52:03.488060 DQS0 = 35, DQS1 = 51
6398 10:52:03.491465 DQM Delay:
6399 10:52:03.491544 DQM0 = 5, DQM1 = 10
6400 10:52:03.494602 DQ Delay:
6401 10:52:03.494683 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6402 10:52:03.497802 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6403 10:52:03.501323 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6404 10:52:03.504740 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6405 10:52:03.504820
6406 10:52:03.504882
6407 10:52:03.504940 ==
6408 10:52:03.508276 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 10:52:03.514498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 10:52:03.514603 ==
6411 10:52:03.514687
6412 10:52:03.514751
6413 10:52:03.514808 TX Vref Scan disable
6414 10:52:03.517978 == TX Byte 0 ==
6415 10:52:03.521649 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 10:52:03.524597 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 10:52:03.527881 == TX Byte 1 ==
6418 10:52:03.531075 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6419 10:52:03.534610 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6420 10:52:03.538028 ==
6421 10:52:03.541416 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 10:52:03.544218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:52:03.544299 ==
6424 10:52:03.544361
6425 10:52:03.544418
6426 10:52:03.547754 TX Vref Scan disable
6427 10:52:03.547834 == TX Byte 0 ==
6428 10:52:03.551132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 10:52:03.557851 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 10:52:03.557930 == TX Byte 1 ==
6431 10:52:03.561327 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6432 10:52:03.568060 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6433 10:52:03.568139
6434 10:52:03.568201 [DATLAT]
6435 10:52:03.568283 Freq=400, CH0 RK0
6436 10:52:03.568354
6437 10:52:03.571013 DATLAT Default: 0xf
6438 10:52:03.574114 0, 0xFFFF, sum = 0
6439 10:52:03.574194 1, 0xFFFF, sum = 0
6440 10:52:03.577761 2, 0xFFFF, sum = 0
6441 10:52:03.577842 3, 0xFFFF, sum = 0
6442 10:52:03.581178 4, 0xFFFF, sum = 0
6443 10:52:03.581260 5, 0xFFFF, sum = 0
6444 10:52:03.584164 6, 0xFFFF, sum = 0
6445 10:52:03.584275 7, 0xFFFF, sum = 0
6446 10:52:03.587757 8, 0xFFFF, sum = 0
6447 10:52:03.587839 9, 0xFFFF, sum = 0
6448 10:52:03.590600 10, 0xFFFF, sum = 0
6449 10:52:03.590681 11, 0xFFFF, sum = 0
6450 10:52:03.594038 12, 0xFFFF, sum = 0
6451 10:52:03.594120 13, 0x0, sum = 1
6452 10:52:03.597718 14, 0x0, sum = 2
6453 10:52:03.597800 15, 0x0, sum = 3
6454 10:52:03.601117 16, 0x0, sum = 4
6455 10:52:03.601199 best_step = 14
6456 10:52:03.601262
6457 10:52:03.601321 ==
6458 10:52:03.604503 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 10:52:03.607805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 10:52:03.611130 ==
6461 10:52:03.611242 RX Vref Scan: 1
6462 10:52:03.611307
6463 10:52:03.613945 RX Vref 0 -> 0, step: 1
6464 10:52:03.614030
6465 10:52:03.617800 RX Delay -343 -> 252, step: 8
6466 10:52:03.617880
6467 10:52:03.620919 Set Vref, RX VrefLevel [Byte0]: 51
6468 10:52:03.624126 [Byte1]: 51
6469 10:52:03.624207
6470 10:52:03.627129 Final RX Vref Byte 0 = 51 to rank0
6471 10:52:03.630800 Final RX Vref Byte 1 = 51 to rank0
6472 10:52:03.633896 Final RX Vref Byte 0 = 51 to rank1
6473 10:52:03.637106 Final RX Vref Byte 1 = 51 to rank1==
6474 10:52:03.640370 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 10:52:03.643684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 10:52:03.643765 ==
6477 10:52:03.647208 DQS Delay:
6478 10:52:03.647288 DQS0 = 44, DQS1 = 60
6479 10:52:03.650616 DQM Delay:
6480 10:52:03.650697 DQM0 = 11, DQM1 = 14
6481 10:52:03.653965 DQ Delay:
6482 10:52:03.654045 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6483 10:52:03.657337 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6484 10:52:03.660680 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6485 10:52:03.663685 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6486 10:52:03.663765
6487 10:52:03.663829
6488 10:52:03.673637 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f4c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6489 10:52:03.677260 CH0 RK0: MR19=C0C, MR18=7F4C
6490 10:52:03.683537 CH0_RK0: MR19=0xC0C, MR18=0x7F4C, DQSOSC=393, MR23=63, INC=382, DEC=254
6491 10:52:03.683618 ==
6492 10:52:03.687141 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 10:52:03.690665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 10:52:03.690761 ==
6495 10:52:03.693795 [Gating] SW mode calibration
6496 10:52:03.699995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 10:52:03.703683 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 10:52:03.710181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 10:52:03.713443 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 10:52:03.717247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 10:52:03.723364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 10:52:03.726399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 10:52:03.729947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 10:52:03.736382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 10:52:03.739648 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 10:52:03.743650 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 10:52:03.746638 Total UI for P1: 0, mck2ui 16
6508 10:52:03.750111 best dqsien dly found for B0: ( 0, 14, 24)
6509 10:52:03.753514 Total UI for P1: 0, mck2ui 16
6510 10:52:03.756829 best dqsien dly found for B1: ( 0, 14, 24)
6511 10:52:03.759764 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 10:52:03.763011 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 10:52:03.766466
6514 10:52:03.769973 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 10:52:03.773341 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 10:52:03.776910 [Gating] SW calibration Done
6517 10:52:03.776994 ==
6518 10:52:03.779778 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 10:52:03.783275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 10:52:03.783427 ==
6521 10:52:03.783520 RX Vref Scan: 0
6522 10:52:03.783616
6523 10:52:03.786198 RX Vref 0 -> 0, step: 1
6524 10:52:03.786292
6525 10:52:03.789862 RX Delay -410 -> 252, step: 16
6526 10:52:03.793255 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6527 10:52:03.800113 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6528 10:52:03.803017 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6529 10:52:03.806519 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6530 10:52:03.809366 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6531 10:52:03.816047 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6532 10:52:03.819443 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6533 10:52:03.822924 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6534 10:52:03.826321 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6535 10:52:03.832798 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6536 10:52:03.836259 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6537 10:52:03.839845 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6538 10:52:03.842564 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6539 10:52:03.849414 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6540 10:52:03.852977 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6541 10:52:03.855795 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6542 10:52:03.855866 ==
6543 10:52:03.859268 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 10:52:03.865692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 10:52:03.865784 ==
6546 10:52:03.865894 DQS Delay:
6547 10:52:03.869191 DQS0 = 43, DQS1 = 51
6548 10:52:03.869259 DQM Delay:
6549 10:52:03.869321 DQM0 = 11, DQM1 = 10
6550 10:52:03.872588 DQ Delay:
6551 10:52:03.875991 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6552 10:52:03.876062 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6553 10:52:03.879241 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6554 10:52:03.882841 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6555 10:52:03.882907
6556 10:52:03.882987
6557 10:52:03.885757 ==
6558 10:52:03.889265 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 10:52:03.892465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 10:52:03.892531 ==
6561 10:52:03.892592
6562 10:52:03.892649
6563 10:52:03.895784 TX Vref Scan disable
6564 10:52:03.895849 == TX Byte 0 ==
6565 10:52:03.899455 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6566 10:52:03.905914 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6567 10:52:03.905992 == TX Byte 1 ==
6568 10:52:03.909080 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6569 10:52:03.912641 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6570 10:52:03.916023 ==
6571 10:52:03.918819 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 10:52:03.922339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 10:52:03.922419 ==
6574 10:52:03.922482
6575 10:52:03.922541
6576 10:52:03.925759 TX Vref Scan disable
6577 10:52:03.925834 == TX Byte 0 ==
6578 10:52:03.929320 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6579 10:52:03.935645 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6580 10:52:03.935714 == TX Byte 1 ==
6581 10:52:03.939029 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6582 10:52:03.945593 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6583 10:52:03.945664
6584 10:52:03.945725 [DATLAT]
6585 10:52:03.945785 Freq=400, CH0 RK1
6586 10:52:03.945842
6587 10:52:03.949001 DATLAT Default: 0xe
6588 10:52:03.952301 0, 0xFFFF, sum = 0
6589 10:52:03.952373 1, 0xFFFF, sum = 0
6590 10:52:03.955712 2, 0xFFFF, sum = 0
6591 10:52:03.955782 3, 0xFFFF, sum = 0
6592 10:52:03.959049 4, 0xFFFF, sum = 0
6593 10:52:03.959120 5, 0xFFFF, sum = 0
6594 10:52:03.961958 6, 0xFFFF, sum = 0
6595 10:52:03.962032 7, 0xFFFF, sum = 0
6596 10:52:03.965147 8, 0xFFFF, sum = 0
6597 10:52:03.965220 9, 0xFFFF, sum = 0
6598 10:52:03.968647 10, 0xFFFF, sum = 0
6599 10:52:03.968724 11, 0xFFFF, sum = 0
6600 10:52:03.972180 12, 0xFFFF, sum = 0
6601 10:52:03.972268 13, 0x0, sum = 1
6602 10:52:03.975718 14, 0x0, sum = 2
6603 10:52:03.975789 15, 0x0, sum = 3
6604 10:52:03.978624 16, 0x0, sum = 4
6605 10:52:03.978710 best_step = 14
6606 10:52:03.978775
6607 10:52:03.978849 ==
6608 10:52:03.981828 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 10:52:03.985723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 10:52:03.988860 ==
6611 10:52:03.988941 RX Vref Scan: 0
6612 10:52:03.989004
6613 10:52:03.991777 RX Vref 0 -> 0, step: 1
6614 10:52:03.991857
6615 10:52:03.994840 RX Delay -343 -> 252, step: 8
6616 10:52:04.001788 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6617 10:52:04.004807 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6618 10:52:04.008650 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6619 10:52:04.012030 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6620 10:52:04.018779 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6621 10:52:04.021714 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6622 10:52:04.024896 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6623 10:52:04.028481 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6624 10:52:04.035250 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6625 10:52:04.038297 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6626 10:52:04.041869 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6627 10:52:04.044782 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6628 10:52:04.051326 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6629 10:52:04.054840 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6630 10:52:04.058008 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6631 10:52:04.061300 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6632 10:52:04.061383 ==
6633 10:52:04.064653 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 10:52:04.071386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 10:52:04.071467 ==
6636 10:52:04.071530 DQS Delay:
6637 10:52:04.074789 DQS0 = 48, DQS1 = 60
6638 10:52:04.074869 DQM Delay:
6639 10:52:04.077774 DQM0 = 14, DQM1 = 13
6640 10:52:04.077855 DQ Delay:
6641 10:52:04.081390 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6642 10:52:04.084865 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6643 10:52:04.088116 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6644 10:52:04.091191 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6645 10:52:04.091271
6646 10:52:04.091334
6647 10:52:04.097653 [DQSOSCAuto] RK1, (LSB)MR18= 0x9466, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6648 10:52:04.101210 CH0 RK1: MR19=C0C, MR18=9466
6649 10:52:04.107761 CH0_RK1: MR19=0xC0C, MR18=0x9466, DQSOSC=391, MR23=63, INC=386, DEC=257
6650 10:52:04.111139 [RxdqsGatingPostProcess] freq 400
6651 10:52:04.117702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 10:52:04.117823 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 10:52:04.121194 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 10:52:04.124577 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 10:52:04.127421 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 10:52:04.131296 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 10:52:04.134106 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 10:52:04.137408 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 10:52:04.141106 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 10:52:04.143932 Pre-setting of DQS Precalculation
6661 10:52:04.151146 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 10:52:04.151252 ==
6663 10:52:04.153828 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 10:52:04.157852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 10:52:04.157956 ==
6666 10:52:04.161177 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 10:52:04.167281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6668 10:52:04.170602 [CA 0] Center 36 (8~64) winsize 57
6669 10:52:04.173926 [CA 1] Center 36 (8~64) winsize 57
6670 10:52:04.177023 [CA 2] Center 36 (8~64) winsize 57
6671 10:52:04.180594 [CA 3] Center 36 (8~64) winsize 57
6672 10:52:04.183850 [CA 4] Center 36 (8~64) winsize 57
6673 10:52:04.187271 [CA 5] Center 36 (8~64) winsize 57
6674 10:52:04.187388
6675 10:52:04.190570 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6676 10:52:04.190704
6677 10:52:04.193920 [CATrainingPosCal] consider 1 rank data
6678 10:52:04.197520 u2DelayCellTimex100 = 270/100 ps
6679 10:52:04.201004 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:52:04.203892 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 10:52:04.207506 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 10:52:04.211035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 10:52:04.213973 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 10:52:04.220948 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 10:52:04.221047
6686 10:52:04.224763 CA PerBit enable=1, Macro0, CA PI delay=36
6687 10:52:04.224883
6688 10:52:04.227562 [CBTSetCACLKResult] CA Dly = 36
6689 10:52:04.227649 CS Dly: 1 (0~32)
6690 10:52:04.227718 ==
6691 10:52:04.230369 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 10:52:04.233890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 10:52:04.237191 ==
6694 10:52:04.240630 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 10:52:04.247330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6696 10:52:04.250908 [CA 0] Center 36 (8~64) winsize 57
6697 10:52:04.253835 [CA 1] Center 36 (8~64) winsize 57
6698 10:52:04.257529 [CA 2] Center 36 (8~64) winsize 57
6699 10:52:04.260384 [CA 3] Center 36 (8~64) winsize 57
6700 10:52:04.263920 [CA 4] Center 36 (8~64) winsize 57
6701 10:52:04.267469 [CA 5] Center 36 (8~64) winsize 57
6702 10:52:04.267548
6703 10:52:04.270705 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6704 10:52:04.270778
6705 10:52:04.273938 [CATrainingPosCal] consider 2 rank data
6706 10:52:04.277080 u2DelayCellTimex100 = 270/100 ps
6707 10:52:04.280545 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 10:52:04.283867 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 10:52:04.286829 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 10:52:04.290276 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 10:52:04.293603 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 10:52:04.296979 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 10:52:04.297053
6714 10:52:04.304114 CA PerBit enable=1, Macro0, CA PI delay=36
6715 10:52:04.304199
6716 10:52:04.304267 [CBTSetCACLKResult] CA Dly = 36
6717 10:52:04.307090 CS Dly: 1 (0~32)
6718 10:52:04.307170
6719 10:52:04.310548 ----->DramcWriteLeveling(PI) begin...
6720 10:52:04.310634 ==
6721 10:52:04.313638 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 10:52:04.317055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 10:52:04.317130 ==
6724 10:52:04.320465 Write leveling (Byte 0): 40 => 8
6725 10:52:04.323625 Write leveling (Byte 1): 40 => 8
6726 10:52:04.326889 DramcWriteLeveling(PI) end<-----
6727 10:52:04.326967
6728 10:52:04.327029 ==
6729 10:52:04.330541 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 10:52:04.333915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 10:52:04.333989 ==
6732 10:52:04.336850 [Gating] SW mode calibration
6733 10:52:04.343498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 10:52:04.350201 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 10:52:04.353663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 10:52:04.360230 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6737 10:52:04.364260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 10:52:04.367008 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 10:52:04.373349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 10:52:04.377078 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 10:52:04.380051 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 10:52:04.387007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 10:52:04.390372 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 10:52:04.393729 Total UI for P1: 0, mck2ui 16
6745 10:52:04.397228 best dqsien dly found for B0: ( 0, 14, 24)
6746 10:52:04.400441 Total UI for P1: 0, mck2ui 16
6747 10:52:04.403381 best dqsien dly found for B1: ( 0, 14, 24)
6748 10:52:04.407150 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 10:52:04.410148 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 10:52:04.410227
6751 10:52:04.413777 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 10:52:04.416926 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 10:52:04.420441 [Gating] SW calibration Done
6754 10:52:04.420522 ==
6755 10:52:04.423801 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 10:52:04.426686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 10:52:04.426795 ==
6758 10:52:04.429927 RX Vref Scan: 0
6759 10:52:04.430033
6760 10:52:04.433185 RX Vref 0 -> 0, step: 1
6761 10:52:04.433261
6762 10:52:04.433324 RX Delay -410 -> 252, step: 16
6763 10:52:04.440126 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6764 10:52:04.443559 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6765 10:52:04.446853 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6766 10:52:04.450399 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6767 10:52:04.457352 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6768 10:52:04.460292 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6769 10:52:04.463267 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6770 10:52:04.466742 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6771 10:52:04.473496 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6772 10:52:04.476792 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6773 10:52:04.480152 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6774 10:52:04.483418 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6775 10:52:04.490044 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6776 10:52:04.493486 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6777 10:52:04.496356 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6778 10:52:04.503025 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6779 10:52:04.503103 ==
6780 10:52:04.506601 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:52:04.510015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:52:04.510087 ==
6783 10:52:04.510149 DQS Delay:
6784 10:52:04.513600 DQS0 = 51, DQS1 = 59
6785 10:52:04.513668 DQM Delay:
6786 10:52:04.516611 DQM0 = 19, DQM1 = 17
6787 10:52:04.516710 DQ Delay:
6788 10:52:04.520240 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6789 10:52:04.523051 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6790 10:52:04.526358 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6791 10:52:04.529848 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6792 10:52:04.529945
6793 10:52:04.530024
6794 10:52:04.530101 ==
6795 10:52:04.533136 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 10:52:04.536428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 10:52:04.536525 ==
6798 10:52:04.536603
6799 10:52:04.536696
6800 10:52:04.539834 TX Vref Scan disable
6801 10:52:04.542802 == TX Byte 0 ==
6802 10:52:04.546277 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 10:52:04.549610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 10:52:04.553077 == TX Byte 1 ==
6805 10:52:04.556359 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 10:52:04.559615 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 10:52:04.559696 ==
6808 10:52:04.562675 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 10:52:04.566272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:52:04.566355 ==
6811 10:52:04.569821
6812 10:52:04.569901
6813 10:52:04.569965 TX Vref Scan disable
6814 10:52:04.572814 == TX Byte 0 ==
6815 10:52:04.575974 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 10:52:04.579873 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 10:52:04.582879 == TX Byte 1 ==
6818 10:52:04.586055 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 10:52:04.589573 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 10:52:04.589657
6821 10:52:04.589740 [DATLAT]
6822 10:52:04.593086 Freq=400, CH1 RK0
6823 10:52:04.593170
6824 10:52:04.596076 DATLAT Default: 0xf
6825 10:52:04.596159 0, 0xFFFF, sum = 0
6826 10:52:04.599462 1, 0xFFFF, sum = 0
6827 10:52:04.599547 2, 0xFFFF, sum = 0
6828 10:52:04.602706 3, 0xFFFF, sum = 0
6829 10:52:04.602791 4, 0xFFFF, sum = 0
6830 10:52:04.606254 5, 0xFFFF, sum = 0
6831 10:52:04.606338 6, 0xFFFF, sum = 0
6832 10:52:04.609111 7, 0xFFFF, sum = 0
6833 10:52:04.609196 8, 0xFFFF, sum = 0
6834 10:52:04.612317 9, 0xFFFF, sum = 0
6835 10:52:04.612402 10, 0xFFFF, sum = 0
6836 10:52:04.615754 11, 0xFFFF, sum = 0
6837 10:52:04.615841 12, 0xFFFF, sum = 0
6838 10:52:04.619332 13, 0x0, sum = 1
6839 10:52:04.619452 14, 0x0, sum = 2
6840 10:52:04.622876 15, 0x0, sum = 3
6841 10:52:04.622960 16, 0x0, sum = 4
6842 10:52:04.626288 best_step = 14
6843 10:52:04.626371
6844 10:52:04.626454 ==
6845 10:52:04.629447 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 10:52:04.632160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 10:52:04.632244 ==
6848 10:52:04.635433 RX Vref Scan: 1
6849 10:52:04.635515
6850 10:52:04.635598 RX Vref 0 -> 0, step: 1
6851 10:52:04.635676
6852 10:52:04.639059 RX Delay -359 -> 252, step: 8
6853 10:52:04.639142
6854 10:52:04.642455 Set Vref, RX VrefLevel [Byte0]: 54
6855 10:52:04.646007 [Byte1]: 53
6856 10:52:04.650394
6857 10:52:04.650477 Final RX Vref Byte 0 = 54 to rank0
6858 10:52:04.653874 Final RX Vref Byte 1 = 53 to rank0
6859 10:52:04.656898 Final RX Vref Byte 0 = 54 to rank1
6860 10:52:04.660342 Final RX Vref Byte 1 = 53 to rank1==
6861 10:52:04.663285 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 10:52:04.669795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 10:52:04.669879 ==
6864 10:52:04.669963 DQS Delay:
6865 10:52:04.673219 DQS0 = 48, DQS1 = 60
6866 10:52:04.673303 DQM Delay:
6867 10:52:04.673387 DQM0 = 12, DQM1 = 13
6868 10:52:04.677174 DQ Delay:
6869 10:52:04.680168 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6870 10:52:04.683281 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6871 10:52:04.683385 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6872 10:52:04.686993 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6873 10:52:04.689986
6874 10:52:04.690068
6875 10:52:04.696663 [DQSOSCAuto] RK0, (LSB)MR18= 0x852b, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6876 10:52:04.700040 CH1 RK0: MR19=C0C, MR18=852B
6877 10:52:04.707154 CH1_RK0: MR19=0xC0C, MR18=0x852B, DQSOSC=393, MR23=63, INC=382, DEC=254
6878 10:52:04.707238 ==
6879 10:52:04.710145 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 10:52:04.713684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 10:52:04.713768 ==
6882 10:52:04.716650 [Gating] SW mode calibration
6883 10:52:04.723205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 10:52:04.730057 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 10:52:04.732950 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 10:52:04.736544 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 10:52:04.742797 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 10:52:04.746166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 10:52:04.749722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 10:52:04.756371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 10:52:04.759740 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 10:52:04.763150 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 10:52:04.769835 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 10:52:04.769918 Total UI for P1: 0, mck2ui 16
6895 10:52:04.773092 best dqsien dly found for B0: ( 0, 14, 24)
6896 10:52:04.776723 Total UI for P1: 0, mck2ui 16
6897 10:52:04.779625 best dqsien dly found for B1: ( 0, 14, 24)
6898 10:52:04.786130 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 10:52:04.789625 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 10:52:04.789709
6901 10:52:04.793000 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 10:52:04.795841 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 10:52:04.799252 [Gating] SW calibration Done
6904 10:52:04.799334 ==
6905 10:52:04.802730 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 10:52:04.806085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 10:52:04.806170 ==
6908 10:52:04.809423 RX Vref Scan: 0
6909 10:52:04.809506
6910 10:52:04.809589 RX Vref 0 -> 0, step: 1
6911 10:52:04.809668
6912 10:52:04.813254 RX Delay -410 -> 252, step: 16
6913 10:52:04.819615 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6914 10:52:04.822722 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6915 10:52:04.825724 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6916 10:52:04.829366 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6917 10:52:04.835686 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6918 10:52:04.839639 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6919 10:52:04.842668 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6920 10:52:04.845533 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6921 10:52:04.848918 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6922 10:52:04.855868 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6923 10:52:04.859140 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6924 10:52:04.862603 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6925 10:52:04.868877 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6926 10:52:04.872728 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6927 10:52:04.875746 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6928 10:52:04.879391 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6929 10:52:04.879488 ==
6930 10:52:04.882189 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 10:52:04.888660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 10:52:04.888744 ==
6933 10:52:04.888828 DQS Delay:
6934 10:52:04.892172 DQS0 = 51, DQS1 = 59
6935 10:52:04.892256 DQM Delay:
6936 10:52:04.895505 DQM0 = 17, DQM1 = 20
6937 10:52:04.895588 DQ Delay:
6938 10:52:04.898744 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6939 10:52:04.902190 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6940 10:52:04.905767 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6941 10:52:04.909027 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6942 10:52:04.909110
6943 10:52:04.909193
6944 10:52:04.909271 ==
6945 10:52:04.912110 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 10:52:04.915354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 10:52:04.915452 ==
6948 10:52:04.915582
6949 10:52:04.915692
6950 10:52:04.918706 TX Vref Scan disable
6951 10:52:04.918789 == TX Byte 0 ==
6952 10:52:04.925915 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6953 10:52:04.928924 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6954 10:52:04.929008 == TX Byte 1 ==
6955 10:52:04.935330 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6956 10:52:04.938850 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6957 10:52:04.938934 ==
6958 10:52:04.942367 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 10:52:04.945029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 10:52:04.945126 ==
6961 10:52:04.945206
6962 10:52:04.945268
6963 10:52:04.948331 TX Vref Scan disable
6964 10:52:04.948402 == TX Byte 0 ==
6965 10:52:04.955105 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6966 10:52:04.958620 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6967 10:52:04.958697 == TX Byte 1 ==
6968 10:52:04.965284 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6969 10:52:04.968621 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6970 10:52:04.968704
6971 10:52:04.968768 [DATLAT]
6972 10:52:04.971795 Freq=400, CH1 RK1
6973 10:52:04.971868
6974 10:52:04.971929 DATLAT Default: 0xe
6975 10:52:04.975157 0, 0xFFFF, sum = 0
6976 10:52:04.975274 1, 0xFFFF, sum = 0
6977 10:52:04.978082 2, 0xFFFF, sum = 0
6978 10:52:04.978185 3, 0xFFFF, sum = 0
6979 10:52:04.981598 4, 0xFFFF, sum = 0
6980 10:52:04.981669 5, 0xFFFF, sum = 0
6981 10:52:04.985341 6, 0xFFFF, sum = 0
6982 10:52:04.985416 7, 0xFFFF, sum = 0
6983 10:52:04.988141 8, 0xFFFF, sum = 0
6984 10:52:04.988212 9, 0xFFFF, sum = 0
6985 10:52:04.991643 10, 0xFFFF, sum = 0
6986 10:52:04.994676 11, 0xFFFF, sum = 0
6987 10:52:04.994749 12, 0xFFFF, sum = 0
6988 10:52:04.998671 13, 0x0, sum = 1
6989 10:52:04.998757 14, 0x0, sum = 2
6990 10:52:05.001780 15, 0x0, sum = 3
6991 10:52:05.001855 16, 0x0, sum = 4
6992 10:52:05.001924 best_step = 14
6993 10:52:05.001981
6994 10:52:05.004598 ==
6995 10:52:05.008053 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 10:52:05.011451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 10:52:05.011534 ==
6998 10:52:05.011597 RX Vref Scan: 0
6999 10:52:05.011655
7000 10:52:05.014413 RX Vref 0 -> 0, step: 1
7001 10:52:05.014511
7002 10:52:05.017670 RX Delay -359 -> 252, step: 8
7003 10:52:05.025284 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7004 10:52:05.028256 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7005 10:52:05.031774 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7006 10:52:05.035590 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7007 10:52:05.041851 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7008 10:52:05.045010 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7009 10:52:05.048209 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7010 10:52:05.051655 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7011 10:52:05.058028 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7012 10:52:05.061523 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7013 10:52:05.064984 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7014 10:52:05.071635 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
7015 10:52:05.075421 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7016 10:52:05.077952 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7017 10:52:05.081369 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7018 10:52:05.088061 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7019 10:52:05.088143 ==
7020 10:52:05.091522 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 10:52:05.094589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 10:52:05.094685 ==
7023 10:52:05.094774 DQS Delay:
7024 10:52:05.097950 DQS0 = 52, DQS1 = 56
7025 10:52:05.098031 DQM Delay:
7026 10:52:05.101362 DQM0 = 12, DQM1 = 9
7027 10:52:05.101443 DQ Delay:
7028 10:52:05.104771 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7029 10:52:05.108111 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7030 10:52:05.111048 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7031 10:52:05.114482 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7032 10:52:05.114564
7033 10:52:05.114627
7034 10:52:05.120989 [DQSOSCAuto] RK1, (LSB)MR18= 0x788d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7035 10:52:05.124827 CH1 RK1: MR19=C0C, MR18=788D
7036 10:52:05.131192 CH1_RK1: MR19=0xC0C, MR18=0x788D, DQSOSC=392, MR23=63, INC=384, DEC=256
7037 10:52:05.134726 [RxdqsGatingPostProcess] freq 400
7038 10:52:05.141081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 10:52:05.141163 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 10:52:05.144465 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 10:52:05.147511 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 10:52:05.150455 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 10:52:05.154046 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 10:52:05.157594 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 10:52:05.160959 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 10:52:05.163945 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 10:52:05.167506 Pre-setting of DQS Precalculation
7048 10:52:05.173935 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 10:52:05.180817 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 10:52:05.187189 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 10:52:05.187273
7052 10:52:05.187337
7053 10:52:05.190584 [Calibration Summary] 800 Mbps
7054 10:52:05.190664 CH 0, Rank 0
7055 10:52:05.193722 SW Impedance : PASS
7056 10:52:05.197231 DUTY Scan : NO K
7057 10:52:05.197313 ZQ Calibration : PASS
7058 10:52:05.200730 Jitter Meter : NO K
7059 10:52:05.203791 CBT Training : PASS
7060 10:52:05.203875 Write leveling : PASS
7061 10:52:05.206971 RX DQS gating : PASS
7062 10:52:05.207080 RX DQ/DQS(RDDQC) : PASS
7063 10:52:05.210384 TX DQ/DQS : PASS
7064 10:52:05.213827 RX DATLAT : PASS
7065 10:52:05.213928 RX DQ/DQS(Engine): PASS
7066 10:52:05.217271 TX OE : NO K
7067 10:52:05.217370 All Pass.
7068 10:52:05.217477
7069 10:52:05.220217 CH 0, Rank 1
7070 10:52:05.220295 SW Impedance : PASS
7071 10:52:05.223384 DUTY Scan : NO K
7072 10:52:05.226786 ZQ Calibration : PASS
7073 10:52:05.226897 Jitter Meter : NO K
7074 10:52:05.230700 CBT Training : PASS
7075 10:52:05.233772 Write leveling : NO K
7076 10:52:05.233875 RX DQS gating : PASS
7077 10:52:05.236684 RX DQ/DQS(RDDQC) : PASS
7078 10:52:05.240176 TX DQ/DQS : PASS
7079 10:52:05.240274 RX DATLAT : PASS
7080 10:52:05.243832 RX DQ/DQS(Engine): PASS
7081 10:52:05.247166 TX OE : NO K
7082 10:52:05.247279 All Pass.
7083 10:52:05.247400
7084 10:52:05.247477 CH 1, Rank 0
7085 10:52:05.250065 SW Impedance : PASS
7086 10:52:05.253614 DUTY Scan : NO K
7087 10:52:05.253722 ZQ Calibration : PASS
7088 10:52:05.256418 Jitter Meter : NO K
7089 10:52:05.260023 CBT Training : PASS
7090 10:52:05.260123 Write leveling : PASS
7091 10:52:05.263685 RX DQS gating : PASS
7092 10:52:05.263756 RX DQ/DQS(RDDQC) : PASS
7093 10:52:05.267106 TX DQ/DQS : PASS
7094 10:52:05.270171 RX DATLAT : PASS
7095 10:52:05.270271 RX DQ/DQS(Engine): PASS
7096 10:52:05.273456 TX OE : NO K
7097 10:52:05.273553 All Pass.
7098 10:52:05.273640
7099 10:52:05.276808 CH 1, Rank 1
7100 10:52:05.276878 SW Impedance : PASS
7101 10:52:05.280200 DUTY Scan : NO K
7102 10:52:05.283640 ZQ Calibration : PASS
7103 10:52:05.283734 Jitter Meter : NO K
7104 10:52:05.286549 CBT Training : PASS
7105 10:52:05.289905 Write leveling : NO K
7106 10:52:05.290001 RX DQS gating : PASS
7107 10:52:05.293596 RX DQ/DQS(RDDQC) : PASS
7108 10:52:05.296734 TX DQ/DQS : PASS
7109 10:52:05.296829 RX DATLAT : PASS
7110 10:52:05.300010 RX DQ/DQS(Engine): PASS
7111 10:52:05.302976 TX OE : NO K
7112 10:52:05.303073 All Pass.
7113 10:52:05.303161
7114 10:52:05.303245 DramC Write-DBI off
7115 10:52:05.306565 PER_BANK_REFRESH: Hybrid Mode
7116 10:52:05.310093 TX_TRACKING: ON
7117 10:52:05.316359 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 10:52:05.320064 [FAST_K] Save calibration result to emmc
7119 10:52:05.326432 dramc_set_vcore_voltage set vcore to 725000
7120 10:52:05.326518 Read voltage for 1600, 0
7121 10:52:05.330043 Vio18 = 0
7122 10:52:05.330146 Vcore = 725000
7123 10:52:05.330240 Vdram = 0
7124 10:52:05.333444 Vddq = 0
7125 10:52:05.333542 Vmddr = 0
7126 10:52:05.336686 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 10:52:05.343013 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 10:52:05.346650 MEM_TYPE=3, freq_sel=13
7129 10:52:05.350017 sv_algorithm_assistance_LP4_3733
7130 10:52:05.353053 ============ PULL DRAM RESETB DOWN ============
7131 10:52:05.356629 ========== PULL DRAM RESETB DOWN end =========
7132 10:52:05.359540 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 10:52:05.363204 ===================================
7134 10:52:05.366033 LPDDR4 DRAM CONFIGURATION
7135 10:52:05.369471 ===================================
7136 10:52:05.373141 EX_ROW_EN[0] = 0x0
7137 10:52:05.373241 EX_ROW_EN[1] = 0x0
7138 10:52:05.375909 LP4Y_EN = 0x0
7139 10:52:05.375980 WORK_FSP = 0x1
7140 10:52:05.379368 WL = 0x5
7141 10:52:05.379454 RL = 0x5
7142 10:52:05.382546 BL = 0x2
7143 10:52:05.382613 RPST = 0x0
7144 10:52:05.386588 RD_PRE = 0x0
7145 10:52:05.389221 WR_PRE = 0x1
7146 10:52:05.389318 WR_PST = 0x1
7147 10:52:05.392586 DBI_WR = 0x0
7148 10:52:05.392680 DBI_RD = 0x0
7149 10:52:05.395998 OTF = 0x1
7150 10:52:05.399355 ===================================
7151 10:52:05.403043 ===================================
7152 10:52:05.403141 ANA top config
7153 10:52:05.406061 ===================================
7154 10:52:05.409422 DLL_ASYNC_EN = 0
7155 10:52:05.412590 ALL_SLAVE_EN = 0
7156 10:52:05.412665 NEW_RANK_MODE = 1
7157 10:52:05.415874 DLL_IDLE_MODE = 1
7158 10:52:05.419188 LP45_APHY_COMB_EN = 1
7159 10:52:05.422723 TX_ODT_DIS = 0
7160 10:52:05.422828 NEW_8X_MODE = 1
7161 10:52:05.426205 ===================================
7162 10:52:05.428992 ===================================
7163 10:52:05.432437 data_rate = 3200
7164 10:52:05.436021 CKR = 1
7165 10:52:05.438817 DQ_P2S_RATIO = 8
7166 10:52:05.442712 ===================================
7167 10:52:05.445626 CA_P2S_RATIO = 8
7168 10:52:05.449026 DQ_CA_OPEN = 0
7169 10:52:05.449121 DQ_SEMI_OPEN = 0
7170 10:52:05.452675 CA_SEMI_OPEN = 0
7171 10:52:05.455897 CA_FULL_RATE = 0
7172 10:52:05.459311 DQ_CKDIV4_EN = 0
7173 10:52:05.462065 CA_CKDIV4_EN = 0
7174 10:52:05.465357 CA_PREDIV_EN = 0
7175 10:52:05.469028 PH8_DLY = 12
7176 10:52:05.469135 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 10:52:05.472023 DQ_AAMCK_DIV = 4
7178 10:52:05.475321 CA_AAMCK_DIV = 4
7179 10:52:05.478738 CA_ADMCK_DIV = 4
7180 10:52:05.482156 DQ_TRACK_CA_EN = 0
7181 10:52:05.485432 CA_PICK = 1600
7182 10:52:05.488860 CA_MCKIO = 1600
7183 10:52:05.488956 MCKIO_SEMI = 0
7184 10:52:05.491874 PLL_FREQ = 3068
7185 10:52:05.495261 DQ_UI_PI_RATIO = 32
7186 10:52:05.498424 CA_UI_PI_RATIO = 0
7187 10:52:05.502097 ===================================
7188 10:52:05.505551 ===================================
7189 10:52:05.508587 memory_type:LPDDR4
7190 10:52:05.508660 GP_NUM : 10
7191 10:52:05.512218 SRAM_EN : 1
7192 10:52:05.512313 MD32_EN : 0
7193 10:52:05.515217 ===================================
7194 10:52:05.518814 [ANA_INIT] >>>>>>>>>>>>>>
7195 10:52:05.521617 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 10:52:05.524874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 10:52:05.528304 ===================================
7198 10:52:05.531868 data_rate = 3200,PCW = 0X7600
7199 10:52:05.534924 ===================================
7200 10:52:05.538788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 10:52:05.545121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 10:52:05.548367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 10:52:05.554616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 10:52:05.558186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 10:52:05.561678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 10:52:05.561772 [ANA_INIT] flow start
7207 10:52:05.564550 [ANA_INIT] PLL >>>>>>>>
7208 10:52:05.568301 [ANA_INIT] PLL <<<<<<<<
7209 10:52:05.568392 [ANA_INIT] MIDPI >>>>>>>>
7210 10:52:05.571743 [ANA_INIT] MIDPI <<<<<<<<
7211 10:52:05.574597 [ANA_INIT] DLL >>>>>>>>
7212 10:52:05.578057 [ANA_INIT] DLL <<<<<<<<
7213 10:52:05.578154 [ANA_INIT] flow end
7214 10:52:05.581453 ============ LP4 DIFF to SE enter ============
7215 10:52:05.588135 ============ LP4 DIFF to SE exit ============
7216 10:52:05.588208 [ANA_INIT] <<<<<<<<<<<<<
7217 10:52:05.591471 [Flow] Enable top DCM control >>>>>
7218 10:52:05.594892 [Flow] Enable top DCM control <<<<<
7219 10:52:05.597986 Enable DLL master slave shuffle
7220 10:52:05.604498 ==============================================================
7221 10:52:05.604575 Gating Mode config
7222 10:52:05.610763 ==============================================================
7223 10:52:05.614285 Config description:
7224 10:52:05.624128 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 10:52:05.630777 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 10:52:05.634152 SELPH_MODE 0: By rank 1: By Phase
7227 10:52:05.641079 ==============================================================
7228 10:52:05.643906 GAT_TRACK_EN = 1
7229 10:52:05.647982 RX_GATING_MODE = 2
7230 10:52:05.648082 RX_GATING_TRACK_MODE = 2
7231 10:52:05.650642 SELPH_MODE = 1
7232 10:52:05.654007 PICG_EARLY_EN = 1
7233 10:52:05.657479 VALID_LAT_VALUE = 1
7234 10:52:05.664009 ==============================================================
7235 10:52:05.667654 Enter into Gating configuration >>>>
7236 10:52:05.670506 Exit from Gating configuration <<<<
7237 10:52:05.674123 Enter into DVFS_PRE_config >>>>>
7238 10:52:05.683633 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 10:52:05.686955 Exit from DVFS_PRE_config <<<<<
7240 10:52:05.690560 Enter into PICG configuration >>>>
7241 10:52:05.693867 Exit from PICG configuration <<<<
7242 10:52:05.697269 [RX_INPUT] configuration >>>>>
7243 10:52:05.700172 [RX_INPUT] configuration <<<<<
7244 10:52:05.703356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 10:52:05.710099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 10:52:05.716549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 10:52:05.723216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 10:52:05.730548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 10:52:05.733484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 10:52:05.739997 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 10:52:05.743337 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 10:52:05.746888 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 10:52:05.750174 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 10:52:05.753515 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 10:52:05.760193 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 10:52:05.763013 ===================================
7257 10:52:05.766670 LPDDR4 DRAM CONFIGURATION
7258 10:52:05.770399 ===================================
7259 10:52:05.770499 EX_ROW_EN[0] = 0x0
7260 10:52:05.773014 EX_ROW_EN[1] = 0x0
7261 10:52:05.773110 LP4Y_EN = 0x0
7262 10:52:05.776454 WORK_FSP = 0x1
7263 10:52:05.776548 WL = 0x5
7264 10:52:05.780116 RL = 0x5
7265 10:52:05.780223 BL = 0x2
7266 10:52:05.783330 RPST = 0x0
7267 10:52:05.783439 RD_PRE = 0x0
7268 10:52:05.786391 WR_PRE = 0x1
7269 10:52:05.786494 WR_PST = 0x1
7270 10:52:05.790062 DBI_WR = 0x0
7271 10:52:05.790169 DBI_RD = 0x0
7272 10:52:05.793002 OTF = 0x1
7273 10:52:05.796375 ===================================
7274 10:52:05.799473 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 10:52:05.803006 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 10:52:05.809769 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 10:52:05.813276 ===================================
7278 10:52:05.813376 LPDDR4 DRAM CONFIGURATION
7279 10:52:05.816125 ===================================
7280 10:52:05.819449 EX_ROW_EN[0] = 0x10
7281 10:52:05.823053 EX_ROW_EN[1] = 0x0
7282 10:52:05.823151 LP4Y_EN = 0x0
7283 10:52:05.826649 WORK_FSP = 0x1
7284 10:52:05.826771 WL = 0x5
7285 10:52:05.829734 RL = 0x5
7286 10:52:05.829814 BL = 0x2
7287 10:52:05.832970 RPST = 0x0
7288 10:52:05.833050 RD_PRE = 0x0
7289 10:52:05.836391 WR_PRE = 0x1
7290 10:52:05.836471 WR_PST = 0x1
7291 10:52:05.839804 DBI_WR = 0x0
7292 10:52:05.839884 DBI_RD = 0x0
7293 10:52:05.843091 OTF = 0x1
7294 10:52:05.846374 ===================================
7295 10:52:05.852846 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 10:52:05.852927 ==
7297 10:52:05.856334 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 10:52:05.859526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 10:52:05.859607 ==
7300 10:52:05.863090 [Duty_Offset_Calibration]
7301 10:52:05.863195 B0:2 B1:-1 CA:1
7302 10:52:05.863285
7303 10:52:05.865793 [DutyScan_Calibration_Flow] k_type=0
7304 10:52:05.875915
7305 10:52:05.875994 ==CLK 0==
7306 10:52:05.879515 Final CLK duty delay cell = -4
7307 10:52:05.883209 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7308 10:52:05.886054 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7309 10:52:05.889465 [-4] AVG Duty = 4922%(X100)
7310 10:52:05.889545
7311 10:52:05.892870 CH0 CLK Duty spec in!! Max-Min= 156%
7312 10:52:05.896266 [DutyScan_Calibration_Flow] ====Done====
7313 10:52:05.896345
7314 10:52:05.899227 [DutyScan_Calibration_Flow] k_type=1
7315 10:52:05.915955
7316 10:52:05.916063 ==DQS 0 ==
7317 10:52:05.919290 Final DQS duty delay cell = 0
7318 10:52:05.922671 [0] MAX Duty = 5125%(X100), DQS PI = 56
7319 10:52:05.925541 [0] MIN Duty = 5000%(X100), DQS PI = 14
7320 10:52:05.929100 [0] AVG Duty = 5062%(X100)
7321 10:52:05.929211
7322 10:52:05.929315 ==DQS 1 ==
7323 10:52:05.932090 Final DQS duty delay cell = -4
7324 10:52:05.935607 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7325 10:52:05.939068 [-4] MIN Duty = 5000%(X100), DQS PI = 42
7326 10:52:05.942402 [-4] AVG Duty = 5046%(X100)
7327 10:52:05.942518
7328 10:52:05.945770 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7329 10:52:05.945875
7330 10:52:05.948728 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7331 10:52:05.952078 [DutyScan_Calibration_Flow] ====Done====
7332 10:52:05.952159
7333 10:52:05.955629 [DutyScan_Calibration_Flow] k_type=3
7334 10:52:05.973106
7335 10:52:05.973187 ==DQM 0 ==
7336 10:52:05.976104 Final DQM duty delay cell = 0
7337 10:52:05.979624 [0] MAX Duty = 5000%(X100), DQS PI = 20
7338 10:52:05.982654 [0] MIN Duty = 4875%(X100), DQS PI = 4
7339 10:52:05.986123 [0] AVG Duty = 4937%(X100)
7340 10:52:05.986203
7341 10:52:05.986265 ==DQM 1 ==
7342 10:52:05.989671 Final DQM duty delay cell = 0
7343 10:52:05.992676 [0] MAX Duty = 5218%(X100), DQS PI = 58
7344 10:52:05.996262 [0] MIN Duty = 4969%(X100), DQS PI = 18
7345 10:52:05.999487 [0] AVG Duty = 5093%(X100)
7346 10:52:05.999565
7347 10:52:06.002942 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7348 10:52:06.003020
7349 10:52:06.006459 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7350 10:52:06.009149 [DutyScan_Calibration_Flow] ====Done====
7351 10:52:06.009226
7352 10:52:06.012496 [DutyScan_Calibration_Flow] k_type=2
7353 10:52:06.029246
7354 10:52:06.029327 ==DQ 0 ==
7355 10:52:06.032267 Final DQ duty delay cell = -4
7356 10:52:06.036009 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7357 10:52:06.039198 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7358 10:52:06.042772 [-4] AVG Duty = 4937%(X100)
7359 10:52:06.042851
7360 10:52:06.042912 ==DQ 1 ==
7361 10:52:06.045971 Final DQ duty delay cell = 0
7362 10:52:06.048854 [0] MAX Duty = 5031%(X100), DQS PI = 30
7363 10:52:06.052916 [0] MIN Duty = 4907%(X100), DQS PI = 18
7364 10:52:06.055750 [0] AVG Duty = 4969%(X100)
7365 10:52:06.055828
7366 10:52:06.059114 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7367 10:52:06.059218
7368 10:52:06.062556 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7369 10:52:06.066092 [DutyScan_Calibration_Flow] ====Done====
7370 10:52:06.066171 ==
7371 10:52:06.068918 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 10:52:06.072426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 10:52:06.072505 ==
7374 10:52:06.076007 [Duty_Offset_Calibration]
7375 10:52:06.076088 B0:1 B1:1 CA:2
7376 10:52:06.076149
7377 10:52:06.078956 [DutyScan_Calibration_Flow] k_type=0
7378 10:52:06.089791
7379 10:52:06.089869 ==CLK 0==
7380 10:52:06.093303 Final CLK duty delay cell = 0
7381 10:52:06.096785 [0] MAX Duty = 5187%(X100), DQS PI = 24
7382 10:52:06.100038 [0] MIN Duty = 4938%(X100), DQS PI = 50
7383 10:52:06.102789 [0] AVG Duty = 5062%(X100)
7384 10:52:06.102867
7385 10:52:06.106368 CH1 CLK Duty spec in!! Max-Min= 249%
7386 10:52:06.109784 [DutyScan_Calibration_Flow] ====Done====
7387 10:52:06.109862
7388 10:52:06.113258 [DutyScan_Calibration_Flow] k_type=1
7389 10:52:06.129719
7390 10:52:06.129808 ==DQS 0 ==
7391 10:52:06.132718 Final DQS duty delay cell = 0
7392 10:52:06.136184 [0] MAX Duty = 5031%(X100), DQS PI = 20
7393 10:52:06.139308 [0] MIN Duty = 4844%(X100), DQS PI = 50
7394 10:52:06.142709 [0] AVG Duty = 4937%(X100)
7395 10:52:06.142787
7396 10:52:06.142849 ==DQS 1 ==
7397 10:52:06.145960 Final DQS duty delay cell = 0
7398 10:52:06.149435 [0] MAX Duty = 5031%(X100), DQS PI = 36
7399 10:52:06.152758 [0] MIN Duty = 4938%(X100), DQS PI = 12
7400 10:52:06.152850 [0] AVG Duty = 4984%(X100)
7401 10:52:06.156166
7402 10:52:06.159570 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7403 10:52:06.159649
7404 10:52:06.162775 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7405 10:52:06.165944 [DutyScan_Calibration_Flow] ====Done====
7406 10:52:06.166025
7407 10:52:06.170192 [DutyScan_Calibration_Flow] k_type=3
7408 10:52:06.186430
7409 10:52:06.186512 ==DQM 0 ==
7410 10:52:06.189938 Final DQM duty delay cell = 0
7411 10:52:06.192923 [0] MAX Duty = 5156%(X100), DQS PI = 20
7412 10:52:06.196353 [0] MIN Duty = 4813%(X100), DQS PI = 50
7413 10:52:06.199879 [0] AVG Duty = 4984%(X100)
7414 10:52:06.199959
7415 10:52:06.200023 ==DQM 1 ==
7416 10:52:06.202877 Final DQM duty delay cell = 0
7417 10:52:06.206332 [0] MAX Duty = 5156%(X100), DQS PI = 60
7418 10:52:06.209448 [0] MIN Duty = 4907%(X100), DQS PI = 20
7419 10:52:06.212833 [0] AVG Duty = 5031%(X100)
7420 10:52:06.212914
7421 10:52:06.216225 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7422 10:52:06.216306
7423 10:52:06.219576 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7424 10:52:06.222899 [DutyScan_Calibration_Flow] ====Done====
7425 10:52:06.222995
7426 10:52:06.225781 [DutyScan_Calibration_Flow] k_type=2
7427 10:52:06.243184
7428 10:52:06.243265 ==DQ 0 ==
7429 10:52:06.246572 Final DQ duty delay cell = 0
7430 10:52:06.250083 [0] MAX Duty = 5156%(X100), DQS PI = 22
7431 10:52:06.253157 [0] MIN Duty = 4907%(X100), DQS PI = 52
7432 10:52:06.253240 [0] AVG Duty = 5031%(X100)
7433 10:52:06.253305
7434 10:52:06.256583 ==DQ 1 ==
7435 10:52:06.260163 Final DQ duty delay cell = 0
7436 10:52:06.263611 [0] MAX Duty = 5093%(X100), DQS PI = 8
7437 10:52:06.266455 [0] MIN Duty = 5031%(X100), DQS PI = 2
7438 10:52:06.266540 [0] AVG Duty = 5062%(X100)
7439 10:52:06.266604
7440 10:52:06.270213 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7441 10:52:06.270295
7442 10:52:06.273239 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7443 10:52:06.279920 [DutyScan_Calibration_Flow] ====Done====
7444 10:52:06.283383 nWR fixed to 30
7445 10:52:06.283492 [ModeRegInit_LP4] CH0 RK0
7446 10:52:06.286439 [ModeRegInit_LP4] CH0 RK1
7447 10:52:06.289838 [ModeRegInit_LP4] CH1 RK0
7448 10:52:06.289923 [ModeRegInit_LP4] CH1 RK1
7449 10:52:06.293324 match AC timing 5
7450 10:52:06.296274 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 10:52:06.300110 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 10:52:06.306300 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 10:52:06.309815 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 10:52:06.316154 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 10:52:06.316254 [MiockJmeterHQA]
7456 10:52:06.316359
7457 10:52:06.319656 [DramcMiockJmeter] u1RxGatingPI = 0
7458 10:52:06.322907 0 : 4253, 4026
7459 10:52:06.323026 4 : 4255, 4029
7460 10:52:06.323126 8 : 4255, 4029
7461 10:52:06.326499 12 : 4253, 4027
7462 10:52:06.326589 16 : 4255, 4030
7463 10:52:06.329388 20 : 4366, 4140
7464 10:52:06.329490 24 : 4257, 4029
7465 10:52:06.332941 28 : 4366, 4140
7466 10:52:06.333019 32 : 4258, 4029
7467 10:52:06.335977 36 : 4250, 4026
7468 10:52:06.336050 40 : 4257, 4029
7469 10:52:06.336112 44 : 4363, 4140
7470 10:52:06.339262 48 : 4361, 4137
7471 10:52:06.339382 52 : 4255, 4029
7472 10:52:06.342718 56 : 4250, 4027
7473 10:52:06.342790 60 : 4361, 4138
7474 10:52:06.346140 64 : 4249, 4027
7475 10:52:06.346214 68 : 4250, 4027
7476 10:52:06.346276 72 : 4252, 4027
7477 10:52:06.349234 76 : 4250, 4027
7478 10:52:06.349335 80 : 4250, 4027
7479 10:52:06.352668 84 : 4250, 4027
7480 10:52:06.352741 88 : 4250, 4026
7481 10:52:06.355905 92 : 4253, 4029
7482 10:52:06.355975 96 : 4368, 3234
7483 10:52:06.356037 100 : 4365, 0
7484 10:52:06.359480 104 : 4254, 0
7485 10:52:06.359554 108 : 4258, 0
7486 10:52:06.362873 112 : 4255, 0
7487 10:52:06.362947 116 : 4255, 0
7488 10:52:06.363016 120 : 4257, 0
7489 10:52:06.366259 124 : 4363, 0
7490 10:52:06.366328 128 : 4252, 0
7491 10:52:06.369677 132 : 4361, 0
7492 10:52:06.369752 136 : 4253, 0
7493 10:52:06.369821 140 : 4250, 0
7494 10:52:06.373105 144 : 4257, 0
7495 10:52:06.373172 148 : 4360, 0
7496 10:52:06.376000 152 : 4252, 0
7497 10:52:06.376072 156 : 4250, 0
7498 10:52:06.376134 160 : 4249, 0
7499 10:52:06.379663 164 : 4252, 0
7500 10:52:06.379737 168 : 4365, 0
7501 10:52:06.379804 172 : 4252, 0
7502 10:52:06.382888 176 : 4363, 0
7503 10:52:06.382983 180 : 4250, 0
7504 10:52:06.386243 184 : 4252, 0
7505 10:52:06.386315 188 : 4365, 0
7506 10:52:06.386376 192 : 4253, 0
7507 10:52:06.389765 196 : 4363, 0
7508 10:52:06.389833 200 : 4252, 0
7509 10:52:06.392669 204 : 4253, 0
7510 10:52:06.392765 208 : 4363, 0
7511 10:52:06.392857 212 : 4250, 137
7512 10:52:06.395754 216 : 4255, 3765
7513 10:52:06.395821 220 : 4252, 4027
7514 10:52:06.399215 224 : 4252, 4029
7515 10:52:06.399308 228 : 4257, 4034
7516 10:52:06.402811 232 : 4252, 4029
7517 10:52:06.402886 236 : 4250, 4027
7518 10:52:06.405749 240 : 4250, 4026
7519 10:52:06.405826 244 : 4255, 4032
7520 10:52:06.409446 248 : 4363, 4138
7521 10:52:06.409514 252 : 4361, 4137
7522 10:52:06.412904 256 : 4253, 4029
7523 10:52:06.412970 260 : 4254, 4030
7524 10:52:06.413031 264 : 4255, 4032
7525 10:52:06.415832 268 : 4363, 4137
7526 10:52:06.415903 272 : 4253, 4029
7527 10:52:06.419286 276 : 4363, 4140
7528 10:52:06.419429 280 : 4250, 4027
7529 10:52:06.422386 284 : 4250, 4026
7530 10:52:06.422455 288 : 4253, 4029
7531 10:52:06.425827 292 : 4360, 4137
7532 10:52:06.425901 296 : 4250, 4026
7533 10:52:06.429208 300 : 4363, 4140
7534 10:52:06.429282 304 : 4250, 4026
7535 10:52:06.432578 308 : 4250, 4026
7536 10:52:06.432656 312 : 4363, 4140
7537 10:52:06.435993 316 : 4250, 4027
7538 10:52:06.436065 320 : 4361, 4137
7539 10:52:06.436128 324 : 4255, 4029
7540 10:52:06.439403 328 : 4255, 4029
7541 10:52:06.439489 332 : 4255, 2818
7542 10:52:06.442882 336 : 4250, 24
7543 10:52:06.442976
7544 10:52:06.445715 MIOCK jitter meter ch=0
7545 10:52:06.445786
7546 10:52:06.445855 1T = (336-100) = 236 dly cells
7547 10:52:06.452522 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7548 10:52:06.452667 ==
7549 10:52:06.455940 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 10:52:06.459376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 10:52:06.462787 ==
7552 10:52:06.465607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 10:52:06.468993 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 10:52:06.475850 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 10:52:06.479306 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 10:52:06.489453 [CA 0] Center 44 (14~75) winsize 62
7557 10:52:06.492660 [CA 1] Center 44 (13~75) winsize 63
7558 10:52:06.496220 [CA 2] Center 40 (11~69) winsize 59
7559 10:52:06.499514 [CA 3] Center 39 (10~69) winsize 60
7560 10:52:06.503187 [CA 4] Center 38 (8~68) winsize 61
7561 10:52:06.506185 [CA 5] Center 37 (7~67) winsize 61
7562 10:52:06.506278
7563 10:52:06.509597 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 10:52:06.509667
7565 10:52:06.516281 [CATrainingPosCal] consider 1 rank data
7566 10:52:06.516357 u2DelayCellTimex100 = 275/100 ps
7567 10:52:06.522593 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7568 10:52:06.525988 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7569 10:52:06.529440 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7570 10:52:06.532722 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7571 10:52:06.535814 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7572 10:52:06.539270 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7573 10:52:06.539374
7574 10:52:06.542848 CA PerBit enable=1, Macro0, CA PI delay=37
7575 10:52:06.542944
7576 10:52:06.545736 [CBTSetCACLKResult] CA Dly = 37
7577 10:52:06.549203 CS Dly: 11 (0~42)
7578 10:52:06.552703 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 10:52:06.556383 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 10:52:06.556480 ==
7581 10:52:06.559015 Dram Type= 6, Freq= 0, CH_0, rank 1
7582 10:52:06.565778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 10:52:06.565886 ==
7584 10:52:06.569289 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7585 10:52:06.576034 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7586 10:52:06.579418 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7587 10:52:06.585555 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7588 10:52:06.593315 [CA 0] Center 43 (13~74) winsize 62
7589 10:52:06.596763 [CA 1] Center 43 (13~74) winsize 62
7590 10:52:06.599789 [CA 2] Center 39 (10~69) winsize 60
7591 10:52:06.603202 [CA 3] Center 38 (9~68) winsize 60
7592 10:52:06.607449 [CA 4] Center 37 (7~67) winsize 61
7593 10:52:06.610754 [CA 5] Center 37 (7~67) winsize 61
7594 10:52:06.610875
7595 10:52:06.613413 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7596 10:52:06.613494
7597 10:52:06.616831 [CATrainingPosCal] consider 2 rank data
7598 10:52:06.620227 u2DelayCellTimex100 = 275/100 ps
7599 10:52:06.626601 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7600 10:52:06.629957 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7601 10:52:06.633376 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7602 10:52:06.636518 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7603 10:52:06.639793 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7604 10:52:06.643293 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7605 10:52:06.643432
7606 10:52:06.646300 CA PerBit enable=1, Macro0, CA PI delay=37
7607 10:52:06.646396
7608 10:52:06.650256 [CBTSetCACLKResult] CA Dly = 37
7609 10:52:06.653074 CS Dly: 12 (0~44)
7610 10:52:06.656733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7611 10:52:06.659782 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7612 10:52:06.659878
7613 10:52:06.663368 ----->DramcWriteLeveling(PI) begin...
7614 10:52:06.663458 ==
7615 10:52:06.666630 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 10:52:06.673298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 10:52:06.673409 ==
7618 10:52:06.676563 Write leveling (Byte 0): 34 => 34
7619 10:52:06.676642 Write leveling (Byte 1): 28 => 28
7620 10:52:06.679872 DramcWriteLeveling(PI) end<-----
7621 10:52:06.679941
7622 10:52:06.679999 ==
7623 10:52:06.683219 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 10:52:06.689971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 10:52:06.690090 ==
7626 10:52:06.693111 [Gating] SW mode calibration
7627 10:52:06.700259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7628 10:52:06.703268 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7629 10:52:06.710025 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 10:52:06.713107 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 10:52:06.716569 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 10:52:06.723102 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 10:52:06.726632 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 10:52:06.730200 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7635 10:52:06.736943 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7636 10:52:06.739646 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 10:52:06.743204 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 10:52:06.749831 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 10:52:06.753324 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 10:52:06.756934 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7641 10:52:06.763207 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7642 10:52:06.766138 1 5 20 | B1->B0 | 3333 2323 | 1 1 | (1 0) (1 0)
7643 10:52:06.769520 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7644 10:52:06.773224 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 10:52:06.779584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 10:52:06.783083 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 10:52:06.785870 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 10:52:06.793302 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 10:52:06.796120 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7650 10:52:06.799440 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7651 10:52:06.805854 1 6 24 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
7652 10:52:06.809191 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 10:52:06.812734 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 10:52:06.819232 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 10:52:06.823030 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 10:52:06.825659 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 10:52:06.832949 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7658 10:52:06.835865 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7659 10:52:06.839219 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7660 10:52:06.845793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 10:52:06.849039 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 10:52:06.852411 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 10:52:06.859376 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 10:52:06.862202 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 10:52:06.866047 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 10:52:06.872372 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 10:52:06.875629 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 10:52:06.879565 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 10:52:06.885863 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 10:52:06.889093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 10:52:06.892318 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 10:52:06.898913 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7673 10:52:06.901908 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7674 10:52:06.905345 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7675 10:52:06.912168 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 10:52:06.912294 Total UI for P1: 0, mck2ui 16
7677 10:52:06.918826 best dqsien dly found for B0: ( 1, 9, 16)
7678 10:52:06.918903 Total UI for P1: 0, mck2ui 16
7679 10:52:06.921896 best dqsien dly found for B1: ( 1, 9, 20)
7680 10:52:06.928789 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7681 10:52:06.932342 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7682 10:52:06.932418
7683 10:52:06.935168 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7684 10:52:06.938719 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7685 10:52:06.942254 [Gating] SW calibration Done
7686 10:52:06.942334 ==
7687 10:52:06.945132 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 10:52:06.948826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 10:52:06.948910 ==
7690 10:52:06.951828 RX Vref Scan: 0
7691 10:52:06.951903
7692 10:52:06.951975 RX Vref 0 -> 0, step: 1
7693 10:52:06.952036
7694 10:52:06.955401 RX Delay 0 -> 252, step: 8
7695 10:52:06.958587 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7696 10:52:06.962009 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7697 10:52:06.968959 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7698 10:52:06.972105 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7699 10:52:06.975324 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7700 10:52:06.978277 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7701 10:52:06.982023 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7702 10:52:06.988945 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7703 10:52:06.991871 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7704 10:52:06.995282 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7705 10:52:06.998385 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7706 10:52:07.002031 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7707 10:52:07.008404 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7708 10:52:07.011586 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7709 10:52:07.015499 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7710 10:52:07.018832 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7711 10:52:07.018933 ==
7712 10:52:07.021933 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 10:52:07.028381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 10:52:07.028490 ==
7715 10:52:07.028594 DQS Delay:
7716 10:52:07.031881 DQS0 = 0, DQS1 = 0
7717 10:52:07.031978 DQM Delay:
7718 10:52:07.032082 DQM0 = 132, DQM1 = 125
7719 10:52:07.035495 DQ Delay:
7720 10:52:07.038777 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7721 10:52:07.041804 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7722 10:52:07.045214 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123
7723 10:52:07.048234 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7724 10:52:07.048307
7725 10:52:07.048407
7726 10:52:07.048468 ==
7727 10:52:07.052156 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 10:52:07.055397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 10:52:07.058431 ==
7730 10:52:07.058537
7731 10:52:07.058627
7732 10:52:07.058717 TX Vref Scan disable
7733 10:52:07.062084 == TX Byte 0 ==
7734 10:52:07.064999 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7735 10:52:07.068405 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7736 10:52:07.071936 == TX Byte 1 ==
7737 10:52:07.075565 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7738 10:52:07.078442 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7739 10:52:07.081939 ==
7740 10:52:07.084758 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 10:52:07.088079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 10:52:07.088158 ==
7743 10:52:07.102190
7744 10:52:07.105543 TX Vref early break, caculate TX vref
7745 10:52:07.108930 TX Vref=16, minBit 4, minWin=21, winSum=361
7746 10:52:07.112314 TX Vref=18, minBit 1, minWin=22, winSum=373
7747 10:52:07.115762 TX Vref=20, minBit 1, minWin=23, winSum=382
7748 10:52:07.118828 TX Vref=22, minBit 4, minWin=23, winSum=396
7749 10:52:07.122266 TX Vref=24, minBit 4, minWin=24, winSum=407
7750 10:52:07.129114 TX Vref=26, minBit 4, minWin=24, winSum=411
7751 10:52:07.132105 TX Vref=28, minBit 4, minWin=25, winSum=421
7752 10:52:07.135727 TX Vref=30, minBit 4, minWin=25, winSum=421
7753 10:52:07.138658 TX Vref=32, minBit 4, minWin=24, winSum=415
7754 10:52:07.142239 TX Vref=34, minBit 4, minWin=23, winSum=404
7755 10:52:07.145386 TX Vref=36, minBit 0, minWin=23, winSum=394
7756 10:52:07.152226 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 28
7757 10:52:07.152329
7758 10:52:07.155711 Final TX Range 0 Vref 28
7759 10:52:07.155785
7760 10:52:07.155853 ==
7761 10:52:07.159030 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 10:52:07.161887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 10:52:07.161984 ==
7764 10:52:07.162078
7765 10:52:07.162164
7766 10:52:07.165439 TX Vref Scan disable
7767 10:52:07.172146 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7768 10:52:07.172226 == TX Byte 0 ==
7769 10:52:07.175687 u2DelayCellOfst[0]=14 cells (4 PI)
7770 10:52:07.178714 u2DelayCellOfst[1]=17 cells (5 PI)
7771 10:52:07.181620 u2DelayCellOfst[2]=7 cells (2 PI)
7772 10:52:07.185063 u2DelayCellOfst[3]=14 cells (4 PI)
7773 10:52:07.188371 u2DelayCellOfst[4]=10 cells (3 PI)
7774 10:52:07.191977 u2DelayCellOfst[5]=0 cells (0 PI)
7775 10:52:07.195196 u2DelayCellOfst[6]=17 cells (5 PI)
7776 10:52:07.198814 u2DelayCellOfst[7]=17 cells (5 PI)
7777 10:52:07.202194 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7778 10:52:07.205127 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7779 10:52:07.208235 == TX Byte 1 ==
7780 10:52:07.211750 u2DelayCellOfst[8]=0 cells (0 PI)
7781 10:52:07.214837 u2DelayCellOfst[9]=3 cells (1 PI)
7782 10:52:07.218086 u2DelayCellOfst[10]=7 cells (2 PI)
7783 10:52:07.218222 u2DelayCellOfst[11]=3 cells (1 PI)
7784 10:52:07.221474 u2DelayCellOfst[12]=14 cells (4 PI)
7785 10:52:07.225072 u2DelayCellOfst[13]=14 cells (4 PI)
7786 10:52:07.228111 u2DelayCellOfst[14]=14 cells (4 PI)
7787 10:52:07.231702 u2DelayCellOfst[15]=10 cells (3 PI)
7788 10:52:07.238346 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7789 10:52:07.241750 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7790 10:52:07.241853 DramC Write-DBI on
7791 10:52:07.241961 ==
7792 10:52:07.244715 Dram Type= 6, Freq= 0, CH_0, rank 0
7793 10:52:07.251269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7794 10:52:07.251408 ==
7795 10:52:07.251518
7796 10:52:07.251583
7797 10:52:07.254779 TX Vref Scan disable
7798 10:52:07.254884 == TX Byte 0 ==
7799 10:52:07.261656 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7800 10:52:07.261777 == TX Byte 1 ==
7801 10:52:07.264816 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7802 10:52:07.267736 DramC Write-DBI off
7803 10:52:07.267820
7804 10:52:07.267885 [DATLAT]
7805 10:52:07.271417 Freq=1600, CH0 RK0
7806 10:52:07.271490
7807 10:52:07.271551 DATLAT Default: 0xf
7808 10:52:07.274932 0, 0xFFFF, sum = 0
7809 10:52:07.275003 1, 0xFFFF, sum = 0
7810 10:52:07.277702 2, 0xFFFF, sum = 0
7811 10:52:07.277777 3, 0xFFFF, sum = 0
7812 10:52:07.281462 4, 0xFFFF, sum = 0
7813 10:52:07.281542 5, 0xFFFF, sum = 0
7814 10:52:07.284769 6, 0xFFFF, sum = 0
7815 10:52:07.284849 7, 0xFFFF, sum = 0
7816 10:52:07.287657 8, 0xFFFF, sum = 0
7817 10:52:07.287754 9, 0xFFFF, sum = 0
7818 10:52:07.291124 10, 0xFFFF, sum = 0
7819 10:52:07.294839 11, 0xFFFF, sum = 0
7820 10:52:07.294920 12, 0xFFFF, sum = 0
7821 10:52:07.297705 13, 0xFFFF, sum = 0
7822 10:52:07.297780 14, 0x0, sum = 1
7823 10:52:07.301532 15, 0x0, sum = 2
7824 10:52:07.301616 16, 0x0, sum = 3
7825 10:52:07.304679 17, 0x0, sum = 4
7826 10:52:07.304757 best_step = 15
7827 10:52:07.304820
7828 10:52:07.304879 ==
7829 10:52:07.308660 Dram Type= 6, Freq= 0, CH_0, rank 0
7830 10:52:07.311136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7831 10:52:07.311214 ==
7832 10:52:07.314481 RX Vref Scan: 1
7833 10:52:07.314589
7834 10:52:07.317742 Set Vref Range= 24 -> 127
7835 10:52:07.317823
7836 10:52:07.317887 RX Vref 24 -> 127, step: 1
7837 10:52:07.317947
7838 10:52:07.321306 RX Delay 11 -> 252, step: 4
7839 10:52:07.321378
7840 10:52:07.324741 Set Vref, RX VrefLevel [Byte0]: 24
7841 10:52:07.327867 [Byte1]: 24
7842 10:52:07.330790
7843 10:52:07.330871 Set Vref, RX VrefLevel [Byte0]: 25
7844 10:52:07.334262 [Byte1]: 25
7845 10:52:07.338583
7846 10:52:07.338663 Set Vref, RX VrefLevel [Byte0]: 26
7847 10:52:07.341908 [Byte1]: 26
7848 10:52:07.346174
7849 10:52:07.346254 Set Vref, RX VrefLevel [Byte0]: 27
7850 10:52:07.349163 [Byte1]: 27
7851 10:52:07.353718
7852 10:52:07.353798 Set Vref, RX VrefLevel [Byte0]: 28
7853 10:52:07.356946 [Byte1]: 28
7854 10:52:07.361715
7855 10:52:07.361796 Set Vref, RX VrefLevel [Byte0]: 29
7856 10:52:07.367882 [Byte1]: 29
7857 10:52:07.367963
7858 10:52:07.371345 Set Vref, RX VrefLevel [Byte0]: 30
7859 10:52:07.374464 [Byte1]: 30
7860 10:52:07.374562
7861 10:52:07.377921 Set Vref, RX VrefLevel [Byte0]: 31
7862 10:52:07.380911 [Byte1]: 31
7863 10:52:07.384372
7864 10:52:07.384452 Set Vref, RX VrefLevel [Byte0]: 32
7865 10:52:07.387975 [Byte1]: 32
7866 10:52:07.392124
7867 10:52:07.392205 Set Vref, RX VrefLevel [Byte0]: 33
7868 10:52:07.394965 [Byte1]: 33
7869 10:52:07.399407
7870 10:52:07.399502 Set Vref, RX VrefLevel [Byte0]: 34
7871 10:52:07.402712 [Byte1]: 34
7872 10:52:07.406710
7873 10:52:07.406790 Set Vref, RX VrefLevel [Byte0]: 35
7874 10:52:07.410557 [Byte1]: 35
7875 10:52:07.414439
7876 10:52:07.414519 Set Vref, RX VrefLevel [Byte0]: 36
7877 10:52:07.417664 [Byte1]: 36
7878 10:52:07.422088
7879 10:52:07.422170 Set Vref, RX VrefLevel [Byte0]: 37
7880 10:52:07.425439 [Byte1]: 37
7881 10:52:07.430077
7882 10:52:07.430158 Set Vref, RX VrefLevel [Byte0]: 38
7883 10:52:07.433369 [Byte1]: 38
7884 10:52:07.437259
7885 10:52:07.437334 Set Vref, RX VrefLevel [Byte0]: 39
7886 10:52:07.440826 [Byte1]: 39
7887 10:52:07.444899
7888 10:52:07.444972 Set Vref, RX VrefLevel [Byte0]: 40
7889 10:52:07.448416 [Byte1]: 40
7890 10:52:07.452587
7891 10:52:07.452664 Set Vref, RX VrefLevel [Byte0]: 41
7892 10:52:07.456040 [Byte1]: 41
7893 10:52:07.460444
7894 10:52:07.460519 Set Vref, RX VrefLevel [Byte0]: 42
7895 10:52:07.463466 [Byte1]: 42
7896 10:52:07.467725
7897 10:52:07.467797 Set Vref, RX VrefLevel [Byte0]: 43
7898 10:52:07.471564 [Byte1]: 43
7899 10:52:07.475555
7900 10:52:07.475630 Set Vref, RX VrefLevel [Byte0]: 44
7901 10:52:07.479129 [Byte1]: 44
7902 10:52:07.483068
7903 10:52:07.483142 Set Vref, RX VrefLevel [Byte0]: 45
7904 10:52:07.486467 [Byte1]: 45
7905 10:52:07.490783
7906 10:52:07.490855 Set Vref, RX VrefLevel [Byte0]: 46
7907 10:52:07.493730 [Byte1]: 46
7908 10:52:07.498396
7909 10:52:07.498469 Set Vref, RX VrefLevel [Byte0]: 47
7910 10:52:07.501852 [Byte1]: 47
7911 10:52:07.506034
7912 10:52:07.506117 Set Vref, RX VrefLevel [Byte0]: 48
7913 10:52:07.511745 [Byte1]: 48
7914 10:52:07.513500
7915 10:52:07.513581 Set Vref, RX VrefLevel [Byte0]: 49
7916 10:52:07.517062 [Byte1]: 49
7917 10:52:07.521279
7918 10:52:07.521360 Set Vref, RX VrefLevel [Byte0]: 50
7919 10:52:07.524308 [Byte1]: 50
7920 10:52:07.528916
7921 10:52:07.528998 Set Vref, RX VrefLevel [Byte0]: 51
7922 10:52:07.532263 [Byte1]: 51
7923 10:52:07.536504
7924 10:52:07.536584 Set Vref, RX VrefLevel [Byte0]: 52
7925 10:52:07.539677 [Byte1]: 52
7926 10:52:07.544224
7927 10:52:07.544305 Set Vref, RX VrefLevel [Byte0]: 53
7928 10:52:07.547269 [Byte1]: 53
7929 10:52:07.551885
7930 10:52:07.551966 Set Vref, RX VrefLevel [Byte0]: 54
7931 10:52:07.554899 [Byte1]: 54
7932 10:52:07.559302
7933 10:52:07.559418 Set Vref, RX VrefLevel [Byte0]: 55
7934 10:52:07.562891 [Byte1]: 55
7935 10:52:07.567053
7936 10:52:07.567133 Set Vref, RX VrefLevel [Byte0]: 56
7937 10:52:07.570564 [Byte1]: 56
7938 10:52:07.574878
7939 10:52:07.574958 Set Vref, RX VrefLevel [Byte0]: 57
7940 10:52:07.577880 [Byte1]: 57
7941 10:52:07.582218
7942 10:52:07.582315 Set Vref, RX VrefLevel [Byte0]: 58
7943 10:52:07.585341 [Byte1]: 58
7944 10:52:07.590034
7945 10:52:07.590114 Set Vref, RX VrefLevel [Byte0]: 59
7946 10:52:07.592790 [Byte1]: 59
7947 10:52:07.597136
7948 10:52:07.597216 Set Vref, RX VrefLevel [Byte0]: 60
7949 10:52:07.600793 [Byte1]: 60
7950 10:52:07.605230
7951 10:52:07.605310 Set Vref, RX VrefLevel [Byte0]: 61
7952 10:52:07.608184 [Byte1]: 61
7953 10:52:07.612484
7954 10:52:07.612573 Set Vref, RX VrefLevel [Byte0]: 62
7955 10:52:07.615889 [Byte1]: 62
7956 10:52:07.620419
7957 10:52:07.620504 Set Vref, RX VrefLevel [Byte0]: 63
7958 10:52:07.623520 [Byte1]: 63
7959 10:52:07.627616
7960 10:52:07.627700 Set Vref, RX VrefLevel [Byte0]: 64
7961 10:52:07.630936 [Byte1]: 64
7962 10:52:07.635204
7963 10:52:07.635289 Set Vref, RX VrefLevel [Byte0]: 65
7964 10:52:07.638840 [Byte1]: 65
7965 10:52:07.643010
7966 10:52:07.643092 Set Vref, RX VrefLevel [Byte0]: 66
7967 10:52:07.646432 [Byte1]: 66
7968 10:52:07.651175
7969 10:52:07.651258 Set Vref, RX VrefLevel [Byte0]: 67
7970 10:52:07.653890 [Byte1]: 67
7971 10:52:07.658419
7972 10:52:07.658501 Set Vref, RX VrefLevel [Byte0]: 68
7973 10:52:07.661424 [Byte1]: 68
7974 10:52:07.666158
7975 10:52:07.666241 Set Vref, RX VrefLevel [Byte0]: 69
7976 10:52:07.668986 [Byte1]: 69
7977 10:52:07.673764
7978 10:52:07.673847 Set Vref, RX VrefLevel [Byte0]: 70
7979 10:52:07.676860 [Byte1]: 70
7980 10:52:07.681206
7981 10:52:07.681289 Set Vref, RX VrefLevel [Byte0]: 71
7982 10:52:07.684729 [Byte1]: 71
7983 10:52:07.688575
7984 10:52:07.688661 Set Vref, RX VrefLevel [Byte0]: 72
7985 10:52:07.692243 [Byte1]: 72
7986 10:52:07.696381
7987 10:52:07.696464 Set Vref, RX VrefLevel [Byte0]: 73
7988 10:52:07.699866 [Byte1]: 73
7989 10:52:07.704141
7990 10:52:07.704224 Set Vref, RX VrefLevel [Byte0]: 74
7991 10:52:07.707006 [Byte1]: 74
7992 10:52:07.711447
7993 10:52:07.711532 Set Vref, RX VrefLevel [Byte0]: 75
7994 10:52:07.714972 [Byte1]: 75
7995 10:52:07.718955
7996 10:52:07.719038 Set Vref, RX VrefLevel [Byte0]: 76
7997 10:52:07.722174 [Byte1]: 76
7998 10:52:07.726514
7999 10:52:07.726611 Set Vref, RX VrefLevel [Byte0]: 77
8000 10:52:07.729810 [Byte1]: 77
8001 10:52:07.734231
8002 10:52:07.734347 Final RX Vref Byte 0 = 61 to rank0
8003 10:52:07.737772 Final RX Vref Byte 1 = 63 to rank0
8004 10:52:07.741163 Final RX Vref Byte 0 = 61 to rank1
8005 10:52:07.743983 Final RX Vref Byte 1 = 63 to rank1==
8006 10:52:07.748186 Dram Type= 6, Freq= 0, CH_0, rank 0
8007 10:52:07.754383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 10:52:07.754486 ==
8009 10:52:07.754579 DQS Delay:
8010 10:52:07.757528 DQS0 = 0, DQS1 = 0
8011 10:52:07.757624 DQM Delay:
8012 10:52:07.757716 DQM0 = 129, DQM1 = 122
8013 10:52:07.761119 DQ Delay:
8014 10:52:07.764199 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
8015 10:52:07.767450 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8016 10:52:07.771181 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8017 10:52:07.774140 DQ12 =128, DQ13 =128, DQ14 =130, DQ15 =132
8018 10:52:07.774247
8019 10:52:07.774341
8020 10:52:07.774435
8021 10:52:07.777079 [DramC_TX_OE_Calibration] TA2
8022 10:52:07.780572 Original DQ_B0 (3 6) =30, OEN = 27
8023 10:52:07.783897 Original DQ_B1 (3 6) =30, OEN = 27
8024 10:52:07.787110 24, 0x0, End_B0=24 End_B1=24
8025 10:52:07.787217 25, 0x0, End_B0=25 End_B1=25
8026 10:52:07.790850 26, 0x0, End_B0=26 End_B1=26
8027 10:52:07.793836 27, 0x0, End_B0=27 End_B1=27
8028 10:52:07.797255 28, 0x0, End_B0=28 End_B1=28
8029 10:52:07.800502 29, 0x0, End_B0=29 End_B1=29
8030 10:52:07.800583 30, 0x0, End_B0=30 End_B1=30
8031 10:52:07.803558 31, 0x4141, End_B0=30 End_B1=30
8032 10:52:07.807043 Byte0 end_step=30 best_step=27
8033 10:52:07.810549 Byte1 end_step=30 best_step=27
8034 10:52:07.813547 Byte0 TX OE(2T, 0.5T) = (3, 3)
8035 10:52:07.817257 Byte1 TX OE(2T, 0.5T) = (3, 3)
8036 10:52:07.817355
8037 10:52:07.817448
8038 10:52:07.823844 [DQSOSCAuto] RK0, (LSB)MR18= 0x1407, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
8039 10:52:07.826554 CH0 RK0: MR19=303, MR18=1407
8040 10:52:07.833297 CH0_RK0: MR19=0x303, MR18=0x1407, DQSOSC=399, MR23=63, INC=23, DEC=15
8041 10:52:07.833381
8042 10:52:07.836758 ----->DramcWriteLeveling(PI) begin...
8043 10:52:07.836837 ==
8044 10:52:07.839993 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 10:52:07.843463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 10:52:07.843536 ==
8047 10:52:07.846553 Write leveling (Byte 0): 34 => 34
8048 10:52:07.849850 Write leveling (Byte 1): 25 => 25
8049 10:52:07.853859 DramcWriteLeveling(PI) end<-----
8050 10:52:07.853960
8051 10:52:07.854049 ==
8052 10:52:07.856773 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 10:52:07.860035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 10:52:07.860104 ==
8055 10:52:07.863243 [Gating] SW mode calibration
8056 10:52:07.869764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8057 10:52:07.876596 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8058 10:52:07.880274 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 10:52:07.886493 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 10:52:07.889761 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 10:52:07.893473 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8062 10:52:07.899528 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8063 10:52:07.903260 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8064 10:52:07.906597 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 10:52:07.913171 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 10:52:07.916621 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 10:52:07.919891 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 10:52:07.926677 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8069 10:52:07.930049 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8070 10:52:07.932850 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8071 10:52:07.936671 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8072 10:52:07.942892 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 10:52:07.946290 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 10:52:07.949509 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 10:52:07.956726 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 10:52:07.959676 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8077 10:52:07.962813 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8078 10:52:07.969678 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8079 10:52:07.972658 1 6 20 | B1->B0 | 3232 4646 | 1 0 | (1 1) (0 0)
8080 10:52:07.976149 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 10:52:07.983125 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 10:52:07.986029 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 10:52:07.989250 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 10:52:07.996627 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 10:52:07.999482 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 10:52:08.002723 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8087 10:52:08.009583 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8088 10:52:08.012921 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 10:52:08.016262 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 10:52:08.022571 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 10:52:08.025931 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 10:52:08.029247 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 10:52:08.035800 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 10:52:08.039074 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 10:52:08.042396 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 10:52:08.049295 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 10:52:08.052800 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 10:52:08.055605 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 10:52:08.062191 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 10:52:08.065806 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 10:52:08.068888 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8102 10:52:08.072537 Total UI for P1: 0, mck2ui 16
8103 10:52:08.075836 best dqsien dly found for B0: ( 1, 9, 8)
8104 10:52:08.079221 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8105 10:52:08.085745 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 10:52:08.088948 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 10:52:08.092361 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 10:52:08.095676 Total UI for P1: 0, mck2ui 16
8109 10:52:08.099099 best dqsien dly found for B1: ( 1, 9, 22)
8110 10:52:08.102423 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8111 10:52:08.105709 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8112 10:52:08.109042
8113 10:52:08.112074 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8114 10:52:08.115659 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8115 10:52:08.118714 [Gating] SW calibration Done
8116 10:52:08.118798 ==
8117 10:52:08.122168 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 10:52:08.125860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 10:52:08.125946 ==
8120 10:52:08.128660 RX Vref Scan: 0
8121 10:52:08.128745
8122 10:52:08.128811 RX Vref 0 -> 0, step: 1
8123 10:52:08.128874
8124 10:52:08.132331 RX Delay 0 -> 252, step: 8
8125 10:52:08.135728 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8126 10:52:08.138795 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8127 10:52:08.145007 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8128 10:52:08.148797 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8129 10:52:08.151654 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8130 10:52:08.155088 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8131 10:52:08.158370 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8132 10:52:08.164848 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8133 10:52:08.168222 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8134 10:52:08.171774 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8135 10:52:08.175293 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8136 10:52:08.178228 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8137 10:52:08.184797 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8138 10:52:08.188576 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8139 10:52:08.191930 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8140 10:52:08.194776 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8141 10:52:08.194898 ==
8142 10:52:08.198124 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 10:52:08.204895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 10:52:08.205002 ==
8145 10:52:08.205070 DQS Delay:
8146 10:52:08.208285 DQS0 = 0, DQS1 = 0
8147 10:52:08.208369 DQM Delay:
8148 10:52:08.211733 DQM0 = 130, DQM1 = 125
8149 10:52:08.211816 DQ Delay:
8150 10:52:08.214898 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8151 10:52:08.218301 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8152 10:52:08.221492 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
8153 10:52:08.224950 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
8154 10:52:08.225030
8155 10:52:08.225095
8156 10:52:08.225154 ==
8157 10:52:08.228216 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 10:52:08.234810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 10:52:08.234892 ==
8160 10:52:08.234956
8161 10:52:08.235016
8162 10:52:08.235073 TX Vref Scan disable
8163 10:52:08.238171 == TX Byte 0 ==
8164 10:52:08.241275 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8165 10:52:08.248126 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8166 10:52:08.248207 == TX Byte 1 ==
8167 10:52:08.251512 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8168 10:52:08.258390 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8169 10:52:08.258489 ==
8170 10:52:08.261679 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 10:52:08.265407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 10:52:08.265514 ==
8173 10:52:08.279200
8174 10:52:08.282769 TX Vref early break, caculate TX vref
8175 10:52:08.286100 TX Vref=16, minBit 0, minWin=22, winSum=369
8176 10:52:08.289413 TX Vref=18, minBit 0, minWin=23, winSum=383
8177 10:52:08.292787 TX Vref=20, minBit 2, minWin=23, winSum=387
8178 10:52:08.296240 TX Vref=22, minBit 3, minWin=24, winSum=395
8179 10:52:08.299035 TX Vref=24, minBit 4, minWin=24, winSum=404
8180 10:52:08.306302 TX Vref=26, minBit 4, minWin=24, winSum=410
8181 10:52:08.309510 TX Vref=28, minBit 0, minWin=25, winSum=418
8182 10:52:08.312357 TX Vref=30, minBit 0, minWin=25, winSum=416
8183 10:52:08.316000 TX Vref=32, minBit 0, minWin=25, winSum=412
8184 10:52:08.319221 TX Vref=34, minBit 4, minWin=24, winSum=405
8185 10:52:08.322385 TX Vref=36, minBit 4, minWin=23, winSum=392
8186 10:52:08.328989 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8187 10:52:08.329071
8188 10:52:08.332612 Final TX Range 0 Vref 28
8189 10:52:08.332707
8190 10:52:08.332777 ==
8191 10:52:08.335597 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 10:52:08.338958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 10:52:08.339036 ==
8194 10:52:08.339109
8195 10:52:08.339173
8196 10:52:08.342473 TX Vref Scan disable
8197 10:52:08.348845 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8198 10:52:08.348925 == TX Byte 0 ==
8199 10:52:08.352120 u2DelayCellOfst[0]=14 cells (4 PI)
8200 10:52:08.355755 u2DelayCellOfst[1]=17 cells (5 PI)
8201 10:52:08.358596 u2DelayCellOfst[2]=10 cells (3 PI)
8202 10:52:08.361809 u2DelayCellOfst[3]=10 cells (3 PI)
8203 10:52:08.365099 u2DelayCellOfst[4]=7 cells (2 PI)
8204 10:52:08.368478 u2DelayCellOfst[5]=0 cells (0 PI)
8205 10:52:08.371755 u2DelayCellOfst[6]=17 cells (5 PI)
8206 10:52:08.375209 u2DelayCellOfst[7]=17 cells (5 PI)
8207 10:52:08.378393 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8208 10:52:08.381777 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8209 10:52:08.385486 == TX Byte 1 ==
8210 10:52:08.388520 u2DelayCellOfst[8]=0 cells (0 PI)
8211 10:52:08.392230 u2DelayCellOfst[9]=0 cells (0 PI)
8212 10:52:08.395302 u2DelayCellOfst[10]=3 cells (1 PI)
8213 10:52:08.395441 u2DelayCellOfst[11]=0 cells (0 PI)
8214 10:52:08.398500 u2DelayCellOfst[12]=10 cells (3 PI)
8215 10:52:08.401945 u2DelayCellOfst[13]=10 cells (3 PI)
8216 10:52:08.405274 u2DelayCellOfst[14]=14 cells (4 PI)
8217 10:52:08.408330 u2DelayCellOfst[15]=10 cells (3 PI)
8218 10:52:08.415142 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8219 10:52:08.418399 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8220 10:52:08.418482 DramC Write-DBI on
8221 10:52:08.421768 ==
8222 10:52:08.421851 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 10:52:08.428552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 10:52:08.428628 ==
8225 10:52:08.428699
8226 10:52:08.428762
8227 10:52:08.431374 TX Vref Scan disable
8228 10:52:08.431492 == TX Byte 0 ==
8229 10:52:08.438633 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8230 10:52:08.438712 == TX Byte 1 ==
8231 10:52:08.441624 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8232 10:52:08.444739 DramC Write-DBI off
8233 10:52:08.444824
8234 10:52:08.444890 [DATLAT]
8235 10:52:08.448553 Freq=1600, CH0 RK1
8236 10:52:08.448627
8237 10:52:08.448690 DATLAT Default: 0xf
8238 10:52:08.451264 0, 0xFFFF, sum = 0
8239 10:52:08.451340 1, 0xFFFF, sum = 0
8240 10:52:08.454887 2, 0xFFFF, sum = 0
8241 10:52:08.454962 3, 0xFFFF, sum = 0
8242 10:52:08.458340 4, 0xFFFF, sum = 0
8243 10:52:08.458414 5, 0xFFFF, sum = 0
8244 10:52:08.461353 6, 0xFFFF, sum = 0
8245 10:52:08.461432 7, 0xFFFF, sum = 0
8246 10:52:08.465176 8, 0xFFFF, sum = 0
8247 10:52:08.465254 9, 0xFFFF, sum = 0
8248 10:52:08.468554 10, 0xFFFF, sum = 0
8249 10:52:08.471260 11, 0xFFFF, sum = 0
8250 10:52:08.471335 12, 0xFFFF, sum = 0
8251 10:52:08.474681 13, 0xFFFF, sum = 0
8252 10:52:08.474760 14, 0x0, sum = 1
8253 10:52:08.477988 15, 0x0, sum = 2
8254 10:52:08.478063 16, 0x0, sum = 3
8255 10:52:08.481559 17, 0x0, sum = 4
8256 10:52:08.481639 best_step = 15
8257 10:52:08.481700
8258 10:52:08.481763 ==
8259 10:52:08.484794 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 10:52:08.488009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 10:52:08.488105 ==
8262 10:52:08.491443 RX Vref Scan: 0
8263 10:52:08.491531
8264 10:52:08.494556 RX Vref 0 -> 0, step: 1
8265 10:52:08.494622
8266 10:52:08.494682 RX Delay 11 -> 252, step: 4
8267 10:52:08.502082 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8268 10:52:08.504948 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8269 10:52:08.508083 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8270 10:52:08.511846 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8271 10:52:08.515093 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8272 10:52:08.521871 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8273 10:52:08.524966 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8274 10:52:08.528350 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8275 10:52:08.531494 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8276 10:52:08.534951 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8277 10:52:08.541581 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8278 10:52:08.545248 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8279 10:52:08.548536 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8280 10:52:08.551493 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8281 10:52:08.555013 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8282 10:52:08.561350 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8283 10:52:08.561425 ==
8284 10:52:08.564933 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 10:52:08.568298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 10:52:08.568376 ==
8287 10:52:08.568440 DQS Delay:
8288 10:52:08.571709 DQS0 = 0, DQS1 = 0
8289 10:52:08.571783 DQM Delay:
8290 10:52:08.574690 DQM0 = 127, DQM1 = 122
8291 10:52:08.574765 DQ Delay:
8292 10:52:08.578337 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8293 10:52:08.581960 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =136
8294 10:52:08.584753 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8295 10:52:08.588274 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8296 10:52:08.591437
8297 10:52:08.591517
8298 10:52:08.591581
8299 10:52:08.591639 [DramC_TX_OE_Calibration] TA2
8300 10:52:08.594972 Original DQ_B0 (3 6) =30, OEN = 27
8301 10:52:08.597876 Original DQ_B1 (3 6) =30, OEN = 27
8302 10:52:08.601200 24, 0x0, End_B0=24 End_B1=24
8303 10:52:08.604639 25, 0x0, End_B0=25 End_B1=25
8304 10:52:08.608337 26, 0x0, End_B0=26 End_B1=26
8305 10:52:08.608419 27, 0x0, End_B0=27 End_B1=27
8306 10:52:08.611228 28, 0x0, End_B0=28 End_B1=28
8307 10:52:08.615061 29, 0x0, End_B0=29 End_B1=29
8308 10:52:08.617879 30, 0x0, End_B0=30 End_B1=30
8309 10:52:08.621318 31, 0x4141, End_B0=30 End_B1=30
8310 10:52:08.625013 Byte0 end_step=30 best_step=27
8311 10:52:08.625094 Byte1 end_step=30 best_step=27
8312 10:52:08.627805 Byte0 TX OE(2T, 0.5T) = (3, 3)
8313 10:52:08.631458 Byte1 TX OE(2T, 0.5T) = (3, 3)
8314 10:52:08.631567
8315 10:52:08.631631
8316 10:52:08.641270 [DQSOSCAuto] RK1, (LSB)MR18= 0x1609, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
8317 10:52:08.641355 CH0 RK1: MR19=303, MR18=1609
8318 10:52:08.647455 CH0_RK1: MR19=0x303, MR18=0x1609, DQSOSC=398, MR23=63, INC=23, DEC=15
8319 10:52:08.651483 [RxdqsGatingPostProcess] freq 1600
8320 10:52:08.657348 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8321 10:52:08.661021 best DQS0 dly(2T, 0.5T) = (1, 1)
8322 10:52:08.664546 best DQS1 dly(2T, 0.5T) = (1, 1)
8323 10:52:08.667556 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8324 10:52:08.670737 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8325 10:52:08.670817 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 10:52:08.674003 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 10:52:08.677581 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 10:52:08.680652 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 10:52:08.684343 Pre-setting of DQS Precalculation
8330 10:52:08.690907 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8331 10:52:08.690988 ==
8332 10:52:08.694356 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 10:52:08.698000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 10:52:08.698081 ==
8335 10:52:08.704282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 10:52:08.707529 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 10:52:08.710818 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 10:52:08.717645 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 10:52:08.726118 [CA 0] Center 43 (14~72) winsize 59
8340 10:52:08.729219 [CA 1] Center 43 (14~72) winsize 59
8341 10:52:08.732735 [CA 2] Center 38 (10~67) winsize 58
8342 10:52:08.735861 [CA 3] Center 37 (8~66) winsize 59
8343 10:52:08.739298 [CA 4] Center 38 (9~68) winsize 60
8344 10:52:08.742764 [CA 5] Center 37 (9~66) winsize 58
8345 10:52:08.742871
8346 10:52:08.745935 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 10:52:08.746034
8348 10:52:08.749248 [CATrainingPosCal] consider 1 rank data
8349 10:52:08.752988 u2DelayCellTimex100 = 275/100 ps
8350 10:52:08.755683 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8351 10:52:08.762405 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8352 10:52:08.765788 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8353 10:52:08.769177 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8354 10:52:08.772703 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 10:52:08.776113 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8356 10:52:08.776209
8357 10:52:08.778878 CA PerBit enable=1, Macro0, CA PI delay=37
8358 10:52:08.778982
8359 10:52:08.782239 [CBTSetCACLKResult] CA Dly = 37
8360 10:52:08.785581 CS Dly: 9 (0~40)
8361 10:52:08.788946 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 10:52:08.792384 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 10:52:08.792471 ==
8364 10:52:08.795974 Dram Type= 6, Freq= 0, CH_1, rank 1
8365 10:52:08.799037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 10:52:08.802310 ==
8367 10:52:08.805802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 10:52:08.809135 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 10:52:08.815851 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 10:52:08.818876 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 10:52:08.829199 [CA 0] Center 42 (13~72) winsize 60
8372 10:52:08.832366 [CA 1] Center 42 (14~71) winsize 58
8373 10:52:08.836018 [CA 2] Center 37 (8~66) winsize 59
8374 10:52:08.838797 [CA 3] Center 36 (7~66) winsize 60
8375 10:52:08.842842 [CA 4] Center 37 (8~67) winsize 60
8376 10:52:08.845721 [CA 5] Center 36 (7~66) winsize 60
8377 10:52:08.845820
8378 10:52:08.849220 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8379 10:52:08.849324
8380 10:52:08.852247 [CATrainingPosCal] consider 2 rank data
8381 10:52:08.855550 u2DelayCellTimex100 = 275/100 ps
8382 10:52:08.858885 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8383 10:52:08.865466 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8384 10:52:08.869226 CA2 delay=38 (10~66),Diff = 1 PI (3 cell)
8385 10:52:08.872252 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8386 10:52:08.875489 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8387 10:52:08.879331 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8388 10:52:08.879467
8389 10:52:08.882205 CA PerBit enable=1, Macro0, CA PI delay=37
8390 10:52:08.882304
8391 10:52:08.885610 [CBTSetCACLKResult] CA Dly = 37
8392 10:52:08.888898 CS Dly: 11 (0~44)
8393 10:52:08.892239 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 10:52:08.895386 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 10:52:08.895492
8396 10:52:08.898639 ----->DramcWriteLeveling(PI) begin...
8397 10:52:08.898750 ==
8398 10:52:08.902005 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 10:52:08.908689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 10:52:08.908777 ==
8401 10:52:08.912203 Write leveling (Byte 0): 25 => 25
8402 10:52:08.912283 Write leveling (Byte 1): 28 => 28
8403 10:52:08.915475 DramcWriteLeveling(PI) end<-----
8404 10:52:08.915547
8405 10:52:08.915625 ==
8406 10:52:08.918571 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 10:52:08.925166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 10:52:08.925273 ==
8409 10:52:08.928942 [Gating] SW mode calibration
8410 10:52:08.935229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8411 10:52:08.938552 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8412 10:52:08.945233 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 10:52:08.948834 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 10:52:08.951580 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 10:52:08.958520 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 10:52:08.961768 1 4 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8417 10:52:08.965024 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 10:52:08.971719 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 10:52:08.975047 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 10:52:08.978436 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 10:52:08.984641 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 10:52:08.988036 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 10:52:08.991943 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 10:52:08.998446 1 5 16 | B1->B0 | 2727 2f2f | 0 0 | (1 0) (0 1)
8425 10:52:09.001579 1 5 20 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
8426 10:52:09.004991 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 10:52:09.011636 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 10:52:09.014428 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 10:52:09.017883 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 10:52:09.024487 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 10:52:09.028186 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 10:52:09.031237 1 6 16 | B1->B0 | 3f3f 3636 | 0 0 | (0 0) (0 0)
8433 10:52:09.034575 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 10:52:09.041596 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 10:52:09.044399 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 10:52:09.047829 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 10:52:09.054607 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 10:52:09.058005 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 10:52:09.061425 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8440 10:52:09.067959 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 10:52:09.071080 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8442 10:52:09.074793 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 10:52:09.081607 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 10:52:09.084848 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 10:52:09.087686 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 10:52:09.094772 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 10:52:09.097946 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 10:52:09.101109 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 10:52:09.107941 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 10:52:09.111400 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 10:52:09.114381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 10:52:09.121556 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 10:52:09.124295 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 10:52:09.127562 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 10:52:09.134605 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8456 10:52:09.137776 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 10:52:09.141015 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8458 10:52:09.144434 Total UI for P1: 0, mck2ui 16
8459 10:52:09.147382 best dqsien dly found for B0: ( 1, 9, 16)
8460 10:52:09.150611 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 10:52:09.153972 Total UI for P1: 0, mck2ui 16
8462 10:52:09.157693 best dqsien dly found for B1: ( 1, 9, 16)
8463 10:52:09.164092 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8464 10:52:09.167788 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8465 10:52:09.167891
8466 10:52:09.170461 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8467 10:52:09.173839 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8468 10:52:09.177232 [Gating] SW calibration Done
8469 10:52:09.177332 ==
8470 10:52:09.180764 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 10:52:09.184048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 10:52:09.184221 ==
8473 10:52:09.187311 RX Vref Scan: 0
8474 10:52:09.187452
8475 10:52:09.187544 RX Vref 0 -> 0, step: 1
8476 10:52:09.187630
8477 10:52:09.190662 RX Delay 0 -> 252, step: 8
8478 10:52:09.194395 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8479 10:52:09.200704 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8480 10:52:09.203971 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8481 10:52:09.207250 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8482 10:52:09.210818 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8483 10:52:09.214069 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8484 10:52:09.217167 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8485 10:52:09.223649 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8486 10:52:09.226874 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8487 10:52:09.230754 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8488 10:52:09.233793 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8489 10:52:09.237161 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8490 10:52:09.243564 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8491 10:52:09.247313 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8492 10:52:09.250203 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8493 10:52:09.253802 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8494 10:52:09.253884 ==
8495 10:52:09.257238 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 10:52:09.263829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 10:52:09.263911 ==
8498 10:52:09.263975 DQS Delay:
8499 10:52:09.266752 DQS0 = 0, DQS1 = 0
8500 10:52:09.266833 DQM Delay:
8501 10:52:09.270150 DQM0 = 135, DQM1 = 127
8502 10:52:09.270231 DQ Delay:
8503 10:52:09.273326 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8504 10:52:09.276641 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8505 10:52:09.280305 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8506 10:52:09.283476 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8507 10:52:09.283558
8508 10:52:09.283622
8509 10:52:09.283680 ==
8510 10:52:09.286616 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 10:52:09.293303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 10:52:09.293385 ==
8513 10:52:09.293449
8514 10:52:09.293507
8515 10:52:09.293564 TX Vref Scan disable
8516 10:52:09.296642 == TX Byte 0 ==
8517 10:52:09.300541 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8518 10:52:09.303602 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8519 10:52:09.306751 == TX Byte 1 ==
8520 10:52:09.310400 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8521 10:52:09.316976 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8522 10:52:09.317057 ==
8523 10:52:09.320437 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 10:52:09.323431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 10:52:09.323513 ==
8526 10:52:09.335764
8527 10:52:09.339086 TX Vref early break, caculate TX vref
8528 10:52:09.342353 TX Vref=16, minBit 8, minWin=20, winSum=365
8529 10:52:09.345647 TX Vref=18, minBit 8, minWin=21, winSum=369
8530 10:52:09.349117 TX Vref=20, minBit 8, minWin=22, winSum=384
8531 10:52:09.352403 TX Vref=22, minBit 8, minWin=22, winSum=392
8532 10:52:09.355978 TX Vref=24, minBit 8, minWin=23, winSum=404
8533 10:52:09.362272 TX Vref=26, minBit 8, minWin=24, winSum=411
8534 10:52:09.365801 TX Vref=28, minBit 8, minWin=24, winSum=417
8535 10:52:09.369072 TX Vref=30, minBit 8, minWin=25, winSum=418
8536 10:52:09.372037 TX Vref=32, minBit 8, minWin=24, winSum=408
8537 10:52:09.375748 TX Vref=34, minBit 11, minWin=23, winSum=396
8538 10:52:09.382523 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 30
8539 10:52:09.382605
8540 10:52:09.385797 Final TX Range 0 Vref 30
8541 10:52:09.385879
8542 10:52:09.385944 ==
8543 10:52:09.389061 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 10:52:09.392289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 10:52:09.392370 ==
8546 10:52:09.392434
8547 10:52:09.392492
8548 10:52:09.395650 TX Vref Scan disable
8549 10:52:09.402193 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8550 10:52:09.402274 == TX Byte 0 ==
8551 10:52:09.405415 u2DelayCellOfst[0]=17 cells (5 PI)
8552 10:52:09.408880 u2DelayCellOfst[1]=14 cells (4 PI)
8553 10:52:09.411907 u2DelayCellOfst[2]=0 cells (0 PI)
8554 10:52:09.415104 u2DelayCellOfst[3]=7 cells (2 PI)
8555 10:52:09.418621 u2DelayCellOfst[4]=10 cells (3 PI)
8556 10:52:09.421899 u2DelayCellOfst[5]=17 cells (5 PI)
8557 10:52:09.425223 u2DelayCellOfst[6]=17 cells (5 PI)
8558 10:52:09.428260 u2DelayCellOfst[7]=7 cells (2 PI)
8559 10:52:09.431664 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8560 10:52:09.435141 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8561 10:52:09.438160 == TX Byte 1 ==
8562 10:52:09.441690 u2DelayCellOfst[8]=0 cells (0 PI)
8563 10:52:09.441768 u2DelayCellOfst[9]=3 cells (1 PI)
8564 10:52:09.445103 u2DelayCellOfst[10]=10 cells (3 PI)
8565 10:52:09.448292 u2DelayCellOfst[11]=7 cells (2 PI)
8566 10:52:09.451656 u2DelayCellOfst[12]=14 cells (4 PI)
8567 10:52:09.454956 u2DelayCellOfst[13]=14 cells (4 PI)
8568 10:52:09.458168 u2DelayCellOfst[14]=17 cells (5 PI)
8569 10:52:09.461612 u2DelayCellOfst[15]=17 cells (5 PI)
8570 10:52:09.464665 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8571 10:52:09.472050 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8572 10:52:09.472132 DramC Write-DBI on
8573 10:52:09.472197 ==
8574 10:52:09.474724 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 10:52:09.482108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 10:52:09.482190 ==
8577 10:52:09.482255
8578 10:52:09.482316
8579 10:52:09.482373 TX Vref Scan disable
8580 10:52:09.485294 == TX Byte 0 ==
8581 10:52:09.488674 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8582 10:52:09.491756 == TX Byte 1 ==
8583 10:52:09.495456 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8584 10:52:09.498465 DramC Write-DBI off
8585 10:52:09.498545
8586 10:52:09.498609 [DATLAT]
8587 10:52:09.498668 Freq=1600, CH1 RK0
8588 10:52:09.498726
8589 10:52:09.502207 DATLAT Default: 0xf
8590 10:52:09.502345 0, 0xFFFF, sum = 0
8591 10:52:09.505174 1, 0xFFFF, sum = 0
8592 10:52:09.508744 2, 0xFFFF, sum = 0
8593 10:52:09.508841 3, 0xFFFF, sum = 0
8594 10:52:09.511461 4, 0xFFFF, sum = 0
8595 10:52:09.511544 5, 0xFFFF, sum = 0
8596 10:52:09.514881 6, 0xFFFF, sum = 0
8597 10:52:09.514955 7, 0xFFFF, sum = 0
8598 10:52:09.518537 8, 0xFFFF, sum = 0
8599 10:52:09.518610 9, 0xFFFF, sum = 0
8600 10:52:09.521906 10, 0xFFFF, sum = 0
8601 10:52:09.521980 11, 0xFFFF, sum = 0
8602 10:52:09.525146 12, 0xFFFF, sum = 0
8603 10:52:09.525231 13, 0xFFFF, sum = 0
8604 10:52:09.528176 14, 0x0, sum = 1
8605 10:52:09.528259 15, 0x0, sum = 2
8606 10:52:09.531729 16, 0x0, sum = 3
8607 10:52:09.531803 17, 0x0, sum = 4
8608 10:52:09.534946 best_step = 15
8609 10:52:09.535022
8610 10:52:09.535085 ==
8611 10:52:09.538350 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 10:52:09.541571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 10:52:09.541646 ==
8614 10:52:09.541708 RX Vref Scan: 1
8615 10:52:09.544967
8616 10:52:09.545040 Set Vref Range= 24 -> 127
8617 10:52:09.545101
8618 10:52:09.548980 RX Vref 24 -> 127, step: 1
8619 10:52:09.549049
8620 10:52:09.551635 RX Delay 11 -> 252, step: 4
8621 10:52:09.551706
8622 10:52:09.555453 Set Vref, RX VrefLevel [Byte0]: 24
8623 10:52:09.558393 [Byte1]: 24
8624 10:52:09.558465
8625 10:52:09.561607 Set Vref, RX VrefLevel [Byte0]: 25
8626 10:52:09.564667 [Byte1]: 25
8627 10:52:09.564749
8628 10:52:09.568450 Set Vref, RX VrefLevel [Byte0]: 26
8629 10:52:09.571947 [Byte1]: 26
8630 10:52:09.575697
8631 10:52:09.575769 Set Vref, RX VrefLevel [Byte0]: 27
8632 10:52:09.578649 [Byte1]: 27
8633 10:52:09.583008
8634 10:52:09.583089 Set Vref, RX VrefLevel [Byte0]: 28
8635 10:52:09.586468 [Byte1]: 28
8636 10:52:09.590707
8637 10:52:09.590824 Set Vref, RX VrefLevel [Byte0]: 29
8638 10:52:09.594354 [Byte1]: 29
8639 10:52:09.598296
8640 10:52:09.598404 Set Vref, RX VrefLevel [Byte0]: 30
8641 10:52:09.601738 [Byte1]: 30
8642 10:52:09.606019
8643 10:52:09.606117 Set Vref, RX VrefLevel [Byte0]: 31
8644 10:52:09.609424 [Byte1]: 31
8645 10:52:09.613492
8646 10:52:09.613596 Set Vref, RX VrefLevel [Byte0]: 32
8647 10:52:09.617236 [Byte1]: 32
8648 10:52:09.621182
8649 10:52:09.621287 Set Vref, RX VrefLevel [Byte0]: 33
8650 10:52:09.624813 [Byte1]: 33
8651 10:52:09.628817
8652 10:52:09.628922 Set Vref, RX VrefLevel [Byte0]: 34
8653 10:52:09.632339 [Byte1]: 34
8654 10:52:09.636443
8655 10:52:09.636542 Set Vref, RX VrefLevel [Byte0]: 35
8656 10:52:09.639679 [Byte1]: 35
8657 10:52:09.644340
8658 10:52:09.644440 Set Vref, RX VrefLevel [Byte0]: 36
8659 10:52:09.647324 [Byte1]: 36
8660 10:52:09.651662
8661 10:52:09.651764 Set Vref, RX VrefLevel [Byte0]: 37
8662 10:52:09.655009 [Byte1]: 37
8663 10:52:09.659486
8664 10:52:09.659561 Set Vref, RX VrefLevel [Byte0]: 38
8665 10:52:09.662628 [Byte1]: 38
8666 10:52:09.667140
8667 10:52:09.667247 Set Vref, RX VrefLevel [Byte0]: 39
8668 10:52:09.670518 [Byte1]: 39
8669 10:52:09.675432
8670 10:52:09.675513 Set Vref, RX VrefLevel [Byte0]: 40
8671 10:52:09.678137 [Byte1]: 40
8672 10:52:09.682079
8673 10:52:09.682178 Set Vref, RX VrefLevel [Byte0]: 41
8674 10:52:09.688750 [Byte1]: 41
8675 10:52:09.688857
8676 10:52:09.692074 Set Vref, RX VrefLevel [Byte0]: 42
8677 10:52:09.695634 [Byte1]: 42
8678 10:52:09.695704
8679 10:52:09.698503 Set Vref, RX VrefLevel [Byte0]: 43
8680 10:52:09.702141 [Byte1]: 43
8681 10:52:09.702229
8682 10:52:09.705082 Set Vref, RX VrefLevel [Byte0]: 44
8683 10:52:09.708358 [Byte1]: 44
8684 10:52:09.712776
8685 10:52:09.712874 Set Vref, RX VrefLevel [Byte0]: 45
8686 10:52:09.715953 [Byte1]: 45
8687 10:52:09.720425
8688 10:52:09.720523 Set Vref, RX VrefLevel [Byte0]: 46
8689 10:52:09.723672 [Byte1]: 46
8690 10:52:09.727961
8691 10:52:09.728032 Set Vref, RX VrefLevel [Byte0]: 47
8692 10:52:09.731443 [Byte1]: 47
8693 10:52:09.735182
8694 10:52:09.735279 Set Vref, RX VrefLevel [Byte0]: 48
8695 10:52:09.739155 [Byte1]: 48
8696 10:52:09.743138
8697 10:52:09.743235 Set Vref, RX VrefLevel [Byte0]: 49
8698 10:52:09.746275 [Byte1]: 49
8699 10:52:09.750555
8700 10:52:09.750637 Set Vref, RX VrefLevel [Byte0]: 50
8701 10:52:09.754192 [Byte1]: 50
8702 10:52:09.758181
8703 10:52:09.758262 Set Vref, RX VrefLevel [Byte0]: 51
8704 10:52:09.761962 [Byte1]: 51
8705 10:52:09.765994
8706 10:52:09.766089 Set Vref, RX VrefLevel [Byte0]: 52
8707 10:52:09.769336 [Byte1]: 52
8708 10:52:09.773829
8709 10:52:09.773909 Set Vref, RX VrefLevel [Byte0]: 53
8710 10:52:09.776862 [Byte1]: 53
8711 10:52:09.781306
8712 10:52:09.781386 Set Vref, RX VrefLevel [Byte0]: 54
8713 10:52:09.784983 [Byte1]: 54
8714 10:52:09.788757
8715 10:52:09.788869 Set Vref, RX VrefLevel [Byte0]: 55
8716 10:52:09.791926 [Byte1]: 55
8717 10:52:09.796209
8718 10:52:09.796285 Set Vref, RX VrefLevel [Byte0]: 56
8719 10:52:09.799521 [Byte1]: 56
8720 10:52:09.804213
8721 10:52:09.804315 Set Vref, RX VrefLevel [Byte0]: 57
8722 10:52:09.807439 [Byte1]: 57
8723 10:52:09.811644
8724 10:52:09.811755 Set Vref, RX VrefLevel [Byte0]: 58
8725 10:52:09.815064 [Byte1]: 58
8726 10:52:09.819285
8727 10:52:09.819392 Set Vref, RX VrefLevel [Byte0]: 59
8728 10:52:09.822399 [Byte1]: 59
8729 10:52:09.826756
8730 10:52:09.826838 Set Vref, RX VrefLevel [Byte0]: 60
8731 10:52:09.830396 [Byte1]: 60
8732 10:52:09.834480
8733 10:52:09.834562 Set Vref, RX VrefLevel [Byte0]: 61
8734 10:52:09.837823 [Byte1]: 61
8735 10:52:09.841921
8736 10:52:09.842003 Set Vref, RX VrefLevel [Byte0]: 62
8737 10:52:09.845200 [Byte1]: 62
8738 10:52:09.849975
8739 10:52:09.850057 Set Vref, RX VrefLevel [Byte0]: 63
8740 10:52:09.853396 [Byte1]: 63
8741 10:52:09.857624
8742 10:52:09.857706 Set Vref, RX VrefLevel [Byte0]: 64
8743 10:52:09.860405 [Byte1]: 64
8744 10:52:09.864928
8745 10:52:09.865045 Set Vref, RX VrefLevel [Byte0]: 65
8746 10:52:09.867895 [Byte1]: 65
8747 10:52:09.872208
8748 10:52:09.872290 Set Vref, RX VrefLevel [Byte0]: 66
8749 10:52:09.875543 [Byte1]: 66
8750 10:52:09.880377
8751 10:52:09.880494 Set Vref, RX VrefLevel [Byte0]: 67
8752 10:52:09.883263 [Byte1]: 67
8753 10:52:09.888154
8754 10:52:09.888260 Set Vref, RX VrefLevel [Byte0]: 68
8755 10:52:09.891494 [Byte1]: 68
8756 10:52:09.895251
8757 10:52:09.895337 Set Vref, RX VrefLevel [Byte0]: 69
8758 10:52:09.898411 [Byte1]: 69
8759 10:52:09.903111
8760 10:52:09.903186 Set Vref, RX VrefLevel [Byte0]: 70
8761 10:52:09.906689 [Byte1]: 70
8762 10:52:09.910634
8763 10:52:09.910711 Set Vref, RX VrefLevel [Byte0]: 71
8764 10:52:09.913672 [Byte1]: 71
8765 10:52:09.918062
8766 10:52:09.918137 Set Vref, RX VrefLevel [Byte0]: 72
8767 10:52:09.921519 [Byte1]: 72
8768 10:52:09.925601
8769 10:52:09.925676 Final RX Vref Byte 0 = 60 to rank0
8770 10:52:09.929236 Final RX Vref Byte 1 = 58 to rank0
8771 10:52:09.932615 Final RX Vref Byte 0 = 60 to rank1
8772 10:52:09.935578 Final RX Vref Byte 1 = 58 to rank1==
8773 10:52:09.939096 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 10:52:09.945978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 10:52:09.946055 ==
8776 10:52:09.946123 DQS Delay:
8777 10:52:09.946182 DQS0 = 0, DQS1 = 0
8778 10:52:09.948813 DQM Delay:
8779 10:52:09.948879 DQM0 = 131, DQM1 = 124
8780 10:52:09.952162 DQ Delay:
8781 10:52:09.955515 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8782 10:52:09.958868 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8783 10:52:09.962039 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8784 10:52:09.965517 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8785 10:52:09.965594
8786 10:52:09.965656
8787 10:52:09.965713
8788 10:52:09.969132 [DramC_TX_OE_Calibration] TA2
8789 10:52:09.972531 Original DQ_B0 (3 6) =30, OEN = 27
8790 10:52:09.975736 Original DQ_B1 (3 6) =30, OEN = 27
8791 10:52:09.979204 24, 0x0, End_B0=24 End_B1=24
8792 10:52:09.979273 25, 0x0, End_B0=25 End_B1=25
8793 10:52:09.982172 26, 0x0, End_B0=26 End_B1=26
8794 10:52:09.985637 27, 0x0, End_B0=27 End_B1=27
8795 10:52:09.988763 28, 0x0, End_B0=28 End_B1=28
8796 10:52:09.991942 29, 0x0, End_B0=29 End_B1=29
8797 10:52:09.992014 30, 0x0, End_B0=30 End_B1=30
8798 10:52:09.995671 31, 0x4141, End_B0=30 End_B1=30
8799 10:52:09.998887 Byte0 end_step=30 best_step=27
8800 10:52:10.002280 Byte1 end_step=30 best_step=27
8801 10:52:10.005351 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 10:52:10.008586 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 10:52:10.008655
8804 10:52:10.008721
8805 10:52:10.015219 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8806 10:52:10.018805 CH1 RK0: MR19=303, MR18=1701
8807 10:52:10.025219 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8808 10:52:10.025289
8809 10:52:10.028561 ----->DramcWriteLeveling(PI) begin...
8810 10:52:10.028630 ==
8811 10:52:10.031938 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 10:52:10.035645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 10:52:10.035726 ==
8814 10:52:10.038410 Write leveling (Byte 0): 25 => 25
8815 10:52:10.041855 Write leveling (Byte 1): 27 => 27
8816 10:52:10.045413 DramcWriteLeveling(PI) end<-----
8817 10:52:10.045480
8818 10:52:10.045540 ==
8819 10:52:10.049058 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 10:52:10.051794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 10:52:10.051863 ==
8822 10:52:10.054954 [Gating] SW mode calibration
8823 10:52:10.061497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 10:52:10.068617 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 10:52:10.072506 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 10:52:10.075290 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 10:52:10.081835 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8828 10:52:10.085261 1 4 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8829 10:52:10.088309 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 10:52:10.095012 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 10:52:10.098381 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 10:52:10.101946 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 10:52:10.107887 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 10:52:10.111238 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8835 10:52:10.114637 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8836 10:52:10.121301 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8837 10:52:10.124564 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8838 10:52:10.128036 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 10:52:10.134862 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 10:52:10.138174 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 10:52:10.141329 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 10:52:10.148209 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 10:52:10.151041 1 6 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
8844 10:52:10.154547 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8845 10:52:10.160964 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 10:52:10.164271 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 10:52:10.167636 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 10:52:10.174436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 10:52:10.177643 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 10:52:10.181131 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 10:52:10.187584 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8852 10:52:10.191096 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8853 10:52:10.194398 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 10:52:10.200931 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 10:52:10.204352 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 10:52:10.207699 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 10:52:10.214444 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 10:52:10.217714 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 10:52:10.220632 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 10:52:10.227545 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 10:52:10.230591 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 10:52:10.234056 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 10:52:10.240807 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 10:52:10.243984 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 10:52:10.247628 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 10:52:10.253817 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 10:52:10.257200 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8868 10:52:10.260678 Total UI for P1: 0, mck2ui 16
8869 10:52:10.264062 best dqsien dly found for B0: ( 1, 9, 6)
8870 10:52:10.266942 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8871 10:52:10.270469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 10:52:10.273738 Total UI for P1: 0, mck2ui 16
8873 10:52:10.277143 best dqsien dly found for B1: ( 1, 9, 10)
8874 10:52:10.280546 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8875 10:52:10.287223 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8876 10:52:10.287330
8877 10:52:10.290629 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8878 10:52:10.293852 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8879 10:52:10.296878 [Gating] SW calibration Done
8880 10:52:10.296949 ==
8881 10:52:10.300332 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 10:52:10.303766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 10:52:10.303835 ==
8884 10:52:10.306982 RX Vref Scan: 0
8885 10:52:10.307054
8886 10:52:10.307114 RX Vref 0 -> 0, step: 1
8887 10:52:10.307178
8888 10:52:10.309980 RX Delay 0 -> 252, step: 8
8889 10:52:10.313829 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8890 10:52:10.317063 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8891 10:52:10.323660 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8892 10:52:10.326935 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8893 10:52:10.330284 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8894 10:52:10.333745 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8895 10:52:10.336747 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8896 10:52:10.343530 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8897 10:52:10.346827 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8898 10:52:10.350409 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8899 10:52:10.353198 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8900 10:52:10.356536 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8901 10:52:10.363541 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8902 10:52:10.366803 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8903 10:52:10.370065 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8904 10:52:10.373407 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8905 10:52:10.373506 ==
8906 10:52:10.376659 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 10:52:10.383750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 10:52:10.383846 ==
8909 10:52:10.383941 DQS Delay:
8910 10:52:10.384029 DQS0 = 0, DQS1 = 0
8911 10:52:10.386943 DQM Delay:
8912 10:52:10.387027 DQM0 = 132, DQM1 = 127
8913 10:52:10.390302 DQ Delay:
8914 10:52:10.393512 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8915 10:52:10.396849 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8916 10:52:10.399805 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8917 10:52:10.403594 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8918 10:52:10.403668
8919 10:52:10.403730
8920 10:52:10.403792 ==
8921 10:52:10.406638 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 10:52:10.410120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 10:52:10.413180 ==
8924 10:52:10.413278
8925 10:52:10.413376
8926 10:52:10.413464 TX Vref Scan disable
8927 10:52:10.416354 == TX Byte 0 ==
8928 10:52:10.419771 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8929 10:52:10.423381 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8930 10:52:10.426615 == TX Byte 1 ==
8931 10:52:10.429721 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8932 10:52:10.433190 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8933 10:52:10.437001 ==
8934 10:52:10.437104 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 10:52:10.443450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 10:52:10.443530 ==
8937 10:52:10.456417
8938 10:52:10.459539 TX Vref early break, caculate TX vref
8939 10:52:10.462826 TX Vref=16, minBit 8, minWin=21, winSum=380
8940 10:52:10.466081 TX Vref=18, minBit 13, minWin=23, winSum=391
8941 10:52:10.469390 TX Vref=20, minBit 5, minWin=24, winSum=397
8942 10:52:10.472830 TX Vref=22, minBit 15, minWin=24, winSum=408
8943 10:52:10.475899 TX Vref=24, minBit 0, minWin=25, winSum=412
8944 10:52:10.482600 TX Vref=26, minBit 9, minWin=25, winSum=418
8945 10:52:10.486059 TX Vref=28, minBit 15, minWin=25, winSum=425
8946 10:52:10.489244 TX Vref=30, minBit 0, minWin=25, winSum=420
8947 10:52:10.492475 TX Vref=32, minBit 0, minWin=25, winSum=421
8948 10:52:10.495694 TX Vref=34, minBit 0, minWin=25, winSum=408
8949 10:52:10.502539 TX Vref=36, minBit 0, minWin=23, winSum=397
8950 10:52:10.505512 [TxChooseVref] Worse bit 15, Min win 25, Win sum 425, Final Vref 28
8951 10:52:10.505611
8952 10:52:10.508988 Final TX Range 0 Vref 28
8953 10:52:10.509062
8954 10:52:10.509125 ==
8955 10:52:10.512743 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 10:52:10.515638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 10:52:10.518949 ==
8958 10:52:10.519046
8959 10:52:10.519137
8960 10:52:10.519223 TX Vref Scan disable
8961 10:52:10.525848 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8962 10:52:10.525947 == TX Byte 0 ==
8963 10:52:10.528912 u2DelayCellOfst[0]=14 cells (4 PI)
8964 10:52:10.532764 u2DelayCellOfst[1]=14 cells (4 PI)
8965 10:52:10.535756 u2DelayCellOfst[2]=0 cells (0 PI)
8966 10:52:10.538967 u2DelayCellOfst[3]=7 cells (2 PI)
8967 10:52:10.542171 u2DelayCellOfst[4]=10 cells (3 PI)
8968 10:52:10.545392 u2DelayCellOfst[5]=17 cells (5 PI)
8969 10:52:10.548587 u2DelayCellOfst[6]=17 cells (5 PI)
8970 10:52:10.552375 u2DelayCellOfst[7]=3 cells (1 PI)
8971 10:52:10.555113 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8972 10:52:10.558720 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8973 10:52:10.562038 == TX Byte 1 ==
8974 10:52:10.565605 u2DelayCellOfst[8]=0 cells (0 PI)
8975 10:52:10.568659 u2DelayCellOfst[9]=3 cells (1 PI)
8976 10:52:10.572092 u2DelayCellOfst[10]=10 cells (3 PI)
8977 10:52:10.575081 u2DelayCellOfst[11]=7 cells (2 PI)
8978 10:52:10.578562 u2DelayCellOfst[12]=14 cells (4 PI)
8979 10:52:10.578643 u2DelayCellOfst[13]=14 cells (4 PI)
8980 10:52:10.582075 u2DelayCellOfst[14]=17 cells (5 PI)
8981 10:52:10.585442 u2DelayCellOfst[15]=17 cells (5 PI)
8982 10:52:10.591827 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8983 10:52:10.595066 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8984 10:52:10.595178 DramC Write-DBI on
8985 10:52:10.598395 ==
8986 10:52:10.601916 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 10:52:10.605079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 10:52:10.605161 ==
8989 10:52:10.605225
8990 10:52:10.605284
8991 10:52:10.608733 TX Vref Scan disable
8992 10:52:10.608814 == TX Byte 0 ==
8993 10:52:10.615013 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8994 10:52:10.615094 == TX Byte 1 ==
8995 10:52:10.618175 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8996 10:52:10.621642 DramC Write-DBI off
8997 10:52:10.621722
8998 10:52:10.621786 [DATLAT]
8999 10:52:10.625053 Freq=1600, CH1 RK1
9000 10:52:10.625134
9001 10:52:10.625198 DATLAT Default: 0xf
9002 10:52:10.628188 0, 0xFFFF, sum = 0
9003 10:52:10.628271 1, 0xFFFF, sum = 0
9004 10:52:10.631288 2, 0xFFFF, sum = 0
9005 10:52:10.631411 3, 0xFFFF, sum = 0
9006 10:52:10.634675 4, 0xFFFF, sum = 0
9007 10:52:10.634749 5, 0xFFFF, sum = 0
9008 10:52:10.638473 6, 0xFFFF, sum = 0
9009 10:52:10.638548 7, 0xFFFF, sum = 0
9010 10:52:10.641730 8, 0xFFFF, sum = 0
9011 10:52:10.644850 9, 0xFFFF, sum = 0
9012 10:52:10.644929 10, 0xFFFF, sum = 0
9013 10:52:10.648164 11, 0xFFFF, sum = 0
9014 10:52:10.648237 12, 0xFFFF, sum = 0
9015 10:52:10.651706 13, 0xFFFF, sum = 0
9016 10:52:10.651777 14, 0x0, sum = 1
9017 10:52:10.654821 15, 0x0, sum = 2
9018 10:52:10.654893 16, 0x0, sum = 3
9019 10:52:10.657926 17, 0x0, sum = 4
9020 10:52:10.657997 best_step = 15
9021 10:52:10.658056
9022 10:52:10.658121 ==
9023 10:52:10.661423 Dram Type= 6, Freq= 0, CH_1, rank 1
9024 10:52:10.664731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9025 10:52:10.664805 ==
9026 10:52:10.667905 RX Vref Scan: 0
9027 10:52:10.667989
9028 10:52:10.671048 RX Vref 0 -> 0, step: 1
9029 10:52:10.671128
9030 10:52:10.671189 RX Delay 11 -> 252, step: 4
9031 10:52:10.678381 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
9032 10:52:10.681808 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9033 10:52:10.685170 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9034 10:52:10.688694 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
9035 10:52:10.691849 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9036 10:52:10.698638 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9037 10:52:10.701790 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9038 10:52:10.705305 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9039 10:52:10.708582 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9040 10:52:10.711900 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9041 10:52:10.718527 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9042 10:52:10.721807 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9043 10:52:10.725162 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9044 10:52:10.728698 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9045 10:52:10.731543 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
9046 10:52:10.738665 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9047 10:52:10.738745 ==
9048 10:52:10.741887 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 10:52:10.744953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 10:52:10.745028 ==
9051 10:52:10.745090 DQS Delay:
9052 10:52:10.748643 DQS0 = 0, DQS1 = 0
9053 10:52:10.748709 DQM Delay:
9054 10:52:10.751754 DQM0 = 129, DQM1 = 126
9055 10:52:10.751837 DQ Delay:
9056 10:52:10.755601 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9057 10:52:10.758130 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9058 10:52:10.762140 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9059 10:52:10.765368 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9060 10:52:10.765449
9061 10:52:10.768211
9062 10:52:10.768291
9063 10:52:10.768355 [DramC_TX_OE_Calibration] TA2
9064 10:52:10.771729 Original DQ_B0 (3 6) =30, OEN = 27
9065 10:52:10.775251 Original DQ_B1 (3 6) =30, OEN = 27
9066 10:52:10.778496 24, 0x0, End_B0=24 End_B1=24
9067 10:52:10.781317 25, 0x0, End_B0=25 End_B1=25
9068 10:52:10.784979 26, 0x0, End_B0=26 End_B1=26
9069 10:52:10.785062 27, 0x0, End_B0=27 End_B1=27
9070 10:52:10.788380 28, 0x0, End_B0=28 End_B1=28
9071 10:52:10.791666 29, 0x0, End_B0=29 End_B1=29
9072 10:52:10.795116 30, 0x0, End_B0=30 End_B1=30
9073 10:52:10.798433 31, 0x4545, End_B0=30 End_B1=30
9074 10:52:10.798529 Byte0 end_step=30 best_step=27
9075 10:52:10.801883 Byte1 end_step=30 best_step=27
9076 10:52:10.804946 Byte0 TX OE(2T, 0.5T) = (3, 3)
9077 10:52:10.808542 Byte1 TX OE(2T, 0.5T) = (3, 3)
9078 10:52:10.808623
9079 10:52:10.808686
9080 10:52:10.818150 [DQSOSCAuto] RK1, (LSB)MR18= 0x1118, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
9081 10:52:10.818236 CH1 RK1: MR19=303, MR18=1118
9082 10:52:10.824594 CH1_RK1: MR19=0x303, MR18=0x1118, DQSOSC=397, MR23=63, INC=23, DEC=15
9083 10:52:10.827942 [RxdqsGatingPostProcess] freq 1600
9084 10:52:10.834549 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9085 10:52:10.838010 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 10:52:10.841314 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 10:52:10.845616 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 10:52:10.845696 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 10:52:10.847587 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 10:52:10.851048 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 10:52:10.854342 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 10:52:10.857620 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 10:52:10.861041 Pre-setting of DQS Precalculation
9094 10:52:10.867422 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9095 10:52:10.874644 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9096 10:52:10.880863 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 10:52:10.880973
9098 10:52:10.881067
9099 10:52:10.884699 [Calibration Summary] 3200 Mbps
9100 10:52:10.884797 CH 0, Rank 0
9101 10:52:10.887397 SW Impedance : PASS
9102 10:52:10.890895 DUTY Scan : NO K
9103 10:52:10.891000 ZQ Calibration : PASS
9104 10:52:10.894140 Jitter Meter : NO K
9105 10:52:10.897525 CBT Training : PASS
9106 10:52:10.897620 Write leveling : PASS
9107 10:52:10.901029 RX DQS gating : PASS
9108 10:52:10.901131 RX DQ/DQS(RDDQC) : PASS
9109 10:52:10.903972 TX DQ/DQS : PASS
9110 10:52:10.907567 RX DATLAT : PASS
9111 10:52:10.907665 RX DQ/DQS(Engine): PASS
9112 10:52:10.911063 TX OE : PASS
9113 10:52:10.911169 All Pass.
9114 10:52:10.911268
9115 10:52:10.914534 CH 0, Rank 1
9116 10:52:10.914634 SW Impedance : PASS
9117 10:52:10.917564 DUTY Scan : NO K
9118 10:52:10.920859 ZQ Calibration : PASS
9119 10:52:10.920958 Jitter Meter : NO K
9120 10:52:10.924428 CBT Training : PASS
9121 10:52:10.927800 Write leveling : PASS
9122 10:52:10.927899 RX DQS gating : PASS
9123 10:52:10.930959 RX DQ/DQS(RDDQC) : PASS
9124 10:52:10.934413 TX DQ/DQS : PASS
9125 10:52:10.934486 RX DATLAT : PASS
9126 10:52:10.937411 RX DQ/DQS(Engine): PASS
9127 10:52:10.940693 TX OE : PASS
9128 10:52:10.940791 All Pass.
9129 10:52:10.940890
9130 10:52:10.940985 CH 1, Rank 0
9131 10:52:10.944665 SW Impedance : PASS
9132 10:52:10.947233 DUTY Scan : NO K
9133 10:52:10.947331 ZQ Calibration : PASS
9134 10:52:10.950559 Jitter Meter : NO K
9135 10:52:10.953874 CBT Training : PASS
9136 10:52:10.953979 Write leveling : PASS
9137 10:52:10.957214 RX DQS gating : PASS
9138 10:52:10.957313 RX DQ/DQS(RDDQC) : PASS
9139 10:52:10.960428 TX DQ/DQS : PASS
9140 10:52:10.964028 RX DATLAT : PASS
9141 10:52:10.964133 RX DQ/DQS(Engine): PASS
9142 10:52:10.967478 TX OE : PASS
9143 10:52:10.967581 All Pass.
9144 10:52:10.967665
9145 10:52:10.970565 CH 1, Rank 1
9146 10:52:10.970680 SW Impedance : PASS
9147 10:52:10.973872 DUTY Scan : NO K
9148 10:52:10.977153 ZQ Calibration : PASS
9149 10:52:10.977256 Jitter Meter : NO K
9150 10:52:10.980154 CBT Training : PASS
9151 10:52:10.983601 Write leveling : PASS
9152 10:52:10.983678 RX DQS gating : PASS
9153 10:52:10.987068 RX DQ/DQS(RDDQC) : PASS
9154 10:52:10.990343 TX DQ/DQS : PASS
9155 10:52:10.990425 RX DATLAT : PASS
9156 10:52:10.994005 RX DQ/DQS(Engine): PASS
9157 10:52:10.997031 TX OE : PASS
9158 10:52:10.997131 All Pass.
9159 10:52:10.997233
9160 10:52:10.997329 DramC Write-DBI on
9161 10:52:11.000229 PER_BANK_REFRESH: Hybrid Mode
9162 10:52:11.003657 TX_TRACKING: ON
9163 10:52:11.009994 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9164 10:52:11.019877 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9165 10:52:11.026449 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9166 10:52:11.030192 [FAST_K] Save calibration result to emmc
9167 10:52:11.033637 sync common calibartion params.
9168 10:52:11.036751 sync cbt_mode0:1, 1:1
9169 10:52:11.036859 dram_init: ddr_geometry: 2
9170 10:52:11.039782 dram_init: ddr_geometry: 2
9171 10:52:11.043883 dram_init: ddr_geometry: 2
9172 10:52:11.046248 0:dram_rank_size:100000000
9173 10:52:11.046352 1:dram_rank_size:100000000
9174 10:52:11.053031 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9175 10:52:11.056118 DFS_SHUFFLE_HW_MODE: ON
9176 10:52:11.059598 dramc_set_vcore_voltage set vcore to 725000
9177 10:52:11.059676 Read voltage for 1600, 0
9178 10:52:11.062747 Vio18 = 0
9179 10:52:11.062849 Vcore = 725000
9180 10:52:11.062948 Vdram = 0
9181 10:52:11.066624 Vddq = 0
9182 10:52:11.066730 Vmddr = 0
9183 10:52:11.069399 switch to 3200 Mbps bootup
9184 10:52:11.069498 [DramcRunTimeConfig]
9185 10:52:11.069599 PHYPLL
9186 10:52:11.073208 DPM_CONTROL_AFTERK: ON
9187 10:52:11.076158 PER_BANK_REFRESH: ON
9188 10:52:11.079727 REFRESH_OVERHEAD_REDUCTION: ON
9189 10:52:11.079828 CMD_PICG_NEW_MODE: OFF
9190 10:52:11.082949 XRTWTW_NEW_MODE: ON
9191 10:52:11.083047 XRTRTR_NEW_MODE: ON
9192 10:52:11.086112 TX_TRACKING: ON
9193 10:52:11.086211 RDSEL_TRACKING: OFF
9194 10:52:11.089841 DQS Precalculation for DVFS: ON
9195 10:52:11.092713 RX_TRACKING: OFF
9196 10:52:11.092789 HW_GATING DBG: ON
9197 10:52:11.096042 ZQCS_ENABLE_LP4: ON
9198 10:52:11.096116 RX_PICG_NEW_MODE: ON
9199 10:52:11.099888 TX_PICG_NEW_MODE: ON
9200 10:52:11.099972 ENABLE_RX_DCM_DPHY: ON
9201 10:52:11.102787 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9202 10:52:11.105953 DUMMY_READ_FOR_TRACKING: OFF
9203 10:52:11.109614 !!! SPM_CONTROL_AFTERK: OFF
9204 10:52:11.112753 !!! SPM could not control APHY
9205 10:52:11.112827 IMPEDANCE_TRACKING: ON
9206 10:52:11.115860 TEMP_SENSOR: ON
9207 10:52:11.115957 HW_SAVE_FOR_SR: OFF
9208 10:52:11.119591 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9209 10:52:11.122628 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9210 10:52:11.126006 Read ODT Tracking: ON
9211 10:52:11.129131 Refresh Rate DeBounce: ON
9212 10:52:11.129206 DFS_NO_QUEUE_FLUSH: ON
9213 10:52:11.132882 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9214 10:52:11.136149 ENABLE_DFS_RUNTIME_MRW: OFF
9215 10:52:11.139325 DDR_RESERVE_NEW_MODE: ON
9216 10:52:11.139433 MR_CBT_SWITCH_FREQ: ON
9217 10:52:11.142346 =========================
9218 10:52:11.161166 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9219 10:52:11.164409 dram_init: ddr_geometry: 2
9220 10:52:11.182547 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9221 10:52:11.186437 dram_init: dram init end (result: 0)
9222 10:52:11.192788 DRAM-K: Full calibration passed in 24576 msecs
9223 10:52:11.196117 MRC: failed to locate region type 0.
9224 10:52:11.196199 DRAM rank0 size:0x100000000,
9225 10:52:11.199225 DRAM rank1 size=0x100000000
9226 10:52:11.209692 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9227 10:52:11.216210 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9228 10:52:11.222813 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9229 10:52:11.228962 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9230 10:52:11.232446 DRAM rank0 size:0x100000000,
9231 10:52:11.235758 DRAM rank1 size=0x100000000
9232 10:52:11.235839 CBMEM:
9233 10:52:11.239270 IMD: root @ 0xfffff000 254 entries.
9234 10:52:11.242127 IMD: root @ 0xffffec00 62 entries.
9235 10:52:11.245523 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9236 10:52:11.249233 WARNING: RO_VPD is uninitialized or empty.
9237 10:52:11.255598 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9238 10:52:11.263064 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9239 10:52:11.275538 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9240 10:52:11.287255 BS: romstage times (exec / console): total (unknown) / 24083 ms
9241 10:52:11.287340
9242 10:52:11.287426
9243 10:52:11.296686 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9244 10:52:11.300096 ARM64: Exception handlers installed.
9245 10:52:11.303647 ARM64: Testing exception
9246 10:52:11.306596 ARM64: Done test exception
9247 10:52:11.306676 Enumerating buses...
9248 10:52:11.310157 Show all devs... Before device enumeration.
9249 10:52:11.313480 Root Device: enabled 1
9250 10:52:11.316925 CPU_CLUSTER: 0: enabled 1
9251 10:52:11.317006 CPU: 00: enabled 1
9252 10:52:11.319830 Compare with tree...
9253 10:52:11.319910 Root Device: enabled 1
9254 10:52:11.323188 CPU_CLUSTER: 0: enabled 1
9255 10:52:11.326273 CPU: 00: enabled 1
9256 10:52:11.326353 Root Device scanning...
9257 10:52:11.330020 scan_static_bus for Root Device
9258 10:52:11.333014 CPU_CLUSTER: 0 enabled
9259 10:52:11.336137 scan_static_bus for Root Device done
9260 10:52:11.339645 scan_bus: bus Root Device finished in 8 msecs
9261 10:52:11.339730 done
9262 10:52:11.346365 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9263 10:52:11.349075 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9264 10:52:11.356273 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9265 10:52:11.359210 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9266 10:52:11.362488 Allocating resources...
9267 10:52:11.365977 Reading resources...
9268 10:52:11.369190 Root Device read_resources bus 0 link: 0
9269 10:52:11.372463 DRAM rank0 size:0x100000000,
9270 10:52:11.372545 DRAM rank1 size=0x100000000
9271 10:52:11.379476 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9272 10:52:11.379558 CPU: 00 missing read_resources
9273 10:52:11.385901 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9274 10:52:11.389407 Root Device read_resources bus 0 link: 0 done
9275 10:52:11.392228 Done reading resources.
9276 10:52:11.396050 Show resources in subtree (Root Device)...After reading.
9277 10:52:11.398991 Root Device child on link 0 CPU_CLUSTER: 0
9278 10:52:11.402740 CPU_CLUSTER: 0 child on link 0 CPU: 00
9279 10:52:11.412816 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9280 10:52:11.412902 CPU: 00
9281 10:52:11.416228 Root Device assign_resources, bus 0 link: 0
9282 10:52:11.419686 CPU_CLUSTER: 0 missing set_resources
9283 10:52:11.425582 Root Device assign_resources, bus 0 link: 0 done
9284 10:52:11.425663 Done setting resources.
9285 10:52:11.432403 Show resources in subtree (Root Device)...After assigning values.
9286 10:52:11.436052 Root Device child on link 0 CPU_CLUSTER: 0
9287 10:52:11.438965 CPU_CLUSTER: 0 child on link 0 CPU: 00
9288 10:52:11.449019 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9289 10:52:11.449104 CPU: 00
9290 10:52:11.452081 Done allocating resources.
9291 10:52:11.458950 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9292 10:52:11.459032 Enabling resources...
9293 10:52:11.459096 done.
9294 10:52:11.465149 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9295 10:52:11.469480 Initializing devices...
9296 10:52:11.469567 Root Device init
9297 10:52:11.471947 init hardware done!
9298 10:52:11.472053 0x00000018: ctrlr->caps
9299 10:52:11.475187 52.000 MHz: ctrlr->f_max
9300 10:52:11.478442 0.400 MHz: ctrlr->f_min
9301 10:52:11.478551 0x40ff8080: ctrlr->voltages
9302 10:52:11.481852 sclk: 390625
9303 10:52:11.481932 Bus Width = 1
9304 10:52:11.481995 sclk: 390625
9305 10:52:11.485287 Bus Width = 1
9306 10:52:11.485369 Early init status = 3
9307 10:52:11.491878 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9308 10:52:11.495459 in-header: 03 fc 00 00 01 00 00 00
9309 10:52:11.498479 in-data: 00
9310 10:52:11.501850 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9311 10:52:11.505485 in-header: 03 fd 00 00 00 00 00 00
9312 10:52:11.508794 in-data:
9313 10:52:11.512060 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9314 10:52:11.516087 in-header: 03 fc 00 00 01 00 00 00
9315 10:52:11.519433 in-data: 00
9316 10:52:11.522217 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9317 10:52:11.527042 in-header: 03 fd 00 00 00 00 00 00
9318 10:52:11.530231 in-data:
9319 10:52:11.533514 [SSUSB] Setting up USB HOST controller...
9320 10:52:11.537043 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9321 10:52:11.540347 [SSUSB] phy power-on done.
9322 10:52:11.543854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9323 10:52:11.549959 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9324 10:52:11.553260 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9325 10:52:11.560160 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9326 10:52:11.566979 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9327 10:52:11.573534 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9328 10:52:11.579925 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9329 10:52:11.586547 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9330 10:52:11.589804 SPM: binary array size = 0x9dc
9331 10:52:11.593454 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9332 10:52:11.599964 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9333 10:52:11.606656 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9334 10:52:11.609644 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9335 10:52:11.616309 configure_display: Starting display init
9336 10:52:11.649961 anx7625_power_on_init: Init interface.
9337 10:52:11.653657 anx7625_disable_pd_protocol: Disabled PD feature.
9338 10:52:11.656706 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9339 10:52:11.684854 anx7625_start_dp_work: Secure OCM version=00
9340 10:52:11.687982 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9341 10:52:11.702417 sp_tx_get_edid_block: EDID Block = 1
9342 10:52:11.805257 Extracted contents:
9343 10:52:11.808916 header: 00 ff ff ff ff ff ff 00
9344 10:52:11.812081 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9345 10:52:11.815089 version: 01 04
9346 10:52:11.818845 basic params: 95 1f 11 78 0a
9347 10:52:11.821654 chroma info: 76 90 94 55 54 90 27 21 50 54
9348 10:52:11.824973 established: 00 00 00
9349 10:52:11.831802 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9350 10:52:11.835221 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9351 10:52:11.841787 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9352 10:52:11.848432 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9353 10:52:11.855544 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9354 10:52:11.858125 extensions: 00
9355 10:52:11.858223 checksum: fb
9356 10:52:11.858299
9357 10:52:11.861335 Manufacturer: IVO Model 57d Serial Number 0
9358 10:52:11.865006 Made week 0 of 2020
9359 10:52:11.865085 EDID version: 1.4
9360 10:52:11.868740 Digital display
9361 10:52:11.871333 6 bits per primary color channel
9362 10:52:11.871438 DisplayPort interface
9363 10:52:11.874757 Maximum image size: 31 cm x 17 cm
9364 10:52:11.878582 Gamma: 220%
9365 10:52:11.878660 Check DPMS levels
9366 10:52:11.881320 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9367 10:52:11.885049 First detailed timing is preferred timing
9368 10:52:11.888420 Established timings supported:
9369 10:52:11.891606 Standard timings supported:
9370 10:52:11.894817 Detailed timings
9371 10:52:11.898061 Hex of detail: 383680a07038204018303c0035ae10000019
9372 10:52:11.901872 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9373 10:52:11.908229 0780 0798 07c8 0820 hborder 0
9374 10:52:11.911754 0438 043b 0447 0458 vborder 0
9375 10:52:11.914879 -hsync -vsync
9376 10:52:11.914958 Did detailed timing
9377 10:52:11.918095 Hex of detail: 000000000000000000000000000000000000
9378 10:52:11.921500 Manufacturer-specified data, tag 0
9379 10:52:11.927894 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9380 10:52:11.927971 ASCII string: InfoVision
9381 10:52:11.934759 Hex of detail: 000000fe00523134304e574635205248200a
9382 10:52:11.938123 ASCII string: R140NWF5 RH
9383 10:52:11.938194 Checksum
9384 10:52:11.938260 Checksum: 0xfb (valid)
9385 10:52:11.945000 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9386 10:52:11.948230 DSI data_rate: 832800000 bps
9387 10:52:11.951629 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9388 10:52:11.958071 anx7625_parse_edid: pixelclock(138800).
9389 10:52:11.961341 hactive(1920), hsync(48), hfp(24), hbp(88)
9390 10:52:11.964870 vactive(1080), vsync(12), vfp(3), vbp(17)
9391 10:52:11.968338 anx7625_dsi_config: config dsi.
9392 10:52:11.974341 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9393 10:52:11.987308 anx7625_dsi_config: success to config DSI
9394 10:52:11.990597 anx7625_dp_start: MIPI phy setup OK.
9395 10:52:11.993742 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9396 10:52:11.996977 mtk_ddp_mode_set invalid vrefresh 60
9397 10:52:12.000551 main_disp_path_setup
9398 10:52:12.000636 ovl_layer_smi_id_en
9399 10:52:12.003814 ovl_layer_smi_id_en
9400 10:52:12.003895 ccorr_config
9401 10:52:12.003959 aal_config
9402 10:52:12.006934 gamma_config
9403 10:52:12.007014 postmask_config
9404 10:52:12.010291 dither_config
9405 10:52:12.013917 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9406 10:52:12.020671 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9407 10:52:12.023827 Root Device init finished in 551 msecs
9408 10:52:12.027305 CPU_CLUSTER: 0 init
9409 10:52:12.034147 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9410 10:52:12.036989 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9411 10:52:12.040214 APU_MBOX 0x190000b0 = 0x10001
9412 10:52:12.043581 APU_MBOX 0x190001b0 = 0x10001
9413 10:52:12.047005 APU_MBOX 0x190005b0 = 0x10001
9414 10:52:12.050126 APU_MBOX 0x190006b0 = 0x10001
9415 10:52:12.053780 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9416 10:52:12.066439 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9417 10:52:12.078707 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9418 10:52:12.086057 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9419 10:52:12.097125 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9420 10:52:12.106132 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9421 10:52:12.109272 CPU_CLUSTER: 0 init finished in 81 msecs
9422 10:52:12.112703 Devices initialized
9423 10:52:12.116028 Show all devs... After init.
9424 10:52:12.116116 Root Device: enabled 1
9425 10:52:12.119698 CPU_CLUSTER: 0: enabled 1
9426 10:52:12.122685 CPU: 00: enabled 1
9427 10:52:12.126025 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9428 10:52:12.129326 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9429 10:52:12.132420 ELOG: NV offset 0x57f000 size 0x1000
9430 10:52:12.139185 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9431 10:52:12.145891 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9432 10:52:12.149117 ELOG: Event(17) added with size 13 at 2023-06-05 10:52:12 UTC
9433 10:52:12.155780 out: cmd=0x121: 03 db 21 01 00 00 00 00
9434 10:52:12.158980 in-header: 03 d2 00 00 2c 00 00 00
9435 10:52:12.169517 in-data: 8d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9436 10:52:12.175321 ELOG: Event(A1) added with size 10 at 2023-06-05 10:52:12 UTC
9437 10:52:12.181973 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9438 10:52:12.188854 ELOG: Event(A0) added with size 9 at 2023-06-05 10:52:12 UTC
9439 10:52:12.192292 elog_add_boot_reason: Logged dev mode boot
9440 10:52:12.198503 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9441 10:52:12.198575 Finalize devices...
9442 10:52:12.202253 Devices finalized
9443 10:52:12.205529 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9444 10:52:12.208366 Writing coreboot table at 0xffe64000
9445 10:52:12.211701 0. 000000000010a000-0000000000113fff: RAMSTAGE
9446 10:52:12.218000 1. 0000000040000000-00000000400fffff: RAM
9447 10:52:12.221749 2. 0000000040100000-000000004032afff: RAMSTAGE
9448 10:52:12.225013 3. 000000004032b000-00000000545fffff: RAM
9449 10:52:12.228401 4. 0000000054600000-000000005465ffff: BL31
9450 10:52:12.231666 5. 0000000054660000-00000000ffe63fff: RAM
9451 10:52:12.238425 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9452 10:52:12.241502 7. 0000000100000000-000000023fffffff: RAM
9453 10:52:12.244860 Passing 5 GPIOs to payload:
9454 10:52:12.247963 NAME | PORT | POLARITY | VALUE
9455 10:52:12.254689 EC in RW | 0x000000aa | low | undefined
9456 10:52:12.258007 EC interrupt | 0x00000005 | low | undefined
9457 10:52:12.261513 TPM interrupt | 0x000000ab | high | undefined
9458 10:52:12.268125 SD card detect | 0x00000011 | high | undefined
9459 10:52:12.271449 speaker enable | 0x00000093 | high | undefined
9460 10:52:12.274965 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9461 10:52:12.277861 in-header: 03 f9 00 00 02 00 00 00
9462 10:52:12.281101 in-data: 02 00
9463 10:52:12.284653 ADC[4]: Raw value=900221 ID=7
9464 10:52:12.284762 ADC[3]: Raw value=213336 ID=1
9465 10:52:12.288116 RAM Code: 0x71
9466 10:52:12.291461 ADC[6]: Raw value=74557 ID=0
9467 10:52:12.294725 ADC[5]: Raw value=212229 ID=1
9468 10:52:12.294805 SKU Code: 0x1
9469 10:52:12.301481 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9470 10:52:12.301562 coreboot table: 964 bytes.
9471 10:52:12.304349 IMD ROOT 0. 0xfffff000 0x00001000
9472 10:52:12.308006 IMD SMALL 1. 0xffffe000 0x00001000
9473 10:52:12.311278 RO MCACHE 2. 0xffffc000 0x00001104
9474 10:52:12.314298 CONSOLE 3. 0xfff7c000 0x00080000
9475 10:52:12.317549 FMAP 4. 0xfff7b000 0x00000452
9476 10:52:12.321199 TIME STAMP 5. 0xfff7a000 0x00000910
9477 10:52:12.324409 VBOOT WORK 6. 0xfff66000 0x00014000
9478 10:52:12.327853 RAMOOPS 7. 0xffe66000 0x00100000
9479 10:52:12.331470 COREBOOT 8. 0xffe64000 0x00002000
9480 10:52:12.334653 IMD small region:
9481 10:52:12.337886 IMD ROOT 0. 0xffffec00 0x00000400
9482 10:52:12.341264 VPD 1. 0xffffeba0 0x0000004c
9483 10:52:12.343981 MMC STATUS 2. 0xffffeb80 0x00000004
9484 10:52:12.347268 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9485 10:52:12.350563 Probing TPM: done!
9486 10:52:12.354627 Connected to device vid:did:rid of 1ae0:0028:00
9487 10:52:12.364995 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9488 10:52:12.368702 Initialized TPM device CR50 revision 0
9489 10:52:12.372150 Checking cr50 for pending updates
9490 10:52:12.375828 Reading cr50 TPM mode
9491 10:52:12.384280 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9492 10:52:12.391411 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9493 10:52:12.431229 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9494 10:52:12.434570 Checking segment from ROM address 0x40100000
9495 10:52:12.437936 Checking segment from ROM address 0x4010001c
9496 10:52:12.444717 Loading segment from ROM address 0x40100000
9497 10:52:12.444793 code (compression=0)
9498 10:52:12.454497 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9499 10:52:12.461361 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9500 10:52:12.461463 it's not compressed!
9501 10:52:12.468118 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9502 10:52:12.471255 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9503 10:52:12.491599 Loading segment from ROM address 0x4010001c
9504 10:52:12.491709 Entry Point 0x80000000
9505 10:52:12.495160 Loaded segments
9506 10:52:12.498240 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9507 10:52:12.505349 Jumping to boot code at 0x80000000(0xffe64000)
9508 10:52:12.511861 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9509 10:52:12.518147 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9510 10:52:12.526218 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9511 10:52:12.529276 Checking segment from ROM address 0x40100000
9512 10:52:12.532877 Checking segment from ROM address 0x4010001c
9513 10:52:12.539231 Loading segment from ROM address 0x40100000
9514 10:52:12.539316 code (compression=1)
9515 10:52:12.546358 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9516 10:52:12.556296 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9517 10:52:12.556378 using LZMA
9518 10:52:12.564194 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9519 10:52:12.571693 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9520 10:52:12.574818 Loading segment from ROM address 0x4010001c
9521 10:52:12.574896 Entry Point 0x54601000
9522 10:52:12.577649 Loaded segments
9523 10:52:12.580789 NOTICE: MT8192 bl31_setup
9524 10:52:12.588077 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9525 10:52:12.591436 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9526 10:52:12.594703 WARNING: region 0:
9527 10:52:12.598106 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 10:52:12.598189 WARNING: region 1:
9529 10:52:12.604620 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9530 10:52:12.608160 WARNING: region 2:
9531 10:52:12.611514 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9532 10:52:12.614516 WARNING: region 3:
9533 10:52:12.617820 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9534 10:52:12.621009 WARNING: region 4:
9535 10:52:12.628106 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9536 10:52:12.628185 WARNING: region 5:
9537 10:52:12.631330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 10:52:12.634599 WARNING: region 6:
9539 10:52:12.637805 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 10:52:12.641067 WARNING: region 7:
9541 10:52:12.644504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 10:52:12.651431 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9543 10:52:12.654510 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9544 10:52:12.657806 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9545 10:52:12.664472 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9546 10:52:12.667662 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9547 10:52:12.671195 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9548 10:52:12.677630 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9549 10:52:12.680899 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9550 10:52:12.687754 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9551 10:52:12.691130 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9552 10:52:12.694731 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9553 10:52:12.701135 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9554 10:52:12.704378 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9555 10:52:12.707784 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9556 10:52:12.714570 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9557 10:52:12.717993 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9558 10:52:12.724456 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9559 10:52:12.727860 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9560 10:52:12.731164 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9561 10:52:12.737828 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9562 10:52:12.741016 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9563 10:52:12.744316 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9564 10:52:12.751003 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9565 10:52:12.754953 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9566 10:52:12.761383 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9567 10:52:12.764257 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9568 10:52:12.768052 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9569 10:52:12.774063 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9570 10:52:12.777601 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9571 10:52:12.784661 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9572 10:52:12.788044 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9573 10:52:12.790801 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9574 10:52:12.798027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9575 10:52:12.801085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9576 10:52:12.804559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9577 10:52:12.808089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9578 10:52:12.814391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9579 10:52:12.818033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9580 10:52:12.821322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9581 10:52:12.824556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9582 10:52:12.831125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9583 10:52:12.834414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9584 10:52:12.837647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9585 10:52:12.841253 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9586 10:52:12.847606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9587 10:52:12.851437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9588 10:52:12.854238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9589 10:52:12.857785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9590 10:52:12.864742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9591 10:52:12.867914 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9592 10:52:12.874560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9593 10:52:12.877826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9594 10:52:12.881164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9595 10:52:12.887697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9596 10:52:12.891022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9597 10:52:12.897874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9598 10:52:12.901024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9599 10:52:12.907611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9600 10:52:12.911297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9601 10:52:12.914901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9602 10:52:12.921550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9603 10:52:12.924428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9604 10:52:12.931672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9605 10:52:12.934497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9606 10:52:12.941541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9607 10:52:12.944485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9608 10:52:12.947702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9609 10:52:12.954591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9610 10:52:12.957925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9611 10:52:12.964464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9612 10:52:12.967872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9613 10:52:12.974345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9614 10:52:12.977793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9615 10:52:12.981391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9616 10:52:12.988556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9617 10:52:12.991590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9618 10:52:12.998193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9619 10:52:13.001112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9620 10:52:13.008113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9621 10:52:13.011296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9622 10:52:13.017838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9623 10:52:13.021095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9624 10:52:13.024541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9625 10:52:13.031453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9626 10:52:13.034540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9627 10:52:13.041122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9628 10:52:13.044389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9629 10:52:13.051128 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9630 10:52:13.054498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9631 10:52:13.057741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9632 10:52:13.064412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9633 10:52:13.068054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9634 10:52:13.074499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9635 10:52:13.077974 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9636 10:52:13.084326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9637 10:52:13.087836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9638 10:52:13.091143 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9639 10:52:13.098103 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9640 10:52:13.101023 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9641 10:52:13.104360 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9642 10:52:13.108240 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9643 10:52:13.114773 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9644 10:52:13.118090 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9645 10:52:13.124590 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9646 10:52:13.127882 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9647 10:52:13.131095 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9648 10:52:13.137968 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9649 10:52:13.140988 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9650 10:52:13.148027 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9651 10:52:13.151047 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9652 10:52:13.154298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9653 10:52:13.161265 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9654 10:52:13.164435 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9655 10:52:13.171457 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9656 10:52:13.174244 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9657 10:52:13.177960 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9658 10:52:13.181428 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9659 10:52:13.187745 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9660 10:52:13.191133 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9661 10:52:13.194765 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9662 10:52:13.201487 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9663 10:52:13.204618 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9664 10:52:13.207967 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9665 10:52:13.210946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9666 10:52:13.218271 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9667 10:52:13.221194 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9668 10:52:13.224531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9669 10:52:13.231162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9670 10:52:13.234390 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9671 10:52:13.241406 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9672 10:52:13.244490 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9673 10:52:13.247816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9674 10:52:13.254657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9675 10:52:13.257819 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9676 10:52:13.264818 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9677 10:52:13.267831 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9678 10:52:13.271704 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9679 10:52:13.277671 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9680 10:52:13.280952 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9681 10:52:13.284386 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9682 10:52:13.291222 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9683 10:52:13.294580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9684 10:52:13.301472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9685 10:52:13.304920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9686 10:52:13.308221 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9687 10:52:13.315063 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9688 10:52:13.318528 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9689 10:52:13.324592 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9690 10:52:13.328185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9691 10:52:13.331616 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9692 10:52:13.337997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9693 10:52:13.341827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9694 10:52:13.345067 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9695 10:52:13.351504 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9696 10:52:13.354844 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9697 10:52:13.361646 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9698 10:52:13.364652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9699 10:52:13.368567 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9700 10:52:13.375129 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9701 10:52:13.378225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9702 10:52:13.381635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9703 10:52:13.388443 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9704 10:52:13.391835 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9705 10:52:13.398222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9706 10:52:13.401515 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9707 10:52:13.404564 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9708 10:52:13.411374 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9709 10:52:13.414793 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9710 10:52:13.421484 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9711 10:52:13.425188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9712 10:52:13.427997 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9713 10:52:13.434596 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9714 10:52:13.438163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9715 10:52:13.441469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9716 10:52:13.448440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9717 10:52:13.451412 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9718 10:52:13.458248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9719 10:52:13.461259 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9720 10:52:13.468083 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9721 10:52:13.471088 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9722 10:52:13.474876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9723 10:52:13.481089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9724 10:52:13.485017 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9725 10:52:13.488337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9726 10:52:13.494409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9727 10:52:13.497789 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9728 10:52:13.504411 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9729 10:52:13.508300 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9730 10:52:13.511462 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9731 10:52:13.517743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9732 10:52:13.521148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9733 10:52:13.527970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9734 10:52:13.531492 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9735 10:52:13.534401 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9736 10:52:13.541074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9737 10:52:13.544198 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9738 10:52:13.551139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9739 10:52:13.554212 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9740 10:52:13.561251 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9741 10:52:13.564198 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9742 10:52:13.568176 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9743 10:52:13.574503 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9744 10:52:13.577758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9745 10:52:13.584025 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9746 10:52:13.587685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9747 10:52:13.594124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9748 10:52:13.597312 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9749 10:52:13.600868 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9750 10:52:13.607143 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9751 10:52:13.610711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9752 10:52:13.617499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9753 10:52:13.620431 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9754 10:52:13.623963 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9755 10:52:13.630797 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9756 10:52:13.634191 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9757 10:52:13.640392 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9758 10:52:13.643948 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9759 10:52:13.650630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9760 10:52:13.653602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9761 10:52:13.657358 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9762 10:52:13.663880 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9763 10:52:13.667090 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9764 10:52:13.673849 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9765 10:52:13.676574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9766 10:52:13.683161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9767 10:52:13.686569 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9768 10:52:13.690058 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9769 10:52:13.696683 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9770 10:52:13.700182 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9771 10:52:13.703586 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9772 10:52:13.710194 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9773 10:52:13.713360 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9774 10:52:13.716957 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9775 10:52:13.719974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9776 10:52:13.726955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9777 10:52:13.730342 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9778 10:52:13.733795 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9779 10:52:13.740067 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9780 10:52:13.743623 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9781 10:52:13.746559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9782 10:52:13.753261 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9783 10:52:13.756506 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9784 10:52:13.763137 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9785 10:52:13.766539 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9786 10:52:13.770021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9787 10:52:13.776711 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9788 10:52:13.780335 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9789 10:52:13.783290 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9790 10:52:13.789945 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9791 10:52:13.793563 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9792 10:52:13.796774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9793 10:52:13.803266 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9794 10:52:13.806801 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9795 10:52:13.810115 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9796 10:52:13.816280 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9797 10:52:13.819526 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9798 10:52:13.826272 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9799 10:52:13.829496 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9800 10:52:13.832872 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9801 10:52:13.839560 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9802 10:52:13.842880 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9803 10:52:13.849968 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9804 10:52:13.853336 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9805 10:52:13.856268 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9806 10:52:13.862749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9807 10:52:13.866438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9808 10:52:13.869751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9809 10:52:13.876287 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9810 10:52:13.879505 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9811 10:52:13.883462 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9812 10:52:13.886463 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9813 10:52:13.892961 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9814 10:52:13.896183 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9815 10:52:13.899361 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9816 10:52:13.902999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9817 10:52:13.909243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9818 10:52:13.912734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9819 10:52:13.916094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9820 10:52:13.919113 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9821 10:52:13.925884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9822 10:52:13.929484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9823 10:52:13.932861 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9824 10:52:13.939250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9825 10:52:13.942912 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9826 10:52:13.946146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9827 10:52:13.952285 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9828 10:52:13.955780 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9829 10:52:13.962575 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9830 10:52:13.966422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9831 10:52:13.969296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9832 10:52:13.975556 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9833 10:52:13.979102 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9834 10:52:13.985460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9835 10:52:13.988811 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9836 10:52:13.995618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9837 10:52:13.999121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9838 10:52:14.002108 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9839 10:52:14.009027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9840 10:52:14.012760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9841 10:52:14.019042 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9842 10:52:14.022455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9843 10:52:14.025596 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9844 10:52:14.032488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9845 10:52:14.035772 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9846 10:52:14.041966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9847 10:52:14.045904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9848 10:52:14.048825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9849 10:52:14.055976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9850 10:52:14.058910 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9851 10:52:14.065391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9852 10:52:14.068555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9853 10:52:14.075140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9854 10:52:14.078782 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9855 10:52:14.081787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9856 10:52:14.088584 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9857 10:52:14.092090 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9858 10:52:14.098614 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9859 10:52:14.101834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9860 10:52:14.104917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9861 10:52:14.111586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9862 10:52:14.115443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9863 10:52:14.121561 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9864 10:52:14.125200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9865 10:52:14.128137 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9866 10:52:14.135186 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9867 10:52:14.138116 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9868 10:52:14.145091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9869 10:52:14.148346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9870 10:52:14.155138 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9871 10:52:14.158556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9872 10:52:14.161482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9873 10:52:14.168284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9874 10:52:14.171384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9875 10:52:14.178364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9876 10:52:14.181575 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9877 10:52:14.184608 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9878 10:52:14.191255 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9879 10:52:14.194729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9880 10:52:14.201612 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9881 10:52:14.204698 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9882 10:52:14.208188 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9883 10:52:14.214742 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9884 10:52:14.218565 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9885 10:52:14.224904 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9886 10:52:14.227793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9887 10:52:14.231630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9888 10:52:14.238098 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9889 10:52:14.241103 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9890 10:52:14.247820 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9891 10:52:14.251186 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9892 10:52:14.254477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9893 10:52:14.261586 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9894 10:52:14.264639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9895 10:52:14.271100 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9896 10:52:14.274734 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9897 10:52:14.280912 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9898 10:52:14.284151 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9899 10:52:14.288001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9900 10:52:14.294512 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9901 10:52:14.298101 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9902 10:52:14.304278 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9903 10:52:14.307565 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9904 10:52:14.314314 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9905 10:52:14.318322 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9906 10:52:14.320894 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9907 10:52:14.327575 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9908 10:52:14.330972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9909 10:52:14.337612 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9910 10:52:14.340917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9911 10:52:14.347250 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9912 10:52:14.351047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9913 10:52:14.354113 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9914 10:52:14.360726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9915 10:52:14.364013 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9916 10:52:14.370830 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9917 10:52:14.373963 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9918 10:52:14.381004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9919 10:52:14.383774 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9920 10:52:14.387476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9921 10:52:14.393798 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9922 10:52:14.397279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9923 10:52:14.404292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9924 10:52:14.407570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9925 10:52:14.413651 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9926 10:52:14.417420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9927 10:52:14.424148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9928 10:52:14.427245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9929 10:52:14.430698 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9930 10:52:14.437335 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9931 10:52:14.440709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9932 10:52:14.447119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9933 10:52:14.450795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9934 10:52:14.457130 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9935 10:52:14.460295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9936 10:52:14.463638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9937 10:52:14.470409 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9938 10:52:14.473544 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9939 10:52:14.479993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9940 10:52:14.483567 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9941 10:52:14.489885 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9942 10:52:14.493253 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9943 10:52:14.496609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9944 10:52:14.503546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9945 10:52:14.506943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9946 10:52:14.513358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9947 10:52:14.516444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9948 10:52:14.522986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9949 10:52:14.526420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9950 10:52:14.533160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9951 10:52:14.536951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9952 10:52:14.543141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9953 10:52:14.546532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9954 10:52:14.553014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9955 10:52:14.556387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9956 10:52:14.562922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9957 10:52:14.566196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9958 10:52:14.572962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9959 10:52:14.576445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9960 10:52:14.579421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9961 10:52:14.586221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9962 10:52:14.589664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9963 10:52:14.596529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9964 10:52:14.599967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9965 10:52:14.606328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9966 10:52:14.609994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9967 10:52:14.616345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9968 10:52:14.619672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9969 10:52:14.626264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9970 10:52:14.629508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9971 10:52:14.635960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9972 10:52:14.639459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9973 10:52:14.646102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9974 10:52:14.649263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9975 10:52:14.656236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9976 10:52:14.659519 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9977 10:52:14.662972 INFO: [APUAPC] vio 0
9978 10:52:14.665701 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9979 10:52:14.672730 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9980 10:52:14.676234 INFO: [APUAPC] D0_APC_0: 0x400510
9981 10:52:14.679632 INFO: [APUAPC] D0_APC_1: 0x0
9982 10:52:14.682467 INFO: [APUAPC] D0_APC_2: 0x1540
9983 10:52:14.682542 INFO: [APUAPC] D0_APC_3: 0x0
9984 10:52:14.686674 INFO: [APUAPC] D1_APC_0: 0xffffffff
9985 10:52:14.689160 INFO: [APUAPC] D1_APC_1: 0xffffffff
9986 10:52:14.692503 INFO: [APUAPC] D1_APC_2: 0x3fffff
9987 10:52:14.695955 INFO: [APUAPC] D1_APC_3: 0x0
9988 10:52:14.699686 INFO: [APUAPC] D2_APC_0: 0xffffffff
9989 10:52:14.702747 INFO: [APUAPC] D2_APC_1: 0xffffffff
9990 10:52:14.705854 INFO: [APUAPC] D2_APC_2: 0x3fffff
9991 10:52:14.709594 INFO: [APUAPC] D2_APC_3: 0x0
9992 10:52:14.712520 INFO: [APUAPC] D3_APC_0: 0xffffffff
9993 10:52:14.715988 INFO: [APUAPC] D3_APC_1: 0xffffffff
9994 10:52:14.719389 INFO: [APUAPC] D3_APC_2: 0x3fffff
9995 10:52:14.722531 INFO: [APUAPC] D3_APC_3: 0x0
9996 10:52:14.725866 INFO: [APUAPC] D4_APC_0: 0xffffffff
9997 10:52:14.728943 INFO: [APUAPC] D4_APC_1: 0xffffffff
9998 10:52:14.732332 INFO: [APUAPC] D4_APC_2: 0x3fffff
9999 10:52:14.735578 INFO: [APUAPC] D4_APC_3: 0x0
10000 10:52:14.739244 INFO: [APUAPC] D5_APC_0: 0xffffffff
10001 10:52:14.742029 INFO: [APUAPC] D5_APC_1: 0xffffffff
10002 10:52:14.745805 INFO: [APUAPC] D5_APC_2: 0x3fffff
10003 10:52:14.748930 INFO: [APUAPC] D5_APC_3: 0x0
10004 10:52:14.752024 INFO: [APUAPC] D6_APC_0: 0xffffffff
10005 10:52:14.755632 INFO: [APUAPC] D6_APC_1: 0xffffffff
10006 10:52:14.759006 INFO: [APUAPC] D6_APC_2: 0x3fffff
10007 10:52:14.762113 INFO: [APUAPC] D6_APC_3: 0x0
10008 10:52:14.765490 INFO: [APUAPC] D7_APC_0: 0xffffffff
10009 10:52:14.768832 INFO: [APUAPC] D7_APC_1: 0xffffffff
10010 10:52:14.772294 INFO: [APUAPC] D7_APC_2: 0x3fffff
10011 10:52:14.775270 INFO: [APUAPC] D7_APC_3: 0x0
10012 10:52:14.778603 INFO: [APUAPC] D8_APC_0: 0xffffffff
10013 10:52:14.782072 INFO: [APUAPC] D8_APC_1: 0xffffffff
10014 10:52:14.785754 INFO: [APUAPC] D8_APC_2: 0x3fffff
10015 10:52:14.788470 INFO: [APUAPC] D8_APC_3: 0x0
10016 10:52:14.792149 INFO: [APUAPC] D9_APC_0: 0xffffffff
10017 10:52:14.795382 INFO: [APUAPC] D9_APC_1: 0xffffffff
10018 10:52:14.798604 INFO: [APUAPC] D9_APC_2: 0x3fffff
10019 10:52:14.802245 INFO: [APUAPC] D9_APC_3: 0x0
10020 10:52:14.805474 INFO: [APUAPC] D10_APC_0: 0xffffffff
10021 10:52:14.808720 INFO: [APUAPC] D10_APC_1: 0xffffffff
10022 10:52:14.811813 INFO: [APUAPC] D10_APC_2: 0x3fffff
10023 10:52:14.815543 INFO: [APUAPC] D10_APC_3: 0x0
10024 10:52:14.818745 INFO: [APUAPC] D11_APC_0: 0xffffffff
10025 10:52:14.821728 INFO: [APUAPC] D11_APC_1: 0xffffffff
10026 10:52:14.825333 INFO: [APUAPC] D11_APC_2: 0x3fffff
10027 10:52:14.828650 INFO: [APUAPC] D11_APC_3: 0x0
10028 10:52:14.831666 INFO: [APUAPC] D12_APC_0: 0xffffffff
10029 10:52:14.835435 INFO: [APUAPC] D12_APC_1: 0xffffffff
10030 10:52:14.838929 INFO: [APUAPC] D12_APC_2: 0x3fffff
10031 10:52:14.842162 INFO: [APUAPC] D12_APC_3: 0x0
10032 10:52:14.845368 INFO: [APUAPC] D13_APC_0: 0xffffffff
10033 10:52:14.848564 INFO: [APUAPC] D13_APC_1: 0xffffffff
10034 10:52:14.852109 INFO: [APUAPC] D13_APC_2: 0x3fffff
10035 10:52:14.855469 INFO: [APUAPC] D13_APC_3: 0x0
10036 10:52:14.858781 INFO: [APUAPC] D14_APC_0: 0xffffffff
10037 10:52:14.861693 INFO: [APUAPC] D14_APC_1: 0xffffffff
10038 10:52:14.864981 INFO: [APUAPC] D14_APC_2: 0x3fffff
10039 10:52:14.868427 INFO: [APUAPC] D14_APC_3: 0x0
10040 10:52:14.871777 INFO: [APUAPC] D15_APC_0: 0xffffffff
10041 10:52:14.874831 INFO: [APUAPC] D15_APC_1: 0xffffffff
10042 10:52:14.878798 INFO: [APUAPC] D15_APC_2: 0x3fffff
10043 10:52:14.881477 INFO: [APUAPC] D15_APC_3: 0x0
10044 10:52:14.885170 INFO: [APUAPC] APC_CON: 0x4
10045 10:52:14.888479 INFO: [NOCDAPC] D0_APC_0: 0x0
10046 10:52:14.888578 INFO: [NOCDAPC] D0_APC_1: 0x0
10047 10:52:14.891726 INFO: [NOCDAPC] D1_APC_0: 0x0
10048 10:52:14.895033 INFO: [NOCDAPC] D1_APC_1: 0xfff
10049 10:52:14.898190 INFO: [NOCDAPC] D2_APC_0: 0x0
10050 10:52:14.901537 INFO: [NOCDAPC] D2_APC_1: 0xfff
10051 10:52:14.905256 INFO: [NOCDAPC] D3_APC_0: 0x0
10052 10:52:14.908530 INFO: [NOCDAPC] D3_APC_1: 0xfff
10053 10:52:14.911731 INFO: [NOCDAPC] D4_APC_0: 0x0
10054 10:52:14.914713 INFO: [NOCDAPC] D4_APC_1: 0xfff
10055 10:52:14.918348 INFO: [NOCDAPC] D5_APC_0: 0x0
10056 10:52:14.918418 INFO: [NOCDAPC] D5_APC_1: 0xfff
10057 10:52:14.922412 INFO: [NOCDAPC] D6_APC_0: 0x0
10058 10:52:14.924965 INFO: [NOCDAPC] D6_APC_1: 0xfff
10059 10:52:14.928018 INFO: [NOCDAPC] D7_APC_0: 0x0
10060 10:52:14.931778 INFO: [NOCDAPC] D7_APC_1: 0xfff
10061 10:52:14.935270 INFO: [NOCDAPC] D8_APC_0: 0x0
10062 10:52:14.938242 INFO: [NOCDAPC] D8_APC_1: 0xfff
10063 10:52:14.941392 INFO: [NOCDAPC] D9_APC_0: 0x0
10064 10:52:14.944487 INFO: [NOCDAPC] D9_APC_1: 0xfff
10065 10:52:14.948208 INFO: [NOCDAPC] D10_APC_0: 0x0
10066 10:52:14.951582 INFO: [NOCDAPC] D10_APC_1: 0xfff
10067 10:52:14.954799 INFO: [NOCDAPC] D11_APC_0: 0x0
10068 10:52:14.958054 INFO: [NOCDAPC] D11_APC_1: 0xfff
10069 10:52:14.958156 INFO: [NOCDAPC] D12_APC_0: 0x0
10070 10:52:14.961672 INFO: [NOCDAPC] D12_APC_1: 0xfff
10071 10:52:14.964515 INFO: [NOCDAPC] D13_APC_0: 0x0
10072 10:52:14.967862 INFO: [NOCDAPC] D13_APC_1: 0xfff
10073 10:52:14.971376 INFO: [NOCDAPC] D14_APC_0: 0x0
10074 10:52:14.974770 INFO: [NOCDAPC] D14_APC_1: 0xfff
10075 10:52:14.978133 INFO: [NOCDAPC] D15_APC_0: 0x0
10076 10:52:14.981516 INFO: [NOCDAPC] D15_APC_1: 0xfff
10077 10:52:14.984465 INFO: [NOCDAPC] APC_CON: 0x4
10078 10:52:14.987739 INFO: [APUAPC] set_apusys_apc done
10079 10:52:14.991120 INFO: [DEVAPC] devapc_init done
10080 10:52:14.995045 INFO: GICv3 without legacy support detected.
10081 10:52:14.998179 INFO: ARM GICv3 driver initialized in EL3
10082 10:52:15.001520 INFO: Maximum SPI INTID supported: 639
10083 10:52:15.007663 INFO: BL31: Initializing runtime services
10084 10:52:15.011524 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10085 10:52:15.014435 INFO: SPM: enable CPC mode
10086 10:52:15.021523 INFO: mcdi ready for mcusys-off-idle and system suspend
10087 10:52:15.024314 INFO: BL31: Preparing for EL3 exit to normal world
10088 10:52:15.027831 INFO: Entry point address = 0x80000000
10089 10:52:15.030808 INFO: SPSR = 0x8
10090 10:52:15.036355
10091 10:52:15.036438
10092 10:52:15.036512
10093 10:52:15.039456 Starting depthcharge on Spherion...
10094 10:52:15.039548
10095 10:52:15.039635 Wipe memory regions:
10096 10:52:15.039727
10097 10:52:15.040569 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10098 10:52:15.040699 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10099 10:52:15.040818 Setting prompt string to ['asurada:']
10100 10:52:15.041203 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10101 10:52:15.042799 [0x00000040000000, 0x00000054600000)
10102 10:52:15.164883
10103 10:52:15.165018 [0x00000054660000, 0x00000080000000)
10104 10:52:15.425548
10105 10:52:15.425691 [0x000000821a7280, 0x000000ffe64000)
10106 10:52:16.170750
10107 10:52:16.170925 [0x00000100000000, 0x00000240000000)
10108 10:52:18.060540
10109 10:52:18.063840 Initializing XHCI USB controller at 0x11200000.
10110 10:52:19.102095
10111 10:52:19.105085 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10112 10:52:19.105171
10113 10:52:19.105243
10114 10:52:19.105309
10115 10:52:19.105585 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 10:52:19.205880 asurada: tftpboot 192.168.201.1 10591012/tftp-deploy-70bw0c7d/kernel/image.itb 10591012/tftp-deploy-70bw0c7d/kernel/cmdline
10118 10:52:19.206053 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10119 10:52:19.206152 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10120 10:52:19.210241 tftpboot 192.168.201.1 10591012/tftp-deploy-70bw0c7d/kernel/image.itp-deploy-70bw0c7d/kernel/cmdline
10121 10:52:19.210327
10122 10:52:19.210393 Waiting for link
10123 10:52:19.370484
10124 10:52:19.370640 R8152: Initializing
10125 10:52:19.370711
10126 10:52:19.373780 Version 6 (ocp_data = 5c30)
10127 10:52:19.373857
10128 10:52:19.377825 R8152: Done initializing
10129 10:52:19.377902
10130 10:52:19.377965 Adding net device
10131 10:52:21.311561
10132 10:52:21.311703 done.
10133 10:52:21.311781
10134 10:52:21.311847 MAC: 00:24:32:30:78:52
10135 10:52:21.311943
10136 10:52:21.314881 Sending DHCP discover... done.
10137 10:52:21.314961
10138 10:52:31.132692 Waiting for reply... R8152: Bulk read error 0xffffffbf
10139 10:52:31.132850
10140 10:52:31.136074 Receive failed.
10141 10:52:31.136152
10142 10:52:31.136224 done.
10143 10:52:31.136284
10144 10:52:31.139439 Sending DHCP request... done.
10145 10:52:31.139520
10146 10:52:31.142973 Waiting for reply... done.
10147 10:52:31.143047
10148 10:52:31.143108 My ip is 192.168.201.14
10149 10:52:31.143168
10150 10:52:31.146259 The DHCP server ip is 192.168.201.1
10151 10:52:31.146329
10152 10:52:31.152517 TFTP server IP predefined by user: 192.168.201.1
10153 10:52:31.152595
10154 10:52:31.159401 Bootfile predefined by user: 10591012/tftp-deploy-70bw0c7d/kernel/image.itb
10155 10:52:31.159483
10156 10:52:31.162671 Sending tftp read request... done.
10157 10:52:31.162758
10158 10:52:31.166300 Waiting for the transfer...
10159 10:52:31.166423
10160 10:52:31.709898 00000000 ################################################################
10161 10:52:31.710028
10162 10:52:32.254666 00080000 ################################################################
10163 10:52:32.254802
10164 10:52:32.796894 00100000 ################################################################
10165 10:52:32.797045
10166 10:52:33.339816 00180000 ################################################################
10167 10:52:33.339959
10168 10:52:33.859090 00200000 ################################################################
10169 10:52:33.859232
10170 10:52:34.385116 00280000 ################################################################
10171 10:52:34.385273
10172 10:52:34.922705 00300000 ################################################################
10173 10:52:34.922849
10174 10:52:35.451705 00380000 ################################################################
10175 10:52:35.451846
10176 10:52:35.978628 00400000 ################################################################
10177 10:52:35.978771
10178 10:52:36.494979 00480000 ################################################################
10179 10:52:36.495164
10180 10:52:37.011756 00500000 ################################################################
10181 10:52:37.011933
10182 10:52:37.529003 00580000 ################################################################
10183 10:52:37.529161
10184 10:52:38.052578 00600000 ################################################################
10185 10:52:38.052731
10186 10:52:38.572308 00680000 ################################################################
10187 10:52:38.572463
10188 10:52:39.088530 00700000 ################################################################
10189 10:52:39.088673
10190 10:52:39.607199 00780000 ################################################################
10191 10:52:39.607345
10192 10:52:40.135428 00800000 ################################################################
10193 10:52:40.135558
10194 10:52:40.663817 00880000 ################################################################
10195 10:52:40.663949
10196 10:52:41.183533 00900000 ################################################################
10197 10:52:41.183668
10198 10:52:41.717093 00980000 ################################################################
10199 10:52:41.717228
10200 10:52:42.243644 00a00000 ################################################################
10201 10:52:42.243822
10202 10:52:42.764887 00a80000 ################################################################
10203 10:52:42.765048
10204 10:52:43.288727 00b00000 ################################################################
10205 10:52:43.288889
10206 10:52:43.837229 00b80000 ################################################################
10207 10:52:43.837889
10208 10:52:44.422567 00c00000 ################################################################
10209 10:52:44.422714
10210 10:52:44.941363 00c80000 ################################################################
10211 10:52:44.941499
10212 10:52:45.468977 00d00000 ################################################################
10213 10:52:45.469115
10214 10:52:46.001889 00d80000 ################################################################
10215 10:52:46.002061
10216 10:52:46.546902 00e00000 ################################################################
10217 10:52:46.547076
10218 10:52:47.074886 00e80000 ################################################################
10219 10:52:47.075071
10220 10:52:47.605962 00f00000 ################################################################
10221 10:52:47.606127
10222 10:52:48.125560 00f80000 ################################################################
10223 10:52:48.125699
10224 10:52:48.663661 01000000 ################################################################
10225 10:52:48.663801
10226 10:52:49.191498 01080000 ################################################################
10227 10:52:49.191639
10228 10:52:49.735001 01100000 ################################################################
10229 10:52:49.735150
10230 10:52:50.269629 01180000 ################################################################
10231 10:52:50.269778
10232 10:52:50.814790 01200000 ################################################################
10233 10:52:50.814953
10234 10:52:51.371361 01280000 ################################################################
10235 10:52:51.371508
10236 10:52:51.895532 01300000 ################################################################
10237 10:52:51.895689
10238 10:52:52.428334 01380000 ################################################################
10239 10:52:52.428490
10240 10:52:52.973306 01400000 ################################################################
10241 10:52:52.973447
10242 10:52:53.523207 01480000 ################################################################
10243 10:52:53.523345
10244 10:52:54.055526 01500000 ################################################################
10245 10:52:54.055660
10246 10:52:54.648049 01580000 ################################################################
10247 10:52:54.648204
10248 10:52:55.245508 01600000 ################################################################
10249 10:52:55.245664
10250 10:52:55.835867 01680000 ################################################################
10251 10:52:55.836002
10252 10:52:56.413588 01700000 ################################################################
10253 10:52:56.413733
10254 10:52:57.013131 01780000 ################################################################
10255 10:52:57.013270
10256 10:52:57.598417 01800000 ################################################################
10257 10:52:57.598558
10258 10:52:58.198005 01880000 ################################################################
10259 10:52:58.198145
10260 10:52:58.797279 01900000 ################################################################
10261 10:52:58.797433
10262 10:52:59.400287 01980000 ################################################################
10263 10:52:59.400436
10264 10:52:59.978788 01a00000 ############################################################## done.
10265 10:52:59.978944
10266 10:52:59.982127 The bootfile was 27768626 bytes long.
10267 10:52:59.982221
10268 10:52:59.985613 Sending tftp read request... done.
10269 10:52:59.985701
10270 10:52:59.985765 Waiting for the transfer...
10271 10:52:59.985825
10272 10:52:59.988966 00000000 # done.
10273 10:52:59.989054
10274 10:52:59.995070 Command line loaded dynamically from TFTP file: 10591012/tftp-deploy-70bw0c7d/kernel/cmdline
10275 10:52:59.995198
10276 10:53:00.015229 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10277 10:53:00.015419
10278 10:53:00.018615 Loading FIT.
10279 10:53:00.018700
10280 10:53:00.021999 Image ramdisk-1 has 17637731 bytes.
10281 10:53:00.022083
10282 10:53:00.022147 Image fdt-1 has 46924 bytes.
10283 10:53:00.022206
10284 10:53:00.025502 Image kernel-1 has 10081937 bytes.
10285 10:53:00.025586
10286 10:53:00.035327 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10287 10:53:00.035465
10288 10:53:00.051723 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10289 10:53:00.051873
10290 10:53:00.058187 Choosing best match conf-1 for compat google,spherion-rev2.
10291 10:53:00.062252
10292 10:53:00.066370 Connected to device vid:did:rid of 1ae0:0028:00
10293 10:53:00.073416
10294 10:53:00.077192 tpm_get_response: command 0x17b, return code 0x0
10295 10:53:00.077292
10296 10:53:00.079978 ec_init: CrosEC protocol v3 supported (256, 248)
10297 10:53:00.084564
10298 10:53:00.087872 tpm_cleanup: add release locality here.
10299 10:53:00.087962
10300 10:53:00.088026 Shutting down all USB controllers.
10301 10:53:00.091499
10302 10:53:00.091584 Removing current net device
10303 10:53:00.091650
10304 10:53:00.098159 Exiting depthcharge with code 4 at timestamp: 74460004
10305 10:53:00.098262
10306 10:53:00.101330 LZMA decompressing kernel-1 to 0x821a6718
10307 10:53:00.101417
10308 10:53:00.104829 LZMA decompressing kernel-1 to 0x40000000
10309 10:53:01.370572
10310 10:53:01.370725 jumping to kernel
10311 10:53:01.371130 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10312 10:53:01.371229 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10313 10:53:01.371305 Setting prompt string to ['Linux version [0-9]']
10314 10:53:01.371434 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10315 10:53:01.371503 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10316 10:53:01.452176
10317 10:53:01.455369 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10318 10:53:01.459169 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10319 10:53:01.459276 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10320 10:53:01.459365 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10321 10:53:01.459454 Using line separator: #'\n'#
10322 10:53:01.459530 No login prompt set.
10323 10:53:01.459603 Parsing kernel messages
10324 10:53:01.459674 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10325 10:53:01.459832 [login-action] Waiting for messages, (timeout 00:03:39)
10326 10:53:01.478848 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10327 10:53:01.482231 [ 0.000000] random: crng init done
10328 10:53:01.485345 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10329 10:53:01.488531 [ 0.000000] efi: UEFI not found.
10330 10:53:01.498985 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10331 10:53:01.505235 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10332 10:53:01.515693 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10333 10:53:01.525577 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10334 10:53:01.532456 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10335 10:53:01.535185 [ 0.000000] printk: bootconsole [mtk8250] enabled
10336 10:53:01.543692 [ 0.000000] NUMA: No NUMA configuration found
10337 10:53:01.550555 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10338 10:53:01.557144 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10339 10:53:01.557225 [ 0.000000] Zone ranges:
10340 10:53:01.563888 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10341 10:53:01.567314 [ 0.000000] DMA32 empty
10342 10:53:01.573973 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10343 10:53:01.576586 [ 0.000000] Movable zone start for each node
10344 10:53:01.580136 [ 0.000000] Early memory node ranges
10345 10:53:01.586896 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10346 10:53:01.593436 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10347 10:53:01.600092 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10348 10:53:01.606896 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10349 10:53:01.613212 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10350 10:53:01.619848 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10351 10:53:01.676390 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10352 10:53:01.682927 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10353 10:53:01.689267 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10354 10:53:01.692638 [ 0.000000] psci: probing for conduit method from DT.
10355 10:53:01.699146 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10356 10:53:01.703386 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10357 10:53:01.709347 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10358 10:53:01.713046 [ 0.000000] psci: SMC Calling Convention v1.2
10359 10:53:01.719629 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10360 10:53:01.722559 [ 0.000000] Detected VIPT I-cache on CPU0
10361 10:53:01.729385 [ 0.000000] CPU features: detected: GIC system register CPU interface
10362 10:53:01.735968 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10363 10:53:01.742473 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10364 10:53:01.749091 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10365 10:53:01.755610 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10366 10:53:01.766001 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10367 10:53:01.768907 [ 0.000000] alternatives: applying boot alternatives
10368 10:53:01.775621 [ 0.000000] Fallback order for Node 0: 0
10369 10:53:01.782101 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10370 10:53:01.785693 [ 0.000000] Policy zone: Normal
10371 10:53:01.805397 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10372 10:53:01.815196 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10373 10:53:01.825794 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10374 10:53:01.835618 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10375 10:53:01.842310 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10376 10:53:01.845210 <6>[ 0.000000] software IO TLB: area num 8.
10377 10:53:01.902056 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10378 10:53:02.051572 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10379 10:53:02.058199 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10380 10:53:02.065032 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10381 10:53:02.068079 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10382 10:53:02.074892 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10383 10:53:02.081295 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10384 10:53:02.084651 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10385 10:53:02.094597 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10386 10:53:02.101231 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10387 10:53:02.107760 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10388 10:53:02.114197 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10389 10:53:02.117389 <6>[ 0.000000] GICv3: 608 SPIs implemented
10390 10:53:02.121329 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10391 10:53:02.127621 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10392 10:53:02.131254 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10393 10:53:02.137321 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10394 10:53:02.150690 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10395 10:53:02.163990 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10396 10:53:02.170413 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10397 10:53:02.178277 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10398 10:53:02.191586 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10399 10:53:02.197735 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10400 10:53:02.204667 <6>[ 0.009178] Console: colour dummy device 80x25
10401 10:53:02.214570 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10402 10:53:02.220938 <6>[ 0.024443] pid_max: default: 32768 minimum: 301
10403 10:53:02.224730 <6>[ 0.029346] LSM: Security Framework initializing
10404 10:53:02.231038 <6>[ 0.034287] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10405 10:53:02.240938 <6>[ 0.042100] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 10:53:02.250990 <6>[ 0.051579] cblist_init_generic: Setting adjustable number of callback queues.
10407 10:53:02.254136 <6>[ 0.059076] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 10:53:02.260744 <6>[ 0.065414] cblist_init_generic: Setting shift to 3 and lim to 1.
10409 10:53:02.267608 <6>[ 0.071824] rcu: Hierarchical SRCU implementation.
10410 10:53:02.274131 <6>[ 0.076838] rcu: Max phase no-delay instances is 1000.
10411 10:53:02.280674 <6>[ 0.083853] EFI services will not be available.
10412 10:53:02.283861 <6>[ 0.088853] smp: Bringing up secondary CPUs ...
10413 10:53:02.291770 <6>[ 0.093904] Detected VIPT I-cache on CPU1
10414 10:53:02.298524 <6>[ 0.093977] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10415 10:53:02.305524 <6>[ 0.094006] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10416 10:53:02.308377 <6>[ 0.094343] Detected VIPT I-cache on CPU2
10417 10:53:02.315190 <6>[ 0.094393] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10418 10:53:02.321461 <6>[ 0.094409] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10419 10:53:02.328133 <6>[ 0.094665] Detected VIPT I-cache on CPU3
10420 10:53:02.334618 <6>[ 0.094707] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10421 10:53:02.341758 <6>[ 0.094720] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10422 10:53:02.345008 <6>[ 0.095011] CPU features: detected: Spectre-v4
10423 10:53:02.351388 <6>[ 0.095016] CPU features: detected: Spectre-BHB
10424 10:53:02.354921 <6>[ 0.095021] Detected PIPT I-cache on CPU4
10425 10:53:02.361467 <6>[ 0.095072] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10426 10:53:02.368527 <6>[ 0.095088] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10427 10:53:02.374677 <6>[ 0.095385] Detected PIPT I-cache on CPU5
10428 10:53:02.381282 <6>[ 0.095446] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10429 10:53:02.387996 <6>[ 0.095462] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10430 10:53:02.391086 <6>[ 0.095744] Detected PIPT I-cache on CPU6
10431 10:53:02.398021 <6>[ 0.095811] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10432 10:53:02.404653 <6>[ 0.095827] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10433 10:53:02.411149 <6>[ 0.096127] Detected PIPT I-cache on CPU7
10434 10:53:02.417429 <6>[ 0.096192] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10435 10:53:02.424508 <6>[ 0.096208] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10436 10:53:02.427790 <6>[ 0.096256] smp: Brought up 1 node, 8 CPUs
10437 10:53:02.434044 <6>[ 0.237499] SMP: Total of 8 processors activated.
10438 10:53:02.437578 <6>[ 0.242450] CPU features: detected: 32-bit EL0 Support
10439 10:53:02.447136 <6>[ 0.247813] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10440 10:53:02.454282 <6>[ 0.256613] CPU features: detected: Common not Private translations
10441 10:53:02.457677 <6>[ 0.263088] CPU features: detected: CRC32 instructions
10442 10:53:02.463953 <6>[ 0.268440] CPU features: detected: RCpc load-acquire (LDAPR)
10443 10:53:02.470675 <6>[ 0.274399] CPU features: detected: LSE atomic instructions
10444 10:53:02.476993 <6>[ 0.280180] CPU features: detected: Privileged Access Never
10445 10:53:02.480575 <6>[ 0.285960] CPU features: detected: RAS Extension Support
10446 10:53:02.490903 <6>[ 0.291568] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10447 10:53:02.493357 <6>[ 0.298795] CPU: All CPU(s) started at EL2
10448 10:53:02.500172 <6>[ 0.303138] alternatives: applying system-wide alternatives
10449 10:53:02.509440 <6>[ 0.313872] devtmpfs: initialized
10450 10:53:02.525217 <6>[ 0.323043] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10451 10:53:02.531620 <6>[ 0.333005] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10452 10:53:02.538205 <6>[ 0.341222] pinctrl core: initialized pinctrl subsystem
10453 10:53:02.541614 <6>[ 0.347885] DMI not present or invalid.
10454 10:53:02.548090 <6>[ 0.352293] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10455 10:53:02.558075 <6>[ 0.359189] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10456 10:53:02.564669 <6>[ 0.366769] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10457 10:53:02.574544 <6>[ 0.374997] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10458 10:53:02.578016 <6>[ 0.383240] audit: initializing netlink subsys (disabled)
10459 10:53:02.588195 <5>[ 0.388939] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10460 10:53:02.594650 <6>[ 0.389654] thermal_sys: Registered thermal governor 'step_wise'
10461 10:53:02.601483 <6>[ 0.396907] thermal_sys: Registered thermal governor 'power_allocator'
10462 10:53:02.604452 <6>[ 0.403164] cpuidle: using governor menu
10463 10:53:02.611041 <6>[ 0.414123] NET: Registered PF_QIPCRTR protocol family
10464 10:53:02.617688 <6>[ 0.419612] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10465 10:53:02.624744 <6>[ 0.426713] ASID allocator initialised with 32768 entries
10466 10:53:02.627800 <6>[ 0.433298] Serial: AMBA PL011 UART driver
10467 10:53:02.637612 <4>[ 0.442044] Trying to register duplicate clock ID: 134
10468 10:53:02.693441 <6>[ 0.501431] KASLR enabled
10469 10:53:02.708035 <6>[ 0.509253] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10470 10:53:02.714407 <6>[ 0.516264] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10471 10:53:02.721825 <6>[ 0.522752] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10472 10:53:02.728253 <6>[ 0.529759] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10473 10:53:02.734475 <6>[ 0.536244] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10474 10:53:02.741607 <6>[ 0.543247] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10475 10:53:02.747798 <6>[ 0.549734] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10476 10:53:02.754244 <6>[ 0.556740] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10477 10:53:02.757847 <6>[ 0.564211] ACPI: Interpreter disabled.
10478 10:53:02.766009 <6>[ 0.570614] iommu: Default domain type: Translated
10479 10:53:02.772903 <6>[ 0.575725] iommu: DMA domain TLB invalidation policy: strict mode
10480 10:53:02.775951 <5>[ 0.582375] SCSI subsystem initialized
10481 10:53:02.782920 <6>[ 0.586543] usbcore: registered new interface driver usbfs
10482 10:53:02.789368 <6>[ 0.592275] usbcore: registered new interface driver hub
10483 10:53:02.792328 <6>[ 0.597826] usbcore: registered new device driver usb
10484 10:53:02.799250 <6>[ 0.603900] pps_core: LinuxPPS API ver. 1 registered
10485 10:53:02.809302 <6>[ 0.609095] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10486 10:53:02.812559 <6>[ 0.618440] PTP clock support registered
10487 10:53:02.815973 <6>[ 0.622682] EDAC MC: Ver: 3.0.0
10488 10:53:02.823383 <6>[ 0.627831] FPGA manager framework
10489 10:53:02.829977 <6>[ 0.631511] Advanced Linux Sound Architecture Driver Initialized.
10490 10:53:02.833054 <6>[ 0.638284] vgaarb: loaded
10491 10:53:02.839683 <6>[ 0.641472] clocksource: Switched to clocksource arch_sys_counter
10492 10:53:02.843294 <5>[ 0.647894] VFS: Disk quotas dquot_6.6.0
10493 10:53:02.849665 <6>[ 0.652079] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10494 10:53:02.853172 <6>[ 0.659270] pnp: PnP ACPI: disabled
10495 10:53:02.861501 <6>[ 0.666013] NET: Registered PF_INET protocol family
10496 10:53:02.871335 <6>[ 0.671611] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10497 10:53:02.882340 <6>[ 0.683913] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10498 10:53:02.892593 <6>[ 0.692728] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10499 10:53:02.899196 <6>[ 0.700699] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10500 10:53:02.908986 <6>[ 0.709396] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10501 10:53:02.915955 <6>[ 0.719137] TCP: Hash tables configured (established 65536 bind 65536)
10502 10:53:02.922798 <6>[ 0.725993] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10503 10:53:02.932396 <6>[ 0.733188] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10504 10:53:02.935329 <6>[ 0.740887] NET: Registered PF_UNIX/PF_LOCAL protocol family
10505 10:53:02.942602 <6>[ 0.747048] RPC: Registered named UNIX socket transport module.
10506 10:53:02.948965 <6>[ 0.753203] RPC: Registered udp transport module.
10507 10:53:02.952321 <6>[ 0.758136] RPC: Registered tcp transport module.
10508 10:53:02.959066 <6>[ 0.763068] RPC: Registered tcp NFSv4.1 backchannel transport module.
10509 10:53:02.965581 <6>[ 0.769733] PCI: CLS 0 bytes, default 64
10510 10:53:02.968887 <6>[ 0.774083] Unpacking initramfs...
10511 10:53:02.975802 <6>[ 0.778193] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10512 10:53:02.985414 <6>[ 0.786850] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10513 10:53:02.992140 <6>[ 0.795730] kvm [1]: IPA Size Limit: 40 bits
10514 10:53:02.995646 <6>[ 0.800276] kvm [1]: GICv3: no GICV resource entry
10515 10:53:02.999330 <6>[ 0.805296] kvm [1]: disabling GICv2 emulation
10516 10:53:03.005669 <6>[ 0.809982] kvm [1]: GIC system register CPU interface enabled
10517 10:53:03.012166 <6>[ 0.816142] kvm [1]: vgic interrupt IRQ18
10518 10:53:03.015192 <6>[ 0.820499] kvm [1]: VHE mode initialized successfully
10519 10:53:03.022329 <5>[ 0.826924] Initialise system trusted keyrings
10520 10:53:03.029075 <6>[ 0.831756] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10521 10:53:03.037321 <6>[ 0.841914] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10522 10:53:03.044328 <5>[ 0.848321] NFS: Registering the id_resolver key type
10523 10:53:03.047115 <5>[ 0.853622] Key type id_resolver registered
10524 10:53:03.053617 <5>[ 0.858036] Key type id_legacy registered
10525 10:53:03.060299 <6>[ 0.862314] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10526 10:53:03.067328 <6>[ 0.869235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10527 10:53:03.073369 <6>[ 0.876971] 9p: Installing v9fs 9p2000 file system support
10528 10:53:03.110818 <5>[ 0.915410] Key type asymmetric registered
10529 10:53:03.114010 <5>[ 0.919742] Asymmetric key parser 'x509' registered
10530 10:53:03.124232 <6>[ 0.924903] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10531 10:53:03.127217 <6>[ 0.932517] io scheduler mq-deadline registered
10532 10:53:03.130830 <6>[ 0.937277] io scheduler kyber registered
10533 10:53:03.149611 <6>[ 0.954233] EINJ: ACPI disabled.
10534 10:53:03.181995 <4>[ 0.980146] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 10:53:03.191814 <4>[ 0.990799] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 10:53:03.207085 <6>[ 1.011750] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10537 10:53:03.215112 <6>[ 1.019848] printk: console [ttyS0] disabled
10538 10:53:03.243251 <6>[ 1.044506] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10539 10:53:03.249983 <6>[ 1.053995] printk: console [ttyS0] enabled
10540 10:53:03.253201 <6>[ 1.053995] printk: console [ttyS0] enabled
10541 10:53:03.260016 <6>[ 1.062890] printk: bootconsole [mtk8250] disabled
10542 10:53:03.262900 <6>[ 1.062890] printk: bootconsole [mtk8250] disabled
10543 10:53:03.269955 <6>[ 1.074187] SuperH (H)SCI(F) driver initialized
10544 10:53:03.273265 <6>[ 1.079472] msm_serial: driver initialized
10545 10:53:03.286876 <6>[ 1.088431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10546 10:53:03.296737 <6>[ 1.096981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10547 10:53:03.303554 <6>[ 1.105524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10548 10:53:03.313618 <6>[ 1.114152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10549 10:53:03.323177 <6>[ 1.122857] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10550 10:53:03.329853 <6>[ 1.131581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10551 10:53:03.339894 <6>[ 1.140127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10552 10:53:03.346613 <6>[ 1.148927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10553 10:53:03.356645 <6>[ 1.157473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10554 10:53:03.368313 <6>[ 1.173311] loop: module loaded
10555 10:53:03.375145 <6>[ 1.179434] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10556 10:53:03.397901 <4>[ 1.202844] mtk-pmic-keys: Failed to locate of_node [id: -1]
10557 10:53:03.405223 <6>[ 1.209647] megasas: 07.719.03.00-rc1
10558 10:53:03.414197 <6>[ 1.219163] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10559 10:53:03.424502 <6>[ 1.228853] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10560 10:53:03.440941 <6>[ 1.245543] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10561 10:53:03.501731 <6>[ 1.299995] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10562 10:53:03.739395 <6>[ 1.544045] Freeing initrd memory: 17220K
10563 10:53:03.749880 <6>[ 1.554340] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10564 10:53:03.760809 <6>[ 1.565151] tun: Universal TUN/TAP device driver, 1.6
10565 10:53:03.763633 <6>[ 1.571202] thunder_xcv, ver 1.0
10566 10:53:03.767061 <6>[ 1.574710] thunder_bgx, ver 1.0
10567 10:53:03.770567 <6>[ 1.578204] nicpf, ver 1.0
10568 10:53:03.780821 <6>[ 1.582220] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10569 10:53:03.784361 <6>[ 1.589698] hns3: Copyright (c) 2017 Huawei Corporation.
10570 10:53:03.790797 <6>[ 1.595289] hclge is initializing
10571 10:53:03.793873 <6>[ 1.598867] e1000: Intel(R) PRO/1000 Network Driver
10572 10:53:03.800824 <6>[ 1.603996] e1000: Copyright (c) 1999-2006 Intel Corporation.
10573 10:53:03.803911 <6>[ 1.610009] e1000e: Intel(R) PRO/1000 Network Driver
10574 10:53:03.810812 <6>[ 1.615225] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10575 10:53:03.817669 <6>[ 1.621409] igb: Intel(R) Gigabit Ethernet Network Driver
10576 10:53:03.823941 <6>[ 1.627059] igb: Copyright (c) 2007-2014 Intel Corporation.
10577 10:53:03.830370 <6>[ 1.632894] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10578 10:53:03.837152 <6>[ 1.639412] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10579 10:53:03.840394 <6>[ 1.645874] sky2: driver version 1.30
10580 10:53:03.847182 <6>[ 1.650858] VFIO - User Level meta-driver version: 0.3
10581 10:53:03.854167 <6>[ 1.659020] usbcore: registered new interface driver usb-storage
10582 10:53:03.861339 <6>[ 1.665469] usbcore: registered new device driver onboard-usb-hub
10583 10:53:03.869895 <6>[ 1.674513] mt6397-rtc mt6359-rtc: registered as rtc0
10584 10:53:03.879749 <6>[ 1.679980] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:53:04 UTC (1685962384)
10585 10:53:03.883042 <6>[ 1.689546] i2c_dev: i2c /dev entries driver
10586 10:53:03.900170 <6>[ 1.701204] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10587 10:53:03.906692 <6>[ 1.711415] sdhci: Secure Digital Host Controller Interface driver
10588 10:53:03.913289 <6>[ 1.717853] sdhci: Copyright(c) Pierre Ossman
10589 10:53:03.920043 <6>[ 1.723251] Synopsys Designware Multimedia Card Interface Driver
10590 10:53:03.923320 <6>[ 1.729909] mmc0: CQHCI version 5.10
10591 10:53:03.930151 <6>[ 1.730408] sdhci-pltfm: SDHCI platform and OF driver helper
10592 10:53:03.937983 <6>[ 1.741846] ledtrig-cpu: registered to indicate activity on CPUs
10593 10:53:03.948003 <6>[ 1.749167] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10594 10:53:03.951022 <6>[ 1.756562] usbcore: registered new interface driver usbhid
10595 10:53:03.958071 <6>[ 1.762389] usbhid: USB HID core driver
10596 10:53:03.964281 <6>[ 1.766624] spi_master spi0: will run message pump with realtime priority
10597 10:53:04.013090 <6>[ 1.810787] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10598 10:53:04.020625 <6>[ 1.825035] mmc0: Command Queue Engine enabled
10599 10:53:04.027176 <6>[ 1.829770] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10600 10:53:04.033701 <6>[ 1.837207] mmcblk0: mmc0:0001 DA4128 116 GiB
10601 10:53:04.046655 <6>[ 1.842589] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10602 10:53:04.053290 <6>[ 1.845530] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 10:53:04.060251 <6>[ 1.863090] cros-ec-spi spi0.0: Chrome EC device registered
10604 10:53:04.063557 <6>[ 1.863414] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10605 10:53:04.070139 <6>[ 1.875001] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 10:53:04.076928 <6>[ 1.881077] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 10:53:04.100196 <6>[ 1.901829] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10608 10:53:04.108701 <6>[ 1.913256] NET: Registered PF_PACKET protocol family
10609 10:53:04.111696 <6>[ 1.918676] 9pnet: Installing 9P2000 support
10610 10:53:04.118478 <5>[ 1.923239] Key type dns_resolver registered
10611 10:53:04.121975 <6>[ 1.928443] registered taskstats version 1
10612 10:53:04.128536 <5>[ 1.932839] Loading compiled-in X.509 certificates
10613 10:53:04.161467 <4>[ 1.959696] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 10:53:04.171687 <4>[ 1.970397] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 10:53:04.181348 <3>[ 1.983030] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10616 10:53:04.193680 <6>[ 1.998396] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10617 10:53:04.200707 <6>[ 2.005137] xhci-mtk 11200000.usb: xHCI Host Controller
10618 10:53:04.207029 <6>[ 2.010634] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10619 10:53:04.216878 <6>[ 2.018493] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10620 10:53:04.223597 <6>[ 2.027948] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10621 10:53:04.230149 <6>[ 2.034167] xhci-mtk 11200000.usb: xHCI Host Controller
10622 10:53:04.236927 <6>[ 2.039663] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 10:53:04.243518 <6>[ 2.047325] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10624 10:53:04.250299 <6>[ 2.055228] hub 1-0:1.0: USB hub found
10625 10:53:04.253615 <6>[ 2.059262] hub 1-0:1.0: 1 port detected
10626 10:53:04.263687 <6>[ 2.063618] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10627 10:53:04.266973 <6>[ 2.072399] hub 2-0:1.0: USB hub found
10628 10:53:04.270804 <6>[ 2.076433] hub 2-0:1.0: 1 port detected
10629 10:53:04.279110 <6>[ 2.083589] mtk-msdc 11f70000.mmc: Got CD GPIO
10630 10:53:04.296167 <6>[ 2.097557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10631 10:53:04.302943 <6>[ 2.105581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10632 10:53:04.313045 <4>[ 2.113561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10633 10:53:04.323024 <6>[ 2.123218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10634 10:53:04.329557 <6>[ 2.131300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10635 10:53:04.336475 <6>[ 2.139293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10636 10:53:04.345983 <6>[ 2.147209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10637 10:53:04.352957 <6>[ 2.155030] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10638 10:53:04.363128 <6>[ 2.162857] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10639 10:53:04.372713 <6>[ 2.173345] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10640 10:53:04.379375 <6>[ 2.181734] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 10:53:04.389667 <6>[ 2.190088] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 10:53:04.396068 <6>[ 2.198431] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 10:53:04.406449 <6>[ 2.206774] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 10:53:04.412847 <6>[ 2.215117] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 10:53:04.422735 <6>[ 2.223459] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 10:53:04.429345 <6>[ 2.231803] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 10:53:04.439277 <6>[ 2.240146] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 10:53:04.445797 <6>[ 2.248493] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 10:53:04.456080 <6>[ 2.256836] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 10:53:04.462910 <6>[ 2.265179] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 10:53:04.472410 <6>[ 2.273522] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 10:53:04.479234 <6>[ 2.281866] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 10:53:04.489449 <6>[ 2.290210] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 10:53:04.495887 <6>[ 2.299132] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 10:53:04.502155 <6>[ 2.306596] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 10:53:04.509088 <6>[ 2.313632] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 10:53:04.519259 <6>[ 2.320713] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 10:53:04.525963 <6>[ 2.327978] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 10:53:04.536066 <6>[ 2.334876] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 10:53:04.542624 <6>[ 2.344018] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 10:53:04.552456 <6>[ 2.353145] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 10:53:04.562091 <6>[ 2.362447] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 10:53:04.572225 <6>[ 2.371923] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 10:53:04.581914 <6>[ 2.381398] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 10:53:04.588658 <6>[ 2.390525] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 10:53:04.598480 <6>[ 2.399999] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 10:53:04.608633 <6>[ 2.409126] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 10:53:04.618370 <6>[ 2.418433] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 10:53:04.628281 <6>[ 2.428599] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 10:53:04.639127 <6>[ 2.440543] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10671 10:53:04.645960 <6>[ 2.450542] Trying to probe devices needed for running init ...
10672 10:53:04.659896 <6>[ 2.461735] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10673 10:53:04.687204 <6>[ 2.492230] hub 2-1:1.0: USB hub found
10674 10:53:04.690925 <6>[ 2.496680] hub 2-1:1.0: 3 ports detected
10675 10:53:04.811866 <6>[ 2.613739] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10676 10:53:04.966899 <6>[ 2.771472] hub 1-1:1.0: USB hub found
10677 10:53:04.969686 <6>[ 2.775913] hub 1-1:1.0: 4 ports detected
10678 10:53:05.048089 <6>[ 2.849978] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10679 10:53:05.292044 <6>[ 3.093743] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10680 10:53:05.424757 <6>[ 3.229827] hub 1-1.4:1.0: USB hub found
10681 10:53:05.428371 <6>[ 3.234480] hub 1-1.4:1.0: 2 ports detected
10682 10:53:05.724051 <6>[ 3.525739] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10683 10:53:05.916082 <6>[ 3.717739] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10684 10:53:16.921122 <6>[ 14.730318] ALSA device list:
10685 10:53:16.927863 <6>[ 14.733577] No soundcards found.
10686 10:53:16.939937 <6>[ 14.745946] Freeing unused kernel memory: 8384K
10687 10:53:16.943205 <6>[ 14.750881] Run /init as init process
10688 10:53:16.954176 Loading, please wait...
10689 10:53:16.973450 Starting version 247.3-7+deb11u2
10690 10:53:17.292220 <6>[ 15.094734] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10691 10:53:17.308360 <6>[ 15.114483] remoteproc remoteproc0: scp is available
10692 10:53:17.318141 <4>[ 15.120249] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10693 10:53:17.325122 <6>[ 15.130186] remoteproc remoteproc0: powering up scp
10694 10:53:17.334804 <4>[ 15.135353] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10695 10:53:17.341175 <3>[ 15.145605] remoteproc remoteproc0: request_firmware failed: -2
10696 10:53:17.355835 <3>[ 15.158737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 10:53:17.362348 <3>[ 15.166870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 10:53:17.371986 <3>[ 15.174959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 10:53:17.385409 <6>[ 15.188169] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10700 10:53:17.391620 <6>[ 15.195788] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10701 10:53:17.401683 <6>[ 15.204502] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10702 10:53:17.408320 <3>[ 15.208794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 10:53:17.418580 <3>[ 15.221322] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 10:53:17.424964 <3>[ 15.229415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 10:53:17.431762 <6>[ 15.230845] mc: Linux media interface: v0.10
10706 10:53:17.438307 <6>[ 15.231502] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10707 10:53:17.444561 <4>[ 15.236702] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10708 10:53:17.454868 <3>[ 15.237543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 10:53:17.461128 <3>[ 15.237563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 10:53:17.468026 <4>[ 15.244730] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 10:53:17.478635 <3>[ 15.251491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 10:53:17.481593 <6>[ 15.252408] usbcore: registered new interface driver r8152
10713 10:53:17.491715 <4>[ 15.259378] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10714 10:53:17.498263 <4>[ 15.259378] Fallback method does not support PEC.
10715 10:53:17.505434 <3>[ 15.268373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 10:53:17.515103 <3>[ 15.289712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 10:53:17.522443 <3>[ 15.294926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 10:53:17.531971 <3>[ 15.329874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 10:53:17.538830 <6>[ 15.330940] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10720 10:53:17.542062 <6>[ 15.330948] pci_bus 0000:00: root bus resource [bus 00-ff]
10721 10:53:17.551566 <6>[ 15.330957] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10722 10:53:17.561820 <6>[ 15.330963] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10723 10:53:17.568187 <6>[ 15.331000] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10724 10:53:17.574740 <6>[ 15.331018] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10725 10:53:17.578317 <6>[ 15.331100] pci 0000:00:00.0: supports D1 D2
10726 10:53:17.585202 <6>[ 15.331104] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 10:53:17.594458 <6>[ 15.332906] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10728 10:53:17.601782 <6>[ 15.333006] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10729 10:53:17.607760 <6>[ 15.333035] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10730 10:53:17.614360 <6>[ 15.333054] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10731 10:53:17.621058 <6>[ 15.333071] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10732 10:53:17.627640 <6>[ 15.333182] pci 0000:01:00.0: supports D1 D2
10733 10:53:17.634344 <6>[ 15.333185] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10734 10:53:17.640877 <3>[ 15.333351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 10:53:17.651281 <6>[ 15.342503] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10736 10:53:17.657365 <6>[ 15.345504] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10737 10:53:17.664057 <6>[ 15.345532] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10738 10:53:17.670554 <6>[ 15.345539] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10739 10:53:17.680752 <6>[ 15.345551] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10740 10:53:17.687495 <6>[ 15.345567] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10741 10:53:17.697241 <6>[ 15.345583] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10742 10:53:17.700699 <6>[ 15.345598] pci 0000:00:00.0: PCI bridge to [bus 01]
10743 10:53:17.710645 <6>[ 15.345605] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10744 10:53:17.717416 <6>[ 15.345722] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10745 10:53:17.723600 <6>[ 15.346559] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10746 10:53:17.727067 <6>[ 15.346928] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10747 10:53:17.736812 <3>[ 15.349056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 10:53:17.746608 <6>[ 15.358503] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10749 10:53:17.753216 <3>[ 15.361850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 10:53:17.762987 <6>[ 15.366230] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10751 10:53:17.773315 <6>[ 15.372056] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10752 10:53:17.783160 <4>[ 15.377120] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10753 10:53:17.789719 <4>[ 15.377130] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10754 10:53:17.796135 <3>[ 15.378020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 10:53:17.802543 <6>[ 15.398311] videodev: Linux video capture interface: v2.00
10756 10:53:17.809611 <6>[ 15.398472] usbcore: registered new interface driver cdc_ether
10757 10:53:17.816088 <3>[ 15.405271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 10:53:17.822784 <6>[ 15.405578] usbcore: registered new interface driver r8153_ecm
10759 10:53:17.826127 <6>[ 15.413533] Bluetooth: Core ver 2.22
10760 10:53:17.835575 <5>[ 15.414649] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10761 10:53:17.842278 <3>[ 15.418982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 10:53:17.849254 <5>[ 15.425212] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10763 10:53:17.858843 <4>[ 15.425287] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10764 10:53:17.865715 <6>[ 15.425294] cfg80211: failed to load regulatory.db
10765 10:53:17.869179 <6>[ 15.426558] NET: Registered PF_BLUETOOTH protocol family
10766 10:53:17.875335 <6>[ 15.429642] r8152 2-1.3:1.0 eth0: v1.12.13
10767 10:53:17.882240 <3>[ 15.434138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 10:53:17.888666 <6>[ 15.438337] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10769 10:53:17.895127 <6>[ 15.438503] Bluetooth: HCI device and connection manager initialized
10770 10:53:17.898510 <6>[ 15.438521] Bluetooth: HCI socket layer initialized
10771 10:53:17.908641 <6>[ 15.454435] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10772 10:53:17.912031 <6>[ 15.460608] Bluetooth: L2CAP socket layer initialized
10773 10:53:17.918290 <6>[ 15.460622] Bluetooth: SCO socket layer initialized
10774 10:53:17.928330 <6>[ 15.468651] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10775 10:53:17.935201 <6>[ 15.492546] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10776 10:53:17.942032 <6>[ 15.499883] usbcore: registered new interface driver uvcvideo
10777 10:53:17.948287 <6>[ 15.527810] usbcore: registered new interface driver btusb
10778 10:53:17.958593 <4>[ 15.528609] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10779 10:53:17.964903 <3>[ 15.528619] Bluetooth: hci0: Failed to load firmware file (-2)
10780 10:53:17.971203 <3>[ 15.528623] Bluetooth: hci0: Failed to set up firmware (-2)
10781 10:53:17.981569 <4>[ 15.528626] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10782 10:53:18.037694 <6>[ 15.840984] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10783 10:53:18.044415 <6>[ 15.848503] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10784 10:53:18.069002 <6>[ 15.875303] mt7921e 0000:01:00.0: ASIC revision: 79610010
10785 10:53:18.174018 <4>[ 15.973835] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 10:53:18.187010 Begin: Loading essential drivers ... done.
10787 10:53:18.190637 Begin: Running /scripts/init-premount ... done.
10788 10:53:18.196976 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10789 10:53:18.206970 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10790 10:53:18.210137 Device /sys/class/net/enx002432307852 found
10791 10:53:18.210220 done.
10792 10:53:18.266322 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10793 10:53:18.296186 <4>[ 16.095798] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 10:53:18.415458 <4>[ 16.215437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 10:53:18.531327 <4>[ 16.331302] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 10:53:18.647991 <4>[ 16.447232] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 10:53:18.763243 <4>[ 16.563126] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 10:53:18.879513 <4>[ 16.679118] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 10:53:18.994989 <4>[ 16.795001] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 10:53:19.111026 <4>[ 16.911062] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 10:53:19.227111 <4>[ 17.026958] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 10:53:19.322703 <6>[ 17.129571] r8152 2-1.3:1.0 enx002432307852: carrier on
10803 10:53:19.334378 <3>[ 17.140825] mt7921e 0000:01:00.0: hardware init failed
10804 10:53:19.373336 IP-Config: no response after 2 secs - giving up
10805 10:53:19.402248 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10806 10:53:19.406211 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10807 10:53:19.412494 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10808 10:53:19.419203 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10809 10:53:19.425879 host : mt8192-asurada-spherion-r0-cbg-3
10810 10:53:19.432091 domain : lava-rack
10811 10:53:19.438795 rootserver: 192.168.201.1 rootpath:
10812 10:53:19.438892 filename :
10813 10:53:19.451089 done.
10814 10:53:19.459261 Begin: Running /scripts/nfs-bottom ... done.
10815 10:53:19.477147 Begin: Running /scripts/init-bottom ... done.
10816 10:53:20.606236 <6>[ 18.412857] NET: Registered PF_INET6 protocol family
10817 10:53:20.613312 <6>[ 18.419993] Segment Routing with IPv6
10818 10:53:20.616723 <6>[ 18.423965] In-situ OAM (IOAM) with IPv6
10819 10:53:20.736056 <30>[ 18.523120] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10820 10:53:20.739517 <30>[ 18.546901] systemd[1]: Detected architecture arm64.
10821 10:53:20.760942
10822 10:53:20.763840 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10823 10:53:20.763956
10824 10:53:20.781628 <30>[ 18.588379] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10825 10:53:21.377053 <30>[ 19.180286] systemd[1]: Queued start job for default target Graphical Interface.
10826 10:53:21.408317 <30>[ 19.214824] systemd[1]: Created slice system-getty.slice.
10827 10:53:21.414648 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10828 10:53:21.431570 <30>[ 19.238302] systemd[1]: Created slice system-modprobe.slice.
10829 10:53:21.437779 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10830 10:53:21.456162 <30>[ 19.262910] systemd[1]: Created slice system-serial\x2dgetty.slice.
10831 10:53:21.466239 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10832 10:53:21.479155 <30>[ 19.286258] systemd[1]: Created slice User and Session Slice.
10833 10:53:21.485810 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10834 10:53:21.506956 <30>[ 19.310312] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10835 10:53:21.513674 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10836 10:53:21.534234 <30>[ 19.337867] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10837 10:53:21.540916 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10838 10:53:21.561546 <30>[ 19.361856] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10839 10:53:21.568006 <30>[ 19.373895] systemd[1]: Reached target Local Encrypted Volumes.
10840 10:53:21.574869 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10841 10:53:21.591298 <30>[ 19.397972] systemd[1]: Reached target Paths.
10842 10:53:21.594604 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10843 10:53:21.611130 <30>[ 19.417785] systemd[1]: Reached target Remote File Systems.
10844 10:53:21.617655 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10845 10:53:21.630705 <30>[ 19.437764] systemd[1]: Reached target Slices.
10846 10:53:21.634163 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10847 10:53:21.651125 <30>[ 19.457730] systemd[1]: Reached target Swap.
10848 10:53:21.654036 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10849 10:53:21.674767 <30>[ 19.478092] systemd[1]: Listening on initctl Compatibility Named Pipe.
10850 10:53:21.681074 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10851 10:53:21.688215 <30>[ 19.493551] systemd[1]: Listening on Journal Audit Socket.
10852 10:53:21.694303 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10853 10:53:21.707978 <30>[ 19.514770] systemd[1]: Listening on Journal Socket (/dev/log).
10854 10:53:21.714456 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10855 10:53:21.731946 <30>[ 19.538563] systemd[1]: Listening on Journal Socket.
10856 10:53:21.738487 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10857 10:53:21.755387 <30>[ 19.559078] systemd[1]: Listening on Network Service Netlink Socket.
10858 10:53:21.762634 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10859 10:53:21.778051 <30>[ 19.584320] systemd[1]: Listening on udev Control Socket.
10860 10:53:21.783865 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10861 10:53:21.799208 <30>[ 19.606063] systemd[1]: Listening on udev Kernel Socket.
10862 10:53:21.806193 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10863 10:53:21.839032 <30>[ 19.646115] systemd[1]: Mounting Huge Pages File System...
10864 10:53:21.845929 Mounting [0;1;39mHuge Pages File System[0m...
10865 10:53:21.861355 <30>[ 19.668552] systemd[1]: Mounting POSIX Message Queue File System...
10866 10:53:21.868582 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10867 10:53:21.885784 <30>[ 19.692237] systemd[1]: Mounting Kernel Debug File System...
10868 10:53:21.891618 Mounting [0;1;39mKernel Debug File System[0m...
10869 10:53:21.910440 <30>[ 19.714034] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10870 10:53:21.930379 <30>[ 19.733738] systemd[1]: Starting Create list of static device nodes for the current kernel...
10871 10:53:21.937033 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10872 10:53:21.957898 <30>[ 19.764549] systemd[1]: Starting Load Kernel Module configfs...
10873 10:53:21.964208 Starting [0;1;39mLoad Kernel Module configfs[0m...
10874 10:53:21.981806 <30>[ 19.788458] systemd[1]: Starting Load Kernel Module drm...
10875 10:53:21.988187 Starting [0;1;39mLoad Kernel Module drm[0m...
10876 10:53:22.005620 <30>[ 19.812423] systemd[1]: Starting Load Kernel Module fuse...
10877 10:53:22.012629 Starting [0;1;39mLoad Kernel Module fuse[0m...
10878 10:53:22.046498 <6>[ 19.853417] fuse: init (API version 7.37)
10879 10:53:22.056238 <30>[ 19.853562] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10880 10:53:22.064713 <30>[ 19.871638] systemd[1]: Starting Journal Service...
10881 10:53:22.067819 Starting [0;1;39mJournal Service[0m...
10882 10:53:22.090445 <30>[ 19.897241] systemd[1]: Starting Load Kernel Modules...
10883 10:53:22.097018 Starting [0;1;39mLoad Kernel Modules[0m...
10884 10:53:22.117116 <30>[ 19.920486] systemd[1]: Starting Remount Root and Kernel File Systems...
10885 10:53:22.123243 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10886 10:53:22.138900 <30>[ 19.945805] systemd[1]: Starting Coldplug All udev Devices...
10887 10:53:22.145216 Starting [0;1;39mColdplug All udev Devices[0m...
10888 10:53:22.162053 <30>[ 19.968829] systemd[1]: Mounted Huge Pages File System.
10889 10:53:22.168315 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10890 10:53:22.183301 <30>[ 19.990242] systemd[1]: Mounted POSIX Message Queue File System.
10891 10:53:22.190125 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10892 10:53:22.207422 <30>[ 20.014550] systemd[1]: Mounted Kernel Debug File System.
10893 10:53:22.214433 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10894 10:53:22.231862 <3>[ 20.035424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 10:53:22.241877 <30>[ 20.045301] systemd[1]: Finished Create list of static device nodes for the current kernel.
10896 10:53:22.251652 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10897 10:53:22.263566 <30>[ 20.070560] systemd[1]: modprobe@configfs.service: Succeeded.
10898 10:53:22.273507 <3>[ 20.074874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 10:53:22.280241 <30>[ 20.077238] systemd[1]: Finished Load Kernel Module configfs.
10900 10:53:22.286269 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10901 10:53:22.300349 <30>[ 20.106908] systemd[1]: modprobe@drm.service: Succeeded.
10902 10:53:22.306265 <30>[ 20.113132] systemd[1]: Finished Load Kernel Module drm.
10903 10:53:22.313228 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10904 10:53:22.324448 <3>[ 20.127872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 10:53:22.332017 <30>[ 20.139006] systemd[1]: modprobe@fuse.service: Succeeded.
10906 10:53:22.338360 <30>[ 20.145328] systemd[1]: Finished Load Kernel Module fuse.
10907 10:53:22.345673 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10908 10:53:22.355809 <3>[ 20.158920] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 10:53:22.363091 <30>[ 20.169056] systemd[1]: Finished Load Kernel Modules.
10910 10:53:22.368985 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10911 10:53:22.386947 <3>[ 20.190511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 10:53:22.393266 <30>[ 20.190712] systemd[1]: Finished Remount Root and Kernel File Systems.
10913 10:53:22.400545 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10914 10:53:22.417360 <3>[ 20.221011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 10:53:22.444008 <30>[ 20.250468] systemd[1]: Mounting FUSE Control File System...
10916 10:53:22.453555 <3>[ 20.255116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 10:53:22.460254 Mounting [0;1;39mFUSE Control File System[0m...
10918 10:53:22.477369 <30>[ 20.284123] systemd[1]: Mounting Kernel Configuration File System...
10919 10:53:22.487153 <3>[ 20.287257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 10:53:22.493670 Mounting [0;1;39mKernel Configuration File System[0m...
10921 10:53:22.517320 <3>[ 20.320932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 10:53:22.527467 <30>[ 20.324132] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10923 10:53:22.537289 <30>[ 20.338752] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10924 10:53:22.547649 <3>[ 20.350470] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 10:53:22.571667 <30>[ 20.378164] systemd[1]: Starting Load/Save Random Seed...
10926 10:53:22.581646 <3>[ 20.381612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 10:53:22.584757 Starting [0;1;39mLoad/Save Random Seed[0m...
10928 10:53:22.602190 <30>[ 20.408838] systemd[1]: Starting Apply Kernel Variables...
10929 10:53:22.615571 Starting [0;1;39mApply<3>[ 20.416996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 10:53:22.618495 Kernel Variables[0m...
10931 10:53:22.635608 <30>[ 20.441999] systemd[1]: Starting Create System Users...
10932 10:53:22.649000 Starting [0;1;39mCreat<3>[ 20.449829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 10:53:22.649082 e System Users[0m...
10934 10:53:22.666868 <30>[ 20.473506] systemd[1]: Mounted FUSE Control File System.
10935 10:53:22.679942 [[0;32m OK [0m] Mounted [0;<3>[ 20.480997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 10:53:22.683506 1;39mFUSE Control File System[0m.
10937 10:53:22.699676 <30>[ 20.506234] systemd[1]: Mounted Kernel Configuration File System.
10938 10:53:22.709906 <3>[ 20.511786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 10:53:22.716449 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10940 10:53:22.732374 <30>[ 20.538857] systemd[1]: Finished Load/Save Random Seed.
10941 10:53:22.741848 <3>[ 20.541213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 10:53:22.748794 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10943 10:53:22.764455 <30>[ 20.571012] systemd[1]: Finished Apply Kernel Variables.
10944 10:53:22.774540 <3>[ 20.573520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 10:53:22.780816 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10946 10:53:22.796255 <30>[ 20.602966] systemd[1]: Finished Create System Users.
10947 10:53:22.806555 <3>[ 20.606318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 10:53:22.809205 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10949 10:53:22.831667 <30>[ 20.634381] systemd[1]: Condition check resulted in First Boot Complete being skipped.
10950 10:53:22.854948 <30>[ 20.658460] systemd[1]: Starting Create Static Device Nodes in /dev...
10951 10:53:22.858460 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10952 10:53:22.907245 <4>[ 20.704477] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10953 10:53:22.914122 <30>[ 20.706844] systemd[1]: Started Journal Service.
10954 10:53:22.920606 <3>[ 20.720153] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10955 10:53:22.927177 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10956 10:53:22.945227 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10957 10:53:22.963814 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10958 10:53:22.975188 See 'systemctl status systemd-udev-trigger.service' for details.
10959 10:53:22.991746 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10960 10:53:23.006689 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10961 10:53:23.055543 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10962 10:53:23.083769 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10963 10:53:23.105059 <46>[ 20.908928] systemd-journald[293]: Received client request to flush runtime journal.
10964 10:53:24.501594 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10965 10:53:24.563970 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10966 10:53:24.582742 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10967 10:53:24.606494 Starting [0;1;39mNetwork Service[0m...
10968 10:53:24.859030 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10969 10:53:24.878788 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10970 10:53:24.938849 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10971 10:53:25.117634 <6>[ 22.924814] remoteproc remoteproc0: powering up scp
10972 10:53:25.153705 <4>[ 22.957104] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10973 10:53:25.160188 <3>[ 22.967626] remoteproc remoteproc0: request_firmware failed: -2
10974 10:53:25.170509 <3>[ 22.974153] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10975 10:53:25.349370 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10976 10:53:25.372776 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10977 10:53:25.390851 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10978 10:53:25.414154 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 10:53:25.451546 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10980 10:53:25.471395 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10981 10:53:25.539172 Starting [0;1;39mNetwork Name Resolution[0m...
10982 10:53:25.567551 Starting [0;1;39mNetwork Time Synchronization[0m...
10983 10:53:25.589503 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10984 10:53:25.607191 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 10:53:25.637236 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10986 10:53:25.775250 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10987 10:53:25.790844 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10988 10:53:25.813541 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10989 10:53:25.826413 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10990 10:53:25.842293 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10991 10:53:25.932482 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10992 10:53:25.959390 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10993 10:53:26.025272 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10994 10:53:26.313137 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10995 10:53:26.326454 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10996 10:53:26.587637 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10997 10:53:26.602148 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10998 10:53:26.618505 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10999 10:53:26.663512 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11000 10:53:26.795596 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11001 10:53:27.163122 Starting [0;1;39mUser Login Management[0m...
11002 10:53:27.179500 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11003 10:53:27.196215 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11004 10:53:27.213848 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11005 10:53:27.229214 Starting [0;1;39mPermit User Sessions[0m...
11006 10:53:27.382134 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11007 10:53:27.434844 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11008 10:53:27.452694 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11009 10:53:27.470912 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11010 10:53:27.491488 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11011 10:53:27.514309 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11012 10:53:27.531328 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11013 10:53:27.550787 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11014 10:53:27.586407 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11015 10:53:27.624757 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11016 10:53:27.686359
11017 10:53:27.686478
11018 10:53:27.689572 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11019 10:53:27.689681
11020 10:53:27.693254 debian-bullseye-arm64 login: root (automatic login)
11021 10:53:27.693362
11022 10:53:27.693461
11023 10:53:28.011781 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11024 10:53:28.011924
11025 10:53:28.018726 The programs included with the Debian GNU/Linux system are free software;
11026 10:53:28.025220 the exact distribution terms for each program are described in the
11027 10:53:28.028402 individual files in /usr/share/doc/*/copyright.
11028 10:53:28.028478
11029 10:53:28.035169 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11030 10:53:28.038005 permitted by applicable law.
11031 10:53:28.101752 Matched prompt #10: / #
11033 10:53:28.102091 Setting prompt string to ['/ #']
11034 10:53:28.102216 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11036 10:53:28.102521 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11037 10:53:28.102615 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11038 10:53:28.102690 Setting prompt string to ['/ #']
11039 10:53:28.102752 Forcing a shell prompt, looking for ['/ #']
11041 10:53:28.152964 / #
11042 10:53:28.153063 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11043 10:53:28.153137 Waiting using forced prompt support (timeout 00:02:30)
11044 10:53:28.158007
11045 10:53:28.158292 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11046 10:53:28.158385 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11048 10:53:28.258683 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g'
11049 10:53:28.264352 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591012/extract-nfsrootfs-aq7rbc1g'
11051 10:53:28.364804 / # export NFS_SERVER_IP='192.168.201.1'
11052 10:53:28.370199 export NFS_SERVER_IP='192.168.201.1'
11053 10:53:28.370474 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11054 10:53:28.370571 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11055 10:53:28.370656 end: 2 depthcharge-action (duration 00:01:48) [common]
11056 10:53:28.370748 start: 3 lava-test-retry (timeout 00:01:00) [common]
11057 10:53:28.370832 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11058 10:53:28.370909 Using namespace: common
11060 10:53:28.471182 / # #
11061 10:53:28.471317 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11062 10:53:28.476230 #
11063 10:53:28.476489 Using /lava-10591012
11065 10:53:28.576755 / # export SHELL=/bin/sh
11066 10:53:28.582556 export SHELL=/bin/sh
11068 10:53:28.683058 / # . /lava-10591012/environment
11069 10:53:28.688299 . /lava-10591012/environment
11071 10:53:28.793436 / # /lava-10591012/bin/lava-test-runner /lava-10591012/0
11072 10:53:28.793568 Test shell timeout: 10s (minimum of the action and connection timeout)
11073 10:53:28.798122 /lava-10591012/bin/lava-test-runner /lava-10591012/0
11074 10:53:29.048762 + export TESTRUN_ID=0_dmesg
11075 10:53:29.052312 + cd /lava-10591012/0/tests/0_dmesg
11076 10:53:29.055271 + cat uuid
11077 10:53:29.074226 + UUID=10591012_<8>[ 26.878502] <LAVA_SIGNAL_STARTRUN 0_dmesg 10591012_1.6.2.3.1>
11078 10:53:29.074343 1.6.2.3.1
11079 10:53:29.074437 + set +x
11080 10:53:29.074730 Received signal: <STARTRUN> 0_dmesg 10591012_1.6.2.3.1
11081 10:53:29.074828 Starting test lava.0_dmesg (10591012_1.6.2.3.1)
11082 10:53:29.074913 Skipping test definition patterns.
11083 10:53:29.080420 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11084 10:53:29.168751 <8>[ 26.972935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11085 10:53:29.169031 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11087 10:53:29.238971 <8>[ 27.043157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11088 10:53:29.239277 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11090 10:53:29.312390 <8>[ 27.116907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11091 10:53:29.312671 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11093 10:53:29.315896 + set +x
11094 10:53:29.318827 <8>[ 27.126357] <LAVA_SIGNAL_ENDRUN 0_dmesg 10591012_1.6.2.3.1>
11095 10:53:29.319072 Received signal: <ENDRUN> 0_dmesg 10591012_1.6.2.3.1
11096 10:53:29.319160 Ending use of test pattern.
11097 10:53:29.319221 Ending test lava.0_dmesg (10591012_1.6.2.3.1), duration 0.24
11099 10:53:29.325742 <LAVA_TEST_RUNNER EXIT>
11100 10:53:29.325988 ok: lava_test_shell seems to have completed
11101 10:53:29.326090 alert: pass
crit: pass
emerg: pass
11102 10:53:29.326212 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11103 10:53:29.326323 end: 3 lava-test-retry (duration 00:00:01) [common]
11104 10:53:29.326443 start: 4 lava-test-retry (timeout 00:01:00) [common]
11105 10:53:29.326552 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11106 10:53:29.326651 Using namespace: common
11108 10:53:29.427001 / # #
11109 10:53:29.427139 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11110 10:53:29.427268 Using /lava-10591012
11112 10:53:29.527667 export SHELL=/bin/sh
11113 10:53:29.527877 #
11115 10:53:29.628389 / # export SHELL=/bin/sh. /lava-10591012/environment
11116 10:53:29.628535
11118 10:53:29.729027 / # . /lava-10591012/environment/lava-10591012/bin/lava-test-runner /lava-10591012/1
11119 10:53:29.729147 Test shell timeout: 10s (minimum of the action and connection timeout)
11120 10:53:29.729292
11121 10:53:29.733889 / # /lava-10591012/bin/lava-test-runner /lava-10591012/1
11122 10:53:29.869460 + export TESTRUN_ID=1_bootrr
11123 10:53:29.872922 + cd /lava-10591012/1/tests/1_bootrr
11124 10:53:29.876262 + cat uuid
11125 10:53:29.888876 + UUID=10591012_1.<8>[ 27.693630] <LAVA_SIGNAL_STARTRUN 1_bootrr 10591012_1.6.2.3.5>
11126 10:53:29.888962 6.2.3.5
11127 10:53:29.889064 + set +x
11128 10:53:29.889298 Received signal: <STARTRUN> 1_bootrr 10591012_1.6.2.3.5
11129 10:53:29.889363 Starting test lava.1_bootrr (10591012_1.6.2.3.5)
11130 10:53:29.889514 Skipping test definition patterns.
11131 10:53:29.902317 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10591012/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11132 10:53:29.905352 + cd /opt/bootrr/libexec/bootrr
11133 10:53:29.905456 + sh helpers/bootrr-auto
11134 10:53:29.969086 /lava-10591012/1/../bin/lava-test-case
11135 10:53:29.997858 <8>[ 27.802770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11136 10:53:29.998128 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11138 10:53:30.047743 /lava-10591012/1/../bin/lava-test-case
11139 10:53:30.080875 <8>[ 27.885608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11140 10:53:30.081139 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11142 10:53:30.105220 /lava-10591012/1/../bin/lava-test-case
11143 10:53:30.133524 <8>[ 27.937974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11144 10:53:30.133787 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11146 10:53:30.189829 /lava-10591012/1/../bin/lava-test-case
11147 10:53:30.219729 <8>[ 28.024232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11148 10:53:30.220005 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11150 10:53:30.256975 /lava-10591012/1/../bin/lava-test-case
11151 10:53:30.282512 <8>[ 28.087344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11152 10:53:30.282771 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11154 10:53:30.315599 /lava-10591012/1/../bin/lava-test-case
11155 10:53:30.342180 <8>[ 28.146653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11156 10:53:30.342438 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11158 10:53:30.374661 /lava-10591012/1/../bin/lava-test-case
11159 10:53:30.402598 <8>[ 28.207543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11160 10:53:30.402859 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11162 10:53:30.438385 /lava-10591012/1/../bin/lava-test-case
11163 10:53:30.468284 <8>[ 28.273090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11164 10:53:30.468555 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11166 10:53:30.490184 /lava-10591012/1/../bin/lava-test-case
11167 10:53:30.520358 <8>[ 28.325213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11168 10:53:30.520628 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11170 10:53:30.554273 /lava-10591012/1/../bin/lava-test-case
11171 10:53:30.580583 <8>[ 28.384795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11172 10:53:30.580846 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11174 10:53:30.612183 /lava-10591012/1/../bin/lava-test-case
11175 10:53:30.637583 <8>[ 28.442292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11176 10:53:30.637842 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11178 10:53:30.671849 /lava-10591012/1/../bin/lava-test-case
11179 10:53:30.697856 <8>[ 28.502527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11180 10:53:30.698119 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11182 10:53:30.729337 /lava-10591012/1/../bin/lava-test-case
11183 10:53:30.756152 <8>[ 28.560856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11184 10:53:30.756407 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11186 10:53:30.793099 /lava-10591012/1/../bin/lava-test-case
11187 10:53:30.823675 <8>[ 28.628238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11188 10:53:30.823938 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11190 10:53:30.856149 /lava-10591012/1/../bin/lava-test-case
11191 10:53:30.880312 <8>[ 28.685285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11192 10:53:30.880583 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11194 10:53:30.905328 /lava-10591012/1/../bin/lava-test-case
11195 10:53:30.934684 <8>[ 28.739086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11196 10:53:30.934940 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11198 10:53:30.978655 /lava-10591012/1/../bin/lava-test-case
11199 10:53:31.004886 <8>[ 28.809604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11200 10:53:31.005161 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11202 10:53:31.028731 /lava-10591012/1/../bin/lava-test-case
11203 10:53:31.056237 <8>[ 28.860524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11204 10:53:31.056499 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11206 10:53:31.091722 /lava-10591012/1/../bin/lava-test-case
11207 10:53:31.123918 <8>[ 28.928703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11208 10:53:31.124188 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11210 10:53:31.145221 /lava-10591012/1/../bin/lava-test-case
11211 10:53:31.175447 <8>[ 28.980176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11212 10:53:31.175719 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11214 10:53:31.209467 /lava-10591012/1/../bin/lava-test-case
11215 10:53:31.240051 <8>[ 29.044838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11216 10:53:31.240311 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11218 10:53:31.262190 /lava-10591012/1/../bin/lava-test-case
11219 10:53:31.294277 <8>[ 29.098925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11220 10:53:31.294564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11222 10:53:31.335581 /lava-10591012/1/../bin/lava-test-case
11223 10:53:31.363536 <8>[ 29.168212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11224 10:53:31.363793 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11226 10:53:31.387815 /lava-10591012/1/../bin/lava-test-case
11227 10:53:31.417382 <8>[ 29.222341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11228 10:53:31.417672 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11230 10:53:31.456015 /lava-10591012/1/../bin/lava-test-case
11231 10:53:31.485567 <8>[ 29.289904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11232 10:53:31.485885 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11234 10:53:31.523632 /lava-10591012/1/../bin/lava-test-case
11235 10:53:31.552250 <8>[ 29.357026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11236 10:53:31.552509 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11238 10:53:31.574446 /lava-10591012/1/../bin/lava-test-case
11239 10:53:31.606663 <8>[ 29.411525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11240 10:53:31.606925 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11242 10:53:31.645189 /lava-10591012/1/../bin/lava-test-case
11243 10:53:31.672081 <8>[ 29.477013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11244 10:53:31.672336 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11246 10:53:31.696368 /lava-10591012/1/../bin/lava-test-case
11247 10:53:31.723923 <8>[ 29.528945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11248 10:53:31.724181 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11250 10:53:31.758822 /lava-10591012/1/../bin/lava-test-case
11251 10:53:31.787465 <8>[ 29.592487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11252 10:53:31.787724 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11254 10:53:31.824877 /lava-10591012/1/../bin/lava-test-case
11255 10:53:31.851668 <8>[ 29.656696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11256 10:53:31.851926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11258 10:53:31.884783 /lava-10591012/1/../bin/lava-test-case
11259 10:53:31.912756 <8>[ 29.717589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11260 10:53:31.913019 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11262 10:53:31.952596 /lava-10591012/1/../bin/lava-test-case
11263 10:53:31.984012 <8>[ 29.789044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11264 10:53:31.984274 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11266 10:53:32.012216 /lava-10591012/1/../bin/lava-test-case
11267 10:53:32.037508 <8>[ 29.842200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11268 10:53:32.037772 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11270 10:53:32.076007 /lava-10591012/1/../bin/lava-test-case
11271 10:53:32.103230 <8>[ 29.907948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11272 10:53:32.103515 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11274 10:53:32.135466 /lava-10591012/1/../bin/lava-test-case
11275 10:53:32.161846 <8>[ 29.966556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11276 10:53:32.162150 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11278 10:53:32.184510 /lava-10591012/1/../bin/lava-test-case
11279 10:53:32.219234 <8>[ 30.023850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11280 10:53:32.219507 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11282 10:53:32.253467 /lava-10591012/1/../bin/lava-test-case
11283 10:53:32.281815 <8>[ 30.086608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11284 10:53:32.282077 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11286 10:53:32.306197 /lava-10591012/1/../bin/lava-test-case
11287 10:53:32.334645 <8>[ 30.139812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11288 10:53:32.334903 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11290 10:53:32.379014 /lava-10591012/1/../bin/lava-test-case
11291 10:53:32.406345 <8>[ 30.211045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11292 10:53:32.406604 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11294 10:53:32.428517 /lava-10591012/1/../bin/lava-test-case
11295 10:53:32.455993 <8>[ 30.260810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11296 10:53:32.456250 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11298 10:53:32.492008 /lava-10591012/1/../bin/lava-test-case
11299 10:53:32.520322 <8>[ 30.325089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11300 10:53:32.520579 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11302 10:53:32.541529 /lava-10591012/1/../bin/lava-test-case
11303 10:53:32.569161 <8>[ 30.374083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11304 10:53:32.569414 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11306 10:53:32.605018 /lava-10591012/1/../bin/lava-test-case
11307 10:53:32.633389 <8>[ 30.438531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11308 10:53:32.633686 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11310 10:53:32.658555 /lava-10591012/1/../bin/lava-test-case
11311 10:53:32.688944 <8>[ 30.493798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11312 10:53:32.689201 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11314 10:53:32.730101 /lava-10591012/1/../bin/lava-test-case
11315 10:53:32.758272 <8>[ 30.562892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11316 10:53:32.758537 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11318 10:53:32.780902 /lava-10591012/1/../bin/lava-test-case
11319 10:53:32.810079 <8>[ 30.615094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11320 10:53:32.810340 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11322 10:53:32.845630 /lava-10591012/1/../bin/lava-test-case
11323 10:53:32.876992 <8>[ 30.681809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11324 10:53:32.877253 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11326 10:53:32.900670 /lava-10591012/1/../bin/lava-test-case
11327 10:53:32.928738 <8>[ 30.733894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11328 10:53:32.928995 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11330 10:53:32.962070 /lava-10591012/1/../bin/lava-test-case
11331 10:53:32.986445 <8>[ 30.791543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11332 10:53:32.986703 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11334 10:53:33.020763 /lava-10591012/1/../bin/lava-test-case
11335 10:53:33.049528 <8>[ 30.854531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11336 10:53:33.049814 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11338 10:53:34.094754 /lava-10591012/1/../bin/lava-test-case
11339 10:53:34.121181 <8>[ 31.926578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11340 10:53:34.121459 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11342 10:53:35.155585 /lava-10591012/1/../bin/lava-test-case
11343 10:53:35.189358 <8>[ 32.994664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11344 10:53:35.189646 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11345 10:53:35.189734 Bad test result: blocked
11346 10:53:35.212208 /lava-10591012/1/../bin/lava-test-case
11347 10:53:35.241284 <8>[ 33.046298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11348 10:53:35.241540 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11350 10:53:35.279449 /lava-10591012/1/../bin/lava-test-case
11351 10:53:35.311723 <8>[ 33.116851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11352 10:53:35.311983 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11354 10:53:35.348001 /lava-10591012/1/../bin/lava-test-case
11355 10:53:35.375752 <8>[ 33.180950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11356 10:53:35.376005 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11358 10:53:35.412288 /lava-10591012/1/../bin/lava-test-case
11359 10:53:35.440062 <8>[ 33.245192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11360 10:53:35.440313 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11362 10:53:35.477360 /lava-10591012/1/../bin/lava-test-case
11363 10:53:35.502512 <8>[ 33.307757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11364 10:53:35.502771 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11366 10:53:35.542523 /lava-10591012/1/../bin/lava-test-case
11367 10:53:35.567642 <8>[ 33.373186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11368 10:53:35.567902 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11370 10:53:35.587612 /lava-10591012/1/../bin/lava-test-case
11371 10:53:35.620371 <8>[ 33.425529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11372 10:53:35.620633 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11374 10:53:35.655064 /lava-10591012/1/../bin/lava-test-case
11375 10:53:35.684444 <8>[ 33.489841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11376 10:53:35.684697 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11378 10:53:35.718648 /lava-10591012/1/../bin/lava-test-case
11379 10:53:35.747291 <8>[ 33.552597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11380 10:53:35.747567 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11382 10:53:35.767727 /lava-10591012/1/../bin/lava-test-case
11383 10:53:35.794179 <8>[ 33.599372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11384 10:53:35.794432 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11386 10:53:35.830351 /lava-10591012/1/../bin/lava-test-case
11387 10:53:35.860626 <8>[ 33.665907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11388 10:53:35.860882 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11390 10:53:35.889375 /lava-10591012/1/../bin/lava-test-case
11391 10:53:35.916989 <8>[ 33.721935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11392 10:53:35.917261 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11394 10:53:35.951045 /lava-10591012/1/../bin/lava-test-case
11395 10:53:35.977335 <8>[ 33.782808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11396 10:53:35.977588 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11398 10:53:35.999489 /lava-10591012/1/../bin/lava-test-case
11399 10:53:36.030191 <8>[ 33.835364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11400 10:53:36.030465 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11402 10:53:36.064706 /lava-10591012/1/../bin/lava-test-case
11403 10:53:36.093208 <8>[ 33.898626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11404 10:53:36.093472 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11406 10:53:36.127704 /lava-10591012/1/../bin/lava-test-case
11407 10:53:36.157483 <8>[ 33.962598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11408 10:53:36.157740 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11410 10:53:36.187798 /lava-10591012/1/../bin/lava-test-case
11411 10:53:36.215119 <8>[ 34.020575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11412 10:53:36.215389 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11414 10:53:36.260840 /lava-10591012/1/../bin/lava-test-case
11415 10:53:36.294603 <8>[ 34.099762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11416 10:53:36.294861 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11418 10:53:36.329280 /lava-10591012/1/../bin/lava-test-case
11419 10:53:36.357067 <8>[ 34.162575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11420 10:53:36.357326 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11422 10:53:36.390882 /lava-10591012/1/../bin/lava-test-case
11423 10:53:36.418878 <8>[ 34.224003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11424 10:53:36.419137 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11426 10:53:36.450789 /lava-10591012/1/../bin/lava-test-case
11427 10:53:36.478356 <8>[ 34.283620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11428 10:53:36.478617 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11430 10:53:36.514809 /lava-10591012/1/../bin/lava-test-case
11431 10:53:36.541576 <8>[ 34.346805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11432 10:53:36.541840 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11434 10:53:36.572534 /lava-10591012/1/../bin/lava-test-case
11435 10:53:36.597631 <8>[ 34.402663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11436 10:53:36.597886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11438 10:53:36.637223 /lava-10591012/1/../bin/lava-test-case
11439 10:53:36.663525 <8>[ 34.469157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11440 10:53:36.663786 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11442 10:53:36.699869 /lava-10591012/1/../bin/lava-test-case
11443 10:53:36.728415 <8>[ 34.534098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11444 10:53:36.728675 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11446 10:53:36.762283 /lava-10591012/1/../bin/lava-test-case
11447 10:53:36.791633 <8>[ 34.596695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11448 10:53:36.791893 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11450 10:53:36.829178 /lava-10591012/1/../bin/lava-test-case
11451 10:53:36.860183 <8>[ 34.665397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11452 10:53:36.860486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11454 10:53:36.898669 /lava-10591012/1/../bin/lava-test-case
11455 10:53:36.925001 <8>[ 34.730161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11456 10:53:36.925262 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11458 10:53:36.962984 /lava-10591012/1/../bin/lava-test-case
11459 10:53:36.989428 <8>[ 34.795006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11460 10:53:36.989687 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11462 10:53:37.012796 /lava-10591012/1/../bin/lava-test-case
11463 10:53:37.040609 <8>[ 34.846060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11464 10:53:37.040878 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11466 10:53:37.072079 /lava-10591012/1/../bin/lava-test-case
11467 10:53:37.098311 <8>[ 34.904011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11468 10:53:37.098577 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11470 10:53:37.119980 /lava-10591012/1/../bin/lava-test-case
11471 10:53:37.154042 <8>[ 34.959417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11472 10:53:37.154306 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11474 10:53:37.186179 /lava-10591012/1/../bin/lava-test-case
11475 10:53:37.215145 <8>[ 35.020333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11476 10:53:37.215397 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11478 10:53:37.236327 /lava-10591012/1/../bin/lava-test-case
11479 10:53:37.263310 <8>[ 35.068916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11480 10:53:37.263595 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11482 10:53:37.305110 /lava-10591012/1/../bin/lava-test-case
11483 10:53:37.330849 <8>[ 35.136414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11484 10:53:37.331112 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11486 10:53:37.353489 /lava-10591012/1/../bin/lava-test-case
11487 10:53:37.380295 <8>[ 35.185775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11488 10:53:37.380554 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11490 10:53:37.427740 /lava-10591012/1/../bin/lava-test-case
11491 10:53:37.454634 <8>[ 35.260005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11492 10:53:37.454896 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11494 10:53:37.476830 /lava-10591012/1/../bin/lava-test-case
11495 10:53:37.507820 <8>[ 35.313383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11496 10:53:37.508086 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11498 10:53:37.542496 /lava-10591012/1/../bin/lava-test-case
11499 10:53:37.567872 <8>[ 35.373260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11500 10:53:37.568131 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11502 10:53:37.590991 /lava-10591012/1/../bin/lava-test-case
11503 10:53:37.623322 <8>[ 35.428951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11504 10:53:37.623626 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11506 10:53:37.664661 /lava-10591012/1/../bin/lava-test-case
11507 10:53:37.694786 <8>[ 35.500026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11508 10:53:37.695050 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11510 10:53:37.727611 /lava-10591012/1/../bin/lava-test-case
11511 10:53:37.755007 <8>[ 35.560548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11512 10:53:37.755266 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11514 10:53:37.777620 /lava-10591012/1/../bin/lava-test-case
11515 10:53:37.806484 <8>[ 35.612310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11516 10:53:37.806756 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11518 10:53:37.840523 /lava-10591012/1/../bin/lava-test-case
11519 10:53:37.865686 <8>[ 35.671239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11520 10:53:37.865942 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11522 10:53:37.888759 /lava-10591012/1/../bin/lava-test-case
11523 10:53:37.914992 <8>[ 35.720733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11524 10:53:37.915253 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11526 10:53:37.956352 /lava-10591012/1/../bin/lava-test-case
11527 10:53:37.986001 <8>[ 35.791258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11528 10:53:37.986290 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11530 10:53:38.006052 /lava-10591012/1/../bin/lava-test-case
11531 10:53:38.031384 <8>[ 35.837170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11532 10:53:38.031651 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11534 10:53:39.078434 /lava-10591012/1/../bin/lava-test-case
11535 10:53:39.107329 <8>[ 36.912757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11536 10:53:39.107628 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11538 10:53:39.129159 /lava-10591012/1/../bin/lava-test-case
11539 10:53:39.157477 <8>[ 36.962771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11540 10:53:39.157735 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11542 10:53:40.204303 /lava-10591012/1/../bin/lava-test-case
11543 10:53:40.233589 <8>[ 38.039405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11544 10:53:40.233869 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11546 10:53:40.254375 /lava-10591012/1/../bin/lava-test-case
11547 10:53:40.278879 <8>[ 38.084884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11548 10:53:40.279130 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11550 10:53:41.325345 /lava-10591012/1/../bin/lava-test-case
11551 10:53:41.363849 <8>[ 39.169583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11552 10:53:41.364120 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11554 10:53:41.386079 /lava-10591012/1/../bin/lava-test-case
11555 10:53:41.417961 <8>[ 39.223671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11556 10:53:41.418224 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11558 10:53:42.465808 /lava-10591012/1/../bin/lava-test-case
11559 10:53:42.494701 <8>[ 40.300887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11560 10:53:42.495146 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11562 10:53:42.517445 /lava-10591012/1/../bin/lava-test-case
11563 10:53:42.545990 <8>[ 40.351913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11564 10:53:42.546289 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11566 10:53:43.588866 /lava-10591012/1/../bin/lava-test-case
11567 10:53:43.621245 <8>[ 41.427306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11568 10:53:43.621556 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11570 10:53:43.644510 /lava-10591012/1/../bin/lava-test-case
11571 10:53:43.667797 <8>[ 41.474251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11572 10:53:43.668068 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11574 10:53:44.719986 /lava-10591012/1/../bin/lava-test-case
11575 10:53:44.746229 <8>[ 42.552602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11576 10:53:44.746543 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11578 10:53:44.767609 /lava-10591012/1/../bin/lava-test-case
11579 10:53:44.794037 <8>[ 42.600108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11580 10:53:44.794325 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11582 10:53:45.840390 /lava-10591012/1/../bin/lava-test-case
11583 10:53:45.876849 <8>[ 43.682794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11584 10:53:45.877614 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11586 10:53:45.903119 /lava-10591012/1/../bin/lava-test-case
11587 10:53:45.931144 <8>[ 43.737949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11588 10:53:45.931439 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11590 10:53:45.955382 /lava-10591012/1/../bin/lava-test-case
11591 10:53:45.987471 <8>[ 43.793954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11592 10:53:45.987729 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11594 10:53:47.034676 /lava-10591012/1/../bin/lava-test-case
11595 10:53:47.061507 <8>[ 44.868215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11596 10:53:47.061771 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11598 10:53:47.083384 /lava-10591012/1/../bin/lava-test-case
11599 10:53:47.108505 <8>[ 44.915073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11600 10:53:47.108802 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11602 10:53:47.141289 /lava-10591012/1/../bin/lava-test-case
11603 10:53:47.167685 <8>[ 44.974286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11604 10:53:47.167986 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11606 10:53:47.190141 /lava-10591012/1/../bin/lava-test-case
11607 10:53:47.215290 <8>[ 45.021844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11608 10:53:47.215596 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11610 10:53:47.249713 /lava-10591012/1/../bin/lava-test-case
11611 10:53:47.274755 <8>[ 45.081658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11612 10:53:47.275013 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11614 10:53:47.311001 /lava-10591012/1/../bin/lava-test-case
11615 10:53:47.342508 <8>[ 45.149319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11616 10:53:47.342775 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11618 10:53:47.388391 /lava-10591012/1/../bin/lava-test-case
11619 10:53:47.414096 <8>[ 45.220782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11620 10:53:47.414357 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11622 10:53:47.436704 /lava-10591012/1/../bin/lava-test-case
11623 10:53:47.465794 <8>[ 45.272467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11624 10:53:47.466053 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11626 10:53:47.501614 /lava-10591012/1/../bin/lava-test-case
11627 10:53:47.532052 <8>[ 45.338491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11628 10:53:47.532315 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11630 10:53:47.570697 /lava-10591012/1/../bin/lava-test-case
11631 10:53:47.596629 <8>[ 45.403391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11632 10:53:47.596884 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11634 10:53:47.618155 /lava-10591012/1/../bin/lava-test-case
11635 10:53:47.646405 <8>[ 45.453153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11636 10:53:47.646667 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11638 10:53:47.681826 /lava-10591012/1/../bin/lava-test-case
11639 10:53:47.710585 <8>[ 45.516979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11640 10:53:47.710871 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11642 10:53:47.737642 /lava-10591012/1/../bin/lava-test-case
11643 10:53:47.764798 <8>[ 45.571395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11644 10:53:47.765061 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11646 10:53:47.799393 /lava-10591012/1/../bin/lava-test-case
11647 10:53:47.829323 <8>[ 45.635938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11648 10:53:47.829583 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11650 10:53:47.853953 /lava-10591012/1/../bin/lava-test-case
11651 10:53:47.882621 <8>[ 45.689482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11652 10:53:47.882877 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11654 10:53:47.922287 /lava-10591012/1/../bin/lava-test-case
11655 10:53:47.950436 <8>[ 45.757056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11656 10:53:47.950698 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11658 10:53:47.973118 /lava-10591012/1/../bin/lava-test-case
11659 10:53:47.997746 <8>[ 45.804615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11660 10:53:47.998002 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11662 10:53:48.034247 /lava-10591012/1/../bin/lava-test-case
11663 10:53:48.061812 <8>[ 45.868584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11664 10:53:48.062113 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11666 10:53:48.089989 /lava-10591012/1/../bin/lava-test-case
11667 10:53:48.116988 <8>[ 45.923407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11668 10:53:48.117246 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11670 10:53:48.151961 /lava-10591012/1/../bin/lava-test-case
11671 10:53:48.178525 <8>[ 45.984930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11672 10:53:48.178786 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11674 10:53:48.197554 /lava-10591012/1/../bin/lava-test-case
11675 10:53:48.225043 <8>[ 46.031627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11676 10:53:48.225305 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11678 10:53:48.340589 <6>[ 46.153983] vpu: disabling
11679 10:53:48.344190 <6>[ 46.157037] vproc2: disabling
11680 10:53:48.347523 <6>[ 46.160318] vproc1: disabling
11681 10:53:48.350891 <6>[ 46.163581] vaud18: disabling
11682 10:53:48.357262 <6>[ 46.166990] vsram_others: disabling
11683 10:53:48.360555 <6>[ 46.170863] va09: disabling
11684 10:53:48.363460 <6>[ 46.173968] vsram_md: disabling
11685 10:53:48.366757 <6>[ 46.177451] Vgpu: disabling
11686 10:53:49.272424 /lava-10591012/1/../bin/lava-test-case
11687 10:53:49.302308 <8>[ 47.109274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11688 10:53:49.302636 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11690 10:53:50.346142 /lava-10591012/1/../bin/lava-test-case
11691 10:53:50.375562 <8>[ 48.182843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11692 10:53:50.375828 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11694 10:53:50.396512 /lava-10591012/1/../bin/lava-test-case
11695 10:53:50.420072 <8>[ 48.227256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11696 10:53:50.420329 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11698 10:53:50.451908 /lava-10591012/1/../bin/lava-test-case
11699 10:53:50.478478 <8>[ 48.285329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11700 10:53:50.478764 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11702 10:53:50.499447 /lava-10591012/1/../bin/lava-test-case
11703 10:53:50.528750 <8>[ 48.335475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11704 10:53:50.529007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11706 10:53:50.559925 /lava-10591012/1/../bin/lava-test-case
11707 10:53:50.585574 <8>[ 48.392676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11708 10:53:50.585829 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11710 10:53:50.606445 /lava-10591012/1/../bin/lava-test-case
11711 10:53:50.634089 <8>[ 48.441452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11712 10:53:50.634373 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11714 10:53:50.673056 /lava-10591012/1/../bin/lava-test-case
11715 10:53:50.697954 <8>[ 48.505167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11716 10:53:50.698256 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11718 10:53:50.722743 /lava-10591012/1/../bin/lava-test-case
11719 10:53:50.748620 <8>[ 48.555549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11720 10:53:50.748904 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11722 10:53:50.781481 /lava-10591012/1/../bin/lava-test-case
11723 10:53:50.810978 <8>[ 48.617876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11724 10:53:50.811243 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11726 10:53:50.833217 /lava-10591012/1/../bin/lava-test-case
11727 10:53:50.867141 <8>[ 48.673948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11728 10:53:50.867387 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11730 10:53:50.902197 /lava-10591012/1/../bin/lava-test-case
11731 10:53:50.933116 <8>[ 48.740398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11732 10:53:50.933385 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11734 10:53:50.954728 /lava-10591012/1/../bin/lava-test-case
11735 10:53:50.982233 <8>[ 48.789428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11736 10:53:50.982544 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11738 10:53:51.025247 /lava-10591012/1/../bin/lava-test-case
11739 10:53:51.052775 <8>[ 48.860106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11740 10:53:51.053042 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11742 10:53:51.074519 /lava-10591012/1/../bin/lava-test-case
11743 10:53:51.100081 <8>[ 48.907087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11744 10:53:51.100339 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11746 10:53:51.132181 /lava-10591012/1/../bin/lava-test-case
11747 10:53:51.157893 <8>[ 48.965109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11748 10:53:51.158147 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11750 10:53:51.178877 /lava-10591012/1/../bin/lava-test-case
11751 10:53:51.205620 <8>[ 49.012718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11752 10:53:51.205886 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11754 10:53:51.237614 /lava-10591012/1/../bin/lava-test-case
11755 10:53:51.263068 <8>[ 49.070276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11756 10:53:51.263323 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11758 10:53:51.283823 /lava-10591012/1/../bin/lava-test-case
11759 10:53:51.309985 <8>[ 49.116992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11760 10:53:51.310285 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11762 10:53:51.348837 /lava-10591012/1/../bin/lava-test-case
11763 10:53:51.373587 <8>[ 49.180514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11764 10:53:51.373844 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11766 10:53:51.392601 /lava-10591012/1/../bin/lava-test-case
11767 10:53:51.418494 <8>[ 49.225855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11768 10:53:51.418756 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11770 10:53:51.452555 /lava-10591012/1/../bin/lava-test-case
11771 10:53:51.478194 <8>[ 49.285337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11772 10:53:51.478451 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11774 10:53:52.511004 /lava-10591012/1/../bin/lava-test-case
11775 10:53:52.540924 <8>[ 50.348071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11776 10:53:52.541194 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11778 10:53:53.576248 /lava-10591012/1/../bin/lava-test-case
11779 10:53:53.612698 <8>[ 51.419421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11780 10:53:53.613554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11781 10:53:53.614013 Bad test result: blocked
11782 10:53:53.639344 /lava-10591012/1/../bin/lava-test-case
11783 10:53:53.675075 <8>[ 51.481785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11784 10:53:53.675919 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11786 10:53:54.734893 /lava-10591012/1/../bin/lava-test-case
11787 10:53:54.771152 <8>[ 52.578144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11788 10:53:54.771899 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11790 10:53:54.797729 /lava-10591012/1/../bin/lava-test-case
11791 10:53:54.829175 <8>[ 52.636145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11792 10:53:54.830004 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11794 10:53:54.871878 /lava-10591012/1/../bin/lava-test-case
11795 10:53:54.908816 <8>[ 52.716298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11796 10:53:54.909579 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11798 10:53:54.950067 /lava-10591012/1/../bin/lava-test-case
11799 10:53:54.984996 <8>[ 52.792264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11800 10:53:54.985685 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11802 10:53:55.010517 /lava-10591012/1/../bin/lava-test-case
11803 10:53:55.042927 <8>[ 52.850078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11804 10:53:55.043567 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11806 10:53:55.094872 /lava-10591012/1/../bin/lava-test-case
11807 10:53:55.135937 <8>[ 52.943163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11808 10:53:55.136651 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11810 10:53:55.162603 /lava-10591012/1/../bin/lava-test-case
11811 10:53:55.196540 <8>[ 53.003528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11812 10:53:55.197240 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11814 10:53:56.254352 /lava-10591012/1/../bin/lava-test-case
11815 10:53:56.296744 <8>[ 54.103482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11816 10:53:56.297734 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11818 10:53:56.328579 /lava-10591012/1/../bin/lava-test-case
11819 10:53:56.365527 <8>[ 54.173181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11820 10:53:56.366303 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11822 10:53:57.426173 /lava-10591012/1/../bin/lava-test-case
11823 10:53:57.461231 <8>[ 55.268416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11824 10:53:57.462045 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11826 10:53:57.487436 /lava-10591012/1/../bin/lava-test-case
11827 10:53:57.520218 <8>[ 55.327729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11828 10:53:57.521109 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11830 10:53:58.580490 /lava-10591012/1/../bin/lava-test-case
11831 10:53:58.632536 <8>[ 56.440063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11832 10:53:58.633325 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11834 10:53:58.660798 /lava-10591012/1/../bin/lava-test-case
11835 10:53:58.697846 <8>[ 56.504876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11836 10:53:58.698638 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11838 10:53:59.755197 /lava-10591012/1/../bin/lava-test-case
11839 10:53:59.790523 <8>[ 57.598029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11840 10:53:59.791379 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11842 10:53:59.819800 /lava-10591012/1/../bin/lava-test-case
11843 10:53:59.858768 <8>[ 57.666404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11844 10:53:59.859684 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11846 10:53:59.904441 /lava-10591012/1/../bin/lava-test-case
11847 10:53:59.941630 <8>[ 57.749687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11848 10:53:59.942378 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11850 10:53:59.984646 /lava-10591012/1/../bin/lava-test-case
11851 10:54:00.025443 <8>[ 57.833361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11852 10:54:00.026177 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11854 10:54:00.053541 /lava-10591012/1/../bin/lava-test-case
11855 10:54:00.087053 <8>[ 57.894781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11856 10:54:00.087872 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11858 10:54:00.139612 /lava-10591012/1/../bin/lava-test-case
11859 10:54:00.181369 <8>[ 57.989325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11860 10:54:00.182131 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11862 10:54:00.209649 /lava-10591012/1/../bin/lava-test-case
11863 10:54:00.247116 <8>[ 58.054425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11864 10:54:00.247904 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11866 10:54:00.296520 /lava-10591012/1/../bin/lava-test-case
11867 10:54:00.339346 <8>[ 58.146830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11868 10:54:00.340220 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11870 10:54:00.368827 /lava-10591012/1/../bin/lava-test-case
11871 10:54:00.403772 <8>[ 58.211403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11872 10:54:00.404529 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11874 10:54:01.465921 /lava-10591012/1/../bin/lava-test-case
11875 10:54:01.503845 <8>[ 59.311346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11876 10:54:01.504616 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11878 10:54:01.513124 + <8>[ 59.324494] <LAVA_SIGNAL_ENDRUN 1_bootrr 10591012_1.6.2.3.5>
11879 10:54:01.513916 Received signal: <ENDRUN> 1_bootrr 10591012_1.6.2.3.5
11880 10:54:01.514306 Ending use of test pattern.
11881 10:54:01.514609 Ending test lava.1_bootrr (10591012_1.6.2.3.5), duration 31.63
11883 10:54:01.516607 set +x
11884 10:54:01.521625 <LAVA_TEST_RUNNER EXIT>
11885 10:54:01.522265 ok: lava_test_shell seems to have completed
11886 10:54:01.527084 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11887 10:54:01.527785 end: 4.1 lava-test-shell (duration 00:00:32) [common]
11888 10:54:01.528213 end: 4 lava-test-retry (duration 00:00:32) [common]
11889 10:54:01.528643 start: 5 finalize (timeout 00:06:52) [common]
11890 10:54:01.529071 start: 5.1 power-off (timeout 00:00:30) [common]
11891 10:54:01.529809 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11892 10:54:01.614955 >> Command sent successfully.
11893 10:54:01.619259 Returned 0 in 0 seconds
11894 10:54:01.720095 end: 5.1 power-off (duration 00:00:00) [common]
11896 10:54:01.721496 start: 5.2 read-feedback (timeout 00:06:52) [common]
11897 10:54:01.722669 Listened to connection for namespace 'common' for up to 1s
11898 10:54:02.723383 Finalising connection for namespace 'common'
11899 10:54:02.724029 Disconnecting from shell: Finalise
11900 10:54:02.724451 / #
11901 10:54:02.825418 end: 5.2 read-feedback (duration 00:00:01) [common]
11902 10:54:02.826050 end: 5 finalize (duration 00:00:01) [common]
11903 10:54:02.826605 Cleaning after the job
11904 10:54:02.827068 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/ramdisk
11905 10:54:02.835868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/kernel
11906 10:54:02.865984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/dtb
11907 10:54:02.866342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/nfsrootfs
11908 10:54:02.926672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591012/tftp-deploy-70bw0c7d/modules
11909 10:54:02.931891 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591012
11910 10:54:03.222475 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591012
11911 10:54:03.222652 Job finished correctly