Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 10:50:31.353301 lava-dispatcher, installed at version: 2023.05.1
2 10:50:31.353507 start: 0 validate
3 10:50:31.353646 Start time: 2023-06-05 10:50:31.353639+00:00 (UTC)
4 10:50:31.353804 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:50:31.353985 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:50:31.646463 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:50:31.646643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:50:31.937894 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:50:31.938122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:51:03.178589 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:51:03.178765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:51:03.751654 validate duration: 32.40
14 10:51:03.752300 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:51:03.752398 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:51:03.752487 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:51:03.752616 Not decompressing ramdisk as can be used compressed.
18 10:51:03.752716 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 10:51:03.752783 saving as /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/ramdisk/rootfs.cpio.gz
20 10:51:03.752844 total size: 43394293 (41MB)
21 10:51:11.628622 progress 0% (0MB)
22 10:51:11.640269 progress 5% (2MB)
23 10:51:11.651725 progress 10% (4MB)
24 10:51:11.662574 progress 15% (6MB)
25 10:51:11.673506 progress 20% (8MB)
26 10:51:11.684521 progress 25% (10MB)
27 10:51:11.695379 progress 30% (12MB)
28 10:51:11.706267 progress 35% (14MB)
29 10:51:11.717509 progress 40% (16MB)
30 10:51:11.728509 progress 45% (18MB)
31 10:51:11.740029 progress 50% (20MB)
32 10:51:11.750941 progress 55% (22MB)
33 10:51:11.761810 progress 60% (24MB)
34 10:51:11.772795 progress 65% (26MB)
35 10:51:11.783961 progress 70% (29MB)
36 10:51:11.795220 progress 75% (31MB)
37 10:51:11.806100 progress 80% (33MB)
38 10:51:11.817083 progress 85% (35MB)
39 10:51:11.828302 progress 90% (37MB)
40 10:51:11.839264 progress 95% (39MB)
41 10:51:11.851195 progress 100% (41MB)
42 10:51:11.851368 41MB downloaded in 8.10s (5.11MB/s)
43 10:51:11.851559 end: 1.1.1 http-download (duration 00:00:08) [common]
45 10:51:11.851846 end: 1.1 download-retry (duration 00:00:08) [common]
46 10:51:11.851937 start: 1.2 download-retry (timeout 00:09:52) [common]
47 10:51:11.852050 start: 1.2.1 http-download (timeout 00:09:52) [common]
48 10:51:11.852200 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:51:11.852275 saving as /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/kernel/Image
50 10:51:11.852338 total size: 45746688 (43MB)
51 10:51:11.852399 No compression specified
52 10:51:12.154771 progress 0% (0MB)
53 10:51:12.166320 progress 5% (2MB)
54 10:51:12.178040 progress 10% (4MB)
55 10:51:12.189960 progress 15% (6MB)
56 10:51:12.201873 progress 20% (8MB)
57 10:51:12.214053 progress 25% (10MB)
58 10:51:12.225709 progress 30% (13MB)
59 10:51:12.237528 progress 35% (15MB)
60 10:51:12.249686 progress 40% (17MB)
61 10:51:12.261561 progress 45% (19MB)
62 10:51:12.273427 progress 50% (21MB)
63 10:51:12.285007 progress 55% (24MB)
64 10:51:12.296762 progress 60% (26MB)
65 10:51:12.309047 progress 65% (28MB)
66 10:51:12.321198 progress 70% (30MB)
67 10:51:12.333280 progress 75% (32MB)
68 10:51:12.345536 progress 80% (34MB)
69 10:51:12.357954 progress 85% (37MB)
70 10:51:12.369857 progress 90% (39MB)
71 10:51:12.381653 progress 95% (41MB)
72 10:51:12.393339 progress 100% (43MB)
73 10:51:12.393484 43MB downloaded in 0.54s (80.62MB/s)
74 10:51:12.393635 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:51:12.393871 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:51:12.393962 start: 1.3 download-retry (timeout 00:09:51) [common]
78 10:51:12.394052 start: 1.3.1 http-download (timeout 00:09:51) [common]
79 10:51:12.394191 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:51:12.394268 saving as /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/dtb/mt8192-asurada-spherion-r0.dtb
81 10:51:12.394332 total size: 46924 (0MB)
82 10:51:12.394393 No compression specified
83 10:51:12.395525 progress 69% (0MB)
84 10:51:12.395807 progress 100% (0MB)
85 10:51:12.395976 0MB downloaded in 0.00s (27.28MB/s)
86 10:51:12.396102 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:51:12.396330 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:51:12.396418 start: 1.4 download-retry (timeout 00:09:51) [common]
90 10:51:12.396504 start: 1.4.1 http-download (timeout 00:09:51) [common]
91 10:51:12.396619 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:51:12.396691 saving as /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/modules/modules.tar
93 10:51:12.396752 total size: 8542412 (8MB)
94 10:51:12.396814 Using unxz to decompress xz
95 10:51:12.400420 progress 0% (0MB)
96 10:51:12.422315 progress 5% (0MB)
97 10:51:12.447396 progress 10% (0MB)
98 10:51:12.473539 progress 15% (1MB)
99 10:51:12.498451 progress 20% (1MB)
100 10:51:12.524394 progress 25% (2MB)
101 10:51:12.549481 progress 30% (2MB)
102 10:51:12.575150 progress 35% (2MB)
103 10:51:12.599963 progress 40% (3MB)
104 10:51:12.625416 progress 45% (3MB)
105 10:51:12.649313 progress 50% (4MB)
106 10:51:12.672133 progress 55% (4MB)
107 10:51:12.697266 progress 60% (4MB)
108 10:51:12.722508 progress 65% (5MB)
109 10:51:12.747957 progress 70% (5MB)
110 10:51:12.774950 progress 75% (6MB)
111 10:51:12.804633 progress 80% (6MB)
112 10:51:12.827477 progress 85% (6MB)
113 10:51:12.852277 progress 90% (7MB)
114 10:51:12.875289 progress 95% (7MB)
115 10:51:12.899180 progress 100% (8MB)
116 10:51:12.904768 8MB downloaded in 0.51s (16.04MB/s)
117 10:51:12.905060 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:51:12.905348 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:51:12.905456 start: 1.5 prepare-tftp-overlay (timeout 00:09:51) [common]
121 10:51:12.905567 start: 1.5.1 extract-nfsrootfs (timeout 00:09:51) [common]
122 10:51:12.905691 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:51:12.905820 start: 1.5.2 lava-overlay (timeout 00:09:51) [common]
124 10:51:12.906092 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9
125 10:51:12.906263 makedir: /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin
126 10:51:12.906404 makedir: /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/tests
127 10:51:12.906541 makedir: /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/results
128 10:51:12.906693 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-add-keys
129 10:51:12.906913 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-add-sources
130 10:51:12.907060 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-background-process-start
131 10:51:12.907232 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-background-process-stop
132 10:51:12.907397 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-common-functions
133 10:51:12.907573 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-echo-ipv4
134 10:51:12.907739 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-install-packages
135 10:51:12.907901 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-installed-packages
136 10:51:12.908038 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-os-build
137 10:51:12.908176 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-probe-channel
138 10:51:12.908317 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-probe-ip
139 10:51:12.908483 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-target-ip
140 10:51:12.908647 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-target-mac
141 10:51:12.908810 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-target-storage
142 10:51:12.908982 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-case
143 10:51:12.909148 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-event
144 10:51:12.909312 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-feedback
145 10:51:12.909477 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-raise
146 10:51:12.909643 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-reference
147 10:51:12.909807 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-runner
148 10:51:12.909967 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-set
149 10:51:12.910105 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-test-shell
150 10:51:12.910249 Updating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-install-packages (oe)
151 10:51:12.910442 Updating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/bin/lava-installed-packages (oe)
152 10:51:12.910601 Creating /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/environment
153 10:51:12.910742 LAVA metadata
154 10:51:12.910870 - LAVA_JOB_ID=10590977
155 10:51:12.910966 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:51:12.911099 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:51) [common]
157 10:51:12.911199 skipped lava-vland-overlay
158 10:51:12.911319 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:51:12.911443 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
160 10:51:12.911541 skipped lava-multinode-overlay
161 10:51:12.911661 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:51:12.911789 start: 1.5.2.3 test-definition (timeout 00:09:51) [common]
163 10:51:12.911905 Loading test definitions
164 10:51:12.912037 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:51) [common]
165 10:51:12.912142 Using /lava-10590977 at stage 0
166 10:51:12.912546 uuid=10590977_1.5.2.3.1 testdef=None
167 10:51:12.912664 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:51:12.912779 start: 1.5.2.3.2 test-overlay (timeout 00:09:51) [common]
169 10:51:12.913576 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:51:12.913923 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:51) [common]
172 10:51:12.914770 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:51:12.915102 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
175 10:51:12.915679 runner path: /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/0/tests/0_igt-gpu-panfrost test_uuid 10590977_1.5.2.3.1
176 10:51:12.915831 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:51:12.916037 Creating lava-test-runner.conf files
179 10:51:12.916100 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10590977/lava-overlay-56ujxtr9/lava-10590977/0 for stage 0
180 10:51:12.916186 - 0_igt-gpu-panfrost
181 10:51:12.916280 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:51:12.916363 start: 1.5.2.4 compress-overlay (timeout 00:09:51) [common]
183 10:51:12.922988 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:51:12.923095 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
185 10:51:12.923183 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:51:12.923268 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:51:12.923359 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
188 10:51:14.279808 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:51:14.280186 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
190 10:51:14.280350 extracting modules file /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590977/extract-overlay-ramdisk-edv9zxpi/ramdisk
191 10:51:14.491201 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:51:14.491377 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
193 10:51:14.491492 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590977/compress-overlay-pnvogpco/overlay-1.5.2.4.tar.gz to ramdisk
194 10:51:14.491578 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590977/compress-overlay-pnvogpco/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10590977/extract-overlay-ramdisk-edv9zxpi/ramdisk
195 10:51:14.497882 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:51:14.498008 start: 1.5.6 configure-preseed-file (timeout 00:09:49) [common]
197 10:51:14.498129 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:51:14.498236 start: 1.5.7 compress-ramdisk (timeout 00:09:49) [common]
199 10:51:14.498356 Building ramdisk /var/lib/lava/dispatcher/tmp/10590977/extract-overlay-ramdisk-edv9zxpi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10590977/extract-overlay-ramdisk-edv9zxpi/ramdisk
200 10:51:15.378312 >> 369039 blocks
201 10:51:21.059646 rename /var/lib/lava/dispatcher/tmp/10590977/extract-overlay-ramdisk-edv9zxpi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/ramdisk/ramdisk.cpio.gz
202 10:51:21.060070 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 10:51:21.060192 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
204 10:51:21.060293 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
205 10:51:21.060401 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/kernel/Image'
206 10:51:32.801058 Returned 0 in 11 seconds
207 10:51:32.901647 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/kernel/image.itb
208 10:51:33.808145 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:51:33.808497 output: Created: Mon Jun 5 11:51:33 2023
210 10:51:33.808574 output: Image 0 (kernel-1)
211 10:51:33.808641 output: Description:
212 10:51:33.808708 output: Created: Mon Jun 5 11:51:33 2023
213 10:51:33.808771 output: Type: Kernel Image
214 10:51:33.808834 output: Compression: lzma compressed
215 10:51:33.808893 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
216 10:51:33.808952 output: Architecture: AArch64
217 10:51:33.809006 output: OS: Linux
218 10:51:33.809060 output: Load Address: 0x00000000
219 10:51:33.809113 output: Entry Point: 0x00000000
220 10:51:33.809169 output: Hash algo: crc32
221 10:51:33.809223 output: Hash value: 8ce42972
222 10:51:33.809276 output: Image 1 (fdt-1)
223 10:51:33.809329 output: Description: mt8192-asurada-spherion-r0
224 10:51:33.809382 output: Created: Mon Jun 5 11:51:33 2023
225 10:51:33.809436 output: Type: Flat Device Tree
226 10:51:33.809505 output: Compression: uncompressed
227 10:51:33.809603 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:51:33.809687 output: Architecture: AArch64
229 10:51:33.809740 output: Hash algo: crc32
230 10:51:33.809792 output: Hash value: 1df858fa
231 10:51:33.809845 output: Image 2 (ramdisk-1)
232 10:51:33.809897 output: Description: unavailable
233 10:51:33.809950 output: Created: Mon Jun 5 11:51:33 2023
234 10:51:33.810003 output: Type: RAMDisk Image
235 10:51:33.810055 output: Compression: Unknown Compression
236 10:51:33.810108 output: Data Size: 56348737 Bytes = 55028.06 KiB = 53.74 MiB
237 10:51:33.810162 output: Architecture: AArch64
238 10:51:33.810215 output: OS: Linux
239 10:51:33.810267 output: Load Address: unavailable
240 10:51:33.810320 output: Entry Point: unavailable
241 10:51:33.810373 output: Hash algo: crc32
242 10:51:33.810425 output: Hash value: 5bb2ae2a
243 10:51:33.810478 output: Default Configuration: 'conf-1'
244 10:51:33.810530 output: Configuration 0 (conf-1)
245 10:51:33.810641 output: Description: mt8192-asurada-spherion-r0
246 10:51:33.810693 output: Kernel: kernel-1
247 10:51:33.810746 output: Init Ramdisk: ramdisk-1
248 10:51:33.810797 output: FDT: fdt-1
249 10:51:33.810887 output: Loadables: kernel-1
250 10:51:33.810940 output:
251 10:51:33.811128 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:51:33.811226 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:51:33.811332 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 10:51:33.811427 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
255 10:51:33.811506 No LXC device requested
256 10:51:33.811585 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:51:33.811676 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
258 10:51:33.811754 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:51:33.811822 Checking files for TFTP limit of 4294967296 bytes.
260 10:51:33.812310 end: 1 tftp-deploy (duration 00:00:30) [common]
261 10:51:33.812415 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:51:33.812508 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:51:33.812628 substitutions:
264 10:51:33.812695 - {DTB}: 10590977/tftp-deploy-rfimzci5/dtb/mt8192-asurada-spherion-r0.dtb
265 10:51:33.812758 - {INITRD}: 10590977/tftp-deploy-rfimzci5/ramdisk/ramdisk.cpio.gz
266 10:51:33.812817 - {KERNEL}: 10590977/tftp-deploy-rfimzci5/kernel/Image
267 10:51:33.812874 - {LAVA_MAC}: None
268 10:51:33.812930 - {PRESEED_CONFIG}: None
269 10:51:33.812986 - {PRESEED_LOCAL}: None
270 10:51:33.813040 - {RAMDISK}: 10590977/tftp-deploy-rfimzci5/ramdisk/ramdisk.cpio.gz
271 10:51:33.813095 - {ROOT_PART}: None
272 10:51:33.813149 - {ROOT}: None
273 10:51:33.813203 - {SERVER_IP}: 192.168.201.1
274 10:51:33.813256 - {TEE}: None
275 10:51:33.813310 Parsed boot commands:
276 10:51:33.813363 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:51:33.813529 Parsed boot commands: tftpboot 192.168.201.1 10590977/tftp-deploy-rfimzci5/kernel/image.itb 10590977/tftp-deploy-rfimzci5/kernel/cmdline
278 10:51:33.813617 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:51:33.813701 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:51:33.813791 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:51:33.813877 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:51:33.813949 Not connected, no need to disconnect.
283 10:51:33.814024 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:51:33.814105 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:51:33.814173 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 10:51:33.817606 Setting prompt string to ['lava-test: # ']
287 10:51:33.817939 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:51:33.818071 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:51:33.818183 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:51:33.818275 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:51:33.818495 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 10:51:38.952850 >> Command sent successfully.
293 10:51:38.955481 Returned 0 in 5 seconds
294 10:51:39.055850 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:51:39.056437 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:51:39.056541 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:51:39.056646 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:51:39.056713 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:51:39.056781 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:51:39.057036 [Enter `^Ec?' for help]
302 10:51:39.229088
303 10:51:39.229235
304 10:51:39.229338 F0: 102B 0000
305 10:51:39.229421
306 10:51:39.229524 F3: 1001 0000 [0200]
307 10:51:39.229630
308 10:51:39.232883 F3: 1001 0000
309 10:51:39.233018
310 10:51:39.233118 F7: 102D 0000
311 10:51:39.233212
312 10:51:39.236140 F1: 0000 0000
313 10:51:39.236248
314 10:51:39.236329 V0: 0000 0000 [0001]
315 10:51:39.236401
316 10:51:39.239502 00: 0007 8000
317 10:51:39.239593
318 10:51:39.239679 01: 0000 0000
319 10:51:39.239764
320 10:51:39.242772 BP: 0C00 0209 [0000]
321 10:51:39.242865
322 10:51:39.242956 G0: 1182 0000
323 10:51:39.243058
324 10:51:39.243159 EC: 0000 0021 [4000]
325 10:51:39.246786
326 10:51:39.246884 S7: 0000 0000 [0000]
327 10:51:39.246986
328 10:51:39.249576 CC: 0000 0000 [0001]
329 10:51:39.249693
330 10:51:39.249797 T0: 0000 0040 [010F]
331 10:51:39.249910
332 10:51:39.250013 Jump to BL
333 10:51:39.250128
334 10:51:39.276104
335 10:51:39.276260
336 10:51:39.276371
337 10:51:39.282951 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:51:39.286708 ARM64: Exception handlers installed.
339 10:51:39.290373 ARM64: Testing exception
340 10:51:39.293613 ARM64: Done test exception
341 10:51:39.300033 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:51:39.310418 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:51:39.316496 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:51:39.326584 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:51:39.333564 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:51:39.343835 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:51:39.354561 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:51:39.360959 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:51:39.379277 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:51:39.382378 WDT: Last reset was cold boot
351 10:51:39.386268 SPI1(PAD0) initialized at 2873684 Hz
352 10:51:39.388894 SPI5(PAD0) initialized at 992727 Hz
353 10:51:39.392358 VBOOT: Loading verstage.
354 10:51:39.399311 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:51:39.402697 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:51:39.405744 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:51:39.408990 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:51:39.416175 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:51:39.422789 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:51:39.434051 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 10:51:39.434173
362 10:51:39.434271
363 10:51:39.443589 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:51:39.447781 ARM64: Exception handlers installed.
365 10:51:39.450274 ARM64: Testing exception
366 10:51:39.450385 ARM64: Done test exception
367 10:51:39.457518 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:51:39.460314 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:51:39.475362 Probing TPM: . done!
370 10:51:39.475470 TPM ready after 0 ms
371 10:51:39.481806 Connected to device vid:did:rid of 1ae0:0028:00
372 10:51:39.488485 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 10:51:39.531594 Initialized TPM device CR50 revision 0
374 10:51:39.543134 tlcl_send_startup: Startup return code is 0
375 10:51:39.543282 TPM: setup succeeded
376 10:51:39.554189 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:51:39.562837 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:51:39.574154 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:51:39.583830 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:51:39.586962 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:51:39.590784 in-header: 03 07 00 00 08 00 00 00
382 10:51:39.594549 in-data: aa e4 47 04 13 02 00 00
383 10:51:39.597999 Chrome EC: UHEPI supported
384 10:51:39.605244 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:51:39.609162 in-header: 03 9d 00 00 08 00 00 00
386 10:51:39.612570 in-data: 10 20 20 08 00 00 00 00
387 10:51:39.612654 Phase 1
388 10:51:39.616439 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:51:39.623651 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:51:39.627363 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:51:39.631160 Recovery requested (1009000e)
392 10:51:39.635309 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:51:39.643610 tlcl_extend: response is 0
394 10:51:39.652228 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:51:39.657255 tlcl_extend: response is 0
396 10:51:39.663739 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:51:39.684442 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:51:39.691907 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:51:39.692044
400 10:51:39.692117
401 10:51:39.702288 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:51:39.706504 ARM64: Exception handlers installed.
403 10:51:39.706589 ARM64: Testing exception
404 10:51:39.709390 ARM64: Done test exception
405 10:51:39.730078 pmic_efuse_setting: Set efuses in 11 msecs
406 10:51:39.733779 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:51:39.737842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:51:39.744746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:51:39.748879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:51:39.751842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:51:39.759238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:51:39.762846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:51:39.766028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:51:39.773491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:51:39.777041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:51:39.783223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:51:39.786788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:51:39.790364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:51:39.796486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:51:39.803559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:51:39.806743 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:51:39.813114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:51:39.820220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:51:39.823514 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:51:39.830601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:51:39.837796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:51:39.841491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:51:39.848537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:51:39.851600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:51:39.858842 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:51:39.862411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:51:39.869065 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:51:39.876197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:51:39.879438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:51:39.882800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:51:39.889249 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:51:39.892968 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:51:39.900115 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:51:39.903738 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:51:39.907727 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:51:39.914876 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:51:39.918440 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:51:39.925237 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:51:39.928465 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:51:39.931803 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:51:39.938333 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:51:39.941473 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:51:39.945120 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:51:39.951477 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:51:39.954715 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:51:39.958041 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:51:39.964507 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:51:39.968245 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:51:39.971258 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:51:39.977837 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:51:39.981193 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:51:39.984447 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:51:39.990954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:51:40.001190 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:51:40.004140 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:51:40.014436 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:51:40.021074 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:51:40.027876 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:51:40.031073 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:51:40.034102 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:51:40.042218 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 10:51:40.049112 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:51:40.052238 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 10:51:40.055429 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:51:40.067005 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 10:51:40.070351 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 10:51:40.076799 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 10:51:40.080238 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 10:51:40.083662 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 10:51:40.086758 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 10:51:40.090600 ADC[4]: Raw value=896670 ID=7
477 10:51:40.093733 ADC[3]: Raw value=212700 ID=1
478 10:51:40.096859 RAM Code: 0x71
479 10:51:40.100302 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 10:51:40.103783 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 10:51:40.113504 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 10:51:40.120569 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 10:51:40.123787 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 10:51:40.127510 in-header: 03 07 00 00 08 00 00 00
485 10:51:40.130819 in-data: aa e4 47 04 13 02 00 00
486 10:51:40.133772 Chrome EC: UHEPI supported
487 10:51:40.140289 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 10:51:40.144105 in-header: 03 d5 00 00 08 00 00 00
489 10:51:40.147479 in-data: 98 20 60 08 00 00 00 00
490 10:51:40.150922 MRC: failed to locate region type 0.
491 10:51:40.154598 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 10:51:40.158347 DRAM-K: Running full calibration
493 10:51:40.165353 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 10:51:40.168845 header.status = 0x0
495 10:51:40.171717 header.version = 0x6 (expected: 0x6)
496 10:51:40.175148 header.size = 0xd00 (expected: 0xd00)
497 10:51:40.175278 header.flags = 0x0
498 10:51:40.181951 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 10:51:40.199494 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 10:51:40.205699 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 10:51:40.209271 dram_init: ddr_geometry: 2
502 10:51:40.212304 [EMI] MDL number = 2
503 10:51:40.212398 [EMI] Get MDL freq = 0
504 10:51:40.216213 dram_init: ddr_type: 0
505 10:51:40.216306 is_discrete_lpddr4: 1
506 10:51:40.219289 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 10:51:40.219377
508 10:51:40.219445
509 10:51:40.222698 [Bian_co] ETT version 0.0.0.1
510 10:51:40.229253 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 10:51:40.229381
512 10:51:40.232397 dramc_set_vcore_voltage set vcore to 650000
513 10:51:40.235475 Read voltage for 800, 4
514 10:51:40.235554 Vio18 = 0
515 10:51:40.235621 Vcore = 650000
516 10:51:40.238802 Vdram = 0
517 10:51:40.238896 Vddq = 0
518 10:51:40.238973 Vmddr = 0
519 10:51:40.242412 dram_init: config_dvfs: 1
520 10:51:40.245491 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 10:51:40.252307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 10:51:40.255271 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 10:51:40.259051 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 10:51:40.262134 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 10:51:40.269132 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 10:51:40.269227 MEM_TYPE=3, freq_sel=18
527 10:51:40.272113 sv_algorithm_assistance_LP4_1600
528 10:51:40.275245 ============ PULL DRAM RESETB DOWN ============
529 10:51:40.281917 ========== PULL DRAM RESETB DOWN end =========
530 10:51:40.285292 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 10:51:40.288797 ===================================
532 10:51:40.292272 LPDDR4 DRAM CONFIGURATION
533 10:51:40.295138 ===================================
534 10:51:40.295230 EX_ROW_EN[0] = 0x0
535 10:51:40.298739 EX_ROW_EN[1] = 0x0
536 10:51:40.298857 LP4Y_EN = 0x0
537 10:51:40.301679 WORK_FSP = 0x0
538 10:51:40.301795 WL = 0x2
539 10:51:40.305285 RL = 0x2
540 10:51:40.305371 BL = 0x2
541 10:51:40.308348 RPST = 0x0
542 10:51:40.312059 RD_PRE = 0x0
543 10:51:40.312146 WR_PRE = 0x1
544 10:51:40.315124 WR_PST = 0x0
545 10:51:40.315210 DBI_WR = 0x0
546 10:51:40.318307 DBI_RD = 0x0
547 10:51:40.318396 OTF = 0x1
548 10:51:40.322037 ===================================
549 10:51:40.325618 ===================================
550 10:51:40.325735 ANA top config
551 10:51:40.329064 ===================================
552 10:51:40.332363 DLL_ASYNC_EN = 0
553 10:51:40.336236 ALL_SLAVE_EN = 1
554 10:51:40.339993 NEW_RANK_MODE = 1
555 10:51:40.340086 DLL_IDLE_MODE = 1
556 10:51:40.343636 LP45_APHY_COMB_EN = 1
557 10:51:40.346794 TX_ODT_DIS = 1
558 10:51:40.346908 NEW_8X_MODE = 1
559 10:51:40.350589 ===================================
560 10:51:40.354354 ===================================
561 10:51:40.358023 data_rate = 1600
562 10:51:40.361974 CKR = 1
563 10:51:40.362096 DQ_P2S_RATIO = 8
564 10:51:40.365779 ===================================
565 10:51:40.368974 CA_P2S_RATIO = 8
566 10:51:40.372801 DQ_CA_OPEN = 0
567 10:51:40.376073 DQ_SEMI_OPEN = 0
568 10:51:40.376166 CA_SEMI_OPEN = 0
569 10:51:40.379891 CA_FULL_RATE = 0
570 10:51:40.383726 DQ_CKDIV4_EN = 1
571 10:51:40.387369 CA_CKDIV4_EN = 1
572 10:51:40.387487 CA_PREDIV_EN = 0
573 10:51:40.391016 PH8_DLY = 0
574 10:51:40.394958 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 10:51:40.397900 DQ_AAMCK_DIV = 4
576 10:51:40.398014 CA_AAMCK_DIV = 4
577 10:51:40.401855 CA_ADMCK_DIV = 4
578 10:51:40.405497 DQ_TRACK_CA_EN = 0
579 10:51:40.409288 CA_PICK = 800
580 10:51:40.412816 CA_MCKIO = 800
581 10:51:40.412932 MCKIO_SEMI = 0
582 10:51:40.415977 PLL_FREQ = 3068
583 10:51:40.419795 DQ_UI_PI_RATIO = 32
584 10:51:40.423079 CA_UI_PI_RATIO = 0
585 10:51:40.426353 ===================================
586 10:51:40.429345 ===================================
587 10:51:40.432463 memory_type:LPDDR4
588 10:51:40.432586 GP_NUM : 10
589 10:51:40.436231 SRAM_EN : 1
590 10:51:40.436359 MD32_EN : 0
591 10:51:40.439261 ===================================
592 10:51:40.442441 [ANA_INIT] >>>>>>>>>>>>>>
593 10:51:40.446224 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 10:51:40.449567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 10:51:40.452634 ===================================
596 10:51:40.455895 data_rate = 1600,PCW = 0X7600
597 10:51:40.459530 ===================================
598 10:51:40.462528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 10:51:40.469223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 10:51:40.472420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 10:51:40.478904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 10:51:40.482461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 10:51:40.485718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 10:51:40.485840 [ANA_INIT] flow start
605 10:51:40.489524 [ANA_INIT] PLL >>>>>>>>
606 10:51:40.489655 [ANA_INIT] PLL <<<<<<<<
607 10:51:40.493321 [ANA_INIT] MIDPI >>>>>>>>
608 10:51:40.496859 [ANA_INIT] MIDPI <<<<<<<<
609 10:51:40.500527 [ANA_INIT] DLL >>>>>>>>
610 10:51:40.500651 [ANA_INIT] flow end
611 10:51:40.504200 ============ LP4 DIFF to SE enter ============
612 10:51:40.507535 ============ LP4 DIFF to SE exit ============
613 10:51:40.511042 [ANA_INIT] <<<<<<<<<<<<<
614 10:51:40.515370 [Flow] Enable top DCM control >>>>>
615 10:51:40.518381 [Flow] Enable top DCM control <<<<<
616 10:51:40.521978 Enable DLL master slave shuffle
617 10:51:40.525891 ==============================================================
618 10:51:40.529239 Gating Mode config
619 10:51:40.532519 ==============================================================
620 10:51:40.536207 Config description:
621 10:51:40.545684 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 10:51:40.552440 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 10:51:40.555705 SELPH_MODE 0: By rank 1: By Phase
624 10:51:40.562377 ==============================================================
625 10:51:40.565578 GAT_TRACK_EN = 1
626 10:51:40.569164 RX_GATING_MODE = 2
627 10:51:40.572540 RX_GATING_TRACK_MODE = 2
628 10:51:40.572665 SELPH_MODE = 1
629 10:51:40.575721 PICG_EARLY_EN = 1
630 10:51:40.579081 VALID_LAT_VALUE = 1
631 10:51:40.585444 ==============================================================
632 10:51:40.588577 Enter into Gating configuration >>>>
633 10:51:40.592010 Exit from Gating configuration <<<<
634 10:51:40.595203 Enter into DVFS_PRE_config >>>>>
635 10:51:40.605269 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 10:51:40.608607 Exit from DVFS_PRE_config <<<<<
637 10:51:40.612118 Enter into PICG configuration >>>>
638 10:51:40.615719 Exit from PICG configuration <<<<
639 10:51:40.619073 [RX_INPUT] configuration >>>>>
640 10:51:40.622016 [RX_INPUT] configuration <<<<<
641 10:51:40.625327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 10:51:40.631652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 10:51:40.638485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 10:51:40.645042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 10:51:40.652095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 10:51:40.655371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 10:51:40.658630 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 10:51:40.664888 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 10:51:40.668677 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 10:51:40.671726 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 10:51:40.675418 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 10:51:40.681996 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 10:51:40.685313 ===================================
654 10:51:40.688392 LPDDR4 DRAM CONFIGURATION
655 10:51:40.691552 ===================================
656 10:51:40.691666 EX_ROW_EN[0] = 0x0
657 10:51:40.694717 EX_ROW_EN[1] = 0x0
658 10:51:40.694805 LP4Y_EN = 0x0
659 10:51:40.698571 WORK_FSP = 0x0
660 10:51:40.698689 WL = 0x2
661 10:51:40.701926 RL = 0x2
662 10:51:40.702045 BL = 0x2
663 10:51:40.704689 RPST = 0x0
664 10:51:40.704799 RD_PRE = 0x0
665 10:51:40.708550 WR_PRE = 0x1
666 10:51:40.708651 WR_PST = 0x0
667 10:51:40.711551 DBI_WR = 0x0
668 10:51:40.711669 DBI_RD = 0x0
669 10:51:40.714790 OTF = 0x1
670 10:51:40.718361 ===================================
671 10:51:40.722156 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 10:51:40.724864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 10:51:40.731294 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 10:51:40.734810 ===================================
675 10:51:40.734937 LPDDR4 DRAM CONFIGURATION
676 10:51:40.738562 ===================================
677 10:51:40.741383 EX_ROW_EN[0] = 0x10
678 10:51:40.745016 EX_ROW_EN[1] = 0x0
679 10:51:40.745126 LP4Y_EN = 0x0
680 10:51:40.748148 WORK_FSP = 0x0
681 10:51:40.748230 WL = 0x2
682 10:51:40.751483 RL = 0x2
683 10:51:40.751588 BL = 0x2
684 10:51:40.754835 RPST = 0x0
685 10:51:40.754946 RD_PRE = 0x0
686 10:51:40.757972 WR_PRE = 0x1
687 10:51:40.758078 WR_PST = 0x0
688 10:51:40.761494 DBI_WR = 0x0
689 10:51:40.761573 DBI_RD = 0x0
690 10:51:40.764533 OTF = 0x1
691 10:51:40.768044 ===================================
692 10:51:40.774979 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 10:51:40.778959 nWR fixed to 40
694 10:51:40.779050 [ModeRegInit_LP4] CH0 RK0
695 10:51:40.782637 [ModeRegInit_LP4] CH0 RK1
696 10:51:40.785942 [ModeRegInit_LP4] CH1 RK0
697 10:51:40.786057 [ModeRegInit_LP4] CH1 RK1
698 10:51:40.789309 match AC timing 13
699 10:51:40.793169 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 10:51:40.796950 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 10:51:40.800130 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 10:51:40.807324 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 10:51:40.811441 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 10:51:40.811557 [EMI DOE] emi_dcm 0
705 10:51:40.818460 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 10:51:40.818565 ==
707 10:51:40.822363 Dram Type= 6, Freq= 0, CH_0, rank 0
708 10:51:40.825938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 10:51:40.826025 ==
710 10:51:40.828930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 10:51:40.835837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 10:51:40.845429 [CA 0] Center 37 (7~68) winsize 62
713 10:51:40.849182 [CA 1] Center 37 (7~68) winsize 62
714 10:51:40.853139 [CA 2] Center 35 (5~66) winsize 62
715 10:51:40.856978 [CA 3] Center 35 (5~66) winsize 62
716 10:51:40.860306 [CA 4] Center 34 (4~65) winsize 62
717 10:51:40.860421 [CA 5] Center 34 (4~65) winsize 62
718 10:51:40.864638
719 10:51:40.868144 [CmdBusTrainingLP45] Vref(ca) range 1: 30
720 10:51:40.868267
721 10:51:40.871561 [CATrainingPosCal] consider 1 rank data
722 10:51:40.871674 u2DelayCellTimex100 = 270/100 ps
723 10:51:40.875283 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
724 10:51:40.879060 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 10:51:40.882847 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 10:51:40.886441 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 10:51:40.890309 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 10:51:40.894107 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 10:51:40.894232
730 10:51:40.897844 CA PerBit enable=1, Macro0, CA PI delay=34
731 10:51:40.897970
732 10:51:40.901039 [CBTSetCACLKResult] CA Dly = 34
733 10:51:40.904911 CS Dly: 6 (0~37)
734 10:51:40.904997 ==
735 10:51:40.905068 Dram Type= 6, Freq= 0, CH_0, rank 1
736 10:51:40.912855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 10:51:40.912998 ==
738 10:51:40.916080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 10:51:40.923117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 10:51:40.931901 [CA 0] Center 37 (7~68) winsize 62
741 10:51:40.935527 [CA 1] Center 38 (7~69) winsize 63
742 10:51:40.939620 [CA 2] Center 35 (5~66) winsize 62
743 10:51:40.943387 [CA 3] Center 35 (5~66) winsize 62
744 10:51:40.947016 [CA 4] Center 34 (4~65) winsize 62
745 10:51:40.947110 [CA 5] Center 34 (4~65) winsize 62
746 10:51:40.947179
747 10:51:40.950592 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 10:51:40.950712
749 10:51:40.954755 [CATrainingPosCal] consider 2 rank data
750 10:51:40.957962 u2DelayCellTimex100 = 270/100 ps
751 10:51:40.961915 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
752 10:51:40.965771 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 10:51:40.969425 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 10:51:40.973112 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 10:51:40.976909 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 10:51:40.980610 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 10:51:40.980726
758 10:51:40.983833 CA PerBit enable=1, Macro0, CA PI delay=34
759 10:51:40.983923
760 10:51:40.987801 [CBTSetCACLKResult] CA Dly = 34
761 10:51:40.987902 CS Dly: 6 (0~38)
762 10:51:40.991864
763 10:51:40.991947 ----->DramcWriteLeveling(PI) begin...
764 10:51:40.995382 ==
765 10:51:40.995468 Dram Type= 6, Freq= 0, CH_0, rank 0
766 10:51:40.998736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 10:51:41.002806 ==
768 10:51:41.002919 Write leveling (Byte 0): 32 => 32
769 10:51:41.006131 Write leveling (Byte 1): 32 => 32
770 10:51:41.010135 DramcWriteLeveling(PI) end<-----
771 10:51:41.010258
772 10:51:41.010360 ==
773 10:51:41.013367 Dram Type= 6, Freq= 0, CH_0, rank 0
774 10:51:41.017327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 10:51:41.017443 ==
776 10:51:41.021054 [Gating] SW mode calibration
777 10:51:41.028413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 10:51:41.031819 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 10:51:41.036161 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 10:51:41.043268 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 10:51:41.046957 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 10:51:41.050638 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 10:51:41.054442 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 10:51:41.057909 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 10:51:41.065934 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 10:51:41.069329 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 10:51:41.072998 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 10:51:41.076552 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 10:51:41.080454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:51:41.084459 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:51:41.090681 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:51:41.094295 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:51:41.097628 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:51:41.104209 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:51:41.107861 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:51:41.110973 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:51:41.117528 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 10:51:41.120736 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 10:51:41.123934 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:51:41.131108 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:51:41.133945 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:51:41.137652 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:51:41.144174 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:51:41.147337 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 10:51:41.151057 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:51:41.157537 0 9 12 | B1->B0 | 2323 3333 | 1 0 | (1 1) (0 0)
807 10:51:41.160515 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 10:51:41.164253 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 10:51:41.170539 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 10:51:41.173782 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 10:51:41.177000 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 10:51:41.180833 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
813 10:51:41.187330 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
814 10:51:41.190583 0 10 12 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
815 10:51:41.197443 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 10:51:41.200121 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 10:51:41.203432 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 10:51:41.207174 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 10:51:41.213576 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 10:51:41.216814 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 10:51:41.220224 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
822 10:51:41.226572 0 11 12 | B1->B0 | 3131 4343 | 0 0 | (1 1) (0 0)
823 10:51:41.230385 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 10:51:41.233641 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 10:51:41.239854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 10:51:41.243254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 10:51:41.247027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 10:51:41.253399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 10:51:41.256439 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 10:51:41.260026 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 10:51:41.266654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 10:51:41.270196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 10:51:41.273105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 10:51:41.279813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 10:51:41.283031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 10:51:41.286891 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 10:51:41.293356 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:51:41.296570 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:51:41.299672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:51:41.306303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:51:41.309925 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:51:41.313247 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:51:41.319809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:51:41.323112 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:51:41.326392 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 10:51:41.333253 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 10:51:41.333372 Total UI for P1: 0, mck2ui 16
848 10:51:41.336257 best dqsien dly found for B0: ( 0, 14, 8)
849 10:51:41.343099 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 10:51:41.346720 Total UI for P1: 0, mck2ui 16
851 10:51:41.349755 best dqsien dly found for B1: ( 0, 14, 12)
852 10:51:41.352912 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 10:51:41.356051 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 10:51:41.356132
855 10:51:41.359975 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 10:51:41.363116 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 10:51:41.366126 [Gating] SW calibration Done
858 10:51:41.366209 ==
859 10:51:41.369592 Dram Type= 6, Freq= 0, CH_0, rank 0
860 10:51:41.372624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 10:51:41.372713 ==
862 10:51:41.376203 RX Vref Scan: 0
863 10:51:41.376308
864 10:51:41.379341 RX Vref 0 -> 0, step: 1
865 10:51:41.379440
866 10:51:41.379546 RX Delay -130 -> 252, step: 16
867 10:51:41.386245 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 10:51:41.389249 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 10:51:41.392928 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 10:51:41.396123 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 10:51:41.399344 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 10:51:41.406068 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 10:51:41.409400 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 10:51:41.412586 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 10:51:41.415930 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
876 10:51:41.419545 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 10:51:41.426207 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 10:51:41.429450 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 10:51:41.432588 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 10:51:41.435796 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 10:51:41.442768 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 10:51:41.445864 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 10:51:41.445955 ==
884 10:51:41.449105 Dram Type= 6, Freq= 0, CH_0, rank 0
885 10:51:41.452681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 10:51:41.452798 ==
887 10:51:41.452898 DQS Delay:
888 10:51:41.456024 DQS0 = 0, DQS1 = 0
889 10:51:41.456114 DQM Delay:
890 10:51:41.459376 DQM0 = 81, DQM1 = 70
891 10:51:41.459491 DQ Delay:
892 10:51:41.462581 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 10:51:41.465908 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 10:51:41.469144 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
895 10:51:41.472839 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 10:51:41.472954
897 10:51:41.473055
898 10:51:41.473151 ==
899 10:51:41.475950 Dram Type= 6, Freq= 0, CH_0, rank 0
900 10:51:41.479865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 10:51:41.479983 ==
902 10:51:41.482914
903 10:51:41.483026
904 10:51:41.483129 TX Vref Scan disable
905 10:51:41.486515 == TX Byte 0 ==
906 10:51:41.489507 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 10:51:41.492576 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 10:51:41.496029 == TX Byte 1 ==
909 10:51:41.499138 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 10:51:41.502448 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 10:51:41.502533 ==
912 10:51:41.506631 Dram Type= 6, Freq= 0, CH_0, rank 0
913 10:51:41.512482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 10:51:41.512578 ==
915 10:51:41.524291 TX Vref=22, minBit 1, minWin=26, winSum=430
916 10:51:41.527900 TX Vref=24, minBit 0, minWin=27, winSum=437
917 10:51:41.531229 TX Vref=26, minBit 0, minWin=27, winSum=443
918 10:51:41.534080 TX Vref=28, minBit 0, minWin=27, winSum=442
919 10:51:41.537876 TX Vref=30, minBit 9, minWin=27, winSum=445
920 10:51:41.544181 TX Vref=32, minBit 9, minWin=27, winSum=443
921 10:51:41.547973 [TxChooseVref] Worse bit 9, Min win 27, Win sum 445, Final Vref 30
922 10:51:41.548066
923 10:51:41.551277 Final TX Range 1 Vref 30
924 10:51:41.551373
925 10:51:41.551440 ==
926 10:51:41.554211 Dram Type= 6, Freq= 0, CH_0, rank 0
927 10:51:41.557872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 10:51:41.557976 ==
929 10:51:41.561187
930 10:51:41.561289
931 10:51:41.561385 TX Vref Scan disable
932 10:51:41.564448 == TX Byte 0 ==
933 10:51:41.567749 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 10:51:41.574372 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 10:51:41.574483 == TX Byte 1 ==
936 10:51:41.577473 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
937 10:51:41.584011 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
938 10:51:41.584121
939 10:51:41.584219 [DATLAT]
940 10:51:41.584312 Freq=800, CH0 RK0
941 10:51:41.584406
942 10:51:41.587914 DATLAT Default: 0xa
943 10:51:41.588027 0, 0xFFFF, sum = 0
944 10:51:41.591106 1, 0xFFFF, sum = 0
945 10:51:41.593974 2, 0xFFFF, sum = 0
946 10:51:41.594058 3, 0xFFFF, sum = 0
947 10:51:41.597571 4, 0xFFFF, sum = 0
948 10:51:41.597678 5, 0xFFFF, sum = 0
949 10:51:41.600555 6, 0xFFFF, sum = 0
950 10:51:41.600632 7, 0xFFFF, sum = 0
951 10:51:41.603930 8, 0xFFFF, sum = 0
952 10:51:41.604001 9, 0x0, sum = 1
953 10:51:41.607581 10, 0x0, sum = 2
954 10:51:41.607657 11, 0x0, sum = 3
955 10:51:41.607722 12, 0x0, sum = 4
956 10:51:41.610715 best_step = 10
957 10:51:41.610811
958 10:51:41.610890 ==
959 10:51:41.613898 Dram Type= 6, Freq= 0, CH_0, rank 0
960 10:51:41.617673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 10:51:41.617773 ==
962 10:51:41.620589 RX Vref Scan: 1
963 10:51:41.620679
964 10:51:41.623893 Set Vref Range= 32 -> 127
965 10:51:41.623979
966 10:51:41.624049 RX Vref 32 -> 127, step: 1
967 10:51:41.624114
968 10:51:41.627657 RX Delay -111 -> 252, step: 8
969 10:51:41.627769
970 10:51:41.630788 Set Vref, RX VrefLevel [Byte0]: 32
971 10:51:41.634085 [Byte1]: 32
972 10:51:41.634197
973 10:51:41.637691 Set Vref, RX VrefLevel [Byte0]: 33
974 10:51:41.640768 [Byte1]: 33
975 10:51:41.644975
976 10:51:41.645068 Set Vref, RX VrefLevel [Byte0]: 34
977 10:51:41.648204 [Byte1]: 34
978 10:51:41.652589
979 10:51:41.652676 Set Vref, RX VrefLevel [Byte0]: 35
980 10:51:41.655999 [Byte1]: 35
981 10:51:41.660436
982 10:51:41.660523 Set Vref, RX VrefLevel [Byte0]: 36
983 10:51:41.663472 [Byte1]: 36
984 10:51:41.667988
985 10:51:41.668067 Set Vref, RX VrefLevel [Byte0]: 37
986 10:51:41.671117 [Byte1]: 37
987 10:51:41.675465
988 10:51:41.675554 Set Vref, RX VrefLevel [Byte0]: 38
989 10:51:41.678592 [Byte1]: 38
990 10:51:41.682919
991 10:51:41.682998 Set Vref, RX VrefLevel [Byte0]: 39
992 10:51:41.686623 [Byte1]: 39
993 10:51:41.690457
994 10:51:41.690546 Set Vref, RX VrefLevel [Byte0]: 40
995 10:51:41.693856 [Byte1]: 40
996 10:51:41.698429
997 10:51:41.698519 Set Vref, RX VrefLevel [Byte0]: 41
998 10:51:41.701447 [Byte1]: 41
999 10:51:41.706096
1000 10:51:41.706204 Set Vref, RX VrefLevel [Byte0]: 42
1001 10:51:41.709073 [Byte1]: 42
1002 10:51:41.713368
1003 10:51:41.713484 Set Vref, RX VrefLevel [Byte0]: 43
1004 10:51:41.717200 [Byte1]: 43
1005 10:51:41.721428
1006 10:51:41.721523 Set Vref, RX VrefLevel [Byte0]: 44
1007 10:51:41.724332 [Byte1]: 44
1008 10:51:41.728856
1009 10:51:41.728941 Set Vref, RX VrefLevel [Byte0]: 45
1010 10:51:41.732882 [Byte1]: 45
1011 10:51:41.736684
1012 10:51:41.736771 Set Vref, RX VrefLevel [Byte0]: 46
1013 10:51:41.739938 [Byte1]: 46
1014 10:51:41.744723
1015 10:51:41.744809 Set Vref, RX VrefLevel [Byte0]: 47
1016 10:51:41.748136 [Byte1]: 47
1017 10:51:41.752410
1018 10:51:41.752527 Set Vref, RX VrefLevel [Byte0]: 48
1019 10:51:41.756206 [Byte1]: 48
1020 10:51:41.759730
1021 10:51:41.759818 Set Vref, RX VrefLevel [Byte0]: 49
1022 10:51:41.763422 [Byte1]: 49
1023 10:51:41.767862
1024 10:51:41.767954 Set Vref, RX VrefLevel [Byte0]: 50
1025 10:51:41.771268 [Byte1]: 50
1026 10:51:41.775113
1027 10:51:41.775200 Set Vref, RX VrefLevel [Byte0]: 51
1028 10:51:41.778413 [Byte1]: 51
1029 10:51:41.782226
1030 10:51:41.782309 Set Vref, RX VrefLevel [Byte0]: 52
1031 10:51:41.785943 [Byte1]: 52
1032 10:51:41.790471
1033 10:51:41.790560 Set Vref, RX VrefLevel [Byte0]: 53
1034 10:51:41.793716 [Byte1]: 53
1035 10:51:41.797538
1036 10:51:41.797648 Set Vref, RX VrefLevel [Byte0]: 54
1037 10:51:41.801239 [Byte1]: 54
1038 10:51:41.805493
1039 10:51:41.805581 Set Vref, RX VrefLevel [Byte0]: 55
1040 10:51:41.808578 [Byte1]: 55
1041 10:51:41.813305
1042 10:51:41.813415 Set Vref, RX VrefLevel [Byte0]: 56
1043 10:51:41.816480 [Byte1]: 56
1044 10:51:41.820683
1045 10:51:41.820768 Set Vref, RX VrefLevel [Byte0]: 57
1046 10:51:41.826787 [Byte1]: 57
1047 10:51:41.826891
1048 10:51:41.830734 Set Vref, RX VrefLevel [Byte0]: 58
1049 10:51:41.833789 [Byte1]: 58
1050 10:51:41.833874
1051 10:51:41.836990 Set Vref, RX VrefLevel [Byte0]: 59
1052 10:51:41.840408 [Byte1]: 59
1053 10:51:41.840492
1054 10:51:41.843619 Set Vref, RX VrefLevel [Byte0]: 60
1055 10:51:41.846738 [Byte1]: 60
1056 10:51:41.851410
1057 10:51:41.851496 Set Vref, RX VrefLevel [Byte0]: 61
1058 10:51:41.854927 [Byte1]: 61
1059 10:51:41.859290
1060 10:51:41.859375 Set Vref, RX VrefLevel [Byte0]: 62
1061 10:51:41.862026 [Byte1]: 62
1062 10:51:41.866412
1063 10:51:41.866493 Set Vref, RX VrefLevel [Byte0]: 63
1064 10:51:41.870080 [Byte1]: 63
1065 10:51:41.873854
1066 10:51:41.873963 Set Vref, RX VrefLevel [Byte0]: 64
1067 10:51:41.877688 [Byte1]: 64
1068 10:51:41.881799
1069 10:51:41.881909 Set Vref, RX VrefLevel [Byte0]: 65
1070 10:51:41.884937 [Byte1]: 65
1071 10:51:41.889234
1072 10:51:41.889322 Set Vref, RX VrefLevel [Byte0]: 66
1073 10:51:41.892989 [Byte1]: 66
1074 10:51:41.897008
1075 10:51:41.897088 Set Vref, RX VrefLevel [Byte0]: 67
1076 10:51:41.900306 [Byte1]: 67
1077 10:51:41.904969
1078 10:51:41.905053 Set Vref, RX VrefLevel [Byte0]: 68
1079 10:51:41.908162 [Byte1]: 68
1080 10:51:41.912450
1081 10:51:41.912533 Set Vref, RX VrefLevel [Byte0]: 69
1082 10:51:41.915474 [Byte1]: 69
1083 10:51:41.920342
1084 10:51:41.920427 Set Vref, RX VrefLevel [Byte0]: 70
1085 10:51:41.926376 [Byte1]: 70
1086 10:51:41.926502
1087 10:51:41.929806 Set Vref, RX VrefLevel [Byte0]: 71
1088 10:51:41.932984 [Byte1]: 71
1089 10:51:41.933102
1090 10:51:41.936196 Set Vref, RX VrefLevel [Byte0]: 72
1091 10:51:41.939843 [Byte1]: 72
1092 10:51:41.943031
1093 10:51:41.943117 Set Vref, RX VrefLevel [Byte0]: 73
1094 10:51:41.946230 [Byte1]: 73
1095 10:51:41.951051
1096 10:51:41.951139 Set Vref, RX VrefLevel [Byte0]: 74
1097 10:51:41.953693 [Byte1]: 74
1098 10:51:41.958335
1099 10:51:41.958424 Set Vref, RX VrefLevel [Byte0]: 75
1100 10:51:41.961909 [Byte1]: 75
1101 10:51:41.965693
1102 10:51:41.965775 Set Vref, RX VrefLevel [Byte0]: 76
1103 10:51:41.969305 [Byte1]: 76
1104 10:51:41.973611
1105 10:51:41.973761 Set Vref, RX VrefLevel [Byte0]: 77
1106 10:51:41.976723 [Byte1]: 77
1107 10:51:41.981249
1108 10:51:41.981373 Set Vref, RX VrefLevel [Byte0]: 78
1109 10:51:41.984507 [Byte1]: 78
1110 10:51:41.989141
1111 10:51:41.989226 Set Vref, RX VrefLevel [Byte0]: 79
1112 10:51:41.992235 [Byte1]: 79
1113 10:51:41.996700
1114 10:51:41.996801 Final RX Vref Byte 0 = 66 to rank0
1115 10:51:42.000162 Final RX Vref Byte 1 = 60 to rank0
1116 10:51:42.002859 Final RX Vref Byte 0 = 66 to rank1
1117 10:51:42.006181 Final RX Vref Byte 1 = 60 to rank1==
1118 10:51:42.009968 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 10:51:42.016421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 10:51:42.016507 ==
1121 10:51:42.016573 DQS Delay:
1122 10:51:42.016635 DQS0 = 0, DQS1 = 0
1123 10:51:42.019362 DQM Delay:
1124 10:51:42.019481 DQM0 = 80, DQM1 = 67
1125 10:51:42.022804 DQ Delay:
1126 10:51:42.026446 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =76
1127 10:51:42.029254 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1128 10:51:42.032730 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 10:51:42.035861 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1130 10:51:42.035956
1131 10:51:42.036022
1132 10:51:42.042764 [DQSOSCAuto] RK0, (LSB)MR18= 0x2625, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 10:51:42.045847 CH0 RK0: MR19=606, MR18=2625
1134 10:51:42.053024 CH0_RK0: MR19=0x606, MR18=0x2625, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 10:51:42.053111
1136 10:51:42.056095 ----->DramcWriteLeveling(PI) begin...
1137 10:51:42.056181 ==
1138 10:51:42.059147 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 10:51:42.062503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 10:51:42.062614 ==
1141 10:51:42.065783 Write leveling (Byte 0): 32 => 32
1142 10:51:42.069579 Write leveling (Byte 1): 29 => 29
1143 10:51:42.072738 DramcWriteLeveling(PI) end<-----
1144 10:51:42.072825
1145 10:51:42.072920 ==
1146 10:51:42.075750 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 10:51:42.079253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 10:51:42.079347 ==
1149 10:51:42.082761 [Gating] SW mode calibration
1150 10:51:42.089195 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 10:51:42.095788 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 10:51:42.099394 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 10:51:42.105970 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 10:51:42.109068 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 10:51:42.112312 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 10:51:42.118913 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:51:42.122125 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:51:42.125582 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:51:42.129090 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:51:42.135598 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:51:42.139193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:51:42.142624 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:51:42.148973 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:51:42.152034 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:51:42.196080 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:51:42.196398 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:51:42.196661 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:51:42.196764 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:51:42.196857 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 10:51:42.196947 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1171 10:51:42.197048 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:51:42.197138 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:51:42.197225 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:51:42.197310 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:51:42.240061 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:51:42.240372 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:51:42.240502 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:51:42.240604 0 9 8 | B1->B0 | 2323 3232 | 1 1 | (0 0) (1 1)
1179 10:51:42.240676 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:51:42.241212 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:51:42.241475 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:51:42.241557 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:51:42.241625 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:51:42.241698 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 10:51:42.244769 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1186 10:51:42.248164 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1187 10:51:42.255280 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1188 10:51:42.258406 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:51:42.261550 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:51:42.268506 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:51:42.271213 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:51:42.274737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:51:42.281821 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1194 10:51:42.284390 0 11 8 | B1->B0 | 2929 3737 | 1 0 | (0 0) (0 0)
1195 10:51:42.287966 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1196 10:51:42.294333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:51:42.298054 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:51:42.301159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:51:42.307860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:51:42.311578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:51:42.315615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:51:42.318573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 10:51:42.322506 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:51:42.329350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:51:42.332890 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:51:42.336337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:51:42.339876 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:51:42.346873 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:51:42.350290 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:51:42.353208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:51:42.360096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:51:42.363747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:51:42.366878 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:51:42.373573 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:51:42.376886 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:51:42.380139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:51:42.386462 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:51:42.389927 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1219 10:51:42.393562 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 10:51:42.396463 Total UI for P1: 0, mck2ui 16
1221 10:51:42.399715 best dqsien dly found for B0: ( 0, 14, 8)
1222 10:51:42.406654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 10:51:42.406741 Total UI for P1: 0, mck2ui 16
1224 10:51:42.413399 best dqsien dly found for B1: ( 0, 14, 12)
1225 10:51:42.416629 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1226 10:51:42.419914 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1227 10:51:42.420032
1228 10:51:42.423088 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 10:51:42.426503 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1230 10:51:42.429832 [Gating] SW calibration Done
1231 10:51:42.429946 ==
1232 10:51:42.432975 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 10:51:42.436063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 10:51:42.436175 ==
1235 10:51:42.439558 RX Vref Scan: 0
1236 10:51:42.439669
1237 10:51:42.439777 RX Vref 0 -> 0, step: 1
1238 10:51:42.439870
1239 10:51:42.442710 RX Delay -130 -> 252, step: 16
1240 10:51:42.446323 iDelay=222, Bit 0, Center 77 (-34 ~ 189) 224
1241 10:51:42.452763 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1242 10:51:42.456247 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1243 10:51:42.460013 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1244 10:51:42.462719 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1245 10:51:42.465919 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1246 10:51:42.472847 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1247 10:51:42.476003 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1248 10:51:42.479752 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1249 10:51:42.482988 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1250 10:51:42.486155 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 10:51:42.492540 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1252 10:51:42.496161 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1253 10:51:42.499720 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1254 10:51:42.502464 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1255 10:51:42.509202 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1256 10:51:42.509291 ==
1257 10:51:42.512343 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 10:51:42.515917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 10:51:42.516005 ==
1260 10:51:42.516092 DQS Delay:
1261 10:51:42.519113 DQS0 = 0, DQS1 = 0
1262 10:51:42.519194 DQM Delay:
1263 10:51:42.522280 DQM0 = 78, DQM1 = 71
1264 10:51:42.522378 DQ Delay:
1265 10:51:42.525563 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1266 10:51:42.529533 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =101
1267 10:51:42.532732 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1268 10:51:42.535882 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1269 10:51:42.535963
1270 10:51:42.536047
1271 10:51:42.536147 ==
1272 10:51:42.539162 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 10:51:42.542235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 10:51:42.542316 ==
1275 10:51:42.542399
1276 10:51:42.545827
1277 10:51:42.545932 TX Vref Scan disable
1278 10:51:42.548884 == TX Byte 0 ==
1279 10:51:42.552381 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1280 10:51:42.555856 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1281 10:51:42.559457 == TX Byte 1 ==
1282 10:51:42.562108 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1283 10:51:42.565581 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1284 10:51:42.565660 ==
1285 10:51:42.568987 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 10:51:42.575776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 10:51:42.575867 ==
1288 10:51:42.587595 TX Vref=22, minBit 0, minWin=27, winSum=435
1289 10:51:42.590826 TX Vref=24, minBit 0, minWin=27, winSum=437
1290 10:51:42.594531 TX Vref=26, minBit 3, minWin=27, winSum=441
1291 10:51:42.597778 TX Vref=28, minBit 2, minWin=27, winSum=441
1292 10:51:42.600811 TX Vref=30, minBit 1, minWin=27, winSum=445
1293 10:51:42.607069 TX Vref=32, minBit 1, minWin=27, winSum=442
1294 10:51:42.610788 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
1295 10:51:42.610892
1296 10:51:42.613777 Final TX Range 1 Vref 30
1297 10:51:42.613859
1298 10:51:42.613924 ==
1299 10:51:42.617436 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 10:51:42.620469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 10:51:42.623773 ==
1302 10:51:42.623854
1303 10:51:42.623916
1304 10:51:42.623975 TX Vref Scan disable
1305 10:51:42.627481 == TX Byte 0 ==
1306 10:51:42.631012 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1307 10:51:42.637801 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1308 10:51:42.637877 == TX Byte 1 ==
1309 10:51:42.640845 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1310 10:51:42.647686 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1311 10:51:42.647788
1312 10:51:42.647879 [DATLAT]
1313 10:51:42.647967 Freq=800, CH0 RK1
1314 10:51:42.648053
1315 10:51:42.650676 DATLAT Default: 0xa
1316 10:51:42.650780 0, 0xFFFF, sum = 0
1317 10:51:42.653976 1, 0xFFFF, sum = 0
1318 10:51:42.654085 2, 0xFFFF, sum = 0
1319 10:51:42.657554 3, 0xFFFF, sum = 0
1320 10:51:42.660724 4, 0xFFFF, sum = 0
1321 10:51:42.660802 5, 0xFFFF, sum = 0
1322 10:51:42.663938 6, 0xFFFF, sum = 0
1323 10:51:42.664053 7, 0xFFFF, sum = 0
1324 10:51:42.667708 8, 0xFFFF, sum = 0
1325 10:51:42.667814 9, 0x0, sum = 1
1326 10:51:42.670581 10, 0x0, sum = 2
1327 10:51:42.670696 11, 0x0, sum = 3
1328 10:51:42.670797 12, 0x0, sum = 4
1329 10:51:42.674087 best_step = 10
1330 10:51:42.674167
1331 10:51:42.674232 ==
1332 10:51:42.676968 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 10:51:42.680379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 10:51:42.680461 ==
1335 10:51:42.683921 RX Vref Scan: 0
1336 10:51:42.683997
1337 10:51:42.686743 RX Vref 0 -> 0, step: 1
1338 10:51:42.686854
1339 10:51:42.686956 RX Delay -111 -> 252, step: 8
1340 10:51:42.694041 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1341 10:51:42.697945 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1342 10:51:42.701309 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1343 10:51:42.704361 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1344 10:51:42.707364 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1345 10:51:42.714423 iDelay=209, Bit 5, Center 64 (-47 ~ 176) 224
1346 10:51:42.717349 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1347 10:51:42.721052 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1348 10:51:42.724171 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1349 10:51:42.727470 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1350 10:51:42.734372 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1351 10:51:42.737655 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1352 10:51:42.740774 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1353 10:51:42.743976 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1354 10:51:42.750973 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1355 10:51:42.754060 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1356 10:51:42.754140 ==
1357 10:51:42.757185 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 10:51:42.761008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 10:51:42.761084 ==
1360 10:51:42.764034 DQS Delay:
1361 10:51:42.764106 DQS0 = 0, DQS1 = 0
1362 10:51:42.764168 DQM Delay:
1363 10:51:42.767055 DQM0 = 79, DQM1 = 70
1364 10:51:42.767130 DQ Delay:
1365 10:51:42.770820 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =76
1366 10:51:42.773598 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1367 10:51:42.777355 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1368 10:51:42.780540 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1369 10:51:42.780624
1370 10:51:42.780688
1371 10:51:42.790724 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1372 10:51:42.790805 CH0 RK1: MR19=606, MR18=4924
1373 10:51:42.797137 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1374 10:51:42.800139 [RxdqsGatingPostProcess] freq 800
1375 10:51:42.807221 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 10:51:42.810415 Pre-setting of DQS Precalculation
1377 10:51:42.813519 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 10:51:42.813590 ==
1379 10:51:42.817117 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 10:51:42.823509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 10:51:42.823590 ==
1382 10:51:42.826893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 10:51:42.833634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 10:51:42.842573 [CA 0] Center 36 (6~66) winsize 61
1385 10:51:42.846216 [CA 1] Center 36 (6~67) winsize 62
1386 10:51:42.849366 [CA 2] Center 34 (5~64) winsize 60
1387 10:51:42.852524 [CA 3] Center 34 (4~64) winsize 61
1388 10:51:42.856518 [CA 4] Center 34 (4~64) winsize 61
1389 10:51:42.859280 [CA 5] Center 34 (4~64) winsize 61
1390 10:51:42.859378
1391 10:51:42.862483 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1392 10:51:42.862578
1393 10:51:42.866141 [CATrainingPosCal] consider 1 rank data
1394 10:51:42.869376 u2DelayCellTimex100 = 270/100 ps
1395 10:51:42.872361 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1396 10:51:42.879110 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 10:51:42.882515 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1398 10:51:42.885438 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 10:51:42.888931 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 10:51:42.892496 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 10:51:42.892603
1402 10:51:42.895582 CA PerBit enable=1, Macro0, CA PI delay=34
1403 10:51:42.895656
1404 10:51:42.899139 [CBTSetCACLKResult] CA Dly = 34
1405 10:51:42.899241 CS Dly: 5 (0~36)
1406 10:51:42.902452 ==
1407 10:51:42.905403 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 10:51:42.909214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 10:51:42.909336 ==
1410 10:51:42.912295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 10:51:42.918677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 10:51:42.928745 [CA 0] Center 36 (6~66) winsize 61
1413 10:51:42.932308 [CA 1] Center 36 (6~67) winsize 62
1414 10:51:42.935652 [CA 2] Center 34 (4~65) winsize 62
1415 10:51:42.938758 [CA 3] Center 33 (3~64) winsize 62
1416 10:51:42.941982 [CA 4] Center 34 (4~65) winsize 62
1417 10:51:42.945309 [CA 5] Center 33 (3~64) winsize 62
1418 10:51:42.945386
1419 10:51:42.948392 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 10:51:42.948498
1421 10:51:42.952190 [CATrainingPosCal] consider 2 rank data
1422 10:51:42.955407 u2DelayCellTimex100 = 270/100 ps
1423 10:51:42.958656 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1424 10:51:42.965680 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 10:51:42.968616 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1426 10:51:42.971774 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 10:51:42.975401 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 10:51:42.979210 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 10:51:42.979310
1430 10:51:42.982782 CA PerBit enable=1, Macro0, CA PI delay=34
1431 10:51:42.982880
1432 10:51:42.986493 [CBTSetCACLKResult] CA Dly = 34
1433 10:51:42.986603 CS Dly: 6 (0~38)
1434 10:51:42.986699
1435 10:51:42.989946 ----->DramcWriteLeveling(PI) begin...
1436 10:51:42.990050 ==
1437 10:51:42.993038 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 10:51:42.996658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 10:51:42.996762 ==
1440 10:51:43.000079 Write leveling (Byte 0): 27 => 27
1441 10:51:43.003787 Write leveling (Byte 1): 29 => 29
1442 10:51:43.006823 DramcWriteLeveling(PI) end<-----
1443 10:51:43.006910
1444 10:51:43.006978 ==
1445 10:51:43.010415 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 10:51:43.014199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 10:51:43.014286 ==
1448 10:51:43.017325 [Gating] SW mode calibration
1449 10:51:43.024212 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 10:51:43.030814 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 10:51:43.033811 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 10:51:43.040352 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 10:51:43.043821 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:51:43.046962 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:51:43.053834 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:51:43.056943 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:51:43.060136 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:51:43.066885 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:51:43.070067 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:51:43.073830 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:51:43.077379 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:51:43.083472 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:51:43.087013 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:51:43.090147 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:51:43.096892 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:51:43.099854 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:51:43.103449 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:51:43.110199 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1469 10:51:43.113493 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1470 10:51:43.116672 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:51:43.123190 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:51:43.126332 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:51:43.130148 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:51:43.136705 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:51:43.140025 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:51:43.143101 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:51:43.149769 0 9 8 | B1->B0 | 2d2d 2828 | 1 1 | (1 1) (0 0)
1478 10:51:43.153150 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:51:43.156313 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:51:43.163221 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 10:51:43.166291 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 10:51:43.169626 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 10:51:43.176072 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 10:51:43.179917 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1485 10:51:43.183083 0 10 8 | B1->B0 | 2c2c 2c2c | 0 0 | (1 0) (0 0)
1486 10:51:43.189400 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:51:43.192915 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:51:43.196492 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:51:43.202923 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:51:43.206382 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:51:43.210152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:51:43.216413 0 11 4 | B1->B0 | 2929 2424 | 1 0 | (0 0) (1 1)
1493 10:51:43.219524 0 11 8 | B1->B0 | 3c3c 3c3c | 0 1 | (0 0) (0 0)
1494 10:51:43.222823 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:51:43.229365 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:51:43.232619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 10:51:43.236396 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 10:51:43.239331 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 10:51:43.246325 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 10:51:43.249673 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 10:51:43.252986 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 10:51:43.259371 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1503 10:51:43.262572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:51:43.265901 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:51:43.272714 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:51:43.275764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:51:43.279444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:51:43.285764 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:51:43.288872 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:51:43.292543 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:51:43.299260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:51:43.302588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:51:43.305451 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:51:43.312442 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:51:43.315456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:51:43.318925 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:51:43.325455 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 10:51:43.329057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 10:51:43.332110 Total UI for P1: 0, mck2ui 16
1520 10:51:43.335467 best dqsien dly found for B0: ( 0, 14, 8)
1521 10:51:43.338816 Total UI for P1: 0, mck2ui 16
1522 10:51:43.342457 best dqsien dly found for B1: ( 0, 14, 8)
1523 10:51:43.345452 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1524 10:51:43.348585 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1525 10:51:43.348670
1526 10:51:43.352013 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 10:51:43.355587 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 10:51:43.358688 [Gating] SW calibration Done
1529 10:51:43.358779 ==
1530 10:51:43.362082 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 10:51:43.365190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 10:51:43.368484 ==
1533 10:51:43.368569 RX Vref Scan: 0
1534 10:51:43.368637
1535 10:51:43.372441 RX Vref 0 -> 0, step: 1
1536 10:51:43.372526
1537 10:51:43.375408 RX Delay -130 -> 252, step: 16
1538 10:51:43.378581 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1539 10:51:43.381727 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1540 10:51:43.385357 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1541 10:51:43.388545 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1542 10:51:43.395259 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1543 10:51:43.398408 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1544 10:51:43.401836 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1545 10:51:43.405293 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1546 10:51:43.408468 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1547 10:51:43.415065 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1548 10:51:43.418498 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1549 10:51:43.421717 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1550 10:51:43.424853 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1551 10:51:43.428639 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1552 10:51:43.434838 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1553 10:51:43.437876 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1554 10:51:43.437964 ==
1555 10:51:43.441515 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 10:51:43.445195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 10:51:43.445299 ==
1558 10:51:43.448097 DQS Delay:
1559 10:51:43.448200 DQS0 = 0, DQS1 = 0
1560 10:51:43.448294 DQM Delay:
1561 10:51:43.451431 DQM0 = 81, DQM1 = 73
1562 10:51:43.451513 DQ Delay:
1563 10:51:43.454963 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1564 10:51:43.458155 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1565 10:51:43.461171 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1566 10:51:43.464768 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1567 10:51:43.464854
1568 10:51:43.464920
1569 10:51:43.464982 ==
1570 10:51:43.467762 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 10:51:43.474790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 10:51:43.474884 ==
1573 10:51:43.474951
1574 10:51:43.475014
1575 10:51:43.475073 TX Vref Scan disable
1576 10:51:43.478528 == TX Byte 0 ==
1577 10:51:43.481763 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1578 10:51:43.485115 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1579 10:51:43.488823 == TX Byte 1 ==
1580 10:51:43.491665 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1581 10:51:43.497931 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1582 10:51:43.498017 ==
1583 10:51:43.501661 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 10:51:43.504832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 10:51:43.504940 ==
1586 10:51:43.517783 TX Vref=22, minBit 10, minWin=26, winSum=445
1587 10:51:43.520742 TX Vref=24, minBit 8, minWin=27, winSum=447
1588 10:51:43.524155 TX Vref=26, minBit 11, minWin=27, winSum=457
1589 10:51:43.527124 TX Vref=28, minBit 1, minWin=28, winSum=458
1590 10:51:43.530571 TX Vref=30, minBit 8, minWin=28, winSum=458
1591 10:51:43.538014 TX Vref=32, minBit 9, minWin=27, winSum=455
1592 10:51:43.541028 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
1593 10:51:43.541108
1594 10:51:43.543992 Final TX Range 1 Vref 28
1595 10:51:43.544084
1596 10:51:43.544150 ==
1597 10:51:43.547520 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 10:51:43.551284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 10:51:43.551363 ==
1600 10:51:43.551427
1601 10:51:43.554900
1602 10:51:43.555018 TX Vref Scan disable
1603 10:51:43.558109 == TX Byte 0 ==
1604 10:51:43.561454 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 10:51:43.564469 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 10:51:43.567986 == TX Byte 1 ==
1607 10:51:43.571027 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 10:51:43.574054 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 10:51:43.577761
1610 10:51:43.577869 [DATLAT]
1611 10:51:43.577967 Freq=800, CH1 RK0
1612 10:51:43.578060
1613 10:51:43.580915 DATLAT Default: 0xa
1614 10:51:43.581000 0, 0xFFFF, sum = 0
1615 10:51:43.584111 1, 0xFFFF, sum = 0
1616 10:51:43.584187 2, 0xFFFF, sum = 0
1617 10:51:43.587784 3, 0xFFFF, sum = 0
1618 10:51:43.587861 4, 0xFFFF, sum = 0
1619 10:51:43.590756 5, 0xFFFF, sum = 0
1620 10:51:43.594033 6, 0xFFFF, sum = 0
1621 10:51:43.594107 7, 0xFFFF, sum = 0
1622 10:51:43.597198 8, 0xFFFF, sum = 0
1623 10:51:43.597280 9, 0x0, sum = 1
1624 10:51:43.597348 10, 0x0, sum = 2
1625 10:51:43.600935 11, 0x0, sum = 3
1626 10:51:43.601011 12, 0x0, sum = 4
1627 10:51:43.604095 best_step = 10
1628 10:51:43.604175
1629 10:51:43.604241 ==
1630 10:51:43.607457 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 10:51:43.610485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 10:51:43.610571 ==
1633 10:51:43.614606 RX Vref Scan: 1
1634 10:51:43.614693
1635 10:51:43.617782 Set Vref Range= 32 -> 127
1636 10:51:43.617882
1637 10:51:43.617950 RX Vref 32 -> 127, step: 1
1638 10:51:43.618015
1639 10:51:43.620463 RX Delay -111 -> 252, step: 8
1640 10:51:43.620548
1641 10:51:43.624223 Set Vref, RX VrefLevel [Byte0]: 32
1642 10:51:43.627217 [Byte1]: 32
1643 10:51:43.630733
1644 10:51:43.630819 Set Vref, RX VrefLevel [Byte0]: 33
1645 10:51:43.633734 [Byte1]: 33
1646 10:51:43.637757
1647 10:51:43.637842 Set Vref, RX VrefLevel [Byte0]: 34
1648 10:51:43.641046 [Byte1]: 34
1649 10:51:43.645982
1650 10:51:43.646068 Set Vref, RX VrefLevel [Byte0]: 35
1651 10:51:43.649023 [Byte1]: 35
1652 10:51:43.653578
1653 10:51:43.653662 Set Vref, RX VrefLevel [Byte0]: 36
1654 10:51:43.656916 [Byte1]: 36
1655 10:51:43.660814
1656 10:51:43.660897 Set Vref, RX VrefLevel [Byte0]: 37
1657 10:51:43.664365 [Byte1]: 37
1658 10:51:43.668954
1659 10:51:43.669033 Set Vref, RX VrefLevel [Byte0]: 38
1660 10:51:43.671917 [Byte1]: 38
1661 10:51:43.675991
1662 10:51:43.676103 Set Vref, RX VrefLevel [Byte0]: 39
1663 10:51:43.679808 [Byte1]: 39
1664 10:51:43.684039
1665 10:51:43.684150 Set Vref, RX VrefLevel [Byte0]: 40
1666 10:51:43.687234 [Byte1]: 40
1667 10:51:43.691586
1668 10:51:43.691670 Set Vref, RX VrefLevel [Byte0]: 41
1669 10:51:43.694578 [Byte1]: 41
1670 10:51:43.698947
1671 10:51:43.699031 Set Vref, RX VrefLevel [Byte0]: 42
1672 10:51:43.702550 [Byte1]: 42
1673 10:51:43.706947
1674 10:51:43.707031 Set Vref, RX VrefLevel [Byte0]: 43
1675 10:51:43.710091 [Byte1]: 43
1676 10:51:43.714567
1677 10:51:43.714719 Set Vref, RX VrefLevel [Byte0]: 44
1678 10:51:43.717635 [Byte1]: 44
1679 10:51:43.721978
1680 10:51:43.722098 Set Vref, RX VrefLevel [Byte0]: 45
1681 10:51:43.725746 [Byte1]: 45
1682 10:51:43.730180
1683 10:51:43.730289 Set Vref, RX VrefLevel [Byte0]: 46
1684 10:51:43.733084 [Byte1]: 46
1685 10:51:43.737224
1686 10:51:43.737332 Set Vref, RX VrefLevel [Byte0]: 47
1687 10:51:43.740720 [Byte1]: 47
1688 10:51:43.745046
1689 10:51:43.745138 Set Vref, RX VrefLevel [Byte0]: 48
1690 10:51:43.748558 [Byte1]: 48
1691 10:51:43.752950
1692 10:51:43.753055 Set Vref, RX VrefLevel [Byte0]: 49
1693 10:51:43.756145 [Byte1]: 49
1694 10:51:43.760396
1695 10:51:43.760472 Set Vref, RX VrefLevel [Byte0]: 50
1696 10:51:43.763555 [Byte1]: 50
1697 10:51:43.767949
1698 10:51:43.768029 Set Vref, RX VrefLevel [Byte0]: 51
1699 10:51:43.771188 [Byte1]: 51
1700 10:51:43.775909
1701 10:51:43.775989 Set Vref, RX VrefLevel [Byte0]: 52
1702 10:51:43.779192 [Byte1]: 52
1703 10:51:43.783376
1704 10:51:43.783479 Set Vref, RX VrefLevel [Byte0]: 53
1705 10:51:43.786808 [Byte1]: 53
1706 10:51:43.791206
1707 10:51:43.791311 Set Vref, RX VrefLevel [Byte0]: 54
1708 10:51:43.794333 [Byte1]: 54
1709 10:51:43.798449
1710 10:51:43.798552 Set Vref, RX VrefLevel [Byte0]: 55
1711 10:51:43.802293 [Byte1]: 55
1712 10:51:43.806100
1713 10:51:43.806200 Set Vref, RX VrefLevel [Byte0]: 56
1714 10:51:43.809876 [Byte1]: 56
1715 10:51:43.813716
1716 10:51:43.813825 Set Vref, RX VrefLevel [Byte0]: 57
1717 10:51:43.816991 [Byte1]: 57
1718 10:51:43.821507
1719 10:51:43.821612 Set Vref, RX VrefLevel [Byte0]: 58
1720 10:51:43.824622 [Byte1]: 58
1721 10:51:43.829036
1722 10:51:43.829141 Set Vref, RX VrefLevel [Byte0]: 59
1723 10:51:43.832804 [Byte1]: 59
1724 10:51:43.836628
1725 10:51:43.836741 Set Vref, RX VrefLevel [Byte0]: 60
1726 10:51:43.840304 [Byte1]: 60
1727 10:51:43.844312
1728 10:51:43.844421 Set Vref, RX VrefLevel [Byte0]: 61
1729 10:51:43.847975 [Byte1]: 61
1730 10:51:43.852425
1731 10:51:43.852539 Set Vref, RX VrefLevel [Byte0]: 62
1732 10:51:43.855487 [Byte1]: 62
1733 10:51:43.859950
1734 10:51:43.860029 Set Vref, RX VrefLevel [Byte0]: 63
1735 10:51:43.863105 [Byte1]: 63
1736 10:51:43.867702
1737 10:51:43.867811 Set Vref, RX VrefLevel [Byte0]: 64
1738 10:51:43.870948 [Byte1]: 64
1739 10:51:43.875545
1740 10:51:43.875631 Set Vref, RX VrefLevel [Byte0]: 65
1741 10:51:43.878214 [Byte1]: 65
1742 10:51:43.882787
1743 10:51:43.882886 Set Vref, RX VrefLevel [Byte0]: 66
1744 10:51:43.886220 [Byte1]: 66
1745 10:51:43.890243
1746 10:51:43.890358 Set Vref, RX VrefLevel [Byte0]: 67
1747 10:51:43.893936 [Byte1]: 67
1748 10:51:43.897869
1749 10:51:43.897956 Set Vref, RX VrefLevel [Byte0]: 68
1750 10:51:43.901829 [Byte1]: 68
1751 10:51:43.905780
1752 10:51:43.905866 Set Vref, RX VrefLevel [Byte0]: 69
1753 10:51:43.908887 [Byte1]: 69
1754 10:51:43.913320
1755 10:51:43.913407 Set Vref, RX VrefLevel [Byte0]: 70
1756 10:51:43.916610 [Byte1]: 70
1757 10:51:43.921057
1758 10:51:43.921142 Set Vref, RX VrefLevel [Byte0]: 71
1759 10:51:43.924471 [Byte1]: 71
1760 10:51:43.928481
1761 10:51:43.928562 Set Vref, RX VrefLevel [Byte0]: 72
1762 10:51:43.931868 [Byte1]: 72
1763 10:51:43.936054
1764 10:51:43.936135 Set Vref, RX VrefLevel [Byte0]: 73
1765 10:51:43.939889 [Byte1]: 73
1766 10:51:43.943880
1767 10:51:43.943971 Set Vref, RX VrefLevel [Byte0]: 74
1768 10:51:43.947479 [Byte1]: 74
1769 10:51:43.951569
1770 10:51:43.951681 Set Vref, RX VrefLevel [Byte0]: 75
1771 10:51:43.954835 [Byte1]: 75
1772 10:51:43.959418
1773 10:51:43.959506 Set Vref, RX VrefLevel [Byte0]: 76
1774 10:51:43.962302 [Byte1]: 76
1775 10:51:43.966710
1776 10:51:43.966837 Set Vref, RX VrefLevel [Byte0]: 77
1777 10:51:43.969842 [Byte1]: 77
1778 10:51:43.974790
1779 10:51:43.974901 Final RX Vref Byte 0 = 54 to rank0
1780 10:51:43.977561 Final RX Vref Byte 1 = 55 to rank0
1781 10:51:43.980819 Final RX Vref Byte 0 = 54 to rank1
1782 10:51:43.984348 Final RX Vref Byte 1 = 55 to rank1==
1783 10:51:43.988048 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 10:51:43.994004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 10:51:43.994109 ==
1786 10:51:43.994176 DQS Delay:
1787 10:51:43.997535 DQS0 = 0, DQS1 = 0
1788 10:51:43.997616 DQM Delay:
1789 10:51:43.997689 DQM0 = 80, DQM1 = 71
1790 10:51:44.000981 DQ Delay:
1791 10:51:44.004241 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1792 10:51:44.007436 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1793 10:51:44.010746 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1794 10:51:44.013773 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1795 10:51:44.013861
1796 10:51:44.013932
1797 10:51:44.020736 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1798 10:51:44.023972 CH1 RK0: MR19=606, MR18=D17
1799 10:51:44.030862 CH1_RK0: MR19=0x606, MR18=0xD17, DQSOSC=404, MR23=63, INC=90, DEC=60
1800 10:51:44.030949
1801 10:51:44.034108 ----->DramcWriteLeveling(PI) begin...
1802 10:51:44.034194 ==
1803 10:51:44.037341 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 10:51:44.040449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 10:51:44.040535 ==
1806 10:51:44.043712 Write leveling (Byte 0): 28 => 28
1807 10:51:44.046832 Write leveling (Byte 1): 29 => 29
1808 10:51:44.050326 DramcWriteLeveling(PI) end<-----
1809 10:51:44.050440
1810 10:51:44.050534 ==
1811 10:51:44.053857 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 10:51:44.056799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 10:51:44.056891 ==
1814 10:51:44.060379 [Gating] SW mode calibration
1815 10:51:44.066656 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 10:51:44.073814 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 10:51:44.076977 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 10:51:44.083310 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1819 10:51:44.086597 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1820 10:51:44.089742 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:51:44.096546 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:51:44.099526 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:51:44.102918 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:51:44.109873 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:51:44.112801 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:51:44.115891 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:51:44.122739 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:51:44.125949 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:51:44.129241 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:51:44.135705 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:51:44.139437 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:51:44.142607 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:51:44.149522 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:51:44.152733 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1835 10:51:44.155764 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1836 10:51:44.162750 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:51:44.165950 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:51:44.169579 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:51:44.175966 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 10:51:44.179068 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:51:44.182650 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:51:44.189220 0 9 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1843 10:51:44.192264 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1844 10:51:44.195537 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 10:51:44.202283 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 10:51:44.205566 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 10:51:44.209021 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 10:51:44.212507 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 10:51:44.218588 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 10:51:44.222063 0 10 4 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (0 0)
1851 10:51:44.225753 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 10:51:44.231997 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 10:51:44.235891 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:51:44.239163 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 10:51:44.245398 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 10:51:44.248531 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 10:51:44.251772 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:51:44.258623 0 11 4 | B1->B0 | 2e2e 3737 | 0 0 | (1 1) (1 1)
1859 10:51:44.262335 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1860 10:51:44.265453 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 10:51:44.272020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 10:51:44.275658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 10:51:44.278516 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 10:51:44.285519 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 10:51:44.288578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 10:51:44.292038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 10:51:44.298379 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:51:44.301618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:51:44.305216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:51:44.311556 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:51:44.315085 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:51:44.318177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:51:44.324491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:51:44.327972 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:51:44.331570 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:51:44.337854 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:51:44.341014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:51:44.344866 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:51:44.351220 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 10:51:44.354433 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 10:51:44.357571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 10:51:44.364838 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1883 10:51:44.368013 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 10:51:44.371109 Total UI for P1: 0, mck2ui 16
1885 10:51:44.374608 best dqsien dly found for B0: ( 0, 14, 4)
1886 10:51:44.378186 Total UI for P1: 0, mck2ui 16
1887 10:51:44.380824 best dqsien dly found for B1: ( 0, 14, 4)
1888 10:51:44.384173 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1889 10:51:44.387831 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1890 10:51:44.387921
1891 10:51:44.390961 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1892 10:51:44.394700 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 10:51:44.397439 [Gating] SW calibration Done
1894 10:51:44.397542 ==
1895 10:51:44.400632 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 10:51:44.404502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 10:51:44.404610 ==
1898 10:51:44.407614 RX Vref Scan: 0
1899 10:51:44.407726
1900 10:51:44.410612 RX Vref 0 -> 0, step: 1
1901 10:51:44.410719
1902 10:51:44.410821 RX Delay -130 -> 252, step: 16
1903 10:51:44.417773 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1904 10:51:44.420814 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1905 10:51:44.424219 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1906 10:51:44.427968 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1907 10:51:44.430590 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1908 10:51:44.437482 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1909 10:51:44.440583 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1910 10:51:44.443800 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1911 10:51:44.447852 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1912 10:51:44.450669 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1913 10:51:44.457315 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1914 10:51:44.460826 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1915 10:51:44.464006 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1916 10:51:44.466941 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1917 10:51:44.473734 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1918 10:51:44.476915 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1919 10:51:44.477056 ==
1920 10:51:44.480641 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 10:51:44.483635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 10:51:44.483767 ==
1923 10:51:44.487138 DQS Delay:
1924 10:51:44.487275 DQS0 = 0, DQS1 = 0
1925 10:51:44.487397 DQM Delay:
1926 10:51:44.490298 DQM0 = 79, DQM1 = 72
1927 10:51:44.490428 DQ Delay:
1928 10:51:44.493521 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1929 10:51:44.496990 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1930 10:51:44.500675 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1931 10:51:44.503588 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1932 10:51:44.503723
1933 10:51:44.503843
1934 10:51:44.503962 ==
1935 10:51:44.507324 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 10:51:44.513454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 10:51:44.513596 ==
1938 10:51:44.513725
1939 10:51:44.513848
1940 10:51:44.513970 TX Vref Scan disable
1941 10:51:44.516750 == TX Byte 0 ==
1942 10:51:44.520302 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1943 10:51:44.523944 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1944 10:51:44.526994 == TX Byte 1 ==
1945 10:51:44.530294 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1946 10:51:44.537263 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1947 10:51:44.537353 ==
1948 10:51:44.539948 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 10:51:44.543459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 10:51:44.543547 ==
1951 10:51:44.556033 TX Vref=22, minBit 9, minWin=27, winSum=452
1952 10:51:44.559143 TX Vref=24, minBit 9, minWin=27, winSum=452
1953 10:51:44.562342 TX Vref=26, minBit 3, minWin=28, winSum=456
1954 10:51:44.565531 TX Vref=28, minBit 3, minWin=28, winSum=459
1955 10:51:44.568810 TX Vref=30, minBit 2, minWin=28, winSum=459
1956 10:51:44.575789 TX Vref=32, minBit 8, minWin=28, winSum=461
1957 10:51:44.578915 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 32
1958 10:51:44.579005
1959 10:51:44.582124 Final TX Range 1 Vref 32
1960 10:51:44.582214
1961 10:51:44.582285 ==
1962 10:51:44.585875 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 10:51:44.588808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 10:51:44.591893 ==
1965 10:51:44.591985
1966 10:51:44.592061
1967 10:51:44.592128 TX Vref Scan disable
1968 10:51:44.595903 == TX Byte 0 ==
1969 10:51:44.598718 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 10:51:44.606211 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 10:51:44.606299 == TX Byte 1 ==
1972 10:51:44.608925 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1973 10:51:44.615657 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1974 10:51:44.615746
1975 10:51:44.615814 [DATLAT]
1976 10:51:44.615876 Freq=800, CH1 RK1
1977 10:51:44.615936
1978 10:51:44.618796 DATLAT Default: 0xa
1979 10:51:44.618888 0, 0xFFFF, sum = 0
1980 10:51:44.621954 1, 0xFFFF, sum = 0
1981 10:51:44.625894 2, 0xFFFF, sum = 0
1982 10:51:44.626010 3, 0xFFFF, sum = 0
1983 10:51:44.628793 4, 0xFFFF, sum = 0
1984 10:51:44.628871 5, 0xFFFF, sum = 0
1985 10:51:44.632494 6, 0xFFFF, sum = 0
1986 10:51:44.632572 7, 0xFFFF, sum = 0
1987 10:51:44.635235 8, 0xFFFF, sum = 0
1988 10:51:44.635309 9, 0x0, sum = 1
1989 10:51:44.638715 10, 0x0, sum = 2
1990 10:51:44.638823 11, 0x0, sum = 3
1991 10:51:44.638899 12, 0x0, sum = 4
1992 10:51:44.642360 best_step = 10
1993 10:51:44.642447
1994 10:51:44.642519 ==
1995 10:51:44.645306 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 10:51:44.648416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 10:51:44.648525 ==
1998 10:51:44.652199 RX Vref Scan: 0
1999 10:51:44.652285
2000 10:51:44.655432 RX Vref 0 -> 0, step: 1
2001 10:51:44.655512
2002 10:51:44.655578 RX Delay -111 -> 252, step: 8
2003 10:51:44.662572 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2004 10:51:44.665743 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2005 10:51:44.669013 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2006 10:51:44.672808 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2007 10:51:44.676113 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2008 10:51:44.682488 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2009 10:51:44.685734 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2010 10:51:44.688779 iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240
2011 10:51:44.692543 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2012 10:51:44.695568 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2013 10:51:44.702605 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2014 10:51:44.705551 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2015 10:51:44.708965 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2016 10:51:44.712087 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2017 10:51:44.718658 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2018 10:51:44.722336 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2019 10:51:44.722453 ==
2020 10:51:44.725379 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 10:51:44.728572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 10:51:44.728687 ==
2023 10:51:44.732560 DQS Delay:
2024 10:51:44.732669 DQS0 = 0, DQS1 = 0
2025 10:51:44.732782 DQM Delay:
2026 10:51:44.735212 DQM0 = 77, DQM1 = 72
2027 10:51:44.735304 DQ Delay:
2028 10:51:44.738820 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2029 10:51:44.741848 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =72
2030 10:51:44.745207 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
2031 10:51:44.748753 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
2032 10:51:44.748850
2033 10:51:44.748921
2034 10:51:44.758242 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c34, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2035 10:51:44.758349 CH1 RK1: MR19=606, MR18=1C34
2036 10:51:44.765017 CH1_RK1: MR19=0x606, MR18=0x1C34, DQSOSC=396, MR23=63, INC=94, DEC=62
2037 10:51:44.768322 [RxdqsGatingPostProcess] freq 800
2038 10:51:44.775239 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 10:51:44.778454 Pre-setting of DQS Precalculation
2040 10:51:44.781467 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 10:51:44.791726 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 10:51:44.798376 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 10:51:44.798498
2044 10:51:44.798594
2045 10:51:44.801310 [Calibration Summary] 1600 Mbps
2046 10:51:44.801416 CH 0, Rank 0
2047 10:51:44.804889 SW Impedance : PASS
2048 10:51:44.804969 DUTY Scan : NO K
2049 10:51:44.807878 ZQ Calibration : PASS
2050 10:51:44.811307 Jitter Meter : NO K
2051 10:51:44.811396 CBT Training : PASS
2052 10:51:44.814806 Write leveling : PASS
2053 10:51:44.818006 RX DQS gating : PASS
2054 10:51:44.818115 RX DQ/DQS(RDDQC) : PASS
2055 10:51:44.821537 TX DQ/DQS : PASS
2056 10:51:44.824440 RX DATLAT : PASS
2057 10:51:44.824556 RX DQ/DQS(Engine): PASS
2058 10:51:44.828162 TX OE : NO K
2059 10:51:44.828262 All Pass.
2060 10:51:44.828353
2061 10:51:44.831315 CH 0, Rank 1
2062 10:51:44.831386 SW Impedance : PASS
2063 10:51:44.834591 DUTY Scan : NO K
2064 10:51:44.834688 ZQ Calibration : PASS
2065 10:51:44.838160 Jitter Meter : NO K
2066 10:51:44.841329 CBT Training : PASS
2067 10:51:44.841443 Write leveling : PASS
2068 10:51:44.845014 RX DQS gating : PASS
2069 10:51:44.847918 RX DQ/DQS(RDDQC) : PASS
2070 10:51:44.848004 TX DQ/DQS : PASS
2071 10:51:44.850925 RX DATLAT : PASS
2072 10:51:44.854579 RX DQ/DQS(Engine): PASS
2073 10:51:44.854661 TX OE : NO K
2074 10:51:44.857602 All Pass.
2075 10:51:44.857688
2076 10:51:44.857755 CH 1, Rank 0
2077 10:51:44.860947 SW Impedance : PASS
2078 10:51:44.861034 DUTY Scan : NO K
2079 10:51:44.864054 ZQ Calibration : PASS
2080 10:51:44.867837 Jitter Meter : NO K
2081 10:51:44.867913 CBT Training : PASS
2082 10:51:44.871334 Write leveling : PASS
2083 10:51:44.874214 RX DQS gating : PASS
2084 10:51:44.874316 RX DQ/DQS(RDDQC) : PASS
2085 10:51:44.877395 TX DQ/DQS : PASS
2086 10:51:44.881278 RX DATLAT : PASS
2087 10:51:44.881389 RX DQ/DQS(Engine): PASS
2088 10:51:44.884271 TX OE : NO K
2089 10:51:44.884373 All Pass.
2090 10:51:44.884473
2091 10:51:44.887890 CH 1, Rank 1
2092 10:51:44.887970 SW Impedance : PASS
2093 10:51:44.890950 DUTY Scan : NO K
2094 10:51:44.891053 ZQ Calibration : PASS
2095 10:51:44.894136 Jitter Meter : NO K
2096 10:51:44.897330 CBT Training : PASS
2097 10:51:44.897431 Write leveling : PASS
2098 10:51:44.901049 RX DQS gating : PASS
2099 10:51:44.904214 RX DQ/DQS(RDDQC) : PASS
2100 10:51:44.904319 TX DQ/DQS : PASS
2101 10:51:44.907330 RX DATLAT : PASS
2102 10:51:44.910768 RX DQ/DQS(Engine): PASS
2103 10:51:44.910870 TX OE : NO K
2104 10:51:44.913813 All Pass.
2105 10:51:44.913889
2106 10:51:44.913951 DramC Write-DBI off
2107 10:51:44.917322 PER_BANK_REFRESH: Hybrid Mode
2108 10:51:44.920881 TX_TRACKING: ON
2109 10:51:44.923741 [GetDramInforAfterCalByMRR] Vendor 6.
2110 10:51:44.927523 [GetDramInforAfterCalByMRR] Revision 606.
2111 10:51:44.930514 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 10:51:44.930632 MR0 0x3b3b
2113 10:51:44.930737 MR8 0x5151
2114 10:51:44.934193 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 10:51:44.937374
2116 10:51:44.937459 MR0 0x3b3b
2117 10:51:44.937526 MR8 0x5151
2118 10:51:44.940550 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 10:51:44.940634
2120 10:51:44.950581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 10:51:44.953519 [FAST_K] Save calibration result to emmc
2122 10:51:44.957010 [FAST_K] Save calibration result to emmc
2123 10:51:44.960976 dram_init: config_dvfs: 1
2124 10:51:44.963709 dramc_set_vcore_voltage set vcore to 662500
2125 10:51:44.967080 Read voltage for 1200, 2
2126 10:51:44.967182 Vio18 = 0
2127 10:51:44.967252 Vcore = 662500
2128 10:51:44.970226 Vdram = 0
2129 10:51:44.970308 Vddq = 0
2130 10:51:44.970372 Vmddr = 0
2131 10:51:44.977192 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 10:51:44.980798 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 10:51:44.983893 MEM_TYPE=3, freq_sel=15
2134 10:51:44.987235 sv_algorithm_assistance_LP4_1600
2135 10:51:44.990226 ============ PULL DRAM RESETB DOWN ============
2136 10:51:44.993857 ========== PULL DRAM RESETB DOWN end =========
2137 10:51:45.000288 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 10:51:45.003833 ===================================
2139 10:51:45.007112 LPDDR4 DRAM CONFIGURATION
2140 10:51:45.007198 ===================================
2141 10:51:45.010238 EX_ROW_EN[0] = 0x0
2142 10:51:45.013949 EX_ROW_EN[1] = 0x0
2143 10:51:45.014047 LP4Y_EN = 0x0
2144 10:51:45.016928 WORK_FSP = 0x0
2145 10:51:45.017019 WL = 0x4
2146 10:51:45.020307 RL = 0x4
2147 10:51:45.020401 BL = 0x2
2148 10:51:45.023986 RPST = 0x0
2149 10:51:45.024082 RD_PRE = 0x0
2150 10:51:45.026672 WR_PRE = 0x1
2151 10:51:45.026787 WR_PST = 0x0
2152 10:51:45.030039 DBI_WR = 0x0
2153 10:51:45.030129 DBI_RD = 0x0
2154 10:51:45.033664 OTF = 0x1
2155 10:51:45.036417 ===================================
2156 10:51:45.039924 ===================================
2157 10:51:45.040024 ANA top config
2158 10:51:45.043053 ===================================
2159 10:51:45.047245 DLL_ASYNC_EN = 0
2160 10:51:45.049537 ALL_SLAVE_EN = 0
2161 10:51:45.052771 NEW_RANK_MODE = 1
2162 10:51:45.056412 DLL_IDLE_MODE = 1
2163 10:51:45.056566 LP45_APHY_COMB_EN = 1
2164 10:51:45.059450 TX_ODT_DIS = 1
2165 10:51:45.062929 NEW_8X_MODE = 1
2166 10:51:45.066481 ===================================
2167 10:51:45.069558 ===================================
2168 10:51:45.073086 data_rate = 2400
2169 10:51:45.076205 CKR = 1
2170 10:51:45.076317 DQ_P2S_RATIO = 8
2171 10:51:45.079463 ===================================
2172 10:51:45.083006 CA_P2S_RATIO = 8
2173 10:51:45.086197 DQ_CA_OPEN = 0
2174 10:51:45.089648 DQ_SEMI_OPEN = 0
2175 10:51:45.092640 CA_SEMI_OPEN = 0
2176 10:51:45.096222 CA_FULL_RATE = 0
2177 10:51:45.096319 DQ_CKDIV4_EN = 0
2178 10:51:45.099321 CA_CKDIV4_EN = 0
2179 10:51:45.102555 CA_PREDIV_EN = 0
2180 10:51:45.106176 PH8_DLY = 17
2181 10:51:45.109530 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 10:51:45.112646 DQ_AAMCK_DIV = 4
2183 10:51:45.115803 CA_AAMCK_DIV = 4
2184 10:51:45.115883 CA_ADMCK_DIV = 4
2185 10:51:45.119202 DQ_TRACK_CA_EN = 0
2186 10:51:45.122695 CA_PICK = 1200
2187 10:51:45.125593 CA_MCKIO = 1200
2188 10:51:45.129160 MCKIO_SEMI = 0
2189 10:51:45.131989 PLL_FREQ = 2366
2190 10:51:45.135564 DQ_UI_PI_RATIO = 32
2191 10:51:45.135667 CA_UI_PI_RATIO = 0
2192 10:51:45.138972 ===================================
2193 10:51:45.141997 ===================================
2194 10:51:45.145648 memory_type:LPDDR4
2195 10:51:45.149089 GP_NUM : 10
2196 10:51:45.149199 SRAM_EN : 1
2197 10:51:45.151842 MD32_EN : 0
2198 10:51:45.155851 ===================================
2199 10:51:45.159021 [ANA_INIT] >>>>>>>>>>>>>>
2200 10:51:45.162075 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 10:51:45.165531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 10:51:45.168689 ===================================
2203 10:51:45.168796 data_rate = 2400,PCW = 0X5b00
2204 10:51:45.172071 ===================================
2205 10:51:45.178602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 10:51:45.181960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 10:51:45.188208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 10:51:45.191884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 10:51:45.194980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 10:51:45.198779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 10:51:45.201799 [ANA_INIT] flow start
2212 10:51:45.205039 [ANA_INIT] PLL >>>>>>>>
2213 10:51:45.205132 [ANA_INIT] PLL <<<<<<<<
2214 10:51:45.208620 [ANA_INIT] MIDPI >>>>>>>>
2215 10:51:45.211994 [ANA_INIT] MIDPI <<<<<<<<
2216 10:51:45.212081 [ANA_INIT] DLL >>>>>>>>
2217 10:51:45.215173 [ANA_INIT] DLL <<<<<<<<
2218 10:51:45.218393 [ANA_INIT] flow end
2219 10:51:45.221566 ============ LP4 DIFF to SE enter ============
2220 10:51:45.224884 ============ LP4 DIFF to SE exit ============
2221 10:51:45.227913 [ANA_INIT] <<<<<<<<<<<<<
2222 10:51:45.231528 [Flow] Enable top DCM control >>>>>
2223 10:51:45.234845 [Flow] Enable top DCM control <<<<<
2224 10:51:45.238139 Enable DLL master slave shuffle
2225 10:51:45.241274 ==============================================================
2226 10:51:45.244597 Gating Mode config
2227 10:51:45.251681 ==============================================================
2228 10:51:45.251790 Config description:
2229 10:51:45.260821 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 10:51:45.267798 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 10:51:45.274410 SELPH_MODE 0: By rank 1: By Phase
2232 10:51:45.278042 ==============================================================
2233 10:51:45.281003 GAT_TRACK_EN = 1
2234 10:51:45.284567 RX_GATING_MODE = 2
2235 10:51:45.287683 RX_GATING_TRACK_MODE = 2
2236 10:51:45.291260 SELPH_MODE = 1
2237 10:51:45.294554 PICG_EARLY_EN = 1
2238 10:51:45.297772 VALID_LAT_VALUE = 1
2239 10:51:45.300807 ==============================================================
2240 10:51:45.304396 Enter into Gating configuration >>>>
2241 10:51:45.307658 Exit from Gating configuration <<<<
2242 10:51:45.310722 Enter into DVFS_PRE_config >>>>>
2243 10:51:45.324160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 10:51:45.327362 Exit from DVFS_PRE_config <<<<<
2245 10:51:45.330473 Enter into PICG configuration >>>>
2246 10:51:45.330572 Exit from PICG configuration <<<<
2247 10:51:45.334153 [RX_INPUT] configuration >>>>>
2248 10:51:45.337118 [RX_INPUT] configuration <<<<<
2249 10:51:45.344149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 10:51:45.347213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 10:51:45.353529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 10:51:45.360626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 10:51:45.366782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 10:51:45.373646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 10:51:45.376781 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 10:51:45.380382 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 10:51:45.386816 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 10:51:45.390319 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 10:51:45.393806 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 10:51:45.396944 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 10:51:45.400173 ===================================
2262 10:51:45.403953 LPDDR4 DRAM CONFIGURATION
2263 10:51:45.407073 ===================================
2264 10:51:45.410039 EX_ROW_EN[0] = 0x0
2265 10:51:45.410148 EX_ROW_EN[1] = 0x0
2266 10:51:45.413339 LP4Y_EN = 0x0
2267 10:51:45.413446 WORK_FSP = 0x0
2268 10:51:45.417048 WL = 0x4
2269 10:51:45.417158 RL = 0x4
2270 10:51:45.420311 BL = 0x2
2271 10:51:45.420423 RPST = 0x0
2272 10:51:45.423502 RD_PRE = 0x0
2273 10:51:45.423586 WR_PRE = 0x1
2274 10:51:45.426602 WR_PST = 0x0
2275 10:51:45.426717 DBI_WR = 0x0
2276 10:51:45.430456 DBI_RD = 0x0
2277 10:51:45.430567 OTF = 0x1
2278 10:51:45.433894 ===================================
2279 10:51:45.440070 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 10:51:45.443444 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 10:51:45.446529 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 10:51:45.450333 ===================================
2283 10:51:45.453559 LPDDR4 DRAM CONFIGURATION
2284 10:51:45.456533 ===================================
2285 10:51:45.459990 EX_ROW_EN[0] = 0x10
2286 10:51:45.460075 EX_ROW_EN[1] = 0x0
2287 10:51:45.463527 LP4Y_EN = 0x0
2288 10:51:45.463612 WORK_FSP = 0x0
2289 10:51:45.466625 WL = 0x4
2290 10:51:45.466709 RL = 0x4
2291 10:51:45.470542 BL = 0x2
2292 10:51:45.470628 RPST = 0x0
2293 10:51:45.473661 RD_PRE = 0x0
2294 10:51:45.473755 WR_PRE = 0x1
2295 10:51:45.476531 WR_PST = 0x0
2296 10:51:45.476620 DBI_WR = 0x0
2297 10:51:45.480137 DBI_RD = 0x0
2298 10:51:45.480251 OTF = 0x1
2299 10:51:45.483100 ===================================
2300 10:51:45.490074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 10:51:45.490230 ==
2302 10:51:45.493578 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 10:51:45.496513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 10:51:45.499777 ==
2305 10:51:45.499904 [Duty_Offset_Calibration]
2306 10:51:45.503577 B0:2 B1:0 CA:3
2307 10:51:45.503667
2308 10:51:45.506751 [DutyScan_Calibration_Flow] k_type=0
2309 10:51:45.515456
2310 10:51:45.515601 ==CLK 0==
2311 10:51:45.518684 Final CLK duty delay cell = 0
2312 10:51:45.521895 [0] MAX Duty = 5062%(X100), DQS PI = 20
2313 10:51:45.524996 [0] MIN Duty = 4906%(X100), DQS PI = 54
2314 10:51:45.528143 [0] AVG Duty = 4984%(X100)
2315 10:51:45.528251
2316 10:51:45.531983 CH0 CLK Duty spec in!! Max-Min= 156%
2317 10:51:45.535090 [DutyScan_Calibration_Flow] ====Done====
2318 10:51:45.535194
2319 10:51:45.538301 [DutyScan_Calibration_Flow] k_type=1
2320 10:51:45.553653
2321 10:51:45.553764 ==DQS 0 ==
2322 10:51:45.557372 Final DQS duty delay cell = 0
2323 10:51:45.560089 [0] MAX Duty = 5062%(X100), DQS PI = 12
2324 10:51:45.563291 [0] MIN Duty = 4907%(X100), DQS PI = 2
2325 10:51:45.566722 [0] AVG Duty = 4984%(X100)
2326 10:51:45.566825
2327 10:51:45.566899 ==DQS 1 ==
2328 10:51:45.570347 Final DQS duty delay cell = -4
2329 10:51:45.573424 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2330 10:51:45.576945 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2331 10:51:45.580166 [-4] AVG Duty = 4937%(X100)
2332 10:51:45.580298
2333 10:51:45.583401 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2334 10:51:45.583514
2335 10:51:45.586508 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2336 10:51:45.590063 [DutyScan_Calibration_Flow] ====Done====
2337 10:51:45.590141
2338 10:51:45.593307 [DutyScan_Calibration_Flow] k_type=3
2339 10:51:45.611105
2340 10:51:45.611211 ==DQM 0 ==
2341 10:51:45.614905 Final DQM duty delay cell = 0
2342 10:51:45.617652 [0] MAX Duty = 5124%(X100), DQS PI = 28
2343 10:51:45.621433 [0] MIN Duty = 4876%(X100), DQS PI = 0
2344 10:51:45.621538 [0] AVG Duty = 5000%(X100)
2345 10:51:45.624609
2346 10:51:45.624684 ==DQM 1 ==
2347 10:51:45.627848 Final DQM duty delay cell = 4
2348 10:51:45.631014 [4] MAX Duty = 5124%(X100), DQS PI = 50
2349 10:51:45.634537 [4] MIN Duty = 5000%(X100), DQS PI = 32
2350 10:51:45.637899 [4] AVG Duty = 5062%(X100)
2351 10:51:45.638000
2352 10:51:45.641046 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2353 10:51:45.641140
2354 10:51:45.644165 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2355 10:51:45.648152 [DutyScan_Calibration_Flow] ====Done====
2356 10:51:45.648255
2357 10:51:45.650775 [DutyScan_Calibration_Flow] k_type=2
2358 10:51:45.666221
2359 10:51:45.666331 ==DQ 0 ==
2360 10:51:45.669775 Final DQ duty delay cell = -4
2361 10:51:45.672643 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2362 10:51:45.676252 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2363 10:51:45.679463 [-4] AVG Duty = 4969%(X100)
2364 10:51:45.679574
2365 10:51:45.679669 ==DQ 1 ==
2366 10:51:45.682406 Final DQ duty delay cell = -4
2367 10:51:45.686077 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2368 10:51:45.689304 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2369 10:51:45.692502 [-4] AVG Duty = 4938%(X100)
2370 10:51:45.692587
2371 10:51:45.696095 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2372 10:51:45.696180
2373 10:51:45.699005 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2374 10:51:45.702742 [DutyScan_Calibration_Flow] ====Done====
2375 10:51:45.702857 ==
2376 10:51:45.705642 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 10:51:45.709113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 10:51:45.709202 ==
2379 10:51:45.712687 [Duty_Offset_Calibration]
2380 10:51:45.712777 B0:1 B1:-2 CA:0
2381 10:51:45.712843
2382 10:51:45.715508 [DutyScan_Calibration_Flow] k_type=0
2383 10:51:45.726822
2384 10:51:45.726913 ==CLK 0==
2385 10:51:45.729989 Final CLK duty delay cell = 0
2386 10:51:45.733039 [0] MAX Duty = 5062%(X100), DQS PI = 30
2387 10:51:45.736870 [0] MIN Duty = 4844%(X100), DQS PI = 58
2388 10:51:45.736975 [0] AVG Duty = 4953%(X100)
2389 10:51:45.739983
2390 10:51:45.743269 CH1 CLK Duty spec in!! Max-Min= 218%
2391 10:51:45.746381 [DutyScan_Calibration_Flow] ====Done====
2392 10:51:45.746468
2393 10:51:45.749503 [DutyScan_Calibration_Flow] k_type=1
2394 10:51:45.765436
2395 10:51:45.765521 ==DQS 0 ==
2396 10:51:45.768388 Final DQS duty delay cell = -4
2397 10:51:45.772019 [-4] MAX Duty = 5000%(X100), DQS PI = 16
2398 10:51:45.775176 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2399 10:51:45.778370 [-4] AVG Duty = 4953%(X100)
2400 10:51:45.778455
2401 10:51:45.778540 ==DQS 1 ==
2402 10:51:45.781830 Final DQS duty delay cell = 0
2403 10:51:45.785287 [0] MAX Duty = 5093%(X100), DQS PI = 0
2404 10:51:45.788848 [0] MIN Duty = 4875%(X100), DQS PI = 26
2405 10:51:45.791675 [0] AVG Duty = 4984%(X100)
2406 10:51:45.791759
2407 10:51:45.795319 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2408 10:51:45.795404
2409 10:51:45.798689 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2410 10:51:45.801524 [DutyScan_Calibration_Flow] ====Done====
2411 10:51:45.801620
2412 10:51:45.805267 [DutyScan_Calibration_Flow] k_type=3
2413 10:51:45.821875
2414 10:51:45.822014 ==DQM 0 ==
2415 10:51:45.824828 Final DQM duty delay cell = 0
2416 10:51:45.828316 [0] MAX Duty = 5031%(X100), DQS PI = 24
2417 10:51:45.831845 [0] MIN Duty = 4844%(X100), DQS PI = 54
2418 10:51:45.835098 [0] AVG Duty = 4937%(X100)
2419 10:51:45.835180
2420 10:51:45.835244 ==DQM 1 ==
2421 10:51:45.838303 Final DQM duty delay cell = 0
2422 10:51:45.841498 [0] MAX Duty = 5031%(X100), DQS PI = 36
2423 10:51:45.845166 [0] MIN Duty = 4907%(X100), DQS PI = 4
2424 10:51:45.848699 [0] AVG Duty = 4969%(X100)
2425 10:51:45.848800
2426 10:51:45.851761 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2427 10:51:45.851843
2428 10:51:45.855032 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2429 10:51:45.858522 [DutyScan_Calibration_Flow] ====Done====
2430 10:51:45.858604
2431 10:51:45.861599 [DutyScan_Calibration_Flow] k_type=2
2432 10:51:45.878292
2433 10:51:45.878374 ==DQ 0 ==
2434 10:51:45.881541 Final DQ duty delay cell = 0
2435 10:51:45.884760 [0] MAX Duty = 5093%(X100), DQS PI = 32
2436 10:51:45.887815 [0] MIN Duty = 4938%(X100), DQS PI = 56
2437 10:51:45.891410 [0] AVG Duty = 5015%(X100)
2438 10:51:45.891492
2439 10:51:45.891556 ==DQ 1 ==
2440 10:51:45.894666 Final DQ duty delay cell = 0
2441 10:51:45.897801 [0] MAX Duty = 5125%(X100), DQS PI = 36
2442 10:51:45.901424 [0] MIN Duty = 4969%(X100), DQS PI = 26
2443 10:51:45.901506 [0] AVG Duty = 5047%(X100)
2444 10:51:45.904516
2445 10:51:45.908190 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2446 10:51:45.908293
2447 10:51:45.911333 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2448 10:51:45.914454 [DutyScan_Calibration_Flow] ====Done====
2449 10:51:45.918122 nWR fixed to 30
2450 10:51:45.918204 [ModeRegInit_LP4] CH0 RK0
2451 10:51:45.921098 [ModeRegInit_LP4] CH0 RK1
2452 10:51:45.924684 [ModeRegInit_LP4] CH1 RK0
2453 10:51:45.928150 [ModeRegInit_LP4] CH1 RK1
2454 10:51:45.928247 match AC timing 7
2455 10:51:45.930968 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 10:51:45.938087 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 10:51:45.941098 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 10:51:45.948001 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 10:51:45.951356 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 10:51:45.951445 ==
2461 10:51:45.954592 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 10:51:45.957626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 10:51:45.957749 ==
2464 10:51:45.964287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 10:51:45.970771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2466 10:51:45.978045 [CA 0] Center 40 (10~71) winsize 62
2467 10:51:45.981605 [CA 1] Center 39 (9~70) winsize 62
2468 10:51:45.984940 [CA 2] Center 36 (6~66) winsize 61
2469 10:51:45.988034 [CA 3] Center 35 (5~66) winsize 62
2470 10:51:45.991610 [CA 4] Center 34 (4~65) winsize 62
2471 10:51:45.995115 [CA 5] Center 33 (3~64) winsize 62
2472 10:51:45.995197
2473 10:51:45.997925 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2474 10:51:45.998007
2475 10:51:46.001500 [CATrainingPosCal] consider 1 rank data
2476 10:51:46.005282 u2DelayCellTimex100 = 270/100 ps
2477 10:51:46.008044 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2478 10:51:46.014697 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2479 10:51:46.018203 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2480 10:51:46.021237 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2481 10:51:46.024614 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2482 10:51:46.028124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2483 10:51:46.028240
2484 10:51:46.031075 CA PerBit enable=1, Macro0, CA PI delay=33
2485 10:51:46.031154
2486 10:51:46.034635 [CBTSetCACLKResult] CA Dly = 33
2487 10:51:46.037539 CS Dly: 7 (0~38)
2488 10:51:46.037661 ==
2489 10:51:46.041051 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 10:51:46.044736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 10:51:46.044851 ==
2492 10:51:46.050953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 10:51:46.054353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 10:51:46.064078 [CA 0] Center 40 (10~71) winsize 62
2495 10:51:46.067103 [CA 1] Center 40 (10~70) winsize 61
2496 10:51:46.071001 [CA 2] Center 35 (5~66) winsize 62
2497 10:51:46.074125 [CA 3] Center 35 (5~66) winsize 62
2498 10:51:46.077326 [CA 4] Center 34 (4~65) winsize 62
2499 10:51:46.081104 [CA 5] Center 33 (3~63) winsize 61
2500 10:51:46.081188
2501 10:51:46.084106 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2502 10:51:46.084189
2503 10:51:46.087157 [CATrainingPosCal] consider 2 rank data
2504 10:51:46.090974 u2DelayCellTimex100 = 270/100 ps
2505 10:51:46.094175 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2506 10:51:46.100435 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2507 10:51:46.104275 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2508 10:51:46.107324 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 10:51:46.110771 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2510 10:51:46.113670 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2511 10:51:46.113753
2512 10:51:46.117167 CA PerBit enable=1, Macro0, CA PI delay=33
2513 10:51:46.117280
2514 10:51:46.120586 [CBTSetCACLKResult] CA Dly = 33
2515 10:51:46.123653 CS Dly: 8 (0~40)
2516 10:51:46.123760
2517 10:51:46.127385 ----->DramcWriteLeveling(PI) begin...
2518 10:51:46.127484 ==
2519 10:51:46.130224 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 10:51:46.133567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 10:51:46.133650 ==
2522 10:51:46.137014 Write leveling (Byte 0): 33 => 33
2523 10:51:46.140555 Write leveling (Byte 1): 30 => 30
2524 10:51:46.143749 DramcWriteLeveling(PI) end<-----
2525 10:51:46.143832
2526 10:51:46.143901 ==
2527 10:51:46.147125 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 10:51:46.150578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 10:51:46.150662 ==
2530 10:51:46.153995 [Gating] SW mode calibration
2531 10:51:46.160354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 10:51:46.166826 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 10:51:46.170324 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 10:51:46.173442 0 15 4 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2535 10:51:46.180326 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 10:51:46.183527 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 10:51:46.186539 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 10:51:46.193496 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 10:51:46.196588 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 10:51:46.200261 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2541 10:51:46.206602 1 0 0 | B1->B0 | 3333 2727 | 1 0 | (1 1) (0 1)
2542 10:51:46.209869 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2543 10:51:46.213009 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 10:51:46.219663 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 10:51:46.223227 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 10:51:46.226365 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 10:51:46.232961 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 10:51:46.236628 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2549 10:51:46.239553 1 1 0 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
2550 10:51:46.246030 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2551 10:51:46.249447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 10:51:46.252947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 10:51:46.259786 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 10:51:46.262702 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 10:51:46.266569 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 10:51:46.272631 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 10:51:46.275733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 10:51:46.279373 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 10:51:46.285719 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:51:46.289603 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:51:46.292617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:51:46.299074 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:51:46.302647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:51:46.305703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:51:46.312620 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:51:46.315971 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:51:46.319017 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:51:46.325800 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 10:51:46.329343 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 10:51:46.332457 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 10:51:46.339217 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 10:51:46.342045 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 10:51:46.345678 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 10:51:46.349033 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 10:51:46.352502 Total UI for P1: 0, mck2ui 16
2576 10:51:46.355469 best dqsien dly found for B0: ( 1, 3, 30)
2577 10:51:46.362309 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 10:51:46.365568 Total UI for P1: 0, mck2ui 16
2579 10:51:46.369078 best dqsien dly found for B1: ( 1, 4, 4)
2580 10:51:46.372264 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2581 10:51:46.375626 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2582 10:51:46.375701
2583 10:51:46.379207 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2584 10:51:46.382100 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2585 10:51:46.385377 [Gating] SW calibration Done
2586 10:51:46.385452 ==
2587 10:51:46.388965 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 10:51:46.392209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 10:51:46.392280 ==
2590 10:51:46.395363 RX Vref Scan: 0
2591 10:51:46.395459
2592 10:51:46.398318 RX Vref 0 -> 0, step: 1
2593 10:51:46.398414
2594 10:51:46.398502 RX Delay -40 -> 252, step: 8
2595 10:51:46.405327 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2596 10:51:46.408258 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2597 10:51:46.412065 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2598 10:51:46.415099 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2599 10:51:46.418320 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2600 10:51:46.425239 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2601 10:51:46.428340 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2602 10:51:46.431520 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2603 10:51:46.434966 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2604 10:51:46.437988 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2605 10:51:46.445363 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2606 10:51:46.448061 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2607 10:51:46.451540 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2608 10:51:46.454958 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2609 10:51:46.458413 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2610 10:51:46.464918 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2611 10:51:46.465031 ==
2612 10:51:46.467785 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 10:51:46.471161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 10:51:46.471273 ==
2615 10:51:46.471367 DQS Delay:
2616 10:51:46.474424 DQS0 = 0, DQS1 = 0
2617 10:51:46.474538 DQM Delay:
2618 10:51:46.478092 DQM0 = 112, DQM1 = 102
2619 10:51:46.478205 DQ Delay:
2620 10:51:46.481357 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2621 10:51:46.484786 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2622 10:51:46.487859 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2623 10:51:46.490958 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2624 10:51:46.491069
2625 10:51:46.491164
2626 10:51:46.491230 ==
2627 10:51:46.495055 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 10:51:46.501549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 10:51:46.501638 ==
2630 10:51:46.501706
2631 10:51:46.501768
2632 10:51:46.501829 TX Vref Scan disable
2633 10:51:46.505120 == TX Byte 0 ==
2634 10:51:46.508380 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2635 10:51:46.515245 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2636 10:51:46.515360 == TX Byte 1 ==
2637 10:51:46.518531 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2638 10:51:46.524582 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2639 10:51:46.524689 ==
2640 10:51:46.527979 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 10:51:46.531632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 10:51:46.531717 ==
2643 10:51:46.543074 TX Vref=22, minBit 11, minWin=25, winSum=415
2644 10:51:46.546234 TX Vref=24, minBit 1, minWin=26, winSum=423
2645 10:51:46.549916 TX Vref=26, minBit 10, minWin=26, winSum=432
2646 10:51:46.552914 TX Vref=28, minBit 12, minWin=26, winSum=431
2647 10:51:46.556838 TX Vref=30, minBit 8, minWin=26, winSum=430
2648 10:51:46.563108 TX Vref=32, minBit 2, minWin=26, winSum=427
2649 10:51:46.566128 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 26
2650 10:51:46.566213
2651 10:51:46.569630 Final TX Range 1 Vref 26
2652 10:51:46.569723
2653 10:51:46.569791 ==
2654 10:51:46.573106 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 10:51:46.579217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 10:51:46.579322 ==
2657 10:51:46.579416
2658 10:51:46.579496
2659 10:51:46.579556 TX Vref Scan disable
2660 10:51:46.583408 == TX Byte 0 ==
2661 10:51:46.586512 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2662 10:51:46.593308 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2663 10:51:46.593390 == TX Byte 1 ==
2664 10:51:46.596353 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2665 10:51:46.603253 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2666 10:51:46.603340
2667 10:51:46.603412 [DATLAT]
2668 10:51:46.603477 Freq=1200, CH0 RK0
2669 10:51:46.603537
2670 10:51:46.606338 DATLAT Default: 0xd
2671 10:51:46.606412 0, 0xFFFF, sum = 0
2672 10:51:46.609372 1, 0xFFFF, sum = 0
2673 10:51:46.609445 2, 0xFFFF, sum = 0
2674 10:51:46.613178 3, 0xFFFF, sum = 0
2675 10:51:46.616152 4, 0xFFFF, sum = 0
2676 10:51:46.616226 5, 0xFFFF, sum = 0
2677 10:51:46.619891 6, 0xFFFF, sum = 0
2678 10:51:46.619969 7, 0xFFFF, sum = 0
2679 10:51:46.623077 8, 0xFFFF, sum = 0
2680 10:51:46.623164 9, 0xFFFF, sum = 0
2681 10:51:46.626284 10, 0xFFFF, sum = 0
2682 10:51:46.626356 11, 0xFFFF, sum = 0
2683 10:51:46.629545 12, 0x0, sum = 1
2684 10:51:46.629630 13, 0x0, sum = 2
2685 10:51:46.633302 14, 0x0, sum = 3
2686 10:51:46.633387 15, 0x0, sum = 4
2687 10:51:46.636383 best_step = 13
2688 10:51:46.636466
2689 10:51:46.636532 ==
2690 10:51:46.639642 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 10:51:46.642701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 10:51:46.642808 ==
2693 10:51:46.642890 RX Vref Scan: 1
2694 10:51:46.642952
2695 10:51:46.645805 Set Vref Range= 32 -> 127
2696 10:51:46.645874
2697 10:51:46.649472 RX Vref 32 -> 127, step: 1
2698 10:51:46.649570
2699 10:51:46.652507 RX Delay -37 -> 252, step: 4
2700 10:51:46.652615
2701 10:51:46.656041 Set Vref, RX VrefLevel [Byte0]: 32
2702 10:51:46.659151 [Byte1]: 32
2703 10:51:46.659234
2704 10:51:46.662973 Set Vref, RX VrefLevel [Byte0]: 33
2705 10:51:46.665862 [Byte1]: 33
2706 10:51:46.669409
2707 10:51:46.673087 Set Vref, RX VrefLevel [Byte0]: 34
2708 10:51:46.675990 [Byte1]: 34
2709 10:51:46.676100
2710 10:51:46.679552 Set Vref, RX VrefLevel [Byte0]: 35
2711 10:51:46.683098 [Byte1]: 35
2712 10:51:46.683207
2713 10:51:46.686070 Set Vref, RX VrefLevel [Byte0]: 36
2714 10:51:46.689960 [Byte1]: 36
2715 10:51:46.693689
2716 10:51:46.693792 Set Vref, RX VrefLevel [Byte0]: 37
2717 10:51:46.696843 [Byte1]: 37
2718 10:51:46.701609
2719 10:51:46.701717 Set Vref, RX VrefLevel [Byte0]: 38
2720 10:51:46.705005 [Byte1]: 38
2721 10:51:46.709957
2722 10:51:46.710043 Set Vref, RX VrefLevel [Byte0]: 39
2723 10:51:46.713061 [Byte1]: 39
2724 10:51:46.718028
2725 10:51:46.718112 Set Vref, RX VrefLevel [Byte0]: 40
2726 10:51:46.721033 [Byte1]: 40
2727 10:51:46.725906
2728 10:51:46.726016 Set Vref, RX VrefLevel [Byte0]: 41
2729 10:51:46.729092 [Byte1]: 41
2730 10:51:46.734081
2731 10:51:46.734159 Set Vref, RX VrefLevel [Byte0]: 42
2732 10:51:46.737191 [Byte1]: 42
2733 10:51:46.741749
2734 10:51:46.741857 Set Vref, RX VrefLevel [Byte0]: 43
2735 10:51:46.745431 [Byte1]: 43
2736 10:51:46.749876
2737 10:51:46.749956 Set Vref, RX VrefLevel [Byte0]: 44
2738 10:51:46.752782 [Byte1]: 44
2739 10:51:46.757874
2740 10:51:46.757951 Set Vref, RX VrefLevel [Byte0]: 45
2741 10:51:46.760858 [Byte1]: 45
2742 10:51:46.765957
2743 10:51:46.766036 Set Vref, RX VrefLevel [Byte0]: 46
2744 10:51:46.768826 [Byte1]: 46
2745 10:51:46.773600
2746 10:51:46.773676 Set Vref, RX VrefLevel [Byte0]: 47
2747 10:51:46.777245 [Byte1]: 47
2748 10:51:46.781775
2749 10:51:46.781857 Set Vref, RX VrefLevel [Byte0]: 48
2750 10:51:46.784986 [Byte1]: 48
2751 10:51:46.789729
2752 10:51:46.789832 Set Vref, RX VrefLevel [Byte0]: 49
2753 10:51:46.793488 [Byte1]: 49
2754 10:51:46.797850
2755 10:51:46.797934 Set Vref, RX VrefLevel [Byte0]: 50
2756 10:51:46.801239 [Byte1]: 50
2757 10:51:46.805852
2758 10:51:46.805931 Set Vref, RX VrefLevel [Byte0]: 51
2759 10:51:46.809031 [Byte1]: 51
2760 10:51:46.814009
2761 10:51:46.814091 Set Vref, RX VrefLevel [Byte0]: 52
2762 10:51:46.817212 [Byte1]: 52
2763 10:51:46.821577
2764 10:51:46.821659 Set Vref, RX VrefLevel [Byte0]: 53
2765 10:51:46.825373 [Byte1]: 53
2766 10:51:46.829463
2767 10:51:46.829574 Set Vref, RX VrefLevel [Byte0]: 54
2768 10:51:46.833587 [Byte1]: 54
2769 10:51:46.837650
2770 10:51:46.837760 Set Vref, RX VrefLevel [Byte0]: 55
2771 10:51:46.840814 [Byte1]: 55
2772 10:51:46.845938
2773 10:51:46.846048 Set Vref, RX VrefLevel [Byte0]: 56
2774 10:51:46.849172 [Byte1]: 56
2775 10:51:46.853615
2776 10:51:46.853727 Set Vref, RX VrefLevel [Byte0]: 57
2777 10:51:46.857279 [Byte1]: 57
2778 10:51:46.862004
2779 10:51:46.862138 Set Vref, RX VrefLevel [Byte0]: 58
2780 10:51:46.865220 [Byte1]: 58
2781 10:51:46.869881
2782 10:51:46.869981 Set Vref, RX VrefLevel [Byte0]: 59
2783 10:51:46.873029 [Byte1]: 59
2784 10:51:46.877932
2785 10:51:46.878075 Set Vref, RX VrefLevel [Byte0]: 60
2786 10:51:46.880988 [Byte1]: 60
2787 10:51:46.885904
2788 10:51:46.885986 Set Vref, RX VrefLevel [Byte0]: 61
2789 10:51:46.888920 [Byte1]: 61
2790 10:51:46.893977
2791 10:51:46.894060 Set Vref, RX VrefLevel [Byte0]: 62
2792 10:51:46.897475 [Byte1]: 62
2793 10:51:46.901755
2794 10:51:46.901839 Set Vref, RX VrefLevel [Byte0]: 63
2795 10:51:46.904766 [Byte1]: 63
2796 10:51:46.909952
2797 10:51:46.910051 Set Vref, RX VrefLevel [Byte0]: 64
2798 10:51:46.912944 [Byte1]: 64
2799 10:51:46.917849
2800 10:51:46.917946 Set Vref, RX VrefLevel [Byte0]: 65
2801 10:51:46.921124 [Byte1]: 65
2802 10:51:46.925729
2803 10:51:46.925813 Set Vref, RX VrefLevel [Byte0]: 66
2804 10:51:46.929254 [Byte1]: 66
2805 10:51:46.933500
2806 10:51:46.933596 Set Vref, RX VrefLevel [Byte0]: 67
2807 10:51:46.937290 [Byte1]: 67
2808 10:51:46.941959
2809 10:51:46.942094 Set Vref, RX VrefLevel [Byte0]: 68
2810 10:51:46.945068 [Byte1]: 68
2811 10:51:46.949845
2812 10:51:46.949927 Set Vref, RX VrefLevel [Byte0]: 69
2813 10:51:46.953027 [Byte1]: 69
2814 10:51:46.957441
2815 10:51:46.957579 Set Vref, RX VrefLevel [Byte0]: 70
2816 10:51:46.961314 [Byte1]: 70
2817 10:51:46.965468
2818 10:51:46.965580 Set Vref, RX VrefLevel [Byte0]: 71
2819 10:51:46.969578 [Byte1]: 71
2820 10:51:46.973702
2821 10:51:46.973864 Set Vref, RX VrefLevel [Byte0]: 72
2822 10:51:46.977244 [Byte1]: 72
2823 10:51:46.981531
2824 10:51:46.981615 Set Vref, RX VrefLevel [Byte0]: 73
2825 10:51:46.985350 [Byte1]: 73
2826 10:51:46.989619
2827 10:51:46.989729 Set Vref, RX VrefLevel [Byte0]: 74
2828 10:51:46.992832 [Byte1]: 74
2829 10:51:46.997647
2830 10:51:46.997754 Final RX Vref Byte 0 = 63 to rank0
2831 10:51:47.001094 Final RX Vref Byte 1 = 58 to rank0
2832 10:51:47.004639 Final RX Vref Byte 0 = 63 to rank1
2833 10:51:47.007546 Final RX Vref Byte 1 = 58 to rank1==
2834 10:51:47.011160 Dram Type= 6, Freq= 0, CH_0, rank 0
2835 10:51:47.017565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 10:51:47.017676 ==
2837 10:51:47.017780 DQS Delay:
2838 10:51:47.017879 DQS0 = 0, DQS1 = 0
2839 10:51:47.021296 DQM Delay:
2840 10:51:47.021397 DQM0 = 112, DQM1 = 102
2841 10:51:47.024401 DQ Delay:
2842 10:51:47.027695 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2843 10:51:47.030713 DQ4 =114, DQ5 =104, DQ6 =118, DQ7 =120
2844 10:51:47.034350 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2845 10:51:47.037312 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2846 10:51:47.037392
2847 10:51:47.037473
2848 10:51:47.044279 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2849 10:51:47.047375 CH0 RK0: MR19=303, MR18=F9F9
2850 10:51:47.054376 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2851 10:51:47.054464
2852 10:51:47.057653 ----->DramcWriteLeveling(PI) begin...
2853 10:51:47.057766 ==
2854 10:51:47.060765 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 10:51:47.063879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 10:51:47.067944 ==
2857 10:51:47.068027 Write leveling (Byte 0): 32 => 32
2858 10:51:47.070684 Write leveling (Byte 1): 30 => 30
2859 10:51:47.074149 DramcWriteLeveling(PI) end<-----
2860 10:51:47.074257
2861 10:51:47.074352 ==
2862 10:51:47.077216 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 10:51:47.083969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 10:51:47.084046 ==
2865 10:51:47.087477 [Gating] SW mode calibration
2866 10:51:47.093763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2867 10:51:47.096891 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2868 10:51:47.103817 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2869 10:51:47.106887 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 10:51:47.110407 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 10:51:47.116844 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 10:51:47.120421 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 10:51:47.123516 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 10:51:47.130099 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2875 10:51:47.133392 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2876 10:51:47.136966 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2877 10:51:47.143589 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 10:51:47.146881 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 10:51:47.149953 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 10:51:47.156396 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 10:51:47.160188 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 10:51:47.163429 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2883 10:51:47.169874 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2884 10:51:47.173058 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2885 10:51:47.176754 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 10:51:47.183295 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 10:51:47.186226 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 10:51:47.189672 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 10:51:47.193384 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 10:51:47.199953 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 10:51:47.203419 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2892 10:51:47.206767 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 10:51:47.213075 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 10:51:47.216872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 10:51:47.219540 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 10:51:47.226473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 10:51:47.229475 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 10:51:47.232920 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 10:51:47.239827 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 10:51:47.242616 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 10:51:47.246253 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 10:51:47.252963 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 10:51:47.256112 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 10:51:47.259370 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 10:51:47.266264 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:51:47.269467 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:51:47.272566 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2908 10:51:47.279492 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 10:51:47.282667 Total UI for P1: 0, mck2ui 16
2910 10:51:47.285555 best dqsien dly found for B0: ( 1, 3, 28)
2911 10:51:47.285661 Total UI for P1: 0, mck2ui 16
2912 10:51:47.292296 best dqsien dly found for B1: ( 1, 3, 30)
2913 10:51:47.295839 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2914 10:51:47.299209 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2915 10:51:47.299297
2916 10:51:47.302428 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2917 10:51:47.305667 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2918 10:51:47.308705 [Gating] SW calibration Done
2919 10:51:47.308780 ==
2920 10:51:47.312486 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 10:51:47.315358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 10:51:47.315441 ==
2923 10:51:47.318812 RX Vref Scan: 0
2924 10:51:47.318927
2925 10:51:47.319021 RX Vref 0 -> 0, step: 1
2926 10:51:47.319111
2927 10:51:47.322527 RX Delay -40 -> 252, step: 8
2928 10:51:47.329019 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2929 10:51:47.332445 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2930 10:51:47.335505 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2931 10:51:47.339001 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2932 10:51:47.342413 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2933 10:51:47.345287 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2934 10:51:47.352089 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2935 10:51:47.355872 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2936 10:51:47.359137 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2937 10:51:47.362327 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2938 10:51:47.365418 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2939 10:51:47.372404 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2940 10:51:47.375599 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2941 10:51:47.378600 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2942 10:51:47.382433 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2943 10:51:47.385543 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2944 10:51:47.389146 ==
2945 10:51:47.389259 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 10:51:47.395721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 10:51:47.395805 ==
2948 10:51:47.395874 DQS Delay:
2949 10:51:47.398814 DQS0 = 0, DQS1 = 0
2950 10:51:47.398901 DQM Delay:
2951 10:51:47.401885 DQM0 = 112, DQM1 = 102
2952 10:51:47.401963 DQ Delay:
2953 10:51:47.405160 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2954 10:51:47.408537 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2955 10:51:47.412344 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2956 10:51:47.415539 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2957 10:51:47.415619
2958 10:51:47.415685
2959 10:51:47.415746 ==
2960 10:51:47.418699 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 10:51:47.424958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 10:51:47.425065 ==
2963 10:51:47.425161
2964 10:51:47.425251
2965 10:51:47.425341 TX Vref Scan disable
2966 10:51:47.428968 == TX Byte 0 ==
2967 10:51:47.432176 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2968 10:51:47.438558 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2969 10:51:47.438665 == TX Byte 1 ==
2970 10:51:47.441987 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2971 10:51:47.448207 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2972 10:51:47.448292 ==
2973 10:51:47.451550 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 10:51:47.454955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 10:51:47.455061 ==
2976 10:51:47.466707 TX Vref=22, minBit 8, minWin=26, winSum=428
2977 10:51:47.469905 TX Vref=24, minBit 5, minWin=26, winSum=431
2978 10:51:47.473109 TX Vref=26, minBit 5, minWin=26, winSum=435
2979 10:51:47.476256 TX Vref=28, minBit 5, minWin=26, winSum=440
2980 10:51:47.480045 TX Vref=30, minBit 1, minWin=27, winSum=444
2981 10:51:47.486156 TX Vref=32, minBit 8, minWin=26, winSum=438
2982 10:51:47.489351 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
2983 10:51:47.489458
2984 10:51:47.493343 Final TX Range 1 Vref 30
2985 10:51:47.493421
2986 10:51:47.493488 ==
2987 10:51:47.496232 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 10:51:47.499226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 10:51:47.502917 ==
2990 10:51:47.503023
2991 10:51:47.503125
2992 10:51:47.503192 TX Vref Scan disable
2993 10:51:47.506082 == TX Byte 0 ==
2994 10:51:47.509599 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2995 10:51:47.516753 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2996 10:51:47.516868 == TX Byte 1 ==
2997 10:51:47.519723 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2998 10:51:47.525819 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2999 10:51:47.525932
3000 10:51:47.526027 [DATLAT]
3001 10:51:47.526093 Freq=1200, CH0 RK1
3002 10:51:47.526154
3003 10:51:47.529447 DATLAT Default: 0xd
3004 10:51:47.532609 0, 0xFFFF, sum = 0
3005 10:51:47.532692 1, 0xFFFF, sum = 0
3006 10:51:47.536123 2, 0xFFFF, sum = 0
3007 10:51:47.536210 3, 0xFFFF, sum = 0
3008 10:51:47.539211 4, 0xFFFF, sum = 0
3009 10:51:47.539326 5, 0xFFFF, sum = 0
3010 10:51:47.542788 6, 0xFFFF, sum = 0
3011 10:51:47.542882 7, 0xFFFF, sum = 0
3012 10:51:47.545830 8, 0xFFFF, sum = 0
3013 10:51:47.545947 9, 0xFFFF, sum = 0
3014 10:51:47.549500 10, 0xFFFF, sum = 0
3015 10:51:47.549585 11, 0xFFFF, sum = 0
3016 10:51:47.552465 12, 0x0, sum = 1
3017 10:51:47.552577 13, 0x0, sum = 2
3018 10:51:47.555980 14, 0x0, sum = 3
3019 10:51:47.556065 15, 0x0, sum = 4
3020 10:51:47.558802 best_step = 13
3021 10:51:47.558899
3022 10:51:47.558966 ==
3023 10:51:47.562405 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 10:51:47.566047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 10:51:47.566122 ==
3026 10:51:47.569413 RX Vref Scan: 0
3027 10:51:47.569502
3028 10:51:47.569566 RX Vref 0 -> 0, step: 1
3029 10:51:47.569646
3030 10:51:47.572331 RX Delay -29 -> 252, step: 4
3031 10:51:47.579080 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3032 10:51:47.582446 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3033 10:51:47.585966 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3034 10:51:47.588810 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3035 10:51:47.591984 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3036 10:51:47.599059 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3037 10:51:47.602150 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3038 10:51:47.605746 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3039 10:51:47.608846 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3040 10:51:47.612031 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3041 10:51:47.618774 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3042 10:51:47.622309 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3043 10:51:47.625458 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3044 10:51:47.628505 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3045 10:51:47.632229 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3046 10:51:47.638222 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3047 10:51:47.638309 ==
3048 10:51:47.641869 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 10:51:47.645119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 10:51:47.645208 ==
3051 10:51:47.645276 DQS Delay:
3052 10:51:47.648459 DQS0 = 0, DQS1 = 0
3053 10:51:47.648542 DQM Delay:
3054 10:51:47.651476 DQM0 = 110, DQM1 = 101
3055 10:51:47.651559 DQ Delay:
3056 10:51:47.654886 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3057 10:51:47.658438 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3058 10:51:47.661818 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3059 10:51:47.664665 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3060 10:51:47.664748
3061 10:51:47.668175
3062 10:51:47.674790 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3063 10:51:47.677972 CH0 RK1: MR19=403, MR18=15FC
3064 10:51:47.684927 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3065 10:51:47.688173 [RxdqsGatingPostProcess] freq 1200
3066 10:51:47.691177 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3067 10:51:47.694971 best DQS0 dly(2T, 0.5T) = (0, 11)
3068 10:51:47.698115 best DQS1 dly(2T, 0.5T) = (0, 12)
3069 10:51:47.701383 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3070 10:51:47.704497 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3071 10:51:47.707961 best DQS0 dly(2T, 0.5T) = (0, 11)
3072 10:51:47.711490 best DQS1 dly(2T, 0.5T) = (0, 11)
3073 10:51:47.714384 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3074 10:51:47.718137 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3075 10:51:47.721405 Pre-setting of DQS Precalculation
3076 10:51:47.724637 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3077 10:51:47.724719 ==
3078 10:51:47.727711 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 10:51:47.731169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 10:51:47.734283 ==
3081 10:51:47.737780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3082 10:51:47.744766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3083 10:51:47.752571 [CA 0] Center 37 (7~67) winsize 61
3084 10:51:47.756147 [CA 1] Center 37 (7~68) winsize 62
3085 10:51:47.759199 [CA 2] Center 34 (4~64) winsize 61
3086 10:51:47.762336 [CA 3] Center 33 (3~64) winsize 62
3087 10:51:47.765608 [CA 4] Center 34 (4~64) winsize 61
3088 10:51:47.769089 [CA 5] Center 33 (3~63) winsize 61
3089 10:51:47.769197
3090 10:51:47.772582 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3091 10:51:47.772689
3092 10:51:47.775506 [CATrainingPosCal] consider 1 rank data
3093 10:51:47.779208 u2DelayCellTimex100 = 270/100 ps
3094 10:51:47.782596 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3095 10:51:47.788652 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3096 10:51:47.792483 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 10:51:47.795651 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3098 10:51:47.798741 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 10:51:47.802528 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3100 10:51:47.802644
3101 10:51:47.805577 CA PerBit enable=1, Macro0, CA PI delay=33
3102 10:51:47.805686
3103 10:51:47.808649 [CBTSetCACLKResult] CA Dly = 33
3104 10:51:47.812593 CS Dly: 5 (0~36)
3105 10:51:47.812682 ==
3106 10:51:47.815475 Dram Type= 6, Freq= 0, CH_1, rank 1
3107 10:51:47.818501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 10:51:47.818586 ==
3109 10:51:47.825168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 10:51:47.828442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3111 10:51:47.838048 [CA 0] Center 37 (8~67) winsize 60
3112 10:51:47.841717 [CA 1] Center 37 (7~68) winsize 62
3113 10:51:47.844720 [CA 2] Center 34 (4~65) winsize 62
3114 10:51:47.847880 [CA 3] Center 33 (3~64) winsize 62
3115 10:51:47.851516 [CA 4] Center 34 (4~65) winsize 62
3116 10:51:47.854440 [CA 5] Center 33 (3~63) winsize 61
3117 10:51:47.854565
3118 10:51:47.858123 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3119 10:51:47.858330
3120 10:51:47.861529 [CATrainingPosCal] consider 2 rank data
3121 10:51:47.864454 u2DelayCellTimex100 = 270/100 ps
3122 10:51:47.867924 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3123 10:51:47.874850 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 10:51:47.878487 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 10:51:47.881336 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3126 10:51:47.884694 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 10:51:47.887751 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3128 10:51:47.887825
3129 10:51:47.890859 CA PerBit enable=1, Macro0, CA PI delay=33
3130 10:51:47.890949
3131 10:51:47.894523 [CBTSetCACLKResult] CA Dly = 33
3132 10:51:47.894624 CS Dly: 7 (0~40)
3133 10:51:47.897762
3134 10:51:47.900828 ----->DramcWriteLeveling(PI) begin...
3135 10:51:47.900903 ==
3136 10:51:47.904084 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 10:51:47.907912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 10:51:47.908027 ==
3139 10:51:47.911000 Write leveling (Byte 0): 25 => 25
3140 10:51:47.914203 Write leveling (Byte 1): 30 => 30
3141 10:51:47.917356 DramcWriteLeveling(PI) end<-----
3142 10:51:47.917458
3143 10:51:47.917549 ==
3144 10:51:47.921236 Dram Type= 6, Freq= 0, CH_1, rank 0
3145 10:51:47.924309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 10:51:47.924412 ==
3147 10:51:47.927524 [Gating] SW mode calibration
3148 10:51:47.934121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3149 10:51:47.940619 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3150 10:51:47.944054 0 15 0 | B1->B0 | 2d2d 2727 | 0 1 | (0 0) (0 0)
3151 10:51:47.947548 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 10:51:47.953920 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 10:51:47.957627 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 10:51:47.960529 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 10:51:47.967063 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 10:51:47.970575 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 10:51:47.974096 0 15 28 | B1->B0 | 2727 2a2a | 1 1 | (1 0) (1 0)
3158 10:51:47.980605 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3159 10:51:47.983792 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 10:51:47.987479 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 10:51:47.993439 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 10:51:47.997265 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 10:51:48.000509 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 10:51:48.006786 1 0 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3165 10:51:48.010743 1 0 28 | B1->B0 | 4141 3c3b | 0 1 | (0 0) (1 1)
3166 10:51:48.013879 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 10:51:48.020155 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 10:51:48.024200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 10:51:48.027063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 10:51:48.033697 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 10:51:48.036994 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 10:51:48.040390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 10:51:48.043590 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3174 10:51:48.050212 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3175 10:51:48.053699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 10:51:48.057033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 10:51:48.063332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 10:51:48.066885 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 10:51:48.070591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 10:51:48.076886 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 10:51:48.080263 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 10:51:48.083481 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 10:51:48.089890 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 10:51:48.093315 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 10:51:48.096887 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 10:51:48.103007 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 10:51:48.106600 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:51:48.109819 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:51:48.116820 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3190 10:51:48.120066 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 10:51:48.123334 Total UI for P1: 0, mck2ui 16
3192 10:51:48.126582 best dqsien dly found for B0: ( 1, 3, 28)
3193 10:51:48.129600 Total UI for P1: 0, mck2ui 16
3194 10:51:48.132728 best dqsien dly found for B1: ( 1, 3, 28)
3195 10:51:48.136257 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3196 10:51:48.139840 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3197 10:51:48.139932
3198 10:51:48.142922 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3199 10:51:48.146417 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3200 10:51:48.149873 [Gating] SW calibration Done
3201 10:51:48.149989 ==
3202 10:51:48.152948 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 10:51:48.156447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 10:51:48.160171 ==
3205 10:51:48.160253 RX Vref Scan: 0
3206 10:51:48.160323
3207 10:51:48.163103 RX Vref 0 -> 0, step: 1
3208 10:51:48.163180
3209 10:51:48.166160 RX Delay -40 -> 252, step: 8
3210 10:51:48.169248 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3211 10:51:48.172927 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3212 10:51:48.175888 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3213 10:51:48.179507 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3214 10:51:48.186070 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3215 10:51:48.189516 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3216 10:51:48.192888 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3217 10:51:48.196237 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3218 10:51:48.199160 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3219 10:51:48.202368 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3220 10:51:48.209563 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3221 10:51:48.212726 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3222 10:51:48.215952 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3223 10:51:48.219056 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3224 10:51:48.225917 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3225 10:51:48.229109 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3226 10:51:48.229206 ==
3227 10:51:48.232776 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 10:51:48.235896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 10:51:48.235974 ==
3230 10:51:48.238957 DQS Delay:
3231 10:51:48.239035 DQS0 = 0, DQS1 = 0
3232 10:51:48.239099 DQM Delay:
3233 10:51:48.242092 DQM0 = 113, DQM1 = 106
3234 10:51:48.242166 DQ Delay:
3235 10:51:48.245775 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =111
3236 10:51:48.249245 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3237 10:51:48.252254 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3238 10:51:48.259074 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3239 10:51:48.259182
3240 10:51:48.259266
3241 10:51:48.259326 ==
3242 10:51:48.262031 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 10:51:48.265633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 10:51:48.265712 ==
3245 10:51:48.265775
3246 10:51:48.265833
3247 10:51:48.268816 TX Vref Scan disable
3248 10:51:48.268892 == TX Byte 0 ==
3249 10:51:48.275586 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3250 10:51:48.278858 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3251 10:51:48.278935 == TX Byte 1 ==
3252 10:51:48.285257 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3253 10:51:48.288533 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3254 10:51:48.288616 ==
3255 10:51:48.291824 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 10:51:48.295350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 10:51:48.295433 ==
3258 10:51:48.308304 TX Vref=22, minBit 1, minWin=25, winSum=414
3259 10:51:48.311686 TX Vref=24, minBit 8, minWin=25, winSum=419
3260 10:51:48.315050 TX Vref=26, minBit 8, minWin=25, winSum=428
3261 10:51:48.318227 TX Vref=28, minBit 1, minWin=26, winSum=428
3262 10:51:48.321368 TX Vref=30, minBit 3, minWin=26, winSum=430
3263 10:51:48.328274 TX Vref=32, minBit 0, minWin=26, winSum=427
3264 10:51:48.331596 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 30
3265 10:51:48.331681
3266 10:51:48.335187 Final TX Range 1 Vref 30
3267 10:51:48.335270
3268 10:51:48.335336 ==
3269 10:51:48.338273 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 10:51:48.341378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 10:51:48.341462 ==
3272 10:51:48.344439
3273 10:51:48.344521
3274 10:51:48.344585 TX Vref Scan disable
3275 10:51:48.348204 == TX Byte 0 ==
3276 10:51:48.351156 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3277 10:51:48.358089 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3278 10:51:48.358173 == TX Byte 1 ==
3279 10:51:48.361053 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3280 10:51:48.367772 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3281 10:51:48.367855
3282 10:51:48.367920 [DATLAT]
3283 10:51:48.367979 Freq=1200, CH1 RK0
3284 10:51:48.368037
3285 10:51:48.371278 DATLAT Default: 0xd
3286 10:51:48.374515 0, 0xFFFF, sum = 0
3287 10:51:48.374600 1, 0xFFFF, sum = 0
3288 10:51:48.377905 2, 0xFFFF, sum = 0
3289 10:51:48.377988 3, 0xFFFF, sum = 0
3290 10:51:48.381024 4, 0xFFFF, sum = 0
3291 10:51:48.381112 5, 0xFFFF, sum = 0
3292 10:51:48.384668 6, 0xFFFF, sum = 0
3293 10:51:48.384788 7, 0xFFFF, sum = 0
3294 10:51:48.387802 8, 0xFFFF, sum = 0
3295 10:51:48.387885 9, 0xFFFF, sum = 0
3296 10:51:48.390841 10, 0xFFFF, sum = 0
3297 10:51:48.390976 11, 0xFFFF, sum = 0
3298 10:51:48.394457 12, 0x0, sum = 1
3299 10:51:48.394539 13, 0x0, sum = 2
3300 10:51:48.398019 14, 0x0, sum = 3
3301 10:51:48.398102 15, 0x0, sum = 4
3302 10:51:48.400698 best_step = 13
3303 10:51:48.400768
3304 10:51:48.400828 ==
3305 10:51:48.404262 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 10:51:48.407656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 10:51:48.407741 ==
3308 10:51:48.407805 RX Vref Scan: 1
3309 10:51:48.411300
3310 10:51:48.411380 Set Vref Range= 32 -> 127
3311 10:51:48.411444
3312 10:51:48.414399 RX Vref 32 -> 127, step: 1
3313 10:51:48.414480
3314 10:51:48.417366 RX Delay -21 -> 252, step: 4
3315 10:51:48.417447
3316 10:51:48.420734 Set Vref, RX VrefLevel [Byte0]: 32
3317 10:51:48.423743 [Byte1]: 32
3318 10:51:48.423826
3319 10:51:48.427449 Set Vref, RX VrefLevel [Byte0]: 33
3320 10:51:48.430752 [Byte1]: 33
3321 10:51:48.434761
3322 10:51:48.434900 Set Vref, RX VrefLevel [Byte0]: 34
3323 10:51:48.438002 [Byte1]: 34
3324 10:51:48.442364
3325 10:51:48.442444 Set Vref, RX VrefLevel [Byte0]: 35
3326 10:51:48.445455 [Byte1]: 35
3327 10:51:48.450489
3328 10:51:48.450570 Set Vref, RX VrefLevel [Byte0]: 36
3329 10:51:48.453566 [Byte1]: 36
3330 10:51:48.458110
3331 10:51:48.458191 Set Vref, RX VrefLevel [Byte0]: 37
3332 10:51:48.461761 [Byte1]: 37
3333 10:51:48.465994
3334 10:51:48.466102 Set Vref, RX VrefLevel [Byte0]: 38
3335 10:51:48.469719 [Byte1]: 38
3336 10:51:48.473870
3337 10:51:48.473951 Set Vref, RX VrefLevel [Byte0]: 39
3338 10:51:48.477351 [Byte1]: 39
3339 10:51:48.482150
3340 10:51:48.482230 Set Vref, RX VrefLevel [Byte0]: 40
3341 10:51:48.485811 [Byte1]: 40
3342 10:51:48.490089
3343 10:51:48.490169 Set Vref, RX VrefLevel [Byte0]: 41
3344 10:51:48.493194 [Byte1]: 41
3345 10:51:48.497990
3346 10:51:48.498070 Set Vref, RX VrefLevel [Byte0]: 42
3347 10:51:48.500981 [Byte1]: 42
3348 10:51:48.505879
3349 10:51:48.505960 Set Vref, RX VrefLevel [Byte0]: 43
3350 10:51:48.509316 [Byte1]: 43
3351 10:51:48.513922
3352 10:51:48.514010 Set Vref, RX VrefLevel [Byte0]: 44
3353 10:51:48.516983 [Byte1]: 44
3354 10:51:48.521744
3355 10:51:48.524775 Set Vref, RX VrefLevel [Byte0]: 45
3356 10:51:48.528202 [Byte1]: 45
3357 10:51:48.528282
3358 10:51:48.531668 Set Vref, RX VrefLevel [Byte0]: 46
3359 10:51:48.534901 [Byte1]: 46
3360 10:51:48.534983
3361 10:51:48.537989 Set Vref, RX VrefLevel [Byte0]: 47
3362 10:51:48.541090 [Byte1]: 47
3363 10:51:48.545485
3364 10:51:48.545584 Set Vref, RX VrefLevel [Byte0]: 48
3365 10:51:48.548648 [Byte1]: 48
3366 10:51:48.553760
3367 10:51:48.553851 Set Vref, RX VrefLevel [Byte0]: 49
3368 10:51:48.556818 [Byte1]: 49
3369 10:51:48.561509
3370 10:51:48.561589 Set Vref, RX VrefLevel [Byte0]: 50
3371 10:51:48.564828 [Byte1]: 50
3372 10:51:48.569525
3373 10:51:48.569616 Set Vref, RX VrefLevel [Byte0]: 51
3374 10:51:48.572798 [Byte1]: 51
3375 10:51:48.577346
3376 10:51:48.577425 Set Vref, RX VrefLevel [Byte0]: 52
3377 10:51:48.580275 [Byte1]: 52
3378 10:51:48.585176
3379 10:51:48.585273 Set Vref, RX VrefLevel [Byte0]: 53
3380 10:51:48.588190 [Byte1]: 53
3381 10:51:48.592737
3382 10:51:48.592814 Set Vref, RX VrefLevel [Byte0]: 54
3383 10:51:48.596518 [Byte1]: 54
3384 10:51:48.600877
3385 10:51:48.600951 Set Vref, RX VrefLevel [Byte0]: 55
3386 10:51:48.604511 [Byte1]: 55
3387 10:51:48.608872
3388 10:51:48.608946 Set Vref, RX VrefLevel [Byte0]: 56
3389 10:51:48.611915 [Byte1]: 56
3390 10:51:48.616606
3391 10:51:48.616692 Set Vref, RX VrefLevel [Byte0]: 57
3392 10:51:48.620126 [Byte1]: 57
3393 10:51:48.624435
3394 10:51:48.624513 Set Vref, RX VrefLevel [Byte0]: 58
3395 10:51:48.627808 [Byte1]: 58
3396 10:51:48.632685
3397 10:51:48.632764 Set Vref, RX VrefLevel [Byte0]: 59
3398 10:51:48.636023 [Byte1]: 59
3399 10:51:48.640538
3400 10:51:48.640665 Set Vref, RX VrefLevel [Byte0]: 60
3401 10:51:48.643668 [Byte1]: 60
3402 10:51:48.648606
3403 10:51:48.648713 Set Vref, RX VrefLevel [Byte0]: 61
3404 10:51:48.651688 [Byte1]: 61
3405 10:51:48.656071
3406 10:51:48.656160 Set Vref, RX VrefLevel [Byte0]: 62
3407 10:51:48.659780 [Byte1]: 62
3408 10:51:48.664019
3409 10:51:48.664095 Set Vref, RX VrefLevel [Byte0]: 63
3410 10:51:48.667603 [Byte1]: 63
3411 10:51:48.672004
3412 10:51:48.672078 Set Vref, RX VrefLevel [Byte0]: 64
3413 10:51:48.675656 [Byte1]: 64
3414 10:51:48.680032
3415 10:51:48.680107 Set Vref, RX VrefLevel [Byte0]: 65
3416 10:51:48.683131 [Byte1]: 65
3417 10:51:48.688036
3418 10:51:48.688155 Set Vref, RX VrefLevel [Byte0]: 66
3419 10:51:48.691105 [Byte1]: 66
3420 10:51:48.695756
3421 10:51:48.695840 Final RX Vref Byte 0 = 58 to rank0
3422 10:51:48.699159 Final RX Vref Byte 1 = 52 to rank0
3423 10:51:48.702306 Final RX Vref Byte 0 = 58 to rank1
3424 10:51:48.705926 Final RX Vref Byte 1 = 52 to rank1==
3425 10:51:48.709008 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 10:51:48.715798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 10:51:48.715880 ==
3428 10:51:48.715944 DQS Delay:
3429 10:51:48.716002 DQS0 = 0, DQS1 = 0
3430 10:51:48.718892 DQM Delay:
3431 10:51:48.718973 DQM0 = 113, DQM1 = 106
3432 10:51:48.722388 DQ Delay:
3433 10:51:48.725893 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3434 10:51:48.728807 DQ4 =110, DQ5 =124, DQ6 =124, DQ7 =112
3435 10:51:48.732360 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =102
3436 10:51:48.735850 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3437 10:51:48.735932
3438 10:51:48.735996
3439 10:51:48.745485 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3440 10:51:48.745596 CH1 RK0: MR19=303, MR18=EDF3
3441 10:51:48.752434 CH1_RK0: MR19=0x303, MR18=0xEDF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3442 10:51:48.752516
3443 10:51:48.755532 ----->DramcWriteLeveling(PI) begin...
3444 10:51:48.755644 ==
3445 10:51:48.758634 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 10:51:48.765388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 10:51:48.765471 ==
3448 10:51:48.768958 Write leveling (Byte 0): 24 => 24
3449 10:51:48.769040 Write leveling (Byte 1): 29 => 29
3450 10:51:48.771977 DramcWriteLeveling(PI) end<-----
3451 10:51:48.772059
3452 10:51:48.772153 ==
3453 10:51:48.775124 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 10:51:48.781912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 10:51:48.781995 ==
3456 10:51:48.785499 [Gating] SW mode calibration
3457 10:51:48.791865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 10:51:48.795003 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 10:51:48.802018 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3460 10:51:48.805344 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 10:51:48.808408 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 10:51:48.815091 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 10:51:48.818280 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 10:51:48.822046 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 10:51:48.828324 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
3466 10:51:48.831971 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3467 10:51:48.835106 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 10:51:48.841587 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 10:51:48.844911 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 10:51:48.848394 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 10:51:48.854729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 10:51:48.857913 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3473 10:51:48.861141 1 0 24 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3474 10:51:48.867835 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3475 10:51:48.871019 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 10:51:48.874560 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 10:51:48.881353 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 10:51:48.884444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 10:51:48.887576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 10:51:48.894286 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3481 10:51:48.897783 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 10:51:48.901067 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3483 10:51:48.907747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 10:51:48.910626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 10:51:48.913737 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 10:51:48.920376 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 10:51:48.924225 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 10:51:48.927544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 10:51:48.933711 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 10:51:48.937410 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 10:51:48.940322 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 10:51:48.946804 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 10:51:48.950319 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 10:51:48.953796 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 10:51:48.959996 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 10:51:48.963574 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3497 10:51:48.966606 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3498 10:51:48.973546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 10:51:48.973631 Total UI for P1: 0, mck2ui 16
3500 10:51:48.980007 best dqsien dly found for B0: ( 1, 3, 22)
3501 10:51:48.980120 Total UI for P1: 0, mck2ui 16
3502 10:51:48.986592 best dqsien dly found for B1: ( 1, 3, 22)
3503 10:51:48.989724 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3504 10:51:48.992830 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3505 10:51:48.992948
3506 10:51:48.996539 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3507 10:51:48.999726 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 10:51:49.003175 [Gating] SW calibration Done
3509 10:51:49.003281 ==
3510 10:51:49.006098 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 10:51:49.009602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 10:51:49.009716 ==
3513 10:51:49.012747 RX Vref Scan: 0
3514 10:51:49.012829
3515 10:51:49.012907 RX Vref 0 -> 0, step: 1
3516 10:51:49.012969
3517 10:51:49.016172 RX Delay -40 -> 252, step: 8
3518 10:51:49.022896 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3519 10:51:49.025872 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3520 10:51:49.029595 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3521 10:51:49.032503 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3522 10:51:49.036147 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3523 10:51:49.039111 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3524 10:51:49.045950 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3525 10:51:49.049018 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3526 10:51:49.052436 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3527 10:51:49.055910 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3528 10:51:49.058796 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3529 10:51:49.065567 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3530 10:51:49.068888 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3531 10:51:49.072279 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3532 10:51:49.075425 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3533 10:51:49.082105 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3534 10:51:49.082214 ==
3535 10:51:49.085067 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 10:51:49.088880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 10:51:49.088985 ==
3538 10:51:49.089080 DQS Delay:
3539 10:51:49.092000 DQS0 = 0, DQS1 = 0
3540 10:51:49.092100 DQM Delay:
3541 10:51:49.095119 DQM0 = 110, DQM1 = 108
3542 10:51:49.095222 DQ Delay:
3543 10:51:49.098396 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3544 10:51:49.102075 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3545 10:51:49.104999 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3546 10:51:49.108596 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =115
3547 10:51:49.108699
3548 10:51:49.108792
3549 10:51:49.111509 ==
3550 10:51:49.115125 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 10:51:49.118123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 10:51:49.118234 ==
3553 10:51:49.118335
3554 10:51:49.118436
3555 10:51:49.121724 TX Vref Scan disable
3556 10:51:49.121833 == TX Byte 0 ==
3557 10:51:49.128152 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3558 10:51:49.131839 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3559 10:51:49.131947 == TX Byte 1 ==
3560 10:51:49.137921 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3561 10:51:49.141675 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3562 10:51:49.141797 ==
3563 10:51:49.144791 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 10:51:49.147894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 10:51:49.147996 ==
3566 10:51:49.160644 TX Vref=22, minBit 0, minWin=25, winSum=425
3567 10:51:49.164042 TX Vref=24, minBit 0, minWin=26, winSum=429
3568 10:51:49.167121 TX Vref=26, minBit 1, minWin=26, winSum=429
3569 10:51:49.170773 TX Vref=28, minBit 4, minWin=26, winSum=434
3570 10:51:49.174131 TX Vref=30, minBit 1, minWin=26, winSum=433
3571 10:51:49.180572 TX Vref=32, minBit 3, minWin=26, winSum=433
3572 10:51:49.184151 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 28
3573 10:51:49.184270
3574 10:51:49.187463 Final TX Range 1 Vref 28
3575 10:51:49.187565
3576 10:51:49.187657 ==
3577 10:51:49.190151 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 10:51:49.193889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 10:51:49.197054 ==
3580 10:51:49.197154
3581 10:51:49.197246
3582 10:51:49.197333 TX Vref Scan disable
3583 10:51:49.200121 == TX Byte 0 ==
3584 10:51:49.203374 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3585 10:51:49.210152 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3586 10:51:49.210239 == TX Byte 1 ==
3587 10:51:49.213593 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3588 10:51:49.220367 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3589 10:51:49.220449
3590 10:51:49.220513 [DATLAT]
3591 10:51:49.220574 Freq=1200, CH1 RK1
3592 10:51:49.220632
3593 10:51:49.223464 DATLAT Default: 0xd
3594 10:51:49.226516 0, 0xFFFF, sum = 0
3595 10:51:49.226599 1, 0xFFFF, sum = 0
3596 10:51:49.230059 2, 0xFFFF, sum = 0
3597 10:51:49.230141 3, 0xFFFF, sum = 0
3598 10:51:49.233573 4, 0xFFFF, sum = 0
3599 10:51:49.233656 5, 0xFFFF, sum = 0
3600 10:51:49.237004 6, 0xFFFF, sum = 0
3601 10:51:49.237087 7, 0xFFFF, sum = 0
3602 10:51:49.239813 8, 0xFFFF, sum = 0
3603 10:51:49.239896 9, 0xFFFF, sum = 0
3604 10:51:49.243389 10, 0xFFFF, sum = 0
3605 10:51:49.243477 11, 0xFFFF, sum = 0
3606 10:51:49.246342 12, 0x0, sum = 1
3607 10:51:49.246425 13, 0x0, sum = 2
3608 10:51:49.250042 14, 0x0, sum = 3
3609 10:51:49.250124 15, 0x0, sum = 4
3610 10:51:49.253217 best_step = 13
3611 10:51:49.253298
3612 10:51:49.253362 ==
3613 10:51:49.256439 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 10:51:49.259571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 10:51:49.259653 ==
3616 10:51:49.262970 RX Vref Scan: 0
3617 10:51:49.263051
3618 10:51:49.263115 RX Vref 0 -> 0, step: 1
3619 10:51:49.263174
3620 10:51:49.266604 RX Delay -21 -> 252, step: 4
3621 10:51:49.273153 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3622 10:51:49.276015 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3623 10:51:49.279209 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3624 10:51:49.282480 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3625 10:51:49.285799 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3626 10:51:49.292641 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3627 10:51:49.295601 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3628 10:51:49.299332 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3629 10:51:49.302562 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3630 10:51:49.305594 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3631 10:51:49.312417 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3632 10:51:49.315448 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3633 10:51:49.319061 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3634 10:51:49.322365 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3635 10:51:49.328780 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3636 10:51:49.331888 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3637 10:51:49.331970 ==
3638 10:51:49.335466 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 10:51:49.338387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 10:51:49.338468 ==
3641 10:51:49.342177 DQS Delay:
3642 10:51:49.342259 DQS0 = 0, DQS1 = 0
3643 10:51:49.342323 DQM Delay:
3644 10:51:49.345144 DQM0 = 112, DQM1 = 109
3645 10:51:49.345226 DQ Delay:
3646 10:51:49.348446 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =110
3647 10:51:49.351492 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3648 10:51:49.358268 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3649 10:51:49.361453 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3650 10:51:49.361534
3651 10:51:49.361598
3652 10:51:49.368174 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3653 10:51:49.371363 CH1 RK1: MR19=304, MR18=F808
3654 10:51:49.377964 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3655 10:51:49.381373 [RxdqsGatingPostProcess] freq 1200
3656 10:51:49.387841 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 10:51:49.387940 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 10:51:49.391619 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 10:51:49.394304 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 10:51:49.397945 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 10:51:49.401209 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 10:51:49.404285 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 10:51:49.408135 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 10:51:49.411290 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 10:51:49.414364 Pre-setting of DQS Precalculation
3666 10:51:49.421145 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 10:51:49.427818 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 10:51:49.434303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 10:51:49.434399
3670 10:51:49.434495
3671 10:51:49.437467 [Calibration Summary] 2400 Mbps
3672 10:51:49.437550 CH 0, Rank 0
3673 10:51:49.440722 SW Impedance : PASS
3674 10:51:49.443908 DUTY Scan : NO K
3675 10:51:49.443985 ZQ Calibration : PASS
3676 10:51:49.447202 Jitter Meter : NO K
3677 10:51:49.450755 CBT Training : PASS
3678 10:51:49.450854 Write leveling : PASS
3679 10:51:49.453686 RX DQS gating : PASS
3680 10:51:49.457084 RX DQ/DQS(RDDQC) : PASS
3681 10:51:49.457168 TX DQ/DQS : PASS
3682 10:51:49.460273 RX DATLAT : PASS
3683 10:51:49.463935 RX DQ/DQS(Engine): PASS
3684 10:51:49.464038 TX OE : NO K
3685 10:51:49.464134 All Pass.
3686 10:51:49.464199
3687 10:51:49.467022 CH 0, Rank 1
3688 10:51:49.470715 SW Impedance : PASS
3689 10:51:49.470834 DUTY Scan : NO K
3690 10:51:49.473805 ZQ Calibration : PASS
3691 10:51:49.473909 Jitter Meter : NO K
3692 10:51:49.476987 CBT Training : PASS
3693 10:51:49.480107 Write leveling : PASS
3694 10:51:49.480189 RX DQS gating : PASS
3695 10:51:49.483646 RX DQ/DQS(RDDQC) : PASS
3696 10:51:49.486569 TX DQ/DQS : PASS
3697 10:51:49.486673 RX DATLAT : PASS
3698 10:51:49.490145 RX DQ/DQS(Engine): PASS
3699 10:51:49.493089 TX OE : NO K
3700 10:51:49.493175 All Pass.
3701 10:51:49.493242
3702 10:51:49.493303 CH 1, Rank 0
3703 10:51:49.496451 SW Impedance : PASS
3704 10:51:49.499979 DUTY Scan : NO K
3705 10:51:49.500064 ZQ Calibration : PASS
3706 10:51:49.503430 Jitter Meter : NO K
3707 10:51:49.506334 CBT Training : PASS
3708 10:51:49.506413 Write leveling : PASS
3709 10:51:49.510137 RX DQS gating : PASS
3710 10:51:49.513287 RX DQ/DQS(RDDQC) : PASS
3711 10:51:49.513371 TX DQ/DQS : PASS
3712 10:51:49.516355 RX DATLAT : PASS
3713 10:51:49.519982 RX DQ/DQS(Engine): PASS
3714 10:51:49.520066 TX OE : NO K
3715 10:51:49.523069 All Pass.
3716 10:51:49.523152
3717 10:51:49.523218 CH 1, Rank 1
3718 10:51:49.526026 SW Impedance : PASS
3719 10:51:49.526113 DUTY Scan : NO K
3720 10:51:49.529767 ZQ Calibration : PASS
3721 10:51:49.532961 Jitter Meter : NO K
3722 10:51:49.533045 CBT Training : PASS
3723 10:51:49.536020 Write leveling : PASS
3724 10:51:49.539519 RX DQS gating : PASS
3725 10:51:49.539603 RX DQ/DQS(RDDQC) : PASS
3726 10:51:49.542577 TX DQ/DQS : PASS
3727 10:51:49.546482 RX DATLAT : PASS
3728 10:51:49.546561 RX DQ/DQS(Engine): PASS
3729 10:51:49.549258 TX OE : NO K
3730 10:51:49.549342 All Pass.
3731 10:51:49.549408
3732 10:51:49.552829 DramC Write-DBI off
3733 10:51:49.556162 PER_BANK_REFRESH: Hybrid Mode
3734 10:51:49.556245 TX_TRACKING: ON
3735 10:51:49.565832 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 10:51:49.568966 [FAST_K] Save calibration result to emmc
3737 10:51:49.572010 dramc_set_vcore_voltage set vcore to 650000
3738 10:51:49.575596 Read voltage for 600, 5
3739 10:51:49.575677 Vio18 = 0
3740 10:51:49.575741 Vcore = 650000
3741 10:51:49.578680 Vdram = 0
3742 10:51:49.578761 Vddq = 0
3743 10:51:49.578825 Vmddr = 0
3744 10:51:49.585666 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 10:51:49.588618 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 10:51:49.591738 MEM_TYPE=3, freq_sel=19
3747 10:51:49.595213 sv_algorithm_assistance_LP4_1600
3748 10:51:49.598530 ============ PULL DRAM RESETB DOWN ============
3749 10:51:49.601968 ========== PULL DRAM RESETB DOWN end =========
3750 10:51:49.608469 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 10:51:49.611777 ===================================
3752 10:51:49.614812 LPDDR4 DRAM CONFIGURATION
3753 10:51:49.618632 ===================================
3754 10:51:49.618732 EX_ROW_EN[0] = 0x0
3755 10:51:49.621806 EX_ROW_EN[1] = 0x0
3756 10:51:49.621903 LP4Y_EN = 0x0
3757 10:51:49.624865 WORK_FSP = 0x0
3758 10:51:49.624958 WL = 0x2
3759 10:51:49.628477 RL = 0x2
3760 10:51:49.628550 BL = 0x2
3761 10:51:49.631385 RPST = 0x0
3762 10:51:49.631456 RD_PRE = 0x0
3763 10:51:49.634588 WR_PRE = 0x1
3764 10:51:49.634682 WR_PST = 0x0
3765 10:51:49.638339 DBI_WR = 0x0
3766 10:51:49.641423 DBI_RD = 0x0
3767 10:51:49.641518 OTF = 0x1
3768 10:51:49.644484 ===================================
3769 10:51:49.647530 ===================================
3770 10:51:49.650865 ANA top config
3771 10:51:49.654405 ===================================
3772 10:51:49.654506 DLL_ASYNC_EN = 0
3773 10:51:49.657496 ALL_SLAVE_EN = 1
3774 10:51:49.661226 NEW_RANK_MODE = 1
3775 10:51:49.664269 DLL_IDLE_MODE = 1
3776 10:51:49.664340 LP45_APHY_COMB_EN = 1
3777 10:51:49.667392 TX_ODT_DIS = 1
3778 10:51:49.670747 NEW_8X_MODE = 1
3779 10:51:49.674320 ===================================
3780 10:51:49.677338 ===================================
3781 10:51:49.680907 data_rate = 1200
3782 10:51:49.684072 CKR = 1
3783 10:51:49.687083 DQ_P2S_RATIO = 8
3784 10:51:49.690348 ===================================
3785 10:51:49.690443 CA_P2S_RATIO = 8
3786 10:51:49.693482 DQ_CA_OPEN = 0
3787 10:51:49.697177 DQ_SEMI_OPEN = 0
3788 10:51:49.700144 CA_SEMI_OPEN = 0
3789 10:51:49.703605 CA_FULL_RATE = 0
3790 10:51:49.706940 DQ_CKDIV4_EN = 1
3791 10:51:49.707037 CA_CKDIV4_EN = 1
3792 10:51:49.710263 CA_PREDIV_EN = 0
3793 10:51:49.713079 PH8_DLY = 0
3794 10:51:49.716737 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 10:51:49.719855 DQ_AAMCK_DIV = 4
3796 10:51:49.723378 CA_AAMCK_DIV = 4
3797 10:51:49.726376 CA_ADMCK_DIV = 4
3798 10:51:49.726477 DQ_TRACK_CA_EN = 0
3799 10:51:49.729493 CA_PICK = 600
3800 10:51:49.733053 CA_MCKIO = 600
3801 10:51:49.736115 MCKIO_SEMI = 0
3802 10:51:49.739414 PLL_FREQ = 2288
3803 10:51:49.742578 DQ_UI_PI_RATIO = 32
3804 10:51:49.746356 CA_UI_PI_RATIO = 0
3805 10:51:49.749538 ===================================
3806 10:51:49.752563 ===================================
3807 10:51:49.752637 memory_type:LPDDR4
3808 10:51:49.756184 GP_NUM : 10
3809 10:51:49.759550 SRAM_EN : 1
3810 10:51:49.759627 MD32_EN : 0
3811 10:51:49.762551 ===================================
3812 10:51:49.766056 [ANA_INIT] >>>>>>>>>>>>>>
3813 10:51:49.768876 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 10:51:49.772397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 10:51:49.775678 ===================================
3816 10:51:49.779008 data_rate = 1200,PCW = 0X5800
3817 10:51:49.781920 ===================================
3818 10:51:49.785674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 10:51:49.788903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 10:51:49.795203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 10:51:49.802033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 10:51:49.805194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 10:51:49.808676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 10:51:49.808751 [ANA_INIT] flow start
3825 10:51:49.811545 [ANA_INIT] PLL >>>>>>>>
3826 10:51:49.815150 [ANA_INIT] PLL <<<<<<<<
3827 10:51:49.815250 [ANA_INIT] MIDPI >>>>>>>>
3828 10:51:49.818044 [ANA_INIT] MIDPI <<<<<<<<
3829 10:51:49.821349 [ANA_INIT] DLL >>>>>>>>
3830 10:51:49.821452 [ANA_INIT] flow end
3831 10:51:49.828218 ============ LP4 DIFF to SE enter ============
3832 10:51:49.831124 ============ LP4 DIFF to SE exit ============
3833 10:51:49.834811 [ANA_INIT] <<<<<<<<<<<<<
3834 10:51:49.837832 [Flow] Enable top DCM control >>>>>
3835 10:51:49.841431 [Flow] Enable top DCM control <<<<<
3836 10:51:49.844507 Enable DLL master slave shuffle
3837 10:51:49.847668 ==============================================================
3838 10:51:49.851609 Gating Mode config
3839 10:51:49.854373 ==============================================================
3840 10:51:49.857518 Config description:
3841 10:51:49.867604 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 10:51:49.874427 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 10:51:49.877416 SELPH_MODE 0: By rank 1: By Phase
3844 10:51:49.884203 ==============================================================
3845 10:51:49.887731 GAT_TRACK_EN = 1
3846 10:51:49.890339 RX_GATING_MODE = 2
3847 10:51:49.893858 RX_GATING_TRACK_MODE = 2
3848 10:51:49.897001 SELPH_MODE = 1
3849 10:51:49.900820 PICG_EARLY_EN = 1
3850 10:51:49.903853 VALID_LAT_VALUE = 1
3851 10:51:49.906979 ==============================================================
3852 10:51:49.910683 Enter into Gating configuration >>>>
3853 10:51:49.913610 Exit from Gating configuration <<<<
3854 10:51:49.917056 Enter into DVFS_PRE_config >>>>>
3855 10:51:49.929867 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 10:51:49.933189 Exit from DVFS_PRE_config <<<<<
3857 10:51:49.933295 Enter into PICG configuration >>>>
3858 10:51:49.936750 Exit from PICG configuration <<<<
3859 10:51:49.940225 [RX_INPUT] configuration >>>>>
3860 10:51:49.943088 [RX_INPUT] configuration <<<<<
3861 10:51:49.950012 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 10:51:49.953327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 10:51:49.959292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 10:51:49.966053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 10:51:49.972851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 10:51:49.979360 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 10:51:49.982476 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 10:51:49.986483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 10:51:49.992562 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 10:51:49.995925 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 10:51:49.999223 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 10:51:50.002328 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 10:51:50.005929 ===================================
3874 10:51:50.009083 LPDDR4 DRAM CONFIGURATION
3875 10:51:50.012249 ===================================
3876 10:51:50.015839 EX_ROW_EN[0] = 0x0
3877 10:51:50.015913 EX_ROW_EN[1] = 0x0
3878 10:51:50.018696 LP4Y_EN = 0x0
3879 10:51:50.018795 WORK_FSP = 0x0
3880 10:51:50.022394 WL = 0x2
3881 10:51:50.022491 RL = 0x2
3882 10:51:50.025377 BL = 0x2
3883 10:51:50.025450 RPST = 0x0
3884 10:51:50.028498 RD_PRE = 0x0
3885 10:51:50.032103 WR_PRE = 0x1
3886 10:51:50.032187 WR_PST = 0x0
3887 10:51:50.035424 DBI_WR = 0x0
3888 10:51:50.035506 DBI_RD = 0x0
3889 10:51:50.038941 OTF = 0x1
3890 10:51:50.041845 ===================================
3891 10:51:50.045247 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 10:51:50.048649 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 10:51:50.052121 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 10:51:50.055274 ===================================
3895 10:51:50.058379 LPDDR4 DRAM CONFIGURATION
3896 10:51:50.062025 ===================================
3897 10:51:50.065147 EX_ROW_EN[0] = 0x10
3898 10:51:50.065228 EX_ROW_EN[1] = 0x0
3899 10:51:50.068250 LP4Y_EN = 0x0
3900 10:51:50.068332 WORK_FSP = 0x0
3901 10:51:50.071462 WL = 0x2
3902 10:51:50.074936 RL = 0x2
3903 10:51:50.075018 BL = 0x2
3904 10:51:50.077886 RPST = 0x0
3905 10:51:50.077968 RD_PRE = 0x0
3906 10:51:50.081231 WR_PRE = 0x1
3907 10:51:50.081312 WR_PST = 0x0
3908 10:51:50.084799 DBI_WR = 0x0
3909 10:51:50.084881 DBI_RD = 0x0
3910 10:51:50.088005 OTF = 0x1
3911 10:51:50.090993 ===================================
3912 10:51:50.097845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 10:51:50.101049 nWR fixed to 30
3914 10:51:50.101131 [ModeRegInit_LP4] CH0 RK0
3915 10:51:50.103956 [ModeRegInit_LP4] CH0 RK1
3916 10:51:50.107640 [ModeRegInit_LP4] CH1 RK0
3917 10:51:50.110766 [ModeRegInit_LP4] CH1 RK1
3918 10:51:50.110886 match AC timing 17
3919 10:51:50.117956 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 10:51:50.120849 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 10:51:50.124198 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 10:51:50.130433 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 10:51:50.134314 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 10:51:50.134397 ==
3925 10:51:50.137269 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 10:51:50.140187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 10:51:50.140273 ==
3928 10:51:50.146903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 10:51:50.153390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3930 10:51:50.156709 [CA 0] Center 37 (7~67) winsize 61
3931 10:51:50.160048 [CA 1] Center 36 (6~67) winsize 62
3932 10:51:50.163648 [CA 2] Center 35 (5~65) winsize 61
3933 10:51:50.167233 [CA 3] Center 35 (5~65) winsize 61
3934 10:51:50.170401 [CA 4] Center 34 (4~65) winsize 62
3935 10:51:50.173498 [CA 5] Center 34 (3~65) winsize 63
3936 10:51:50.173580
3937 10:51:50.176619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3938 10:51:50.176701
3939 10:51:50.180373 [CATrainingPosCal] consider 1 rank data
3940 10:51:50.183266 u2DelayCellTimex100 = 270/100 ps
3941 10:51:50.186453 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3942 10:51:50.190017 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3943 10:51:50.193611 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3944 10:51:50.196373 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 10:51:50.200128 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3946 10:51:50.206923 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3947 10:51:50.207005
3948 10:51:50.209622 CA PerBit enable=1, Macro0, CA PI delay=34
3949 10:51:50.209704
3950 10:51:50.213250 [CBTSetCACLKResult] CA Dly = 34
3951 10:51:50.213332 CS Dly: 5 (0~36)
3952 10:51:50.213397 ==
3953 10:51:50.216463 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 10:51:50.219564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 10:51:50.222950 ==
3956 10:51:50.226363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 10:51:50.232491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3958 10:51:50.235727 [CA 0] Center 37 (7~67) winsize 61
3959 10:51:50.238851 [CA 1] Center 36 (6~67) winsize 62
3960 10:51:50.242501 [CA 2] Center 35 (5~65) winsize 61
3961 10:51:50.245473 [CA 3] Center 35 (5~65) winsize 61
3962 10:51:50.248804 [CA 4] Center 34 (4~65) winsize 62
3963 10:51:50.252191 [CA 5] Center 34 (3~65) winsize 63
3964 10:51:50.252273
3965 10:51:50.255417 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3966 10:51:50.255524
3967 10:51:50.258888 [CATrainingPosCal] consider 2 rank data
3968 10:51:50.262377 u2DelayCellTimex100 = 270/100 ps
3969 10:51:50.265249 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3970 10:51:50.272196 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3971 10:51:50.275300 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3972 10:51:50.278393 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 10:51:50.281491 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3974 10:51:50.285149 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3975 10:51:50.285256
3976 10:51:50.288234 CA PerBit enable=1, Macro0, CA PI delay=34
3977 10:51:50.288318
3978 10:51:50.292122 [CBTSetCACLKResult] CA Dly = 34
3979 10:51:50.294594 CS Dly: 5 (0~37)
3980 10:51:50.294675
3981 10:51:50.298146 ----->DramcWriteLeveling(PI) begin...
3982 10:51:50.298229 ==
3983 10:51:50.301465 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 10:51:50.304798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 10:51:50.304881 ==
3986 10:51:50.307938 Write leveling (Byte 0): 31 => 31
3987 10:51:50.311639 Write leveling (Byte 1): 30 => 30
3988 10:51:50.314512 DramcWriteLeveling(PI) end<-----
3989 10:51:50.314594
3990 10:51:50.314657 ==
3991 10:51:50.318064 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 10:51:50.321392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 10:51:50.321475 ==
3994 10:51:50.324472 [Gating] SW mode calibration
3995 10:51:50.331132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 10:51:50.337943 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 10:51:50.341000 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 10:51:50.344141 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 10:51:50.350811 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 10:51:50.354548 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
4001 10:51:50.357440 0 9 16 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
4002 10:51:50.364368 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 10:51:50.367386 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 10:51:50.370958 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 10:51:50.377718 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 10:51:50.380948 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 10:51:50.384156 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 10:51:50.391061 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4009 10:51:50.394114 0 10 16 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
4010 10:51:50.397037 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 10:51:50.403882 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 10:51:50.407479 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 10:51:50.410981 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 10:51:50.416753 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 10:51:50.420316 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 10:51:50.423784 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 10:51:50.430061 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4018 10:51:50.433785 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 10:51:50.436796 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 10:51:50.443548 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 10:51:50.446825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 10:51:50.450385 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 10:51:50.456577 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 10:51:50.460115 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 10:51:50.463179 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 10:51:50.469907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 10:51:50.473475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 10:51:50.476730 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 10:51:50.483045 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 10:51:50.486751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 10:51:50.489881 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 10:51:50.496058 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4033 10:51:50.499799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 10:51:50.502792 Total UI for P1: 0, mck2ui 16
4035 10:51:50.506332 best dqsien dly found for B0: ( 0, 13, 12)
4036 10:51:50.509611 Total UI for P1: 0, mck2ui 16
4037 10:51:50.512855 best dqsien dly found for B1: ( 0, 13, 12)
4038 10:51:50.516210 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4039 10:51:50.519191 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4040 10:51:50.519277
4041 10:51:50.522271 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4042 10:51:50.528925 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4043 10:51:50.529007 [Gating] SW calibration Done
4044 10:51:50.529072 ==
4045 10:51:50.532522 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 10:51:50.538945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 10:51:50.539028 ==
4048 10:51:50.539093 RX Vref Scan: 0
4049 10:51:50.539153
4050 10:51:50.542572 RX Vref 0 -> 0, step: 1
4051 10:51:50.542654
4052 10:51:50.545773 RX Delay -230 -> 252, step: 16
4053 10:51:50.548935 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4054 10:51:50.552635 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4055 10:51:50.555758 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4056 10:51:50.562517 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4057 10:51:50.565559 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4058 10:51:50.569128 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4059 10:51:50.571934 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4060 10:51:50.578860 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4061 10:51:50.581783 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4062 10:51:50.585063 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4063 10:51:50.588540 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4064 10:51:50.595493 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4065 10:51:50.598637 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4066 10:51:50.601762 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4067 10:51:50.604975 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4068 10:51:50.611594 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4069 10:51:50.611677 ==
4070 10:51:50.615053 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 10:51:50.617875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 10:51:50.617985 ==
4073 10:51:50.618057 DQS Delay:
4074 10:51:50.621420 DQS0 = 0, DQS1 = 0
4075 10:51:50.621528 DQM Delay:
4076 10:51:50.624759 DQM0 = 38, DQM1 = 30
4077 10:51:50.624840 DQ Delay:
4078 10:51:50.627819 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4079 10:51:50.631414 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4080 10:51:50.634795 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4081 10:51:50.637883 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4082 10:51:50.637962
4083 10:51:50.638026
4084 10:51:50.638085 ==
4085 10:51:50.641362 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 10:51:50.644699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 10:51:50.647582 ==
4088 10:51:50.647659
4089 10:51:50.647722
4090 10:51:50.647780 TX Vref Scan disable
4091 10:51:50.651421 == TX Byte 0 ==
4092 10:51:50.654537 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4093 10:51:50.657685 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4094 10:51:50.660796 == TX Byte 1 ==
4095 10:51:50.664549 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4096 10:51:50.667943 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4097 10:51:50.670729 ==
4098 10:51:50.674307 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 10:51:50.677505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 10:51:50.677612 ==
4101 10:51:50.677685
4102 10:51:50.677744
4103 10:51:50.680561 TX Vref Scan disable
4104 10:51:50.683882 == TX Byte 0 ==
4105 10:51:50.687283 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4106 10:51:50.690772 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4107 10:51:50.694020 == TX Byte 1 ==
4108 10:51:50.697523 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4109 10:51:50.700631 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4110 10:51:50.700714
4111 10:51:50.700778 [DATLAT]
4112 10:51:50.703999 Freq=600, CH0 RK0
4113 10:51:50.704082
4114 10:51:50.707008 DATLAT Default: 0x9
4115 10:51:50.707090 0, 0xFFFF, sum = 0
4116 10:51:50.710199 1, 0xFFFF, sum = 0
4117 10:51:50.710283 2, 0xFFFF, sum = 0
4118 10:51:50.714179 3, 0xFFFF, sum = 0
4119 10:51:50.714279 4, 0xFFFF, sum = 0
4120 10:51:50.716863 5, 0xFFFF, sum = 0
4121 10:51:50.716946 6, 0xFFFF, sum = 0
4122 10:51:50.720331 7, 0xFFFF, sum = 0
4123 10:51:50.720414 8, 0x0, sum = 1
4124 10:51:50.723299 9, 0x0, sum = 2
4125 10:51:50.723382 10, 0x0, sum = 3
4126 10:51:50.726808 11, 0x0, sum = 4
4127 10:51:50.726930 best_step = 9
4128 10:51:50.726995
4129 10:51:50.727054 ==
4130 10:51:50.730149 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 10:51:50.733754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 10:51:50.733836 ==
4133 10:51:50.736881 RX Vref Scan: 1
4134 10:51:50.736962
4135 10:51:50.740397 RX Vref 0 -> 0, step: 1
4136 10:51:50.740478
4137 10:51:50.740543 RX Delay -195 -> 252, step: 8
4138 10:51:50.740603
4139 10:51:50.743493 Set Vref, RX VrefLevel [Byte0]: 63
4140 10:51:50.746687 [Byte1]: 58
4141 10:51:50.751501
4142 10:51:50.751582 Final RX Vref Byte 0 = 63 to rank0
4143 10:51:50.754624 Final RX Vref Byte 1 = 58 to rank0
4144 10:51:50.758154 Final RX Vref Byte 0 = 63 to rank1
4145 10:51:50.761306 Final RX Vref Byte 1 = 58 to rank1==
4146 10:51:50.764447 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 10:51:50.771248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 10:51:50.771330 ==
4149 10:51:50.771395 DQS Delay:
4150 10:51:50.774301 DQS0 = 0, DQS1 = 0
4151 10:51:50.774383 DQM Delay:
4152 10:51:50.774447 DQM0 = 36, DQM1 = 27
4153 10:51:50.777951 DQ Delay:
4154 10:51:50.780893 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4155 10:51:50.784403 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =48
4156 10:51:50.788150 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4157 10:51:50.791070 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4158 10:51:50.791151
4159 10:51:50.791215
4160 10:51:50.797773 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4161 10:51:50.801125 CH0 RK0: MR19=808, MR18=3838
4162 10:51:50.807538 CH0_RK0: MR19=0x808, MR18=0x3838, DQSOSC=399, MR23=63, INC=164, DEC=109
4163 10:51:50.807620
4164 10:51:50.810611 ----->DramcWriteLeveling(PI) begin...
4165 10:51:50.810694 ==
4166 10:51:50.813760 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 10:51:50.817363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 10:51:50.817449 ==
4169 10:51:50.820428 Write leveling (Byte 0): 36 => 36
4170 10:51:50.824122 Write leveling (Byte 1): 30 => 30
4171 10:51:50.827100 DramcWriteLeveling(PI) end<-----
4172 10:51:50.827182
4173 10:51:50.827245 ==
4174 10:51:50.830589 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 10:51:50.836944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 10:51:50.837026 ==
4177 10:51:50.837091 [Gating] SW mode calibration
4178 10:51:50.847014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4179 10:51:50.850125 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4180 10:51:50.853335 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 10:51:50.860037 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 10:51:50.863286 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 10:51:50.866598 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4184 10:51:50.873417 0 9 16 | B1->B0 | 2d2d 2424 | 1 1 | (1 1) (1 0)
4185 10:51:50.876567 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 10:51:50.879715 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 10:51:50.886309 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 10:51:50.890031 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 10:51:50.893226 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 10:51:50.899483 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 10:51:50.903018 0 10 12 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
4192 10:51:50.906446 0 10 16 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)
4193 10:51:50.912715 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 10:51:50.915917 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 10:51:50.919575 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 10:51:50.925799 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 10:51:50.928925 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 10:51:50.932508 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 10:51:50.938791 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4200 10:51:50.942148 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 10:51:50.945628 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 10:51:50.952192 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 10:51:50.955431 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 10:51:50.962043 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 10:51:50.965523 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 10:51:50.968587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 10:51:50.975104 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 10:51:50.978197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 10:51:50.981933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 10:51:50.988284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 10:51:50.991627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 10:51:50.994883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 10:51:51.001317 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 10:51:51.004904 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 10:51:51.008330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 10:51:51.014775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4217 10:51:51.014923 Total UI for P1: 0, mck2ui 16
4218 10:51:51.020968 best dqsien dly found for B0: ( 0, 13, 14)
4219 10:51:51.024664 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 10:51:51.027802 Total UI for P1: 0, mck2ui 16
4221 10:51:51.030929 best dqsien dly found for B1: ( 0, 13, 16)
4222 10:51:51.034581 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4223 10:51:51.037670 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4224 10:51:51.037771
4225 10:51:51.040776 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4226 10:51:51.044378 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4227 10:51:51.047341 [Gating] SW calibration Done
4228 10:51:51.047420 ==
4229 10:51:51.050723 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 10:51:51.057122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 10:51:51.057211 ==
4232 10:51:51.057294 RX Vref Scan: 0
4233 10:51:51.057371
4234 10:51:51.060272 RX Vref 0 -> 0, step: 1
4235 10:51:51.060347
4236 10:51:51.064045 RX Delay -230 -> 252, step: 16
4237 10:51:51.066999 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4238 10:51:51.070436 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4239 10:51:51.073568 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4240 10:51:51.080074 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4241 10:51:51.083819 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4242 10:51:51.086985 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4243 10:51:51.090105 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4244 10:51:51.096896 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4245 10:51:51.100351 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4246 10:51:51.103648 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4247 10:51:51.106590 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4248 10:51:51.113717 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4249 10:51:51.116351 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4250 10:51:51.119809 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4251 10:51:51.122991 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4252 10:51:51.129859 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4253 10:51:51.129941 ==
4254 10:51:51.132884 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 10:51:51.136644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 10:51:51.136741 ==
4257 10:51:51.136873 DQS Delay:
4258 10:51:51.139583 DQS0 = 0, DQS1 = 0
4259 10:51:51.139664 DQM Delay:
4260 10:51:51.142744 DQM0 = 38, DQM1 = 28
4261 10:51:51.142825 DQ Delay:
4262 10:51:51.146300 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4263 10:51:51.149367 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4264 10:51:51.152410 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4265 10:51:51.155973 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4266 10:51:51.156054
4267 10:51:51.156118
4268 10:51:51.156177 ==
4269 10:51:51.159485 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 10:51:51.162416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 10:51:51.166073 ==
4272 10:51:51.166154
4273 10:51:51.166218
4274 10:51:51.166277 TX Vref Scan disable
4275 10:51:51.169139 == TX Byte 0 ==
4276 10:51:51.172107 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4277 10:51:51.175742 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4278 10:51:51.179072 == TX Byte 1 ==
4279 10:51:51.182418 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4280 10:51:51.188740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4281 10:51:51.188822 ==
4282 10:51:51.191901 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 10:51:51.195570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 10:51:51.195652 ==
4285 10:51:51.195717
4286 10:51:51.195777
4287 10:51:51.198664 TX Vref Scan disable
4288 10:51:51.201818 == TX Byte 0 ==
4289 10:51:51.205318 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4290 10:51:51.208620 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4291 10:51:51.212102 == TX Byte 1 ==
4292 10:51:51.215018 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4293 10:51:51.218636 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4294 10:51:51.218717
4295 10:51:51.218779 [DATLAT]
4296 10:51:51.222060 Freq=600, CH0 RK1
4297 10:51:51.222162
4298 10:51:51.225077 DATLAT Default: 0x9
4299 10:51:51.225157 0, 0xFFFF, sum = 0
4300 10:51:51.228474 1, 0xFFFF, sum = 0
4301 10:51:51.228555 2, 0xFFFF, sum = 0
4302 10:51:51.231518 3, 0xFFFF, sum = 0
4303 10:51:51.231599 4, 0xFFFF, sum = 0
4304 10:51:51.235255 5, 0xFFFF, sum = 0
4305 10:51:51.235336 6, 0xFFFF, sum = 0
4306 10:51:51.238267 7, 0xFFFF, sum = 0
4307 10:51:51.238347 8, 0x0, sum = 1
4308 10:51:51.241433 9, 0x0, sum = 2
4309 10:51:51.241514 10, 0x0, sum = 3
4310 10:51:51.244623 11, 0x0, sum = 4
4311 10:51:51.244704 best_step = 9
4312 10:51:51.244767
4313 10:51:51.244824 ==
4314 10:51:51.248252 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 10:51:51.251441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 10:51:51.254425 ==
4317 10:51:51.254505 RX Vref Scan: 0
4318 10:51:51.254568
4319 10:51:51.257938 RX Vref 0 -> 0, step: 1
4320 10:51:51.258017
4321 10:51:51.261303 RX Delay -195 -> 252, step: 8
4322 10:51:51.264459 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4323 10:51:51.270734 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4324 10:51:51.274288 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4325 10:51:51.277314 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4326 10:51:51.280417 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4327 10:51:51.284100 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4328 10:51:51.290693 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4329 10:51:51.293814 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4330 10:51:51.297700 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4331 10:51:51.300573 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4332 10:51:51.306796 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4333 10:51:51.310562 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4334 10:51:51.313514 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4335 10:51:51.317203 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4336 10:51:51.323567 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4337 10:51:51.326493 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4338 10:51:51.326573 ==
4339 10:51:51.330074 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 10:51:51.333316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 10:51:51.333397 ==
4342 10:51:51.336875 DQS Delay:
4343 10:51:51.336955 DQS0 = 0, DQS1 = 0
4344 10:51:51.337018 DQM Delay:
4345 10:51:51.340015 DQM0 = 34, DQM1 = 27
4346 10:51:51.340094 DQ Delay:
4347 10:51:51.343143 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4348 10:51:51.346234 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4349 10:51:51.349924 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4350 10:51:51.353059 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4351 10:51:51.353139
4352 10:51:51.353201
4353 10:51:51.362965 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4354 10:51:51.366362 CH0 RK1: MR19=808, MR18=6A38
4355 10:51:51.372733 CH0_RK1: MR19=0x808, MR18=0x6A38, DQSOSC=389, MR23=63, INC=173, DEC=115
4356 10:51:51.372840 [RxdqsGatingPostProcess] freq 600
4357 10:51:51.379410 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 10:51:51.382841 Pre-setting of DQS Precalculation
4359 10:51:51.385889 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 10:51:51.389607 ==
4361 10:51:51.392781 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 10:51:51.396051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 10:51:51.396131 ==
4364 10:51:51.399034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 10:51:51.405835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4366 10:51:51.409490 [CA 0] Center 36 (6~66) winsize 61
4367 10:51:51.412858 [CA 1] Center 35 (5~66) winsize 62
4368 10:51:51.416493 [CA 2] Center 34 (4~65) winsize 62
4369 10:51:51.419333 [CA 3] Center 34 (4~65) winsize 62
4370 10:51:51.422900 [CA 4] Center 34 (4~65) winsize 62
4371 10:51:51.426359 [CA 5] Center 33 (3~64) winsize 62
4372 10:51:51.426440
4373 10:51:51.429832 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4374 10:51:51.429913
4375 10:51:51.432735 [CATrainingPosCal] consider 1 rank data
4376 10:51:51.436061 u2DelayCellTimex100 = 270/100 ps
4377 10:51:51.439592 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4378 10:51:51.445788 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 10:51:51.448962 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 10:51:51.452690 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 10:51:51.455956 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 10:51:51.459034 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 10:51:51.459130
4384 10:51:51.462740 CA PerBit enable=1, Macro0, CA PI delay=33
4385 10:51:51.462860
4386 10:51:51.465615 [CBTSetCACLKResult] CA Dly = 33
4387 10:51:51.469195 CS Dly: 5 (0~36)
4388 10:51:51.469290 ==
4389 10:51:51.472220 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 10:51:51.475757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 10:51:51.475828 ==
4392 10:51:51.482072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 10:51:51.485471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4394 10:51:51.490033 [CA 0] Center 36 (6~66) winsize 61
4395 10:51:51.493024 [CA 1] Center 35 (5~66) winsize 62
4396 10:51:51.496614 [CA 2] Center 34 (4~65) winsize 62
4397 10:51:51.499795 [CA 3] Center 34 (3~65) winsize 63
4398 10:51:51.503273 [CA 4] Center 34 (4~65) winsize 62
4399 10:51:51.506251 [CA 5] Center 33 (3~64) winsize 62
4400 10:51:51.506350
4401 10:51:51.509392 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4402 10:51:51.509491
4403 10:51:51.512531 [CATrainingPosCal] consider 2 rank data
4404 10:51:51.516231 u2DelayCellTimex100 = 270/100 ps
4405 10:51:51.519431 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4406 10:51:51.526097 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 10:51:51.529580 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 10:51:51.532418 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 10:51:51.536028 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 10:51:51.539390 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 10:51:51.539487
4412 10:51:51.542768 CA PerBit enable=1, Macro0, CA PI delay=33
4413 10:51:51.542904
4414 10:51:51.545924 [CBTSetCACLKResult] CA Dly = 33
4415 10:51:51.549298 CS Dly: 6 (0~38)
4416 10:51:51.549396
4417 10:51:51.552390 ----->DramcWriteLeveling(PI) begin...
4418 10:51:51.552462 ==
4419 10:51:51.555473 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 10:51:51.559321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 10:51:51.559422 ==
4422 10:51:51.562469 Write leveling (Byte 0): 29 => 29
4423 10:51:51.565556 Write leveling (Byte 1): 29 => 29
4424 10:51:51.568923 DramcWriteLeveling(PI) end<-----
4425 10:51:51.568992
4426 10:51:51.569052 ==
4427 10:51:51.572217 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 10:51:51.575348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 10:51:51.575421 ==
4430 10:51:51.579042 [Gating] SW mode calibration
4431 10:51:51.585633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 10:51:51.591777 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 10:51:51.595250 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 10:51:51.598537 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 10:51:51.605208 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 10:51:51.608873 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (1 0)
4437 10:51:51.611708 0 9 16 | B1->B0 | 2b2b 2525 | 0 1 | (1 0) (1 0)
4438 10:51:51.618508 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 10:51:51.621671 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 10:51:51.624737 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 10:51:51.631499 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 10:51:51.634943 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 10:51:51.637763 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 10:51:51.644792 0 10 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
4445 10:51:51.648143 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4446 10:51:51.650978 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 10:51:51.657534 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 10:51:51.661266 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 10:51:51.664364 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 10:51:51.670702 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 10:51:51.674443 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 10:51:51.677445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4453 10:51:51.684200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4454 10:51:51.687253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 10:51:51.690983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 10:51:51.697389 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 10:51:51.700777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 10:51:51.704468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 10:51:51.710806 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 10:51:51.713807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 10:51:51.717095 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 10:51:51.723829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 10:51:51.726948 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 10:51:51.730077 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 10:51:51.736928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 10:51:51.740380 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 10:51:51.743248 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 10:51:51.749917 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4469 10:51:51.753324 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4470 10:51:51.756683 Total UI for P1: 0, mck2ui 16
4471 10:51:51.759912 best dqsien dly found for B1: ( 0, 13, 12)
4472 10:51:51.763236 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 10:51:51.766320 Total UI for P1: 0, mck2ui 16
4474 10:51:51.769420 best dqsien dly found for B0: ( 0, 13, 14)
4475 10:51:51.776279 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4476 10:51:51.779401 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4477 10:51:51.779473
4478 10:51:51.783111 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4479 10:51:51.786287 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 10:51:51.789330 [Gating] SW calibration Done
4481 10:51:51.789428 ==
4482 10:51:51.792889 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 10:51:51.796037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 10:51:51.796137 ==
4485 10:51:51.799186 RX Vref Scan: 0
4486 10:51:51.799261
4487 10:51:51.799325 RX Vref 0 -> 0, step: 1
4488 10:51:51.799385
4489 10:51:51.802687 RX Delay -230 -> 252, step: 16
4490 10:51:51.809172 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4491 10:51:51.812197 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4492 10:51:51.815598 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4493 10:51:51.818940 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4494 10:51:51.822530 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4495 10:51:51.828962 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4496 10:51:51.832112 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4497 10:51:51.835261 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4498 10:51:51.838952 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4499 10:51:51.845172 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4500 10:51:51.848741 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4501 10:51:51.851709 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4502 10:51:51.855044 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4503 10:51:51.861439 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4504 10:51:51.864974 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4505 10:51:51.868197 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4506 10:51:51.868297 ==
4507 10:51:51.871557 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 10:51:51.875211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 10:51:51.878304 ==
4510 10:51:51.878403 DQS Delay:
4511 10:51:51.878493 DQS0 = 0, DQS1 = 0
4512 10:51:51.881393 DQM Delay:
4513 10:51:51.881491 DQM0 = 38, DQM1 = 28
4514 10:51:51.885034 DQ Delay:
4515 10:51:51.888229 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4516 10:51:51.888304 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4517 10:51:51.891859 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4518 10:51:51.894953 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4519 10:51:51.898082
4520 10:51:51.898157
4521 10:51:51.898249 ==
4522 10:51:51.901279 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 10:51:51.905189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 10:51:51.905264 ==
4525 10:51:51.905328
4526 10:51:51.905389
4527 10:51:51.907958 TX Vref Scan disable
4528 10:51:51.908032 == TX Byte 0 ==
4529 10:51:51.914505 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4530 10:51:51.918115 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4531 10:51:51.918215 == TX Byte 1 ==
4532 10:51:51.924554 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 10:51:51.927967 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 10:51:51.928068 ==
4535 10:51:51.930963 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 10:51:51.934287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 10:51:51.934388 ==
4538 10:51:51.934481
4539 10:51:51.937780
4540 10:51:51.937877 TX Vref Scan disable
4541 10:51:51.940931 == TX Byte 0 ==
4542 10:51:51.944644 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 10:51:51.950779 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 10:51:51.950921 == TX Byte 1 ==
4545 10:51:51.954284 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4546 10:51:51.960785 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4547 10:51:51.960890
4548 10:51:51.960982 [DATLAT]
4549 10:51:51.961070 Freq=600, CH1 RK0
4550 10:51:51.961159
4551 10:51:51.964353 DATLAT Default: 0x9
4552 10:51:51.964449 0, 0xFFFF, sum = 0
4553 10:51:51.967282 1, 0xFFFF, sum = 0
4554 10:51:51.970799 2, 0xFFFF, sum = 0
4555 10:51:51.970925 3, 0xFFFF, sum = 0
4556 10:51:51.974155 4, 0xFFFF, sum = 0
4557 10:51:51.974258 5, 0xFFFF, sum = 0
4558 10:51:51.977055 6, 0xFFFF, sum = 0
4559 10:51:51.977135 7, 0xFFFF, sum = 0
4560 10:51:51.980758 8, 0x0, sum = 1
4561 10:51:51.980833 9, 0x0, sum = 2
4562 10:51:51.983913 10, 0x0, sum = 3
4563 10:51:51.984008 11, 0x0, sum = 4
4564 10:51:51.984073 best_step = 9
4565 10:51:51.984131
4566 10:51:51.987511 ==
4567 10:51:51.987584 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 10:51:51.994211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 10:51:51.994320 ==
4570 10:51:51.994415 RX Vref Scan: 1
4571 10:51:51.994503
4572 10:51:51.997301 RX Vref 0 -> 0, step: 1
4573 10:51:51.997373
4574 10:51:52.000424 RX Delay -195 -> 252, step: 8
4575 10:51:52.000496
4576 10:51:52.003472 Set Vref, RX VrefLevel [Byte0]: 58
4577 10:51:52.007158 [Byte1]: 52
4578 10:51:52.007239
4579 10:51:52.010188 Final RX Vref Byte 0 = 58 to rank0
4580 10:51:52.013828 Final RX Vref Byte 1 = 52 to rank0
4581 10:51:52.016891 Final RX Vref Byte 0 = 58 to rank1
4582 10:51:52.020508 Final RX Vref Byte 1 = 52 to rank1==
4583 10:51:52.023984 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 10:51:52.026914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 10:51:52.030277 ==
4586 10:51:52.030360 DQS Delay:
4587 10:51:52.030426 DQS0 = 0, DQS1 = 0
4588 10:51:52.033672 DQM Delay:
4589 10:51:52.033754 DQM0 = 39, DQM1 = 29
4590 10:51:52.036653 DQ Delay:
4591 10:51:52.036737 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4592 10:51:52.040224 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4593 10:51:52.043308 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4594 10:51:52.046529 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4595 10:51:52.050108
4596 10:51:52.050191
4597 10:51:52.056805 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c29, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
4598 10:51:52.059879 CH1 RK0: MR19=808, MR18=1C29
4599 10:51:52.066481 CH1_RK0: MR19=0x808, MR18=0x1C29, DQSOSC=402, MR23=63, INC=162, DEC=108
4600 10:51:52.066564
4601 10:51:52.070274 ----->DramcWriteLeveling(PI) begin...
4602 10:51:52.070358 ==
4603 10:51:52.072894 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 10:51:52.076373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 10:51:52.076457 ==
4606 10:51:52.079398 Write leveling (Byte 0): 28 => 28
4607 10:51:52.082824 Write leveling (Byte 1): 30 => 30
4608 10:51:52.086387 DramcWriteLeveling(PI) end<-----
4609 10:51:52.086470
4610 10:51:52.086535 ==
4611 10:51:52.089570 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 10:51:52.092591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 10:51:52.092675 ==
4614 10:51:52.096139 [Gating] SW mode calibration
4615 10:51:52.102464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4616 10:51:52.109385 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4617 10:51:52.112595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 10:51:52.119091 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 10:51:52.122758 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4620 10:51:52.125781 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4621 10:51:52.132136 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
4622 10:51:52.135620 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 10:51:52.139070 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 10:51:52.145447 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 10:51:52.148709 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 10:51:52.151741 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 10:51:52.158592 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4628 10:51:52.162139 0 10 12 | B1->B0 | 3232 4343 | 0 0 | (0 0) (0 0)
4629 10:51:52.165030 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 10:51:52.171762 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 10:51:52.175482 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 10:51:52.178208 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 10:51:52.184860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 10:51:52.188353 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 10:51:52.191586 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 10:51:52.198051 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 10:51:52.201135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 10:51:52.204849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 10:51:52.211054 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 10:51:52.214781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 10:51:52.217803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 10:51:52.224613 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 10:51:52.227762 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 10:51:52.231134 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 10:51:52.237961 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 10:51:52.240862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 10:51:52.244285 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 10:51:52.250724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 10:51:52.254382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 10:51:52.257502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 10:51:52.263861 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 10:51:52.267380 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4653 10:51:52.270264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 10:51:52.274005 Total UI for P1: 0, mck2ui 16
4655 10:51:52.277160 best dqsien dly found for B0: ( 0, 13, 12)
4656 10:51:52.280367 Total UI for P1: 0, mck2ui 16
4657 10:51:52.283867 best dqsien dly found for B1: ( 0, 13, 12)
4658 10:51:52.286861 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4659 10:51:52.290452 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4660 10:51:52.293790
4661 10:51:52.296675 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4662 10:51:52.300033 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 10:51:52.303478 [Gating] SW calibration Done
4664 10:51:52.303586 ==
4665 10:51:52.306485 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 10:51:52.310316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 10:51:52.310387 ==
4668 10:51:52.313406 RX Vref Scan: 0
4669 10:51:52.313478
4670 10:51:52.313539 RX Vref 0 -> 0, step: 1
4671 10:51:52.313602
4672 10:51:52.316843 RX Delay -230 -> 252, step: 16
4673 10:51:52.319569 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4674 10:51:52.326156 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4675 10:51:52.329956 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4676 10:51:52.332966 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4677 10:51:52.336110 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4678 10:51:52.342699 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4679 10:51:52.346173 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4680 10:51:52.349846 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4681 10:51:52.352543 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4682 10:51:52.356238 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4683 10:51:52.362570 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4684 10:51:52.366294 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4685 10:51:52.369550 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4686 10:51:52.372448 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4687 10:51:52.379139 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4688 10:51:52.382252 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4689 10:51:52.382335 ==
4690 10:51:52.385948 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 10:51:52.388890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 10:51:52.388977 ==
4693 10:51:52.392551 DQS Delay:
4694 10:51:52.392636 DQS0 = 0, DQS1 = 0
4695 10:51:52.395743 DQM Delay:
4696 10:51:52.395860 DQM0 = 33, DQM1 = 30
4697 10:51:52.395925 DQ Delay:
4698 10:51:52.399238 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4699 10:51:52.402638 DQ4 =33, DQ5 =41, DQ6 =41, DQ7 =33
4700 10:51:52.405525 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4701 10:51:52.408890 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4702 10:51:52.408972
4703 10:51:52.409036
4704 10:51:52.412226 ==
4705 10:51:52.412308 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 10:51:52.419026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 10:51:52.419111 ==
4708 10:51:52.419176
4709 10:51:52.419235
4710 10:51:52.421977 TX Vref Scan disable
4711 10:51:52.422058 == TX Byte 0 ==
4712 10:51:52.428535 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 10:51:52.431632 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 10:51:52.431714 == TX Byte 1 ==
4715 10:51:52.438454 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4716 10:51:52.441520 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4717 10:51:52.441603 ==
4718 10:51:52.445200 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 10:51:52.448149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 10:51:52.448232 ==
4721 10:51:52.448297
4722 10:51:52.448356
4723 10:51:52.451556 TX Vref Scan disable
4724 10:51:52.454975 == TX Byte 0 ==
4725 10:51:52.458006 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4726 10:51:52.461518 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4727 10:51:52.464629 == TX Byte 1 ==
4728 10:51:52.468046 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4729 10:51:52.471257 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4730 10:51:52.474411
4731 10:51:52.474492 [DATLAT]
4732 10:51:52.474556 Freq=600, CH1 RK1
4733 10:51:52.474616
4734 10:51:52.477971 DATLAT Default: 0x9
4735 10:51:52.478055 0, 0xFFFF, sum = 0
4736 10:51:52.481059 1, 0xFFFF, sum = 0
4737 10:51:52.481142 2, 0xFFFF, sum = 0
4738 10:51:52.484709 3, 0xFFFF, sum = 0
4739 10:51:52.488221 4, 0xFFFF, sum = 0
4740 10:51:52.488303 5, 0xFFFF, sum = 0
4741 10:51:52.491257 6, 0xFFFF, sum = 0
4742 10:51:52.491344 7, 0xFFFF, sum = 0
4743 10:51:52.494351 8, 0x0, sum = 1
4744 10:51:52.494433 9, 0x0, sum = 2
4745 10:51:52.494499 10, 0x0, sum = 3
4746 10:51:52.497541 11, 0x0, sum = 4
4747 10:51:52.497624 best_step = 9
4748 10:51:52.497689
4749 10:51:52.497749 ==
4750 10:51:52.501190 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 10:51:52.507732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 10:51:52.507818 ==
4753 10:51:52.507909 RX Vref Scan: 0
4754 10:51:52.507972
4755 10:51:52.510785 RX Vref 0 -> 0, step: 1
4756 10:51:52.510904
4757 10:51:52.514232 RX Delay -195 -> 252, step: 8
4758 10:51:52.520443 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4759 10:51:52.524053 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 10:51:52.527173 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4761 10:51:52.530321 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4762 10:51:52.533934 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4763 10:51:52.540276 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4764 10:51:52.543389 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 10:51:52.547135 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4766 10:51:52.550198 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4767 10:51:52.556628 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4768 10:51:52.559980 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4769 10:51:52.563202 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4770 10:51:52.566710 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4771 10:51:52.573048 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4772 10:51:52.576852 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4773 10:51:52.579956 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4774 10:51:52.580039 ==
4775 10:51:52.583025 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 10:51:52.586666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 10:51:52.589744 ==
4778 10:51:52.589825 DQS Delay:
4779 10:51:52.589894 DQS0 = 0, DQS1 = 0
4780 10:51:52.592822 DQM Delay:
4781 10:51:52.592905 DQM0 = 36, DQM1 = 29
4782 10:51:52.596482 DQ Delay:
4783 10:51:52.599512 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4784 10:51:52.599595 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4785 10:51:52.603198 DQ8 =16, DQ9 =16, DQ10 =36, DQ11 =20
4786 10:51:52.609760 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4787 10:51:52.609877
4788 10:51:52.609943
4789 10:51:52.616168 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4790 10:51:52.619604 CH1 RK1: MR19=808, MR18=3959
4791 10:51:52.626109 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4792 10:51:52.629234 [RxdqsGatingPostProcess] freq 600
4793 10:51:52.632390 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 10:51:52.635983 Pre-setting of DQS Precalculation
4795 10:51:52.642092 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 10:51:52.649245 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 10:51:52.655838 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 10:51:52.655921
4799 10:51:52.655986
4800 10:51:52.658838 [Calibration Summary] 1200 Mbps
4801 10:51:52.658953 CH 0, Rank 0
4802 10:51:52.662459 SW Impedance : PASS
4803 10:51:52.665390 DUTY Scan : NO K
4804 10:51:52.665472 ZQ Calibration : PASS
4805 10:51:52.668873 Jitter Meter : NO K
4806 10:51:52.672250 CBT Training : PASS
4807 10:51:52.672332 Write leveling : PASS
4808 10:51:52.675244 RX DQS gating : PASS
4809 10:51:52.679005 RX DQ/DQS(RDDQC) : PASS
4810 10:51:52.679087 TX DQ/DQS : PASS
4811 10:51:52.681947 RX DATLAT : PASS
4812 10:51:52.685018 RX DQ/DQS(Engine): PASS
4813 10:51:52.685101 TX OE : NO K
4814 10:51:52.688655 All Pass.
4815 10:51:52.688737
4816 10:51:52.688801 CH 0, Rank 1
4817 10:51:52.691804 SW Impedance : PASS
4818 10:51:52.691887 DUTY Scan : NO K
4819 10:51:52.694994 ZQ Calibration : PASS
4820 10:51:52.698116 Jitter Meter : NO K
4821 10:51:52.698199 CBT Training : PASS
4822 10:51:52.701892 Write leveling : PASS
4823 10:51:52.704854 RX DQS gating : PASS
4824 10:51:52.704936 RX DQ/DQS(RDDQC) : PASS
4825 10:51:52.708114 TX DQ/DQS : PASS
4826 10:51:52.711784 RX DATLAT : PASS
4827 10:51:52.711867 RX DQ/DQS(Engine): PASS
4828 10:51:52.714879 TX OE : NO K
4829 10:51:52.714962 All Pass.
4830 10:51:52.715027
4831 10:51:52.717934 CH 1, Rank 0
4832 10:51:52.718016 SW Impedance : PASS
4833 10:51:52.721316 DUTY Scan : NO K
4834 10:51:52.724699 ZQ Calibration : PASS
4835 10:51:52.724781 Jitter Meter : NO K
4836 10:51:52.727988 CBT Training : PASS
4837 10:51:52.728088 Write leveling : PASS
4838 10:51:52.731018 RX DQS gating : PASS
4839 10:51:52.734427 RX DQ/DQS(RDDQC) : PASS
4840 10:51:52.734509 TX DQ/DQS : PASS
4841 10:51:52.737859 RX DATLAT : PASS
4842 10:51:52.741322 RX DQ/DQS(Engine): PASS
4843 10:51:52.741405 TX OE : NO K
4844 10:51:52.744262 All Pass.
4845 10:51:52.744345
4846 10:51:52.744409 CH 1, Rank 1
4847 10:51:52.748036 SW Impedance : PASS
4848 10:51:52.748119 DUTY Scan : NO K
4849 10:51:52.751195 ZQ Calibration : PASS
4850 10:51:52.754247 Jitter Meter : NO K
4851 10:51:52.754330 CBT Training : PASS
4852 10:51:52.757372 Write leveling : PASS
4853 10:51:52.760653 RX DQS gating : PASS
4854 10:51:52.760735 RX DQ/DQS(RDDQC) : PASS
4855 10:51:52.764197 TX DQ/DQS : PASS
4856 10:51:52.767576 RX DATLAT : PASS
4857 10:51:52.767659 RX DQ/DQS(Engine): PASS
4858 10:51:52.770685 TX OE : NO K
4859 10:51:52.770793 All Pass.
4860 10:51:52.770917
4861 10:51:52.774196 DramC Write-DBI off
4862 10:51:52.777066 PER_BANK_REFRESH: Hybrid Mode
4863 10:51:52.777148 TX_TRACKING: ON
4864 10:51:52.787101 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 10:51:52.790997 [FAST_K] Save calibration result to emmc
4866 10:51:52.793996 dramc_set_vcore_voltage set vcore to 662500
4867 10:51:52.796857 Read voltage for 933, 3
4868 10:51:52.796933 Vio18 = 0
4869 10:51:52.796998 Vcore = 662500
4870 10:51:52.800605 Vdram = 0
4871 10:51:52.800678 Vddq = 0
4872 10:51:52.800738 Vmddr = 0
4873 10:51:52.807156 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 10:51:52.810045 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 10:51:52.813274 MEM_TYPE=3, freq_sel=17
4876 10:51:52.817079 sv_algorithm_assistance_LP4_1600
4877 10:51:52.820068 ============ PULL DRAM RESETB DOWN ============
4878 10:51:52.826765 ========== PULL DRAM RESETB DOWN end =========
4879 10:51:52.829673 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 10:51:52.833246 ===================================
4881 10:51:52.836743 LPDDR4 DRAM CONFIGURATION
4882 10:51:52.839774 ===================================
4883 10:51:52.839856 EX_ROW_EN[0] = 0x0
4884 10:51:52.843021 EX_ROW_EN[1] = 0x0
4885 10:51:52.843103 LP4Y_EN = 0x0
4886 10:51:52.846473 WORK_FSP = 0x0
4887 10:51:52.846555 WL = 0x3
4888 10:51:52.849772 RL = 0x3
4889 10:51:52.849880 BL = 0x2
4890 10:51:52.852791 RPST = 0x0
4891 10:51:52.856534 RD_PRE = 0x0
4892 10:51:52.856615 WR_PRE = 0x1
4893 10:51:52.859671 WR_PST = 0x0
4894 10:51:52.859754 DBI_WR = 0x0
4895 10:51:52.862758 DBI_RD = 0x0
4896 10:51:52.862869 OTF = 0x1
4897 10:51:52.866585 ===================================
4898 10:51:52.869551 ===================================
4899 10:51:52.873389 ANA top config
4900 10:51:52.876012 ===================================
4901 10:51:52.876093 DLL_ASYNC_EN = 0
4902 10:51:52.879522 ALL_SLAVE_EN = 1
4903 10:51:52.882746 NEW_RANK_MODE = 1
4904 10:51:52.885764 DLL_IDLE_MODE = 1
4905 10:51:52.885846 LP45_APHY_COMB_EN = 1
4906 10:51:52.889386 TX_ODT_DIS = 1
4907 10:51:52.892760 NEW_8X_MODE = 1
4908 10:51:52.895526 ===================================
4909 10:51:52.899092 ===================================
4910 10:51:52.902188 data_rate = 1866
4911 10:51:52.905905 CKR = 1
4912 10:51:52.908949 DQ_P2S_RATIO = 8
4913 10:51:52.911967 ===================================
4914 10:51:52.912048 CA_P2S_RATIO = 8
4915 10:51:52.915593 DQ_CA_OPEN = 0
4916 10:51:52.918540 DQ_SEMI_OPEN = 0
4917 10:51:52.921826 CA_SEMI_OPEN = 0
4918 10:51:52.925470 CA_FULL_RATE = 0
4919 10:51:52.928529 DQ_CKDIV4_EN = 1
4920 10:51:52.931969 CA_CKDIV4_EN = 1
4921 10:51:52.932052 CA_PREDIV_EN = 0
4922 10:51:52.935160 PH8_DLY = 0
4923 10:51:52.938700 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 10:51:52.941663 DQ_AAMCK_DIV = 4
4925 10:51:52.945285 CA_AAMCK_DIV = 4
4926 10:51:52.948147 CA_ADMCK_DIV = 4
4927 10:51:52.948222 DQ_TRACK_CA_EN = 0
4928 10:51:52.951511 CA_PICK = 933
4929 10:51:52.954920 CA_MCKIO = 933
4930 10:51:52.958454 MCKIO_SEMI = 0
4931 10:51:52.961542 PLL_FREQ = 3732
4932 10:51:52.964689 DQ_UI_PI_RATIO = 32
4933 10:51:52.967801 CA_UI_PI_RATIO = 0
4934 10:51:52.971802 ===================================
4935 10:51:52.974568 ===================================
4936 10:51:52.974640 memory_type:LPDDR4
4937 10:51:52.977667 GP_NUM : 10
4938 10:51:52.981166 SRAM_EN : 1
4939 10:51:52.981255 MD32_EN : 0
4940 10:51:52.984575 ===================================
4941 10:51:52.987504 [ANA_INIT] >>>>>>>>>>>>>>
4942 10:51:52.990809 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 10:51:52.994601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 10:51:52.997805 ===================================
4945 10:51:53.001184 data_rate = 1866,PCW = 0X8f00
4946 10:51:53.004237 ===================================
4947 10:51:53.007381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 10:51:53.010525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 10:51:53.017184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 10:51:53.021016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 10:51:53.027164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 10:51:53.030290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 10:51:53.030365 [ANA_INIT] flow start
4954 10:51:53.033956 [ANA_INIT] PLL >>>>>>>>
4955 10:51:53.037351 [ANA_INIT] PLL <<<<<<<<
4956 10:51:53.037436 [ANA_INIT] MIDPI >>>>>>>>
4957 10:51:53.040454 [ANA_INIT] MIDPI <<<<<<<<
4958 10:51:53.043530 [ANA_INIT] DLL >>>>>>>>
4959 10:51:53.043617 [ANA_INIT] flow end
4960 10:51:53.047121 ============ LP4 DIFF to SE enter ============
4961 10:51:53.053558 ============ LP4 DIFF to SE exit ============
4962 10:51:53.053637 [ANA_INIT] <<<<<<<<<<<<<
4963 10:51:53.057001 [Flow] Enable top DCM control >>>>>
4964 10:51:53.060285 [Flow] Enable top DCM control <<<<<
4965 10:51:53.063822 Enable DLL master slave shuffle
4966 10:51:53.070080 ==============================================================
4967 10:51:53.074000 Gating Mode config
4968 10:51:53.077048 ==============================================================
4969 10:51:53.080016 Config description:
4970 10:51:53.089775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 10:51:53.096609 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 10:51:53.100019 SELPH_MODE 0: By rank 1: By Phase
4973 10:51:53.106424 ==============================================================
4974 10:51:53.109787 GAT_TRACK_EN = 1
4975 10:51:53.112892 RX_GATING_MODE = 2
4976 10:51:53.116543 RX_GATING_TRACK_MODE = 2
4977 10:51:53.119565 SELPH_MODE = 1
4978 10:51:53.119682 PICG_EARLY_EN = 1
4979 10:51:53.122725 VALID_LAT_VALUE = 1
4980 10:51:53.129773 ==============================================================
4981 10:51:53.132881 Enter into Gating configuration >>>>
4982 10:51:53.135946 Exit from Gating configuration <<<<
4983 10:51:53.139633 Enter into DVFS_PRE_config >>>>>
4984 10:51:53.149316 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 10:51:53.152894 Exit from DVFS_PRE_config <<<<<
4986 10:51:53.155875 Enter into PICG configuration >>>>
4987 10:51:53.159407 Exit from PICG configuration <<<<
4988 10:51:53.162808 [RX_INPUT] configuration >>>>>
4989 10:51:53.165735 [RX_INPUT] configuration <<<<<
4990 10:51:53.169007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 10:51:53.175764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 10:51:53.182485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 10:51:53.188815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 10:51:53.195499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 10:51:53.201830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 10:51:53.205267 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 10:51:53.208459 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 10:51:53.211966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 10:51:53.218766 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 10:51:53.221630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 10:51:53.225172 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 10:51:53.228413 ===================================
5003 10:51:53.231578 LPDDR4 DRAM CONFIGURATION
5004 10:51:53.235202 ===================================
5005 10:51:53.235285 EX_ROW_EN[0] = 0x0
5006 10:51:53.238346 EX_ROW_EN[1] = 0x0
5007 10:51:53.241318 LP4Y_EN = 0x0
5008 10:51:53.241426 WORK_FSP = 0x0
5009 10:51:53.244878 WL = 0x3
5010 10:51:53.244961 RL = 0x3
5011 10:51:53.248233 BL = 0x2
5012 10:51:53.248316 RPST = 0x0
5013 10:51:53.251337 RD_PRE = 0x0
5014 10:51:53.251420 WR_PRE = 0x1
5015 10:51:53.254484 WR_PST = 0x0
5016 10:51:53.254591 DBI_WR = 0x0
5017 10:51:53.258141 DBI_RD = 0x0
5018 10:51:53.258223 OTF = 0x1
5019 10:51:53.261123 ===================================
5020 10:51:53.267686 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 10:51:53.271231 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 10:51:53.274834 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 10:51:53.277523 ===================================
5024 10:51:53.280727 LPDDR4 DRAM CONFIGURATION
5025 10:51:53.284344 ===================================
5026 10:51:53.287423 EX_ROW_EN[0] = 0x10
5027 10:51:53.287505 EX_ROW_EN[1] = 0x0
5028 10:51:53.290637 LP4Y_EN = 0x0
5029 10:51:53.290718 WORK_FSP = 0x0
5030 10:51:53.294189 WL = 0x3
5031 10:51:53.294271 RL = 0x3
5032 10:51:53.297290 BL = 0x2
5033 10:51:53.297372 RPST = 0x0
5034 10:51:53.300797 RD_PRE = 0x0
5035 10:51:53.300883 WR_PRE = 0x1
5036 10:51:53.303811 WR_PST = 0x0
5037 10:51:53.303893 DBI_WR = 0x0
5038 10:51:53.307266 DBI_RD = 0x0
5039 10:51:53.307347 OTF = 0x1
5040 10:51:53.310578 ===================================
5041 10:51:53.317265 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 10:51:53.321955 nWR fixed to 30
5043 10:51:53.325279 [ModeRegInit_LP4] CH0 RK0
5044 10:51:53.325361 [ModeRegInit_LP4] CH0 RK1
5045 10:51:53.328585 [ModeRegInit_LP4] CH1 RK0
5046 10:51:53.332202 [ModeRegInit_LP4] CH1 RK1
5047 10:51:53.332283 match AC timing 9
5048 10:51:53.338356 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 10:51:53.342125 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 10:51:53.345430 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 10:51:53.351672 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 10:51:53.355490 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 10:51:53.355572 ==
5054 10:51:53.358687 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 10:51:53.361863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 10:51:53.361949 ==
5057 10:51:53.368252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 10:51:53.374754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5059 10:51:53.378392 [CA 0] Center 38 (8~69) winsize 62
5060 10:51:53.381861 [CA 1] Center 38 (8~68) winsize 61
5061 10:51:53.385141 [CA 2] Center 35 (6~65) winsize 60
5062 10:51:53.387940 [CA 3] Center 35 (5~65) winsize 61
5063 10:51:53.391126 [CA 4] Center 34 (4~64) winsize 61
5064 10:51:53.394946 [CA 5] Center 33 (3~64) winsize 62
5065 10:51:53.395021
5066 10:51:53.398057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5067 10:51:53.398128
5068 10:51:53.401156 [CATrainingPosCal] consider 1 rank data
5069 10:51:53.404185 u2DelayCellTimex100 = 270/100 ps
5070 10:51:53.407832 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5071 10:51:53.410721 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5072 10:51:53.414170 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5073 10:51:53.420632 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5074 10:51:53.424235 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5075 10:51:53.427255 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 10:51:53.427345
5077 10:51:53.431220 CA PerBit enable=1, Macro0, CA PI delay=33
5078 10:51:53.431330
5079 10:51:53.433854 [CBTSetCACLKResult] CA Dly = 33
5080 10:51:53.433927 CS Dly: 6 (0~37)
5081 10:51:53.433987 ==
5082 10:51:53.437204 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 10:51:53.443796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 10:51:53.443910 ==
5085 10:51:53.446973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 10:51:53.453886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5087 10:51:53.457227 [CA 0] Center 38 (8~69) winsize 62
5088 10:51:53.460333 [CA 1] Center 38 (8~69) winsize 62
5089 10:51:53.463656 [CA 2] Center 35 (5~66) winsize 62
5090 10:51:53.467341 [CA 3] Center 35 (5~66) winsize 62
5091 10:51:53.470384 [CA 4] Center 34 (4~64) winsize 61
5092 10:51:53.473438 [CA 5] Center 33 (3~64) winsize 62
5093 10:51:53.473510
5094 10:51:53.476985 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5095 10:51:53.477054
5096 10:51:53.480537 [CATrainingPosCal] consider 2 rank data
5097 10:51:53.483420 u2DelayCellTimex100 = 270/100 ps
5098 10:51:53.486771 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 10:51:53.493567 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5100 10:51:53.497019 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5101 10:51:53.500191 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5102 10:51:53.503319 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5103 10:51:53.506479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 10:51:53.506551
5105 10:51:53.509626 CA PerBit enable=1, Macro0, CA PI delay=33
5106 10:51:53.509694
5107 10:51:53.513240 [CBTSetCACLKResult] CA Dly = 33
5108 10:51:53.516245 CS Dly: 6 (0~38)
5109 10:51:53.516326
5110 10:51:53.519930 ----->DramcWriteLeveling(PI) begin...
5111 10:51:53.520015 ==
5112 10:51:53.523222 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 10:51:53.526257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 10:51:53.526340 ==
5115 10:51:53.529784 Write leveling (Byte 0): 33 => 33
5116 10:51:53.532993 Write leveling (Byte 1): 31 => 31
5117 10:51:53.536334 DramcWriteLeveling(PI) end<-----
5118 10:51:53.536416
5119 10:51:53.536480 ==
5120 10:51:53.539590 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 10:51:53.542624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 10:51:53.542732 ==
5123 10:51:53.546131 [Gating] SW mode calibration
5124 10:51:53.552749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 10:51:53.558937 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 10:51:53.562636 0 14 0 | B1->B0 | 2323 2e2e | 1 1 | (0 0) (1 1)
5127 10:51:53.568764 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5128 10:51:53.572006 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 10:51:53.575919 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 10:51:53.582143 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 10:51:53.585423 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 10:51:53.588979 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 10:51:53.595529 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5134 10:51:53.598520 0 15 0 | B1->B0 | 3131 2c2c | 1 0 | (1 1) (1 1)
5135 10:51:53.601561 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5136 10:51:53.608111 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 10:51:53.611906 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 10:51:53.614978 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 10:51:53.621519 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 10:51:53.625050 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 10:51:53.628160 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 10:51:53.634977 1 0 0 | B1->B0 | 2727 3b3b | 0 1 | (0 0) (0 0)
5143 10:51:53.638057 1 0 4 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5144 10:51:53.641272 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 10:51:53.647870 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 10:51:53.651372 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 10:51:53.654550 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 10:51:53.660959 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 10:51:53.664478 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5150 10:51:53.667583 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 10:51:53.674486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5152 10:51:53.677535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 10:51:53.681193 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 10:51:53.687261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 10:51:53.691063 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 10:51:53.694107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 10:51:53.700735 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 10:51:53.704014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 10:51:53.707500 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 10:51:53.713990 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 10:51:53.717172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 10:51:53.720809 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 10:51:53.727271 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 10:51:53.729990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 10:51:53.733477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 10:51:53.740012 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5167 10:51:53.740095 Total UI for P1: 0, mck2ui 16
5168 10:51:53.746701 best dqsien dly found for B0: ( 1, 2, 30)
5169 10:51:53.750302 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 10:51:53.753520 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 10:51:53.756648 Total UI for P1: 0, mck2ui 16
5172 10:51:53.759993 best dqsien dly found for B1: ( 1, 3, 4)
5173 10:51:53.763000 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 10:51:53.766573 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5175 10:51:53.766656
5176 10:51:53.772959 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 10:51:53.776974 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5178 10:51:53.779812 [Gating] SW calibration Done
5179 10:51:53.779896 ==
5180 10:51:53.782821 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 10:51:53.785861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 10:51:53.785948 ==
5183 10:51:53.786013 RX Vref Scan: 0
5184 10:51:53.786073
5185 10:51:53.789412 RX Vref 0 -> 0, step: 1
5186 10:51:53.789512
5187 10:51:53.792621 RX Delay -80 -> 252, step: 8
5188 10:51:53.795732 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5189 10:51:53.799664 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5190 10:51:53.805711 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5191 10:51:53.809181 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 10:51:53.812027 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5193 10:51:53.815395 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5194 10:51:53.818812 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5195 10:51:53.822423 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5196 10:51:53.828547 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5197 10:51:53.832239 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5198 10:51:53.835241 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5199 10:51:53.838583 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5200 10:51:53.845353 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5201 10:51:53.848464 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5202 10:51:53.851377 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5203 10:51:53.854972 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5204 10:51:53.855056 ==
5205 10:51:53.858176 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 10:51:53.864820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 10:51:53.864933 ==
5208 10:51:53.865025 DQS Delay:
5209 10:51:53.865090 DQS0 = 0, DQS1 = 0
5210 10:51:53.867869 DQM Delay:
5211 10:51:53.867951 DQM0 = 95, DQM1 = 83
5212 10:51:53.871320 DQ Delay:
5213 10:51:53.874324 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5214 10:51:53.878176 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5215 10:51:53.881297 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =79
5216 10:51:53.884233 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5217 10:51:53.884346
5218 10:51:53.884419
5219 10:51:53.884480 ==
5220 10:51:53.887361 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 10:51:53.891089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 10:51:53.891173 ==
5223 10:51:53.891238
5224 10:51:53.891299
5225 10:51:53.894012 TX Vref Scan disable
5226 10:51:53.897761 == TX Byte 0 ==
5227 10:51:53.900861 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5228 10:51:53.903913 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5229 10:51:53.907672 == TX Byte 1 ==
5230 10:51:53.910678 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5231 10:51:53.913814 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5232 10:51:53.913897 ==
5233 10:51:53.917328 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 10:51:53.920861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 10:51:53.923754 ==
5236 10:51:53.923837
5237 10:51:53.923902
5238 10:51:53.923963 TX Vref Scan disable
5239 10:51:53.927750 == TX Byte 0 ==
5240 10:51:53.930678 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5241 10:51:53.937543 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5242 10:51:53.937647 == TX Byte 1 ==
5243 10:51:53.940512 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5244 10:51:53.947009 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5245 10:51:53.947093
5246 10:51:53.947158 [DATLAT]
5247 10:51:53.947219 Freq=933, CH0 RK0
5248 10:51:53.947278
5249 10:51:53.950672 DATLAT Default: 0xd
5250 10:51:53.953867 0, 0xFFFF, sum = 0
5251 10:51:53.953956 1, 0xFFFF, sum = 0
5252 10:51:53.957207 2, 0xFFFF, sum = 0
5253 10:51:53.957293 3, 0xFFFF, sum = 0
5254 10:51:53.960550 4, 0xFFFF, sum = 0
5255 10:51:53.960635 5, 0xFFFF, sum = 0
5256 10:51:53.964090 6, 0xFFFF, sum = 0
5257 10:51:53.964176 7, 0xFFFF, sum = 0
5258 10:51:53.967240 8, 0xFFFF, sum = 0
5259 10:51:53.967366 9, 0xFFFF, sum = 0
5260 10:51:53.970389 10, 0x0, sum = 1
5261 10:51:53.970474 11, 0x0, sum = 2
5262 10:51:53.973340 12, 0x0, sum = 3
5263 10:51:53.973427 13, 0x0, sum = 4
5264 10:51:53.976672 best_step = 11
5265 10:51:53.976755
5266 10:51:53.976820 ==
5267 10:51:53.980069 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 10:51:53.983218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 10:51:53.983305 ==
5270 10:51:53.983370 RX Vref Scan: 1
5271 10:51:53.986901
5272 10:51:53.986985 RX Vref 0 -> 0, step: 1
5273 10:51:53.987051
5274 10:51:53.989971 RX Delay -77 -> 252, step: 4
5275 10:51:53.990053
5276 10:51:53.993060 Set Vref, RX VrefLevel [Byte0]: 63
5277 10:51:53.996632 [Byte1]: 58
5278 10:51:54.000257
5279 10:51:54.000339 Final RX Vref Byte 0 = 63 to rank0
5280 10:51:54.003578 Final RX Vref Byte 1 = 58 to rank0
5281 10:51:54.006506 Final RX Vref Byte 0 = 63 to rank1
5282 10:51:54.009722 Final RX Vref Byte 1 = 58 to rank1==
5283 10:51:54.013444 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 10:51:54.019522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 10:51:54.019632 ==
5286 10:51:54.019701 DQS Delay:
5287 10:51:54.023401 DQS0 = 0, DQS1 = 0
5288 10:51:54.023483 DQM Delay:
5289 10:51:54.023547 DQM0 = 96, DQM1 = 84
5290 10:51:54.026202 DQ Delay:
5291 10:51:54.029891 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5292 10:51:54.033462 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5293 10:51:54.036229 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5294 10:51:54.039855 DQ12 =90, DQ13 =88, DQ14 =92, DQ15 =90
5295 10:51:54.039934
5296 10:51:54.039995
5297 10:51:54.046534 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5298 10:51:54.049474 CH0 RK0: MR19=505, MR18=1211
5299 10:51:54.056031 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5300 10:51:54.056111
5301 10:51:54.059325 ----->DramcWriteLeveling(PI) begin...
5302 10:51:54.059406 ==
5303 10:51:54.062701 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 10:51:54.066214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 10:51:54.066315 ==
5306 10:51:54.069072 Write leveling (Byte 0): 32 => 32
5307 10:51:54.072478 Write leveling (Byte 1): 31 => 31
5308 10:51:54.076158 DramcWriteLeveling(PI) end<-----
5309 10:51:54.076236
5310 10:51:54.076298 ==
5311 10:51:54.079233 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 10:51:54.085957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 10:51:54.086036 ==
5314 10:51:54.086099 [Gating] SW mode calibration
5315 10:51:54.095743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 10:51:54.098928 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 10:51:54.102504 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5318 10:51:54.108567 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 10:51:54.112366 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 10:51:54.115569 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 10:51:54.121822 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 10:51:54.125316 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 10:51:54.128355 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5324 10:51:54.135234 0 14 28 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 1)
5325 10:51:54.138097 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5326 10:51:54.141886 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 10:51:54.148291 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 10:51:54.151816 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 10:51:54.155009 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 10:51:54.161208 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 10:51:54.164633 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 10:51:54.168069 0 15 28 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (0 0)
5333 10:51:54.174486 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5334 10:51:54.177816 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 10:51:54.184326 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 10:51:54.187986 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 10:51:54.190977 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 10:51:54.194315 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 10:51:54.200708 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 10:51:54.204405 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 10:51:54.210897 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5342 10:51:54.214015 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 10:51:54.217709 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 10:51:54.220807 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 10:51:54.227386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 10:51:54.230879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 10:51:54.233957 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 10:51:54.240569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 10:51:54.243707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 10:51:54.247316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 10:51:54.253872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 10:51:54.256783 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 10:51:54.260513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 10:51:54.266611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 10:51:54.270037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 10:51:54.273703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 10:51:54.277082 Total UI for P1: 0, mck2ui 16
5358 10:51:54.280972 best dqsien dly found for B0: ( 1, 2, 26)
5359 10:51:54.286833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 10:51:54.289768 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 10:51:54.293549 Total UI for P1: 0, mck2ui 16
5362 10:51:54.296398 best dqsien dly found for B1: ( 1, 2, 30)
5363 10:51:54.300131 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5364 10:51:54.303496 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5365 10:51:54.303577
5366 10:51:54.306781 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5367 10:51:54.313353 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5368 10:51:54.313435 [Gating] SW calibration Done
5369 10:51:54.313501 ==
5370 10:51:54.316407 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 10:51:54.323303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 10:51:54.323386 ==
5373 10:51:54.323451 RX Vref Scan: 0
5374 10:51:54.323511
5375 10:51:54.326457 RX Vref 0 -> 0, step: 1
5376 10:51:54.326539
5377 10:51:54.329560 RX Delay -80 -> 252, step: 8
5378 10:51:54.333132 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5379 10:51:54.336154 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5380 10:51:54.339813 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5381 10:51:54.346044 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5382 10:51:54.349130 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5383 10:51:54.352829 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5384 10:51:54.355691 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5385 10:51:54.359226 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 10:51:54.366146 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5387 10:51:54.369191 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5388 10:51:54.372596 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5389 10:51:54.375736 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5390 10:51:54.378893 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5391 10:51:54.385732 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5392 10:51:54.388562 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5393 10:51:54.391897 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5394 10:51:54.391979 ==
5395 10:51:54.395347 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 10:51:54.399034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 10:51:54.399118 ==
5398 10:51:54.401757 DQS Delay:
5399 10:51:54.401839 DQS0 = 0, DQS1 = 0
5400 10:51:54.405226 DQM Delay:
5401 10:51:54.405308 DQM0 = 92, DQM1 = 83
5402 10:51:54.405373 DQ Delay:
5403 10:51:54.408644 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5404 10:51:54.412357 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5405 10:51:54.415538 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5406 10:51:54.418288 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5407 10:51:54.418370
5408 10:51:54.422040
5409 10:51:54.422120 ==
5410 10:51:54.425124 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 10:51:54.428458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 10:51:54.428540 ==
5413 10:51:54.428605
5414 10:51:54.428665
5415 10:51:54.431933 TX Vref Scan disable
5416 10:51:54.432014 == TX Byte 0 ==
5417 10:51:54.438491 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5418 10:51:54.441633 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5419 10:51:54.441716 == TX Byte 1 ==
5420 10:51:54.448341 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5421 10:51:54.451603 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5422 10:51:54.451686 ==
5423 10:51:54.454611 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 10:51:54.458371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 10:51:54.458453 ==
5426 10:51:54.458517
5427 10:51:54.458576
5428 10:51:54.461258 TX Vref Scan disable
5429 10:51:54.464757 == TX Byte 0 ==
5430 10:51:54.467773 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5431 10:51:54.471551 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5432 10:51:54.474489 == TX Byte 1 ==
5433 10:51:54.478054 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5434 10:51:54.481384 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5435 10:51:54.481466
5436 10:51:54.484363 [DATLAT]
5437 10:51:54.484445 Freq=933, CH0 RK1
5438 10:51:54.484510
5439 10:51:54.488157 DATLAT Default: 0xb
5440 10:51:54.488238 0, 0xFFFF, sum = 0
5441 10:51:54.491219 1, 0xFFFF, sum = 0
5442 10:51:54.491302 2, 0xFFFF, sum = 0
5443 10:51:54.494150 3, 0xFFFF, sum = 0
5444 10:51:54.494233 4, 0xFFFF, sum = 0
5445 10:51:54.497581 5, 0xFFFF, sum = 0
5446 10:51:54.497665 6, 0xFFFF, sum = 0
5447 10:51:54.500973 7, 0xFFFF, sum = 0
5448 10:51:54.504380 8, 0xFFFF, sum = 0
5449 10:51:54.504464 9, 0xFFFF, sum = 0
5450 10:51:54.504529 10, 0x0, sum = 1
5451 10:51:54.507311 11, 0x0, sum = 2
5452 10:51:54.507393 12, 0x0, sum = 3
5453 10:51:54.510506 13, 0x0, sum = 4
5454 10:51:54.510588 best_step = 11
5455 10:51:54.510652
5456 10:51:54.510711 ==
5457 10:51:54.514016 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 10:51:54.521175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 10:51:54.521257 ==
5460 10:51:54.521322 RX Vref Scan: 0
5461 10:51:54.521380
5462 10:51:54.523717 RX Vref 0 -> 0, step: 1
5463 10:51:54.523799
5464 10:51:54.527595 RX Delay -77 -> 252, step: 4
5465 10:51:54.530582 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5466 10:51:54.537308 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5467 10:51:54.540294 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5468 10:51:54.543826 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5469 10:51:54.547018 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5470 10:51:54.550524 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5471 10:51:54.556594 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5472 10:51:54.560409 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5473 10:51:54.563541 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5474 10:51:54.566648 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5475 10:51:54.570238 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5476 10:51:54.576452 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5477 10:51:54.580009 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5478 10:51:54.583173 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5479 10:51:54.586851 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5480 10:51:54.590092 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5481 10:51:54.593110 ==
5482 10:51:54.593218 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 10:51:54.600009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 10:51:54.600091 ==
5485 10:51:54.600156 DQS Delay:
5486 10:51:54.602849 DQS0 = 0, DQS1 = 0
5487 10:51:54.602945 DQM Delay:
5488 10:51:54.606358 DQM0 = 93, DQM1 = 84
5489 10:51:54.606465 DQ Delay:
5490 10:51:54.609864 DQ0 =90, DQ1 =94, DQ2 =90, DQ3 =90
5491 10:51:54.613196 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5492 10:51:54.616049 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5493 10:51:54.619411 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =92
5494 10:51:54.619495
5495 10:51:54.619560
5496 10:51:54.626223 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5497 10:51:54.629304 CH0 RK1: MR19=505, MR18=2E0F
5498 10:51:54.635895 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5499 10:51:54.638992 [RxdqsGatingPostProcess] freq 933
5500 10:51:54.646106 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 10:51:54.649280 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 10:51:54.649362 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 10:51:54.652515 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 10:51:54.655908 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 10:51:54.658999 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 10:51:54.662184 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 10:51:54.665900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 10:51:54.669019 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 10:51:54.672264 Pre-setting of DQS Precalculation
5510 10:51:54.678716 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 10:51:54.678834 ==
5512 10:51:54.682120 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 10:51:54.685570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 10:51:54.685654 ==
5515 10:51:54.691826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 10:51:54.698710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5517 10:51:54.701883 [CA 0] Center 37 (7~67) winsize 61
5518 10:51:54.704968 [CA 1] Center 37 (7~68) winsize 62
5519 10:51:54.708464 [CA 2] Center 34 (5~64) winsize 60
5520 10:51:54.711595 [CA 3] Center 34 (5~64) winsize 60
5521 10:51:54.715234 [CA 4] Center 35 (5~65) winsize 61
5522 10:51:54.718144 [CA 5] Center 33 (4~63) winsize 60
5523 10:51:54.718226
5524 10:51:54.721477 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5525 10:51:54.721560
5526 10:51:54.724871 [CATrainingPosCal] consider 1 rank data
5527 10:51:54.728202 u2DelayCellTimex100 = 270/100 ps
5528 10:51:54.731639 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5529 10:51:54.735112 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5530 10:51:54.738022 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5531 10:51:54.741458 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5532 10:51:54.744557 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5533 10:51:54.748139 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5534 10:51:54.748223
5535 10:51:54.754821 CA PerBit enable=1, Macro0, CA PI delay=33
5536 10:51:54.754937
5537 10:51:54.755003 [CBTSetCACLKResult] CA Dly = 33
5538 10:51:54.757819 CS Dly: 6 (0~37)
5539 10:51:54.757902 ==
5540 10:51:54.761220 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 10:51:54.764408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 10:51:54.764492 ==
5543 10:51:54.771469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 10:51:54.777562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5545 10:51:54.781225 [CA 0] Center 38 (8~68) winsize 61
5546 10:51:54.784295 [CA 1] Center 37 (7~68) winsize 62
5547 10:51:54.787770 [CA 2] Center 35 (5~65) winsize 61
5548 10:51:54.790780 [CA 3] Center 34 (4~65) winsize 62
5549 10:51:54.794221 [CA 4] Center 34 (4~65) winsize 62
5550 10:51:54.797382 [CA 5] Center 33 (3~64) winsize 62
5551 10:51:54.797465
5552 10:51:54.801009 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5553 10:51:54.801092
5554 10:51:54.804407 [CATrainingPosCal] consider 2 rank data
5555 10:51:54.807307 u2DelayCellTimex100 = 270/100 ps
5556 10:51:54.811009 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5557 10:51:54.813812 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5558 10:51:54.817517 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5559 10:51:54.820585 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5560 10:51:54.827263 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5561 10:51:54.830264 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5562 10:51:54.830347
5563 10:51:54.833560 CA PerBit enable=1, Macro0, CA PI delay=33
5564 10:51:54.833682
5565 10:51:54.836951 [CBTSetCACLKResult] CA Dly = 33
5566 10:51:54.837033 CS Dly: 7 (0~39)
5567 10:51:54.837098
5568 10:51:54.840514 ----->DramcWriteLeveling(PI) begin...
5569 10:51:54.840599 ==
5570 10:51:54.843602 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 10:51:54.850065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 10:51:54.850153 ==
5573 10:51:54.853635 Write leveling (Byte 0): 28 => 28
5574 10:51:54.856466 Write leveling (Byte 1): 28 => 28
5575 10:51:54.856549 DramcWriteLeveling(PI) end<-----
5576 10:51:54.860133
5577 10:51:54.860215 ==
5578 10:51:54.863078 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 10:51:54.866718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 10:51:54.866801 ==
5581 10:51:54.869893 [Gating] SW mode calibration
5582 10:51:54.876973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 10:51:54.882968 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 10:51:54.886542 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5585 10:51:54.889512 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 10:51:54.893167 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 10:51:54.899337 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 10:51:54.902793 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 10:51:54.906384 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 10:51:54.912808 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 10:51:54.915834 0 14 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
5592 10:51:54.919297 0 15 0 | B1->B0 | 2c2c 2a2a | 0 1 | (0 0) (1 0)
5593 10:51:54.926239 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 10:51:54.929333 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 10:51:54.932432 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 10:51:54.939309 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 10:51:54.942752 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 10:51:54.945683 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 10:51:54.952230 0 15 28 | B1->B0 | 3333 3838 | 1 0 | (0 0) (0 0)
5600 10:51:54.955613 1 0 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
5601 10:51:54.959034 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 10:51:54.965624 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 10:51:54.968618 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 10:51:54.972535 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 10:51:54.978857 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 10:51:54.981634 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 10:51:54.988421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 10:51:54.991917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5609 10:51:54.995255 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 10:51:54.998637 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 10:51:55.004913 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 10:51:55.008450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 10:51:55.011418 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 10:51:55.018358 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 10:51:55.021429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 10:51:55.028222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 10:51:55.031316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 10:51:55.034422 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 10:51:55.040883 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 10:51:55.044453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 10:51:55.047456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 10:51:55.054610 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 10:51:55.057614 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5624 10:51:55.060854 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5625 10:51:55.064503 Total UI for P1: 0, mck2ui 16
5626 10:51:55.067366 best dqsien dly found for B0: ( 1, 2, 28)
5627 10:51:55.070982 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 10:51:55.073972 Total UI for P1: 0, mck2ui 16
5629 10:51:55.077653 best dqsien dly found for B1: ( 1, 2, 30)
5630 10:51:55.083907 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5631 10:51:55.087482 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5632 10:51:55.087565
5633 10:51:55.090590 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 10:51:55.093768 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5635 10:51:55.097307 [Gating] SW calibration Done
5636 10:51:55.097391 ==
5637 10:51:55.100606 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 10:51:55.103750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 10:51:55.103834 ==
5640 10:51:55.107154 RX Vref Scan: 0
5641 10:51:55.107237
5642 10:51:55.107302 RX Vref 0 -> 0, step: 1
5643 10:51:55.107361
5644 10:51:55.109948 RX Delay -80 -> 252, step: 8
5645 10:51:55.113558 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5646 10:51:55.120182 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5647 10:51:55.123909 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5648 10:51:55.126559 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5649 10:51:55.129702 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5650 10:51:55.133541 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5651 10:51:55.136618 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5652 10:51:55.143379 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5653 10:51:55.146679 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5654 10:51:55.149915 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5655 10:51:55.153393 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5656 10:51:55.156287 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5657 10:51:55.162749 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5658 10:51:55.166204 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5659 10:51:55.169733 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5660 10:51:55.173110 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5661 10:51:55.173196 ==
5662 10:51:55.176477 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 10:51:55.183254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 10:51:55.183339 ==
5665 10:51:55.183423 DQS Delay:
5666 10:51:55.183503 DQS0 = 0, DQS1 = 0
5667 10:51:55.186378 DQM Delay:
5668 10:51:55.186462 DQM0 = 94, DQM1 = 87
5669 10:51:55.189498 DQ Delay:
5670 10:51:55.192712 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5671 10:51:55.195844 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5672 10:51:55.199717 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5673 10:51:55.202636 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5674 10:51:55.202721
5675 10:51:55.202822
5676 10:51:55.202936 ==
5677 10:51:55.206055 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 10:51:55.209246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 10:51:55.209331 ==
5680 10:51:55.209414
5681 10:51:55.209493
5682 10:51:55.212396 TX Vref Scan disable
5683 10:51:55.215464 == TX Byte 0 ==
5684 10:51:55.219004 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5685 10:51:55.222669 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5686 10:51:55.225806 == TX Byte 1 ==
5687 10:51:55.228772 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5688 10:51:55.232169 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5689 10:51:55.232255 ==
5690 10:51:55.235715 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 10:51:55.238728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 10:51:55.242027 ==
5693 10:51:55.242110
5694 10:51:55.242194
5695 10:51:55.242274 TX Vref Scan disable
5696 10:51:55.245697 == TX Byte 0 ==
5697 10:51:55.248843 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 10:51:55.255760 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 10:51:55.255844 == TX Byte 1 ==
5700 10:51:55.258751 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5701 10:51:55.265615 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5702 10:51:55.265696
5703 10:51:55.265760 [DATLAT]
5704 10:51:55.265820 Freq=933, CH1 RK0
5705 10:51:55.265877
5706 10:51:55.268613 DATLAT Default: 0xd
5707 10:51:55.272077 0, 0xFFFF, sum = 0
5708 10:51:55.272187 1, 0xFFFF, sum = 0
5709 10:51:55.275175 2, 0xFFFF, sum = 0
5710 10:51:55.275257 3, 0xFFFF, sum = 0
5711 10:51:55.278678 4, 0xFFFF, sum = 0
5712 10:51:55.278760 5, 0xFFFF, sum = 0
5713 10:51:55.281992 6, 0xFFFF, sum = 0
5714 10:51:55.282074 7, 0xFFFF, sum = 0
5715 10:51:55.284963 8, 0xFFFF, sum = 0
5716 10:51:55.285046 9, 0xFFFF, sum = 0
5717 10:51:55.288152 10, 0x0, sum = 1
5718 10:51:55.288234 11, 0x0, sum = 2
5719 10:51:55.291340 12, 0x0, sum = 3
5720 10:51:55.291422 13, 0x0, sum = 4
5721 10:51:55.295353 best_step = 11
5722 10:51:55.295478
5723 10:51:55.295560 ==
5724 10:51:55.298390 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 10:51:55.301552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 10:51:55.301634 ==
5727 10:51:55.304486 RX Vref Scan: 1
5728 10:51:55.304566
5729 10:51:55.304629 RX Vref 0 -> 0, step: 1
5730 10:51:55.304687
5731 10:51:55.308260 RX Delay -69 -> 252, step: 4
5732 10:51:55.308341
5733 10:51:55.311296 Set Vref, RX VrefLevel [Byte0]: 58
5734 10:51:55.314406 [Byte1]: 52
5735 10:51:55.318181
5736 10:51:55.318264 Final RX Vref Byte 0 = 58 to rank0
5737 10:51:55.321808 Final RX Vref Byte 1 = 52 to rank0
5738 10:51:55.324807 Final RX Vref Byte 0 = 58 to rank1
5739 10:51:55.327971 Final RX Vref Byte 1 = 52 to rank1==
5740 10:51:55.331152 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 10:51:55.338208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 10:51:55.338291 ==
5743 10:51:55.338356 DQS Delay:
5744 10:51:55.341026 DQS0 = 0, DQS1 = 0
5745 10:51:55.341111 DQM Delay:
5746 10:51:55.341177 DQM0 = 96, DQM1 = 88
5747 10:51:55.344571 DQ Delay:
5748 10:51:55.347770 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =92
5749 10:51:55.351496 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5750 10:51:55.354526 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5751 10:51:55.358148 DQ12 =98, DQ13 =94, DQ14 =94, DQ15 =94
5752 10:51:55.358230
5753 10:51:55.358295
5754 10:51:55.364566 [DQSOSCAuto] RK0, (LSB)MR18= 0x20a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5755 10:51:55.367937 CH1 RK0: MR19=505, MR18=20A
5756 10:51:55.374538 CH1_RK0: MR19=0x505, MR18=0x20A, DQSOSC=418, MR23=63, INC=62, DEC=41
5757 10:51:55.374621
5758 10:51:55.377540 ----->DramcWriteLeveling(PI) begin...
5759 10:51:55.377624 ==
5760 10:51:55.381045 Dram Type= 6, Freq= 0, CH_1, rank 1
5761 10:51:55.383905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 10:51:55.383988 ==
5763 10:51:55.387487 Write leveling (Byte 0): 24 => 24
5764 10:51:55.390401 Write leveling (Byte 1): 27 => 27
5765 10:51:55.394035 DramcWriteLeveling(PI) end<-----
5766 10:51:55.394117
5767 10:51:55.394182 ==
5768 10:51:55.397193 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 10:51:55.400409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 10:51:55.404130 ==
5771 10:51:55.404212 [Gating] SW mode calibration
5772 10:51:55.413669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5773 10:51:55.416733 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5774 10:51:55.420487 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5775 10:51:55.426438 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 10:51:55.430148 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 10:51:55.436410 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 10:51:55.439648 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 10:51:55.443138 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 10:51:55.449618 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (0 0) (0 0)
5781 10:51:55.452834 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
5782 10:51:55.456094 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 10:51:55.462813 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 10:51:55.466274 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 10:51:55.469253 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 10:51:55.476081 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 10:51:55.479883 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 10:51:55.482659 0 15 24 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
5789 10:51:55.489091 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5790 10:51:55.492555 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 10:51:55.495871 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 10:51:55.502087 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 10:51:55.505912 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 10:51:55.508872 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 10:51:55.515683 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 10:51:55.518725 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 10:51:55.521896 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5798 10:51:55.528657 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 10:51:55.532085 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 10:51:55.535367 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 10:51:55.541991 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 10:51:55.545078 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 10:51:55.548831 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 10:51:55.555296 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 10:51:55.558196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 10:51:55.561529 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 10:51:55.568391 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 10:51:55.571352 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 10:51:55.574832 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 10:51:55.581651 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 10:51:55.584575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 10:51:55.588260 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5813 10:51:55.591577 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5814 10:51:55.597890 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 10:51:55.601209 Total UI for P1: 0, mck2ui 16
5816 10:51:55.604794 best dqsien dly found for B0: ( 1, 2, 26)
5817 10:51:55.608014 Total UI for P1: 0, mck2ui 16
5818 10:51:55.611554 best dqsien dly found for B1: ( 1, 2, 26)
5819 10:51:55.614632 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5820 10:51:55.617629 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5821 10:51:55.617704
5822 10:51:55.621226 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5823 10:51:55.624366 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5824 10:51:55.628371 [Gating] SW calibration Done
5825 10:51:55.628445 ==
5826 10:51:55.631245 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 10:51:55.634137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 10:51:55.634217 ==
5829 10:51:55.637738 RX Vref Scan: 0
5830 10:51:55.637815
5831 10:51:55.640937 RX Vref 0 -> 0, step: 1
5832 10:51:55.641047
5833 10:51:55.641154 RX Delay -80 -> 252, step: 8
5834 10:51:55.647932 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5835 10:51:55.651146 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5836 10:51:55.654199 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5837 10:51:55.657409 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5838 10:51:55.660845 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5839 10:51:55.667568 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5840 10:51:55.670731 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5841 10:51:55.673886 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5842 10:51:55.677535 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5843 10:51:55.680715 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5844 10:51:55.687342 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5845 10:51:55.690803 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5846 10:51:55.693824 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5847 10:51:55.697452 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5848 10:51:55.700176 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5849 10:51:55.706945 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5850 10:51:55.707022 ==
5851 10:51:55.710437 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 10:51:55.713408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 10:51:55.713482 ==
5854 10:51:55.713551 DQS Delay:
5855 10:51:55.717082 DQS0 = 0, DQS1 = 0
5856 10:51:55.717152 DQM Delay:
5857 10:51:55.720209 DQM0 = 93, DQM1 = 88
5858 10:51:55.720286 DQ Delay:
5859 10:51:55.723255 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5860 10:51:55.726937 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5861 10:51:55.729924 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5862 10:51:55.732962 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =99
5863 10:51:55.733034
5864 10:51:55.733095
5865 10:51:55.733160 ==
5866 10:51:55.736762 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 10:51:55.739582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 10:51:55.743305 ==
5869 10:51:55.743382
5870 10:51:55.743444
5871 10:51:55.743508 TX Vref Scan disable
5872 10:51:55.746450 == TX Byte 0 ==
5873 10:51:55.749517 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5874 10:51:55.753124 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5875 10:51:55.756276 == TX Byte 1 ==
5876 10:51:55.759414 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 10:51:55.763280 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 10:51:55.766063 ==
5879 10:51:55.769318 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 10:51:55.772715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 10:51:55.772816 ==
5882 10:51:55.772913
5883 10:51:55.772999
5884 10:51:55.775812 TX Vref Scan disable
5885 10:51:55.775886 == TX Byte 0 ==
5886 10:51:55.782502 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5887 10:51:55.786040 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5888 10:51:55.786115 == TX Byte 1 ==
5889 10:51:55.792380 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5890 10:51:55.795749 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5891 10:51:55.795826
5892 10:51:55.795889 [DATLAT]
5893 10:51:55.798746 Freq=933, CH1 RK1
5894 10:51:55.798885
5895 10:51:55.798964 DATLAT Default: 0xb
5896 10:51:55.802229 0, 0xFFFF, sum = 0
5897 10:51:55.802327 1, 0xFFFF, sum = 0
5898 10:51:55.805626 2, 0xFFFF, sum = 0
5899 10:51:55.809109 3, 0xFFFF, sum = 0
5900 10:51:55.809192 4, 0xFFFF, sum = 0
5901 10:51:55.811842 5, 0xFFFF, sum = 0
5902 10:51:55.811948 6, 0xFFFF, sum = 0
5903 10:51:55.815212 7, 0xFFFF, sum = 0
5904 10:51:55.815293 8, 0xFFFF, sum = 0
5905 10:51:55.819001 9, 0xFFFF, sum = 0
5906 10:51:55.819108 10, 0x0, sum = 1
5907 10:51:55.821814 11, 0x0, sum = 2
5908 10:51:55.821890 12, 0x0, sum = 3
5909 10:51:55.825493 13, 0x0, sum = 4
5910 10:51:55.825569 best_step = 11
5911 10:51:55.825631
5912 10:51:55.825697 ==
5913 10:51:55.828352 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 10:51:55.832125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 10:51:55.832199 ==
5916 10:51:55.835207 RX Vref Scan: 0
5917 10:51:55.835281
5918 10:51:55.838222 RX Vref 0 -> 0, step: 1
5919 10:51:55.838303
5920 10:51:55.838367 RX Delay -69 -> 252, step: 4
5921 10:51:55.846579 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5922 10:51:55.849648 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5923 10:51:55.852826 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5924 10:51:55.856132 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5925 10:51:55.859640 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5926 10:51:55.865847 iDelay=203, Bit 5, Center 104 (7 ~ 202) 196
5927 10:51:55.869425 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5928 10:51:55.873138 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5929 10:51:55.876135 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5930 10:51:55.879821 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5931 10:51:55.882970 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5932 10:51:55.889041 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5933 10:51:55.892589 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5934 10:51:55.896011 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5935 10:51:55.898806 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5936 10:51:55.902328 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5937 10:51:55.906180 ==
5938 10:51:55.908910 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 10:51:55.912342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 10:51:55.912425 ==
5941 10:51:55.912490 DQS Delay:
5942 10:51:55.915760 DQS0 = 0, DQS1 = 0
5943 10:51:55.915845 DQM Delay:
5944 10:51:55.918468 DQM0 = 91, DQM1 = 90
5945 10:51:55.918549 DQ Delay:
5946 10:51:55.922057 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5947 10:51:55.925462 DQ4 =88, DQ5 =104, DQ6 =104, DQ7 =88
5948 10:51:55.928655 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
5949 10:51:55.931609 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =94
5950 10:51:55.931692
5951 10:51:55.931756
5952 10:51:55.938321 [DQSOSCAuto] RK1, (LSB)MR18= 0x1025, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5953 10:51:55.941473 CH1 RK1: MR19=505, MR18=1025
5954 10:51:55.948110 CH1_RK1: MR19=0x505, MR18=0x1025, DQSOSC=410, MR23=63, INC=64, DEC=42
5955 10:51:55.951899 [RxdqsGatingPostProcess] freq 933
5956 10:51:55.958225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 10:51:55.961374 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 10:51:55.965090 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 10:51:55.968263 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 10:51:55.971229 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 10:51:55.971312 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 10:51:55.975006 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 10:51:55.977921 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 10:51:55.981674 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 10:51:55.984531 Pre-setting of DQS Precalculation
5966 10:51:55.991335 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 10:51:55.997962 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 10:51:56.004371 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 10:51:56.004454
5970 10:51:56.004519
5971 10:51:56.007986 [Calibration Summary] 1866 Mbps
5972 10:51:56.010570 CH 0, Rank 0
5973 10:51:56.010651 SW Impedance : PASS
5974 10:51:56.014155 DUTY Scan : NO K
5975 10:51:56.014237 ZQ Calibration : PASS
5976 10:51:56.017709 Jitter Meter : NO K
5977 10:51:56.020570 CBT Training : PASS
5978 10:51:56.020652 Write leveling : PASS
5979 10:51:56.023935 RX DQS gating : PASS
5980 10:51:56.027596 RX DQ/DQS(RDDQC) : PASS
5981 10:51:56.027679 TX DQ/DQS : PASS
5982 10:51:56.030723 RX DATLAT : PASS
5983 10:51:56.033653 RX DQ/DQS(Engine): PASS
5984 10:51:56.033735 TX OE : NO K
5985 10:51:56.037267 All Pass.
5986 10:51:56.037348
5987 10:51:56.037413 CH 0, Rank 1
5988 10:51:56.040335 SW Impedance : PASS
5989 10:51:56.040417 DUTY Scan : NO K
5990 10:51:56.044066 ZQ Calibration : PASS
5991 10:51:56.047081 Jitter Meter : NO K
5992 10:51:56.047164 CBT Training : PASS
5993 10:51:56.050046 Write leveling : PASS
5994 10:51:56.053721 RX DQS gating : PASS
5995 10:51:56.053804 RX DQ/DQS(RDDQC) : PASS
5996 10:51:56.056854 TX DQ/DQS : PASS
5997 10:51:56.060019 RX DATLAT : PASS
5998 10:51:56.060101 RX DQ/DQS(Engine): PASS
5999 10:51:56.063642 TX OE : NO K
6000 10:51:56.063724 All Pass.
6001 10:51:56.063789
6002 10:51:56.066756 CH 1, Rank 0
6003 10:51:56.066895 SW Impedance : PASS
6004 10:51:56.069901 DUTY Scan : NO K
6005 10:51:56.073562 ZQ Calibration : PASS
6006 10:51:56.073643 Jitter Meter : NO K
6007 10:51:56.076464 CBT Training : PASS
6008 10:51:56.080167 Write leveling : PASS
6009 10:51:56.080249 RX DQS gating : PASS
6010 10:51:56.083435 RX DQ/DQS(RDDQC) : PASS
6011 10:51:56.086488 TX DQ/DQS : PASS
6012 10:51:56.086570 RX DATLAT : PASS
6013 10:51:56.090060 RX DQ/DQS(Engine): PASS
6014 10:51:56.090141 TX OE : NO K
6015 10:51:56.093293 All Pass.
6016 10:51:56.093400
6017 10:51:56.093492 CH 1, Rank 1
6018 10:51:56.096464 SW Impedance : PASS
6019 10:51:56.096546 DUTY Scan : NO K
6020 10:51:56.099545 ZQ Calibration : PASS
6021 10:51:56.103013 Jitter Meter : NO K
6022 10:51:56.103095 CBT Training : PASS
6023 10:51:56.106415 Write leveling : PASS
6024 10:51:56.109857 RX DQS gating : PASS
6025 10:51:56.109943 RX DQ/DQS(RDDQC) : PASS
6026 10:51:56.112766 TX DQ/DQS : PASS
6027 10:51:56.116160 RX DATLAT : PASS
6028 10:51:56.116242 RX DQ/DQS(Engine): PASS
6029 10:51:56.119779 TX OE : NO K
6030 10:51:56.119860 All Pass.
6031 10:51:56.119925
6032 10:51:56.122731 DramC Write-DBI off
6033 10:51:56.126144 PER_BANK_REFRESH: Hybrid Mode
6034 10:51:56.126227 TX_TRACKING: ON
6035 10:51:56.135977 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 10:51:56.139504 [FAST_K] Save calibration result to emmc
6037 10:51:56.143000 dramc_set_vcore_voltage set vcore to 650000
6038 10:51:56.146330 Read voltage for 400, 6
6039 10:51:56.146413 Vio18 = 0
6040 10:51:56.146478 Vcore = 650000
6041 10:51:56.149219 Vdram = 0
6042 10:51:56.149327 Vddq = 0
6043 10:51:56.149419 Vmddr = 0
6044 10:51:56.155877 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 10:51:56.159538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 10:51:56.162690 MEM_TYPE=3, freq_sel=20
6047 10:51:56.165698 sv_algorithm_assistance_LP4_800
6048 10:51:56.169363 ============ PULL DRAM RESETB DOWN ============
6049 10:51:56.175593 ========== PULL DRAM RESETB DOWN end =========
6050 10:51:56.179216 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 10:51:56.182139 ===================================
6052 10:51:56.185974 LPDDR4 DRAM CONFIGURATION
6053 10:51:56.189090 ===================================
6054 10:51:56.189172 EX_ROW_EN[0] = 0x0
6055 10:51:56.192273 EX_ROW_EN[1] = 0x0
6056 10:51:56.192355 LP4Y_EN = 0x0
6057 10:51:56.195761 WORK_FSP = 0x0
6058 10:51:56.195843 WL = 0x2
6059 10:51:56.198863 RL = 0x2
6060 10:51:56.198958 BL = 0x2
6061 10:51:56.202048 RPST = 0x0
6062 10:51:56.202130 RD_PRE = 0x0
6063 10:51:56.205780 WR_PRE = 0x1
6064 10:51:56.205862 WR_PST = 0x0
6065 10:51:56.209147 DBI_WR = 0x0
6066 10:51:56.212302 DBI_RD = 0x0
6067 10:51:56.212384 OTF = 0x1
6068 10:51:56.215720 ===================================
6069 10:51:56.218523 ===================================
6070 10:51:56.218605 ANA top config
6071 10:51:56.221951 ===================================
6072 10:51:56.225467 DLL_ASYNC_EN = 0
6073 10:51:56.228872 ALL_SLAVE_EN = 1
6074 10:51:56.232282 NEW_RANK_MODE = 1
6075 10:51:56.235877 DLL_IDLE_MODE = 1
6076 10:51:56.235959 LP45_APHY_COMB_EN = 1
6077 10:51:56.238720 TX_ODT_DIS = 1
6078 10:51:56.241872 NEW_8X_MODE = 1
6079 10:51:56.245136 ===================================
6080 10:51:56.248597 ===================================
6081 10:51:56.251936 data_rate = 800
6082 10:51:56.255003 CKR = 1
6083 10:51:56.255113 DQ_P2S_RATIO = 4
6084 10:51:56.258719 ===================================
6085 10:51:56.261822 CA_P2S_RATIO = 4
6086 10:51:56.265315 DQ_CA_OPEN = 0
6087 10:51:56.268556 DQ_SEMI_OPEN = 1
6088 10:51:56.271539 CA_SEMI_OPEN = 1
6089 10:51:56.274728 CA_FULL_RATE = 0
6090 10:51:56.274873 DQ_CKDIV4_EN = 0
6091 10:51:56.278482 CA_CKDIV4_EN = 1
6092 10:51:56.281682 CA_PREDIV_EN = 0
6093 10:51:56.284651 PH8_DLY = 0
6094 10:51:56.288464 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 10:51:56.291580 DQ_AAMCK_DIV = 0
6096 10:51:56.291662 CA_AAMCK_DIV = 0
6097 10:51:56.294622 CA_ADMCK_DIV = 4
6098 10:51:56.298500 DQ_TRACK_CA_EN = 0
6099 10:51:56.301495 CA_PICK = 800
6100 10:51:56.304530 CA_MCKIO = 400
6101 10:51:56.308124 MCKIO_SEMI = 400
6102 10:51:56.311322 PLL_FREQ = 3016
6103 10:51:56.314371 DQ_UI_PI_RATIO = 32
6104 10:51:56.314454 CA_UI_PI_RATIO = 32
6105 10:51:56.317965 ===================================
6106 10:51:56.321517 ===================================
6107 10:51:56.324398 memory_type:LPDDR4
6108 10:51:56.327783 GP_NUM : 10
6109 10:51:56.327865 SRAM_EN : 1
6110 10:51:56.331067 MD32_EN : 0
6111 10:51:56.334429 ===================================
6112 10:51:56.337527 [ANA_INIT] >>>>>>>>>>>>>>
6113 10:51:56.341000 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 10:51:56.344351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 10:51:56.347759 ===================================
6116 10:51:56.347842 data_rate = 800,PCW = 0X7400
6117 10:51:56.350551 ===================================
6118 10:51:56.357311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 10:51:56.360919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 10:51:56.373756 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 10:51:56.377457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 10:51:56.380590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 10:51:56.383625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 10:51:56.386822 [ANA_INIT] flow start
6125 10:51:56.386925 [ANA_INIT] PLL >>>>>>>>
6126 10:51:56.390357 [ANA_INIT] PLL <<<<<<<<
6127 10:51:56.393464 [ANA_INIT] MIDPI >>>>>>>>
6128 10:51:56.397312 [ANA_INIT] MIDPI <<<<<<<<
6129 10:51:56.397398 [ANA_INIT] DLL >>>>>>>>
6130 10:51:56.400286 [ANA_INIT] flow end
6131 10:51:56.403394 ============ LP4 DIFF to SE enter ============
6132 10:51:56.406926 ============ LP4 DIFF to SE exit ============
6133 10:51:56.409935 [ANA_INIT] <<<<<<<<<<<<<
6134 10:51:56.413655 [Flow] Enable top DCM control >>>>>
6135 10:51:56.416809 [Flow] Enable top DCM control <<<<<
6136 10:51:56.419761 Enable DLL master slave shuffle
6137 10:51:56.426367 ==============================================================
6138 10:51:56.426449 Gating Mode config
6139 10:51:56.433535 ==============================================================
6140 10:51:56.433617 Config description:
6141 10:51:56.442844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 10:51:56.449348 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 10:51:56.455947 SELPH_MODE 0: By rank 1: By Phase
6144 10:51:56.462810 ==============================================================
6145 10:51:56.462913 GAT_TRACK_EN = 0
6146 10:51:56.466253 RX_GATING_MODE = 2
6147 10:51:56.469026 RX_GATING_TRACK_MODE = 2
6148 10:51:56.472868 SELPH_MODE = 1
6149 10:51:56.475965 PICG_EARLY_EN = 1
6150 10:51:56.478997 VALID_LAT_VALUE = 1
6151 10:51:56.485890 ==============================================================
6152 10:51:56.489001 Enter into Gating configuration >>>>
6153 10:51:56.492581 Exit from Gating configuration <<<<
6154 10:51:56.495494 Enter into DVFS_PRE_config >>>>>
6155 10:51:56.505505 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 10:51:56.509234 Exit from DVFS_PRE_config <<<<<
6157 10:51:56.512380 Enter into PICG configuration >>>>
6158 10:51:56.515358 Exit from PICG configuration <<<<
6159 10:51:56.519063 [RX_INPUT] configuration >>>>>
6160 10:51:56.522170 [RX_INPUT] configuration <<<<<
6161 10:51:56.525693 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 10:51:56.531889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 10:51:56.538611 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 10:51:56.541972 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 10:51:56.548875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 10:51:56.555000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 10:51:56.558462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 10:51:56.564733 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 10:51:56.568072 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 10:51:56.571450 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 10:51:56.574969 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 10:51:56.580979 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 10:51:56.584597 ===================================
6174 10:51:56.587754 LPDDR4 DRAM CONFIGURATION
6175 10:51:56.590936 ===================================
6176 10:51:56.591017 EX_ROW_EN[0] = 0x0
6177 10:51:56.594596 EX_ROW_EN[1] = 0x0
6178 10:51:56.594695 LP4Y_EN = 0x0
6179 10:51:56.597532 WORK_FSP = 0x0
6180 10:51:56.597618 WL = 0x2
6181 10:51:56.601259 RL = 0x2
6182 10:51:56.601340 BL = 0x2
6183 10:51:56.604423 RPST = 0x0
6184 10:51:56.604505 RD_PRE = 0x0
6185 10:51:56.607479 WR_PRE = 0x1
6186 10:51:56.607560 WR_PST = 0x0
6187 10:51:56.610679 DBI_WR = 0x0
6188 10:51:56.614466 DBI_RD = 0x0
6189 10:51:56.614548 OTF = 0x1
6190 10:51:56.617467 ===================================
6191 10:51:56.620369 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 10:51:56.627088 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 10:51:56.630702 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 10:51:56.633797 ===================================
6195 10:51:56.636937 LPDDR4 DRAM CONFIGURATION
6196 10:51:56.640672 ===================================
6197 10:51:56.640769 EX_ROW_EN[0] = 0x10
6198 10:51:56.643684 EX_ROW_EN[1] = 0x0
6199 10:51:56.643767 LP4Y_EN = 0x0
6200 10:51:56.647173 WORK_FSP = 0x0
6201 10:51:56.647257 WL = 0x2
6202 10:51:56.650550 RL = 0x2
6203 10:51:56.650633 BL = 0x2
6204 10:51:56.653372 RPST = 0x0
6205 10:51:56.653455 RD_PRE = 0x0
6206 10:51:56.656818 WR_PRE = 0x1
6207 10:51:56.660301 WR_PST = 0x0
6208 10:51:56.660383 DBI_WR = 0x0
6209 10:51:56.663844 DBI_RD = 0x0
6210 10:51:56.663926 OTF = 0x1
6211 10:51:56.666781 ===================================
6212 10:51:56.673286 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 10:51:56.677209 nWR fixed to 30
6214 10:51:56.680960 [ModeRegInit_LP4] CH0 RK0
6215 10:51:56.681042 [ModeRegInit_LP4] CH0 RK1
6216 10:51:56.684276 [ModeRegInit_LP4] CH1 RK0
6217 10:51:56.686884 [ModeRegInit_LP4] CH1 RK1
6218 10:51:56.686965 match AC timing 19
6219 10:51:56.693767 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 10:51:56.696907 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 10:51:56.699896 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 10:51:56.706668 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 10:51:56.709764 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 10:51:56.709837 ==
6225 10:51:56.713506 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 10:51:56.716934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 10:51:56.717017 ==
6228 10:51:56.723294 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 10:51:56.729851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 10:51:56.732809 [CA 0] Center 36 (8~64) winsize 57
6231 10:51:56.736416 [CA 1] Center 36 (8~64) winsize 57
6232 10:51:56.739765 [CA 2] Center 36 (8~64) winsize 57
6233 10:51:56.742717 [CA 3] Center 36 (8~64) winsize 57
6234 10:51:56.746449 [CA 4] Center 36 (8~64) winsize 57
6235 10:51:56.749444 [CA 5] Center 36 (8~64) winsize 57
6236 10:51:56.749525
6237 10:51:56.753146 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 10:51:56.753228
6239 10:51:56.756139 [CATrainingPosCal] consider 1 rank data
6240 10:51:56.759336 u2DelayCellTimex100 = 270/100 ps
6241 10:51:56.762513 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 10:51:56.765866 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 10:51:56.769197 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:51:56.772495 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:51:56.775991 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 10:51:56.779006 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 10:51:56.779081
6248 10:51:56.785913 CA PerBit enable=1, Macro0, CA PI delay=36
6249 10:51:56.785988
6250 10:51:56.788904 [CBTSetCACLKResult] CA Dly = 36
6251 10:51:56.789006 CS Dly: 1 (0~32)
6252 10:51:56.789101 ==
6253 10:51:56.792399 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 10:51:56.795743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 10:51:56.795829 ==
6256 10:51:56.802324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 10:51:56.808920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6258 10:51:56.812106 [CA 0] Center 36 (8~64) winsize 57
6259 10:51:56.815139 [CA 1] Center 36 (8~64) winsize 57
6260 10:51:56.818887 [CA 2] Center 36 (8~64) winsize 57
6261 10:51:56.821982 [CA 3] Center 36 (8~64) winsize 57
6262 10:51:56.825154 [CA 4] Center 36 (8~64) winsize 57
6263 10:51:56.828324 [CA 5] Center 36 (8~64) winsize 57
6264 10:51:56.828407
6265 10:51:56.831828 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6266 10:51:56.831911
6267 10:51:56.834816 [CATrainingPosCal] consider 2 rank data
6268 10:51:56.838423 u2DelayCellTimex100 = 270/100 ps
6269 10:51:56.841564 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 10:51:56.845393 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 10:51:56.848409 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 10:51:56.851550 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 10:51:56.855268 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 10:51:56.858361 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 10:51:56.858443
6276 10:51:56.861427 CA PerBit enable=1, Macro0, CA PI delay=36
6277 10:51:56.865033
6278 10:51:56.865115 [CBTSetCACLKResult] CA Dly = 36
6279 10:51:56.867985 CS Dly: 1 (0~32)
6280 10:51:56.868067
6281 10:51:56.871318 ----->DramcWriteLeveling(PI) begin...
6282 10:51:56.871401 ==
6283 10:51:56.874660 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 10:51:56.878057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 10:51:56.878140 ==
6286 10:51:56.881427 Write leveling (Byte 0): 40 => 8
6287 10:51:56.884412 Write leveling (Byte 1): 32 => 0
6288 10:51:56.888047 DramcWriteLeveling(PI) end<-----
6289 10:51:56.888129
6290 10:51:56.888194 ==
6291 10:51:56.890815 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 10:51:56.894377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 10:51:56.897904 ==
6294 10:51:56.897986 [Gating] SW mode calibration
6295 10:51:56.907652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 10:51:56.910672 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 10:51:56.914317 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 10:51:56.920654 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 10:51:56.923779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 10:51:56.927312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 10:51:56.933614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 10:51:56.937260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 10:51:56.940235 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 10:51:56.946758 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 10:51:56.949931 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 10:51:56.953714 Total UI for P1: 0, mck2ui 16
6307 10:51:56.956870 best dqsien dly found for B0: ( 0, 14, 24)
6308 10:51:56.959962 Total UI for P1: 0, mck2ui 16
6309 10:51:56.963079 best dqsien dly found for B1: ( 0, 14, 24)
6310 10:51:56.966242 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 10:51:56.969917 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 10:51:56.970023
6313 10:51:56.976130 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 10:51:56.979777 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 10:51:56.979863 [Gating] SW calibration Done
6316 10:51:56.983002 ==
6317 10:51:56.986424 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 10:51:56.989784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 10:51:56.989890 ==
6320 10:51:56.989981 RX Vref Scan: 0
6321 10:51:56.990046
6322 10:51:56.992851 RX Vref 0 -> 0, step: 1
6323 10:51:56.992994
6324 10:51:56.995885 RX Delay -410 -> 252, step: 16
6325 10:51:56.999380 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6326 10:51:57.002569 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6327 10:51:57.009165 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6328 10:51:57.012568 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6329 10:51:57.015905 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6330 10:51:57.022263 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6331 10:51:57.025937 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6332 10:51:57.029101 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6333 10:51:57.032158 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6334 10:51:57.039103 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6335 10:51:57.042301 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6336 10:51:57.045648 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6337 10:51:57.049157 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6338 10:51:57.055408 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6339 10:51:57.058551 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6340 10:51:57.062212 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6341 10:51:57.062321 ==
6342 10:51:57.065322 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 10:51:57.071678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 10:51:57.071759 ==
6345 10:51:57.071821 DQS Delay:
6346 10:51:57.075430 DQS0 = 59, DQS1 = 59
6347 10:51:57.075536 DQM Delay:
6348 10:51:57.075628 DQM0 = 17, DQM1 = 10
6349 10:51:57.078523 DQ Delay:
6350 10:51:57.082078 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6351 10:51:57.085085 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6352 10:51:57.085165 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6353 10:51:57.091734 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6354 10:51:57.091814
6355 10:51:57.091877
6356 10:51:57.091935 ==
6357 10:51:57.095079 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 10:51:57.098471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 10:51:57.098555 ==
6360 10:51:57.098619
6361 10:51:57.098679
6362 10:51:57.101740 TX Vref Scan disable
6363 10:51:57.101821 == TX Byte 0 ==
6364 10:51:57.108180 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 10:51:57.111642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 10:51:57.111723 == TX Byte 1 ==
6367 10:51:57.117719 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 10:51:57.121125 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 10:51:57.121207 ==
6370 10:51:57.124426 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 10:51:57.127840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 10:51:57.127922 ==
6373 10:51:57.127986
6374 10:51:57.128045
6375 10:51:57.131252 TX Vref Scan disable
6376 10:51:57.131377 == TX Byte 0 ==
6377 10:51:57.137871 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 10:51:57.141050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 10:51:57.141132 == TX Byte 1 ==
6380 10:51:57.147809 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6381 10:51:57.151262 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6382 10:51:57.151346
6383 10:51:57.151409 [DATLAT]
6384 10:51:57.154100 Freq=400, CH0 RK0
6385 10:51:57.154181
6386 10:51:57.154245 DATLAT Default: 0xf
6387 10:51:57.157628 0, 0xFFFF, sum = 0
6388 10:51:57.157713 1, 0xFFFF, sum = 0
6389 10:51:57.160626 2, 0xFFFF, sum = 0
6390 10:51:57.160708 3, 0xFFFF, sum = 0
6391 10:51:57.164390 4, 0xFFFF, sum = 0
6392 10:51:57.167341 5, 0xFFFF, sum = 0
6393 10:51:57.167451 6, 0xFFFF, sum = 0
6394 10:51:57.170489 7, 0xFFFF, sum = 0
6395 10:51:57.170573 8, 0xFFFF, sum = 0
6396 10:51:57.174075 9, 0xFFFF, sum = 0
6397 10:51:57.174159 10, 0xFFFF, sum = 0
6398 10:51:57.177238 11, 0xFFFF, sum = 0
6399 10:51:57.177323 12, 0xFFFF, sum = 0
6400 10:51:57.180353 13, 0x0, sum = 1
6401 10:51:57.180437 14, 0x0, sum = 2
6402 10:51:57.184137 15, 0x0, sum = 3
6403 10:51:57.184221 16, 0x0, sum = 4
6404 10:51:57.187079 best_step = 14
6405 10:51:57.187162
6406 10:51:57.187227 ==
6407 10:51:57.190538 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 10:51:57.193551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 10:51:57.193634 ==
6410 10:51:57.196864 RX Vref Scan: 1
6411 10:51:57.196990
6412 10:51:57.197084 RX Vref 0 -> 0, step: 1
6413 10:51:57.197171
6414 10:51:57.200304 RX Delay -359 -> 252, step: 8
6415 10:51:57.200412
6416 10:51:57.203887 Set Vref, RX VrefLevel [Byte0]: 63
6417 10:51:57.206638 [Byte1]: 58
6418 10:51:57.211245
6419 10:51:57.211327 Final RX Vref Byte 0 = 63 to rank0
6420 10:51:57.214745 Final RX Vref Byte 1 = 58 to rank0
6421 10:51:57.217885 Final RX Vref Byte 0 = 63 to rank1
6422 10:51:57.221137 Final RX Vref Byte 1 = 58 to rank1==
6423 10:51:57.224507 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 10:51:57.231277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 10:51:57.231360 ==
6426 10:51:57.231426 DQS Delay:
6427 10:51:57.234468 DQS0 = 60, DQS1 = 68
6428 10:51:57.234550 DQM Delay:
6429 10:51:57.234615 DQM0 = 14, DQM1 = 14
6430 10:51:57.237474 DQ Delay:
6431 10:51:57.241187 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6432 10:51:57.244353 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6433 10:51:57.247513 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6434 10:51:57.250593 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6435 10:51:57.250676
6436 10:51:57.250741
6437 10:51:57.257300 [DQSOSCAuto] RK0, (LSB)MR18= 0x8280, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6438 10:51:57.260517 CH0 RK0: MR19=C0C, MR18=8280
6439 10:51:57.267465 CH0_RK0: MR19=0xC0C, MR18=0x8280, DQSOSC=393, MR23=63, INC=382, DEC=254
6440 10:51:57.267549 ==
6441 10:51:57.270437 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 10:51:57.274201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 10:51:57.274317 ==
6444 10:51:57.277286 [Gating] SW mode calibration
6445 10:51:57.283578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 10:51:57.290405 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 10:51:57.293668 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 10:51:57.296507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 10:51:57.303150 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 10:51:57.306591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 10:51:57.313175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 10:51:57.316522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 10:51:57.320053 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 10:51:57.322941 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 10:51:57.330032 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 10:51:57.333255 Total UI for P1: 0, mck2ui 16
6457 10:51:57.336217 best dqsien dly found for B0: ( 0, 14, 24)
6458 10:51:57.339697 Total UI for P1: 0, mck2ui 16
6459 10:51:57.343058 best dqsien dly found for B1: ( 0, 14, 24)
6460 10:51:57.346335 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 10:51:57.349784 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 10:51:57.349867
6463 10:51:57.352972 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 10:51:57.356098 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 10:51:57.359822 [Gating] SW calibration Done
6466 10:51:57.359904 ==
6467 10:51:57.362935 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 10:51:57.366046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 10:51:57.366159 ==
6470 10:51:57.369428 RX Vref Scan: 0
6471 10:51:57.369537
6472 10:51:57.372937 RX Vref 0 -> 0, step: 1
6473 10:51:57.373034
6474 10:51:57.375760 RX Delay -410 -> 252, step: 16
6475 10:51:57.379555 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6476 10:51:57.382740 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6477 10:51:57.385831 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6478 10:51:57.392570 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6479 10:51:57.395703 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6480 10:51:57.399490 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6481 10:51:57.402670 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6482 10:51:57.409195 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6483 10:51:57.412282 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6484 10:51:57.415951 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6485 10:51:57.418817 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6486 10:51:57.425791 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6487 10:51:57.429147 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6488 10:51:57.431988 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6489 10:51:57.435471 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6490 10:51:57.441820 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6491 10:51:57.441900 ==
6492 10:51:57.445522 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 10:51:57.448591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 10:51:57.448669 ==
6495 10:51:57.451899 DQS Delay:
6496 10:51:57.451975 DQS0 = 59, DQS1 = 59
6497 10:51:57.452062 DQM Delay:
6498 10:51:57.455134 DQM0 = 16, DQM1 = 10
6499 10:51:57.455207 DQ Delay:
6500 10:51:57.458296 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6501 10:51:57.462022 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6502 10:51:57.465086 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 10:51:57.468944 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 10:51:57.469021
6505 10:51:57.469101
6506 10:51:57.469182 ==
6507 10:51:57.471937 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 10:51:57.478197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 10:51:57.478275 ==
6510 10:51:57.478355
6511 10:51:57.478437
6512 10:51:57.478511 TX Vref Scan disable
6513 10:51:57.481468 == TX Byte 0 ==
6514 10:51:57.484871 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6515 10:51:57.488498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6516 10:51:57.491636 == TX Byte 1 ==
6517 10:51:57.494556 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6518 10:51:57.498394 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6519 10:51:57.498472 ==
6520 10:51:57.501492 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 10:51:57.507728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 10:51:57.507805 ==
6523 10:51:57.507885
6524 10:51:57.507960
6525 10:51:57.508046 TX Vref Scan disable
6526 10:51:57.511629 == TX Byte 0 ==
6527 10:51:57.514703 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6528 10:51:57.517871 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6529 10:51:57.520880 == TX Byte 1 ==
6530 10:51:57.524355 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6531 10:51:57.527846 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6532 10:51:57.527926
6533 10:51:57.531250 [DATLAT]
6534 10:51:57.531360 Freq=400, CH0 RK1
6535 10:51:57.531461
6536 10:51:57.534578 DATLAT Default: 0xe
6537 10:51:57.534666 0, 0xFFFF, sum = 0
6538 10:51:57.537677 1, 0xFFFF, sum = 0
6539 10:51:57.537753 2, 0xFFFF, sum = 0
6540 10:51:57.540653 3, 0xFFFF, sum = 0
6541 10:51:57.540738 4, 0xFFFF, sum = 0
6542 10:51:57.544130 5, 0xFFFF, sum = 0
6543 10:51:57.547694 6, 0xFFFF, sum = 0
6544 10:51:57.547775 7, 0xFFFF, sum = 0
6545 10:51:57.550432 8, 0xFFFF, sum = 0
6546 10:51:57.550509 9, 0xFFFF, sum = 0
6547 10:51:57.553900 10, 0xFFFF, sum = 0
6548 10:51:57.553979 11, 0xFFFF, sum = 0
6549 10:51:57.557203 12, 0xFFFF, sum = 0
6550 10:51:57.557286 13, 0x0, sum = 1
6551 10:51:57.560645 14, 0x0, sum = 2
6552 10:51:57.560721 15, 0x0, sum = 3
6553 10:51:57.563748 16, 0x0, sum = 4
6554 10:51:57.563833 best_step = 14
6555 10:51:57.563909
6556 10:51:57.563991 ==
6557 10:51:57.566802 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 10:51:57.570526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 10:51:57.573869 ==
6560 10:51:57.573942 RX Vref Scan: 0
6561 10:51:57.574027
6562 10:51:57.577145 RX Vref 0 -> 0, step: 1
6563 10:51:57.577217
6564 10:51:57.580526 RX Delay -359 -> 252, step: 8
6565 10:51:57.587505 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6566 10:51:57.590435 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6567 10:51:57.593340 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6568 10:51:57.597059 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6569 10:51:57.603522 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6570 10:51:57.606663 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6571 10:51:57.609839 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6572 10:51:57.613352 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6573 10:51:57.619978 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6574 10:51:57.623156 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6575 10:51:57.626602 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6576 10:51:57.629689 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6577 10:51:57.636162 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6578 10:51:57.639491 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6579 10:51:57.643010 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6580 10:51:57.649198 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6581 10:51:57.649288 ==
6582 10:51:57.652891 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 10:51:57.656186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 10:51:57.656265 ==
6585 10:51:57.656345 DQS Delay:
6586 10:51:57.659562 DQS0 = 60, DQS1 = 68
6587 10:51:57.659639 DQM Delay:
6588 10:51:57.662516 DQM0 = 12, DQM1 = 14
6589 10:51:57.662614 DQ Delay:
6590 10:51:57.665916 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6591 10:51:57.669362 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6592 10:51:57.672654 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6593 10:51:57.675681 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6594 10:51:57.675758
6595 10:51:57.675844
6596 10:51:57.682452 [DQSOSCAuto] RK1, (LSB)MR18= 0xc177, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6597 10:51:57.685525 CH0 RK1: MR19=C0C, MR18=C177
6598 10:51:57.692357 CH0_RK1: MR19=0xC0C, MR18=0xC177, DQSOSC=385, MR23=63, INC=398, DEC=265
6599 10:51:57.695837 [RxdqsGatingPostProcess] freq 400
6600 10:51:57.702134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 10:51:57.705711 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 10:51:57.705789 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 10:51:57.708800 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 10:51:57.711965 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 10:51:57.715115 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 10:51:57.718736 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 10:51:57.722291 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 10:51:57.725429 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 10:51:57.728580 Pre-setting of DQS Precalculation
6610 10:51:57.734565 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 10:51:57.734647 ==
6612 10:51:57.738353 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 10:51:57.741512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 10:51:57.741594 ==
6615 10:51:57.748170 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 10:51:57.754592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6617 10:51:57.758002 [CA 0] Center 36 (8~64) winsize 57
6618 10:51:57.758085 [CA 1] Center 36 (8~64) winsize 57
6619 10:51:57.761456 [CA 2] Center 36 (8~64) winsize 57
6620 10:51:57.764263 [CA 3] Center 36 (8~64) winsize 57
6621 10:51:57.767791 [CA 4] Center 36 (8~64) winsize 57
6622 10:51:57.771388 [CA 5] Center 36 (8~64) winsize 57
6623 10:51:57.771484
6624 10:51:57.774157 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6625 10:51:57.774245
6626 10:51:57.781466 [CATrainingPosCal] consider 1 rank data
6627 10:51:57.781547 u2DelayCellTimex100 = 270/100 ps
6628 10:51:57.787423 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 10:51:57.790570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 10:51:57.794278 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:51:57.797185 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:51:57.800811 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 10:51:57.803840 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 10:51:57.803921
6635 10:51:57.807595 CA PerBit enable=1, Macro0, CA PI delay=36
6636 10:51:57.807676
6637 10:51:57.810517 [CBTSetCACLKResult] CA Dly = 36
6638 10:51:57.813598 CS Dly: 1 (0~32)
6639 10:51:57.813679 ==
6640 10:51:57.816800 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 10:51:57.820439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 10:51:57.820520 ==
6643 10:51:57.827120 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 10:51:57.833375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6645 10:51:57.836518 [CA 0] Center 36 (8~64) winsize 57
6646 10:51:57.836600 [CA 1] Center 36 (8~64) winsize 57
6647 10:51:57.840106 [CA 2] Center 36 (8~64) winsize 57
6648 10:51:57.843351 [CA 3] Center 36 (8~64) winsize 57
6649 10:51:57.846365 [CA 4] Center 36 (8~64) winsize 57
6650 10:51:57.850012 [CA 5] Center 36 (8~64) winsize 57
6651 10:51:57.850093
6652 10:51:57.852863 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6653 10:51:57.852936
6654 10:51:57.859713 [CATrainingPosCal] consider 2 rank data
6655 10:51:57.859796 u2DelayCellTimex100 = 270/100 ps
6656 10:51:57.866437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 10:51:57.869341 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 10:51:57.873058 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 10:51:57.876255 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 10:51:57.879760 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 10:51:57.882428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 10:51:57.882533
6663 10:51:57.886039 CA PerBit enable=1, Macro0, CA PI delay=36
6664 10:51:57.886115
6665 10:51:57.889580 [CBTSetCACLKResult] CA Dly = 36
6666 10:51:57.893000 CS Dly: 1 (0~32)
6667 10:51:57.893082
6668 10:51:57.895830 ----->DramcWriteLeveling(PI) begin...
6669 10:51:57.895905 ==
6670 10:51:57.898915 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 10:51:57.902571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 10:51:57.902679 ==
6673 10:51:57.906020 Write leveling (Byte 0): 40 => 8
6674 10:51:57.908998 Write leveling (Byte 1): 40 => 8
6675 10:51:57.912168 DramcWriteLeveling(PI) end<-----
6676 10:51:57.912251
6677 10:51:57.912333 ==
6678 10:51:57.915667 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 10:51:57.918816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 10:51:57.918921 ==
6681 10:51:57.922420 [Gating] SW mode calibration
6682 10:51:57.929067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 10:51:57.935297 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 10:51:57.938969 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 10:51:57.941952 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 10:51:57.948949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 10:51:57.952073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 10:51:57.955150 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 10:51:57.961817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 10:51:57.965349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 10:51:57.968222 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 10:51:57.975065 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 10:51:57.978449 Total UI for P1: 0, mck2ui 16
6694 10:51:57.981659 best dqsien dly found for B0: ( 0, 14, 24)
6695 10:51:57.984992 Total UI for P1: 0, mck2ui 16
6696 10:51:57.988421 best dqsien dly found for B1: ( 0, 14, 24)
6697 10:51:57.991578 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 10:51:57.994801 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 10:51:57.994921
6700 10:51:57.998060 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 10:51:58.001610 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 10:51:58.004827 [Gating] SW calibration Done
6703 10:51:58.004901 ==
6704 10:51:58.007778 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 10:51:58.011233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 10:51:58.011314 ==
6707 10:51:58.014929 RX Vref Scan: 0
6708 10:51:58.015035
6709 10:51:58.017908 RX Vref 0 -> 0, step: 1
6710 10:51:58.017984
6711 10:51:58.018082 RX Delay -410 -> 252, step: 16
6712 10:51:58.025029 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6713 10:51:58.028209 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6714 10:51:58.031319 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6715 10:51:58.037982 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6716 10:51:58.041050 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6717 10:51:58.044711 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6718 10:51:58.047745 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6719 10:51:58.054541 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6720 10:51:58.057809 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6721 10:51:58.060986 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 10:51:58.064419 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6723 10:51:58.071128 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6724 10:51:58.074089 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6725 10:51:58.077572 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6726 10:51:58.081164 iDelay=230, Bit 14, Center -51 (-314 ~ 213) 528
6727 10:51:58.087320 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6728 10:51:58.087481 ==
6729 10:51:58.090377 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 10:51:58.093773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 10:51:58.093900 ==
6732 10:51:58.097168 DQS Delay:
6733 10:51:58.097250 DQS0 = 51, DQS1 = 67
6734 10:51:58.097334 DQM Delay:
6735 10:51:58.100467 DQM0 = 12, DQM1 = 18
6736 10:51:58.100545 DQ Delay:
6737 10:51:58.103495 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6738 10:51:58.107232 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6739 10:51:58.110223 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6740 10:51:58.113886 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =32
6741 10:51:58.113989
6742 10:51:58.114088
6743 10:51:58.114192 ==
6744 10:51:58.116976 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 10:51:58.120151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 10:51:58.123778 ==
6747 10:51:58.123854
6748 10:51:58.123938
6749 10:51:58.124014 TX Vref Scan disable
6750 10:51:58.126729 == TX Byte 0 ==
6751 10:51:58.130367 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 10:51:58.133404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 10:51:58.136405 == TX Byte 1 ==
6754 10:51:58.139949 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 10:51:58.143711 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 10:51:58.143788 ==
6757 10:51:58.146880 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 10:51:58.153522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 10:51:58.153602 ==
6760 10:51:58.153683
6761 10:51:58.153766
6762 10:51:58.153840 TX Vref Scan disable
6763 10:51:58.156635 == TX Byte 0 ==
6764 10:51:58.159797 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 10:51:58.162845 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 10:51:58.166507 == TX Byte 1 ==
6767 10:51:58.169587 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 10:51:58.172740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 10:51:58.172818
6770 10:51:58.176264 [DATLAT]
6771 10:51:58.176369 Freq=400, CH1 RK0
6772 10:51:58.176478
6773 10:51:58.179341 DATLAT Default: 0xf
6774 10:51:58.179417 0, 0xFFFF, sum = 0
6775 10:51:58.182957 1, 0xFFFF, sum = 0
6776 10:51:58.183034 2, 0xFFFF, sum = 0
6777 10:51:58.185872 3, 0xFFFF, sum = 0
6778 10:51:58.185982 4, 0xFFFF, sum = 0
6779 10:51:58.189326 5, 0xFFFF, sum = 0
6780 10:51:58.189411 6, 0xFFFF, sum = 0
6781 10:51:58.192762 7, 0xFFFF, sum = 0
6782 10:51:58.192841 8, 0xFFFF, sum = 0
6783 10:51:58.196184 9, 0xFFFF, sum = 0
6784 10:51:58.199012 10, 0xFFFF, sum = 0
6785 10:51:58.199093 11, 0xFFFF, sum = 0
6786 10:51:58.202406 12, 0xFFFF, sum = 0
6787 10:51:58.202481 13, 0x0, sum = 1
6788 10:51:58.205621 14, 0x0, sum = 2
6789 10:51:58.205696 15, 0x0, sum = 3
6790 10:51:58.209177 16, 0x0, sum = 4
6791 10:51:58.209284 best_step = 14
6792 10:51:58.209384
6793 10:51:58.209474 ==
6794 10:51:58.212444 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 10:51:58.215548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 10:51:58.215646 ==
6797 10:51:58.219124 RX Vref Scan: 1
6798 10:51:58.219200
6799 10:51:58.222240 RX Vref 0 -> 0, step: 1
6800 10:51:58.222312
6801 10:51:58.222380 RX Delay -375 -> 252, step: 8
6802 10:51:58.225430
6803 10:51:58.225500 Set Vref, RX VrefLevel [Byte0]: 58
6804 10:51:58.229099 [Byte1]: 52
6805 10:51:58.234474
6806 10:51:58.234547 Final RX Vref Byte 0 = 58 to rank0
6807 10:51:58.238132 Final RX Vref Byte 1 = 52 to rank0
6808 10:51:58.241075 Final RX Vref Byte 0 = 58 to rank1
6809 10:51:58.244799 Final RX Vref Byte 1 = 52 to rank1==
6810 10:51:58.247871 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 10:51:58.254477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 10:51:58.254556 ==
6813 10:51:58.254622 DQS Delay:
6814 10:51:58.257916 DQS0 = 56, DQS1 = 64
6815 10:51:58.257989 DQM Delay:
6816 10:51:58.258056 DQM0 = 13, DQM1 = 11
6817 10:51:58.260724 DQ Delay:
6818 10:51:58.264574 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6819 10:51:58.267682 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6820 10:51:58.267769 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6821 10:51:58.274390 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6822 10:51:58.274501
6823 10:51:58.274596
6824 10:51:58.280434 [DQSOSCAuto] RK0, (LSB)MR18= 0x5366, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6825 10:51:58.284129 CH1 RK0: MR19=C0C, MR18=5366
6826 10:51:58.290731 CH1_RK0: MR19=0xC0C, MR18=0x5366, DQSOSC=396, MR23=63, INC=376, DEC=251
6827 10:51:58.290848 ==
6828 10:51:58.293792 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 10:51:58.297357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 10:51:58.297469 ==
6831 10:51:58.300767 [Gating] SW mode calibration
6832 10:51:58.307272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 10:51:58.313961 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 10:51:58.317238 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 10:51:58.320143 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 10:51:58.327425 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 10:51:58.330401 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 10:51:58.333146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 10:51:58.339891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 10:51:58.343543 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 10:51:58.346450 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 10:51:58.353210 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 10:51:58.356331 Total UI for P1: 0, mck2ui 16
6844 10:51:58.359870 best dqsien dly found for B0: ( 0, 14, 24)
6845 10:51:58.362954 Total UI for P1: 0, mck2ui 16
6846 10:51:58.366094 best dqsien dly found for B1: ( 0, 14, 24)
6847 10:51:58.369861 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 10:51:58.372919 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 10:51:58.373002
6850 10:51:58.376380 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 10:51:58.379288 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 10:51:58.382821 [Gating] SW calibration Done
6853 10:51:58.382943 ==
6854 10:51:58.385865 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 10:51:58.389585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 10:51:58.389694 ==
6857 10:51:58.393004 RX Vref Scan: 0
6858 10:51:58.393080
6859 10:51:58.396329 RX Vref 0 -> 0, step: 1
6860 10:51:58.396403
6861 10:51:58.396466 RX Delay -410 -> 252, step: 16
6862 10:51:58.402630 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6863 10:51:58.406112 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 10:51:58.409647 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6865 10:51:58.415946 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6866 10:51:58.419559 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6867 10:51:58.422447 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6868 10:51:58.425985 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 10:51:58.432208 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6870 10:51:58.435612 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6871 10:51:58.438723 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6872 10:51:58.442384 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 10:51:58.448845 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6874 10:51:58.451868 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6875 10:51:58.455539 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6876 10:51:58.461589 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6877 10:51:58.465171 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6878 10:51:58.465271 ==
6879 10:51:58.468357 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 10:51:58.471467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 10:51:58.471578 ==
6882 10:51:58.475190 DQS Delay:
6883 10:51:58.475289 DQS0 = 59, DQS1 = 59
6884 10:51:58.475370 DQM Delay:
6885 10:51:58.478149 DQM0 = 19, DQM1 = 14
6886 10:51:58.478289 DQ Delay:
6887 10:51:58.481368 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6888 10:51:58.485139 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6889 10:51:58.488189 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6890 10:51:58.491115 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6891 10:51:58.491198
6892 10:51:58.491263
6893 10:51:58.491324 ==
6894 10:51:58.494754 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 10:51:58.501106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 10:51:58.501190 ==
6897 10:51:58.501255
6898 10:51:58.501317
6899 10:51:58.501375 TX Vref Scan disable
6900 10:51:58.504778 == TX Byte 0 ==
6901 10:51:58.507663 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6902 10:51:58.511281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6903 10:51:58.514146 == TX Byte 1 ==
6904 10:51:58.517580 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6905 10:51:58.520989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6906 10:51:58.523994 ==
6907 10:51:58.524081 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 10:51:58.530709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 10:51:58.530792 ==
6910 10:51:58.530898
6911 10:51:58.530961
6912 10:51:58.534099 TX Vref Scan disable
6913 10:51:58.534173 == TX Byte 0 ==
6914 10:51:58.537296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6915 10:51:58.543485 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6916 10:51:58.543572 == TX Byte 1 ==
6917 10:51:58.547275 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6918 10:51:58.553530 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6919 10:51:58.553639
6920 10:51:58.553735 [DATLAT]
6921 10:51:58.553826 Freq=400, CH1 RK1
6922 10:51:58.553895
6923 10:51:58.557234 DATLAT Default: 0xe
6924 10:51:58.557335 0, 0xFFFF, sum = 0
6925 10:51:58.560372 1, 0xFFFF, sum = 0
6926 10:51:58.563434 2, 0xFFFF, sum = 0
6927 10:51:58.563518 3, 0xFFFF, sum = 0
6928 10:51:58.567069 4, 0xFFFF, sum = 0
6929 10:51:58.567164 5, 0xFFFF, sum = 0
6930 10:51:58.570088 6, 0xFFFF, sum = 0
6931 10:51:58.570179 7, 0xFFFF, sum = 0
6932 10:51:58.573318 8, 0xFFFF, sum = 0
6933 10:51:58.573420 9, 0xFFFF, sum = 0
6934 10:51:58.577044 10, 0xFFFF, sum = 0
6935 10:51:58.577121 11, 0xFFFF, sum = 0
6936 10:51:58.580168 12, 0xFFFF, sum = 0
6937 10:51:58.580242 13, 0x0, sum = 1
6938 10:51:58.583084 14, 0x0, sum = 2
6939 10:51:58.583158 15, 0x0, sum = 3
6940 10:51:58.586361 16, 0x0, sum = 4
6941 10:51:58.586436 best_step = 14
6942 10:51:58.586497
6943 10:51:58.586556 ==
6944 10:51:58.589899 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 10:51:58.596732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 10:51:58.596835 ==
6947 10:51:58.596927 RX Vref Scan: 0
6948 10:51:58.597015
6949 10:51:58.599848 RX Vref 0 -> 0, step: 1
6950 10:51:58.599923
6951 10:51:58.602752 RX Delay -359 -> 252, step: 8
6952 10:51:58.609570 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6953 10:51:58.613206 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6954 10:51:58.616119 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6955 10:51:58.619649 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6956 10:51:58.625997 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6957 10:51:58.629455 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6958 10:51:58.632919 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6959 10:51:58.635856 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6960 10:51:58.642351 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6961 10:51:58.645961 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6962 10:51:58.648981 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6963 10:51:58.655791 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6964 10:51:58.658810 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6965 10:51:58.662338 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6966 10:51:58.665716 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6967 10:51:58.672446 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6968 10:51:58.672529 ==
6969 10:51:58.675558 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 10:51:58.678744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 10:51:58.678835 ==
6972 10:51:58.678933 DQS Delay:
6973 10:51:58.681895 DQS0 = 60, DQS1 = 64
6974 10:51:58.681977 DQM Delay:
6975 10:51:58.685521 DQM0 = 13, DQM1 = 10
6976 10:51:58.685606 DQ Delay:
6977 10:51:58.688475 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6978 10:51:58.692168 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6979 10:51:58.695184 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6980 10:51:58.698736 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6981 10:51:58.698819
6982 10:51:58.698924
6983 10:51:58.708673 [DQSOSCAuto] RK1, (LSB)MR18= 0x72a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6984 10:51:58.708758 CH1 RK1: MR19=C0C, MR18=72A3
6985 10:51:58.714769 CH1_RK1: MR19=0xC0C, MR18=0x72A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6986 10:51:58.718575 [RxdqsGatingPostProcess] freq 400
6987 10:51:58.724820 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 10:51:58.728364 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 10:51:58.731236 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 10:51:58.734744 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 10:51:58.738081 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 10:51:58.741204 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 10:51:58.744310 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 10:51:58.747607 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 10:51:58.747692 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 10:51:58.751372 Pre-setting of DQS Precalculation
6997 10:51:58.757949 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 10:51:58.764168 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 10:51:58.771071 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 10:51:58.771155
7001 10:51:58.771221
7002 10:51:58.774095 [Calibration Summary] 800 Mbps
7003 10:51:58.777364 CH 0, Rank 0
7004 10:51:58.777446 SW Impedance : PASS
7005 10:51:58.781007 DUTY Scan : NO K
7006 10:51:58.784048 ZQ Calibration : PASS
7007 10:51:58.784131 Jitter Meter : NO K
7008 10:51:58.787186 CBT Training : PASS
7009 10:51:58.790747 Write leveling : PASS
7010 10:51:58.790875 RX DQS gating : PASS
7011 10:51:58.793964 RX DQ/DQS(RDDQC) : PASS
7012 10:51:58.794046 TX DQ/DQS : PASS
7013 10:51:58.797192 RX DATLAT : PASS
7014 10:51:58.800749 RX DQ/DQS(Engine): PASS
7015 10:51:58.800832 TX OE : NO K
7016 10:51:58.803746 All Pass.
7017 10:51:58.803828
7018 10:51:58.803893 CH 0, Rank 1
7019 10:51:58.807233 SW Impedance : PASS
7020 10:51:58.807316 DUTY Scan : NO K
7021 10:51:58.810346 ZQ Calibration : PASS
7022 10:51:58.813428 Jitter Meter : NO K
7023 10:51:58.813511 CBT Training : PASS
7024 10:51:58.817170 Write leveling : NO K
7025 10:51:58.820403 RX DQS gating : PASS
7026 10:51:58.820486 RX DQ/DQS(RDDQC) : PASS
7027 10:51:58.823368 TX DQ/DQS : PASS
7028 10:51:58.826975 RX DATLAT : PASS
7029 10:51:58.827058 RX DQ/DQS(Engine): PASS
7030 10:51:58.829886 TX OE : NO K
7031 10:51:58.829995 All Pass.
7032 10:51:58.830068
7033 10:51:58.833186 CH 1, Rank 0
7034 10:51:58.833287 SW Impedance : PASS
7035 10:51:58.836402 DUTY Scan : NO K
7036 10:51:58.840026 ZQ Calibration : PASS
7037 10:51:58.840101 Jitter Meter : NO K
7038 10:51:58.843544 CBT Training : PASS
7039 10:51:58.847127 Write leveling : PASS
7040 10:51:58.847206 RX DQS gating : PASS
7041 10:51:58.849858 RX DQ/DQS(RDDQC) : PASS
7042 10:51:58.853017 TX DQ/DQS : PASS
7043 10:51:58.853119 RX DATLAT : PASS
7044 10:51:58.856723 RX DQ/DQS(Engine): PASS
7045 10:51:58.859726 TX OE : NO K
7046 10:51:58.859812 All Pass.
7047 10:51:58.859880
7048 10:51:58.859950 CH 1, Rank 1
7049 10:51:58.862795 SW Impedance : PASS
7050 10:51:58.866456 DUTY Scan : NO K
7051 10:51:58.866534 ZQ Calibration : PASS
7052 10:51:58.869482 Jitter Meter : NO K
7053 10:51:58.873112 CBT Training : PASS
7054 10:51:58.873195 Write leveling : NO K
7055 10:51:58.876184 RX DQS gating : PASS
7056 10:51:58.879741 RX DQ/DQS(RDDQC) : PASS
7057 10:51:58.879824 TX DQ/DQS : PASS
7058 10:51:58.882591 RX DATLAT : PASS
7059 10:51:58.882700 RX DQ/DQS(Engine): PASS
7060 10:51:58.885972 TX OE : NO K
7061 10:51:58.886081 All Pass.
7062 10:51:58.886174
7063 10:51:58.889359 DramC Write-DBI off
7064 10:51:58.892803 PER_BANK_REFRESH: Hybrid Mode
7065 10:51:58.892906 TX_TRACKING: ON
7066 10:51:58.902637 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 10:51:58.905708 [FAST_K] Save calibration result to emmc
7068 10:51:58.908816 dramc_set_vcore_voltage set vcore to 725000
7069 10:51:58.912447 Read voltage for 1600, 0
7070 10:51:58.912548 Vio18 = 0
7071 10:51:58.915428 Vcore = 725000
7072 10:51:58.915502 Vdram = 0
7073 10:51:58.915563 Vddq = 0
7074 10:51:58.915621 Vmddr = 0
7075 10:51:58.922296 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 10:51:58.928733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 10:51:58.928834 MEM_TYPE=3, freq_sel=13
7078 10:51:58.932197 sv_algorithm_assistance_LP4_3733
7079 10:51:58.938775 ============ PULL DRAM RESETB DOWN ============
7080 10:51:58.942232 ========== PULL DRAM RESETB DOWN end =========
7081 10:51:58.945024 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 10:51:58.948631 ===================================
7083 10:51:58.952036 LPDDR4 DRAM CONFIGURATION
7084 10:51:58.954906 ===================================
7085 10:51:58.955015 EX_ROW_EN[0] = 0x0
7086 10:51:58.958562 EX_ROW_EN[1] = 0x0
7087 10:51:58.962291 LP4Y_EN = 0x0
7088 10:51:58.962399 WORK_FSP = 0x1
7089 10:51:58.965375 WL = 0x5
7090 10:51:58.965485 RL = 0x5
7091 10:51:58.968043 BL = 0x2
7092 10:51:58.968126 RPST = 0x0
7093 10:51:58.971773 RD_PRE = 0x0
7094 10:51:58.971883 WR_PRE = 0x1
7095 10:51:58.974860 WR_PST = 0x1
7096 10:51:58.974972 DBI_WR = 0x0
7097 10:51:58.978528 DBI_RD = 0x0
7098 10:51:58.978636 OTF = 0x1
7099 10:51:58.981579 ===================================
7100 10:51:58.984794 ===================================
7101 10:51:58.987847 ANA top config
7102 10:51:58.991409 ===================================
7103 10:51:58.994602 DLL_ASYNC_EN = 0
7104 10:51:58.994710 ALL_SLAVE_EN = 0
7105 10:51:58.997595 NEW_RANK_MODE = 1
7106 10:51:59.001512 DLL_IDLE_MODE = 1
7107 10:51:59.004368 LP45_APHY_COMB_EN = 1
7108 10:51:59.004476 TX_ODT_DIS = 0
7109 10:51:59.007985 NEW_8X_MODE = 1
7110 10:51:59.011098 ===================================
7111 10:51:59.014202 ===================================
7112 10:51:59.018048 data_rate = 3200
7113 10:51:59.021168 CKR = 1
7114 10:51:59.024140 DQ_P2S_RATIO = 8
7115 10:51:59.027862 ===================================
7116 10:51:59.030855 CA_P2S_RATIO = 8
7117 10:51:59.034047 DQ_CA_OPEN = 0
7118 10:51:59.034149 DQ_SEMI_OPEN = 0
7119 10:51:59.037209 CA_SEMI_OPEN = 0
7120 10:51:59.040747 CA_FULL_RATE = 0
7121 10:51:59.043895 DQ_CKDIV4_EN = 0
7122 10:51:59.047572 CA_CKDIV4_EN = 0
7123 10:51:59.050484 CA_PREDIV_EN = 0
7124 10:51:59.050595 PH8_DLY = 12
7125 10:51:59.054056 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 10:51:59.057241 DQ_AAMCK_DIV = 4
7127 10:51:59.060546 CA_AAMCK_DIV = 4
7128 10:51:59.063949 CA_ADMCK_DIV = 4
7129 10:51:59.066670 DQ_TRACK_CA_EN = 0
7130 10:51:59.070041 CA_PICK = 1600
7131 10:51:59.070157 CA_MCKIO = 1600
7132 10:51:59.073519 MCKIO_SEMI = 0
7133 10:51:59.077118 PLL_FREQ = 3068
7134 10:51:59.080042 DQ_UI_PI_RATIO = 32
7135 10:51:59.083805 CA_UI_PI_RATIO = 0
7136 10:51:59.087027 ===================================
7137 10:51:59.090053 ===================================
7138 10:51:59.093707 memory_type:LPDDR4
7139 10:51:59.093815 GP_NUM : 10
7140 10:51:59.096690 SRAM_EN : 1
7141 10:51:59.096772 MD32_EN : 0
7142 10:51:59.100122 ===================================
7143 10:51:59.103591 [ANA_INIT] >>>>>>>>>>>>>>
7144 10:51:59.106701 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 10:51:59.109920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 10:51:59.112886 ===================================
7147 10:51:59.116530 data_rate = 3200,PCW = 0X7600
7148 10:51:59.119701 ===================================
7149 10:51:59.122774 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 10:51:59.129707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 10:51:59.132764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 10:51:59.139636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 10:51:59.143230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 10:51:59.146219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 10:51:59.146320 [ANA_INIT] flow start
7156 10:51:59.149424 [ANA_INIT] PLL >>>>>>>>
7157 10:51:59.152568 [ANA_INIT] PLL <<<<<<<<
7158 10:51:59.152650 [ANA_INIT] MIDPI >>>>>>>>
7159 10:51:59.156194 [ANA_INIT] MIDPI <<<<<<<<
7160 10:51:59.159629 [ANA_INIT] DLL >>>>>>>>
7161 10:51:59.162616 [ANA_INIT] DLL <<<<<<<<
7162 10:51:59.162740 [ANA_INIT] flow end
7163 10:51:59.166052 ============ LP4 DIFF to SE enter ============
7164 10:51:59.172526 ============ LP4 DIFF to SE exit ============
7165 10:51:59.172608 [ANA_INIT] <<<<<<<<<<<<<
7166 10:51:59.175931 [Flow] Enable top DCM control >>>>>
7167 10:51:59.179478 [Flow] Enable top DCM control <<<<<
7168 10:51:59.182490 Enable DLL master slave shuffle
7169 10:51:59.189169 ==============================================================
7170 10:51:59.189252 Gating Mode config
7171 10:51:59.195348 ==============================================================
7172 10:51:59.198993 Config description:
7173 10:51:59.208467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 10:51:59.215157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 10:51:59.218627 SELPH_MODE 0: By rank 1: By Phase
7176 10:51:59.225263 ==============================================================
7177 10:51:59.228455 GAT_TRACK_EN = 1
7178 10:51:59.231875 RX_GATING_MODE = 2
7179 10:51:59.234735 RX_GATING_TRACK_MODE = 2
7180 10:51:59.234888 SELPH_MODE = 1
7181 10:51:59.238389 PICG_EARLY_EN = 1
7182 10:51:59.241540 VALID_LAT_VALUE = 1
7183 10:51:59.248487 ==============================================================
7184 10:51:59.251444 Enter into Gating configuration >>>>
7185 10:51:59.254342 Exit from Gating configuration <<<<
7186 10:51:59.258102 Enter into DVFS_PRE_config >>>>>
7187 10:51:59.267809 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 10:51:59.271584 Exit from DVFS_PRE_config <<<<<
7189 10:51:59.274533 Enter into PICG configuration >>>>
7190 10:51:59.277699 Exit from PICG configuration <<<<
7191 10:51:59.281109 [RX_INPUT] configuration >>>>>
7192 10:51:59.284067 [RX_INPUT] configuration <<<<<
7193 10:51:59.290472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 10:51:59.293853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 10:51:59.300338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 10:51:59.307319 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 10:51:59.313866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 10:51:59.320574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 10:51:59.323477 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 10:51:59.327377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 10:51:59.330211 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 10:51:59.336555 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 10:51:59.340247 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 10:51:59.343341 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 10:51:59.346448 ===================================
7206 10:51:59.350101 LPDDR4 DRAM CONFIGURATION
7207 10:51:59.353278 ===================================
7208 10:51:59.356342 EX_ROW_EN[0] = 0x0
7209 10:51:59.356428 EX_ROW_EN[1] = 0x0
7210 10:51:59.360071 LP4Y_EN = 0x0
7211 10:51:59.360160 WORK_FSP = 0x1
7212 10:51:59.363109 WL = 0x5
7213 10:51:59.363194 RL = 0x5
7214 10:51:59.366742 BL = 0x2
7215 10:51:59.366826 RPST = 0x0
7216 10:51:59.369633 RD_PRE = 0x0
7217 10:51:59.369711 WR_PRE = 0x1
7218 10:51:59.372763 WR_PST = 0x1
7219 10:51:59.372838 DBI_WR = 0x0
7220 10:51:59.376214 DBI_RD = 0x0
7221 10:51:59.376303 OTF = 0x1
7222 10:51:59.379547 ===================================
7223 10:51:59.386072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 10:51:59.389552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 10:51:59.392867 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 10:51:59.395940 ===================================
7227 10:51:59.399349 LPDDR4 DRAM CONFIGURATION
7228 10:51:59.402223 ===================================
7229 10:51:59.405717 EX_ROW_EN[0] = 0x10
7230 10:51:59.405824 EX_ROW_EN[1] = 0x0
7231 10:51:59.409255 LP4Y_EN = 0x0
7232 10:51:59.409333 WORK_FSP = 0x1
7233 10:51:59.412325 WL = 0x5
7234 10:51:59.412402 RL = 0x5
7235 10:51:59.415397 BL = 0x2
7236 10:51:59.415470 RPST = 0x0
7237 10:51:59.419123 RD_PRE = 0x0
7238 10:51:59.419205 WR_PRE = 0x1
7239 10:51:59.422107 WR_PST = 0x1
7240 10:51:59.422189 DBI_WR = 0x0
7241 10:51:59.425649 DBI_RD = 0x0
7242 10:51:59.428568 OTF = 0x1
7243 10:51:59.431971 ===================================
7244 10:51:59.435287 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 10:51:59.435364 ==
7246 10:51:59.439018 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 10:51:59.445090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 10:51:59.445167 ==
7249 10:51:59.448857 [Duty_Offset_Calibration]
7250 10:51:59.448933 B0:2 B1:0 CA:3
7251 10:51:59.449004
7252 10:51:59.451873 [DutyScan_Calibration_Flow] k_type=0
7253 10:51:59.461583
7254 10:51:59.461659 ==CLK 0==
7255 10:51:59.464842 Final CLK duty delay cell = 0
7256 10:51:59.468524 [0] MAX Duty = 5031%(X100), DQS PI = 12
7257 10:51:59.471439 [0] MIN Duty = 4875%(X100), DQS PI = 54
7258 10:51:59.475059 [0] AVG Duty = 4953%(X100)
7259 10:51:59.475143
7260 10:51:59.478412 CH0 CLK Duty spec in!! Max-Min= 156%
7261 10:51:59.481386 [DutyScan_Calibration_Flow] ====Done====
7262 10:51:59.481482
7263 10:51:59.484853 [DutyScan_Calibration_Flow] k_type=1
7264 10:51:59.501853
7265 10:51:59.501934 ==DQS 0 ==
7266 10:51:59.504829 Final DQS duty delay cell = 0
7267 10:51:59.508349 [0] MAX Duty = 5125%(X100), DQS PI = 30
7268 10:51:59.511696 [0] MIN Duty = 4875%(X100), DQS PI = 48
7269 10:51:59.514582 [0] AVG Duty = 5000%(X100)
7270 10:51:59.514656
7271 10:51:59.514718 ==DQS 1 ==
7272 10:51:59.518432 Final DQS duty delay cell = 0
7273 10:51:59.521480 [0] MAX Duty = 5156%(X100), DQS PI = 32
7274 10:51:59.524463 [0] MIN Duty = 5031%(X100), DQS PI = 14
7275 10:51:59.528028 [0] AVG Duty = 5093%(X100)
7276 10:51:59.528111
7277 10:51:59.531517 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7278 10:51:59.531589
7279 10:51:59.534546 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7280 10:51:59.538113 [DutyScan_Calibration_Flow] ====Done====
7281 10:51:59.538188
7282 10:51:59.541102 [DutyScan_Calibration_Flow] k_type=3
7283 10:51:59.559647
7284 10:51:59.559744 ==DQM 0 ==
7285 10:51:59.563292 Final DQM duty delay cell = 0
7286 10:51:59.566453 [0] MAX Duty = 5156%(X100), DQS PI = 30
7287 10:51:59.569816 [0] MIN Duty = 4875%(X100), DQS PI = 0
7288 10:51:59.573259 [0] AVG Duty = 5015%(X100)
7289 10:51:59.573340
7290 10:51:59.573404 ==DQM 1 ==
7291 10:51:59.576126 Final DQM duty delay cell = 4
7292 10:51:59.579289 [4] MAX Duty = 5187%(X100), DQS PI = 60
7293 10:51:59.582511 [4] MIN Duty = 5031%(X100), DQS PI = 12
7294 10:51:59.585660 [4] AVG Duty = 5109%(X100)
7295 10:51:59.585731
7296 10:51:59.589210 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7297 10:51:59.589280
7298 10:51:59.592722 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7299 10:51:59.595707 [DutyScan_Calibration_Flow] ====Done====
7300 10:51:59.595787
7301 10:51:59.599127 [DutyScan_Calibration_Flow] k_type=2
7302 10:51:59.616145
7303 10:51:59.616224 ==DQ 0 ==
7304 10:51:59.619119 Final DQ duty delay cell = -4
7305 10:51:59.622467 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7306 10:51:59.626214 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7307 10:51:59.629102 [-4] AVG Duty = 4938%(X100)
7308 10:51:59.629181
7309 10:51:59.629242 ==DQ 1 ==
7310 10:51:59.632736 Final DQ duty delay cell = 0
7311 10:51:59.635945 [0] MAX Duty = 5156%(X100), DQS PI = 60
7312 10:51:59.639548 [0] MIN Duty = 5000%(X100), DQS PI = 16
7313 10:51:59.642666 [0] AVG Duty = 5078%(X100)
7314 10:51:59.642799
7315 10:51:59.645725 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7316 10:51:59.645796
7317 10:51:59.649054 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7318 10:51:59.652531 [DutyScan_Calibration_Flow] ====Done====
7319 10:51:59.652628 ==
7320 10:51:59.655668 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 10:51:59.658871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 10:51:59.658957 ==
7323 10:51:59.662451 [Duty_Offset_Calibration]
7324 10:51:59.662547 B0:1 B1:-2 CA:0
7325 10:51:59.662640
7326 10:51:59.665481 [DutyScan_Calibration_Flow] k_type=0
7327 10:51:59.676548
7328 10:51:59.676623 ==CLK 0==
7329 10:51:59.680169 Final CLK duty delay cell = 0
7330 10:51:59.683232 [0] MAX Duty = 5093%(X100), DQS PI = 22
7331 10:51:59.686392 [0] MIN Duty = 4844%(X100), DQS PI = 58
7332 10:51:59.689503 [0] AVG Duty = 4968%(X100)
7333 10:51:59.689583
7334 10:51:59.693272 CH1 CLK Duty spec in!! Max-Min= 249%
7335 10:51:59.696252 [DutyScan_Calibration_Flow] ====Done====
7336 10:51:59.696334
7337 10:51:59.699886 [DutyScan_Calibration_Flow] k_type=1
7338 10:51:59.715430
7339 10:51:59.715511 ==DQS 0 ==
7340 10:51:59.719100 Final DQS duty delay cell = -4
7341 10:51:59.722205 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7342 10:51:59.725865 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7343 10:51:59.728546 [-4] AVG Duty = 4906%(X100)
7344 10:51:59.728626
7345 10:51:59.728688 ==DQS 1 ==
7346 10:51:59.732184 Final DQS duty delay cell = 0
7347 10:51:59.735578 [0] MAX Duty = 5093%(X100), DQS PI = 58
7348 10:51:59.739008 [0] MIN Duty = 4844%(X100), DQS PI = 24
7349 10:51:59.741748 [0] AVG Duty = 4968%(X100)
7350 10:51:59.741827
7351 10:51:59.745532 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7352 10:51:59.745611
7353 10:51:59.748653 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7354 10:51:59.751744 [DutyScan_Calibration_Flow] ====Done====
7355 10:51:59.751824
7356 10:51:59.755181 [DutyScan_Calibration_Flow] k_type=3
7357 10:51:59.772665
7358 10:51:59.772747 ==DQM 0 ==
7359 10:51:59.776293 Final DQM duty delay cell = 0
7360 10:51:59.779557 [0] MAX Duty = 5031%(X100), DQS PI = 24
7361 10:51:59.782582 [0] MIN Duty = 4813%(X100), DQS PI = 54
7362 10:51:59.786196 [0] AVG Duty = 4922%(X100)
7363 10:51:59.786284
7364 10:51:59.786354 ==DQM 1 ==
7365 10:51:59.789409 Final DQM duty delay cell = 0
7366 10:51:59.792499 [0] MAX Duty = 5062%(X100), DQS PI = 34
7367 10:51:59.795807 [0] MIN Duty = 4875%(X100), DQS PI = 24
7368 10:51:59.799309 [0] AVG Duty = 4968%(X100)
7369 10:51:59.799379
7370 10:51:59.802373 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7371 10:51:59.802449
7372 10:51:59.805962 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7373 10:51:59.808905 [DutyScan_Calibration_Flow] ====Done====
7374 10:51:59.808982
7375 10:51:59.812318 [DutyScan_Calibration_Flow] k_type=2
7376 10:51:59.829956
7377 10:51:59.830061 ==DQ 0 ==
7378 10:51:59.833036 Final DQ duty delay cell = 0
7379 10:51:59.836431 [0] MAX Duty = 5124%(X100), DQS PI = 24
7380 10:51:59.839912 [0] MIN Duty = 4907%(X100), DQS PI = 62
7381 10:51:59.842812 [0] AVG Duty = 5015%(X100)
7382 10:51:59.842929
7383 10:51:59.842997 ==DQ 1 ==
7384 10:51:59.846380 Final DQ duty delay cell = 0
7385 10:51:59.849513 [0] MAX Duty = 5156%(X100), DQS PI = 36
7386 10:51:59.852699 [0] MIN Duty = 4938%(X100), DQS PI = 24
7387 10:51:59.855809 [0] AVG Duty = 5047%(X100)
7388 10:51:59.855887
7389 10:51:59.859480 CH1 DQ 0 Duty spec in!! Max-Min= 217%
7390 10:51:59.859551
7391 10:51:59.862723 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7392 10:51:59.865873 [DutyScan_Calibration_Flow] ====Done====
7393 10:51:59.869503 nWR fixed to 30
7394 10:51:59.872483 [ModeRegInit_LP4] CH0 RK0
7395 10:51:59.872552 [ModeRegInit_LP4] CH0 RK1
7396 10:51:59.875949 [ModeRegInit_LP4] CH1 RK0
7397 10:51:59.878961 [ModeRegInit_LP4] CH1 RK1
7398 10:51:59.879035 match AC timing 5
7399 10:51:59.885758 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 10:51:59.889484 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 10:51:59.892393 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 10:51:59.899262 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 10:51:59.902311 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 10:51:59.902414 [MiockJmeterHQA]
7405 10:51:59.902504
7406 10:51:59.905860 [DramcMiockJmeter] u1RxGatingPI = 0
7407 10:51:59.909017 0 : 4253, 4027
7408 10:51:59.909091 4 : 4363, 4137
7409 10:51:59.912100 8 : 4253, 4027
7410 10:51:59.912174 12 : 4253, 4027
7411 10:51:59.915695 16 : 4252, 4026
7412 10:51:59.915769 20 : 4363, 4138
7413 10:51:59.915841 24 : 4252, 4027
7414 10:51:59.918470 28 : 4363, 4137
7415 10:51:59.918575 32 : 4253, 4027
7416 10:51:59.921677 36 : 4252, 4027
7417 10:51:59.921752 40 : 4253, 4026
7418 10:51:59.925273 44 : 4255, 4029
7419 10:51:59.925348 48 : 4363, 4137
7420 10:51:59.928687 52 : 4252, 4027
7421 10:51:59.928756 56 : 4363, 4138
7422 10:51:59.928817 60 : 4253, 4027
7423 10:51:59.932080 64 : 4252, 4026
7424 10:51:59.932153 68 : 4250, 4027
7425 10:51:59.935010 72 : 4360, 4138
7426 10:51:59.935084 76 : 4250, 4027
7427 10:51:59.938950 80 : 4360, 4137
7428 10:51:59.939053 84 : 4250, 4027
7429 10:51:59.941714 88 : 4250, 4027
7430 10:51:59.941797 92 : 4252, 4027
7431 10:51:59.941863 96 : 4252, 4029
7432 10:51:59.945375 100 : 4360, 4137
7433 10:51:59.945447 104 : 4250, 3743
7434 10:51:59.948360 108 : 4250, 6
7435 10:51:59.948442 112 : 4360, 0
7436 10:51:59.951474 116 : 4250, 0
7437 10:51:59.951557 120 : 4252, 0
7438 10:51:59.951622 124 : 4250, 0
7439 10:51:59.954866 128 : 4250, 0
7440 10:51:59.954963 132 : 4252, 0
7441 10:51:59.958042 136 : 4360, 0
7442 10:51:59.958124 140 : 4250, 0
7443 10:51:59.958189 144 : 4250, 0
7444 10:51:59.961876 148 : 4361, 0
7445 10:51:59.961958 152 : 4361, 0
7446 10:51:59.965122 156 : 4363, 0
7447 10:51:59.965204 160 : 4250, 0
7448 10:51:59.965269 164 : 4250, 0
7449 10:51:59.968105 168 : 4250, 0
7450 10:51:59.968188 172 : 4252, 0
7451 10:51:59.968253 176 : 4250, 0
7452 10:51:59.971525 180 : 4250, 0
7453 10:51:59.971607 184 : 4252, 0
7454 10:51:59.975038 188 : 4360, 0
7455 10:51:59.975121 192 : 4250, 0
7456 10:51:59.975186 196 : 4249, 0
7457 10:51:59.978301 200 : 4250, 0
7458 10:51:59.978383 204 : 4360, 0
7459 10:51:59.981251 208 : 4361, 0
7460 10:51:59.981334 212 : 4250, 0
7461 10:51:59.981400 216 : 4250, 0
7462 10:51:59.984948 220 : 4250, 0
7463 10:51:59.985030 224 : 4252, 0
7464 10:51:59.988169 228 : 4250, 0
7465 10:51:59.988251 232 : 4250, 2
7466 10:51:59.988316 236 : 4253, 1234
7467 10:51:59.991060 240 : 4250, 4027
7468 10:51:59.991142 244 : 4363, 4140
7469 10:51:59.994658 248 : 4360, 4138
7470 10:51:59.994740 252 : 4250, 4027
7471 10:51:59.997792 256 : 4363, 4140
7472 10:51:59.997874 260 : 4360, 4137
7473 10:52:00.000840 264 : 4250, 4027
7474 10:52:00.000922 268 : 4250, 4027
7475 10:52:00.004554 272 : 4253, 4030
7476 10:52:00.004632 276 : 4250, 4027
7477 10:52:00.007524 280 : 4250, 4027
7478 10:52:00.007607 284 : 4250, 4027
7479 10:52:00.010688 288 : 4252, 4030
7480 10:52:00.010770 292 : 4250, 4027
7481 10:52:00.014432 296 : 4361, 4137
7482 10:52:00.014514 300 : 4360, 4138
7483 10:52:00.014578 304 : 4249, 4027
7484 10:52:00.017471 308 : 4363, 4139
7485 10:52:00.017553 312 : 4360, 4137
7486 10:52:00.020637 316 : 4250, 4027
7487 10:52:00.020720 320 : 4250, 4027
7488 10:52:00.024254 324 : 4252, 4030
7489 10:52:00.024343 328 : 4250, 4027
7490 10:52:00.027128 332 : 4250, 4027
7491 10:52:00.027210 336 : 4250, 4027
7492 10:52:00.030621 340 : 4252, 4029
7493 10:52:00.030704 344 : 4250, 4027
7494 10:52:00.034096 348 : 4360, 4137
7495 10:52:00.034178 352 : 4360, 4126
7496 10:52:00.036946 356 : 4250, 2973
7497 10:52:00.037028 360 : 4363, 0
7498 10:52:00.037094
7499 10:52:00.040286 MIOCK jitter meter ch=0
7500 10:52:00.040419
7501 10:52:00.043537 1T = (360-108) = 252 dly cells
7502 10:52:00.047210 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7503 10:52:00.047292 ==
7504 10:52:00.050410 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 10:52:00.056802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 10:52:00.056884 ==
7507 10:52:00.060141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 10:52:00.066866 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 10:52:00.070072 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 10:52:00.076690 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 10:52:00.084681 [CA 0] Center 44 (14~75) winsize 62
7512 10:52:00.088348 [CA 1] Center 43 (13~74) winsize 62
7513 10:52:00.091502 [CA 2] Center 40 (11~69) winsize 59
7514 10:52:00.094536 [CA 3] Center 39 (10~68) winsize 59
7515 10:52:00.098120 [CA 4] Center 37 (8~67) winsize 60
7516 10:52:00.101294 [CA 5] Center 37 (7~67) winsize 61
7517 10:52:00.101402
7518 10:52:00.104462 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 10:52:00.107593
7520 10:52:00.110670 [CATrainingPosCal] consider 1 rank data
7521 10:52:00.110745 u2DelayCellTimex100 = 258/100 ps
7522 10:52:00.117359 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7523 10:52:00.121094 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7524 10:52:00.124326 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7525 10:52:00.127263 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 10:52:00.130933 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7527 10:52:00.133905 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 10:52:00.133978
7529 10:52:00.137298 CA PerBit enable=1, Macro0, CA PI delay=37
7530 10:52:00.137395
7531 10:52:00.140980 [CBTSetCACLKResult] CA Dly = 37
7532 10:52:00.143926 CS Dly: 11 (0~42)
7533 10:52:00.147509 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 10:52:00.150378 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 10:52:00.150520 ==
7536 10:52:00.153951 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 10:52:00.160567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 10:52:00.160702 ==
7539 10:52:00.163680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 10:52:00.170203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 10:52:00.173366 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 10:52:00.180375 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 10:52:00.188759 [CA 0] Center 44 (14~74) winsize 61
7544 10:52:00.191577 [CA 1] Center 43 (13~74) winsize 62
7545 10:52:00.194976 [CA 2] Center 39 (10~68) winsize 59
7546 10:52:00.198403 [CA 3] Center 39 (10~68) winsize 59
7547 10:52:00.202063 [CA 4] Center 36 (7~66) winsize 60
7548 10:52:00.204832 [CA 5] Center 36 (7~66) winsize 60
7549 10:52:00.204925
7550 10:52:00.208662 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 10:52:00.208747
7552 10:52:00.215018 [CATrainingPosCal] consider 2 rank data
7553 10:52:00.215103 u2DelayCellTimex100 = 258/100 ps
7554 10:52:00.221388 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7555 10:52:00.225099 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7556 10:52:00.228288 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7557 10:52:00.231443 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7558 10:52:00.234938 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7559 10:52:00.237965 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7560 10:52:00.238048
7561 10:52:00.241258 CA PerBit enable=1, Macro0, CA PI delay=36
7562 10:52:00.244297
7563 10:52:00.244393 [CBTSetCACLKResult] CA Dly = 36
7564 10:52:00.247740 CS Dly: 11 (0~43)
7565 10:52:00.251231 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 10:52:00.254105 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 10:52:00.257907
7568 10:52:00.261213 ----->DramcWriteLeveling(PI) begin...
7569 10:52:00.261300 ==
7570 10:52:00.264298 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 10:52:00.267656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 10:52:00.267740 ==
7573 10:52:00.271083 Write leveling (Byte 0): 36 => 36
7574 10:52:00.273913 Write leveling (Byte 1): 28 => 28
7575 10:52:00.277568 DramcWriteLeveling(PI) end<-----
7576 10:52:00.277652
7577 10:52:00.277717 ==
7578 10:52:00.280683 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 10:52:00.283939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 10:52:00.284022 ==
7581 10:52:00.287002 [Gating] SW mode calibration
7582 10:52:00.293473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 10:52:00.300317 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 10:52:00.303951 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 10:52:00.307252 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 10:52:00.313618 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 10:52:00.316803 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 10:52:00.319959 1 4 16 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7589 10:52:00.326690 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7590 10:52:00.329804 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 10:52:00.333508 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 10:52:00.340166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 10:52:00.343210 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 10:52:00.346795 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 10:52:00.353165 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7596 10:52:00.356381 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7597 10:52:00.359745 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7598 10:52:00.366579 1 5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7599 10:52:00.369576 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:52:00.372904 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 10:52:00.379677 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 10:52:00.382660 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 10:52:00.385843 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7604 10:52:00.392790 1 6 16 | B1->B0 | 2323 4343 | 0 1 | (0 0) (0 0)
7605 10:52:00.395766 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7606 10:52:00.399355 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
7607 10:52:00.405552 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 10:52:00.409097 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 10:52:00.412167 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 10:52:00.418955 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 10:52:00.422027 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 10:52:00.425579 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 10:52:00.431894 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 10:52:00.435586 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 10:52:00.438651 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 10:52:00.445335 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 10:52:00.448472 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 10:52:00.451651 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 10:52:00.458189 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 10:52:00.461783 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 10:52:00.464837 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:52:00.471454 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:52:00.474941 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:52:00.478020 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:52:00.485097 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:52:00.488304 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 10:52:00.491415 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:52:00.498198 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 10:52:00.501182 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 10:52:00.504271 Total UI for P1: 0, mck2ui 16
7631 10:52:00.508008 best dqsien dly found for B0: ( 1, 9, 16)
7632 10:52:00.511097 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 10:52:00.517861 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 10:52:00.520972 Total UI for P1: 0, mck2ui 16
7635 10:52:00.524429 best dqsien dly found for B1: ( 1, 9, 22)
7636 10:52:00.527347 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7637 10:52:00.530721 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7638 10:52:00.530821
7639 10:52:00.534351 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7640 10:52:00.537481 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7641 10:52:00.540750 [Gating] SW calibration Done
7642 10:52:00.540832 ==
7643 10:52:00.544194 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 10:52:00.547105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 10:52:00.550254 ==
7646 10:52:00.550367 RX Vref Scan: 0
7647 10:52:00.550462
7648 10:52:00.553494 RX Vref 0 -> 0, step: 1
7649 10:52:00.553590
7650 10:52:00.553678 RX Delay 0 -> 252, step: 8
7651 10:52:00.560354 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7652 10:52:00.563998 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7653 10:52:00.567102 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7654 10:52:00.569962 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7655 10:52:00.576444 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7656 10:52:00.579863 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7657 10:52:00.583225 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7658 10:52:00.586964 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7659 10:52:00.589724 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7660 10:52:00.596522 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7661 10:52:00.600150 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7662 10:52:00.603232 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7663 10:52:00.606244 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7664 10:52:00.610078 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7665 10:52:00.616617 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7666 10:52:00.619947 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7667 10:52:00.620066 ==
7668 10:52:00.622986 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 10:52:00.626675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 10:52:00.626794 ==
7671 10:52:00.629669 DQS Delay:
7672 10:52:00.629786 DQS0 = 0, DQS1 = 0
7673 10:52:00.629899 DQM Delay:
7674 10:52:00.632682 DQM0 = 127, DQM1 = 123
7675 10:52:00.632794 DQ Delay:
7676 10:52:00.636381 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7677 10:52:00.639549 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =135
7678 10:52:00.646325 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7679 10:52:00.649315 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7680 10:52:00.649439
7681 10:52:00.649546
7682 10:52:00.649694 ==
7683 10:52:00.652419 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 10:52:00.656141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 10:52:00.656249 ==
7686 10:52:00.656341
7687 10:52:00.656439
7688 10:52:00.659222 TX Vref Scan disable
7689 10:52:00.662334 == TX Byte 0 ==
7690 10:52:00.665896 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7691 10:52:00.669320 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7692 10:52:00.672496 == TX Byte 1 ==
7693 10:52:00.675556 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7694 10:52:00.679330 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7695 10:52:00.679446 ==
7696 10:52:00.682277 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 10:52:00.685866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 10:52:00.688836 ==
7699 10:52:00.700944
7700 10:52:00.704162 TX Vref early break, caculate TX vref
7701 10:52:00.707790 TX Vref=16, minBit 8, minWin=21, winSum=359
7702 10:52:00.710668 TX Vref=18, minBit 11, minWin=21, winSum=374
7703 10:52:00.714510 TX Vref=20, minBit 8, minWin=22, winSum=382
7704 10:52:00.717643 TX Vref=22, minBit 8, minWin=23, winSum=392
7705 10:52:00.720572 TX Vref=24, minBit 8, minWin=24, winSum=402
7706 10:52:00.727704 TX Vref=26, minBit 8, minWin=24, winSum=409
7707 10:52:00.730529 TX Vref=28, minBit 8, minWin=24, winSum=412
7708 10:52:00.734101 TX Vref=30, minBit 4, minWin=24, winSum=403
7709 10:52:00.737262 TX Vref=32, minBit 8, minWin=22, winSum=391
7710 10:52:00.740299 TX Vref=34, minBit 9, minWin=22, winSum=384
7711 10:52:00.747199 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28
7712 10:52:00.747324
7713 10:52:00.750247 Final TX Range 0 Vref 28
7714 10:52:00.750361
7715 10:52:00.750460 ==
7716 10:52:00.753862 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 10:52:00.756852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 10:52:00.756967 ==
7719 10:52:00.757063
7720 10:52:00.757160
7721 10:52:00.760078 TX Vref Scan disable
7722 10:52:00.766893 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7723 10:52:00.766976 == TX Byte 0 ==
7724 10:52:00.769924 u2DelayCellOfst[0]=11 cells (3 PI)
7725 10:52:00.773696 u2DelayCellOfst[1]=18 cells (5 PI)
7726 10:52:00.776519 u2DelayCellOfst[2]=11 cells (3 PI)
7727 10:52:00.780214 u2DelayCellOfst[3]=11 cells (3 PI)
7728 10:52:00.783349 u2DelayCellOfst[4]=7 cells (2 PI)
7729 10:52:00.786443 u2DelayCellOfst[5]=0 cells (0 PI)
7730 10:52:00.789894 u2DelayCellOfst[6]=18 cells (5 PI)
7731 10:52:00.793429 u2DelayCellOfst[7]=18 cells (5 PI)
7732 10:52:00.796241 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7733 10:52:00.799746 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7734 10:52:00.803160 == TX Byte 1 ==
7735 10:52:00.806519 u2DelayCellOfst[8]=0 cells (0 PI)
7736 10:52:00.809746 u2DelayCellOfst[9]=3 cells (1 PI)
7737 10:52:00.813042 u2DelayCellOfst[10]=7 cells (2 PI)
7738 10:52:00.816004 u2DelayCellOfst[11]=7 cells (2 PI)
7739 10:52:00.819476 u2DelayCellOfst[12]=15 cells (4 PI)
7740 10:52:00.822525 u2DelayCellOfst[13]=11 cells (3 PI)
7741 10:52:00.822607 u2DelayCellOfst[14]=15 cells (4 PI)
7742 10:52:00.826175 u2DelayCellOfst[15]=11 cells (3 PI)
7743 10:52:00.832513 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7744 10:52:00.835934 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7745 10:52:00.839044 DramC Write-DBI on
7746 10:52:00.839125 ==
7747 10:52:00.842803 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 10:52:00.845930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 10:52:00.846011 ==
7750 10:52:00.846076
7751 10:52:00.846134
7752 10:52:00.848934 TX Vref Scan disable
7753 10:52:00.849033 == TX Byte 0 ==
7754 10:52:00.855861 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7755 10:52:00.855965 == TX Byte 1 ==
7756 10:52:00.858788 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7757 10:52:00.862414 DramC Write-DBI off
7758 10:52:00.862495
7759 10:52:00.862565 [DATLAT]
7760 10:52:00.865609 Freq=1600, CH0 RK0
7761 10:52:00.865690
7762 10:52:00.865754 DATLAT Default: 0xf
7763 10:52:00.869274 0, 0xFFFF, sum = 0
7764 10:52:00.869356 1, 0xFFFF, sum = 0
7765 10:52:00.872682 2, 0xFFFF, sum = 0
7766 10:52:00.875448 3, 0xFFFF, sum = 0
7767 10:52:00.875531 4, 0xFFFF, sum = 0
7768 10:52:00.879062 5, 0xFFFF, sum = 0
7769 10:52:00.879145 6, 0xFFFF, sum = 0
7770 10:52:00.882092 7, 0xFFFF, sum = 0
7771 10:52:00.882174 8, 0xFFFF, sum = 0
7772 10:52:00.885789 9, 0xFFFF, sum = 0
7773 10:52:00.885873 10, 0xFFFF, sum = 0
7774 10:52:00.888930 11, 0xFFFF, sum = 0
7775 10:52:00.889015 12, 0xFFFF, sum = 0
7776 10:52:00.891959 13, 0xEFFF, sum = 0
7777 10:52:00.892058 14, 0x0, sum = 1
7778 10:52:00.895526 15, 0x0, sum = 2
7779 10:52:00.895610 16, 0x0, sum = 3
7780 10:52:00.898615 17, 0x0, sum = 4
7781 10:52:00.898740 best_step = 15
7782 10:52:00.898840
7783 10:52:00.898935 ==
7784 10:52:00.902222 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 10:52:00.908434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 10:52:00.908516 ==
7787 10:52:00.908597 RX Vref Scan: 1
7788 10:52:00.908726
7789 10:52:00.911825 Set Vref Range= 24 -> 127
7790 10:52:00.911906
7791 10:52:00.914973 RX Vref 24 -> 127, step: 1
7792 10:52:00.915071
7793 10:52:00.915165 RX Delay 11 -> 252, step: 4
7794 10:52:00.915240
7795 10:52:00.918592 Set Vref, RX VrefLevel [Byte0]: 24
7796 10:52:00.921473 [Byte1]: 24
7797 10:52:00.925585
7798 10:52:00.925670 Set Vref, RX VrefLevel [Byte0]: 25
7799 10:52:00.929204 [Byte1]: 25
7800 10:52:00.933506
7801 10:52:00.933590 Set Vref, RX VrefLevel [Byte0]: 26
7802 10:52:00.936582 [Byte1]: 26
7803 10:52:00.941328
7804 10:52:00.941411 Set Vref, RX VrefLevel [Byte0]: 27
7805 10:52:00.944412 [Byte1]: 27
7806 10:52:00.948785
7807 10:52:00.948868 Set Vref, RX VrefLevel [Byte0]: 28
7808 10:52:00.951730 [Byte1]: 28
7809 10:52:00.956583
7810 10:52:00.956667 Set Vref, RX VrefLevel [Byte0]: 29
7811 10:52:00.959645 [Byte1]: 29
7812 10:52:00.964104
7813 10:52:00.964189 Set Vref, RX VrefLevel [Byte0]: 30
7814 10:52:00.967159 [Byte1]: 30
7815 10:52:00.971530
7816 10:52:00.971651 Set Vref, RX VrefLevel [Byte0]: 31
7817 10:52:00.974820 [Byte1]: 31
7818 10:52:00.979398
7819 10:52:00.979480 Set Vref, RX VrefLevel [Byte0]: 32
7820 10:52:00.982432 [Byte1]: 32
7821 10:52:00.986869
7822 10:52:00.986965 Set Vref, RX VrefLevel [Byte0]: 33
7823 10:52:00.990031 [Byte1]: 33
7824 10:52:00.994411
7825 10:52:00.994493 Set Vref, RX VrefLevel [Byte0]: 34
7826 10:52:00.997379 [Byte1]: 34
7827 10:52:01.002040
7828 10:52:01.002123 Set Vref, RX VrefLevel [Byte0]: 35
7829 10:52:01.005181 [Byte1]: 35
7830 10:52:01.009370
7831 10:52:01.009452 Set Vref, RX VrefLevel [Byte0]: 36
7832 10:52:01.012936 [Byte1]: 36
7833 10:52:01.017017
7834 10:52:01.017100 Set Vref, RX VrefLevel [Byte0]: 37
7835 10:52:01.020403 [Byte1]: 37
7836 10:52:01.025093
7837 10:52:01.025176 Set Vref, RX VrefLevel [Byte0]: 38
7838 10:52:01.028001 [Byte1]: 38
7839 10:52:01.032663
7840 10:52:01.032746 Set Vref, RX VrefLevel [Byte0]: 39
7841 10:52:01.035425 [Byte1]: 39
7842 10:52:01.039745
7843 10:52:01.039828 Set Vref, RX VrefLevel [Byte0]: 40
7844 10:52:01.043441 [Byte1]: 40
7845 10:52:01.047658
7846 10:52:01.047741 Set Vref, RX VrefLevel [Byte0]: 41
7847 10:52:01.050805 [Byte1]: 41
7848 10:52:01.055043
7849 10:52:01.055125 Set Vref, RX VrefLevel [Byte0]: 42
7850 10:52:01.058708 [Byte1]: 42
7851 10:52:01.063279
7852 10:52:01.063364 Set Vref, RX VrefLevel [Byte0]: 43
7853 10:52:01.066046 [Byte1]: 43
7854 10:52:01.070612
7855 10:52:01.070693 Set Vref, RX VrefLevel [Byte0]: 44
7856 10:52:01.073964 [Byte1]: 44
7857 10:52:01.077833
7858 10:52:01.077925 Set Vref, RX VrefLevel [Byte0]: 45
7859 10:52:01.081519 [Byte1]: 45
7860 10:52:01.085777
7861 10:52:01.085873 Set Vref, RX VrefLevel [Byte0]: 46
7862 10:52:01.088798 [Byte1]: 46
7863 10:52:01.093174
7864 10:52:01.093257 Set Vref, RX VrefLevel [Byte0]: 47
7865 10:52:01.096370 [Byte1]: 47
7866 10:52:01.100796
7867 10:52:01.100886 Set Vref, RX VrefLevel [Byte0]: 48
7868 10:52:01.104075 [Byte1]: 48
7869 10:52:01.108592
7870 10:52:01.108668 Set Vref, RX VrefLevel [Byte0]: 49
7871 10:52:01.111613 [Byte1]: 49
7872 10:52:01.116163
7873 10:52:01.116237 Set Vref, RX VrefLevel [Byte0]: 50
7874 10:52:01.119322 [Byte1]: 50
7875 10:52:01.123516
7876 10:52:01.123601 Set Vref, RX VrefLevel [Byte0]: 51
7877 10:52:01.127007 [Byte1]: 51
7878 10:52:01.131576
7879 10:52:01.131657 Set Vref, RX VrefLevel [Byte0]: 52
7880 10:52:01.134632 [Byte1]: 52
7881 10:52:01.139068
7882 10:52:01.139149 Set Vref, RX VrefLevel [Byte0]: 53
7883 10:52:01.142255 [Byte1]: 53
7884 10:52:01.146388
7885 10:52:01.146470 Set Vref, RX VrefLevel [Byte0]: 54
7886 10:52:01.149839 [Byte1]: 54
7887 10:52:01.154181
7888 10:52:01.154263 Set Vref, RX VrefLevel [Byte0]: 55
7889 10:52:01.157228 [Byte1]: 55
7890 10:52:01.161878
7891 10:52:01.161952 Set Vref, RX VrefLevel [Byte0]: 56
7892 10:52:01.164974 [Byte1]: 56
7893 10:52:01.169403
7894 10:52:01.169478 Set Vref, RX VrefLevel [Byte0]: 57
7895 10:52:01.173020 [Byte1]: 57
7896 10:52:01.177136
7897 10:52:01.177230 Set Vref, RX VrefLevel [Byte0]: 58
7898 10:52:01.180455 [Byte1]: 58
7899 10:52:01.184513
7900 10:52:01.184589 Set Vref, RX VrefLevel [Byte0]: 59
7901 10:52:01.187959 [Byte1]: 59
7902 10:52:01.192131
7903 10:52:01.192213 Set Vref, RX VrefLevel [Byte0]: 60
7904 10:52:01.195798 [Byte1]: 60
7905 10:52:01.200112
7906 10:52:01.200184 Set Vref, RX VrefLevel [Byte0]: 61
7907 10:52:01.203063 [Byte1]: 61
7908 10:52:01.207263
7909 10:52:01.207346 Set Vref, RX VrefLevel [Byte0]: 62
7910 10:52:01.211019 [Byte1]: 62
7911 10:52:01.215552
7912 10:52:01.215634 Set Vref, RX VrefLevel [Byte0]: 63
7913 10:52:01.218328 [Byte1]: 63
7914 10:52:01.222608
7915 10:52:01.222717 Set Vref, RX VrefLevel [Byte0]: 64
7916 10:52:01.226256 [Byte1]: 64
7917 10:52:01.230201
7918 10:52:01.230317 Set Vref, RX VrefLevel [Byte0]: 65
7919 10:52:01.233636 [Byte1]: 65
7920 10:52:01.238237
7921 10:52:01.238349 Set Vref, RX VrefLevel [Byte0]: 66
7922 10:52:01.241277 [Byte1]: 66
7923 10:52:01.245419
7924 10:52:01.245518 Set Vref, RX VrefLevel [Byte0]: 67
7925 10:52:01.248925 [Byte1]: 67
7926 10:52:01.253295
7927 10:52:01.253405 Set Vref, RX VrefLevel [Byte0]: 68
7928 10:52:01.256572 [Byte1]: 68
7929 10:52:01.260997
7930 10:52:01.261108 Set Vref, RX VrefLevel [Byte0]: 69
7931 10:52:01.263936 [Byte1]: 69
7932 10:52:01.268306
7933 10:52:01.268414 Set Vref, RX VrefLevel [Byte0]: 70
7934 10:52:01.271436 [Byte1]: 70
7935 10:52:01.275804
7936 10:52:01.275884 Set Vref, RX VrefLevel [Byte0]: 71
7937 10:52:01.279476 [Byte1]: 71
7938 10:52:01.283519
7939 10:52:01.283597 Set Vref, RX VrefLevel [Byte0]: 72
7940 10:52:01.287182 [Byte1]: 72
7941 10:52:01.291246
7942 10:52:01.291348 Set Vref, RX VrefLevel [Byte0]: 73
7943 10:52:01.294875 [Byte1]: 73
7944 10:52:01.299130
7945 10:52:01.299206 Final RX Vref Byte 0 = 59 to rank0
7946 10:52:01.302206 Final RX Vref Byte 1 = 61 to rank0
7947 10:52:01.305298 Final RX Vref Byte 0 = 59 to rank1
7948 10:52:01.308409 Final RX Vref Byte 1 = 61 to rank1==
7949 10:52:01.312091 Dram Type= 6, Freq= 0, CH_0, rank 0
7950 10:52:01.318867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 10:52:01.318971 ==
7952 10:52:01.319064 DQS Delay:
7953 10:52:01.321989 DQS0 = 0, DQS1 = 0
7954 10:52:01.322073 DQM Delay:
7955 10:52:01.322138 DQM0 = 125, DQM1 = 119
7956 10:52:01.325132 DQ Delay:
7957 10:52:01.328841 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7958 10:52:01.331719 DQ4 =124, DQ5 =112, DQ6 =132, DQ7 =138
7959 10:52:01.335239 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7960 10:52:01.338657 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7961 10:52:01.338764
7962 10:52:01.338909
7963 10:52:01.339016
7964 10:52:01.341662 [DramC_TX_OE_Calibration] TA2
7965 10:52:01.345255 Original DQ_B0 (3 6) =30, OEN = 27
7966 10:52:01.348455 Original DQ_B1 (3 6) =30, OEN = 27
7967 10:52:01.352335 24, 0x0, End_B0=24 End_B1=24
7968 10:52:01.352447 25, 0x0, End_B0=25 End_B1=25
7969 10:52:01.355212 26, 0x0, End_B0=26 End_B1=26
7970 10:52:01.358165 27, 0x0, End_B0=27 End_B1=27
7971 10:52:01.361690 28, 0x0, End_B0=28 End_B1=28
7972 10:52:01.364876 29, 0x0, End_B0=29 End_B1=29
7973 10:52:01.364982 30, 0x0, End_B0=30 End_B1=30
7974 10:52:01.367935 31, 0x4545, End_B0=30 End_B1=30
7975 10:52:01.371619 Byte0 end_step=30 best_step=27
7976 10:52:01.374647 Byte1 end_step=30 best_step=27
7977 10:52:01.377814 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 10:52:01.381483 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 10:52:01.381586
7980 10:52:01.381678
7981 10:52:01.387948 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
7982 10:52:01.390849 CH0 RK0: MR19=303, MR18=F0F
7983 10:52:01.397871 CH0_RK0: MR19=0x303, MR18=0xF0F, DQSOSC=402, MR23=63, INC=22, DEC=15
7984 10:52:01.397980
7985 10:52:01.400929 ----->DramcWriteLeveling(PI) begin...
7986 10:52:01.401045 ==
7987 10:52:01.404319 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 10:52:01.407406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 10:52:01.407488 ==
7990 10:52:01.411178 Write leveling (Byte 0): 34 => 34
7991 10:52:01.414305 Write leveling (Byte 1): 28 => 28
7992 10:52:01.417195 DramcWriteLeveling(PI) end<-----
7993 10:52:01.417302
7994 10:52:01.417395 ==
7995 10:52:01.421223 Dram Type= 6, Freq= 0, CH_0, rank 1
7996 10:52:01.424131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 10:52:01.427254 ==
7998 10:52:01.427334 [Gating] SW mode calibration
7999 10:52:01.437116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8000 10:52:01.440461 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8001 10:52:01.443814 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 10:52:01.450113 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 10:52:01.453873 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 10:52:01.456810 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8005 10:52:01.463529 1 4 16 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8006 10:52:01.467096 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 10:52:01.470135 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 10:52:01.476633 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 10:52:01.480369 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 10:52:01.483428 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 10:52:01.490335 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 10:52:01.493063 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
8013 10:52:01.496662 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8014 10:52:01.502921 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8015 10:52:01.506242 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 10:52:01.509569 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 10:52:01.516322 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 10:52:01.519329 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 10:52:01.522992 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8020 10:52:01.529170 1 6 12 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
8021 10:52:01.532865 1 6 16 | B1->B0 | 302f 4646 | 1 0 | (0 0) (0 0)
8022 10:52:01.535928 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 10:52:01.542762 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 10:52:01.545659 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 10:52:01.549067 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 10:52:01.555807 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 10:52:01.558689 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 10:52:01.562240 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 10:52:01.569022 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8030 10:52:01.572014 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8031 10:52:01.575606 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 10:52:01.582088 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 10:52:01.585426 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 10:52:01.588455 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 10:52:01.595279 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 10:52:01.598693 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 10:52:01.601808 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 10:52:01.608663 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 10:52:01.611489 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 10:52:01.614794 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 10:52:01.621372 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 10:52:01.624972 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 10:52:01.628010 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 10:52:01.634849 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 10:52:01.638100 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8046 10:52:01.641126 Total UI for P1: 0, mck2ui 16
8047 10:52:01.644845 best dqsien dly found for B0: ( 1, 9, 10)
8048 10:52:01.648115 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 10:52:01.654448 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 10:52:01.657970 Total UI for P1: 0, mck2ui 16
8051 10:52:01.660927 best dqsien dly found for B1: ( 1, 9, 18)
8052 10:52:01.664414 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8053 10:52:01.667880 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8054 10:52:01.667963
8055 10:52:01.670746 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8056 10:52:01.674563 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8057 10:52:01.677977 [Gating] SW calibration Done
8058 10:52:01.678058 ==
8059 10:52:01.680817 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 10:52:01.683907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 10:52:01.683990 ==
8062 10:52:01.687691 RX Vref Scan: 0
8063 10:52:01.687773
8064 10:52:01.690415 RX Vref 0 -> 0, step: 1
8065 10:52:01.690523
8066 10:52:01.690624 RX Delay 0 -> 252, step: 8
8067 10:52:01.697322 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8068 10:52:01.700400 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8069 10:52:01.703981 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8070 10:52:01.707083 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8071 10:52:01.713289 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8072 10:52:01.716919 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8073 10:52:01.719888 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8074 10:52:01.723571 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8075 10:52:01.726994 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8076 10:52:01.733534 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8077 10:52:01.736769 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8078 10:52:01.740253 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8079 10:52:01.743154 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8080 10:52:01.746422 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8081 10:52:01.752829 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8082 10:52:01.756083 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8083 10:52:01.756214 ==
8084 10:52:01.759890 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 10:52:01.762897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 10:52:01.763007 ==
8087 10:52:01.765821 DQS Delay:
8088 10:52:01.765906 DQS0 = 0, DQS1 = 0
8089 10:52:01.769320 DQM Delay:
8090 10:52:01.769433 DQM0 = 129, DQM1 = 122
8091 10:52:01.772333 DQ Delay:
8092 10:52:01.775786 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8093 10:52:01.779305 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8094 10:52:01.782563 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8095 10:52:01.785739 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8096 10:52:01.785849
8097 10:52:01.785944
8098 10:52:01.786034 ==
8099 10:52:01.788953 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 10:52:01.792674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 10:52:01.792772 ==
8102 10:52:01.792840
8103 10:52:01.796018
8104 10:52:01.796102 TX Vref Scan disable
8105 10:52:01.799127 == TX Byte 0 ==
8106 10:52:01.802515 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8107 10:52:01.805444 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8108 10:52:01.808542 == TX Byte 1 ==
8109 10:52:01.811863 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8110 10:52:01.815934 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8111 10:52:01.816020 ==
8112 10:52:01.818783 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 10:52:01.824989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 10:52:01.825115 ==
8115 10:52:01.837362
8116 10:52:01.840779 TX Vref early break, caculate TX vref
8117 10:52:01.843907 TX Vref=16, minBit 8, minWin=21, winSum=363
8118 10:52:01.847196 TX Vref=18, minBit 0, minWin=22, winSum=372
8119 10:52:01.850392 TX Vref=20, minBit 1, minWin=23, winSum=381
8120 10:52:01.854332 TX Vref=22, minBit 0, minWin=24, winSum=397
8121 10:52:01.857483 TX Vref=24, minBit 0, minWin=24, winSum=401
8122 10:52:01.863899 TX Vref=26, minBit 0, minWin=24, winSum=403
8123 10:52:01.867005 TX Vref=28, minBit 8, minWin=24, winSum=411
8124 10:52:01.870718 TX Vref=30, minBit 8, minWin=24, winSum=408
8125 10:52:01.873549 TX Vref=32, minBit 11, minWin=23, winSum=397
8126 10:52:01.876868 TX Vref=34, minBit 8, minWin=22, winSum=386
8127 10:52:01.883331 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 28
8128 10:52:01.883458
8129 10:52:01.887128 Final TX Range 0 Vref 28
8130 10:52:01.887245
8131 10:52:01.887344 ==
8132 10:52:01.890169 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 10:52:01.893705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 10:52:01.893817 ==
8135 10:52:01.893913
8136 10:52:01.894004
8137 10:52:01.896759 TX Vref Scan disable
8138 10:52:01.903134 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8139 10:52:01.903219 == TX Byte 0 ==
8140 10:52:01.907098 u2DelayCellOfst[0]=11 cells (3 PI)
8141 10:52:01.909824 u2DelayCellOfst[1]=18 cells (5 PI)
8142 10:52:01.913357 u2DelayCellOfst[2]=11 cells (3 PI)
8143 10:52:01.916565 u2DelayCellOfst[3]=11 cells (3 PI)
8144 10:52:01.920297 u2DelayCellOfst[4]=7 cells (2 PI)
8145 10:52:01.923495 u2DelayCellOfst[5]=0 cells (0 PI)
8146 10:52:01.926680 u2DelayCellOfst[6]=18 cells (5 PI)
8147 10:52:01.929893 u2DelayCellOfst[7]=18 cells (5 PI)
8148 10:52:01.933868 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8149 10:52:01.936768 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8150 10:52:01.939794 == TX Byte 1 ==
8151 10:52:01.943088 u2DelayCellOfst[8]=0 cells (0 PI)
8152 10:52:01.946154 u2DelayCellOfst[9]=0 cells (0 PI)
8153 10:52:01.950007 u2DelayCellOfst[10]=7 cells (2 PI)
8154 10:52:01.950134 u2DelayCellOfst[11]=7 cells (2 PI)
8155 10:52:01.953281 u2DelayCellOfst[12]=15 cells (4 PI)
8156 10:52:01.956414 u2DelayCellOfst[13]=11 cells (3 PI)
8157 10:52:01.959510 u2DelayCellOfst[14]=15 cells (4 PI)
8158 10:52:01.963293 u2DelayCellOfst[15]=15 cells (4 PI)
8159 10:52:01.969650 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8160 10:52:01.972861 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8161 10:52:01.972976 DramC Write-DBI on
8162 10:52:01.975870 ==
8163 10:52:01.975986 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 10:52:01.982771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 10:52:01.982907 ==
8166 10:52:01.983005
8167 10:52:01.983096
8168 10:52:01.986125 TX Vref Scan disable
8169 10:52:01.986246 == TX Byte 0 ==
8170 10:52:01.992804 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8171 10:52:01.992927 == TX Byte 1 ==
8172 10:52:01.995674 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8173 10:52:01.999080 DramC Write-DBI off
8174 10:52:01.999170
8175 10:52:01.999256 [DATLAT]
8176 10:52:02.002541 Freq=1600, CH0 RK1
8177 10:52:02.002654
8178 10:52:02.002754 DATLAT Default: 0xf
8179 10:52:02.005498 0, 0xFFFF, sum = 0
8180 10:52:02.005611 1, 0xFFFF, sum = 0
8181 10:52:02.009204 2, 0xFFFF, sum = 0
8182 10:52:02.009311 3, 0xFFFF, sum = 0
8183 10:52:02.012630 4, 0xFFFF, sum = 0
8184 10:52:02.015242 5, 0xFFFF, sum = 0
8185 10:52:02.015357 6, 0xFFFF, sum = 0
8186 10:52:02.018901 7, 0xFFFF, sum = 0
8187 10:52:02.018982 8, 0xFFFF, sum = 0
8188 10:52:02.021831 9, 0xFFFF, sum = 0
8189 10:52:02.021919 10, 0xFFFF, sum = 0
8190 10:52:02.025681 11, 0xFFFF, sum = 0
8191 10:52:02.025766 12, 0xFFFF, sum = 0
8192 10:52:02.028874 13, 0xCFFF, sum = 0
8193 10:52:02.028984 14, 0x0, sum = 1
8194 10:52:02.032007 15, 0x0, sum = 2
8195 10:52:02.032120 16, 0x0, sum = 3
8196 10:52:02.035410 17, 0x0, sum = 4
8197 10:52:02.035495 best_step = 15
8198 10:52:02.035561
8199 10:52:02.035622 ==
8200 10:52:02.038416 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 10:52:02.042017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 10:52:02.044947 ==
8203 10:52:02.045027 RX Vref Scan: 0
8204 10:52:02.045094
8205 10:52:02.048433 RX Vref 0 -> 0, step: 1
8206 10:52:02.048515
8207 10:52:02.051509 RX Delay 3 -> 252, step: 4
8208 10:52:02.054789 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8209 10:52:02.058011 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8210 10:52:02.061262 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8211 10:52:02.068339 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8212 10:52:02.071538 iDelay=191, Bit 4, Center 122 (67 ~ 178) 112
8213 10:52:02.074736 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8214 10:52:02.077974 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8215 10:52:02.081142 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8216 10:52:02.088163 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8217 10:52:02.091214 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8218 10:52:02.094217 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8219 10:52:02.097526 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8220 10:52:02.104062 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8221 10:52:02.107750 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8222 10:52:02.111249 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8223 10:52:02.114089 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8224 10:52:02.114214 ==
8225 10:52:02.117748 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 10:52:02.123756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 10:52:02.123877 ==
8228 10:52:02.123948 DQS Delay:
8229 10:52:02.127443 DQS0 = 0, DQS1 = 0
8230 10:52:02.127531 DQM Delay:
8231 10:52:02.127598 DQM0 = 124, DQM1 = 118
8232 10:52:02.130489 DQ Delay:
8233 10:52:02.134550 DQ0 =122, DQ1 =126, DQ2 =122, DQ3 =122
8234 10:52:02.137398 DQ4 =122, DQ5 =112, DQ6 =136, DQ7 =136
8235 10:52:02.140872 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8236 10:52:02.143772 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8237 10:52:02.143864
8238 10:52:02.143932
8239 10:52:02.143993
8240 10:52:02.146822 [DramC_TX_OE_Calibration] TA2
8241 10:52:02.150507 Original DQ_B0 (3 6) =30, OEN = 27
8242 10:52:02.153519 Original DQ_B1 (3 6) =30, OEN = 27
8243 10:52:02.156954 24, 0x0, End_B0=24 End_B1=24
8244 10:52:02.160012 25, 0x0, End_B0=25 End_B1=25
8245 10:52:02.160123 26, 0x0, End_B0=26 End_B1=26
8246 10:52:02.163259 27, 0x0, End_B0=27 End_B1=27
8247 10:52:02.166547 28, 0x0, End_B0=28 End_B1=28
8248 10:52:02.170296 29, 0x0, End_B0=29 End_B1=29
8249 10:52:02.170374 30, 0x0, End_B0=30 End_B1=30
8250 10:52:02.173367 31, 0x4545, End_B0=30 End_B1=30
8251 10:52:02.176539 Byte0 end_step=30 best_step=27
8252 10:52:02.179757 Byte1 end_step=30 best_step=27
8253 10:52:02.183452 Byte0 TX OE(2T, 0.5T) = (3, 3)
8254 10:52:02.186536 Byte1 TX OE(2T, 0.5T) = (3, 3)
8255 10:52:02.186620
8256 10:52:02.186685
8257 10:52:02.193397 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8258 10:52:02.196500 CH0 RK1: MR19=303, MR18=2512
8259 10:52:02.203268 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8260 10:52:02.206650 [RxdqsGatingPostProcess] freq 1600
8261 10:52:02.212855 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8262 10:52:02.212945 best DQS0 dly(2T, 0.5T) = (1, 1)
8263 10:52:02.216403 best DQS1 dly(2T, 0.5T) = (1, 1)
8264 10:52:02.219260 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8265 10:52:02.222754 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8266 10:52:02.225908 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 10:52:02.229066 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 10:52:02.232760 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 10:52:02.236238 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 10:52:02.239131 Pre-setting of DQS Precalculation
8271 10:52:02.242984 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8272 10:52:02.245824 ==
8273 10:52:02.245940 Dram Type= 6, Freq= 0, CH_1, rank 0
8274 10:52:02.252144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 10:52:02.252255 ==
8276 10:52:02.255985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 10:52:02.262006 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 10:52:02.265515 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 10:52:02.272026 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 10:52:02.280454 [CA 0] Center 41 (12~70) winsize 59
8281 10:52:02.283702 [CA 1] Center 42 (12~72) winsize 61
8282 10:52:02.286700 [CA 2] Center 37 (8~66) winsize 59
8283 10:52:02.290445 [CA 3] Center 37 (8~66) winsize 59
8284 10:52:02.293641 [CA 4] Center 37 (8~67) winsize 60
8285 10:52:02.296714 [CA 5] Center 36 (7~66) winsize 60
8286 10:52:02.296817
8287 10:52:02.299889 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8288 10:52:02.299998
8289 10:52:02.303180 [CATrainingPosCal] consider 1 rank data
8290 10:52:02.306328 u2DelayCellTimex100 = 258/100 ps
8291 10:52:02.312981 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8292 10:52:02.316716 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8293 10:52:02.320116 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8294 10:52:02.323077 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8295 10:52:02.326318 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8296 10:52:02.329868 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8297 10:52:02.329948
8298 10:52:02.332786 CA PerBit enable=1, Macro0, CA PI delay=36
8299 10:52:02.332886
8300 10:52:02.336415 [CBTSetCACLKResult] CA Dly = 36
8301 10:52:02.339856 CS Dly: 10 (0~41)
8302 10:52:02.343116 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 10:52:02.346535 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 10:52:02.346638 ==
8305 10:52:02.349353 Dram Type= 6, Freq= 0, CH_1, rank 1
8306 10:52:02.356237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 10:52:02.356354 ==
8308 10:52:02.359408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 10:52:02.365868 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 10:52:02.369438 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 10:52:02.376024 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 10:52:02.383644 [CA 0] Center 42 (13~72) winsize 60
8313 10:52:02.386890 [CA 1] Center 42 (12~72) winsize 61
8314 10:52:02.390053 [CA 2] Center 38 (9~67) winsize 59
8315 10:52:02.393010 [CA 3] Center 36 (7~66) winsize 60
8316 10:52:02.396276 [CA 4] Center 37 (8~67) winsize 60
8317 10:52:02.399526 [CA 5] Center 36 (7~66) winsize 60
8318 10:52:02.399608
8319 10:52:02.403345 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 10:52:02.403453
8321 10:52:02.409774 [CATrainingPosCal] consider 2 rank data
8322 10:52:02.409858 u2DelayCellTimex100 = 258/100 ps
8323 10:52:02.416053 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8324 10:52:02.419500 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8325 10:52:02.423278 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8326 10:52:02.425945 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8327 10:52:02.429472 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8328 10:52:02.432406 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8329 10:52:02.432483
8330 10:52:02.435917 CA PerBit enable=1, Macro0, CA PI delay=36
8331 10:52:02.435993
8332 10:52:02.439286 [CBTSetCACLKResult] CA Dly = 36
8333 10:52:02.442273 CS Dly: 11 (0~44)
8334 10:52:02.445787 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 10:52:02.449238 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 10:52:02.449347
8337 10:52:02.452374 ----->DramcWriteLeveling(PI) begin...
8338 10:52:02.455320 ==
8339 10:52:02.459251 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 10:52:02.462388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 10:52:02.462498 ==
8342 10:52:02.465657 Write leveling (Byte 0): 25 => 25
8343 10:52:02.468926 Write leveling (Byte 1): 28 => 28
8344 10:52:02.471999 DramcWriteLeveling(PI) end<-----
8345 10:52:02.472082
8346 10:52:02.472146 ==
8347 10:52:02.475075 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 10:52:02.478808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 10:52:02.478900 ==
8350 10:52:02.481896 [Gating] SW mode calibration
8351 10:52:02.488532 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8352 10:52:02.494760 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8353 10:52:02.498504 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 10:52:02.501635 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 10:52:02.508551 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 10:52:02.511591 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 10:52:02.514810 1 4 16 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 0)
8358 10:52:02.521793 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 10:52:02.524951 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 10:52:02.528325 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 10:52:02.534732 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 10:52:02.537803 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 10:52:02.541312 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 10:52:02.548261 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8365 10:52:02.551171 1 5 16 | B1->B0 | 2d2d 2a2a | 0 0 | (1 0) (1 0)
8366 10:52:02.554515 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 10:52:02.560730 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 10:52:02.564309 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8369 10:52:02.567527 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 10:52:02.574014 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 10:52:02.577541 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 10:52:02.580802 1 6 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
8373 10:52:02.587518 1 6 16 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
8374 10:52:02.590747 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 10:52:02.594019 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 10:52:02.600096 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 10:52:02.603661 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 10:52:02.606664 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 10:52:02.613466 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 10:52:02.616717 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 10:52:02.619898 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 10:52:02.626285 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 10:52:02.630117 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 10:52:02.632986 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 10:52:02.639648 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 10:52:02.643320 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 10:52:02.646196 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 10:52:02.652896 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 10:52:02.656053 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 10:52:02.659729 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 10:52:02.666656 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 10:52:02.669446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 10:52:02.672672 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 10:52:02.678935 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 10:52:02.682509 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 10:52:02.685799 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8397 10:52:02.692467 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 10:52:02.695757 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8399 10:52:02.698993 Total UI for P1: 0, mck2ui 16
8400 10:52:02.702241 best dqsien dly found for B0: ( 1, 9, 14)
8401 10:52:02.705296 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 10:52:02.708482 Total UI for P1: 0, mck2ui 16
8403 10:52:02.712239 best dqsien dly found for B1: ( 1, 9, 18)
8404 10:52:02.715321 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8405 10:52:02.721606 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8406 10:52:02.721724
8407 10:52:02.725323 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8408 10:52:02.728610 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8409 10:52:02.731663 [Gating] SW calibration Done
8410 10:52:02.731772 ==
8411 10:52:02.734812 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 10:52:02.738524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 10:52:02.738642 ==
8414 10:52:02.741744 RX Vref Scan: 0
8415 10:52:02.741855
8416 10:52:02.741955 RX Vref 0 -> 0, step: 1
8417 10:52:02.742028
8418 10:52:02.745116 RX Delay 0 -> 252, step: 8
8419 10:52:02.748341 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8420 10:52:02.754717 iDelay=208, Bit 1, Center 123 (64 ~ 183) 120
8421 10:52:02.758273 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8422 10:52:02.761352 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8423 10:52:02.764710 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8424 10:52:02.768112 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8425 10:52:02.774697 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8426 10:52:02.777694 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8427 10:52:02.781390 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8428 10:52:02.784354 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8429 10:52:02.787967 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8430 10:52:02.794912 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8431 10:52:02.797489 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8432 10:52:02.800995 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8433 10:52:02.804118 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8434 10:52:02.810728 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8435 10:52:02.810835 ==
8436 10:52:02.814517 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 10:52:02.817337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 10:52:02.817427 ==
8439 10:52:02.817494 DQS Delay:
8440 10:52:02.820949 DQS0 = 0, DQS1 = 0
8441 10:52:02.821034 DQM Delay:
8442 10:52:02.823991 DQM0 = 131, DQM1 = 125
8443 10:52:02.824076 DQ Delay:
8444 10:52:02.827051 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8445 10:52:02.830667 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8446 10:52:02.833639 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8447 10:52:02.836872 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8448 10:52:02.836978
8449 10:52:02.837072
8450 10:52:02.840594 ==
8451 10:52:02.843914 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 10:52:02.846790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 10:52:02.846903 ==
8454 10:52:02.846984
8455 10:52:02.847051
8456 10:52:02.850499 TX Vref Scan disable
8457 10:52:02.850586 == TX Byte 0 ==
8458 10:52:02.856911 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8459 10:52:02.860462 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8460 10:52:02.860577 == TX Byte 1 ==
8461 10:52:02.866961 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8462 10:52:02.869824 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 10:52:02.869937 ==
8464 10:52:02.873130 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 10:52:02.876933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 10:52:02.877046 ==
8467 10:52:02.890930
8468 10:52:02.894592 TX Vref early break, caculate TX vref
8469 10:52:02.897699 TX Vref=16, minBit 1, minWin=22, winSum=359
8470 10:52:02.901196 TX Vref=18, minBit 11, minWin=21, winSum=372
8471 10:52:02.904206 TX Vref=20, minBit 1, minWin=23, winSum=382
8472 10:52:02.907666 TX Vref=22, minBit 11, minWin=22, winSum=390
8473 10:52:02.914217 TX Vref=24, minBit 5, minWin=24, winSum=403
8474 10:52:02.917333 TX Vref=26, minBit 0, minWin=25, winSum=413
8475 10:52:02.921012 TX Vref=28, minBit 1, minWin=25, winSum=416
8476 10:52:02.924257 TX Vref=30, minBit 1, minWin=24, winSum=411
8477 10:52:02.927582 TX Vref=32, minBit 0, minWin=24, winSum=406
8478 10:52:02.930565 TX Vref=34, minBit 0, minWin=23, winSum=397
8479 10:52:02.937313 TX Vref=36, minBit 1, minWin=22, winSum=383
8480 10:52:02.940422 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
8481 10:52:02.940513
8482 10:52:02.943554 Final TX Range 0 Vref 28
8483 10:52:02.943645
8484 10:52:02.943712 ==
8485 10:52:02.947404 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 10:52:02.950351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 10:52:02.953653 ==
8488 10:52:02.953772
8489 10:52:02.953869
8490 10:52:02.953959 TX Vref Scan disable
8491 10:52:02.960533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8492 10:52:02.960664 == TX Byte 0 ==
8493 10:52:02.964020 u2DelayCellOfst[0]=22 cells (6 PI)
8494 10:52:02.966870 u2DelayCellOfst[1]=18 cells (5 PI)
8495 10:52:02.970412 u2DelayCellOfst[2]=0 cells (0 PI)
8496 10:52:02.973998 u2DelayCellOfst[3]=7 cells (2 PI)
8497 10:52:02.976893 u2DelayCellOfst[4]=11 cells (3 PI)
8498 10:52:02.980123 u2DelayCellOfst[5]=26 cells (7 PI)
8499 10:52:02.983700 u2DelayCellOfst[6]=22 cells (6 PI)
8500 10:52:02.986843 u2DelayCellOfst[7]=7 cells (2 PI)
8501 10:52:02.990296 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8502 10:52:02.993176 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8503 10:52:02.996995 == TX Byte 1 ==
8504 10:52:03.000156 u2DelayCellOfst[8]=0 cells (0 PI)
8505 10:52:03.003410 u2DelayCellOfst[9]=7 cells (2 PI)
8506 10:52:03.006435 u2DelayCellOfst[10]=15 cells (4 PI)
8507 10:52:03.009819 u2DelayCellOfst[11]=11 cells (3 PI)
8508 10:52:03.013268 u2DelayCellOfst[12]=18 cells (5 PI)
8509 10:52:03.016344 u2DelayCellOfst[13]=22 cells (6 PI)
8510 10:52:03.020194 u2DelayCellOfst[14]=22 cells (6 PI)
8511 10:52:03.022954 u2DelayCellOfst[15]=22 cells (6 PI)
8512 10:52:03.026552 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8513 10:52:03.029877 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8514 10:52:03.033044 DramC Write-DBI on
8515 10:52:03.033132 ==
8516 10:52:03.036316 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 10:52:03.039713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 10:52:03.039807 ==
8519 10:52:03.039875
8520 10:52:03.039938
8521 10:52:03.042749 TX Vref Scan disable
8522 10:52:03.045885 == TX Byte 0 ==
8523 10:52:03.049642 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8524 10:52:03.049730 == TX Byte 1 ==
8525 10:52:03.055921 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8526 10:52:03.056051 DramC Write-DBI off
8527 10:52:03.056148
8528 10:52:03.056248 [DATLAT]
8529 10:52:03.059241 Freq=1600, CH1 RK0
8530 10:52:03.059357
8531 10:52:03.062700 DATLAT Default: 0xf
8532 10:52:03.062816 0, 0xFFFF, sum = 0
8533 10:52:03.066146 1, 0xFFFF, sum = 0
8534 10:52:03.066235 2, 0xFFFF, sum = 0
8535 10:52:03.068997 3, 0xFFFF, sum = 0
8536 10:52:03.069084 4, 0xFFFF, sum = 0
8537 10:52:03.072422 5, 0xFFFF, sum = 0
8538 10:52:03.072541 6, 0xFFFF, sum = 0
8539 10:52:03.075848 7, 0xFFFF, sum = 0
8540 10:52:03.075930 8, 0xFFFF, sum = 0
8541 10:52:03.078913 9, 0xFFFF, sum = 0
8542 10:52:03.079028 10, 0xFFFF, sum = 0
8543 10:52:03.082271 11, 0xFFFF, sum = 0
8544 10:52:03.082386 12, 0xFFFF, sum = 0
8545 10:52:03.085919 13, 0x8FFF, sum = 0
8546 10:52:03.086034 14, 0x0, sum = 1
8547 10:52:03.089134 15, 0x0, sum = 2
8548 10:52:03.089244 16, 0x0, sum = 3
8549 10:52:03.092003 17, 0x0, sum = 4
8550 10:52:03.092094 best_step = 15
8551 10:52:03.092177
8552 10:52:03.092250 ==
8553 10:52:03.095570 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 10:52:03.101785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 10:52:03.101879 ==
8556 10:52:03.101947 RX Vref Scan: 1
8557 10:52:03.102011
8558 10:52:03.105435 Set Vref Range= 24 -> 127
8559 10:52:03.105522
8560 10:52:03.108475 RX Vref 24 -> 127, step: 1
8561 10:52:03.108558
8562 10:52:03.112185 RX Delay 11 -> 252, step: 4
8563 10:52:03.112266
8564 10:52:03.115075 Set Vref, RX VrefLevel [Byte0]: 24
8565 10:52:03.118509 [Byte1]: 24
8566 10:52:03.118619
8567 10:52:03.121879 Set Vref, RX VrefLevel [Byte0]: 25
8568 10:52:03.124999 [Byte1]: 25
8569 10:52:03.125138
8570 10:52:03.128602 Set Vref, RX VrefLevel [Byte0]: 26
8571 10:52:03.131551 [Byte1]: 26
8572 10:52:03.135146
8573 10:52:03.135265 Set Vref, RX VrefLevel [Byte0]: 27
8574 10:52:03.138258 [Byte1]: 27
8575 10:52:03.142363
8576 10:52:03.142506 Set Vref, RX VrefLevel [Byte0]: 28
8577 10:52:03.146199 [Byte1]: 28
8578 10:52:03.150533
8579 10:52:03.150655 Set Vref, RX VrefLevel [Byte0]: 29
8580 10:52:03.153783 [Byte1]: 29
8581 10:52:03.157981
8582 10:52:03.158106 Set Vref, RX VrefLevel [Byte0]: 30
8583 10:52:03.160952 [Byte1]: 30
8584 10:52:03.165671
8585 10:52:03.165807 Set Vref, RX VrefLevel [Byte0]: 31
8586 10:52:03.168639 [Byte1]: 31
8587 10:52:03.173223
8588 10:52:03.173349 Set Vref, RX VrefLevel [Byte0]: 32
8589 10:52:03.176487 [Byte1]: 32
8590 10:52:03.180507
8591 10:52:03.180648 Set Vref, RX VrefLevel [Byte0]: 33
8592 10:52:03.184041 [Byte1]: 33
8593 10:52:03.188084
8594 10:52:03.188210 Set Vref, RX VrefLevel [Byte0]: 34
8595 10:52:03.191388 [Byte1]: 34
8596 10:52:03.196107
8597 10:52:03.196238 Set Vref, RX VrefLevel [Byte0]: 35
8598 10:52:03.199038 [Byte1]: 35
8599 10:52:03.203821
8600 10:52:03.203956 Set Vref, RX VrefLevel [Byte0]: 36
8601 10:52:03.206884 [Byte1]: 36
8602 10:52:03.211236
8603 10:52:03.211371 Set Vref, RX VrefLevel [Byte0]: 37
8604 10:52:03.214344 [Byte1]: 37
8605 10:52:03.218774
8606 10:52:03.218909 Set Vref, RX VrefLevel [Byte0]: 38
8607 10:52:03.221908 [Byte1]: 38
8608 10:52:03.226524
8609 10:52:03.226673 Set Vref, RX VrefLevel [Byte0]: 39
8610 10:52:03.229499 [Byte1]: 39
8611 10:52:03.234481
8612 10:52:03.234632 Set Vref, RX VrefLevel [Byte0]: 40
8613 10:52:03.237007 [Byte1]: 40
8614 10:52:03.241788
8615 10:52:03.241903 Set Vref, RX VrefLevel [Byte0]: 41
8616 10:52:03.244740 [Byte1]: 41
8617 10:52:03.249268
8618 10:52:03.249391 Set Vref, RX VrefLevel [Byte0]: 42
8619 10:52:03.252459 [Byte1]: 42
8620 10:52:03.256852
8621 10:52:03.256969 Set Vref, RX VrefLevel [Byte0]: 43
8622 10:52:03.260424 [Byte1]: 43
8623 10:52:03.264223
8624 10:52:03.264352 Set Vref, RX VrefLevel [Byte0]: 44
8625 10:52:03.267737 [Byte1]: 44
8626 10:52:03.271945
8627 10:52:03.272059 Set Vref, RX VrefLevel [Byte0]: 45
8628 10:52:03.275315 [Byte1]: 45
8629 10:52:03.279698
8630 10:52:03.279817 Set Vref, RX VrefLevel [Byte0]: 46
8631 10:52:03.283274 [Byte1]: 46
8632 10:52:03.287550
8633 10:52:03.287668 Set Vref, RX VrefLevel [Byte0]: 47
8634 10:52:03.290534 [Byte1]: 47
8635 10:52:03.294674
8636 10:52:03.294786 Set Vref, RX VrefLevel [Byte0]: 48
8637 10:52:03.298176 [Byte1]: 48
8638 10:52:03.302425
8639 10:52:03.302541 Set Vref, RX VrefLevel [Byte0]: 49
8640 10:52:03.305912 [Byte1]: 49
8641 10:52:03.310094
8642 10:52:03.310186 Set Vref, RX VrefLevel [Byte0]: 50
8643 10:52:03.313524 [Byte1]: 50
8644 10:52:03.317610
8645 10:52:03.317720 Set Vref, RX VrefLevel [Byte0]: 51
8646 10:52:03.320797 [Byte1]: 51
8647 10:52:03.325047
8648 10:52:03.325170 Set Vref, RX VrefLevel [Byte0]: 52
8649 10:52:03.328722 [Byte1]: 52
8650 10:52:03.333369
8651 10:52:03.333486 Set Vref, RX VrefLevel [Byte0]: 53
8652 10:52:03.336573 [Byte1]: 53
8653 10:52:03.340592
8654 10:52:03.340714 Set Vref, RX VrefLevel [Byte0]: 54
8655 10:52:03.343964 [Byte1]: 54
8656 10:52:03.348237
8657 10:52:03.348371 Set Vref, RX VrefLevel [Byte0]: 55
8658 10:52:03.351363 [Byte1]: 55
8659 10:52:03.355710
8660 10:52:03.355800 Set Vref, RX VrefLevel [Byte0]: 56
8661 10:52:03.358791 [Byte1]: 56
8662 10:52:03.363123
8663 10:52:03.363222 Set Vref, RX VrefLevel [Byte0]: 57
8664 10:52:03.366944 [Byte1]: 57
8665 10:52:03.371034
8666 10:52:03.371149 Set Vref, RX VrefLevel [Byte0]: 58
8667 10:52:03.374164 [Byte1]: 58
8668 10:52:03.378258
8669 10:52:03.378347 Set Vref, RX VrefLevel [Byte0]: 59
8670 10:52:03.381729 [Byte1]: 59
8671 10:52:03.386252
8672 10:52:03.386371 Set Vref, RX VrefLevel [Byte0]: 60
8673 10:52:03.389522 [Byte1]: 60
8674 10:52:03.394069
8675 10:52:03.394203 Set Vref, RX VrefLevel [Byte0]: 61
8676 10:52:03.396937 [Byte1]: 61
8677 10:52:03.401625
8678 10:52:03.401723 Set Vref, RX VrefLevel [Byte0]: 62
8679 10:52:03.404716 [Byte1]: 62
8680 10:52:03.409220
8681 10:52:03.409347 Set Vref, RX VrefLevel [Byte0]: 63
8682 10:52:03.412840 [Byte1]: 63
8683 10:52:03.416815
8684 10:52:03.416931 Set Vref, RX VrefLevel [Byte0]: 64
8685 10:52:03.419923 [Byte1]: 64
8686 10:52:03.424243
8687 10:52:03.424358 Set Vref, RX VrefLevel [Byte0]: 65
8688 10:52:03.427465 [Byte1]: 65
8689 10:52:03.431720
8690 10:52:03.431809 Set Vref, RX VrefLevel [Byte0]: 66
8691 10:52:03.435345 [Byte1]: 66
8692 10:52:03.439337
8693 10:52:03.439456 Set Vref, RX VrefLevel [Byte0]: 67
8694 10:52:03.442666 [Byte1]: 67
8695 10:52:03.447201
8696 10:52:03.447324 Set Vref, RX VrefLevel [Byte0]: 68
8697 10:52:03.450454 [Byte1]: 68
8698 10:52:03.454733
8699 10:52:03.454872 Set Vref, RX VrefLevel [Byte0]: 69
8700 10:52:03.457768 [Byte1]: 69
8701 10:52:03.462085
8702 10:52:03.462203 Set Vref, RX VrefLevel [Byte0]: 70
8703 10:52:03.465612 [Byte1]: 70
8704 10:52:03.469951
8705 10:52:03.470068 Set Vref, RX VrefLevel [Byte0]: 71
8706 10:52:03.472960 [Byte1]: 71
8707 10:52:03.477676
8708 10:52:03.477792 Set Vref, RX VrefLevel [Byte0]: 72
8709 10:52:03.480689 [Byte1]: 72
8710 10:52:03.485371
8711 10:52:03.485491 Final RX Vref Byte 0 = 60 to rank0
8712 10:52:03.488284 Final RX Vref Byte 1 = 55 to rank0
8713 10:52:03.492036 Final RX Vref Byte 0 = 60 to rank1
8714 10:52:03.495009 Final RX Vref Byte 1 = 55 to rank1==
8715 10:52:03.498156 Dram Type= 6, Freq= 0, CH_1, rank 0
8716 10:52:03.504934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 10:52:03.505025 ==
8718 10:52:03.505094 DQS Delay:
8719 10:52:03.505158 DQS0 = 0, DQS1 = 0
8720 10:52:03.508405 DQM Delay:
8721 10:52:03.508490 DQM0 = 129, DQM1 = 122
8722 10:52:03.511485 DQ Delay:
8723 10:52:03.514949 DQ0 =136, DQ1 =126, DQ2 =118, DQ3 =126
8724 10:52:03.518376 DQ4 =128, DQ5 =140, DQ6 =140, DQ7 =124
8725 10:52:03.521243 DQ8 =106, DQ9 =112, DQ10 =122, DQ11 =114
8726 10:52:03.524979 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =132
8727 10:52:03.525064
8728 10:52:03.525130
8729 10:52:03.525193
8730 10:52:03.528106 [DramC_TX_OE_Calibration] TA2
8731 10:52:03.531266 Original DQ_B0 (3 6) =30, OEN = 27
8732 10:52:03.534746 Original DQ_B1 (3 6) =30, OEN = 27
8733 10:52:03.538209 24, 0x0, End_B0=24 End_B1=24
8734 10:52:03.541154 25, 0x0, End_B0=25 End_B1=25
8735 10:52:03.541240 26, 0x0, End_B0=26 End_B1=26
8736 10:52:03.544224 27, 0x0, End_B0=27 End_B1=27
8737 10:52:03.547791 28, 0x0, End_B0=28 End_B1=28
8738 10:52:03.551144 29, 0x0, End_B0=29 End_B1=29
8739 10:52:03.551231 30, 0x0, End_B0=30 End_B1=30
8740 10:52:03.554326 31, 0x4141, End_B0=30 End_B1=30
8741 10:52:03.557601 Byte0 end_step=30 best_step=27
8742 10:52:03.560937 Byte1 end_step=30 best_step=27
8743 10:52:03.564412 Byte0 TX OE(2T, 0.5T) = (3, 3)
8744 10:52:03.567510 Byte1 TX OE(2T, 0.5T) = (3, 3)
8745 10:52:03.567626
8746 10:52:03.567731
8747 10:52:03.574234 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8748 10:52:03.577297 CH1 RK0: MR19=303, MR18=A0F
8749 10:52:03.583860 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8750 10:52:03.583945
8751 10:52:03.587582 ----->DramcWriteLeveling(PI) begin...
8752 10:52:03.587681 ==
8753 10:52:03.590448 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 10:52:03.593880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 10:52:03.593961 ==
8756 10:52:03.597346 Write leveling (Byte 0): 23 => 23
8757 10:52:03.600232 Write leveling (Byte 1): 29 => 29
8758 10:52:03.603486 DramcWriteLeveling(PI) end<-----
8759 10:52:03.603567
8760 10:52:03.603654 ==
8761 10:52:03.607166 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 10:52:03.610475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 10:52:03.613948 ==
8764 10:52:03.614044 [Gating] SW mode calibration
8765 10:52:03.620536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8766 10:52:03.627318 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8767 10:52:03.630312 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 10:52:03.637234 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 10:52:03.640225 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8770 10:52:03.643312 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8771 10:52:03.650047 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 10:52:03.653190 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 10:52:03.656857 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 10:52:03.663195 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 10:52:03.666364 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 10:52:03.669807 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8777 10:52:03.676318 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8778 10:52:03.680139 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
8779 10:52:03.683112 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 10:52:03.689736 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 10:52:03.692890 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 10:52:03.696743 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 10:52:03.702811 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 10:52:03.706351 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8785 10:52:03.709228 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8786 10:52:03.716000 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8787 10:52:03.719366 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 10:52:03.722924 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 10:52:03.729018 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 10:52:03.732507 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 10:52:03.735616 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 10:52:03.742477 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 10:52:03.745456 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 10:52:03.749174 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8795 10:52:03.755652 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 10:52:03.758697 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 10:52:03.762331 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 10:52:03.768457 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 10:52:03.772024 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 10:52:03.775373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:52:03.781749 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:52:03.784762 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:52:03.788515 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 10:52:03.795155 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 10:52:03.798296 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 10:52:03.801662 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 10:52:03.808341 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 10:52:03.811667 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 10:52:03.814760 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 10:52:03.821354 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8811 10:52:03.824651 Total UI for P1: 0, mck2ui 16
8812 10:52:03.828027 best dqsien dly found for B0: ( 1, 9, 6)
8813 10:52:03.831177 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8814 10:52:03.834865 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 10:52:03.837640 Total UI for P1: 0, mck2ui 16
8816 10:52:03.841338 best dqsien dly found for B1: ( 1, 9, 14)
8817 10:52:03.844219 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8818 10:52:03.847936 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8819 10:52:03.848045
8820 10:52:03.854401 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8821 10:52:03.857547 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8822 10:52:03.860553 [Gating] SW calibration Done
8823 10:52:03.860659 ==
8824 10:52:03.864147 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 10:52:03.867219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 10:52:03.867299 ==
8827 10:52:03.867365 RX Vref Scan: 0
8828 10:52:03.870995
8829 10:52:03.871075 RX Vref 0 -> 0, step: 1
8830 10:52:03.871141
8831 10:52:03.874073 RX Delay 0 -> 252, step: 8
8832 10:52:03.877252 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8833 10:52:03.880859 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8834 10:52:03.886932 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8835 10:52:03.890274 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8836 10:52:03.893910 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8837 10:52:03.897000 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8838 10:52:03.900143 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8839 10:52:03.907374 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8840 10:52:03.910023 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8841 10:52:03.913609 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8842 10:52:03.916987 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8843 10:52:03.923414 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8844 10:52:03.926801 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8845 10:52:03.929726 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8846 10:52:03.933021 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8847 10:52:03.936358 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8848 10:52:03.939508 ==
8849 10:52:03.943016 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 10:52:03.946783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 10:52:03.946894 ==
8852 10:52:03.946962 DQS Delay:
8853 10:52:03.949497 DQS0 = 0, DQS1 = 0
8854 10:52:03.949579 DQM Delay:
8855 10:52:03.952711 DQM0 = 132, DQM1 = 128
8856 10:52:03.952791 DQ Delay:
8857 10:52:03.955800 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8858 10:52:03.959345 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8859 10:52:03.962484 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8860 10:52:03.966359 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =135
8861 10:52:03.966443
8862 10:52:03.966509
8863 10:52:03.969380 ==
8864 10:52:03.969464 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 10:52:03.976028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 10:52:03.976124 ==
8867 10:52:03.976197
8868 10:52:03.976261
8869 10:52:03.979023 TX Vref Scan disable
8870 10:52:03.979139 == TX Byte 0 ==
8871 10:52:03.982790 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8872 10:52:03.988906 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8873 10:52:03.989002 == TX Byte 1 ==
8874 10:52:03.992515 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8875 10:52:03.998888 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8876 10:52:03.998977 ==
8877 10:52:04.001982 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 10:52:04.005715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 10:52:04.005825 ==
8880 10:52:04.020461
8881 10:52:04.023310 TX Vref early break, caculate TX vref
8882 10:52:04.026682 TX Vref=16, minBit 0, minWin=22, winSum=373
8883 10:52:04.030077 TX Vref=18, minBit 1, minWin=22, winSum=383
8884 10:52:04.033808 TX Vref=20, minBit 0, minWin=22, winSum=388
8885 10:52:04.036977 TX Vref=22, minBit 0, minWin=23, winSum=399
8886 10:52:04.039787 TX Vref=24, minBit 0, minWin=24, winSum=405
8887 10:52:04.046519 TX Vref=26, minBit 0, minWin=24, winSum=414
8888 10:52:04.050146 TX Vref=28, minBit 6, minWin=24, winSum=415
8889 10:52:04.053382 TX Vref=30, minBit 0, minWin=25, winSum=412
8890 10:52:04.056818 TX Vref=32, minBit 6, minWin=24, winSum=405
8891 10:52:04.059714 TX Vref=34, minBit 5, minWin=23, winSum=394
8892 10:52:04.066184 TX Vref=36, minBit 8, minWin=22, winSum=383
8893 10:52:04.069767 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
8894 10:52:04.069881
8895 10:52:04.072628 Final TX Range 0 Vref 30
8896 10:52:04.072731
8897 10:52:04.072824 ==
8898 10:52:04.076247 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 10:52:04.079244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 10:52:04.082436 ==
8901 10:52:04.082537
8902 10:52:04.082628
8903 10:52:04.082718 TX Vref Scan disable
8904 10:52:04.089304 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8905 10:52:04.089389 == TX Byte 0 ==
8906 10:52:04.092950 u2DelayCellOfst[0]=18 cells (5 PI)
8907 10:52:04.095756 u2DelayCellOfst[1]=15 cells (4 PI)
8908 10:52:04.099347 u2DelayCellOfst[2]=0 cells (0 PI)
8909 10:52:04.102840 u2DelayCellOfst[3]=7 cells (2 PI)
8910 10:52:04.105710 u2DelayCellOfst[4]=7 cells (2 PI)
8911 10:52:04.109209 u2DelayCellOfst[5]=22 cells (6 PI)
8912 10:52:04.113081 u2DelayCellOfst[6]=22 cells (6 PI)
8913 10:52:04.116110 u2DelayCellOfst[7]=7 cells (2 PI)
8914 10:52:04.119258 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8915 10:52:04.122238 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8916 10:52:04.125851 == TX Byte 1 ==
8917 10:52:04.129028 u2DelayCellOfst[8]=0 cells (0 PI)
8918 10:52:04.132510 u2DelayCellOfst[9]=7 cells (2 PI)
8919 10:52:04.135710 u2DelayCellOfst[10]=15 cells (4 PI)
8920 10:52:04.138853 u2DelayCellOfst[11]=7 cells (2 PI)
8921 10:52:04.141821 u2DelayCellOfst[12]=18 cells (5 PI)
8922 10:52:04.145266 u2DelayCellOfst[13]=18 cells (5 PI)
8923 10:52:04.148846 u2DelayCellOfst[14]=22 cells (6 PI)
8924 10:52:04.151681 u2DelayCellOfst[15]=22 cells (6 PI)
8925 10:52:04.155077 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8926 10:52:04.158725 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8927 10:52:04.161696 DramC Write-DBI on
8928 10:52:04.161804 ==
8929 10:52:04.164751 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 10:52:04.168300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 10:52:04.168383 ==
8932 10:52:04.168450
8933 10:52:04.168540
8934 10:52:04.171240 TX Vref Scan disable
8935 10:52:04.174806 == TX Byte 0 ==
8936 10:52:04.177852 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8937 10:52:04.177956 == TX Byte 1 ==
8938 10:52:04.184629 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8939 10:52:04.184752 DramC Write-DBI off
8940 10:52:04.184862
8941 10:52:04.184967 [DATLAT]
8942 10:52:04.188266 Freq=1600, CH1 RK1
8943 10:52:04.188343
8944 10:52:04.191490 DATLAT Default: 0xf
8945 10:52:04.191593 0, 0xFFFF, sum = 0
8946 10:52:04.194611 1, 0xFFFF, sum = 0
8947 10:52:04.194713 2, 0xFFFF, sum = 0
8948 10:52:04.197768 3, 0xFFFF, sum = 0
8949 10:52:04.197878 4, 0xFFFF, sum = 0
8950 10:52:04.201180 5, 0xFFFF, sum = 0
8951 10:52:04.201290 6, 0xFFFF, sum = 0
8952 10:52:04.204469 7, 0xFFFF, sum = 0
8953 10:52:04.204581 8, 0xFFFF, sum = 0
8954 10:52:04.207501 9, 0xFFFF, sum = 0
8955 10:52:04.207609 10, 0xFFFF, sum = 0
8956 10:52:04.210976 11, 0xFFFF, sum = 0
8957 10:52:04.211062 12, 0xFFFF, sum = 0
8958 10:52:04.214591 13, 0x8FFF, sum = 0
8959 10:52:04.214698 14, 0x0, sum = 1
8960 10:52:04.217614 15, 0x0, sum = 2
8961 10:52:04.217725 16, 0x0, sum = 3
8962 10:52:04.221224 17, 0x0, sum = 4
8963 10:52:04.221314 best_step = 15
8964 10:52:04.221383
8965 10:52:04.221446 ==
8966 10:52:04.224377 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 10:52:04.231028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 10:52:04.231109 ==
8969 10:52:04.231175 RX Vref Scan: 0
8970 10:52:04.231240
8971 10:52:04.234158 RX Vref 0 -> 0, step: 1
8972 10:52:04.234236
8973 10:52:04.237266 RX Delay 3 -> 252, step: 4
8974 10:52:04.240977 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8975 10:52:04.244053 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8976 10:52:04.251017 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8977 10:52:04.254378 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8978 10:52:04.257039 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8979 10:52:04.260422 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8980 10:52:04.263956 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8981 10:52:04.270361 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8982 10:52:04.273530 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8983 10:52:04.276876 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8984 10:52:04.280223 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8985 10:52:04.283763 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8986 10:52:04.290494 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8987 10:52:04.293638 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8988 10:52:04.296846 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8989 10:52:04.300012 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8990 10:52:04.300092 ==
8991 10:52:04.303516 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 10:52:04.310180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 10:52:04.310292 ==
8994 10:52:04.310394 DQS Delay:
8995 10:52:04.313345 DQS0 = 0, DQS1 = 0
8996 10:52:04.313452 DQM Delay:
8997 10:52:04.316666 DQM0 = 129, DQM1 = 124
8998 10:52:04.316773 DQ Delay:
8999 10:52:04.319680 DQ0 =136, DQ1 =128, DQ2 =116, DQ3 =126
9000 10:52:04.323251 DQ4 =124, DQ5 =138, DQ6 =140, DQ7 =126
9001 10:52:04.326309 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
9002 10:52:04.330032 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9003 10:52:04.330140
9004 10:52:04.330235
9005 10:52:04.330325
9006 10:52:04.333042 [DramC_TX_OE_Calibration] TA2
9007 10:52:04.336646 Original DQ_B0 (3 6) =30, OEN = 27
9008 10:52:04.339836 Original DQ_B1 (3 6) =30, OEN = 27
9009 10:52:04.342679 24, 0x0, End_B0=24 End_B1=24
9010 10:52:04.346332 25, 0x0, End_B0=25 End_B1=25
9011 10:52:04.346461 26, 0x0, End_B0=26 End_B1=26
9012 10:52:04.349427 27, 0x0, End_B0=27 End_B1=27
9013 10:52:04.352873 28, 0x0, End_B0=28 End_B1=28
9014 10:52:04.355861 29, 0x0, End_B0=29 End_B1=29
9015 10:52:04.359197 30, 0x0, End_B0=30 End_B1=30
9016 10:52:04.359306 31, 0x4141, End_B0=30 End_B1=30
9017 10:52:04.362651 Byte0 end_step=30 best_step=27
9018 10:52:04.365918 Byte1 end_step=30 best_step=27
9019 10:52:04.369249 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 10:52:04.372430 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 10:52:04.372537
9022 10:52:04.372645
9023 10:52:04.379029 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9024 10:52:04.382454 CH1 RK1: MR19=303, MR18=101D
9025 10:52:04.388761 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
9026 10:52:04.392290 [RxdqsGatingPostProcess] freq 1600
9027 10:52:04.399301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 10:52:04.402176 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 10:52:04.402257 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 10:52:04.405262 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 10:52:04.408860 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 10:52:04.411845 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 10:52:04.415461 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 10:52:04.418458 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 10:52:04.421614 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 10:52:04.424927 Pre-setting of DQS Precalculation
9037 10:52:04.431829 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 10:52:04.438030 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 10:52:04.444862 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 10:52:04.444978
9041 10:52:04.445076
9042 10:52:04.447845 [Calibration Summary] 3200 Mbps
9043 10:52:04.447931 CH 0, Rank 0
9044 10:52:04.451438 SW Impedance : PASS
9045 10:52:04.454586 DUTY Scan : NO K
9046 10:52:04.454671 ZQ Calibration : PASS
9047 10:52:04.458148 Jitter Meter : NO K
9048 10:52:04.461544 CBT Training : PASS
9049 10:52:04.461653 Write leveling : PASS
9050 10:52:04.464788 RX DQS gating : PASS
9051 10:52:04.467738 RX DQ/DQS(RDDQC) : PASS
9052 10:52:04.467845 TX DQ/DQS : PASS
9053 10:52:04.470995 RX DATLAT : PASS
9054 10:52:04.474387 RX DQ/DQS(Engine): PASS
9055 10:52:04.474497 TX OE : PASS
9056 10:52:04.474594 All Pass.
9057 10:52:04.477762
9058 10:52:04.477869 CH 0, Rank 1
9059 10:52:04.481089 SW Impedance : PASS
9060 10:52:04.481200 DUTY Scan : NO K
9061 10:52:04.484472 ZQ Calibration : PASS
9062 10:52:04.484575 Jitter Meter : NO K
9063 10:52:04.487431 CBT Training : PASS
9064 10:52:04.490967 Write leveling : PASS
9065 10:52:04.491043 RX DQS gating : PASS
9066 10:52:04.494242 RX DQ/DQS(RDDQC) : PASS
9067 10:52:04.497247 TX DQ/DQS : PASS
9068 10:52:04.497358 RX DATLAT : PASS
9069 10:52:04.500783 RX DQ/DQS(Engine): PASS
9070 10:52:04.504390 TX OE : PASS
9071 10:52:04.504465 All Pass.
9072 10:52:04.504535
9073 10:52:04.504598 CH 1, Rank 0
9074 10:52:04.507377 SW Impedance : PASS
9075 10:52:04.510807 DUTY Scan : NO K
9076 10:52:04.510895 ZQ Calibration : PASS
9077 10:52:04.514329 Jitter Meter : NO K
9078 10:52:04.517298 CBT Training : PASS
9079 10:52:04.517371 Write leveling : PASS
9080 10:52:04.520890 RX DQS gating : PASS
9081 10:52:04.523882 RX DQ/DQS(RDDQC) : PASS
9082 10:52:04.523960 TX DQ/DQS : PASS
9083 10:52:04.527314 RX DATLAT : PASS
9084 10:52:04.530700 RX DQ/DQS(Engine): PASS
9085 10:52:04.530805 TX OE : PASS
9086 10:52:04.533839 All Pass.
9087 10:52:04.533941
9088 10:52:04.534041 CH 1, Rank 1
9089 10:52:04.537380 SW Impedance : PASS
9090 10:52:04.537459 DUTY Scan : NO K
9091 10:52:04.540307 ZQ Calibration : PASS
9092 10:52:04.543902 Jitter Meter : NO K
9093 10:52:04.543981 CBT Training : PASS
9094 10:52:04.546820 Write leveling : PASS
9095 10:52:04.550489 RX DQS gating : PASS
9096 10:52:04.550595 RX DQ/DQS(RDDQC) : PASS
9097 10:52:04.553334 TX DQ/DQS : PASS
9098 10:52:04.553444 RX DATLAT : PASS
9099 10:52:04.557019 RX DQ/DQS(Engine): PASS
9100 10:52:04.560061 TX OE : PASS
9101 10:52:04.560143 All Pass.
9102 10:52:04.560207
9103 10:52:04.563523 DramC Write-DBI on
9104 10:52:04.563595 PER_BANK_REFRESH: Hybrid Mode
9105 10:52:04.567005 TX_TRACKING: ON
9106 10:52:04.576872 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 10:52:04.583512 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 10:52:04.589771 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 10:52:04.592889 [FAST_K] Save calibration result to emmc
9110 10:52:04.596098 sync common calibartion params.
9111 10:52:04.599552 sync cbt_mode0:1, 1:1
9112 10:52:04.602932 dram_init: ddr_geometry: 2
9113 10:52:04.603006 dram_init: ddr_geometry: 2
9114 10:52:04.606089 dram_init: ddr_geometry: 2
9115 10:52:04.609366 0:dram_rank_size:100000000
9116 10:52:04.612763 1:dram_rank_size:100000000
9117 10:52:04.616290 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 10:52:04.619292 DFS_SHUFFLE_HW_MODE: ON
9119 10:52:04.622840 dramc_set_vcore_voltage set vcore to 725000
9120 10:52:04.625885 Read voltage for 1600, 0
9121 10:52:04.625959 Vio18 = 0
9122 10:52:04.626021 Vcore = 725000
9123 10:52:04.629545 Vdram = 0
9124 10:52:04.629615 Vddq = 0
9125 10:52:04.629676 Vmddr = 0
9126 10:52:04.632661 switch to 3200 Mbps bootup
9127 10:52:04.636306 [DramcRunTimeConfig]
9128 10:52:04.636379 PHYPLL
9129 10:52:04.636447 DPM_CONTROL_AFTERK: ON
9130 10:52:04.638961 PER_BANK_REFRESH: ON
9131 10:52:04.642670 REFRESH_OVERHEAD_REDUCTION: ON
9132 10:52:04.642768 CMD_PICG_NEW_MODE: OFF
9133 10:52:04.645575 XRTWTW_NEW_MODE: ON
9134 10:52:04.649175 XRTRTR_NEW_MODE: ON
9135 10:52:04.649251 TX_TRACKING: ON
9136 10:52:04.652055 RDSEL_TRACKING: OFF
9137 10:52:04.652126 DQS Precalculation for DVFS: ON
9138 10:52:04.655589 RX_TRACKING: OFF
9139 10:52:04.655698 HW_GATING DBG: ON
9140 10:52:04.659255 ZQCS_ENABLE_LP4: ON
9141 10:52:04.662343 RX_PICG_NEW_MODE: ON
9142 10:52:04.662420 TX_PICG_NEW_MODE: ON
9143 10:52:04.665355 ENABLE_RX_DCM_DPHY: ON
9144 10:52:04.668730 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 10:52:04.668800 DUMMY_READ_FOR_TRACKING: OFF
9146 10:52:04.672257 !!! SPM_CONTROL_AFTERK: OFF
9147 10:52:04.675368 !!! SPM could not control APHY
9148 10:52:04.678815 IMPEDANCE_TRACKING: ON
9149 10:52:04.678932 TEMP_SENSOR: ON
9150 10:52:04.682374 HW_SAVE_FOR_SR: OFF
9151 10:52:04.685166 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 10:52:04.688450 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 10:52:04.688526 Read ODT Tracking: ON
9154 10:52:04.691831 Refresh Rate DeBounce: ON
9155 10:52:04.695291 DFS_NO_QUEUE_FLUSH: ON
9156 10:52:04.698969 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 10:52:04.699075 ENABLE_DFS_RUNTIME_MRW: OFF
9158 10:52:04.702039 DDR_RESERVE_NEW_MODE: ON
9159 10:52:04.705026 MR_CBT_SWITCH_FREQ: ON
9160 10:52:04.705122 =========================
9161 10:52:04.725317 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 10:52:04.728179 dram_init: ddr_geometry: 2
9163 10:52:04.746631 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 10:52:04.750056 dram_init: dram init end (result: 0)
9165 10:52:04.756185 DRAM-K: Full calibration passed in 24585 msecs
9166 10:52:04.759729 MRC: failed to locate region type 0.
9167 10:52:04.759816 DRAM rank0 size:0x100000000,
9168 10:52:04.762702 DRAM rank1 size=0x100000000
9169 10:52:04.772949 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 10:52:04.779511 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 10:52:04.785739 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 10:52:04.795597 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 10:52:04.795699 DRAM rank0 size:0x100000000,
9174 10:52:04.798940 DRAM rank1 size=0x100000000
9175 10:52:04.799024 CBMEM:
9176 10:52:04.802352 IMD: root @ 0xfffff000 254 entries.
9177 10:52:04.805882 IMD: root @ 0xffffec00 62 entries.
9178 10:52:04.809119 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 10:52:04.815479 WARNING: RO_VPD is uninitialized or empty.
9180 10:52:04.819055 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 10:52:04.826513 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 10:52:04.839458 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9183 10:52:04.850774 BS: romstage times (exec / console): total (unknown) / 24049 ms
9184 10:52:04.850887
9185 10:52:04.850955
9186 10:52:04.860814 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 10:52:04.863755 ARM64: Exception handlers installed.
9188 10:52:04.867354 ARM64: Testing exception
9189 10:52:04.870476 ARM64: Done test exception
9190 10:52:04.870590 Enumerating buses...
9191 10:52:04.873463 Show all devs... Before device enumeration.
9192 10:52:04.876856 Root Device: enabled 1
9193 10:52:04.880668 CPU_CLUSTER: 0: enabled 1
9194 10:52:04.880746 CPU: 00: enabled 1
9195 10:52:04.883808 Compare with tree...
9196 10:52:04.883891 Root Device: enabled 1
9197 10:52:04.886747 CPU_CLUSTER: 0: enabled 1
9198 10:52:04.890243 CPU: 00: enabled 1
9199 10:52:04.890317 Root Device scanning...
9200 10:52:04.893759 scan_static_bus for Root Device
9201 10:52:04.896813 CPU_CLUSTER: 0 enabled
9202 10:52:04.900295 scan_static_bus for Root Device done
9203 10:52:04.903689 scan_bus: bus Root Device finished in 8 msecs
9204 10:52:04.903803 done
9205 10:52:04.910352 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 10:52:04.913194 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 10:52:04.919861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 10:52:04.923197 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 10:52:04.926658 Allocating resources...
9210 10:52:04.929683 Reading resources...
9211 10:52:04.933426 Root Device read_resources bus 0 link: 0
9212 10:52:04.936537 DRAM rank0 size:0x100000000,
9213 10:52:04.936662 DRAM rank1 size=0x100000000
9214 10:52:04.943300 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 10:52:04.943410 CPU: 00 missing read_resources
9216 10:52:04.949458 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 10:52:04.953411 Root Device read_resources bus 0 link: 0 done
9218 10:52:04.956004 Done reading resources.
9219 10:52:04.959538 Show resources in subtree (Root Device)...After reading.
9220 10:52:04.962522 Root Device child on link 0 CPU_CLUSTER: 0
9221 10:52:04.966335 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 10:52:04.976295 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 10:52:04.976385 CPU: 00
9224 10:52:04.982972 Root Device assign_resources, bus 0 link: 0
9225 10:52:04.983097 CPU_CLUSTER: 0 missing set_resources
9226 10:52:04.989175 Root Device assign_resources, bus 0 link: 0 done
9227 10:52:04.989260 Done setting resources.
9228 10:52:04.996081 Show resources in subtree (Root Device)...After assigning values.
9229 10:52:04.999219 Root Device child on link 0 CPU_CLUSTER: 0
9230 10:52:05.002390 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 10:52:05.012486 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 10:52:05.012577 CPU: 00
9233 10:52:05.015857 Done allocating resources.
9234 10:52:05.022081 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 10:52:05.022167 Enabling resources...
9236 10:52:05.025598 done.
9237 10:52:05.029160 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 10:52:05.032423 Initializing devices...
9239 10:52:05.032507 Root Device init
9240 10:52:05.035727 init hardware done!
9241 10:52:05.035811 0x00000018: ctrlr->caps
9242 10:52:05.038715 52.000 MHz: ctrlr->f_max
9243 10:52:05.042267 0.400 MHz: ctrlr->f_min
9244 10:52:05.042391 0x40ff8080: ctrlr->voltages
9245 10:52:05.045497 sclk: 390625
9246 10:52:05.045607 Bus Width = 1
9247 10:52:05.048594 sclk: 390625
9248 10:52:05.048677 Bus Width = 1
9249 10:52:05.052292 Early init status = 3
9250 10:52:05.055327 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 10:52:05.058436 in-header: 03 fc 00 00 01 00 00 00
9252 10:52:05.061957 in-data: 00
9253 10:52:05.065444 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 10:52:05.069701 in-header: 03 fd 00 00 00 00 00 00
9255 10:52:05.072606 in-data:
9256 10:52:05.075792 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 10:52:05.079478 in-header: 03 fc 00 00 01 00 00 00
9258 10:52:05.082520 in-data: 00
9259 10:52:05.085963 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 10:52:05.090374 in-header: 03 fd 00 00 00 00 00 00
9261 10:52:05.094209 in-data:
9262 10:52:05.097150 [SSUSB] Setting up USB HOST controller...
9263 10:52:05.100564 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 10:52:05.103605 [SSUSB] phy power-on done.
9265 10:52:05.107289 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 10:52:05.113725 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 10:52:05.116865 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 10:52:05.123359 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 10:52:05.130002 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 10:52:05.136325 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 10:52:05.143123 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 10:52:05.149535 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9273 10:52:05.153319 SPM: binary array size = 0x9dc
9274 10:52:05.159543 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 10:52:05.162753 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 10:52:05.172964 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 10:52:05.175996 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 10:52:05.179209 configure_display: Starting display init
9279 10:52:05.214190 anx7625_power_on_init: Init interface.
9280 10:52:05.217230 anx7625_disable_pd_protocol: Disabled PD feature.
9281 10:52:05.220595 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 10:52:05.248477 anx7625_start_dp_work: Secure OCM version=00
9283 10:52:05.251872 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 10:52:05.266389 sp_tx_get_edid_block: EDID Block = 1
9285 10:52:05.369283 Extracted contents:
9286 10:52:05.372378 header: 00 ff ff ff ff ff ff 00
9287 10:52:05.375532 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 10:52:05.379087 version: 01 04
9289 10:52:05.382026 basic params: 95 1f 11 78 0a
9290 10:52:05.385179 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 10:52:05.388759 established: 00 00 00
9292 10:52:05.395163 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 10:52:05.402005 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 10:52:05.405006 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 10:52:05.411782 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 10:52:05.418652 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 10:52:05.422016 extensions: 00
9298 10:52:05.422098 checksum: fb
9299 10:52:05.422164
9300 10:52:05.428523 Manufacturer: IVO Model 57d Serial Number 0
9301 10:52:05.428606 Made week 0 of 2020
9302 10:52:05.431914 EDID version: 1.4
9303 10:52:05.431996 Digital display
9304 10:52:05.434806 6 bits per primary color channel
9305 10:52:05.438349 DisplayPort interface
9306 10:52:05.438430 Maximum image size: 31 cm x 17 cm
9307 10:52:05.441230 Gamma: 220%
9308 10:52:05.441312 Check DPMS levels
9309 10:52:05.448099 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 10:52:05.451338 First detailed timing is preferred timing
9311 10:52:05.454731 Established timings supported:
9312 10:52:05.454845 Standard timings supported:
9313 10:52:05.457671 Detailed timings
9314 10:52:05.461221 Hex of detail: 383680a07038204018303c0035ae10000019
9315 10:52:05.467768 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 10:52:05.470686 0780 0798 07c8 0820 hborder 0
9317 10:52:05.474481 0438 043b 0447 0458 vborder 0
9318 10:52:05.477549 -hsync -vsync
9319 10:52:05.477634 Did detailed timing
9320 10:52:05.484194 Hex of detail: 000000000000000000000000000000000000
9321 10:52:05.487568 Manufacturer-specified data, tag 0
9322 10:52:05.490759 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 10:52:05.493805 ASCII string: InfoVision
9324 10:52:05.497364 Hex of detail: 000000fe00523134304e574635205248200a
9325 10:52:05.500427 ASCII string: R140NWF5 RH
9326 10:52:05.500507 Checksum
9327 10:52:05.503948 Checksum: 0xfb (valid)
9328 10:52:05.507365 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 10:52:05.510475 DSI data_rate: 832800000 bps
9330 10:52:05.517463 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 10:52:05.520833 anx7625_parse_edid: pixelclock(138800).
9332 10:52:05.523448 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 10:52:05.527165 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 10:52:05.530407 anx7625_dsi_config: config dsi.
9335 10:52:05.536586 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 10:52:05.551135 anx7625_dsi_config: success to config DSI
9337 10:52:05.554210 anx7625_dp_start: MIPI phy setup OK.
9338 10:52:05.557849 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 10:52:05.560741 mtk_ddp_mode_set invalid vrefresh 60
9340 10:52:05.564247 main_disp_path_setup
9341 10:52:05.564362 ovl_layer_smi_id_en
9342 10:52:05.567110 ovl_layer_smi_id_en
9343 10:52:05.567215 ccorr_config
9344 10:52:05.567305 aal_config
9345 10:52:05.570616 gamma_config
9346 10:52:05.570718 postmask_config
9347 10:52:05.574185 dither_config
9348 10:52:05.577184 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 10:52:05.584082 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 10:52:05.587050 Root Device init finished in 551 msecs
9351 10:52:05.590222 CPU_CLUSTER: 0 init
9352 10:52:05.596846 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 10:52:05.603712 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 10:52:05.603797 APU_MBOX 0x190000b0 = 0x10001
9355 10:52:05.607087 APU_MBOX 0x190001b0 = 0x10001
9356 10:52:05.609926 APU_MBOX 0x190005b0 = 0x10001
9357 10:52:05.613346 APU_MBOX 0x190006b0 = 0x10001
9358 10:52:05.619960 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 10:52:05.629953 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9360 10:52:05.642230 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 10:52:05.649077 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 10:52:05.660529 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9363 10:52:05.669841 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 10:52:05.673282 CPU_CLUSTER: 0 init finished in 81 msecs
9365 10:52:05.676181 Devices initialized
9366 10:52:05.679546 Show all devs... After init.
9367 10:52:05.679631 Root Device: enabled 1
9368 10:52:05.682761 CPU_CLUSTER: 0: enabled 1
9369 10:52:05.686344 CPU: 00: enabled 1
9370 10:52:05.689363 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9371 10:52:05.692939 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 10:52:05.696054 ELOG: NV offset 0x57f000 size 0x1000
9373 10:52:05.702765 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9374 10:52:05.709369 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 10:52:05.712953 ELOG: Event(17) added with size 13 at 2023-06-05 10:52:05 UTC
9376 10:52:05.719367 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 10:52:05.723056 in-header: 03 48 00 00 2c 00 00 00
9378 10:52:05.732435 in-data: 16 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 10:52:05.739311 ELOG: Event(A1) added with size 10 at 2023-06-05 10:52:05 UTC
9380 10:52:05.746208 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 10:52:05.752150 ELOG: Event(A0) added with size 9 at 2023-06-05 10:52:06 UTC
9382 10:52:05.755749 elog_add_boot_reason: Logged dev mode boot
9383 10:52:05.761994 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9384 10:52:05.762081 Finalize devices...
9385 10:52:05.765119 Devices finalized
9386 10:52:05.768903 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 10:52:05.771852 Writing coreboot table at 0xffe64000
9388 10:52:05.775388 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 10:52:05.782036 1. 0000000040000000-00000000400fffff: RAM
9390 10:52:05.784990 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 10:52:05.788504 3. 000000004032b000-00000000545fffff: RAM
9392 10:52:05.791552 4. 0000000054600000-000000005465ffff: BL31
9393 10:52:05.795215 5. 0000000054660000-00000000ffe63fff: RAM
9394 10:52:05.801333 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 10:52:05.804978 7. 0000000100000000-000000023fffffff: RAM
9396 10:52:05.808058 Passing 5 GPIOs to payload:
9397 10:52:05.811724 NAME | PORT | POLARITY | VALUE
9398 10:52:05.817940 EC in RW | 0x000000aa | low | undefined
9399 10:52:05.821569 EC interrupt | 0x00000005 | low | undefined
9400 10:52:05.827737 TPM interrupt | 0x000000ab | high | undefined
9401 10:52:05.831161 SD card detect | 0x00000011 | high | undefined
9402 10:52:05.834798 speaker enable | 0x00000093 | high | undefined
9403 10:52:05.837746 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 10:52:05.841298 in-header: 03 f9 00 00 02 00 00 00
9405 10:52:05.844393 in-data: 02 00
9406 10:52:05.848090 ADC[4]: Raw value=896670 ID=7
9407 10:52:05.851165 ADC[3]: Raw value=212700 ID=1
9408 10:52:05.851248 RAM Code: 0x71
9409 10:52:05.854205 ADC[6]: Raw value=74352 ID=0
9410 10:52:05.857942 ADC[5]: Raw value=212700 ID=1
9411 10:52:05.858025 SKU Code: 0x1
9412 10:52:05.864458 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9413 10:52:05.864542 coreboot table: 964 bytes.
9414 10:52:05.867545 IMD ROOT 0. 0xfffff000 0x00001000
9415 10:52:05.870682 IMD SMALL 1. 0xffffe000 0x00001000
9416 10:52:05.874446 RO MCACHE 2. 0xffffc000 0x00001104
9417 10:52:05.877493 CONSOLE 3. 0xfff7c000 0x00080000
9418 10:52:05.880566 FMAP 4. 0xfff7b000 0x00000452
9419 10:52:05.884038 TIME STAMP 5. 0xfff7a000 0x00000910
9420 10:52:05.887501 VBOOT WORK 6. 0xfff66000 0x00014000
9421 10:52:05.890717 RAMOOPS 7. 0xffe66000 0x00100000
9422 10:52:05.894287 COREBOOT 8. 0xffe64000 0x00002000
9423 10:52:05.897172 IMD small region:
9424 10:52:05.900654 IMD ROOT 0. 0xffffec00 0x00000400
9425 10:52:05.903718 VPD 1. 0xffffeba0 0x0000004c
9426 10:52:05.906769 MMC STATUS 2. 0xffffeb80 0x00000004
9427 10:52:05.913488 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 10:52:05.913591 Probing TPM: done!
9429 10:52:05.920275 Connected to device vid:did:rid of 1ae0:0028:00
9430 10:52:05.927080 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9431 10:52:05.930049 Initialized TPM device CR50 revision 0
9432 10:52:05.934310 Checking cr50 for pending updates
9433 10:52:05.939169 Reading cr50 TPM mode
9434 10:52:05.947733 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 10:52:05.954274 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 10:52:05.995045 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9437 10:52:05.997866 Checking segment from ROM address 0x40100000
9438 10:52:06.001436 Checking segment from ROM address 0x4010001c
9439 10:52:06.008191 Loading segment from ROM address 0x40100000
9440 10:52:06.008275 code (compression=0)
9441 10:52:06.017973 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 10:52:06.024267 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 10:52:06.024364 it's not compressed!
9444 10:52:06.030963 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 10:52:06.037413 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 10:52:06.055086 Loading segment from ROM address 0x4010001c
9447 10:52:06.055168 Entry Point 0x80000000
9448 10:52:06.058290 Loaded segments
9449 10:52:06.061830 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 10:52:06.068648 Jumping to boot code at 0x80000000(0xffe64000)
9451 10:52:06.075188 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 10:52:06.081382 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 10:52:06.089287 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9454 10:52:06.092374 Checking segment from ROM address 0x40100000
9455 10:52:06.096090 Checking segment from ROM address 0x4010001c
9456 10:52:06.102680 Loading segment from ROM address 0x40100000
9457 10:52:06.102763 code (compression=1)
9458 10:52:06.109064 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 10:52:06.118658 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 10:52:06.118743 using LZMA
9461 10:52:06.127554 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 10:52:06.134289 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 10:52:06.138038 Loading segment from ROM address 0x4010001c
9464 10:52:06.138131 Entry Point 0x54601000
9465 10:52:06.141085 Loaded segments
9466 10:52:06.144334 NOTICE: MT8192 bl31_setup
9467 10:52:06.151500 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 10:52:06.154686 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 10:52:06.158147 WARNING: region 0:
9470 10:52:06.161867 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 10:52:06.161941 WARNING: region 1:
9472 10:52:06.167926 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 10:52:06.171261 WARNING: region 2:
9474 10:52:06.174715 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 10:52:06.178233 WARNING: region 3:
9476 10:52:06.181614 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 10:52:06.184455 WARNING: region 4:
9478 10:52:06.191357 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 10:52:06.191440 WARNING: region 5:
9480 10:52:06.194947 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 10:52:06.197983 WARNING: region 6:
9482 10:52:06.201064 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 10:52:06.204247 WARNING: region 7:
9484 10:52:06.207749 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 10:52:06.214196 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 10:52:06.217949 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 10:52:06.221244 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 10:52:06.227536 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 10:52:06.231026 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 10:52:06.237773 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 10:52:06.240801 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 10:52:06.244389 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 10:52:06.250937 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 10:52:06.254418 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 10:52:06.257616 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 10:52:06.264384 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 10:52:06.267446 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 10:52:06.274155 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 10:52:06.277729 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 10:52:06.280502 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 10:52:06.287101 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 10:52:06.290844 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 10:52:06.296993 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 10:52:06.300703 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 10:52:06.303730 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 10:52:06.310555 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 10:52:06.314119 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 10:52:06.316988 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 10:52:06.323538 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 10:52:06.326928 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 10:52:06.333339 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 10:52:06.336814 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 10:52:06.343808 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 10:52:06.346707 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 10:52:06.350330 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 10:52:06.356784 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 10:52:06.360447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 10:52:06.363791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 10:52:06.366665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 10:52:06.373478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 10:52:06.376581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 10:52:06.380100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 10:52:06.383557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 10:52:06.389896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 10:52:06.393523 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 10:52:06.396941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 10:52:06.399764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 10:52:06.406375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 10:52:06.410091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 10:52:06.413165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 10:52:06.419765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 10:52:06.423247 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 10:52:06.426311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 10:52:06.432885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 10:52:06.436368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 10:52:06.442713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 10:52:06.446232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 10:52:06.449429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 10:52:06.455857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 10:52:06.459520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 10:52:06.466333 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 10:52:06.469521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 10:52:06.475750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 10:52:06.479407 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 10:52:06.486030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 10:52:06.489074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 10:52:06.492603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 10:52:06.498949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 10:52:06.502687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 10:52:06.509290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 10:52:06.512424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 10:52:06.519077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 10:52:06.522174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 10:52:06.525854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 10:52:06.532325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 10:52:06.535322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 10:52:06.542251 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 10:52:06.545727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 10:52:06.552154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 10:52:06.555202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 10:52:06.561876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 10:52:06.565682 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 10:52:06.568518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 10:52:06.575203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 10:52:06.579001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 10:52:06.585174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 10:52:06.588770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 10:52:06.594931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 10:52:06.598495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 10:52:06.604918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 10:52:06.608536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 10:52:06.611437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 10:52:06.618289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 10:52:06.621480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 10:52:06.628180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 10:52:06.632066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 10:52:06.638422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 10:52:06.641259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 10:52:06.647966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 10:52:06.651823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 10:52:06.654843 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 10:52:06.661196 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 10:52:06.664653 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 10:52:06.668259 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 10:52:06.671064 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 10:52:06.677966 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 10:52:06.681121 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 10:52:06.688088 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 10:52:06.691134 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 10:52:06.694403 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 10:52:06.700536 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 10:52:06.704193 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 10:52:06.710882 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 10:52:06.714284 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 10:52:06.717199 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 10:52:06.724037 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 10:52:06.727204 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 10:52:06.734133 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 10:52:06.737141 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 10:52:06.740631 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 10:52:06.747706 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 10:52:06.750507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 10:52:06.754011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 10:52:06.760379 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 10:52:06.763801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 10:52:06.767091 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 10:52:06.770623 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 10:52:06.777014 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 10:52:06.780644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 10:52:06.783760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 10:52:06.790510 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 10:52:06.793646 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 10:52:06.800218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 10:52:06.803653 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 10:52:06.806994 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 10:52:06.813758 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 10:52:06.816689 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 10:52:06.823533 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 10:52:06.826655 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 10:52:06.830395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 10:52:06.836677 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 10:52:06.839847 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 10:52:06.843440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 10:52:06.849756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 10:52:06.853267 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 10:52:06.860464 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 10:52:06.863126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 10:52:06.866991 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 10:52:06.872992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 10:52:06.876540 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 10:52:06.883197 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 10:52:06.886219 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 10:52:06.889984 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 10:52:06.896183 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 10:52:06.899913 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 10:52:06.906546 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 10:52:06.909571 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 10:52:06.913171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 10:52:06.919399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 10:52:06.923035 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 10:52:06.929359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 10:52:06.933080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 10:52:06.936207 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 10:52:06.942409 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 10:52:06.946157 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 10:52:06.952781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 10:52:06.956126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 10:52:06.958847 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 10:52:06.965947 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 10:52:06.968770 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 10:52:06.975518 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 10:52:06.978981 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 10:52:06.982666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 10:52:06.989029 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 10:52:06.992048 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 10:52:06.998821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 10:52:07.001857 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 10:52:07.005354 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 10:52:07.011590 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 10:52:07.015127 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 10:52:07.021920 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 10:52:07.025013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 10:52:07.028666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 10:52:07.035195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 10:52:07.038435 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 10:52:07.044803 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 10:52:07.048512 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 10:52:07.051629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 10:52:07.058109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 10:52:07.061414 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 10:52:07.067855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 10:52:07.071434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 10:52:07.074935 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 10:52:07.081238 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 10:52:07.084660 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 10:52:07.091093 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 10:52:07.094513 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 10:52:07.101090 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 10:52:07.104159 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 10:52:07.107829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 10:52:07.113891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 10:52:07.117611 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 10:52:07.123725 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 10:52:07.127379 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 10:52:07.133709 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 10:52:07.136800 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 10:52:07.140408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 10:52:07.146816 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 10:52:07.150492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 10:52:07.156956 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 10:52:07.160033 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 10:52:07.166646 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 10:52:07.169814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 10:52:07.173497 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 10:52:07.179750 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 10:52:07.183256 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 10:52:07.189824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 10:52:07.193073 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 10:52:07.199812 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 10:52:07.202789 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 10:52:07.205904 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 10:52:07.212542 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 10:52:07.216200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 10:52:07.222313 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 10:52:07.225859 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 10:52:07.232640 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 10:52:07.235753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 10:52:07.238961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 10:52:07.245588 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 10:52:07.248717 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 10:52:07.255207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 10:52:07.258794 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 10:52:07.265521 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 10:52:07.268689 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 10:52:07.271760 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 10:52:07.275342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 10:52:07.278771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 10:52:07.285499 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 10:52:07.288680 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 10:52:07.294862 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 10:52:07.298233 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 10:52:07.301823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 10:52:07.308107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 10:52:07.311779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 10:52:07.314832 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 10:52:07.321593 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 10:52:07.324916 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 10:52:07.328196 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 10:52:07.334424 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 10:52:07.338065 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 10:52:07.344277 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 10:52:07.347901 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 10:52:07.350765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 10:52:07.358108 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 10:52:07.360931 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 10:52:07.367532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 10:52:07.371168 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 10:52:07.374271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 10:52:07.380988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 10:52:07.383961 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 10:52:07.387467 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 10:52:07.394221 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 10:52:07.397539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 10:52:07.400553 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 10:52:07.407421 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 10:52:07.410303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 10:52:07.417397 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 10:52:07.420495 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 10:52:07.424069 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 10:52:07.430122 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 10:52:07.433741 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 10:52:07.439929 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 10:52:07.443650 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 10:52:07.446761 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 10:52:07.449978 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 10:52:07.453495 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 10:52:07.460518 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 10:52:07.463209 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 10:52:07.466467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 10:52:07.470146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 10:52:07.476294 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 10:52:07.479508 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 10:52:07.483214 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 10:52:07.489783 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 10:52:07.492747 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 10:52:07.496061 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 10:52:07.503113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 10:52:07.505844 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 10:52:07.509210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 10:52:07.516351 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 10:52:07.519184 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 10:52:07.526149 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 10:52:07.529181 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 10:52:07.532333 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 10:52:07.539099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 10:52:07.542251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 10:52:07.549099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 10:52:07.552186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 10:52:07.558844 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 10:52:07.562004 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 10:52:07.568743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 10:52:07.572295 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 10:52:07.575315 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 10:52:07.582086 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 10:52:07.585326 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 10:52:07.591996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 10:52:07.595447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 10:52:07.598448 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 10:52:07.605143 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 10:52:07.608248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 10:52:07.615107 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 10:52:07.618064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 10:52:07.621647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 10:52:07.627970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 10:52:07.631578 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 10:52:07.637658 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 10:52:07.641203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 10:52:07.648025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 10:52:07.651081 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 10:52:07.654724 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 10:52:07.660858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 10:52:07.664236 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 10:52:07.670947 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 10:52:07.673985 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 10:52:07.680677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 10:52:07.684211 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 10:52:07.687402 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 10:52:07.694106 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 10:52:07.697227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 10:52:07.703576 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 10:52:07.707076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 10:52:07.710653 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 10:52:07.716921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 10:52:07.720618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 10:52:07.727085 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 10:52:07.730524 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 10:52:07.733627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 10:52:07.740544 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 10:52:07.743568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 10:52:07.750231 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 10:52:07.753298 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 10:52:07.760228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 10:52:07.763361 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 10:52:07.766298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 10:52:07.773381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 10:52:07.776453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 10:52:07.782729 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 10:52:07.786571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 10:52:07.793022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 10:52:07.796108 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 10:52:07.799296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 10:52:07.805871 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 10:52:07.809474 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 10:52:07.815790 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 10:52:07.819332 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 10:52:07.825568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 10:52:07.829155 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 10:52:07.832690 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 10:52:07.838786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 10:52:07.842136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 10:52:07.848993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 10:52:07.851916 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 10:52:07.858826 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 10:52:07.861875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 10:52:07.868745 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 10:52:07.871722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 10:52:07.875172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 10:52:07.881810 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 10:52:07.884925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 10:52:07.891850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 10:52:07.895357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 10:52:07.901523 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 10:52:07.905117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 10:52:07.908177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 10:52:07.915001 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 10:52:07.918357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 10:52:07.924701 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 10:52:07.928141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 10:52:07.934546 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 10:52:07.937730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 10:52:07.944503 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 10:52:07.947909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 10:52:07.950736 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 10:52:07.957358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 10:52:07.961074 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 10:52:07.967361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 10:52:07.970513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 10:52:07.977393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 10:52:07.980654 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 10:52:07.983622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 10:52:07.990529 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 10:52:07.993679 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 10:52:08.000448 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 10:52:08.003475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 10:52:08.010099 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 10:52:08.013922 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 10:52:08.020078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 10:52:08.023723 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 10:52:08.030186 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 10:52:08.033415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 10:52:08.036503 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 10:52:08.043023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 10:52:08.047055 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 10:52:08.053067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 10:52:08.056556 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 10:52:08.062766 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 10:52:08.066073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 10:52:08.069721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 10:52:08.076466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 10:52:08.079579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 10:52:08.086160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 10:52:08.089371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 10:52:08.095757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 10:52:08.099649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 10:52:08.105735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 10:52:08.109037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 10:52:08.115736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 10:52:08.118750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 10:52:08.125540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 10:52:08.129308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 10:52:08.135270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 10:52:08.138734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 10:52:08.145461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 10:52:08.148478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 10:52:08.155130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 10:52:08.158607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 10:52:08.164929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 10:52:08.167919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 10:52:08.174632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 10:52:08.177716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 10:52:08.184327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 10:52:08.187973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 10:52:08.194759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 10:52:08.197824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 10:52:08.204056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 10:52:08.207782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 10:52:08.214263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 10:52:08.217781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 10:52:08.223879 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 10:52:08.223999 INFO: [APUAPC] vio 0
9921 10:52:08.231122 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 10:52:08.234708 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 10:52:08.237722 INFO: [APUAPC] D0_APC_0: 0x400510
9924 10:52:08.241260 INFO: [APUAPC] D0_APC_1: 0x0
9925 10:52:08.244771 INFO: [APUAPC] D0_APC_2: 0x1540
9926 10:52:08.247640 INFO: [APUAPC] D0_APC_3: 0x0
9927 10:52:08.251032 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 10:52:08.254113 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 10:52:08.257924 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 10:52:08.261252 INFO: [APUAPC] D1_APC_3: 0x0
9931 10:52:08.263913 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 10:52:08.267407 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 10:52:08.270730 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 10:52:08.274025 INFO: [APUAPC] D2_APC_3: 0x0
9935 10:52:08.277425 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 10:52:08.280934 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 10:52:08.284366 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 10:52:08.287385 INFO: [APUAPC] D3_APC_3: 0x0
9939 10:52:08.291030 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 10:52:08.293922 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 10:52:08.297643 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 10:52:08.300734 INFO: [APUAPC] D4_APC_3: 0x0
9943 10:52:08.303883 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 10:52:08.306972 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 10:52:08.310122 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 10:52:08.313966 INFO: [APUAPC] D5_APC_3: 0x0
9947 10:52:08.316875 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 10:52:08.319826 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 10:52:08.323654 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 10:52:08.326600 INFO: [APUAPC] D6_APC_3: 0x0
9951 10:52:08.330197 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 10:52:08.333177 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 10:52:08.336817 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 10:52:08.336921 INFO: [APUAPC] D7_APC_3: 0x0
9955 10:52:08.343005 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 10:52:08.346496 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 10:52:08.349894 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 10:52:08.349999 INFO: [APUAPC] D8_APC_3: 0x0
9959 10:52:08.353401 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 10:52:08.356312 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 10:52:08.359874 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 10:52:08.362919 INFO: [APUAPC] D9_APC_3: 0x0
9963 10:52:08.366502 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 10:52:08.372740 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 10:52:08.376475 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 10:52:08.376587 INFO: [APUAPC] D10_APC_3: 0x0
9967 10:52:08.383057 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 10:52:08.386419 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 10:52:08.389425 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 10:52:08.389538 INFO: [APUAPC] D11_APC_3: 0x0
9971 10:52:08.396031 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 10:52:08.399020 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 10:52:08.402658 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 10:52:08.405733 INFO: [APUAPC] D12_APC_3: 0x0
9975 10:52:08.408826 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 10:52:08.412575 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 10:52:08.415849 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 10:52:08.418656 INFO: [APUAPC] D13_APC_3: 0x0
9979 10:52:08.422008 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 10:52:08.425375 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 10:52:08.428926 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 10:52:08.431763 INFO: [APUAPC] D14_APC_3: 0x0
9983 10:52:08.435403 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 10:52:08.438537 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 10:52:08.441663 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 10:52:08.445668 INFO: [APUAPC] D15_APC_3: 0x0
9987 10:52:08.448543 INFO: [APUAPC] APC_CON: 0x4
9988 10:52:08.448643 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 10:52:08.451506 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 10:52:08.454966 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 10:52:08.458400 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 10:52:08.461228 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 10:52:08.464768 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 10:52:08.468167 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 10:52:08.471458 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 10:52:08.474545 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 10:52:08.478250 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 10:52:08.481182 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 10:52:08.484715 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 10:52:08.484814 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 10:52:08.487883 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 10:52:08.491031 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 10:52:08.494266 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 10:52:08.497552 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 10:52:08.500862 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 10:52:08.504214 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 10:52:08.507792 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 10:52:08.510794 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 10:52:08.513980 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 10:52:08.517603 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 10:52:08.520670 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 10:52:08.524443 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 10:52:08.527464 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 10:52:08.527566 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 10:52:08.530482 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 10:52:08.534107 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 10:52:08.537179 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 10:52:08.540480 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 10:52:08.544075 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 10:52:08.547117 INFO: [NOCDAPC] APC_CON: 0x4
10021 10:52:08.550927 INFO: [APUAPC] set_apusys_apc done
10022 10:52:08.554104 INFO: [DEVAPC] devapc_init done
10023 10:52:08.557030 INFO: GICv3 without legacy support detected.
10024 10:52:08.560683 INFO: ARM GICv3 driver initialized in EL3
10025 10:52:08.567158 INFO: Maximum SPI INTID supported: 639
10026 10:52:08.570751 INFO: BL31: Initializing runtime services
10027 10:52:08.576682 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 10:52:08.576781 INFO: SPM: enable CPC mode
10029 10:52:08.583464 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 10:52:08.587061 INFO: BL31: Preparing for EL3 exit to normal world
10031 10:52:08.590066 INFO: Entry point address = 0x80000000
10032 10:52:08.593228 INFO: SPSR = 0x8
10033 10:52:08.599714
10034 10:52:08.599795
10035 10:52:08.599896
10036 10:52:08.602400 Starting depthcharge on Spherion...
10037 10:52:08.602497
10038 10:52:08.602591 Wipe memory regions:
10039 10:52:08.602667
10040 10:52:08.603328 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 10:52:08.603432 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 10:52:08.603516 Setting prompt string to ['asurada:']
10043 10:52:08.603594 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 10:52:08.606418 [0x00000040000000, 0x00000054600000)
10045 10:52:08.728431
10046 10:52:08.728561 [0x00000054660000, 0x00000080000000)
10047 10:52:08.988779
10048 10:52:08.988917 [0x000000821a7280, 0x000000ffe64000)
10049 10:52:09.734035
10050 10:52:09.734186 [0x00000100000000, 0x00000240000000)
10051 10:52:11.623980
10052 10:52:11.627637 Initializing XHCI USB controller at 0x11200000.
10053 10:52:12.666300
10054 10:52:12.669459 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 10:52:12.669553
10056 10:52:12.669618
10057 10:52:12.669682
10058 10:52:12.669963 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 10:52:12.770323 asurada: tftpboot 192.168.201.1 10590977/tftp-deploy-rfimzci5/kernel/image.itb 10590977/tftp-deploy-rfimzci5/kernel/cmdline
10061 10:52:12.770471 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 10:52:12.770553 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 10:52:12.774237 tftpboot 192.168.201.1 10590977/tftp-deploy-rfimzci5/kernel/image.itp-deploy-rfimzci5/kernel/cmdline
10064 10:52:12.774322
10065 10:52:12.774388 Waiting for link
10066 10:52:12.934699
10067 10:52:12.934853 R8152: Initializing
10068 10:52:12.934941
10069 10:52:12.938412 Version 6 (ocp_data = 5c30)
10070 10:52:12.938496
10071 10:52:12.941446 R8152: Done initializing
10072 10:52:12.941530
10073 10:52:12.941595 Adding net device
10074 10:52:14.987351
10075 10:52:14.987508 done.
10076 10:52:14.987578
10077 10:52:14.987666 MAC: 00:24:32:30:78:ff
10078 10:52:14.987728
10079 10:52:14.990450 Sending DHCP discover... done.
10080 10:52:14.990533
10081 10:52:18.091559 Waiting for reply... done.
10082 10:52:18.091731
10083 10:52:18.091831 Sending DHCP request... done.
10084 10:52:18.094891
10085 10:52:18.094973 Waiting for reply... done.
10086 10:52:18.095038
10087 10:52:18.097822 My ip is 192.168.201.21
10088 10:52:18.097932
10089 10:52:18.101477 The DHCP server ip is 192.168.201.1
10090 10:52:18.101559
10091 10:52:18.104581 TFTP server IP predefined by user: 192.168.201.1
10092 10:52:18.104663
10093 10:52:18.111448 Bootfile predefined by user: 10590977/tftp-deploy-rfimzci5/kernel/image.itb
10094 10:52:18.111530
10095 10:52:18.114441 Sending tftp read request... done.
10096 10:52:18.114522
10097 10:52:18.118083 Waiting for the transfer...
10098 10:52:18.118166
10099 10:52:18.666555 00000000 ################################################################
10100 10:52:18.666691
10101 10:52:19.199429 00080000 ################################################################
10102 10:52:19.199566
10103 10:52:19.744224 00100000 ################################################################
10104 10:52:19.744361
10105 10:52:20.297591 00180000 ################################################################
10106 10:52:20.297736
10107 10:52:20.845277 00200000 ################################################################
10108 10:52:20.845423
10109 10:52:21.378195 00280000 ################################################################
10110 10:52:21.378344
10111 10:52:21.931634 00300000 ################################################################
10112 10:52:21.931782
10113 10:52:22.463100 00380000 ################################################################
10114 10:52:22.463286
10115 10:52:23.001714 00400000 ################################################################
10116 10:52:23.001889
10117 10:52:23.543972 00480000 ################################################################
10118 10:52:23.544137
10119 10:52:24.087367 00500000 ################################################################
10120 10:52:24.087505
10121 10:52:24.636038 00580000 ################################################################
10122 10:52:24.636248
10123 10:52:25.179114 00600000 ################################################################
10124 10:52:25.179248
10125 10:52:25.709699 00680000 ################################################################
10126 10:52:25.709868
10127 10:52:26.252859 00700000 ################################################################
10128 10:52:26.253009
10129 10:52:26.800202 00780000 ################################################################
10130 10:52:26.800424
10131 10:52:27.346149 00800000 ################################################################
10132 10:52:27.346297
10133 10:52:27.903784 00880000 ################################################################
10134 10:52:27.903945
10135 10:52:28.435596 00900000 ################################################################
10136 10:52:28.435757
10137 10:52:28.966177 00980000 ################################################################
10138 10:52:28.966309
10139 10:52:29.513667 00a00000 ################################################################
10140 10:52:29.513804
10141 10:52:30.042078 00a80000 ################################################################
10142 10:52:30.042225
10143 10:52:30.590102 00b00000 ################################################################
10144 10:52:30.590244
10145 10:52:31.137827 00b80000 ################################################################
10146 10:52:31.138013
10147 10:52:31.670635 00c00000 ################################################################
10148 10:52:31.670800
10149 10:52:32.198412 00c80000 ################################################################
10150 10:52:32.198553
10151 10:52:32.728358 00d00000 ################################################################
10152 10:52:32.728497
10153 10:52:33.265334 00d80000 ################################################################
10154 10:52:33.265499
10155 10:52:33.804299 00e00000 ################################################################
10156 10:52:33.804470
10157 10:52:34.350559 00e80000 ################################################################
10158 10:52:34.350704
10159 10:52:34.895703 00f00000 ################################################################
10160 10:52:34.895843
10161 10:52:35.477850 00f80000 ################################################################
10162 10:52:35.478136
10163 10:52:36.166484 01000000 ################################################################
10164 10:52:36.166624
10165 10:52:36.764285 01080000 ################################################################
10166 10:52:36.764837
10167 10:52:37.407546 01100000 ################################################################
10168 10:52:37.408364
10169 10:52:37.989598 01180000 ################################################################
10170 10:52:37.989768
10171 10:52:38.542452 01200000 ################################################################
10172 10:52:38.542668
10173 10:52:39.163240 01280000 ################################################################
10174 10:52:39.163377
10175 10:52:39.710267 01300000 ################################################################
10176 10:52:39.710430
10177 10:52:40.251369 01380000 ################################################################
10178 10:52:40.251505
10179 10:52:40.792131 01400000 ################################################################
10180 10:52:40.792299
10181 10:52:41.382736 01480000 ################################################################
10182 10:52:41.382903
10183 10:52:42.030953 01500000 ################################################################
10184 10:52:42.031467
10185 10:52:42.588576 01580000 ################################################################
10186 10:52:42.588747
10187 10:52:43.292220 01600000 ################################################################
10188 10:52:43.292796
10189 10:52:43.980099 01680000 ################################################################
10190 10:52:43.980600
10191 10:52:44.667538 01700000 ################################################################
10192 10:52:44.667675
10193 10:52:45.315725 01780000 ################################################################
10194 10:52:45.316232
10195 10:52:46.033354 01800000 ################################################################
10196 10:52:46.033939
10197 10:52:46.701355 01880000 ################################################################
10198 10:52:46.701924
10199 10:52:47.398802 01900000 ################################################################
10200 10:52:47.399333
10201 10:52:48.097686 01980000 ################################################################
10202 10:52:48.098204
10203 10:52:48.804713 01a00000 ################################################################
10204 10:52:48.805240
10205 10:52:49.506350 01a80000 ################################################################
10206 10:52:49.506898
10207 10:52:50.186546 01b00000 ################################################################
10208 10:52:50.187180
10209 10:52:50.871746 01b80000 ################################################################
10210 10:52:50.872246
10211 10:52:51.517894 01c00000 ################################################################
10212 10:52:51.518068
10213 10:52:52.089395 01c80000 ################################################################
10214 10:52:52.089534
10215 10:52:52.696607 01d00000 ################################################################
10216 10:52:52.696775
10217 10:52:53.242391 01d80000 ################################################################
10218 10:52:53.242543
10219 10:52:53.816224 01e00000 ################################################################
10220 10:52:53.816376
10221 10:52:54.372876 01e80000 ################################################################
10222 10:52:54.373028
10223 10:52:54.939581 01f00000 ################################################################
10224 10:52:54.939720
10225 10:52:55.515535 01f80000 ################################################################
10226 10:52:55.515675
10227 10:52:56.073529 02000000 ################################################################
10228 10:52:56.073669
10229 10:52:56.645759 02080000 ################################################################
10230 10:52:56.645916
10231 10:52:57.216834 02100000 ################################################################
10232 10:52:57.216995
10233 10:52:57.773126 02180000 ################################################################
10234 10:52:57.773264
10235 10:52:58.340033 02200000 ################################################################
10236 10:52:58.340174
10237 10:52:58.893075 02280000 ################################################################
10238 10:52:58.893208
10239 10:52:59.453418 02300000 ################################################################
10240 10:52:59.453562
10241 10:53:00.018059 02380000 ################################################################
10242 10:53:00.018203
10243 10:53:00.592398 02400000 ################################################################
10244 10:53:00.592536
10245 10:53:01.179661 02480000 ################################################################
10246 10:53:01.179799
10247 10:53:01.749529 02500000 ################################################################
10248 10:53:01.749669
10249 10:53:02.317201 02580000 ################################################################
10250 10:53:02.317363
10251 10:53:02.893750 02600000 ################################################################
10252 10:53:02.893889
10253 10:53:03.425459 02680000 ################################################################
10254 10:53:03.425624
10255 10:53:04.046854 02700000 ################################################################
10256 10:53:04.047259
10257 10:53:04.624949 02780000 ################################################################
10258 10:53:04.625088
10259 10:53:05.174747 02800000 ################################################################
10260 10:53:05.174919
10261 10:53:05.738776 02880000 ################################################################
10262 10:53:05.738950
10263 10:53:06.325378 02900000 ################################################################
10264 10:53:06.325751
10265 10:53:06.910338 02980000 ################################################################
10266 10:53:06.910481
10267 10:53:07.484632 02a00000 ################################################################
10268 10:53:07.485151
10269 10:53:08.076588 02a80000 ################################################################
10270 10:53:08.076727
10271 10:53:08.647783 02b00000 ################################################################
10272 10:53:08.648164
10273 10:53:09.214422 02b80000 ################################################################
10274 10:53:09.214557
10275 10:53:09.788728 02c00000 ################################################################
10276 10:53:09.788893
10277 10:53:10.351973 02c80000 ################################################################
10278 10:53:10.352116
10279 10:53:10.924234 02d00000 ################################################################
10280 10:53:10.924384
10281 10:53:11.495034 02d80000 ################################################################
10282 10:53:11.495183
10283 10:53:12.071901 02e00000 ################################################################
10284 10:53:12.072039
10285 10:53:12.638853 02e80000 ################################################################
10286 10:53:12.639038
10287 10:53:13.208340 02f00000 ################################################################
10288 10:53:13.208476
10289 10:53:13.788920 02f80000 ################################################################
10290 10:53:13.789063
10291 10:53:14.951481 03000000 ################################################################
10292 10:53:14.952200
10293 10:53:15.070935 03080000 ################################################################
10294 10:53:15.071075
10295 10:53:15.641075 03100000 ################################################################
10296 10:53:15.641218
10297 10:53:16.226525 03180000 ################################################################
10298 10:53:16.226656
10299 10:53:16.807381 03200000 ################################################################
10300 10:53:16.807528
10301 10:53:17.387767 03280000 ################################################################
10302 10:53:17.387911
10303 10:53:17.967262 03300000 ################################################################
10304 10:53:17.967408
10305 10:53:18.542986 03380000 ################################################################
10306 10:53:18.543126
10307 10:53:19.262927 03400000 ################################################################
10308 10:53:19.263692
10309 10:53:19.715489 03480000 ################################################################
10310 10:53:19.715667
10311 10:53:20.326006 03500000 ################################################################
10312 10:53:20.326502
10313 10:53:21.016056 03580000 ################################################################
10314 10:53:21.016587
10315 10:53:21.680792 03600000 ################################################################
10316 10:53:21.680951
10317 10:53:22.308647 03680000 ################################################################
10318 10:53:22.308789
10319 10:53:22.864598 03700000 ################################################################
10320 10:53:22.864769
10321 10:53:23.388063 03780000 ################################################################
10322 10:53:23.388228
10323 10:53:23.908409 03800000 ################################################################
10324 10:53:23.908555
10325 10:53:24.444887 03880000 ################################################################
10326 10:53:24.445052
10327 10:53:24.997164 03900000 ################################################################
10328 10:53:24.997308
10329 10:53:25.563858 03980000 ################################################################
10330 10:53:25.564021
10331 10:53:26.112166 03a00000 ################################################################
10332 10:53:26.112300
10333 10:53:26.648325 03a80000 ################################################################
10334 10:53:26.648459
10335 10:53:27.186764 03b00000 ################################################################
10336 10:53:27.186920
10337 10:53:27.720774 03b80000 ################################################################
10338 10:53:27.720938
10339 10:53:28.262160 03c00000 ################################################################
10340 10:53:28.262290
10341 10:53:28.800755 03c80000 ################################################################
10342 10:53:28.800898
10343 10:53:29.360492 03d00000 ################################################################
10344 10:53:29.360651
10345 10:53:29.918863 03d80000 ################################################################
10346 10:53:29.918995
10347 10:53:30.515831 03e00000 ################################################################
10348 10:53:30.516396
10349 10:53:31.080770 03e80000 ################################################################
10350 10:53:31.080933
10351 10:53:31.514078 03f00000 #################################################### done.
10352 10:53:31.514214
10353 10:53:31.517731 The bootfile was 66479634 bytes long.
10354 10:53:31.517814
10355 10:53:31.521065 Sending tftp read request... done.
10356 10:53:31.521151
10357 10:53:31.523746 Waiting for the transfer...
10358 10:53:31.523857
10359 10:53:31.523949 00000000 # done.
10360 10:53:31.524041
10361 10:53:31.534130 Command line loaded dynamically from TFTP file: 10590977/tftp-deploy-rfimzci5/kernel/cmdline
10362 10:53:31.534253
10363 10:53:31.543943 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10364 10:53:31.544031
10365 10:53:31.547138 Loading FIT.
10366 10:53:31.547219
10367 10:53:31.550079 Image ramdisk-1 has 56348737 bytes.
10368 10:53:31.550187
10369 10:53:31.550280 Image fdt-1 has 46924 bytes.
10370 10:53:31.550369
10371 10:53:31.553330 Image kernel-1 has 10081937 bytes.
10372 10:53:31.553441
10373 10:53:31.563646 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10374 10:53:31.563730
10375 10:53:31.580370 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10376 10:53:31.580484
10377 10:53:31.586782 Choosing best match conf-1 for compat google,spherion-rev2.
10378 10:53:31.590536
10379 10:53:31.595099 Connected to device vid:did:rid of 1ae0:0028:00
10380 10:53:31.601993
10381 10:53:31.605438 tpm_get_response: command 0x17b, return code 0x0
10382 10:53:31.605528
10383 10:53:31.608894 ec_init: CrosEC protocol v3 supported (256, 248)
10384 10:53:31.612765
10385 10:53:31.616093 tpm_cleanup: add release locality here.
10386 10:53:31.616174
10387 10:53:31.616239 Shutting down all USB controllers.
10388 10:53:31.619465
10389 10:53:31.619546 Removing current net device
10390 10:53:31.619610
10391 10:53:31.625891 Exiting depthcharge with code 4 at timestamp: 112346163
10392 10:53:31.625972
10393 10:53:31.629038 LZMA decompressing kernel-1 to 0x821a6718
10394 10:53:31.629119
10395 10:53:31.632444 LZMA decompressing kernel-1 to 0x40000000
10396 10:53:32.898553
10397 10:53:32.898692 jumping to kernel
10398 10:53:32.899454 end: 2.2.4 bootloader-commands (duration 00:01:24) [common]
10399 10:53:32.899591 start: 2.2.5 auto-login-action (timeout 00:03:01) [common]
10400 10:53:32.899710 Setting prompt string to ['Linux version [0-9]']
10401 10:53:32.899824 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10402 10:53:32.899935 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10403 10:53:32.981084
10404 10:53:32.984424 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10405 10:53:32.987868 start: 2.2.5.1 login-action (timeout 00:03:01) [common]
10406 10:53:32.987992 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10407 10:53:32.988123 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10408 10:53:32.988230 Using line separator: #'\n'#
10409 10:53:32.988330 No login prompt set.
10410 10:53:32.988420 Parsing kernel messages
10411 10:53:32.988493 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10412 10:53:32.988679 [login-action] Waiting for messages, (timeout 00:03:01)
10413 10:53:33.007431 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10414 10:53:33.010666 [ 0.000000] random: crng init done
10415 10:53:33.017207 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10416 10:53:33.020538 [ 0.000000] efi: UEFI not found.
10417 10:53:33.027493 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10418 10:53:33.033611 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10419 10:53:33.043464 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10420 10:53:33.053599 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10421 10:53:33.060536 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10422 10:53:33.067039 [ 0.000000] printk: bootconsole [mtk8250] enabled
10423 10:53:33.073382 [ 0.000000] NUMA: No NUMA configuration found
10424 10:53:33.079997 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10425 10:53:33.083347 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10426 10:53:33.086723 [ 0.000000] Zone ranges:
10427 10:53:33.093351 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10428 10:53:33.096583 [ 0.000000] DMA32 empty
10429 10:53:33.102712 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10430 10:53:33.106732 [ 0.000000] Movable zone start for each node
10431 10:53:33.109979 [ 0.000000] Early memory node ranges
10432 10:53:33.116697 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10433 10:53:33.123006 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10434 10:53:33.129580 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10435 10:53:33.136397 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10436 10:53:33.142749 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10437 10:53:33.149360 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10438 10:53:33.205147 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10439 10:53:33.211839 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10440 10:53:33.218368 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10441 10:53:33.221630 [ 0.000000] psci: probing for conduit method from DT.
10442 10:53:33.228379 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10443 10:53:33.231528 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10444 10:53:33.238401 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10445 10:53:33.241325 [ 0.000000] psci: SMC Calling Convention v1.2
10446 10:53:33.247714 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10447 10:53:33.251633 [ 0.000000] Detected VIPT I-cache on CPU0
10448 10:53:33.257692 [ 0.000000] CPU features: detected: GIC system register CPU interface
10449 10:53:33.265013 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10450 10:53:33.271082 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10451 10:53:33.277736 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10452 10:53:33.287653 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10453 10:53:33.294278 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10454 10:53:33.297611 [ 0.000000] alternatives: applying boot alternatives
10455 10:53:33.304222 [ 0.000000] Fallback order for Node 0: 0
10456 10:53:33.310407 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10457 10:53:33.313749 [ 0.000000] Policy zone: Normal
10458 10:53:33.323603 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10459 10:53:33.337075 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10460 10:53:33.346974 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10461 10:53:33.356915 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10462 10:53:33.363544 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10463 10:53:33.366636 <6>[ 0.000000] software IO TLB: area num 8.
10464 10:53:33.423542 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10465 10:53:33.572620 <6>[ 0.000000] Memory: 7917912K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434856K reserved, 32768K cma-reserved)
10466 10:53:33.579019 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10467 10:53:33.585703 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10468 10:53:33.589175 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10469 10:53:33.595543 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10470 10:53:33.601814 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10471 10:53:33.605468 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10472 10:53:33.615385 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10473 10:53:33.621425 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10474 10:53:33.627939 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10475 10:53:33.634539 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10476 10:53:33.637841 <6>[ 0.000000] GICv3: 608 SPIs implemented
10477 10:53:33.641662 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10478 10:53:33.647927 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10479 10:53:33.651597 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10480 10:53:33.657888 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10481 10:53:33.671068 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10482 10:53:33.684000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10483 10:53:33.690751 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10484 10:53:33.698764 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10485 10:53:33.711913 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10486 10:53:33.718933 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10487 10:53:33.725520 <6>[ 0.009169] Console: colour dummy device 80x25
10488 10:53:33.735443 <6>[ 0.013895] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10489 10:53:33.742022 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10490 10:53:33.745193 <6>[ 0.029306] LSM: Security Framework initializing
10491 10:53:33.751677 <6>[ 0.034247] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10492 10:53:33.761387 <6>[ 0.042028] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10493 10:53:33.771232 <6>[ 0.051460] cblist_init_generic: Setting adjustable number of callback queues.
10494 10:53:33.777968 <6>[ 0.058960] cblist_init_generic: Setting shift to 3 and lim to 1.
10495 10:53:33.781179 <6>[ 0.065297] cblist_init_generic: Setting shift to 3 and lim to 1.
10496 10:53:33.788125 <6>[ 0.071705] rcu: Hierarchical SRCU implementation.
10497 10:53:33.794344 <6>[ 0.076719] rcu: Max phase no-delay instances is 1000.
10498 10:53:33.801054 <6>[ 0.083735] EFI services will not be available.
10499 10:53:33.804291 <6>[ 0.088709] smp: Bringing up secondary CPUs ...
10500 10:53:33.812323 <6>[ 0.093761] Detected VIPT I-cache on CPU1
10501 10:53:33.819087 <6>[ 0.093833] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10502 10:53:33.825388 <6>[ 0.093865] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10503 10:53:33.828619 <6>[ 0.094205] Detected VIPT I-cache on CPU2
10504 10:53:33.835806 <6>[ 0.094259] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10505 10:53:33.845658 <6>[ 0.094279] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10506 10:53:33.848730 <6>[ 0.094541] Detected VIPT I-cache on CPU3
10507 10:53:33.855153 <6>[ 0.094588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10508 10:53:33.861902 <6>[ 0.094603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10509 10:53:33.868298 <6>[ 0.094908] CPU features: detected: Spectre-v4
10510 10:53:33.871738 <6>[ 0.094914] CPU features: detected: Spectre-BHB
10511 10:53:33.874976 <6>[ 0.094920] Detected PIPT I-cache on CPU4
10512 10:53:33.881449 <6>[ 0.094978] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10513 10:53:33.888004 <6>[ 0.094994] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10514 10:53:33.894493 <6>[ 0.095285] Detected PIPT I-cache on CPU5
10515 10:53:33.901417 <6>[ 0.095350] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10516 10:53:33.907567 <6>[ 0.095367] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10517 10:53:33.910719 <6>[ 0.095651] Detected PIPT I-cache on CPU6
10518 10:53:33.921336 <6>[ 0.095716] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10519 10:53:33.927254 <6>[ 0.095732] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10520 10:53:33.931106 <6>[ 0.096033] Detected PIPT I-cache on CPU7
10521 10:53:33.937645 <6>[ 0.096097] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10522 10:53:33.944073 <6>[ 0.096113] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10523 10:53:33.947327 <6>[ 0.096159] smp: Brought up 1 node, 8 CPUs
10524 10:53:33.953554 <6>[ 0.237394] SMP: Total of 8 processors activated.
10525 10:53:33.960273 <6>[ 0.242345] CPU features: detected: 32-bit EL0 Support
10526 10:53:33.966699 <6>[ 0.247708] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10527 10:53:33.973204 <6>[ 0.256508] CPU features: detected: Common not Private translations
10528 10:53:33.980338 <6>[ 0.262984] CPU features: detected: CRC32 instructions
10529 10:53:33.986981 <6>[ 0.268335] CPU features: detected: RCpc load-acquire (LDAPR)
10530 10:53:33.989623 <6>[ 0.274294] CPU features: detected: LSE atomic instructions
10531 10:53:33.996381 <6>[ 0.280075] CPU features: detected: Privileged Access Never
10532 10:53:34.003494 <6>[ 0.285855] CPU features: detected: RAS Extension Support
10533 10:53:34.009864 <6>[ 0.291463] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10534 10:53:34.013143 <6>[ 0.298728] CPU: All CPU(s) started at EL2
10535 10:53:34.019731 <6>[ 0.303044] alternatives: applying system-wide alternatives
10536 10:53:34.029632 <6>[ 0.313710] devtmpfs: initialized
10537 10:53:34.045604 <6>[ 0.322806] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10538 10:53:34.052087 <6>[ 0.332767] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10539 10:53:34.058429 <6>[ 0.341014] pinctrl core: initialized pinctrl subsystem
10540 10:53:34.061807 <6>[ 0.347673] DMI not present or invalid.
10541 10:53:34.069051 <6>[ 0.352078] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10542 10:53:34.078742 <6>[ 0.358958] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10543 10:53:34.085082 <6>[ 0.366539] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10544 10:53:34.095022 <6>[ 0.374769] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10545 10:53:34.098447 <6>[ 0.383012] audit: initializing netlink subsys (disabled)
10546 10:53:34.108315 <5>[ 0.388708] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10547 10:53:34.114795 <6>[ 0.389417] thermal_sys: Registered thermal governor 'step_wise'
10548 10:53:34.121542 <6>[ 0.396676] thermal_sys: Registered thermal governor 'power_allocator'
10549 10:53:34.124695 <6>[ 0.402932] cpuidle: using governor menu
10550 10:53:34.131009 <6>[ 0.413891] NET: Registered PF_QIPCRTR protocol family
10551 10:53:34.137342 <6>[ 0.419370] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10552 10:53:34.144289 <6>[ 0.426471] ASID allocator initialised with 32768 entries
10553 10:53:34.147545 <6>[ 0.433041] Serial: AMBA PL011 UART driver
10554 10:53:34.158105 <4>[ 0.441707] Trying to register duplicate clock ID: 134
10555 10:53:34.211936 <6>[ 0.499019] KASLR enabled
10556 10:53:34.226509 <6>[ 0.506801] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10557 10:53:34.232993 <6>[ 0.513818] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10558 10:53:34.239697 <6>[ 0.520308] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10559 10:53:34.245901 <6>[ 0.527313] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10560 10:53:34.252332 <6>[ 0.533800] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10561 10:53:34.259379 <6>[ 0.540805] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10562 10:53:34.265901 <6>[ 0.547292] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10563 10:53:34.272442 <6>[ 0.554293] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10564 10:53:34.275614 <6>[ 0.561704] ACPI: Interpreter disabled.
10565 10:53:34.284624 <6>[ 0.568086] iommu: Default domain type: Translated
10566 10:53:34.291058 <6>[ 0.573200] iommu: DMA domain TLB invalidation policy: strict mode
10567 10:53:34.294115 <5>[ 0.579854] SCSI subsystem initialized
10568 10:53:34.300899 <6>[ 0.584017] usbcore: registered new interface driver usbfs
10569 10:53:34.307697 <6>[ 0.589749] usbcore: registered new interface driver hub
10570 10:53:34.310693 <6>[ 0.595299] usbcore: registered new device driver usb
10571 10:53:34.317416 <6>[ 0.601381] pps_core: LinuxPPS API ver. 1 registered
10572 10:53:34.327573 <6>[ 0.606574] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10573 10:53:34.330573 <6>[ 0.615922] PTP clock support registered
10574 10:53:34.333694 <6>[ 0.620163] EDAC MC: Ver: 3.0.0
10575 10:53:34.341435 <6>[ 0.625308] FPGA manager framework
10576 10:53:34.348190 <6>[ 0.628988] Advanced Linux Sound Architecture Driver Initialized.
10577 10:53:34.351342 <6>[ 0.635755] vgaarb: loaded
10578 10:53:34.357441 <6>[ 0.638921] clocksource: Switched to clocksource arch_sys_counter
10579 10:53:34.361164 <5>[ 0.645339] VFS: Disk quotas dquot_6.6.0
10580 10:53:34.367446 <6>[ 0.649522] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10581 10:53:34.370727 <6>[ 0.656710] pnp: PnP ACPI: disabled
10582 10:53:34.379562 <6>[ 0.663379] NET: Registered PF_INET protocol family
10583 10:53:34.389138 <6>[ 0.668964] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10584 10:53:34.400592 <6>[ 0.681251] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10585 10:53:34.410642 <6>[ 0.690064] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10586 10:53:34.417133 <6>[ 0.698036] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10587 10:53:34.426965 <6>[ 0.706736] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10588 10:53:34.433438 <6>[ 0.716490] TCP: Hash tables configured (established 65536 bind 65536)
10589 10:53:34.440156 <6>[ 0.723347] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10590 10:53:34.449892 <6>[ 0.730545] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10591 10:53:34.456729 <6>[ 0.738244] NET: Registered PF_UNIX/PF_LOCAL protocol family
10592 10:53:34.463426 <6>[ 0.744409] RPC: Registered named UNIX socket transport module.
10593 10:53:34.466626 <6>[ 0.750566] RPC: Registered udp transport module.
10594 10:53:34.472992 <6>[ 0.755499] RPC: Registered tcp transport module.
10595 10:53:34.479464 <6>[ 0.760431] RPC: Registered tcp NFSv4.1 backchannel transport module.
10596 10:53:34.483126 <6>[ 0.767101] PCI: CLS 0 bytes, default 64
10597 10:53:34.486524 <6>[ 0.771452] Unpacking initramfs...
10598 10:53:34.502996 <6>[ 0.783570] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10599 10:53:34.513489 <6>[ 0.792218] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10600 10:53:34.516584 <6>[ 0.801050] kvm [1]: IPA Size Limit: 40 bits
10601 10:53:34.523459 <6>[ 0.805579] kvm [1]: GICv3: no GICV resource entry
10602 10:53:34.526803 <6>[ 0.810601] kvm [1]: disabling GICv2 emulation
10603 10:53:34.533059 <6>[ 0.815289] kvm [1]: GIC system register CPU interface enabled
10604 10:53:34.536479 <6>[ 0.821466] kvm [1]: vgic interrupt IRQ18
10605 10:53:34.542947 <6>[ 0.825833] kvm [1]: VHE mode initialized successfully
10606 10:53:34.549489 <5>[ 0.832336] Initialise system trusted keyrings
10607 10:53:34.555861 <6>[ 0.837163] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10608 10:53:34.564321 <6>[ 0.847161] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10609 10:53:34.570524 <5>[ 0.853568] NFS: Registering the id_resolver key type
10610 10:53:34.573693 <5>[ 0.858872] Key type id_resolver registered
10611 10:53:34.580091 <5>[ 0.863284] Key type id_legacy registered
10612 10:53:34.587200 <6>[ 0.867566] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10613 10:53:34.593842 <6>[ 0.874489] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10614 10:53:34.599531 <6>[ 0.882246] 9p: Installing v9fs 9p2000 file system support
10615 10:53:34.637066 <5>[ 0.920485] Key type asymmetric registered
10616 10:53:34.640262 <5>[ 0.924820] Asymmetric key parser 'x509' registered
10617 10:53:34.650243 <6>[ 0.929955] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10618 10:53:34.653456 <6>[ 0.937571] io scheduler mq-deadline registered
10619 10:53:34.657256 <6>[ 0.942332] io scheduler kyber registered
10620 10:53:34.675605 <6>[ 0.959048] EINJ: ACPI disabled.
10621 10:53:34.707925 <4>[ 0.984705] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 10:53:34.717913 <4>[ 0.995327] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10623 10:53:34.732379 <6>[ 1.016196] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10624 10:53:34.740900 <6>[ 1.024277] printk: console [ttyS0] disabled
10625 10:53:34.768555 <6>[ 1.048924] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10626 10:53:34.775278 <6>[ 1.058422] printk: console [ttyS0] enabled
10627 10:53:34.778370 <6>[ 1.058422] printk: console [ttyS0] enabled
10628 10:53:34.785070 <6>[ 1.067318] printk: bootconsole [mtk8250] disabled
10629 10:53:34.788195 <6>[ 1.067318] printk: bootconsole [mtk8250] disabled
10630 10:53:34.794564 <6>[ 1.078550] SuperH (H)SCI(F) driver initialized
10631 10:53:34.798517 <6>[ 1.083828] msm_serial: driver initialized
10632 10:53:34.812136 <6>[ 1.092736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10633 10:53:34.822383 <6>[ 1.101283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10634 10:53:34.829000 <6>[ 1.109825] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10635 10:53:34.838678 <6>[ 1.118454] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10636 10:53:34.848547 <6>[ 1.127159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10637 10:53:34.855172 <6>[ 1.135873] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10638 10:53:34.864965 <6>[ 1.144421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10639 10:53:34.871700 <6>[ 1.153225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10640 10:53:34.881480 <6>[ 1.161774] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10641 10:53:34.893186 <6>[ 1.177335] loop: module loaded
10642 10:53:34.900162 <6>[ 1.183086] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10643 10:53:34.922766 <4>[ 1.206747] mtk-pmic-keys: Failed to locate of_node [id: -1]
10644 10:53:34.929839 <6>[ 1.213746] megasas: 07.719.03.00-rc1
10645 10:53:34.939799 <6>[ 1.223799] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10646 10:53:34.946468 <6>[ 1.230328] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10647 10:53:34.963326 <6>[ 1.246884] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10648 10:53:35.023348 <6>[ 1.300686] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10649 10:53:36.886724 <6>[ 3.170620] Freeing initrd memory: 55024K
10650 10:53:36.896387 <6>[ 3.180680] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10651 10:53:36.907460 <6>[ 3.191627] tun: Universal TUN/TAP device driver, 1.6
10652 10:53:36.910898 <6>[ 3.197672] thunder_xcv, ver 1.0
10653 10:53:36.914385 <6>[ 3.201173] thunder_bgx, ver 1.0
10654 10:53:36.917408 <6>[ 3.204668] nicpf, ver 1.0
10655 10:53:36.927856 <6>[ 3.208671] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10656 10:53:36.931202 <6>[ 3.216147] hns3: Copyright (c) 2017 Huawei Corporation.
10657 10:53:36.938038 <6>[ 3.221732] hclge is initializing
10658 10:53:36.941368 <6>[ 3.225313] e1000: Intel(R) PRO/1000 Network Driver
10659 10:53:36.947862 <6>[ 3.230443] e1000: Copyright (c) 1999-2006 Intel Corporation.
10660 10:53:36.951088 <6>[ 3.236457] e1000e: Intel(R) PRO/1000 Network Driver
10661 10:53:36.957571 <6>[ 3.241673] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10662 10:53:36.964310 <6>[ 3.247857] igb: Intel(R) Gigabit Ethernet Network Driver
10663 10:53:36.970911 <6>[ 3.253507] igb: Copyright (c) 2007-2014 Intel Corporation.
10664 10:53:36.977685 <6>[ 3.259342] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10665 10:53:36.984360 <6>[ 3.265859] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10666 10:53:36.987062 <6>[ 3.272320] sky2: driver version 1.30
10667 10:53:36.994195 <6>[ 3.277293] VFIO - User Level meta-driver version: 0.3
10668 10:53:37.001328 <6>[ 3.285434] usbcore: registered new interface driver usb-storage
10669 10:53:37.007984 <6>[ 3.291874] usbcore: registered new device driver onboard-usb-hub
10670 10:53:37.016584 <6>[ 3.300905] mt6397-rtc mt6359-rtc: registered as rtc0
10671 10:53:37.026525 <6>[ 3.306364] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:53:37 UTC (1685962417)
10672 10:53:37.029731 <6>[ 3.315948] i2c_dev: i2c /dev entries driver
10673 10:53:37.046282 <6>[ 3.327517] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10674 10:53:37.053354 <6>[ 3.337725] sdhci: Secure Digital Host Controller Interface driver
10675 10:53:37.059996 <6>[ 3.344162] sdhci: Copyright(c) Pierre Ossman
10676 10:53:37.066842 <6>[ 3.349554] Synopsys Designware Multimedia Card Interface Driver
10677 10:53:37.069996 <6>[ 3.356183] mmc0: CQHCI version 5.10
10678 10:53:37.076628 <6>[ 3.356705] sdhci-pltfm: SDHCI platform and OF driver helper
10679 10:53:37.084125 <6>[ 3.368411] ledtrig-cpu: registered to indicate activity on CPUs
10680 10:53:37.095004 <6>[ 3.375814] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10681 10:53:37.101288 <6>[ 3.383215] usbcore: registered new interface driver usbhid
10682 10:53:37.104496 <6>[ 3.389042] usbhid: USB HID core driver
10683 10:53:37.111495 <6>[ 3.393288] spi_master spi0: will run message pump with realtime priority
10684 10:53:37.158267 <6>[ 3.436148] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10685 10:53:37.178020 <6>[ 3.451718] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10686 10:53:37.181166 <6>[ 3.465301] mmc0: Command Queue Engine enabled
10687 10:53:37.187675 <6>[ 3.466722] cros-ec-spi spi0.0: Chrome EC device registered
10688 10:53:37.194776 <6>[ 3.470040] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10689 10:53:37.197430 <6>[ 3.483189] mmcblk0: mmc0:0001 DA4128 116 GiB
10690 10:53:37.211836 <6>[ 3.492709] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10691 10:53:37.218378 <6>[ 3.495282] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10692 10:53:37.225044 <6>[ 3.504226] NET: Registered PF_PACKET protocol family
10693 10:53:37.228301 <6>[ 3.509394] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10694 10:53:37.234785 <6>[ 3.513387] 9pnet: Installing 9P2000 support
10695 10:53:37.238614 <6>[ 3.519121] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10696 10:53:37.245015 <5>[ 3.523052] Key type dns_resolver registered
10697 10:53:37.251515 <6>[ 3.528844] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10698 10:53:37.254663 <6>[ 3.533353] registered taskstats version 1
10699 10:53:37.258035 <5>[ 3.543660] Loading compiled-in X.509 certificates
10700 10:53:37.293577 <4>[ 3.571147] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10701 10:53:37.303498 <4>[ 3.581843] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10702 10:53:37.313592 <3>[ 3.594406] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10703 10:53:37.325659 <6>[ 3.609890] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10704 10:53:37.332542 <6>[ 3.616798] xhci-mtk 11200000.usb: xHCI Host Controller
10705 10:53:37.338919 <6>[ 3.622306] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10706 10:53:37.349108 <6>[ 3.630151] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10707 10:53:37.355593 <6>[ 3.639581] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10708 10:53:37.362037 <6>[ 3.645670] xhci-mtk 11200000.usb: xHCI Host Controller
10709 10:53:37.368615 <6>[ 3.651151] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10710 10:53:37.375401 <6>[ 3.658802] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10711 10:53:37.382127 <6>[ 3.666489] hub 1-0:1.0: USB hub found
10712 10:53:37.385914 <6>[ 3.670513] hub 1-0:1.0: 1 port detected
10713 10:53:37.395381 <6>[ 3.674847] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10714 10:53:37.398682 <6>[ 3.683564] hub 2-0:1.0: USB hub found
10715 10:53:37.401719 <6>[ 3.687605] hub 2-0:1.0: 1 port detected
10716 10:53:37.410690 <6>[ 3.695078] mtk-msdc 11f70000.mmc: Got CD GPIO
10717 10:53:37.428070 <6>[ 3.709380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10718 10:53:37.434763 <6>[ 3.717579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10719 10:53:37.444523 <4>[ 3.725571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10720 10:53:37.454772 <6>[ 3.735280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10721 10:53:37.461069 <6>[ 3.743368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10722 10:53:37.471112 <6>[ 3.751426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10723 10:53:37.477687 <6>[ 3.759345] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10724 10:53:37.484354 <6>[ 3.767201] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10725 10:53:37.494039 <6>[ 3.775025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10726 10:53:37.504634 <6>[ 3.785824] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10727 10:53:37.515009 <6>[ 3.794185] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10728 10:53:37.521461 <6>[ 3.802577] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10729 10:53:37.531050 <6>[ 3.810925] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10730 10:53:37.538104 <6>[ 3.819293] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10731 10:53:37.548017 <6>[ 3.827641] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10732 10:53:37.554432 <6>[ 3.836009] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10733 10:53:37.564098 <6>[ 3.844354] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10734 10:53:37.570462 <6>[ 3.852717] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10735 10:53:37.580435 <6>[ 3.861061] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10736 10:53:37.587150 <6>[ 3.869405] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10737 10:53:37.596972 <6>[ 3.877747] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10738 10:53:37.603567 <6>[ 3.886090] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10739 10:53:37.613790 <6>[ 3.894434] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10740 10:53:37.620379 <6>[ 3.902777] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10741 10:53:37.627200 <6>[ 3.911683] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10742 10:53:37.635244 <6>[ 3.919115] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10743 10:53:37.641643 <6>[ 3.926151] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10744 10:53:37.652037 <6>[ 3.933253] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10745 10:53:37.658703 <6>[ 3.940559] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10746 10:53:37.668721 <6>[ 3.947458] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10747 10:53:37.675300 <6>[ 3.956598] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10748 10:53:37.685082 <6>[ 3.965770] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10749 10:53:37.695088 <6>[ 3.975186] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10750 10:53:37.705053 <6>[ 3.984668] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10751 10:53:37.714707 <6>[ 3.994142] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10752 10:53:37.724732 <6>[ 4.003269] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10753 10:53:37.731233 <6>[ 4.012744] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10754 10:53:37.741345 <6>[ 4.021870] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10755 10:53:37.751695 <6>[ 4.031173] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10756 10:53:37.761282 <6>[ 4.041339] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10757 10:53:37.772084 <6>[ 4.052854] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10758 10:53:37.829913 <6>[ 4.111062] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10759 10:53:37.984711 <6>[ 4.268536] hub 1-1:1.0: USB hub found
10760 10:53:37.987913 <6>[ 4.272959] hub 1-1:1.0: 4 ports detected
10761 10:53:38.110007 <6>[ 4.391351] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10762 10:53:38.135370 <6>[ 4.419668] hub 2-1:1.0: USB hub found
10763 10:53:38.138634 <6>[ 4.424066] hub 2-1:1.0: 3 ports detected
10764 10:53:38.310397 <6>[ 4.591192] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10765 10:53:38.443650 <6>[ 4.727421] hub 1-1.4:1.0: USB hub found
10766 10:53:38.446896 <6>[ 4.732093] hub 1-1.4:1.0: 2 ports detected
10767 10:53:38.522880 <6>[ 4.803424] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10768 10:53:38.746125 <6>[ 5.027192] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10769 10:53:38.938495 <6>[ 5.219192] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10770 10:53:50.042581 <6>[ 16.331537] ALSA device list:
10771 10:53:50.049464 <6>[ 16.334765] No soundcards found.
10772 10:53:50.056167 <6>[ 16.341158] Freeing unused kernel memory: 8384K
10773 10:53:50.059362 <6>[ 16.346066] Run /init as init process
10774 10:53:50.084263 <6>[ 16.370181] NET: Registered PF_INET6 protocol family
10775 10:53:50.090823 <6>[ 16.376298] Segment Routing with IPv6
10776 10:53:50.094639 <6>[ 16.380290] In-situ OAM (IOAM) with IPv6
10777 10:53:50.126793 <30>[ 16.392879] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10778 10:53:50.130044 <30>[ 16.416598] systemd[1]: Detected architecture arm64.
10779 10:53:50.130144
10780 10:53:50.136831 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10781 10:53:50.136916
10782 10:53:50.149296 <30>[ 16.435180] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10783 10:53:50.272898 <30>[ 16.555160] systemd[1]: Queued start job for default target Graphical Interface.
10784 10:53:50.314499 <30>[ 16.600179] systemd[1]: Created slice system-getty.slice.
10785 10:53:50.321213 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10786 10:53:50.338292 <30>[ 16.623713] systemd[1]: Created slice system-modprobe.slice.
10787 10:53:50.344684 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10788 10:53:50.361981 <30>[ 16.647857] systemd[1]: Created slice system-serial\x2dgetty.slice.
10789 10:53:50.371981 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10790 10:53:50.386317 <30>[ 16.671786] systemd[1]: Created slice User and Session Slice.
10791 10:53:50.392442 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10792 10:53:50.413379 <30>[ 16.695414] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10793 10:53:50.422668 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10794 10:53:50.436858 <30>[ 16.719257] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10795 10:53:50.443542 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10796 10:53:50.464509 <30>[ 16.743187] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10797 10:53:50.471177 <30>[ 16.755194] systemd[1]: Reached target Local Encrypted Volumes.
10798 10:53:50.477169 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10799 10:53:50.493908 <30>[ 16.779297] systemd[1]: Reached target Paths.
10800 10:53:50.496609 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10801 10:53:50.513191 <30>[ 16.799156] systemd[1]: Reached target Remote File Systems.
10802 10:53:50.519899 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10803 10:53:50.533472 <30>[ 16.819144] systemd[1]: Reached target Slices.
10804 10:53:50.536476 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10805 10:53:50.553644 <30>[ 16.839174] systemd[1]: Reached target Swap.
10806 10:53:50.556738 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10807 10:53:50.576650 <30>[ 16.859378] systemd[1]: Listening on initctl Compatibility Named Pipe.
10808 10:53:50.583370 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10809 10:53:50.598015 <30>[ 16.883732] systemd[1]: Listening on Journal Audit Socket.
10810 10:53:50.604637 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10811 10:53:50.621785 <30>[ 16.907644] systemd[1]: Listening on Journal Socket (/dev/log).
10812 10:53:50.628494 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10813 10:53:50.646208 <30>[ 16.931630] systemd[1]: Listening on Journal Socket.
10814 10:53:50.652171 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10815 10:53:50.665661 <30>[ 16.951408] systemd[1]: Listening on udev Control Socket.
10816 10:53:50.672294 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10817 10:53:50.685685 <30>[ 16.971343] systemd[1]: Listening on udev Kernel Socket.
10818 10:53:50.692337 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10819 10:53:50.721631 <30>[ 17.007215] systemd[1]: Mounting Huge Pages File System...
10820 10:53:50.728325 Mounting [0;1;39mHuge Pages File System[0m...
10821 10:53:50.743159 <30>[ 17.028709] systemd[1]: Mounting POSIX Message Queue File System...
10822 10:53:50.749436 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10823 10:53:50.767016 <30>[ 17.052786] systemd[1]: Mounting Kernel Debug File System...
10824 10:53:50.773556 Mounting [0;1;39mKernel Debug File System[0m...
10825 10:53:50.792954 <30>[ 17.075350] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10826 10:53:50.803325 <30>[ 17.085765] systemd[1]: Starting Create list of static device nodes for the current kernel...
10827 10:53:50.810081 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10828 10:53:50.827081 <30>[ 17.112798] systemd[1]: Starting Load Kernel Module configfs...
10829 10:53:50.833677 Starting [0;1;39mLoad Kernel Module configfs[0m...
10830 10:53:50.850935 <30>[ 17.136838] systemd[1]: Starting Load Kernel Module drm...
10831 10:53:50.857483 Starting [0;1;39mLoad Kernel Module drm[0m...
10832 10:53:50.876688 <30>[ 17.159295] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10833 10:53:50.886419 <30>[ 17.171959] systemd[1]: Starting Journal Service...
10834 10:53:50.889524 Starting [0;1;39mJournal Service[0m...
10835 10:53:50.906997 <30>[ 17.193051] systemd[1]: Starting Load Kernel Modules...
10836 10:53:50.913936 Starting [0;1;39mLoad Kernel Modules[0m...
10837 10:53:50.930262 <30>[ 17.212870] systemd[1]: Starting Remount Root and Kernel File Systems...
10838 10:53:50.936930 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10839 10:53:50.951294 <30>[ 17.236830] systemd[1]: Starting Coldplug All udev Devices...
10840 10:53:50.957816 Starting [0;1;39mColdplug All udev Devices[0m...
10841 10:53:50.975275 <30>[ 17.261195] systemd[1]: Mounted Huge Pages File System.
10842 10:53:50.981948 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10843 10:53:50.997769 <30>[ 17.283343] systemd[1]: Started Journal Service.
10844 10:53:51.003927 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10845 10:53:51.018450 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10846 10:53:51.034181 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10847 10:53:51.053451 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10848 10:53:51.066572 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10849 10:53:51.082295 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10850 10:53:51.098312 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10851 10:53:51.117616 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10852 10:53:51.133560 See 'systemctl status systemd-remount-fs.service' for details.
10853 10:53:51.179943 Mounting [0;1;39mKernel Configuration File System[0m...
10854 10:53:51.199346 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10855 10:53:51.214533 <46>[ 17.497191] systemd-journald[181]: Received client request to flush runtime journal.
10856 10:53:51.221891 Starting [0;1;39mLoad/Save Random Seed[0m...
10857 10:53:51.243396 Starting [0;1;39mApply Kernel Variables[0m...
10858 10:53:51.259288 Starting [0;1;39mCreate System Users[0m...
10859 10:53:51.279307 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10860 10:53:51.301616 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10861 10:53:51.318343 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10862 10:53:51.338074 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10863 10:53:51.358118 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10864 10:53:51.374247 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10865 10:53:51.421615 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10866 10:53:51.442032 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10867 10:53:51.453691 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10868 10:53:51.469658 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10869 10:53:51.525612 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10870 10:53:51.552162 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10871 10:53:51.569461 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10872 10:53:51.588632 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10873 10:53:51.605392 Starting [0;1;39mNetwork Time Synchronization[0m...
10874 10:53:51.622898 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10875 10:53:51.656580 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10876 10:53:51.702159 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10877 10:53:51.715983 <6>[ 17.998663] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10878 10:53:51.724856 <6>[ 18.011094] remoteproc remoteproc0: scp is available
10879 10:53:51.735310 <4>[ 18.017715] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10880 10:53:51.741565 <6>[ 18.027581] remoteproc remoteproc0: powering up scp
10881 10:53:51.751434 <4>[ 18.032963] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10882 10:53:51.757907 <6>[ 18.033431] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10883 10:53:51.764561 <3>[ 18.046145] remoteproc remoteproc0: request_firmware failed: -2
10884 10:53:51.774931 <6>[ 18.050493] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10885 10:53:51.781378 <3>[ 18.057659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 10:53:51.791483 <6>[ 18.065476] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10887 10:53:51.797638 <3>[ 18.073831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 10:53:51.807575 <3>[ 18.090311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 10:53:51.814408 Startin<6>[ 18.099281] mc: Linux media interface: v0.10
10890 10:53:51.820878 <3>[ 18.103397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 10:53:51.831066 g [0;1;39mLoad/<3>[ 18.112524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 10:53:51.840905 Save Screen …o<4>[ 18.121538] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10893 10:53:51.847349 <3>[ 18.121991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 10:53:51.857097 f leds:white:kbd<4>[ 18.130821] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10895 10:53:51.867148 _backlight[0m..<3>[ 18.138744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 10:53:51.867232 .
10897 10:53:51.873577 <3>[ 18.138751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 10:53:51.883767 <3>[ 18.138803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 10:53:51.887059 <6>[ 18.139503] videodev: Linux video capture interface: v2.00
10900 10:53:51.893507 <6>[ 18.147681] usbcore: registered new interface driver r8152
10901 10:53:51.903227 <3>[ 18.185237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 10:53:51.909913 <3>[ 18.193451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 10:53:51.919926 <6>[ 18.193969] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10904 10:53:51.929563 [[0;32m OK [<3>[ 18.201554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 10:53:51.940168 0m] Started [0;<6>[ 18.211975] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10906 10:53:51.946289 <6>[ 18.227304] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10907 10:53:51.953179 1;39mNetwork Tim<6>[ 18.237021] pci_bus 0000:00: root bus resource [bus 00-ff]
10908 10:53:51.962954 e Synchronizatio<3>[ 18.238246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 10:53:51.963045 n[0m.
10910 10:53:51.969642 <6>[ 18.244127] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10911 10:53:51.979546 <6>[ 18.244137] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10912 10:53:51.986287 <6>[ 18.244168] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10913 10:53:51.995883 <3>[ 18.253588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 10:53:52.002690 <6>[ 18.255685] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10915 10:53:52.010007 <6>[ 18.261417] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10916 10:53:52.019603 <3>[ 18.271303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 10:53:52.026047 <3>[ 18.271312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 10:53:52.032660 <6>[ 18.277641] pci 0000:00:00.0: supports D1 D2
10919 10:53:52.039189 <4>[ 18.281810] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10920 10:53:52.046219 <4>[ 18.281810] Fallback method does not support PEC.
10921 10:53:52.052903 <3>[ 18.285652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 10:53:52.062407 <3>[ 18.285722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 10:53:52.069038 <6>[ 18.294716] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10924 10:53:52.075551 <6>[ 18.295175] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10925 10:53:52.085398 <6>[ 18.306360] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10926 10:53:52.092501 <6>[ 18.312836] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10927 10:53:52.102402 <4>[ 18.318246] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10928 10:53:52.111896 <4>[ 18.318257] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10929 10:53:52.115088 <6>[ 18.347631] Bluetooth: Core ver 2.22
10930 10:53:52.122315 <6>[ 18.353272] usbcore: registered new interface driver cdc_ether
10931 10:53:52.125607 <6>[ 18.353359] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10932 10:53:52.136176 <6>[ 18.353391] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10933 10:53:52.142363 <6>[ 18.353426] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10934 10:53:52.149210 <6>[ 18.353444] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10935 10:53:52.152431 <6>[ 18.353571] pci 0000:01:00.0: supports D1 D2
10936 10:53:52.162274 <6>[ 18.353575] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10937 10:53:52.169055 <3>[ 18.353844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 10:53:52.175601 <6>[ 18.359689] NET: Registered PF_BLUETOOTH protocol family
10939 10:53:52.182837 <6>[ 18.366989] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10940 10:53:52.190193 <6>[ 18.376101] Bluetooth: HCI device and connection manager initialized
10941 10:53:52.193432 <6>[ 18.376118] Bluetooth: HCI socket layer initialized
10942 10:53:52.200683 <6>[ 18.384401] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10943 10:53:52.207363 <6>[ 18.387844] usbcore: registered new interface driver r8153_ecm
10944 10:53:52.213765 <6>[ 18.393416] Bluetooth: L2CAP socket layer initialized
10945 10:53:52.217020 <6>[ 18.396793] r8152 2-1.3:1.0 eth0: v1.12.13
10946 10:53:52.227105 <6>[ 18.401540] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10947 10:53:52.230087 <6>[ 18.405359] Bluetooth: SCO socket layer initialized
10948 10:53:52.236555 <6>[ 18.405903] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10949 10:53:52.246635 <6>[ 18.411547] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10950 10:53:52.257654 <6>[ 18.426491] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10951 10:53:52.263888 <6>[ 18.429241] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10952 10:53:52.270753 <6>[ 18.432788] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10953 10:53:52.280804 <3>[ 18.436478] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 10:53:52.290194 <3>[ 18.437187] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10955 10:53:52.297649 <6>[ 18.440878] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10956 10:53:52.300920 <6>[ 18.441130] usbcore: registered new interface driver uvcvideo
10957 10:53:52.311525 <6>[ 18.444775] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10958 10:53:52.314705 <6>[ 18.452194] usbcore: registered new interface driver btusb
10959 10:53:52.327663 <4>[ 18.452646] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10960 10:53:52.330913 <3>[ 18.452654] Bluetooth: hci0: Failed to load firmware file (-2)
10961 10:53:52.337805 <3>[ 18.452658] Bluetooth: hci0: Failed to set up firmware (-2)
10962 10:53:52.347541 <4>[ 18.452661] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10963 10:53:52.354958 <6>[ 18.455313] remoteproc remoteproc0: powering up scp
10964 10:53:52.364912 <4>[ 18.455358] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10965 10:53:52.368130 <3>[ 18.455365] remoteproc remoteproc0: request_firmware failed: -2
10966 10:53:52.378639 <3>[ 18.455369] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10967 10:53:52.382305 <6>[ 18.460842] pci 0000:00:00.0: PCI bridge to [bus 01]
10968 10:53:52.392095 <3>[ 18.478408] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10969 10:53:52.398957 <6>[ 18.479848] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10970 10:53:52.409139 <3>[ 18.491507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 10:53:52.412309 <6>[ 18.492947] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10972 10:53:52.423057 <3>[ 18.548002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 10:53:52.429394 <6>[ 18.549915] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10974 10:53:52.436116 <3>[ 18.555548] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10975 10:53:52.443305 <6>[ 18.563408] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10976 10:53:52.449866 <3>[ 18.596327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 10:53:52.460159 <3>[ 18.617158] power_supply sbs-5-000b: driver failed to report `charge_full' property: -6
10978 10:53:52.467168 <5>[ 18.625170] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10979 10:53:52.476661 <3>[ 18.647677] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 10:53:52.483524 <5>[ 18.665537] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10981 10:53:52.493282 <4>[ 18.773736] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10982 10:53:52.496749 <6>[ 18.782627] cfg80211: failed to load regulatory.db
10983 10:53:52.506309 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10984 10:53:52.521341 <6>[ 18.804035] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10985 10:53:52.528240 <6>[ 18.811514] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10986 10:53:52.534690 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10987 10:53:52.549100 <6>[ 18.835083] mt7921e 0000:01:00.0: ASIC revision: 79610010
10988 10:53:52.646394 <4>[ 18.925876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 10:53:52.708055 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10990 10:53:52.720950 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10991 10:53:52.747719 [[0;32m OK [0m] Started [0;<4>[ 19.024836] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 10:53:52.750334 1;39mDaily Cleanup of Temporary Directories[0m.
10993 10:53:52.764994 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10994 10:53:52.781093 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10995 10:53:52.801064 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10996 10:53:52.813187 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10997 10:53:52.832888 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10998 10:53:52.849645 <4>[ 19.128869] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 10:53:52.856241 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11000 10:53:52.869505 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11001 10:53:52.888717 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11002 10:53:52.937459 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11003 10:53:52.953446 <4>[ 19.233068] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11004 10:53:52.967942 Starting [0;1;39mUser Login Management[0m...
11005 10:53:52.983064 Starting [0;1;39mPermit User Sessions[0m...
11006 10:53:52.998439 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11007 10:53:53.015174 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11008 10:53:53.031484 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11009 10:53:53.053347 <4>[ 19.332747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11010 10:53:53.060109 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11011 10:53:53.075206 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11012 10:53:53.089776 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11013 10:53:53.106083 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11014 10:53:53.122019 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11015 10:53:53.137495 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11016 10:53:53.157614 <4>[ 19.437074] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 10:53:53.201045 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11018 10:53:53.224786 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11019 10:53:53.237992
11020 10:53:53.238078
11021 10:53:53.241008 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11022 10:53:53.241113
11023 10:53:53.244209 debian-bullseye-arm64 login: root (automatic login)
11024 10:53:53.244310
11025 10:53:53.244438
11026 10:53:53.257199 <4>[ 19.536938] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11027 10:53:53.264307 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11028 10:53:53.264411
11029 10:53:53.270938 The programs included with the Debian GNU/Linux system are free software;
11030 10:53:53.277241 the exact distribution terms for each program are described in the
11031 10:53:53.280563 individual files in /usr/share/doc/*/copyright.
11032 10:53:53.280665
11033 10:53:53.287144 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11034 10:53:53.290312 permitted by applicable law.
11035 10:53:53.290776 Matched prompt #10: / #
11037 10:53:53.291043 Setting prompt string to ['/ #']
11038 10:53:53.291167 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11040 10:53:53.291520 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11041 10:53:53.291639 start: 2.2.6 expect-shell-connection (timeout 00:02:41) [common]
11042 10:53:53.291736 Setting prompt string to ['/ #']
11043 10:53:53.291825 Forcing a shell prompt, looking for ['/ #']
11045 10:53:53.342101 / #
11046 10:53:53.342243 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11047 10:53:53.342360 Waiting using forced prompt support (timeout 00:02:30)
11048 10:53:53.347121
11049 10:53:53.356605 <4>[ 19.636984] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 10:53:53.356916 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11051 10:53:53.357053 start: 2.2.7 export-device-env (timeout 00:02:40) [common]
11052 10:53:53.357193 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11053 10:53:53.357326 end: 2.2 depthcharge-retry (duration 00:02:20) [common]
11054 10:53:53.357458 end: 2 depthcharge-action (duration 00:02:20) [common]
11055 10:53:53.357589 start: 3 lava-test-retry (timeout 00:07:10) [common]
11056 10:53:53.357718 start: 3.1 lava-test-shell (timeout 00:07:10) [common]
11057 10:53:53.357831 Using namespace: common
11059 10:53:53.458146 / # #
11060 10:53:53.458315 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11061 10:53:53.458479 #<4>[ 19.736999] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11062 10:53:53.463458
11063 10:53:53.463725 Using /lava-10590977
11065 10:53:53.563967 / # export SHELL=/bin/sh
11066 10:53:53.564144 export SHELL=/bin/sh<4>[ 19.837094] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11067 10:53:53.568789
11069 10:53:53.669249 / # . /lava-10590977/environment
11070 10:53:53.669407 . /lava-10590977/environment<3>[ 19.934990] mt7921e 0000:01:00.0: hardware init failed
11071 10:53:53.673788
11073 10:53:53.774285 / # /lava-10590977/bin/lava-test-runner /lava-10590977/0
11074 10:53:53.774416 Test shell timeout: 10s (minimum of the action and connection timeout)
11075 10:53:53.779014 /lava-10590977/bin/lava-test-runner /lava-10590977/0
11076 10:53:53.802392 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.086624] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10590977_1.5.2.3.1>
11077 10:53:53.802681 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10590977_1.5.2.3.1
11078 10:53:53.802786 Starting test lava.0_igt-gpu-panfrost (10590977_1.5.2.3.1)
11079 10:53:53.802924 Skipping test definition patterns.
11080 10:53:53.805585 nfrost
11081 10:53:53.808753 + cd /lava-10590977/0/tests/0_igt-gpu-panfrost
11082 10:53:53.808852 + cat uuid
11083 10:53:53.811974 + UUID=10590977_1.5.2.3.1
11084 10:53:53.812043 + set +x
11085 10:53:53.821849 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11086 10:53:53.829899 <8>[ 20.116287] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11087 10:53:53.830152 Received signal: <TESTSET> START panfrost_gem_new
11088 10:53:53.830229 Starting test_set panfrost_gem_new
11089 10:53:53.852736 <14>[ 20.138614] [IGT] panfrost_gem_new: executing
11090 10:53:53.862490 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.146809] [IGT] panfrost_gem_new: exiting, ret=77
11091 10:53:53.862570 .1.31 aarch64)
11092 10:53:53.875783 Test requirement not met in function drm_open_dr<8>[ 20.158096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11093 10:53:53.875876 iver, file ../lib/drmtest.c:621:
11094 10:53:53.876118 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11096 10:53:53.878777 Test requirement: !(fd<0)
11097 10:53:53.885787 No known gpu found for chipset flags 0x32 (panfrost)
11098 10:53:53.889026 Last errno: 2, No such file or directory
11099 10:53:53.895425 [1mSubtest gem-new<14>[ 20.179939] [IGT] panfrost_gem_new: executing
11100 10:53:53.895511 -4096: SKIP (0.000s)[0m
11101 10:53:53.905313 IGT-Version: 1.27.1-g7<14>[ 20.188378] [IGT] panfrost_gem_new: exiting, ret=77
11102 10:53:53.908937 66edf9 (aarch64) (Linux: 6.1.31 aarch64)
11103 10:53:53.915228 Test requirement not m<8>[ 20.199852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11104 10:53:53.915485 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11106 10:53:53.921843 et in function drm_open_driver, file ../lib/drmtest.c:621:
11107 10:53:53.925099 Test requirement: !(fd<0)
11108 10:53:53.928364 No known gpu found for chipset flags 0x32 (panfrost)
11109 10:53:53.931718 Last errno: 2, No such file or directory
11110 10:53:53.938473 [1mSubtest gem-new-0: SK<14>[ 20.223784] [IGT] panfrost_gem_new: executing
11111 10:53:53.941593 IP (0.000s)[0m
11112 10:53:53.948074 IGT-Version: 1.27.1-g766edf9 (a<14>[ 20.232987] [IGT] panfrost_gem_new: exiting, ret=77
11113 10:53:53.951438 arch64) (Linux: 6.1.31 aarch64)
11114 10:53:53.961239 Test requirement not met in fun<8>[ 20.244398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11115 10:53:53.961515 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11117 10:53:53.967798 ction drm_open_driver, file ../l<8>[ 20.253462] <LAVA_SIGNAL_TESTSET STOP>
11118 10:53:53.967910 ib/drmtest.c:621:
11119 10:53:53.968181 Received signal: <TESTSET> STOP
11120 10:53:53.968284 Closing test_set panfrost_gem_new
11121 10:53:53.971607 Test requirement: !(fd<0)
11122 10:53:53.974987 No known gpu found for chipset flags 0x32 (panfrost)
11123 10:53:53.981511 Last errno: 2, No such file or directory
11124 10:53:53.984715 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11125 10:53:53.991030 <8>[ 20.276038] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11126 10:53:53.991314 Received signal: <TESTSET> START panfrost_get_param
11127 10:53:53.991423 Starting test_set panfrost_get_param
11128 10:53:54.012524 <14>[ 20.298204] [IGT] panfrost_get_param: executing
11129 10:53:54.021830 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.306191] [IGT] panfrost_get_param: exiting, ret=77
11130 10:53:54.021943 .1.31 aarch64)
11131 10:53:54.035172 Test requirement not met in function drm_open_dr<8>[ 20.317959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11132 10:53:54.035433 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11134 10:53:54.038315 iver, file ../lib/drmtest.c:621:
11135 10:53:54.038398 Test requirement: !(fd<0)
11136 10:53:54.045098 No known gpu found for chipset flags 0x32 (panfrost)
11137 10:53:54.048435 Last errno: 2, No such file or directory
11138 10:53:54.055152 [1mSubtest base-pa<14>[ 20.339796] [IGT] panfrost_get_param: executing
11139 10:53:54.055251 rams: SKIP (0.000s)[0m
11140 10:53:54.064893 IGT-Version: 1.27.1-g76<14>[ 20.348351] [IGT] panfrost_get_param: exiting, ret=77
11141 10:53:54.068155 6edf9 (aarch64) (Linux: 6.1.31 aarch64)
11142 10:53:54.074852 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11144 10:53:54.078032 Test requirement not me<8>[ 20.359976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11145 10:53:54.081241 t in function drm_open_driver, file ../lib/drmtest.c:621:
11146 10:53:54.084612 Test requirement: !(fd<0)
11147 10:53:54.087979 No known gpu found for chipset flags 0x32 (panfrost)
11148 10:53:54.091244 Last errno: 2, No such file or directory
11149 10:53:54.097818 [1mSubtes<14>[ 20.383957] [IGT] panfrost_get_param: executing
11150 10:53:54.101430 t get-bad-param: SKIP (0.000s)[0m
11151 10:53:54.108099 IGT-Version:<14>[ 20.392313] [IGT] panfrost_get_param: exiting, ret=77
11152 10:53:54.110846 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11153 10:53:54.121166 Test require<8>[ 20.403988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11154 10:53:54.121427 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11156 10:53:54.127444 ment not met in function drm_ope<8>[ 20.412852] <LAVA_SIGNAL_TESTSET STOP>
11157 10:53:54.127729 Received signal: <TESTSET> STOP
11158 10:53:54.127829 Closing test_set panfrost_get_param
11159 10:53:54.130913 n_driver, file ../lib/drmtest.c:621:
11160 10:53:54.134036 Test requirement: !(fd<0)
11161 10:53:54.137415 No known gpu found for chipset flags 0x32 (panfrost)
11162 10:53:54.140674 Last errno: 2, No such file or directory
11163 10:53:54.143904 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11164 10:53:54.151474 <8>[ 20.437601] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11165 10:53:54.151757 Received signal: <TESTSET> START panfrost_prime
11166 10:53:54.151860 Starting test_set panfrost_prime
11167 10:53:54.173639 <14>[ 20.459547] [IGT] panfrost_prime: executing
11168 10:53:54.183558 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.467435] [IGT] panfrost_prime: exiting, ret=77
11169 10:53:54.183645 .1.31 aarch64)
11170 10:53:54.196323 Test requirement not met in function drm_open_dr<8>[ 20.478579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11171 10:53:54.196580 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11173 10:53:54.199486 iver, file ../li<8>[ 20.487646] <LAVA_SIGNAL_TESTSET STOP>
11174 10:53:54.199754 Received signal: <TESTSET> STOP
11175 10:53:54.199839 Closing test_set panfrost_prime
11176 10:53:54.202716 b/drmtest.c:621:
11177 10:53:54.202849 Test requirement: !(fd<0)
11178 10:53:54.209310 No known gpu found for chipset flags 0x32 (panfrost)
11179 10:53:54.213099 Last errno: 2, No such file or directory
11180 10:53:54.216342 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11181 10:53:54.224845 <8>[ 20.511141] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11182 10:53:54.225100 Received signal: <TESTSET> START panfrost_submit
11183 10:53:54.225171 Starting test_set panfrost_submit
11184 10:53:54.246527 <14>[ 20.533005] [IGT] panfrost_submit: executing
11185 10:53:54.256784 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.540832] [IGT] panfrost_submit: exiting, ret=77
11186 10:53:54.256894 .1.31 aarch64)
11187 10:53:54.266649 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11189 10:53:54.269553 Test requirement not met in function drm_open_dr<8>[ 20.552345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11190 10:53:54.269644 iver, file ../lib/drmtest.c:621:
11191 10:53:54.272898 Test requirement: !(fd<0)
11192 10:53:54.279614 No known gpu found for chipset flags 0x32 (panfrost)
11193 10:53:54.282766 Last errno: 2, No such file or directory
11194 10:53:54.289394 [1mSubtest pan-submit: SKIP (0.000<14>[ 20.575796] [IGT] panfrost_submit: executing
11195 10:53:54.289492 s)[0m
11196 10:53:54.299649 IGT-Version: 1.27.1-g766edf9 (aa<14>[ 20.583923] [IGT] panfrost_submit: exiting, ret=77
11197 10:53:54.299750 rch64) (Linux: 6.1.31 aarch64)
11198 10:53:54.312767 Test requirement not met in func<8>[ 20.594493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11199 10:53:54.313050 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11201 10:53:54.315662 tion drm_open_driver, file ../lib/drmtest.c:621:
11202 10:53:54.319562 Test requirement: !(fd<0)
11203 10:53:54.322673 No known gpu found for chipset flags 0x32 (panfrost)
11204 10:53:54.325754 Last errno: 2, No such file or directory
11205 10:53:54.335655 [1mSubtest pan-submit-error-no-jc:<14>[ 20.619688] [IGT] panfrost_submit: executing
11206 10:53:54.335739 SKIP (0.000s)[0m
11207 10:53:54.342448 IGT-Version: 1.27.1-g766edf9<14>[ 20.628487] [IGT] panfrost_submit: exiting, ret=77
11208 10:53:54.345883 (aarch64) (Linux: 6.1.31 aarch64)
11209 10:53:54.358688 Test requirement not met in <8>[ 20.639921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11210 10:53:54.358949 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11212 10:53:54.361788 function drm_open_driver, file ../lib/drmtest.c:621:
11213 10:53:54.365761 Test requirement: !(fd<0)
11214 10:53:54.368420 No known gpu found for chipset flags 0x32 (panfrost)
11215 10:53:54.371757 Last errno: 2, No such file or directory
11216 10:53:54.378839 [1mSubtest pan<14>[ 20.665268] [IGT] panfrost_submit: executing
11217 10:53:54.382252 -submit-error-bad-in-syncs: SKIP (0.000s)[0m
11218 10:53:54.388815 I<14>[ 20.673214] [IGT] panfrost_submit: exiting, ret=77
11219 10:53:54.395203 GT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11220 10:53:54.401840 T<8>[ 20.684627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11221 10:53:54.402107 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11223 10:53:54.408269 est requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11224 10:53:54.411577 Test requirement: !(fd<0)
11225 10:53:54.414871 No known gpu found for chipset flags 0x32 (panfrost)
11226 10:53:54.421246 Last errno: 2, No such file or directory
11227 10:53:54.424519 [1m<14>[ 20.710238] [IGT] panfrost_submit: executing
11228 10:53:54.434679 Subtest pan-submit-error-bad-bo-handles: SKIP (0<14>[ 20.719195] [IGT] panfrost_submit: exiting, ret=77
11229 10:53:54.434766 .000s)[0m
11230 10:53:54.448207 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.3<8>[ 20.730625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11231 10:53:54.448464 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11233 10:53:54.451405 1 aarch64)
11234 10:53:54.458046 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11235 10:53:54.458131 Test requirement: !(fd<0)
11236 10:53:54.464293 No known gpu found for chipset flags 0x32 (panfrost)
11237 10:53:54.470857 Last errno: 2, No<14>[ 20.756285] [IGT] panfrost_submit: executing
11238 10:53:54.470970 such file or directory
11239 10:53:54.480829 [1mSubtest pan-submit-<14>[ 20.764326] [IGT] panfrost_submit: exiting, ret=77
11240 10:53:54.484117 error-bad-requirements: SKIP (0.000s)[0m
11241 10:53:54.493952 IGT-Version: 1.27.1-g<8>[ 20.775660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11242 10:53:54.494238 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11244 10:53:54.497042 766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11245 10:53:54.503719 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11246 10:53:54.506857 Test requirement: !(fd<0)
11247 10:53:54.513459 No known gpu found for chipset flags 0x3<14>[ 20.800788] [IGT] panfrost_submit: executing
11248 10:53:54.517398 2 (panfrost)
11249 10:53:54.523872 Last errno: 2, No such file or dir<14>[ 20.808850] [IGT] panfrost_submit: exiting, ret=77
11250 10:53:54.523982 ectory
11251 10:53:54.536599 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)<8>[ 20.820437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11252 10:53:54.536713 [0m
11253 10:53:54.536989 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11255 10:53:54.543644 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11256 10:53:54.550344 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11257 10:53:54.553477 Test requirement: !(fd<0)
11258 10:53:54.556670 No known gpu <14>[ 20.843772] [IGT] panfrost_submit: executing
11259 10:53:54.559668 found for chipset flags 0x32 (panfrost)
11260 10:53:54.566686 Last er<14>[ 20.851843] [IGT] panfrost_submit: exiting, ret=77
11261 10:53:54.569779 rno: 2, No such file or directory
11262 10:53:54.579886 [1mSubtest pan-reset: SKIP (<8>[ 20.863228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11263 10:53:54.579975 0.000s)[0m
11264 10:53:54.580221 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11266 10:53:54.586285 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11267 10:53:54.592864 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11268 10:53:54.596109 Test requirement: !(fd<0)
11269 10:53:54.603153 No kno<14>[ 20.887495] [IGT] panfrost_submit: executing
11270 10:53:54.605859 wn gpu found for chipset flags 0x32 (panfrost)
11271 10:53:54.609200 <14>[ 20.895648] [IGT] panfrost_submit: exiting, ret=77
11272 10:53:54.612986 Last errno: 2, No such file or directory
11273 10:53:54.622918 [1mSubtest pan-submit<8>[ 20.906853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11274 10:53:54.623176 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11276 10:53:54.626299 -and-close: SKIP (0.000s)[0m
11277 10:53:54.629568 I<8>[ 20.916699] <LAVA_SIGNAL_TESTSET STOP>
11278 10:53:54.629822 Received signal: <TESTSET> STOP
11279 10:53:54.629893 Closing test_set panfrost_submit
11280 10:53:54.639080 GT-Version: 1.27<8>[ 20.922580] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10590977_1.5.2.3.1>
11281 10:53:54.639334 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10590977_1.5.2.3.1
11282 10:53:54.639423 Ending use of test pattern.
11283 10:53:54.639488 Ending test lava.0_igt-gpu-panfrost (10590977_1.5.2.3.1), duration 0.84
11285 10:53:54.642350 .1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11286 10:53:54.649646 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11287 10:53:54.652468 Test requirement: !(fd<0)
11288 10:53:54.655758 No known gpu found for chipset flags 0x32 (panfrost)
11289 10:53:54.662252 Last errno: 2, No such file or directory
11290 10:53:54.665254 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11291 10:53:54.665345 + set +x
11292 10:53:54.669103 <LAVA_TEST_RUNNER EXIT>
11293 10:53:54.669401 ok: lava_test_shell seems to have completed
11294 10:53:54.669821 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11295 10:53:54.669941 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11296 10:53:54.670057 end: 3 lava-test-retry (duration 00:00:01) [common]
11297 10:53:54.670186 start: 4 finalize (timeout 00:07:09) [common]
11298 10:53:54.670307 start: 4.1 power-off (timeout 00:00:30) [common]
11299 10:53:54.670503 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11300 10:53:54.746698 >> Command sent successfully.
11301 10:53:54.749097 Returned 0 in 0 seconds
11302 10:53:54.849464 end: 4.1 power-off (duration 00:00:00) [common]
11304 10:53:54.849786 start: 4.2 read-feedback (timeout 00:07:09) [common]
11305 10:53:54.850053 Listened to connection for namespace 'common' for up to 1s
11306 10:53:55.851087 Finalising connection for namespace 'common'
11307 10:53:55.851728 Disconnecting from shell: Finalise
11308 10:53:55.852144 / #
11309 10:53:55.953207 end: 4.2 read-feedback (duration 00:00:01) [common]
11310 10:53:55.953858 end: 4 finalize (duration 00:00:01) [common]
11311 10:53:55.954474 Cleaning after the job
11312 10:53:55.955004 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/ramdisk
11313 10:53:55.982079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/kernel
11314 10:53:55.997836 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/dtb
11315 10:53:55.998184 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590977/tftp-deploy-rfimzci5/modules
11316 10:53:56.006991 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10590977
11317 10:53:56.104691 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10590977
11318 10:53:56.104849 Job finished correctly