Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 10:57:01.412400 lava-dispatcher, installed at version: 2023.05.1
2 10:57:01.412617 start: 0 validate
3 10:57:01.412755 Start time: 2023-06-05 10:57:01.412748+00:00 (UTC)
4 10:57:01.412881 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:57:01.413012 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:57:01.700031 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:57:01.700211 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:57:01.992131 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:57:01.992317 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:57:02.278893 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:57:02.279080 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:57:02.579409 validate duration: 1.17
14 10:57:02.579688 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:57:02.579786 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:57:02.579880 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:57:02.580010 Not decompressing ramdisk as can be used compressed.
18 10:57:02.580097 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 10:57:02.580162 saving as /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/ramdisk/rootfs.cpio.gz
20 10:57:02.580224 total size: 43394293 (41MB)
21 10:57:02.581383 progress 0% (0MB)
22 10:57:02.592795 progress 5% (2MB)
23 10:57:02.604084 progress 10% (4MB)
24 10:57:02.615456 progress 15% (6MB)
25 10:57:02.626659 progress 20% (8MB)
26 10:57:02.638207 progress 25% (10MB)
27 10:57:02.649471 progress 30% (12MB)
28 10:57:02.660734 progress 35% (14MB)
29 10:57:02.671905 progress 40% (16MB)
30 10:57:02.683176 progress 45% (18MB)
31 10:57:02.694589 progress 50% (20MB)
32 10:57:02.705958 progress 55% (22MB)
33 10:57:02.717296 progress 60% (24MB)
34 10:57:02.728494 progress 65% (26MB)
35 10:57:02.740129 progress 70% (29MB)
36 10:57:02.751316 progress 75% (31MB)
37 10:57:02.762589 progress 80% (33MB)
38 10:57:02.773938 progress 85% (35MB)
39 10:57:02.785252 progress 90% (37MB)
40 10:57:02.796811 progress 95% (39MB)
41 10:57:02.808331 progress 100% (41MB)
42 10:57:02.808544 41MB downloaded in 0.23s (181.26MB/s)
43 10:57:02.808713 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:57:02.808956 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:57:02.809044 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:57:02.809128 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:57:02.809265 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:57:02.809339 saving as /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/kernel/Image
50 10:57:02.809401 total size: 45746688 (43MB)
51 10:57:02.809462 No compression specified
52 10:57:02.810585 progress 0% (0MB)
53 10:57:02.822301 progress 5% (2MB)
54 10:57:02.834387 progress 10% (4MB)
55 10:57:02.846517 progress 15% (6MB)
56 10:57:02.858554 progress 20% (8MB)
57 10:57:02.870408 progress 25% (10MB)
58 10:57:02.882285 progress 30% (13MB)
59 10:57:02.894146 progress 35% (15MB)
60 10:57:02.906068 progress 40% (17MB)
61 10:57:02.917949 progress 45% (19MB)
62 10:57:02.929913 progress 50% (21MB)
63 10:57:02.941529 progress 55% (24MB)
64 10:57:02.953592 progress 60% (26MB)
65 10:57:02.965353 progress 65% (28MB)
66 10:57:02.977121 progress 70% (30MB)
67 10:57:02.989116 progress 75% (32MB)
68 10:57:03.000945 progress 80% (34MB)
69 10:57:03.012812 progress 85% (37MB)
70 10:57:03.024596 progress 90% (39MB)
71 10:57:03.036400 progress 95% (41MB)
72 10:57:03.047930 progress 100% (43MB)
73 10:57:03.048114 43MB downloaded in 0.24s (182.76MB/s)
74 10:57:03.048275 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:57:03.048507 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:57:03.048594 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:57:03.048680 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:57:03.048821 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:57:03.048893 saving as /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/dtb/mt8192-asurada-spherion-r0.dtb
81 10:57:03.048956 total size: 46924 (0MB)
82 10:57:03.049016 No compression specified
83 10:57:03.050155 progress 69% (0MB)
84 10:57:03.050434 progress 100% (0MB)
85 10:57:03.050592 0MB downloaded in 0.00s (27.39MB/s)
86 10:57:03.050721 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:57:03.050947 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:57:03.051035 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:57:03.051119 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:57:03.051236 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:57:03.051307 saving as /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/modules/modules.tar
93 10:57:03.051411 total size: 8542412 (8MB)
94 10:57:03.051483 Using unxz to decompress xz
95 10:57:03.055644 progress 0% (0MB)
96 10:57:03.078856 progress 5% (0MB)
97 10:57:03.105212 progress 10% (0MB)
98 10:57:03.134148 progress 15% (1MB)
99 10:57:03.161515 progress 20% (1MB)
100 10:57:03.189684 progress 25% (2MB)
101 10:57:03.216025 progress 30% (2MB)
102 10:57:03.243903 progress 35% (2MB)
103 10:57:03.270748 progress 40% (3MB)
104 10:57:03.298246 progress 45% (3MB)
105 10:57:03.324422 progress 50% (4MB)
106 10:57:03.349700 progress 55% (4MB)
107 10:57:03.377694 progress 60% (4MB)
108 10:57:03.405230 progress 65% (5MB)
109 10:57:03.433009 progress 70% (5MB)
110 10:57:03.462770 progress 75% (6MB)
111 10:57:03.495352 progress 80% (6MB)
112 10:57:03.520105 progress 85% (6MB)
113 10:57:03.548196 progress 90% (7MB)
114 10:57:03.574308 progress 95% (7MB)
115 10:57:03.600750 progress 100% (8MB)
116 10:57:03.606827 8MB downloaded in 0.56s (14.67MB/s)
117 10:57:03.607145 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:57:03.607477 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:57:03.607593 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:57:03.607702 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:57:03.607810 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:57:03.607911 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:57:03.608194 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234
125 10:57:03.608382 makedir: /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin
126 10:57:03.608526 makedir: /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/tests
127 10:57:03.608662 makedir: /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/results
128 10:57:03.608816 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-add-keys
129 10:57:03.608998 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-add-sources
130 10:57:03.609159 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-background-process-start
131 10:57:03.609322 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-background-process-stop
132 10:57:03.609478 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-common-functions
133 10:57:03.609632 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-echo-ipv4
134 10:57:03.609789 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-install-packages
135 10:57:03.609942 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-installed-packages
136 10:57:03.610095 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-os-build
137 10:57:03.610272 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-probe-channel
138 10:57:03.610443 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-probe-ip
139 10:57:03.610592 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-target-ip
140 10:57:03.610720 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-target-mac
141 10:57:03.610847 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-target-storage
142 10:57:03.610973 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-case
143 10:57:03.611096 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-event
144 10:57:03.611217 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-feedback
145 10:57:03.611353 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-raise
146 10:57:03.611523 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-reference
147 10:57:03.611678 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-runner
148 10:57:03.611835 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-set
149 10:57:03.611992 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-test-shell
150 10:57:03.612152 Updating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-install-packages (oe)
151 10:57:03.612335 Updating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/bin/lava-installed-packages (oe)
152 10:57:03.612485 Creating /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/environment
153 10:57:03.612613 LAVA metadata
154 10:57:03.612690 - LAVA_JOB_ID=10591023
155 10:57:03.612758 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:57:03.612868 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:57:03.612936 skipped lava-vland-overlay
158 10:57:03.613012 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:57:03.613095 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:57:03.613158 skipped lava-multinode-overlay
161 10:57:03.613235 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:57:03.613317 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:57:03.613396 Loading test definitions
164 10:57:03.613489 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:57:03.613566 Using /lava-10591023 at stage 0
166 10:57:03.613877 uuid=10591023_1.5.2.3.1 testdef=None
167 10:57:03.613968 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:57:03.614053 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:57:03.614580 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:57:03.614809 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:57:03.615515 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:57:03.615771 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:57:03.616454 runner path: /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/0/tests/0_igt-kms-mediatek test_uuid 10591023_1.5.2.3.1
176 10:57:03.616612 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:57:03.616826 Creating lava-test-runner.conf files
179 10:57:03.616891 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591023/lava-overlay-zm1_b234/lava-10591023/0 for stage 0
180 10:57:03.616979 - 0_igt-kms-mediatek
181 10:57:03.617074 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:57:03.617167 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:57:03.624663 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:57:03.624836 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:57:03.624963 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:57:03.625085 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:57:03.625207 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:57:05.084913 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:57:05.085293 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 10:57:05.085423 extracting modules file /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591023/extract-overlay-ramdisk-6g38ksna/ramdisk
191 10:57:05.308458 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:57:05.308628 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 10:57:05.308727 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591023/compress-overlay-hnrz12wh/overlay-1.5.2.4.tar.gz to ramdisk
194 10:57:05.308799 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591023/compress-overlay-hnrz12wh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591023/extract-overlay-ramdisk-6g38ksna/ramdisk
195 10:57:05.315310 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:57:05.315433 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 10:57:05.315528 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:57:05.315621 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 10:57:05.315705 Building ramdisk /var/lib/lava/dispatcher/tmp/10591023/extract-overlay-ramdisk-6g38ksna/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591023/extract-overlay-ramdisk-6g38ksna/ramdisk
200 10:57:06.395984 >> 369039 blocks
201 10:57:12.202762 rename /var/lib/lava/dispatcher/tmp/10591023/extract-overlay-ramdisk-6g38ksna/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/ramdisk/ramdisk.cpio.gz
202 10:57:12.203204 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 10:57:12.203340 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 10:57:12.203477 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 10:57:12.203583 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/kernel/Image'
206 10:57:24.461761 Returned 0 in 12 seconds
207 10:57:24.562322 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/kernel/image.itb
208 10:57:25.334039 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:57:25.334394 output: Created: Mon Jun 5 11:57:25 2023
210 10:57:25.334495 output: Image 0 (kernel-1)
211 10:57:25.334581 output: Description:
212 10:57:25.334665 output: Created: Mon Jun 5 11:57:25 2023
213 10:57:25.334770 output: Type: Kernel Image
214 10:57:25.334872 output: Compression: lzma compressed
215 10:57:25.334974 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
216 10:57:25.335074 output: Architecture: AArch64
217 10:57:25.335175 output: OS: Linux
218 10:57:25.335272 output: Load Address: 0x00000000
219 10:57:25.335404 output: Entry Point: 0x00000000
220 10:57:25.335502 output: Hash algo: crc32
221 10:57:25.335595 output: Hash value: 8ce42972
222 10:57:25.335688 output: Image 1 (fdt-1)
223 10:57:25.335807 output: Description: mt8192-asurada-spherion-r0
224 10:57:25.335928 output: Created: Mon Jun 5 11:57:25 2023
225 10:57:25.336021 output: Type: Flat Device Tree
226 10:57:25.336113 output: Compression: uncompressed
227 10:57:25.336205 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:57:25.336297 output: Architecture: AArch64
229 10:57:25.336389 output: Hash algo: crc32
230 10:57:25.336481 output: Hash value: 1df858fa
231 10:57:25.336572 output: Image 2 (ramdisk-1)
232 10:57:25.336663 output: Description: unavailable
233 10:57:25.336755 output: Created: Mon Jun 5 11:57:25 2023
234 10:57:25.336847 output: Type: RAMDisk Image
235 10:57:25.336938 output: Compression: Unknown Compression
236 10:57:25.337030 output: Data Size: 56365979 Bytes = 55044.90 KiB = 53.75 MiB
237 10:57:25.337122 output: Architecture: AArch64
238 10:57:25.337213 output: OS: Linux
239 10:57:25.337304 output: Load Address: unavailable
240 10:57:25.337395 output: Entry Point: unavailable
241 10:57:25.337492 output: Hash algo: crc32
242 10:57:25.337585 output: Hash value: a2f4e9a4
243 10:57:25.337682 output: Default Configuration: 'conf-1'
244 10:57:25.337776 output: Configuration 0 (conf-1)
245 10:57:25.337862 output: Description: mt8192-asurada-spherion-r0
246 10:57:25.337946 output: Kernel: kernel-1
247 10:57:25.338030 output: Init Ramdisk: ramdisk-1
248 10:57:25.338113 output: FDT: fdt-1
249 10:57:25.338195 output: Loadables: kernel-1
250 10:57:25.338277 output:
251 10:57:25.338502 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:57:25.338628 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:57:25.338764 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 10:57:25.338887 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 10:57:25.338989 No LXC device requested
256 10:57:25.339097 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:57:25.339215 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 10:57:25.339347 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:57:25.339436 Checking files for TFTP limit of 4294967296 bytes.
260 10:57:25.339922 end: 1 tftp-deploy (duration 00:00:23) [common]
261 10:57:25.340023 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:57:25.340114 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:57:25.340237 substitutions:
264 10:57:25.340307 - {DTB}: 10591023/tftp-deploy-_ex67_zt/dtb/mt8192-asurada-spherion-r0.dtb
265 10:57:25.340371 - {INITRD}: 10591023/tftp-deploy-_ex67_zt/ramdisk/ramdisk.cpio.gz
266 10:57:25.340430 - {KERNEL}: 10591023/tftp-deploy-_ex67_zt/kernel/Image
267 10:57:25.340487 - {LAVA_MAC}: None
268 10:57:25.340543 - {PRESEED_CONFIG}: None
269 10:57:25.340599 - {PRESEED_LOCAL}: None
270 10:57:25.340653 - {RAMDISK}: 10591023/tftp-deploy-_ex67_zt/ramdisk/ramdisk.cpio.gz
271 10:57:25.340707 - {ROOT_PART}: None
272 10:57:25.340762 - {ROOT}: None
273 10:57:25.340815 - {SERVER_IP}: 192.168.201.1
274 10:57:25.340868 - {TEE}: None
275 10:57:25.340922 Parsed boot commands:
276 10:57:25.340977 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:57:25.341146 Parsed boot commands: tftpboot 192.168.201.1 10591023/tftp-deploy-_ex67_zt/kernel/image.itb 10591023/tftp-deploy-_ex67_zt/kernel/cmdline
278 10:57:25.341238 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:57:25.341328 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:57:25.341421 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:57:25.341507 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:57:25.341580 Not connected, no need to disconnect.
283 10:57:25.341662 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:57:25.341757 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:57:25.341857 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 10:57:25.345230 Setting prompt string to ['lava-test: # ']
287 10:57:25.345563 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:57:25.345679 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:57:25.345810 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:57:25.345936 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:57:25.346138 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 10:57:30.482443 >> Command sent successfully.
293 10:57:30.484727 Returned 0 in 5 seconds
294 10:57:30.585114 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:57:30.585815 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:57:30.585943 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:57:30.586035 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:57:30.586103 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:57:30.586171 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:57:30.586426 [Enter `^Ec?' for help]
302 10:57:30.761102
303 10:57:30.761273
304 10:57:30.761377 F0: 102B 0000
305 10:57:30.761470
306 10:57:30.761559 F3: 1001 0000 [0200]
307 10:57:30.761648
308 10:57:30.765125 F3: 1001 0000
309 10:57:30.765221
310 10:57:30.765309 F7: 102D 0000
311 10:57:30.765397
312 10:57:30.765482 F1: 0000 0000
313 10:57:30.769072
314 10:57:30.769168 V0: 0000 0000 [0001]
315 10:57:30.769256
316 10:57:30.769343 00: 0007 8000
317 10:57:30.769431
318 10:57:30.772381 01: 0000 0000
319 10:57:30.772450
320 10:57:30.772508 BP: 0C00 0209 [0000]
321 10:57:30.772565
322 10:57:30.776413 G0: 1182 0000
323 10:57:30.776502
324 10:57:30.776567 EC: 0000 0021 [4000]
325 10:57:30.776627
326 10:57:30.779687 S7: 0000 0000 [0000]
327 10:57:30.779770
328 10:57:30.779835 CC: 0000 0000 [0001]
329 10:57:30.779896
330 10:57:30.782753 T0: 0000 0040 [010F]
331 10:57:30.782835
332 10:57:30.782900 Jump to BL
333 10:57:30.782959
334 10:57:30.808668
335 10:57:30.808761
336 10:57:30.808829
337 10:57:30.815757 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:57:30.819621 ARM64: Exception handlers installed.
339 10:57:30.822765 ARM64: Testing exception
340 10:57:30.827217 ARM64: Done test exception
341 10:57:30.831125 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:57:30.842389 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:57:30.849726 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:57:30.859446 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:57:30.866277 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:57:30.872578 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:57:30.884896 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:57:30.891505 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:57:30.910893 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:57:30.914092 WDT: Last reset was cold boot
351 10:57:30.917420 SPI1(PAD0) initialized at 2873684 Hz
352 10:57:30.921177 SPI5(PAD0) initialized at 992727 Hz
353 10:57:30.924647 VBOOT: Loading verstage.
354 10:57:30.931082 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:57:30.934697 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:57:30.937979 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:57:30.941230 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:57:30.948444 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:57:30.954868 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:57:30.965855 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 10:57:30.965940
362 10:57:30.966006
363 10:57:30.976628 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:57:30.979947 ARM64: Exception handlers installed.
365 10:57:30.983386 ARM64: Testing exception
366 10:57:30.983471 ARM64: Done test exception
367 10:57:30.989774 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:57:30.993021 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:57:31.007131 Probing TPM: . done!
370 10:57:31.007248 TPM ready after 0 ms
371 10:57:31.014527 Connected to device vid:did:rid of 1ae0:0028:00
372 10:57:31.021288 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 10:57:31.081169 Initialized TPM device CR50 revision 0
374 10:57:31.092979 tlcl_send_startup: Startup return code is 0
375 10:57:31.093121 TPM: setup succeeded
376 10:57:31.104448 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:57:31.112859 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:57:31.126877 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:57:31.134318 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:57:31.138214 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:57:31.142099 in-header: 03 07 00 00 08 00 00 00
382 10:57:31.145237 in-data: aa e4 47 04 13 02 00 00
383 10:57:31.149003 Chrome EC: UHEPI supported
384 10:57:31.152899 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:57:31.156970 in-header: 03 95 00 00 08 00 00 00
386 10:57:31.160963 in-data: 18 20 20 08 00 00 00 00
387 10:57:31.161053 Phase 1
388 10:57:31.164877 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:57:31.172150 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:57:31.180086 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:57:31.180178 Recovery requested (1009000e)
392 10:57:31.189624 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:57:31.195001 tlcl_extend: response is 0
394 10:57:31.204470 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:57:31.209815 tlcl_extend: response is 0
396 10:57:31.216973 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:57:31.236795 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 10:57:31.243343 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:57:31.243438
400 10:57:31.243526
401 10:57:31.253458 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:57:31.256718 ARM64: Exception handlers installed.
403 10:57:31.259965 ARM64: Testing exception
404 10:57:31.260060 ARM64: Done test exception
405 10:57:31.282448 pmic_efuse_setting: Set efuses in 11 msecs
406 10:57:31.285789 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:57:31.292495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:57:31.296199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:57:31.303268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:57:31.307186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:57:31.310527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:57:31.313879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:57:31.321588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:57:31.325182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:57:31.329029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:57:31.335955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:57:31.339760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:57:31.343809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:57:31.346988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:57:31.355574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:57:31.358672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:57:31.366037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:57:31.373669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:57:31.377791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:57:31.385058 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:57:31.389065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:57:31.392386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:57:31.400095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:57:31.407537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:57:31.411478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:57:31.415388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:57:31.422903 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:57:31.426098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:57:31.433902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:57:31.437735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:57:31.441030 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:57:31.444979 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:57:31.452021 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:57:31.455940 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:57:31.463539 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:57:31.466707 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:57:31.470761 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:57:31.477977 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:57:31.481860 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:57:31.485136 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:57:31.488948 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:57:31.496365 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:57:31.500237 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:57:31.504019 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:57:31.507987 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:57:31.511870 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:57:31.515201 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:57:31.519200 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:57:31.526552 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:57:31.529863 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:57:31.533947 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:57:31.537093 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:57:31.544641 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:57:31.552669 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:57:31.560418 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:57:31.568001 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:57:31.574833 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:57:31.578861 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:57:31.582169 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:57:31.590608 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:57:31.593908 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 10:57:31.601138 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:57:31.605110 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 10:57:31.608233 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:57:31.620226 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 10:57:31.629646 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 10:57:31.639572 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 10:57:31.648735 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 10:57:31.657827 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 10:57:31.667657 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 10:57:31.677550 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 10:57:31.681014 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 10:57:31.684944 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 10:57:31.688897 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:57:31.696469 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:57:31.700436 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:57:31.704469 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:57:31.704555 ADC[4]: Raw value=906942 ID=7
484 10:57:31.707649 ADC[3]: Raw value=213441 ID=1
485 10:57:31.712331 RAM Code: 0x71
486 10:57:31.715442 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:57:31.719973 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:57:31.727277 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:57:31.735097 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:57:31.738409 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:57:31.741950 in-header: 03 07 00 00 08 00 00 00
492 10:57:31.745900 in-data: aa e4 47 04 13 02 00 00
493 10:57:31.749794 Chrome EC: UHEPI supported
494 10:57:31.752886 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:57:31.757335 in-header: 03 95 00 00 08 00 00 00
496 10:57:31.760976 in-data: 18 20 20 08 00 00 00 00
497 10:57:31.764641 MRC: failed to locate region type 0.
498 10:57:31.772269 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:57:31.776098 DRAM-K: Running full calibration
500 10:57:31.779310 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:57:31.783688 header.status = 0x0
502 10:57:31.787003 header.version = 0x6 (expected: 0x6)
503 10:57:31.790686 header.size = 0xd00 (expected: 0xd00)
504 10:57:31.790852 header.flags = 0x0
505 10:57:31.798017 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:57:31.815544 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 10:57:31.823305 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:57:31.823428 dram_init: ddr_geometry: 2
509 10:57:31.826714 [EMI] MDL number = 2
510 10:57:31.826796 [EMI] Get MDL freq = 0
511 10:57:31.830255 dram_init: ddr_type: 0
512 10:57:31.834056 is_discrete_lpddr4: 1
513 10:57:31.834139 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:57:31.834205
515 10:57:31.837428
516 10:57:31.837512 [Bian_co] ETT version 0.0.0.1
517 10:57:31.845532 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:57:31.845643
519 10:57:31.848800 dramc_set_vcore_voltage set vcore to 650000
520 10:57:31.848911 Read voltage for 800, 4
521 10:57:31.848978 Vio18 = 0
522 10:57:31.852611 Vcore = 650000
523 10:57:31.852693 Vdram = 0
524 10:57:31.852775 Vddq = 0
525 10:57:31.855818 Vmddr = 0
526 10:57:31.855901 dram_init: config_dvfs: 1
527 10:57:31.863591 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:57:31.867391 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:57:31.871013 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 10:57:31.874326 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 10:57:31.878322 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 10:57:31.881544 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 10:57:31.884620 MEM_TYPE=3, freq_sel=18
534 10:57:31.888386 sv_algorithm_assistance_LP4_1600
535 10:57:31.891562 ============ PULL DRAM RESETB DOWN ============
536 10:57:31.894828 ========== PULL DRAM RESETB DOWN end =========
537 10:57:31.902050 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:57:31.906057 ===================================
539 10:57:31.906140 LPDDR4 DRAM CONFIGURATION
540 10:57:31.909625 ===================================
541 10:57:31.913007 EX_ROW_EN[0] = 0x0
542 10:57:31.913090 EX_ROW_EN[1] = 0x0
543 10:57:31.916957 LP4Y_EN = 0x0
544 10:57:31.917041 WORK_FSP = 0x0
545 10:57:31.920261 WL = 0x2
546 10:57:31.920344 RL = 0x2
547 10:57:31.923351 BL = 0x2
548 10:57:31.923447 RPST = 0x0
549 10:57:31.927143 RD_PRE = 0x0
550 10:57:31.927226 WR_PRE = 0x1
551 10:57:31.930394 WR_PST = 0x0
552 10:57:31.930477 DBI_WR = 0x0
553 10:57:31.933730 DBI_RD = 0x0
554 10:57:31.933814 OTF = 0x1
555 10:57:31.937009 ===================================
556 10:57:31.940400 ===================================
557 10:57:31.944351 ANA top config
558 10:57:31.944433 ===================================
559 10:57:31.948409 DLL_ASYNC_EN = 0
560 10:57:31.951665 ALL_SLAVE_EN = 1
561 10:57:31.954912 NEW_RANK_MODE = 1
562 10:57:31.954996 DLL_IDLE_MODE = 1
563 10:57:31.958064 LP45_APHY_COMB_EN = 1
564 10:57:31.961883 TX_ODT_DIS = 1
565 10:57:31.965390 NEW_8X_MODE = 1
566 10:57:31.965474 ===================================
567 10:57:31.969125 ===================================
568 10:57:31.972865 data_rate = 1600
569 10:57:31.975709 CKR = 1
570 10:57:31.979239 DQ_P2S_RATIO = 8
571 10:57:31.982679 ===================================
572 10:57:31.985808 CA_P2S_RATIO = 8
573 10:57:31.985891 DQ_CA_OPEN = 0
574 10:57:31.989038 DQ_SEMI_OPEN = 0
575 10:57:31.992708 CA_SEMI_OPEN = 0
576 10:57:31.995815 CA_FULL_RATE = 0
577 10:57:31.999312 DQ_CKDIV4_EN = 1
578 10:57:32.002450 CA_CKDIV4_EN = 1
579 10:57:32.002533 CA_PREDIV_EN = 0
580 10:57:32.005735 PH8_DLY = 0
581 10:57:32.009117 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:57:32.012594 DQ_AAMCK_DIV = 4
583 10:57:32.015774 CA_AAMCK_DIV = 4
584 10:57:32.018961 CA_ADMCK_DIV = 4
585 10:57:32.019044 DQ_TRACK_CA_EN = 0
586 10:57:32.022812 CA_PICK = 800
587 10:57:32.026158 CA_MCKIO = 800
588 10:57:32.029893 MCKIO_SEMI = 0
589 10:57:32.033184 PLL_FREQ = 3068
590 10:57:32.033282 DQ_UI_PI_RATIO = 32
591 10:57:32.037094 CA_UI_PI_RATIO = 0
592 10:57:32.041174 ===================================
593 10:57:32.045309 ===================================
594 10:57:32.048651 memory_type:LPDDR4
595 10:57:32.048743 GP_NUM : 10
596 10:57:32.052008 SRAM_EN : 1
597 10:57:32.052105 MD32_EN : 0
598 10:57:32.056096 ===================================
599 10:57:32.059382 [ANA_INIT] >>>>>>>>>>>>>>
600 10:57:32.063459 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:57:32.063618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:57:32.066884 ===================================
603 10:57:32.070205 data_rate = 1600,PCW = 0X7600
604 10:57:32.073422 ===================================
605 10:57:32.076635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:57:32.083454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:57:32.090452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:57:32.093727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:57:32.097195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:57:32.100372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:57:32.103582 [ANA_INIT] flow start
612 10:57:32.103689 [ANA_INIT] PLL >>>>>>>>
613 10:57:32.106747 [ANA_INIT] PLL <<<<<<<<
614 10:57:32.110293 [ANA_INIT] MIDPI >>>>>>>>
615 10:57:32.110398 [ANA_INIT] MIDPI <<<<<<<<
616 10:57:32.113586 [ANA_INIT] DLL >>>>>>>>
617 10:57:32.116966 [ANA_INIT] flow end
618 10:57:32.120242 ============ LP4 DIFF to SE enter ============
619 10:57:32.123723 ============ LP4 DIFF to SE exit ============
620 10:57:32.126930 [ANA_INIT] <<<<<<<<<<<<<
621 10:57:32.130187 [Flow] Enable top DCM control >>>>>
622 10:57:32.133382 [Flow] Enable top DCM control <<<<<
623 10:57:32.136649 Enable DLL master slave shuffle
624 10:57:32.139990 ==============================================================
625 10:57:32.143333 Gating Mode config
626 10:57:32.150070 ==============================================================
627 10:57:32.150155 Config description:
628 10:57:32.160100 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:57:32.166886 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:57:32.170076 SELPH_MODE 0: By rank 1: By Phase
631 10:57:32.176751 ==============================================================
632 10:57:32.180408 GAT_TRACK_EN = 1
633 10:57:32.183531 RX_GATING_MODE = 2
634 10:57:32.187220 RX_GATING_TRACK_MODE = 2
635 10:57:32.190285 SELPH_MODE = 1
636 10:57:32.193371 PICG_EARLY_EN = 1
637 10:57:32.193470 VALID_LAT_VALUE = 1
638 10:57:32.199866 ==============================================================
639 10:57:32.203582 Enter into Gating configuration >>>>
640 10:57:32.206898 Exit from Gating configuration <<<<
641 10:57:32.210126 Enter into DVFS_PRE_config >>>>>
642 10:57:32.220038 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:57:32.223460 Exit from DVFS_PRE_config <<<<<
644 10:57:32.226889 Enter into PICG configuration >>>>
645 10:57:32.230188 Exit from PICG configuration <<<<
646 10:57:32.233585 [RX_INPUT] configuration >>>>>
647 10:57:32.236819 [RX_INPUT] configuration <<<<<
648 10:57:32.240113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:57:32.246558 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:57:32.253225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:57:32.260066 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:57:32.266806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:57:32.270052 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:57:32.276777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:57:32.280196 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:57:32.283309 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:57:32.287317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:57:32.293702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:57:32.296836 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:57:32.300140 ===================================
661 10:57:32.303461 LPDDR4 DRAM CONFIGURATION
662 10:57:32.306578 ===================================
663 10:57:32.306681 EX_ROW_EN[0] = 0x0
664 10:57:32.309788 EX_ROW_EN[1] = 0x0
665 10:57:32.309899 LP4Y_EN = 0x0
666 10:57:32.313570 WORK_FSP = 0x0
667 10:57:32.313672 WL = 0x2
668 10:57:32.316832 RL = 0x2
669 10:57:32.316934 BL = 0x2
670 10:57:32.320164 RPST = 0x0
671 10:57:32.320238 RD_PRE = 0x0
672 10:57:32.323311 WR_PRE = 0x1
673 10:57:32.323423 WR_PST = 0x0
674 10:57:32.326552 DBI_WR = 0x0
675 10:57:32.330362 DBI_RD = 0x0
676 10:57:32.330463 OTF = 0x1
677 10:57:32.333490 ===================================
678 10:57:32.336838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:57:32.340060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:57:32.346704 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:57:32.349909 ===================================
682 10:57:32.350020 LPDDR4 DRAM CONFIGURATION
683 10:57:32.353763 ===================================
684 10:57:32.357093 EX_ROW_EN[0] = 0x10
685 10:57:32.359795 EX_ROW_EN[1] = 0x0
686 10:57:32.359872 LP4Y_EN = 0x0
687 10:57:32.363224 WORK_FSP = 0x0
688 10:57:32.363330 WL = 0x2
689 10:57:32.367073 RL = 0x2
690 10:57:32.367153 BL = 0x2
691 10:57:32.369870 RPST = 0x0
692 10:57:32.369975 RD_PRE = 0x0
693 10:57:32.373309 WR_PRE = 0x1
694 10:57:32.373409 WR_PST = 0x0
695 10:57:32.376600 DBI_WR = 0x0
696 10:57:32.376678 DBI_RD = 0x0
697 10:57:32.380500 OTF = 0x1
698 10:57:32.383868 ===================================
699 10:57:32.390231 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:57:32.393671 nWR fixed to 40
701 10:57:32.393753 [ModeRegInit_LP4] CH0 RK0
702 10:57:32.396948 [ModeRegInit_LP4] CH0 RK1
703 10:57:32.400428 [ModeRegInit_LP4] CH1 RK0
704 10:57:32.403706 [ModeRegInit_LP4] CH1 RK1
705 10:57:32.403791 match AC timing 13
706 10:57:32.406805 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:57:32.413547 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:57:32.417492 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:57:32.420675 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:57:32.427231 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:57:32.427358 [EMI DOE] emi_dcm 0
712 10:57:32.433581 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:57:32.433686 ==
714 10:57:32.436970 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:57:32.440624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:57:32.440706 ==
717 10:57:32.443956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:57:32.450220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:57:32.460126 [CA 0] Center 36 (6~67) winsize 62
720 10:57:32.464257 [CA 1] Center 36 (6~67) winsize 62
721 10:57:32.467465 [CA 2] Center 34 (4~65) winsize 62
722 10:57:32.470677 [CA 3] Center 33 (3~64) winsize 62
723 10:57:32.473962 [CA 4] Center 33 (3~63) winsize 61
724 10:57:32.477271 [CA 5] Center 32 (2~62) winsize 61
725 10:57:32.477382
726 10:57:32.480653 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:57:32.480783
728 10:57:32.483868 [CATrainingPosCal] consider 1 rank data
729 10:57:32.487137 u2DelayCellTimex100 = 270/100 ps
730 10:57:32.490388 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 10:57:32.493697 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 10:57:32.500617 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 10:57:32.503742 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 10:57:32.506803 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 10:57:32.510523 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 10:57:32.510600
737 10:57:32.513678 CA PerBit enable=1, Macro0, CA PI delay=32
738 10:57:32.513850
739 10:57:32.517361 [CBTSetCACLKResult] CA Dly = 32
740 10:57:32.517443 CS Dly: 4 (0~35)
741 10:57:32.517545 ==
742 10:57:32.520542 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:57:32.527574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:57:32.527665 ==
745 10:57:32.530632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:57:32.537091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:57:32.546273 [CA 0] Center 36 (6~67) winsize 62
748 10:57:32.550247 [CA 1] Center 36 (6~67) winsize 62
749 10:57:32.553471 [CA 2] Center 34 (4~65) winsize 62
750 10:57:32.556878 [CA 3] Center 34 (3~65) winsize 63
751 10:57:32.560063 [CA 4] Center 32 (2~63) winsize 62
752 10:57:32.563249 [CA 5] Center 32 (2~63) winsize 62
753 10:57:32.563369
754 10:57:32.566106 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:57:32.566188
756 10:57:32.569292 [CATrainingPosCal] consider 2 rank data
757 10:57:32.573368 u2DelayCellTimex100 = 270/100 ps
758 10:57:32.576210 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 10:57:32.582735 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 10:57:32.585959 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 10:57:32.589469 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 10:57:32.592832 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 10:57:32.596152 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 10:57:32.596297
765 10:57:32.600003 CA PerBit enable=1, Macro0, CA PI delay=32
766 10:57:32.600086
767 10:57:32.603285 [CBTSetCACLKResult] CA Dly = 32
768 10:57:32.603435 CS Dly: 4 (0~36)
769 10:57:32.606598
770 10:57:32.606680 ----->DramcWriteLeveling(PI) begin...
771 10:57:32.610122 ==
772 10:57:32.610209 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:57:32.613840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:57:32.617469 ==
775 10:57:32.617591 Write leveling (Byte 0): 34 => 34
776 10:57:32.621446 Write leveling (Byte 1): 29 => 29
777 10:57:32.625202 DramcWriteLeveling(PI) end<-----
778 10:57:32.625316
779 10:57:32.625413 ==
780 10:57:32.628480 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:57:32.631721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:57:32.631805 ==
783 10:57:32.635435 [Gating] SW mode calibration
784 10:57:32.642898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:57:32.649461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:57:32.652628 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:57:32.656399 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 10:57:32.663065 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 10:57:32.666436 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 10:57:32.669715 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:57:32.673071 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:57:32.679732 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:57:32.683244 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:57:32.686634 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:57:32.693241 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:57:32.696559 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:57:32.699855 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:57:32.706572 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:57:32.709861 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:57:32.713244 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:57:32.719788 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:57:32.722932 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:57:32.726479 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:57:32.733246 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 10:57:32.736388 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:57:32.739567 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:57:32.743114 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:57:32.749628 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:57:32.753346 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:57:32.756590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:57:32.762919 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:57:32.766233 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
813 10:57:32.769989 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
814 10:57:32.776712 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:57:32.779985 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:57:32.783347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:57:32.790018 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:57:32.793367 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:57:32.796188 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 10:57:32.803394 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
821 10:57:32.806670 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 10:57:32.810017 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:57:32.816652 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:57:32.820035 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:57:32.823337 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:57:32.829900 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:57:32.833016 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 10:57:32.836182 0 11 8 | B1->B0 | 2b2b 3a3a | 0 1 | (0 0) (0 0)
829 10:57:32.839683 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
830 10:57:32.846440 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:57:32.849751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:57:32.853440 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:57:32.859659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:57:32.862942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:57:32.866864 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 10:57:32.873333 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 10:57:32.876418 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:57:32.880085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:57:32.886799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:57:32.890358 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:57:32.893558 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:57:32.899676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:57:32.903665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:57:32.907014 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:57:32.910138 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:57:32.917004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:57:32.920370 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:57:32.923813 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:57:32.929940 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:57:32.933526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:57:32.936530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:57:32.943695 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:57:32.943778 Total UI for P1: 0, mck2ui 16
854 10:57:32.950341 best dqsien dly found for B0: ( 0, 14, 6)
855 10:57:32.953741 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:57:32.956934 Total UI for P1: 0, mck2ui 16
857 10:57:32.961357 best dqsien dly found for B1: ( 0, 14, 8)
858 10:57:32.964709 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 10:57:32.967932 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 10:57:32.968026
861 10:57:32.970964 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 10:57:32.974550 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:57:32.977655 [Gating] SW calibration Done
864 10:57:32.977734 ==
865 10:57:32.981056 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:57:32.984374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:57:32.984505 ==
868 10:57:32.988015 RX Vref Scan: 0
869 10:57:32.988247
870 10:57:32.988343 RX Vref 0 -> 0, step: 1
871 10:57:32.988436
872 10:57:32.991203 RX Delay -130 -> 252, step: 16
873 10:57:32.994311 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 10:57:33.001014 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 10:57:33.004321 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 10:57:33.007655 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 10:57:33.010961 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 10:57:33.014824 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 10:57:33.020884 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 10:57:33.024724 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 10:57:33.028089 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 10:57:33.031235 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 10:57:33.034598 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 10:57:33.041077 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 10:57:33.044354 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 10:57:33.047738 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 10:57:33.051101 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 10:57:33.054937 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 10:57:33.055061 ==
890 10:57:33.057956 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:57:33.064418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:57:33.064547 ==
893 10:57:33.064617 DQS Delay:
894 10:57:33.068114 DQS0 = 0, DQS1 = 0
895 10:57:33.068223 DQM Delay:
896 10:57:33.068317 DQM0 = 88, DQM1 = 83
897 10:57:33.071549 DQ Delay:
898 10:57:33.074305 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 10:57:33.078031 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 10:57:33.080927 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 10:57:33.084553 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
902 10:57:33.084699
903 10:57:33.084782
904 10:57:33.084857 ==
905 10:57:33.087626 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:57:33.091557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:57:33.091641 ==
908 10:57:33.091708
909 10:57:33.091771
910 10:57:33.094738 TX Vref Scan disable
911 10:57:33.094848 == TX Byte 0 ==
912 10:57:33.101068 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 10:57:33.104334 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 10:57:33.104419 == TX Byte 1 ==
915 10:57:33.111541 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 10:57:33.114942 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 10:57:33.115026 ==
918 10:57:33.118202 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:57:33.120854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:57:33.120943 ==
921 10:57:33.135501 TX Vref=22, minBit 8, minWin=27, winSum=447
922 10:57:33.139312 TX Vref=24, minBit 8, minWin=27, winSum=451
923 10:57:33.142595 TX Vref=26, minBit 8, minWin=27, winSum=451
924 10:57:33.145884 TX Vref=28, minBit 0, minWin=28, winSum=457
925 10:57:33.149333 TX Vref=30, minBit 11, minWin=28, winSum=460
926 10:57:33.152482 TX Vref=32, minBit 5, minWin=28, winSum=458
927 10:57:33.159189 [TxChooseVref] Worse bit 11, Min win 28, Win sum 460, Final Vref 30
928 10:57:33.159311
929 10:57:33.162410 Final TX Range 1 Vref 30
930 10:57:33.162495
931 10:57:33.162561 ==
932 10:57:33.166091 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:57:33.169055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:57:33.169149 ==
935 10:57:33.169237
936 10:57:33.172531
937 10:57:33.172612 TX Vref Scan disable
938 10:57:33.175796 == TX Byte 0 ==
939 10:57:33.179002 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 10:57:33.182365 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 10:57:33.186243 == TX Byte 1 ==
942 10:57:33.189367 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 10:57:33.192389 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 10:57:33.196376
945 10:57:33.196526 [DATLAT]
946 10:57:33.196620 Freq=800, CH0 RK0
947 10:57:33.196709
948 10:57:33.199511 DATLAT Default: 0xa
949 10:57:33.199613 0, 0xFFFF, sum = 0
950 10:57:33.202805 1, 0xFFFF, sum = 0
951 10:57:33.202889 2, 0xFFFF, sum = 0
952 10:57:33.206281 3, 0xFFFF, sum = 0
953 10:57:33.206409 4, 0xFFFF, sum = 0
954 10:57:33.209478 5, 0xFFFF, sum = 0
955 10:57:33.209601 6, 0xFFFF, sum = 0
956 10:57:33.212740 7, 0xFFFF, sum = 0
957 10:57:33.215972 8, 0xFFFF, sum = 0
958 10:57:33.216053 9, 0x0, sum = 1
959 10:57:33.216149 10, 0x0, sum = 2
960 10:57:33.219357 11, 0x0, sum = 3
961 10:57:33.219481 12, 0x0, sum = 4
962 10:57:33.222665 best_step = 10
963 10:57:33.222777
964 10:57:33.222874 ==
965 10:57:33.226083 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:57:33.229356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:57:33.229459 ==
968 10:57:33.232789 RX Vref Scan: 1
969 10:57:33.232893
970 10:57:33.232994 Set Vref Range= 32 -> 127
971 10:57:33.233091
972 10:57:33.236339 RX Vref 32 -> 127, step: 1
973 10:57:33.236443
974 10:57:33.239709 RX Delay -79 -> 252, step: 8
975 10:57:33.239818
976 10:57:33.242805 Set Vref, RX VrefLevel [Byte0]: 32
977 10:57:33.246165 [Byte1]: 32
978 10:57:33.246278
979 10:57:33.249395 Set Vref, RX VrefLevel [Byte0]: 33
980 10:57:33.252626 [Byte1]: 33
981 10:57:33.256473
982 10:57:33.256551 Set Vref, RX VrefLevel [Byte0]: 34
983 10:57:33.259672 [Byte1]: 34
984 10:57:33.263860
985 10:57:33.263967 Set Vref, RX VrefLevel [Byte0]: 35
986 10:57:33.267110 [Byte1]: 35
987 10:57:33.271366
988 10:57:33.271446 Set Vref, RX VrefLevel [Byte0]: 36
989 10:57:33.275420 [Byte1]: 36
990 10:57:33.279273
991 10:57:33.279403 Set Vref, RX VrefLevel [Byte0]: 37
992 10:57:33.282452 [Byte1]: 37
993 10:57:33.287014
994 10:57:33.287137 Set Vref, RX VrefLevel [Byte0]: 38
995 10:57:33.290219 [Byte1]: 38
996 10:57:33.294833
997 10:57:33.294913 Set Vref, RX VrefLevel [Byte0]: 39
998 10:57:33.298164 [Byte1]: 39
999 10:57:33.301772
1000 10:57:33.301846 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:57:33.305603 [Byte1]: 40
1002 10:57:33.308903
1003 10:57:33.309008 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:57:33.311996 [Byte1]: 41
1005 10:57:33.316435
1006 10:57:33.316552 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:57:33.319680 [Byte1]: 42
1008 10:57:33.324354
1009 10:57:33.324469 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:57:33.327573 [Byte1]: 43
1011 10:57:33.331683
1012 10:57:33.331762 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:57:33.335048 [Byte1]: 44
1014 10:57:33.338987
1015 10:57:33.339088 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:57:33.342295 [Byte1]: 45
1017 10:57:33.346809
1018 10:57:33.346911 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:57:33.350025 [Byte1]: 46
1020 10:57:33.354310
1021 10:57:33.354417 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:57:33.357532 [Byte1]: 47
1023 10:57:33.362085
1024 10:57:33.362184 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:57:33.365387 [Byte1]: 48
1026 10:57:33.369439
1027 10:57:33.369537 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:57:33.372695 [Byte1]: 49
1029 10:57:33.377336
1030 10:57:33.377443 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:57:33.379961 [Byte1]: 50
1032 10:57:33.384579
1033 10:57:33.384682 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:57:33.387698 [Byte1]: 51
1035 10:57:33.391953
1036 10:57:33.392025 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:57:33.395539 [Byte1]: 52
1038 10:57:33.399564
1039 10:57:33.399637 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:57:33.402564 [Byte1]: 53
1041 10:57:33.406933
1042 10:57:33.407044 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:57:33.410605 [Byte1]: 54
1044 10:57:33.414851
1045 10:57:33.414928 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:57:33.417944 [Byte1]: 55
1047 10:57:33.422416
1048 10:57:33.422494 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:57:33.425660 [Byte1]: 56
1050 10:57:33.430117
1051 10:57:33.430217 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:57:33.433336 [Byte1]: 57
1053 10:57:33.437422
1054 10:57:33.437521 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:57:33.440633 [Byte1]: 58
1056 10:57:33.445295
1057 10:57:33.445409 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:57:33.448183 [Byte1]: 59
1059 10:57:33.452696
1060 10:57:33.452767 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:57:33.455738 [Byte1]: 60
1062 10:57:33.460154
1063 10:57:33.460235 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:57:33.463335 [Byte1]: 61
1065 10:57:33.467394
1066 10:57:33.467475 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:57:33.470589 [Byte1]: 62
1068 10:57:33.475240
1069 10:57:33.475366 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:57:33.478221 [Byte1]: 63
1071 10:57:33.482752
1072 10:57:33.482833 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:57:33.486009 [Byte1]: 64
1074 10:57:33.489954
1075 10:57:33.490035 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:57:33.493843 [Byte1]: 65
1077 10:57:33.497599
1078 10:57:33.497680 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:57:33.501334 [Byte1]: 66
1080 10:57:33.505630
1081 10:57:33.505710 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:57:33.508729 [Byte1]: 67
1083 10:57:33.513073
1084 10:57:33.513161 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:57:33.516193 [Byte1]: 68
1086 10:57:33.520401
1087 10:57:33.520472 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:57:33.523954 [Byte1]: 69
1089 10:57:33.527705
1090 10:57:33.527802 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:57:33.531558 [Byte1]: 70
1092 10:57:33.535264
1093 10:57:33.535374 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:57:33.538818 [Byte1]: 71
1095 10:57:33.542875
1096 10:57:33.542950 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:57:33.546148 [Byte1]: 72
1098 10:57:33.550910
1099 10:57:33.550989 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:57:33.553629 [Byte1]: 73
1101 10:57:33.558022
1102 10:57:33.558103 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:57:33.564314 [Byte1]: 74
1104 10:57:33.564395
1105 10:57:33.568207 Set Vref, RX VrefLevel [Byte0]: 75
1106 10:57:33.571398 [Byte1]: 75
1107 10:57:33.571473
1108 10:57:33.574683 Set Vref, RX VrefLevel [Byte0]: 76
1109 10:57:33.577991 [Byte1]: 76
1110 10:57:33.578093
1111 10:57:33.581290 Set Vref, RX VrefLevel [Byte0]: 77
1112 10:57:33.584496 [Byte1]: 77
1113 10:57:33.588375
1114 10:57:33.588452 Final RX Vref Byte 0 = 57 to rank0
1115 10:57:33.591727 Final RX Vref Byte 1 = 61 to rank0
1116 10:57:33.595085 Final RX Vref Byte 0 = 57 to rank1
1117 10:57:33.598345 Final RX Vref Byte 1 = 61 to rank1==
1118 10:57:33.601589 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 10:57:33.608549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 10:57:33.608628 ==
1121 10:57:33.608720 DQS Delay:
1122 10:57:33.608838 DQS0 = 0, DQS1 = 0
1123 10:57:33.611563 DQM Delay:
1124 10:57:33.611637 DQM0 = 91, DQM1 = 86
1125 10:57:33.614976 DQ Delay:
1126 10:57:33.618585 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 10:57:33.618663 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1128 10:57:33.621780 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1129 10:57:33.625390 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1130 10:57:33.628422
1131 10:57:33.628492
1132 10:57:33.635205 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1133 10:57:33.638491 CH0 RK0: MR19=606, MR18=493F
1134 10:57:33.645369 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1135 10:57:33.645472
1136 10:57:33.648447 ----->DramcWriteLeveling(PI) begin...
1137 10:57:33.648523 ==
1138 10:57:33.651547 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 10:57:33.654953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 10:57:33.655030 ==
1141 10:57:33.658815 Write leveling (Byte 0): 34 => 34
1142 10:57:33.662192 Write leveling (Byte 1): 29 => 29
1143 10:57:33.665313 DramcWriteLeveling(PI) end<-----
1144 10:57:33.665413
1145 10:57:33.665514 ==
1146 10:57:33.668347 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 10:57:33.671513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 10:57:33.671609 ==
1149 10:57:33.675433 [Gating] SW mode calibration
1150 10:57:33.681997 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 10:57:33.725611 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 10:57:33.725885 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 10:57:33.725956 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 10:57:33.726019 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 10:57:33.726079 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:57:33.726164 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:57:33.726270 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:57:33.726356 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:57:33.726453 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:57:33.726511 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:57:33.770135 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:57:33.770700 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:57:33.771470 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:57:33.771570 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:57:33.771668 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:57:33.771937 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:57:33.772016 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:57:33.772088 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:57:33.772176 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 10:57:33.772249 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 10:57:33.811679 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:57:33.811951 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:57:33.812023 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:57:33.812164 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:57:33.812224 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:57:33.812299 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:57:33.812395 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1178 10:57:33.812476 0 9 8 | B1->B0 | 2d2d 2b2b | 0 1 | (0 0) (1 1)
1179 10:57:33.812533 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:57:33.815919 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:57:33.819130 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:57:33.822783 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:57:33.829161 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:57:33.832165 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 10:57:33.835860 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1186 10:57:33.842689 0 10 8 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (1 0)
1187 10:57:33.845659 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:57:33.849427 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:57:33.853158 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:57:33.860077 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:57:33.864530 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:57:33.868471 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:57:33.871621 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1194 10:57:33.875019 0 11 8 | B1->B0 | 4040 3e3e | 1 0 | (0 0) (1 1)
1195 10:57:33.882026 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 10:57:33.885348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:57:33.888609 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:57:33.895079 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:57:33.898811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:57:33.902012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:57:33.908628 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:57:33.912032 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 10:57:33.915277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1204 10:57:33.918633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:57:33.925705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:57:33.928934 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:57:33.931905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:57:33.938772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:57:33.941890 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:57:33.945631 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:57:33.952070 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:57:33.955195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:57:33.959047 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:57:33.965306 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:57:33.968489 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:57:33.972177 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:57:33.978572 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:57:33.982449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1219 10:57:33.985631 Total UI for P1: 0, mck2ui 16
1220 10:57:33.988879 best dqsien dly found for B1: ( 0, 14, 6)
1221 10:57:33.992215 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 10:57:33.995624 Total UI for P1: 0, mck2ui 16
1223 10:57:33.998817 best dqsien dly found for B0: ( 0, 14, 8)
1224 10:57:34.002052 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 10:57:34.005098 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1226 10:57:34.005217
1227 10:57:34.009009 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 10:57:34.012280 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 10:57:34.015493 [Gating] SW calibration Done
1230 10:57:34.015586 ==
1231 10:57:34.018825 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 10:57:34.025421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 10:57:34.025499 ==
1234 10:57:34.025563 RX Vref Scan: 0
1235 10:57:34.025623
1236 10:57:34.028559 RX Vref 0 -> 0, step: 1
1237 10:57:34.028632
1238 10:57:34.031958 RX Delay -130 -> 252, step: 16
1239 10:57:34.035285 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 10:57:34.038974 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 10:57:34.041939 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 10:57:34.045227 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 10:57:34.052003 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 10:57:34.055644 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 10:57:34.058874 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 10:57:34.062052 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 10:57:34.065379 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 10:57:34.072307 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1249 10:57:34.075486 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1250 10:57:34.079147 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 10:57:34.082271 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1252 10:57:34.085442 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 10:57:34.092574 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 10:57:34.095690 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1255 10:57:34.095797 ==
1256 10:57:34.099033 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 10:57:34.102286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 10:57:34.102391 ==
1259 10:57:34.102458 DQS Delay:
1260 10:57:34.105973 DQS0 = 0, DQS1 = 0
1261 10:57:34.106072 DQM Delay:
1262 10:57:34.109168 DQM0 = 93, DQM1 = 84
1263 10:57:34.109274 DQ Delay:
1264 10:57:34.112557 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 10:57:34.115749 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 10:57:34.119062 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1267 10:57:34.122382 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1268 10:57:34.122488
1269 10:57:34.122579
1270 10:57:34.122664 ==
1271 10:57:34.125661 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 10:57:34.129063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 10:57:34.132494 ==
1274 10:57:34.132596
1275 10:57:34.132686
1276 10:57:34.132781 TX Vref Scan disable
1277 10:57:34.136162 == TX Byte 0 ==
1278 10:57:34.139550 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1279 10:57:34.142714 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1280 10:57:34.145875 == TX Byte 1 ==
1281 10:57:34.149589 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1282 10:57:34.152721 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1283 10:57:34.156259 ==
1284 10:57:34.156366 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 10:57:34.162907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 10:57:34.163013 ==
1287 10:57:34.175398 TX Vref=22, minBit 8, minWin=27, winSum=445
1288 10:57:34.179093 TX Vref=24, minBit 12, minWin=27, winSum=452
1289 10:57:34.182310 TX Vref=26, minBit 1, minWin=28, winSum=456
1290 10:57:34.185369 TX Vref=28, minBit 4, minWin=28, winSum=458
1291 10:57:34.189006 TX Vref=30, minBit 1, minWin=28, winSum=458
1292 10:57:34.192048 TX Vref=32, minBit 2, minWin=28, winSum=456
1293 10:57:34.198652 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
1294 10:57:34.198736
1295 10:57:34.201983 Final TX Range 1 Vref 28
1296 10:57:34.202063
1297 10:57:34.202126 ==
1298 10:57:34.205335 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 10:57:34.209121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 10:57:34.209230 ==
1301 10:57:34.209321
1302 10:57:34.212208
1303 10:57:34.212288 TX Vref Scan disable
1304 10:57:34.215426 == TX Byte 0 ==
1305 10:57:34.218649 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1306 10:57:34.222042 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1307 10:57:34.225378 == TX Byte 1 ==
1308 10:57:34.229270 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1309 10:57:34.232453 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1310 10:57:34.235669
1311 10:57:34.235757 [DATLAT]
1312 10:57:34.235832 Freq=800, CH0 RK1
1313 10:57:34.235898
1314 10:57:34.238984 DATLAT Default: 0xa
1315 10:57:34.239081 0, 0xFFFF, sum = 0
1316 10:57:34.242150 1, 0xFFFF, sum = 0
1317 10:57:34.242257 2, 0xFFFF, sum = 0
1318 10:57:34.245355 3, 0xFFFF, sum = 0
1319 10:57:34.245435 4, 0xFFFF, sum = 0
1320 10:57:34.248600 5, 0xFFFF, sum = 0
1321 10:57:34.248761 6, 0xFFFF, sum = 0
1322 10:57:34.252465 7, 0xFFFF, sum = 0
1323 10:57:34.255599 8, 0xFFFF, sum = 0
1324 10:57:34.255707 9, 0x0, sum = 1
1325 10:57:34.255800 10, 0x0, sum = 2
1326 10:57:34.258658 11, 0x0, sum = 3
1327 10:57:34.258765 12, 0x0, sum = 4
1328 10:57:34.262228 best_step = 10
1329 10:57:34.262331
1330 10:57:34.262421 ==
1331 10:57:34.265423 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 10:57:34.269036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 10:57:34.269116 ==
1334 10:57:34.272088 RX Vref Scan: 0
1335 10:57:34.272167
1336 10:57:34.272230 RX Vref 0 -> 0, step: 1
1337 10:57:34.272290
1338 10:57:34.275304 RX Delay -79 -> 252, step: 8
1339 10:57:34.282473 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 10:57:34.285592 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 10:57:34.288726 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 10:57:34.291793 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 10:57:34.295582 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 10:57:34.301943 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1345 10:57:34.305263 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 10:57:34.309062 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 10:57:34.312438 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 10:57:34.315499 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 10:57:34.322392 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 10:57:34.325683 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 10:57:34.328951 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1352 10:57:34.332081 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1353 10:57:34.335494 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 10:57:34.342524 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 10:57:34.342604 ==
1356 10:57:34.345656 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 10:57:34.348904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 10:57:34.348985 ==
1359 10:57:34.349047 DQS Delay:
1360 10:57:34.352080 DQS0 = 0, DQS1 = 0
1361 10:57:34.352160 DQM Delay:
1362 10:57:34.355315 DQM0 = 92, DQM1 = 84
1363 10:57:34.355431 DQ Delay:
1364 10:57:34.358806 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1365 10:57:34.361998 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1366 10:57:34.365673 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 10:57:34.368750 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1368 10:57:34.368833
1369 10:57:34.368960
1370 10:57:34.375658 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 10:57:34.378667 CH0 RK1: MR19=606, MR18=4212
1372 10:57:34.385727 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 10:57:34.389091 [RxdqsGatingPostProcess] freq 800
1374 10:57:34.395582 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 10:57:34.399196 Pre-setting of DQS Precalculation
1376 10:57:34.402319 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 10:57:34.402423 ==
1378 10:57:34.405476 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 10:57:34.408854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 10:57:34.408927 ==
1381 10:57:34.415794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 10:57:34.422508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 10:57:34.430274 [CA 0] Center 36 (6~67) winsize 62
1384 10:57:34.433748 [CA 1] Center 36 (6~67) winsize 62
1385 10:57:34.437008 [CA 2] Center 35 (5~66) winsize 62
1386 10:57:34.440372 [CA 3] Center 34 (4~65) winsize 62
1387 10:57:34.443610 [CA 4] Center 35 (5~65) winsize 61
1388 10:57:34.447364 [CA 5] Center 34 (4~65) winsize 62
1389 10:57:34.447458
1390 10:57:34.450642 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 10:57:34.450711
1392 10:57:34.453962 [CATrainingPosCal] consider 1 rank data
1393 10:57:34.457335 u2DelayCellTimex100 = 270/100 ps
1394 10:57:34.460580 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 10:57:34.463920 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 10:57:34.471019 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1397 10:57:34.474193 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 10:57:34.477348 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 10:57:34.481009 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 10:57:34.481115
1401 10:57:34.484127 CA PerBit enable=1, Macro0, CA PI delay=34
1402 10:57:34.484208
1403 10:57:34.487152 [CBTSetCACLKResult] CA Dly = 34
1404 10:57:34.487257 CS Dly: 7 (0~38)
1405 10:57:34.487365 ==
1406 10:57:34.490712 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 10:57:34.497567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 10:57:34.497671 ==
1409 10:57:34.500871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 10:57:34.507149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 10:57:34.516742 [CA 0] Center 36 (6~67) winsize 62
1412 10:57:34.520641 [CA 1] Center 37 (6~68) winsize 63
1413 10:57:34.524594 [CA 2] Center 35 (5~66) winsize 62
1414 10:57:34.527712 [CA 3] Center 34 (4~65) winsize 62
1415 10:57:34.531538 [CA 4] Center 35 (5~66) winsize 62
1416 10:57:34.536086 [CA 5] Center 34 (4~65) winsize 62
1417 10:57:34.536168
1418 10:57:34.539422 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 10:57:34.539530
1420 10:57:34.543461 [CATrainingPosCal] consider 2 rank data
1421 10:57:34.543536 u2DelayCellTimex100 = 270/100 ps
1422 10:57:34.546658 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 10:57:34.551252 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 10:57:34.554355 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1425 10:57:34.557671 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 10:57:34.561141 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 10:57:34.567892 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 10:57:34.568369
1429 10:57:34.571737 CA PerBit enable=1, Macro0, CA PI delay=34
1430 10:57:34.572157
1431 10:57:34.574982 [CBTSetCACLKResult] CA Dly = 34
1432 10:57:34.575588 CS Dly: 7 (0~38)
1433 10:57:34.576124
1434 10:57:34.578319 ----->DramcWriteLeveling(PI) begin...
1435 10:57:34.578747 ==
1436 10:57:34.581565 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 10:57:34.584684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 10:57:34.588239 ==
1439 10:57:34.588659 Write leveling (Byte 0): 23 => 23
1440 10:57:34.591193 Write leveling (Byte 1): 25 => 25
1441 10:57:34.594977 DramcWriteLeveling(PI) end<-----
1442 10:57:34.595435
1443 10:57:34.595778 ==
1444 10:57:34.597962 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 10:57:34.604850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 10:57:34.605392 ==
1447 10:57:34.605812 [Gating] SW mode calibration
1448 10:57:34.615052 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 10:57:34.618183 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 10:57:34.621491 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 10:57:34.628514 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1452 10:57:34.631523 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:57:34.634851 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:57:34.641621 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:57:34.645474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:57:34.648802 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:57:34.654719 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:57:34.658370 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:57:34.661725 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:57:34.668614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:57:34.671564 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:57:34.675038 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:57:34.681460 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:57:34.685387 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:57:34.688820 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:57:34.691503 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 10:57:34.698447 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 10:57:34.701732 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:57:34.704705 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:57:34.711549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:57:34.714780 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:57:34.718499 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:57:34.725271 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:57:34.728123 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:57:34.731383 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1476 10:57:34.738590 0 9 8 | B1->B0 | 2c2c 3333 | 1 1 | (1 1) (1 1)
1477 10:57:34.741470 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 10:57:34.744704 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:57:34.752294 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:57:34.755298 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 10:57:34.758699 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 10:57:34.765048 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1483 10:57:34.768194 0 10 4 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
1484 10:57:34.771596 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:57:34.778501 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:57:34.781571 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:57:34.784799 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:57:34.788794 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:57:34.794969 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:57:34.798782 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1491 10:57:34.801852 0 11 4 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (0 0)
1492 10:57:34.808243 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1493 10:57:34.811571 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 10:57:34.814649 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:57:34.821518 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:57:34.824808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 10:57:34.828567 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 10:57:34.834628 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 10:57:34.838419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 10:57:34.841688 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 10:57:34.848573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:57:34.851752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:57:34.854994 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:57:34.862202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:57:34.865399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:57:34.868848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:57:34.872173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:57:34.878822 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:57:34.882021 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:57:34.885090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:57:34.891849 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:57:34.895003 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:57:34.898317 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:57:34.905220 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:57:34.908331 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 10:57:34.911786 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 10:57:34.915394 Total UI for P1: 0, mck2ui 16
1518 10:57:34.918462 best dqsien dly found for B0: ( 0, 14, 4)
1519 10:57:34.922207 Total UI for P1: 0, mck2ui 16
1520 10:57:34.925249 best dqsien dly found for B1: ( 0, 14, 4)
1521 10:57:34.928569 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 10:57:34.932241 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 10:57:34.932753
1524 10:57:34.935422 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 10:57:34.941797 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 10:57:34.942288 [Gating] SW calibration Done
1527 10:57:34.942631 ==
1528 10:57:34.945447 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 10:57:34.951918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 10:57:34.952349 ==
1531 10:57:34.952685 RX Vref Scan: 0
1532 10:57:34.952999
1533 10:57:34.955685 RX Vref 0 -> 0, step: 1
1534 10:57:34.956346
1535 10:57:34.959065 RX Delay -130 -> 252, step: 16
1536 10:57:34.962433 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 10:57:34.965890 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 10:57:34.968833 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1539 10:57:34.972046 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 10:57:34.979496 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 10:57:34.982534 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 10:57:34.985856 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1543 10:57:34.989170 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 10:57:34.992294 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1545 10:57:34.999127 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1546 10:57:35.002367 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 10:57:35.005350 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 10:57:35.009132 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 10:57:35.012291 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 10:57:35.019401 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 10:57:35.022325 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 10:57:35.022869 ==
1553 10:57:35.026005 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 10:57:35.029207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 10:57:35.029578 ==
1556 10:57:35.032709 DQS Delay:
1557 10:57:35.033219 DQS0 = 0, DQS1 = 0
1558 10:57:35.033561 DQM Delay:
1559 10:57:35.035714 DQM0 = 93, DQM1 = 89
1560 10:57:35.036139 DQ Delay:
1561 10:57:35.039603 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1562 10:57:35.042264 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1563 10:57:35.046165 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1564 10:57:35.049406 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 10:57:35.049834
1566 10:57:35.050166
1567 10:57:35.050473 ==
1568 10:57:35.052563 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 10:57:35.059263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 10:57:35.059733 ==
1571 10:57:35.060073
1572 10:57:35.060384
1573 10:57:35.060805 TX Vref Scan disable
1574 10:57:35.062330 == TX Byte 0 ==
1575 10:57:35.066057 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1576 10:57:35.069248 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1577 10:57:35.072788 == TX Byte 1 ==
1578 10:57:35.076030 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1579 10:57:35.079416 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1580 10:57:35.082736 ==
1581 10:57:35.085892 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 10:57:35.089182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 10:57:35.089617 ==
1584 10:57:35.101831 TX Vref=22, minBit 1, minWin=26, winSum=434
1585 10:57:35.105366 TX Vref=24, minBit 0, minWin=27, winSum=442
1586 10:57:35.108456 TX Vref=26, minBit 5, minWin=27, winSum=446
1587 10:57:35.111640 TX Vref=28, minBit 5, minWin=27, winSum=451
1588 10:57:35.115582 TX Vref=30, minBit 0, minWin=27, winSum=452
1589 10:57:35.118925 TX Vref=32, minBit 0, minWin=27, winSum=447
1590 10:57:35.125616 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30
1591 10:57:35.126191
1592 10:57:35.128709 Final TX Range 1 Vref 30
1593 10:57:35.129166
1594 10:57:35.129583 ==
1595 10:57:35.131718 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 10:57:35.135401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 10:57:35.135851 ==
1598 10:57:35.136190
1599 10:57:35.136505
1600 10:57:35.138455 TX Vref Scan disable
1601 10:57:35.142144 == TX Byte 0 ==
1602 10:57:35.145671 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1603 10:57:35.148640 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1604 10:57:35.151992 == TX Byte 1 ==
1605 10:57:35.155407 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1606 10:57:35.158812 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1607 10:57:35.159238
1608 10:57:35.161870 [DATLAT]
1609 10:57:35.162288 Freq=800, CH1 RK0
1610 10:57:35.162622
1611 10:57:35.165610 DATLAT Default: 0xa
1612 10:57:35.166033 0, 0xFFFF, sum = 0
1613 10:57:35.168667 1, 0xFFFF, sum = 0
1614 10:57:35.169235 2, 0xFFFF, sum = 0
1615 10:57:35.172242 3, 0xFFFF, sum = 0
1616 10:57:35.172668 4, 0xFFFF, sum = 0
1617 10:57:35.175671 5, 0xFFFF, sum = 0
1618 10:57:35.176269 6, 0xFFFF, sum = 0
1619 10:57:35.178456 7, 0xFFFF, sum = 0
1620 10:57:35.178881 8, 0xFFFF, sum = 0
1621 10:57:35.182129 9, 0x0, sum = 1
1622 10:57:35.182551 10, 0x0, sum = 2
1623 10:57:35.185414 11, 0x0, sum = 3
1624 10:57:35.185839 12, 0x0, sum = 4
1625 10:57:35.188707 best_step = 10
1626 10:57:35.189170
1627 10:57:35.189506 ==
1628 10:57:35.192017 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 10:57:35.195198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 10:57:35.195704 ==
1631 10:57:35.196041 RX Vref Scan: 1
1632 10:57:35.198532
1633 10:57:35.198949 Set Vref Range= 32 -> 127
1634 10:57:35.199281
1635 10:57:35.201878 RX Vref 32 -> 127, step: 1
1636 10:57:35.202297
1637 10:57:35.205158 RX Delay -63 -> 252, step: 8
1638 10:57:35.205577
1639 10:57:35.208280 Set Vref, RX VrefLevel [Byte0]: 32
1640 10:57:35.211944 [Byte1]: 32
1641 10:57:35.212453
1642 10:57:35.215215 Set Vref, RX VrefLevel [Byte0]: 33
1643 10:57:35.218407 [Byte1]: 33
1644 10:57:35.218888
1645 10:57:35.221672 Set Vref, RX VrefLevel [Byte0]: 34
1646 10:57:35.224987 [Byte1]: 34
1647 10:57:35.228990
1648 10:57:35.229407 Set Vref, RX VrefLevel [Byte0]: 35
1649 10:57:35.232198 [Byte1]: 35
1650 10:57:35.236422
1651 10:57:35.236973 Set Vref, RX VrefLevel [Byte0]: 36
1652 10:57:35.239606 [Byte1]: 36
1653 10:57:35.244018
1654 10:57:35.244438 Set Vref, RX VrefLevel [Byte0]: 37
1655 10:57:35.246935 [Byte1]: 37
1656 10:57:35.251422
1657 10:57:35.251842 Set Vref, RX VrefLevel [Byte0]: 38
1658 10:57:35.254660 [Byte1]: 38
1659 10:57:35.259148
1660 10:57:35.259603 Set Vref, RX VrefLevel [Byte0]: 39
1661 10:57:35.262342 [Byte1]: 39
1662 10:57:35.266044
1663 10:57:35.266556 Set Vref, RX VrefLevel [Byte0]: 40
1664 10:57:35.269396 [Byte1]: 40
1665 10:57:35.274013
1666 10:57:35.274549 Set Vref, RX VrefLevel [Byte0]: 41
1667 10:57:35.277349 [Byte1]: 41
1668 10:57:35.281371
1669 10:57:35.282012 Set Vref, RX VrefLevel [Byte0]: 42
1670 10:57:35.284553 [Byte1]: 42
1671 10:57:35.288911
1672 10:57:35.289466 Set Vref, RX VrefLevel [Byte0]: 43
1673 10:57:35.291874 [Byte1]: 43
1674 10:57:35.296577
1675 10:57:35.296995 Set Vref, RX VrefLevel [Byte0]: 44
1676 10:57:35.299885 [Byte1]: 44
1677 10:57:35.303874
1678 10:57:35.304316 Set Vref, RX VrefLevel [Byte0]: 45
1679 10:57:35.307228 [Byte1]: 45
1680 10:57:35.311967
1681 10:57:35.312492 Set Vref, RX VrefLevel [Byte0]: 46
1682 10:57:35.314919 [Byte1]: 46
1683 10:57:35.318955
1684 10:57:35.319536 Set Vref, RX VrefLevel [Byte0]: 47
1685 10:57:35.322040 [Byte1]: 47
1686 10:57:35.326753
1687 10:57:35.327269 Set Vref, RX VrefLevel [Byte0]: 48
1688 10:57:35.330066 [Byte1]: 48
1689 10:57:35.334147
1690 10:57:35.334660 Set Vref, RX VrefLevel [Byte0]: 49
1691 10:57:35.337420 [Byte1]: 49
1692 10:57:35.341622
1693 10:57:35.342041 Set Vref, RX VrefLevel [Byte0]: 50
1694 10:57:35.344709 [Byte1]: 50
1695 10:57:35.348705
1696 10:57:35.349142 Set Vref, RX VrefLevel [Byte0]: 51
1697 10:57:35.351964 [Byte1]: 51
1698 10:57:35.356264
1699 10:57:35.356684 Set Vref, RX VrefLevel [Byte0]: 52
1700 10:57:35.359468 [Byte1]: 52
1701 10:57:35.363708
1702 10:57:35.364125 Set Vref, RX VrefLevel [Byte0]: 53
1703 10:57:35.366812 [Byte1]: 53
1704 10:57:35.371232
1705 10:57:35.371697 Set Vref, RX VrefLevel [Byte0]: 54
1706 10:57:35.374634 [Byte1]: 54
1707 10:57:35.379024
1708 10:57:35.379506 Set Vref, RX VrefLevel [Byte0]: 55
1709 10:57:35.382384 [Byte1]: 55
1710 10:57:35.386556
1711 10:57:35.387168 Set Vref, RX VrefLevel [Byte0]: 56
1712 10:57:35.389676 [Byte1]: 56
1713 10:57:35.394114
1714 10:57:35.394540 Set Vref, RX VrefLevel [Byte0]: 57
1715 10:57:35.397207 [Byte1]: 57
1716 10:57:35.401525
1717 10:57:35.401948 Set Vref, RX VrefLevel [Byte0]: 58
1718 10:57:35.404835 [Byte1]: 58
1719 10:57:35.408740
1720 10:57:35.409153 Set Vref, RX VrefLevel [Byte0]: 59
1721 10:57:35.411914 [Byte1]: 59
1722 10:57:35.416579
1723 10:57:35.416993 Set Vref, RX VrefLevel [Byte0]: 60
1724 10:57:35.419780 [Byte1]: 60
1725 10:57:35.423595
1726 10:57:35.424006 Set Vref, RX VrefLevel [Byte0]: 61
1727 10:57:35.427037 [Byte1]: 61
1728 10:57:35.431384
1729 10:57:35.431809 Set Vref, RX VrefLevel [Byte0]: 62
1730 10:57:35.434856 [Byte1]: 62
1731 10:57:35.438873
1732 10:57:35.439297 Set Vref, RX VrefLevel [Byte0]: 63
1733 10:57:35.442072 [Byte1]: 63
1734 10:57:35.446506
1735 10:57:35.447165 Set Vref, RX VrefLevel [Byte0]: 64
1736 10:57:35.449600 [Byte1]: 64
1737 10:57:35.454147
1738 10:57:35.454665 Set Vref, RX VrefLevel [Byte0]: 65
1739 10:57:35.457714 [Byte1]: 65
1740 10:57:35.461475
1741 10:57:35.461984 Set Vref, RX VrefLevel [Byte0]: 66
1742 10:57:35.464583 [Byte1]: 66
1743 10:57:35.468749
1744 10:57:35.469177 Set Vref, RX VrefLevel [Byte0]: 67
1745 10:57:35.472500 [Byte1]: 67
1746 10:57:35.476074
1747 10:57:35.476495 Set Vref, RX VrefLevel [Byte0]: 68
1748 10:57:35.479858 [Byte1]: 68
1749 10:57:35.483820
1750 10:57:35.484401 Set Vref, RX VrefLevel [Byte0]: 69
1751 10:57:35.487084 [Byte1]: 69
1752 10:57:35.491503
1753 10:57:35.491927 Set Vref, RX VrefLevel [Byte0]: 70
1754 10:57:35.494661 [Byte1]: 70
1755 10:57:35.498895
1756 10:57:35.499313 Final RX Vref Byte 0 = 59 to rank0
1757 10:57:35.502116 Final RX Vref Byte 1 = 54 to rank0
1758 10:57:35.505399 Final RX Vref Byte 0 = 59 to rank1
1759 10:57:35.509156 Final RX Vref Byte 1 = 54 to rank1==
1760 10:57:35.512327 Dram Type= 6, Freq= 0, CH_1, rank 0
1761 10:57:35.515180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1762 10:57:35.518595 ==
1763 10:57:35.519066 DQS Delay:
1764 10:57:35.519625 DQS0 = 0, DQS1 = 0
1765 10:57:35.522342 DQM Delay:
1766 10:57:35.522765 DQM0 = 95, DQM1 = 90
1767 10:57:35.525521 DQ Delay:
1768 10:57:35.528915 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1769 10:57:35.532238 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
1770 10:57:35.535404 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1771 10:57:35.538704 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96
1772 10:57:35.539128
1773 10:57:35.539510
1774 10:57:35.545364 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1775 10:57:35.548769 CH1 RK0: MR19=606, MR18=2945
1776 10:57:35.555738 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1777 10:57:35.556410
1778 10:57:35.559071 ----->DramcWriteLeveling(PI) begin...
1779 10:57:35.559711 ==
1780 10:57:35.562366 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 10:57:35.565731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 10:57:35.566158 ==
1783 10:57:35.569084 Write leveling (Byte 0): 26 => 26
1784 10:57:35.572193 Write leveling (Byte 1): 28 => 28
1785 10:57:35.576032 DramcWriteLeveling(PI) end<-----
1786 10:57:35.576548
1787 10:57:35.577062 ==
1788 10:57:35.579043 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 10:57:35.582111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 10:57:35.582693 ==
1791 10:57:35.585623 [Gating] SW mode calibration
1792 10:57:35.592540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1793 10:57:35.598883 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1794 10:57:35.602223 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1795 10:57:35.605469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1796 10:57:35.612422 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 10:57:35.615632 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 10:57:35.618789 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 10:57:35.625450 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 10:57:35.628673 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 10:57:35.632106 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 10:57:35.638896 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 10:57:35.642521 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 10:57:35.645881 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 10:57:35.652351 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 10:57:35.655413 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 10:57:35.658693 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 10:57:35.665180 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 10:57:35.668617 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 10:57:35.672538 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1811 10:57:35.679170 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1812 10:57:35.682375 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:57:35.685381 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:57:35.688951 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:57:35.695759 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:57:35.698737 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:57:35.702499 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:57:35.708777 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:57:35.712449 0 9 4 | B1->B0 | 2f2f 2323 | 0 1 | (0 0) (1 1)
1820 10:57:35.715588 0 9 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 1)
1821 10:57:35.722215 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 10:57:35.725172 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 10:57:35.729010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 10:57:35.735564 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 10:57:35.738999 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 10:57:35.742213 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1827 10:57:35.748891 0 10 4 | B1->B0 | 2a2a 3131 | 0 0 | (1 0) (0 1)
1828 10:57:35.752148 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1829 10:57:35.755611 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:57:35.762329 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:57:35.765719 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:57:35.769075 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:57:35.772352 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:57:35.778922 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:57:35.782312 0 11 4 | B1->B0 | 3c3c 3030 | 0 0 | (0 0) (0 0)
1836 10:57:35.785682 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1837 10:57:35.792731 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 10:57:35.795205 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 10:57:35.798789 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 10:57:35.805084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 10:57:35.808693 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 10:57:35.811888 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 10:57:35.818911 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1844 10:57:35.822008 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 10:57:35.825696 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 10:57:35.829057 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 10:57:35.835295 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 10:57:35.839089 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 10:57:35.842348 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 10:57:35.848844 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 10:57:35.852247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 10:57:35.855473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 10:57:35.862124 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 10:57:35.866019 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 10:57:35.869234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 10:57:35.875724 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 10:57:35.879054 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 10:57:35.882307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1859 10:57:35.889002 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 10:57:35.889099 Total UI for P1: 0, mck2ui 16
1861 10:57:35.895599 best dqsien dly found for B0: ( 0, 14, 0)
1862 10:57:35.895682 Total UI for P1: 0, mck2ui 16
1863 10:57:35.899282 best dqsien dly found for B1: ( 0, 14, 2)
1864 10:57:35.905573 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1865 10:57:35.909306 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1866 10:57:35.909387
1867 10:57:35.912448 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1868 10:57:35.915506 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1869 10:57:35.919030 [Gating] SW calibration Done
1870 10:57:35.919110 ==
1871 10:57:35.922149 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 10:57:35.925501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 10:57:35.925582 ==
1874 10:57:35.925646 RX Vref Scan: 0
1875 10:57:35.925720
1876 10:57:35.929262 RX Vref 0 -> 0, step: 1
1877 10:57:35.929343
1878 10:57:35.932346 RX Delay -130 -> 252, step: 16
1879 10:57:35.935435 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1880 10:57:35.939265 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1881 10:57:35.945609 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1882 10:57:35.949233 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1883 10:57:35.952514 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1884 10:57:35.955872 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1885 10:57:35.959097 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1886 10:57:35.965652 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1887 10:57:35.969434 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1888 10:57:35.972549 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1889 10:57:35.975925 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1890 10:57:35.979105 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1891 10:57:35.986312 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1892 10:57:35.989747 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1893 10:57:35.993035 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1894 10:57:35.996430 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1895 10:57:35.996512 ==
1896 10:57:35.999250 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 10:57:36.002977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 10:57:36.006295 ==
1899 10:57:36.006379 DQS Delay:
1900 10:57:36.006462 DQS0 = 0, DQS1 = 0
1901 10:57:36.009502 DQM Delay:
1902 10:57:36.009586 DQM0 = 92, DQM1 = 87
1903 10:57:36.012810 DQ Delay:
1904 10:57:36.012894 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1905 10:57:36.015943 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1906 10:57:36.019562 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1907 10:57:36.022633 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1908 10:57:36.026164
1909 10:57:36.026248
1910 10:57:36.026332 ==
1911 10:57:36.029248 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 10:57:36.033077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 10:57:36.033163 ==
1914 10:57:36.033247
1915 10:57:36.033327
1916 10:57:36.036216 TX Vref Scan disable
1917 10:57:36.036299 == TX Byte 0 ==
1918 10:57:36.043270 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1919 10:57:36.046432 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1920 10:57:36.046517 == TX Byte 1 ==
1921 10:57:36.052855 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1922 10:57:36.056052 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1923 10:57:36.056136 ==
1924 10:57:36.059679 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 10:57:36.062863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 10:57:36.062981 ==
1927 10:57:36.076499 TX Vref=22, minBit 1, minWin=26, winSum=442
1928 10:57:36.079614 TX Vref=24, minBit 5, minWin=26, winSum=445
1929 10:57:36.082986 TX Vref=26, minBit 2, minWin=27, winSum=450
1930 10:57:36.086123 TX Vref=28, minBit 2, minWin=27, winSum=449
1931 10:57:36.089996 TX Vref=30, minBit 2, minWin=27, winSum=448
1932 10:57:36.093151 TX Vref=32, minBit 0, minWin=27, winSum=447
1933 10:57:36.099707 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 26
1934 10:57:36.099789
1935 10:57:36.103035 Final TX Range 1 Vref 26
1936 10:57:36.103116
1937 10:57:36.103180 ==
1938 10:57:36.106421 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 10:57:36.109484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 10:57:36.109566 ==
1941 10:57:36.109630
1942 10:57:36.112759
1943 10:57:36.112840 TX Vref Scan disable
1944 10:57:36.116656 == TX Byte 0 ==
1945 10:57:36.120034 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1946 10:57:36.123106 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1947 10:57:36.126283 == TX Byte 1 ==
1948 10:57:36.129478 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1949 10:57:36.133289 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1950 10:57:36.133365
1951 10:57:36.136368 [DATLAT]
1952 10:57:36.136443 Freq=800, CH1 RK1
1953 10:57:36.136506
1954 10:57:36.140128 DATLAT Default: 0xa
1955 10:57:36.140201 0, 0xFFFF, sum = 0
1956 10:57:36.143118 1, 0xFFFF, sum = 0
1957 10:57:36.143189 2, 0xFFFF, sum = 0
1958 10:57:36.146449 3, 0xFFFF, sum = 0
1959 10:57:36.146528 4, 0xFFFF, sum = 0
1960 10:57:36.149528 5, 0xFFFF, sum = 0
1961 10:57:36.149611 6, 0xFFFF, sum = 0
1962 10:57:36.152665 7, 0xFFFF, sum = 0
1963 10:57:36.156657 8, 0xFFFF, sum = 0
1964 10:57:36.156740 9, 0x0, sum = 1
1965 10:57:36.156805 10, 0x0, sum = 2
1966 10:57:36.159291 11, 0x0, sum = 3
1967 10:57:36.159421 12, 0x0, sum = 4
1968 10:57:36.163117 best_step = 10
1969 10:57:36.163198
1970 10:57:36.163261 ==
1971 10:57:36.166144 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 10:57:36.169865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 10:57:36.169948 ==
1974 10:57:36.173020 RX Vref Scan: 0
1975 10:57:36.173106
1976 10:57:36.173171 RX Vref 0 -> 0, step: 1
1977 10:57:36.173232
1978 10:57:36.176503 RX Delay -79 -> 252, step: 8
1979 10:57:36.182855 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1980 10:57:36.186063 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1981 10:57:36.190037 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1982 10:57:36.192920 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1983 10:57:36.196089 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1984 10:57:36.199983 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1985 10:57:36.206635 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1986 10:57:36.209964 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1987 10:57:36.213145 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1988 10:57:36.216363 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1989 10:57:36.220186 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1990 10:57:36.226771 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1991 10:57:36.229891 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1992 10:57:36.233104 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1993 10:57:36.236753 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1994 10:57:36.239830 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1995 10:57:36.239912 ==
1996 10:57:36.243475 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 10:57:36.250397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 10:57:36.250480 ==
1999 10:57:36.250546 DQS Delay:
2000 10:57:36.252998 DQS0 = 0, DQS1 = 0
2001 10:57:36.253081 DQM Delay:
2002 10:57:36.253145 DQM0 = 97, DQM1 = 91
2003 10:57:36.256780 DQ Delay:
2004 10:57:36.259996 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2005 10:57:36.263173 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2006 10:57:36.266470 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2007 10:57:36.269680 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2008 10:57:36.269760
2009 10:57:36.269827
2010 10:57:36.276709 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2011 10:57:36.280010 CH1 RK1: MR19=606, MR18=4913
2012 10:57:36.286849 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2013 10:57:36.290043 [RxdqsGatingPostProcess] freq 800
2014 10:57:36.293438 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2015 10:57:36.296671 Pre-setting of DQS Precalculation
2016 10:57:36.303468 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2017 10:57:36.309768 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2018 10:57:36.316342 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2019 10:57:36.316430
2020 10:57:36.316495
2021 10:57:36.320155 [Calibration Summary] 1600 Mbps
2022 10:57:36.320232 CH 0, Rank 0
2023 10:57:36.323432 SW Impedance : PASS
2024 10:57:36.326966 DUTY Scan : NO K
2025 10:57:36.327039 ZQ Calibration : PASS
2026 10:57:36.330132 Jitter Meter : NO K
2027 10:57:36.333462 CBT Training : PASS
2028 10:57:36.333544 Write leveling : PASS
2029 10:57:36.336669 RX DQS gating : PASS
2030 10:57:36.339678 RX DQ/DQS(RDDQC) : PASS
2031 10:57:36.339760 TX DQ/DQS : PASS
2032 10:57:36.343391 RX DATLAT : PASS
2033 10:57:36.343473 RX DQ/DQS(Engine): PASS
2034 10:57:36.346479 TX OE : NO K
2035 10:57:36.346568 All Pass.
2036 10:57:36.346634
2037 10:57:36.350288 CH 0, Rank 1
2038 10:57:36.350392 SW Impedance : PASS
2039 10:57:36.353374 DUTY Scan : NO K
2040 10:57:36.357065 ZQ Calibration : PASS
2041 10:57:36.357148 Jitter Meter : NO K
2042 10:57:36.360293 CBT Training : PASS
2043 10:57:36.363560 Write leveling : PASS
2044 10:57:36.363648 RX DQS gating : PASS
2045 10:57:36.367250 RX DQ/DQS(RDDQC) : PASS
2046 10:57:36.370452 TX DQ/DQS : PASS
2047 10:57:36.370535 RX DATLAT : PASS
2048 10:57:36.373734 RX DQ/DQS(Engine): PASS
2049 10:57:36.373817 TX OE : NO K
2050 10:57:36.376871 All Pass.
2051 10:57:36.376953
2052 10:57:36.377017 CH 1, Rank 0
2053 10:57:36.380658 SW Impedance : PASS
2054 10:57:36.380833 DUTY Scan : NO K
2055 10:57:36.383877 ZQ Calibration : PASS
2056 10:57:36.386991 Jitter Meter : NO K
2057 10:57:36.387072 CBT Training : PASS
2058 10:57:36.390277 Write leveling : PASS
2059 10:57:36.394010 RX DQS gating : PASS
2060 10:57:36.394093 RX DQ/DQS(RDDQC) : PASS
2061 10:57:36.397258 TX DQ/DQS : PASS
2062 10:57:36.400751 RX DATLAT : PASS
2063 10:57:36.400834 RX DQ/DQS(Engine): PASS
2064 10:57:36.403506 TX OE : NO K
2065 10:57:36.403589 All Pass.
2066 10:57:36.403654
2067 10:57:36.407482 CH 1, Rank 1
2068 10:57:36.407565 SW Impedance : PASS
2069 10:57:36.410071 DUTY Scan : NO K
2070 10:57:36.413373 ZQ Calibration : PASS
2071 10:57:36.413455 Jitter Meter : NO K
2072 10:57:36.417320 CBT Training : PASS
2073 10:57:36.417406 Write leveling : PASS
2074 10:57:36.420564 RX DQS gating : PASS
2075 10:57:36.423981 RX DQ/DQS(RDDQC) : PASS
2076 10:57:36.424072 TX DQ/DQS : PASS
2077 10:57:36.427138 RX DATLAT : PASS
2078 10:57:36.430359 RX DQ/DQS(Engine): PASS
2079 10:57:36.430441 TX OE : NO K
2080 10:57:36.433644 All Pass.
2081 10:57:36.433725
2082 10:57:36.433791 DramC Write-DBI off
2083 10:57:36.436929 PER_BANK_REFRESH: Hybrid Mode
2084 10:57:36.437041 TX_TRACKING: ON
2085 10:57:36.440902 [GetDramInforAfterCalByMRR] Vendor 6.
2086 10:57:36.447288 [GetDramInforAfterCalByMRR] Revision 606.
2087 10:57:36.450437 [GetDramInforAfterCalByMRR] Revision 2 0.
2088 10:57:36.450548 MR0 0x3b3b
2089 10:57:36.450640 MR8 0x5151
2090 10:57:36.454011 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2091 10:57:36.454120
2092 10:57:36.457110 MR0 0x3b3b
2093 10:57:36.457201 MR8 0x5151
2094 10:57:36.460675 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 10:57:36.460753
2096 10:57:36.470492 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2097 10:57:36.474072 [FAST_K] Save calibration result to emmc
2098 10:57:36.476999 [FAST_K] Save calibration result to emmc
2099 10:57:36.480710 dram_init: config_dvfs: 1
2100 10:57:36.483872 dramc_set_vcore_voltage set vcore to 662500
2101 10:57:36.487185 Read voltage for 1200, 2
2102 10:57:36.487262 Vio18 = 0
2103 10:57:36.487337 Vcore = 662500
2104 10:57:36.490461 Vdram = 0
2105 10:57:36.490558 Vddq = 0
2106 10:57:36.490622 Vmddr = 0
2107 10:57:36.497295 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2108 10:57:36.500550 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2109 10:57:36.503793 MEM_TYPE=3, freq_sel=15
2110 10:57:36.507087 sv_algorithm_assistance_LP4_1600
2111 10:57:36.510898 ============ PULL DRAM RESETB DOWN ============
2112 10:57:36.514115 ========== PULL DRAM RESETB DOWN end =========
2113 10:57:36.520778 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 10:57:36.524191 ===================================
2115 10:57:36.524280 LPDDR4 DRAM CONFIGURATION
2116 10:57:36.527224 ===================================
2117 10:57:36.530387 EX_ROW_EN[0] = 0x0
2118 10:57:36.533712 EX_ROW_EN[1] = 0x0
2119 10:57:36.533792 LP4Y_EN = 0x0
2120 10:57:36.536934 WORK_FSP = 0x0
2121 10:57:36.537014 WL = 0x4
2122 10:57:36.540296 RL = 0x4
2123 10:57:36.540382 BL = 0x2
2124 10:57:36.543609 RPST = 0x0
2125 10:57:36.543687 RD_PRE = 0x0
2126 10:57:36.546981 WR_PRE = 0x1
2127 10:57:36.547065 WR_PST = 0x0
2128 10:57:36.550255 DBI_WR = 0x0
2129 10:57:36.550334 DBI_RD = 0x0
2130 10:57:36.554043 OTF = 0x1
2131 10:57:36.556981 ===================================
2132 10:57:36.560262 ===================================
2133 10:57:36.560348 ANA top config
2134 10:57:36.563998 ===================================
2135 10:57:36.567020 DLL_ASYNC_EN = 0
2136 10:57:36.570871 ALL_SLAVE_EN = 0
2137 10:57:36.570946 NEW_RANK_MODE = 1
2138 10:57:36.573974 DLL_IDLE_MODE = 1
2139 10:57:36.577305 LP45_APHY_COMB_EN = 1
2140 10:57:36.580488 TX_ODT_DIS = 1
2141 10:57:36.580569 NEW_8X_MODE = 1
2142 10:57:36.584118 ===================================
2143 10:57:36.587240 ===================================
2144 10:57:36.591112 data_rate = 2400
2145 10:57:36.594237 CKR = 1
2146 10:57:36.597591 DQ_P2S_RATIO = 8
2147 10:57:36.600596 ===================================
2148 10:57:36.604381 CA_P2S_RATIO = 8
2149 10:57:36.607590 DQ_CA_OPEN = 0
2150 10:57:36.607673 DQ_SEMI_OPEN = 0
2151 10:57:36.610884 CA_SEMI_OPEN = 0
2152 10:57:36.614168 CA_FULL_RATE = 0
2153 10:57:36.617435 DQ_CKDIV4_EN = 0
2154 10:57:36.620619 CA_CKDIV4_EN = 0
2155 10:57:36.624026 CA_PREDIV_EN = 0
2156 10:57:36.624115 PH8_DLY = 17
2157 10:57:36.627471 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2158 10:57:36.630724 DQ_AAMCK_DIV = 4
2159 10:57:36.634510 CA_AAMCK_DIV = 4
2160 10:57:36.637787 CA_ADMCK_DIV = 4
2161 10:57:36.641116 DQ_TRACK_CA_EN = 0
2162 10:57:36.641207 CA_PICK = 1200
2163 10:57:36.644485 CA_MCKIO = 1200
2164 10:57:36.647762 MCKIO_SEMI = 0
2165 10:57:36.651149 PLL_FREQ = 2366
2166 10:57:36.654363 DQ_UI_PI_RATIO = 32
2167 10:57:36.657654 CA_UI_PI_RATIO = 0
2168 10:57:36.660915 ===================================
2169 10:57:36.664056 ===================================
2170 10:57:36.664140 memory_type:LPDDR4
2171 10:57:36.667730 GP_NUM : 10
2172 10:57:36.670656 SRAM_EN : 1
2173 10:57:36.670770 MD32_EN : 0
2174 10:57:36.674413 ===================================
2175 10:57:36.677570 [ANA_INIT] >>>>>>>>>>>>>>
2176 10:57:36.681322 <<<<<< [CONFIGURE PHASE]: ANA_TX
2177 10:57:36.684481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2178 10:57:36.687754 ===================================
2179 10:57:36.691037 data_rate = 2400,PCW = 0X5b00
2180 10:57:36.694637 ===================================
2181 10:57:36.697767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2182 10:57:36.700798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 10:57:36.707870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 10:57:36.710801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2185 10:57:36.714348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2186 10:57:36.717635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2187 10:57:36.721033 [ANA_INIT] flow start
2188 10:57:36.724328 [ANA_INIT] PLL >>>>>>>>
2189 10:57:36.724409 [ANA_INIT] PLL <<<<<<<<
2190 10:57:36.727577 [ANA_INIT] MIDPI >>>>>>>>
2191 10:57:36.730954 [ANA_INIT] MIDPI <<<<<<<<
2192 10:57:36.731035 [ANA_INIT] DLL >>>>>>>>
2193 10:57:36.734728 [ANA_INIT] DLL <<<<<<<<
2194 10:57:36.737906 [ANA_INIT] flow end
2195 10:57:36.741301 ============ LP4 DIFF to SE enter ============
2196 10:57:36.744570 ============ LP4 DIFF to SE exit ============
2197 10:57:36.747916 [ANA_INIT] <<<<<<<<<<<<<
2198 10:57:36.751155 [Flow] Enable top DCM control >>>>>
2199 10:57:36.754508 [Flow] Enable top DCM control <<<<<
2200 10:57:36.757681 Enable DLL master slave shuffle
2201 10:57:36.761079 ==============================================================
2202 10:57:36.764326 Gating Mode config
2203 10:57:36.771273 ==============================================================
2204 10:57:36.771454 Config description:
2205 10:57:36.781032 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2206 10:57:36.787768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2207 10:57:36.791679 SELPH_MODE 0: By rank 1: By Phase
2208 10:57:36.798291 ==============================================================
2209 10:57:36.801427 GAT_TRACK_EN = 1
2210 10:57:36.804530 RX_GATING_MODE = 2
2211 10:57:36.807874 RX_GATING_TRACK_MODE = 2
2212 10:57:36.811669 SELPH_MODE = 1
2213 10:57:36.814824 PICG_EARLY_EN = 1
2214 10:57:36.814924 VALID_LAT_VALUE = 1
2215 10:57:36.821609 ==============================================================
2216 10:57:36.824943 Enter into Gating configuration >>>>
2217 10:57:36.828063 Exit from Gating configuration <<<<
2218 10:57:36.831611 Enter into DVFS_PRE_config >>>>>
2219 10:57:36.841331 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2220 10:57:36.844640 Exit from DVFS_PRE_config <<<<<
2221 10:57:36.847992 Enter into PICG configuration >>>>
2222 10:57:36.851371 Exit from PICG configuration <<<<
2223 10:57:36.854696 [RX_INPUT] configuration >>>>>
2224 10:57:36.857876 [RX_INPUT] configuration <<<<<
2225 10:57:36.864414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2226 10:57:36.867832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2227 10:57:36.874514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2228 10:57:36.881284 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2229 10:57:36.888240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 10:57:36.894457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 10:57:36.897689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2232 10:57:36.900941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2233 10:57:36.904339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2234 10:57:36.907649 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2235 10:57:36.915042 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2236 10:57:36.917810 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2237 10:57:36.921451 ===================================
2238 10:57:36.924454 LPDDR4 DRAM CONFIGURATION
2239 10:57:36.928305 ===================================
2240 10:57:36.928400 EX_ROW_EN[0] = 0x0
2241 10:57:36.931594 EX_ROW_EN[1] = 0x0
2242 10:57:36.931678 LP4Y_EN = 0x0
2243 10:57:36.934841 WORK_FSP = 0x0
2244 10:57:36.934925 WL = 0x4
2245 10:57:36.938047 RL = 0x4
2246 10:57:36.938131 BL = 0x2
2247 10:57:36.941246 RPST = 0x0
2248 10:57:36.941328 RD_PRE = 0x0
2249 10:57:36.944400 WR_PRE = 0x1
2250 10:57:36.944482 WR_PST = 0x0
2251 10:57:36.947802 DBI_WR = 0x0
2252 10:57:36.951202 DBI_RD = 0x0
2253 10:57:36.951284 OTF = 0x1
2254 10:57:36.954615 ===================================
2255 10:57:36.957766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2256 10:57:36.961137 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2257 10:57:36.968100 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 10:57:36.971545 ===================================
2259 10:57:36.974694 LPDDR4 DRAM CONFIGURATION
2260 10:57:36.977918 ===================================
2261 10:57:36.978001 EX_ROW_EN[0] = 0x10
2262 10:57:36.981334 EX_ROW_EN[1] = 0x0
2263 10:57:36.981430 LP4Y_EN = 0x0
2264 10:57:36.984458 WORK_FSP = 0x0
2265 10:57:36.984554 WL = 0x4
2266 10:57:36.988095 RL = 0x4
2267 10:57:36.988177 BL = 0x2
2268 10:57:36.991126 RPST = 0x0
2269 10:57:36.991236 RD_PRE = 0x0
2270 10:57:36.994682 WR_PRE = 0x1
2271 10:57:36.994782 WR_PST = 0x0
2272 10:57:36.997987 DBI_WR = 0x0
2273 10:57:36.998071 DBI_RD = 0x0
2274 10:57:37.001254 OTF = 0x1
2275 10:57:37.004519 ===================================
2276 10:57:37.011725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2277 10:57:37.011827 ==
2278 10:57:37.014871 Dram Type= 6, Freq= 0, CH_0, rank 0
2279 10:57:37.018133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2280 10:57:37.018257 ==
2281 10:57:37.021634 [Duty_Offset_Calibration]
2282 10:57:37.021769 B0:2 B1:1 CA:1
2283 10:57:37.021907
2284 10:57:37.024864 [DutyScan_Calibration_Flow] k_type=0
2285 10:57:37.035190
2286 10:57:37.035312 ==CLK 0==
2287 10:57:37.038330 Final CLK duty delay cell = 0
2288 10:57:37.041594 [0] MAX Duty = 5218%(X100), DQS PI = 24
2289 10:57:37.044944 [0] MIN Duty = 4844%(X100), DQS PI = 48
2290 10:57:37.045029 [0] AVG Duty = 5031%(X100)
2291 10:57:37.048034
2292 10:57:37.051254 CH0 CLK Duty spec in!! Max-Min= 374%
2293 10:57:37.054724 [DutyScan_Calibration_Flow] ====Done====
2294 10:57:37.054807
2295 10:57:37.057973 [DutyScan_Calibration_Flow] k_type=1
2296 10:57:37.073679
2297 10:57:37.073789 ==DQS 0 ==
2298 10:57:37.076945 Final DQS duty delay cell = -4
2299 10:57:37.080263 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2300 10:57:37.083629 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2301 10:57:37.086966 [-4] AVG Duty = 4953%(X100)
2302 10:57:37.087046
2303 10:57:37.087110 ==DQS 1 ==
2304 10:57:37.090119 Final DQS duty delay cell = 0
2305 10:57:37.093892 [0] MAX Duty = 5156%(X100), DQS PI = 62
2306 10:57:37.096969 [0] MIN Duty = 5031%(X100), DQS PI = 34
2307 10:57:37.100500 [0] AVG Duty = 5093%(X100)
2308 10:57:37.100573
2309 10:57:37.103642 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2310 10:57:37.103722
2311 10:57:37.106855 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2312 10:57:37.110291 [DutyScan_Calibration_Flow] ====Done====
2313 10:57:37.110385
2314 10:57:37.113591 [DutyScan_Calibration_Flow] k_type=3
2315 10:57:37.130266
2316 10:57:37.130371 ==DQM 0 ==
2317 10:57:37.134040 Final DQM duty delay cell = 0
2318 10:57:37.137026 [0] MAX Duty = 5156%(X100), DQS PI = 30
2319 10:57:37.140368 [0] MIN Duty = 4875%(X100), DQS PI = 58
2320 10:57:37.144043 [0] AVG Duty = 5015%(X100)
2321 10:57:37.144177
2322 10:57:37.144292 ==DQM 1 ==
2323 10:57:37.147310 Final DQM duty delay cell = 0
2324 10:57:37.150617 [0] MAX Duty = 5093%(X100), DQS PI = 0
2325 10:57:37.153814 [0] MIN Duty = 5031%(X100), DQS PI = 14
2326 10:57:37.153945 [0] AVG Duty = 5062%(X100)
2327 10:57:37.157039
2328 10:57:37.160332 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2329 10:57:37.160468
2330 10:57:37.164275 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2331 10:57:37.167033 [DutyScan_Calibration_Flow] ====Done====
2332 10:57:37.167136
2333 10:57:37.170860 [DutyScan_Calibration_Flow] k_type=2
2334 10:57:37.187281
2335 10:57:37.187425 ==DQ 0 ==
2336 10:57:37.190457 Final DQ duty delay cell = 0
2337 10:57:37.193672 [0] MAX Duty = 5062%(X100), DQS PI = 32
2338 10:57:37.196709 [0] MIN Duty = 4906%(X100), DQS PI = 0
2339 10:57:37.196807 [0] AVG Duty = 4984%(X100)
2340 10:57:37.196896
2341 10:57:37.199988 ==DQ 1 ==
2342 10:57:37.203586 Final DQ duty delay cell = 0
2343 10:57:37.207153 [0] MAX Duty = 5093%(X100), DQS PI = 24
2344 10:57:37.210210 [0] MIN Duty = 4969%(X100), DQS PI = 2
2345 10:57:37.210292 [0] AVG Duty = 5031%(X100)
2346 10:57:37.210356
2347 10:57:37.213554 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2348 10:57:37.213637
2349 10:57:37.217509 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2350 10:57:37.223739 [DutyScan_Calibration_Flow] ====Done====
2351 10:57:37.223851 ==
2352 10:57:37.226872 Dram Type= 6, Freq= 0, CH_1, rank 0
2353 10:57:37.230106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 10:57:37.230189 ==
2355 10:57:37.233404 [Duty_Offset_Calibration]
2356 10:57:37.233487 B0:1 B1:0 CA:0
2357 10:57:37.233590
2358 10:57:37.237111 [DutyScan_Calibration_Flow] k_type=0
2359 10:57:37.245972
2360 10:57:37.246055 ==CLK 0==
2361 10:57:37.249600 Final CLK duty delay cell = -4
2362 10:57:37.252758 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2363 10:57:37.256032 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2364 10:57:37.259216 [-4] AVG Duty = 4969%(X100)
2365 10:57:37.259304
2366 10:57:37.262562 CH1 CLK Duty spec in!! Max-Min= 124%
2367 10:57:37.266385 [DutyScan_Calibration_Flow] ====Done====
2368 10:57:37.266469
2369 10:57:37.269002 [DutyScan_Calibration_Flow] k_type=1
2370 10:57:37.285840
2371 10:57:37.285945 ==DQS 0 ==
2372 10:57:37.289106 Final DQS duty delay cell = 0
2373 10:57:37.292329 [0] MAX Duty = 5094%(X100), DQS PI = 26
2374 10:57:37.295805 [0] MIN Duty = 4875%(X100), DQS PI = 0
2375 10:57:37.295899 [0] AVG Duty = 4984%(X100)
2376 10:57:37.298999
2377 10:57:37.299120 ==DQS 1 ==
2378 10:57:37.302098 Final DQS duty delay cell = 0
2379 10:57:37.305778 [0] MAX Duty = 5218%(X100), DQS PI = 20
2380 10:57:37.308963 [0] MIN Duty = 4969%(X100), DQS PI = 8
2381 10:57:37.309106 [0] AVG Duty = 5093%(X100)
2382 10:57:37.309171
2383 10:57:37.312530 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2384 10:57:37.315630
2385 10:57:37.318950 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2386 10:57:37.322712 [DutyScan_Calibration_Flow] ====Done====
2387 10:57:37.322820
2388 10:57:37.325803 [DutyScan_Calibration_Flow] k_type=3
2389 10:57:37.342476
2390 10:57:37.342560 ==DQM 0 ==
2391 10:57:37.345604 Final DQM duty delay cell = 0
2392 10:57:37.348679 [0] MAX Duty = 5156%(X100), DQS PI = 6
2393 10:57:37.352314 [0] MIN Duty = 5031%(X100), DQS PI = 0
2394 10:57:37.352396 [0] AVG Duty = 5093%(X100)
2395 10:57:37.352462
2396 10:57:37.355260 ==DQM 1 ==
2397 10:57:37.359128 Final DQM duty delay cell = 0
2398 10:57:37.362322 [0] MAX Duty = 5031%(X100), DQS PI = 16
2399 10:57:37.365635 [0] MIN Duty = 4907%(X100), DQS PI = 36
2400 10:57:37.365744 [0] AVG Duty = 4969%(X100)
2401 10:57:37.365841
2402 10:57:37.368844 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2403 10:57:37.372254
2404 10:57:37.375454 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2405 10:57:37.379505 [DutyScan_Calibration_Flow] ====Done====
2406 10:57:37.379587
2407 10:57:37.382033 [DutyScan_Calibration_Flow] k_type=2
2408 10:57:37.397513
2409 10:57:37.397600 ==DQ 0 ==
2410 10:57:37.401391 Final DQ duty delay cell = -4
2411 10:57:37.404679 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2412 10:57:37.407916 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2413 10:57:37.408025 [-4] AVG Duty = 5016%(X100)
2414 10:57:37.410992
2415 10:57:37.411098 ==DQ 1 ==
2416 10:57:37.414188 Final DQ duty delay cell = 0
2417 10:57:37.417949 [0] MAX Duty = 5125%(X100), DQS PI = 18
2418 10:57:37.421135 [0] MIN Duty = 4969%(X100), DQS PI = 12
2419 10:57:37.421218 [0] AVG Duty = 5047%(X100)
2420 10:57:37.424628
2421 10:57:37.427998 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2422 10:57:37.428082
2423 10:57:37.431130 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2424 10:57:37.434316 [DutyScan_Calibration_Flow] ====Done====
2425 10:57:37.437484 nWR fixed to 30
2426 10:57:37.437570 [ModeRegInit_LP4] CH0 RK0
2427 10:57:37.441232 [ModeRegInit_LP4] CH0 RK1
2428 10:57:37.444493 [ModeRegInit_LP4] CH1 RK0
2429 10:57:37.447775 [ModeRegInit_LP4] CH1 RK1
2430 10:57:37.447870 match AC timing 7
2431 10:57:37.454145 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2432 10:57:37.457850 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2433 10:57:37.460944 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2434 10:57:37.467824 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2435 10:57:37.470910 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2436 10:57:37.471010 ==
2437 10:57:37.474113 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 10:57:37.477407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 10:57:37.477533 ==
2440 10:57:37.484731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2441 10:57:37.491006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2442 10:57:37.498242 [CA 0] Center 39 (8~70) winsize 63
2443 10:57:37.501424 [CA 1] Center 39 (8~70) winsize 63
2444 10:57:37.504810 [CA 2] Center 35 (5~66) winsize 62
2445 10:57:37.508195 [CA 3] Center 34 (4~65) winsize 62
2446 10:57:37.511468 [CA 4] Center 33 (3~64) winsize 62
2447 10:57:37.515164 [CA 5] Center 32 (3~62) winsize 60
2448 10:57:37.515246
2449 10:57:37.518084 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2450 10:57:37.518167
2451 10:57:37.521705 [CATrainingPosCal] consider 1 rank data
2452 10:57:37.524871 u2DelayCellTimex100 = 270/100 ps
2453 10:57:37.528114 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2454 10:57:37.531279 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2455 10:57:37.538342 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2456 10:57:37.541365 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2457 10:57:37.545049 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2458 10:57:37.548385 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2459 10:57:37.548465
2460 10:57:37.551652 CA PerBit enable=1, Macro0, CA PI delay=32
2461 10:57:37.551730
2462 10:57:37.554949 [CBTSetCACLKResult] CA Dly = 32
2463 10:57:37.555024 CS Dly: 6 (0~37)
2464 10:57:37.555087 ==
2465 10:57:37.558137 Dram Type= 6, Freq= 0, CH_0, rank 1
2466 10:57:37.565095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 10:57:37.565179 ==
2468 10:57:37.568223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 10:57:37.575224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 10:57:37.583546 [CA 0] Center 38 (8~69) winsize 62
2471 10:57:37.586819 [CA 1] Center 38 (8~69) winsize 62
2472 10:57:37.590856 [CA 2] Center 35 (4~66) winsize 63
2473 10:57:37.593923 [CA 3] Center 34 (4~65) winsize 62
2474 10:57:37.597055 [CA 4] Center 33 (3~64) winsize 62
2475 10:57:37.600298 [CA 5] Center 32 (3~62) winsize 60
2476 10:57:37.600381
2477 10:57:37.603518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 10:57:37.603600
2479 10:57:37.606885 [CATrainingPosCal] consider 2 rank data
2480 10:57:37.610218 u2DelayCellTimex100 = 270/100 ps
2481 10:57:37.613536 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2482 10:57:37.620243 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2483 10:57:37.623449 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2484 10:57:37.627200 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2485 10:57:37.630055 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2486 10:57:37.633773 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2487 10:57:37.633847
2488 10:57:37.636824 CA PerBit enable=1, Macro0, CA PI delay=32
2489 10:57:37.636896
2490 10:57:37.640405 [CBTSetCACLKResult] CA Dly = 32
2491 10:57:37.640480 CS Dly: 6 (0~38)
2492 10:57:37.640541
2493 10:57:37.643462 ----->DramcWriteLeveling(PI) begin...
2494 10:57:37.647207 ==
2495 10:57:37.650279 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 10:57:37.653514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 10:57:37.653588 ==
2498 10:57:37.656753 Write leveling (Byte 0): 33 => 33
2499 10:57:37.660120 Write leveling (Byte 1): 28 => 28
2500 10:57:37.663859 DramcWriteLeveling(PI) end<-----
2501 10:57:37.663933
2502 10:57:37.663995 ==
2503 10:57:37.667063 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 10:57:37.670284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 10:57:37.670389 ==
2506 10:57:37.673504 [Gating] SW mode calibration
2507 10:57:37.680436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2508 10:57:37.686909 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2509 10:57:37.690066 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
2510 10:57:37.694061 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2511 10:57:37.697240 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 10:57:37.703691 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 10:57:37.706918 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 10:57:37.710319 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 10:57:37.716966 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2516 10:57:37.720338 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2517 10:57:37.723613 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2518 10:57:37.730322 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 10:57:37.733604 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 10:57:37.737379 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 10:57:37.744143 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 10:57:37.747179 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 10:57:37.750245 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2524 10:57:37.757380 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
2525 10:57:37.760531 1 1 0 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
2526 10:57:37.763637 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2527 10:57:37.770742 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 10:57:37.773947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 10:57:37.777116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 10:57:37.780323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 10:57:37.787487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2532 10:57:37.790391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2533 10:57:37.793529 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2534 10:57:37.800648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 10:57:37.803931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 10:57:37.807189 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 10:57:37.814044 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 10:57:37.817283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 10:57:37.820519 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 10:57:37.827143 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 10:57:37.830358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 10:57:37.833764 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 10:57:37.840780 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 10:57:37.843946 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 10:57:37.847038 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 10:57:37.850562 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 10:57:37.857408 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 10:57:37.861023 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2549 10:57:37.864162 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2550 10:57:37.867475 Total UI for P1: 0, mck2ui 16
2551 10:57:37.870465 best dqsien dly found for B0: ( 1, 3, 28)
2552 10:57:37.877580 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 10:57:37.881037 Total UI for P1: 0, mck2ui 16
2554 10:57:37.884262 best dqsien dly found for B1: ( 1, 4, 0)
2555 10:57:37.887272 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2556 10:57:37.890446 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2557 10:57:37.890552
2558 10:57:37.893745 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2559 10:57:37.897511 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2560 10:57:37.900614 [Gating] SW calibration Done
2561 10:57:37.900702 ==
2562 10:57:37.903923 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 10:57:37.907066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 10:57:37.907173 ==
2565 10:57:37.910369 RX Vref Scan: 0
2566 10:57:37.910451
2567 10:57:37.910515 RX Vref 0 -> 0, step: 1
2568 10:57:37.910573
2569 10:57:37.914222 RX Delay -40 -> 252, step: 8
2570 10:57:37.917574 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2571 10:57:37.924327 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2572 10:57:37.927627 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2573 10:57:37.930352 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2574 10:57:37.934235 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2575 10:57:37.937609 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2576 10:57:37.944091 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2577 10:57:37.947753 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2578 10:57:37.950971 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2579 10:57:37.954128 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2580 10:57:37.957082 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2581 10:57:37.963825 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2582 10:57:37.967575 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2583 10:57:37.970735 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2584 10:57:37.974070 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2585 10:57:37.977166 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2586 10:57:37.980978 ==
2587 10:57:37.981060 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 10:57:37.987051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 10:57:37.987166 ==
2590 10:57:37.987265 DQS Delay:
2591 10:57:37.990870 DQS0 = 0, DQS1 = 0
2592 10:57:37.990949 DQM Delay:
2593 10:57:37.994078 DQM0 = 121, DQM1 = 113
2594 10:57:37.994186 DQ Delay:
2595 10:57:37.997146 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2596 10:57:38.000906 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2597 10:57:38.004050 DQ8 =103, DQ9 =107, DQ10 =111, DQ11 =107
2598 10:57:38.007113 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2599 10:57:38.007237
2600 10:57:38.007347
2601 10:57:38.007455 ==
2602 10:57:38.010879 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 10:57:38.017492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 10:57:38.017596 ==
2605 10:57:38.017687
2606 10:57:38.017781
2607 10:57:38.017872 TX Vref Scan disable
2608 10:57:38.020779 == TX Byte 0 ==
2609 10:57:38.023991 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2610 10:57:38.027393 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2611 10:57:38.030595 == TX Byte 1 ==
2612 10:57:38.034029 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2613 10:57:38.037347 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2614 10:57:38.040629 ==
2615 10:57:38.043894 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 10:57:38.047182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 10:57:38.047290 ==
2618 10:57:38.058682 TX Vref=22, minBit 0, minWin=25, winSum=405
2619 10:57:38.062510 TX Vref=24, minBit 4, minWin=25, winSum=412
2620 10:57:38.065756 TX Vref=26, minBit 7, minWin=25, winSum=416
2621 10:57:38.068745 TX Vref=28, minBit 13, minWin=25, winSum=423
2622 10:57:38.072607 TX Vref=30, minBit 13, minWin=25, winSum=421
2623 10:57:38.078663 TX Vref=32, minBit 0, minWin=26, winSum=422
2624 10:57:38.082433 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 32
2625 10:57:38.082538
2626 10:57:38.085541 Final TX Range 1 Vref 32
2627 10:57:38.085648
2628 10:57:38.085737 ==
2629 10:57:38.088923 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 10:57:38.092127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 10:57:38.092234 ==
2632 10:57:38.095470
2633 10:57:38.095580
2634 10:57:38.095702 TX Vref Scan disable
2635 10:57:38.098628 == TX Byte 0 ==
2636 10:57:38.102509 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 10:57:38.105762 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 10:57:38.108684 == TX Byte 1 ==
2639 10:57:38.112497 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2640 10:57:38.115653 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2641 10:57:38.115737
2642 10:57:38.119274 [DATLAT]
2643 10:57:38.119409 Freq=1200, CH0 RK0
2644 10:57:38.119475
2645 10:57:38.122548 DATLAT Default: 0xd
2646 10:57:38.122677 0, 0xFFFF, sum = 0
2647 10:57:38.125848 1, 0xFFFF, sum = 0
2648 10:57:38.125929 2, 0xFFFF, sum = 0
2649 10:57:38.129148 3, 0xFFFF, sum = 0
2650 10:57:38.129230 4, 0xFFFF, sum = 0
2651 10:57:38.132245 5, 0xFFFF, sum = 0
2652 10:57:38.132326 6, 0xFFFF, sum = 0
2653 10:57:38.135618 7, 0xFFFF, sum = 0
2654 10:57:38.135713 8, 0xFFFF, sum = 0
2655 10:57:38.138942 9, 0xFFFF, sum = 0
2656 10:57:38.142394 10, 0xFFFF, sum = 0
2657 10:57:38.142477 11, 0xFFFF, sum = 0
2658 10:57:38.145516 12, 0x0, sum = 1
2659 10:57:38.145598 13, 0x0, sum = 2
2660 10:57:38.145663 14, 0x0, sum = 3
2661 10:57:38.148840 15, 0x0, sum = 4
2662 10:57:38.148922 best_step = 13
2663 10:57:38.148986
2664 10:57:38.149044 ==
2665 10:57:38.152716 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 10:57:38.159143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 10:57:38.159224 ==
2668 10:57:38.159304 RX Vref Scan: 1
2669 10:57:38.159388
2670 10:57:38.162420 Set Vref Range= 32 -> 127
2671 10:57:38.162501
2672 10:57:38.166217 RX Vref 32 -> 127, step: 1
2673 10:57:38.166298
2674 10:57:38.166361 RX Delay -5 -> 252, step: 4
2675 10:57:38.169312
2676 10:57:38.169392 Set Vref, RX VrefLevel [Byte0]: 32
2677 10:57:38.172508 [Byte1]: 32
2678 10:57:38.177457
2679 10:57:38.177538 Set Vref, RX VrefLevel [Byte0]: 33
2680 10:57:38.180561 [Byte1]: 33
2681 10:57:38.185071
2682 10:57:38.185152 Set Vref, RX VrefLevel [Byte0]: 34
2683 10:57:38.188191 [Byte1]: 34
2684 10:57:38.192525
2685 10:57:38.192607 Set Vref, RX VrefLevel [Byte0]: 35
2686 10:57:38.199141 [Byte1]: 35
2687 10:57:38.199248
2688 10:57:38.202356 Set Vref, RX VrefLevel [Byte0]: 36
2689 10:57:38.205717 [Byte1]: 36
2690 10:57:38.205801
2691 10:57:38.208977 Set Vref, RX VrefLevel [Byte0]: 37
2692 10:57:38.212921 [Byte1]: 37
2693 10:57:38.216541
2694 10:57:38.216670 Set Vref, RX VrefLevel [Byte0]: 38
2695 10:57:38.219875 [Byte1]: 38
2696 10:57:38.224164
2697 10:57:38.224285 Set Vref, RX VrefLevel [Byte0]: 39
2698 10:57:38.227274 [Byte1]: 39
2699 10:57:38.231879
2700 10:57:38.231960 Set Vref, RX VrefLevel [Byte0]: 40
2701 10:57:38.235184 [Byte1]: 40
2702 10:57:38.239772
2703 10:57:38.239853 Set Vref, RX VrefLevel [Byte0]: 41
2704 10:57:38.243142 [Byte1]: 41
2705 10:57:38.247550
2706 10:57:38.247632 Set Vref, RX VrefLevel [Byte0]: 42
2707 10:57:38.250899 [Byte1]: 42
2708 10:57:38.255510
2709 10:57:38.255609 Set Vref, RX VrefLevel [Byte0]: 43
2710 10:57:38.258852 [Byte1]: 43
2711 10:57:38.263711
2712 10:57:38.263793 Set Vref, RX VrefLevel [Byte0]: 44
2713 10:57:38.266958 [Byte1]: 44
2714 10:57:38.271702
2715 10:57:38.271784 Set Vref, RX VrefLevel [Byte0]: 45
2716 10:57:38.274751 [Byte1]: 45
2717 10:57:38.279073
2718 10:57:38.279156 Set Vref, RX VrefLevel [Byte0]: 46
2719 10:57:38.282722 [Byte1]: 46
2720 10:57:38.287025
2721 10:57:38.287108 Set Vref, RX VrefLevel [Byte0]: 47
2722 10:57:38.290199 [Byte1]: 47
2723 10:57:38.294607
2724 10:57:38.298292 Set Vref, RX VrefLevel [Byte0]: 48
2725 10:57:38.298375 [Byte1]: 48
2726 10:57:38.302961
2727 10:57:38.303043 Set Vref, RX VrefLevel [Byte0]: 49
2728 10:57:38.306102 [Byte1]: 49
2729 10:57:38.310333
2730 10:57:38.310415 Set Vref, RX VrefLevel [Byte0]: 50
2731 10:57:38.313788 [Byte1]: 50
2732 10:57:38.318739
2733 10:57:38.318816 Set Vref, RX VrefLevel [Byte0]: 51
2734 10:57:38.321921 [Byte1]: 51
2735 10:57:38.326457
2736 10:57:38.326539 Set Vref, RX VrefLevel [Byte0]: 52
2737 10:57:38.329697 [Byte1]: 52
2738 10:57:38.334110
2739 10:57:38.334193 Set Vref, RX VrefLevel [Byte0]: 53
2740 10:57:38.337162 [Byte1]: 53
2741 10:57:38.341764
2742 10:57:38.341845 Set Vref, RX VrefLevel [Byte0]: 54
2743 10:57:38.345011 [Byte1]: 54
2744 10:57:38.349626
2745 10:57:38.349708 Set Vref, RX VrefLevel [Byte0]: 55
2746 10:57:38.352959 [Byte1]: 55
2747 10:57:38.357663
2748 10:57:38.357749 Set Vref, RX VrefLevel [Byte0]: 56
2749 10:57:38.360912 [Byte1]: 56
2750 10:57:38.365306
2751 10:57:38.365388 Set Vref, RX VrefLevel [Byte0]: 57
2752 10:57:38.369043 [Byte1]: 57
2753 10:57:38.373629
2754 10:57:38.373710 Set Vref, RX VrefLevel [Byte0]: 58
2755 10:57:38.377045 [Byte1]: 58
2756 10:57:38.380917
2757 10:57:38.381015 Set Vref, RX VrefLevel [Byte0]: 59
2758 10:57:38.384826 [Byte1]: 59
2759 10:57:38.389259
2760 10:57:38.389341 Set Vref, RX VrefLevel [Byte0]: 60
2761 10:57:38.392191 [Byte1]: 60
2762 10:57:38.396706
2763 10:57:38.396788 Set Vref, RX VrefLevel [Byte0]: 61
2764 10:57:38.400431 [Byte1]: 61
2765 10:57:38.404721
2766 10:57:38.404803 Set Vref, RX VrefLevel [Byte0]: 62
2767 10:57:38.408312 [Byte1]: 62
2768 10:57:38.412430
2769 10:57:38.412513 Set Vref, RX VrefLevel [Byte0]: 63
2770 10:57:38.416190 [Byte1]: 63
2771 10:57:38.420843
2772 10:57:38.420924 Set Vref, RX VrefLevel [Byte0]: 64
2773 10:57:38.424039 [Byte1]: 64
2774 10:57:38.428492
2775 10:57:38.428573 Set Vref, RX VrefLevel [Byte0]: 65
2776 10:57:38.431716 [Byte1]: 65
2777 10:57:38.436302
2778 10:57:38.436384 Set Vref, RX VrefLevel [Byte0]: 66
2779 10:57:38.439786 [Byte1]: 66
2780 10:57:38.444011
2781 10:57:38.444093 Set Vref, RX VrefLevel [Byte0]: 67
2782 10:57:38.447139 [Byte1]: 67
2783 10:57:38.451736
2784 10:57:38.451847 Set Vref, RX VrefLevel [Byte0]: 68
2785 10:57:38.455061 [Byte1]: 68
2786 10:57:38.459760
2787 10:57:38.459837 Set Vref, RX VrefLevel [Byte0]: 69
2788 10:57:38.463122 [Byte1]: 69
2789 10:57:38.467630
2790 10:57:38.467704 Set Vref, RX VrefLevel [Byte0]: 70
2791 10:57:38.470923 [Byte1]: 70
2792 10:57:38.475469
2793 10:57:38.475542 Set Vref, RX VrefLevel [Byte0]: 71
2794 10:57:38.478733 [Byte1]: 71
2795 10:57:38.483290
2796 10:57:38.483412 Final RX Vref Byte 0 = 54 to rank0
2797 10:57:38.486590 Final RX Vref Byte 1 = 57 to rank0
2798 10:57:38.489828 Final RX Vref Byte 0 = 54 to rank1
2799 10:57:38.493499 Final RX Vref Byte 1 = 57 to rank1==
2800 10:57:38.496548 Dram Type= 6, Freq= 0, CH_0, rank 0
2801 10:57:38.503520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2802 10:57:38.503603 ==
2803 10:57:38.503667 DQS Delay:
2804 10:57:38.503728 DQS0 = 0, DQS1 = 0
2805 10:57:38.506645 DQM Delay:
2806 10:57:38.506727 DQM0 = 120, DQM1 = 113
2807 10:57:38.509759 DQ Delay:
2808 10:57:38.513554 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2809 10:57:38.516651 DQ4 =124, DQ5 =112, DQ6 =126, DQ7 =126
2810 10:57:38.519812 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2811 10:57:38.523016 DQ12 =118, DQ13 =118, DQ14 =126, DQ15 =122
2812 10:57:38.523138
2813 10:57:38.523202
2814 10:57:38.530367 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2815 10:57:38.533607 CH0 RK0: MR19=404, MR18=120B
2816 10:57:38.539957 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2817 10:57:38.540039
2818 10:57:38.543143 ----->DramcWriteLeveling(PI) begin...
2819 10:57:38.543243 ==
2820 10:57:38.546424 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 10:57:38.550107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 10:57:38.553403 ==
2823 10:57:38.553484 Write leveling (Byte 0): 36 => 36
2824 10:57:38.556651 Write leveling (Byte 1): 30 => 30
2825 10:57:38.559901 DramcWriteLeveling(PI) end<-----
2826 10:57:38.559983
2827 10:57:38.560046 ==
2828 10:57:38.563176 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 10:57:38.569818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 10:57:38.569900 ==
2831 10:57:38.569964 [Gating] SW mode calibration
2832 10:57:38.580077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2833 10:57:38.583281 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2834 10:57:38.586662 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
2835 10:57:38.593369 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 10:57:38.597026 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 10:57:38.600283 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 10:57:38.607002 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 10:57:38.610093 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 10:57:38.613247 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 10:57:38.619940 0 15 28 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
2842 10:57:38.623629 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 10:57:38.626859 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 10:57:38.633398 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 10:57:38.636702 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 10:57:38.640479 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 10:57:38.647437 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 10:57:38.650632 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2849 10:57:38.653943 1 0 28 | B1->B0 | 3939 3939 | 1 1 | (0 0) (0 0)
2850 10:57:38.657205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 10:57:38.663644 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 10:57:38.667015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 10:57:38.670235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 10:57:38.677404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 10:57:38.680576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 10:57:38.683851 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 10:57:38.690433 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2858 10:57:38.693665 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2859 10:57:38.697526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 10:57:38.703928 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 10:57:38.706932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 10:57:38.710803 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 10:57:38.717360 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 10:57:38.720380 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 10:57:38.724133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 10:57:38.730566 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 10:57:38.734239 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:57:38.737406 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:57:38.740674 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:57:38.747249 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:57:38.750985 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 10:57:38.753976 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:57:38.761289 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2874 10:57:38.763880 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 10:57:38.767636 Total UI for P1: 0, mck2ui 16
2876 10:57:38.770977 best dqsien dly found for B0: ( 1, 3, 28)
2877 10:57:38.774222 Total UI for P1: 0, mck2ui 16
2878 10:57:38.777574 best dqsien dly found for B1: ( 1, 3, 28)
2879 10:57:38.780911 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2880 10:57:38.783917 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2881 10:57:38.783999
2882 10:57:38.787717 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2883 10:57:38.790972 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 10:57:38.794296 [Gating] SW calibration Done
2885 10:57:38.794378 ==
2886 10:57:38.797538 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 10:57:38.800900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 10:57:38.800982 ==
2889 10:57:38.804325 RX Vref Scan: 0
2890 10:57:38.804406
2891 10:57:38.807636 RX Vref 0 -> 0, step: 1
2892 10:57:38.807717
2893 10:57:38.807780 RX Delay -40 -> 252, step: 8
2894 10:57:38.814341 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2895 10:57:38.817436 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 10:57:38.820587 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2897 10:57:38.824302 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2898 10:57:38.827381 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2899 10:57:38.834204 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2900 10:57:38.837116 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 10:57:38.840405 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2902 10:57:38.844254 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
2903 10:57:38.847600 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2904 10:57:38.854244 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2905 10:57:38.857493 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2906 10:57:38.860583 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2907 10:57:38.863746 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2908 10:57:38.867506 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2909 10:57:38.874415 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2910 10:57:38.874498 ==
2911 10:57:38.877496 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 10:57:38.880837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 10:57:38.880919 ==
2914 10:57:38.880984 DQS Delay:
2915 10:57:38.884050 DQS0 = 0, DQS1 = 0
2916 10:57:38.884131 DQM Delay:
2917 10:57:38.887270 DQM0 = 122, DQM1 = 114
2918 10:57:38.887377 DQ Delay:
2919 10:57:38.890648 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2920 10:57:38.893868 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2921 10:57:38.897697 DQ8 =107, DQ9 =99, DQ10 =115, DQ11 =107
2922 10:57:38.900937 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2923 10:57:38.901020
2924 10:57:38.901083
2925 10:57:38.904194 ==
2926 10:57:38.907493 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 10:57:38.910738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 10:57:38.910820 ==
2929 10:57:38.910885
2930 10:57:38.910945
2931 10:57:38.913992 TX Vref Scan disable
2932 10:57:38.914073 == TX Byte 0 ==
2933 10:57:38.917585 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
2934 10:57:38.924293 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
2935 10:57:38.924380 == TX Byte 1 ==
2936 10:57:38.927537 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2937 10:57:38.933734 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2938 10:57:38.933842 ==
2939 10:57:38.937656 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 10:57:38.940588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 10:57:38.940664 ==
2942 10:57:38.953320 TX Vref=22, minBit 1, minWin=24, winSum=412
2943 10:57:38.956531 TX Vref=24, minBit 3, minWin=25, winSum=415
2944 10:57:38.959854 TX Vref=26, minBit 1, minWin=26, winSum=425
2945 10:57:38.963673 TX Vref=28, minBit 10, minWin=25, winSum=421
2946 10:57:38.966953 TX Vref=30, minBit 5, minWin=25, winSum=426
2947 10:57:38.970076 TX Vref=32, minBit 0, minWin=26, winSum=421
2948 10:57:38.977153 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 26
2949 10:57:38.977237
2950 10:57:38.980253 Final TX Range 1 Vref 26
2951 10:57:38.980330
2952 10:57:38.980391 ==
2953 10:57:38.983290 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 10:57:38.986745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 10:57:38.986821 ==
2956 10:57:38.986881
2957 10:57:38.986939
2958 10:57:38.990022 TX Vref Scan disable
2959 10:57:38.993313 == TX Byte 0 ==
2960 10:57:38.996973 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2961 10:57:39.000251 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2962 10:57:39.003614 == TX Byte 1 ==
2963 10:57:39.006680 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2964 10:57:39.010051 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2965 10:57:39.010132
2966 10:57:39.013394 [DATLAT]
2967 10:57:39.013474 Freq=1200, CH0 RK1
2968 10:57:39.013539
2969 10:57:39.016748 DATLAT Default: 0xd
2970 10:57:39.016829 0, 0xFFFF, sum = 0
2971 10:57:39.020528 1, 0xFFFF, sum = 0
2972 10:57:39.020610 2, 0xFFFF, sum = 0
2973 10:57:39.023600 3, 0xFFFF, sum = 0
2974 10:57:39.023683 4, 0xFFFF, sum = 0
2975 10:57:39.026832 5, 0xFFFF, sum = 0
2976 10:57:39.026914 6, 0xFFFF, sum = 0
2977 10:57:39.030572 7, 0xFFFF, sum = 0
2978 10:57:39.030654 8, 0xFFFF, sum = 0
2979 10:57:39.033670 9, 0xFFFF, sum = 0
2980 10:57:39.033752 10, 0xFFFF, sum = 0
2981 10:57:39.036985 11, 0xFFFF, sum = 0
2982 10:57:39.037067 12, 0x0, sum = 1
2983 10:57:39.040147 13, 0x0, sum = 2
2984 10:57:39.040229 14, 0x0, sum = 3
2985 10:57:39.043403 15, 0x0, sum = 4
2986 10:57:39.043485 best_step = 13
2987 10:57:39.043548
2988 10:57:39.043606 ==
2989 10:57:39.047180 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 10:57:39.054156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 10:57:39.054238 ==
2992 10:57:39.054302 RX Vref Scan: 0
2993 10:57:39.054361
2994 10:57:39.057457 RX Vref 0 -> 0, step: 1
2995 10:57:39.057538
2996 10:57:39.060611 RX Delay -13 -> 252, step: 4
2997 10:57:39.063965 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2998 10:57:39.067298 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2999 10:57:39.073964 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3000 10:57:39.077395 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3001 10:57:39.080592 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3002 10:57:39.083763 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3003 10:57:39.086966 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3004 10:57:39.090222 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3005 10:57:39.097357 iDelay=195, Bit 8, Center 104 (39 ~ 170) 132
3006 10:57:39.100630 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3007 10:57:39.103753 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3008 10:57:39.107038 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3009 10:57:39.110365 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3010 10:57:39.117035 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3011 10:57:39.120246 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3012 10:57:39.124365 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3013 10:57:39.124446 ==
3014 10:57:39.127505 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 10:57:39.130565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 10:57:39.133628 ==
3017 10:57:39.133709 DQS Delay:
3018 10:57:39.133772 DQS0 = 0, DQS1 = 0
3019 10:57:39.137274 DQM Delay:
3020 10:57:39.137355 DQM0 = 120, DQM1 = 112
3021 10:57:39.140439 DQ Delay:
3022 10:57:39.143686 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3023 10:57:39.147489 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3024 10:57:39.150706 DQ8 =104, DQ9 =98, DQ10 =114, DQ11 =104
3025 10:57:39.153880 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3026 10:57:39.153961
3027 10:57:39.154025
3028 10:57:39.160651 [DQSOSCAuto] RK1, (LSB)MR18= 0xcec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 405 ps
3029 10:57:39.164005 CH0 RK1: MR19=403, MR18=CEC
3030 10:57:39.170262 CH0_RK1: MR19=0x403, MR18=0xCEC, DQSOSC=405, MR23=63, INC=39, DEC=26
3031 10:57:39.174189 [RxdqsGatingPostProcess] freq 1200
3032 10:57:39.177365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 10:57:39.180584 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 10:57:39.183846 best DQS1 dly(2T, 0.5T) = (0, 12)
3035 10:57:39.187503 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 10:57:39.190759 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3037 10:57:39.194033 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 10:57:39.197221 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 10:57:39.201055 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 10:57:39.204281 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 10:57:39.207680 Pre-setting of DQS Precalculation
3042 10:57:39.210761 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 10:57:39.210867 ==
3044 10:57:39.213965 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 10:57:39.220576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 10:57:39.220682 ==
3047 10:57:39.223994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 10:57:39.230688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3049 10:57:39.239508 [CA 0] Center 37 (7~68) winsize 62
3050 10:57:39.243042 [CA 1] Center 37 (7~68) winsize 62
3051 10:57:39.246144 [CA 2] Center 34 (4~65) winsize 62
3052 10:57:39.249897 [CA 3] Center 34 (4~64) winsize 61
3053 10:57:39.252931 [CA 4] Center 34 (4~64) winsize 61
3054 10:57:39.255901 [CA 5] Center 33 (3~63) winsize 61
3055 10:57:39.255997
3056 10:57:39.259033 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3057 10:57:39.259116
3058 10:57:39.262703 [CATrainingPosCal] consider 1 rank data
3059 10:57:39.266358 u2DelayCellTimex100 = 270/100 ps
3060 10:57:39.269481 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 10:57:39.276064 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 10:57:39.279385 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3063 10:57:39.282665 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 10:57:39.285973 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 10:57:39.289321 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3066 10:57:39.289403
3067 10:57:39.292360 CA PerBit enable=1, Macro0, CA PI delay=33
3068 10:57:39.292442
3069 10:57:39.296300 [CBTSetCACLKResult] CA Dly = 33
3070 10:57:39.296383 CS Dly: 8 (0~39)
3071 10:57:39.299528 ==
3072 10:57:39.299649 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 10:57:39.305822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 10:57:39.305930 ==
3075 10:57:39.308968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 10:57:39.315675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 10:57:39.324848 [CA 0] Center 37 (7~68) winsize 62
3078 10:57:39.328415 [CA 1] Center 37 (7~68) winsize 62
3079 10:57:39.331813 [CA 2] Center 35 (5~65) winsize 61
3080 10:57:39.334883 [CA 3] Center 34 (4~65) winsize 62
3081 10:57:39.338839 [CA 4] Center 34 (4~65) winsize 62
3082 10:57:39.342121 [CA 5] Center 34 (4~64) winsize 61
3083 10:57:39.342204
3084 10:57:39.345327 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 10:57:39.345402
3086 10:57:39.348204 [CATrainingPosCal] consider 2 rank data
3087 10:57:39.351886 u2DelayCellTimex100 = 270/100 ps
3088 10:57:39.354880 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 10:57:39.358628 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 10:57:39.361691 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 10:57:39.368491 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 10:57:39.371611 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 10:57:39.375322 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3094 10:57:39.375440
3095 10:57:39.378492 CA PerBit enable=1, Macro0, CA PI delay=33
3096 10:57:39.378566
3097 10:57:39.381619 [CBTSetCACLKResult] CA Dly = 33
3098 10:57:39.381728 CS Dly: 9 (0~41)
3099 10:57:39.381819
3100 10:57:39.384808 ----->DramcWriteLeveling(PI) begin...
3101 10:57:39.388731 ==
3102 10:57:39.388819 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 10:57:39.395333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 10:57:39.395449 ==
3105 10:57:39.398491 Write leveling (Byte 0): 27 => 27
3106 10:57:39.401734 Write leveling (Byte 1): 27 => 27
3107 10:57:39.401847 DramcWriteLeveling(PI) end<-----
3108 10:57:39.405094
3109 10:57:39.405201 ==
3110 10:57:39.408433 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 10:57:39.412185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 10:57:39.412286 ==
3113 10:57:39.415182 [Gating] SW mode calibration
3114 10:57:39.421824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 10:57:39.425182 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 10:57:39.431717 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 10:57:39.434957 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 10:57:39.438268 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 10:57:39.445290 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 10:57:39.448637 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 10:57:39.451905 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 10:57:39.458518 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
3123 10:57:39.461997 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3124 10:57:39.465537 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 10:57:39.471602 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 10:57:39.475465 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 10:57:39.478611 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 10:57:39.482227 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 10:57:39.488866 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 10:57:39.492053 1 0 24 | B1->B0 | 3030 4141 | 0 1 | (0 0) (0 0)
3131 10:57:39.495322 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3132 10:57:39.502106 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 10:57:39.505386 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 10:57:39.508481 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 10:57:39.515411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 10:57:39.518562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 10:57:39.521628 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 10:57:39.528446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 10:57:39.531698 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 10:57:39.535642 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 10:57:39.541623 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 10:57:39.545651 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 10:57:39.548963 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 10:57:39.555708 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 10:57:39.558950 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 10:57:39.562028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 10:57:39.568594 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 10:57:39.572109 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 10:57:39.575230 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:57:39.578460 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:57:39.585996 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:57:39.588798 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:57:39.591868 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:57:39.598624 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3155 10:57:39.602374 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 10:57:39.605623 Total UI for P1: 0, mck2ui 16
3157 10:57:39.608976 best dqsien dly found for B0: ( 1, 3, 24)
3158 10:57:39.612177 Total UI for P1: 0, mck2ui 16
3159 10:57:39.615949 best dqsien dly found for B1: ( 1, 3, 24)
3160 10:57:39.618558 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3161 10:57:39.622444 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3162 10:57:39.622542
3163 10:57:39.625293 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3164 10:57:39.629328 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 10:57:39.632419 [Gating] SW calibration Done
3166 10:57:39.632521 ==
3167 10:57:39.635749 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 10:57:39.638984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 10:57:39.642292 ==
3170 10:57:39.642392 RX Vref Scan: 0
3171 10:57:39.642482
3172 10:57:39.645656 RX Vref 0 -> 0, step: 1
3173 10:57:39.645754
3174 10:57:39.645843 RX Delay -40 -> 252, step: 8
3175 10:57:39.652396 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3176 10:57:39.656202 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3177 10:57:39.659565 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 10:57:39.662767 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3179 10:57:39.666000 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3180 10:57:39.672710 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3181 10:57:39.676062 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3182 10:57:39.679051 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3183 10:57:39.682453 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3184 10:57:39.686036 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3185 10:57:39.692955 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3186 10:57:39.696040 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3187 10:57:39.699733 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 10:57:39.702592 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3189 10:57:39.706128 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3190 10:57:39.712615 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3191 10:57:39.712697 ==
3192 10:57:39.715906 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 10:57:39.719153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 10:57:39.719258 ==
3195 10:57:39.719385 DQS Delay:
3196 10:57:39.722936 DQS0 = 0, DQS1 = 0
3197 10:57:39.723013 DQM Delay:
3198 10:57:39.726346 DQM0 = 120, DQM1 = 116
3199 10:57:39.726416 DQ Delay:
3200 10:57:39.729478 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3201 10:57:39.733016 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3202 10:57:39.736290 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3203 10:57:39.739476 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3204 10:57:39.739550
3205 10:57:39.739613
3206 10:57:39.739671 ==
3207 10:57:39.742680 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 10:57:39.749413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 10:57:39.749491 ==
3210 10:57:39.749554
3211 10:57:39.749613
3212 10:57:39.749670 TX Vref Scan disable
3213 10:57:39.753310 == TX Byte 0 ==
3214 10:57:39.756555 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3215 10:57:39.760038 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3216 10:57:39.763212 == TX Byte 1 ==
3217 10:57:39.766521 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3218 10:57:39.773114 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3219 10:57:39.773186 ==
3220 10:57:39.776376 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 10:57:39.780105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 10:57:39.780184 ==
3223 10:57:39.790854 TX Vref=22, minBit 11, minWin=24, winSum=410
3224 10:57:39.794550 TX Vref=24, minBit 9, minWin=25, winSum=418
3225 10:57:39.797411 TX Vref=26, minBit 1, minWin=26, winSum=424
3226 10:57:39.800565 TX Vref=28, minBit 9, minWin=25, winSum=428
3227 10:57:39.804257 TX Vref=30, minBit 1, minWin=26, winSum=431
3228 10:57:39.807487 TX Vref=32, minBit 9, minWin=26, winSum=430
3229 10:57:39.814128 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3230 10:57:39.814208
3231 10:57:39.817938 Final TX Range 1 Vref 30
3232 10:57:39.818016
3233 10:57:39.818087 ==
3234 10:57:39.821303 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 10:57:39.823960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 10:57:39.824036 ==
3237 10:57:39.824108
3238 10:57:39.827699
3239 10:57:39.827784 TX Vref Scan disable
3240 10:57:39.831080 == TX Byte 0 ==
3241 10:57:39.834362 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 10:57:39.837444 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 10:57:39.840542 == TX Byte 1 ==
3244 10:57:39.844255 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3245 10:57:39.847639 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3246 10:57:39.847714
3247 10:57:39.850876 [DATLAT]
3248 10:57:39.850978 Freq=1200, CH1 RK0
3249 10:57:39.851077
3250 10:57:39.854141 DATLAT Default: 0xd
3251 10:57:39.854215 0, 0xFFFF, sum = 0
3252 10:57:39.857523 1, 0xFFFF, sum = 0
3253 10:57:39.857594 2, 0xFFFF, sum = 0
3254 10:57:39.860751 3, 0xFFFF, sum = 0
3255 10:57:39.860829 4, 0xFFFF, sum = 0
3256 10:57:39.864045 5, 0xFFFF, sum = 0
3257 10:57:39.864127 6, 0xFFFF, sum = 0
3258 10:57:39.867246 7, 0xFFFF, sum = 0
3259 10:57:39.867388 8, 0xFFFF, sum = 0
3260 10:57:39.870693 9, 0xFFFF, sum = 0
3261 10:57:39.874498 10, 0xFFFF, sum = 0
3262 10:57:39.874573 11, 0xFFFF, sum = 0
3263 10:57:39.877787 12, 0x0, sum = 1
3264 10:57:39.877861 13, 0x0, sum = 2
3265 10:57:39.877923 14, 0x0, sum = 3
3266 10:57:39.881044 15, 0x0, sum = 4
3267 10:57:39.881120 best_step = 13
3268 10:57:39.881181
3269 10:57:39.884126 ==
3270 10:57:39.884198 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 10:57:39.890747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 10:57:39.890821 ==
3273 10:57:39.890890 RX Vref Scan: 1
3274 10:57:39.890947
3275 10:57:39.894132 Set Vref Range= 32 -> 127
3276 10:57:39.894207
3277 10:57:39.897921 RX Vref 32 -> 127, step: 1
3278 10:57:39.898001
3279 10:57:39.900869 RX Delay -5 -> 252, step: 4
3280 10:57:39.900956
3281 10:57:39.904131 Set Vref, RX VrefLevel [Byte0]: 32
3282 10:57:39.907767 [Byte1]: 32
3283 10:57:39.907841
3284 10:57:39.910963 Set Vref, RX VrefLevel [Byte0]: 33
3285 10:57:39.914009 [Byte1]: 33
3286 10:57:39.914081
3287 10:57:39.917580 Set Vref, RX VrefLevel [Byte0]: 34
3288 10:57:39.920600 [Byte1]: 34
3289 10:57:39.924922
3290 10:57:39.924997 Set Vref, RX VrefLevel [Byte0]: 35
3291 10:57:39.928059 [Byte1]: 35
3292 10:57:39.932664
3293 10:57:39.932736 Set Vref, RX VrefLevel [Byte0]: 36
3294 10:57:39.935653 [Byte1]: 36
3295 10:57:39.940397
3296 10:57:39.940466 Set Vref, RX VrefLevel [Byte0]: 37
3297 10:57:39.943626 [Byte1]: 37
3298 10:57:39.947988
3299 10:57:39.948060 Set Vref, RX VrefLevel [Byte0]: 38
3300 10:57:39.951955 [Byte1]: 38
3301 10:57:39.955857
3302 10:57:39.955930 Set Vref, RX VrefLevel [Byte0]: 39
3303 10:57:39.959696 [Byte1]: 39
3304 10:57:39.964394
3305 10:57:39.964474 Set Vref, RX VrefLevel [Byte0]: 40
3306 10:57:39.967073 [Byte1]: 40
3307 10:57:39.971548
3308 10:57:39.971621 Set Vref, RX VrefLevel [Byte0]: 41
3309 10:57:39.974837 [Byte1]: 41
3310 10:57:39.979404
3311 10:57:39.979473 Set Vref, RX VrefLevel [Byte0]: 42
3312 10:57:39.982655 [Byte1]: 42
3313 10:57:39.987601
3314 10:57:39.987675 Set Vref, RX VrefLevel [Byte0]: 43
3315 10:57:39.990911 [Byte1]: 43
3316 10:57:39.995575
3317 10:57:39.995664 Set Vref, RX VrefLevel [Byte0]: 44
3318 10:57:39.998826 [Byte1]: 44
3319 10:57:40.002875
3320 10:57:40.002954 Set Vref, RX VrefLevel [Byte0]: 45
3321 10:57:40.006601 [Byte1]: 45
3322 10:57:40.011244
3323 10:57:40.011332 Set Vref, RX VrefLevel [Byte0]: 46
3324 10:57:40.014316 [Byte1]: 46
3325 10:57:40.018627
3326 10:57:40.018706 Set Vref, RX VrefLevel [Byte0]: 47
3327 10:57:40.022361 [Byte1]: 47
3328 10:57:40.026469
3329 10:57:40.026548 Set Vref, RX VrefLevel [Byte0]: 48
3330 10:57:40.030265 [Byte1]: 48
3331 10:57:40.034532
3332 10:57:40.034612 Set Vref, RX VrefLevel [Byte0]: 49
3333 10:57:40.037811 [Byte1]: 49
3334 10:57:40.042272
3335 10:57:40.042351 Set Vref, RX VrefLevel [Byte0]: 50
3336 10:57:40.046097 [Byte1]: 50
3337 10:57:40.049959
3338 10:57:40.050055 Set Vref, RX VrefLevel [Byte0]: 51
3339 10:57:40.053270 [Byte1]: 51
3340 10:57:40.058462
3341 10:57:40.058541 Set Vref, RX VrefLevel [Byte0]: 52
3342 10:57:40.061645 [Byte1]: 52
3343 10:57:40.065670
3344 10:57:40.065779 Set Vref, RX VrefLevel [Byte0]: 53
3345 10:57:40.069013 [Byte1]: 53
3346 10:57:40.073668
3347 10:57:40.073769 Set Vref, RX VrefLevel [Byte0]: 54
3348 10:57:40.077108 [Byte1]: 54
3349 10:57:40.081609
3350 10:57:40.081701 Set Vref, RX VrefLevel [Byte0]: 55
3351 10:57:40.084997 [Byte1]: 55
3352 10:57:40.089641
3353 10:57:40.089732 Set Vref, RX VrefLevel [Byte0]: 56
3354 10:57:40.092854 [Byte1]: 56
3355 10:57:40.097447
3356 10:57:40.097545 Set Vref, RX VrefLevel [Byte0]: 57
3357 10:57:40.100758 [Byte1]: 57
3358 10:57:40.105274
3359 10:57:40.105354 Set Vref, RX VrefLevel [Byte0]: 58
3360 10:57:40.108621 [Byte1]: 58
3361 10:57:40.113257
3362 10:57:40.113336 Set Vref, RX VrefLevel [Byte0]: 59
3363 10:57:40.116301 [Byte1]: 59
3364 10:57:40.120670
3365 10:57:40.120750 Set Vref, RX VrefLevel [Byte0]: 60
3366 10:57:40.124411 [Byte1]: 60
3367 10:57:40.128785
3368 10:57:40.128894 Set Vref, RX VrefLevel [Byte0]: 61
3369 10:57:40.131875 [Byte1]: 61
3370 10:57:40.136586
3371 10:57:40.136665 Set Vref, RX VrefLevel [Byte0]: 62
3372 10:57:40.142824 [Byte1]: 62
3373 10:57:40.142904
3374 10:57:40.146599 Set Vref, RX VrefLevel [Byte0]: 63
3375 10:57:40.149767 [Byte1]: 63
3376 10:57:40.149847
3377 10:57:40.152888 Set Vref, RX VrefLevel [Byte0]: 64
3378 10:57:40.156607 [Byte1]: 64
3379 10:57:40.160304
3380 10:57:40.160383 Set Vref, RX VrefLevel [Byte0]: 65
3381 10:57:40.163475 [Byte1]: 65
3382 10:57:40.168002
3383 10:57:40.168084 Set Vref, RX VrefLevel [Byte0]: 66
3384 10:57:40.171352 [Byte1]: 66
3385 10:57:40.175679
3386 10:57:40.175757 Set Vref, RX VrefLevel [Byte0]: 67
3387 10:57:40.178963 [Byte1]: 67
3388 10:57:40.183701
3389 10:57:40.183780 Set Vref, RX VrefLevel [Byte0]: 68
3390 10:57:40.187111 [Byte1]: 68
3391 10:57:40.191730
3392 10:57:40.191841 Set Vref, RX VrefLevel [Byte0]: 69
3393 10:57:40.194854 [Byte1]: 69
3394 10:57:40.199293
3395 10:57:40.199412 Final RX Vref Byte 0 = 56 to rank0
3396 10:57:40.202562 Final RX Vref Byte 1 = 53 to rank0
3397 10:57:40.205817 Final RX Vref Byte 0 = 56 to rank1
3398 10:57:40.209628 Final RX Vref Byte 1 = 53 to rank1==
3399 10:57:40.212888 Dram Type= 6, Freq= 0, CH_1, rank 0
3400 10:57:40.219398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3401 10:57:40.219481 ==
3402 10:57:40.219545 DQS Delay:
3403 10:57:40.219604 DQS0 = 0, DQS1 = 0
3404 10:57:40.222590 DQM Delay:
3405 10:57:40.222672 DQM0 = 120, DQM1 = 117
3406 10:57:40.226461 DQ Delay:
3407 10:57:40.229375 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3408 10:57:40.232543 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3409 10:57:40.236482 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3410 10:57:40.239317 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3411 10:57:40.239442
3412 10:57:40.239507
3413 10:57:40.246067 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3414 10:57:40.249263 CH1 RK0: MR19=404, MR18=215
3415 10:57:40.256131 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3416 10:57:40.256213
3417 10:57:40.259424 ----->DramcWriteLeveling(PI) begin...
3418 10:57:40.259507 ==
3419 10:57:40.262444 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 10:57:40.266238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 10:57:40.266322 ==
3422 10:57:40.269293 Write leveling (Byte 0): 25 => 25
3423 10:57:40.272475 Write leveling (Byte 1): 29 => 29
3424 10:57:40.275830 DramcWriteLeveling(PI) end<-----
3425 10:57:40.275913
3426 10:57:40.275979 ==
3427 10:57:40.279645 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 10:57:40.286309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 10:57:40.286393 ==
3430 10:57:40.286458 [Gating] SW mode calibration
3431 10:57:40.296154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3432 10:57:40.299322 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3433 10:57:40.302487 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 10:57:40.309653 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 10:57:40.313054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 10:57:40.316301 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 10:57:40.323085 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 10:57:40.326335 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 10:57:40.329675 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (1 0) (0 0)
3440 10:57:40.335878 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3441 10:57:40.339514 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 10:57:40.342554 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 10:57:40.349291 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 10:57:40.353087 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 10:57:40.356231 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 10:57:40.362776 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3447 10:57:40.366405 1 0 24 | B1->B0 | 3f3f 2929 | 0 0 | (0 0) (0 0)
3448 10:57:40.369610 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 10:57:40.372893 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 10:57:40.379659 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 10:57:40.382567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 10:57:40.385961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 10:57:40.392808 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 10:57:40.396072 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3455 10:57:40.399381 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3456 10:57:40.406144 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3457 10:57:40.409217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 10:57:40.412568 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 10:57:40.419241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 10:57:40.422470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 10:57:40.426090 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 10:57:40.432723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 10:57:40.436187 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 10:57:40.439365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 10:57:40.446061 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 10:57:40.449208 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 10:57:40.452369 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:57:40.459296 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:57:40.462389 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:57:40.466438 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:57:40.472829 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3472 10:57:40.472965 Total UI for P1: 0, mck2ui 16
3473 10:57:40.479416 best dqsien dly found for B1: ( 1, 3, 22)
3474 10:57:40.482602 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3475 10:57:40.486075 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 10:57:40.489366 Total UI for P1: 0, mck2ui 16
3477 10:57:40.492544 best dqsien dly found for B0: ( 1, 3, 26)
3478 10:57:40.496059 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3479 10:57:40.499399 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3480 10:57:40.499698
3481 10:57:40.502751 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3482 10:57:40.509303 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3483 10:57:40.509824 [Gating] SW calibration Done
3484 10:57:40.510162 ==
3485 10:57:40.512780 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 10:57:40.519175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 10:57:40.519642 ==
3488 10:57:40.519977 RX Vref Scan: 0
3489 10:57:40.520289
3490 10:57:40.522442 RX Vref 0 -> 0, step: 1
3491 10:57:40.522861
3492 10:57:40.526298 RX Delay -40 -> 252, step: 8
3493 10:57:40.529474 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3494 10:57:40.532834 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3495 10:57:40.536164 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3496 10:57:40.542861 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3497 10:57:40.546050 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3498 10:57:40.549366 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3499 10:57:40.552583 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3500 10:57:40.556152 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3501 10:57:40.562836 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3502 10:57:40.565934 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3503 10:57:40.569559 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3504 10:57:40.572760 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3505 10:57:40.576283 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3506 10:57:40.582141 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3507 10:57:40.585768 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3508 10:57:40.588949 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3509 10:57:40.589025 ==
3510 10:57:40.592033 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 10:57:40.595229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 10:57:40.595307 ==
3513 10:57:40.599080 DQS Delay:
3514 10:57:40.599193 DQS0 = 0, DQS1 = 0
3515 10:57:40.602433 DQM Delay:
3516 10:57:40.602524 DQM0 = 120, DQM1 = 118
3517 10:57:40.602593 DQ Delay:
3518 10:57:40.605691 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3519 10:57:40.612218 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3520 10:57:40.615431 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3521 10:57:40.619269 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3522 10:57:40.619383
3523 10:57:40.619448
3524 10:57:40.619514 ==
3525 10:57:40.622533 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 10:57:40.625723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 10:57:40.625825 ==
3528 10:57:40.625915
3529 10:57:40.626001
3530 10:57:40.629046 TX Vref Scan disable
3531 10:57:40.632137 == TX Byte 0 ==
3532 10:57:40.635417 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3533 10:57:40.638693 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3534 10:57:40.642016 == TX Byte 1 ==
3535 10:57:40.645342 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3536 10:57:40.648597 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3537 10:57:40.648702 ==
3538 10:57:40.652385 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 10:57:40.655778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 10:57:40.658341 ==
3541 10:57:40.668718 TX Vref=22, minBit 1, minWin=25, winSum=422
3542 10:57:40.672017 TX Vref=24, minBit 1, minWin=26, winSum=426
3543 10:57:40.675535 TX Vref=26, minBit 10, minWin=25, winSum=427
3544 10:57:40.678714 TX Vref=28, minBit 9, minWin=26, winSum=432
3545 10:57:40.681954 TX Vref=30, minBit 9, minWin=26, winSum=435
3546 10:57:40.688688 TX Vref=32, minBit 4, minWin=26, winSum=432
3547 10:57:40.692013 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3548 10:57:40.692121
3549 10:57:40.695162 Final TX Range 1 Vref 30
3550 10:57:40.695262
3551 10:57:40.695375 ==
3552 10:57:40.698978 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 10:57:40.702032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 10:57:40.702133 ==
3555 10:57:40.705293
3556 10:57:40.705395
3557 10:57:40.705489 TX Vref Scan disable
3558 10:57:40.708697 == TX Byte 0 ==
3559 10:57:40.712377 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3560 10:57:40.718306 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3561 10:57:40.718405 == TX Byte 1 ==
3562 10:57:40.721476 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3563 10:57:40.728612 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3564 10:57:40.728709
3565 10:57:40.728804 [DATLAT]
3566 10:57:40.728892 Freq=1200, CH1 RK1
3567 10:57:40.728984
3568 10:57:40.731915 DATLAT Default: 0xd
3569 10:57:40.732014 0, 0xFFFF, sum = 0
3570 10:57:40.735172 1, 0xFFFF, sum = 0
3571 10:57:40.738396 2, 0xFFFF, sum = 0
3572 10:57:40.738466 3, 0xFFFF, sum = 0
3573 10:57:40.741662 4, 0xFFFF, sum = 0
3574 10:57:40.741761 5, 0xFFFF, sum = 0
3575 10:57:40.744973 6, 0xFFFF, sum = 0
3576 10:57:40.745069 7, 0xFFFF, sum = 0
3577 10:57:40.748193 8, 0xFFFF, sum = 0
3578 10:57:40.748292 9, 0xFFFF, sum = 0
3579 10:57:40.751496 10, 0xFFFF, sum = 0
3580 10:57:40.751568 11, 0xFFFF, sum = 0
3581 10:57:40.754841 12, 0x0, sum = 1
3582 10:57:40.754941 13, 0x0, sum = 2
3583 10:57:40.758186 14, 0x0, sum = 3
3584 10:57:40.758313 15, 0x0, sum = 4
3585 10:57:40.761441 best_step = 13
3586 10:57:40.761544
3587 10:57:40.761635 ==
3588 10:57:40.764653 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 10:57:40.768318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 10:57:40.768421 ==
3591 10:57:40.768516 RX Vref Scan: 0
3592 10:57:40.768604
3593 10:57:40.771322 RX Vref 0 -> 0, step: 1
3594 10:57:40.771404
3595 10:57:40.774971 RX Delay -5 -> 252, step: 4
3596 10:57:40.778118 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3597 10:57:40.784964 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3598 10:57:40.788229 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3599 10:57:40.791265 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3600 10:57:40.794433 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3601 10:57:40.797768 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3602 10:57:40.804704 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3603 10:57:40.807959 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3604 10:57:40.811461 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3605 10:57:40.814851 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3606 10:57:40.817938 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3607 10:57:40.824865 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3608 10:57:40.828094 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3609 10:57:40.831251 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3610 10:57:40.834053 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3611 10:57:40.841284 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3612 10:57:40.841403 ==
3613 10:57:40.844467 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 10:57:40.847625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 10:57:40.847719 ==
3616 10:57:40.847811 DQS Delay:
3617 10:57:40.850936 DQS0 = 0, DQS1 = 0
3618 10:57:40.851034 DQM Delay:
3619 10:57:40.854206 DQM0 = 120, DQM1 = 118
3620 10:57:40.854304 DQ Delay:
3621 10:57:40.857437 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3622 10:57:40.860745 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3623 10:57:40.864057 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3624 10:57:40.867318 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3625 10:57:40.867404
3626 10:57:40.867466
3627 10:57:40.877369 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3628 10:57:40.880929 CH1 RK1: MR19=403, MR18=11EE
3629 10:57:40.887696 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3630 10:57:40.887812 [RxdqsGatingPostProcess] freq 1200
3631 10:57:40.894017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3632 10:57:40.897201 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 10:57:40.900870 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 10:57:40.904284 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 10:57:40.907450 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 10:57:40.911147 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 10:57:40.914301 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 10:57:40.917554 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 10:57:40.920705 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 10:57:40.923948 Pre-setting of DQS Precalculation
3641 10:57:40.927659 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3642 10:57:40.934089 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3643 10:57:40.940568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3644 10:57:40.944498
3645 10:57:40.944575
3646 10:57:40.944661 [Calibration Summary] 2400 Mbps
3647 10:57:40.947105 CH 0, Rank 0
3648 10:57:40.947178 SW Impedance : PASS
3649 10:57:40.950484 DUTY Scan : NO K
3650 10:57:40.953777 ZQ Calibration : PASS
3651 10:57:40.953858 Jitter Meter : NO K
3652 10:57:40.956945 CBT Training : PASS
3653 10:57:40.960868 Write leveling : PASS
3654 10:57:40.960944 RX DQS gating : PASS
3655 10:57:40.964062 RX DQ/DQS(RDDQC) : PASS
3656 10:57:40.967322 TX DQ/DQS : PASS
3657 10:57:40.967431 RX DATLAT : PASS
3658 10:57:40.970229 RX DQ/DQS(Engine): PASS
3659 10:57:40.974187 TX OE : NO K
3660 10:57:40.974339 All Pass.
3661 10:57:40.974436
3662 10:57:40.974522 CH 0, Rank 1
3663 10:57:40.977439 SW Impedance : PASS
3664 10:57:40.980437 DUTY Scan : NO K
3665 10:57:40.980543 ZQ Calibration : PASS
3666 10:57:40.983537 Jitter Meter : NO K
3667 10:57:40.987279 CBT Training : PASS
3668 10:57:40.987391 Write leveling : PASS
3669 10:57:40.990509 RX DQS gating : PASS
3670 10:57:40.990594 RX DQ/DQS(RDDQC) : PASS
3671 10:57:40.994121 TX DQ/DQS : PASS
3672 10:57:40.997199 RX DATLAT : PASS
3673 10:57:40.997291 RX DQ/DQS(Engine): PASS
3674 10:57:41.000415 TX OE : NO K
3675 10:57:41.000512 All Pass.
3676 10:57:41.000586
3677 10:57:41.003606 CH 1, Rank 0
3678 10:57:41.003701 SW Impedance : PASS
3679 10:57:41.007467 DUTY Scan : NO K
3680 10:57:41.010623 ZQ Calibration : PASS
3681 10:57:41.011094 Jitter Meter : NO K
3682 10:57:41.013860 CBT Training : PASS
3683 10:57:41.017523 Write leveling : PASS
3684 10:57:41.018021 RX DQS gating : PASS
3685 10:57:41.020746 RX DQ/DQS(RDDQC) : PASS
3686 10:57:41.023798 TX DQ/DQS : PASS
3687 10:57:41.024227 RX DATLAT : PASS
3688 10:57:41.026998 RX DQ/DQS(Engine): PASS
3689 10:57:41.030814 TX OE : NO K
3690 10:57:41.031376 All Pass.
3691 10:57:41.031745
3692 10:57:41.032063 CH 1, Rank 1
3693 10:57:41.034004 SW Impedance : PASS
3694 10:57:41.037009 DUTY Scan : NO K
3695 10:57:41.037522 ZQ Calibration : PASS
3696 10:57:41.040413 Jitter Meter : NO K
3697 10:57:41.043617 CBT Training : PASS
3698 10:57:41.044041 Write leveling : PASS
3699 10:57:41.047034 RX DQS gating : PASS
3700 10:57:41.047548 RX DQ/DQS(RDDQC) : PASS
3701 10:57:41.050818 TX DQ/DQS : PASS
3702 10:57:41.054261 RX DATLAT : PASS
3703 10:57:41.054703 RX DQ/DQS(Engine): PASS
3704 10:57:41.057447 TX OE : NO K
3705 10:57:41.057873 All Pass.
3706 10:57:41.058207
3707 10:57:41.060923 DramC Write-DBI off
3708 10:57:41.064136 PER_BANK_REFRESH: Hybrid Mode
3709 10:57:41.064561 TX_TRACKING: ON
3710 10:57:41.073800 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3711 10:57:41.076966 [FAST_K] Save calibration result to emmc
3712 10:57:41.079849 dramc_set_vcore_voltage set vcore to 650000
3713 10:57:41.083178 Read voltage for 600, 5
3714 10:57:41.083259 Vio18 = 0
3715 10:57:41.083329 Vcore = 650000
3716 10:57:41.086703 Vdram = 0
3717 10:57:41.086785 Vddq = 0
3718 10:57:41.086848 Vmddr = 0
3719 10:57:41.093452 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3720 10:57:41.096676 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3721 10:57:41.099707 MEM_TYPE=3, freq_sel=19
3722 10:57:41.103573 sv_algorithm_assistance_LP4_1600
3723 10:57:41.106580 ============ PULL DRAM RESETB DOWN ============
3724 10:57:41.112874 ========== PULL DRAM RESETB DOWN end =========
3725 10:57:41.116884 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 10:57:41.120017 ===================================
3727 10:57:41.123173 LPDDR4 DRAM CONFIGURATION
3728 10:57:41.126501 ===================================
3729 10:57:41.126920 EX_ROW_EN[0] = 0x0
3730 10:57:41.130251 EX_ROW_EN[1] = 0x0
3731 10:57:41.130756 LP4Y_EN = 0x0
3732 10:57:41.133433 WORK_FSP = 0x0
3733 10:57:41.133849 WL = 0x2
3734 10:57:41.136618 RL = 0x2
3735 10:57:41.137036 BL = 0x2
3736 10:57:41.139757 RPST = 0x0
3737 10:57:41.140298 RD_PRE = 0x0
3738 10:57:41.143516 WR_PRE = 0x1
3739 10:57:41.143931 WR_PST = 0x0
3740 10:57:41.146693 DBI_WR = 0x0
3741 10:57:41.149898 DBI_RD = 0x0
3742 10:57:41.150310 OTF = 0x1
3743 10:57:41.153387 ===================================
3744 10:57:41.156742 ===================================
3745 10:57:41.157160 ANA top config
3746 10:57:41.160132 ===================================
3747 10:57:41.163349 DLL_ASYNC_EN = 0
3748 10:57:41.166345 ALL_SLAVE_EN = 1
3749 10:57:41.169560 NEW_RANK_MODE = 1
3750 10:57:41.172630 DLL_IDLE_MODE = 1
3751 10:57:41.172711 LP45_APHY_COMB_EN = 1
3752 10:57:41.176008 TX_ODT_DIS = 1
3753 10:57:41.179429 NEW_8X_MODE = 1
3754 10:57:41.182779 ===================================
3755 10:57:41.186067 ===================================
3756 10:57:41.189357 data_rate = 1200
3757 10:57:41.193173 CKR = 1
3758 10:57:41.193294 DQ_P2S_RATIO = 8
3759 10:57:41.196349 ===================================
3760 10:57:41.199353 CA_P2S_RATIO = 8
3761 10:57:41.203011 DQ_CA_OPEN = 0
3762 10:57:41.206162 DQ_SEMI_OPEN = 0
3763 10:57:41.209363 CA_SEMI_OPEN = 0
3764 10:57:41.213115 CA_FULL_RATE = 0
3765 10:57:41.213273 DQ_CKDIV4_EN = 1
3766 10:57:41.216461 CA_CKDIV4_EN = 1
3767 10:57:41.219376 CA_PREDIV_EN = 0
3768 10:57:41.222780 PH8_DLY = 0
3769 10:57:41.226106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3770 10:57:41.229223 DQ_AAMCK_DIV = 4
3771 10:57:41.229473 CA_AAMCK_DIV = 4
3772 10:57:41.233260 CA_ADMCK_DIV = 4
3773 10:57:41.235965 DQ_TRACK_CA_EN = 0
3774 10:57:41.239606 CA_PICK = 600
3775 10:57:41.242793 CA_MCKIO = 600
3776 10:57:41.245978 MCKIO_SEMI = 0
3777 10:57:41.250189 PLL_FREQ = 2288
3778 10:57:41.250714 DQ_UI_PI_RATIO = 32
3779 10:57:41.252641 CA_UI_PI_RATIO = 0
3780 10:57:41.256688 ===================================
3781 10:57:41.259896 ===================================
3782 10:57:41.263244 memory_type:LPDDR4
3783 10:57:41.266382 GP_NUM : 10
3784 10:57:41.266939 SRAM_EN : 1
3785 10:57:41.269409 MD32_EN : 0
3786 10:57:41.272927 ===================================
3787 10:57:41.273499 [ANA_INIT] >>>>>>>>>>>>>>
3788 10:57:41.275974 <<<<<< [CONFIGURE PHASE]: ANA_TX
3789 10:57:41.279496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3790 10:57:41.283396 ===================================
3791 10:57:41.286691 data_rate = 1200,PCW = 0X5800
3792 10:57:41.289931 ===================================
3793 10:57:41.293341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3794 10:57:41.299444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 10:57:41.306409 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 10:57:41.309175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3797 10:57:41.312754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3798 10:57:41.316421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3799 10:57:41.319292 [ANA_INIT] flow start
3800 10:57:41.319798 [ANA_INIT] PLL >>>>>>>>
3801 10:57:41.322687 [ANA_INIT] PLL <<<<<<<<
3802 10:57:41.326506 [ANA_INIT] MIDPI >>>>>>>>
3803 10:57:41.326978 [ANA_INIT] MIDPI <<<<<<<<
3804 10:57:41.329827 [ANA_INIT] DLL >>>>>>>>
3805 10:57:41.332923 [ANA_INIT] flow end
3806 10:57:41.335953 ============ LP4 DIFF to SE enter ============
3807 10:57:41.339633 ============ LP4 DIFF to SE exit ============
3808 10:57:41.342752 [ANA_INIT] <<<<<<<<<<<<<
3809 10:57:41.346031 [Flow] Enable top DCM control >>>>>
3810 10:57:41.349333 [Flow] Enable top DCM control <<<<<
3811 10:57:41.352758 Enable DLL master slave shuffle
3812 10:57:41.355937 ==============================================================
3813 10:57:41.359421 Gating Mode config
3814 10:57:41.366477 ==============================================================
3815 10:57:41.367042 Config description:
3816 10:57:41.376426 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3817 10:57:41.382689 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3818 10:57:41.386269 SELPH_MODE 0: By rank 1: By Phase
3819 10:57:41.392484 ==============================================================
3820 10:57:41.395653 GAT_TRACK_EN = 1
3821 10:57:41.399008 RX_GATING_MODE = 2
3822 10:57:41.402757 RX_GATING_TRACK_MODE = 2
3823 10:57:41.405552 SELPH_MODE = 1
3824 10:57:41.409170 PICG_EARLY_EN = 1
3825 10:57:41.412279 VALID_LAT_VALUE = 1
3826 10:57:41.415912 ==============================================================
3827 10:57:41.419015 Enter into Gating configuration >>>>
3828 10:57:41.422650 Exit from Gating configuration <<<<
3829 10:57:41.425617 Enter into DVFS_PRE_config >>>>>
3830 10:57:41.438676 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3831 10:57:41.439295 Exit from DVFS_PRE_config <<<<<
3832 10:57:41.442130 Enter into PICG configuration >>>>
3833 10:57:41.445706 Exit from PICG configuration <<<<
3834 10:57:41.448908 [RX_INPUT] configuration >>>>>
3835 10:57:41.452272 [RX_INPUT] configuration <<<<<
3836 10:57:41.458946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3837 10:57:41.462491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3838 10:57:41.468752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 10:57:41.475185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 10:57:41.482014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 10:57:41.488391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 10:57:41.491699 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3843 10:57:41.495409 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3844 10:57:41.498678 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3845 10:57:41.505466 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3846 10:57:41.509024 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3847 10:57:41.512092 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 10:57:41.515038 ===================================
3849 10:57:41.518365 LPDDR4 DRAM CONFIGURATION
3850 10:57:41.521913 ===================================
3851 10:57:41.522382 EX_ROW_EN[0] = 0x0
3852 10:57:41.524995 EX_ROW_EN[1] = 0x0
3853 10:57:41.529004 LP4Y_EN = 0x0
3854 10:57:41.529520 WORK_FSP = 0x0
3855 10:57:41.532019 WL = 0x2
3856 10:57:41.532482 RL = 0x2
3857 10:57:41.534998 BL = 0x2
3858 10:57:41.535452 RPST = 0x0
3859 10:57:41.538291 RD_PRE = 0x0
3860 10:57:41.538712 WR_PRE = 0x1
3861 10:57:41.542041 WR_PST = 0x0
3862 10:57:41.542460 DBI_WR = 0x0
3863 10:57:41.545271 DBI_RD = 0x0
3864 10:57:41.545790 OTF = 0x1
3865 10:57:41.548258 ===================================
3866 10:57:41.551961 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3867 10:57:41.558571 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3868 10:57:41.561760 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 10:57:41.565102 ===================================
3870 10:57:41.568071 LPDDR4 DRAM CONFIGURATION
3871 10:57:41.571477 ===================================
3872 10:57:41.571992 EX_ROW_EN[0] = 0x10
3873 10:57:41.574643 EX_ROW_EN[1] = 0x0
3874 10:57:41.578095 LP4Y_EN = 0x0
3875 10:57:41.578625 WORK_FSP = 0x0
3876 10:57:41.581010 WL = 0x2
3877 10:57:41.581092 RL = 0x2
3878 10:57:41.584816 BL = 0x2
3879 10:57:41.584898 RPST = 0x0
3880 10:57:41.588006 RD_PRE = 0x0
3881 10:57:41.588087 WR_PRE = 0x1
3882 10:57:41.591218 WR_PST = 0x0
3883 10:57:41.591301 DBI_WR = 0x0
3884 10:57:41.594398 DBI_RD = 0x0
3885 10:57:41.594480 OTF = 0x1
3886 10:57:41.597664 ===================================
3887 10:57:41.604304 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3888 10:57:41.608306 nWR fixed to 30
3889 10:57:41.611637 [ModeRegInit_LP4] CH0 RK0
3890 10:57:41.611711 [ModeRegInit_LP4] CH0 RK1
3891 10:57:41.614989 [ModeRegInit_LP4] CH1 RK0
3892 10:57:41.618309 [ModeRegInit_LP4] CH1 RK1
3893 10:57:41.618407 match AC timing 17
3894 10:57:41.624939 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3895 10:57:41.628578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3896 10:57:41.631773 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3897 10:57:41.638563 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3898 10:57:41.641791 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3899 10:57:41.641874 ==
3900 10:57:41.645011 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 10:57:41.648772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3902 10:57:41.648854 ==
3903 10:57:41.655560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3904 10:57:41.661823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3905 10:57:41.665094 [CA 0] Center 35 (4~66) winsize 63
3906 10:57:41.668349 [CA 1] Center 35 (5~66) winsize 62
3907 10:57:41.672108 [CA 2] Center 33 (3~64) winsize 62
3908 10:57:41.675020 [CA 3] Center 33 (2~64) winsize 63
3909 10:57:41.678677 [CA 4] Center 33 (2~64) winsize 63
3910 10:57:41.681750 [CA 5] Center 32 (2~63) winsize 62
3911 10:57:41.681832
3912 10:57:41.685125 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3913 10:57:41.685207
3914 10:57:41.688304 [CATrainingPosCal] consider 1 rank data
3915 10:57:41.692210 u2DelayCellTimex100 = 270/100 ps
3916 10:57:41.695354 CA0 delay=35 (4~66),Diff = 3 PI (28 cell)
3917 10:57:41.698687 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3918 10:57:41.701996 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3919 10:57:41.705228 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3920 10:57:41.708565 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 10:57:41.712025 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3922 10:57:41.712125
3923 10:57:41.717988 CA PerBit enable=1, Macro0, CA PI delay=32
3924 10:57:41.718088
3925 10:57:41.721322 [CBTSetCACLKResult] CA Dly = 32
3926 10:57:41.721421 CS Dly: 4 (0~35)
3927 10:57:41.721515 ==
3928 10:57:41.724596 Dram Type= 6, Freq= 0, CH_0, rank 1
3929 10:57:41.728239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 10:57:41.728347 ==
3931 10:57:41.734980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 10:57:41.741258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 10:57:41.745034 [CA 0] Center 36 (5~67) winsize 63
3934 10:57:41.748328 [CA 1] Center 36 (5~67) winsize 63
3935 10:57:41.751559 [CA 2] Center 34 (3~65) winsize 63
3936 10:57:41.754832 [CA 3] Center 34 (3~65) winsize 63
3937 10:57:41.757957 [CA 4] Center 33 (2~64) winsize 63
3938 10:57:41.761707 [CA 5] Center 32 (2~63) winsize 62
3939 10:57:41.761807
3940 10:57:41.765068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 10:57:41.765175
3942 10:57:41.768106 [CATrainingPosCal] consider 2 rank data
3943 10:57:41.771456 u2DelayCellTimex100 = 270/100 ps
3944 10:57:41.774662 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3945 10:57:41.777812 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 10:57:41.781052 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3947 10:57:41.784286 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 10:57:41.787963 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3949 10:57:41.794679 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3950 10:57:41.794761
3951 10:57:41.798118 CA PerBit enable=1, Macro0, CA PI delay=32
3952 10:57:41.798205
3953 10:57:41.801334 [CBTSetCACLKResult] CA Dly = 32
3954 10:57:41.801428 CS Dly: 4 (0~35)
3955 10:57:41.801503
3956 10:57:41.804698 ----->DramcWriteLeveling(PI) begin...
3957 10:57:41.804793 ==
3958 10:57:41.807915 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 10:57:41.811260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 10:57:41.814842 ==
3961 10:57:41.818097 Write leveling (Byte 0): 34 => 34
3962 10:57:41.818298 Write leveling (Byte 1): 33 => 33
3963 10:57:41.821460 DramcWriteLeveling(PI) end<-----
3964 10:57:41.821674
3965 10:57:41.821792 ==
3966 10:57:41.824840 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 10:57:41.831430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 10:57:41.831684 ==
3969 10:57:41.835120 [Gating] SW mode calibration
3970 10:57:41.841552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 10:57:41.844839 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3972 10:57:41.851876 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 10:57:41.855211 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 10:57:41.858399 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3975 10:57:41.861346 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
3976 10:57:41.868352 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
3977 10:57:41.871579 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 10:57:41.874743 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 10:57:41.881410 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 10:57:41.884989 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 10:57:41.888235 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 10:57:41.894781 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 10:57:41.897928 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
3984 10:57:41.901705 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3985 10:57:41.908225 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 10:57:41.911497 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 10:57:41.914919 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 10:57:41.921664 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 10:57:41.924760 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 10:57:41.928055 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 10:57:41.934653 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3992 10:57:41.937951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3993 10:57:41.941729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 10:57:41.948002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 10:57:41.951685 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 10:57:41.954807 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 10:57:41.961534 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 10:57:41.964664 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 10:57:41.968028 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 10:57:41.974910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 10:57:41.978298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 10:57:41.981329 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:57:41.984776 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:57:41.991316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:57:41.994461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:57:41.997823 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:57:42.004284 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4008 10:57:42.007988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 10:57:42.011314 Total UI for P1: 0, mck2ui 16
4010 10:57:42.014608 best dqsien dly found for B0: ( 0, 13, 12)
4011 10:57:42.017952 Total UI for P1: 0, mck2ui 16
4012 10:57:42.021151 best dqsien dly found for B1: ( 0, 13, 14)
4013 10:57:42.024419 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4014 10:57:42.027754 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4015 10:57:42.028172
4016 10:57:42.031073 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4017 10:57:42.034321 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 10:57:42.037528 [Gating] SW calibration Done
4019 10:57:42.037946 ==
4020 10:57:42.041218 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 10:57:42.047624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 10:57:42.048055 ==
4023 10:57:42.048388 RX Vref Scan: 0
4024 10:57:42.048700
4025 10:57:42.051363 RX Vref 0 -> 0, step: 1
4026 10:57:42.051784
4027 10:57:42.054487 RX Delay -230 -> 252, step: 16
4028 10:57:42.057418 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4029 10:57:42.061126 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4030 10:57:42.064247 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4031 10:57:42.070973 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4032 10:57:42.074306 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4033 10:57:42.077305 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4034 10:57:42.081024 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4035 10:57:42.087267 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4036 10:57:42.090440 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4037 10:57:42.094102 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4038 10:57:42.097520 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4039 10:57:42.100597 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4040 10:57:42.107225 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4041 10:57:42.110458 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4042 10:57:42.113525 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4043 10:57:42.120123 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4044 10:57:42.120211 ==
4045 10:57:42.123348 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 10:57:42.126768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 10:57:42.126870 ==
4048 10:57:42.126950 DQS Delay:
4049 10:57:42.130166 DQS0 = 0, DQS1 = 0
4050 10:57:42.130285 DQM Delay:
4051 10:57:42.133464 DQM0 = 52, DQM1 = 47
4052 10:57:42.133575 DQ Delay:
4053 10:57:42.136812 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4054 10:57:42.140290 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4055 10:57:42.143230 DQ8 =41, DQ9 =25, DQ10 =49, DQ11 =49
4056 10:57:42.147235 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4057 10:57:42.147368
4058 10:57:42.147441
4059 10:57:42.147506 ==
4060 10:57:42.149828 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 10:57:42.153215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 10:57:42.153310 ==
4063 10:57:42.153385
4064 10:57:42.153454
4065 10:57:42.156944 TX Vref Scan disable
4066 10:57:42.160053 == TX Byte 0 ==
4067 10:57:42.163556 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4068 10:57:42.166886 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4069 10:57:42.170313 == TX Byte 1 ==
4070 10:57:42.173553 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4071 10:57:42.176627 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4072 10:57:42.176832 ==
4073 10:57:42.180050 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 10:57:42.186404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 10:57:42.186715 ==
4076 10:57:42.186896
4077 10:57:42.187054
4078 10:57:42.187232 TX Vref Scan disable
4079 10:57:42.190785 == TX Byte 0 ==
4080 10:57:42.194061 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4081 10:57:42.200950 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4082 10:57:42.201340 == TX Byte 1 ==
4083 10:57:42.204414 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4084 10:57:42.210953 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4085 10:57:42.211409
4086 10:57:42.211750 [DATLAT]
4087 10:57:42.212159 Freq=600, CH0 RK0
4088 10:57:42.212471
4089 10:57:42.214302 DATLAT Default: 0x9
4090 10:57:42.214765 0, 0xFFFF, sum = 0
4091 10:57:42.217596 1, 0xFFFF, sum = 0
4092 10:57:42.218022 2, 0xFFFF, sum = 0
4093 10:57:42.220745 3, 0xFFFF, sum = 0
4094 10:57:42.224390 4, 0xFFFF, sum = 0
4095 10:57:42.224927 5, 0xFFFF, sum = 0
4096 10:57:42.227437 6, 0xFFFF, sum = 0
4097 10:57:42.227910 7, 0xFFFF, sum = 0
4098 10:57:42.230903 8, 0x0, sum = 1
4099 10:57:42.231359 9, 0x0, sum = 2
4100 10:57:42.231731 10, 0x0, sum = 3
4101 10:57:42.234282 11, 0x0, sum = 4
4102 10:57:42.234707 best_step = 9
4103 10:57:42.235040
4104 10:57:42.235392 ==
4105 10:57:42.237553 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 10:57:42.244024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 10:57:42.244446 ==
4108 10:57:42.244779 RX Vref Scan: 1
4109 10:57:42.245093
4110 10:57:42.247502 RX Vref 0 -> 0, step: 1
4111 10:57:42.247921
4112 10:57:42.250894 RX Delay -179 -> 252, step: 8
4113 10:57:42.251315
4114 10:57:42.254189 Set Vref, RX VrefLevel [Byte0]: 54
4115 10:57:42.257641 [Byte1]: 57
4116 10:57:42.258072
4117 10:57:42.260786 Final RX Vref Byte 0 = 54 to rank0
4118 10:57:42.264584 Final RX Vref Byte 1 = 57 to rank0
4119 10:57:42.267198 Final RX Vref Byte 0 = 54 to rank1
4120 10:57:42.270811 Final RX Vref Byte 1 = 57 to rank1==
4121 10:57:42.274488 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 10:57:42.277611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 10:57:42.278035 ==
4124 10:57:42.280529 DQS Delay:
4125 10:57:42.281075 DQS0 = 0, DQS1 = 0
4126 10:57:42.281553 DQM Delay:
4127 10:57:42.284351 DQM0 = 53, DQM1 = 47
4128 10:57:42.284846 DQ Delay:
4129 10:57:42.287641 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4130 10:57:42.290922 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4131 10:57:42.294041 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =44
4132 10:57:42.297784 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4133 10:57:42.298204
4134 10:57:42.298534
4135 10:57:42.307763 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4136 10:57:42.310976 CH0 RK0: MR19=808, MR18=6D60
4137 10:57:42.314313 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4138 10:57:42.314815
4139 10:57:42.317475 ----->DramcWriteLeveling(PI) begin...
4140 10:57:42.320755 ==
4141 10:57:42.324150 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 10:57:42.327403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 10:57:42.327825 ==
4144 10:57:42.330585 Write leveling (Byte 0): 34 => 34
4145 10:57:42.334216 Write leveling (Byte 1): 29 => 29
4146 10:57:42.337414 DramcWriteLeveling(PI) end<-----
4147 10:57:42.337837
4148 10:57:42.338168 ==
4149 10:57:42.340634 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 10:57:42.343703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 10:57:42.344132 ==
4152 10:57:42.347169 [Gating] SW mode calibration
4153 10:57:42.354295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4154 10:57:42.360768 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4155 10:57:42.363986 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 10:57:42.366813 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 10:57:42.373680 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 10:57:42.377080 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4159 10:57:42.380227 0 9 16 | B1->B0 | 2a2a 2828 | 1 0 | (1 0) (0 0)
4160 10:57:42.386811 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 10:57:42.390584 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 10:57:42.393789 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 10:57:42.397063 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 10:57:42.403835 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 10:57:42.406887 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 10:57:42.410041 0 10 12 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
4167 10:57:42.416989 0 10 16 | B1->B0 | 4141 4343 | 0 0 | (0 0) (0 0)
4168 10:57:42.420187 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 10:57:42.423455 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 10:57:42.430078 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 10:57:42.433464 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 10:57:42.436706 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 10:57:42.443655 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4174 10:57:42.446975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4175 10:57:42.450134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4176 10:57:42.456866 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 10:57:42.459843 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 10:57:42.463158 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 10:57:42.469715 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 10:57:42.473034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 10:57:42.476419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 10:57:42.483424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 10:57:42.486372 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 10:57:42.489713 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 10:57:42.496399 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 10:57:42.499477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:57:42.503280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:57:42.510154 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:57:42.512665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:57:42.516008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:57:42.523162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 10:57:42.523668 Total UI for P1: 0, mck2ui 16
4193 10:57:42.529638 best dqsien dly found for B0: ( 0, 13, 14)
4194 10:57:42.530059 Total UI for P1: 0, mck2ui 16
4195 10:57:42.536409 best dqsien dly found for B1: ( 0, 13, 14)
4196 10:57:42.539443 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4197 10:57:42.542924 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4198 10:57:42.543489
4199 10:57:42.546288 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 10:57:42.549835 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 10:57:42.552839 [Gating] SW calibration Done
4202 10:57:42.553259 ==
4203 10:57:42.556051 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 10:57:42.559524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 10:57:42.560050 ==
4206 10:57:42.562916 RX Vref Scan: 0
4207 10:57:42.563364
4208 10:57:42.563703 RX Vref 0 -> 0, step: 1
4209 10:57:42.564022
4210 10:57:42.566277 RX Delay -230 -> 252, step: 16
4211 10:57:42.572702 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4212 10:57:42.575981 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4213 10:57:42.579152 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4214 10:57:42.582570 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4215 10:57:42.585650 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4216 10:57:42.592803 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4217 10:57:42.595662 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4218 10:57:42.599202 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4219 10:57:42.602504 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4220 10:57:42.605972 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4221 10:57:42.612539 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4222 10:57:42.616085 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4223 10:57:42.619184 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4224 10:57:42.622276 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4225 10:57:42.628857 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4226 10:57:42.632542 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4227 10:57:42.633021 ==
4228 10:57:42.635815 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 10:57:42.638980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 10:57:42.639436 ==
4231 10:57:42.642479 DQS Delay:
4232 10:57:42.643044 DQS0 = 0, DQS1 = 0
4233 10:57:42.643559 DQM Delay:
4234 10:57:42.645501 DQM0 = 52, DQM1 = 43
4235 10:57:42.645999 DQ Delay:
4236 10:57:42.648798 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4237 10:57:42.652661 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4238 10:57:42.655870 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4239 10:57:42.659205 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4240 10:57:42.659659
4241 10:57:42.659995
4242 10:57:42.660306 ==
4243 10:57:42.662502 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 10:57:42.669062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 10:57:42.669526 ==
4246 10:57:42.669874
4247 10:57:42.670186
4248 10:57:42.670482 TX Vref Scan disable
4249 10:57:42.672889 == TX Byte 0 ==
4250 10:57:42.676211 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4251 10:57:42.683052 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4252 10:57:42.683601 == TX Byte 1 ==
4253 10:57:42.686246 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4254 10:57:42.689680 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4255 10:57:42.692664 ==
4256 10:57:42.696006 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 10:57:42.699448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 10:57:42.700037 ==
4259 10:57:42.700379
4260 10:57:42.700688
4261 10:57:42.702563 TX Vref Scan disable
4262 10:57:42.706048 == TX Byte 0 ==
4263 10:57:42.709011 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4264 10:57:42.712792 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4265 10:57:42.715972 == TX Byte 1 ==
4266 10:57:42.719510 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4267 10:57:42.722695 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4268 10:57:42.723120
4269 10:57:42.723544 [DATLAT]
4270 10:57:42.725695 Freq=600, CH0 RK1
4271 10:57:42.726121
4272 10:57:42.726457 DATLAT Default: 0x9
4273 10:57:42.729497 0, 0xFFFF, sum = 0
4274 10:57:42.732673 1, 0xFFFF, sum = 0
4275 10:57:42.733104 2, 0xFFFF, sum = 0
4276 10:57:42.735796 3, 0xFFFF, sum = 0
4277 10:57:42.736225 4, 0xFFFF, sum = 0
4278 10:57:42.738967 5, 0xFFFF, sum = 0
4279 10:57:42.739433 6, 0xFFFF, sum = 0
4280 10:57:42.742672 7, 0xFFFF, sum = 0
4281 10:57:42.743193 8, 0x0, sum = 1
4282 10:57:42.745693 9, 0x0, sum = 2
4283 10:57:42.746175 10, 0x0, sum = 3
4284 10:57:42.746522 11, 0x0, sum = 4
4285 10:57:42.748894 best_step = 9
4286 10:57:42.749314
4287 10:57:42.749647 ==
4288 10:57:42.752675 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 10:57:42.756117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 10:57:42.756696 ==
4291 10:57:42.759447 RX Vref Scan: 0
4292 10:57:42.759930
4293 10:57:42.760265 RX Vref 0 -> 0, step: 1
4294 10:57:42.760571
4295 10:57:42.762479 RX Delay -163 -> 252, step: 8
4296 10:57:42.769797 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4297 10:57:42.773111 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4298 10:57:42.776427 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4299 10:57:42.779799 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4300 10:57:42.786329 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4301 10:57:42.789759 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4302 10:57:42.792793 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4303 10:57:42.796022 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4304 10:57:42.799874 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4305 10:57:42.806457 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4306 10:57:42.809510 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4307 10:57:42.812765 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4308 10:57:42.816269 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4309 10:57:42.819394 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4310 10:57:42.825909 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4311 10:57:42.829131 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4312 10:57:42.829648 ==
4313 10:57:42.833093 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 10:57:42.836112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 10:57:42.836779 ==
4316 10:57:42.839268 DQS Delay:
4317 10:57:42.839840 DQS0 = 0, DQS1 = 0
4318 10:57:42.840362 DQM Delay:
4319 10:57:42.842550 DQM0 = 52, DQM1 = 46
4320 10:57:42.843098 DQ Delay:
4321 10:57:42.846165 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4322 10:57:42.849412 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4323 10:57:42.852393 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4324 10:57:42.855408 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4325 10:57:42.855828
4326 10:57:42.856242
4327 10:57:42.865935 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4328 10:57:42.869097 CH0 RK1: MR19=808, MR18=6425
4329 10:57:42.872378 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4330 10:57:42.875538 [RxdqsGatingPostProcess] freq 600
4331 10:57:42.882109 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4332 10:57:42.885399 Pre-setting of DQS Precalculation
4333 10:57:42.888817 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4334 10:57:42.888913 ==
4335 10:57:42.892100 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 10:57:42.898645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 10:57:42.898726 ==
4338 10:57:42.902047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4339 10:57:42.908882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4340 10:57:42.911648 [CA 0] Center 35 (5~66) winsize 62
4341 10:57:42.915036 [CA 1] Center 35 (5~66) winsize 62
4342 10:57:42.918284 [CA 2] Center 34 (4~65) winsize 62
4343 10:57:42.922288 [CA 3] Center 34 (4~65) winsize 62
4344 10:57:42.925275 [CA 4] Center 34 (4~65) winsize 62
4345 10:57:42.928614 [CA 5] Center 33 (3~64) winsize 62
4346 10:57:42.928801
4347 10:57:42.931690 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4348 10:57:42.931868
4349 10:57:42.934944 [CATrainingPosCal] consider 1 rank data
4350 10:57:42.938762 u2DelayCellTimex100 = 270/100 ps
4351 10:57:42.941686 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4352 10:57:42.945501 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4353 10:57:42.948654 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 10:57:42.955342 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4355 10:57:42.958551 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 10:57:42.961730 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4357 10:57:42.961847
4358 10:57:42.965315 CA PerBit enable=1, Macro0, CA PI delay=33
4359 10:57:42.965393
4360 10:57:42.968440 [CBTSetCACLKResult] CA Dly = 33
4361 10:57:42.968518 CS Dly: 6 (0~37)
4362 10:57:42.968584 ==
4363 10:57:42.971920 Dram Type= 6, Freq= 0, CH_1, rank 1
4364 10:57:42.978413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 10:57:42.978499 ==
4366 10:57:42.981702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 10:57:42.988374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4368 10:57:42.991726 [CA 0] Center 36 (5~67) winsize 63
4369 10:57:42.994904 [CA 1] Center 36 (5~67) winsize 63
4370 10:57:42.998229 [CA 2] Center 35 (4~66) winsize 63
4371 10:57:43.001607 [CA 3] Center 34 (4~65) winsize 62
4372 10:57:43.004932 [CA 4] Center 34 (4~65) winsize 62
4373 10:57:43.008385 [CA 5] Center 34 (3~65) winsize 63
4374 10:57:43.008481
4375 10:57:43.011984 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4376 10:57:43.012068
4377 10:57:43.015126 [CATrainingPosCal] consider 2 rank data
4378 10:57:43.018447 u2DelayCellTimex100 = 270/100 ps
4379 10:57:43.021785 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 10:57:43.025157 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 10:57:43.032022 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 10:57:43.035151 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 10:57:43.038140 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 10:57:43.041432 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 10:57:43.041525
4386 10:57:43.044700 CA PerBit enable=1, Macro0, CA PI delay=33
4387 10:57:43.044786
4388 10:57:43.048529 [CBTSetCACLKResult] CA Dly = 33
4389 10:57:43.048622 CS Dly: 6 (0~37)
4390 10:57:43.051562
4391 10:57:43.054792 ----->DramcWriteLeveling(PI) begin...
4392 10:57:43.054886 ==
4393 10:57:43.057869 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 10:57:43.061291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 10:57:43.061392 ==
4396 10:57:43.064710 Write leveling (Byte 0): 30 => 30
4397 10:57:43.067850 Write leveling (Byte 1): 30 => 30
4398 10:57:43.071136 DramcWriteLeveling(PI) end<-----
4399 10:57:43.071240
4400 10:57:43.071338 ==
4401 10:57:43.075006 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 10:57:43.078258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 10:57:43.078345 ==
4404 10:57:43.081441 [Gating] SW mode calibration
4405 10:57:43.088266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 10:57:43.094896 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4407 10:57:43.098284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 10:57:43.101538 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 10:57:43.108247 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 10:57:43.110890 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 1)
4411 10:57:43.114350 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4412 10:57:43.121109 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 10:57:43.124411 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 10:57:43.127732 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 10:57:43.131113 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 10:57:43.138044 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 10:57:43.141173 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 10:57:43.144227 0 10 12 | B1->B0 | 3434 3838 | 0 0 | (0 0) (0 0)
4419 10:57:43.151310 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 10:57:43.154425 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 10:57:43.157575 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 10:57:43.164687 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 10:57:43.167818 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 10:57:43.171186 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 10:57:43.177702 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 10:57:43.180944 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4427 10:57:43.184241 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 10:57:43.190748 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 10:57:43.194276 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 10:57:43.197536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 10:57:43.204273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 10:57:43.207509 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 10:57:43.210893 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 10:57:43.217704 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 10:57:43.221091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 10:57:43.224279 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 10:57:43.230705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 10:57:43.234110 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:57:43.236851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:57:43.244130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:57:43.247408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4442 10:57:43.250525 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4443 10:57:43.257046 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 10:57:43.257130 Total UI for P1: 0, mck2ui 16
4445 10:57:43.263415 best dqsien dly found for B0: ( 0, 13, 10)
4446 10:57:43.263518 Total UI for P1: 0, mck2ui 16
4447 10:57:43.270229 best dqsien dly found for B1: ( 0, 13, 12)
4448 10:57:43.273609 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4449 10:57:43.276840 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4450 10:57:43.276939
4451 10:57:43.280116 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4452 10:57:43.283515 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4453 10:57:43.286762 [Gating] SW calibration Done
4454 10:57:43.286849 ==
4455 10:57:43.289936 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 10:57:43.293376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 10:57:43.293478 ==
4458 10:57:43.296562 RX Vref Scan: 0
4459 10:57:43.296661
4460 10:57:43.296729 RX Vref 0 -> 0, step: 1
4461 10:57:43.296792
4462 10:57:43.300500 RX Delay -230 -> 252, step: 16
4463 10:57:43.306862 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4464 10:57:43.310042 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4465 10:57:43.313581 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4466 10:57:43.316852 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4467 10:57:43.320069 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4468 10:57:43.326865 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4469 10:57:43.330064 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4470 10:57:43.333549 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4471 10:57:43.336808 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4472 10:57:43.343555 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4473 10:57:43.346849 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4474 10:57:43.349882 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4475 10:57:43.353563 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4476 10:57:43.359863 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4477 10:57:43.363099 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4478 10:57:43.366420 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4479 10:57:43.366505 ==
4480 10:57:43.369899 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 10:57:43.373049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 10:57:43.373134 ==
4483 10:57:43.376320 DQS Delay:
4484 10:57:43.376404 DQS0 = 0, DQS1 = 0
4485 10:57:43.379557 DQM Delay:
4486 10:57:43.379640 DQM0 = 52, DQM1 = 49
4487 10:57:43.379707 DQ Delay:
4488 10:57:43.382966 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4489 10:57:43.386183 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4490 10:57:43.389973 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4491 10:57:43.393534 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4492 10:57:43.393640
4493 10:57:43.393734
4494 10:57:43.396594 ==
4495 10:57:43.399905 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 10:57:43.403065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 10:57:43.403172 ==
4498 10:57:43.403290
4499 10:57:43.403400
4500 10:57:43.406240 TX Vref Scan disable
4501 10:57:43.406350 == TX Byte 0 ==
4502 10:57:43.409498 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4503 10:57:43.416215 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4504 10:57:43.416300 == TX Byte 1 ==
4505 10:57:43.422852 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 10:57:43.426109 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 10:57:43.426197 ==
4508 10:57:43.429389 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 10:57:43.432814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 10:57:43.432898 ==
4511 10:57:43.432964
4512 10:57:43.433025
4513 10:57:43.436267 TX Vref Scan disable
4514 10:57:43.439316 == TX Byte 0 ==
4515 10:57:43.442839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 10:57:43.446097 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 10:57:43.449342 == TX Byte 1 ==
4518 10:57:43.452675 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 10:57:43.455801 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 10:57:43.455905
4521 10:57:43.459050 [DATLAT]
4522 10:57:43.459158 Freq=600, CH1 RK0
4523 10:57:43.459253
4524 10:57:43.462967 DATLAT Default: 0x9
4525 10:57:43.463051 0, 0xFFFF, sum = 0
4526 10:57:43.465990 1, 0xFFFF, sum = 0
4527 10:57:43.466080 2, 0xFFFF, sum = 0
4528 10:57:43.469390 3, 0xFFFF, sum = 0
4529 10:57:43.469490 4, 0xFFFF, sum = 0
4530 10:57:43.472669 5, 0xFFFF, sum = 0
4531 10:57:43.472744 6, 0xFFFF, sum = 0
4532 10:57:43.476128 7, 0xFFFF, sum = 0
4533 10:57:43.476208 8, 0x0, sum = 1
4534 10:57:43.479090 9, 0x0, sum = 2
4535 10:57:43.479174 10, 0x0, sum = 3
4536 10:57:43.483076 11, 0x0, sum = 4
4537 10:57:43.483151 best_step = 9
4538 10:57:43.483214
4539 10:57:43.483274 ==
4540 10:57:43.486282 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 10:57:43.488934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 10:57:43.492203 ==
4543 10:57:43.492326 RX Vref Scan: 1
4544 10:57:43.492404
4545 10:57:43.495579 RX Vref 0 -> 0, step: 1
4546 10:57:43.495716
4547 10:57:43.498938 RX Delay -147 -> 252, step: 8
4548 10:57:43.499051
4549 10:57:43.502276 Set Vref, RX VrefLevel [Byte0]: 56
4550 10:57:43.505630 [Byte1]: 53
4551 10:57:43.505749
4552 10:57:43.508975 Final RX Vref Byte 0 = 56 to rank0
4553 10:57:43.512194 Final RX Vref Byte 1 = 53 to rank0
4554 10:57:43.516008 Final RX Vref Byte 0 = 56 to rank1
4555 10:57:43.519189 Final RX Vref Byte 1 = 53 to rank1==
4556 10:57:43.522642 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 10:57:43.525866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 10:57:43.525964 ==
4559 10:57:43.526029 DQS Delay:
4560 10:57:43.529136 DQS0 = 0, DQS1 = 0
4561 10:57:43.529229 DQM Delay:
4562 10:57:43.532487 DQM0 = 49, DQM1 = 45
4563 10:57:43.532584 DQ Delay:
4564 10:57:43.535797 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4565 10:57:43.539247 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4566 10:57:43.542417 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4567 10:57:43.545616 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4568 10:57:43.545705
4569 10:57:43.545791
4570 10:57:43.555598 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4571 10:57:43.555733 CH1 RK0: MR19=808, MR18=496E
4572 10:57:43.562465 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4573 10:57:43.562578
4574 10:57:43.565398 ----->DramcWriteLeveling(PI) begin...
4575 10:57:43.565517 ==
4576 10:57:43.568514 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 10:57:43.575517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 10:57:43.575624 ==
4579 10:57:43.578753 Write leveling (Byte 0): 31 => 31
4580 10:57:43.581822 Write leveling (Byte 1): 32 => 32
4581 10:57:43.581910 DramcWriteLeveling(PI) end<-----
4582 10:57:43.585324
4583 10:57:43.585409 ==
4584 10:57:43.588412 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 10:57:43.592266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 10:57:43.592351 ==
4587 10:57:43.595285 [Gating] SW mode calibration
4588 10:57:43.602252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 10:57:43.605467 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 10:57:43.611939 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 10:57:43.615086 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 10:57:43.618875 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4593 10:57:43.625317 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (0 0) (1 0)
4594 10:57:43.628569 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4595 10:57:43.631920 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 10:57:43.638604 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 10:57:43.641945 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 10:57:43.645064 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 10:57:43.651835 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 10:57:43.655083 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 10:57:43.658601 0 10 12 | B1->B0 | 3636 3434 | 1 1 | (0 0) (0 0)
4602 10:57:43.665024 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 10:57:43.668366 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 10:57:43.671496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 10:57:43.678144 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 10:57:43.681263 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 10:57:43.684941 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 10:57:43.691940 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 10:57:43.695031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4610 10:57:43.698592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 10:57:43.701564 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 10:57:43.708013 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 10:57:43.711379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 10:57:43.714582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 10:57:43.721715 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 10:57:43.724999 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 10:57:43.728259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 10:57:43.734834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 10:57:43.738238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 10:57:43.741466 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 10:57:43.748115 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:57:43.751251 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:57:43.754688 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:57:43.761613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:57:43.764368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4626 10:57:43.767581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 10:57:43.770937 Total UI for P1: 0, mck2ui 16
4628 10:57:43.774733 best dqsien dly found for B0: ( 0, 13, 12)
4629 10:57:43.777823 Total UI for P1: 0, mck2ui 16
4630 10:57:43.780732 best dqsien dly found for B1: ( 0, 13, 12)
4631 10:57:43.784139 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4632 10:57:43.790997 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4633 10:57:43.791106
4634 10:57:43.794148 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4635 10:57:43.797256 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4636 10:57:43.800434 [Gating] SW calibration Done
4637 10:57:43.800532 ==
4638 10:57:43.804014 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 10:57:43.807100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 10:57:43.807245 ==
4641 10:57:43.810274 RX Vref Scan: 0
4642 10:57:43.810485
4643 10:57:43.810586 RX Vref 0 -> 0, step: 1
4644 10:57:43.810673
4645 10:57:43.814123 RX Delay -230 -> 252, step: 16
4646 10:57:43.817114 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4647 10:57:43.823600 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4648 10:57:43.827201 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4649 10:57:43.830792 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4650 10:57:43.834084 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4651 10:57:43.840618 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4652 10:57:43.843945 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4653 10:57:43.847338 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4654 10:57:43.850641 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4655 10:57:43.854004 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4656 10:57:43.860731 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4657 10:57:43.863447 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4658 10:57:43.866717 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4659 10:57:43.870182 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4660 10:57:43.876878 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4661 10:57:43.880222 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4662 10:57:43.880306 ==
4663 10:57:43.883308 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 10:57:43.886524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 10:57:43.886605 ==
4666 10:57:43.890123 DQS Delay:
4667 10:57:43.890237 DQS0 = 0, DQS1 = 0
4668 10:57:43.890332 DQM Delay:
4669 10:57:43.893172 DQM0 = 49, DQM1 = 48
4670 10:57:43.893246 DQ Delay:
4671 10:57:43.897058 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4672 10:57:43.900173 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4673 10:57:43.903241 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4674 10:57:43.906967 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4675 10:57:43.907092
4676 10:57:43.907190
4677 10:57:43.907290 ==
4678 10:57:43.910127 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 10:57:43.917011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 10:57:43.917107 ==
4681 10:57:43.917175
4682 10:57:43.917236
4683 10:57:43.917295 TX Vref Scan disable
4684 10:57:43.920274 == TX Byte 0 ==
4685 10:57:43.923442 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4686 10:57:43.927291 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4687 10:57:43.930675 == TX Byte 1 ==
4688 10:57:43.933989 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4689 10:57:43.937315 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4690 10:57:43.940683 ==
4691 10:57:43.943748 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 10:57:43.947088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 10:57:43.947198 ==
4694 10:57:43.947309
4695 10:57:43.947398
4696 10:57:43.950502 TX Vref Scan disable
4697 10:57:43.950657 == TX Byte 0 ==
4698 10:57:43.957235 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4699 10:57:43.960466 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4700 10:57:43.960569 == TX Byte 1 ==
4701 10:57:43.967160 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4702 10:57:43.970510 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4703 10:57:43.970610
4704 10:57:43.970763 [DATLAT]
4705 10:57:43.973350 Freq=600, CH1 RK1
4706 10:57:43.973451
4707 10:57:43.973593 DATLAT Default: 0x9
4708 10:57:43.976711 0, 0xFFFF, sum = 0
4709 10:57:43.976813 1, 0xFFFF, sum = 0
4710 10:57:43.979997 2, 0xFFFF, sum = 0
4711 10:57:43.980127 3, 0xFFFF, sum = 0
4712 10:57:43.983384 4, 0xFFFF, sum = 0
4713 10:57:43.986898 5, 0xFFFF, sum = 0
4714 10:57:43.987037 6, 0xFFFF, sum = 0
4715 10:57:43.990293 7, 0xFFFF, sum = 0
4716 10:57:43.990378 8, 0x0, sum = 1
4717 10:57:43.990444 9, 0x0, sum = 2
4718 10:57:43.993410 10, 0x0, sum = 3
4719 10:57:43.993494 11, 0x0, sum = 4
4720 10:57:43.997119 best_step = 9
4721 10:57:43.997203
4722 10:57:43.997298 ==
4723 10:57:43.999974 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 10:57:44.003751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 10:57:44.003835 ==
4726 10:57:44.006885 RX Vref Scan: 0
4727 10:57:44.007005
4728 10:57:44.007115 RX Vref 0 -> 0, step: 1
4729 10:57:44.007233
4730 10:57:44.009943 RX Delay -163 -> 252, step: 8
4731 10:57:44.017216 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4732 10:57:44.021013 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4733 10:57:44.024140 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4734 10:57:44.027531 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4735 10:57:44.030666 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4736 10:57:44.037248 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4737 10:57:44.041029 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4738 10:57:44.044332 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4739 10:57:44.047590 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4740 10:57:44.050752 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4741 10:57:44.057594 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4742 10:57:44.060708 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4743 10:57:44.064045 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4744 10:57:44.067289 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4745 10:57:44.074014 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4746 10:57:44.077351 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4747 10:57:44.077446 ==
4748 10:57:44.080746 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 10:57:44.084199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 10:57:44.084277 ==
4751 10:57:44.084340 DQS Delay:
4752 10:57:44.087274 DQS0 = 0, DQS1 = 0
4753 10:57:44.087360 DQM Delay:
4754 10:57:44.090581 DQM0 = 48, DQM1 = 46
4755 10:57:44.090665 DQ Delay:
4756 10:57:44.094019 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4757 10:57:44.097301 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4758 10:57:44.100478 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4759 10:57:44.104176 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4760 10:57:44.104261
4761 10:57:44.104328
4762 10:57:44.114014 [DQSOSCAuto] RK1, (LSB)MR18= 0x651c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4763 10:57:44.114105 CH1 RK1: MR19=808, MR18=651C
4764 10:57:44.120942 CH1_RK1: MR19=0x808, MR18=0x651C, DQSOSC=390, MR23=63, INC=172, DEC=114
4765 10:57:44.124052 [RxdqsGatingPostProcess] freq 600
4766 10:57:44.130479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 10:57:44.134225 Pre-setting of DQS Precalculation
4768 10:57:44.137342 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 10:57:44.143854 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 10:57:44.151011 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 10:57:44.151121
4772 10:57:44.154382
4773 10:57:44.154480 [Calibration Summary] 1200 Mbps
4774 10:57:44.157585 CH 0, Rank 0
4775 10:57:44.157683 SW Impedance : PASS
4776 10:57:44.161022 DUTY Scan : NO K
4777 10:57:44.164109 ZQ Calibration : PASS
4778 10:57:44.164200 Jitter Meter : NO K
4779 10:57:44.167280 CBT Training : PASS
4780 10:57:44.170438 Write leveling : PASS
4781 10:57:44.170556 RX DQS gating : PASS
4782 10:57:44.173773 RX DQ/DQS(RDDQC) : PASS
4783 10:57:44.177032 TX DQ/DQS : PASS
4784 10:57:44.177162 RX DATLAT : PASS
4785 10:57:44.180474 RX DQ/DQS(Engine): PASS
4786 10:57:44.183811 TX OE : NO K
4787 10:57:44.183945 All Pass.
4788 10:57:44.184048
4789 10:57:44.184138 CH 0, Rank 1
4790 10:57:44.187135 SW Impedance : PASS
4791 10:57:44.190450 DUTY Scan : NO K
4792 10:57:44.190632 ZQ Calibration : PASS
4793 10:57:44.193804 Jitter Meter : NO K
4794 10:57:44.197123 CBT Training : PASS
4795 10:57:44.197352 Write leveling : PASS
4796 10:57:44.200496 RX DQS gating : PASS
4797 10:57:44.200715 RX DQ/DQS(RDDQC) : PASS
4798 10:57:44.203771 TX DQ/DQS : PASS
4799 10:57:44.207030 RX DATLAT : PASS
4800 10:57:44.207356 RX DQ/DQS(Engine): PASS
4801 10:57:44.210231 TX OE : NO K
4802 10:57:44.210534 All Pass.
4803 10:57:44.210809
4804 10:57:44.214011 CH 1, Rank 0
4805 10:57:44.214473 SW Impedance : PASS
4806 10:57:44.217041 DUTY Scan : NO K
4807 10:57:44.220249 ZQ Calibration : PASS
4808 10:57:44.220702 Jitter Meter : NO K
4809 10:57:44.223908 CBT Training : PASS
4810 10:57:44.227108 Write leveling : PASS
4811 10:57:44.227615 RX DQS gating : PASS
4812 10:57:44.230201 RX DQ/DQS(RDDQC) : PASS
4813 10:57:44.233801 TX DQ/DQS : PASS
4814 10:57:44.234262 RX DATLAT : PASS
4815 10:57:44.236987 RX DQ/DQS(Engine): PASS
4816 10:57:44.240512 TX OE : NO K
4817 10:57:44.240976 All Pass.
4818 10:57:44.241316
4819 10:57:44.241649 CH 1, Rank 1
4820 10:57:44.243534 SW Impedance : PASS
4821 10:57:44.247345 DUTY Scan : NO K
4822 10:57:44.247539 ZQ Calibration : PASS
4823 10:57:44.250715 Jitter Meter : NO K
4824 10:57:44.250953 CBT Training : PASS
4825 10:57:44.253939 Write leveling : PASS
4826 10:57:44.257158 RX DQS gating : PASS
4827 10:57:44.257293 RX DQ/DQS(RDDQC) : PASS
4828 10:57:44.260378 TX DQ/DQS : PASS
4829 10:57:44.263527 RX DATLAT : PASS
4830 10:57:44.263678 RX DQ/DQS(Engine): PASS
4831 10:57:44.266753 TX OE : NO K
4832 10:57:44.266857 All Pass.
4833 10:57:44.266938
4834 10:57:44.269970 DramC Write-DBI off
4835 10:57:44.273808 PER_BANK_REFRESH: Hybrid Mode
4836 10:57:44.273949 TX_TRACKING: ON
4837 10:57:44.283638 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 10:57:44.287042 [FAST_K] Save calibration result to emmc
4839 10:57:44.290370 dramc_set_vcore_voltage set vcore to 662500
4840 10:57:44.293649 Read voltage for 933, 3
4841 10:57:44.293761 Vio18 = 0
4842 10:57:44.293857 Vcore = 662500
4843 10:57:44.297145 Vdram = 0
4844 10:57:44.297228 Vddq = 0
4845 10:57:44.297293 Vmddr = 0
4846 10:57:44.303210 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 10:57:44.306921 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 10:57:44.310168 MEM_TYPE=3, freq_sel=17
4849 10:57:44.312971 sv_algorithm_assistance_LP4_1600
4850 10:57:44.316767 ============ PULL DRAM RESETB DOWN ============
4851 10:57:44.319875 ========== PULL DRAM RESETB DOWN end =========
4852 10:57:44.326674 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 10:57:44.329688 ===================================
4854 10:57:44.333045 LPDDR4 DRAM CONFIGURATION
4855 10:57:44.336358 ===================================
4856 10:57:44.336439 EX_ROW_EN[0] = 0x0
4857 10:57:44.339660 EX_ROW_EN[1] = 0x0
4858 10:57:44.339742 LP4Y_EN = 0x0
4859 10:57:44.342751 WORK_FSP = 0x0
4860 10:57:44.342834 WL = 0x3
4861 10:57:44.346580 RL = 0x3
4862 10:57:44.346686 BL = 0x2
4863 10:57:44.350143 RPST = 0x0
4864 10:57:44.350223 RD_PRE = 0x0
4865 10:57:44.352842 WR_PRE = 0x1
4866 10:57:44.352924 WR_PST = 0x0
4867 10:57:44.356713 DBI_WR = 0x0
4868 10:57:44.356796 DBI_RD = 0x0
4869 10:57:44.359700 OTF = 0x1
4870 10:57:44.362827 ===================================
4871 10:57:44.366098 ===================================
4872 10:57:44.366187 ANA top config
4873 10:57:44.369799 ===================================
4874 10:57:44.373165 DLL_ASYNC_EN = 0
4875 10:57:44.376846 ALL_SLAVE_EN = 1
4876 10:57:44.380349 NEW_RANK_MODE = 1
4877 10:57:44.380810 DLL_IDLE_MODE = 1
4878 10:57:44.383469 LP45_APHY_COMB_EN = 1
4879 10:57:44.386609 TX_ODT_DIS = 1
4880 10:57:44.390193 NEW_8X_MODE = 1
4881 10:57:44.393376 ===================================
4882 10:57:44.396742 ===================================
4883 10:57:44.400034 data_rate = 1866
4884 10:57:44.403300 CKR = 1
4885 10:57:44.403941 DQ_P2S_RATIO = 8
4886 10:57:44.406762 ===================================
4887 10:57:44.409790 CA_P2S_RATIO = 8
4888 10:57:44.412962 DQ_CA_OPEN = 0
4889 10:57:44.416063 DQ_SEMI_OPEN = 0
4890 10:57:44.419493 CA_SEMI_OPEN = 0
4891 10:57:44.419934 CA_FULL_RATE = 0
4892 10:57:44.422786 DQ_CKDIV4_EN = 1
4893 10:57:44.426097 CA_CKDIV4_EN = 1
4894 10:57:44.429288 CA_PREDIV_EN = 0
4895 10:57:44.433135 PH8_DLY = 0
4896 10:57:44.436155 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 10:57:44.436582 DQ_AAMCK_DIV = 4
4898 10:57:44.439397 CA_AAMCK_DIV = 4
4899 10:57:44.442924 CA_ADMCK_DIV = 4
4900 10:57:44.446020 DQ_TRACK_CA_EN = 0
4901 10:57:44.449597 CA_PICK = 933
4902 10:57:44.452331 CA_MCKIO = 933
4903 10:57:44.456136 MCKIO_SEMI = 0
4904 10:57:44.456291 PLL_FREQ = 3732
4905 10:57:44.459239 DQ_UI_PI_RATIO = 32
4906 10:57:44.462442 CA_UI_PI_RATIO = 0
4907 10:57:44.466226 ===================================
4908 10:57:44.469468 ===================================
4909 10:57:44.472723 memory_type:LPDDR4
4910 10:57:44.475748 GP_NUM : 10
4911 10:57:44.475855 SRAM_EN : 1
4912 10:57:44.478879 MD32_EN : 0
4913 10:57:44.482095 ===================================
4914 10:57:44.482196 [ANA_INIT] >>>>>>>>>>>>>>
4915 10:57:44.485954 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 10:57:44.489353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 10:57:44.492572 ===================================
4918 10:57:44.495966 data_rate = 1866,PCW = 0X8f00
4919 10:57:44.499199 ===================================
4920 10:57:44.502665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 10:57:44.509523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 10:57:44.512695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 10:57:44.519383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 10:57:44.522207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 10:57:44.525462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 10:57:44.528924 [ANA_INIT] flow start
4927 10:57:44.529003 [ANA_INIT] PLL >>>>>>>>
4928 10:57:44.532116 [ANA_INIT] PLL <<<<<<<<
4929 10:57:44.535385 [ANA_INIT] MIDPI >>>>>>>>
4930 10:57:44.535463 [ANA_INIT] MIDPI <<<<<<<<
4931 10:57:44.538932 [ANA_INIT] DLL >>>>>>>>
4932 10:57:44.542341 [ANA_INIT] flow end
4933 10:57:44.545478 ============ LP4 DIFF to SE enter ============
4934 10:57:44.548766 ============ LP4 DIFF to SE exit ============
4935 10:57:44.552263 [ANA_INIT] <<<<<<<<<<<<<
4936 10:57:44.555303 [Flow] Enable top DCM control >>>>>
4937 10:57:44.559128 [Flow] Enable top DCM control <<<<<
4938 10:57:44.562116 Enable DLL master slave shuffle
4939 10:57:44.565786 ==============================================================
4940 10:57:44.568799 Gating Mode config
4941 10:57:44.572637 ==============================================================
4942 10:57:44.575930 Config description:
4943 10:57:44.585378 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 10:57:44.592360 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 10:57:44.595116 SELPH_MODE 0: By rank 1: By Phase
4946 10:57:44.601792 ==============================================================
4947 10:57:44.605104 GAT_TRACK_EN = 1
4948 10:57:44.608676 RX_GATING_MODE = 2
4949 10:57:44.611948 RX_GATING_TRACK_MODE = 2
4950 10:57:44.615085 SELPH_MODE = 1
4951 10:57:44.618366 PICG_EARLY_EN = 1
4952 10:57:44.621589 VALID_LAT_VALUE = 1
4953 10:57:44.625071 ==============================================================
4954 10:57:44.628394 Enter into Gating configuration >>>>
4955 10:57:44.631598 Exit from Gating configuration <<<<
4956 10:57:44.634754 Enter into DVFS_PRE_config >>>>>
4957 10:57:44.648629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 10:57:44.648884 Exit from DVFS_PRE_config <<<<<
4959 10:57:44.652071 Enter into PICG configuration >>>>
4960 10:57:44.655124 Exit from PICG configuration <<<<
4961 10:57:44.658397 [RX_INPUT] configuration >>>>>
4962 10:57:44.661749 [RX_INPUT] configuration <<<<<
4963 10:57:44.668122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 10:57:44.671814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 10:57:44.678320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 10:57:44.684748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 10:57:44.691351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 10:57:44.698253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 10:57:44.701189 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 10:57:44.704515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 10:57:44.708390 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 10:57:44.714970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 10:57:44.718313 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 10:57:44.721642 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 10:57:44.724841 ===================================
4976 10:57:44.728220 LPDDR4 DRAM CONFIGURATION
4977 10:57:44.731539 ===================================
4978 10:57:44.731623 EX_ROW_EN[0] = 0x0
4979 10:57:44.734731 EX_ROW_EN[1] = 0x0
4980 10:57:44.734848 LP4Y_EN = 0x0
4981 10:57:44.737915 WORK_FSP = 0x0
4982 10:57:44.741821 WL = 0x3
4983 10:57:44.741923 RL = 0x3
4984 10:57:44.745200 BL = 0x2
4985 10:57:44.745297 RPST = 0x0
4986 10:57:44.747922 RD_PRE = 0x0
4987 10:57:44.748018 WR_PRE = 0x1
4988 10:57:44.751494 WR_PST = 0x0
4989 10:57:44.751592 DBI_WR = 0x0
4990 10:57:44.754655 DBI_RD = 0x0
4991 10:57:44.754750 OTF = 0x1
4992 10:57:44.758157 ===================================
4993 10:57:44.761258 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 10:57:44.768267 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 10:57:44.771363 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 10:57:44.774539 ===================================
4997 10:57:44.778232 LPDDR4 DRAM CONFIGURATION
4998 10:57:44.781211 ===================================
4999 10:57:44.781295 EX_ROW_EN[0] = 0x10
5000 10:57:44.784970 EX_ROW_EN[1] = 0x0
5001 10:57:44.785053 LP4Y_EN = 0x0
5002 10:57:44.788066 WORK_FSP = 0x0
5003 10:57:44.788149 WL = 0x3
5004 10:57:44.791174 RL = 0x3
5005 10:57:44.791284 BL = 0x2
5006 10:57:44.795183 RPST = 0x0
5007 10:57:44.795267 RD_PRE = 0x0
5008 10:57:44.798199 WR_PRE = 0x1
5009 10:57:44.801448 WR_PST = 0x0
5010 10:57:44.801538 DBI_WR = 0x0
5011 10:57:44.804596 DBI_RD = 0x0
5012 10:57:44.804731 OTF = 0x1
5013 10:57:44.807791 ===================================
5014 10:57:44.814559 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 10:57:44.818339 nWR fixed to 30
5016 10:57:44.821634 [ModeRegInit_LP4] CH0 RK0
5017 10:57:44.821715 [ModeRegInit_LP4] CH0 RK1
5018 10:57:44.825093 [ModeRegInit_LP4] CH1 RK0
5019 10:57:44.828362 [ModeRegInit_LP4] CH1 RK1
5020 10:57:44.828446 match AC timing 9
5021 10:57:44.834774 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 10:57:44.838034 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 10:57:44.841367 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 10:57:44.848329 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 10:57:44.851791 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 10:57:44.851915 ==
5027 10:57:44.854873 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 10:57:44.858435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 10:57:44.858572 ==
5030 10:57:44.865075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 10:57:44.871585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5032 10:57:44.874757 [CA 0] Center 37 (6~68) winsize 63
5033 10:57:44.878232 [CA 1] Center 37 (7~68) winsize 62
5034 10:57:44.881333 [CA 2] Center 34 (4~65) winsize 62
5035 10:57:44.885059 [CA 3] Center 34 (3~65) winsize 63
5036 10:57:44.888151 [CA 4] Center 33 (3~64) winsize 62
5037 10:57:44.891765 [CA 5] Center 32 (2~62) winsize 61
5038 10:57:44.892183
5039 10:57:44.894940 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5040 10:57:44.895470
5041 10:57:44.898104 [CATrainingPosCal] consider 1 rank data
5042 10:57:44.901967 u2DelayCellTimex100 = 270/100 ps
5043 10:57:44.904643 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5044 10:57:44.908291 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 10:57:44.911310 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5046 10:57:44.915269 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5047 10:57:44.918270 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5048 10:57:44.924970 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5049 10:57:44.925554
5050 10:57:44.928270 CA PerBit enable=1, Macro0, CA PI delay=32
5051 10:57:44.928865
5052 10:57:44.931612 [CBTSetCACLKResult] CA Dly = 32
5053 10:57:44.932092 CS Dly: 5 (0~36)
5054 10:57:44.932412 ==
5055 10:57:44.934820 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 10:57:44.938063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 10:57:44.938424 ==
5058 10:57:44.944990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 10:57:44.951290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 10:57:44.954909 [CA 0] Center 37 (6~68) winsize 63
5061 10:57:44.958212 [CA 1] Center 37 (6~68) winsize 63
5062 10:57:44.960837 [CA 2] Center 34 (4~65) winsize 62
5063 10:57:44.964772 [CA 3] Center 34 (3~65) winsize 63
5064 10:57:44.968237 [CA 4] Center 33 (3~63) winsize 61
5065 10:57:44.971337 [CA 5] Center 32 (2~62) winsize 61
5066 10:57:44.971424
5067 10:57:44.974831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 10:57:44.974923
5069 10:57:44.977452 [CATrainingPosCal] consider 2 rank data
5070 10:57:44.980701 u2DelayCellTimex100 = 270/100 ps
5071 10:57:44.984287 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5072 10:57:44.987291 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 10:57:44.990580 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5074 10:57:44.994381 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5075 10:57:45.000491 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5076 10:57:45.004190 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5077 10:57:45.004274
5078 10:57:45.007290 CA PerBit enable=1, Macro0, CA PI delay=32
5079 10:57:45.007388
5080 10:57:45.010707 [CBTSetCACLKResult] CA Dly = 32
5081 10:57:45.010791 CS Dly: 5 (0~37)
5082 10:57:45.010857
5083 10:57:45.013907 ----->DramcWriteLeveling(PI) begin...
5084 10:57:45.014009 ==
5085 10:57:45.017644 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 10:57:45.024126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 10:57:45.024225 ==
5088 10:57:45.027415 Write leveling (Byte 0): 31 => 31
5089 10:57:45.030742 Write leveling (Byte 1): 30 => 30
5090 10:57:45.030847 DramcWriteLeveling(PI) end<-----
5091 10:57:45.030957
5092 10:57:45.034197 ==
5093 10:57:45.037296 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 10:57:45.040680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 10:57:45.040861 ==
5096 10:57:45.043918 [Gating] SW mode calibration
5097 10:57:45.050750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 10:57:45.053885 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 10:57:45.060584 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5100 10:57:45.063948 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 10:57:45.067140 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 10:57:45.073792 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 10:57:45.077427 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 10:57:45.080466 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 10:57:45.087091 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5106 10:57:45.090342 0 14 28 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
5107 10:57:45.093636 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5108 10:57:45.100428 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 10:57:45.104195 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 10:57:45.108366 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 10:57:45.113792 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 10:57:45.117157 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 10:57:45.120292 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5114 10:57:45.127270 0 15 28 | B1->B0 | 2929 4040 | 0 0 | (0 0) (1 1)
5115 10:57:45.130387 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5116 10:57:45.133748 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 10:57:45.140209 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 10:57:45.143216 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 10:57:45.147213 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 10:57:45.153685 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 10:57:45.156934 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 10:57:45.160080 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 10:57:45.163273 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 10:57:45.170570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 10:57:45.173840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 10:57:45.177083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 10:57:45.183173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 10:57:45.186545 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 10:57:45.189774 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 10:57:45.196864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 10:57:45.200086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 10:57:45.203232 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 10:57:45.209987 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 10:57:45.213212 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:57:45.216504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:57:45.223104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:57:45.226344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:57:45.229850 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5139 10:57:45.233135 Total UI for P1: 0, mck2ui 16
5140 10:57:45.236260 best dqsien dly found for B0: ( 1, 2, 26)
5141 10:57:45.242958 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 10:57:45.246194 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 10:57:45.249928 Total UI for P1: 0, mck2ui 16
5144 10:57:45.252943 best dqsien dly found for B1: ( 1, 3, 0)
5145 10:57:45.256709 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5146 10:57:45.260005 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5147 10:57:45.260221
5148 10:57:45.263139 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5149 10:57:45.266416 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5150 10:57:45.269742 [Gating] SW calibration Done
5151 10:57:45.269938 ==
5152 10:57:45.272854 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 10:57:45.276239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 10:57:45.276386 ==
5155 10:57:45.279402 RX Vref Scan: 0
5156 10:57:45.279546
5157 10:57:45.282772 RX Vref 0 -> 0, step: 1
5158 10:57:45.282914
5159 10:57:45.283044 RX Delay -80 -> 252, step: 8
5160 10:57:45.289945 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5161 10:57:45.293365 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5162 10:57:45.296565 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5163 10:57:45.299886 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5164 10:57:45.303144 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5165 10:57:45.306358 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5166 10:57:45.312779 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5167 10:57:45.316368 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5168 10:57:45.319615 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5169 10:57:45.322732 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5170 10:57:45.326584 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5171 10:57:45.329891 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5172 10:57:45.336159 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5173 10:57:45.339347 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5174 10:57:45.343231 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5175 10:57:45.346315 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5176 10:57:45.346400 ==
5177 10:57:45.349571 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 10:57:45.355944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 10:57:45.356042 ==
5180 10:57:45.356118 DQS Delay:
5181 10:57:45.359821 DQS0 = 0, DQS1 = 0
5182 10:57:45.359919 DQM Delay:
5183 10:57:45.359995 DQM0 = 104, DQM1 = 94
5184 10:57:45.363081 DQ Delay:
5185 10:57:45.366291 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5186 10:57:45.369476 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5187 10:57:45.372713 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5188 10:57:45.376069 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5189 10:57:45.376210
5190 10:57:45.376319
5191 10:57:45.376422 ==
5192 10:57:45.379302 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 10:57:45.382616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 10:57:45.382774 ==
5195 10:57:45.382898
5196 10:57:45.383013
5197 10:57:45.386040 TX Vref Scan disable
5198 10:57:45.389122 == TX Byte 0 ==
5199 10:57:45.392613 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5200 10:57:45.395807 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5201 10:57:45.399227 == TX Byte 1 ==
5202 10:57:45.402487 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5203 10:57:45.406480 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5204 10:57:45.406898 ==
5205 10:57:45.409770 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 10:57:45.416006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 10:57:45.416428 ==
5208 10:57:45.416756
5209 10:57:45.417063
5210 10:57:45.417481 TX Vref Scan disable
5211 10:57:45.419670 == TX Byte 0 ==
5212 10:57:45.423232 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5213 10:57:45.430265 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5214 10:57:45.430684 == TX Byte 1 ==
5215 10:57:45.433327 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5216 10:57:45.439663 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5217 10:57:45.440083
5218 10:57:45.440466 [DATLAT]
5219 10:57:45.440781 Freq=933, CH0 RK0
5220 10:57:45.441079
5221 10:57:45.442862 DATLAT Default: 0xd
5222 10:57:45.443277 0, 0xFFFF, sum = 0
5223 10:57:45.446272 1, 0xFFFF, sum = 0
5224 10:57:45.446693 2, 0xFFFF, sum = 0
5225 10:57:45.449924 3, 0xFFFF, sum = 0
5226 10:57:45.450400 4, 0xFFFF, sum = 0
5227 10:57:45.453126 5, 0xFFFF, sum = 0
5228 10:57:45.456829 6, 0xFFFF, sum = 0
5229 10:57:45.457295 7, 0xFFFF, sum = 0
5230 10:57:45.459940 8, 0xFFFF, sum = 0
5231 10:57:45.460363 9, 0xFFFF, sum = 0
5232 10:57:45.463235 10, 0x0, sum = 1
5233 10:57:45.463704 11, 0x0, sum = 2
5234 10:57:45.464041 12, 0x0, sum = 3
5235 10:57:45.466403 13, 0x0, sum = 4
5236 10:57:45.466822 best_step = 11
5237 10:57:45.467148
5238 10:57:45.469727 ==
5239 10:57:45.470143 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 10:57:45.476664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 10:57:45.477087 ==
5242 10:57:45.477420 RX Vref Scan: 1
5243 10:57:45.477728
5244 10:57:45.479985 RX Vref 0 -> 0, step: 1
5245 10:57:45.480405
5246 10:57:45.483210 RX Delay -53 -> 252, step: 4
5247 10:57:45.483662
5248 10:57:45.486502 Set Vref, RX VrefLevel [Byte0]: 54
5249 10:57:45.489787 [Byte1]: 57
5250 10:57:45.490207
5251 10:57:45.493179 Final RX Vref Byte 0 = 54 to rank0
5252 10:57:45.496345 Final RX Vref Byte 1 = 57 to rank0
5253 10:57:45.499752 Final RX Vref Byte 0 = 54 to rank1
5254 10:57:45.502885 Final RX Vref Byte 1 = 57 to rank1==
5255 10:57:45.505754 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 10:57:45.509028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 10:57:45.509112 ==
5258 10:57:45.512458 DQS Delay:
5259 10:57:45.512541 DQS0 = 0, DQS1 = 0
5260 10:57:45.516404 DQM Delay:
5261 10:57:45.516486 DQM0 = 104, DQM1 = 97
5262 10:57:45.516551 DQ Delay:
5263 10:57:45.519602 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5264 10:57:45.522656 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5265 10:57:45.526366 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5266 10:57:45.532880 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5267 10:57:45.532962
5268 10:57:45.533026
5269 10:57:45.539116 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5270 10:57:45.542407 CH0 RK0: MR19=505, MR18=2E26
5271 10:57:45.549163 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5272 10:57:45.549246
5273 10:57:45.552502 ----->DramcWriteLeveling(PI) begin...
5274 10:57:45.552586 ==
5275 10:57:45.555808 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 10:57:45.559365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 10:57:45.559462 ==
5278 10:57:45.562561 Write leveling (Byte 0): 33 => 33
5279 10:57:45.565788 Write leveling (Byte 1): 30 => 30
5280 10:57:45.569091 DramcWriteLeveling(PI) end<-----
5281 10:57:45.569173
5282 10:57:45.569238 ==
5283 10:57:45.572345 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 10:57:45.575486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 10:57:45.575570 ==
5286 10:57:45.579224 [Gating] SW mode calibration
5287 10:57:45.585703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 10:57:45.592300 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 10:57:45.595523 0 14 0 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
5290 10:57:45.602596 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 10:57:45.605325 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 10:57:45.609376 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 10:57:45.615367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 10:57:45.619293 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 10:57:45.622605 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5296 10:57:45.625686 0 14 28 | B1->B0 | 2f2f 2c2c | 0 0 | (0 1) (0 1)
5297 10:57:45.632507 0 15 0 | B1->B0 | 2525 2525 | 0 0 | (0 0) (1 0)
5298 10:57:45.635986 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 10:57:45.639078 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 10:57:45.646064 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 10:57:45.649227 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 10:57:45.652416 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 10:57:45.659779 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5304 10:57:45.662329 0 15 28 | B1->B0 | 3939 3131 | 0 1 | (0 0) (1 1)
5305 10:57:45.666328 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5306 10:57:45.672892 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 10:57:45.676093 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 10:57:45.679356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 10:57:45.685783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 10:57:45.688896 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 10:57:45.692972 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 10:57:45.699389 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5313 10:57:45.702771 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 10:57:45.706103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 10:57:45.712826 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 10:57:45.715889 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 10:57:45.719227 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 10:57:45.725829 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 10:57:45.729108 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 10:57:45.732366 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 10:57:45.739251 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 10:57:45.742247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 10:57:45.745273 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 10:57:45.749285 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:57:45.755506 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:57:45.759265 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:57:45.762103 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:57:45.768625 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5329 10:57:45.772533 Total UI for P1: 0, mck2ui 16
5330 10:57:45.775667 best dqsien dly found for B0: ( 1, 2, 26)
5331 10:57:45.778479 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 10:57:45.782309 Total UI for P1: 0, mck2ui 16
5333 10:57:45.785352 best dqsien dly found for B1: ( 1, 2, 28)
5334 10:57:45.788495 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5335 10:57:45.792062 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5336 10:57:45.792142
5337 10:57:45.795287 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5338 10:57:45.798639 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5339 10:57:45.801976 [Gating] SW calibration Done
5340 10:57:45.802055 ==
5341 10:57:45.805503 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 10:57:45.812038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 10:57:45.812202 ==
5344 10:57:45.812285 RX Vref Scan: 0
5345 10:57:45.812358
5346 10:57:45.815427 RX Vref 0 -> 0, step: 1
5347 10:57:45.815552
5348 10:57:45.818472 RX Delay -80 -> 252, step: 8
5349 10:57:45.821955 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5350 10:57:45.825110 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5351 10:57:45.828511 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5352 10:57:45.831760 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5353 10:57:45.838216 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5354 10:57:45.841921 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5355 10:57:45.845120 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5356 10:57:45.848193 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5357 10:57:45.852142 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5358 10:57:45.855262 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5359 10:57:45.861456 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5360 10:57:45.865291 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5361 10:57:45.868339 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5362 10:57:45.871463 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5363 10:57:45.874766 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5364 10:57:45.877931 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5365 10:57:45.881388 ==
5366 10:57:45.881470 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 10:57:45.888237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 10:57:45.888319 ==
5369 10:57:45.888385 DQS Delay:
5370 10:57:45.891906 DQS0 = 0, DQS1 = 0
5371 10:57:45.891987 DQM Delay:
5372 10:57:45.895101 DQM0 = 104, DQM1 = 93
5373 10:57:45.895182 DQ Delay:
5374 10:57:45.898592 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5375 10:57:45.901785 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5376 10:57:45.905108 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5377 10:57:45.908508 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5378 10:57:45.908589
5379 10:57:45.908654
5380 10:57:45.908713 ==
5381 10:57:45.911659 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 10:57:45.915061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 10:57:45.915144 ==
5384 10:57:45.915208
5385 10:57:45.915268
5386 10:57:45.918368 TX Vref Scan disable
5387 10:57:45.921624 == TX Byte 0 ==
5388 10:57:45.924994 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5389 10:57:45.928383 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5390 10:57:45.931730 == TX Byte 1 ==
5391 10:57:45.934863 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5392 10:57:45.938019 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5393 10:57:45.938101 ==
5394 10:57:45.941359 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 10:57:45.947648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 10:57:45.947730 ==
5397 10:57:45.947794
5398 10:57:45.947854
5399 10:57:45.947912 TX Vref Scan disable
5400 10:57:45.952026 == TX Byte 0 ==
5401 10:57:45.955527 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5402 10:57:45.962475 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5403 10:57:45.962557 == TX Byte 1 ==
5404 10:57:45.965724 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5405 10:57:45.972330 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5406 10:57:45.972441
5407 10:57:45.972510 [DATLAT]
5408 10:57:45.972571 Freq=933, CH0 RK1
5409 10:57:45.972631
5410 10:57:45.975242 DATLAT Default: 0xb
5411 10:57:45.975391 0, 0xFFFF, sum = 0
5412 10:57:45.979062 1, 0xFFFF, sum = 0
5413 10:57:45.979145 2, 0xFFFF, sum = 0
5414 10:57:45.982091 3, 0xFFFF, sum = 0
5415 10:57:45.985405 4, 0xFFFF, sum = 0
5416 10:57:45.985488 5, 0xFFFF, sum = 0
5417 10:57:45.988505 6, 0xFFFF, sum = 0
5418 10:57:45.988587 7, 0xFFFF, sum = 0
5419 10:57:45.991753 8, 0xFFFF, sum = 0
5420 10:57:45.991836 9, 0xFFFF, sum = 0
5421 10:57:45.995579 10, 0x0, sum = 1
5422 10:57:45.995661 11, 0x0, sum = 2
5423 10:57:45.998546 12, 0x0, sum = 3
5424 10:57:45.998629 13, 0x0, sum = 4
5425 10:57:45.998694 best_step = 11
5426 10:57:45.998753
5427 10:57:46.002235 ==
5428 10:57:46.002317 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 10:57:46.008530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 10:57:46.008612 ==
5431 10:57:46.008677 RX Vref Scan: 0
5432 10:57:46.008737
5433 10:57:46.011690 RX Vref 0 -> 0, step: 1
5434 10:57:46.011771
5435 10:57:46.015024 RX Delay -53 -> 252, step: 4
5436 10:57:46.018320 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5437 10:57:46.025599 iDelay=195, Bit 1, Center 108 (23 ~ 194) 172
5438 10:57:46.028826 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5439 10:57:46.032091 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5440 10:57:46.035443 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5441 10:57:46.038833 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5442 10:57:46.044727 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5443 10:57:46.048127 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5444 10:57:46.051803 iDelay=195, Bit 8, Center 88 (7 ~ 170) 164
5445 10:57:46.054854 iDelay=195, Bit 9, Center 88 (7 ~ 170) 164
5446 10:57:46.058437 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5447 10:57:46.061497 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5448 10:57:46.068443 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5449 10:57:46.071519 iDelay=195, Bit 13, Center 100 (15 ~ 186) 172
5450 10:57:46.074882 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5451 10:57:46.078170 iDelay=195, Bit 15, Center 102 (23 ~ 182) 160
5452 10:57:46.078252 ==
5453 10:57:46.081398 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 10:57:46.088100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 10:57:46.088182 ==
5456 10:57:46.088247 DQS Delay:
5457 10:57:46.091261 DQS0 = 0, DQS1 = 0
5458 10:57:46.091399 DQM Delay:
5459 10:57:46.091465 DQM0 = 104, DQM1 = 95
5460 10:57:46.094659 DQ Delay:
5461 10:57:46.097916 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5462 10:57:46.101942 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5463 10:57:46.105108 DQ8 =88, DQ9 =88, DQ10 =94, DQ11 =88
5464 10:57:46.108095 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5465 10:57:46.108177
5466 10:57:46.108240
5467 10:57:46.114888 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5468 10:57:46.118083 CH0 RK1: MR19=505, MR18=2A02
5469 10:57:46.124719 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5470 10:57:46.128011 [RxdqsGatingPostProcess] freq 933
5471 10:57:46.134526 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 10:57:46.138419 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 10:57:46.138501 best DQS1 dly(2T, 0.5T) = (0, 11)
5474 10:57:46.141629 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 10:57:46.145057 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5476 10:57:46.148386 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 10:57:46.151610 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 10:57:46.154872 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 10:57:46.158099 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 10:57:46.161260 Pre-setting of DQS Precalculation
5481 10:57:46.167947 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 10:57:46.168029 ==
5483 10:57:46.171283 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 10:57:46.174741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 10:57:46.174823 ==
5486 10:57:46.181271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 10:57:46.184485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5488 10:57:46.188922 [CA 0] Center 36 (6~67) winsize 62
5489 10:57:46.191889 [CA 1] Center 36 (6~67) winsize 62
5490 10:57:46.195597 [CA 2] Center 34 (4~65) winsize 62
5491 10:57:46.198635 [CA 3] Center 34 (4~65) winsize 62
5492 10:57:46.201955 [CA 4] Center 34 (4~64) winsize 61
5493 10:57:46.205177 [CA 5] Center 33 (3~64) winsize 62
5494 10:57:46.205258
5495 10:57:46.208347 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5496 10:57:46.208428
5497 10:57:46.212029 [CATrainingPosCal] consider 1 rank data
5498 10:57:46.215224 u2DelayCellTimex100 = 270/100 ps
5499 10:57:46.218528 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5500 10:57:46.225428 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 10:57:46.228560 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 10:57:46.231787 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 10:57:46.235043 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5504 10:57:46.238292 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 10:57:46.238381
5506 10:57:46.241745 CA PerBit enable=1, Macro0, CA PI delay=33
5507 10:57:46.241828
5508 10:57:46.244787 [CBTSetCACLKResult] CA Dly = 33
5509 10:57:46.248686 CS Dly: 6 (0~37)
5510 10:57:46.248768 ==
5511 10:57:46.251937 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 10:57:46.255166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 10:57:46.255249 ==
5514 10:57:46.261688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 10:57:46.264975 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5516 10:57:46.268619 [CA 0] Center 36 (6~67) winsize 62
5517 10:57:46.271721 [CA 1] Center 37 (7~68) winsize 62
5518 10:57:46.275203 [CA 2] Center 35 (4~66) winsize 63
5519 10:57:46.278356 [CA 3] Center 34 (4~65) winsize 62
5520 10:57:46.281426 [CA 4] Center 34 (4~65) winsize 62
5521 10:57:46.284825 [CA 5] Center 33 (3~64) winsize 62
5522 10:57:46.284932
5523 10:57:46.288353 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5524 10:57:46.288436
5525 10:57:46.291557 [CATrainingPosCal] consider 2 rank data
5526 10:57:46.294871 u2DelayCellTimex100 = 270/100 ps
5527 10:57:46.297944 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5528 10:57:46.304707 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5529 10:57:46.308051 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5530 10:57:46.311244 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 10:57:46.315137 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5532 10:57:46.318457 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5533 10:57:46.318546
5534 10:57:46.321821 CA PerBit enable=1, Macro0, CA PI delay=33
5535 10:57:46.321916
5536 10:57:46.325033 [CBTSetCACLKResult] CA Dly = 33
5537 10:57:46.328337 CS Dly: 7 (0~39)
5538 10:57:46.328469
5539 10:57:46.331408 ----->DramcWriteLeveling(PI) begin...
5540 10:57:46.331546 ==
5541 10:57:46.335241 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 10:57:46.337682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 10:57:46.337790 ==
5544 10:57:46.341068 Write leveling (Byte 0): 28 => 28
5545 10:57:46.345201 Write leveling (Byte 1): 29 => 29
5546 10:57:46.348324 DramcWriteLeveling(PI) end<-----
5547 10:57:46.348412
5548 10:57:46.348509 ==
5549 10:57:46.351113 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 10:57:46.354476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 10:57:46.354600 ==
5552 10:57:46.358244 [Gating] SW mode calibration
5553 10:57:46.364523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 10:57:46.371054 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 10:57:46.374144 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 10:57:46.377941 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 10:57:46.384289 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 10:57:46.387389 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 10:57:46.390841 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 10:57:46.397963 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 10:57:46.401310 0 14 24 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 1)
5562 10:57:46.404348 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5563 10:57:46.411301 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 10:57:46.414351 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 10:57:46.417726 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 10:57:46.424046 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 10:57:46.427416 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 10:57:46.430725 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 10:57:46.437376 0 15 24 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5570 10:57:46.440379 0 15 28 | B1->B0 | 3838 4242 | 1 1 | (0 0) (0 0)
5571 10:57:46.443947 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 10:57:46.450366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 10:57:46.453753 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 10:57:46.457653 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 10:57:46.464038 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 10:57:46.467316 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 10:57:46.470769 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5578 10:57:46.477086 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5579 10:57:46.480261 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 10:57:46.483310 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 10:57:46.490417 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 10:57:46.493678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 10:57:46.496913 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 10:57:46.503278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 10:57:46.507208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 10:57:46.510319 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 10:57:46.516534 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 10:57:46.519693 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 10:57:46.523645 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:57:46.530130 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:57:46.533298 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:57:46.536708 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:57:46.543210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5594 10:57:46.546391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5595 10:57:46.550285 Total UI for P1: 0, mck2ui 16
5596 10:57:46.553413 best dqsien dly found for B1: ( 1, 2, 24)
5597 10:57:46.556312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 10:57:46.560245 Total UI for P1: 0, mck2ui 16
5599 10:57:46.563427 best dqsien dly found for B0: ( 1, 2, 26)
5600 10:57:46.566787 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5601 10:57:46.570076 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5602 10:57:46.570516
5603 10:57:46.573403 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5604 10:57:46.579961 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 10:57:46.580432 [Gating] SW calibration Done
5606 10:57:46.580772 ==
5607 10:57:46.583157 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 10:57:46.590041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 10:57:46.590493 ==
5610 10:57:46.590830 RX Vref Scan: 0
5611 10:57:46.591140
5612 10:57:46.592974 RX Vref 0 -> 0, step: 1
5613 10:57:46.593396
5614 10:57:46.596484 RX Delay -80 -> 252, step: 8
5615 10:57:46.599703 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5616 10:57:46.603406 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5617 10:57:46.606594 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5618 10:57:46.609836 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5619 10:57:46.616901 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5620 10:57:46.619947 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5621 10:57:46.622931 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5622 10:57:46.626261 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5623 10:57:46.630073 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5624 10:57:46.633711 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5625 10:57:46.639955 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5626 10:57:46.643147 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5627 10:57:46.646729 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5628 10:57:46.650385 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5629 10:57:46.653543 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5630 10:57:46.660092 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5631 10:57:46.660545 ==
5632 10:57:46.663190 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 10:57:46.666263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 10:57:46.666689 ==
5635 10:57:46.667026 DQS Delay:
5636 10:57:46.669574 DQS0 = 0, DQS1 = 0
5637 10:57:46.669999 DQM Delay:
5638 10:57:46.673002 DQM0 = 102, DQM1 = 98
5639 10:57:46.673431 DQ Delay:
5640 10:57:46.676896 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5641 10:57:46.679384 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5642 10:57:46.682394 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5643 10:57:46.686334 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5644 10:57:46.686417
5645 10:57:46.686482
5646 10:57:46.686542 ==
5647 10:57:46.689057 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 10:57:46.692774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 10:57:46.695947 ==
5650 10:57:46.696029
5651 10:57:46.696094
5652 10:57:46.696153 TX Vref Scan disable
5653 10:57:46.699497 == TX Byte 0 ==
5654 10:57:46.702359 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5655 10:57:46.706038 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5656 10:57:46.709047 == TX Byte 1 ==
5657 10:57:46.712877 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5658 10:57:46.716002 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5659 10:57:46.719289 ==
5660 10:57:46.722623 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 10:57:46.725776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 10:57:46.725859 ==
5663 10:57:46.725924
5664 10:57:46.725984
5665 10:57:46.728880 TX Vref Scan disable
5666 10:57:46.728962 == TX Byte 0 ==
5667 10:57:46.735455 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5668 10:57:46.739298 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5669 10:57:46.739452 == TX Byte 1 ==
5670 10:57:46.746229 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 10:57:46.749516 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 10:57:46.750118
5673 10:57:46.750629 [DATLAT]
5674 10:57:46.752820 Freq=933, CH1 RK0
5675 10:57:46.753374
5676 10:57:46.753891 DATLAT Default: 0xd
5677 10:57:46.755849 0, 0xFFFF, sum = 0
5678 10:57:46.756438 1, 0xFFFF, sum = 0
5679 10:57:46.759163 2, 0xFFFF, sum = 0
5680 10:57:46.759715 3, 0xFFFF, sum = 0
5681 10:57:46.762480 4, 0xFFFF, sum = 0
5682 10:57:46.763060 5, 0xFFFF, sum = 0
5683 10:57:46.765750 6, 0xFFFF, sum = 0
5684 10:57:46.766311 7, 0xFFFF, sum = 0
5685 10:57:46.769568 8, 0xFFFF, sum = 0
5686 10:57:46.772723 9, 0xFFFF, sum = 0
5687 10:57:46.773307 10, 0x0, sum = 1
5688 10:57:46.773847 11, 0x0, sum = 2
5689 10:57:46.776153 12, 0x0, sum = 3
5690 10:57:46.776690 13, 0x0, sum = 4
5691 10:57:46.779321 best_step = 11
5692 10:57:46.779936
5693 10:57:46.780449 ==
5694 10:57:46.782724 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 10:57:46.786078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 10:57:46.786625 ==
5697 10:57:46.789230 RX Vref Scan: 1
5698 10:57:46.789821
5699 10:57:46.790352 RX Vref 0 -> 0, step: 1
5700 10:57:46.790851
5701 10:57:46.792445 RX Delay -45 -> 252, step: 4
5702 10:57:46.793073
5703 10:57:46.796533 Set Vref, RX VrefLevel [Byte0]: 56
5704 10:57:46.799161 [Byte1]: 53
5705 10:57:46.803241
5706 10:57:46.803778 Final RX Vref Byte 0 = 56 to rank0
5707 10:57:46.806324 Final RX Vref Byte 1 = 53 to rank0
5708 10:57:46.810249 Final RX Vref Byte 0 = 56 to rank1
5709 10:57:46.813251 Final RX Vref Byte 1 = 53 to rank1==
5710 10:57:46.816982 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 10:57:46.823306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 10:57:46.823867 ==
5713 10:57:46.824256 DQS Delay:
5714 10:57:46.824574 DQS0 = 0, DQS1 = 0
5715 10:57:46.826689 DQM Delay:
5716 10:57:46.827104 DQM0 = 104, DQM1 = 99
5717 10:57:46.830017 DQ Delay:
5718 10:57:46.833203 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5719 10:57:46.836248 DQ4 =102, DQ5 =114, DQ6 =114, DQ7 =104
5720 10:57:46.839985 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5721 10:57:46.843043 DQ12 =104, DQ13 =108, DQ14 =108, DQ15 =108
5722 10:57:46.843648
5723 10:57:46.844080
5724 10:57:46.849695 [DQSOSCAuto] RK0, (LSB)MR18= 0x142c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5725 10:57:46.852888 CH1 RK0: MR19=505, MR18=142C
5726 10:57:46.859794 CH1_RK0: MR19=0x505, MR18=0x142C, DQSOSC=408, MR23=63, INC=65, DEC=43
5727 10:57:46.860306
5728 10:57:46.863168 ----->DramcWriteLeveling(PI) begin...
5729 10:57:46.863637 ==
5730 10:57:46.866453 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 10:57:46.869680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 10:57:46.870231 ==
5733 10:57:46.873051 Write leveling (Byte 0): 25 => 25
5734 10:57:46.876272 Write leveling (Byte 1): 26 => 26
5735 10:57:46.879265 DramcWriteLeveling(PI) end<-----
5736 10:57:46.879775
5737 10:57:46.880206 ==
5738 10:57:46.883222 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 10:57:46.889725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 10:57:46.890166 ==
5741 10:57:46.890592 [Gating] SW mode calibration
5742 10:57:46.899702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5743 10:57:46.902928 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5744 10:57:46.905663 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 10:57:46.912768 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 10:57:46.915770 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 10:57:46.918885 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 10:57:46.925611 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 10:57:46.929327 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 10:57:46.932762 0 14 24 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 1)
5751 10:57:46.939014 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5752 10:57:46.942264 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 10:57:46.945505 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 10:57:46.952605 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 10:57:46.955772 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 10:57:46.958907 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 10:57:46.965873 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 10:57:46.969151 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
5759 10:57:46.972588 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
5760 10:57:46.978881 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 10:57:46.982932 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 10:57:46.985971 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 10:57:46.989320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 10:57:46.995908 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 10:57:46.999159 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5766 10:57:47.002602 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 10:57:47.009274 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 10:57:47.012198 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 10:57:47.015835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 10:57:47.022132 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 10:57:47.025791 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 10:57:47.029442 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 10:57:47.035880 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 10:57:47.038966 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 10:57:47.042746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 10:57:47.049134 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 10:57:47.052606 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:57:47.055801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:57:47.062912 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:57:47.066003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:57:47.069251 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:57:47.076007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5783 10:57:47.079280 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 10:57:47.082715 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 10:57:47.085914 Total UI for P1: 0, mck2ui 16
5786 10:57:47.088885 best dqsien dly found for B0: ( 1, 2, 26)
5787 10:57:47.092571 Total UI for P1: 0, mck2ui 16
5788 10:57:47.095853 best dqsien dly found for B1: ( 1, 2, 26)
5789 10:57:47.099194 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5790 10:57:47.102930 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5791 10:57:47.103671
5792 10:57:47.105877 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5793 10:57:47.112317 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5794 10:57:47.112814 [Gating] SW calibration Done
5795 10:57:47.113339 ==
5796 10:57:47.116141 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 10:57:47.122487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 10:57:47.123034 ==
5799 10:57:47.123563 RX Vref Scan: 0
5800 10:57:47.123953
5801 10:57:47.125500 RX Vref 0 -> 0, step: 1
5802 10:57:47.125995
5803 10:57:47.129223 RX Delay -80 -> 252, step: 8
5804 10:57:47.132316 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5805 10:57:47.135991 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5806 10:57:47.139084 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5807 10:57:47.142521 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5808 10:57:47.149126 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5809 10:57:47.152296 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5810 10:57:47.155625 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5811 10:57:47.158665 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5812 10:57:47.161874 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5813 10:57:47.165298 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 10:57:47.172329 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 10:57:47.175437 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5816 10:57:47.178486 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5817 10:57:47.182220 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5818 10:57:47.185522 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5819 10:57:47.192066 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5820 10:57:47.192557 ==
5821 10:57:47.195288 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 10:57:47.198507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 10:57:47.199042 ==
5824 10:57:47.199429 DQS Delay:
5825 10:57:47.202283 DQS0 = 0, DQS1 = 0
5826 10:57:47.202808 DQM Delay:
5827 10:57:47.205457 DQM0 = 102, DQM1 = 99
5828 10:57:47.205877 DQ Delay:
5829 10:57:47.208693 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5830 10:57:47.212036 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5831 10:57:47.215354 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5832 10:57:47.218705 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5833 10:57:47.219126
5834 10:57:47.219501
5835 10:57:47.219819 ==
5836 10:57:47.222154 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 10:57:47.228598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 10:57:47.229022 ==
5839 10:57:47.229358
5840 10:57:47.229668
5841 10:57:47.230003 TX Vref Scan disable
5842 10:57:47.232188 == TX Byte 0 ==
5843 10:57:47.235509 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5844 10:57:47.242310 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5845 10:57:47.242735 == TX Byte 1 ==
5846 10:57:47.245305 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5847 10:57:47.252332 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5848 10:57:47.252776 ==
5849 10:57:47.255590 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 10:57:47.258748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 10:57:47.259173 ==
5852 10:57:47.259566
5853 10:57:47.259881
5854 10:57:47.262083 TX Vref Scan disable
5855 10:57:47.262533 == TX Byte 0 ==
5856 10:57:47.268475 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5857 10:57:47.271719 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5858 10:57:47.272142 == TX Byte 1 ==
5859 10:57:47.278355 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5860 10:57:47.281515 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5861 10:57:47.281940
5862 10:57:47.282276 [DATLAT]
5863 10:57:47.285578 Freq=933, CH1 RK1
5864 10:57:47.286005
5865 10:57:47.286338 DATLAT Default: 0xb
5866 10:57:47.288775 0, 0xFFFF, sum = 0
5867 10:57:47.289209 1, 0xFFFF, sum = 0
5868 10:57:47.291626 2, 0xFFFF, sum = 0
5869 10:57:47.292057 3, 0xFFFF, sum = 0
5870 10:57:47.294968 4, 0xFFFF, sum = 0
5871 10:57:47.295440 5, 0xFFFF, sum = 0
5872 10:57:47.298298 6, 0xFFFF, sum = 0
5873 10:57:47.302249 7, 0xFFFF, sum = 0
5874 10:57:47.302774 8, 0xFFFF, sum = 0
5875 10:57:47.305308 9, 0xFFFF, sum = 0
5876 10:57:47.305741 10, 0x0, sum = 1
5877 10:57:47.308554 11, 0x0, sum = 2
5878 10:57:47.309013 12, 0x0, sum = 3
5879 10:57:47.309359 13, 0x0, sum = 4
5880 10:57:47.311776 best_step = 11
5881 10:57:47.312199
5882 10:57:47.312535 ==
5883 10:57:47.315049 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 10:57:47.318374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 10:57:47.318800 ==
5886 10:57:47.321889 RX Vref Scan: 0
5887 10:57:47.322474
5888 10:57:47.322816 RX Vref 0 -> 0, step: 1
5889 10:57:47.324933
5890 10:57:47.325448 RX Delay -45 -> 252, step: 4
5891 10:57:47.332660 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5892 10:57:47.335902 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5893 10:57:47.339044 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5894 10:57:47.342164 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5895 10:57:47.345621 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5896 10:57:47.352269 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5897 10:57:47.355485 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5898 10:57:47.359372 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5899 10:57:47.362384 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5900 10:57:47.365409 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5901 10:57:47.372130 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5902 10:57:47.375424 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5903 10:57:47.378618 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5904 10:57:47.381915 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5905 10:57:47.385863 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5906 10:57:47.392060 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5907 10:57:47.392490 ==
5908 10:57:47.395256 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 10:57:47.398574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 10:57:47.398996 ==
5911 10:57:47.399358 DQS Delay:
5912 10:57:47.402137 DQS0 = 0, DQS1 = 0
5913 10:57:47.402564 DQM Delay:
5914 10:57:47.405286 DQM0 = 105, DQM1 = 99
5915 10:57:47.405710 DQ Delay:
5916 10:57:47.408463 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5917 10:57:47.411784 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5918 10:57:47.415755 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =92
5919 10:57:47.418211 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5920 10:57:47.418704
5921 10:57:47.419052
5922 10:57:47.428412 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5923 10:57:47.431790 CH1 RK1: MR19=505, MR18=2D00
5924 10:57:47.435091 CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43
5925 10:57:47.438388 [RxdqsGatingPostProcess] freq 933
5926 10:57:47.445398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 10:57:47.448617 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 10:57:47.451675 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 10:57:47.455088 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 10:57:47.458205 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 10:57:47.461983 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 10:57:47.465107 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 10:57:47.468816 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 10:57:47.471931 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 10:57:47.472353 Pre-setting of DQS Precalculation
5936 10:57:47.478649 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 10:57:47.485116 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 10:57:47.491804 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 10:57:47.492230
5940 10:57:47.492559
5941 10:57:47.495147 [Calibration Summary] 1866 Mbps
5942 10:57:47.498806 CH 0, Rank 0
5943 10:57:47.499227 SW Impedance : PASS
5944 10:57:47.502066 DUTY Scan : NO K
5945 10:57:47.505368 ZQ Calibration : PASS
5946 10:57:47.505788 Jitter Meter : NO K
5947 10:57:47.508507 CBT Training : PASS
5948 10:57:47.508923 Write leveling : PASS
5949 10:57:47.511795 RX DQS gating : PASS
5950 10:57:47.514932 RX DQ/DQS(RDDQC) : PASS
5951 10:57:47.515390 TX DQ/DQS : PASS
5952 10:57:47.518245 RX DATLAT : PASS
5953 10:57:47.521322 RX DQ/DQS(Engine): PASS
5954 10:57:47.521751 TX OE : NO K
5955 10:57:47.524662 All Pass.
5956 10:57:47.525080
5957 10:57:47.525408 CH 0, Rank 1
5958 10:57:47.527874 SW Impedance : PASS
5959 10:57:47.528297 DUTY Scan : NO K
5960 10:57:47.531397 ZQ Calibration : PASS
5961 10:57:47.535052 Jitter Meter : NO K
5962 10:57:47.535508 CBT Training : PASS
5963 10:57:47.538375 Write leveling : PASS
5964 10:57:47.541553 RX DQS gating : PASS
5965 10:57:47.541976 RX DQ/DQS(RDDQC) : PASS
5966 10:57:47.544813 TX DQ/DQS : PASS
5967 10:57:47.548044 RX DATLAT : PASS
5968 10:57:47.548489 RX DQ/DQS(Engine): PASS
5969 10:57:47.551108 TX OE : NO K
5970 10:57:47.551580 All Pass.
5971 10:57:47.551916
5972 10:57:47.554394 CH 1, Rank 0
5973 10:57:47.554815 SW Impedance : PASS
5974 10:57:47.558032 DUTY Scan : NO K
5975 10:57:47.561034 ZQ Calibration : PASS
5976 10:57:47.561460 Jitter Meter : NO K
5977 10:57:47.564600 CBT Training : PASS
5978 10:57:47.567678 Write leveling : PASS
5979 10:57:47.568131 RX DQS gating : PASS
5980 10:57:47.571440 RX DQ/DQS(RDDQC) : PASS
5981 10:57:47.571871 TX DQ/DQS : PASS
5982 10:57:47.574580 RX DATLAT : PASS
5983 10:57:47.577664 RX DQ/DQS(Engine): PASS
5984 10:57:47.578088 TX OE : NO K
5985 10:57:47.581166 All Pass.
5986 10:57:47.581587
5987 10:57:47.581920 CH 1, Rank 1
5988 10:57:47.584350 SW Impedance : PASS
5989 10:57:47.584776 DUTY Scan : NO K
5990 10:57:47.587592 ZQ Calibration : PASS
5991 10:57:47.590933 Jitter Meter : NO K
5992 10:57:47.591385 CBT Training : PASS
5993 10:57:47.594848 Write leveling : PASS
5994 10:57:47.597993 RX DQS gating : PASS
5995 10:57:47.598418 RX DQ/DQS(RDDQC) : PASS
5996 10:57:47.601253 TX DQ/DQS : PASS
5997 10:57:47.604290 RX DATLAT : PASS
5998 10:57:47.604717 RX DQ/DQS(Engine): PASS
5999 10:57:47.607730 TX OE : NO K
6000 10:57:47.608157 All Pass.
6001 10:57:47.608492
6002 10:57:47.610874 DramC Write-DBI off
6003 10:57:47.614620 PER_BANK_REFRESH: Hybrid Mode
6004 10:57:47.615062 TX_TRACKING: ON
6005 10:57:47.624723 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 10:57:47.627809 [FAST_K] Save calibration result to emmc
6007 10:57:47.630959 dramc_set_vcore_voltage set vcore to 650000
6008 10:57:47.634321 Read voltage for 400, 6
6009 10:57:47.634747 Vio18 = 0
6010 10:57:47.635079 Vcore = 650000
6011 10:57:47.637543 Vdram = 0
6012 10:57:47.638003 Vddq = 0
6013 10:57:47.638341 Vmddr = 0
6014 10:57:47.644161 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 10:57:47.647435 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 10:57:47.650931 MEM_TYPE=3, freq_sel=20
6017 10:57:47.654161 sv_algorithm_assistance_LP4_800
6018 10:57:47.657416 ============ PULL DRAM RESETB DOWN ============
6019 10:57:47.661185 ========== PULL DRAM RESETB DOWN end =========
6020 10:57:47.667251 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 10:57:47.671118 ===================================
6022 10:57:47.671595 LPDDR4 DRAM CONFIGURATION
6023 10:57:47.674034 ===================================
6024 10:57:47.677798 EX_ROW_EN[0] = 0x0
6025 10:57:47.680841 EX_ROW_EN[1] = 0x0
6026 10:57:47.681253 LP4Y_EN = 0x0
6027 10:57:47.683964 WORK_FSP = 0x0
6028 10:57:47.684521 WL = 0x2
6029 10:57:47.687102 RL = 0x2
6030 10:57:47.687563 BL = 0x2
6031 10:57:47.690314 RPST = 0x0
6032 10:57:47.690730 RD_PRE = 0x0
6033 10:57:47.694219 WR_PRE = 0x1
6034 10:57:47.694635 WR_PST = 0x0
6035 10:57:47.697492 DBI_WR = 0x0
6036 10:57:47.697930 DBI_RD = 0x0
6037 10:57:47.700825 OTF = 0x1
6038 10:57:47.704122 ===================================
6039 10:57:47.707357 ===================================
6040 10:57:47.707778 ANA top config
6041 10:57:47.710611 ===================================
6042 10:57:47.713519 DLL_ASYNC_EN = 0
6043 10:57:47.717422 ALL_SLAVE_EN = 1
6044 10:57:47.720703 NEW_RANK_MODE = 1
6045 10:57:47.721171 DLL_IDLE_MODE = 1
6046 10:57:47.723947 LP45_APHY_COMB_EN = 1
6047 10:57:47.726877 TX_ODT_DIS = 1
6048 10:57:47.730415 NEW_8X_MODE = 1
6049 10:57:47.733600 ===================================
6050 10:57:47.736806 ===================================
6051 10:57:47.740542 data_rate = 800
6052 10:57:47.741090 CKR = 1
6053 10:57:47.743892 DQ_P2S_RATIO = 4
6054 10:57:47.747316 ===================================
6055 10:57:47.749993 CA_P2S_RATIO = 4
6056 10:57:47.754148 DQ_CA_OPEN = 0
6057 10:57:47.756543 DQ_SEMI_OPEN = 1
6058 10:57:47.759867 CA_SEMI_OPEN = 1
6059 10:57:47.760299 CA_FULL_RATE = 0
6060 10:57:47.763722 DQ_CKDIV4_EN = 0
6061 10:57:47.766964 CA_CKDIV4_EN = 1
6062 10:57:47.769959 CA_PREDIV_EN = 0
6063 10:57:47.773629 PH8_DLY = 0
6064 10:57:47.776793 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 10:57:47.777209 DQ_AAMCK_DIV = 0
6066 10:57:47.780485 CA_AAMCK_DIV = 0
6067 10:57:47.783615 CA_ADMCK_DIV = 4
6068 10:57:47.786604 DQ_TRACK_CA_EN = 0
6069 10:57:47.790292 CA_PICK = 800
6070 10:57:47.793392 CA_MCKIO = 400
6071 10:57:47.796751 MCKIO_SEMI = 400
6072 10:57:47.797283 PLL_FREQ = 3016
6073 10:57:47.800399 DQ_UI_PI_RATIO = 32
6074 10:57:47.803630 CA_UI_PI_RATIO = 32
6075 10:57:47.806467 ===================================
6076 10:57:47.810348 ===================================
6077 10:57:47.813424 memory_type:LPDDR4
6078 10:57:47.813836 GP_NUM : 10
6079 10:57:47.816677 SRAM_EN : 1
6080 10:57:47.819876 MD32_EN : 0
6081 10:57:47.822961 ===================================
6082 10:57:47.823551 [ANA_INIT] >>>>>>>>>>>>>>
6083 10:57:47.826414 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 10:57:47.830234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 10:57:47.833403 ===================================
6086 10:57:47.836342 data_rate = 800,PCW = 0X7400
6087 10:57:47.839680 ===================================
6088 10:57:47.842923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 10:57:47.849882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 10:57:47.859784 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 10:57:47.866258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 10:57:47.869632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 10:57:47.872733 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 10:57:47.873228 [ANA_INIT] flow start
6095 10:57:47.876366 [ANA_INIT] PLL >>>>>>>>
6096 10:57:47.879454 [ANA_INIT] PLL <<<<<<<<
6097 10:57:47.879984 [ANA_INIT] MIDPI >>>>>>>>
6098 10:57:47.883302 [ANA_INIT] MIDPI <<<<<<<<
6099 10:57:47.886224 [ANA_INIT] DLL >>>>>>>>
6100 10:57:47.886612 [ANA_INIT] flow end
6101 10:57:47.893005 ============ LP4 DIFF to SE enter ============
6102 10:57:47.896065 ============ LP4 DIFF to SE exit ============
6103 10:57:47.899315 [ANA_INIT] <<<<<<<<<<<<<
6104 10:57:47.902909 [Flow] Enable top DCM control >>>>>
6105 10:57:47.906006 [Flow] Enable top DCM control <<<<<
6106 10:57:47.906459 Enable DLL master slave shuffle
6107 10:57:47.912718 ==============================================================
6108 10:57:47.915854 Gating Mode config
6109 10:57:47.919064 ==============================================================
6110 10:57:47.922413 Config description:
6111 10:57:47.932694 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 10:57:47.939306 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 10:57:47.942371 SELPH_MODE 0: By rank 1: By Phase
6114 10:57:47.949343 ==============================================================
6115 10:57:47.952616 GAT_TRACK_EN = 0
6116 10:57:47.956450 RX_GATING_MODE = 2
6117 10:57:47.959841 RX_GATING_TRACK_MODE = 2
6118 10:57:47.960269 SELPH_MODE = 1
6119 10:57:47.963216 PICG_EARLY_EN = 1
6120 10:57:47.966193 VALID_LAT_VALUE = 1
6121 10:57:47.972695 ==============================================================
6122 10:57:47.975879 Enter into Gating configuration >>>>
6123 10:57:47.979206 Exit from Gating configuration <<<<
6124 10:57:47.982318 Enter into DVFS_PRE_config >>>>>
6125 10:57:47.992516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 10:57:47.996252 Exit from DVFS_PRE_config <<<<<
6127 10:57:47.999270 Enter into PICG configuration >>>>
6128 10:57:48.002294 Exit from PICG configuration <<<<
6129 10:57:48.005834 [RX_INPUT] configuration >>>>>
6130 10:57:48.009007 [RX_INPUT] configuration <<<<<
6131 10:57:48.012638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 10:57:48.019184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 10:57:48.025582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 10:57:48.032015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 10:57:48.038642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 10:57:48.042095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 10:57:48.048594 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 10:57:48.052307 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 10:57:48.055617 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 10:57:48.058664 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 10:57:48.065139 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 10:57:48.068355 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 10:57:48.072097 ===================================
6144 10:57:48.075388 LPDDR4 DRAM CONFIGURATION
6145 10:57:48.078815 ===================================
6146 10:57:48.079236 EX_ROW_EN[0] = 0x0
6147 10:57:48.082012 EX_ROW_EN[1] = 0x0
6148 10:57:48.082467 LP4Y_EN = 0x0
6149 10:57:48.085342 WORK_FSP = 0x0
6150 10:57:48.085792 WL = 0x2
6151 10:57:48.088341 RL = 0x2
6152 10:57:48.091608 BL = 0x2
6153 10:57:48.092060 RPST = 0x0
6154 10:57:48.094689 RD_PRE = 0x0
6155 10:57:48.095114 WR_PRE = 0x1
6156 10:57:48.098102 WR_PST = 0x0
6157 10:57:48.098526 DBI_WR = 0x0
6158 10:57:48.101774 DBI_RD = 0x0
6159 10:57:48.102371 OTF = 0x1
6160 10:57:48.104921 ===================================
6161 10:57:48.108608 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 10:57:48.114767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 10:57:48.118445 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 10:57:48.121573 ===================================
6165 10:57:48.124749 LPDDR4 DRAM CONFIGURATION
6166 10:57:48.128447 ===================================
6167 10:57:48.128874 EX_ROW_EN[0] = 0x10
6168 10:57:48.131756 EX_ROW_EN[1] = 0x0
6169 10:57:48.132205 LP4Y_EN = 0x0
6170 10:57:48.134874 WORK_FSP = 0x0
6171 10:57:48.135278 WL = 0x2
6172 10:57:48.138050 RL = 0x2
6173 10:57:48.138476 BL = 0x2
6174 10:57:48.141411 RPST = 0x0
6175 10:57:48.141860 RD_PRE = 0x0
6176 10:57:48.145286 WR_PRE = 0x1
6177 10:57:48.145714 WR_PST = 0x0
6178 10:57:48.147944 DBI_WR = 0x0
6179 10:57:48.151275 DBI_RD = 0x0
6180 10:57:48.151764 OTF = 0x1
6181 10:57:48.155111 ===================================
6182 10:57:48.161511 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 10:57:48.164737 nWR fixed to 30
6184 10:57:48.168480 [ModeRegInit_LP4] CH0 RK0
6185 10:57:48.168946 [ModeRegInit_LP4] CH0 RK1
6186 10:57:48.171651 [ModeRegInit_LP4] CH1 RK0
6187 10:57:48.174974 [ModeRegInit_LP4] CH1 RK1
6188 10:57:48.175444 match AC timing 19
6189 10:57:48.181497 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 10:57:48.184821 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 10:57:48.188041 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 10:57:48.195144 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 10:57:48.198497 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 10:57:48.198727 ==
6195 10:57:48.201629 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 10:57:48.204645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 10:57:48.204895 ==
6198 10:57:48.211361 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 10:57:48.217910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 10:57:48.221035 [CA 0] Center 36 (8~64) winsize 57
6201 10:57:48.224903 [CA 1] Center 36 (8~64) winsize 57
6202 10:57:48.227919 [CA 2] Center 36 (8~64) winsize 57
6203 10:57:48.228002 [CA 3] Center 36 (8~64) winsize 57
6204 10:57:48.231473 [CA 4] Center 36 (8~64) winsize 57
6205 10:57:48.234568 [CA 5] Center 36 (8~64) winsize 57
6206 10:57:48.234652
6207 10:57:48.237713 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 10:57:48.241601
6209 10:57:48.244249 [CATrainingPosCal] consider 1 rank data
6210 10:57:48.244331 u2DelayCellTimex100 = 270/100 ps
6211 10:57:48.251259 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 10:57:48.254544 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 10:57:48.257844 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 10:57:48.261210 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 10:57:48.264443 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 10:57:48.267598 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 10:57:48.267681
6218 10:57:48.271312 CA PerBit enable=1, Macro0, CA PI delay=36
6219 10:57:48.271432
6220 10:57:48.274607 [CBTSetCACLKResult] CA Dly = 36
6221 10:57:48.277851 CS Dly: 1 (0~32)
6222 10:57:48.277937 ==
6223 10:57:48.281186 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 10:57:48.284393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 10:57:48.284479 ==
6226 10:57:48.291368 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 10:57:48.294666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 10:57:48.298013 [CA 0] Center 36 (8~64) winsize 57
6229 10:57:48.301368 [CA 1] Center 36 (8~64) winsize 57
6230 10:57:48.304088 [CA 2] Center 36 (8~64) winsize 57
6231 10:57:48.308034 [CA 3] Center 36 (8~64) winsize 57
6232 10:57:48.311063 [CA 4] Center 36 (8~64) winsize 57
6233 10:57:48.314541 [CA 5] Center 36 (8~64) winsize 57
6234 10:57:48.314624
6235 10:57:48.317453 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 10:57:48.317536
6237 10:57:48.320973 [CATrainingPosCal] consider 2 rank data
6238 10:57:48.324115 u2DelayCellTimex100 = 270/100 ps
6239 10:57:48.327831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 10:57:48.330918 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 10:57:48.334012 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 10:57:48.340715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 10:57:48.344502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:57:48.347583 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:57:48.347667
6246 10:57:48.350740 CA PerBit enable=1, Macro0, CA PI delay=36
6247 10:57:48.350823
6248 10:57:48.354095 [CBTSetCACLKResult] CA Dly = 36
6249 10:57:48.354178 CS Dly: 1 (0~32)
6250 10:57:48.354243
6251 10:57:48.357348 ----->DramcWriteLeveling(PI) begin...
6252 10:57:48.357431 ==
6253 10:57:48.360744 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 10:57:48.367777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 10:57:48.367864 ==
6256 10:57:48.370989 Write leveling (Byte 0): 40 => 8
6257 10:57:48.371071 Write leveling (Byte 1): 40 => 8
6258 10:57:48.374284 DramcWriteLeveling(PI) end<-----
6259 10:57:48.374369
6260 10:57:48.377325 ==
6261 10:57:48.377407 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 10:57:48.383902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 10:57:48.383986 ==
6264 10:57:48.387082 [Gating] SW mode calibration
6265 10:57:48.393692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 10:57:48.397564 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 10:57:48.403936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 10:57:48.407229 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 10:57:48.410702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 10:57:48.417301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 10:57:48.420516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 10:57:48.424167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 10:57:48.430434 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 10:57:48.434220 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 10:57:48.437402 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 10:57:48.440265 Total UI for P1: 0, mck2ui 16
6277 10:57:48.443885 best dqsien dly found for B0: ( 0, 14, 24)
6278 10:57:48.447020 Total UI for P1: 0, mck2ui 16
6279 10:57:48.450634 best dqsien dly found for B1: ( 0, 14, 24)
6280 10:57:48.454040 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 10:57:48.457161 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 10:57:48.457244
6283 10:57:48.463981 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 10:57:48.467294 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 10:57:48.467422 [Gating] SW calibration Done
6286 10:57:48.470629 ==
6287 10:57:48.473872 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 10:57:48.477078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 10:57:48.477161 ==
6290 10:57:48.477226 RX Vref Scan: 0
6291 10:57:48.477286
6292 10:57:48.480390 RX Vref 0 -> 0, step: 1
6293 10:57:48.480471
6294 10:57:48.483530 RX Delay -410 -> 252, step: 16
6295 10:57:48.486699 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 10:57:48.490078 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 10:57:48.496649 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6298 10:57:48.500110 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 10:57:48.503933 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6300 10:57:48.507090 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 10:57:48.513733 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 10:57:48.517060 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6303 10:57:48.520480 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 10:57:48.523641 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 10:57:48.529965 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 10:57:48.533504 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6307 10:57:48.536474 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 10:57:48.543341 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 10:57:48.546366 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6310 10:57:48.549606 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 10:57:48.549701 ==
6312 10:57:48.553419 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 10:57:48.556473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 10:57:48.556555 ==
6315 10:57:48.559620 DQS Delay:
6316 10:57:48.559701 DQS0 = 27, DQS1 = 35
6317 10:57:48.563381 DQM Delay:
6318 10:57:48.563462 DQM0 = 9, DQM1 = 12
6319 10:57:48.566537 DQ Delay:
6320 10:57:48.566617 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6321 10:57:48.570000 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6322 10:57:48.573443 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6323 10:57:48.576660 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6324 10:57:48.576742
6325 10:57:48.576805
6326 10:57:48.576869 ==
6327 10:57:48.579971 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 10:57:48.586422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 10:57:48.586506 ==
6330 10:57:48.586569
6331 10:57:48.586628
6332 10:57:48.586684 TX Vref Scan disable
6333 10:57:48.589746 == TX Byte 0 ==
6334 10:57:48.593561 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 10:57:48.596812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 10:57:48.599671 == TX Byte 1 ==
6337 10:57:48.603101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 10:57:48.606434 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 10:57:48.606515 ==
6340 10:57:48.609773 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 10:57:48.616260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 10:57:48.616372 ==
6343 10:57:48.616472
6344 10:57:48.616564
6345 10:57:48.616656 TX Vref Scan disable
6346 10:57:48.619841 == TX Byte 0 ==
6347 10:57:48.623053 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 10:57:48.626429 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 10:57:48.629730 == TX Byte 1 ==
6350 10:57:48.632940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 10:57:48.636182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 10:57:48.636269
6353 10:57:48.639491 [DATLAT]
6354 10:57:48.639572 Freq=400, CH0 RK0
6355 10:57:48.639635
6356 10:57:48.643091 DATLAT Default: 0xf
6357 10:57:48.643171 0, 0xFFFF, sum = 0
6358 10:57:48.646289 1, 0xFFFF, sum = 0
6359 10:57:48.646398 2, 0xFFFF, sum = 0
6360 10:57:48.649417 3, 0xFFFF, sum = 0
6361 10:57:48.649506 4, 0xFFFF, sum = 0
6362 10:57:48.652725 5, 0xFFFF, sum = 0
6363 10:57:48.652810 6, 0xFFFF, sum = 0
6364 10:57:48.656108 7, 0xFFFF, sum = 0
6365 10:57:48.656190 8, 0xFFFF, sum = 0
6366 10:57:48.659976 9, 0xFFFF, sum = 0
6367 10:57:48.662991 10, 0xFFFF, sum = 0
6368 10:57:48.663099 11, 0xFFFF, sum = 0
6369 10:57:48.666186 12, 0xFFFF, sum = 0
6370 10:57:48.666257 13, 0x0, sum = 1
6371 10:57:48.669816 14, 0x0, sum = 2
6372 10:57:48.669900 15, 0x0, sum = 3
6373 10:57:48.669964 16, 0x0, sum = 4
6374 10:57:48.672992 best_step = 14
6375 10:57:48.673076
6376 10:57:48.673140 ==
6377 10:57:48.675885 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 10:57:48.679830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 10:57:48.679912 ==
6380 10:57:48.683090 RX Vref Scan: 1
6381 10:57:48.683171
6382 10:57:48.683234 RX Vref 0 -> 0, step: 1
6383 10:57:48.686145
6384 10:57:48.686224 RX Delay -311 -> 252, step: 8
6385 10:57:48.686293
6386 10:57:48.689492 Set Vref, RX VrefLevel [Byte0]: 54
6387 10:57:48.692720 [Byte1]: 57
6388 10:57:48.697784
6389 10:57:48.697890 Final RX Vref Byte 0 = 54 to rank0
6390 10:57:48.701075 Final RX Vref Byte 1 = 57 to rank0
6391 10:57:48.704230 Final RX Vref Byte 0 = 54 to rank1
6392 10:57:48.707537 Final RX Vref Byte 1 = 57 to rank1==
6393 10:57:48.710763 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:57:48.717356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:57:48.717438 ==
6396 10:57:48.717502 DQS Delay:
6397 10:57:48.721321 DQS0 = 28, DQS1 = 32
6398 10:57:48.721407 DQM Delay:
6399 10:57:48.721474 DQM0 = 11, DQM1 = 9
6400 10:57:48.724627 DQ Delay:
6401 10:57:48.727876 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6402 10:57:48.728019 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6403 10:57:48.730699 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6404 10:57:48.734110 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6405 10:57:48.734193
6406 10:57:48.737844
6407 10:57:48.744278 [DQSOSCAuto] RK0, (LSB)MR18= 0xc6b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6408 10:57:48.747548 CH0 RK0: MR19=C0C, MR18=C6B3
6409 10:57:48.754489 CH0_RK0: MR19=0xC0C, MR18=0xC6B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6410 10:57:48.754574 ==
6411 10:57:48.757630 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 10:57:48.760583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 10:57:48.760666 ==
6414 10:57:48.764300 [Gating] SW mode calibration
6415 10:57:48.770614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 10:57:48.777597 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 10:57:48.780606 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 10:57:48.783809 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 10:57:48.787505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 10:57:48.794129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 10:57:48.797332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 10:57:48.800575 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 10:57:48.807082 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 10:57:48.810465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 10:57:48.813640 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 10:57:48.817536 Total UI for P1: 0, mck2ui 16
6427 10:57:48.820761 best dqsien dly found for B0: ( 0, 14, 24)
6428 10:57:48.824108 Total UI for P1: 0, mck2ui 16
6429 10:57:48.827309 best dqsien dly found for B1: ( 0, 14, 24)
6430 10:57:48.830794 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 10:57:48.834031 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 10:57:48.837363
6433 10:57:48.840521 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 10:57:48.844278 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 10:57:48.847649 [Gating] SW calibration Done
6436 10:57:48.847732 ==
6437 10:57:48.850897 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 10:57:48.854050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 10:57:48.854158 ==
6440 10:57:48.854251 RX Vref Scan: 0
6441 10:57:48.854340
6442 10:57:48.857335 RX Vref 0 -> 0, step: 1
6443 10:57:48.857419
6444 10:57:48.860702 RX Delay -410 -> 252, step: 16
6445 10:57:48.863812 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 10:57:48.870404 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 10:57:48.873594 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 10:57:48.877400 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 10:57:48.880379 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 10:57:48.887445 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6451 10:57:48.890516 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6452 10:57:48.893629 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 10:57:48.897373 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 10:57:48.903884 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6455 10:57:48.907128 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 10:57:48.910276 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6457 10:57:48.913438 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 10:57:48.920046 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 10:57:48.923359 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6460 10:57:48.926763 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 10:57:48.926853 ==
6462 10:57:48.929963 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 10:57:48.933372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 10:57:48.936647 ==
6465 10:57:48.936779 DQS Delay:
6466 10:57:48.936893 DQS0 = 27, DQS1 = 35
6467 10:57:48.940036 DQM Delay:
6468 10:57:48.940135 DQM0 = 12, DQM1 = 11
6469 10:57:48.943233 DQ Delay:
6470 10:57:48.943374 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6471 10:57:48.947054 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6472 10:57:48.950162 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6473 10:57:48.953635 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6474 10:57:48.953764
6475 10:57:48.953881
6476 10:57:48.956816 ==
6477 10:57:48.959884 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 10:57:48.963088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 10:57:48.963185 ==
6480 10:57:48.963278
6481 10:57:48.963365
6482 10:57:48.966327 TX Vref Scan disable
6483 10:57:48.966424 == TX Byte 0 ==
6484 10:57:48.970184 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6485 10:57:48.976402 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6486 10:57:48.976492 == TX Byte 1 ==
6487 10:57:48.979539 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6488 10:57:48.983201 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6489 10:57:48.986288 ==
6490 10:57:48.990122 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 10:57:48.993251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 10:57:48.993367 ==
6493 10:57:48.993458
6494 10:57:48.993561
6495 10:57:48.996370 TX Vref Scan disable
6496 10:57:48.996507 == TX Byte 0 ==
6497 10:57:49.000078 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6498 10:57:49.006562 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6499 10:57:49.006639 == TX Byte 1 ==
6500 10:57:49.009671 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6501 10:57:49.013032 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6502 10:57:49.016342
6503 10:57:49.016441 [DATLAT]
6504 10:57:49.016536 Freq=400, CH0 RK1
6505 10:57:49.016624
6506 10:57:49.019728 DATLAT Default: 0xe
6507 10:57:49.019801 0, 0xFFFF, sum = 0
6508 10:57:49.023078 1, 0xFFFF, sum = 0
6509 10:57:49.023155 2, 0xFFFF, sum = 0
6510 10:57:49.026287 3, 0xFFFF, sum = 0
6511 10:57:49.026370 4, 0xFFFF, sum = 0
6512 10:57:49.029717 5, 0xFFFF, sum = 0
6513 10:57:49.029801 6, 0xFFFF, sum = 0
6514 10:57:49.033568 7, 0xFFFF, sum = 0
6515 10:57:49.036354 8, 0xFFFF, sum = 0
6516 10:57:49.036438 9, 0xFFFF, sum = 0
6517 10:57:49.039658 10, 0xFFFF, sum = 0
6518 10:57:49.039741 11, 0xFFFF, sum = 0
6519 10:57:49.042835 12, 0xFFFF, sum = 0
6520 10:57:49.042919 13, 0x0, sum = 1
6521 10:57:49.046646 14, 0x0, sum = 2
6522 10:57:49.046729 15, 0x0, sum = 3
6523 10:57:49.049411 16, 0x0, sum = 4
6524 10:57:49.049494 best_step = 14
6525 10:57:49.049559
6526 10:57:49.049618 ==
6527 10:57:49.053083 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 10:57:49.056401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 10:57:49.059625 ==
6530 10:57:49.059707 RX Vref Scan: 0
6531 10:57:49.059771
6532 10:57:49.062890 RX Vref 0 -> 0, step: 1
6533 10:57:49.062972
6534 10:57:49.066049 RX Delay -311 -> 252, step: 8
6535 10:57:49.069352 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6536 10:57:49.075898 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6537 10:57:49.079543 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6538 10:57:49.082995 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6539 10:57:49.086073 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6540 10:57:49.092699 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 10:57:49.096037 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 10:57:49.099103 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6543 10:57:49.102364 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6544 10:57:49.109254 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6545 10:57:49.112485 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6546 10:57:49.115762 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6547 10:57:49.118901 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6548 10:57:49.125904 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6549 10:57:49.129110 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 10:57:49.132431 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 10:57:49.132538 ==
6552 10:57:49.135560 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 10:57:49.142205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 10:57:49.142304 ==
6555 10:57:49.142394 DQS Delay:
6556 10:57:49.145620 DQS0 = 24, DQS1 = 32
6557 10:57:49.145720 DQM Delay:
6558 10:57:49.145817 DQM0 = 7, DQM1 = 10
6559 10:57:49.148841 DQ Delay:
6560 10:57:49.152726 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6561 10:57:49.152807 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6562 10:57:49.155894 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6563 10:57:49.159099 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6564 10:57:49.159180
6565 10:57:49.159245
6566 10:57:49.168904 [DQSOSCAuto] RK1, (LSB)MR18= 0xb857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6567 10:57:49.172157 CH0 RK1: MR19=C0C, MR18=B857
6568 10:57:49.178810 CH0_RK1: MR19=0xC0C, MR18=0xB857, DQSOSC=386, MR23=63, INC=396, DEC=264
6569 10:57:49.178892 [RxdqsGatingPostProcess] freq 400
6570 10:57:49.185739 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 10:57:49.189090 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 10:57:49.192211 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 10:57:49.195863 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 10:57:49.198891 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 10:57:49.202612 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 10:57:49.205818 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 10:57:49.208941 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 10:57:49.212153 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 10:57:49.216128 Pre-setting of DQS Precalculation
6580 10:57:49.219226 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 10:57:49.219360 ==
6582 10:57:49.222239 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 10:57:49.225570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 10:57:49.225652 ==
6585 10:57:49.232501 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 10:57:49.238850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6587 10:57:49.242130 [CA 0] Center 36 (8~64) winsize 57
6588 10:57:49.246047 [CA 1] Center 36 (8~64) winsize 57
6589 10:57:49.249284 [CA 2] Center 36 (8~64) winsize 57
6590 10:57:49.252640 [CA 3] Center 36 (8~64) winsize 57
6591 10:57:49.255976 [CA 4] Center 36 (8~64) winsize 57
6592 10:57:49.256048 [CA 5] Center 36 (8~64) winsize 57
6593 10:57:49.259124
6594 10:57:49.262317 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6595 10:57:49.262424
6596 10:57:49.265436 [CATrainingPosCal] consider 1 rank data
6597 10:57:49.268739 u2DelayCellTimex100 = 270/100 ps
6598 10:57:49.272119 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 10:57:49.275287 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 10:57:49.278573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 10:57:49.282453 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 10:57:49.285553 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 10:57:49.288972 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 10:57:49.289055
6605 10:57:49.291948 CA PerBit enable=1, Macro0, CA PI delay=36
6606 10:57:49.292054
6607 10:57:49.295684 [CBTSetCACLKResult] CA Dly = 36
6608 10:57:49.298878 CS Dly: 1 (0~32)
6609 10:57:49.298960 ==
6610 10:57:49.302015 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 10:57:49.305737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 10:57:49.305845 ==
6613 10:57:49.311894 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 10:57:49.318568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 10:57:49.322482 [CA 0] Center 36 (8~64) winsize 57
6616 10:57:49.322568 [CA 1] Center 36 (8~64) winsize 57
6617 10:57:49.325707 [CA 2] Center 36 (8~64) winsize 57
6618 10:57:49.329006 [CA 3] Center 36 (8~64) winsize 57
6619 10:57:49.332023 [CA 4] Center 36 (8~64) winsize 57
6620 10:57:49.335137 [CA 5] Center 36 (8~64) winsize 57
6621 10:57:49.335237
6622 10:57:49.338853 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 10:57:49.338965
6624 10:57:49.341946 [CATrainingPosCal] consider 2 rank data
6625 10:57:49.345474 u2DelayCellTimex100 = 270/100 ps
6626 10:57:49.348667 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 10:57:49.352080 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 10:57:49.358678 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 10:57:49.362040 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 10:57:49.365142 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:57:49.368341 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:57:49.368423
6633 10:57:49.371603 CA PerBit enable=1, Macro0, CA PI delay=36
6634 10:57:49.371696
6635 10:57:49.375540 [CBTSetCACLKResult] CA Dly = 36
6636 10:57:49.375622 CS Dly: 1 (0~32)
6637 10:57:49.378980
6638 10:57:49.381609 ----->DramcWriteLeveling(PI) begin...
6639 10:57:49.381702 ==
6640 10:57:49.385446 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 10:57:49.388545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 10:57:49.388662 ==
6643 10:57:49.392021 Write leveling (Byte 0): 40 => 8
6644 10:57:49.395104 Write leveling (Byte 1): 40 => 8
6645 10:57:49.399010 DramcWriteLeveling(PI) end<-----
6646 10:57:49.399092
6647 10:57:49.399157 ==
6648 10:57:49.402183 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 10:57:49.405369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 10:57:49.405452 ==
6651 10:57:49.408593 [Gating] SW mode calibration
6652 10:57:49.415462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 10:57:49.418440 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 10:57:49.425323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 10:57:49.428439 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 10:57:49.431563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 10:57:49.438683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 10:57:49.442046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 10:57:49.444976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 10:57:49.451920 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 10:57:49.455232 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 10:57:49.458551 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 10:57:49.461942 Total UI for P1: 0, mck2ui 16
6664 10:57:49.465353 best dqsien dly found for B0: ( 0, 14, 24)
6665 10:57:49.468401 Total UI for P1: 0, mck2ui 16
6666 10:57:49.471529 best dqsien dly found for B1: ( 0, 14, 24)
6667 10:57:49.474878 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 10:57:49.481260 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 10:57:49.481343
6670 10:57:49.485169 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 10:57:49.488412 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 10:57:49.491668 [Gating] SW calibration Done
6673 10:57:49.491750 ==
6674 10:57:49.494871 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 10:57:49.498125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 10:57:49.498208 ==
6677 10:57:49.498273 RX Vref Scan: 0
6678 10:57:49.498333
6679 10:57:49.501460 RX Vref 0 -> 0, step: 1
6680 10:57:49.501541
6681 10:57:49.504741 RX Delay -410 -> 252, step: 16
6682 10:57:49.508410 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 10:57:49.514819 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6684 10:57:49.517971 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6685 10:57:49.521719 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 10:57:49.524776 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 10:57:49.531924 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 10:57:49.534965 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 10:57:49.538164 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 10:57:49.541462 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 10:57:49.544656 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 10:57:49.551535 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 10:57:49.554456 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 10:57:49.558366 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 10:57:49.564924 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 10:57:49.568182 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6697 10:57:49.571465 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 10:57:49.571547 ==
6699 10:57:49.574998 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 10:57:49.578266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 10:57:49.581478 ==
6702 10:57:49.581561 DQS Delay:
6703 10:57:49.581626 DQS0 = 35, DQS1 = 35
6704 10:57:49.584804 DQM Delay:
6705 10:57:49.584886 DQM0 = 18, DQM1 = 13
6706 10:57:49.587901 DQ Delay:
6707 10:57:49.591211 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6708 10:57:49.591293 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6709 10:57:49.594640 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 10:57:49.597905 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6711 10:57:49.598003
6712 10:57:49.598067
6713 10:57:49.601062 ==
6714 10:57:49.604375 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 10:57:49.607637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 10:57:49.607734 ==
6717 10:57:49.607800
6718 10:57:49.607860
6719 10:57:49.611337 TX Vref Scan disable
6720 10:57:49.611434 == TX Byte 0 ==
6721 10:57:49.614451 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 10:57:49.620877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 10:57:49.620960 == TX Byte 1 ==
6724 10:57:49.624587 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 10:57:49.631346 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 10:57:49.631445 ==
6727 10:57:49.634562 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 10:57:49.637718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 10:57:49.637802 ==
6730 10:57:49.637867
6731 10:57:49.637927
6732 10:57:49.640919 TX Vref Scan disable
6733 10:57:49.641001 == TX Byte 0 ==
6734 10:57:49.644205 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 10:57:49.651292 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 10:57:49.651405 == TX Byte 1 ==
6737 10:57:49.654556 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 10:57:49.661217 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 10:57:49.661306
6740 10:57:49.661371 [DATLAT]
6741 10:57:49.661432 Freq=400, CH1 RK0
6742 10:57:49.664405
6743 10:57:49.664487 DATLAT Default: 0xf
6744 10:57:49.667715 0, 0xFFFF, sum = 0
6745 10:57:49.667799 1, 0xFFFF, sum = 0
6746 10:57:49.671065 2, 0xFFFF, sum = 0
6747 10:57:49.671184 3, 0xFFFF, sum = 0
6748 10:57:49.674404 4, 0xFFFF, sum = 0
6749 10:57:49.674488 5, 0xFFFF, sum = 0
6750 10:57:49.677652 6, 0xFFFF, sum = 0
6751 10:57:49.677762 7, 0xFFFF, sum = 0
6752 10:57:49.680582 8, 0xFFFF, sum = 0
6753 10:57:49.680658 9, 0xFFFF, sum = 0
6754 10:57:49.683835 10, 0xFFFF, sum = 0
6755 10:57:49.683919 11, 0xFFFF, sum = 0
6756 10:57:49.687811 12, 0xFFFF, sum = 0
6757 10:57:49.687894 13, 0x0, sum = 1
6758 10:57:49.690987 14, 0x0, sum = 2
6759 10:57:49.691096 15, 0x0, sum = 3
6760 10:57:49.694340 16, 0x0, sum = 4
6761 10:57:49.694424 best_step = 14
6762 10:57:49.694488
6763 10:57:49.694549 ==
6764 10:57:49.697479 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 10:57:49.704119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 10:57:49.704202 ==
6767 10:57:49.704301 RX Vref Scan: 1
6768 10:57:49.704361
6769 10:57:49.707433 RX Vref 0 -> 0, step: 1
6770 10:57:49.707515
6771 10:57:49.710626 RX Delay -311 -> 252, step: 8
6772 10:57:49.710708
6773 10:57:49.713939 Set Vref, RX VrefLevel [Byte0]: 56
6774 10:57:49.717221 [Byte1]: 53
6775 10:57:49.717303
6776 10:57:49.720390 Final RX Vref Byte 0 = 56 to rank0
6777 10:57:49.724074 Final RX Vref Byte 1 = 53 to rank0
6778 10:57:49.727211 Final RX Vref Byte 0 = 56 to rank1
6779 10:57:49.730304 Final RX Vref Byte 1 = 53 to rank1==
6780 10:57:49.734032 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:57:49.737122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:57:49.737205 ==
6783 10:57:49.740340 DQS Delay:
6784 10:57:49.740422 DQS0 = 28, DQS1 = 32
6785 10:57:49.743504 DQM Delay:
6786 10:57:49.743585 DQM0 = 10, DQM1 = 11
6787 10:57:49.747197 DQ Delay:
6788 10:57:49.747279 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6789 10:57:49.750553 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6790 10:57:49.753727 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6791 10:57:49.756967 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6792 10:57:49.757050
6793 10:57:49.757115
6794 10:57:49.767225 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6795 10:57:49.767310 CH1 RK0: MR19=C0C, MR18=8EC6
6796 10:57:49.773863 CH1_RK0: MR19=0xC0C, MR18=0x8EC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6797 10:57:49.773946 ==
6798 10:57:49.776971 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 10:57:49.783736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 10:57:49.783819 ==
6801 10:57:49.787165 [Gating] SW mode calibration
6802 10:57:49.793521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 10:57:49.796831 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 10:57:49.803647 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 10:57:49.807532 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 10:57:49.810647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 10:57:49.817170 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 10:57:49.820592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 10:57:49.823846 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 10:57:49.826940 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 10:57:49.833696 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 10:57:49.836971 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 10:57:49.839965 Total UI for P1: 0, mck2ui 16
6814 10:57:49.843623 best dqsien dly found for B0: ( 0, 14, 24)
6815 10:57:49.846837 Total UI for P1: 0, mck2ui 16
6816 10:57:49.850585 best dqsien dly found for B1: ( 0, 14, 24)
6817 10:57:49.853692 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 10:57:49.856953 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 10:57:49.857035
6820 10:57:49.860146 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 10:57:49.866591 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 10:57:49.866674 [Gating] SW calibration Done
6823 10:57:49.866739 ==
6824 10:57:49.869928 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 10:57:49.876529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 10:57:49.876610 ==
6827 10:57:49.876675 RX Vref Scan: 0
6828 10:57:49.876734
6829 10:57:49.880456 RX Vref 0 -> 0, step: 1
6830 10:57:49.880537
6831 10:57:49.883566 RX Delay -410 -> 252, step: 16
6832 10:57:49.886691 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6833 10:57:49.890488 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 10:57:49.897096 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 10:57:49.900226 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 10:57:49.903535 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 10:57:49.906743 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 10:57:49.913893 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6839 10:57:49.916472 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 10:57:49.920314 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 10:57:49.923063 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6842 10:57:49.930183 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 10:57:49.933439 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 10:57:49.936473 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 10:57:49.940032 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 10:57:49.946587 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 10:57:49.949765 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 10:57:49.949846 ==
6849 10:57:49.953300 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 10:57:49.956592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 10:57:49.956674 ==
6852 10:57:49.960203 DQS Delay:
6853 10:57:49.960284 DQS0 = 35, DQS1 = 35
6854 10:57:49.960347 DQM Delay:
6855 10:57:49.963290 DQM0 = 19, DQM1 = 14
6856 10:57:49.963403 DQ Delay:
6857 10:57:49.966951 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6858 10:57:49.970162 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6859 10:57:49.972791 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6860 10:57:49.976203 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 10:57:49.976286
6862 10:57:49.976350
6863 10:57:49.976410 ==
6864 10:57:49.980024 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 10:57:49.986183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 10:57:49.986267 ==
6867 10:57:49.986333
6868 10:57:49.986394
6869 10:57:49.986452 TX Vref Scan disable
6870 10:57:49.990033 == TX Byte 0 ==
6871 10:57:49.993217 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6872 10:57:49.996375 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6873 10:57:49.999595 == TX Byte 1 ==
6874 10:57:50.003344 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6875 10:57:50.006157 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6876 10:57:50.006262 ==
6877 10:57:50.009366 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 10:57:50.016523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 10:57:50.016629 ==
6880 10:57:50.016733
6881 10:57:50.016832
6882 10:57:50.016930 TX Vref Scan disable
6883 10:57:50.019820 == TX Byte 0 ==
6884 10:57:50.023095 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6885 10:57:50.026338 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6886 10:57:50.029765 == TX Byte 1 ==
6887 10:57:50.032916 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6888 10:57:50.036276 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6889 10:57:50.036378
6890 10:57:50.039468 [DATLAT]
6891 10:57:50.039569 Freq=400, CH1 RK1
6892 10:57:50.039671
6893 10:57:50.043285 DATLAT Default: 0xe
6894 10:57:50.043427 0, 0xFFFF, sum = 0
6895 10:57:50.046481 1, 0xFFFF, sum = 0
6896 10:57:50.046583 2, 0xFFFF, sum = 0
6897 10:57:50.049548 3, 0xFFFF, sum = 0
6898 10:57:50.049657 4, 0xFFFF, sum = 0
6899 10:57:50.053305 5, 0xFFFF, sum = 0
6900 10:57:50.053383 6, 0xFFFF, sum = 0
6901 10:57:50.056339 7, 0xFFFF, sum = 0
6902 10:57:50.056414 8, 0xFFFF, sum = 0
6903 10:57:50.059291 9, 0xFFFF, sum = 0
6904 10:57:50.059427 10, 0xFFFF, sum = 0
6905 10:57:50.063164 11, 0xFFFF, sum = 0
6906 10:57:50.066394 12, 0xFFFF, sum = 0
6907 10:57:50.066495 13, 0x0, sum = 1
6908 10:57:50.066596 14, 0x0, sum = 2
6909 10:57:50.069378 15, 0x0, sum = 3
6910 10:57:50.069482 16, 0x0, sum = 4
6911 10:57:50.073120 best_step = 14
6912 10:57:50.073223
6913 10:57:50.073305 ==
6914 10:57:50.076326 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 10:57:50.079357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 10:57:50.079473 ==
6917 10:57:50.082667 RX Vref Scan: 0
6918 10:57:50.082768
6919 10:57:50.082868 RX Vref 0 -> 0, step: 1
6920 10:57:50.082966
6921 10:57:50.086043 RX Delay -311 -> 252, step: 8
6922 10:57:50.094114 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6923 10:57:50.097749 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6924 10:57:50.101070 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 10:57:50.104526 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6926 10:57:50.110701 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 10:57:50.114114 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6928 10:57:50.117303 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 10:57:50.120537 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6930 10:57:50.127748 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6931 10:57:50.130338 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 10:57:50.134313 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6933 10:57:50.137796 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6934 10:57:50.144300 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 10:57:50.147618 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 10:57:50.150890 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 10:57:50.157413 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 10:57:50.157522 ==
6939 10:57:50.160845 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 10:57:50.163868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 10:57:50.163947 ==
6942 10:57:50.164010 DQS Delay:
6943 10:57:50.167101 DQS0 = 28, DQS1 = 32
6944 10:57:50.167199 DQM Delay:
6945 10:57:50.170881 DQM0 = 11, DQM1 = 11
6946 10:57:50.170979 DQ Delay:
6947 10:57:50.173931 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6948 10:57:50.177610 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6949 10:57:50.180857 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6950 10:57:50.183894 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6951 10:57:50.183967
6952 10:57:50.184029
6953 10:57:50.190221 [DQSOSCAuto] RK1, (LSB)MR18= 0xc557, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6954 10:57:50.194174 CH1 RK1: MR19=C0C, MR18=C557
6955 10:57:50.200657 CH1_RK1: MR19=0xC0C, MR18=0xC557, DQSOSC=385, MR23=63, INC=398, DEC=265
6956 10:57:50.204342 [RxdqsGatingPostProcess] freq 400
6957 10:57:50.207090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 10:57:50.210421 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 10:57:50.213528 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 10:57:50.217542 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 10:57:50.220791 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 10:57:50.224034 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 10:57:50.227271 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 10:57:50.230537 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 10:57:50.233853 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 10:57:50.237125 Pre-setting of DQS Precalculation
6967 10:57:50.240420 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 10:57:50.250530 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 10:57:50.257125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 10:57:50.257212
6971 10:57:50.257281
6972 10:57:50.260358 [Calibration Summary] 800 Mbps
6973 10:57:50.260444 CH 0, Rank 0
6974 10:57:50.263581 SW Impedance : PASS
6975 10:57:50.263682 DUTY Scan : NO K
6976 10:57:50.266768 ZQ Calibration : PASS
6977 10:57:50.270387 Jitter Meter : NO K
6978 10:57:50.270489 CBT Training : PASS
6979 10:57:50.273929 Write leveling : PASS
6980 10:57:50.277288 RX DQS gating : PASS
6981 10:57:50.277411 RX DQ/DQS(RDDQC) : PASS
6982 10:57:50.280452 TX DQ/DQS : PASS
6983 10:57:50.283549 RX DATLAT : PASS
6984 10:57:50.283697 RX DQ/DQS(Engine): PASS
6985 10:57:50.286784 TX OE : NO K
6986 10:57:50.286945 All Pass.
6987 10:57:50.287066
6988 10:57:50.290553 CH 0, Rank 1
6989 10:57:50.290708 SW Impedance : PASS
6990 10:57:50.293755 DUTY Scan : NO K
6991 10:57:50.293937 ZQ Calibration : PASS
6992 10:57:50.296960 Jitter Meter : NO K
6993 10:57:50.300855 CBT Training : PASS
6994 10:57:50.301063 Write leveling : NO K
6995 10:57:50.304117 RX DQS gating : PASS
6996 10:57:50.306939 RX DQ/DQS(RDDQC) : PASS
6997 10:57:50.307244 TX DQ/DQS : PASS
6998 10:57:50.310748 RX DATLAT : PASS
6999 10:57:50.313932 RX DQ/DQS(Engine): PASS
7000 10:57:50.314320 TX OE : NO K
7001 10:57:50.317267 All Pass.
7002 10:57:50.317684
7003 10:57:50.318103 CH 1, Rank 0
7004 10:57:50.320477 SW Impedance : PASS
7005 10:57:50.320895 DUTY Scan : NO K
7006 10:57:50.323820 ZQ Calibration : PASS
7007 10:57:50.327144 Jitter Meter : NO K
7008 10:57:50.327638 CBT Training : PASS
7009 10:57:50.331082 Write leveling : PASS
7010 10:57:50.333722 RX DQS gating : PASS
7011 10:57:50.334145 RX DQ/DQS(RDDQC) : PASS
7012 10:57:50.337026 TX DQ/DQS : PASS
7013 10:57:50.337444 RX DATLAT : PASS
7014 10:57:50.340444 RX DQ/DQS(Engine): PASS
7015 10:57:50.343758 TX OE : NO K
7016 10:57:50.344180 All Pass.
7017 10:57:50.344512
7018 10:57:50.344818 CH 1, Rank 1
7019 10:57:50.347577 SW Impedance : PASS
7020 10:57:50.350836 DUTY Scan : NO K
7021 10:57:50.351253 ZQ Calibration : PASS
7022 10:57:50.354017 Jitter Meter : NO K
7023 10:57:50.357294 CBT Training : PASS
7024 10:57:50.357714 Write leveling : NO K
7025 10:57:50.361059 RX DQS gating : PASS
7026 10:57:50.364346 RX DQ/DQS(RDDQC) : PASS
7027 10:57:50.364925 TX DQ/DQS : PASS
7028 10:57:50.367585 RX DATLAT : PASS
7029 10:57:50.370898 RX DQ/DQS(Engine): PASS
7030 10:57:50.371322 TX OE : NO K
7031 10:57:50.371848 All Pass.
7032 10:57:50.374102
7033 10:57:50.374518 DramC Write-DBI off
7034 10:57:50.377081 PER_BANK_REFRESH: Hybrid Mode
7035 10:57:50.377448 TX_TRACKING: ON
7036 10:57:50.387128 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 10:57:50.390553 [FAST_K] Save calibration result to emmc
7038 10:57:50.393412 dramc_set_vcore_voltage set vcore to 725000
7039 10:57:50.397289 Read voltage for 1600, 0
7040 10:57:50.397704 Vio18 = 0
7041 10:57:50.400706 Vcore = 725000
7042 10:57:50.401222 Vdram = 0
7043 10:57:50.401589 Vddq = 0
7044 10:57:50.401920 Vmddr = 0
7045 10:57:50.407241 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 10:57:50.413473 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 10:57:50.413893 MEM_TYPE=3, freq_sel=13
7048 10:57:50.417038 sv_algorithm_assistance_LP4_3733
7049 10:57:50.420587 ============ PULL DRAM RESETB DOWN ============
7050 10:57:50.426788 ========== PULL DRAM RESETB DOWN end =========
7051 10:57:50.430083 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 10:57:50.433248 ===================================
7053 10:57:50.436693 LPDDR4 DRAM CONFIGURATION
7054 10:57:50.439982 ===================================
7055 10:57:50.440437 EX_ROW_EN[0] = 0x0
7056 10:57:50.443129 EX_ROW_EN[1] = 0x0
7057 10:57:50.447052 LP4Y_EN = 0x0
7058 10:57:50.447514 WORK_FSP = 0x1
7059 10:57:50.450364 WL = 0x5
7060 10:57:50.450780 RL = 0x5
7061 10:57:50.453621 BL = 0x2
7062 10:57:50.454038 RPST = 0x0
7063 10:57:50.456674 RD_PRE = 0x0
7064 10:57:50.457109 WR_PRE = 0x1
7065 10:57:50.459869 WR_PST = 0x1
7066 10:57:50.460286 DBI_WR = 0x0
7067 10:57:50.463168 DBI_RD = 0x0
7068 10:57:50.463653 OTF = 0x1
7069 10:57:50.466834 ===================================
7070 10:57:50.470067 ===================================
7071 10:57:50.473536 ANA top config
7072 10:57:50.476633 ===================================
7073 10:57:50.477053 DLL_ASYNC_EN = 0
7074 10:57:50.479788 ALL_SLAVE_EN = 0
7075 10:57:50.483594 NEW_RANK_MODE = 1
7076 10:57:50.486792 DLL_IDLE_MODE = 1
7077 10:57:50.489893 LP45_APHY_COMB_EN = 1
7078 10:57:50.490313 TX_ODT_DIS = 0
7079 10:57:50.492952 NEW_8X_MODE = 1
7080 10:57:50.496264 ===================================
7081 10:57:50.500146 ===================================
7082 10:57:50.503068 data_rate = 3200
7083 10:57:50.506224 CKR = 1
7084 10:57:50.509828 DQ_P2S_RATIO = 8
7085 10:57:50.512953 ===================================
7086 10:57:50.513375 CA_P2S_RATIO = 8
7087 10:57:50.516754 DQ_CA_OPEN = 0
7088 10:57:50.520056 DQ_SEMI_OPEN = 0
7089 10:57:50.523013 CA_SEMI_OPEN = 0
7090 10:57:50.526780 CA_FULL_RATE = 0
7091 10:57:50.529563 DQ_CKDIV4_EN = 0
7092 10:57:50.529989 CA_CKDIV4_EN = 0
7093 10:57:50.532871 CA_PREDIV_EN = 0
7094 10:57:50.536366 PH8_DLY = 12
7095 10:57:50.539684 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 10:57:50.542991 DQ_AAMCK_DIV = 4
7097 10:57:50.546215 CA_AAMCK_DIV = 4
7098 10:57:50.546642 CA_ADMCK_DIV = 4
7099 10:57:50.549516 DQ_TRACK_CA_EN = 0
7100 10:57:50.552727 CA_PICK = 1600
7101 10:57:50.556718 CA_MCKIO = 1600
7102 10:57:50.559404 MCKIO_SEMI = 0
7103 10:57:50.563123 PLL_FREQ = 3068
7104 10:57:50.566253 DQ_UI_PI_RATIO = 32
7105 10:57:50.569551 CA_UI_PI_RATIO = 0
7106 10:57:50.572689 ===================================
7107 10:57:50.575923 ===================================
7108 10:57:50.576348 memory_type:LPDDR4
7109 10:57:50.579279 GP_NUM : 10
7110 10:57:50.579723 SRAM_EN : 1
7111 10:57:50.582470 MD32_EN : 0
7112 10:57:50.586361 ===================================
7113 10:57:50.589541 [ANA_INIT] >>>>>>>>>>>>>>
7114 10:57:50.592859 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 10:57:50.596185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 10:57:50.599167 ===================================
7117 10:57:50.599767 data_rate = 3200,PCW = 0X7600
7118 10:57:50.602453 ===================================
7119 10:57:50.609432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 10:57:50.612606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 10:57:50.619445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 10:57:50.622647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 10:57:50.625743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 10:57:50.629434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 10:57:50.632503 [ANA_INIT] flow start
7126 10:57:50.635518 [ANA_INIT] PLL >>>>>>>>
7127 10:57:50.636008 [ANA_INIT] PLL <<<<<<<<
7128 10:57:50.639242 [ANA_INIT] MIDPI >>>>>>>>
7129 10:57:50.642741 [ANA_INIT] MIDPI <<<<<<<<
7130 10:57:50.643225 [ANA_INIT] DLL >>>>>>>>
7131 10:57:50.645885 [ANA_INIT] DLL <<<<<<<<
7132 10:57:50.649371 [ANA_INIT] flow end
7133 10:57:50.652546 ============ LP4 DIFF to SE enter ============
7134 10:57:50.655842 ============ LP4 DIFF to SE exit ============
7135 10:57:50.659083 [ANA_INIT] <<<<<<<<<<<<<
7136 10:57:50.662424 [Flow] Enable top DCM control >>>>>
7137 10:57:50.665588 [Flow] Enable top DCM control <<<<<
7138 10:57:50.668784 Enable DLL master slave shuffle
7139 10:57:50.672724 ==============================================================
7140 10:57:50.675868 Gating Mode config
7141 10:57:50.682306 ==============================================================
7142 10:57:50.682734 Config description:
7143 10:57:50.692858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 10:57:50.698738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 10:57:50.702675 SELPH_MODE 0: By rank 1: By Phase
7146 10:57:50.709260 ==============================================================
7147 10:57:50.712311 GAT_TRACK_EN = 1
7148 10:57:50.715868 RX_GATING_MODE = 2
7149 10:57:50.719022 RX_GATING_TRACK_MODE = 2
7150 10:57:50.722215 SELPH_MODE = 1
7151 10:57:50.725618 PICG_EARLY_EN = 1
7152 10:57:50.728832 VALID_LAT_VALUE = 1
7153 10:57:50.732757 ==============================================================
7154 10:57:50.735585 Enter into Gating configuration >>>>
7155 10:57:50.739178 Exit from Gating configuration <<<<
7156 10:57:50.742572 Enter into DVFS_PRE_config >>>>>
7157 10:57:50.752147 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 10:57:50.755882 Exit from DVFS_PRE_config <<<<<
7159 10:57:50.759073 Enter into PICG configuration >>>>
7160 10:57:50.762534 Exit from PICG configuration <<<<
7161 10:57:50.765757 [RX_INPUT] configuration >>>>>
7162 10:57:50.769010 [RX_INPUT] configuration <<<<<
7163 10:57:50.775606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 10:57:50.778937 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 10:57:50.785919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 10:57:50.792660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 10:57:50.798277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 10:57:50.805497 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 10:57:50.808502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 10:57:50.811706 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 10:57:50.815375 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 10:57:50.822485 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 10:57:50.825586 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 10:57:50.828863 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 10:57:50.832569 ===================================
7176 10:57:50.835664 LPDDR4 DRAM CONFIGURATION
7177 10:57:50.839291 ===================================
7178 10:57:50.839753 EX_ROW_EN[0] = 0x0
7179 10:57:50.842434 EX_ROW_EN[1] = 0x0
7180 10:57:50.843007 LP4Y_EN = 0x0
7181 10:57:50.845420 WORK_FSP = 0x1
7182 10:57:50.845917 WL = 0x5
7183 10:57:50.849302 RL = 0x5
7184 10:57:50.849748 BL = 0x2
7185 10:57:50.852095 RPST = 0x0
7186 10:57:50.852572 RD_PRE = 0x0
7187 10:57:50.855845 WR_PRE = 0x1
7188 10:57:50.858884 WR_PST = 0x1
7189 10:57:50.859311 DBI_WR = 0x0
7190 10:57:50.862251 DBI_RD = 0x0
7191 10:57:50.862682 OTF = 0x1
7192 10:57:50.865908 ===================================
7193 10:57:50.869385 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 10:57:50.871940 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 10:57:50.879011 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 10:57:50.882328 ===================================
7197 10:57:50.885528 LPDDR4 DRAM CONFIGURATION
7198 10:57:50.888590 ===================================
7199 10:57:50.889141 EX_ROW_EN[0] = 0x10
7200 10:57:50.891941 EX_ROW_EN[1] = 0x0
7201 10:57:50.892523 LP4Y_EN = 0x0
7202 10:57:50.895148 WORK_FSP = 0x1
7203 10:57:50.895726 WL = 0x5
7204 10:57:50.898917 RL = 0x5
7205 10:57:50.899562 BL = 0x2
7206 10:57:50.902171 RPST = 0x0
7207 10:57:50.902695 RD_PRE = 0x0
7208 10:57:50.905450 WR_PRE = 0x1
7209 10:57:50.905993 WR_PST = 0x1
7210 10:57:50.908782 DBI_WR = 0x0
7211 10:57:50.909377 DBI_RD = 0x0
7212 10:57:50.911872 OTF = 0x1
7213 10:57:50.915134 ===================================
7214 10:57:50.922234 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 10:57:50.922703 ==
7216 10:57:50.925970 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 10:57:50.928782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 10:57:50.929402 ==
7219 10:57:50.931789 [Duty_Offset_Calibration]
7220 10:57:50.932357 B0:2 B1:1 CA:1
7221 10:57:50.932899
7222 10:57:50.935377 [DutyScan_Calibration_Flow] k_type=0
7223 10:57:50.946485
7224 10:57:50.946956 ==CLK 0==
7225 10:57:50.949517 Final CLK duty delay cell = 0
7226 10:57:50.953211 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 10:57:50.956356 [0] MIN Duty = 4875%(X100), DQS PI = 0
7228 10:57:50.956917 [0] AVG Duty = 5015%(X100)
7229 10:57:50.959305
7230 10:57:50.963095 CH0 CLK Duty spec in!! Max-Min= 281%
7231 10:57:50.966134 [DutyScan_Calibration_Flow] ====Done====
7232 10:57:50.966645
7233 10:57:50.969830 [DutyScan_Calibration_Flow] k_type=1
7234 10:57:50.985273
7235 10:57:50.985848 ==DQS 0 ==
7236 10:57:50.988625 Final DQS duty delay cell = -4
7237 10:57:50.992257 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7238 10:57:50.995721 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7239 10:57:50.999003 [-4] AVG Duty = 4891%(X100)
7240 10:57:50.999653
7241 10:57:51.000109 ==DQS 1 ==
7242 10:57:51.002069 Final DQS duty delay cell = 0
7243 10:57:51.005316 [0] MAX Duty = 5187%(X100), DQS PI = 4
7244 10:57:51.008599 [0] MIN Duty = 5062%(X100), DQS PI = 34
7245 10:57:51.011914 [0] AVG Duty = 5124%(X100)
7246 10:57:51.012572
7247 10:57:51.015352 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 10:57:51.015921
7249 10:57:51.019187 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7250 10:57:51.022243 [DutyScan_Calibration_Flow] ====Done====
7251 10:57:51.022799
7252 10:57:51.025564 [DutyScan_Calibration_Flow] k_type=3
7253 10:57:51.042964
7254 10:57:51.043584 ==DQM 0 ==
7255 10:57:51.046047 Final DQM duty delay cell = 0
7256 10:57:51.049275 [0] MAX Duty = 5187%(X100), DQS PI = 26
7257 10:57:51.053148 [0] MIN Duty = 4907%(X100), DQS PI = 54
7258 10:57:51.056046 [0] AVG Duty = 5047%(X100)
7259 10:57:51.056595
7260 10:57:51.057069 ==DQM 1 ==
7261 10:57:51.059097 Final DQM duty delay cell = 0
7262 10:57:51.062872 [0] MAX Duty = 5187%(X100), DQS PI = 4
7263 10:57:51.065962 [0] MIN Duty = 5031%(X100), DQS PI = 48
7264 10:57:51.069014 [0] AVG Duty = 5109%(X100)
7265 10:57:51.069618
7266 10:57:51.072834 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7267 10:57:51.073328
7268 10:57:51.075765 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7269 10:57:51.079242 [DutyScan_Calibration_Flow] ====Done====
7270 10:57:51.080100
7271 10:57:51.082304 [DutyScan_Calibration_Flow] k_type=2
7272 10:57:51.100308
7273 10:57:51.100754 ==DQ 0 ==
7274 10:57:51.103651 Final DQ duty delay cell = 0
7275 10:57:51.106773 [0] MAX Duty = 5062%(X100), DQS PI = 24
7276 10:57:51.109955 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 10:57:51.110526 [0] AVG Duty = 4984%(X100)
7278 10:57:51.110878
7279 10:57:51.113930 ==DQ 1 ==
7280 10:57:51.117280 Final DQ duty delay cell = 0
7281 10:57:51.120559 [0] MAX Duty = 5125%(X100), DQS PI = 4
7282 10:57:51.123703 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 10:57:51.124134 [0] AVG Duty = 5016%(X100)
7284 10:57:51.124476
7285 10:57:51.126907 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 10:57:51.127555
7287 10:57:51.130232 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7288 10:57:51.136558 [DutyScan_Calibration_Flow] ====Done====
7289 10:57:51.137055 ==
7290 10:57:51.139849 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 10:57:51.143220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 10:57:51.143838 ==
7293 10:57:51.146864 [Duty_Offset_Calibration]
7294 10:57:51.147380 B0:1 B1:0 CA:1
7295 10:57:51.147727
7296 10:57:51.150152 [DutyScan_Calibration_Flow] k_type=0
7297 10:57:51.159715
7298 10:57:51.160180 ==CLK 0==
7299 10:57:51.162979 Final CLK duty delay cell = -4
7300 10:57:51.166027 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7301 10:57:51.169106 [-4] MIN Duty = 4876%(X100), DQS PI = 2
7302 10:57:51.172335 [-4] AVG Duty = 4938%(X100)
7303 10:57:51.172671
7304 10:57:51.175492 CH1 CLK Duty spec in!! Max-Min= 124%
7305 10:57:51.179200 [DutyScan_Calibration_Flow] ====Done====
7306 10:57:51.179569
7307 10:57:51.182090 [DutyScan_Calibration_Flow] k_type=1
7308 10:57:51.198299
7309 10:57:51.198630 ==DQS 0 ==
7310 10:57:51.201511 Final DQS duty delay cell = 0
7311 10:57:51.204933 [0] MAX Duty = 5094%(X100), DQS PI = 24
7312 10:57:51.208174 [0] MIN Duty = 4875%(X100), DQS PI = 0
7313 10:57:51.211883 [0] AVG Duty = 4984%(X100)
7314 10:57:51.212220
7315 10:57:51.212522 ==DQS 1 ==
7316 10:57:51.215198 Final DQS duty delay cell = -4
7317 10:57:51.218490 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7318 10:57:51.221845 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7319 10:57:51.225035 [-4] AVG Duty = 4859%(X100)
7320 10:57:51.225328
7321 10:57:51.228252 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7322 10:57:51.228528
7323 10:57:51.231531 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7324 10:57:51.234904 [DutyScan_Calibration_Flow] ====Done====
7325 10:57:51.235240
7326 10:57:51.238174 [DutyScan_Calibration_Flow] k_type=3
7327 10:57:51.256033
7328 10:57:51.256451 ==DQM 0 ==
7329 10:57:51.258687 Final DQM duty delay cell = 0
7330 10:57:51.262528 [0] MAX Duty = 5218%(X100), DQS PI = 18
7331 10:57:51.265398 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 10:57:51.268797 [0] AVG Duty = 5093%(X100)
7333 10:57:51.269400
7334 10:57:51.269793 ==DQM 1 ==
7335 10:57:51.272401 Final DQM duty delay cell = 0
7336 10:57:51.275514 [0] MAX Duty = 5093%(X100), DQS PI = 16
7337 10:57:51.279243 [0] MIN Duty = 4876%(X100), DQS PI = 52
7338 10:57:51.282439 [0] AVG Duty = 4984%(X100)
7339 10:57:51.282867
7340 10:57:51.285677 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7341 10:57:51.286087
7342 10:57:51.288887 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7343 10:57:51.291881 [DutyScan_Calibration_Flow] ====Done====
7344 10:57:51.292288
7345 10:57:51.295226 [DutyScan_Calibration_Flow] k_type=2
7346 10:57:51.311813
7347 10:57:51.312376 ==DQ 0 ==
7348 10:57:51.314984 Final DQ duty delay cell = -4
7349 10:57:51.318239 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7350 10:57:51.321541 [-4] MIN Duty = 4875%(X100), DQS PI = 48
7351 10:57:51.324968 [-4] AVG Duty = 4968%(X100)
7352 10:57:51.325521
7353 10:57:51.325987 ==DQ 1 ==
7354 10:57:51.328302 Final DQ duty delay cell = 0
7355 10:57:51.331647 [0] MAX Duty = 5124%(X100), DQS PI = 18
7356 10:57:51.334961 [0] MIN Duty = 4938%(X100), DQS PI = 8
7357 10:57:51.338248 [0] AVG Duty = 5031%(X100)
7358 10:57:51.338664
7359 10:57:51.341727 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7360 10:57:51.342371
7361 10:57:51.344908 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7362 10:57:51.348245 [DutyScan_Calibration_Flow] ====Done====
7363 10:57:51.351715 nWR fixed to 30
7364 10:57:51.352227 [ModeRegInit_LP4] CH0 RK0
7365 10:57:51.354871 [ModeRegInit_LP4] CH0 RK1
7366 10:57:51.358648 [ModeRegInit_LP4] CH1 RK0
7367 10:57:51.361753 [ModeRegInit_LP4] CH1 RK1
7368 10:57:51.362369 match AC timing 5
7369 10:57:51.368308 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 10:57:51.372091 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 10:57:51.375238 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 10:57:51.381913 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 10:57:51.385088 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 10:57:51.385517 [MiockJmeterHQA]
7375 10:57:51.385884
7376 10:57:51.388365 [DramcMiockJmeter] u1RxGatingPI = 0
7377 10:57:51.391724 0 : 4252, 4027
7378 10:57:51.392188 4 : 4252, 4027
7379 10:57:51.394812 8 : 4252, 4027
7380 10:57:51.395246 12 : 4252, 4027
7381 10:57:51.395721 16 : 4252, 4027
7382 10:57:51.398527 20 : 4252, 4027
7383 10:57:51.398962 24 : 4252, 4027
7384 10:57:51.401565 28 : 4363, 4137
7385 10:57:51.402037 32 : 4252, 4027
7386 10:57:51.404886 36 : 4255, 4029
7387 10:57:51.405397 40 : 4252, 4027
7388 10:57:51.405750 44 : 4252, 4027
7389 10:57:51.408002 48 : 4253, 4026
7390 10:57:51.408433 52 : 4363, 4138
7391 10:57:51.411707 56 : 4363, 4137
7392 10:57:51.412157 60 : 4254, 4029
7393 10:57:51.414717 64 : 4252, 4027
7394 10:57:51.415202 68 : 4253, 4026
7395 10:57:51.417964 72 : 4252, 4027
7396 10:57:51.418439 76 : 4249, 4027
7397 10:57:51.418807 80 : 4361, 4137
7398 10:57:51.421642 84 : 4250, 4027
7399 10:57:51.422107 88 : 4250, 177
7400 10:57:51.424871 92 : 4361, 0
7401 10:57:51.425357 96 : 4255, 0
7402 10:57:51.425744 100 : 4253, 0
7403 10:57:51.428187 104 : 4360, 0
7404 10:57:51.428586 108 : 4250, 0
7405 10:57:51.431592 112 : 4360, 0
7406 10:57:51.432028 116 : 4250, 0
7407 10:57:51.432483 120 : 4250, 0
7408 10:57:51.434843 124 : 4252, 0
7409 10:57:51.435276 128 : 4250, 0
7410 10:57:51.438668 132 : 4250, 0
7411 10:57:51.439137 136 : 4250, 0
7412 10:57:51.439539 140 : 4250, 0
7413 10:57:51.441408 144 : 4249, 0
7414 10:57:51.441841 148 : 4360, 0
7415 10:57:51.442187 152 : 4361, 0
7416 10:57:51.444656 156 : 4250, 0
7417 10:57:51.445123 160 : 4250, 0
7418 10:57:51.448698 164 : 4250, 0
7419 10:57:51.449133 168 : 4250, 0
7420 10:57:51.449490 172 : 4250, 0
7421 10:57:51.451233 176 : 4252, 0
7422 10:57:51.451717 180 : 4250, 0
7423 10:57:51.455286 184 : 4250, 0
7424 10:57:51.455828 188 : 4250, 0
7425 10:57:51.456196 192 : 4250, 0
7426 10:57:51.458413 196 : 4250, 0
7427 10:57:51.458924 200 : 4360, 0
7428 10:57:51.461555 204 : 4361, 1400
7429 10:57:51.462182 208 : 4250, 3965
7430 10:57:51.464743 212 : 4250, 4027
7431 10:57:51.465195 216 : 4363, 4140
7432 10:57:51.465606 220 : 4249, 4027
7433 10:57:51.468068 224 : 4250, 4027
7434 10:57:51.468551 228 : 4250, 4027
7435 10:57:51.471566 232 : 4250, 4027
7436 10:57:51.472200 236 : 4250, 4026
7437 10:57:51.475055 240 : 4250, 4027
7438 10:57:51.475591 244 : 4360, 4138
7439 10:57:51.478268 248 : 4250, 4027
7440 10:57:51.478697 252 : 4250, 4026
7441 10:57:51.481367 256 : 4361, 4137
7442 10:57:51.481791 260 : 4250, 4027
7443 10:57:51.484444 264 : 4250, 4027
7444 10:57:51.485010 268 : 4360, 4137
7445 10:57:51.488131 272 : 4250, 4026
7446 10:57:51.488557 276 : 4250, 4027
7447 10:57:51.491124 280 : 4250, 4027
7448 10:57:51.491586 284 : 4250, 4027
7449 10:57:51.491942 288 : 4250, 4026
7450 10:57:51.494307 292 : 4250, 4027
7451 10:57:51.494766 296 : 4360, 4138
7452 10:57:51.498211 300 : 4250, 4027
7453 10:57:51.498791 304 : 4250, 4026
7454 10:57:51.501355 308 : 4361, 4101
7455 10:57:51.501796 312 : 4250, 2173
7456 10:57:51.504581 316 : 4253, 9
7457 10:57:51.505032
7458 10:57:51.505364 MIOCK jitter meter ch=0
7459 10:57:51.505688
7460 10:57:51.507708 1T = (316-88) = 228 dly cells
7461 10:57:51.514704 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7462 10:57:51.515295 ==
7463 10:57:51.517853 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 10:57:51.520987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 10:57:51.521498 ==
7466 10:57:51.527578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 10:57:51.530740 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 10:57:51.534476 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 10:57:51.540918 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 10:57:51.550661 [CA 0] Center 42 (12~73) winsize 62
7471 10:57:51.553928 [CA 1] Center 43 (12~74) winsize 63
7472 10:57:51.557282 [CA 2] Center 38 (9~68) winsize 60
7473 10:57:51.560480 [CA 3] Center 37 (8~67) winsize 60
7474 10:57:51.563696 [CA 4] Center 36 (7~66) winsize 60
7475 10:57:51.567385 [CA 5] Center 35 (6~65) winsize 60
7476 10:57:51.568074
7477 10:57:51.570654 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 10:57:51.571277
7479 10:57:51.573867 [CATrainingPosCal] consider 1 rank data
7480 10:57:51.577257 u2DelayCellTimex100 = 285/100 ps
7481 10:57:51.580535 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 10:57:51.587442 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7483 10:57:51.590506 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7484 10:57:51.594154 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7485 10:57:51.597195 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7486 10:57:51.600547 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7487 10:57:51.601168
7488 10:57:51.603677 CA PerBit enable=1, Macro0, CA PI delay=35
7489 10:57:51.604299
7490 10:57:51.607598 [CBTSetCACLKResult] CA Dly = 35
7491 10:57:51.610711 CS Dly: 9 (0~40)
7492 10:57:51.613842 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 10:57:51.617120 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 10:57:51.617814 ==
7495 10:57:51.620748 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 10:57:51.624038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 10:57:51.627084 ==
7498 10:57:51.630304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 10:57:51.633449 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 10:57:51.640285 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 10:57:51.643563 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 10:57:51.653664 [CA 0] Center 42 (12~73) winsize 62
7503 10:57:51.657216 [CA 1] Center 42 (12~73) winsize 62
7504 10:57:51.660870 [CA 2] Center 38 (8~68) winsize 61
7505 10:57:51.664043 [CA 3] Center 37 (8~67) winsize 60
7506 10:57:51.667255 [CA 4] Center 36 (6~66) winsize 61
7507 10:57:51.670358 [CA 5] Center 35 (5~65) winsize 61
7508 10:57:51.670904
7509 10:57:51.674361 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7510 10:57:51.674998
7511 10:57:51.677605 [CATrainingPosCal] consider 2 rank data
7512 10:57:51.680971 u2DelayCellTimex100 = 285/100 ps
7513 10:57:51.683768 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 10:57:51.690244 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 10:57:51.693854 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7516 10:57:51.697178 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 10:57:51.700171 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7518 10:57:51.703912 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7519 10:57:51.704585
7520 10:57:51.706898 CA PerBit enable=1, Macro0, CA PI delay=35
7521 10:57:51.707398
7522 10:57:51.710037 [CBTSetCACLKResult] CA Dly = 35
7523 10:57:51.713257 CS Dly: 10 (0~42)
7524 10:57:51.716711 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 10:57:51.720549 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 10:57:51.721195
7527 10:57:51.723819 ----->DramcWriteLeveling(PI) begin...
7528 10:57:51.724302 ==
7529 10:57:51.726913 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 10:57:51.733315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 10:57:51.733770 ==
7532 10:57:51.736587 Write leveling (Byte 0): 35 => 35
7533 10:57:51.737158 Write leveling (Byte 1): 26 => 26
7534 10:57:51.740429 DramcWriteLeveling(PI) end<-----
7535 10:57:51.741012
7536 10:57:51.743202 ==
7537 10:57:51.743715 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 10:57:51.749924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 10:57:51.750483 ==
7540 10:57:51.753277 [Gating] SW mode calibration
7541 10:57:51.759960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 10:57:51.763241 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 10:57:51.770412 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 10:57:51.773684 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 10:57:51.776684 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7546 10:57:51.783312 1 4 12 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)
7547 10:57:51.786493 1 4 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7548 10:57:51.789917 1 4 20 | B1->B0 | 3333 3635 | 1 1 | (1 1) (1 1)
7549 10:57:51.796458 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7550 10:57:51.799613 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7551 10:57:51.803433 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7552 10:57:51.809497 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 10:57:51.813343 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7554 10:57:51.816284 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7555 10:57:51.822941 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (0 1) (0 0)
7556 10:57:51.826199 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
7557 10:57:51.830056 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7558 10:57:51.836313 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7559 10:57:51.839797 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7560 10:57:51.843063 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7561 10:57:51.846359 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7562 10:57:51.853209 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7563 10:57:51.856289 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7564 10:57:51.859824 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)
7565 10:57:51.866403 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 10:57:51.869647 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 10:57:51.872941 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 10:57:51.879583 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 10:57:51.882680 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 10:57:51.886049 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 10:57:51.892758 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 10:57:51.896045 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 10:57:51.899990 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 10:57:51.906333 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 10:57:51.909687 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 10:57:51.913037 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 10:57:51.919847 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 10:57:51.923048 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 10:57:51.926473 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 10:57:51.933130 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 10:57:51.936241 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 10:57:51.939400 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:57:51.946261 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:57:51.949934 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:57:51.952850 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 10:57:51.959281 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 10:57:51.962970 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7588 10:57:51.966206 Total UI for P1: 0, mck2ui 16
7589 10:57:51.969304 best dqsien dly found for B0: ( 1, 9, 10)
7590 10:57:51.973151 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 10:57:51.975742 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 10:57:51.979596 Total UI for P1: 0, mck2ui 16
7593 10:57:51.982912 best dqsien dly found for B1: ( 1, 9, 20)
7594 10:57:51.986075 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7595 10:57:51.989351 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7596 10:57:51.992638
7597 10:57:51.996088 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7598 10:57:51.999484 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7599 10:57:52.002692 [Gating] SW calibration Done
7600 10:57:52.003120 ==
7601 10:57:52.006070 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 10:57:52.009444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 10:57:52.009989 ==
7604 10:57:52.012253 RX Vref Scan: 0
7605 10:57:52.012819
7606 10:57:52.013252 RX Vref 0 -> 0, step: 1
7607 10:57:52.013615
7608 10:57:52.016026 RX Delay 0 -> 252, step: 8
7609 10:57:52.019288 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7610 10:57:52.022354 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7611 10:57:52.029254 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7612 10:57:52.032322 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7613 10:57:52.035808 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 10:57:52.038980 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7615 10:57:52.042220 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7616 10:57:52.049316 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7617 10:57:52.052386 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7618 10:57:52.055620 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7619 10:57:52.059182 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7620 10:57:52.062149 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7621 10:57:52.069069 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7622 10:57:52.072217 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7623 10:57:52.075463 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7624 10:57:52.078668 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7625 10:57:52.079218 ==
7626 10:57:52.082482 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 10:57:52.089097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 10:57:52.089570 ==
7629 10:57:52.090085 DQS Delay:
7630 10:57:52.090430 DQS0 = 0, DQS1 = 0
7631 10:57:52.092208 DQM Delay:
7632 10:57:52.092816 DQM0 = 136, DQM1 = 129
7633 10:57:52.095353 DQ Delay:
7634 10:57:52.098653 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7635 10:57:52.102002 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7636 10:57:52.105276 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7637 10:57:52.108635 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7638 10:57:52.109055
7639 10:57:52.109470
7640 10:57:52.109789 ==
7641 10:57:52.111884 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 10:57:52.115233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 10:57:52.118882 ==
7644 10:57:52.119306
7645 10:57:52.119696
7646 10:57:52.120274 TX Vref Scan disable
7647 10:57:52.122138 == TX Byte 0 ==
7648 10:57:52.125274 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7649 10:57:52.128429 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7650 10:57:52.132126 == TX Byte 1 ==
7651 10:57:52.135144 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7652 10:57:52.138337 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7653 10:57:52.142144 ==
7654 10:57:52.142724 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 10:57:52.148223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 10:57:52.148822 ==
7657 10:57:52.160456
7658 10:57:52.163807 TX Vref early break, caculate TX vref
7659 10:57:52.166795 TX Vref=16, minBit 7, minWin=22, winSum=379
7660 10:57:52.170403 TX Vref=18, minBit 0, minWin=23, winSum=390
7661 10:57:52.173343 TX Vref=20, minBit 0, minWin=24, winSum=402
7662 10:57:52.177036 TX Vref=22, minBit 0, minWin=24, winSum=411
7663 10:57:52.180293 TX Vref=24, minBit 7, minWin=24, winSum=416
7664 10:57:52.186512 TX Vref=26, minBit 7, minWin=25, winSum=429
7665 10:57:52.190185 TX Vref=28, minBit 1, minWin=25, winSum=422
7666 10:57:52.193448 TX Vref=30, minBit 7, minWin=24, winSum=416
7667 10:57:52.196686 TX Vref=32, minBit 6, minWin=23, winSum=404
7668 10:57:52.203317 [TxChooseVref] Worse bit 7, Min win 25, Win sum 429, Final Vref 26
7669 10:57:52.203782
7670 10:57:52.206478 Final TX Range 0 Vref 26
7671 10:57:52.206899
7672 10:57:52.207304 ==
7673 10:57:52.209806 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 10:57:52.213191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 10:57:52.213744 ==
7676 10:57:52.214238
7677 10:57:52.214658
7678 10:57:52.216429 TX Vref Scan disable
7679 10:57:52.222982 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7680 10:57:52.223571 == TX Byte 0 ==
7681 10:57:52.226583 u2DelayCellOfst[0]=10 cells (3 PI)
7682 10:57:52.229856 u2DelayCellOfst[1]=17 cells (5 PI)
7683 10:57:52.232893 u2DelayCellOfst[2]=10 cells (3 PI)
7684 10:57:52.236619 u2DelayCellOfst[3]=10 cells (3 PI)
7685 10:57:52.239606 u2DelayCellOfst[4]=6 cells (2 PI)
7686 10:57:52.243195 u2DelayCellOfst[5]=0 cells (0 PI)
7687 10:57:52.243734 u2DelayCellOfst[6]=17 cells (5 PI)
7688 10:57:52.246379 u2DelayCellOfst[7]=17 cells (5 PI)
7689 10:57:52.252690 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7690 10:57:52.256100 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7691 10:57:52.256528 == TX Byte 1 ==
7692 10:57:52.259215 u2DelayCellOfst[8]=3 cells (1 PI)
7693 10:57:52.263086 u2DelayCellOfst[9]=0 cells (0 PI)
7694 10:57:52.266333 u2DelayCellOfst[10]=6 cells (2 PI)
7695 10:57:52.269666 u2DelayCellOfst[11]=3 cells (1 PI)
7696 10:57:52.272834 u2DelayCellOfst[12]=10 cells (3 PI)
7697 10:57:52.276494 u2DelayCellOfst[13]=13 cells (4 PI)
7698 10:57:52.279715 u2DelayCellOfst[14]=13 cells (4 PI)
7699 10:57:52.282892 u2DelayCellOfst[15]=10 cells (3 PI)
7700 10:57:52.286484 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7701 10:57:52.289498 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7702 10:57:52.292624 DramC Write-DBI on
7703 10:57:52.293107 ==
7704 10:57:52.296555 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 10:57:52.299600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 10:57:52.300393 ==
7707 10:57:52.300892
7708 10:57:52.303096
7709 10:57:52.303622 TX Vref Scan disable
7710 10:57:52.305821 == TX Byte 0 ==
7711 10:57:52.309295 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7712 10:57:52.312687 == TX Byte 1 ==
7713 10:57:52.316045 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7714 10:57:52.316689 DramC Write-DBI off
7715 10:57:52.317106
7716 10:57:52.319360 [DATLAT]
7717 10:57:52.319734 Freq=1600, CH0 RK0
7718 10:57:52.320123
7719 10:57:52.322584 DATLAT Default: 0xf
7720 10:57:52.323098 0, 0xFFFF, sum = 0
7721 10:57:52.326595 1, 0xFFFF, sum = 0
7722 10:57:52.327030 2, 0xFFFF, sum = 0
7723 10:57:52.329793 3, 0xFFFF, sum = 0
7724 10:57:52.330227 4, 0xFFFF, sum = 0
7725 10:57:52.332921 5, 0xFFFF, sum = 0
7726 10:57:52.333428 6, 0xFFFF, sum = 0
7727 10:57:52.336026 7, 0xFFFF, sum = 0
7728 10:57:52.339809 8, 0xFFFF, sum = 0
7729 10:57:52.340366 9, 0xFFFF, sum = 0
7730 10:57:52.342779 10, 0xFFFF, sum = 0
7731 10:57:52.343264 11, 0xFFFF, sum = 0
7732 10:57:52.345957 12, 0xFFFF, sum = 0
7733 10:57:52.346561 13, 0xFFFF, sum = 0
7734 10:57:52.349706 14, 0x0, sum = 1
7735 10:57:52.350177 15, 0x0, sum = 2
7736 10:57:52.352796 16, 0x0, sum = 3
7737 10:57:52.353299 17, 0x0, sum = 4
7738 10:57:52.353659 best_step = 15
7739 10:57:52.355903
7740 10:57:52.356329 ==
7741 10:57:52.359215 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 10:57:52.363108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 10:57:52.363537 ==
7744 10:57:52.363867 RX Vref Scan: 1
7745 10:57:52.364179
7746 10:57:52.366424 Set Vref Range= 24 -> 127
7747 10:57:52.367035
7748 10:57:52.369407 RX Vref 24 -> 127, step: 1
7749 10:57:52.369851
7750 10:57:52.372814 RX Delay 19 -> 252, step: 4
7751 10:57:52.373320
7752 10:57:52.376018 Set Vref, RX VrefLevel [Byte0]: 24
7753 10:57:52.378999 [Byte1]: 24
7754 10:57:52.379081
7755 10:57:52.382253 Set Vref, RX VrefLevel [Byte0]: 25
7756 10:57:52.386020 [Byte1]: 25
7757 10:57:52.386101
7758 10:57:52.389299 Set Vref, RX VrefLevel [Byte0]: 26
7759 10:57:52.392396 [Byte1]: 26
7760 10:57:52.395928
7761 10:57:52.396038 Set Vref, RX VrefLevel [Byte0]: 27
7762 10:57:52.399083 [Byte1]: 27
7763 10:57:52.403348
7764 10:57:52.403442 Set Vref, RX VrefLevel [Byte0]: 28
7765 10:57:52.407029 [Byte1]: 28
7766 10:57:52.410828
7767 10:57:52.410909 Set Vref, RX VrefLevel [Byte0]: 29
7768 10:57:52.414693 [Byte1]: 29
7769 10:57:52.418706
7770 10:57:52.418787 Set Vref, RX VrefLevel [Byte0]: 30
7771 10:57:52.422080 [Byte1]: 30
7772 10:57:52.426145
7773 10:57:52.426232 Set Vref, RX VrefLevel [Byte0]: 31
7774 10:57:52.429359 [Byte1]: 31
7775 10:57:52.433840
7776 10:57:52.433965 Set Vref, RX VrefLevel [Byte0]: 32
7777 10:57:52.437294 [Byte1]: 32
7778 10:57:52.441596
7779 10:57:52.441707 Set Vref, RX VrefLevel [Byte0]: 33
7780 10:57:52.444717 [Byte1]: 33
7781 10:57:52.448922
7782 10:57:52.449046 Set Vref, RX VrefLevel [Byte0]: 34
7783 10:57:52.452022 [Byte1]: 34
7784 10:57:52.456299
7785 10:57:52.456450 Set Vref, RX VrefLevel [Byte0]: 35
7786 10:57:52.460131 [Byte1]: 35
7787 10:57:52.463843
7788 10:57:52.464016 Set Vref, RX VrefLevel [Byte0]: 36
7789 10:57:52.467846 [Byte1]: 36
7790 10:57:52.471612
7791 10:57:52.471854 Set Vref, RX VrefLevel [Byte0]: 37
7792 10:57:52.474798 [Byte1]: 37
7793 10:57:52.479405
7794 10:57:52.479753 Set Vref, RX VrefLevel [Byte0]: 38
7795 10:57:52.482773 [Byte1]: 38
7796 10:57:52.487461
7797 10:57:52.487916 Set Vref, RX VrefLevel [Byte0]: 39
7798 10:57:52.490573 [Byte1]: 39
7799 10:57:52.494493
7800 10:57:52.495170 Set Vref, RX VrefLevel [Byte0]: 40
7801 10:57:52.498248 [Byte1]: 40
7802 10:57:52.502060
7803 10:57:52.502585 Set Vref, RX VrefLevel [Byte0]: 41
7804 10:57:52.505369 [Byte1]: 41
7805 10:57:52.509672
7806 10:57:52.510254 Set Vref, RX VrefLevel [Byte0]: 42
7807 10:57:52.513439 [Byte1]: 42
7808 10:57:52.517734
7809 10:57:52.518443 Set Vref, RX VrefLevel [Byte0]: 43
7810 10:57:52.520773 [Byte1]: 43
7811 10:57:52.524636
7812 10:57:52.525308 Set Vref, RX VrefLevel [Byte0]: 44
7813 10:57:52.528039 [Byte1]: 44
7814 10:57:52.532745
7815 10:57:52.533205 Set Vref, RX VrefLevel [Byte0]: 45
7816 10:57:52.535921 [Byte1]: 45
7817 10:57:52.539813
7818 10:57:52.540336 Set Vref, RX VrefLevel [Byte0]: 46
7819 10:57:52.543161 [Byte1]: 46
7820 10:57:52.547604
7821 10:57:52.548034 Set Vref, RX VrefLevel [Byte0]: 47
7822 10:57:52.550871 [Byte1]: 47
7823 10:57:52.555280
7824 10:57:52.555762 Set Vref, RX VrefLevel [Byte0]: 48
7825 10:57:52.558720 [Byte1]: 48
7826 10:57:52.562924
7827 10:57:52.563378 Set Vref, RX VrefLevel [Byte0]: 49
7828 10:57:52.566224 [Byte1]: 49
7829 10:57:52.570668
7830 10:57:52.571081 Set Vref, RX VrefLevel [Byte0]: 50
7831 10:57:52.573937 [Byte1]: 50
7832 10:57:52.577777
7833 10:57:52.578197 Set Vref, RX VrefLevel [Byte0]: 51
7834 10:57:52.581000 [Byte1]: 51
7835 10:57:52.585552
7836 10:57:52.585972 Set Vref, RX VrefLevel [Byte0]: 52
7837 10:57:52.588700 [Byte1]: 52
7838 10:57:52.593048
7839 10:57:52.593466 Set Vref, RX VrefLevel [Byte0]: 53
7840 10:57:52.596304 [Byte1]: 53
7841 10:57:52.600695
7842 10:57:52.601112 Set Vref, RX VrefLevel [Byte0]: 54
7843 10:57:52.603892 [Byte1]: 54
7844 10:57:52.608226
7845 10:57:52.608716 Set Vref, RX VrefLevel [Byte0]: 55
7846 10:57:52.611354 [Byte1]: 55
7847 10:57:52.615747
7848 10:57:52.616171 Set Vref, RX VrefLevel [Byte0]: 56
7849 10:57:52.619179 [Byte1]: 56
7850 10:57:52.623392
7851 10:57:52.623818 Set Vref, RX VrefLevel [Byte0]: 57
7852 10:57:52.626475 [Byte1]: 57
7853 10:57:52.630963
7854 10:57:52.631476 Set Vref, RX VrefLevel [Byte0]: 58
7855 10:57:52.634223 [Byte1]: 58
7856 10:57:52.638832
7857 10:57:52.639516 Set Vref, RX VrefLevel [Byte0]: 59
7858 10:57:52.641518 [Byte1]: 59
7859 10:57:52.646084
7860 10:57:52.646623 Set Vref, RX VrefLevel [Byte0]: 60
7861 10:57:52.649560 [Byte1]: 60
7862 10:57:52.653912
7863 10:57:52.654509 Set Vref, RX VrefLevel [Byte0]: 61
7864 10:57:52.657128 [Byte1]: 61
7865 10:57:52.661647
7866 10:57:52.662157 Set Vref, RX VrefLevel [Byte0]: 62
7867 10:57:52.664631 [Byte1]: 62
7868 10:57:52.668870
7869 10:57:52.669349 Set Vref, RX VrefLevel [Byte0]: 63
7870 10:57:52.671924 [Byte1]: 63
7871 10:57:52.676389
7872 10:57:52.676911 Set Vref, RX VrefLevel [Byte0]: 64
7873 10:57:52.679618 [Byte1]: 64
7874 10:57:52.684350
7875 10:57:52.684860 Set Vref, RX VrefLevel [Byte0]: 65
7876 10:57:52.687418 [Byte1]: 65
7877 10:57:52.691292
7878 10:57:52.692019 Set Vref, RX VrefLevel [Byte0]: 66
7879 10:57:52.695189 [Byte1]: 66
7880 10:57:52.699068
7881 10:57:52.699663 Set Vref, RX VrefLevel [Byte0]: 67
7882 10:57:52.702349 [Byte1]: 67
7883 10:57:52.706744
7884 10:57:52.707406 Set Vref, RX VrefLevel [Byte0]: 68
7885 10:57:52.710176 [Byte1]: 68
7886 10:57:52.713971
7887 10:57:52.714449 Set Vref, RX VrefLevel [Byte0]: 69
7888 10:57:52.717383 [Byte1]: 69
7889 10:57:52.721890
7890 10:57:52.722695 Set Vref, RX VrefLevel [Byte0]: 70
7891 10:57:52.725162 [Byte1]: 70
7892 10:57:52.729604
7893 10:57:52.730136 Set Vref, RX VrefLevel [Byte0]: 71
7894 10:57:52.732750 [Byte1]: 71
7895 10:57:52.737119
7896 10:57:52.737600 Set Vref, RX VrefLevel [Byte0]: 72
7897 10:57:52.740440 [Byte1]: 72
7898 10:57:52.744403
7899 10:57:52.744911 Set Vref, RX VrefLevel [Byte0]: 73
7900 10:57:52.747659 [Byte1]: 73
7901 10:57:52.752353
7902 10:57:52.752845 Set Vref, RX VrefLevel [Byte0]: 74
7903 10:57:52.755756 [Byte1]: 74
7904 10:57:52.759298
7905 10:57:52.759856 Set Vref, RX VrefLevel [Byte0]: 75
7906 10:57:52.763070 [Byte1]: 75
7907 10:57:52.767415
7908 10:57:52.768003 Set Vref, RX VrefLevel [Byte0]: 76
7909 10:57:52.770528 [Byte1]: 76
7910 10:57:52.774916
7911 10:57:52.775461 Set Vref, RX VrefLevel [Byte0]: 77
7912 10:57:52.777877 [Byte1]: 77
7913 10:57:52.782510
7914 10:57:52.782973 Final RX Vref Byte 0 = 59 to rank0
7915 10:57:52.785830 Final RX Vref Byte 1 = 60 to rank0
7916 10:57:52.788919 Final RX Vref Byte 0 = 59 to rank1
7917 10:57:52.792411 Final RX Vref Byte 1 = 60 to rank1==
7918 10:57:52.795652 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 10:57:52.802726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 10:57:52.803152 ==
7921 10:57:52.803522 DQS Delay:
7922 10:57:52.803838 DQS0 = 0, DQS1 = 0
7923 10:57:52.805981 DQM Delay:
7924 10:57:52.806616 DQM0 = 134, DQM1 = 127
7925 10:57:52.809376 DQ Delay:
7926 10:57:52.812716 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7927 10:57:52.815996 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7928 10:57:52.819146 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7929 10:57:52.822394 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7930 10:57:52.822948
7931 10:57:52.823299
7932 10:57:52.823677
7933 10:57:52.825630 [DramC_TX_OE_Calibration] TA2
7934 10:57:52.828766 Original DQ_B0 (3 6) =30, OEN = 27
7935 10:57:52.832436 Original DQ_B1 (3 6) =30, OEN = 27
7936 10:57:52.835808 24, 0x0, End_B0=24 End_B1=24
7937 10:57:52.836244 25, 0x0, End_B0=25 End_B1=25
7938 10:57:52.839005 26, 0x0, End_B0=26 End_B1=26
7939 10:57:52.841934 27, 0x0, End_B0=27 End_B1=27
7940 10:57:52.845794 28, 0x0, End_B0=28 End_B1=28
7941 10:57:52.849054 29, 0x0, End_B0=29 End_B1=29
7942 10:57:52.849488 30, 0x0, End_B0=30 End_B1=30
7943 10:57:52.852364 31, 0x4141, End_B0=30 End_B1=30
7944 10:57:52.855639 Byte0 end_step=30 best_step=27
7945 10:57:52.858464 Byte1 end_step=30 best_step=27
7946 10:57:52.861390 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 10:57:52.865373 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 10:57:52.865514
7949 10:57:52.865609
7950 10:57:52.871551 [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7951 10:57:52.874679 CH0 RK0: MR19=303, MR18=2520
7952 10:57:52.881559 CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16
7953 10:57:52.881643
7954 10:57:52.885150 ----->DramcWriteLeveling(PI) begin...
7955 10:57:52.885234 ==
7956 10:57:52.888436 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 10:57:52.891312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 10:57:52.891410 ==
7959 10:57:52.894799 Write leveling (Byte 0): 37 => 37
7960 10:57:52.898160 Write leveling (Byte 1): 26 => 26
7961 10:57:52.901388 DramcWriteLeveling(PI) end<-----
7962 10:57:52.901490
7963 10:57:52.901572 ==
7964 10:57:52.904998 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 10:57:52.908279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 10:57:52.908396 ==
7967 10:57:52.911562 [Gating] SW mode calibration
7968 10:57:52.918694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 10:57:52.925038 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 10:57:52.928528 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7971 10:57:52.931733 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7972 10:57:52.938373 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7973 10:57:52.941518 1 4 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 0)
7974 10:57:52.945510 1 4 16 | B1->B0 | 3030 3736 | 1 1 | (1 1) (0 0)
7975 10:57:52.951907 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7976 10:57:52.955477 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 10:57:52.958717 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 10:57:52.965016 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7979 10:57:52.968756 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 10:57:52.971972 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7981 10:57:52.978240 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
7982 10:57:52.981972 1 5 16 | B1->B0 | 2d2d 2727 | 0 0 | (1 1) (1 0)
7983 10:57:52.985152 1 5 20 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7984 10:57:52.991831 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 10:57:52.994866 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7986 10:57:52.998832 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7987 10:57:53.005143 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7988 10:57:53.008268 1 6 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7989 10:57:53.011965 1 6 12 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
7990 10:57:53.018528 1 6 16 | B1->B0 | 3838 4545 | 0 1 | (0 0) (0 0)
7991 10:57:53.021700 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7992 10:57:53.024865 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 10:57:53.028155 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 10:57:53.034791 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 10:57:53.038010 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 10:57:53.041315 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 10:57:53.047943 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7998 10:57:53.051778 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7999 10:57:53.054752 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 10:57:53.061446 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 10:57:53.064679 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 10:57:53.067833 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 10:57:53.074446 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 10:57:53.077695 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:57:53.081324 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:57:53.087780 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 10:57:53.091191 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 10:57:53.094207 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 10:57:53.100884 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 10:57:53.104920 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 10:57:53.107979 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 10:57:53.114029 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8013 10:57:53.117895 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 10:57:53.120994 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 10:57:53.128074 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 10:57:53.128523 Total UI for P1: 0, mck2ui 16
8017 10:57:53.134152 best dqsien dly found for B0: ( 1, 9, 12)
8018 10:57:53.134704 Total UI for P1: 0, mck2ui 16
8019 10:57:53.141287 best dqsien dly found for B1: ( 1, 9, 12)
8020 10:57:53.144714 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8021 10:57:53.147980 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8022 10:57:53.148429
8023 10:57:53.151169 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8024 10:57:53.154502 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8025 10:57:53.157542 [Gating] SW calibration Done
8026 10:57:53.158021 ==
8027 10:57:53.161270 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 10:57:53.164442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 10:57:53.164936 ==
8030 10:57:53.167668 RX Vref Scan: 0
8031 10:57:53.168151
8032 10:57:53.168498 RX Vref 0 -> 0, step: 1
8033 10:57:53.168817
8034 10:57:53.170957 RX Delay 0 -> 252, step: 8
8035 10:57:53.174152 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 10:57:53.180943 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 10:57:53.184118 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 10:57:53.187878 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 10:57:53.191159 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 10:57:53.194190 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 10:57:53.200926 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8042 10:57:53.204545 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8043 10:57:53.207429 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 10:57:53.211026 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 10:57:53.214312 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8046 10:57:53.221353 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8047 10:57:53.224138 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 10:57:53.227398 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8049 10:57:53.230734 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8050 10:57:53.234016 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8051 10:57:53.237237 ==
8052 10:57:53.240671 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 10:57:53.243963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 10:57:53.244453 ==
8055 10:57:53.244804 DQS Delay:
8056 10:57:53.247253 DQS0 = 0, DQS1 = 0
8057 10:57:53.247731 DQM Delay:
8058 10:57:53.250474 DQM0 = 137, DQM1 = 128
8059 10:57:53.250919 DQ Delay:
8060 10:57:53.253869 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 10:57:53.257477 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =147
8062 10:57:53.260732 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8063 10:57:53.263945 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8064 10:57:53.264372
8065 10:57:53.264711
8066 10:57:53.265025 ==
8067 10:57:53.267271 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 10:57:53.273799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 10:57:53.274231 ==
8070 10:57:53.274566
8071 10:57:53.274880
8072 10:57:53.275180 TX Vref Scan disable
8073 10:57:53.277668 == TX Byte 0 ==
8074 10:57:53.280930 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8075 10:57:53.287789 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8076 10:57:53.288309 == TX Byte 1 ==
8077 10:57:53.291019 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8078 10:57:53.297856 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8079 10:57:53.298378 ==
8080 10:57:53.301008 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 10:57:53.304431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 10:57:53.304874 ==
8083 10:57:53.319140
8084 10:57:53.322222 TX Vref early break, caculate TX vref
8085 10:57:53.325419 TX Vref=16, minBit 1, minWin=22, winSum=381
8086 10:57:53.329110 TX Vref=18, minBit 1, minWin=23, winSum=397
8087 10:57:53.332531 TX Vref=20, minBit 0, minWin=24, winSum=405
8088 10:57:53.335308 TX Vref=22, minBit 3, minWin=24, winSum=410
8089 10:57:53.338605 TX Vref=24, minBit 1, minWin=25, winSum=419
8090 10:57:53.345344 TX Vref=26, minBit 1, minWin=25, winSum=423
8091 10:57:53.349018 TX Vref=28, minBit 4, minWin=24, winSum=420
8092 10:57:53.352446 TX Vref=30, minBit 3, minWin=25, winSum=417
8093 10:57:53.355696 TX Vref=32, minBit 4, minWin=24, winSum=409
8094 10:57:53.358910 TX Vref=34, minBit 0, minWin=24, winSum=402
8095 10:57:53.361988 TX Vref=36, minBit 0, minWin=24, winSum=394
8096 10:57:53.368544 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 26
8097 10:57:53.368773
8098 10:57:53.371763 Final TX Range 0 Vref 26
8099 10:57:53.372006
8100 10:57:53.372152 ==
8101 10:57:53.375455 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 10:57:53.378697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 10:57:53.378852 ==
8104 10:57:53.378972
8105 10:57:53.379083
8106 10:57:53.381939 TX Vref Scan disable
8107 10:57:53.388510 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8108 10:57:53.388684 == TX Byte 0 ==
8109 10:57:53.391778 u2DelayCellOfst[0]=10 cells (3 PI)
8110 10:57:53.395076 u2DelayCellOfst[1]=13 cells (4 PI)
8111 10:57:53.398189 u2DelayCellOfst[2]=10 cells (3 PI)
8112 10:57:53.402095 u2DelayCellOfst[3]=10 cells (3 PI)
8113 10:57:53.405095 u2DelayCellOfst[4]=6 cells (2 PI)
8114 10:57:53.408260 u2DelayCellOfst[5]=0 cells (0 PI)
8115 10:57:53.411798 u2DelayCellOfst[6]=13 cells (4 PI)
8116 10:57:53.414803 u2DelayCellOfst[7]=13 cells (4 PI)
8117 10:57:53.418522 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8118 10:57:53.421947 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8119 10:57:53.425037 == TX Byte 1 ==
8120 10:57:53.428039 u2DelayCellOfst[8]=3 cells (1 PI)
8121 10:57:53.432197 u2DelayCellOfst[9]=0 cells (0 PI)
8122 10:57:53.432367 u2DelayCellOfst[10]=10 cells (3 PI)
8123 10:57:53.435409 u2DelayCellOfst[11]=3 cells (1 PI)
8124 10:57:53.438357 u2DelayCellOfst[12]=10 cells (3 PI)
8125 10:57:53.442030 u2DelayCellOfst[13]=13 cells (4 PI)
8126 10:57:53.445083 u2DelayCellOfst[14]=13 cells (4 PI)
8127 10:57:53.448498 u2DelayCellOfst[15]=10 cells (3 PI)
8128 10:57:53.455113 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8129 10:57:53.458367 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8130 10:57:53.458587 DramC Write-DBI on
8131 10:57:53.458710 ==
8132 10:57:53.461505 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 10:57:53.468511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 10:57:53.468687 ==
8135 10:57:53.468825
8136 10:57:53.468952
8137 10:57:53.469074 TX Vref Scan disable
8138 10:57:53.472551 == TX Byte 0 ==
8139 10:57:53.475646 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8140 10:57:53.478911 == TX Byte 1 ==
8141 10:57:53.482319 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8142 10:57:53.486281 DramC Write-DBI off
8143 10:57:53.486680
8144 10:57:53.486991 [DATLAT]
8145 10:57:53.487284 Freq=1600, CH0 RK1
8146 10:57:53.487604
8147 10:57:53.489542 DATLAT Default: 0xf
8148 10:57:53.489928 0, 0xFFFF, sum = 0
8149 10:57:53.492913 1, 0xFFFF, sum = 0
8150 10:57:53.493338 2, 0xFFFF, sum = 0
8151 10:57:53.496241 3, 0xFFFF, sum = 0
8152 10:57:53.499866 4, 0xFFFF, sum = 0
8153 10:57:53.500638 5, 0xFFFF, sum = 0
8154 10:57:53.502670 6, 0xFFFF, sum = 0
8155 10:57:53.503140 7, 0xFFFF, sum = 0
8156 10:57:53.505693 8, 0xFFFF, sum = 0
8157 10:57:53.506123 9, 0xFFFF, sum = 0
8158 10:57:53.509373 10, 0xFFFF, sum = 0
8159 10:57:53.509804 11, 0xFFFF, sum = 0
8160 10:57:53.512332 12, 0xFFFF, sum = 0
8161 10:57:53.512767 13, 0xFFFF, sum = 0
8162 10:57:53.515636 14, 0x0, sum = 1
8163 10:57:53.516066 15, 0x0, sum = 2
8164 10:57:53.519251 16, 0x0, sum = 3
8165 10:57:53.519801 17, 0x0, sum = 4
8166 10:57:53.522151 best_step = 15
8167 10:57:53.522573
8168 10:57:53.522911 ==
8169 10:57:53.526060 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 10:57:53.529119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 10:57:53.529545 ==
8172 10:57:53.532447 RX Vref Scan: 0
8173 10:57:53.532972
8174 10:57:53.533307 RX Vref 0 -> 0, step: 1
8175 10:57:53.533623
8176 10:57:53.535509 RX Delay 19 -> 252, step: 4
8177 10:57:53.539189 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8178 10:57:53.545736 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8179 10:57:53.548689 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8180 10:57:53.551982 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8181 10:57:53.555289 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8182 10:57:53.558631 iDelay=191, Bit 5, Center 126 (71 ~ 182) 112
8183 10:57:53.565191 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8184 10:57:53.568639 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8185 10:57:53.571826 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8186 10:57:53.575025 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8187 10:57:53.579092 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8188 10:57:53.585454 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8189 10:57:53.588668 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8190 10:57:53.591832 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8191 10:57:53.595024 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8192 10:57:53.601571 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8193 10:57:53.601997 ==
8194 10:57:53.605597 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 10:57:53.608708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 10:57:53.609136 ==
8197 10:57:53.609474 DQS Delay:
8198 10:57:53.612078 DQS0 = 0, DQS1 = 0
8199 10:57:53.612506 DQM Delay:
8200 10:57:53.615167 DQM0 = 134, DQM1 = 127
8201 10:57:53.615717 DQ Delay:
8202 10:57:53.618245 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8203 10:57:53.621911 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8204 10:57:53.625076 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8205 10:57:53.628623 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8206 10:57:53.629074
8207 10:57:53.629414
8208 10:57:53.629728
8209 10:57:53.631634 [DramC_TX_OE_Calibration] TA2
8210 10:57:53.635026 Original DQ_B0 (3 6) =30, OEN = 27
8211 10:57:53.638513 Original DQ_B1 (3 6) =30, OEN = 27
8212 10:57:53.641697 24, 0x0, End_B0=24 End_B1=24
8213 10:57:53.645417 25, 0x0, End_B0=25 End_B1=25
8214 10:57:53.645850 26, 0x0, End_B0=26 End_B1=26
8215 10:57:53.648488 27, 0x0, End_B0=27 End_B1=27
8216 10:57:53.651184 28, 0x0, End_B0=28 End_B1=28
8217 10:57:53.654868 29, 0x0, End_B0=29 End_B1=29
8218 10:57:53.658003 30, 0x0, End_B0=30 End_B1=30
8219 10:57:53.658088 31, 0x4141, End_B0=30 End_B1=30
8220 10:57:53.661303 Byte0 end_step=30 best_step=27
8221 10:57:53.664721 Byte1 end_step=30 best_step=27
8222 10:57:53.668097 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 10:57:53.671474 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 10:57:53.671556
8225 10:57:53.671626
8226 10:57:53.677863 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8227 10:57:53.681062 CH0 RK1: MR19=303, MR18=2109
8228 10:57:53.687516 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8229 10:57:53.691256 [RxdqsGatingPostProcess] freq 1600
8230 10:57:53.697666 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 10:57:53.697749 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 10:57:53.701119 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 10:57:53.704527 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 10:57:53.707600 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 10:57:53.711455 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 10:57:53.714547 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 10:57:53.718026 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 10:57:53.721246 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 10:57:53.724466 Pre-setting of DQS Precalculation
8240 10:57:53.728150 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 10:57:53.728234 ==
8242 10:57:53.731239 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 10:57:53.738115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 10:57:53.738200 ==
8245 10:57:53.741006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 10:57:53.747489 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 10:57:53.750979 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 10:57:53.757601 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 10:57:53.764999 [CA 0] Center 42 (13~71) winsize 59
8250 10:57:53.768995 [CA 1] Center 42 (13~72) winsize 60
8251 10:57:53.772442 [CA 2] Center 39 (10~68) winsize 59
8252 10:57:53.774949 [CA 3] Center 39 (10~68) winsize 59
8253 10:57:53.778394 [CA 4] Center 39 (10~68) winsize 59
8254 10:57:53.781576 [CA 5] Center 37 (8~67) winsize 60
8255 10:57:53.781662
8256 10:57:53.784814 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8257 10:57:53.784899
8258 10:57:53.792076 [CATrainingPosCal] consider 1 rank data
8259 10:57:53.792156 u2DelayCellTimex100 = 285/100 ps
8260 10:57:53.798314 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8261 10:57:53.801578 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8262 10:57:53.804907 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8263 10:57:53.808792 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8264 10:57:53.811981 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8265 10:57:53.815268 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8266 10:57:53.815466
8267 10:57:53.818607 CA PerBit enable=1, Macro0, CA PI delay=37
8268 10:57:53.818706
8269 10:57:53.821990 [CBTSetCACLKResult] CA Dly = 37
8270 10:57:53.825297 CS Dly: 10 (0~41)
8271 10:57:53.828496 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 10:57:53.831671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 10:57:53.831826 ==
8274 10:57:53.834908 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 10:57:53.841832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 10:57:53.841994 ==
8277 10:57:53.844896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 10:57:53.851617 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 10:57:53.856201 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 10:57:53.861835 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 10:57:53.869353 [CA 0] Center 42 (13~72) winsize 60
8282 10:57:53.872429 [CA 1] Center 41 (12~71) winsize 60
8283 10:57:53.875678 [CA 2] Center 38 (9~68) winsize 60
8284 10:57:53.878849 [CA 3] Center 37 (8~67) winsize 60
8285 10:57:53.882089 [CA 4] Center 38 (8~68) winsize 61
8286 10:57:53.885930 [CA 5] Center 37 (8~67) winsize 60
8287 10:57:53.886027
8288 10:57:53.889208 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 10:57:53.889316
8290 10:57:53.892550 [CATrainingPosCal] consider 2 rank data
8291 10:57:53.896051 u2DelayCellTimex100 = 285/100 ps
8292 10:57:53.899356 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8293 10:57:53.905645 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8294 10:57:53.908864 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8295 10:57:53.912048 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8296 10:57:53.915975 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8297 10:57:53.919065 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8298 10:57:53.919206
8299 10:57:53.922368 CA PerBit enable=1, Macro0, CA PI delay=37
8300 10:57:53.922584
8301 10:57:53.925577 [CBTSetCACLKResult] CA Dly = 37
8302 10:57:53.929008 CS Dly: 11 (0~44)
8303 10:57:53.932182 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 10:57:53.935309 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 10:57:53.935503
8306 10:57:53.939156 ----->DramcWriteLeveling(PI) begin...
8307 10:57:53.939422 ==
8308 10:57:53.942349 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 10:57:53.948715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 10:57:53.948979 ==
8311 10:57:53.951742 Write leveling (Byte 0): 25 => 25
8312 10:57:53.951958 Write leveling (Byte 1): 28 => 28
8313 10:57:53.955493 DramcWriteLeveling(PI) end<-----
8314 10:57:53.955634
8315 10:57:53.958589 ==
8316 10:57:53.958671 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 10:57:53.965502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 10:57:53.965585 ==
8319 10:57:53.968520 [Gating] SW mode calibration
8320 10:57:53.975379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 10:57:53.978527 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 10:57:53.984952 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 10:57:53.988083 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 10:57:53.991385 1 4 8 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
8325 10:57:53.998635 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8326 10:57:54.002036 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 10:57:54.004718 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 10:57:54.011716 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 10:57:54.015060 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 10:57:54.017893 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 10:57:54.025155 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 10:57:54.028559 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
8333 10:57:54.032008 1 5 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8334 10:57:54.038471 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 10:57:54.041636 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 10:57:54.044913 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 10:57:54.051487 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 10:57:54.054640 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 10:57:54.058379 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 10:57:54.064943 1 6 8 | B1->B0 | 2424 4141 | 0 1 | (0 0) (0 0)
8341 10:57:54.068207 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 10:57:54.071089 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 10:57:54.077793 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 10:57:54.080941 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 10:57:54.084697 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 10:57:54.088058 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 10:57:54.094594 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 10:57:54.097775 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8349 10:57:54.101047 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 10:57:54.107768 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8351 10:57:54.110974 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 10:57:54.114931 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 10:57:54.121191 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 10:57:54.124430 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:57:54.127521 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:57:54.134537 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:57:54.137949 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:57:54.141092 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 10:57:54.147656 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 10:57:54.150880 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 10:57:54.154122 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 10:57:54.160570 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 10:57:54.164323 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 10:57:54.167379 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 10:57:54.174221 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 10:57:54.177199 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 10:57:54.181093 Total UI for P1: 0, mck2ui 16
8368 10:57:54.184280 best dqsien dly found for B0: ( 1, 9, 10)
8369 10:57:54.187601 Total UI for P1: 0, mck2ui 16
8370 10:57:54.190578 best dqsien dly found for B1: ( 1, 9, 10)
8371 10:57:54.194341 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8372 10:57:54.197442 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8373 10:57:54.197525
8374 10:57:54.200675 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 10:57:54.204034 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 10:57:54.206778 [Gating] SW calibration Done
8377 10:57:54.206889 ==
8378 10:57:54.210630 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 10:57:54.217274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 10:57:54.217361 ==
8381 10:57:54.217427 RX Vref Scan: 0
8382 10:57:54.217491
8383 10:57:54.220529 RX Vref 0 -> 0, step: 1
8384 10:57:54.220681
8385 10:57:54.223669 RX Delay 0 -> 252, step: 8
8386 10:57:54.227286 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8387 10:57:54.230444 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8388 10:57:54.233565 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8389 10:57:54.236954 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8390 10:57:54.243578 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8391 10:57:54.246838 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8392 10:57:54.249940 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 10:57:54.253178 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8394 10:57:54.256986 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8395 10:57:54.263014 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8396 10:57:54.266344 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 10:57:54.270057 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8398 10:57:54.273275 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 10:57:54.276875 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8400 10:57:54.283315 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 10:57:54.286569 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8402 10:57:54.286652 ==
8403 10:57:54.289655 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 10:57:54.293434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 10:57:54.293520 ==
8406 10:57:54.296506 DQS Delay:
8407 10:57:54.296590 DQS0 = 0, DQS1 = 0
8408 10:57:54.296656 DQM Delay:
8409 10:57:54.299570 DQM0 = 136, DQM1 = 132
8410 10:57:54.299653 DQ Delay:
8411 10:57:54.302961 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8412 10:57:54.306846 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8413 10:57:54.310039 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8414 10:57:54.316560 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8415 10:57:54.316644
8416 10:57:54.316710
8417 10:57:54.316771 ==
8418 10:57:54.319876 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 10:57:54.323097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 10:57:54.323181 ==
8421 10:57:54.323247
8422 10:57:54.323308
8423 10:57:54.326249 TX Vref Scan disable
8424 10:57:54.326332 == TX Byte 0 ==
8425 10:57:54.333440 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 10:57:54.336506 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 10:57:54.336590 == TX Byte 1 ==
8428 10:57:54.342966 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8429 10:57:54.346236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8430 10:57:54.346318 ==
8431 10:57:54.349640 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 10:57:54.352772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 10:57:54.352860 ==
8434 10:57:54.367032
8435 10:57:54.370380 TX Vref early break, caculate TX vref
8436 10:57:54.373573 TX Vref=16, minBit 0, minWin=22, winSum=368
8437 10:57:54.376480 TX Vref=18, minBit 0, minWin=23, winSum=381
8438 10:57:54.380137 TX Vref=20, minBit 1, minWin=23, winSum=388
8439 10:57:54.383417 TX Vref=22, minBit 4, minWin=24, winSum=400
8440 10:57:54.386768 TX Vref=24, minBit 0, minWin=24, winSum=414
8441 10:57:54.393358 TX Vref=26, minBit 0, minWin=25, winSum=415
8442 10:57:54.396992 TX Vref=28, minBit 0, minWin=25, winSum=416
8443 10:57:54.400364 TX Vref=30, minBit 2, minWin=25, winSum=419
8444 10:57:54.403805 TX Vref=32, minBit 0, minWin=24, winSum=404
8445 10:57:54.407093 TX Vref=34, minBit 0, minWin=23, winSum=395
8446 10:57:54.413617 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 30
8447 10:57:54.414203
8448 10:57:54.416809 Final TX Range 0 Vref 30
8449 10:57:54.417234
8450 10:57:54.417567 ==
8451 10:57:54.420102 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 10:57:54.423303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 10:57:54.423759 ==
8454 10:57:54.424099
8455 10:57:54.424435
8456 10:57:54.426667 TX Vref Scan disable
8457 10:57:54.433629 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8458 10:57:54.434213 == TX Byte 0 ==
8459 10:57:54.436691 u2DelayCellOfst[0]=20 cells (6 PI)
8460 10:57:54.439952 u2DelayCellOfst[1]=13 cells (4 PI)
8461 10:57:54.443822 u2DelayCellOfst[2]=0 cells (0 PI)
8462 10:57:54.446909 u2DelayCellOfst[3]=6 cells (2 PI)
8463 10:57:54.450327 u2DelayCellOfst[4]=10 cells (3 PI)
8464 10:57:54.453593 u2DelayCellOfst[5]=17 cells (5 PI)
8465 10:57:54.456981 u2DelayCellOfst[6]=20 cells (6 PI)
8466 10:57:54.457408 u2DelayCellOfst[7]=6 cells (2 PI)
8467 10:57:54.463845 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8468 10:57:54.467228 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 10:57:54.467881 == TX Byte 1 ==
8470 10:57:54.470509 u2DelayCellOfst[8]=0 cells (0 PI)
8471 10:57:54.474003 u2DelayCellOfst[9]=3 cells (1 PI)
8472 10:57:54.477066 u2DelayCellOfst[10]=10 cells (3 PI)
8473 10:57:54.480565 u2DelayCellOfst[11]=6 cells (2 PI)
8474 10:57:54.483303 u2DelayCellOfst[12]=13 cells (4 PI)
8475 10:57:54.486927 u2DelayCellOfst[13]=17 cells (5 PI)
8476 10:57:54.489955 u2DelayCellOfst[14]=20 cells (6 PI)
8477 10:57:54.493666 u2DelayCellOfst[15]=17 cells (5 PI)
8478 10:57:54.497330 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8479 10:57:54.503564 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8480 10:57:54.504146 DramC Write-DBI on
8481 10:57:54.504629 ==
8482 10:57:54.506840 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 10:57:54.509997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 10:57:54.513155 ==
8485 10:57:54.513726
8486 10:57:54.514078
8487 10:57:54.514395 TX Vref Scan disable
8488 10:57:54.516269 == TX Byte 0 ==
8489 10:57:54.520202 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8490 10:57:54.523833 == TX Byte 1 ==
8491 10:57:54.526804 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8492 10:57:54.529838 DramC Write-DBI off
8493 10:57:54.530322
8494 10:57:54.530816 [DATLAT]
8495 10:57:54.531230 Freq=1600, CH1 RK0
8496 10:57:54.531676
8497 10:57:54.533397 DATLAT Default: 0xf
8498 10:57:54.534002 0, 0xFFFF, sum = 0
8499 10:57:54.536530 1, 0xFFFF, sum = 0
8500 10:57:54.537000 2, 0xFFFF, sum = 0
8501 10:57:54.539818 3, 0xFFFF, sum = 0
8502 10:57:54.542974 4, 0xFFFF, sum = 0
8503 10:57:54.543435 5, 0xFFFF, sum = 0
8504 10:57:54.546159 6, 0xFFFF, sum = 0
8505 10:57:54.546584 7, 0xFFFF, sum = 0
8506 10:57:54.549981 8, 0xFFFF, sum = 0
8507 10:57:54.550405 9, 0xFFFF, sum = 0
8508 10:57:54.553266 10, 0xFFFF, sum = 0
8509 10:57:54.553693 11, 0xFFFF, sum = 0
8510 10:57:54.556467 12, 0xFFFF, sum = 0
8511 10:57:54.556893 13, 0xFFFF, sum = 0
8512 10:57:54.559833 14, 0x0, sum = 1
8513 10:57:54.560255 15, 0x0, sum = 2
8514 10:57:54.563104 16, 0x0, sum = 3
8515 10:57:54.563597 17, 0x0, sum = 4
8516 10:57:54.566211 best_step = 15
8517 10:57:54.566626
8518 10:57:54.566953 ==
8519 10:57:54.569760 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 10:57:54.572990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 10:57:54.573412 ==
8522 10:57:54.573742 RX Vref Scan: 1
8523 10:57:54.576389
8524 10:57:54.576804 Set Vref Range= 24 -> 127
8525 10:57:54.577133
8526 10:57:54.579552 RX Vref 24 -> 127, step: 1
8527 10:57:54.579970
8528 10:57:54.582857 RX Delay 27 -> 252, step: 4
8529 10:57:54.583276
8530 10:57:54.586396 Set Vref, RX VrefLevel [Byte0]: 24
8531 10:57:54.589538 [Byte1]: 24
8532 10:57:54.589956
8533 10:57:54.592676 Set Vref, RX VrefLevel [Byte0]: 25
8534 10:57:54.596519 [Byte1]: 25
8535 10:57:54.596937
8536 10:57:54.599783 Set Vref, RX VrefLevel [Byte0]: 26
8537 10:57:54.602815 [Byte1]: 26
8538 10:57:54.607011
8539 10:57:54.607587 Set Vref, RX VrefLevel [Byte0]: 27
8540 10:57:54.609948 [Byte1]: 27
8541 10:57:54.614376
8542 10:57:54.614794 Set Vref, RX VrefLevel [Byte0]: 28
8543 10:57:54.617746 [Byte1]: 28
8544 10:57:54.621935
8545 10:57:54.622459 Set Vref, RX VrefLevel [Byte0]: 29
8546 10:57:54.624992 [Byte1]: 29
8547 10:57:54.629706
8548 10:57:54.630221 Set Vref, RX VrefLevel [Byte0]: 30
8549 10:57:54.632603 [Byte1]: 30
8550 10:57:54.636876
8551 10:57:54.637395 Set Vref, RX VrefLevel [Byte0]: 31
8552 10:57:54.639986 [Byte1]: 31
8553 10:57:54.644015
8554 10:57:54.644434 Set Vref, RX VrefLevel [Byte0]: 32
8555 10:57:54.647271 [Byte1]: 32
8556 10:57:54.651718
8557 10:57:54.652166 Set Vref, RX VrefLevel [Byte0]: 33
8558 10:57:54.655025 [Byte1]: 33
8559 10:57:54.659466
8560 10:57:54.659887 Set Vref, RX VrefLevel [Byte0]: 34
8561 10:57:54.662462 [Byte1]: 34
8562 10:57:54.667027
8563 10:57:54.667491 Set Vref, RX VrefLevel [Byte0]: 35
8564 10:57:54.670503 [Byte1]: 35
8565 10:57:54.674959
8566 10:57:54.675424 Set Vref, RX VrefLevel [Byte0]: 36
8567 10:57:54.677733 [Byte1]: 36
8568 10:57:54.682305
8569 10:57:54.682853 Set Vref, RX VrefLevel [Byte0]: 37
8570 10:57:54.685599 [Byte1]: 37
8571 10:57:54.689343
8572 10:57:54.689907 Set Vref, RX VrefLevel [Byte0]: 38
8573 10:57:54.692731 [Byte1]: 38
8574 10:57:54.696980
8575 10:57:54.697424 Set Vref, RX VrefLevel [Byte0]: 39
8576 10:57:54.700214 [Byte1]: 39
8577 10:57:54.704366
8578 10:57:54.704882 Set Vref, RX VrefLevel [Byte0]: 40
8579 10:57:54.708076 [Byte1]: 40
8580 10:57:54.712349
8581 10:57:54.712765 Set Vref, RX VrefLevel [Byte0]: 41
8582 10:57:54.715477 [Byte1]: 41
8583 10:57:54.719783
8584 10:57:54.720268 Set Vref, RX VrefLevel [Byte0]: 42
8585 10:57:54.722821 [Byte1]: 42
8586 10:57:54.727300
8587 10:57:54.727757 Set Vref, RX VrefLevel [Byte0]: 43
8588 10:57:54.730503 [Byte1]: 43
8589 10:57:54.734984
8590 10:57:54.735524 Set Vref, RX VrefLevel [Byte0]: 44
8591 10:57:54.738035 [Byte1]: 44
8592 10:57:54.742055
8593 10:57:54.742525 Set Vref, RX VrefLevel [Byte0]: 45
8594 10:57:54.745247 [Byte1]: 45
8595 10:57:54.749960
8596 10:57:54.750376 Set Vref, RX VrefLevel [Byte0]: 46
8597 10:57:54.753146 [Byte1]: 46
8598 10:57:54.757478
8599 10:57:54.757896 Set Vref, RX VrefLevel [Byte0]: 47
8600 10:57:54.760625 [Byte1]: 47
8601 10:57:54.765165
8602 10:57:54.765580 Set Vref, RX VrefLevel [Byte0]: 48
8603 10:57:54.768248 [Byte1]: 48
8604 10:57:54.772612
8605 10:57:54.773039 Set Vref, RX VrefLevel [Byte0]: 49
8606 10:57:54.775252 [Byte1]: 49
8607 10:57:54.779774
8608 10:57:54.780250 Set Vref, RX VrefLevel [Byte0]: 50
8609 10:57:54.782965 [Byte1]: 50
8610 10:57:54.787867
8611 10:57:54.788448 Set Vref, RX VrefLevel [Byte0]: 51
8612 10:57:54.790840 [Byte1]: 51
8613 10:57:54.794760
8614 10:57:54.795187 Set Vref, RX VrefLevel [Byte0]: 52
8615 10:57:54.798073 [Byte1]: 52
8616 10:57:54.802452
8617 10:57:54.802876 Set Vref, RX VrefLevel [Byte0]: 53
8618 10:57:54.805770 [Byte1]: 53
8619 10:57:54.809678
8620 10:57:54.810101 Set Vref, RX VrefLevel [Byte0]: 54
8621 10:57:54.813590 [Byte1]: 54
8622 10:57:54.817889
8623 10:57:54.818402 Set Vref, RX VrefLevel [Byte0]: 55
8624 10:57:54.821055 [Byte1]: 55
8625 10:57:54.825099
8626 10:57:54.825566 Set Vref, RX VrefLevel [Byte0]: 56
8627 10:57:54.828215 [Byte1]: 56
8628 10:57:54.832599
8629 10:57:54.833025 Set Vref, RX VrefLevel [Byte0]: 57
8630 10:57:54.835762 [Byte1]: 57
8631 10:57:54.840017
8632 10:57:54.840443 Set Vref, RX VrefLevel [Byte0]: 58
8633 10:57:54.843141 [Byte1]: 58
8634 10:57:54.847975
8635 10:57:54.848495 Set Vref, RX VrefLevel [Byte0]: 59
8636 10:57:54.851236 [Byte1]: 59
8637 10:57:54.855066
8638 10:57:54.855528 Set Vref, RX VrefLevel [Byte0]: 60
8639 10:57:54.858248 [Byte1]: 60
8640 10:57:54.862804
8641 10:57:54.863237 Set Vref, RX VrefLevel [Byte0]: 61
8642 10:57:54.866127 [Byte1]: 61
8643 10:57:54.870527
8644 10:57:54.870952 Set Vref, RX VrefLevel [Byte0]: 62
8645 10:57:54.873609 [Byte1]: 62
8646 10:57:54.877850
8647 10:57:54.878278 Set Vref, RX VrefLevel [Byte0]: 63
8648 10:57:54.881131 [Byte1]: 63
8649 10:57:54.885604
8650 10:57:54.886034 Set Vref, RX VrefLevel [Byte0]: 64
8651 10:57:54.888843 [Byte1]: 64
8652 10:57:54.892586
8653 10:57:54.892891 Set Vref, RX VrefLevel [Byte0]: 65
8654 10:57:54.895758 [Byte1]: 65
8655 10:57:54.900385
8656 10:57:54.900613 Set Vref, RX VrefLevel [Byte0]: 66
8657 10:57:54.903543 [Byte1]: 66
8658 10:57:54.907844
8659 10:57:54.908038 Set Vref, RX VrefLevel [Byte0]: 67
8660 10:57:54.910989 [Byte1]: 67
8661 10:57:54.914995
8662 10:57:54.915152 Set Vref, RX VrefLevel [Byte0]: 68
8663 10:57:54.918181 [Byte1]: 68
8664 10:57:54.922517
8665 10:57:54.922619 Set Vref, RX VrefLevel [Byte0]: 69
8666 10:57:54.926174 [Byte1]: 69
8667 10:57:54.930034
8668 10:57:54.930214 Set Vref, RX VrefLevel [Byte0]: 70
8669 10:57:54.933746 [Byte1]: 70
8670 10:57:54.937521
8671 10:57:54.937713 Set Vref, RX VrefLevel [Byte0]: 71
8672 10:57:54.941419 [Byte1]: 71
8673 10:57:54.945218
8674 10:57:54.945322 Set Vref, RX VrefLevel [Byte0]: 72
8675 10:57:54.948321 [Byte1]: 72
8676 10:57:54.952716
8677 10:57:54.952832 Set Vref, RX VrefLevel [Byte0]: 73
8678 10:57:54.956380 [Byte1]: 73
8679 10:57:54.960452
8680 10:57:54.960916 Set Vref, RX VrefLevel [Byte0]: 74
8681 10:57:54.963620 [Byte1]: 74
8682 10:57:54.968297
8683 10:57:54.968815 Set Vref, RX VrefLevel [Byte0]: 75
8684 10:57:54.971581 [Byte1]: 75
8685 10:57:54.975785
8686 10:57:54.976297 Set Vref, RX VrefLevel [Byte0]: 76
8687 10:57:54.978865 [Byte1]: 76
8688 10:57:54.983456
8689 10:57:54.983874 Set Vref, RX VrefLevel [Byte0]: 77
8690 10:57:54.986699 [Byte1]: 77
8691 10:57:54.990407
8692 10:57:54.990829 Set Vref, RX VrefLevel [Byte0]: 78
8693 10:57:54.993863 [Byte1]: 78
8694 10:57:54.998375
8695 10:57:54.998795 Final RX Vref Byte 0 = 58 to rank0
8696 10:57:55.001947 Final RX Vref Byte 1 = 57 to rank0
8697 10:57:55.004998 Final RX Vref Byte 0 = 58 to rank1
8698 10:57:55.008217 Final RX Vref Byte 1 = 57 to rank1==
8699 10:57:55.012175 Dram Type= 6, Freq= 0, CH_1, rank 0
8700 10:57:55.018491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8701 10:57:55.018982 ==
8702 10:57:55.019321 DQS Delay:
8703 10:57:55.019701 DQS0 = 0, DQS1 = 0
8704 10:57:55.021538 DQM Delay:
8705 10:57:55.021959 DQM0 = 134, DQM1 = 131
8706 10:57:55.024721 DQ Delay:
8707 10:57:55.028391 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8708 10:57:55.031399 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8709 10:57:55.035129 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8710 10:57:55.038247 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8711 10:57:55.038680
8712 10:57:55.039008
8713 10:57:55.039311
8714 10:57:55.041379 [DramC_TX_OE_Calibration] TA2
8715 10:57:55.045087 Original DQ_B0 (3 6) =30, OEN = 27
8716 10:57:55.048096 Original DQ_B1 (3 6) =30, OEN = 27
8717 10:57:55.051392 24, 0x0, End_B0=24 End_B1=24
8718 10:57:55.051816 25, 0x0, End_B0=25 End_B1=25
8719 10:57:55.055062 26, 0x0, End_B0=26 End_B1=26
8720 10:57:55.058617 27, 0x0, End_B0=27 End_B1=27
8721 10:57:55.062041 28, 0x0, End_B0=28 End_B1=28
8722 10:57:55.062573 29, 0x0, End_B0=29 End_B1=29
8723 10:57:55.065158 30, 0x0, End_B0=30 End_B1=30
8724 10:57:55.068301 31, 0x4141, End_B0=30 End_B1=30
8725 10:57:55.071832 Byte0 end_step=30 best_step=27
8726 10:57:55.074942 Byte1 end_step=30 best_step=27
8727 10:57:55.078032 Byte0 TX OE(2T, 0.5T) = (3, 3)
8728 10:57:55.078405 Byte1 TX OE(2T, 0.5T) = (3, 3)
8729 10:57:55.081391
8730 10:57:55.081991
8731 10:57:55.087511 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8732 10:57:55.090879 CH1 RK0: MR19=303, MR18=1623
8733 10:57:55.097848 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8734 10:57:55.098271
8735 10:57:55.101077 ----->DramcWriteLeveling(PI) begin...
8736 10:57:55.101505 ==
8737 10:57:55.104456 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 10:57:55.107628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 10:57:55.108068 ==
8740 10:57:55.110874 Write leveling (Byte 0): 26 => 26
8741 10:57:55.114732 Write leveling (Byte 1): 28 => 28
8742 10:57:55.118100 DramcWriteLeveling(PI) end<-----
8743 10:57:55.118629
8744 10:57:55.118972 ==
8745 10:57:55.121003 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 10:57:55.124390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 10:57:55.124853 ==
8748 10:57:55.127633 [Gating] SW mode calibration
8749 10:57:55.134521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8750 10:57:55.140609 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8751 10:57:55.144422 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 10:57:55.147483 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 10:57:55.154231 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8754 10:57:55.157377 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
8755 10:57:55.160968 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 10:57:55.167450 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 10:57:55.170892 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 10:57:55.174124 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 10:57:55.180507 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 10:57:55.184223 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8761 10:57:55.187739 1 5 8 | B1->B0 | 2d2d 3434 | 0 1 | (1 0) (1 0)
8762 10:57:55.194004 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8763 10:57:55.198145 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8764 10:57:55.201323 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 10:57:55.207997 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 10:57:55.211311 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 10:57:55.214372 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 10:57:55.220938 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8769 10:57:55.224172 1 6 8 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8770 10:57:55.227407 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 10:57:55.234051 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 10:57:55.236675 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 10:57:55.240342 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 10:57:55.246943 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 10:57:55.250202 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 10:57:55.253868 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 10:57:55.260553 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 10:57:55.263694 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8779 10:57:55.266889 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8780 10:57:55.273877 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 10:57:55.277068 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 10:57:55.280396 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 10:57:55.283714 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 10:57:55.290642 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 10:57:55.293549 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 10:57:55.297042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 10:57:55.303882 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 10:57:55.307524 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 10:57:55.310773 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 10:57:55.316983 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 10:57:55.320304 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 10:57:55.323680 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8793 10:57:55.330486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8794 10:57:55.333849 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8795 10:57:55.337132 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 10:57:55.340393 Total UI for P1: 0, mck2ui 16
8797 10:57:55.343365 best dqsien dly found for B0: ( 1, 9, 10)
8798 10:57:55.346985 Total UI for P1: 0, mck2ui 16
8799 10:57:55.350177 best dqsien dly found for B1: ( 1, 9, 8)
8800 10:57:55.353768 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8801 10:57:55.356779 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8802 10:57:55.357202
8803 10:57:55.363513 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8804 10:57:55.366519 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8805 10:57:55.367109 [Gating] SW calibration Done
8806 10:57:55.370141 ==
8807 10:57:55.373221 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 10:57:55.376493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 10:57:55.376940 ==
8810 10:57:55.377285 RX Vref Scan: 0
8811 10:57:55.377605
8812 10:57:55.380278 RX Vref 0 -> 0, step: 1
8813 10:57:55.380701
8814 10:57:55.383520 RX Delay 0 -> 252, step: 8
8815 10:57:55.386889 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8816 10:57:55.390194 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8817 10:57:55.393509 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8818 10:57:55.399943 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8819 10:57:55.403157 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8820 10:57:55.406924 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8821 10:57:55.410247 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8822 10:57:55.413564 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8823 10:57:55.419779 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8824 10:57:55.423741 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8825 10:57:55.427241 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8826 10:57:55.430273 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8827 10:57:55.433528 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8828 10:57:55.440106 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8829 10:57:55.443411 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8830 10:57:55.446674 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8831 10:57:55.447104 ==
8832 10:57:55.449952 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 10:57:55.453605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 10:57:55.454046 ==
8835 10:57:55.456721 DQS Delay:
8836 10:57:55.457145 DQS0 = 0, DQS1 = 0
8837 10:57:55.459798 DQM Delay:
8838 10:57:55.460238 DQM0 = 136, DQM1 = 133
8839 10:57:55.463532 DQ Delay:
8840 10:57:55.466541 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8841 10:57:55.469626 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8842 10:57:55.473353 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8843 10:57:55.476715 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8844 10:57:55.477141
8845 10:57:55.477474
8846 10:57:55.477782 ==
8847 10:57:55.479582 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 10:57:55.483480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 10:57:55.483905 ==
8850 10:57:55.484241
8851 10:57:55.484554
8852 10:57:55.486568 TX Vref Scan disable
8853 10:57:55.489803 == TX Byte 0 ==
8854 10:57:55.492995 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8855 10:57:55.496420 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8856 10:57:55.499863 == TX Byte 1 ==
8857 10:57:55.502985 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8858 10:57:55.506280 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8859 10:57:55.506703 ==
8860 10:57:55.509412 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 10:57:55.516542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 10:57:55.516966 ==
8863 10:57:55.528498
8864 10:57:55.531962 TX Vref early break, caculate TX vref
8865 10:57:55.534935 TX Vref=16, minBit 1, minWin=22, winSum=378
8866 10:57:55.538691 TX Vref=18, minBit 0, minWin=23, winSum=388
8867 10:57:55.542029 TX Vref=20, minBit 0, minWin=24, winSum=396
8868 10:57:55.544626 TX Vref=22, minBit 1, minWin=24, winSum=408
8869 10:57:55.548101 TX Vref=24, minBit 1, minWin=24, winSum=409
8870 10:57:55.554630 TX Vref=26, minBit 1, minWin=25, winSum=422
8871 10:57:55.558235 TX Vref=28, minBit 0, minWin=26, winSum=423
8872 10:57:55.561468 TX Vref=30, minBit 0, minWin=25, winSum=421
8873 10:57:55.565147 TX Vref=32, minBit 0, minWin=25, winSum=411
8874 10:57:55.568286 TX Vref=34, minBit 0, minWin=23, winSum=403
8875 10:57:55.571333 TX Vref=36, minBit 1, minWin=23, winSum=393
8876 10:57:55.578218 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8877 10:57:55.578301
8878 10:57:55.581352 Final TX Range 0 Vref 28
8879 10:57:55.581441
8880 10:57:55.581509 ==
8881 10:57:55.585121 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 10:57:55.588270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 10:57:55.588369 ==
8884 10:57:55.588467
8885 10:57:55.588559
8886 10:57:55.591493 TX Vref Scan disable
8887 10:57:55.598605 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8888 10:57:55.598796 == TX Byte 0 ==
8889 10:57:55.601857 u2DelayCellOfst[0]=17 cells (5 PI)
8890 10:57:55.605310 u2DelayCellOfst[1]=13 cells (4 PI)
8891 10:57:55.608378 u2DelayCellOfst[2]=0 cells (0 PI)
8892 10:57:55.611634 u2DelayCellOfst[3]=6 cells (2 PI)
8893 10:57:55.615149 u2DelayCellOfst[4]=10 cells (3 PI)
8894 10:57:55.618116 u2DelayCellOfst[5]=20 cells (6 PI)
8895 10:57:55.621828 u2DelayCellOfst[6]=20 cells (6 PI)
8896 10:57:55.625122 u2DelayCellOfst[7]=6 cells (2 PI)
8897 10:57:55.628467 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 10:57:55.631820 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 10:57:55.635207 == TX Byte 1 ==
8900 10:57:55.635801 u2DelayCellOfst[8]=0 cells (0 PI)
8901 10:57:55.638310 u2DelayCellOfst[9]=3 cells (1 PI)
8902 10:57:55.641906 u2DelayCellOfst[10]=10 cells (3 PI)
8903 10:57:55.645286 u2DelayCellOfst[11]=3 cells (1 PI)
8904 10:57:55.648413 u2DelayCellOfst[12]=13 cells (4 PI)
8905 10:57:55.651708 u2DelayCellOfst[13]=13 cells (4 PI)
8906 10:57:55.655030 u2DelayCellOfst[14]=17 cells (5 PI)
8907 10:57:55.658362 u2DelayCellOfst[15]=17 cells (5 PI)
8908 10:57:55.661584 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8909 10:57:55.668359 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8910 10:57:55.668802 DramC Write-DBI on
8911 10:57:55.669300 ==
8912 10:57:55.671861 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 10:57:55.675133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 10:57:55.678122 ==
8915 10:57:55.678558
8916 10:57:55.678995
8917 10:57:55.679588 TX Vref Scan disable
8918 10:57:55.681797 == TX Byte 0 ==
8919 10:57:55.684988 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8920 10:57:55.688626 == TX Byte 1 ==
8921 10:57:55.691671 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 10:57:55.692110 DramC Write-DBI off
8923 10:57:55.695434
8924 10:57:55.695869 [DATLAT]
8925 10:57:55.696308 Freq=1600, CH1 RK1
8926 10:57:55.696721
8927 10:57:55.698376 DATLAT Default: 0xf
8928 10:57:55.698866 0, 0xFFFF, sum = 0
8929 10:57:55.701612 1, 0xFFFF, sum = 0
8930 10:57:55.702090 2, 0xFFFF, sum = 0
8931 10:57:55.704889 3, 0xFFFF, sum = 0
8932 10:57:55.708766 4, 0xFFFF, sum = 0
8933 10:57:55.709209 5, 0xFFFF, sum = 0
8934 10:57:55.712076 6, 0xFFFF, sum = 0
8935 10:57:55.712523 7, 0xFFFF, sum = 0
8936 10:57:55.715430 8, 0xFFFF, sum = 0
8937 10:57:55.715874 9, 0xFFFF, sum = 0
8938 10:57:55.718567 10, 0xFFFF, sum = 0
8939 10:57:55.719013 11, 0xFFFF, sum = 0
8940 10:57:55.721840 12, 0xFFFF, sum = 0
8941 10:57:55.722418 13, 0xFFFF, sum = 0
8942 10:57:55.724984 14, 0x0, sum = 1
8943 10:57:55.725428 15, 0x0, sum = 2
8944 10:57:55.728668 16, 0x0, sum = 3
8945 10:57:55.729101 17, 0x0, sum = 4
8946 10:57:55.731883 best_step = 15
8947 10:57:55.732308
8948 10:57:55.732641 ==
8949 10:57:55.735213 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 10:57:55.738711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 10:57:55.739238 ==
8952 10:57:55.739660 RX Vref Scan: 0
8953 10:57:55.741708
8954 10:57:55.742145 RX Vref 0 -> 0, step: 1
8955 10:57:55.742668
8956 10:57:55.744858 RX Delay 19 -> 252, step: 4
8957 10:57:55.748708 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8958 10:57:55.755299 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8959 10:57:55.758760 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8960 10:57:55.762235 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8961 10:57:55.765174 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8962 10:57:55.768380 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8963 10:57:55.771461 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8964 10:57:55.778079 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8965 10:57:55.781600 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8966 10:57:55.785375 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 10:57:55.788772 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8968 10:57:55.791781 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8969 10:57:55.798204 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8970 10:57:55.801790 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 10:57:55.804793 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8972 10:57:55.807994 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8973 10:57:55.808453 ==
8974 10:57:55.811830 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 10:57:55.818342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 10:57:55.818914 ==
8977 10:57:55.819311 DQS Delay:
8978 10:57:55.821652 DQS0 = 0, DQS1 = 0
8979 10:57:55.822220 DQM Delay:
8980 10:57:55.822719 DQM0 = 134, DQM1 = 130
8981 10:57:55.824993 DQ Delay:
8982 10:57:55.828051 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8983 10:57:55.831190 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8984 10:57:55.834503 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8985 10:57:55.837924 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8986 10:57:55.838020
8987 10:57:55.838140
8988 10:57:55.838231
8989 10:57:55.841034 [DramC_TX_OE_Calibration] TA2
8990 10:57:55.844401 Original DQ_B0 (3 6) =30, OEN = 27
8991 10:57:55.847508 Original DQ_B1 (3 6) =30, OEN = 27
8992 10:57:55.850676 24, 0x0, End_B0=24 End_B1=24
8993 10:57:55.850760 25, 0x0, End_B0=25 End_B1=25
8994 10:57:55.854611 26, 0x0, End_B0=26 End_B1=26
8995 10:57:55.857907 27, 0x0, End_B0=27 End_B1=27
8996 10:57:55.861203 28, 0x0, End_B0=28 End_B1=28
8997 10:57:55.864525 29, 0x0, End_B0=29 End_B1=29
8998 10:57:55.864596 30, 0x0, End_B0=30 End_B1=30
8999 10:57:55.867795 31, 0x4545, End_B0=30 End_B1=30
9000 10:57:55.871010 Byte0 end_step=30 best_step=27
9001 10:57:55.874335 Byte1 end_step=30 best_step=27
9002 10:57:55.877527 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 10:57:55.881195 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 10:57:55.881277
9005 10:57:55.881341
9006 10:57:55.887546 [DQSOSCAuto] RK1, (LSB)MR18= 0x230a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
9007 10:57:55.890974 CH1 RK1: MR19=303, MR18=230A
9008 10:57:55.897473 CH1_RK1: MR19=0x303, MR18=0x230A, DQSOSC=392, MR23=63, INC=24, DEC=16
9009 10:57:55.901252 [RxdqsGatingPostProcess] freq 1600
9010 10:57:55.904371 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 10:57:55.908036 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 10:57:55.910920 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 10:57:55.914487 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 10:57:55.917481 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 10:57:55.921048 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 10:57:55.924335 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 10:57:55.927696 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 10:57:55.930890 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 10:57:55.934189 Pre-setting of DQS Precalculation
9020 10:57:55.937483 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 10:57:55.944473 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 10:57:55.954026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 10:57:55.954613
9024 10:57:55.954984
9025 10:57:55.957647 [Calibration Summary] 3200 Mbps
9026 10:57:55.958126 CH 0, Rank 0
9027 10:57:55.960749 SW Impedance : PASS
9028 10:57:55.961354 DUTY Scan : NO K
9029 10:57:55.964102 ZQ Calibration : PASS
9030 10:57:55.964712 Jitter Meter : NO K
9031 10:57:55.967241 CBT Training : PASS
9032 10:57:55.970625 Write leveling : PASS
9033 10:57:55.971141 RX DQS gating : PASS
9034 10:57:55.973886 RX DQ/DQS(RDDQC) : PASS
9035 10:57:55.977207 TX DQ/DQS : PASS
9036 10:57:55.977686 RX DATLAT : PASS
9037 10:57:55.980414 RX DQ/DQS(Engine): PASS
9038 10:57:55.983884 TX OE : PASS
9039 10:57:55.984379 All Pass.
9040 10:57:55.985027
9041 10:57:55.985412 CH 0, Rank 1
9042 10:57:55.987490 SW Impedance : PASS
9043 10:57:55.990517 DUTY Scan : NO K
9044 10:57:55.991063 ZQ Calibration : PASS
9045 10:57:55.994202 Jitter Meter : NO K
9046 10:57:55.997194 CBT Training : PASS
9047 10:57:55.997611 Write leveling : PASS
9048 10:57:56.000936 RX DQS gating : PASS
9049 10:57:56.003804 RX DQ/DQS(RDDQC) : PASS
9050 10:57:56.003885 TX DQ/DQS : PASS
9051 10:57:56.006830 RX DATLAT : PASS
9052 10:57:56.006953 RX DQ/DQS(Engine): PASS
9053 10:57:56.010352 TX OE : PASS
9054 10:57:56.010433 All Pass.
9055 10:57:56.010498
9056 10:57:56.013456 CH 1, Rank 0
9057 10:57:56.013533 SW Impedance : PASS
9058 10:57:56.017111 DUTY Scan : NO K
9059 10:57:56.020358 ZQ Calibration : PASS
9060 10:57:56.020429 Jitter Meter : NO K
9061 10:57:56.023336 CBT Training : PASS
9062 10:57:56.026690 Write leveling : PASS
9063 10:57:56.026768 RX DQS gating : PASS
9064 10:57:56.030630 RX DQ/DQS(RDDQC) : PASS
9065 10:57:56.033389 TX DQ/DQS : PASS
9066 10:57:56.033483 RX DATLAT : PASS
9067 10:57:56.037728 RX DQ/DQS(Engine): PASS
9068 10:57:56.040291 TX OE : PASS
9069 10:57:56.040710 All Pass.
9070 10:57:56.041039
9071 10:57:56.041345 CH 1, Rank 1
9072 10:57:56.043565 SW Impedance : PASS
9073 10:57:56.047493 DUTY Scan : NO K
9074 10:57:56.048097 ZQ Calibration : PASS
9075 10:57:56.050725 Jitter Meter : NO K
9076 10:57:56.053797 CBT Training : PASS
9077 10:57:56.054218 Write leveling : PASS
9078 10:57:56.056986 RX DQS gating : PASS
9079 10:57:56.060370 RX DQ/DQS(RDDQC) : PASS
9080 10:57:56.060791 TX DQ/DQS : PASS
9081 10:57:56.064002 RX DATLAT : PASS
9082 10:57:56.064422 RX DQ/DQS(Engine): PASS
9083 10:57:56.066900 TX OE : PASS
9084 10:57:56.067354 All Pass.
9085 10:57:56.067715
9086 10:57:56.070837 DramC Write-DBI on
9087 10:57:56.073737 PER_BANK_REFRESH: Hybrid Mode
9088 10:57:56.074263 TX_TRACKING: ON
9089 10:57:56.083689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 10:57:56.090334 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 10:57:56.097469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 10:57:56.103537 [FAST_K] Save calibration result to emmc
9093 10:57:56.103977 sync common calibartion params.
9094 10:57:56.107557 sync cbt_mode0:1, 1:1
9095 10:57:56.110610 dram_init: ddr_geometry: 2
9096 10:57:56.111110 dram_init: ddr_geometry: 2
9097 10:57:56.113501 dram_init: ddr_geometry: 2
9098 10:57:56.117374 0:dram_rank_size:100000000
9099 10:57:56.120326 1:dram_rank_size:100000000
9100 10:57:56.123408 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 10:57:56.126562 DFS_SHUFFLE_HW_MODE: ON
9102 10:57:56.130101 dramc_set_vcore_voltage set vcore to 725000
9103 10:57:56.133368 Read voltage for 1600, 0
9104 10:57:56.133838 Vio18 = 0
9105 10:57:56.136639 Vcore = 725000
9106 10:57:56.137180 Vdram = 0
9107 10:57:56.137583 Vddq = 0
9108 10:57:56.137957 Vmddr = 0
9109 10:57:56.140107 switch to 3200 Mbps bootup
9110 10:57:56.143444 [DramcRunTimeConfig]
9111 10:57:56.143893 PHYPLL
9112 10:57:56.146769 DPM_CONTROL_AFTERK: ON
9113 10:57:56.147428 PER_BANK_REFRESH: ON
9114 10:57:56.149958 REFRESH_OVERHEAD_REDUCTION: ON
9115 10:57:56.153242 CMD_PICG_NEW_MODE: OFF
9116 10:57:56.153791 XRTWTW_NEW_MODE: ON
9117 10:57:56.156590 XRTRTR_NEW_MODE: ON
9118 10:57:56.157129 TX_TRACKING: ON
9119 10:57:56.159830 RDSEL_TRACKING: OFF
9120 10:57:56.163088 DQS Precalculation for DVFS: ON
9121 10:57:56.163638 RX_TRACKING: OFF
9122 10:57:56.164075 HW_GATING DBG: ON
9123 10:57:56.166489 ZQCS_ENABLE_LP4: ON
9124 10:57:56.169911 RX_PICG_NEW_MODE: ON
9125 10:57:56.170331 TX_PICG_NEW_MODE: ON
9126 10:57:56.173148 ENABLE_RX_DCM_DPHY: ON
9127 10:57:56.176873 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 10:57:56.177296 DUMMY_READ_FOR_TRACKING: OFF
9129 10:57:56.180049 !!! SPM_CONTROL_AFTERK: OFF
9130 10:57:56.183626 !!! SPM could not control APHY
9131 10:57:56.187045 IMPEDANCE_TRACKING: ON
9132 10:57:56.187584 TEMP_SENSOR: ON
9133 10:57:56.190126 HW_SAVE_FOR_SR: OFF
9134 10:57:56.193386 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 10:57:56.196941 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 10:57:56.197462 Read ODT Tracking: ON
9137 10:57:56.200136 Refresh Rate DeBounce: ON
9138 10:57:56.203404 DFS_NO_QUEUE_FLUSH: ON
9139 10:57:56.206541 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 10:57:56.207060 ENABLE_DFS_RUNTIME_MRW: OFF
9141 10:57:56.210069 DDR_RESERVE_NEW_MODE: ON
9142 10:57:56.213133 MR_CBT_SWITCH_FREQ: ON
9143 10:57:56.213552 =========================
9144 10:57:56.232916 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 10:57:56.236428 dram_init: ddr_geometry: 2
9146 10:57:56.254654 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 10:57:56.257762 dram_init: dram init end (result: 0)
9148 10:57:56.264366 DRAM-K: Full calibration passed in 24477 msecs
9149 10:57:56.267360 MRC: failed to locate region type 0.
9150 10:57:56.267945 DRAM rank0 size:0x100000000,
9151 10:57:56.271368 DRAM rank1 size=0x100000000
9152 10:57:56.281008 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 10:57:56.287488 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 10:57:56.294570 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 10:57:56.301172 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 10:57:56.304394 DRAM rank0 size:0x100000000,
9157 10:57:56.307568 DRAM rank1 size=0x100000000
9158 10:57:56.307989 CBMEM:
9159 10:57:56.311311 IMD: root @ 0xfffff000 254 entries.
9160 10:57:56.314046 IMD: root @ 0xffffec00 62 entries.
9161 10:57:56.317777 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 10:57:56.320896 WARNING: RO_VPD is uninitialized or empty.
9163 10:57:56.327602 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 10:57:56.334466 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 10:57:56.347436 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9166 10:57:56.358705 BS: romstage times (exec / console): total (unknown) / 24005 ms
9167 10:57:56.359275
9168 10:57:56.359668
9169 10:57:56.368670 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 10:57:56.371736 ARM64: Exception handlers installed.
9171 10:57:56.375794 ARM64: Testing exception
9172 10:57:56.378308 ARM64: Done test exception
9173 10:57:56.378732 Enumerating buses...
9174 10:57:56.382173 Show all devs... Before device enumeration.
9175 10:57:56.385552 Root Device: enabled 1
9176 10:57:56.388652 CPU_CLUSTER: 0: enabled 1
9177 10:57:56.389077 CPU: 00: enabled 1
9178 10:57:56.391745 Compare with tree...
9179 10:57:56.392168 Root Device: enabled 1
9180 10:57:56.395033 CPU_CLUSTER: 0: enabled 1
9181 10:57:56.398337 CPU: 00: enabled 1
9182 10:57:56.398758 Root Device scanning...
9183 10:57:56.402399 scan_static_bus for Root Device
9184 10:57:56.405308 CPU_CLUSTER: 0 enabled
9185 10:57:56.408615 scan_static_bus for Root Device done
9186 10:57:56.411705 scan_bus: bus Root Device finished in 8 msecs
9187 10:57:56.411934 done
9188 10:57:56.418421 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 10:57:56.421685 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 10:57:56.428113 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 10:57:56.431192 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 10:57:56.435081 Allocating resources...
9193 10:57:56.438211 Reading resources...
9194 10:57:56.441286 Root Device read_resources bus 0 link: 0
9195 10:57:56.441469 DRAM rank0 size:0x100000000,
9196 10:57:56.444513 DRAM rank1 size=0x100000000
9197 10:57:56.448195 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 10:57:56.451285 CPU: 00 missing read_resources
9199 10:57:56.455036 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 10:57:56.461533 Root Device read_resources bus 0 link: 0 done
9201 10:57:56.461720 Done reading resources.
9202 10:57:56.467987 Show resources in subtree (Root Device)...After reading.
9203 10:57:56.471385 Root Device child on link 0 CPU_CLUSTER: 0
9204 10:57:56.474717 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 10:57:56.484399 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 10:57:56.484586 CPU: 00
9207 10:57:56.487716 Root Device assign_resources, bus 0 link: 0
9208 10:57:56.491600 CPU_CLUSTER: 0 missing set_resources
9209 10:57:56.497685 Root Device assign_resources, bus 0 link: 0 done
9210 10:57:56.497855 Done setting resources.
9211 10:57:56.504637 Show resources in subtree (Root Device)...After assigning values.
9212 10:57:56.507948 Root Device child on link 0 CPU_CLUSTER: 0
9213 10:57:56.511181 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 10:57:56.520829 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 10:57:56.520917 CPU: 00
9216 10:57:56.524299 Done allocating resources.
9217 10:57:56.527752 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 10:57:56.530886 Enabling resources...
9219 10:57:56.530980 done.
9220 10:57:56.537829 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 10:57:56.537936 Initializing devices...
9222 10:57:56.541091 Root Device init
9223 10:57:56.541202 init hardware done!
9224 10:57:56.544221 0x00000018: ctrlr->caps
9225 10:57:56.547908 52.000 MHz: ctrlr->f_max
9226 10:57:56.548033 0.400 MHz: ctrlr->f_min
9227 10:57:56.550992 0x40ff8080: ctrlr->voltages
9228 10:57:56.551130 sclk: 390625
9229 10:57:56.554075 Bus Width = 1
9230 10:57:56.554196 sclk: 390625
9231 10:57:56.557395 Bus Width = 1
9232 10:57:56.557556 Early init status = 3
9233 10:57:56.564295 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 10:57:56.567569 in-header: 03 fc 00 00 01 00 00 00
9235 10:57:56.567782 in-data: 00
9236 10:57:56.574158 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 10:57:56.577476 in-header: 03 fd 00 00 00 00 00 00
9238 10:57:56.580920 in-data:
9239 10:57:56.584244 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 10:57:56.587271 in-header: 03 fc 00 00 01 00 00 00
9241 10:57:56.590829 in-data: 00
9242 10:57:56.593948 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 10:57:56.598763 in-header: 03 fd 00 00 00 00 00 00
9244 10:57:56.602619 in-data:
9245 10:57:56.605825 [SSUSB] Setting up USB HOST controller...
9246 10:57:56.609067 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 10:57:56.612267 [SSUSB] phy power-on done.
9248 10:57:56.615695 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 10:57:56.622005 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 10:57:56.625712 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 10:57:56.632434 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 10:57:56.638851 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 10:57:56.645603 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 10:57:56.651867 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 10:57:56.658846 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 10:57:56.659267 SPM: binary array size = 0x9dc
9257 10:57:56.665729 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 10:57:56.672135 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 10:57:56.678653 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 10:57:56.681999 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 10:57:56.685411 configure_display: Starting display init
9262 10:57:56.721550 anx7625_power_on_init: Init interface.
9263 10:57:56.724866 anx7625_disable_pd_protocol: Disabled PD feature.
9264 10:57:56.728035 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 10:57:56.755989 anx7625_start_dp_work: Secure OCM version=00
9266 10:57:56.759744 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 10:57:56.773937 sp_tx_get_edid_block: EDID Block = 1
9268 10:57:56.877009 Extracted contents:
9269 10:57:56.880733 header: 00 ff ff ff ff ff ff 00
9270 10:57:56.883716 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 10:57:56.886965 version: 01 04
9272 10:57:56.890340 basic params: 95 1f 11 78 0a
9273 10:57:56.893668 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 10:57:56.896853 established: 00 00 00
9275 10:57:56.903555 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 10:57:56.907234 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 10:57:56.913401 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 10:57:56.920386 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 10:57:56.926865 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 10:57:56.930208 extensions: 00
9281 10:57:56.930679 checksum: fb
9282 10:57:56.931028
9283 10:57:56.933428 Manufacturer: IVO Model 57d Serial Number 0
9284 10:57:56.936585 Made week 0 of 2020
9285 10:57:56.937027 EDID version: 1.4
9286 10:57:56.939728 Digital display
9287 10:57:56.943297 6 bits per primary color channel
9288 10:57:56.943916 DisplayPort interface
9289 10:57:56.946621 Maximum image size: 31 cm x 17 cm
9290 10:57:56.949883 Gamma: 220%
9291 10:57:56.950452 Check DPMS levels
9292 10:57:56.953294 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 10:57:56.960253 First detailed timing is preferred timing
9294 10:57:56.960804 Established timings supported:
9295 10:57:56.963141 Standard timings supported:
9296 10:57:56.966479 Detailed timings
9297 10:57:56.970003 Hex of detail: 383680a07038204018303c0035ae10000019
9298 10:57:56.973228 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 10:57:56.979951 0780 0798 07c8 0820 hborder 0
9300 10:57:56.983141 0438 043b 0447 0458 vborder 0
9301 10:57:56.986256 -hsync -vsync
9302 10:57:56.986732 Did detailed timing
9303 10:57:56.993225 Hex of detail: 000000000000000000000000000000000000
9304 10:57:56.993646 Manufacturer-specified data, tag 0
9305 10:57:56.999749 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 10:57:57.002949 ASCII string: InfoVision
9307 10:57:57.006330 Hex of detail: 000000fe00523134304e574635205248200a
9308 10:57:57.009462 ASCII string: R140NWF5 RH
9309 10:57:57.010118 Checksum
9310 10:57:57.013310 Checksum: 0xfb (valid)
9311 10:57:57.016725 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 10:57:57.019825 DSI data_rate: 832800000 bps
9313 10:57:57.026227 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 10:57:57.029946 anx7625_parse_edid: pixelclock(138800).
9315 10:57:57.033003 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 10:57:57.036165 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 10:57:57.040045 anx7625_dsi_config: config dsi.
9318 10:57:57.046133 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 10:57:57.059302 anx7625_dsi_config: success to config DSI
9320 10:57:57.062679 anx7625_dp_start: MIPI phy setup OK.
9321 10:57:57.065829 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 10:57:57.068888 mtk_ddp_mode_set invalid vrefresh 60
9323 10:57:57.072796 main_disp_path_setup
9324 10:57:57.073204 ovl_layer_smi_id_en
9325 10:57:57.075796 ovl_layer_smi_id_en
9326 10:57:57.076206 ccorr_config
9327 10:57:57.076526 aal_config
9328 10:57:57.079597 gamma_config
9329 10:57:57.080030 postmask_config
9330 10:57:57.082681 dither_config
9331 10:57:57.085595 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 10:57:57.092608 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 10:57:57.096302 Root Device init finished in 551 msecs
9334 10:57:57.096739 CPU_CLUSTER: 0 init
9335 10:57:57.105865 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 10:57:57.109269 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 10:57:57.112383 APU_MBOX 0x190000b0 = 0x10001
9338 10:57:57.115593 APU_MBOX 0x190001b0 = 0x10001
9339 10:57:57.119008 APU_MBOX 0x190005b0 = 0x10001
9340 10:57:57.122290 APU_MBOX 0x190006b0 = 0x10001
9341 10:57:57.125397 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 10:57:57.138105 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9343 10:57:57.150792 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 10:57:57.157261 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 10:57:57.169022 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9346 10:57:57.177772 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 10:57:57.181822 CPU_CLUSTER: 0 init finished in 81 msecs
9348 10:57:57.184962 Devices initialized
9349 10:57:57.188215 Show all devs... After init.
9350 10:57:57.188650 Root Device: enabled 1
9351 10:57:57.191284 CPU_CLUSTER: 0: enabled 1
9352 10:57:57.194471 CPU: 00: enabled 1
9353 10:57:57.197690 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9354 10:57:57.201227 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 10:57:57.204936 ELOG: NV offset 0x57f000 size 0x1000
9356 10:57:57.211443 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9357 10:57:57.217861 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 10:57:57.221213 ELOG: Event(17) added with size 13 at 2023-06-05 10:57:45 UTC
9359 10:57:57.224361 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 10:57:57.228373 in-header: 03 c3 00 00 2c 00 00 00
9361 10:57:57.241273 in-data: 9c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 10:57:57.247948 ELOG: Event(A1) added with size 10 at 2023-06-05 10:57:45 UTC
9363 10:57:57.255004 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9364 10:57:57.261274 ELOG: Event(A0) added with size 9 at 2023-06-05 10:57:45 UTC
9365 10:57:57.264654 elog_add_boot_reason: Logged dev mode boot
9366 10:57:57.267975 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 10:57:57.271320 Finalize devices...
9368 10:57:57.271772 Devices finalized
9369 10:57:57.277789 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 10:57:57.281158 Writing coreboot table at 0xffe64000
9371 10:57:57.284611 0. 000000000010a000-0000000000113fff: RAMSTAGE
9372 10:57:57.287878 1. 0000000040000000-00000000400fffff: RAM
9373 10:57:57.294577 2. 0000000040100000-000000004032afff: RAMSTAGE
9374 10:57:57.297735 3. 000000004032b000-00000000545fffff: RAM
9375 10:57:57.300751 4. 0000000054600000-000000005465ffff: BL31
9376 10:57:57.304506 5. 0000000054660000-00000000ffe63fff: RAM
9377 10:57:57.310667 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9378 10:57:57.314050 7. 0000000100000000-000000023fffffff: RAM
9379 10:57:57.317718 Passing 5 GPIOs to payload:
9380 10:57:57.321071 NAME | PORT | POLARITY | VALUE
9381 10:57:57.324345 EC in RW | 0x000000aa | low | undefined
9382 10:57:57.331016 EC interrupt | 0x00000005 | low | undefined
9383 10:57:57.334062 TPM interrupt | 0x000000ab | high | undefined
9384 10:57:57.337392 SD card detect | 0x00000011 | high | undefined
9385 10:57:57.343925 speaker enable | 0x00000093 | high | undefined
9386 10:57:57.347735 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9387 10:57:57.350743 in-header: 03 f9 00 00 02 00 00 00
9388 10:57:57.351202 in-data: 02 00
9389 10:57:57.353958 ADC[4]: Raw value=904357 ID=7
9390 10:57:57.357195 ADC[3]: Raw value=213810 ID=1
9391 10:57:57.360989 RAM Code: 0x71
9392 10:57:57.361426 ADC[6]: Raw value=75701 ID=0
9393 10:57:57.364120 ADC[5]: Raw value=213072 ID=1
9394 10:57:57.367463 SKU Code: 0x1
9395 10:57:57.370863 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9396 10:57:57.374123 coreboot table: 964 bytes.
9397 10:57:57.377386 IMD ROOT 0. 0xfffff000 0x00001000
9398 10:57:57.380596 IMD SMALL 1. 0xffffe000 0x00001000
9399 10:57:57.384103 RO MCACHE 2. 0xffffc000 0x00001104
9400 10:57:57.387751 CONSOLE 3. 0xfff7c000 0x00080000
9401 10:57:57.390954 FMAP 4. 0xfff7b000 0x00000452
9402 10:57:57.393845 TIME STAMP 5. 0xfff7a000 0x00000910
9403 10:57:57.397529 VBOOT WORK 6. 0xfff66000 0x00014000
9404 10:57:57.400551 RAMOOPS 7. 0xffe66000 0x00100000
9405 10:57:57.404299 COREBOOT 8. 0xffe64000 0x00002000
9406 10:57:57.404846 IMD small region:
9407 10:57:57.407431 IMD ROOT 0. 0xffffec00 0x00000400
9408 10:57:57.410875 VPD 1. 0xffffeba0 0x0000004c
9409 10:57:57.414409 MMC STATUS 2. 0xffffeb80 0x00000004
9410 10:57:57.420789 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9411 10:57:57.424121 Probing TPM: done!
9412 10:57:57.427466 Connected to device vid:did:rid of 1ae0:0028:00
9413 10:57:57.437223 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9414 10:57:57.440944 Initialized TPM device CR50 revision 0
9415 10:57:57.444487 Checking cr50 for pending updates
9416 10:57:57.447804 Reading cr50 TPM mode
9417 10:57:57.455816 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9418 10:57:57.462966 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 10:57:57.502828 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9420 10:57:57.506090 Checking segment from ROM address 0x40100000
9421 10:57:57.509143 Checking segment from ROM address 0x4010001c
9422 10:57:57.516204 Loading segment from ROM address 0x40100000
9423 10:57:57.516291 code (compression=0)
9424 10:57:57.523016 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 10:57:57.532793 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 10:57:57.532878 it's not compressed!
9427 10:57:57.539281 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 10:57:57.542546 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 10:57:57.563239 Loading segment from ROM address 0x4010001c
9430 10:57:57.563398 Entry Point 0x80000000
9431 10:57:57.566347 Loaded segments
9432 10:57:57.569631 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 10:57:57.576316 Jumping to boot code at 0x80000000(0xffe64000)
9434 10:57:57.582901 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 10:57:57.589502 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 10:57:57.597348 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9437 10:57:57.601243 Checking segment from ROM address 0x40100000
9438 10:57:57.604424 Checking segment from ROM address 0x4010001c
9439 10:57:57.610846 Loading segment from ROM address 0x40100000
9440 10:57:57.610925 code (compression=1)
9441 10:57:57.617668 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 10:57:57.627999 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 10:57:57.628088 using LZMA
9444 10:57:57.636550 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 10:57:57.643182 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 10:57:57.646342 Loading segment from ROM address 0x4010001c
9447 10:57:57.646456 Entry Point 0x54601000
9448 10:57:57.649506 Loaded segments
9449 10:57:57.652709 NOTICE: MT8192 bl31_setup
9450 10:57:57.659981 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 10:57:57.663290 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 10:57:57.666119 WARNING: region 0:
9453 10:57:57.670013 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 10:57:57.670203 WARNING: region 1:
9455 10:57:57.676322 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 10:57:57.679970 WARNING: region 2:
9457 10:57:57.683503 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 10:57:57.686678 WARNING: region 3:
9459 10:57:57.689532 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 10:57:57.693573 WARNING: region 4:
9461 10:57:57.700257 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 10:57:57.700730 WARNING: region 5:
9463 10:57:57.703217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 10:57:57.706847 WARNING: region 6:
9465 10:57:57.709940 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 10:57:57.712913 WARNING: region 7:
9467 10:57:57.716775 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 10:57:57.723545 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 10:57:57.726458 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 10:57:57.730363 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 10:57:57.736922 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 10:57:57.740040 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 10:57:57.743390 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 10:57:57.750012 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 10:57:57.753710 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 10:57:57.756928 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 10:57:57.763314 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 10:57:57.766674 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 10:57:57.773853 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 10:57:57.777259 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 10:57:57.780180 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 10:57:57.787358 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 10:57:57.790288 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 10:57:57.793310 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 10:57:57.799869 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 10:57:57.803223 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 10:57:57.806570 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 10:57:57.812856 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 10:57:57.816622 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 10:57:57.822942 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 10:57:57.826251 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 10:57:57.829972 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 10:57:57.836843 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 10:57:57.839824 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 10:57:57.846760 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 10:57:57.849978 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 10:57:57.853332 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 10:57:57.859890 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 10:57:57.863610 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 10:57:57.866890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 10:57:57.873530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 10:57:57.876760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 10:57:57.880211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 10:57:57.883227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 10:57:57.890412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 10:57:57.893651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 10:57:57.896936 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 10:57:57.900101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 10:57:57.907312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 10:57:57.909999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 10:57:57.913827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 10:57:57.917081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 10:57:57.923999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 10:57:57.927255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 10:57:57.930245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 10:57:57.936987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 10:57:57.940749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 10:57:57.943846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 10:57:57.950703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 10:57:57.953919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 10:57:57.960722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 10:57:57.963903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 10:57:57.970797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 10:57:57.974079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 10:57:57.977380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 10:57:57.983874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 10:57:57.987195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 10:57:57.993967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 10:57:57.997254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 10:57:58.003896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 10:57:58.006977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 10:57:58.010298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 10:57:58.017509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 10:57:58.020303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 10:57:58.027147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 10:57:58.030185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 10:57:58.037173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 10:57:58.040415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 10:57:58.044053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 10:57:58.050539 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 10:57:58.053895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 10:57:58.060562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 10:57:58.063833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 10:57:58.070076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 10:57:58.074117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 10:57:58.077454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 10:57:58.084141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 10:57:58.087658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 10:57:58.094244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 10:57:58.097419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 10:57:58.104234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 10:57:58.107417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 10:57:58.110648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 10:57:58.117081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 10:57:58.120468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 10:57:58.126975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 10:57:58.130352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 10:57:58.137242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 10:57:58.140535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 10:57:58.144263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 10:57:58.150728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 10:57:58.153876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 10:57:58.160765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 10:57:58.163883 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 10:57:58.167123 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 10:57:58.174143 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 10:57:58.177334 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 10:57:58.180900 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 10:57:58.184131 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 10:57:58.190689 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 10:57:58.193963 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 10:57:58.200912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 10:57:58.204128 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 10:57:58.207355 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 10:57:58.214374 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 10:57:58.217536 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 10:57:58.224522 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 10:57:58.227715 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 10:57:58.231022 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 10:57:58.237635 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 10:57:58.240632 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 10:57:58.247342 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 10:57:58.250524 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 10:57:58.253659 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 10:57:58.257395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 10:57:58.264345 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 10:57:58.266987 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 10:57:58.270755 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 10:57:58.274077 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 10:57:58.280332 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 10:57:58.284170 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 10:57:58.287332 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 10:57:58.294024 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 10:57:58.297372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 10:57:58.304012 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 10:57:58.307240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 10:57:58.310449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 10:57:58.317641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 10:57:58.320921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 10:57:58.324206 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 10:57:58.331213 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 10:57:58.334612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 10:57:58.341327 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 10:57:58.344686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 10:57:58.347745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 10:57:58.354544 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 10:57:58.357722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 10:57:58.361353 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 10:57:58.367401 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 10:57:58.371112 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 10:57:58.377776 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 10:57:58.380853 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 10:57:58.384665 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 10:57:58.391167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 10:57:58.394375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 10:57:58.401011 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 10:57:58.404256 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 10:57:58.407645 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 10:57:58.414712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 10:57:58.417945 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 10:57:58.421061 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 10:57:58.427591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 10:57:58.431063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 10:57:58.437938 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 10:57:58.441381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 10:57:58.444587 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 10:57:58.451316 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 10:57:58.454396 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 10:57:58.461040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 10:57:58.464816 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 10:57:58.468087 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 10:57:58.474244 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 10:57:58.478044 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 10:57:58.481020 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 10:57:58.487415 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 10:57:58.491266 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 10:57:58.497703 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 10:57:58.500996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 10:57:58.504461 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 10:57:58.511557 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 10:57:58.514175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 10:57:58.518115 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 10:57:58.524221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 10:57:58.527902 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 10:57:58.534535 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 10:57:58.538015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 10:57:58.541037 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 10:57:58.547741 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 10:57:58.551162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 10:57:58.558226 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 10:57:58.561310 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 10:57:58.564959 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 10:57:58.571282 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 10:57:58.574371 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 10:57:58.581402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 10:57:58.584316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 10:57:58.587957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 10:57:58.594110 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 10:57:58.597836 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 10:57:58.604026 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 10:57:58.607222 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 10:57:58.613773 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 10:57:58.617249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 10:57:58.620786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 10:57:58.627361 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 10:57:58.630645 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 10:57:58.636970 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 10:57:58.640642 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 10:57:58.646888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 10:57:58.650532 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 10:57:58.653799 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 10:57:58.660026 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 10:57:58.663870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 10:57:58.670379 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 10:57:58.673397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 10:57:58.677056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 10:57:58.683484 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 10:57:58.687022 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 10:57:58.693765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 10:57:58.696889 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 10:57:58.703015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 10:57:58.706696 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 10:57:58.709786 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 10:57:58.716331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 10:57:58.719754 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 10:57:58.726472 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 10:57:58.729836 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 10:57:58.733136 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 10:57:58.739502 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 10:57:58.742689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 10:57:58.749760 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 10:57:58.752963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 10:57:58.759238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 10:57:58.762713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 10:57:58.765993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 10:57:58.772584 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 10:57:58.776556 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 10:57:58.779528 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 10:57:58.782522 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 10:57:58.789675 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 10:57:58.792719 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 10:57:58.796421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 10:57:58.802707 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 10:57:58.805726 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 10:57:58.808962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 10:57:58.815691 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 10:57:58.818817 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 10:57:58.825422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 10:57:58.829290 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 10:57:58.832109 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 10:57:58.838724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 10:57:58.841998 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 10:57:58.845284 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 10:57:58.852370 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 10:57:58.855552 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 10:57:58.858838 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 10:57:58.865218 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 10:57:58.869093 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 10:57:58.875725 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 10:57:58.878770 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 10:57:58.882148 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 10:57:58.888430 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 10:57:58.891644 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 10:57:58.895530 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 10:57:58.901885 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 10:57:58.904990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 10:57:58.911830 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 10:57:58.914922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 10:57:58.918637 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 10:57:58.924845 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 10:57:58.928195 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 10:57:58.931477 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 10:57:58.939106 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 10:57:58.941727 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 10:57:58.948375 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 10:57:58.951979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 10:57:58.955309 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 10:57:58.958692 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 10:57:58.961797 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 10:57:58.968216 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 10:57:58.972004 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 10:57:58.975315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 10:57:58.978525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 10:57:58.984903 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 10:57:58.988390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 10:57:58.991712 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 10:57:58.994782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 10:57:59.001902 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 10:57:59.004915 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 10:57:59.008386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 10:57:59.015220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 10:57:59.018269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 10:57:59.025159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 10:57:59.028253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 10:57:59.034650 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 10:57:59.038676 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 10:57:59.041310 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 10:57:59.047959 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 10:57:59.051275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 10:57:59.058111 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 10:57:59.061402 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 10:57:59.064782 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 10:57:59.071780 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 10:57:59.074873 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 10:57:59.077939 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 10:57:59.085021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 10:57:59.088371 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 10:57:59.094905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 10:57:59.098203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 10:57:59.104454 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 10:57:59.108043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 10:57:59.111545 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 10:57:59.117733 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 10:57:59.121598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 10:57:59.127736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 10:57:59.131309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 10:57:59.134514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 10:57:59.141313 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 10:57:59.144562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 10:57:59.151211 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 10:57:59.154540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 10:57:59.157771 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 10:57:59.164193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 10:57:59.167418 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 10:57:59.174012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 10:57:59.177668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 10:57:59.184255 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 10:57:59.187377 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 10:57:59.190755 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 10:57:59.197809 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 10:57:59.201027 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 10:57:59.207628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 10:57:59.210866 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 10:57:59.214159 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 10:57:59.220915 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 10:57:59.223962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 10:57:59.230676 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 10:57:59.233882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 10:57:59.236990 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 10:57:59.243982 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 10:57:59.247626 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 10:57:59.254048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 10:57:59.257456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 10:57:59.263963 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 10:57:59.267144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 10:57:59.270433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 10:57:59.277223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 10:57:59.280372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 10:57:59.287119 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 10:57:59.290299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 10:57:59.294128 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 10:57:59.300503 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 10:57:59.303754 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 10:57:59.310734 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 10:57:59.313974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 10:57:59.317265 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 10:57:59.323596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 10:57:59.327194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 10:57:59.333874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 10:57:59.337066 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 10:57:59.340320 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 10:57:59.347178 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 10:57:59.350369 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 10:57:59.357171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 10:57:59.360563 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 10:57:59.367091 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 10:57:59.370871 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 10:57:59.374263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 10:57:59.380541 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 10:57:59.383745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 10:57:59.390172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 10:57:59.394105 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 10:57:59.400183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 10:57:59.403690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 10:57:59.406837 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 10:57:59.413879 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 10:57:59.416552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 10:57:59.423215 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 10:57:59.426973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 10:57:59.433575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 10:57:59.436696 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 10:57:59.443425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 10:57:59.446313 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 10:57:59.449921 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 10:57:59.456631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 10:57:59.459797 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 10:57:59.466518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 10:57:59.469817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 10:57:59.472879 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 10:57:59.479512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 10:57:59.482819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 10:57:59.489968 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 10:57:59.493146 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 10:57:59.499504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 10:57:59.502773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 10:57:59.506588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 10:57:59.512777 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 10:57:59.516521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 10:57:59.523287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 10:57:59.525925 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 10:57:59.533096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 10:57:59.535865 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 10:57:59.542997 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 10:57:59.546100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 10:57:59.549283 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 10:57:59.556035 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 10:57:59.559718 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 10:57:59.565943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 10:57:59.569677 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 10:57:59.572648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 10:57:59.579601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 10:57:59.582316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 10:57:59.589444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 10:57:59.592706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 10:57:59.599226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 10:57:59.602581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 10:57:59.608980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 10:57:59.612915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 10:57:59.619668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 10:57:59.623025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 10:57:59.629034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 10:57:59.632389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 10:57:59.638855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 10:57:59.642207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 10:57:59.649328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 10:57:59.652487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 10:57:59.658844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 10:57:59.662394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 10:57:59.665560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 10:57:59.672516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 10:57:59.678643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 10:57:59.681780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 10:57:59.688716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 10:57:59.691946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 10:57:59.699243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 10:57:59.702609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 10:57:59.705884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 10:57:59.712290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 10:57:59.718590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 10:57:59.722438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 10:57:59.728716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 10:57:59.731935 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 10:57:59.732009 INFO: [APUAPC] vio 0
9904 10:57:59.739615 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 10:57:59.742751 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 10:57:59.746189 INFO: [APUAPC] D0_APC_0: 0x400510
9907 10:57:59.749566 INFO: [APUAPC] D0_APC_1: 0x0
9908 10:57:59.752708 INFO: [APUAPC] D0_APC_2: 0x1540
9909 10:57:59.755811 INFO: [APUAPC] D0_APC_3: 0x0
9910 10:57:59.759114 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 10:57:59.763005 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 10:57:59.766170 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 10:57:59.769293 INFO: [APUAPC] D1_APC_3: 0x0
9914 10:57:59.772433 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 10:57:59.776060 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 10:57:59.779792 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 10:57:59.782928 INFO: [APUAPC] D2_APC_3: 0x0
9918 10:57:59.785899 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 10:57:59.789402 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 10:57:59.792494 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 10:57:59.792592 INFO: [APUAPC] D3_APC_3: 0x0
9922 10:57:59.796271 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 10:57:59.802832 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 10:57:59.806000 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 10:57:59.806110 INFO: [APUAPC] D4_APC_3: 0x0
9926 10:57:59.809302 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 10:57:59.812676 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 10:57:59.816085 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 10:57:59.819208 INFO: [APUAPC] D5_APC_3: 0x0
9930 10:57:59.822349 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 10:57:59.825554 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 10:57:59.828748 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 10:57:59.832492 INFO: [APUAPC] D6_APC_3: 0x0
9934 10:57:59.835795 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 10:57:59.839095 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 10:57:59.842304 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 10:57:59.845462 INFO: [APUAPC] D7_APC_3: 0x0
9938 10:57:59.848819 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 10:57:59.852187 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 10:57:59.855495 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 10:57:59.858679 INFO: [APUAPC] D8_APC_3: 0x0
9942 10:57:59.861823 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 10:57:59.865224 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 10:57:59.868440 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 10:57:59.872142 INFO: [APUAPC] D9_APC_3: 0x0
9946 10:57:59.875190 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 10:57:59.878266 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 10:57:59.882174 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 10:57:59.885152 INFO: [APUAPC] D10_APC_3: 0x0
9950 10:57:59.888243 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 10:57:59.892044 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 10:57:59.895014 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 10:57:59.898709 INFO: [APUAPC] D11_APC_3: 0x0
9954 10:57:59.901824 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 10:57:59.905068 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 10:57:59.908322 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 10:57:59.911639 INFO: [APUAPC] D12_APC_3: 0x0
9958 10:57:59.914930 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 10:57:59.918082 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 10:57:59.921969 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 10:57:59.925058 INFO: [APUAPC] D13_APC_3: 0x0
9962 10:57:59.928270 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 10:57:59.931488 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 10:57:59.935227 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 10:57:59.938399 INFO: [APUAPC] D14_APC_3: 0x0
9966 10:57:59.941654 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 10:57:59.944962 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 10:57:59.948186 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 10:57:59.951438 INFO: [APUAPC] D15_APC_3: 0x0
9970 10:57:59.954822 INFO: [APUAPC] APC_CON: 0x4
9971 10:57:59.957950 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 10:57:59.961734 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 10:57:59.965101 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 10:57:59.968440 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 10:57:59.971637 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 10:57:59.971741 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 10:57:59.975045 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 10:57:59.978280 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 10:57:59.981369 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 10:57:59.985107 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 10:57:59.988246 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 10:57:59.991210 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 10:57:59.994904 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 10:57:59.998027 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 10:58:00.001805 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 10:58:00.004554 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 10:58:00.004653 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 10:58:00.008232 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 10:58:00.011270 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 10:58:00.014633 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 10:58:00.017942 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 10:58:00.021412 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 10:58:00.025176 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 10:58:00.027861 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 10:58:00.031250 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 10:58:00.034675 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 10:58:00.037869 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 10:58:00.041236 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 10:58:00.044936 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 10:58:00.045088 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 10:58:00.048010 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 10:58:00.051347 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 10:58:00.054446 INFO: [NOCDAPC] APC_CON: 0x4
10004 10:58:00.058527 INFO: [APUAPC] set_apusys_apc done
10005 10:58:00.061799 INFO: [DEVAPC] devapc_init done
10006 10:58:00.064559 INFO: GICv3 without legacy support detected.
10007 10:58:00.071788 INFO: ARM GICv3 driver initialized in EL3
10008 10:58:00.075176 INFO: Maximum SPI INTID supported: 639
10009 10:58:00.078324 INFO: BL31: Initializing runtime services
10010 10:58:00.084822 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 10:58:00.085418 INFO: SPM: enable CPC mode
10012 10:58:00.091665 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 10:58:00.094511 INFO: BL31: Preparing for EL3 exit to normal world
10014 10:58:00.101384 INFO: Entry point address = 0x80000000
10015 10:58:00.101980 INFO: SPSR = 0x8
10016 10:58:00.107901
10017 10:58:00.108482
10018 10:58:00.108994
10019 10:58:00.111399 Starting depthcharge on Spherion...
10020 10:58:00.112007
10021 10:58:00.112522 Wipe memory regions:
10022 10:58:00.113021
10023 10:58:00.116236 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10024 10:58:00.117032 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10025 10:58:00.117616 Setting prompt string to ['asurada:']
10026 10:58:00.118223 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10027 10:58:00.119145 [0x00000040000000, 0x00000054600000)
10028 10:58:00.236302
10029 10:58:00.236808 [0x00000054660000, 0x00000080000000)
10030 10:58:00.496949
10031 10:58:00.497133 [0x000000821a7280, 0x000000ffe64000)
10032 10:58:01.241506
10033 10:58:01.241688 [0x00000100000000, 0x00000240000000)
10034 10:58:03.132177
10035 10:58:03.135237 Initializing XHCI USB controller at 0x11200000.
10036 10:58:04.173478
10037 10:58:04.176484 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 10:58:04.176602
10039 10:58:04.176700
10040 10:58:04.176792
10041 10:58:04.177104 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 10:58:04.277523 asurada: tftpboot 192.168.201.1 10591023/tftp-deploy-_ex67_zt/kernel/image.itb 10591023/tftp-deploy-_ex67_zt/kernel/cmdline
10044 10:58:04.277730 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 10:58:04.277892 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10046 10:58:04.282001 tftpboot 192.168.201.1 10591023/tftp-deploy-_ex67_zt/kernel/image.ittp-deploy-_ex67_zt/kernel/cmdline
10047 10:58:04.282116
10048 10:58:04.282213 Waiting for link
10049 10:58:04.442434
10050 10:58:04.442594 R8152: Initializing
10051 10:58:04.442697
10052 10:58:04.445611 Version 9 (ocp_data = 6010)
10053 10:58:04.445714
10054 10:58:04.449358 R8152: Done initializing
10055 10:58:04.449464
10056 10:58:04.449558 Adding net device
10057 10:58:06.395398
10058 10:58:06.395577 done.
10059 10:58:06.395686
10060 10:58:06.395787 MAC: 00:e0:4c:78:7a:aa
10061 10:58:06.395884
10062 10:58:06.398283 Sending DHCP discover... done.
10063 10:58:06.398395
10064 10:58:06.401568 Waiting for reply... done.
10065 10:58:06.401679
10066 10:58:06.405213 Sending DHCP request... done.
10067 10:58:06.405315
10068 10:58:06.405412 Waiting for reply... done.
10069 10:58:06.405501
10070 10:58:06.408453 My ip is 192.168.201.12
10071 10:58:06.408552
10072 10:58:06.411535 The DHCP server ip is 192.168.201.1
10073 10:58:06.411607
10074 10:58:06.414874 TFTP server IP predefined by user: 192.168.201.1
10075 10:58:06.414974
10076 10:58:06.421544 Bootfile predefined by user: 10591023/tftp-deploy-_ex67_zt/kernel/image.itb
10077 10:58:06.421656
10078 10:58:06.424671 Sending tftp read request... done.
10079 10:58:06.424778
10080 10:58:06.427943 Waiting for the transfer...
10081 10:58:06.428042
10082 10:58:06.685139 00000000 ################################################################
10083 10:58:06.685291
10084 10:58:06.938807 00080000 ################################################################
10085 10:58:06.938960
10086 10:58:07.200216 00100000 ################################################################
10087 10:58:07.200373
10088 10:58:07.461109 00180000 ################################################################
10089 10:58:07.461264
10090 10:58:07.722067 00200000 ################################################################
10091 10:58:07.722220
10092 10:58:07.980084 00280000 ################################################################
10093 10:58:07.980263
10094 10:58:08.232397 00300000 ################################################################
10095 10:58:08.232578
10096 10:58:08.484502 00380000 ################################################################
10097 10:58:08.484675
10098 10:58:08.745074 00400000 ################################################################
10099 10:58:08.745224
10100 10:58:09.028225 00480000 ################################################################
10101 10:58:09.028382
10102 10:58:09.282729 00500000 ################################################################
10103 10:58:09.282887
10104 10:58:09.550254 00580000 ################################################################
10105 10:58:09.550401
10106 10:58:09.803273 00600000 ################################################################
10107 10:58:09.803478
10108 10:58:10.055910 00680000 ################################################################
10109 10:58:10.056084
10110 10:58:10.308693 00700000 ################################################################
10111 10:58:10.308868
10112 10:58:10.562308 00780000 ################################################################
10113 10:58:10.562479
10114 10:58:10.813974 00800000 ################################################################
10115 10:58:10.814141
10116 10:58:11.069740 00880000 ################################################################
10117 10:58:11.069898
10118 10:58:11.332740 00900000 ################################################################
10119 10:58:11.332889
10120 10:58:11.593027 00980000 ################################################################
10121 10:58:11.593210
10122 10:58:11.848617 00a00000 ################################################################
10123 10:58:11.848763
10124 10:58:12.101923 00a80000 ################################################################
10125 10:58:12.102080
10126 10:58:12.359539 00b00000 ################################################################
10127 10:58:12.359712
10128 10:58:12.629260 00b80000 ################################################################
10129 10:58:12.629414
10130 10:58:12.887428 00c00000 ################################################################
10131 10:58:12.887595
10132 10:58:13.149442 00c80000 ################################################################
10133 10:58:13.149584
10134 10:58:13.406107 00d00000 ################################################################
10135 10:58:13.406282
10136 10:58:13.663236 00d80000 ################################################################
10137 10:58:13.663445
10138 10:58:13.919011 00e00000 ################################################################
10139 10:58:13.919190
10140 10:58:14.194558 00e80000 ################################################################
10141 10:58:14.194720
10142 10:58:14.482045 00f00000 ################################################################
10143 10:58:14.482212
10144 10:58:14.759037 00f80000 ################################################################
10145 10:58:14.759213
10146 10:58:15.011755 01000000 ################################################################
10147 10:58:15.011902
10148 10:58:15.264194 01080000 ################################################################
10149 10:58:15.264363
10150 10:58:15.524774 01100000 ################################################################
10151 10:58:15.524928
10152 10:58:15.814318 01180000 ################################################################
10153 10:58:15.814473
10154 10:58:16.104704 01200000 ################################################################
10155 10:58:16.104862
10156 10:58:16.361972 01280000 ################################################################
10157 10:58:16.362132
10158 10:58:16.625620 01300000 ################################################################
10159 10:58:16.625764
10160 10:58:16.887575 01380000 ################################################################
10161 10:58:16.887727
10162 10:58:17.153506 01400000 ################################################################
10163 10:58:17.153641
10164 10:58:17.470372 01480000 ################################################################
10165 10:58:17.470518
10166 10:58:17.747666 01500000 ################################################################
10167 10:58:17.747810
10168 10:58:18.015255 01580000 ################################################################
10169 10:58:18.015435
10170 10:58:18.294147 01600000 ################################################################
10171 10:58:18.294318
10172 10:58:18.566169 01680000 ################################################################
10173 10:58:18.566314
10174 10:58:18.831728 01700000 ################################################################
10175 10:58:18.831876
10176 10:58:19.098185 01780000 ################################################################
10177 10:58:19.098407
10178 10:58:19.390791 01800000 ################################################################
10179 10:58:19.390965
10180 10:58:19.651611 01880000 ################################################################
10181 10:58:19.651772
10182 10:58:19.914930 01900000 ################################################################
10183 10:58:19.915064
10184 10:58:20.190366 01980000 ################################################################
10185 10:58:20.190536
10186 10:58:20.528137 01a00000 ################################################################
10187 10:58:20.528271
10188 10:58:20.861605 01a80000 ################################################################
10189 10:58:20.861746
10190 10:58:21.133237 01b00000 ################################################################
10191 10:58:21.133369
10192 10:58:21.413096 01b80000 ################################################################
10193 10:58:21.413263
10194 10:58:21.676150 01c00000 ################################################################
10195 10:58:21.676289
10196 10:58:21.944987 01c80000 ################################################################
10197 10:58:21.945146
10198 10:58:22.206080 01d00000 ################################################################
10199 10:58:22.206235
10200 10:58:22.461753 01d80000 ################################################################
10201 10:58:22.461887
10202 10:58:22.729270 01e00000 ################################################################
10203 10:58:22.729401
10204 10:58:23.011258 01e80000 ################################################################
10205 10:58:23.011460
10206 10:58:23.303786 01f00000 ################################################################
10207 10:58:23.303918
10208 10:58:23.595737 01f80000 ################################################################
10209 10:58:23.595868
10210 10:58:23.867444 02000000 ################################################################
10211 10:58:23.867580
10212 10:58:24.129055 02080000 ################################################################
10213 10:58:24.129192
10214 10:58:24.382828 02100000 ################################################################
10215 10:58:24.382962
10216 10:58:24.673034 02180000 ################################################################
10217 10:58:24.673170
10218 10:58:24.947156 02200000 ################################################################
10219 10:58:24.947295
10220 10:58:25.210704 02280000 ################################################################
10221 10:58:25.210844
10222 10:58:25.480585 02300000 ################################################################
10223 10:58:25.480717
10224 10:58:25.740394 02380000 ################################################################
10225 10:58:25.740531
10226 10:58:25.994658 02400000 ################################################################
10227 10:58:25.994821
10228 10:58:26.269856 02480000 ################################################################
10229 10:58:26.270019
10230 10:58:26.559793 02500000 ################################################################
10231 10:58:26.559950
10232 10:58:26.814043 02580000 ################################################################
10233 10:58:26.814210
10234 10:58:27.074307 02600000 ################################################################
10235 10:58:27.074452
10236 10:58:27.338517 02680000 ################################################################
10237 10:58:27.338659
10238 10:58:27.611601 02700000 ################################################################
10239 10:58:27.611749
10240 10:58:27.899773 02780000 ################################################################
10241 10:58:27.899932
10242 10:58:28.155634 02800000 ################################################################
10243 10:58:28.155786
10244 10:58:28.407266 02880000 ################################################################
10245 10:58:28.407436
10246 10:58:28.656484 02900000 ################################################################
10247 10:58:28.656639
10248 10:58:28.914968 02980000 ################################################################
10249 10:58:28.915120
10250 10:58:29.163655 02a00000 ################################################################
10251 10:58:29.163831
10252 10:58:29.412361 02a80000 ################################################################
10253 10:58:29.412524
10254 10:58:29.661668 02b00000 ################################################################
10255 10:58:29.661814
10256 10:58:29.909733 02b80000 ################################################################
10257 10:58:29.909903
10258 10:58:30.170047 02c00000 ################################################################
10259 10:58:30.170220
10260 10:58:30.420446 02c80000 ################################################################
10261 10:58:30.420580
10262 10:58:30.678339 02d00000 ################################################################
10263 10:58:30.678478
10264 10:58:30.926775 02d80000 ################################################################
10265 10:58:30.926935
10266 10:58:31.195229 02e00000 ################################################################
10267 10:58:31.195405
10268 10:58:31.463180 02e80000 ################################################################
10269 10:58:31.463376
10270 10:58:31.751558 02f00000 ################################################################
10271 10:58:31.751693
10272 10:58:32.009521 02f80000 ################################################################
10273 10:58:32.009681
10274 10:58:32.264232 03000000 ################################################################
10275 10:58:32.264364
10276 10:58:32.540255 03080000 ################################################################
10277 10:58:32.540390
10278 10:58:32.797679 03100000 ################################################################
10279 10:58:32.797820
10280 10:58:33.051048 03180000 ################################################################
10281 10:58:33.051232
10282 10:58:33.312276 03200000 ################################################################
10283 10:58:33.312440
10284 10:58:33.561503 03280000 ################################################################
10285 10:58:33.561670
10286 10:58:33.819181 03300000 ################################################################
10287 10:58:33.819319
10288 10:58:34.073982 03380000 ################################################################
10289 10:58:34.074140
10290 10:58:34.349694 03400000 ################################################################
10291 10:58:34.349837
10292 10:58:34.686896 03480000 ################################################################
10293 10:58:34.687074
10294 10:58:34.950312 03500000 ################################################################
10295 10:58:34.950488
10296 10:58:35.189424 03580000 ################################################################
10297 10:58:35.189598
10298 10:58:35.437797 03600000 ################################################################
10299 10:58:35.437942
10300 10:58:35.705334 03680000 ################################################################
10301 10:58:35.705470
10302 10:58:35.977716 03700000 ################################################################
10303 10:58:35.977857
10304 10:58:36.246997 03780000 ################################################################
10305 10:58:36.247135
10306 10:58:36.507666 03800000 ################################################################
10307 10:58:36.507814
10308 10:58:36.757903 03880000 ################################################################
10309 10:58:36.758080
10310 10:58:37.007455 03900000 ################################################################
10311 10:58:37.007699
10312 10:58:37.294133 03980000 ################################################################
10313 10:58:37.294311
10314 10:58:37.601700 03a00000 ################################################################
10315 10:58:37.601884
10316 10:58:37.853743 03a80000 ################################################################
10317 10:58:37.853924
10318 10:58:38.145174 03b00000 ################################################################
10319 10:58:38.145322
10320 10:58:38.405588 03b80000 ################################################################
10321 10:58:38.405754
10322 10:58:38.687660 03c00000 ################################################################
10323 10:58:38.687830
10324 10:58:38.962191 03c80000 ################################################################
10325 10:58:38.962331
10326 10:58:39.239017 03d00000 ################################################################
10327 10:58:39.239199
10328 10:58:39.497772 03d80000 ################################################################
10329 10:58:39.497925
10330 10:58:39.744298 03e00000 ################################################################
10331 10:58:39.744445
10332 10:58:39.996696 03e80000 ################################################################
10333 10:58:39.996842
10334 10:58:40.207723 03f00000 ###################################################### done.
10335 10:58:40.207883
10336 10:58:40.210917 The bootfile was 66496874 bytes long.
10337 10:58:40.211002
10338 10:58:40.214745 Sending tftp read request... done.
10339 10:58:40.214829
10340 10:58:40.218062 Waiting for the transfer...
10341 10:58:40.218178
10342 10:58:40.218273 00000000 # done.
10343 10:58:40.218365
10344 10:58:40.227868 Command line loaded dynamically from TFTP file: 10591023/tftp-deploy-_ex67_zt/kernel/cmdline
10345 10:58:40.227955
10346 10:58:40.237923 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10347 10:58:40.238033
10348 10:58:40.238125 Loading FIT.
10349 10:58:40.238213
10350 10:58:40.241135 Image ramdisk-1 has 56365979 bytes.
10351 10:58:40.241217
10352 10:58:40.244371 Image fdt-1 has 46924 bytes.
10353 10:58:40.244478
10354 10:58:40.247558 Image kernel-1 has 10081937 bytes.
10355 10:58:40.247640
10356 10:58:40.257840 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10357 10:58:40.257926
10358 10:58:40.274337 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10359 10:58:40.274425
10360 10:58:40.280593 Choosing best match conf-1 for compat google,spherion-rev2.
10361 10:58:40.280676
10362 10:58:40.288604 Connected to device vid:did:rid of 1ae0:0028:00
10363 10:58:40.296698
10364 10:58:40.299745 tpm_get_response: command 0x17b, return code 0x0
10365 10:58:40.299828
10366 10:58:40.302714 ec_init: CrosEC protocol v3 supported (256, 248)
10367 10:58:40.307150
10368 10:58:40.310370 tpm_cleanup: add release locality here.
10369 10:58:40.310452
10370 10:58:40.310516 Shutting down all USB controllers.
10371 10:58:40.313652
10372 10:58:40.313734 Removing current net device
10373 10:58:40.313799
10374 10:58:40.320468 Exiting depthcharge with code 4 at timestamp: 69508420
10375 10:58:40.320551
10376 10:58:40.323617 LZMA decompressing kernel-1 to 0x821a6718
10377 10:58:40.323700
10378 10:58:40.327101 LZMA decompressing kernel-1 to 0x40000000
10379 10:58:41.593552
10380 10:58:41.593691 jumping to kernel
10381 10:58:41.594127 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10382 10:58:41.594230 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10383 10:58:41.594308 Setting prompt string to ['Linux version [0-9]']
10384 10:58:41.594378 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10385 10:58:41.594447 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10386 10:58:41.676295
10387 10:58:41.679158 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10388 10:58:41.682617 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10389 10:58:41.682710 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10390 10:58:41.682797 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10391 10:58:41.682876 Using line separator: #'\n'#
10392 10:58:41.682938 No login prompt set.
10393 10:58:41.683000 Parsing kernel messages
10394 10:58:41.683056 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10395 10:58:41.683157 [login-action] Waiting for messages, (timeout 00:03:44)
10396 10:58:41.702237 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10397 10:58:41.705470 [ 0.000000] random: crng init done
10398 10:58:41.709377 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10399 10:58:41.712498 [ 0.000000] efi: UEFI not found.
10400 10:58:41.722205 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10401 10:58:41.729148 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10402 10:58:41.738912 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10403 10:58:41.749289 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10404 10:58:41.755789 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10405 10:58:41.759063 [ 0.000000] printk: bootconsole [mtk8250] enabled
10406 10:58:41.767288 [ 0.000000] NUMA: No NUMA configuration found
10407 10:58:41.773850 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10408 10:58:41.780314 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10409 10:58:41.780432 [ 0.000000] Zone ranges:
10410 10:58:41.787280 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10411 10:58:41.790839 [ 0.000000] DMA32 empty
10412 10:58:41.797400 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10413 10:58:41.800133 [ 0.000000] Movable zone start for each node
10414 10:58:41.804229 [ 0.000000] Early memory node ranges
10415 10:58:41.810233 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10416 10:58:41.816783 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10417 10:58:41.823606 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10418 10:58:41.830612 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10419 10:58:41.836617 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10420 10:58:41.843256 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10421 10:58:41.899576 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10422 10:58:41.906178 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10423 10:58:41.913260 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10424 10:58:41.915939 [ 0.000000] psci: probing for conduit method from DT.
10425 10:58:41.923021 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10426 10:58:41.926063 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10427 10:58:41.932313 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10428 10:58:41.935968 [ 0.000000] psci: SMC Calling Convention v1.2
10429 10:58:41.943066 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10430 10:58:41.946123 [ 0.000000] Detected VIPT I-cache on CPU0
10431 10:58:41.952320 [ 0.000000] CPU features: detected: GIC system register CPU interface
10432 10:58:41.959386 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10433 10:58:41.965703 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10434 10:58:41.972358 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10435 10:58:41.979507 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10436 10:58:41.986050 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10437 10:58:41.992428 [ 0.000000] alternatives: applying boot alternatives
10438 10:58:41.995538 [ 0.000000] Fallback order for Node 0: 0
10439 10:58:42.005821 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10440 10:58:42.005953 [ 0.000000] Policy zone: Normal
10441 10:58:42.018903 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10442 10:58:42.028721 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10443 10:58:42.041353 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10444 10:58:42.051638 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10445 10:58:42.057971 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10446 10:58:42.061229 <6>[ 0.000000] software IO TLB: area num 8.
10447 10:58:42.117843 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10448 10:58:42.266856 <6>[ 0.000000] Memory: 7917896K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434872K reserved, 32768K cma-reserved)
10449 10:58:42.273512 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10450 10:58:42.280500 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10451 10:58:42.283629 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10452 10:58:42.290792 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10453 10:58:42.296733 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10454 10:58:42.300490 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10455 10:58:42.309982 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10456 10:58:42.317095 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10457 10:58:42.323066 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10458 10:58:42.330091 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10459 10:58:42.333193 <6>[ 0.000000] GICv3: 608 SPIs implemented
10460 10:58:42.336238 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10461 10:58:42.343193 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10462 10:58:42.346742 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10463 10:58:42.353064 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10464 10:58:42.366358 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10465 10:58:42.379232 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10466 10:58:42.386021 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10467 10:58:42.393536 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10468 10:58:42.406825 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10469 10:58:42.413993 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10470 10:58:42.420040 <6>[ 0.009228] Console: colour dummy device 80x25
10471 10:58:42.430428 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10472 10:58:42.436955 <6>[ 0.024463] pid_max: default: 32768 minimum: 301
10473 10:58:42.440138 <6>[ 0.029337] LSM: Security Framework initializing
10474 10:58:42.447015 <6>[ 0.034307] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10475 10:58:42.456719 <6>[ 0.042122] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10476 10:58:42.463499 <6>[ 0.051553] cblist_init_generic: Setting adjustable number of callback queues.
10477 10:58:42.470255 <6>[ 0.059047] cblist_init_generic: Setting shift to 3 and lim to 1.
10478 10:58:42.476817 <6>[ 0.065385] cblist_init_generic: Setting shift to 3 and lim to 1.
10479 10:58:42.482985 <6>[ 0.071794] rcu: Hierarchical SRCU implementation.
10480 10:58:42.489978 <6>[ 0.076839] rcu: Max phase no-delay instances is 1000.
10481 10:58:42.493278 <6>[ 0.083863] EFI services will not be available.
10482 10:58:42.499990 <6>[ 0.088867] smp: Bringing up secondary CPUs ...
10483 10:58:42.507042 <6>[ 0.093918] Detected VIPT I-cache on CPU1
10484 10:58:42.514249 <6>[ 0.093989] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10485 10:58:42.520632 <6>[ 0.094021] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10486 10:58:42.523878 <6>[ 0.094352] Detected VIPT I-cache on CPU2
10487 10:58:42.530416 <6>[ 0.094402] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10488 10:58:42.540799 <6>[ 0.094417] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10489 10:58:42.543879 <6>[ 0.094676] Detected VIPT I-cache on CPU3
10490 10:58:42.550077 <6>[ 0.094723] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10491 10:58:42.556810 <6>[ 0.094737] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10492 10:58:42.560388 <6>[ 0.095041] CPU features: detected: Spectre-v4
10493 10:58:42.566665 <6>[ 0.095047] CPU features: detected: Spectre-BHB
10494 10:58:42.569794 <6>[ 0.095052] Detected PIPT I-cache on CPU4
10495 10:58:42.576964 <6>[ 0.095110] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10496 10:58:42.583264 <6>[ 0.095126] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10497 10:58:42.589919 <6>[ 0.095420] Detected PIPT I-cache on CPU5
10498 10:58:42.596793 <6>[ 0.095484] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10499 10:58:42.603442 <6>[ 0.095500] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10500 10:58:42.606546 <6>[ 0.095782] Detected PIPT I-cache on CPU6
10501 10:58:42.613093 <6>[ 0.095848] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10502 10:58:42.619514 <6>[ 0.095864] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10503 10:58:42.626643 <6>[ 0.096165] Detected PIPT I-cache on CPU7
10504 10:58:42.633254 <6>[ 0.096232] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10505 10:58:42.639802 <6>[ 0.096247] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10506 10:58:42.642932 <6>[ 0.096295] smp: Brought up 1 node, 8 CPUs
10507 10:58:42.649683 <6>[ 0.237716] SMP: Total of 8 processors activated.
10508 10:58:42.652790 <6>[ 0.242637] CPU features: detected: 32-bit EL0 Support
10509 10:58:42.662763 <6>[ 0.248001] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10510 10:58:42.669430 <6>[ 0.256801] CPU features: detected: Common not Private translations
10511 10:58:42.673030 <6>[ 0.263276] CPU features: detected: CRC32 instructions
10512 10:58:42.679485 <6>[ 0.268627] CPU features: detected: RCpc load-acquire (LDAPR)
10513 10:58:42.686651 <6>[ 0.274587] CPU features: detected: LSE atomic instructions
10514 10:58:42.692950 <6>[ 0.280404] CPU features: detected: Privileged Access Never
10515 10:58:42.696194 <6>[ 0.286183] CPU features: detected: RAS Extension Support
10516 10:58:42.706251 <6>[ 0.291826] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10517 10:58:42.709433 <6>[ 0.299047] CPU: All CPU(s) started at EL2
10518 10:58:42.715902 <6>[ 0.303390] alternatives: applying system-wide alternatives
10519 10:58:42.725261 <6>[ 0.314101] devtmpfs: initialized
10520 10:58:42.737419 <6>[ 0.323167] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10521 10:58:42.747670 <6>[ 0.333125] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10522 10:58:42.754317 <6>[ 0.341260] pinctrl core: initialized pinctrl subsystem
10523 10:58:42.757673 <6>[ 0.347929] DMI not present or invalid.
10524 10:58:42.763766 <6>[ 0.352332] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10525 10:58:42.773889 <6>[ 0.359186] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10526 10:58:42.780636 <6>[ 0.366766] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10527 10:58:42.790187 <6>[ 0.374991] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10528 10:58:42.793944 <6>[ 0.383231] audit: initializing netlink subsys (disabled)
10529 10:58:42.803521 <5>[ 0.388926] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10530 10:58:42.810532 <6>[ 0.389633] thermal_sys: Registered thermal governor 'step_wise'
10531 10:58:42.817443 <6>[ 0.396894] thermal_sys: Registered thermal governor 'power_allocator'
10532 10:58:42.820397 <6>[ 0.403148] cpuidle: using governor menu
10533 10:58:42.826941 <6>[ 0.414108] NET: Registered PF_QIPCRTR protocol family
10534 10:58:42.833399 <6>[ 0.419582] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10535 10:58:42.836862 <6>[ 0.426682] ASID allocator initialised with 32768 entries
10536 10:58:42.843987 <6>[ 0.433267] Serial: AMBA PL011 UART driver
10537 10:58:42.852983 <4>[ 0.441967] Trying to register duplicate clock ID: 134
10538 10:58:42.907393 <6>[ 0.499584] KASLR enabled
10539 10:58:42.921420 <6>[ 0.507357] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10540 10:58:42.928334 <6>[ 0.514373] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10541 10:58:42.935291 <6>[ 0.520863] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10542 10:58:42.941828 <6>[ 0.527869] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10543 10:58:42.948413 <6>[ 0.534354] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10544 10:58:42.954856 <6>[ 0.541358] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10545 10:58:42.961511 <6>[ 0.547846] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10546 10:58:42.967906 <6>[ 0.554850] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10547 10:58:42.971348 <6>[ 0.562362] ACPI: Interpreter disabled.
10548 10:58:42.979945 <6>[ 0.568755] iommu: Default domain type: Translated
10549 10:58:42.986032 <6>[ 0.573870] iommu: DMA domain TLB invalidation policy: strict mode
10550 10:58:42.989289 <5>[ 0.580522] SCSI subsystem initialized
10551 10:58:42.995975 <6>[ 0.584681] usbcore: registered new interface driver usbfs
10552 10:58:43.003147 <6>[ 0.590411] usbcore: registered new interface driver hub
10553 10:58:43.006242 <6>[ 0.595960] usbcore: registered new device driver usb
10554 10:58:43.012949 <6>[ 0.602038] pps_core: LinuxPPS API ver. 1 registered
10555 10:58:43.022918 <6>[ 0.607229] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10556 10:58:43.025951 <6>[ 0.616577] PTP clock support registered
10557 10:58:43.029673 <6>[ 0.620819] EDAC MC: Ver: 3.0.0
10558 10:58:43.037193 <6>[ 0.625962] FPGA manager framework
10559 10:58:43.040356 <6>[ 0.629641] Advanced Linux Sound Architecture Driver Initialized.
10560 10:58:43.044037 <6>[ 0.636407] vgaarb: loaded
10561 10:58:43.050695 <6>[ 0.639576] clocksource: Switched to clocksource arch_sys_counter
10562 10:58:43.057181 <5>[ 0.646010] VFS: Disk quotas dquot_6.6.0
10563 10:58:43.064120 <6>[ 0.650192] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10564 10:58:43.066829 <6>[ 0.657376] pnp: PnP ACPI: disabled
10565 10:58:43.074744 <6>[ 0.664056] NET: Registered PF_INET protocol family
10566 10:58:43.084561 <6>[ 0.669656] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10567 10:58:43.096225 <6>[ 0.681961] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10568 10:58:43.105981 <6>[ 0.690779] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10569 10:58:43.112547 <6>[ 0.698746] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10570 10:58:43.119894 <6>[ 0.707448] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10571 10:58:43.131612 <6>[ 0.717191] TCP: Hash tables configured (established 65536 bind 65536)
10572 10:58:43.138519 <6>[ 0.724051] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10573 10:58:43.144517 <6>[ 0.731250] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10574 10:58:43.151638 <6>[ 0.738949] NET: Registered PF_UNIX/PF_LOCAL protocol family
10575 10:58:43.158004 <6>[ 0.745047] RPC: Registered named UNIX socket transport module.
10576 10:58:43.161432 <6>[ 0.751201] RPC: Registered udp transport module.
10577 10:58:43.167652 <6>[ 0.756136] RPC: Registered tcp transport module.
10578 10:58:43.174292 <6>[ 0.761070] RPC: Registered tcp NFSv4.1 backchannel transport module.
10579 10:58:43.177623 <6>[ 0.767735] PCI: CLS 0 bytes, default 64
10580 10:58:43.181065 <6>[ 0.772118] Unpacking initramfs...
10581 10:58:43.198720 <6>[ 0.784137] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10582 10:58:43.208451 <6>[ 0.792804] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10583 10:58:43.211517 <6>[ 0.801647] kvm [1]: IPA Size Limit: 40 bits
10584 10:58:43.218695 <6>[ 0.806175] kvm [1]: GICv3: no GICV resource entry
10585 10:58:43.221762 <6>[ 0.811194] kvm [1]: disabling GICv2 emulation
10586 10:58:43.228356 <6>[ 0.815881] kvm [1]: GIC system register CPU interface enabled
10587 10:58:43.231503 <6>[ 0.822047] kvm [1]: vgic interrupt IRQ18
10588 10:58:43.238090 <6>[ 0.826432] kvm [1]: VHE mode initialized successfully
10589 10:58:43.244395 <5>[ 0.832857] Initialise system trusted keyrings
10590 10:58:43.251598 <6>[ 0.837665] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10591 10:58:43.258425 <6>[ 0.847579] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10592 10:58:43.265003 <5>[ 0.853962] NFS: Registering the id_resolver key type
10593 10:58:43.268204 <5>[ 0.859261] Key type id_resolver registered
10594 10:58:43.274715 <5>[ 0.863676] Key type id_legacy registered
10595 10:58:43.281432 <6>[ 0.867955] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10596 10:58:43.288132 <6>[ 0.874877] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10597 10:58:43.294405 <6>[ 0.882581] 9p: Installing v9fs 9p2000 file system support
10598 10:58:43.331037 <5>[ 0.920401] Key type asymmetric registered
10599 10:58:43.334393 <5>[ 0.924733] Asymmetric key parser 'x509' registered
10600 10:58:43.344590 <6>[ 0.929872] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10601 10:58:43.347847 <6>[ 0.937481] io scheduler mq-deadline registered
10602 10:58:43.350979 <6>[ 0.942260] io scheduler kyber registered
10603 10:58:43.369536 <6>[ 0.958965] EINJ: ACPI disabled.
10604 10:58:43.401809 <4>[ 0.984015] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 10:58:43.411910 <4>[ 0.994630] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 10:58:43.425761 <6>[ 1.015051] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10607 10:58:43.434348 <6>[ 1.023054] printk: console [ttyS0] disabled
10608 10:58:43.462071 <6>[ 1.047704] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10609 10:58:43.468768 <6>[ 1.057177] printk: console [ttyS0] enabled
10610 10:58:43.471934 <6>[ 1.057177] printk: console [ttyS0] enabled
10611 10:58:43.478414 <6>[ 1.066071] printk: bootconsole [mtk8250] disabled
10612 10:58:43.481582 <6>[ 1.066071] printk: bootconsole [mtk8250] disabled
10613 10:58:43.488193 <6>[ 1.077071] SuperH (H)SCI(F) driver initialized
10614 10:58:43.491419 <6>[ 1.082342] msm_serial: driver initialized
10615 10:58:43.505668 <6>[ 1.091187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10616 10:58:43.515223 <6>[ 1.099733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10617 10:58:43.521850 <6>[ 1.108275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10618 10:58:43.532153 <6>[ 1.116903] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10619 10:58:43.538674 <6>[ 1.125609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10620 10:58:43.548582 <6>[ 1.134323] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10621 10:58:43.558378 <6>[ 1.142865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10622 10:58:43.565449 <6>[ 1.151684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10623 10:58:43.574947 <6>[ 1.160226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10624 10:58:43.586135 <6>[ 1.175517] loop: module loaded
10625 10:58:43.592608 <6>[ 1.181446] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10626 10:58:43.615227 <4>[ 1.204558] mtk-pmic-keys: Failed to locate of_node [id: -1]
10627 10:58:43.621980 <6>[ 1.211183] megasas: 07.719.03.00-rc1
10628 10:58:43.631354 <6>[ 1.220754] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10629 10:58:43.638331 <6>[ 1.226957] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10630 10:58:43.654823 <6>[ 1.243616] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10631 10:58:43.711521 <6>[ 1.294195] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10632 10:58:45.566087 <6>[ 3.155611] Freeing initrd memory: 55040K
10633 10:58:45.576171 <6>[ 3.165778] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10634 10:58:45.587200 <6>[ 3.176441] tun: Universal TUN/TAP device driver, 1.6
10635 10:58:45.590566 <6>[ 3.182484] thunder_xcv, ver 1.0
10636 10:58:45.593387 <6>[ 3.185990] thunder_bgx, ver 1.0
10637 10:58:45.597024 <6>[ 3.189485] nicpf, ver 1.0
10638 10:58:45.607234 <6>[ 3.193499] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10639 10:58:45.610929 <6>[ 3.200974] hns3: Copyright (c) 2017 Huawei Corporation.
10640 10:58:45.617452 <6>[ 3.206560] hclge is initializing
10641 10:58:45.620645 <6>[ 3.210134] e1000: Intel(R) PRO/1000 Network Driver
10642 10:58:45.627640 <6>[ 3.215262] e1000: Copyright (c) 1999-2006 Intel Corporation.
10643 10:58:45.630867 <6>[ 3.221276] e1000e: Intel(R) PRO/1000 Network Driver
10644 10:58:45.637277 <6>[ 3.226491] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10645 10:58:45.644421 <6>[ 3.232677] igb: Intel(R) Gigabit Ethernet Network Driver
10646 10:58:45.650807 <6>[ 3.238327] igb: Copyright (c) 2007-2014 Intel Corporation.
10647 10:58:45.657229 <6>[ 3.244166] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10648 10:58:45.663775 <6>[ 3.250684] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10649 10:58:45.667612 <6>[ 3.257145] sky2: driver version 1.30
10650 10:58:45.673937 <6>[ 3.262122] VFIO - User Level meta-driver version: 0.3
10651 10:58:45.681202 <6>[ 3.270284] usbcore: registered new interface driver usb-storage
10652 10:58:45.687758 <6>[ 3.276736] usbcore: registered new device driver onboard-usb-hub
10653 10:58:45.696240 <6>[ 3.285744] mt6397-rtc mt6359-rtc: registered as rtc0
10654 10:58:45.705986 <6>[ 3.291212] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:58:33 UTC (1685962713)
10655 10:58:45.709730 <6>[ 3.300771] i2c_dev: i2c /dev entries driver
10656 10:58:45.726282 <6>[ 3.312508] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10657 10:58:45.733368 <6>[ 3.322685] sdhci: Secure Digital Host Controller Interface driver
10658 10:58:45.739869 <6>[ 3.329124] sdhci: Copyright(c) Pierre Ossman
10659 10:58:45.746759 <6>[ 3.334522] Synopsys Designware Multimedia Card Interface Driver
10660 10:58:45.749984 <6>[ 3.341152] mmc0: CQHCI version 5.10
10661 10:58:45.756542 <6>[ 3.341662] sdhci-pltfm: SDHCI platform and OF driver helper
10662 10:58:45.763523 <6>[ 3.352999] ledtrig-cpu: registered to indicate activity on CPUs
10663 10:58:45.774542 <6>[ 3.360217] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 10:58:45.777683 <6>[ 3.367622] usbcore: registered new interface driver usbhid
10665 10:58:45.784150 <6>[ 3.373448] usbhid: USB HID core driver
10666 10:58:45.791000 <6>[ 3.377694] spi_master spi0: will run message pump with realtime priority
10667 10:58:45.833773 <6>[ 3.416482] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 10:58:45.851924 <6>[ 3.431556] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 10:58:45.855860 <6>[ 3.445137] mmc0: Command Queue Engine enabled
10670 10:58:45.862430 <6>[ 3.449893] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10671 10:58:45.868784 <6>[ 3.456812] cros-ec-spi spi0.0: Chrome EC device registered
10672 10:58:45.871967 <6>[ 3.457162] mmcblk0: mmc0:0001 DA4128 116 GiB
10673 10:58:45.882251 <6>[ 3.471800] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10674 10:58:45.890050 <6>[ 3.479011] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10675 10:58:45.896248 <6>[ 3.484877] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10676 10:58:45.903106 <6>[ 3.490776] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10677 10:58:45.919390 <6>[ 3.505650] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10678 10:58:45.927874 <6>[ 3.517021] NET: Registered PF_PACKET protocol family
10679 10:58:45.930951 <6>[ 3.522448] 9pnet: Installing 9P2000 support
10680 10:58:45.937948 <5>[ 3.527007] Key type dns_resolver registered
10681 10:58:45.941205 <6>[ 3.532012] registered taskstats version 1
10682 10:58:45.947634 <5>[ 3.536407] Loading compiled-in X.509 certificates
10683 10:58:45.981363 <4>[ 3.564051] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 10:58:45.991114 <4>[ 3.574736] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 10:58:46.001336 <3>[ 3.587266] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10686 10:58:46.013368 <6>[ 3.602647] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10687 10:58:46.020132 <6>[ 3.609408] xhci-mtk 11200000.usb: xHCI Host Controller
10688 10:58:46.026489 <6>[ 3.614909] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10689 10:58:46.036845 <6>[ 3.622766] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10690 10:58:46.043631 <6>[ 3.632199] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10691 10:58:46.050116 <6>[ 3.638395] xhci-mtk 11200000.usb: xHCI Host Controller
10692 10:58:46.056797 <6>[ 3.643900] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10693 10:58:46.063261 <6>[ 3.651557] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10694 10:58:46.069834 <6>[ 3.659449] hub 1-0:1.0: USB hub found
10695 10:58:46.073671 <6>[ 3.663482] hub 1-0:1.0: 1 port detected
10696 10:58:46.082989 <6>[ 3.667839] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10697 10:58:46.086631 <6>[ 3.676459] hub 2-0:1.0: USB hub found
10698 10:58:46.089965 <6>[ 3.680475] hub 2-0:1.0: 1 port detected
10699 10:58:46.098291 <6>[ 3.687729] mtk-msdc 11f70000.mmc: Got CD GPIO
10700 10:58:46.114778 <6>[ 3.700648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10701 10:58:46.121362 <6>[ 3.708676] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10702 10:58:46.131229 <4>[ 3.716644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10703 10:58:46.140894 <6>[ 3.726309] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10704 10:58:46.147739 <6>[ 3.734390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10705 10:58:46.154546 <6>[ 3.742413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10706 10:58:46.164189 <6>[ 3.750331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10707 10:58:46.170850 <6>[ 3.758152] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10708 10:58:46.180497 <6>[ 3.765975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10709 10:58:46.190613 <6>[ 3.776762] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10710 10:58:46.200441 <6>[ 3.785132] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10711 10:58:46.207717 <6>[ 3.793480] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10712 10:58:46.217273 <6>[ 3.801823] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10713 10:58:46.223650 <6>[ 3.810166] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10714 10:58:46.233558 <6>[ 3.818509] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10715 10:58:46.240196 <6>[ 3.826853] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10716 10:58:46.250430 <6>[ 3.835196] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10717 10:58:46.257001 <6>[ 3.843538] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10718 10:58:46.266763 <6>[ 3.851880] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10719 10:58:46.273136 <6>[ 3.860222] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10720 10:58:46.283520 <6>[ 3.868565] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10721 10:58:46.289892 <6>[ 3.876907] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10722 10:58:46.299913 <6>[ 3.885251] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10723 10:58:46.306400 <6>[ 3.893599] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10724 10:58:46.313353 <6>[ 3.902519] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10725 10:58:46.320772 <6>[ 3.909932] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10726 10:58:46.327943 <6>[ 3.916970] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10727 10:58:46.337799 <6>[ 3.924076] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10728 10:58:46.344457 <6>[ 3.931383] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10729 10:58:46.354561 <6>[ 3.938290] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10730 10:58:46.361223 <6>[ 3.947433] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10731 10:58:46.371165 <6>[ 3.956568] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10732 10:58:46.381055 <6>[ 3.965870] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10733 10:58:46.391111 <6>[ 3.975346] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10734 10:58:46.401337 <6>[ 3.984823] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10735 10:58:46.407908 <6>[ 3.993949] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10736 10:58:46.418049 <6>[ 4.003423] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10737 10:58:46.427997 <6>[ 4.012550] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10738 10:58:46.437666 <6>[ 4.021851] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10739 10:58:46.447720 <6>[ 4.032019] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10740 10:58:46.457302 <6>[ 4.043400] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10741 10:58:46.501980 <6>[ 4.087853] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10742 10:58:46.655432 <6>[ 4.245203] hub 1-1:1.0: USB hub found
10743 10:58:46.659214 <6>[ 4.249682] hub 1-1:1.0: 4 ports detected
10744 10:58:46.782008 <6>[ 4.367982] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10745 10:58:46.807265 <6>[ 4.396387] hub 2-1:1.0: USB hub found
10746 10:58:46.810256 <6>[ 4.400787] hub 2-1:1.0: 3 ports detected
10747 10:58:46.981952 <6>[ 4.567850] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10748 10:58:47.114502 <6>[ 4.703799] hub 1-1.4:1.0: USB hub found
10749 10:58:47.117687 <6>[ 4.708473] hub 1-1.4:1.0: 2 ports detected
10750 10:58:47.194112 <6>[ 4.780103] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10751 10:58:47.414020 <6>[ 4.999853] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10752 10:58:47.605741 <6>[ 5.191860] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10753 10:58:58.741501 <6>[ 16.332405] ALSA device list:
10754 10:58:58.744556 <6>[ 16.335662] No soundcards found.
10755 10:58:58.757340 <6>[ 16.348116] Freeing unused kernel memory: 8384K
10756 10:58:58.760376 <6>[ 16.353047] Run /init as init process
10757 10:58:58.791382 <6>[ 16.381860] NET: Registered PF_INET6 protocol family
10758 10:58:58.797708 <6>[ 16.388192] Segment Routing with IPv6
10759 10:58:58.801047 <6>[ 16.392172] In-situ OAM (IOAM) with IPv6
10760 10:58:58.832629 <30>[ 16.406708] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10761 10:58:58.839982 <30>[ 16.430523] systemd[1]: Detected architecture arm64.
10762 10:58:58.840117
10763 10:58:58.846341 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10764 10:58:58.846466
10765 10:58:58.861357 <30>[ 16.451987] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10766 10:58:59.003780 <30>[ 16.591440] systemd[1]: Queued start job for default target Graphical Interface.
10767 10:58:59.046182 <30>[ 16.637162] systemd[1]: Created slice system-getty.slice.
10768 10:58:59.052624 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10769 10:58:59.069688 <30>[ 16.660452] systemd[1]: Created slice system-modprobe.slice.
10770 10:58:59.076361 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10771 10:58:59.093533 <30>[ 16.684332] systemd[1]: Created slice system-serial\x2dgetty.slice.
10772 10:58:59.103252 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10773 10:58:59.118103 <30>[ 16.708893] systemd[1]: Created slice User and Session Slice.
10774 10:58:59.124527 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10775 10:58:59.145302 <30>[ 16.732381] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10776 10:58:59.154537 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10777 10:58:59.173115 <30>[ 16.760373] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10778 10:58:59.179678 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10779 10:58:59.199970 <30>[ 16.783951] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10780 10:58:59.206554 <30>[ 16.795982] systemd[1]: Reached target Local Encrypted Volumes.
10781 10:58:59.212957 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10782 10:58:59.229197 <30>[ 16.820194] systemd[1]: Reached target Paths.
10783 10:58:59.232977 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10784 10:58:59.248906 <30>[ 16.839900] systemd[1]: Reached target Remote File Systems.
10785 10:58:59.255657 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10786 10:58:59.268966 <30>[ 16.859891] systemd[1]: Reached target Slices.
10787 10:58:59.272202 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10788 10:58:59.288856 <30>[ 16.879889] systemd[1]: Reached target Swap.
10789 10:58:59.292549 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10790 10:58:59.312913 <30>[ 16.900135] systemd[1]: Listening on initctl Compatibility Named Pipe.
10791 10:58:59.319256 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10792 10:58:59.325862 <30>[ 16.914893] systemd[1]: Listening on Journal Audit Socket.
10793 10:58:59.332612 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10794 10:58:59.345738 <30>[ 16.936146] systemd[1]: Listening on Journal Socket (/dev/log).
10795 10:58:59.352106 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10796 10:58:59.369370 <30>[ 16.960166] systemd[1]: Listening on Journal Socket.
10797 10:58:59.375704 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10798 10:58:59.389648 <30>[ 16.980167] systemd[1]: Listening on udev Control Socket.
10799 10:58:59.395966 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10800 10:58:59.413617 <30>[ 17.004508] systemd[1]: Listening on udev Kernel Socket.
10801 10:58:59.420052 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10802 10:58:59.453030 <30>[ 17.044005] systemd[1]: Mounting Huge Pages File System...
10803 10:58:59.459567 Mounting [0;1;39mHuge Pages File System[0m...
10804 10:58:59.475083 <30>[ 17.066034] systemd[1]: Mounting POSIX Message Queue File System...
10805 10:58:59.481818 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10806 10:58:59.499106 <30>[ 17.090013] systemd[1]: Mounting Kernel Debug File System...
10807 10:58:59.505857 Mounting [0;1;39mKernel Debug File System[0m...
10808 10:58:59.524598 <30>[ 17.112134] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10809 10:58:59.544658 <30>[ 17.132290] systemd[1]: Starting Create list of static device nodes for the current kernel...
10810 10:58:59.551493 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10811 10:58:59.571534 <30>[ 17.162281] systemd[1]: Starting Load Kernel Module configfs...
10812 10:58:59.577849 Starting [0;1;39mLoad Kernel Module configfs[0m...
10813 10:58:59.595484 <30>[ 17.186219] systemd[1]: Starting Load Kernel Module drm...
10814 10:58:59.601635 Starting [0;1;39mLoad Kernel Module drm[0m...
10815 10:58:59.620212 <30>[ 17.208123] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10816 10:58:59.630407 <30>[ 17.221601] systemd[1]: Starting Journal Service...
10817 10:58:59.634243 Starting [0;1;39mJournal Service[0m...
10818 10:58:59.651973 <30>[ 17.242746] systemd[1]: Starting Load Kernel Modules...
10819 10:58:59.658564 Starting [0;1;39mLoad Kernel Modules[0m...
10820 10:58:59.678919 <30>[ 17.266601] systemd[1]: Starting Remount Root and Kernel File Systems...
10821 10:58:59.685597 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10822 10:58:59.703232 <30>[ 17.294453] systemd[1]: Starting Coldplug All udev Devices...
10823 10:58:59.709966 Starting [0;1;39mColdplug All udev Devices[0m...
10824 10:58:59.727218 <30>[ 17.318457] systemd[1]: Started Journal Service.
10825 10:58:59.733986 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10826 10:58:59.750797 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10827 10:58:59.770077 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10828 10:58:59.785839 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10829 10:58:59.805832 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10830 10:58:59.822481 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10831 10:58:59.839003 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10832 10:58:59.855016 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10833 10:58:59.873769 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10834 10:58:59.889106 See 'systemctl status systemd-remount-fs.service' for details.
10835 10:58:59.925585 Mounting [0;1;39mKernel Configuration File System[0m...
10836 10:58:59.947520 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10837 10:58:59.965163 <46>[ 17.552811] systemd-journald[174]: Received client request to flush runtime journal.
10838 10:58:59.973865 Starting [0;1;39mLoad/Save Random Seed[0m...
10839 10:58:59.992663 Starting [0;1;39mApply Kernel Variables[0m...
10840 10:59:00.008688 Starting [0;1;39mCreate System Users[0m...
10841 10:59:00.029281 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10842 10:59:00.049183 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10843 10:59:00.062264 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10844 10:59:00.078456 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10845 10:59:00.094107 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10846 10:59:00.110026 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10847 10:59:00.166056 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10848 10:59:00.189036 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10849 10:59:00.201342 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10850 10:59:00.217014 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10851 10:59:00.253673 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10852 10:59:00.277072 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10853 10:59:00.293681 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10854 10:59:00.313802 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10855 10:59:00.362628 Starting [0;1;39mNetwork Time Synchronization[0m...
10856 10:59:00.382665 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10857 10:59:00.420412 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10858 10:59:00.468598 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10859 10:59:00.492945 <6>[ 18.080383] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10860 10:59:00.504736 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10861 10:59:00.511302 <6>[ 18.101705] remoteproc remoteproc0: scp is available
10862 10:59:00.521315 <4>[ 18.107238] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10863 10:59:00.527810 <6>[ 18.117195] remoteproc remoteproc0: powering up scp
10864 10:59:00.537619 [[0;32m OK [<4>[ 18.123745] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10865 10:59:00.547853 0m] Reached targ<3>[ 18.135359] remoteproc remoteproc0: request_firmware failed: -2
10866 10:59:00.548006 et [0;1;39mSystem Time Set[0m.
10867 10:59:00.559072 <6>[ 18.150265] usbcore: registered new interface driver r8152
10868 10:59:00.569289 <6>[ 18.150313] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10869 10:59:00.575773 <3>[ 18.152946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 10:59:00.582404 <3>[ 18.152962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 10:59:00.592216 <3>[ 18.152970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 10:59:00.599314 <3>[ 18.153574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 10:59:00.609794 <3>[ 18.153586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 10:59:00.616322 <3>[ 18.153592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 10:59:00.623428 <3>[ 18.153600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 10:59:00.633956 <3>[ 18.153606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 10:59:00.640217 <6>[ 18.153794] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10878 10:59:00.646859 <3>[ 18.155323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 10:59:00.657308 <3>[ 18.172544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 10:59:00.664774 <6>[ 18.180163] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10881 10:59:00.674204 <4>[ 18.181844] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10882 10:59:00.677484 <4>[ 18.181844] Fallback method does not support PEC.
10883 10:59:00.687204 <3>[ 18.187961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 10:59:00.694229 <6>[ 18.196037] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10885 10:59:00.705127 <3>[ 18.198567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 10:59:00.711779 <3>[ 18.204082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 10:59:00.721646 <3>[ 18.210114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 10:59:00.728299 <3>[ 18.221884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 10:59:00.735804 <3>[ 18.228497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 10:59:00.742308 <6>[ 18.231443] mc: Linux media interface: v0.10
10891 10:59:00.749218 <4>[ 18.232926] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10892 10:59:00.755820 <4>[ 18.233057] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10893 10:59:00.765683 <3>[ 18.256401] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 10:59:00.772449 <3>[ 18.260984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 10:59:00.782577 <3>[ 18.260998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 10:59:00.786633 <6>[ 18.261971] videodev: Linux video capture interface: v2.00
10897 10:59:00.796027 <6>[ 18.272261] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10898 10:59:00.806371 <6>[ 18.272894] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10899 10:59:00.816015 <3>[ 18.297124] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 10:59:00.822608 <3>[ 18.300192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 10:59:00.832468 <3>[ 18.301428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 10:59:00.838890 <6>[ 18.304102] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10903 10:59:00.845879 <3>[ 18.329462] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 10:59:00.856770 <4>[ 18.331138] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10905 10:59:00.863844 <4>[ 18.331149] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10906 10:59:00.870754 <6>[ 18.340954] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10907 10:59:00.880477 <6>[ 18.350564] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10908 10:59:00.888027 <6>[ 18.353331] pci_bus 0000:00: root bus resource [bus 00-ff]
10909 10:59:00.895232 <3>[ 18.367883] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 10:59:00.902182 <6>[ 18.369750] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10911 10:59:00.908261 <6>[ 18.383731] r8152 2-1.3:1.0 eth0: v1.12.13
10912 10:59:00.911923 <6>[ 18.384114] usbcore: registered new interface driver cdc_ether
10913 10:59:00.922152 <6>[ 18.393979] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10914 10:59:00.929237 <6>[ 18.394205] usbcore: registered new interface driver r8153_ecm
10915 10:59:00.936069 <6>[ 18.416005] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10916 10:59:00.943173 <6>[ 18.419737] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10917 10:59:00.946504 <6>[ 18.420593] Bluetooth: Core ver 2.22
10918 10:59:00.949704 <6>[ 18.420710] NET: Registered PF_BLUETOOTH protocol family
10919 10:59:00.956684 <6>[ 18.420717] Bluetooth: HCI device and connection manager initialized
10920 10:59:00.963513 <6>[ 18.420792] Bluetooth: HCI socket layer initialized
10921 10:59:00.966546 <6>[ 18.420812] Bluetooth: L2CAP socket layer initialized
10922 10:59:00.973574 <6>[ 18.420844] Bluetooth: SCO socket layer initialized
10923 10:59:00.979838 <6>[ 18.435848] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10924 10:59:00.987118 <6>[ 18.443717] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10925 10:59:00.997472 <3>[ 18.451771] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 10:59:01.004037 <3>[ 18.452544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10927 10:59:01.017743 <6>[ 18.455168] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10928 10:59:01.020562 <6>[ 18.460936] pci 0000:00:00.0: supports D1 D2
10929 10:59:01.030222 <3>[ 18.462271] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 10:59:01.037001 <6>[ 18.468271] usbcore: registered new interface driver uvcvideo
10931 10:59:01.044155 <6>[ 18.468928] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10932 10:59:01.050739 <6>[ 18.469454] usbcore: registered new interface driver btusb
10933 10:59:01.060301 <4>[ 18.469652] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10934 10:59:01.067296 <3>[ 18.469669] Bluetooth: hci0: Failed to load firmware file (-2)
10935 10:59:01.070588 <3>[ 18.469675] Bluetooth: hci0: Failed to set up firmware (-2)
10936 10:59:01.080588 <4>[ 18.469680] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10937 10:59:01.087036 <6>[ 18.474207] remoteproc remoteproc0: powering up scp
10938 10:59:01.097060 <4>[ 18.474264] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10939 10:59:01.103732 <3>[ 18.474273] remoteproc remoteproc0: request_firmware failed: -2
10940 10:59:01.110034 <3>[ 18.474277] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10941 10:59:01.116805 <6>[ 18.477036] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10942 10:59:01.126598 <6>[ 18.478863] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10943 10:59:01.133135 <3>[ 18.488314] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 10:59:01.139847 <6>[ 18.491764] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10945 10:59:01.149507 <6>[ 18.736713] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10946 10:59:01.156314 <6>[ 18.736733] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10947 10:59:01.162938 <6>[ 18.736751] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10948 10:59:01.169393 [[0;32m OK [<6>[ 18.759277] pci 0000:01:00.0: supports D1 D2
10949 10:59:01.175679 <6>[ 18.765118] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10950 10:59:01.182215 0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10951 10:59:01.196111 <6>[ 18.783821] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10952 10:59:01.202716 <6>[ 18.790750] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10953 10:59:01.209272 <6>[ 18.798856] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10954 10:59:01.219517 <6>[ 18.806862] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10955 10:59:01.226249 <6>[ 18.814872] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10956 10:59:01.236341 <6>[ 18.822879] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10957 10:59:01.239512 <6>[ 18.830884] pci 0000:00:00.0: PCI bridge to [bus 01]
10958 10:59:01.249416 <6>[ 18.836106] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10959 10:59:01.255929 <6>[ 18.844274] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10960 10:59:01.262205 <6>[ 18.851512] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10961 10:59:01.268872 <6>[ 18.858190] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10962 10:59:01.288592 <5>[ 18.876072] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10963 10:59:01.307702 <5>[ 18.895435] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10964 10:59:01.314058 <4>[ 18.902450] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10965 10:59:01.320992 <6>[ 18.911385] cfg80211: failed to load regulatory.db
10966 10:59:01.327423 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10967 10:59:01.350699 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10968 10:59:01.367093 <6>[ 18.954857] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10969 10:59:01.373515 <6>[ 18.962382] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10970 10:59:01.376858 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10971 10:59:01.398433 <6>[ 18.989188] mt7921e 0000:01:00.0: ASIC revision: 79610010
10972 10:59:01.502611 <4>[ 19.087145] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 10:59:01.558962 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10974 10:59:01.573284 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10975 10:59:01.592487 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10976 10:59:01.623056 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary <4>[ 19.206483] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 10:59:01.623235 Directories[0m.
10978 10:59:01.629634 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10979 10:59:01.648852 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10980 10:59:01.660878 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10981 10:59:01.676658 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10982 10:59:01.696582 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10983 10:59:01.745652 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0<4>[ 19.327538] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 10:59:01.745805 m.
10985 10:59:01.773719 Starting [0;1;39mUser Login Management[0m...
10986 10:59:01.791390 Starting [0;1;39mPermit User Sessions[0m...
10987 10:59:01.810790 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10988 10:59:01.827970 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10989 10:59:01.855978 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10990 10:59:01.868988 <4>[ 19.453476] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 10:59:01.875495 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10992 10:59:01.893744 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10993 10:59:01.913848 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10994 10:59:01.930056 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10995 10:59:01.950052 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10996 10:59:01.969328 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10997 10:59:01.993396 <4>[ 19.578141] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 10:59:02.025414 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10999 10:59:02.048357 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11000 10:59:02.081243
11001 10:59:02.081440
11002 10:59:02.084647 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11003 10:59:02.084759
11004 10:59:02.088246 debian-bullseye-arm64 login: root (automatic login)
11005 10:59:02.088357
11006 10:59:02.088452
11007 10:59:02.115048 <4>[ 19.699624] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 10:59:02.121418 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11009 10:59:02.121550
11010 10:59:02.128492 The programs included with the Debian GNU/Linux system are free software;
11011 10:59:02.134890 the exact distribution terms for each program are described in the
11012 10:59:02.141754 individual files in /usr/share/doc/*/copyright.
11013 10:59:02.141930
11014 10:59:02.144668 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11015 10:59:02.148402 permitted by applicable law.
11016 10:59:02.148855 Matched prompt #10: / #
11018 10:59:02.149214 Setting prompt string to ['/ #']
11019 10:59:02.149349 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11021 10:59:02.149651 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11022 10:59:02.149775 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11023 10:59:02.149877 Setting prompt string to ['/ #']
11024 10:59:02.149968 Forcing a shell prompt, looking for ['/ #']
11026 10:59:02.200238 / #
11027 10:59:02.200466 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 10:59:02.200587 Waiting using forced prompt support (timeout 00:02:30)
11029 10:59:02.205756
11030 10:59:02.206083 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11031 10:59:02.206217 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11032 10:59:02.206349 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11033 10:59:02.206470 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11034 10:59:02.206595 end: 2 depthcharge-action (duration 00:01:37) [common]
11035 10:59:02.206721 start: 3 lava-test-retry (timeout 00:08:00) [common]
11036 10:59:02.206844 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11037 10:59:02.206951 Using namespace: common
11039 10:59:02.307394 / # #
11040 10:59:02.307626 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11041 10:59:02.307788 <4>[ 19.822117] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11042 10:59:02.312808 #
11043 10:59:02.313121 Using /lava-10591023
11045 10:59:02.413487 / # export SHELL=/bin/sh
11046 10:59:02.413724 <4>[ 19.938168] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11047 10:59:02.419012 export SHELL=/bin/sh
11049 10:59:02.519555 / # . /lava-10591023/environment
11050 10:59:02.519821 <4>[ 20.058132] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11051 10:59:02.525073 . /lava-10591023/environment
11053 10:59:02.625700 / # /lava-10591023/bin/lava-test-runner /lava-10591023/0
11054 10:59:02.625908 Test shell timeout: 10s (minimum of the action and connection timeout)
11055 10:59:02.626474 /lava-10591023/bin/lava-test<4>[ 20.178036] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11056 10:59:02.631077 -runner /lava-10591023/0
11057 10:59:02.671487 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.246809] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10591023_1.5.2.3.1>
11058 10:59:02.671661 diatek
11059 10:59:02.671794 + cd /lava-10591023/0/tests/0_igt-kms-mediatek
11060 10:59:02.671893 + cat uuid
11061 10:59:02.671985 + UUID=10591023_1.5.2.3.1
11062 10:59:02.672060 + set +x
11063 10:59:02.672332 Received signal: <STARTRUN> 0_igt-kms-mediatek 10591023_1.5.2.3.1
11064 10:59:02.672405 Starting test lava.0_igt-kms-mediatek (10591023_1.5.2.3.1)
11065 10:59:02.672485 Skipping test definition patterns.
11066 10:59:02.687476 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic km<8>[ 20.277805] <LAVA_SIGNAL_TESTSET START core_auth>
11067 10:59:02.687771 Received signal: <TESTSET> START core_auth
11068 10:59:02.687853 Starting test_set core_auth
11069 10:59:02.690663 s_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11070 10:59:02.709975 <3>[ 20.301371] mt7921e 0000:01:00.0: hardware init failed
11071 10:59:02.720085 <14>[ 20.311315] [IGT] core_auth: executing
11072 10:59:02.726916 IGT-Version: 1.2<14>[ 20.315761] [IGT] core_auth: starting subtest getclient-simple
11073 10:59:02.733178 7.1-g766edf9 (aa<14>[ 20.323359] [IGT] core_auth: exiting, ret=0
11074 10:59:02.736757 rch64) (Linux: 6.1.31 aarch64)
11075 10:59:02.739963 Starting subtest: getclient-simple
11076 10:59:02.746944 Opened devic<8>[ 20.334909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11077 10:59:02.747218 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11079 10:59:02.750013 e: /dev/dri/card0
11080 10:59:02.753201 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11081 10:59:02.770855 <14>[ 20.361741] [IGT] core_auth: executing
11082 10:59:02.777037 IGT-Version: 1.2<14>[ 20.366382] [IGT] core_auth: starting subtest getclient-master-drop
11083 10:59:02.783511 7.1-g766edf9 (aa<14>[ 20.374608] [IGT] core_auth: exiting, ret=0
11084 10:59:02.786850 rch64) (Linux: 6.1.31 aarch64)
11085 10:59:02.790545 Starting subtest: getclient-master-drop
11086 10:59:02.797516 Opened <8>[ 20.385886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11087 10:59:02.797802 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11089 10:59:02.800781 device: /dev/dri/card0
11090 10:59:02.806845 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11091 10:59:02.822118 <14>[ 20.413260] [IGT] core_auth: executing
11092 10:59:02.828434 IGT-Version: 1.2<14>[ 20.417968] [IGT] core_auth: starting subtest basic-auth
11093 10:59:02.835484 7.1-g766edf9 (aa<14>[ 20.425024] [IGT] core_auth: exiting, ret=0
11094 10:59:02.838837 rch64) (Linux: 6.1.31 aarch64)
11095 10:59:02.838924 Opened device: /dev/dri/card0
11096 10:59:02.848538 Starting subtest:<8>[ 20.436452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11097 10:59:02.848627 basic-auth
11098 10:59:02.848867 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11100 10:59:02.851732 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11101 10:59:02.871393 <14>[ 20.462693] [IGT] core_auth: executing
11102 10:59:02.878268 IGT-Version: 1.2<14>[ 20.467182] [IGT] core_auth: starting subtest many-magics
11103 10:59:02.881726 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11104 10:59:02.885008 Opened device: /dev/dri/card0
11105 10:59:02.888092 Starting subtest: many-magics
11106 10:59:02.891260 Reopening device failed after 1020 opens
11107 10:59:02.894950 <14>[ 20.487180] [IGT] core_auth: exiting, ret=0
11108 10:59:02.901064 [1mSubtest many-magics: SUCCESS (0.013s)[0m
11109 10:59:02.908067 <8>[ 20.497980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11110 10:59:02.908336 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11112 10:59:02.914941 <8>[ 20.506182] <LAVA_SIGNAL_TESTSET STOP>
11113 10:59:02.915196 Received signal: <TESTSET> STOP
11114 10:59:02.915270 Closing test_set core_auth
11115 10:59:02.956177 <14>[ 20.547316] [IGT] core_getclient: executing
11116 10:59:02.962519 IGT-Version: 1.2<14>[ 20.552291] [IGT] core_getclient: exiting, ret=0
11117 10:59:02.966417 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11118 10:59:02.969529 Opened device: /dev/dri/card0
11119 10:59:02.976118 S<8>[ 20.564528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11120 10:59:02.976420 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11122 10:59:02.979119 UCCESS (0.006s)
11123 10:59:03.017792 <14>[ 20.609234] [IGT] core_getstats: executing
11124 10:59:03.024973 IGT-Version: 1.2<14>[ 20.614076] [IGT] core_getstats: exiting, ret=0
11125 10:59:03.028189 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11126 10:59:03.031314 Opened device: /dev/dri/card0
11127 10:59:03.037926 S<8>[ 20.626425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11128 10:59:03.038017 UCCESS (0.006s)
11129 10:59:03.038258 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11131 10:59:03.080401 <14>[ 20.671424] [IGT] core_getversion: executing
11132 10:59:03.086622 IGT-Version: 1.2<14>[ 20.676684] [IGT] core_getversion: exiting, ret=0
11133 10:59:03.089878 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11134 10:59:03.093288 Opened device: /dev/dri/card0
11135 10:59:03.099742 S<8>[ 20.688803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11136 10:59:03.100007 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11138 10:59:03.103527 UCCESS (0.006s)
11139 10:59:03.143490 <14>[ 20.734476] [IGT] core_setmaster_vs_auth: executing
11140 10:59:03.150006 IGT-Version: 1.2<14>[ 20.740207] [IGT] core_setmaster_vs_auth: exiting, ret=0
11141 10:59:03.156313 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11142 10:59:03.156403 Opened device: /dev/dri/card0
11143 10:59:03.166420 S<8>[ 20.753238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11144 10:59:03.166531 UCCESS (0.007s)
11145 10:59:03.166775 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11147 10:59:03.191246 <8>[ 20.782274] <LAVA_SIGNAL_TESTSET START drm_read>
11148 10:59:03.191575 Received signal: <TESTSET> START drm_read
11149 10:59:03.191648 Starting test_set drm_read
11150 10:59:03.214101 <14>[ 20.805037] [IGT] drm_read: executing
11151 10:59:03.220375 IGT-Version: 1.2<14>[ 20.809836] [IGT] drm_read: exiting, ret=77
11152 10:59:03.223965 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11153 10:59:03.227048 Opened device: /dev/dri/card0
11154 10:59:03.233786 N<8>[ 20.821117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11155 10:59:03.234084 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11157 10:59:03.236769 o KMS driver or no outputs, pipes: 8, outputs: 0
11158 10:59:03.240407 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11159 10:59:03.255590 <14>[ 20.846434] [IGT] drm_read: executing
11160 10:59:03.261733 IGT-Version: 1.2<14>[ 20.851111] [IGT] drm_read: exiting, ret=77
11161 10:59:03.264849 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11162 10:59:03.268076 Opened device: /dev/dri/card0
11163 10:59:03.275045 N<8>[ 20.862447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11164 10:59:03.275308 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11166 10:59:03.278192 o KMS driver or no outputs, pipes: 8, outputs: 0
11167 10:59:03.281560 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11168 10:59:03.296153 <14>[ 20.887496] [IGT] drm_read: executing
11169 10:59:03.302758 IGT-Version: 1.2<14>[ 20.892226] [IGT] drm_read: exiting, ret=77
11170 10:59:03.306165 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11171 10:59:03.309461 Opened device: /dev/dri/card0
11172 10:59:03.315797 N<8>[ 20.903418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11173 10:59:03.316055 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11175 10:59:03.319595 o KMS driver or no outputs, pipes: 8, outputs: 0
11176 10:59:03.322823 [1mSubtest empty-block: SKIP (0.000s)[0m
11177 10:59:03.338384 <14>[ 20.929729] [IGT] drm_read: executing
11178 10:59:03.345147 IGT-Version: 1.2<14>[ 20.934596] [IGT] drm_read: exiting, ret=77
11179 10:59:03.348113 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11180 10:59:03.351897 Opened device: /dev/dri/card0
11181 10:59:03.358639 N<8>[ 20.945874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11182 10:59:03.358899 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11184 10:59:03.361772 o KMS driver or no outputs, pipes: 8, outputs: 0
11185 10:59:03.365035 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11186 10:59:03.380366 <14>[ 20.971370] [IGT] drm_read: executing
11187 10:59:03.386827 IGT-Version: 1.2<14>[ 20.976178] [IGT] drm_read: exiting, ret=77
11188 10:59:03.390062 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11189 10:59:03.393783 Opened device: /dev/dri/card0
11190 10:59:03.400165 N<8>[ 20.987103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11191 10:59:03.400426 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11193 10:59:03.403833 o KMS driver or no outputs, pipes: 8, outputs: 0
11194 10:59:03.406580 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11195 10:59:03.421976 <14>[ 21.013091] [IGT] drm_read: executing
11196 10:59:03.428554 IGT-Version: 1.2<14>[ 21.017659] [IGT] drm_read: exiting, ret=77
11197 10:59:03.431814 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11198 10:59:03.434712 Opened device: /dev/dri/card0
11199 10:59:03.441200 N<8>[ 21.029001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11200 10:59:03.441462 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11202 10:59:03.445060 o KMS driver or no outputs, pipes: 8, outputs: 0
11203 10:59:03.451300 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11204 10:59:03.465028 <14>[ 21.056150] [IGT] drm_read: executing
11205 10:59:03.471637 IGT-Version: 1.2<14>[ 21.060828] [IGT] drm_read: exiting, ret=77
11206 10:59:03.474559 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11207 10:59:03.478155 Opened device: /dev/dri/card0
11208 10:59:03.484711 N<8>[ 21.072219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11209 10:59:03.484974 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11211 10:59:03.491485 o KMS driver or no outputs, pipe<8>[ 21.082474] <LAVA_SIGNAL_TESTSET STOP>
11212 10:59:03.491588 s: 8, outputs: 0
11213 10:59:03.491852 Received signal: <TESTSET> STOP
11214 10:59:03.491933 Closing test_set drm_read
11215 10:59:03.497914 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11216 10:59:03.518026 <8>[ 21.109254] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11217 10:59:03.518288 Received signal: <TESTSET> START kms_addfb_basic
11218 10:59:03.518359 Starting test_set kms_addfb_basic
11219 10:59:03.541714 <14>[ 21.132792] [IGT] kms_addfb_basic: executing
11220 10:59:03.548190 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11221 10:59:03.555201 <14>[ 21.142457] [IGT] kms_addfb_basic: starting subtest unused-handle
11222 10:59:03.555320 Opened device: /dev/dri/card0
11223 10:59:03.558269 Starting subtest: unused-handle
11224 10:59:03.565027 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11225 10:59:03.568070 Test requirement<14>[ 21.160125] [IGT] kms_addfb_basic: exiting, ret=0
11226 10:59:03.574688 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11227 10:59:03.584478 Test requirem<8>[ 21.172079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11228 10:59:03.584579 ent: is_i915_device(fd)
11229 10:59:03.584820 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11231 10:59:03.594612 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11232 10:59:03.597786 Test requirement: is_i915_device(fd)
11233 10:59:03.601170 No KMS driver or no outputs, pipes: 8, outputs: 0
11234 10:59:03.604893 <14>[ 21.197468] [IGT] kms_addfb_basic: executing
11235 10:59:03.611123 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11236 10:59:03.617718 <14>[ 21.206897] [IGT] kms_addfb_basic: starting subtest unused-pitches
11237 10:59:03.620819 Opened device: /dev/dri/card0
11238 10:59:03.624611 Starting subtest: unused-pitches
11239 10:59:03.627852 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11240 10:59:03.634783 Test requirement<14>[ 21.224554] [IGT] kms_addfb_basic: exiting, ret=0
11241 10:59:03.641162 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11242 10:59:03.647617 Test requirem<8>[ 21.236966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11243 10:59:03.647892 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11245 10:59:03.650701 ent: is_i915_device(fd)
11246 10:59:03.657814 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11247 10:59:03.660975 Test requirement: is_i915_device(fd)
11248 10:59:03.664128 No KMS driver or no outputs, pipes: 8, outputs: 0
11249 10:59:03.670658 <14>[ 21.262231] [IGT] kms_addfb_basic: executing
11250 10:59:03.677240 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11251 10:59:03.683985 <14>[ 21.271772] [IGT] kms_addfb_basic: starting subtest unused-offsets
11252 10:59:03.684111 Opened device: /dev/dri/card0
11253 10:59:03.687095 Starting subtest: unused-offsets
11254 10:59:03.693888 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11255 10:59:03.697042 Test requirem<14>[ 21.289312] [IGT] kms_addfb_basic: exiting, ret=0
11256 10:59:03.703909 ent not met in function igt_require_i915, file ../lib/drmtest.c:721:
11257 10:59:03.714030 Test requi<8>[ 21.301346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11258 10:59:03.714160 rement: is_i915_device(fd)
11259 10:59:03.714442 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11261 10:59:03.723700 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11262 10:59:03.727020 Test requirement: is_i915_device(fd)
11263 10:59:03.730514 No KMS driver or no outputs, pipes: 8, outputs: 0
11264 10:59:03.736949 <14>[ 21.327826] [IGT] kms_addfb_basic: executing
11265 10:59:03.740835 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11266 10:59:03.747138 <14>[ 21.337510] [IGT] kms_addfb_basic: starting subtest unused-modifier
11267 10:59:03.750575 Opened device: /dev/dri/card0
11268 10:59:03.753769 Starting subtest: unused-modifier
11269 10:59:03.760249 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11270 10:59:03.763538 Test requir<14>[ 21.355113] [IGT] kms_addfb_basic: exiting, ret=0
11271 10:59:03.770285 ement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11272 10:59:03.780067 Test req<8>[ 21.367169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11273 10:59:03.780199 uirement: is_i915_device(fd)
11274 10:59:03.780480 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11276 10:59:03.789952 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11277 10:59:03.793751 Test requirement: is_i915_device(fd)
11278 10:59:03.796990 No KMS driver or no outputs, pipes: 8, outputs: 0
11279 10:59:03.803410 <14>[ 21.393836] [IGT] kms_addfb_basic: executing
11280 10:59:03.806548 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11281 10:59:03.813397 <14>[ 21.403703] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11282 10:59:03.816607 Opened device: /dev/dri/card0
11283 10:59:03.820205 Starting subtest: clobberred-modifier
11284 10:59:03.830016 Test requirement not met in function igt_require_i915, fil<14>[ 21.421426] [IGT] kms_addfb_basic: exiting, ret=77
11285 10:59:03.833331 e ../lib/drmtest.c:721:
11286 10:59:03.836511 Test requirement: is_i915_device(fd)
11287 10:59:03.846726 [1mSubtest clobb<8>[ 21.433674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11288 10:59:03.847038 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11290 10:59:03.849905 erred-modifier: SKIP (0.000s)[0m
11291 10:59:03.856593 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11292 10:59:03.859751 Test requirement: is_i915_device(fd)
11293 10:59:03.869966 Test requirement not met in function igt_require_i91<14>[ 21.459339] [IGT] kms_addfb_basic: executing
11294 10:59:03.870216 5, file ../lib/drmtest.c:721:
11295 10:59:03.882784 Test requirement: is_i915_device(<14>[ 21.469565] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11296 10:59:03.882931 fd)
11297 10:59:03.886071 No KMS driver or no outputs, pipes: 8, outputs: 0
11298 10:59:03.892970 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11299 10:59:03.896042 Opened d<14>[ 21.488130] [IGT] kms_addfb_basic: exiting, ret=77
11300 10:59:03.899182 evice: /dev/dri/card0
11301 10:59:03.902525 Starting subtest: invalid-smem-bo-on-discrete
11302 10:59:03.912818 Test requi<8>[ 21.500493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11303 10:59:03.913150 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11305 10:59:03.919345 rement not met in function igt_require_intel, file ../lib/drmtest.c:716:
11306 10:59:03.922512 Test requirement: is_intel_device(fd)
11307 10:59:03.929675 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11308 10:59:03.935732 Test requirement not met in functio<14>[ 21.526619] [IGT] kms_addfb_basic: executing
11309 10:59:03.939065 n igt_require_i915, file ../lib/drmtest.c:721:
11310 10:59:03.949386 Test requirement<14>[ 21.536959] [IGT] kms_addfb_basic: starting subtest legacy-format
11311 10:59:03.949508 : is_i915_device(fd)
11312 10:59:03.955703 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11313 10:59:03.958995 Test requirement: is_i915_device(fd)
11314 10:59:03.965906 No KMS driver or no outputs, pipes: 8, outputs: 0
11315 10:59:03.969202 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11316 10:59:03.975759 Opened device:<14>[ 21.567245] [IGT] kms_addfb_basic: exiting, ret=0
11317 10:59:03.978753 /dev/dri/card0
11318 10:59:03.982215 Starting subtest: legacy-format
11319 10:59:03.989161 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11321 10:59:03.992132 Successfully fuzzed 10000 {bpp<8>[ 21.578775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11322 10:59:03.992246 , depth} variations
11323 10:59:03.995249 [1mSubtest legacy-format: SUCCESS (0.013s)[0m
11324 10:59:04.005619 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11325 10:59:04.008716 Test requirement: is_i915_device(fd)
11326 10:59:04.012023 Test requirement <14>[ 21.603869] [IGT] kms_addfb_basic: executing
11327 10:59:04.018417 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11328 10:59:04.028714 Test requirement: is_i915_devi<14>[ 21.617108] [IGT] kms_addfb_basic: starting subtest no-handle
11329 10:59:04.028842 ce(fd)
11330 10:59:04.031846 No KMS driver or no outputs, pipes: 8, outputs: 0
11331 10:59:04.042330 IGT-Version: 1.27.1-g766edf9 (aarch64<14>[ 21.631475] [IGT] kms_addfb_basic: exiting, ret=0
11332 10:59:04.042453 ) (Linux: 6.1.31 aarch64)
11333 10:59:04.045423 Opened device: /dev/dri/card0
11334 10:59:04.055406 Starting subtest: no-h<8>[ 21.643711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11335 10:59:04.055527 andle
11336 10:59:04.055806 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11338 10:59:04.058527 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11339 10:59:04.064974 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11340 10:59:04.068370 Test requirement: is_i915_device(fd)
11341 10:59:04.078718 Test requirement not met in functio<14>[ 21.668439] [IGT] kms_addfb_basic: executing
11342 10:59:04.081990 n igt_require_i915, file ../lib/drmtest.c:721:
11343 10:59:04.085179 Test requirement: is_i915_device(fd)
11344 10:59:04.091833 No KMS dri<14>[ 21.681276] [IGT] kms_addfb_basic: starting subtest basic
11345 10:59:04.095268 ver or no outputs, pipes: 8, outputs: 0
11346 10:59:04.104898 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 a<14>[ 21.695394] [IGT] kms_addfb_basic: exiting, ret=0
11347 10:59:04.105020 arch64)
11348 10:59:04.108772 Opened device: /dev/dri/card0
11349 10:59:04.111820 Starting subtest: basic
11350 10:59:04.118574 [1mSubtest bas<8>[ 21.707072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11351 10:59:04.118870 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11353 10:59:04.121720 ic: SUCCESS (0.000s)[0m
11354 10:59:04.128022 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11355 10:59:04.131437 Test requirement: is_i915_device(fd)
11356 10:59:04.141758 Test requirement not met in function igt_require_i915, file .<14>[ 21.731465] [IGT] kms_addfb_basic: executing
11357 10:59:04.141880 ./lib/drmtest.c:721:
11358 10:59:04.144723 Test requirement: is_i915_device(fd)
11359 10:59:04.154565 No KMS driver or no outputs, pipes: <14>[ 21.744788] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11360 10:59:04.157854 8, outputs: 0
11361 10:59:04.161590 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11362 10:59:04.167807 Opened device: /d<14>[ 21.759460] [IGT] kms_addfb_basic: exiting, ret=0
11363 10:59:04.171117 ev/dri/card0
11364 10:59:04.171234 Starting subtest: bad-pitch-0
11365 10:59:04.181298 [1mSubtest bad-pitch-0: SUCCESS (0<8>[ 21.771641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11366 10:59:04.181599 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11368 10:59:04.184506 .000s)[0m
11369 10:59:04.191572 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11370 10:59:04.194591 Test requirement: is_i915_device(fd)
11371 10:59:04.201386 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11372 10:59:04.207857 Test req<14>[ 21.797523] [IGT] kms_addfb_basic: executing
11373 10:59:04.211102 uirement: is_i915_device(fd)
11374 10:59:04.214307 No KMS driver or no outputs, pipes: 8, outputs: 0
11375 10:59:04.221186 IGT-Version: 1.<14>[ 21.811140] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11376 10:59:04.224443 27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11377 10:59:04.227682 Opened device: /dev/dri/card0
11378 10:59:04.234356 Starting subtest<14>[ 21.825566] [IGT] kms_addfb_basic: exiting, ret=0
11379 10:59:04.237667 : bad-pitch-32
11380 10:59:04.240698 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11381 10:59:04.247358 Test requirement<8>[ 21.837816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11382 10:59:04.247660 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11384 10:59:04.254290 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11385 10:59:04.257202 Test requirement: is_i915_device(fd)
11386 10:59:04.264146 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11387 10:59:04.274276 Test requirement: is_i915_device(fd)<14>[ 21.863634] [IGT] kms_addfb_basic: executing
11388 10:59:04.274418
11389 10:59:04.277021 No KMS driver or no outputs, pipes: 8, outputs: 0
11390 10:59:04.287014 IGT-Version: 1.27.1-g766edf9 (aarch64) (Lin<14>[ 21.877116] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11391 10:59:04.290353 ux: 6.1.31 aarch64)
11392 10:59:04.290469 Opened device: /dev/dri/card0
11393 10:59:04.293618 Starting subtest: bad-pitch-63
11394 10:59:04.300880 [1mSubtest <14>[ 21.891785] [IGT] kms_addfb_basic: exiting, ret=0
11395 10:59:04.304232 bad-pitch-63: SUCCESS (0.000s)[0m
11396 10:59:04.313760 Test requirement not met in function igt_req<8>[ 21.903598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11397 10:59:04.314071 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11399 10:59:04.317487 uire_i915, file ../lib/drmtest.c:721:
11400 10:59:04.320685 Test requirement: is_i915_device(fd)
11401 10:59:04.330339 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11402 10:59:04.333527 Test requirement: is_i915_device(fd)
11403 10:59:04.337534 No KMS dri<14>[ 21.928966] [IGT] kms_addfb_basic: executing
11404 10:59:04.340630 ver or no outputs, pipes: 8, outputs: 0
11405 10:59:04.353979 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 a<14>[ 21.941655] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11406 10:59:04.354108 arch64)
11407 10:59:04.356961 Opened device: /dev/dri/card0
11408 10:59:04.360699 Starting subtest: bad-pitch-128
11409 10:59:04.367467 [1mSubtest bad-pitch-1<14>[ 21.956619] [IGT] kms_addfb_basic: exiting, ret=0
11410 10:59:04.367584 28: SUCCESS (0.000s)[0m
11411 10:59:04.380302 Test requirement not met in function igt_require_i915,<8>[ 21.968629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11412 10:59:04.380572 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11414 10:59:04.383743 file ../lib/drmtest.c:721:
11415 10:59:04.386981 Test requirement: is_i915_device(fd)
11416 10:59:04.393439 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11417 10:59:04.397049 Test requirement: is_i915_device(fd)
11418 10:59:04.403789 No KMS driver or no outputs, pipes: <14>[ 21.994624] [IGT] kms_addfb_basic: executing
11419 10:59:04.406855 8, outputs: 0
11420 10:59:04.410422 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11421 10:59:04.420412 Opened device: /<14>[ 22.008343] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11422 10:59:04.420541 dev/dri/card0
11423 10:59:04.423577 Starting subtest: bad-pitch-256
11424 10:59:04.433769 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m<14>[ 22.022769] [IGT] kms_addfb_basic: exiting, ret=0
11425 10:59:04.433905
11426 10:59:04.446317 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<8>[ 22.034886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11427 10:59:04.446450 21:
11428 10:59:04.446733 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11430 10:59:04.450195 Test requirement: is_i915_device(fd)
11431 10:59:04.456536 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11432 10:59:04.459724 Test requirement: is_i915_device(fd)
11433 10:59:04.469612 No KMS driver or no outputs, pipes: 8, outpu<14>[ 22.060087] [IGT] kms_addfb_basic: executing
11434 10:59:04.469758 ts: 0
11435 10:59:04.476531 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11436 10:59:04.483171 Opened device: /<14>[ 22.072772] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11437 10:59:04.483295 dev/dri/card0
11438 10:59:04.486495 Starting subtest: bad-pitch-1024
11439 10:59:04.496753 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[<14>[ 22.087298] [IGT] kms_addfb_basic: exiting, ret=0
11440 10:59:04.496879 0m
11441 10:59:04.509342 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<8>[ 22.099247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11442 10:59:04.509498 :721:
11443 10:59:04.509777 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11445 10:59:04.512592 Test requirement: is_i915_device(fd)
11446 10:59:04.522588 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11447 10:59:04.526360 Test requirement: is_i915_device(fd)
11448 10:59:04.529258 No KMS driver or no outputs, pipes: 8, outputs: 0
11449 10:59:04.533010 <14>[ 22.125178] [IGT] kms_addfb_basic: executing
11450 10:59:04.539971 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11451 10:59:04.543186 Opened device: /dev/dri/card0
11452 10:59:04.549667 <14>[ 22.138231] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11453 10:59:04.552607 Starting subtest: bad-pitch-999
11454 10:59:04.556334 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11455 10:59:04.562499 Test requireme<14>[ 22.152802] [IGT] kms_addfb_basic: exiting, ret=0
11456 10:59:04.569361 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11457 10:59:04.576132 Test requir<8>[ 22.164905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11458 10:59:04.576448 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11460 10:59:04.579071 ement: is_i915_device(fd)
11461 10:59:04.585974 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11462 10:59:04.589356 Test requirement: is_i915_device(fd)
11463 10:59:04.592675 No KMS driver or no outputs, pipes: 8, outputs: 0
11464 10:59:04.599909 <14>[ 22.191223] [IGT] kms_addfb_basic: executing
11465 10:59:04.606537 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11466 10:59:04.606651 Opened device: /dev/dri/card0
11467 10:59:04.613000 <14>[ 22.203367] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11468 10:59:04.616243 Starting subtest: bad-pitch-65536
11469 10:59:04.622721 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11470 10:59:04.629715 Test requi<14>[ 22.218353] [IGT] kms_addfb_basic: exiting, ret=0
11471 10:59:04.632477 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11472 10:59:04.642706 Test re<8>[ 22.230409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11473 10:59:04.643005 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11475 10:59:04.646058 quirement: is_i915_device(fd)
11476 10:59:04.652578 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11477 10:59:04.655771 Test requirement: is_i915_device(fd)
11478 10:59:04.658837 No KMS driver or no outputs, pipes: 8, outputs: 0
11479 10:59:04.665537 <14>[ 22.255876] [IGT] kms_addfb_basic: executing
11480 10:59:04.669273 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11481 10:59:04.672555 Opened device: /dev/dri/card0
11482 10:59:04.682079 <14>[ 22.270536] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11483 10:59:04.685535 Starting subtest: invalid-get-prop-any
11484 10:59:04.692115 [1mSubtest invalid-get-<14>[ 22.282834] [IGT] kms_addfb_basic: exiting, ret=0
11485 10:59:04.695388 prop-any: SUCCESS (0.000s)[0m
11486 10:59:04.705431 Test requirement not met in function igt_require<8>[ 22.294421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11487 10:59:04.705727 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11489 10:59:04.708678 _i915, file ../lib/drmtest.c:721:
11490 10:59:04.712565 Test requirement: is_i915_device(fd)
11491 10:59:04.718578 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11492 10:59:04.721875 Test requirement: is_i915_device(fd)
11493 10:59:04.728683 No KMS driver <14>[ 22.320217] [IGT] kms_addfb_basic: executing
11494 10:59:04.732379 or no outputs, pipes: 8, outputs: 0
11495 10:59:04.738935 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11496 10:59:04.745332 Opened device: /dev/dri/car<14>[ 22.335471] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11497 10:59:04.749126 d0
11498 10:59:04.752093 Starting subtest: invalid-get-prop
11499 10:59:04.758663 [1mSubtest invalid-get-prop<14>[ 22.349106] [IGT] kms_addfb_basic: exiting, ret=0
11500 10:59:04.758777 : SUCCESS (0.000s)[0m
11501 10:59:04.772447 Test requirement not met in function igt_require_i915, f<8>[ 22.360652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11502 10:59:04.772759 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11504 10:59:04.775321 ile ../lib/drmtest.c:721:
11505 10:59:04.778482 Test requirement: is_i915_device(fd)
11506 10:59:04.785589 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11507 10:59:04.788773 Test requirement: is_i915_device(fd)
11508 10:59:04.795465 No KMS driver or no ou<14>[ 22.386045] [IGT] kms_addfb_basic: executing
11509 10:59:04.798448 tputs, pipes: 8, outputs: 0
11510 10:59:04.802197 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11511 10:59:04.805670 Opened device: /dev/dri/card0
11512 10:59:04.812195 <14>[ 22.401420] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11513 10:59:04.815579 Starting subtest: invalid-set-prop-any
11514 10:59:04.825534 [1mSubtest invalid-set-<14>[ 22.414653] [IGT] kms_addfb_basic: exiting, ret=0
11515 10:59:04.825619 prop-any: SUCCESS (0.000s)[0m
11516 10:59:04.838142 Test requirement not met in function igt_require<8>[ 22.426309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11517 10:59:04.838405 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11519 10:59:04.841691 _i915, file ../lib/drmtest.c:721:
11520 10:59:04.844759 Test requirement: is_i915_device(fd)
11521 10:59:04.851378 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11522 10:59:04.855090 Test requirement: is_i915_device(fd)
11523 10:59:04.861790 No KMS driver <14>[ 22.452195] [IGT] kms_addfb_basic: executing
11524 10:59:04.864911 or no outputs, pipes: 8, outputs: 0
11525 10:59:04.868280 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11526 10:59:04.877888 Opened devi<14>[ 22.467103] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11527 10:59:04.877977 ce: /dev/dri/card0
11528 10:59:04.881650 Starting subtest: invalid-set-prop
11529 10:59:04.887894 [1mSubt<14>[ 22.479153] [IGT] kms_addfb_basic: exiting, ret=0
11530 10:59:04.891216 est invalid-set-prop: SUCCESS (0.000s)[0m
11531 10:59:04.901296 Test requirement not met in function<8>[ 22.490940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11532 10:59:04.901559 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11534 10:59:04.904612 igt_require_i915, file ../lib/drmtest.c:721:
11535 10:59:04.908285 Test requirement: is_i915_device(fd)
11536 10:59:04.918588 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11537 10:59:04.921313 Test requirement: is_i915_device(fd)
11538 10:59:04.925237 No<14>[ 22.516353] [IGT] kms_addfb_basic: executing
11539 10:59:04.928678 KMS driver or no outputs, pipes: 8, outputs: 0
11540 10:59:04.935164 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11541 10:59:04.938521 Opened device: /dev/dri/card0
11542 10:59:04.944715 <14>[ 22.533674] [IGT] kms_addfb_basic: starting subtest master-rmfb
11543 10:59:04.948334 Starting subtest: master-rmfb
11544 10:59:04.954520 [1mSubtest maste<14>[ 22.543266] [IGT] kms_addfb_basic: exiting, ret=0
11545 10:59:04.954604 r-rmfb: SUCCESS (0.000s)[0m
11546 10:59:04.967943 Test requirement not met in function igt_require_i<8>[ 22.555520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11547 10:59:04.968218 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11549 10:59:04.970988 915, file ../lib/drmtest.c:721:
11550 10:59:04.974709 Test requirement: is_i915_device(fd)
11551 10:59:04.980986 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11552 10:59:04.984266 Test requirement: is_i915_device(fd)
11553 10:59:04.991117 No KMS driver or<14>[ 22.580736] [IGT] kms_addfb_basic: executing
11554 10:59:04.994378 no outputs, pipes: 8, outputs: 0
11555 10:59:04.997631 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11556 10:59:05.000758 Opened device: /dev/dri/card0
11557 10:59:05.012118 <14>[ 22.600487] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11558 10:59:05.019018 Starting subtest<14>[ 22.608414] [IGT] kms_addfb_basic: exiting, ret=0
11559 10:59:05.019105 : addfb25-modifier-no-flag
11560 10:59:05.032069 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.620501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11561 10:59:05.032178 s)[0m
11562 10:59:05.032457 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11564 10:59:05.041927 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11565 10:59:05.045129 Test requirement: is_i915_device(fd)
11566 10:59:05.055230 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.646667] [IGT] kms_addfb_basic: executing
11567 10:59:05.055364 1:
11568 10:59:05.058831 Test requirement: is_i915_device(fd)
11569 10:59:05.065014 No KMS driver or no outputs, pipes: 8, outputs: 0
11570 10:59:05.068208 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11571 10:59:05.078809 Opened device: /dev<14>[ 22.666542] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11572 10:59:05.078917 /dri/card0
11573 10:59:05.081877 Starting subtest: addfb25-bad-modifier
11574 10:59:05.095213 (kms_addfb_basic:427) CRITICAL: Test assertion failure function addfb25_<14>[ 22.684336] [IGT] kms_addfb_basic: exiting, ret=98
11575 10:59:05.098494 tests, file ../tests/kms_addfb_basic.c:662:
11576 10:59:05.108258 (kms_addfb_basic:427) CRITICAL: Fai<8>[ 22.697022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11577 10:59:05.108609 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11579 10:59:05.124688 led assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11580 10:59:05.127994 (kms_addfb_basic:427) CRITICAL: error: 0 != -1
11581 10:59:05.131264 Stack<14>[ 22.723079] [IGT] kms_addfb_basic: executing
11582 10:59:05.134674 trace:
11583 10:59:05.137983 #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11584 10:59:05.141642 #1 [<unknown>+0xc3b947e0]
11585 10:59:05.141750 #2 [<unknown>+0xc3b96278]
11586 10:59:05.144900 #3 [<unknown>+0xc3b9167c]
11587 10:59:05.148052 #4 [__libc_start_main+0xe8]
11588 10:59:05.151496 <14>[ 22.744019] [IGT] kms_addfb_basic: exiting, ret=77
11589 10:59:05.154544 #5 [<unknown>+0xc3b916b4]
11590 10:59:05.158203 #6 [<unknown>+0xc3b916b4]
11591 10:59:05.167919 Subtest addfb25-bad-mo<8>[ 22.756052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11592 10:59:05.168205 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11594 10:59:05.171049 difier failed.
11595 10:59:05.171169 **** DEBUG ****
11596 10:59:05.181001 (kms_addfb_basic:427) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11597 10:59:05.190980 (kms_addfb_basic:427) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms<14>[ 22.783635] [IGT] kms_addfb_basic: executing
11598 10:59:05.194270 _addfb_basic.c:662:
11599 10:59:05.214157 (kms_addfb_basic:427) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct <14>[ 22.804201] [IGT] kms_addfb_basic: exiting, ret=77
11600 10:59:05.217528 drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11601 10:59:05.227682 (kms_addfb_basic:427) CRITICA<8>[ 22.816086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11602 10:59:05.227964 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11604 10:59:05.230728 L: error: 0 != -1
11605 10:59:05.233874 (kms_addfb_basic:427) igt_core-INFO: Stack trace:
11606 10:59:05.240625 (kms_addfb_basic:427) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11607 10:59:05.247226 (kms_addfb_basic:427) igt_core-INFO: #1 [<unknown>+0xc3b947e0]
11608 10:59:05.250504 (k<14>[ 22.842883] [IGT] kms_addfb_basic: executing
11609 10:59:05.257059 ms_addfb_basic:427) igt_core-INFO: #2 [<unknown>+0xc3b96278]
11610 10:59:05.264076 (kms_addfb_basic:427) igt_core-INFO: #3 [<unknown>+0xc3b9167c]
11611 10:59:05.273557 (kms_addfb_basic:427) igt_core-INFO: #4 [__l<14>[ 22.863591] [IGT] kms_addfb_basic: exiting, ret=77
11612 10:59:05.273667 ibc_start_main+0xe8]
11613 10:59:05.287011 (kms_addfb_basic:427) igt_core-INFO: #5 [<unknown>+0xc3b<8>[ 22.875321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11614 10:59:05.287304 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11616 10:59:05.290466 916b4]
11617 10:59:05.293629 (kms_addfb_basic:427) igt_core-INFO: #6 [<unknown>+0xc3b916b4]
11618 10:59:05.297175 **** END ****
11619 10:59:05.300738 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11620 10:59:05.314096 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721<14>[ 22.903462] [IGT] kms_addfb_basic: executing
11621 10:59:05.314182 :
11622 10:59:05.317126 Test requirement: is_i915_device(fd)
11623 10:59:05.323578 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11624 10:59:05.326753 Test requirement: is_i915_device(fd)
11625 10:59:05.333304 No KMS driver <14>[ 22.923854] [IGT] kms_addfb_basic: exiting, ret=77
11626 10:59:05.336882 or no outputs, pipes: 8, outputs: 0
11627 10:59:05.346717 IGT-Version: 1.27.1-g766edf9 (aarch64) (Lin<8>[ 22.935519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11628 10:59:05.347000 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11630 10:59:05.350111 ux: 6.1.31 aarch64)
11631 10:59:05.353195 Opened device: /dev/dri/card0
11632 10:59:05.360526 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11633 10:59:05.363155 Test requirement: is_i915_device(fd)
11634 10:59:05.370207 [1mSubtest addfb25-x-tiled-mismatc<14>[ 22.961464] [IGT] kms_addfb_basic: executing
11635 10:59:05.373262 h-legacy: SKIP (0.000s)[0m
11636 10:59:05.380055 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11637 10:59:05.383472 Test requirement: is_i915_device(fd)
11638 10:59:05.390252 No KMS driver or no output<14>[ 22.981609] [IGT] kms_addfb_basic: exiting, ret=77
11639 10:59:05.393155 s, pipes: 8, outputs: 0
11640 10:59:05.406567 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 a<8>[ 22.993797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11641 10:59:05.406654 arch64)
11642 10:59:05.406932 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11644 10:59:05.410139 Opened device: /dev/dri/card0
11645 10:59:05.416413 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11646 10:59:05.419763 Test requirement: is_i915_device(fd)
11647 10:59:05.423144 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11648 10:59:05.430082 Test req<14>[ 23.020391] [IGT] kms_addfb_basic: executing
11649 10:59:05.436504 uirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11650 10:59:05.439718 Test requirement: is_i915_device(fd)
11651 10:59:05.442878 No KMS driver or no outputs, pipes: 8, outputs: 0
11652 10:59:05.449505 IGT-Version:<14>[ 23.041358] [IGT] kms_addfb_basic: exiting, ret=77
11653 10:59:05.456685 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11654 10:59:05.463380 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11656 10:59:05.466367 Opened device: /dev/dri/card<8>[ 23.052743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11657 10:59:05.466469 0
11658 10:59:05.473023 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11659 10:59:05.476020 Test requirement: is_i915_device(fd)
11660 10:59:05.482818 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11661 10:59:05.486061 Test requirement n<14>[ 23.078391] [IGT] kms_addfb_basic: executing
11662 10:59:05.492591 ot met in function igt_require_i915, file ../lib/drmtest.c:721:
11663 10:59:05.496266 Test requirement: is_i915_device(fd)
11664 10:59:05.499260 No KMS driver or no outputs, pipes: 8, outputs: 0
11665 10:59:05.509244 IGT-Version: 1.27.1-g7<14>[ 23.098837] [IGT] kms_addfb_basic: exiting, ret=77
11666 10:59:05.512921 66edf9 (aarch64) (Linux: 6.1.31 aarch64)
11667 10:59:05.513006 Opened device: /dev/dri/card0
11668 10:59:05.522935 Test re<8>[ 23.110411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11669 10:59:05.523221 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11671 10:59:05.529041 quirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11672 10:59:05.532635 Test requirement: is_i915_device(fd)
11673 10:59:05.539201 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11674 10:59:05.545845 Test requir<14>[ 23.136529] [IGT] kms_addfb_basic: executing
11675 10:59:05.549014 ement: is_i915_device(fd)
11676 10:59:05.552188 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11677 10:59:05.555501 No KMS driver or no outputs, pipes: 8, outputs: 0
11678 10:59:05.565366 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux<14>[ 23.156799] [IGT] kms_addfb_basic: exiting, ret=77
11679 10:59:05.569231 : 6.1.31 aarch64)
11680 10:59:05.569366 Opened device: /dev/dri/card0
11681 10:59:05.579028 Test requirement not met in fu<8>[ 23.168034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11682 10:59:05.579304 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11684 10:59:05.585489 nction igt_require_i915, file ../lib/drmtest.c:721:
11685 10:59:05.588843 Test requirement: is_i915_device(fd)
11686 10:59:05.595530 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11687 10:59:05.601997 Test requirement: is_i915_device(f<14>[ 23.193950] [IGT] kms_addfb_basic: executing
11688 10:59:05.602112 d)
11689 10:59:05.608883 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11690 10:59:05.612097 No KMS driver or no outputs, pipes: 8, outputs: 0
11691 10:59:05.618319 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11692 10:59:05.621824 <14>[ 23.213656] [IGT] kms_addfb_basic: exiting, ret=77
11693 10:59:05.621936
11694 10:59:05.624872 Opened device: /dev/dri/card0
11695 10:59:05.635031 Test requirement not met in function igt_require<8>[ 23.225229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11696 10:59:05.635322 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11698 10:59:05.638773 _i915, file ../lib/drmtest.c:721:
11699 10:59:05.641843 Test requirement: is_i915_device(fd)
11700 10:59:05.648354 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11701 10:59:05.651759 Test requirement: is_i915_device(fd)
11702 10:59:05.658533 [1mSubtest ti<14>[ 23.249988] [IGT] kms_addfb_basic: executing
11703 10:59:05.661852 le-pitch-mismatch: SKIP (0.000s)[0m
11704 10:59:05.665065 No KMS driver or no outputs, pipes: 8, outputs: 0
11705 10:59:05.671821 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11706 10:59:05.678242 Opened device: /dev/dri<14>[ 23.270385] [IGT] kms_addfb_basic: exiting, ret=77
11707 10:59:05.678371 /card0
11708 10:59:05.691958 Test requirement not met in function igt_require_i915, file ../lib/drmte<8>[ 23.281699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11709 10:59:05.692251 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11711 10:59:05.694684 st.c:721:
11712 10:59:05.698499 Test requirement: is_i915_device(fd)
11713 10:59:05.704956 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11714 10:59:05.708011 Test requirement: is_i915_device(fd)
11715 10:59:05.711096 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11716 10:59:05.718319 N<14>[ 23.307850] [IGT] kms_addfb_basic: executing
11717 10:59:05.721502 o KMS driver or no outputs, pipes: 8, outputs: 0
11718 10:59:05.727918 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11719 10:59:05.728037 Opened device: /dev/dri/card0
11720 10:59:05.737712 Test requirement not met in fun<14>[ 23.328463] [IGT] kms_addfb_basic: exiting, ret=77
11721 10:59:05.741279 ction igt_require_i915, file ../lib/drmtest.c:721:
11722 10:59:05.751251 Test requirement: is_i915_de<8>[ 23.340065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11723 10:59:05.751373 vice(fd)
11724 10:59:05.751618 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11726 10:59:05.757816 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11727 10:59:05.760988 Test requirement: is_i915_device(fd)
11728 10:59:05.767920 No KMS driver or no outputs, pipes: 8, outputs: 0
11729 10:59:05.771118 [1mSubtest size-max: SKIP (0.000s)[0m
11730 10:59:05.774558 I<14>[ 23.366187] [IGT] kms_addfb_basic: executing
11731 10:59:05.781014 GT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11732 10:59:05.784426 Opened device: /dev/dri/card0
11733 10:59:05.790832 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11734 10:59:05.794058 <14>[ 23.386901] [IGT] kms_addfb_basic: exiting, ret=77
11735 10:59:05.794165
11736 10:59:05.797351 Test requirement: is_i915_device(fd)
11737 10:59:05.808029 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11739 10:59:05.811091 Test requirement not met in function igt_<8>[ 23.398372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11740 10:59:05.814221 require_i915, file ../lib/drmtest.c:721:
11741 10:59:05.817401 Test requirement: is_i915_device(fd)
11742 10:59:05.820612 No KMS driver or no outputs, pipes: 8, outputs: 0
11743 10:59:05.824205 [1mSubtest too-wide: SKIP (0.000s)[0m
11744 10:59:05.830547 IGT-Version: 1.27.1-g766edf9 (aarch6<14>[ 23.423121] [IGT] kms_addfb_basic: executing
11745 10:59:05.834019 4) (Linux: 6.1.31 aarch64)
11746 10:59:05.837160 Opened device: /dev/dri/card0
11747 10:59:05.844266 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11748 10:59:05.854276 Test requirement: is_i915_device(f<14>[ 23.443465] [IGT] kms_addfb_basic: exiting, ret=77
11749 10:59:05.854409 d)
11750 10:59:05.867462 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<8>[ 23.455245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11751 10:59:05.867595 :721:
11752 10:59:05.867863 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11754 10:59:05.870640 Test requirement: is_i915_device(fd)
11755 10:59:05.877814 No KMS driver or no outputs, pipes: 8, outputs: 0
11756 10:59:05.880984 [1mSubtest too-high: SKIP (0.000s)[0m
11757 10:59:05.884137 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11758 10:59:05.890617 Opened device: /dev/dri<14>[ 23.482458] [IGT] kms_addfb_basic: executing
11759 10:59:05.893985 /card0
11760 10:59:05.900467 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11761 10:59:05.904197 Test requirement: is_i915_device(fd)
11762 10:59:05.910460 Test requirement not met in function igt_requir<14>[ 23.503476] [IGT] kms_addfb_basic: exiting, ret=77
11763 10:59:05.913934 e_i915, file ../lib/drmtest.c:721:
11764 10:59:05.917211 Test requirement: is_i915_device(fd)
11765 10:59:05.927344 No KMS<8>[ 23.514751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11766 10:59:05.927650 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11768 10:59:05.930627 driver or no outputs, pipes: 8, outputs: 0
11769 10:59:05.934027 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11770 10:59:05.940624 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11771 10:59:05.943602 Opened device: /dev/dri/card0
11772 10:59:05.950138 Test requirement not met in function ig<14>[ 23.542047] [IGT] kms_addfb_basic: executing
11773 10:59:05.953573 t_require_i915, file ../lib/drmtest.c:721:
11774 10:59:05.957324 Test requirement: is_i915_device(fd)
11775 10:59:05.967032 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11776 10:59:05.970873 Test requir<14>[ 23.562700] [IGT] kms_addfb_basic: exiting, ret=77
11777 10:59:05.973880 ement: is_i915_device(fd)
11778 10:59:05.977054 No KMS driver or no outputs, pipes: 8, outputs: 0
11779 10:59:05.986793 [<8>[ 23.574075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11780 10:59:05.987073 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11782 10:59:05.990229 1mSubtest small-bo: SKIP (0.000s)[0m
11783 10:59:05.996776 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11784 10:59:05.996848 Opened device: /dev/dri/card0
11785 10:59:06.010098 Test requirement not met in function igt_require_i915, file ../lib/drmtest<14>[ 23.600419] [IGT] kms_addfb_basic: executing
11786 10:59:06.010211 .c:721:
11787 10:59:06.013796 Test requirement: is_i915_device(fd)
11788 10:59:06.020071 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11789 10:59:06.023549 Test requirement: is_i915_device(fd)
11790 10:59:06.030067 No KMS d<14>[ 23.620618] [IGT] kms_addfb_basic: exiting, ret=77
11791 10:59:06.033036 river or no outputs, pipes: 8, outputs: 0
11792 10:59:06.043076 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11794 10:59:06.046733 [1mSubtest bo-too-small-due-to-tilin<8>[ 23.632133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11795 10:59:06.046833 g: SKIP (0.000s)[0m
11796 10:59:06.053400 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11797 10:59:06.056625 Opened device: /dev/dri/card0
11798 10:59:06.063058 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11799 10:59:06.069844 Test requirement: is_i91<14>[ 23.659966] [IGT] kms_addfb_basic: executing
11800 10:59:06.069945 5_device(fd)
11801 10:59:06.076300 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11802 10:59:06.079411 Test requirement: is_i915_device(fd)
11803 10:59:06.089895 No KMS driver or no outputs, pipes: 8, ou<14>[ 23.680843] [IGT] kms_addfb_basic: exiting, ret=77
11804 10:59:06.089980 tputs: 0
11805 10:59:06.096391 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11806 10:59:06.102967 IGT-Version: 1.<8>[ 23.692246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11807 10:59:06.103221 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11809 10:59:06.109384 27.1-g766edf9 (aarch64) (Linux: <8>[ 23.701984] <LAVA_SIGNAL_TESTSET STOP>
11810 10:59:06.109636 Received signal: <TESTSET> STOP
11811 10:59:06.109703 Closing test_set kms_addfb_basic
11812 10:59:06.112727 6.1.31 aarch64)
11813 10:59:06.116212 Opened device: /dev/dri/card0
11814 10:59:06.122572 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11815 10:59:06.125884 Test requirement: is_i915_device(fd)
11816 10:59:06.133045 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11817 10:59:06.136394 Received signal: <TESTSET> START kms_atomic
11818 10:59:06.136474 Starting test_set kms_atomic
11819 10:59:06.139589 Test<8>[ 23.728279] <LAVA_SIGNAL_TESTSET START kms_atomic>
11820 10:59:06.139671 requirement: is_i915_device(fd)
11821 10:59:06.145761 No KMS driver or no outputs, pipes: 8, outputs: 0
11822 10:59:06.149536 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11823 10:59:06.156142 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11824 10:59:06.159024 Ope<14>[ 23.752251] [IGT] kms_atomic: executing
11825 10:59:06.165883 ned device: /dev<14>[ 23.757283] [IGT] kms_atomic: exiting, ret=77
11826 10:59:06.165965 /dri/card0
11827 10:59:06.179381 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11829 10:59:06.182317 Test requirement not met in function igt_require_i915, file ../lib/d<8>[ 23.769178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11830 10:59:06.182458 rmtest.c:721:
11831 10:59:06.185490 Test requirement: is_i915_device(fd)
11832 10:59:06.192257 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11833 10:59:06.195697 Test requirement: is_i915_device(fd)
11834 10:59:06.202051 No KMS driver or no outputs, pipes<14>[ 23.794490] [IGT] kms_atomic: executing
11835 10:59:06.205369 : 8, outputs: 0
11836 10:59:06.209119 <14>[ 23.800220] [IGT] kms_atomic: exiting, ret=77
11837 10:59:06.209203
11838 10:59:06.215646 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11839 10:59:06.222104 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11841 10:59:06.225663 IGT-Version: 1.27.<8>[ 23.811953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11842 10:59:06.228924 1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11843 10:59:06.232108 Opened device: /dev/dri/card0
11844 10:59:06.238632 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11845 10:59:06.242046 Test requirement: is_i915_device(fd)
11846 10:59:06.245239 Test requi<14>[ 23.837885] [IGT] kms_atomic: executing
11847 10:59:06.252402 rement not met i<14>[ 23.843366] [IGT] kms_atomic: exiting, ret=77
11848 10:59:06.258611 n function igt_require_i915, file ../lib/drmtest.c:721:
11849 10:59:06.268758 Test requirement: is_i9<8>[ 23.854808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11850 10:59:06.268856 15_device(fd)
11851 10:59:06.269094 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11853 10:59:06.274839 No KMS driver or no outputs, pipes: 8, outputs: 0
11854 10:59:06.278498 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11855 10:59:06.285296 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11856 10:59:06.285381 Opened device: /dev/dri/card0
11857 10:59:06.291687 <14>[ 23.881829] [IGT] kms_atomic: executing
11858 10:59:06.291770
11859 10:59:06.295186 No KMS driver o<14>[ 23.887609] [IGT] kms_atomic: exiting, ret=77
11860 10:59:06.298260 r no outputs, pipes: 8, outputs: 0
11861 10:59:06.311616 [1mSubtest plane-overlay-legacy: SKIP (0.00<8>[ 23.899135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11862 10:59:06.311701 0s)[0m
11863 10:59:06.311941 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11865 10:59:06.318652 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11866 10:59:06.321729 Opened device: /dev/dri/card0
11867 10:59:06.324782 No KMS driver or no outputs, pipes: 8, outputs: 0
11868 10:59:06.328447 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11869 10:59:06.335205 <14>[ 23.925150] [IGT] kms_atomic: executing
11870 10:59:06.338559 IGT-Version: 1.2<14>[ 23.930627] [IGT] kms_atomic: exiting, ret=77
11871 10:59:06.345111 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11872 10:59:06.345221 Opened device: /dev/dri/card0
11873 10:59:06.351777 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11875 10:59:06.355245 N<8>[ 23.942063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11876 10:59:06.357996 o KMS driver or no outputs, pipes: 8, outputs: 0
11877 10:59:06.364779 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11878 10:59:06.368143 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11879 10:59:06.371191 Opened device: /dev/dri/card0
11880 10:59:06.378038 No KMS drive<14>[ 23.968145] [IGT] kms_atomic: executing
11881 10:59:06.380982 r or no outputs,<14>[ 23.974192] [IGT] kms_atomic: exiting, ret=77
11882 10:59:06.384599 pipes: 8, outputs: 0
11883 10:59:06.388066 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11884 10:59:06.397984 IGT-<8>[ 23.985457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11885 10:59:06.398252 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11887 10:59:06.401037 Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11888 10:59:06.404864 Opened device: /dev/dri/card0
11889 10:59:06.411400 No KMS driver or no outputs, pipes: 8, outputs: 0
11890 10:59:06.414457 [1mSubtest test-only: SKIP (0.000s)[0m
11891 10:59:06.420942 IGT-Version: 1.27.1-g766<14>[ 24.011243] [IGT] kms_atomic: executing
11892 10:59:06.423947 edf9 (aarch64) (<14>[ 24.016938] [IGT] kms_atomic: exiting, ret=77
11893 10:59:06.427685 Linux: 6.1.31 aarch64)
11894 10:59:06.430840 Opened device: /dev/dri/card0
11895 10:59:06.440827 No KMS driver or no outpu<8>[ 24.028072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11896 10:59:06.441116 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11898 10:59:06.444102 ts, pipes: 8, outputs: 0
11899 10:59:06.447282 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11900 10:59:06.454279 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11901 10:59:06.454387 Opened device: /dev/dri/card0
11902 10:59:06.464177 No KMS driver or no outputs, pipes:<14>[ 24.054365] [IGT] kms_atomic: executing
11903 10:59:06.464283 8, outputs: 0
11904 10:59:06.467429 <14>[ 24.060208] [IGT] kms_atomic: exiting, ret=77
11905 10:59:06.473748 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11906 10:59:06.484120 IGT-Version: 1.27.1-g766edf<8>[ 24.071109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11907 10:59:06.484405 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11909 10:59:06.487186 9 (aarch64) (Linux: 6.1.31 aarch64)
11910 10:59:06.490332 Opened device: /dev/dri/card0
11911 10:59:06.494080 No KMS driver or no outputs, pipes: 8, outputs: 0
11912 10:59:06.500892 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11913 10:59:06.507612 <14>[ 24.098746] [IGT] kms_atomic: executing
11914 10:59:06.513899 IGT-Version: 1.2<14>[ 24.103492] [IGT] kms_atomic: exiting, ret=77
11915 10:59:06.517169 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11916 10:59:06.520840 Opened device: /dev/dri/card0
11917 10:59:06.527155 N<8>[ 24.115243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11918 10:59:06.527424 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11920 10:59:06.530403 o KMS driver or no outputs, pipes: 8, outputs: 0
11921 10:59:06.537424 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11922 10:59:06.549414 <14>[ 24.140980] [IGT] kms_atomic: executing
11923 10:59:06.555894 IGT-Version: 1.2<14>[ 24.145798] [IGT] kms_atomic: exiting, ret=77
11924 10:59:06.559600 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11925 10:59:06.562882 Opened device: /dev/dri/card0
11926 10:59:06.569571 N<8>[ 24.157170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11927 10:59:06.569872 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11929 10:59:06.575907 o KMS driver or no outputs, pipes: 8, outputs: 0
11930 10:59:06.578998 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11931 10:59:06.592906 <14>[ 24.184729] [IGT] kms_atomic: executing
11932 10:59:06.599762 IGT-Version: 1.2<14>[ 24.189587] [IGT] kms_atomic: exiting, ret=77
11933 10:59:06.603310 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11934 10:59:06.606293 Opened device: /dev/dri/card0
11935 10:59:06.613079 N<8>[ 24.201045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11936 10:59:06.613340 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11938 10:59:06.616213 o KMS driver or no outputs, pipes: 8, outputs: 0
11939 10:59:06.623226 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11940 10:59:06.635750 <14>[ 24.227116] [IGT] kms_atomic: executing
11941 10:59:06.642028 IGT-Version: 1.2<14>[ 24.232039] [IGT] kms_atomic: exiting, ret=77
11942 10:59:06.645340 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11943 10:59:06.655138 Opened device: /<8>[ 24.243119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11944 10:59:06.655226 dev/dri/card0
11945 10:59:06.655506 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11947 10:59:06.661675 No KMS driver or <8>[ 24.252420] <LAVA_SIGNAL_TESTSET STOP>
11948 10:59:06.661931 Received signal: <TESTSET> STOP
11949 10:59:06.662005 Closing test_set kms_atomic
11950 10:59:06.665477 no outputs, pipes: 8, outputs: 0
11951 10:59:06.668153 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11952 10:59:06.687557 <8>[ 24.279103] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11953 10:59:06.687826 Received signal: <TESTSET> START kms_flip_event_leak
11954 10:59:06.687902 Starting test_set kms_flip_event_leak
11955 10:59:06.711559 <14>[ 24.302951] [IGT] kms_flip_event_leak: executing
11956 10:59:06.717775 IGT-Version: 1.2<14>[ 24.308705] [IGT] kms_flip_event_leak: exiting, ret=77
11957 10:59:06.720868 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11958 10:59:06.724712 Opened device: /dev/dri/card0
11959 10:59:06.731545 N<8>[ 24.321082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11960 10:59:06.731806 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11962 10:59:06.737872 o KMS driver or no outputs, pipe<8>[ 24.330176] <LAVA_SIGNAL_TESTSET STOP>
11963 10:59:06.738155 Received signal: <TESTSET> STOP
11964 10:59:06.738253 Closing test_set kms_flip_event_leak
11965 10:59:06.741024 s: 8, outputs: 0
11966 10:59:06.744184 [1mSubtest basic: SKIP (0.000s)[0m
11967 10:59:06.764492 <8>[ 24.355912] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11968 10:59:06.764756 Received signal: <TESTSET> START kms_prop_blob
11969 10:59:06.764832 Starting test_set kms_prop_blob
11970 10:59:06.787566 <14>[ 24.379236] [IGT] kms_prop_blob: executing
11971 10:59:06.793926 IGT-Version: 1.2<14>[ 24.384442] [IGT] kms_prop_blob: starting subtest basic
11972 10:59:06.800924 7.1-g766edf9 (aa<14>[ 24.391338] [IGT] kms_prop_blob: exiting, ret=0
11973 10:59:06.804067 rch64) (Linux: 6.1.31 aarch64)
11974 10:59:06.807269 Opened device: /dev/dri/card0
11975 10:59:06.814084 Starting subtest:<8>[ 24.403130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11976 10:59:06.814172 basic
11977 10:59:06.814449 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11979 10:59:06.817258 [1mSubtest basic: SUCCESS (0.000s)[0m
11980 10:59:06.837374 <14>[ 24.429159] [IGT] kms_prop_blob: executing
11981 10:59:06.843939 IGT-Version: 1.2<14>[ 24.433968] [IGT] kms_prop_blob: starting subtest blob-prop-core
11982 10:59:06.850611 7.1-g766edf9 (aa<14>[ 24.441900] [IGT] kms_prop_blob: exiting, ret=0
11983 10:59:06.854664 rch64) (Linux: 6.1.31 aarch64)
11984 10:59:06.857245 Opened device: /dev/dri/card0
11985 10:59:06.864389 Starting subtest:<8>[ 24.453866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11986 10:59:06.864649 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11988 10:59:06.867504 blob-prop-core
11989 10:59:06.870536 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11990 10:59:06.887870 <14>[ 24.479138] [IGT] kms_prop_blob: executing
11991 10:59:06.894130 IGT-Version: 1.2<14>[ 24.484058] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11992 10:59:06.900942 7.1-g766edf9 (aa<14>[ 24.492353] [IGT] kms_prop_blob: exiting, ret=0
11993 10:59:06.904083 rch64) (Linux: 6.1.31 aarch64)
11994 10:59:06.907792 Opened device: /dev/dri/card0
11995 10:59:06.917485 Starting subtest:<8>[ 24.504237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11996 10:59:06.917845 blob-prop-validate
11997 10:59:06.918406 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11999 10:59:06.923951 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12000 10:59:06.938825 <14>[ 24.530066] [IGT] kms_prop_blob: executing
12001 10:59:06.945108 IGT-Version: 1.2<14>[ 24.534912] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12002 10:59:06.951769 7.1-g766edf9 (aa<14>[ 24.543007] [IGT] kms_prop_blob: exiting, ret=0
12003 10:59:06.955403 rch64) (Linux: 6.1.31 aarch64)
12004 10:59:06.958292 Opened device: /dev/dri/card0
12005 10:59:06.965303 Starting subtest:<8>[ 24.554840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12006 10:59:06.965860 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12008 10:59:06.968689 blob-prop-lifetime
12009 10:59:06.971906 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12010 10:59:06.989394 <14>[ 24.580982] [IGT] kms_prop_blob: executing
12011 10:59:06.996510 IGT-Version: 1.2<14>[ 24.585812] [IGT] kms_prop_blob: starting subtest blob-multiple
12012 10:59:07.003393 7.1-g766edf9 (aa<14>[ 24.593530] [IGT] kms_prop_blob: exiting, ret=0
12013 10:59:07.006493 rch64) (Linux: 6.1.31 aarch64)
12014 10:59:07.009466 Opened device: /dev/dri/card0
12015 10:59:07.015862 Starting subtest:<8>[ 24.605273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12016 10:59:07.016416 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12018 10:59:07.019833 blob-multiple
12019 10:59:07.023092 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12020 10:59:07.040264 <14>[ 24.631714] [IGT] kms_prop_blob: executing
12021 10:59:07.046983 IGT-Version: 1.2<14>[ 24.636728] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12022 10:59:07.053923 7.1-g766edf9 (aa<14>[ 24.644864] [IGT] kms_prop_blob: exiting, ret=0
12023 10:59:07.057051 rch64) (Linux: 6.1.31 aarch64)
12024 10:59:07.060162 Opened device: /dev/dri/card0
12025 10:59:07.070329 Starting subtest:<8>[ 24.656755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12026 10:59:07.070653 invalid-get-prop-any
12027 10:59:07.071133 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12029 10:59:07.076829 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12030 10:59:07.092299 <14>[ 24.683994] [IGT] kms_prop_blob: executing
12031 10:59:07.099234 IGT-Version: 1.2<14>[ 24.689029] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12032 10:59:07.105823 7.1-g766edf9 (aa<14>[ 24.696786] [IGT] kms_prop_blob: exiting, ret=0
12033 10:59:07.109317 rch64) (Linux: 6.1.31 aarch64)
12034 10:59:07.112537 Opened device: /dev/dri/card0
12035 10:59:07.119565 Starting subtest:<8>[ 24.708569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12036 10:59:07.120118 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12038 10:59:07.122820 invalid-get-prop
12039 10:59:07.126133 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12040 10:59:07.143063 <14>[ 24.734271] [IGT] kms_prop_blob: executing
12041 10:59:07.149425 IGT-Version: 1.2<14>[ 24.739108] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12042 10:59:07.156187 7.1-g766edf9 (aa<14>[ 24.747302] [IGT] kms_prop_blob: exiting, ret=0
12043 10:59:07.159295 rch64) (Linux: 6.1.31 aarch64)
12044 10:59:07.162521 Opened device: /dev/dri/card0
12045 10:59:07.169346 S<8>[ 24.758764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12046 10:59:07.169895 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12048 10:59:07.172358 tarting subtest: invalid-set-prop-any
12049 10:59:07.179137 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12050 10:59:07.192603 <14>[ 24.783863] [IGT] kms_prop_blob: executing
12051 10:59:07.199103 IGT-Version: 1.2<14>[ 24.788775] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12052 10:59:07.205427 7.1-g766edf9 (aa<14>[ 24.796606] [IGT] kms_prop_blob: exiting, ret=0
12053 10:59:07.208985 rch64) (Linux: 6.1.31 aarch64)
12054 10:59:07.212425 Opened device: /dev/dri/card0
12055 10:59:07.218505 S<8>[ 24.808174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12056 10:59:07.219071 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12058 10:59:07.225949 tarting subtest: invalid-set-pro<8>[ 24.817235] <LAVA_SIGNAL_TESTSET STOP>
12059 10:59:07.226414 p
12060 10:59:07.226949 Received signal: <TESTSET> STOP
12061 10:59:07.227228 Closing test_set kms_prop_blob
12062 10:59:07.231920 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12063 10:59:07.251987 <8>[ 24.843443] <LAVA_SIGNAL_TESTSET START kms_setmode>
12064 10:59:07.252578 Received signal: <TESTSET> START kms_setmode
12065 10:59:07.252877 Starting test_set kms_setmode
12066 10:59:07.275154 <14>[ 24.866652] [IGT] kms_setmode: executing
12067 10:59:07.391714 IGT-Version: 1.2<14>[ 24.871677] [IGT] kms_setmode: starting subtest basic
12068 10:59:07.392595 7.1-g766edf9 (aa<14>[ 24.878236] [IGT] kms_setmode: exiting, ret=77
12069 10:59:07.392990 rch64) (Linux: 6.1.31 aarch64)
12070 10:59:07.393362 Opened device: /dev/dri/card0
12071 10:59:07.393688 Starting subtest:<8>[ 24.890211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12072 10:59:07.394086 basic
12073 10:59:07.394503 No dynamic tests executed.
12074 10:59:07.394931 [1mSubtest basic: SKIP (0.000s)[0m
12075 10:59:07.395376 <14>[ 24.915942] [IGT] kms_setmode: executing
12076 10:59:07.395679 IGT-Version: 1.2<14>[ 24.920852] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12077 10:59:07.396068 7.1-g766edf9 (aa<14>[ 24.929017] [IGT] kms_setmode: exiting, ret=77
12078 10:59:07.396433 rch64) (Linux: 6.1.31 aarch64)
12079 10:59:07.396798 Opened device: /dev/dri/card0
12080 10:59:07.397208 Starting subtest:<8>[ 24.940908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12081 10:59:07.397663 basic-clone-single-crtc
12082 10:59:07.398118 No dynamic tests executed.
12083 10:59:07.398559 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12084 10:59:07.399013 <14>[ 24.967047] [IGT] kms_setmode: executing
12085 10:59:07.399493 IGT-Version: 1.2<14>[ 24.971941] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12086 10:59:07.399941 7.1-g766edf9 (aa<14>[ 24.980197] [IGT] kms_setmode: exiting, ret=77
12087 10:59:07.400408 rch64) (Linux: 6.1.31 aarch64)
12088 10:59:07.400933 Opened device: /dev/dri/card0
12089 10:59:07.401687 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12091 10:59:07.403043 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12093 10:59:07.405615 Starting subtest:<8>[ 24.991808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12094 10:59:07.406410 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12096 10:59:07.408759 invalid-clone-single-crtc
12097 10:59:07.409193 No dynamic tests executed.
12098 10:59:07.415060 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12099 10:59:07.426669 <14>[ 25.018203] [IGT] kms_setmode: executing
12100 10:59:07.433028 IGT-Version: 1.2<14>[ 25.023066] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12101 10:59:07.440296 7.1-g766edf9 (aa<14>[ 25.031761] [IGT] kms_setmode: exiting, ret=77
12102 10:59:07.443482 rch64) (Linux: 6.1.31 aarch64)
12103 10:59:07.446587 Opened device: /dev/dri/card0
12104 10:59:07.456437 S<8>[ 25.043131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12105 10:59:07.456796 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12107 10:59:07.459571 tarting subtest: invalid-clone-exclusive-crtc
12108 10:59:07.463029 No dynamic tests executed.
12109 10:59:07.466395 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12110 10:59:07.476871 <14>[ 25.068976] [IGT] kms_setmode: executing
12111 10:59:07.483730 IGT-Version: 1.2<14>[ 25.073716] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12112 10:59:07.490642 7.1-g766edf9 (aa<14>[ 25.081758] [IGT] kms_setmode: exiting, ret=77
12113 10:59:07.493672 rch64) (Linux: 6.1.31 aarch64)
12114 10:59:07.497041 Opened device: /dev/dri/card0
12115 10:59:07.503727 S<8>[ 25.093204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12116 10:59:07.504020 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12118 10:59:07.506658 tarting subtest: clone-exclusive-crtc
12119 10:59:07.510555 No dynamic tests executed.
12120 10:59:07.513804 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12121 10:59:07.526007 <14>[ 25.118050] [IGT] kms_setmode: executing
12122 10:59:07.535895 IGT-Version: 1.2<14>[ 25.122809] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12123 10:59:07.542344 7.1-g766edf9 (aa<14>[ 25.132106] [IGT] kms_setmode: exiting, ret=77
12124 10:59:07.542485 rch64) (Linux: 6.1.31 aarch64)
12125 10:59:07.546207 Opened device: /dev/dri/card0
12126 10:59:07.556118 S<8>[ 25.143465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12127 10:59:07.556492 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12129 10:59:07.559366 Received signal: <TESTSET> STOP
12130 10:59:07.559482 Closing test_set kms_setmode
12131 10:59:07.562515 tarting subtest:<8>[ 25.153792] <LAVA_SIGNAL_TESTSET STOP>
12132 10:59:07.562630 invalid-clone-single-crtc-stealing
12133 10:59:07.565707 No dynamic tests executed.
12134 10:59:07.572840 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12135 10:59:07.587110 <8>[ 25.179277] <LAVA_SIGNAL_TESTSET START kms_vblank>
12136 10:59:07.587409 Received signal: <TESTSET> START kms_vblank
12137 10:59:07.587486 Starting test_set kms_vblank
12138 10:59:07.611032 <14>[ 25.202675] [IGT] kms_vblank: executing
12139 10:59:07.617377 IGT-Version: 1.2<14>[ 25.207708] [IGT] kms_vblank: exiting, ret=77
12140 10:59:07.621421 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12141 10:59:07.623919 Opened device: /dev/dri/card0
12142 10:59:07.627203 No KMS driver or no outputs, pipes: 8, outputs: 0
12143 10:59:07.630576 [1mSubtest invalid: SKIP (0.000s)[0m
12144 10:59:07.637155 <8>[ 25.228430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12145 10:59:07.637412 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12147 10:59:07.662734 <14>[ 25.254387] [IGT] kms_vblank: executing
12148 10:59:07.669166 IGT-Version: 1.2<14>[ 25.259478] [IGT] kms_vblank: exiting, ret=77
12149 10:59:07.672956 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12150 10:59:07.675597 Opened device: /dev/dri/card0
12151 10:59:07.682625 N<8>[ 25.271130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12152 10:59:07.682881 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12154 10:59:07.685759 o KMS driver or no outputs, pipes: 8, outputs: 0
12155 10:59:07.689001 [1mSubtest crtc-id: SKIP (0.000s)[0m
12156 10:59:07.704734 <14>[ 25.296498] [IGT] kms_vblank: executing
12157 10:59:07.711446 IGT-Version: 1.2<14>[ 25.301737] [IGT] kms_vblank: exiting, ret=77
12158 10:59:07.714704 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12159 10:59:07.718445 Opened device: /dev/dri/card0
12160 10:59:07.724516 N<8>[ 25.313392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12161 10:59:07.724770 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12163 10:59:07.728299 o KMS driver or no outputs, pipes: 8, outputs: 0
12164 10:59:07.734804 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12165 10:59:07.748469 <14>[ 25.339927] [IGT] kms_vblank: executing
12166 10:59:07.754419 IGT-Version: 1.2<14>[ 25.344888] [IGT] kms_vblank: exiting, ret=77
12167 10:59:07.757721 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12168 10:59:07.761627 Opened device: /dev/dri/card0
12169 10:59:07.768161 N<8>[ 25.356565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12170 10:59:07.768415 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12172 10:59:07.771306 o KMS driver or no outputs, pipes: 8, outputs: 0
12173 10:59:07.777702 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12174 10:59:07.790951 <14>[ 25.382984] [IGT] kms_vblank: executing
12175 10:59:07.797806 IGT-Version: 1.2<14>[ 25.388128] [IGT] kms_vblank: exiting, ret=77
12176 10:59:07.800825 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12177 10:59:07.804187 Opened device: /dev/dri/card0
12178 10:59:07.811017 N<8>[ 25.399751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12179 10:59:07.811270 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12181 10:59:07.814223 o KMS driver or no outputs, pipes: 8, outputs: 0
12182 10:59:07.820980 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12183 10:59:07.835425 <14>[ 25.427410] [IGT] kms_vblank: executing
12184 10:59:07.842386 IGT-Version: 1.2<14>[ 25.432802] [IGT] kms_vblank: exiting, ret=77
12185 10:59:07.845773 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12186 10:59:07.848966 Opened device: /dev/dri/card0
12187 10:59:07.855523 N<8>[ 25.444562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12188 10:59:07.855776 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12190 10:59:07.858772 o KMS driver or no outputs, pipes: 8, outputs: 0
12191 10:59:07.865756 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12192 10:59:07.878352 <14>[ 25.469995] [IGT] kms_vblank: executing
12193 10:59:07.885087 IGT-Version: 1.2<14>[ 25.474999] [IGT] kms_vblank: exiting, ret=77
12194 10:59:07.888375 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12195 10:59:07.891666 Opened device: /dev/dri/card0
12196 10:59:07.898064 N<8>[ 25.486213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12197 10:59:07.898319 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12199 10:59:07.901316 o KMS driver or no outputs, pipes: 8, outputs: 0
12200 10:59:07.908143 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12201 10:59:07.921865 <14>[ 25.513759] [IGT] kms_vblank: executing
12202 10:59:07.928863 IGT-Version: 1.2<14>[ 25.518937] [IGT] kms_vblank: exiting, ret=77
12203 10:59:07.931891 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12204 10:59:07.935185 Opened device: /dev/dri/card0
12205 10:59:07.941652 N<8>[ 25.530199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12206 10:59:07.941905 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12208 10:59:07.945074 o KMS driver or no outputs, pipes: 8, outputs: 0
12209 10:59:07.951932 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12210 10:59:07.964484 <14>[ 25.556607] [IGT] kms_vblank: executing
12211 10:59:07.971677 IGT-Version: 1.2<14>[ 25.561607] [IGT] kms_vblank: exiting, ret=77
12212 10:59:07.974938 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12213 10:59:07.978225 Opened device: /dev/dri/card0
12214 10:59:07.984489 N<8>[ 25.573101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12215 10:59:07.984745 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12217 10:59:07.987764 o KMS driver or no outputs, pipes: 8, outputs: 0
12218 10:59:07.994422 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12219 10:59:08.008498 <14>[ 25.600099] [IGT] kms_vblank: executing
12220 10:59:08.015253 IGT-Version: 1.2<14>[ 25.605342] [IGT] kms_vblank: exiting, ret=77
12221 10:59:08.018381 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12222 10:59:08.021577 Opened device: /dev/dri/card0
12223 10:59:08.028060 N<8>[ 25.616597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12224 10:59:08.028321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12226 10:59:08.034958 o KMS driver or no outputs, pipes: 8, outputs: 0
12227 10:59:08.038065 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12228 10:59:08.050899 <14>[ 25.642797] [IGT] kms_vblank: executing
12229 10:59:08.057556 IGT-Version: 1.2<14>[ 25.647875] [IGT] kms_vblank: exiting, ret=77
12230 10:59:08.061230 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12231 10:59:08.064351 Opened device: /dev/dri/card0
12232 10:59:08.071069 N<8>[ 25.659058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12233 10:59:08.071437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12235 10:59:08.077732 o KMS driver or no outputs, pipes: 8, outputs: 0
12236 10:59:08.080978 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12237 10:59:08.094177 <14>[ 25.685683] [IGT] kms_vblank: executing
12238 10:59:08.100819 IGT-Version: 1.2<14>[ 25.690709] [IGT] kms_vblank: exiting, ret=77
12239 10:59:08.103649 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12240 10:59:08.106765 Opened device: /dev/dri/card0
12241 10:59:08.113873 N<8>[ 25.702108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12242 10:59:08.114153 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12244 10:59:08.117052 o KMS driver or no outputs, pipes: 8, outputs: 0
12245 10:59:08.123505 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12246 10:59:08.135428 <14>[ 25.727416] [IGT] kms_vblank: executing
12247 10:59:08.142587 IGT-Version: 1.2<14>[ 25.732487] [IGT] kms_vblank: exiting, ret=77
12248 10:59:08.145435 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12249 10:59:08.148829 Opened device: /dev/dri/card0
12250 10:59:08.155594 N<8>[ 25.743798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12251 10:59:08.156117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12253 10:59:08.158930 o KMS driver or no outputs, pipes: 8, outputs: 0
12254 10:59:08.165937 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12255 10:59:08.178880 <14>[ 25.770462] [IGT] kms_vblank: executing
12256 10:59:08.185620 IGT-Version: 1.2<14>[ 25.775424] [IGT] kms_vblank: exiting, ret=77
12257 10:59:08.188688 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12258 10:59:08.191991 Opened device: /dev/dri/card0
12259 10:59:08.198641 N<8>[ 25.786932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12260 10:59:08.199458 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12262 10:59:08.201803 o KMS driver or no outputs, pipes: 8, outputs: 0
12263 10:59:08.208487 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12264 10:59:08.221948 <14>[ 25.813300] [IGT] kms_vblank: executing
12265 10:59:08.228419 IGT-Version: 1.2<14>[ 25.818464] [IGT] kms_vblank: exiting, ret=77
12266 10:59:08.231995 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12267 10:59:08.234808 Opened device: /dev/dri/card0
12268 10:59:08.242078 N<8>[ 25.829671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12269 10:59:08.242682 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12271 10:59:08.244843 o KMS driver or no outputs, pipes: 8, outputs: 0
12272 10:59:08.251821 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12273 10:59:08.264104 <14>[ 25.855924] [IGT] kms_vblank: executing
12274 10:59:08.271003 IGT-Version: 1.2<14>[ 25.860990] [IGT] kms_vblank: exiting, ret=77
12275 10:59:08.274345 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12276 10:59:08.277934 Opened device: /dev/dri/card0
12277 10:59:08.284457 N<8>[ 25.872212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12278 10:59:08.285061 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12280 10:59:08.287741 o KMS driver or no outputs, pipes: 8, outputs: 0
12281 10:59:08.293936 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12282 10:59:08.306758 <14>[ 25.897512] [IGT] kms_vblank: executing
12283 10:59:08.312679 IGT-Version: 1.2<14>[ 25.902584] [IGT] kms_vblank: exiting, ret=77
12284 10:59:08.316226 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12285 10:59:08.319504 Opened device: /dev/dri/card0
12286 10:59:08.326501 N<8>[ 25.913835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12287 10:59:08.327254 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12289 10:59:08.329358 o KMS driver or no outputs, pipes: 8, outputs: 0
12290 10:59:08.335829 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12291 10:59:08.349597 <14>[ 25.940763] [IGT] kms_vblank: executing
12292 10:59:08.355969 IGT-Version: 1.2<14>[ 25.945688] [IGT] kms_vblank: exiting, ret=77
12293 10:59:08.359163 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12294 10:59:08.362220 Opened device: /dev/dri/card0
12295 10:59:08.369162 N<8>[ 25.957532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12296 10:59:08.369809 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12298 10:59:08.372613 o KMS driver or no outputs, pipes: 8, outputs: 0
12299 10:59:08.378980 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12300 10:59:08.392054 <14>[ 25.983301] [IGT] kms_vblank: executing
12301 10:59:08.398825 IGT-Version: 1.2<14>[ 25.988517] [IGT] kms_vblank: exiting, ret=77
12302 10:59:08.401489 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12303 10:59:08.405282 Opened device: /dev/dri/card0
12304 10:59:08.412012 N<8>[ 25.999734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12305 10:59:08.412785 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12307 10:59:08.419049 o KMS driver or no outputs, pipes: 8, outputs: 0
12308 10:59:08.421711 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12309 10:59:08.434952 <14>[ 26.026204] [IGT] kms_vblank: executing
12310 10:59:08.441361 IGT-Version: 1.2<14>[ 26.031222] [IGT] kms_vblank: exiting, ret=77
12311 10:59:08.444450 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12312 10:59:08.448304 Opened device: /dev/dri/card0
12313 10:59:08.454975 N<8>[ 26.042397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12314 10:59:08.455799 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12316 10:59:08.461583 o KMS driver or no outputs, pipes: 8, outputs: 0
12317 10:59:08.464633 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12318 10:59:08.478314 <14>[ 26.069879] [IGT] kms_vblank: executing
12319 10:59:08.485184 IGT-Version: 1.2<14>[ 26.074853] [IGT] kms_vblank: exiting, ret=77
12320 10:59:08.488134 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12321 10:59:08.491430 Opened device: /dev/dri/card0
12322 10:59:08.498486 N<8>[ 26.086903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12323 10:59:08.499258 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12325 10:59:08.505091 o KMS driver or no outputs, pipes: 8, outputs: 0
12326 10:59:08.508286 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12327 10:59:08.521806 <14>[ 26.113248] [IGT] kms_vblank: executing
12328 10:59:08.528243 IGT-Version: 1.2<14>[ 26.118248] [IGT] kms_vblank: exiting, ret=77
12329 10:59:08.531508 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12330 10:59:08.535067 Opened device: /dev/dri/card0
12331 10:59:08.541933 N<8>[ 26.129305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12332 10:59:08.542605 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12334 10:59:08.548220 o KMS driver or no outputs, pipes: 8, outputs: 0
12335 10:59:08.551968 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12336 10:59:08.565601 <14>[ 26.157057] [IGT] kms_vblank: executing
12337 10:59:08.571814 IGT-Version: 1.2<14>[ 26.162314] [IGT] kms_vblank: exiting, ret=77
12338 10:59:08.575841 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12339 10:59:08.579079 Opened device: /dev/dri/card0
12340 10:59:08.586216 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12342 10:59:08.588824 N<8>[ 26.173369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12343 10:59:08.592206 o KMS driver or no outputs, pipes: 8, outputs: 0
12344 10:59:08.598804 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12345 10:59:08.609444 <14>[ 26.200766] [IGT] kms_vblank: executing
12346 10:59:08.616149 IGT-Version: 1.2<14>[ 26.205752] [IGT] kms_vblank: exiting, ret=77
12347 10:59:08.619088 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12348 10:59:08.622927 Opened device: /dev/dri/card0
12349 10:59:08.629863 N<8>[ 26.216813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12350 10:59:08.630651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12352 10:59:08.635487 o KMS driver or no outputs, pipes: 8, outputs: 0
12353 10:59:08.638737 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12354 10:59:08.652084 <14>[ 26.243493] [IGT] kms_vblank: executing
12355 10:59:08.658371 IGT-Version: 1.2<14>[ 26.248525] [IGT] kms_vblank: exiting, ret=77
12356 10:59:08.661612 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12357 10:59:08.671924 Opened device: /<8>[ 26.259478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12358 10:59:08.672349 dev/dri/card0
12359 10:59:08.672932 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12361 10:59:08.678654 No KMS driver or no outputs, pipes: 8, outputs: 0
12362 10:59:08.681688 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12363 10:59:08.694879 <14>[ 26.286180] [IGT] kms_vblank: executing
12364 10:59:08.701157 IGT-Version: 1.2<14>[ 26.291425] [IGT] kms_vblank: exiting, ret=77
12365 10:59:08.704969 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12366 10:59:08.708026 Opened device: /dev/dri/card0
12367 10:59:08.715257 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12369 10:59:08.718083 N<8>[ 26.302447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12370 10:59:08.721486 o KMS driver or no outputs, pipes: 8, outputs: 0
12371 10:59:08.728000 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12372 10:59:08.739406 <14>[ 26.330857] [IGT] kms_vblank: executing
12373 10:59:08.746135 IGT-Version: 1.2<14>[ 26.336201] [IGT] kms_vblank: exiting, ret=77
12374 10:59:08.749553 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12375 10:59:08.752981 Opened device: /dev/dri/card0
12376 10:59:08.759808 N<8>[ 26.347149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12377 10:59:08.760596 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12379 10:59:08.765835 o KMS driver or no outputs, pipes: 8, outputs: 0
12380 10:59:08.773161 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12381 10:59:08.782929 <14>[ 26.374372] [IGT] kms_vblank: executing
12382 10:59:08.789549 IGT-Version: 1.2<14>[ 26.379448] [IGT] kms_vblank: exiting, ret=77
12383 10:59:08.792868 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12384 10:59:08.796692 Opened device: /dev/dri/card0
12385 10:59:08.802814 N<8>[ 26.390799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12386 10:59:08.803648 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12388 10:59:08.806250 o KMS driver or no outputs, pipes: 8, outputs: 0
12389 10:59:08.812882 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12390 10:59:08.825469 <14>[ 26.416641] [IGT] kms_vblank: executing
12391 10:59:08.831968 IGT-Version: 1.2<14>[ 26.421611] [IGT] kms_vblank: exiting, ret=77
12392 10:59:08.835208 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12393 10:59:08.838641 Opened device: /dev/dri/card0
12394 10:59:08.845122 N<8>[ 26.433028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12395 10:59:08.845814 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12397 10:59:08.848595 o KMS driver or no outputs, pipes: 8, outputs: 0
12398 10:59:08.855102 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12399 10:59:08.867902 <14>[ 26.459544] [IGT] kms_vblank: executing
12400 10:59:08.874783 IGT-Version: 1.2<14>[ 26.464757] [IGT] kms_vblank: exiting, ret=77
12401 10:59:08.877819 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12402 10:59:08.880893 Opened device: /dev/dri/card0
12403 10:59:08.887685 N<8>[ 26.476067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12404 10:59:08.888367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12406 10:59:08.894397 o KMS driver or no outputs, pipes: 8, outputs: 0
12407 10:59:08.897679 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12408 10:59:08.910794 <14>[ 26.502307] [IGT] kms_vblank: executing
12409 10:59:08.917734 IGT-Version: 1.2<14>[ 26.507299] [IGT] kms_vblank: exiting, ret=77
12410 10:59:08.920721 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12411 10:59:08.923818 Opened device: /dev/dri/card0
12412 10:59:08.930574 N<8>[ 26.518881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12413 10:59:08.931385 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12415 10:59:08.933918 o KMS driver or no outputs, pipes: 8, outputs: 0
12416 10:59:08.940308 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12417 10:59:08.954678 <14>[ 26.545720] [IGT] kms_vblank: executing
12418 10:59:08.961396 IGT-Version: 1.2<14>[ 26.550705] [IGT] kms_vblank: exiting, ret=77
12419 10:59:08.964404 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12420 10:59:08.967820 Opened device: /dev/dri/card0
12421 10:59:08.974416 N<8>[ 26.562665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12422 10:59:08.975208 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12424 10:59:08.977486 o KMS driver or no outputs, pipes: 8, outputs: 0
12425 10:59:08.984354 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12426 10:59:08.997885 <14>[ 26.589529] [IGT] kms_vblank: executing
12427 10:59:09.004826 IGT-Version: 1.2<14>[ 26.594557] [IGT] kms_vblank: exiting, ret=77
12428 10:59:09.008002 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12429 10:59:09.011517 Opened device: /dev/dri/card0
12430 10:59:09.017718 N<8>[ 26.606769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12431 10:59:09.018705 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12433 10:59:09.020962 o KMS driver or no outputs, pipes: 8, outputs: 0
12434 10:59:09.027532 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12435 10:59:09.041025 <14>[ 26.632781] [IGT] kms_vblank: executing
12436 10:59:09.047739 IGT-Version: 1.2<14>[ 26.637742] [IGT] kms_vblank: exiting, ret=77
12437 10:59:09.051228 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12438 10:59:09.054866 Opened device: /dev/dri/card0
12439 10:59:09.061457 N<8>[ 26.649827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12440 10:59:09.062253 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12442 10:59:09.064549 o KMS driver or no outputs, pipes: 8, outputs: 0
12443 10:59:09.071261 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12444 10:59:09.083565 <14>[ 26.675195] [IGT] kms_vblank: executing
12445 10:59:09.089886 IGT-Version: 1.2<14>[ 26.680414] [IGT] kms_vblank: exiting, ret=77
12446 10:59:09.093747 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12447 10:59:09.096749 Opened device: /dev/dri/card0
12448 10:59:09.103037 N<8>[ 26.692068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12449 10:59:09.103734 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12451 10:59:09.110345 o KMS driver or no outputs, pipes: 8, outputs: 0
12452 10:59:09.113506 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12453 10:59:09.126361 <14>[ 26.717699] [IGT] kms_vblank: executing
12454 10:59:09.132638 IGT-Version: 1.2<14>[ 26.722692] [IGT] kms_vblank: exiting, ret=77
12455 10:59:09.136101 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12456 10:59:09.139219 Opened device: /dev/dri/card0
12457 10:59:09.145887 N<8>[ 26.734176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12458 10:59:09.146688 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12460 10:59:09.152608 o KMS driver or no outputs, pipes: 8, outputs: 0
12461 10:59:09.155710 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12462 10:59:09.169532 <14>[ 26.760725] [IGT] kms_vblank: executing
12463 10:59:09.175577 IGT-Version: 1.2<14>[ 26.765834] [IGT] kms_vblank: exiting, ret=77
12464 10:59:09.179272 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12465 10:59:09.182690 Opened device: /dev/dri/card0
12466 10:59:09.188659 N<8>[ 26.776974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12467 10:59:09.189389 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12469 10:59:09.191932 o KMS driver or no outputs, pipes: 8, outputs: 0
12470 10:59:09.198910 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12471 10:59:09.210653 <14>[ 26.802452] [IGT] kms_vblank: executing
12472 10:59:09.217439 IGT-Version: 1.2<14>[ 26.807473] [IGT] kms_vblank: exiting, ret=77
12473 10:59:09.220526 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12474 10:59:09.224524 Opened device: /dev/dri/card0
12475 10:59:09.230511 N<8>[ 26.818968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12476 10:59:09.231410 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12478 10:59:09.234260 o KMS driver or no outputs, pipes: 8, outputs: 0
12479 10:59:09.240524 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12480 10:59:09.254035 <14>[ 26.845671] [IGT] kms_vblank: executing
12481 10:59:09.260858 IGT-Version: 1.2<14>[ 26.850614] [IGT] kms_vblank: exiting, ret=77
12482 10:59:09.264158 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12483 10:59:09.267645 Opened device: /dev/dri/card0
12484 10:59:09.274011 N<8>[ 26.862415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12485 10:59:09.274698 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12487 10:59:09.277440 o KMS driver or no outputs, pipes: 8, outputs: 0
12488 10:59:09.283558 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12489 10:59:09.297158 <14>[ 26.888968] [IGT] kms_vblank: executing
12490 10:59:09.303649 IGT-Version: 1.2<14>[ 26.893937] [IGT] kms_vblank: exiting, ret=77
12491 10:59:09.307827 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12492 10:59:09.310841 Opened device: /dev/dri/card0
12493 10:59:09.317038 N<8>[ 26.905630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12494 10:59:09.317717 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12496 10:59:09.320712 o KMS driver or no outputs, pipes: 8, outputs: 0
12497 10:59:09.326869 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12498 10:59:09.339283 <14>[ 26.931288] [IGT] kms_vblank: executing
12499 10:59:09.346080 IGT-Version: 1.2<14>[ 26.936494] [IGT] kms_vblank: exiting, ret=77
12500 10:59:09.349331 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12501 10:59:09.352930 Opened device: /dev/dri/card0
12502 10:59:09.359408 N<8>[ 26.947477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12503 10:59:09.359724 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12505 10:59:09.362509 o KMS driver or no outputs, pipes: 8, outputs: 0
12506 10:59:09.368854 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12507 10:59:09.381272 <14>[ 26.973143] [IGT] kms_vblank: executing
12508 10:59:09.387638 IGT-Version: 1.2<14>[ 26.978129] [IGT] kms_vblank: exiting, ret=77
12509 10:59:09.391000 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12510 10:59:09.394280 Opened device: /dev/dri/card0
12511 10:59:09.401427 N<8>[ 26.989156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12512 10:59:09.401688 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12514 10:59:09.404607 o KMS driver or no outputs, pipes: 8, outputs: 0
12515 10:59:09.411123 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12516 10:59:09.423214 <14>[ 27.015361] [IGT] kms_vblank: executing
12517 10:59:09.430239 IGT-Version: 1.2<14>[ 27.020430] [IGT] kms_vblank: exiting, ret=77
12518 10:59:09.433249 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12519 10:59:09.436458 Opened device: /dev/dri/card0
12520 10:59:09.443357 N<8>[ 27.031475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12521 10:59:09.443779 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12523 10:59:09.446565 o KMS driver or no outputs, pipes: 8, outputs: 0
12524 10:59:09.453644 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12525 10:59:09.465436 <14>[ 27.057586] [IGT] kms_vblank: executing
12526 10:59:09.472517 IGT-Version: 1.2<14>[ 27.062593] [IGT] kms_vblank: exiting, ret=77
12527 10:59:09.475722 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12528 10:59:09.479168 Opened device: /dev/dri/card0
12529 10:59:09.485918 N<8>[ 27.073978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12530 10:59:09.486547 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12532 10:59:09.492325 o KMS driver or no outputs, pipes: 8, outputs: 0
12533 10:59:09.495648 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12534 10:59:09.509624 <14>[ 27.101400] [IGT] kms_vblank: executing
12535 10:59:09.516328 IGT-Version: 1.2<14>[ 27.106907] [IGT] kms_vblank: exiting, ret=77
12536 10:59:09.519318 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12537 10:59:09.522732 Opened device: /dev/dri/card0
12538 10:59:09.529269 N<8>[ 27.118230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12539 10:59:09.529568 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12541 10:59:09.536155 o KMS driver or no outputs, pipes: 8, outputs: 0
12542 10:59:09.539137 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12543 10:59:09.553338 <14>[ 27.145069] [IGT] kms_vblank: executing
12544 10:59:09.559777 IGT-Version: 1.2<14>[ 27.150064] [IGT] kms_vblank: exiting, ret=77
12545 10:59:09.563474 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12546 10:59:09.566984 Opened device: /dev/dri/card0
12547 10:59:09.573603 N<8>[ 27.161858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12548 10:59:09.574380 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12550 10:59:09.579879 o KMS driver or no outputs, pipes: 8, outputs: 0
12551 10:59:09.583183 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12552 10:59:09.596793 <14>[ 27.188287] [IGT] kms_vblank: executing
12553 10:59:09.603373 IGT-Version: 1.2<14>[ 27.193405] [IGT] kms_vblank: exiting, ret=77
12554 10:59:09.606925 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12555 10:59:09.610116 Opened device: /dev/dri/card0
12556 10:59:09.616543 N<8>[ 27.204817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12557 10:59:09.617324 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12559 10:59:09.623098 o KMS driver or no outputs, pipes: 8, outputs: 0
12560 10:59:09.625929 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12561 10:59:09.639439 <14>[ 27.231409] [IGT] kms_vblank: executing
12562 10:59:09.646246 IGT-Version: 1.2<14>[ 27.236499] [IGT] kms_vblank: exiting, ret=77
12563 10:59:09.649175 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12564 10:59:09.652612 Opened device: /dev/dri/card0
12565 10:59:09.659379 N<8>[ 27.247999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12566 10:59:09.659650 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12568 10:59:09.666228 o KMS driver or no outputs, pipes: 8, outputs: 0
12569 10:59:09.672458 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12570 10:59:09.683114 <14>[ 27.274909] [IGT] kms_vblank: executing
12571 10:59:09.689756 IGT-Version: 1.2<14>[ 27.279970] [IGT] kms_vblank: exiting, ret=77
12572 10:59:09.692980 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12573 10:59:09.696313 Opened device: /dev/dri/card0
12574 10:59:09.703229 N<8>[ 27.291265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12575 10:59:09.703837 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12577 10:59:09.709741 o KMS driver or no outputs, pipes: 8, outputs: 0
12578 10:59:09.713302 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12579 10:59:09.726099 <14>[ 27.317803] [IGT] kms_vblank: executing
12580 10:59:09.733004 IGT-Version: 1.2<14>[ 27.322816] [IGT] kms_vblank: exiting, ret=77
12581 10:59:09.736145 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12582 10:59:09.739488 Opened device: /dev/dri/card0
12583 10:59:09.746479 N<8>[ 27.334167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12584 10:59:09.747277 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12586 10:59:09.752732 o KMS driver or no outputs, pipes: 8, outputs: 0
12587 10:59:09.755939 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12588 10:59:09.769336 <14>[ 27.360789] [IGT] kms_vblank: executing
12589 10:59:09.775931 IGT-Version: 1.2<14>[ 27.365925] [IGT] kms_vblank: exiting, ret=77
12590 10:59:09.779022 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12591 10:59:09.782491 Opened device: /dev/dri/card0
12592 10:59:09.789222 N<8>[ 27.377348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12593 10:59:09.789998 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12595 10:59:09.795511 o KMS driver or no outputs, pipes: 8, outputs: 0
12596 10:59:09.802011 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12597 10:59:09.813414 <14>[ 27.404440] [IGT] kms_vblank: executing
12598 10:59:09.819637 IGT-Version: 1.2<14>[ 27.409436] [IGT] kms_vblank: exiting, ret=77
12599 10:59:09.823045 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12600 10:59:09.826668 Opened device: /dev/dri/card0
12601 10:59:09.832662 N<8>[ 27.420768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12602 10:59:09.833450 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12604 10:59:09.839670 o KMS driver or no outputs, pipes: 8, outputs: 0
12605 10:59:09.842727 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12606 10:59:09.856190 <14>[ 27.447639] [IGT] kms_vblank: executing
12607 10:59:09.862963 IGT-Version: 1.2<14>[ 27.452635] [IGT] kms_vblank: exiting, ret=77
12608 10:59:09.866397 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12609 10:59:09.869332 Opened device: /dev/dri/card0
12610 10:59:09.875806 N<8>[ 27.463965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12611 10:59:09.876496 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12613 10:59:09.879013 o KMS driver or no outputs, pipes: 8, outputs: 0
12614 10:59:09.885868 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12615 10:59:09.898452 <14>[ 27.489848] [IGT] kms_vblank: executing
12616 10:59:09.904681 IGT-Version: 1.2<14>[ 27.494939] [IGT] kms_vblank: exiting, ret=77
12617 10:59:09.908501 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12618 10:59:09.911707 Opened device: /dev/dri/card0
12619 10:59:09.918447 N<8>[ 27.506203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12620 10:59:09.919225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12622 10:59:09.921798 o KMS driver or no outputs, pipes: 8, outputs: 0
12623 10:59:09.928157 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12624 10:59:09.940067 <14>[ 27.532017] [IGT] kms_vblank: executing
12625 10:59:09.947086 IGT-Version: 1.2<14>[ 27.536995] [IGT] kms_vblank: exiting, ret=77
12626 10:59:09.950371 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12627 10:59:09.953442 Opened device: /dev/dri/card0
12628 10:59:09.960196 N<8>[ 27.548329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12629 10:59:09.960977 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12631 10:59:09.963392 o KMS driver or no outputs, pipes: 8, outputs: 0
12632 10:59:09.969890 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12633 10:59:09.982669 <14>[ 27.574309] [IGT] kms_vblank: executing
12634 10:59:09.989465 IGT-Version: 1.2<14>[ 27.579300] [IGT] kms_vblank: exiting, ret=77
12635 10:59:09.993037 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12636 10:59:09.995841 Opened device: /dev/dri/card0
12637 10:59:10.002478 N<8>[ 27.590675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12638 10:59:10.003274 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12640 10:59:10.006227 o KMS driver or no outputs, pipes: 8, outputs: 0
12641 10:59:10.012477 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12642 10:59:10.024585 <14>[ 27.616505] [IGT] kms_vblank: executing
12643 10:59:10.031768 IGT-Version: 1.2<14>[ 27.621507] [IGT] kms_vblank: exiting, ret=77
12644 10:59:10.034971 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12645 10:59:10.038426 Opened device: /dev/dri/card0
12646 10:59:10.044840 N<8>[ 27.632815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12647 10:59:10.045518 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12649 10:59:10.048165 o KMS driver or no outputs, pipes: 8, outputs: 0
12650 10:59:10.054827 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12651 10:59:10.067372 <14>[ 27.658910] [IGT] kms_vblank: executing
12652 10:59:10.074292 IGT-Version: 1.2<14>[ 27.664168] [IGT] kms_vblank: exiting, ret=77
12653 10:59:10.077536 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12654 10:59:10.080622 Opened device: /dev/dri/card0
12655 10:59:10.087071 N<8>[ 27.675133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12656 10:59:10.087785 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12658 10:59:10.090359 o KMS driver or no outputs, pipes: 8, outputs: 0
12659 10:59:10.096745 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12660 10:59:10.108992 <14>[ 27.700932] [IGT] kms_vblank: executing
12661 10:59:10.115865 IGT-Version: 1.2<14>[ 27.705910] [IGT] kms_vblank: exiting, ret=77
12662 10:59:10.118960 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12663 10:59:10.122907 Opened device: /dev/dri/card0
12664 10:59:10.129745 N<8>[ 27.717241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12665 10:59:10.130524 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12667 10:59:10.133052 o KMS driver or no outputs, pipes: 8, outputs: 0
12668 10:59:10.139293 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12669 10:59:10.152620 <14>[ 27.743630] [IGT] kms_vblank: executing
12670 10:59:10.159036 IGT-Version: 1.2<14>[ 27.748706] [IGT] kms_vblank: exiting, ret=77
12671 10:59:10.162311 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12672 10:59:10.165606 Opened device: /dev/dri/card0
12673 10:59:10.172054 N<8>[ 27.760056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12674 10:59:10.172836 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12676 10:59:10.175234 o KMS driver or no outputs, pipes: 8, outputs: 0
12677 10:59:10.182391 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12678 10:59:10.195169 <14>[ 27.786351] [IGT] kms_vblank: executing
12679 10:59:10.201181 IGT-Version: 1.2<14>[ 27.791374] [IGT] kms_vblank: exiting, ret=77
12680 10:59:10.204310 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12681 10:59:10.208269 Opened device: /dev/dri/card0
12682 10:59:10.214786 N<8>[ 27.802729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12683 10:59:10.215571 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12685 10:59:10.221465 o KMS driver or no outputs, pipes: 8, outputs: 0
12686 10:59:10.224457 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12687 10:59:10.238086 <14>[ 27.829374] [IGT] kms_vblank: executing
12688 10:59:10.244505 IGT-Version: 1.2<14>[ 27.834398] [IGT] kms_vblank: exiting, ret=77
12689 10:59:10.247815 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12690 10:59:10.251180 Opened device: /dev/dri/card0
12691 10:59:10.257658 N<8>[ 27.845638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12692 10:59:10.258412 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12694 10:59:10.260985 o KMS driver or no outputs, pipes: 8, outputs: 0
12695 10:59:10.264196 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12696 10:59:10.280065 <14>[ 27.871337] [IGT] kms_vblank: executing
12697 10:59:10.286383 IGT-Version: 1.2<14>[ 27.876559] [IGT] kms_vblank: exiting, ret=77
12698 10:59:10.290106 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12699 10:59:10.293232 Opened device: /dev/dri/card0
12700 10:59:10.299994 N<8>[ 27.887759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12701 10:59:10.300673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12703 10:59:10.303174 o KMS driver or no outputs, pipes: 8, outputs: 0
12704 10:59:10.309425 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12705 10:59:10.321828 <14>[ 27.913635] [IGT] kms_vblank: executing
12706 10:59:10.328788 IGT-Version: 1.2<14>[ 27.918618] [IGT] kms_vblank: exiting, ret=77
12707 10:59:10.331860 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12708 10:59:10.335000 Opened device: /dev/dri/card0
12709 10:59:10.342229 N<8>[ 27.930140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12710 10:59:10.343035 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12712 10:59:10.345145 o KMS driver or no outputs, pipes: 8, outputs: 0
12713 10:59:10.352007 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12714 10:59:10.363695 <14>[ 27.955644] [IGT] kms_vblank: executing
12715 10:59:10.371170 IGT-Version: 1.2<14>[ 27.960670] [IGT] kms_vblank: exiting, ret=77
12716 10:59:10.374289 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12717 10:59:10.377596 Opened device: /dev/dri/card0
12718 10:59:10.383909 N<8>[ 27.972052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12719 10:59:10.384684 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12721 10:59:10.386983 o KMS driver or no outputs, pipes: 8, outputs: 0
12722 10:59:10.393713 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12723 10:59:10.406716 <14>[ 27.998081] [IGT] kms_vblank: executing
12724 10:59:10.412808 IGT-Version: 1.2<14>[ 28.003049] [IGT] kms_vblank: exiting, ret=77
12725 10:59:10.416689 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12726 10:59:10.419262 Opened device: /dev/dri/card0
12727 10:59:10.426044 N<8>[ 28.014288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12728 10:59:10.426831 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12730 10:59:12.635354 o KMS driver or no outputs, pipes: 8, outputs: 0
12731 10:59:12.635730 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12732 10:59:12.636045 <14>[ 28.039909] [IGT] kms_vblank: executing
12733 10:59:12.636345 IGT-Version: 1.2<14>[ 28.044891] [IGT] kms_vblank: exiting, ret=77
12734 10:59:12.636637 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12735 10:59:12.636929 Opened device: /dev/dri/card0
12736 10:59:12.637214 N<8>[ 28.056297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12737 10:59:12.637504 o KMS driver or no outputs, pipes: 8, outputs: 0
12738 10:59:12.637783 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12739 10:59:12.638061 <14>[ 28.081965] [IGT] kms_vblank: executing
12740 10:59:12.638338 IGT-Version: 1.2<14>[ 28.086952] [IGT] kms_vblank: exiting, ret=77
12741 10:59:12.638615 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12742 10:59:12.638895 Opened device: /dev/dri/card0
12743 10:59:12.639170 N<8>[ 28.098240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12744 10:59:12.639490 o KMS driver or no outputs, pipes: 8, outputs: 0
12745 10:59:12.639766 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12746 10:59:12.640039 <14>[ 28.125376] [IGT] kms_vblank: executing
12747 10:59:12.640380 IGT-Version: 1.2<14>[ 28.130371] [IGT] kms_vblank: exiting, ret=77
12748 10:59:12.640674 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12749 10:59:12.640953 Opened device: /dev/dri/card0
12750 10:59:12.641227 N<8>[ 28.142455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12751 10:59:12.641506 o KMS driver or no outputs, pipes: 8, outputs: 0
12752 10:59:12.641780 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12753 10:59:12.642051 <14>[ 28.169529] [IGT] kms_vblank: executing
12754 10:59:12.642321 IGT-Version: 1.2<14>[ 28.174574] [IGT] kms_vblank: exiting, ret=77
12755 10:59:12.642697 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12756 10:59:12.642998 Opened device: /dev/dri/card0
12757 10:59:12.643277 N<8>[ 28.186767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12758 10:59:12.643625 o KMS driver or no outputs, pipes: 8, outputs: 0
12759 10:59:12.643903 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12760 10:59:12.644276 <14>[ 28.213825] [IGT] kms_vblank: executing
12761 10:59:12.644567 IGT-Version: 1.2<14>[ 28.218785] [IGT] kms_vblank: exiting, ret=77
12762 10:59:12.644840 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12763 10:59:12.645119 Opened device: /dev/dri/card0
12764 10:59:12.645393 N<8>[ 28.230507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12765 10:59:12.645674 o KMS driver or no outputs, pipes: 8, outputs: 0
12766 10:59:12.645950 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12767 10:59:12.646219 <14>[ 28.256950] [IGT] kms_vblank: executing
12768 10:59:12.646490 IGT-Version: 1.2<14>[ 28.262059] [IGT] kms_vblank: exiting, ret=77
12769 10:59:12.646829 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12770 10:59:12.647125 Opened device: /dev/dri/card0
12771 10:59:12.647436 N<8>[ 28.273481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12772 10:59:12.647722 o KMS driver or no outputs, pipes: 8, outputs: 0
12773 10:59:12.648069 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12774 10:59:12.648394 <14>[ 28.300236] [IGT] kms_vblank: executing
12775 10:59:12.648672 IGT-Version: 1.2<14>[ 28.305367] [IGT] kms_vblank: exiting, ret=77
12776 10:59:12.648947 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12777 10:59:12.649227 Opened device: /dev/dri/card0
12778 10:59:12.649498 N<8>[ 28.316722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12779 10:59:12.649776 o KMS driver or no outputs, pipes: 8, outputs: 0
12780 10:59:12.650051 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12781 10:59:12.650325 <14>[ 28.344043] [IGT] kms_vblank: executing
12782 10:59:12.650595 IGT-Version: 1.2<14>[ 28.349118] [IGT] kms_vblank: exiting, ret=77
12783 10:59:12.650867 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12784 10:59:12.651250 Opened device: /dev/dri/card0
12785 10:59:12.651597 N<8>[ 28.360628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12786 10:59:12.651880 o KMS driver or no outputs, pipes: 8, outputs: 0
12787 10:59:12.652177 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12788 10:59:12.652452 <14>[ 28.387115] [IGT] kms_vblank: executing
12789 10:59:12.652723 IGT-Version: 1.2<14>[ 28.392332] [IGT] kms_vblank: exiting, ret=77
12790 10:59:12.652994 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12791 10:59:12.653273 Opened device: /dev/dri/card0
12792 10:59:12.653545 N<8>[ 28.403458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12793 10:59:12.653818 o KMS driver or no outputs, pipes: 8, outputs: 0
12794 10:59:12.654088 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12795 10:59:12.654360 <14>[ 28.430269] [IGT] kms_vblank: executing
12796 10:59:12.654719 IGT-Version: 1.2<14>[ 28.435258] [IGT] kms_vblank: exiting, ret=77
12797 10:59:12.655002 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12798 10:59:12.655282 Opened device: /dev/dri/card0
12799 10:59:12.655596 N<8>[ 28.446763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12800 10:59:12.655941 o KMS driver or no outputs, pipes: 8, outputs: 0
12801 10:59:12.656504 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12803 10:59:12.657640 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12805 10:59:12.658673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12807 10:59:12.659852 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12809 10:59:12.661112 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12811 10:59:12.662088 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12813 10:59:12.663037 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12815 10:59:12.664020 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12817 10:59:12.665023 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12819 10:59:12.665977 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12821 10:59:12.667008 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12822 10:59:12.667391 <14>[ 28.473520] [IGT] kms_vblank: executing
12823 10:59:12.667677 IGT-Version: 1.2<14>[ 28.478543] [IGT] kms_vblank: exiting, ret=77
12824 10:59:12.667889 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12825 10:59:12.668104 Opened device: /dev/dri/card0
12826 10:59:12.668311 N<8>[ 28.490235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12827 10:59:12.668521 o KMS driver or no outputs, pipes: 8, outputs: 0
12828 10:59:12.668794 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12829 10:59:12.669004 <14>[ 28.516888] [IGT] kms_vblank: executing
12830 10:59:12.669209 IGT-Version: 1.2<14>[ 28.521877] [IGT] kms_vblank: exiting, ret=77
12831 10:59:12.669411 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12832 10:59:12.669617 Opened device: /dev/dri/card0
12833 10:59:12.669817 N<8>[ 28.533304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12834 10:59:12.670021 o KMS driver or no outputs, pipes: 8, outputs: 0
12835 10:59:12.670222 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12836 10:59:12.670422 <14>[ 28.559032] [IGT] kms_vblank: executing
12837 10:59:12.670622 IGT-Version: 1.2<14>[ 28.564102] [IGT] kms_vblank: exiting, ret=77
12838 10:59:12.670822 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12839 10:59:12.671024 Opened device: /dev/dri/card0
12840 10:59:12.671226 N<8>[ 28.575277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12841 10:59:12.671465 o KMS driver or no outputs, pipes: 8, outputs: 0
12842 10:59:12.671668 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12843 10:59:12.671868 <14>[ 28.600889] [IGT] kms_vblank: executing
12844 10:59:12.672113 IGT-Version: 1.2<14>[ 28.605888] [IGT] kms_vblank: exiting, ret=77
12845 10:59:12.672326 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12846 10:59:12.672529 Opened device: /dev/dri/card0
12847 10:59:12.672680 N<8>[ 28.617299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12848 10:59:12.672833 o KMS driver or no outputs, pipes: 8, outputs: 0
12849 10:59:12.672983 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12850 10:59:12.673133 <14>[ 28.643341] [IGT] kms_vblank: executing
12851 10:59:12.673313 IGT-Version: 1.2<14>[ 28.648606] [IGT] kms_vblank: exiting, ret=77
12852 10:59:12.673474 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12853 10:59:12.673628 Opened device: /dev/dri/card0
12854 10:59:12.673778 N<8>[ 28.659702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12855 10:59:12.673932 o KMS driver or no outputs, pipes: 8, outputs: 0
12856 10:59:12.674084 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12857 10:59:12.674233 <14>[ 28.685406] [IGT] kms_vblank: executing
12858 10:59:12.674410 IGT-Version: 1.2<14>[ 28.690408] [IGT] kms_vblank: exiting, ret=77
12859 10:59:12.674573 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12860 10:59:12.674725 Opened device: /dev/dri/card0
12861 10:59:12.674875 N<8>[ 28.701683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12862 10:59:12.675028 o KMS driver or no outputs, pipes: 8, outputs: 0
12863 10:59:12.675178 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12864 10:59:12.675339 <14>[ 28.727790] [IGT] kms_vblank: executing
12865 10:59:12.675498 IGT-Version: 1.2<14>[ 28.732759] [IGT] kms_vblank: exiting, ret=77
12866 10:59:12.675692 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12867 10:59:12.675849 Opened device: /dev/dri/card0
12868 10:59:12.676001 N<8>[ 28.744166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12869 10:59:12.676152 o KMS driver or no outputs, pipes: 8, outputs: 0
12870 10:59:12.676303 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12871 10:59:12.676452 <14>[ 28.770019] [IGT] kms_vblank: executing
12872 10:59:12.676601 IGT-Version: 1.2<14>[ 28.775124] [IGT] kms_vblank: exiting, ret=77
12873 10:59:12.676750 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12874 10:59:12.676903 Opened device: /dev/dri/card0
12875 10:59:12.677054 N<8>[ 28.786364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12876 10:59:12.677204 o KMS driver or no outputs, pipes: 8, outputs: 0
12877 10:59:12.677354 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12878 10:59:12.677549 <14>[ 28.813283] [IGT] kms_vblank: executing
12879 10:59:12.677675 IGT-Version: 1.2<14>[ 28.818247] [IGT] kms_vblank: exiting, ret=77
12880 10:59:12.677795 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12881 10:59:12.677953 Opened device: /dev/dri/card0
12882 10:59:12.678076 N<8>[ 28.829788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12883 10:59:12.678198 o KMS driver or no outputs, pipes: 8, outputs: 0
12884 10:59:12.678320 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12885 10:59:12.678440 <14>[ 28.855860] [IGT] kms_vblank: executing
12886 10:59:12.678559 IGT-Version: 1.2<14>[ 28.860838] [IGT] kms_vblank: exiting, ret=77
12887 10:59:12.678679 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12888 10:59:12.678803 Opened device: /dev/dri/card0
12889 10:59:12.678923 N<8>[ 28.872089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12890 10:59:12.679045 o KMS driver or no outputs, pipes: 8, outputs: 0
12891 10:59:12.679165 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12892 10:59:12.679285 <14>[ 28.899511] [IGT] kms_vblank: executing
12893 10:59:12.679645 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12895 10:59:12.680051 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12897 10:59:12.680454 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12899 10:59:12.680858 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12901 10:59:12.681260 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12903 10:59:12.681698 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12905 10:59:12.682104 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12907 10:59:12.682512 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12909 10:59:12.682865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12911 10:59:12.683228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12913 10:59:12.683722 IGT-Version: 1.2<14>[ 28.904653] [IGT] kms_vblank: exiting, ret=77
12914 10:59:12.683847 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12915 10:59:12.683961 Opened device: /dev/dri/card0
12916 10:59:12.684070 N<8>[ 28.916324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12917 10:59:12.684177 o KMS driver or no outputs, pipes: 8, outputs: 0
12918 10:59:12.684288 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12919 10:59:12.684392 <14>[ 28.942495] [IGT] kms_vblank: executing
12920 10:59:12.684495 IGT-Version: 1.2<14>[ 28.947767] [IGT] kms_vblank: exiting, ret=77
12921 10:59:12.684597 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12922 10:59:12.684699 Opened device: /dev/dri/card0
12923 10:59:12.684800 N<8>[ 28.959002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12924 10:59:12.684903 o KMS driver or no outputs, pipes: 8, outputs: 0
12925 10:59:12.685003 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12926 10:59:12.685103 <14>[ 28.984839] [IGT] kms_vblank: executing
12927 10:59:12.685203 IGT-Version: 1.2<14>[ 28.989813] [IGT] kms_vblank: exiting, ret=77
12928 10:59:12.685304 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12929 10:59:12.685407 Opened device: /dev/dri/card0
12930 10:59:12.685507 N<8>[ 29.001266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12931 10:59:12.685608 o KMS driver or no outputs, pipes: 8, outputs: 0
12932 10:59:12.685708 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12933 10:59:12.685808 <14>[ 29.026746] [IGT] kms_vblank: executing
12934 10:59:12.685908 IGT-Version: 1.2<14>[ 29.031907] [IGT] kms_vblank: exiting, ret=77
12935 10:59:12.686008 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12936 10:59:12.686109 Opened device: /dev/dri/card0
12937 10:59:12.686211 N<8>[ 29.043040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12938 10:59:12.686312 o KMS driver or no outputs, pipes: 8, outputs: 0
12939 10:59:12.686413 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12940 10:59:12.686513 <14>[ 29.069358] [IGT] kms_vblank: executing
12941 10:59:12.686612 IGT-Version: 1.2<14>[ 29.074329] [IGT] kms_vblank: exiting, ret=77
12942 10:59:12.686711 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12943 10:59:12.686813 Opened device: /dev/dri/card0
12944 10:59:12.686913 N<8>[ 29.085593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12945 10:59:12.687015 o KMS driver or no outputs, pipes: 8, outputs: 0
12946 10:59:12.687115 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12947 10:59:12.687215 <14>[ 29.111256] [IGT] kms_vblank: executing
12948 10:59:12.687315 IGT-Version: 1.2<14>[ 29.116455] [IGT] kms_vblank: exiting, ret=77
12949 10:59:12.687440 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12950 10:59:12.687554 Opened device: /dev/dri/card0
12951 10:59:12.687640 N<8>[ 29.127397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12952 10:59:12.687727 o KMS driver or no outputs, pipes: 8, outputs: 0
12953 10:59:12.687812 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12954 10:59:12.687897 <14>[ 29.153526] [IGT] kms_vblank: executing
12955 10:59:12.687983 IGT-Version: 1.2<14>[ 29.158529] [IGT] kms_vblank: exiting, ret=77
12956 10:59:12.688069 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12957 10:59:12.688156 Opened device: /dev/dri/card0
12958 10:59:12.688242 N<8>[ 29.169772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12959 10:59:12.688329 o KMS driver or no outputs, pipes: 8, outputs: 0
12960 10:59:12.688415 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12961 10:59:12.688499 <14>[ 29.196027] [IGT] kms_vblank: executing
12962 10:59:12.688584 IGT-Version: 1.2<14>[ 29.201023] [IGT] kms_vblank: exiting, ret=77
12963 10:59:12.688670 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12964 10:59:12.688757 Opened device: /dev/dri/card0
12965 10:59:12.688843 N<8>[ 29.212384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12966 10:59:12.688931 o KMS driver or no outputs, pipes: 8, outputs: 0
12967 10:59:12.689018 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12968 10:59:12.689103 <14>[ 29.238960] [IGT] kms_vblank: executing
12969 10:59:12.689190 IGT-Version: 1.2<14>[ 29.244005] [IGT] kms_vblank: exiting, ret=77
12970 10:59:12.689275 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12971 10:59:12.689377 Opened device: /dev/dri/card0
12972 10:59:12.689475 N<8>[ 29.255118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12973 10:59:12.689563 o KMS driver or no outputs, pipes: 8, outputs: 0
12974 10:59:12.689650 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
12975 10:59:12.689736 <14>[ 29.281521] [IGT] kms_vblank: executing
12976 10:59:12.689822 IGT-Version: 1.2<14>[ 29.286609] [IGT] kms_vblank: exiting, ret=77
12977 10:59:12.689907 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12978 10:59:12.689995 Opened device: /dev/dri/card0
12979 10:59:12.690082 N<8>[ 29.297880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
12980 10:59:12.690170 o KMS driver or no outputs, pipes: 8, outputs: 0
12981 10:59:12.690256 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
12982 10:59:12.690343 <14>[ 29.324642] [IGT] kms_vblank: executing
12983 10:59:12.690429 IGT-Version: 1.2<14>[ 29.329772] [IGT] kms_vblank: exiting, ret=77
12984 10:59:12.690514 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12985 10:59:12.690610 Opened device: /dev/dri/card0
12986 10:59:12.690888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12988 10:59:12.691179 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12990 10:59:12.691494 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12992 10:59:12.691797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12994 10:59:12.692092 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12996 10:59:12.692382 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12998 10:59:12.692688 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13000 10:59:12.693006 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13002 10:59:12.693267 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13004 10:59:12.693520 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13006 10:59:12.693821 N<8>[ 29.341060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13007 10:59:12.693914 o KMS driver or no outputs, pipes: 8, outputs: 0
13008 10:59:12.693998 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13009 10:59:12.694079 <14>[ 29.367689] [IGT] kms_vblank: executing
13010 10:59:12.694157 IGT-Version: 1.2<14>[ 29.372787] [IGT] kms_vblank: exiting, ret=77
13011 10:59:12.694235 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13012 10:59:12.694315 Opened device: /dev/dri/card0
13013 10:59:12.694392 N<8>[ 29.384097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13014 10:59:12.694470 o KMS driver or no outputs, pipes: 8, outputs: 0
13015 10:59:12.694547 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13016 10:59:12.694623 <14>[ 29.411038] [IGT] kms_vblank: executing
13017 10:59:12.694699 IGT-Version: 1.2<14>[ 29.416289] [IGT] kms_vblank: exiting, ret=77
13018 10:59:12.694773 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13019 10:59:12.694850 Opened device: /dev/dri/card0
13020 10:59:12.694926 N<8>[ 29.427238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13021 10:59:12.695003 o KMS driver or no outputs, pipes: 8, outputs: 0
13022 10:59:12.695078 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13023 10:59:12.695153 <14>[ 29.454094] [IGT] kms_vblank: executing
13024 10:59:12.695228 IGT-Version: 1.2<14>[ 29.459127] [IGT] kms_vblank: exiting, ret=77
13025 10:59:12.695304 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13026 10:59:12.695395 Opened device: /dev/dri/card0
13027 10:59:12.695472 N<8>[ 29.470292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13028 10:59:12.695549 o KMS driver or no outputs, pipes: 8, outputs: 0
13029 10:59:12.695624 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13030 10:59:12.695699 <14>[ 29.497038] [IGT] kms_vblank: executing
13031 10:59:12.695774 IGT-Version: 1.2<14>[ 29.502113] [IGT] kms_vblank: exiting, ret=77
13032 10:59:12.695849 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13033 10:59:12.695925 Opened device: /dev/dri/card0
13034 10:59:12.696001 N<8>[ 29.513354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13035 10:59:12.696078 o KMS driver or no outputs, pipes: 8, outputs: 0
13036 10:59:12.696153 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13037 10:59:12.696228 <14>[ 29.540589] [IGT] kms_vblank: executing
13038 10:59:12.696303 IGT-Version: 1.2<14>[ 29.545690] [IGT] kms_vblank: exiting, ret=77
13039 10:59:12.696378 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13040 10:59:12.696455 Opened device: /dev/dri/card0
13041 10:59:12.696530 N<8>[ 29.557063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13042 10:59:12.696608 o KMS driver or no outputs, pipes: 8, outputs: 0
13043 10:59:12.696684 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13044 10:59:12.696759 <14>[ 29.583933] [IGT] kms_vblank: executing
13045 10:59:12.696835 IGT-Version: 1.2<14>[ 29.588943] [IGT] kms_vblank: exiting, ret=77
13046 10:59:12.696911 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13047 10:59:12.696987 Opened device: /dev/dri/card0
13048 10:59:12.697065 N<8>[ 29.600357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13049 10:59:12.697140 o KMS driver or no outputs, pipes: 8, outputs: 0
13050 10:59:12.697217 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13051 10:59:12.697293 <14>[ 29.626315] [IGT] kms_vblank: executing
13052 10:59:12.697368 IGT-Version: 1.2<14>[ 29.631325] [IGT] kms_vblank: exiting, ret=77
13053 10:59:12.697443 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13054 10:59:12.697532 Opened device: /dev/dri/card0
13055 10:59:12.697600 N<8>[ 29.642587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13056 10:59:12.697668 o KMS driver or no outputs, pipes: 8, outputs: 0
13057 10:59:12.697735 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13058 10:59:12.697801 <14>[ 29.668356] [IGT] kms_vblank: executing
13059 10:59:12.697868 IGT-Version: 1.2<14>[ 29.673344] [IGT] kms_vblank: exiting, ret=77
13060 10:59:12.697960 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13061 10:59:12.698031 Opened device: /dev/dri/card0
13062 10:59:12.698098 N<8>[ 29.684549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13063 10:59:12.698167 o KMS driver or no outputs, pipes: 8, outputs: 0
13064 10:59:12.698234 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13065 10:59:12.698302 <14>[ 29.710603] [IGT] kms_vblank: executing
13066 10:59:12.698369 IGT-Version: 1.2<14>[ 29.715647] [IGT] kms_vblank: exiting, ret=77
13067 10:59:12.698436 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13068 10:59:12.698504 Opened device: /dev/dri/card0
13069 10:59:12.698570 N<8>[ 29.726965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13070 10:59:12.698638 o KMS driver or no outputs, pipes: 8, outputs: 0
13071 10:59:12.698704 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13072 10:59:12.698771 <14>[ 29.752558] [IGT] kms_vblank: executing
13073 10:59:12.698837 IGT-Version: 1.2<14>[ 29.757550] [IGT] kms_vblank: exiting, ret=77
13074 10:59:12.698903 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13075 10:59:12.698972 Opened device: /dev/dri/card0
13076 10:59:12.699039 N<8>[ 29.768868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13077 10:59:12.699289 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13079 10:59:12.699531 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13081 10:59:12.699758 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13083 10:59:12.699982 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13085 10:59:12.700206 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13087 10:59:12.700431 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13089 10:59:12.700657 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13091 10:59:12.700880 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13093 10:59:12.701102 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13095 10:59:12.701325 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13097 10:59:12.701586 o KMS driver or no outputs, pipes: 8, outputs: 0
13098 10:59:12.701668 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13099 10:59:12.701743 <14>[ 29.795077] [IGT] kms_vblank: executing
13100 10:59:12.701814 IGT-Version: 1.2<14>[ 29.800224] [IGT] kms_vblank: exiting, ret=77
13101 10:59:12.701884 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13102 10:59:12.701955 Opened device: /dev/dri/card0
13103 10:59:12.702024 N<8>[ 29.811310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13104 10:59:12.702094 o KMS driver or no outputs, pipes: 8, outputs: 0
13105 10:59:12.702162 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13106 10:59:12.702230 <14>[ 29.837071] [IGT] kms_vblank: executing
13107 10:59:12.702321 IGT-Version: 1.2<14>[ 29.842053] [IGT] kms_vblank: exiting, ret=77
13108 10:59:12.702392 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13109 10:59:12.702462 Opened device: /dev/dri/card0
13110 10:59:12.702537 N<8>[ 29.853465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13111 10:59:12.702600 o KMS driver or no outputs, pipes: 8, outputs: 0
13112 10:59:12.702661 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13113 10:59:12.702726 <14>[ 29.879361] [IGT] kms_vblank: executing
13114 10:59:12.702799 IGT-Version: 1.2<14>[ 29.884518] [IGT] kms_vblank: exiting, ret=77
13115 10:59:12.702860 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13116 10:59:12.702922 Opened device: /dev/dri/card0
13117 10:59:12.702984 N<8>[ 29.895713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13118 10:59:12.703070 o KMS driver or no outputs, pipes: 8, outputs: 0
13119 10:59:12.703169 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13120 10:59:12.703278 <14>[ 29.922027] [IGT] kms_vblank: executing
13121 10:59:12.703374 IGT-Version: 1.2<14>[ 29.927102] [IGT] kms_vblank: exiting, ret=77
13122 10:59:12.703437 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13123 10:59:12.703507 Opened device: /dev/dri/card0
13124 10:59:12.703569 N<8>[ 29.938461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13125 10:59:12.703632 o KMS driver or no outputs, pipes: 8, outputs: 0
13126 10:59:12.703739 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13127 10:59:12.703839 <14>[ 29.965169] [IGT] kms_vblank: executing
13128 10:59:12.703948 IGT-Version: 1.2<14>[ 29.970207] [IGT] kms_vblank: exiting, ret=77
13129 10:59:12.704044 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13130 10:59:12.704139 Opened device: /dev/dri/card0
13131 10:59:12.704234 N<8>[ 29.981499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13132 10:59:12.704329 o KMS driver or no outputs, pipes: 8, outputs: 0
13133 10:59:12.704423 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13134 10:59:12.704517 <14>[ 30.006925] [IGT] kms_vblank: executing
13135 10:59:12.704611 IGT-Version: 1.2<14>[ 30.011950] [IGT] kms_vblank: exiting, ret=77
13136 10:59:12.704705 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13137 10:59:12.704800 Opened device: /dev/dri/card0
13138 10:59:12.704895 N<8>[ 30.023076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13139 10:59:12.704990 o KMS driver or no outputs, pipes: 8, outputs: 0
13140 10:59:12.705084 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13141 10:59:12.705177 <14>[ 30.049045] [IGT] kms_vblank: executing
13142 10:59:12.705271 IGT-Version: 1.2<14>[ 30.053993] [IGT] kms_vblank: exiting, ret=77
13143 10:59:12.705364 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13144 10:59:12.705459 Opened device: /dev/dri/card0
13145 10:59:12.705554 N<8>[ 30.065606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13146 10:59:12.705648 o KMS driver or no outputs, pipes: 8, outputs: 0
13147 10:59:12.705742 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13148 10:59:12.705835 <14>[ 30.091250] [IGT] kms_vblank: executing
13149 10:59:12.705929 IGT-Version: 1.2<14>[ 30.096481] [IGT] kms_vblank: exiting, ret=77
13150 10:59:12.706022 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13151 10:59:12.706117 Opened device: /dev/dri/card0
13152 10:59:12.706212 N<8>[ 30.107815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13153 10:59:12.706307 o KMS driver or no outputs, pipes: 8, outputs: 0
13154 10:59:12.706401 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13155 10:59:12.706494 <14>[ 30.133695] [IGT] kms_vblank: executing
13156 10:59:12.706588 IGT-Version: 1.2<14>[ 30.138668] [IGT] kms_vblank: exiting, ret=77
13157 10:59:12.706681 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13158 10:59:12.706776 Opened device: /dev/dri/card0
13159 10:59:12.706871 N<8>[ 30.149986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13160 10:59:12.706965 o KMS driver or no outputs, pipes: 8, outputs: 0
13161 10:59:12.707059 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13162 10:59:12.707152 <14>[ 30.175479] [IGT] kms_vblank: executing
13163 10:59:12.707245 IGT-Version: 1.2<14>[ 30.180487] [IGT] kms_vblank: exiting, ret=77
13164 10:59:12.707342 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13165 10:59:12.707407 Opened device: /dev/dri/card0
13166 10:59:12.707468 N<8>[ 30.191825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13167 10:59:12.707538 o KMS driver or no outputs, pipes: 8, outputs: 0
13168 10:59:12.707593 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13169 10:59:12.707648 <14>[ 30.217882] [IGT] kms_vblank: executing
13170 10:59:12.707877 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13172 10:59:12.708064 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13174 10:59:12.708249 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13176 10:59:12.708435 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13178 10:59:12.708621 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13180 10:59:12.708805 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13182 10:59:12.708989 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13184 10:59:12.709175 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13186 10:59:12.709361 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13188 10:59:12.709544 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13190 10:59:12.709734 IGT-Version: 1.2<14>[ 30.222860] [IGT] kms_vblank: exiting, ret=77
13191 10:59:12.709800 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13192 10:59:12.709862 Opened device: /dev/dri/card0
13193 10:59:12.709922 N<8>[ 30.234255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13194 10:59:12.709980 o KMS driver or no outputs, pipes: 8, outputs: 0
13195 10:59:12.710038 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13196 10:59:12.710094 <14>[ 30.260310] [IGT] kms_vblank: executing
13197 10:59:12.710150 IGT-Version: 1.2<14>[ 30.265399] [IGT] kms_vblank: exiting, ret=77
13198 10:59:12.710207 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13199 10:59:12.710264 Opened device: /dev/dri/card0
13200 10:59:12.710321 N<8>[ 30.276648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13201 10:59:12.710377 o KMS driver or no outputs, pipes: 8, outputs: 0
13202 10:59:12.710432 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13203 10:59:12.710663 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13205 10:59:12.710851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13207 10:59:12.711161 <14>[ 30.303378] [IGT] kms_vblank: executing
13208 10:59:12.717929 IGT-Version: 1.2<14>[ 30.308576] [IGT] kms_vblank: exiting, ret=77
13209 10:59:12.721267 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13210 10:59:12.724366 Opened device: /dev/dri/card0
13211 10:59:12.730897 N<8>[ 30.319889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13212 10:59:12.731288 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13214 10:59:12.737425 o KMS driver or no outputs, pipes: 8, outputs: 0
13215 10:59:12.741210 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13216 10:59:12.754437 <14>[ 30.346317] [IGT] kms_vblank: executing
13217 10:59:12.760818 IGT-Version: 1.2<14>[ 30.351337] [IGT] kms_vblank: exiting, ret=77
13218 10:59:12.764178 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13219 10:59:12.767825 Opened device: /dev/dri/card0
13220 10:59:12.774242 N<8>[ 30.362551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13221 10:59:12.774931 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13223 10:59:12.781412 o KMS driver or no outputs, pipes: 8, outputs: 0
13224 10:59:12.784217 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13225 10:59:12.797169 <14>[ 30.389323] [IGT] kms_vblank: executing
13226 10:59:12.804345 IGT-Version: 1.2<14>[ 30.394417] [IGT] kms_vblank: exiting, ret=77
13227 10:59:12.807525 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13228 10:59:12.810631 Opened device: /dev/dri/card0
13229 10:59:12.817484 N<8>[ 30.405619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13230 10:59:12.818285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13232 10:59:12.823826 o KMS driver or no outputs, pipes: 8, outputs: 0
13233 10:59:12.827466 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13234 10:59:12.840957 <14>[ 30.432590] [IGT] kms_vblank: executing
13235 10:59:12.847028 IGT-Version: 1.2<14>[ 30.437721] [IGT] kms_vblank: exiting, ret=77
13236 10:59:12.850387 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13237 10:59:12.854292 Opened device: /dev/dri/card0
13238 10:59:12.860769 N<8>[ 30.449063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13239 10:59:12.861538 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13241 10:59:12.867623 o KMS driver or no outputs, pipes: 8, outputs: 0
13242 10:59:12.873630 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13243 10:59:12.884012 <14>[ 30.476094] [IGT] kms_vblank: executing
13244 10:59:12.890547 IGT-Version: 1.2<14>[ 30.481180] [IGT] kms_vblank: exiting, ret=77
13245 10:59:12.893940 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13246 10:59:12.897215 Opened device: /dev/dri/card0
13247 10:59:12.904107 N<8>[ 30.492492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13248 10:59:12.904792 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13250 10:59:12.910968 o KMS driver or no outputs, pipes: 8, outputs: 0
13251 10:59:12.914394 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13252 10:59:12.927081 <14>[ 30.519176] [IGT] kms_vblank: executing
13253 10:59:12.933589 IGT-Version: 1.2<14>[ 30.524382] [IGT] kms_vblank: exiting, ret=77
13254 10:59:12.937348 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13255 10:59:12.940631 Opened device: /dev/dri/card0
13256 10:59:12.946814 N<8>[ 30.535516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13257 10:59:12.947498 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13259 10:59:12.953388 o KMS driver or no outputs, pipes: 8, outputs: 0
13260 10:59:12.956603 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13261 10:59:12.970000 <14>[ 30.562215] [IGT] kms_vblank: executing
13262 10:59:12.976744 IGT-Version: 1.2<14>[ 30.567238] [IGT] kms_vblank: exiting, ret=77
13263 10:59:12.979889 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13264 10:59:12.983539 Opened device: /dev/dri/card0
13265 10:59:12.990502 N<8>[ 30.578474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13266 10:59:12.991314 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13268 10:59:12.997019 o KMS driver or no outputs, pipes: 8, outputs: 0
13269 10:59:13.002946 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13270 10:59:13.013767 <14>[ 30.605658] [IGT] kms_vblank: executing
13271 10:59:13.020307 IGT-Version: 1.2<14>[ 30.610742] [IGT] kms_vblank: exiting, ret=77
13272 10:59:13.023373 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13273 10:59:13.026611 Opened device: /dev/dri/card0
13274 10:59:13.032987 N<8>[ 30.622092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13275 10:59:13.033535 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13277 10:59:13.039783 o KMS driver or no outputs, pipes: 8, outputs: 0
13278 10:59:13.046222 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13279 10:59:13.057193 <14>[ 30.649066] [IGT] kms_vblank: executing
13280 10:59:13.063605 IGT-Version: 1.2<14>[ 30.654047] [IGT] kms_vblank: exiting, ret=77
13281 10:59:13.067155 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13282 10:59:13.070510 Opened device: /dev/dri/card0
13283 10:59:13.076890 N<8>[ 30.665385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13284 10:59:13.077595 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13286 10:59:13.079972 o KMS driver or no outputs, pipes: 8, outputs: 0
13287 10:59:13.086923 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13288 10:59:13.098715 <14>[ 30.691129] [IGT] kms_vblank: executing
13289 10:59:13.106255 IGT-Version: 1.2<14>[ 30.696276] [IGT] kms_vblank: exiting, ret=77
13290 10:59:13.109280 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13291 10:59:13.112528 Opened device: /dev/dri/card0
13292 10:59:13.118822 N<8>[ 30.707333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13293 10:59:13.119517 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13295 10:59:13.122069 o KMS driver or no outputs, pipes: 8, outputs: 0
13296 10:59:13.128444 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13297 10:59:13.141471 <14>[ 30.733257] [IGT] kms_vblank: executing
13298 10:59:13.147949 IGT-Version: 1.2<14>[ 30.738234] [IGT] kms_vblank: exiting, ret=77
13299 10:59:13.151231 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13300 10:59:13.154426 Opened device: /dev/dri/card0
13301 10:59:13.161449 N<8>[ 30.749522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13302 10:59:13.162130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13304 10:59:13.164666 o KMS driver or no outputs, pipes: 8, outputs: 0
13305 10:59:13.171153 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13306 10:59:13.183700 <14>[ 30.775533] [IGT] kms_vblank: executing
13307 10:59:13.190130 IGT-Version: 1.2<14>[ 30.780616] [IGT] kms_vblank: exiting, ret=77
13308 10:59:13.193705 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13309 10:59:13.196600 Opened device: /dev/dri/card0
13310 10:59:13.203648 N<8>[ 30.791953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13311 10:59:13.204354 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13313 10:59:13.206831 o KMS driver or no outputs, pipes: 8, outputs: 0
13314 10:59:13.213116 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13315 10:59:13.225805 <14>[ 30.817693] [IGT] kms_vblank: executing
13316 10:59:13.232067 IGT-Version: 1.2<14>[ 30.822669] [IGT] kms_vblank: exiting, ret=77
13317 10:59:13.236115 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13318 10:59:13.239512 Opened device: /dev/dri/card0
13319 10:59:13.245818 N<8>[ 30.833981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13320 10:59:13.246578 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13322 10:59:13.248994 o KMS driver or no outputs, pipes: 8, outputs: 0
13323 10:59:13.255682 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13324 10:59:13.268403 <14>[ 30.860312] [IGT] kms_vblank: executing
13325 10:59:13.274983 IGT-Version: 1.2<14>[ 30.865356] [IGT] kms_vblank: exiting, ret=77
13326 10:59:13.278223 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13327 10:59:13.281394 Opened device: /dev/dri/card0
13328 10:59:13.288404 N<8>[ 30.876604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13329 10:59:13.289129 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13331 10:59:13.291105 o KMS driver or no outputs, pipes: 8, outputs: 0
13332 10:59:13.297965 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13333 10:59:13.310291 <14>[ 30.902493] [IGT] kms_vblank: executing
13334 10:59:13.316703 IGT-Version: 1.2<14>[ 30.907476] [IGT] kms_vblank: exiting, ret=77
13335 10:59:13.320627 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13336 10:59:13.323733 Opened device: /dev/dri/card0
13337 10:59:13.330341 N<8>[ 30.918809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13338 10:59:13.331112 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13340 10:59:13.333483 o KMS driver or no outputs, pipes: 8, outputs: 0
13341 10:59:13.340066 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13342 10:59:13.352996 <14>[ 30.944865] [IGT] kms_vblank: executing
13343 10:59:13.359029 IGT-Version: 1.2<14>[ 30.949936] [IGT] kms_vblank: exiting, ret=77
13344 10:59:13.362890 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13345 10:59:13.366012 Opened device: /dev/dri/card0
13346 10:59:13.372530 N<8>[ 30.961382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13347 10:59:13.373228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13349 10:59:13.379024 o KMS driver or no outputs, pipes: 8, outputs: 0
13350 10:59:13.382331 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13351 10:59:13.395268 <14>[ 30.987440] [IGT] kms_vblank: executing
13352 10:59:13.402533 IGT-Version: 1.2<14>[ 30.992485] [IGT] kms_vblank: exiting, ret=77
13353 10:59:13.405468 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13354 10:59:13.408463 Opened device: /dev/dri/card0
13355 10:59:13.415082 N<8>[ 31.003804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13356 10:59:13.415823 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13358 10:59:13.421599 o KMS driver or no outputs, pipes: 8, outputs: 0
13359 10:59:13.425044 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13360 10:59:13.438302 <14>[ 31.030156] [IGT] kms_vblank: executing
13361 10:59:13.444840 IGT-Version: 1.2<14>[ 31.035269] [IGT] kms_vblank: exiting, ret=77
13362 10:59:13.448060 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13363 10:59:13.451228 Opened device: /dev/dri/card0
13364 10:59:13.458185 N<8>[ 31.046450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13365 10:59:13.458964 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13367 10:59:13.461431 o KMS driver or no outputs, pipes: 8, outputs: 0
13368 10:59:13.467721 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13369 10:59:13.480210 <14>[ 31.072130] [IGT] kms_vblank: executing
13370 10:59:13.486708 IGT-Version: 1.2<14>[ 31.077112] [IGT] kms_vblank: exiting, ret=77
13371 10:59:13.490070 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13372 10:59:13.493253 Opened device: /dev/dri/card0
13373 10:59:13.499669 N<8>[ 31.088443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13374 10:59:13.500520 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13376 10:59:13.502895 o KMS driver or no outputs, pipes: 8, outputs: 0
13377 10:59:13.510217 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13378 10:59:13.522317 <14>[ 31.114101] [IGT] kms_vblank: executing
13379 10:59:13.529003 IGT-Version: 1.2<14>[ 31.119198] [IGT] kms_vblank: exiting, ret=77
13380 10:59:13.532039 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13381 10:59:13.535076 Opened device: /dev/dri/card0
13382 10:59:13.541998 N<8>[ 31.130497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13383 10:59:13.542683 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13385 10:59:13.545091 o KMS driver or no outputs, pipes: 8, outputs: 0
13386 10:59:13.551643 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13387 10:59:13.563761 <14>[ 31.156054] [IGT] kms_vblank: executing
13388 10:59:13.570693 IGT-Version: 1.2<14>[ 31.161137] [IGT] kms_vblank: exiting, ret=77
13389 10:59:13.574280 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13390 10:59:13.577350 Opened device: /dev/dri/card0
13391 10:59:13.583919 N<8>[ 31.172415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13392 10:59:13.584592 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13394 10:59:13.587255 o KMS driver or no outputs, pipes: 8, outputs: 0
13395 10:59:13.593526 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13396 10:59:13.606259 <14>[ 31.198546] [IGT] kms_vblank: executing
13397 10:59:13.613207 IGT-Version: 1.2<14>[ 31.203670] [IGT] kms_vblank: exiting, ret=77
13398 10:59:13.616459 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13399 10:59:13.619598 Opened device: /dev/dri/card0
13400 10:59:13.626249 N<8>[ 31.214737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13401 10:59:13.626920 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13403 10:59:13.629520 o KMS driver or no outputs, pipes: 8, outputs: 0
13404 10:59:13.636232 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13405 10:59:13.648584 <14>[ 31.240536] [IGT] kms_vblank: executing
13406 10:59:13.655126 IGT-Version: 1.2<14>[ 31.245638] [IGT] kms_vblank: exiting, ret=77
13407 10:59:13.658368 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13408 10:59:13.661904 Opened device: /dev/dri/card0
13409 10:59:13.668567 N<8>[ 31.256856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13410 10:59:13.669243 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13412 10:59:13.671778 o KMS driver or no outputs, pipes: 8, outputs: 0
13413 10:59:13.678031 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13414 10:59:13.690284 <14>[ 31.282666] [IGT] kms_vblank: executing
13415 10:59:13.697408 IGT-Version: 1.2<14>[ 31.287665] [IGT] kms_vblank: exiting, ret=77
13416 10:59:13.700646 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13417 10:59:13.704005 Opened device: /dev/dri/card0
13418 10:59:13.710690 N<8>[ 31.298918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13419 10:59:13.711459 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13421 10:59:13.713716 o KMS driver or no outputs, pipes: 8, outputs: 0
13422 10:59:13.720103 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13423 10:59:13.733039 <14>[ 31.325276] [IGT] kms_vblank: executing
13424 10:59:13.739875 IGT-Version: 1.2<14>[ 31.330284] [IGT] kms_vblank: exiting, ret=77
13425 10:59:13.742880 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13426 10:59:13.746428 Opened device: /dev/dri/card0
13427 10:59:13.753236 N<8>[ 31.341453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13428 10:59:13.753930 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13430 10:59:13.759867 o KMS driver or no outputs, pipes: 8, outputs: 0
13431 10:59:13.762844 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13432 10:59:13.775702 <14>[ 31.367934] [IGT] kms_vblank: executing
13433 10:59:13.782505 IGT-Version: 1.2<14>[ 31.373002] [IGT] kms_vblank: exiting, ret=77
13434 10:59:13.785805 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13435 10:59:13.789070 Opened device: /dev/dri/card0
13436 10:59:13.796196 N<8>[ 31.384465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13437 10:59:13.796961 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13439 10:59:13.802462 o KMS driver or no outputs, pipes: 8, outputs: 0
13440 10:59:13.805905 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13441 10:59:13.819151 <14>[ 31.410684] [IGT] kms_vblank: executing
13442 10:59:13.825530 IGT-Version: 1.2<14>[ 31.415858] [IGT] kms_vblank: exiting, ret=77
13443 10:59:13.828477 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13444 10:59:13.831787 Opened device: /dev/dri/card0
13445 10:59:13.838337 N<8>[ 31.426856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13446 10:59:13.839124 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13448 10:59:13.845457 o KMS driver or no outputs, pipes: 8, outputs: 0
13449 10:59:13.848622 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13450 10:59:13.861542 <14>[ 31.453819] [IGT] kms_vblank: executing
13451 10:59:13.868461 IGT-Version: 1.2<14>[ 31.458920] [IGT] kms_vblank: exiting, ret=77
13452 10:59:13.871847 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13453 10:59:13.874643 Opened device: /dev/dri/card0
13454 10:59:13.881775 N<8>[ 31.470151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13455 10:59:13.882616 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13457 10:59:13.887989 o KMS driver or no outputs, pipes: 8, outputs: 0
13458 10:59:13.891607 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13459 10:59:13.905372 <14>[ 31.497122] [IGT] kms_vblank: executing
13460 10:59:13.911960 IGT-Version: 1.2<14>[ 31.502131] [IGT] kms_vblank: exiting, ret=77
13461 10:59:13.914973 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13462 10:59:13.918380 Opened device: /dev/dri/card0
13463 10:59:13.924822 N<8>[ 31.513414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13464 10:59:13.925536 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13466 10:59:13.931770 o KMS driver or no outputs, pipes: 8, outputs: 0
13467 10:59:13.938447 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13468 10:59:13.948960 <14>[ 31.540790] [IGT] kms_vblank: executing
13469 10:59:13.955539 IGT-Version: 1.2<14>[ 31.545920] [IGT] kms_vblank: exiting, ret=77
13470 10:59:13.958708 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13471 10:59:13.962123 Opened device: /dev/dri/card0
13472 10:59:13.968421 N<8>[ 31.557170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13473 10:59:13.969163 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13475 10:59:13.975056 o KMS driver or no outputs, pipes: 8, outputs: 0
13476 10:59:13.978579 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13477 10:59:13.992252 <14>[ 31.584298] [IGT] kms_vblank: executing
13478 10:59:13.998349 IGT-Version: 1.2<14>[ 31.589286] [IGT] kms_vblank: exiting, ret=77
13479 10:59:14.001967 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13480 10:59:14.005081 Opened device: /dev/dri/card0
13481 10:59:14.011535 N<8>[ 31.600534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13482 10:59:14.012249 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13484 10:59:14.018653 o KMS driver or no outputs, pipes: 8, outputs: 0
13485 10:59:14.022102 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13486 10:59:14.035269 <14>[ 31.627255] [IGT] kms_vblank: executing
13487 10:59:14.041922 IGT-Version: 1.2<14>[ 31.632510] [IGT] kms_vblank: exiting, ret=77
13488 10:59:14.045103 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13489 10:59:14.048563 Opened device: /dev/dri/card0
13490 10:59:14.054997 N<8>[ 31.643468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13491 10:59:14.056006 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13493 10:59:14.061478 o KMS driver or no outputs, pipes: 8, outputs: 0
13494 10:59:14.068323 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13495 10:59:14.078573 <14>[ 31.670708] [IGT] kms_vblank: executing
13496 10:59:14.085223 IGT-Version: 1.2<14>[ 31.675750] [IGT] kms_vblank: exiting, ret=77
13497 10:59:14.088304 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13498 10:59:14.091882 Opened device: /dev/dri/card0
13499 10:59:14.098297 N<8>[ 31.686742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13500 10:59:14.098973 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13502 10:59:14.105201 o KMS driver or no outputs, pipes: 8, outputs: 0
13503 10:59:14.108481 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13504 10:59:14.121836 <14>[ 31.713976] [IGT] kms_vblank: executing
13505 10:59:14.128524 IGT-Version: 1.2<14>[ 31.718983] [IGT] kms_vblank: exiting, ret=77
13506 10:59:14.131685 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13507 10:59:14.134697 Opened device: /dev/dri/card0
13508 10:59:14.141213 N<8>[ 31.730233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13509 10:59:14.141471 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13511 10:59:14.144246 o KMS driver or no outputs, pipes: 8, outputs: 0
13512 10:59:14.150933 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13513 10:59:14.163498 <14>[ 31.756006] [IGT] kms_vblank: executing
13514 10:59:14.169996 IGT-Version: 1.2<14>[ 31.761094] [IGT] kms_vblank: exiting, ret=77
13515 10:59:14.173410 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13516 10:59:14.176655 Opened device: /dev/dri/card0
13517 10:59:14.183048 N<8>[ 31.772401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13518 10:59:14.183303 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13520 10:59:14.186838 o KMS driver or no outputs, pipes: 8, outputs: 0
13521 10:59:14.193202 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13522 10:59:14.205301 <14>[ 31.797985] [IGT] kms_vblank: executing
13523 10:59:14.211738 IGT-Version: 1.2<14>[ 31.802984] [IGT] kms_vblank: exiting, ret=77
13524 10:59:14.215636 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13525 10:59:14.218710 Opened device: /dev/dri/card0
13526 10:59:14.224941 N<8>[ 31.814392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13527 10:59:14.225197 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13529 10:59:14.228657 o KMS driver or no outputs, pipes: 8, outputs: 0
13530 10:59:14.235214 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13531 10:59:14.248601 <14>[ 31.840511] [IGT] kms_vblank: executing
13532 10:59:14.254739 IGT-Version: 1.2<14>[ 31.845506] [IGT] kms_vblank: exiting, ret=77
13533 10:59:14.258573 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13534 10:59:14.261886 Opened device: /dev/dri/card0
13535 10:59:14.268481 N<8>[ 31.856854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13536 10:59:14.269239 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13538 10:59:14.271540 o KMS driver or no outputs, pipes: 8, outputs: 0
13539 10:59:14.278329 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13540 10:59:14.290706 <14>[ 31.882658] [IGT] kms_vblank: executing
13541 10:59:14.297005 IGT-Version: 1.2<14>[ 31.887763] [IGT] kms_vblank: exiting, ret=77
13542 10:59:14.300610 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13543 10:59:14.303630 Opened device: /dev/dri/card0
13544 10:59:14.310216 N<8>[ 31.898826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13545 10:59:14.310908 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13547 10:59:14.314128 o KMS driver or no outputs, pipes: 8, outputs: 0
13548 10:59:14.320750 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13549 10:59:14.333161 <14>[ 31.925255] [IGT] kms_vblank: executing
13550 10:59:14.339604 IGT-Version: 1.2<14>[ 31.930379] [IGT] kms_vblank: exiting, ret=77
13551 10:59:14.342848 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13552 10:59:14.346095 Opened device: /dev/dri/card0
13553 10:59:14.353141 N<8>[ 31.941629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13554 10:59:14.353837 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13556 10:59:14.356594 o KMS driver or no outputs, pipes: 8, outputs: 0
13557 10:59:14.362912 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13558 10:59:14.375073 <14>[ 31.967504] [IGT] kms_vblank: executing
13559 10:59:14.382246 IGT-Version: 1.2<14>[ 31.972627] [IGT] kms_vblank: exiting, ret=77
13560 10:59:14.385647 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13561 10:59:14.388592 Opened device: /dev/dri/card0
13562 10:59:14.395050 N<8>[ 31.983947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13563 10:59:14.395812 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13565 10:59:14.398466 o KMS driver or no outputs, pipes: 8, outputs: 0
13566 10:59:14.405087 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13567 10:59:14.417575 <14>[ 32.009993] [IGT] kms_vblank: executing
13568 10:59:14.424834 IGT-Version: 1.2<14>[ 32.015017] [IGT] kms_vblank: exiting, ret=77
13569 10:59:14.427456 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13570 10:59:14.430789 Opened device: /dev/dri/card0
13571 10:59:14.437633 N<8>[ 32.026282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13572 10:59:14.438489 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13574 10:59:14.444363 o KMS driver or no outputs, pipes: 8, outputs: 0
13575 10:59:14.447802 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13576 10:59:14.460171 <14>[ 32.052411] [IGT] kms_vblank: executing
13577 10:59:14.467186 IGT-Version: 1.2<14>[ 32.057525] [IGT] kms_vblank: exiting, ret=77
13578 10:59:14.470230 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13579 10:59:14.473383 Opened device: /dev/dri/card0
13580 10:59:14.480349 N<8>[ 32.069027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13581 10:59:14.481081 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13583 10:59:14.486848 o KMS driver or no outputs, pipes: 8, outputs: 0
13584 10:59:14.489954 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13585 10:59:14.503885 <14>[ 32.096121] [IGT] kms_vblank: executing
13586 10:59:14.510735 IGT-Version: 1.2<14>[ 32.101082] [IGT] kms_vblank: exiting, ret=77
13587 10:59:14.513872 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13588 10:59:14.517322 Opened device: /dev/dri/card0
13589 10:59:14.524180 N<8>[ 32.112400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13590 10:59:14.524875 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13592 10:59:14.527383 o KMS driver or no outputs, pipes: 8, outputs: 0
13593 10:59:14.530786 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13594 10:59:14.546230 <14>[ 32.138719] [IGT] kms_vblank: executing
13595 10:59:14.552971 IGT-Version: 1.2<14>[ 32.143775] [IGT] kms_vblank: exiting, ret=77
13596 10:59:14.556410 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13597 10:59:14.559648 Opened device: /dev/dri/card0
13598 10:59:14.566879 N<8>[ 32.155423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13599 10:59:14.567689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13601 10:59:14.570132 o KMS driver or no outputs, pipes: 8, outputs: 0
13602 10:59:14.576669 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13603 10:59:14.589694 <14>[ 32.182037] [IGT] kms_vblank: executing
13604 10:59:14.596338 IGT-Version: 1.2<14>[ 32.187271] [IGT] kms_vblank: exiting, ret=77
13605 10:59:14.599415 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13606 10:59:14.602933 Opened device: /dev/dri/card0
13607 10:59:14.609420 N<8>[ 32.198584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13608 10:59:14.610124 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13610 10:59:14.612683 o KMS driver or no outputs, pipes: 8, outputs: 0
13611 10:59:14.619429 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13612 10:59:14.633770 <14>[ 32.225582] [IGT] kms_vblank: executing
13613 10:59:14.640292 IGT-Version: 1.2<14>[ 32.230597] [IGT] kms_vblank: exiting, ret=77
13614 10:59:14.643506 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13615 10:59:14.646702 Opened device: /dev/dri/card0
13616 10:59:14.653036 N<8>[ 32.241984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13617 10:59:14.653782 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13619 10:59:14.656794 o KMS driver or no outputs, pipes: 8, outputs: 0
13620 10:59:14.663406 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13621 10:59:14.675748 <14>[ 32.268080] [IGT] kms_vblank: executing
13622 10:59:14.682309 IGT-Version: 1.2<14>[ 32.273043] [IGT] kms_vblank: exiting, ret=77
13623 10:59:14.686056 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13624 10:59:14.689207 Opened device: /dev/dri/card0
13625 10:59:14.695424 N<8>[ 32.284419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13626 10:59:14.696118 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13628 10:59:14.698893 o KMS driver or no outputs, pipes: 8, outputs: 0
13629 10:59:14.705402 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13630 10:59:14.717823 <14>[ 32.309811] [IGT] kms_vblank: executing
13631 10:59:14.724421 IGT-Version: 1.2<14>[ 32.314894] [IGT] kms_vblank: exiting, ret=77
13632 10:59:14.727413 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13633 10:59:14.730870 Opened device: /dev/dri/card0
13634 10:59:14.737618 N<8>[ 32.326151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13635 10:59:14.738403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13637 10:59:14.740769 o KMS driver or no outputs, pipes: 8, outputs: 0
13638 10:59:14.747145 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13639 10:59:14.760147 <14>[ 32.352384] [IGT] kms_vblank: executing
13640 10:59:14.766597 IGT-Version: 1.2<14>[ 32.357366] [IGT] kms_vblank: exiting, ret=77
13641 10:59:14.770297 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13642 10:59:14.773654 Opened device: /dev/dri/card0
13643 10:59:14.779966 N<8>[ 32.368645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13644 10:59:14.780654 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13646 10:59:14.783223 o KMS driver or no outputs, pipes: 8, outputs: 0
13647 10:59:14.789866 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13648 10:59:14.802370 <14>[ 32.394841] [IGT] kms_vblank: executing
13649 10:59:14.808790 IGT-Version: 1.2<14>[ 32.399906] [IGT] kms_vblank: exiting, ret=77
13650 10:59:14.812971 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13651 10:59:14.815963 Opened device: /dev/dri/card0
13652 10:59:14.822643 N<8>[ 32.410974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13653 10:59:14.823457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13655 10:59:14.829136 o KMS driver or no outputs, pipes: 8, outputs: 0
13656 10:59:14.832119 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13657 10:59:14.845483 <14>[ 32.437780] [IGT] kms_vblank: executing
13658 10:59:14.852433 IGT-Version: 1.2<14>[ 32.442768] [IGT] kms_vblank: exiting, ret=77
13659 10:59:14.855749 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13660 10:59:14.859003 Opened device: /dev/dri/card0
13661 10:59:14.865557 N<8>[ 32.454161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13662 10:59:14.866352 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13664 10:59:14.872446 o KMS driver or no outputs, pipes: 8, outputs: 0
13665 10:59:14.875673 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13666 10:59:14.888263 <14>[ 32.480655] [IGT] kms_vblank: executing
13667 10:59:14.894959 IGT-Version: 1.2<14>[ 32.485636] [IGT] kms_vblank: exiting, ret=77
13668 10:59:14.898608 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13669 10:59:14.901886 Opened device: /dev/dri/card0
13670 10:59:14.908509 N<8>[ 32.497040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13671 10:59:14.909548 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13673 10:59:14.915199 o KMS driver or no outputs, pipes: 8, outputs: 0
13674 10:59:14.918510 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13675 10:59:14.931645 <14>[ 32.523702] [IGT] kms_vblank: executing
13676 10:59:14.937986 IGT-Version: 1.2<14>[ 32.528696] [IGT] kms_vblank: exiting, ret=77
13677 10:59:14.941612 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13678 10:59:14.944412 Opened device: /dev/dri/card0
13679 10:59:14.951302 N<8>[ 32.540100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13680 10:59:14.952092 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13682 10:59:14.957779 o KMS driver or no outputs, pipes: 8, outputs: 0
13683 10:59:14.961614 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13684 10:59:14.974223 <14>[ 32.566822] [IGT] kms_vblank: executing
13685 10:59:14.980824 IGT-Version: 1.2<14>[ 32.571869] [IGT] kms_vblank: exiting, ret=77
13686 10:59:14.984507 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13687 10:59:14.987386 Opened device: /dev/dri/card0
13688 10:59:14.994687 N<8>[ 32.582968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13689 10:59:14.995449 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13691 10:59:15.001001 o KMS driver or no outputs, pipes: 8, outputs: 0
13692 10:59:15.007558 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13693 10:59:15.017806 <14>[ 32.610263] [IGT] kms_vblank: executing
13694 10:59:15.024753 IGT-Version: 1.2<14>[ 32.615322] [IGT] kms_vblank: exiting, ret=77
13695 10:59:15.028122 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13696 10:59:15.031398 Opened device: /dev/dri/card0
13697 10:59:15.037982 N<8>[ 32.626580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13698 10:59:15.038726 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13700 10:59:15.044285 o KMS driver or no outputs, pipes: 8, outputs: 0
13701 10:59:15.047766 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13702 10:59:15.061420 <14>[ 32.653527] [IGT] kms_vblank: executing
13703 10:59:15.067846 IGT-Version: 1.2<14>[ 32.658593] [IGT] kms_vblank: exiting, ret=77
13704 10:59:15.070842 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13705 10:59:15.074020 Opened device: /dev/dri/card0
13706 10:59:15.081200 N<8>[ 32.669860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13707 10:59:15.081902 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13709 10:59:15.087764 o KMS driver or no outputs, pipes: 8, outputs: 0
13710 10:59:15.090907 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13711 10:59:15.104219 <14>[ 32.696831] [IGT] kms_vblank: executing
13712 10:59:15.111274 IGT-Version: 1.2<14>[ 32.701831] [IGT] kms_vblank: exiting, ret=77
13713 10:59:15.114729 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13714 10:59:15.117933 Opened device: /dev/dri/card0
13715 10:59:15.124464 N<8>[ 32.713071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13716 10:59:15.125158 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13718 10:59:15.131275 o KMS driver or no outputs, pipes: 8, outputs: 0
13719 10:59:15.134569 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13720 10:59:15.148330 <14>[ 32.740495] [IGT] kms_vblank: executing
13721 10:59:15.155019 IGT-Version: 1.2<14>[ 32.745504] [IGT] kms_vblank: exiting, ret=77
13722 10:59:15.158005 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13723 10:59:15.161882 Opened device: /dev/dri/card0
13724 10:59:15.168302 N<8>[ 32.756761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13725 10:59:15.168981 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13727 10:59:15.174965 o KMS driver or no outputs, pipes: 8, outputs: 0
13728 10:59:15.181029 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13729 10:59:15.192071 <14>[ 32.784134] [IGT] kms_vblank: executing
13730 10:59:15.198437 IGT-Version: 1.2<14>[ 32.789129] [IGT] kms_vblank: exiting, ret=77
13731 10:59:15.201602 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13732 10:59:15.204881 Opened device: /dev/dri/card0
13733 10:59:15.211420 N<8>[ 32.800937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13734 10:59:15.212213 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13736 10:59:15.215380 o KMS driver or no outputs, pipes: 8, outputs: 0
13737 10:59:15.221367 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13738 10:59:15.234203 <14>[ 32.826452] [IGT] kms_vblank: executing
13739 10:59:15.240678 IGT-Version: 1.2<14>[ 32.831518] [IGT] kms_vblank: exiting, ret=77
13740 10:59:15.244565 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13741 10:59:15.247660 Opened device: /dev/dri/card0
13742 10:59:15.254314 N<8>[ 32.843192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13743 10:59:15.254993 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13745 10:59:15.257353 o KMS driver or no outputs, pipes: 8, outputs: 0
13746 10:59:15.263856 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13747 10:59:15.277712 <14>[ 32.869724] [IGT] kms_vblank: executing
13748 10:59:15.283866 IGT-Version: 1.2<14>[ 32.874714] [IGT] kms_vblank: exiting, ret=77
13749 10:59:15.287611 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13750 10:59:15.290921 Opened device: /dev/dri/card0
13751 10:59:15.297534 N<8>[ 32.886765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13752 10:59:15.298302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13754 10:59:15.300764 o KMS driver or no outputs, pipes: 8, outputs: 0
13755 10:59:15.307176 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13756 10:59:15.321233 <14>[ 32.913686] [IGT] kms_vblank: executing
13757 10:59:15.328025 IGT-Version: 1.2<14>[ 32.918722] [IGT] kms_vblank: exiting, ret=77
13758 10:59:15.331647 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13759 10:59:15.334492 Opened device: /dev/dri/card0
13760 10:59:15.341701 N<8>[ 32.930841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13761 10:59:15.342592 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13763 10:59:15.344854 o KMS driver or no outputs, pipes: 8, outputs: 0
13764 10:59:15.351103 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13765 10:59:15.364595 <14>[ 32.957198] [IGT] kms_vblank: executing
13766 10:59:15.371368 IGT-Version: 1.2<14>[ 32.962174] [IGT] kms_vblank: exiting, ret=77
13767 10:59:15.374901 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13768 10:59:15.377938 Opened device: /dev/dri/card0
13769 10:59:15.384476 N<8>[ 32.974148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13770 10:59:15.385222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13772 10:59:15.387935 o KMS driver or no outputs, pipes: 8, outputs: 0
13773 10:59:15.394217 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13774 10:59:15.407307 <14>[ 32.999765] [IGT] kms_vblank: executing
13775 10:59:15.414010 IGT-Version: 1.2<14>[ 33.004745] [IGT] kms_vblank: exiting, ret=77
13776 10:59:15.417484 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13777 10:59:15.421026 Opened device: /dev/dri/card0
13778 10:59:15.427459 N<8>[ 33.016211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13779 10:59:15.428148 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13781 10:59:15.430622 o KMS driver or no outputs, pipes: 8, outputs: 0
13782 10:59:15.436845 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13783 10:59:15.448664 <14>[ 33.041445] [IGT] kms_vblank: executing
13784 10:59:15.455597 IGT-Version: 1.2<14>[ 33.046502] [IGT] kms_vblank: exiting, ret=77
13785 10:59:15.458730 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13786 10:59:15.462201 Opened device: /dev/dri/card0
13787 10:59:15.468610 N<8>[ 33.058045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13788 10:59:15.468866 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13790 10:59:15.471631 o KMS driver or no outputs, pipes: 8, outputs: 0
13791 10:59:15.478550 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13792 10:59:15.491001 <14>[ 33.083800] [IGT] kms_vblank: executing
13793 10:59:15.497793 IGT-Version: 1.2<14>[ 33.088879] [IGT] kms_vblank: exiting, ret=77
13794 10:59:15.501049 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13795 10:59:15.504265 Opened device: /dev/dri/card0
13796 10:59:15.511164 N<8>[ 33.100299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13797 10:59:15.511423 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13799 10:59:15.517559 o KMS driver or no outputs, pipes: 8, outputs: 0
13800 10:59:15.520706 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13801 10:59:15.533557 <14>[ 33.126343] [IGT] kms_vblank: executing
13802 10:59:15.540154 IGT-Version: 1.2<14>[ 33.131449] [IGT] kms_vblank: exiting, ret=77
13803 10:59:15.543371 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13804 10:59:15.546760 Opened device: /dev/dri/card0
13805 10:59:15.553910 N<8>[ 33.142754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13806 10:59:15.554168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13808 10:59:15.560433 o KMS driver or no outputs, pipes: 8, outputs: 0
13809 10:59:15.563610 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13810 10:59:15.576643 <14>[ 33.169478] [IGT] kms_vblank: executing
13811 10:59:15.583446 IGT-Version: 1.2<14>[ 33.174581] [IGT] kms_vblank: exiting, ret=77
13812 10:59:15.586577 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13813 10:59:15.590232 Opened device: /dev/dri/card0
13814 10:59:15.596667 N<8>[ 33.185886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13815 10:59:15.596925 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13817 10:59:15.599953 o KMS driver or no outputs, pipes: 8, outputs: 0
13818 10:59:15.606828 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13819 10:59:15.618399 <14>[ 33.211315] [IGT] kms_vblank: executing
13820 10:59:15.624863 IGT-Version: 1.2<14>[ 33.216533] [IGT] kms_vblank: exiting, ret=77
13821 10:59:15.628647 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13822 10:59:15.631866 Opened device: /dev/dri/card0
13823 10:59:15.638243 N<8>[ 33.228042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13824 10:59:15.638500 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13826 10:59:15.641480 o KMS driver or no outputs, pipes: 8, outputs: 0
13827 10:59:15.648024 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13828 10:59:15.661237 <14>[ 33.253622] [IGT] kms_vblank: executing
13829 10:59:15.667649 IGT-Version: 1.2<14>[ 33.258620] [IGT] kms_vblank: exiting, ret=77
13830 10:59:15.670927 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13831 10:59:15.674396 Opened device: /dev/dri/card0
13832 10:59:15.680900 N<8>[ 33.269854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13833 10:59:15.681616 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13835 10:59:15.684527 o KMS driver or no outputs, pipes: 8, outputs: 0
13836 10:59:15.691355 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13837 10:59:15.703591 <14>[ 33.295733] [IGT] kms_vblank: executing
13838 10:59:15.709587 IGT-Version: 1.2<14>[ 33.300729] [IGT] kms_vblank: exiting, ret=77
13839 10:59:15.713163 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13840 10:59:15.716528 Opened device: /dev/dri/card0
13841 10:59:15.723011 N<8>[ 33.312487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13842 10:59:15.723309 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13844 10:59:15.726270 o KMS driver or no outputs, pipes: 8, outputs: 0
13845 10:59:15.732786 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13846 10:59:15.746395 <14>[ 33.339272] [IGT] kms_vblank: executing
13847 10:59:15.753461 IGT-Version: 1.2<14>[ 33.344708] [IGT] kms_vblank: exiting, ret=77
13848 10:59:15.756739 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13849 10:59:15.759967 Opened device: /dev/dri/card0
13850 10:59:15.766589 N<8>[ 33.356045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13851 10:59:15.766876 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13853 10:59:15.769684 o KMS driver or no outputs, pipes: 8, outputs: 0
13854 10:59:15.776106 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13855 10:59:15.788320 <14>[ 33.381224] [IGT] kms_vblank: executing
13856 10:59:15.794836 IGT-Version: 1.2<14>[ 33.386215] [IGT] kms_vblank: exiting, ret=77
13857 10:59:15.798599 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13858 10:59:15.801581 Opened device: /dev/dri/card0
13859 10:59:15.808420 N<8>[ 33.398439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13860 10:59:15.808709 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13862 10:59:15.811310 o KMS driver or no outputs, pipes: 8, outputs: 0
13863 10:59:15.818032 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13864 10:59:15.832109 <14>[ 33.424625] [IGT] kms_vblank: executing
13865 10:59:15.838455 IGT-Version: 1.2<14>[ 33.429633] [IGT] kms_vblank: exiting, ret=77
13866 10:59:15.841808 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13867 10:59:15.844900 Opened device: /dev/dri/card0
13868 10:59:15.851300 N<8>[ 33.441555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13869 10:59:15.851610 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13871 10:59:15.854563 o KMS driver or no outputs, pipes: 8, outputs: 0
13872 10:59:15.861842 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13873 10:59:15.874154 <14>[ 33.467265] [IGT] kms_vblank: executing
13874 10:59:15.881203 IGT-Version: 1.2<14>[ 33.472451] [IGT] kms_vblank: exiting, ret=77
13875 10:59:15.884336 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13876 10:59:15.887610 Opened device: /dev/dri/card0
13877 10:59:15.894249 N<8>[ 33.484259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13878 10:59:15.894527 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13880 10:59:15.901159 o KMS driver or no outputs, pipes: 8, outputs: 0
13881 10:59:15.904144 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13882 10:59:15.917164 <14>[ 33.510246] [IGT] kms_vblank: executing
13883 10:59:15.924146 IGT-Version: 1.2<14>[ 33.515263] [IGT] kms_vblank: exiting, ret=77
13884 10:59:15.927181 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13885 10:59:15.930960 Opened device: /dev/dri/card0
13886 10:59:15.937431 N<8>[ 33.527038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13887 10:59:15.937690 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13889 10:59:15.943741 o KMS driver or no outputs, pipes: 8, outputs: 0
13890 10:59:15.946988 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13891 10:59:15.960380 <14>[ 33.553302] [IGT] kms_vblank: executing
13892 10:59:15.967168 IGT-Version: 1.2<14>[ 33.558286] [IGT] kms_vblank: exiting, ret=77
13893 10:59:15.970440 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13894 10:59:15.973842 Opened device: /dev/dri/card0
13895 10:59:15.980261 N<8>[ 33.569929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13896 10:59:15.980568 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13898 10:59:15.987084 o KMS driver or no outputs, pipes: 8, outputs: 0
13899 10:59:15.990444 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13900 10:59:16.004144 <14>[ 33.596631] [IGT] kms_vblank: executing
13901 10:59:16.010473 IGT-Version: 1.2<14>[ 33.601627] [IGT] kms_vblank: exiting, ret=77
13902 10:59:16.013812 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13903 10:59:16.017422 Opened device: /dev/dri/card0
13904 10:59:16.024284 N<8>[ 33.613395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13905 10:59:16.025083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13907 10:59:16.030600 o KMS driver or no outputs, pipes: 8, outputs: 0
13908 10:59:16.033776 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13909 10:59:16.047602 <14>[ 33.640048] [IGT] kms_vblank: executing
13910 10:59:16.054259 IGT-Version: 1.2<14>[ 33.645042] [IGT] kms_vblank: exiting, ret=77
13911 10:59:16.057998 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13912 10:59:16.061186 Opened device: /dev/dri/card0
13913 10:59:16.067639 N<8>[ 33.656969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13914 10:59:16.068367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13916 10:59:16.074479 o KMS driver or no outputs, pipes: 8, outputs: 0
13917 10:59:16.077896 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13918 10:59:16.091442 <14>[ 33.683516] [IGT] kms_vblank: executing
13919 10:59:16.097812 IGT-Version: 1.2<14>[ 33.688682] [IGT] kms_vblank: exiting, ret=77
13920 10:59:16.101093 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13921 10:59:16.104554 Opened device: /dev/dri/card0
13922 10:59:16.110990 N<8>[ 33.700296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13923 10:59:16.111717 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13925 10:59:16.117386 o KMS driver or no outputs, pipes: 8, outputs: 0
13926 10:59:16.120567 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13927 10:59:16.135664 <14>[ 33.728039] [IGT] kms_vblank: executing
13928 10:59:16.142123 IGT-Version: 1.2<14>[ 33.733034] [IGT] kms_vblank: exiting, ret=77
13929 10:59:16.145826 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13930 10:59:16.148711 Opened device: /dev/dri/card0
13931 10:59:16.155706 N<8>[ 33.745050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13932 10:59:16.156441 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13934 10:59:16.162383 o KMS driver or no outputs, pipes: 8, outputs: 0
13935 10:59:16.165598 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13936 10:59:16.178804 <14>[ 33.770974] [IGT] kms_vblank: executing
13937 10:59:16.185449 IGT-Version: 1.2<14>[ 33.776176] [IGT] kms_vblank: exiting, ret=77
13938 10:59:16.188376 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13939 10:59:16.191791 Opened device: /dev/dri/card0
13940 10:59:16.198276 N<8>[ 33.787679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13941 10:59:16.199143 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13943 10:59:16.204836 o KMS driver or no outputs, pipes: 8, outputs: 0
13944 10:59:16.211417 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13945 10:59:16.222416 <14>[ 33.814826] [IGT] kms_vblank: executing
13946 10:59:16.229108 IGT-Version: 1.2<14>[ 33.819906] [IGT] kms_vblank: exiting, ret=77
13947 10:59:16.232729 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13948 10:59:16.235613 Opened device: /dev/dri/card0
13949 10:59:16.242444 N<8>[ 33.831472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13950 10:59:16.243281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13952 10:59:16.249128 o KMS driver or no outputs, pipe<8>[ 33.842818] <LAVA_SIGNAL_TESTSET STOP>
13953 10:59:16.249938 Received signal: <TESTSET> STOP
13954 10:59:16.250501 Closing test_set kms_vblank
13955 10:59:16.258971 s: 8, outputs: 0<8>[ 33.848901] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10591023_1.5.2.3.1>
13956 10:59:16.259453
13957 10:59:16.260042 Received signal: <ENDRUN> 0_igt-kms-mediatek 10591023_1.5.2.3.1
13958 10:59:16.260442 Ending use of test pattern.
13959 10:59:16.260755 Ending test lava.0_igt-kms-mediatek (10591023_1.5.2.3.1), duration 13.59
13961 10:59:16.265467 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13962 10:59:16.265889 + set +x
13963 10:59:16.268767 <LAVA_TEST_RUNNER EXIT>
13964 10:59:16.269409 ok: lava_test_shell seems to have completed
13965 10:59:16.288503 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13966 10:59:16.289132 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13967 10:59:16.289367 end: 3 lava-test-retry (duration 00:00:14) [common]
13968 10:59:16.289603 start: 4 finalize (timeout 00:07:46) [common]
13969 10:59:16.289842 start: 4.1 power-off (timeout 00:00:30) [common]
13970 10:59:16.290248 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
13971 10:59:16.385769 >> Command sent successfully.
13972 10:59:16.395437 Returned 0 in 0 seconds
13973 10:59:16.496630 end: 4.1 power-off (duration 00:00:00) [common]
13975 10:59:16.497999 start: 4.2 read-feedback (timeout 00:07:46) [common]
13976 10:59:16.499185 Listened to connection for namespace 'common' for up to 1s
13977 10:59:17.499437 Finalising connection for namespace 'common'
13978 10:59:17.499598 Disconnecting from shell: Finalise
13979 10:59:17.499677 / #
13980 10:59:17.599994 end: 4.2 read-feedback (duration 00:00:01) [common]
13981 10:59:17.600147 end: 4 finalize (duration 00:00:01) [common]
13982 10:59:17.600257 Cleaning after the job
13983 10:59:17.600353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/ramdisk
13984 10:59:17.605795 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/kernel
13985 10:59:17.611462 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/dtb
13986 10:59:17.611612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591023/tftp-deploy-_ex67_zt/modules
13987 10:59:17.616569 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591023
13988 10:59:17.707684 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591023
13989 10:59:17.707844 Job finished correctly