Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 31
1 10:50:41.276290 lava-dispatcher, installed at version: 2023.05.1
2 10:50:41.276502 start: 0 validate
3 10:50:41.276637 Start time: 2023-06-05 10:50:41.276629+00:00 (UTC)
4 10:50:41.276767 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:50:41.276899 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:50:41.570762 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:50:41.571806 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:50:41.866934 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:50:41.867670 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:51:01.499351 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:51:01.500140 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:51:02.075179 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:51:02.076019 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:51:02.373959 validate duration: 21.10
16 10:51:02.374277 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:51:02.374371 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:51:02.374458 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:51:02.374577 Not decompressing ramdisk as can be used compressed.
20 10:51:02.374659 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:51:02.374722 saving as /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/ramdisk/initrd.cpio.gz
22 10:51:02.374782 total size: 4665601 (4MB)
23 10:51:06.605529 progress 0% (0MB)
24 10:51:06.612837 progress 5% (0MB)
25 10:51:06.619231 progress 10% (0MB)
26 10:51:06.625673 progress 15% (0MB)
27 10:51:06.631808 progress 20% (0MB)
28 10:51:06.636081 progress 25% (1MB)
29 10:51:06.639485 progress 30% (1MB)
30 10:51:06.642522 progress 35% (1MB)
31 10:51:06.645206 progress 40% (1MB)
32 10:51:06.647950 progress 45% (2MB)
33 10:51:06.650129 progress 50% (2MB)
34 10:51:06.652250 progress 55% (2MB)
35 10:51:06.654128 progress 60% (2MB)
36 10:51:06.656012 progress 65% (2MB)
37 10:51:06.657748 progress 70% (3MB)
38 10:51:06.659404 progress 75% (3MB)
39 10:51:06.661053 progress 80% (3MB)
40 10:51:06.662795 progress 85% (3MB)
41 10:51:06.664273 progress 90% (4MB)
42 10:51:06.665737 progress 95% (4MB)
43 10:51:06.667183 progress 100% (4MB)
44 10:51:06.667352 4MB downloaded in 4.29s (1.04MB/s)
45 10:51:06.667511 end: 1.1.1 http-download (duration 00:00:04) [common]
47 10:51:06.667769 end: 1.1 download-retry (duration 00:00:04) [common]
48 10:51:06.667867 start: 1.2 download-retry (timeout 00:09:56) [common]
49 10:51:06.667959 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 10:51:06.668106 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:51:06.668184 saving as /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/kernel/Image
52 10:51:06.668250 total size: 45746688 (43MB)
53 10:51:06.668315 No compression specified
54 10:51:06.669472 progress 0% (0MB)
55 10:51:06.681132 progress 5% (2MB)
56 10:51:06.692684 progress 10% (4MB)
57 10:51:06.704265 progress 15% (6MB)
58 10:51:06.715807 progress 20% (8MB)
59 10:51:06.727332 progress 25% (10MB)
60 10:51:06.738639 progress 30% (13MB)
61 10:51:06.750056 progress 35% (15MB)
62 10:51:06.761420 progress 40% (17MB)
63 10:51:06.772802 progress 45% (19MB)
64 10:51:06.784311 progress 50% (21MB)
65 10:51:06.795711 progress 55% (24MB)
66 10:51:06.807215 progress 60% (26MB)
67 10:51:06.818715 progress 65% (28MB)
68 10:51:06.830198 progress 70% (30MB)
69 10:51:06.841647 progress 75% (32MB)
70 10:51:06.852964 progress 80% (34MB)
71 10:51:06.864548 progress 85% (37MB)
72 10:51:06.876028 progress 90% (39MB)
73 10:51:06.887430 progress 95% (41MB)
74 10:51:06.898686 progress 100% (43MB)
75 10:51:06.898831 43MB downloaded in 0.23s (189.21MB/s)
76 10:51:06.898976 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:51:06.899205 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:51:06.899296 start: 1.3 download-retry (timeout 00:09:55) [common]
80 10:51:06.899429 start: 1.3.1 http-download (timeout 00:09:55) [common]
81 10:51:06.899563 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:51:06.899632 saving as /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/dtb/mt8192-asurada-spherion-r0.dtb
83 10:51:06.899696 total size: 46924 (0MB)
84 10:51:06.899755 No compression specified
85 10:51:06.900870 progress 69% (0MB)
86 10:51:06.901136 progress 100% (0MB)
87 10:51:06.901285 0MB downloaded in 0.00s (28.19MB/s)
88 10:51:06.901403 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:51:06.901619 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:51:06.901701 start: 1.4 download-retry (timeout 00:09:55) [common]
92 10:51:06.901782 start: 1.4.1 http-download (timeout 00:09:55) [common]
93 10:51:06.901892 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:51:06.901958 saving as /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/nfsrootfs/full.rootfs.tar
95 10:51:06.902017 total size: 200770336 (191MB)
96 10:51:06.902075 Using unxz to decompress xz
97 10:51:06.905733 progress 0% (0MB)
98 10:51:07.443862 progress 5% (9MB)
99 10:51:07.955590 progress 10% (19MB)
100 10:51:08.531309 progress 15% (28MB)
101 10:51:08.895313 progress 20% (38MB)
102 10:51:09.216115 progress 25% (47MB)
103 10:51:09.857433 progress 30% (57MB)
104 10:51:10.393440 progress 35% (67MB)
105 10:51:10.974071 progress 40% (76MB)
106 10:51:11.526120 progress 45% (86MB)
107 10:51:12.097633 progress 50% (95MB)
108 10:51:12.718090 progress 55% (105MB)
109 10:51:13.374064 progress 60% (114MB)
110 10:51:13.493806 progress 65% (124MB)
111 10:51:13.636906 progress 70% (134MB)
112 10:51:13.736279 progress 75% (143MB)
113 10:51:13.811520 progress 80% (153MB)
114 10:51:13.880552 progress 85% (162MB)
115 10:51:13.980835 progress 90% (172MB)
116 10:51:14.275217 progress 95% (181MB)
117 10:51:14.871468 progress 100% (191MB)
118 10:51:14.876338 191MB downloaded in 7.97s (24.01MB/s)
119 10:51:14.876695 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:51:14.877058 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:51:14.877162 start: 1.5 download-retry (timeout 00:09:47) [common]
123 10:51:14.877293 start: 1.5.1 http-download (timeout 00:09:47) [common]
124 10:51:14.877450 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:51:14.877555 saving as /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/modules/modules.tar
126 10:51:14.877640 total size: 8542412 (8MB)
127 10:51:14.877757 Using unxz to decompress xz
128 10:51:15.165542 progress 0% (0MB)
129 10:51:15.187863 progress 5% (0MB)
130 10:51:15.213586 progress 10% (0MB)
131 10:51:15.240191 progress 15% (1MB)
132 10:51:15.266798 progress 20% (1MB)
133 10:51:15.293710 progress 25% (2MB)
134 10:51:15.321154 progress 30% (2MB)
135 10:51:15.348129 progress 35% (2MB)
136 10:51:15.373508 progress 40% (3MB)
137 10:51:15.399743 progress 45% (3MB)
138 10:51:15.424408 progress 50% (4MB)
139 10:51:15.448035 progress 55% (4MB)
140 10:51:15.473733 progress 60% (4MB)
141 10:51:15.499025 progress 65% (5MB)
142 10:51:15.525275 progress 70% (5MB)
143 10:51:15.552780 progress 75% (6MB)
144 10:51:15.583078 progress 80% (6MB)
145 10:51:15.606125 progress 85% (6MB)
146 10:51:15.632899 progress 90% (7MB)
147 10:51:15.658292 progress 95% (7MB)
148 10:51:15.683292 progress 100% (8MB)
149 10:51:15.688963 8MB downloaded in 0.81s (10.04MB/s)
150 10:51:15.689257 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:51:15.689670 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:51:15.689798 start: 1.6 prepare-tftp-overlay (timeout 00:09:47) [common]
154 10:51:15.689919 start: 1.6.1 extract-nfsrootfs (timeout 00:09:47) [common]
155 10:51:19.078117 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c
156 10:51:19.078349 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:51:19.078489 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
158 10:51:19.078702 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv
159 10:51:19.078877 makedir: /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin
160 10:51:19.079049 makedir: /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/tests
161 10:51:19.079195 makedir: /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/results
162 10:51:19.079569 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-add-keys
163 10:51:19.079785 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-add-sources
164 10:51:19.079950 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-background-process-start
165 10:51:19.080079 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-background-process-stop
166 10:51:19.080203 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-common-functions
167 10:51:19.080325 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-echo-ipv4
168 10:51:19.080446 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-install-packages
169 10:51:19.080564 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-installed-packages
170 10:51:19.080682 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-os-build
171 10:51:19.080802 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-probe-channel
172 10:51:19.080920 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-probe-ip
173 10:51:19.081038 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-target-ip
174 10:51:19.081155 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-target-mac
175 10:51:19.081272 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-target-storage
176 10:51:19.081392 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-case
177 10:51:19.081510 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-event
178 10:51:19.081626 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-feedback
179 10:51:19.081747 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-raise
180 10:51:19.081865 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-reference
181 10:51:19.081983 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-runner
182 10:51:19.082101 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-set
183 10:51:19.082219 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-test-shell
184 10:51:19.082340 Updating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-add-keys (debian)
185 10:51:19.082480 Updating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-add-sources (debian)
186 10:51:19.082650 Updating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-install-packages (debian)
187 10:51:19.082789 Updating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-installed-packages (debian)
188 10:51:19.082926 Updating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/bin/lava-os-build (debian)
189 10:51:19.083047 Creating /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/environment
190 10:51:19.083144 LAVA metadata
191 10:51:19.083213 - LAVA_JOB_ID=10590982
192 10:51:19.083276 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:51:19.083441 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:43) [common]
194 10:51:19.083520 skipped lava-vland-overlay
195 10:51:19.083595 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:51:19.083675 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:43) [common]
197 10:51:19.083734 skipped lava-multinode-overlay
198 10:51:19.083806 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:51:19.083883 start: 1.6.2.3 test-definition (timeout 00:09:43) [common]
200 10:51:19.083956 Loading test definitions
201 10:51:19.084046 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:43) [common]
202 10:51:19.084115 Using /lava-10590982 at stage 0
203 10:51:19.084395 uuid=10590982_1.6.2.3.1 testdef=None
204 10:51:19.084499 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:51:19.084599 start: 1.6.2.3.2 test-overlay (timeout 00:09:43) [common]
206 10:51:19.085065 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:51:19.085285 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:43) [common]
209 10:51:19.085860 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:51:19.086094 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:43) [common]
212 10:51:19.086613 runner path: /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/0/tests/0_timesync-off test_uuid 10590982_1.6.2.3.1
213 10:51:19.086762 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:51:19.086984 start: 1.6.2.3.5 git-repo-action (timeout 00:09:43) [common]
216 10:51:19.087056 Using /lava-10590982 at stage 0
217 10:51:19.087150 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:51:19.087226 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/0/tests/1_kselftest-rtc'
219 10:51:23.450620 Running '/usr/bin/git checkout kernelci.org
220 10:51:23.596687 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 10:51:23.597654 uuid=10590982_1.6.2.3.5 testdef=None
222 10:51:23.597862 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 10:51:23.598274 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 10:51:23.599520 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:51:23.599827 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 10:51:23.601068 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:51:23.601333 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 10:51:23.602909 runner path: /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/0/tests/1_kselftest-rtc test_uuid 10590982_1.6.2.3.5
232 10:51:23.603035 BOARD='mt8192-asurada-spherion-r0'
233 10:51:23.603136 BRANCH='cip-gitlab'
234 10:51:23.603237 SKIPFILE='/dev/null'
235 10:51:23.603362 SKIP_INSTALL='True'
236 10:51:23.603505 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:51:23.603604 TST_CASENAME=''
238 10:51:23.603700 TST_CMDFILES='rtc'
239 10:51:23.603901 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:51:23.604261 Creating lava-test-runner.conf files
242 10:51:23.604350 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10590982/lava-overlay-es1pq5pv/lava-10590982/0 for stage 0
243 10:51:23.604469 - 0_timesync-off
244 10:51:23.604576 - 1_kselftest-rtc
245 10:51:23.604701 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 10:51:23.604835 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 10:51:31.105080 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:51:31.105229 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 10:51:31.105327 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:51:31.105428 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 10:51:31.105519 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 10:51:31.221289 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:51:31.221665 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 10:51:31.221797 extracting modules file /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c
255 10:51:31.449668 extracting modules file /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590982/extract-overlay-ramdisk-w676rrmf/ramdisk
256 10:51:31.657701 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:51:31.657868 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 10:51:31.657972 [common] Applying overlay to NFS
259 10:51:31.658043 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590982/compress-overlay-5ezrmjkw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c
260 10:51:32.554091 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:51:32.554253 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 10:51:32.554352 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:51:32.554442 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 10:51:32.554527 Building ramdisk /var/lib/lava/dispatcher/tmp/10590982/extract-overlay-ramdisk-w676rrmf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10590982/extract-overlay-ramdisk-w676rrmf/ramdisk
265 10:51:32.860584 >> 117801 blocks
266 10:51:34.857300 rename /var/lib/lava/dispatcher/tmp/10590982/extract-overlay-ramdisk-w676rrmf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/ramdisk/ramdisk.cpio.gz
267 10:51:34.857723 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:51:34.857849 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 10:51:34.857943 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 10:51:34.858049 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/kernel/Image'
271 10:51:46.399106 Returned 0 in 11 seconds
272 10:51:46.499965 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/kernel/image.itb
273 10:51:46.817300 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:51:46.817658 output: Created: Mon Jun 5 11:51:46 2023
275 10:51:46.817732 output: Image 0 (kernel-1)
276 10:51:46.817798 output: Description:
277 10:51:46.817865 output: Created: Mon Jun 5 11:51:46 2023
278 10:51:46.817955 output: Type: Kernel Image
279 10:51:46.818018 output: Compression: lzma compressed
280 10:51:46.818080 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
281 10:51:46.818141 output: Architecture: AArch64
282 10:51:46.818198 output: OS: Linux
283 10:51:46.818254 output: Load Address: 0x00000000
284 10:51:46.818312 output: Entry Point: 0x00000000
285 10:51:46.818367 output: Hash algo: crc32
286 10:51:46.818420 output: Hash value: 8ce42972
287 10:51:46.818472 output: Image 1 (fdt-1)
288 10:51:46.818525 output: Description: mt8192-asurada-spherion-r0
289 10:51:46.818578 output: Created: Mon Jun 5 11:51:46 2023
290 10:51:46.818631 output: Type: Flat Device Tree
291 10:51:46.818683 output: Compression: uncompressed
292 10:51:46.818736 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:51:46.818790 output: Architecture: AArch64
294 10:51:46.818843 output: Hash algo: crc32
295 10:51:46.818896 output: Hash value: 1df858fa
296 10:51:46.818948 output: Image 2 (ramdisk-1)
297 10:51:46.819001 output: Description: unavailable
298 10:51:46.819053 output: Created: Mon Jun 5 11:51:46 2023
299 10:51:46.819106 output: Type: RAMDisk Image
300 10:51:46.819158 output: Compression: Unknown Compression
301 10:51:46.819211 output: Data Size: 17640412 Bytes = 17226.96 KiB = 16.82 MiB
302 10:51:46.819264 output: Architecture: AArch64
303 10:51:46.819316 output: OS: Linux
304 10:51:46.819414 output: Load Address: unavailable
305 10:51:46.819466 output: Entry Point: unavailable
306 10:51:46.819519 output: Hash algo: crc32
307 10:51:46.819571 output: Hash value: a5891362
308 10:51:46.819624 output: Default Configuration: 'conf-1'
309 10:51:46.819676 output: Configuration 0 (conf-1)
310 10:51:46.819728 output: Description: mt8192-asurada-spherion-r0
311 10:51:46.819781 output: Kernel: kernel-1
312 10:51:46.819838 output: Init Ramdisk: ramdisk-1
313 10:51:46.819905 output: FDT: fdt-1
314 10:51:46.819968 output: Loadables: kernel-1
315 10:51:46.820022 output:
316 10:51:46.820228 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:51:46.820371 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:51:46.820481 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 10:51:46.820581 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 10:51:46.820658 No LXC device requested
321 10:51:46.820737 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:51:46.820821 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 10:51:46.820898 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:51:46.820965 Checking files for TFTP limit of 4294967296 bytes.
325 10:51:46.821455 end: 1 tftp-deploy (duration 00:00:44) [common]
326 10:51:46.821561 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:51:46.821653 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:51:46.821777 substitutions:
329 10:51:46.821850 - {DTB}: 10590982/tftp-deploy-jn_vmrpw/dtb/mt8192-asurada-spherion-r0.dtb
330 10:51:46.821952 - {INITRD}: 10590982/tftp-deploy-jn_vmrpw/ramdisk/ramdisk.cpio.gz
331 10:51:46.822041 - {KERNEL}: 10590982/tftp-deploy-jn_vmrpw/kernel/Image
332 10:51:46.822103 - {LAVA_MAC}: None
333 10:51:46.822162 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c
334 10:51:46.822220 - {NFS_SERVER_IP}: 192.168.201.1
335 10:51:46.822279 - {PRESEED_CONFIG}: None
336 10:51:46.822334 - {PRESEED_LOCAL}: None
337 10:51:46.822390 - {RAMDISK}: 10590982/tftp-deploy-jn_vmrpw/ramdisk/ramdisk.cpio.gz
338 10:51:46.822446 - {ROOT_PART}: None
339 10:51:46.822502 - {ROOT}: None
340 10:51:46.822557 - {SERVER_IP}: 192.168.201.1
341 10:51:46.822611 - {TEE}: None
342 10:51:46.822666 Parsed boot commands:
343 10:51:46.822721 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:51:46.822895 Parsed boot commands: tftpboot 192.168.201.1 10590982/tftp-deploy-jn_vmrpw/kernel/image.itb 10590982/tftp-deploy-jn_vmrpw/kernel/cmdline
345 10:51:46.822985 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:51:46.823070 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:51:46.823158 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:51:46.823244 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:51:46.823316 Not connected, no need to disconnect.
350 10:51:46.823432 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:51:46.823512 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:51:46.823582 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 10:51:46.826962 Setting prompt string to ['lava-test: # ']
354 10:51:46.827300 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:51:46.827449 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:51:46.827548 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:51:46.827640 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:51:46.827834 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 10:51:51.971223 >> Command sent successfully.
360 10:51:51.981620 Returned 0 in 5 seconds
361 10:51:52.082834 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:51:52.084402 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:51:52.084991 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:51:52.085555 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:51:52.086049 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:51:52.086506 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:51:52.087906 [Enter `^Ec?' for help]
369 10:51:52.247845
370 10:51:52.248550
371 10:51:52.249032 F0: 102B 0000
372 10:51:52.249458
373 10:51:52.249869 F3: 1001 0000 [0200]
374 10:51:52.250292
375 10:51:52.251637 F3: 1001 0000
376 10:51:52.252069
377 10:51:52.252410 F7: 102D 0000
378 10:51:52.252730
379 10:51:52.253081 F1: 0000 0000
380 10:51:52.253559
381 10:51:52.255540 V0: 0000 0000 [0001]
382 10:51:52.255982
383 10:51:52.256330 00: 0007 8000
384 10:51:52.256851
385 10:51:52.259273 01: 0000 0000
386 10:51:52.259787
387 10:51:52.260131 BP: 0C00 0209 [0000]
388 10:51:52.260450
389 10:51:52.260799 G0: 1182 0000
390 10:51:52.261137
391 10:51:52.263262 EC: 0000 0021 [4000]
392 10:51:52.263746
393 10:51:52.264189 S7: 0000 0000 [0000]
394 10:51:52.267191
395 10:51:52.267673 CC: 0000 0000 [0001]
396 10:51:52.268119
397 10:51:52.268537 T0: 0000 0040 [010F]
398 10:51:52.270133
399 10:51:52.270640 Jump to BL
400 10:51:52.271064
401 10:51:52.294934
402 10:51:52.295421
403 10:51:52.295878
404 10:51:52.302002 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:51:52.305832 ARM64: Exception handlers installed.
406 10:51:52.309047 ARM64: Testing exception
407 10:51:52.313268 ARM64: Done test exception
408 10:51:52.320814 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:51:52.327418 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:51:52.334389 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:51:52.345449 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:51:52.352025 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:51:52.362225 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:51:52.372962 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:51:52.379811 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:51:52.397172 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:51:52.400846 WDT: Last reset was cold boot
418 10:51:52.403957 SPI1(PAD0) initialized at 2873684 Hz
419 10:51:52.407905 SPI5(PAD0) initialized at 992727 Hz
420 10:51:52.411015 VBOOT: Loading verstage.
421 10:51:52.417866 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:51:52.421752 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:51:52.425471 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:51:52.428392 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:51:52.434769 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:51:52.442215 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:51:52.452331 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 10:51:52.452760
429 10:51:52.453096
430 10:51:52.463144 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:51:52.466666 ARM64: Exception handlers installed.
432 10:51:52.467094 ARM64: Testing exception
433 10:51:52.470174 ARM64: Done test exception
434 10:51:52.473060 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:51:52.480135 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:51:52.493429 Probing TPM: . done!
437 10:51:52.493859 TPM ready after 0 ms
438 10:51:52.500591 Connected to device vid:did:rid of 1ae0:0028:00
439 10:51:52.507426 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 10:51:52.567144 Initialized TPM device CR50 revision 0
441 10:51:52.579559 tlcl_send_startup: Startup return code is 0
442 10:51:52.580002 TPM: setup succeeded
443 10:51:52.590814 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:51:52.599553 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:51:52.614639 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:51:52.621728 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:51:52.625567 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:51:52.629327 in-header: 03 07 00 00 08 00 00 00
449 10:51:52.633055 in-data: aa e4 47 04 13 02 00 00
450 10:51:52.633553 Chrome EC: UHEPI supported
451 10:51:52.639706 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:51:52.644064 in-header: 03 95 00 00 08 00 00 00
453 10:51:52.647727 in-data: 18 20 20 08 00 00 00 00
454 10:51:52.648236 Phase 1
455 10:51:52.651900 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:51:52.658802 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:51:52.666773 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:51:52.667266 Recovery requested (1009000e)
459 10:51:52.679054 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:51:52.682280 tlcl_extend: response is 0
461 10:51:52.691547 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:51:52.697105 tlcl_extend: response is 0
463 10:51:52.704101 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:51:52.723604 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:51:52.730410 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:51:52.731047
467 10:51:52.731515
468 10:51:52.740618 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:51:52.743746 ARM64: Exception handlers installed.
470 10:51:52.746944 ARM64: Testing exception
471 10:51:52.747434 ARM64: Done test exception
472 10:51:52.769305 pmic_efuse_setting: Set efuses in 11 msecs
473 10:51:52.772690 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:51:52.779236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:51:52.783106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:51:52.789968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:51:52.793423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:51:52.797950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:51:52.800788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:51:52.808474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:51:52.812220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:51:52.816571 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:51:52.823478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:51:52.827262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:51:52.831011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:51:52.834717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:51:52.841913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:51:52.849618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:51:52.852962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:51:52.860835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:51:52.864345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:51:52.871442 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:51:52.875231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:51:52.882528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:51:52.886233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:51:52.894228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:51:52.897216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:51:52.901471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:51:52.908359 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:51:52.912202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:51:52.919835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:51:52.923441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:51:52.927138 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:51:52.934847 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:51:52.938728 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:51:52.942324 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:51:52.949382 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:51:52.953287 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:51:52.957051 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:51:52.964707 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:51:52.968366 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:51:52.971979 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:51:52.975417 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:51:52.982342 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:51:52.986790 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:51:52.990346 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:51:52.994081 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:51:52.998171 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:51:53.005490 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:51:53.009140 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:51:53.012802 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:51:53.017023 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:51:53.020338 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:51:53.024071 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:51:53.031801 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:51:53.039250 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:51:53.046852 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:51:53.054463 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:51:53.061492 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:51:53.065460 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:51:53.072752 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:51:53.075928 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:51:53.083661 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 10:51:53.086640 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:51:53.091203 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 10:51:53.098034 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:51:53.107281 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 10:51:53.116338 [RTC]rtc_get_frequency_meter,154: input=23, output=943
539 10:51:53.125685 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 10:51:53.135715 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 10:51:53.145327 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 10:51:53.154759 [RTC]rtc_get_frequency_meter,154: input=16, output=783
543 10:51:53.164305 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 10:51:53.168261 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 10:51:53.172158 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 10:51:53.175116 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:51:53.183274 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 10:51:53.186411 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:51:53.190883 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:51:53.194402 ADC[4]: Raw value=906573 ID=7
551 10:51:53.194977 ADC[3]: Raw value=213441 ID=1
552 10:51:53.198221 RAM Code: 0x71
553 10:51:53.201787 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:51:53.205565 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:51:53.216844 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:51:53.220799 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:51:53.224330 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:51:53.227999 in-header: 03 07 00 00 08 00 00 00
559 10:51:53.231580 in-data: aa e4 47 04 13 02 00 00
560 10:51:53.235398 Chrome EC: UHEPI supported
561 10:51:53.243412 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:51:53.243863 in-header: 03 95 00 00 08 00 00 00
563 10:51:53.246960 in-data: 18 20 20 08 00 00 00 00
564 10:51:53.250872 MRC: failed to locate region type 0.
565 10:51:53.258337 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:51:53.262128 DRAM-K: Running full calibration
567 10:51:53.265921 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:51:53.269278 header.status = 0x0
569 10:51:53.272839 header.version = 0x6 (expected: 0x6)
570 10:51:53.276820 header.size = 0xd00 (expected: 0xd00)
571 10:51:53.277328 header.flags = 0x0
572 10:51:53.284168 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:51:53.301756 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
574 10:51:53.308541 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:51:53.312464 dram_init: ddr_geometry: 2
576 10:51:53.312942 [EMI] MDL number = 2
577 10:51:53.316184 [EMI] Get MDL freq = 0
578 10:51:53.316620 dram_init: ddr_type: 0
579 10:51:53.319944 is_discrete_lpddr4: 1
580 10:51:53.323152 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:51:53.323644
582 10:51:53.324031
583 10:51:53.326893 [Bian_co] ETT version 0.0.0.1
584 10:51:53.330506 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:51:53.330991
586 10:51:53.334163 dramc_set_vcore_voltage set vcore to 650000
587 10:51:53.337845 Read voltage for 800, 4
588 10:51:53.338282 Vio18 = 0
589 10:51:53.338706 Vcore = 650000
590 10:51:53.339068 Vdram = 0
591 10:51:53.341451 Vddq = 0
592 10:51:53.341928 Vmddr = 0
593 10:51:53.345721 dram_init: config_dvfs: 1
594 10:51:53.349027 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:51:53.352831 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:51:53.356368 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 10:51:53.360053 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 10:51:53.363790 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 10:51:53.370075 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 10:51:53.370512 MEM_TYPE=3, freq_sel=18
601 10:51:53.373776 sv_algorithm_assistance_LP4_1600
602 10:51:53.377065 ============ PULL DRAM RESETB DOWN ============
603 10:51:53.383976 ========== PULL DRAM RESETB DOWN end =========
604 10:51:53.387856 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:51:53.391536 ===================================
606 10:51:53.391974 LPDDR4 DRAM CONFIGURATION
607 10:51:53.395433 ===================================
608 10:51:53.399215 EX_ROW_EN[0] = 0x0
609 10:51:53.399692 EX_ROW_EN[1] = 0x0
610 10:51:53.403211 LP4Y_EN = 0x0
611 10:51:53.403801 WORK_FSP = 0x0
612 10:51:53.406449 WL = 0x2
613 10:51:53.406928 RL = 0x2
614 10:51:53.410155 BL = 0x2
615 10:51:53.410594 RPST = 0x0
616 10:51:53.413285 RD_PRE = 0x0
617 10:51:53.413722 WR_PRE = 0x1
618 10:51:53.416711 WR_PST = 0x0
619 10:51:53.417141 DBI_WR = 0x0
620 10:51:53.420528 DBI_RD = 0x0
621 10:51:53.420962 OTF = 0x1
622 10:51:53.423643 ===================================
623 10:51:53.427428 ===================================
624 10:51:53.427874 ANA top config
625 10:51:53.430719 ===================================
626 10:51:53.433924 DLL_ASYNC_EN = 0
627 10:51:53.437509 ALL_SLAVE_EN = 1
628 10:51:53.440558 NEW_RANK_MODE = 1
629 10:51:53.441026 DLL_IDLE_MODE = 1
630 10:51:53.444113 LP45_APHY_COMB_EN = 1
631 10:51:53.447179 TX_ODT_DIS = 1
632 10:51:53.450907 NEW_8X_MODE = 1
633 10:51:53.454847 ===================================
634 10:51:53.457844 ===================================
635 10:51:53.458293 data_rate = 1600
636 10:51:53.460977 CKR = 1
637 10:51:53.464527 DQ_P2S_RATIO = 8
638 10:51:53.468359 ===================================
639 10:51:53.471400 CA_P2S_RATIO = 8
640 10:51:53.474533 DQ_CA_OPEN = 0
641 10:51:53.477711 DQ_SEMI_OPEN = 0
642 10:51:53.478323 CA_SEMI_OPEN = 0
643 10:51:53.481649 CA_FULL_RATE = 0
644 10:51:53.484990 DQ_CKDIV4_EN = 1
645 10:51:53.488158 CA_CKDIV4_EN = 1
646 10:51:53.491394 CA_PREDIV_EN = 0
647 10:51:53.495073 PH8_DLY = 0
648 10:51:53.495618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:51:53.498187 DQ_AAMCK_DIV = 4
650 10:51:53.501311 CA_AAMCK_DIV = 4
651 10:51:53.505014 CA_ADMCK_DIV = 4
652 10:51:53.508118 DQ_TRACK_CA_EN = 0
653 10:51:53.511320 CA_PICK = 800
654 10:51:53.511789 CA_MCKIO = 800
655 10:51:53.515156 MCKIO_SEMI = 0
656 10:51:53.519084 PLL_FREQ = 3068
657 10:51:53.522827 DQ_UI_PI_RATIO = 32
658 10:51:53.526684 CA_UI_PI_RATIO = 0
659 10:51:53.527116 ===================================
660 10:51:53.530301 ===================================
661 10:51:53.534213 memory_type:LPDDR4
662 10:51:53.534741 GP_NUM : 10
663 10:51:53.537884 SRAM_EN : 1
664 10:51:53.538333 MD32_EN : 0
665 10:51:53.541680 ===================================
666 10:51:53.546145 [ANA_INIT] >>>>>>>>>>>>>>
667 10:51:53.549767 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:51:53.550216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:51:53.553186 ===================================
670 10:51:53.556346 data_rate = 1600,PCW = 0X7600
671 10:51:53.559363 ===================================
672 10:51:53.563065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:51:53.569866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:51:53.575998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:51:53.579737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:51:53.582821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:51:53.586651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:51:53.589924 [ANA_INIT] flow start
679 10:51:53.590416 [ANA_INIT] PLL >>>>>>>>
680 10:51:53.593043 [ANA_INIT] PLL <<<<<<<<
681 10:51:53.596290 [ANA_INIT] MIDPI >>>>>>>>
682 10:51:53.596721 [ANA_INIT] MIDPI <<<<<<<<
683 10:51:53.599742 [ANA_INIT] DLL >>>>>>>>
684 10:51:53.603509 [ANA_INIT] flow end
685 10:51:53.606607 ============ LP4 DIFF to SE enter ============
686 10:51:53.609795 ============ LP4 DIFF to SE exit ============
687 10:51:53.613064 [ANA_INIT] <<<<<<<<<<<<<
688 10:51:53.616747 [Flow] Enable top DCM control >>>>>
689 10:51:53.619848 [Flow] Enable top DCM control <<<<<
690 10:51:53.623180 Enable DLL master slave shuffle
691 10:51:53.626337 ==============================================================
692 10:51:53.630038 Gating Mode config
693 10:51:53.636776 ==============================================================
694 10:51:53.637211 Config description:
695 10:51:53.646545 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:51:53.653340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:51:53.656365 SELPH_MODE 0: By rank 1: By Phase
698 10:51:53.663515 ==============================================================
699 10:51:53.666987 GAT_TRACK_EN = 1
700 10:51:53.669920 RX_GATING_MODE = 2
701 10:51:53.673363 RX_GATING_TRACK_MODE = 2
702 10:51:53.676749 SELPH_MODE = 1
703 10:51:53.677338 PICG_EARLY_EN = 1
704 10:51:53.680282 VALID_LAT_VALUE = 1
705 10:51:53.686898 ==============================================================
706 10:51:53.690092 Enter into Gating configuration >>>>
707 10:51:53.693217 Exit from Gating configuration <<<<
708 10:51:53.697146 Enter into DVFS_PRE_config >>>>>
709 10:51:53.707127 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:51:53.710188 Exit from DVFS_PRE_config <<<<<
711 10:51:53.713965 Enter into PICG configuration >>>>
712 10:51:53.717246 Exit from PICG configuration <<<<
713 10:51:53.720316 [RX_INPUT] configuration >>>>>
714 10:51:53.724028 [RX_INPUT] configuration <<<<<
715 10:51:53.727069 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:51:53.733485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:51:53.740382 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:51:53.747266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:51:53.750357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:51:53.757325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:51:53.760541 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:51:53.767550 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:51:53.770353 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:51:53.773893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:51:53.776966 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:51:53.784121 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:51:53.787344 ===================================
728 10:51:53.787789 LPDDR4 DRAM CONFIGURATION
729 10:51:53.790352 ===================================
730 10:51:53.794091 EX_ROW_EN[0] = 0x0
731 10:51:53.797192 EX_ROW_EN[1] = 0x0
732 10:51:53.797711 LP4Y_EN = 0x0
733 10:51:53.800283 WORK_FSP = 0x0
734 10:51:53.800752 WL = 0x2
735 10:51:53.804006 RL = 0x2
736 10:51:53.804436 BL = 0x2
737 10:51:53.807214 RPST = 0x0
738 10:51:53.807676 RD_PRE = 0x0
739 10:51:53.810325 WR_PRE = 0x1
740 10:51:53.810755 WR_PST = 0x0
741 10:51:53.814053 DBI_WR = 0x0
742 10:51:53.814486 DBI_RD = 0x0
743 10:51:53.817287 OTF = 0x1
744 10:51:53.821018 ===================================
745 10:51:53.824191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:51:53.827199 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:51:53.834007 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:51:53.837253 ===================================
749 10:51:53.837741 LPDDR4 DRAM CONFIGURATION
750 10:51:53.840534 ===================================
751 10:51:53.844271 EX_ROW_EN[0] = 0x10
752 10:51:53.844757 EX_ROW_EN[1] = 0x0
753 10:51:53.847320 LP4Y_EN = 0x0
754 10:51:53.847803 WORK_FSP = 0x0
755 10:51:53.850722 WL = 0x2
756 10:51:53.851205 RL = 0x2
757 10:51:53.853909 BL = 0x2
758 10:51:53.854391 RPST = 0x0
759 10:51:53.857873 RD_PRE = 0x0
760 10:51:53.860947 WR_PRE = 0x1
761 10:51:53.861426 WR_PST = 0x0
762 10:51:53.864122 DBI_WR = 0x0
763 10:51:53.864552 DBI_RD = 0x0
764 10:51:53.867292 OTF = 0x1
765 10:51:53.871012 ===================================
766 10:51:53.874068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:51:53.879633 nWR fixed to 40
768 10:51:53.882527 [ModeRegInit_LP4] CH0 RK0
769 10:51:53.882959 [ModeRegInit_LP4] CH0 RK1
770 10:51:53.886209 [ModeRegInit_LP4] CH1 RK0
771 10:51:53.889256 [ModeRegInit_LP4] CH1 RK1
772 10:51:53.889736 match AC timing 13
773 10:51:53.896403 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:51:53.899300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:51:53.902971 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:51:53.909518 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:51:53.913111 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:51:53.913596 [EMI DOE] emi_dcm 0
779 10:51:53.919790 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:51:53.920234 ==
781 10:51:53.923032 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:51:53.926248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:51:53.926739 ==
784 10:51:53.932992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:51:53.936107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:51:53.947080 [CA 0] Center 36 (6~67) winsize 62
787 10:51:53.950126 [CA 1] Center 36 (6~67) winsize 62
788 10:51:53.953238 [CA 2] Center 34 (4~65) winsize 62
789 10:51:53.957165 [CA 3] Center 33 (3~64) winsize 62
790 10:51:53.960295 [CA 4] Center 33 (2~64) winsize 63
791 10:51:53.963397 [CA 5] Center 32 (2~62) winsize 61
792 10:51:53.963831
793 10:51:53.966588 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 10:51:53.967018
795 10:51:53.970529 [CATrainingPosCal] consider 1 rank data
796 10:51:53.973585 u2DelayCellTimex100 = 270/100 ps
797 10:51:53.976754 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 10:51:53.980321 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 10:51:53.987244 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 10:51:53.989976 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 10:51:53.993770 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
802 10:51:53.996930 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 10:51:53.997364
804 10:51:54.000008 CA PerBit enable=1, Macro0, CA PI delay=32
805 10:51:54.000442
806 10:51:54.003795 [CBTSetCACLKResult] CA Dly = 32
807 10:51:54.004228 CS Dly: 5 (0~36)
808 10:51:54.004572 ==
809 10:51:54.006729 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:51:54.013596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:51:54.014053 ==
812 10:51:54.017196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:51:54.023848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:51:54.033342 [CA 0] Center 36 (6~67) winsize 62
815 10:51:54.036441 [CA 1] Center 36 (6~67) winsize 62
816 10:51:54.039452 [CA 2] Center 34 (4~65) winsize 62
817 10:51:54.043137 [CA 3] Center 33 (3~64) winsize 62
818 10:51:54.046306 [CA 4] Center 32 (2~63) winsize 62
819 10:51:54.049537 [CA 5] Center 32 (2~63) winsize 62
820 10:51:54.050010
821 10:51:54.053175 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:51:54.053656
823 10:51:54.056111 [CATrainingPosCal] consider 2 rank data
824 10:51:54.059486 u2DelayCellTimex100 = 270/100 ps
825 10:51:54.063209 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 10:51:54.066560 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 10:51:54.072990 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 10:51:54.076271 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 10:51:54.079932 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
830 10:51:54.083011 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 10:51:54.083602
832 10:51:54.086698 CA PerBit enable=1, Macro0, CA PI delay=32
833 10:51:54.087149
834 10:51:54.090071 [CBTSetCACLKResult] CA Dly = 32
835 10:51:54.090552 CS Dly: 5 (0~37)
836 10:51:54.090903
837 10:51:54.093294 ----->DramcWriteLeveling(PI) begin...
838 10:51:54.093738 ==
839 10:51:54.096904 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:51:54.100640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:51:54.104159 ==
842 10:51:54.104597 Write leveling (Byte 0): 32 => 32
843 10:51:54.107853 Write leveling (Byte 1): 30 => 30
844 10:51:54.111247 DramcWriteLeveling(PI) end<-----
845 10:51:54.111760
846 10:51:54.112129 ==
847 10:51:54.114860 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:51:54.118369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:51:54.118879 ==
850 10:51:54.121494 [Gating] SW mode calibration
851 10:51:54.128088 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:51:54.135073 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:51:54.138315 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:51:54.141320 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 10:51:54.148079 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 10:51:54.151948 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:51:54.155141 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:51:54.162062 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:51:54.165134 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:51:54.168268 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:51:54.175387 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:51:54.178737 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:51:54.181818 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:51:54.188655 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:51:54.191783 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:51:54.195643 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:51:54.201987 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:51:54.205444 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:51:54.208434 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:51:54.215001 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 10:51:54.218764 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
872 10:51:54.222122 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 10:51:54.225165 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:51:54.231690 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:51:54.235315 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:51:54.238809 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:51:54.245533 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:51:54.248565 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
879 10:51:54.251507 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (1 1) (1 1)
880 10:51:54.258584 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
881 10:51:54.261679 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:51:54.265454 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:51:54.271814 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:51:54.275718 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:51:54.278372 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:51:54.285113 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
887 10:51:54.288858 0 10 8 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 0)
888 10:51:54.292119 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 10:51:54.298854 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:51:54.302202 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:51:54.305401 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:51:54.308588 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:51:54.315268 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:51:54.318949 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 10:51:54.321979 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
896 10:51:54.328756 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 10:51:54.332394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:51:54.335410 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:51:54.342245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:51:54.345873 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:51:54.349324 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:51:54.355875 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 10:51:54.358836 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 10:51:54.362726 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 10:51:54.365846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:51:54.372684 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:51:54.375940 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:51:54.379222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:51:54.385579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:51:54.389379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:51:54.392606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:51:54.399430 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:51:54.402230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:51:54.406291 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:51:54.412548 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:51:54.415837 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:51:54.419063 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:51:54.426116 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 10:51:54.429108 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
920 10:51:54.432634 Total UI for P1: 0, mck2ui 16
921 10:51:54.436302 best dqsien dly found for B0: ( 0, 14, 4)
922 10:51:54.439621 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 10:51:54.442693 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 10:51:54.445950 Total UI for P1: 0, mck2ui 16
925 10:51:54.450302 best dqsien dly found for B1: ( 0, 14, 12)
926 10:51:54.453283 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
927 10:51:54.456854 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 10:51:54.457284
929 10:51:54.460401 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
930 10:51:54.466592 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 10:51:54.467056 [Gating] SW calibration Done
932 10:51:54.467469 ==
933 10:51:54.470243 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:51:54.477024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:51:54.477526 ==
936 10:51:54.477904 RX Vref Scan: 0
937 10:51:54.478268
938 10:51:54.480294 RX Vref 0 -> 0, step: 1
939 10:51:54.480794
940 10:51:54.483580 RX Delay -130 -> 252, step: 16
941 10:51:54.486724 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
942 10:51:54.490495 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
943 10:51:54.493669 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
944 10:51:54.500008 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
945 10:51:54.503957 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
946 10:51:54.507109 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
947 10:51:54.510207 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
948 10:51:54.513353 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
949 10:51:54.517308 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
950 10:51:54.523453 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
951 10:51:54.527123 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
952 10:51:54.530211 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
953 10:51:54.533756 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
954 10:51:54.540533 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
955 10:51:54.543503 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
956 10:51:54.546812 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
957 10:51:54.547594 ==
958 10:51:54.550695 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:51:54.553497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:51:54.553936 ==
961 10:51:54.556649 DQS Delay:
962 10:51:54.557104 DQS0 = 0, DQS1 = 0
963 10:51:54.559906 DQM Delay:
964 10:51:54.560356 DQM0 = 88, DQM1 = 82
965 10:51:54.560734 DQ Delay:
966 10:51:54.563599 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
967 10:51:54.566775 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
968 10:51:54.569757 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
969 10:51:54.573321 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
970 10:51:54.573755
971 10:51:54.574118
972 10:51:54.574433 ==
973 10:51:54.576614 Dram Type= 6, Freq= 0, CH_0, rank 0
974 10:51:54.583297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 10:51:54.583783 ==
976 10:51:54.584127
977 10:51:54.584486
978 10:51:54.584797 TX Vref Scan disable
979 10:51:54.587228 == TX Byte 0 ==
980 10:51:54.590394 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 10:51:54.593521 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 10:51:54.597477 == TX Byte 1 ==
983 10:51:54.600569 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 10:51:54.603712 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 10:51:54.607387 ==
986 10:51:54.610658 Dram Type= 6, Freq= 0, CH_0, rank 0
987 10:51:54.613854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 10:51:54.614376 ==
989 10:51:54.626505 TX Vref=22, minBit 5, minWin=27, winSum=445
990 10:51:54.629762 TX Vref=24, minBit 8, minWin=27, winSum=449
991 10:51:54.632997 TX Vref=26, minBit 10, minWin=27, winSum=454
992 10:51:54.636624 TX Vref=28, minBit 9, minWin=27, winSum=455
993 10:51:54.639769 TX Vref=30, minBit 0, minWin=28, winSum=456
994 10:51:54.643283 TX Vref=32, minBit 10, minWin=27, winSum=453
995 10:51:54.650169 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
996 10:51:54.650598
997 10:51:54.653052 Final TX Range 1 Vref 30
998 10:51:54.653497
999 10:51:54.654015 ==
1000 10:51:54.656743 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 10:51:54.659875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 10:51:54.660304 ==
1003 10:51:54.660640
1004 10:51:54.662822
1005 10:51:54.663244 TX Vref Scan disable
1006 10:51:54.666471 == TX Byte 0 ==
1007 10:51:54.670191 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 10:51:54.673376 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 10:51:54.676614 == TX Byte 1 ==
1010 10:51:54.679594 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 10:51:54.683195 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 10:51:54.683689
1013 10:51:54.686650 [DATLAT]
1014 10:51:54.687115 Freq=800, CH0 RK0
1015 10:51:54.687509
1016 10:51:54.690132 DATLAT Default: 0xa
1017 10:51:54.690558 0, 0xFFFF, sum = 0
1018 10:51:54.693329 1, 0xFFFF, sum = 0
1019 10:51:54.693762 2, 0xFFFF, sum = 0
1020 10:51:54.696664 3, 0xFFFF, sum = 0
1021 10:51:54.697101 4, 0xFFFF, sum = 0
1022 10:51:54.699904 5, 0xFFFF, sum = 0
1023 10:51:54.700337 6, 0xFFFF, sum = 0
1024 10:51:54.703132 7, 0xFFFF, sum = 0
1025 10:51:54.703620 8, 0xFFFF, sum = 0
1026 10:51:54.706337 9, 0x0, sum = 1
1027 10:51:54.706760 10, 0x0, sum = 2
1028 10:51:54.710231 11, 0x0, sum = 3
1029 10:51:54.710657 12, 0x0, sum = 4
1030 10:51:54.713125 best_step = 10
1031 10:51:54.713542
1032 10:51:54.713871 ==
1033 10:51:54.716904 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 10:51:54.720102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 10:51:54.720528 ==
1036 10:51:54.723261 RX Vref Scan: 1
1037 10:51:54.723710
1038 10:51:54.724042 Set Vref Range= 32 -> 127
1039 10:51:54.724482
1040 10:51:54.727035 RX Vref 32 -> 127, step: 1
1041 10:51:54.727495
1042 10:51:54.730239 RX Delay -79 -> 252, step: 8
1043 10:51:54.730657
1044 10:51:54.733438 Set Vref, RX VrefLevel [Byte0]: 32
1045 10:51:54.736522 [Byte1]: 32
1046 10:51:54.736942
1047 10:51:54.739843 Set Vref, RX VrefLevel [Byte0]: 33
1048 10:51:54.743179 [Byte1]: 33
1049 10:51:54.746812
1050 10:51:54.747233 Set Vref, RX VrefLevel [Byte0]: 34
1051 10:51:54.749752 [Byte1]: 34
1052 10:51:54.753910
1053 10:51:54.754330 Set Vref, RX VrefLevel [Byte0]: 35
1054 10:51:54.757925 [Byte1]: 35
1055 10:51:54.762275
1056 10:51:54.762721 Set Vref, RX VrefLevel [Byte0]: 36
1057 10:51:54.765306 [Byte1]: 36
1058 10:51:54.769706
1059 10:51:54.770175 Set Vref, RX VrefLevel [Byte0]: 37
1060 10:51:54.773568 [Byte1]: 37
1061 10:51:54.777214
1062 10:51:54.777642 Set Vref, RX VrefLevel [Byte0]: 38
1063 10:51:54.780286 [Byte1]: 38
1064 10:51:54.784864
1065 10:51:54.785292 Set Vref, RX VrefLevel [Byte0]: 39
1066 10:51:54.787779 [Byte1]: 39
1067 10:51:54.792231
1068 10:51:54.792662 Set Vref, RX VrefLevel [Byte0]: 40
1069 10:51:54.795649 [Byte1]: 40
1070 10:51:54.799730
1071 10:51:54.800353 Set Vref, RX VrefLevel [Byte0]: 41
1072 10:51:54.802734 [Byte1]: 41
1073 10:51:54.807110
1074 10:51:54.807564 Set Vref, RX VrefLevel [Byte0]: 42
1075 10:51:54.810263 [Byte1]: 42
1076 10:51:54.814706
1077 10:51:54.815128 Set Vref, RX VrefLevel [Byte0]: 43
1078 10:51:54.817791 [Byte1]: 43
1079 10:51:54.822063
1080 10:51:54.822484 Set Vref, RX VrefLevel [Byte0]: 44
1081 10:51:54.825223 [Byte1]: 44
1082 10:51:54.829703
1083 10:51:54.830125 Set Vref, RX VrefLevel [Byte0]: 45
1084 10:51:54.832899 [Byte1]: 45
1085 10:51:54.837599
1086 10:51:54.838132 Set Vref, RX VrefLevel [Byte0]: 46
1087 10:51:54.840683 [Byte1]: 46
1088 10:51:54.845071
1089 10:51:54.845497 Set Vref, RX VrefLevel [Byte0]: 47
1090 10:51:54.848340 [Byte1]: 47
1091 10:51:54.852186
1092 10:51:54.852610 Set Vref, RX VrefLevel [Byte0]: 48
1093 10:51:54.855868 [Byte1]: 48
1094 10:51:54.860080
1095 10:51:54.860600 Set Vref, RX VrefLevel [Byte0]: 49
1096 10:51:54.863179 [Byte1]: 49
1097 10:51:54.867767
1098 10:51:54.868189 Set Vref, RX VrefLevel [Byte0]: 50
1099 10:51:54.870860 [Byte1]: 50
1100 10:51:54.875000
1101 10:51:54.875499 Set Vref, RX VrefLevel [Byte0]: 51
1102 10:51:54.877922 [Byte1]: 51
1103 10:51:54.883098
1104 10:51:54.883573 Set Vref, RX VrefLevel [Byte0]: 52
1105 10:51:54.886198 [Byte1]: 52
1106 10:51:54.890440
1107 10:51:54.890882 Set Vref, RX VrefLevel [Byte0]: 53
1108 10:51:54.893465 [Byte1]: 53
1109 10:51:54.897721
1110 10:51:54.898144 Set Vref, RX VrefLevel [Byte0]: 54
1111 10:51:54.900932 [Byte1]: 54
1112 10:51:54.905437
1113 10:51:54.905859 Set Vref, RX VrefLevel [Byte0]: 55
1114 10:51:54.908440 [Byte1]: 55
1115 10:51:54.912689
1116 10:51:54.913109 Set Vref, RX VrefLevel [Byte0]: 56
1117 10:51:54.916295 [Byte1]: 56
1118 10:51:54.920194
1119 10:51:54.920616 Set Vref, RX VrefLevel [Byte0]: 57
1120 10:51:54.923850 [Byte1]: 57
1121 10:51:54.927718
1122 10:51:54.928239 Set Vref, RX VrefLevel [Byte0]: 58
1123 10:51:54.931427 [Byte1]: 58
1124 10:51:54.935259
1125 10:51:54.935720 Set Vref, RX VrefLevel [Byte0]: 59
1126 10:51:54.939085 [Byte1]: 59
1127 10:51:54.942788
1128 10:51:54.943208 Set Vref, RX VrefLevel [Byte0]: 60
1129 10:51:54.946584 [Byte1]: 60
1130 10:51:54.950398
1131 10:51:54.950892 Set Vref, RX VrefLevel [Byte0]: 61
1132 10:51:54.953796 [Byte1]: 61
1133 10:51:54.958367
1134 10:51:54.958894 Set Vref, RX VrefLevel [Byte0]: 62
1135 10:51:54.961550 [Byte1]: 62
1136 10:51:54.965409
1137 10:51:54.965907 Set Vref, RX VrefLevel [Byte0]: 63
1138 10:51:54.969180 [Byte1]: 63
1139 10:51:54.973341
1140 10:51:54.973806 Set Vref, RX VrefLevel [Byte0]: 64
1141 10:51:54.976436 [Byte1]: 64
1142 10:51:54.980540
1143 10:51:54.980958 Set Vref, RX VrefLevel [Byte0]: 65
1144 10:51:54.984169 [Byte1]: 65
1145 10:51:54.988421
1146 10:51:54.988847 Set Vref, RX VrefLevel [Byte0]: 66
1147 10:51:54.991762 [Byte1]: 66
1148 10:51:54.995950
1149 10:51:54.996388 Set Vref, RX VrefLevel [Byte0]: 67
1150 10:51:54.999124 [Byte1]: 67
1151 10:51:55.003619
1152 10:51:55.004036 Set Vref, RX VrefLevel [Byte0]: 68
1153 10:51:55.006661 [Byte1]: 68
1154 10:51:55.010813
1155 10:51:55.011231 Set Vref, RX VrefLevel [Byte0]: 69
1156 10:51:55.014054 [Byte1]: 69
1157 10:51:55.018384
1158 10:51:55.018824 Set Vref, RX VrefLevel [Byte0]: 70
1159 10:51:55.022042 [Byte1]: 70
1160 10:51:55.026415
1161 10:51:55.026993 Set Vref, RX VrefLevel [Byte0]: 71
1162 10:51:55.029231 [Byte1]: 71
1163 10:51:55.033702
1164 10:51:55.034123 Set Vref, RX VrefLevel [Byte0]: 72
1165 10:51:55.036846 [Byte1]: 72
1166 10:51:55.041285
1167 10:51:55.041704 Set Vref, RX VrefLevel [Byte0]: 73
1168 10:51:55.044318 [Byte1]: 73
1169 10:51:55.048830
1170 10:51:55.049386 Set Vref, RX VrefLevel [Byte0]: 74
1171 10:51:55.051826 [Byte1]: 74
1172 10:51:55.056232
1173 10:51:55.056655 Set Vref, RX VrefLevel [Byte0]: 75
1174 10:51:55.059691 [Byte1]: 75
1175 10:51:55.064032
1176 10:51:55.064564 Set Vref, RX VrefLevel [Byte0]: 76
1177 10:51:55.067223 [Byte1]: 76
1178 10:51:55.071556
1179 10:51:55.072097 Set Vref, RX VrefLevel [Byte0]: 77
1180 10:51:55.074804 [Byte1]: 77
1181 10:51:55.078888
1182 10:51:55.079310 Set Vref, RX VrefLevel [Byte0]: 78
1183 10:51:55.082095 [Byte1]: 78
1184 10:51:55.086345
1185 10:51:55.086768 Set Vref, RX VrefLevel [Byte0]: 79
1186 10:51:55.089811 [Byte1]: 79
1187 10:51:55.093893
1188 10:51:55.094318 Final RX Vref Byte 0 = 57 to rank0
1189 10:51:55.097392 Final RX Vref Byte 1 = 56 to rank0
1190 10:51:55.100477 Final RX Vref Byte 0 = 57 to rank1
1191 10:51:55.104297 Final RX Vref Byte 1 = 56 to rank1==
1192 10:51:55.107254 Dram Type= 6, Freq= 0, CH_0, rank 0
1193 10:51:55.114105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 10:51:55.114530 ==
1195 10:51:55.114874 DQS Delay:
1196 10:51:55.115193 DQS0 = 0, DQS1 = 0
1197 10:51:55.117117 DQM Delay:
1198 10:51:55.117575 DQM0 = 92, DQM1 = 85
1199 10:51:55.120434 DQ Delay:
1200 10:51:55.124186 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1201 10:51:55.127262 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1202 10:51:55.127830 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =80
1203 10:51:55.133668 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1204 10:51:55.134096
1205 10:51:55.134428
1206 10:51:55.140460 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1207 10:51:55.144259 CH0 RK0: MR19=606, MR18=4F45
1208 10:51:55.150821 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1209 10:51:55.151388
1210 10:51:55.153697 ----->DramcWriteLeveling(PI) begin...
1211 10:51:55.154140 ==
1212 10:51:55.157578 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 10:51:55.160833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 10:51:55.161260 ==
1215 10:51:55.164203 Write leveling (Byte 0): 34 => 34
1216 10:51:55.167229 Write leveling (Byte 1): 31 => 31
1217 10:51:55.211284 DramcWriteLeveling(PI) end<-----
1218 10:51:55.211776
1219 10:51:55.212117 ==
1220 10:51:55.212440 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 10:51:55.212745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 10:51:55.213043 ==
1223 10:51:55.213334 [Gating] SW mode calibration
1224 10:51:55.214046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1225 10:51:55.214535 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1226 10:51:55.214856 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1227 10:51:55.215158 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1228 10:51:55.215492 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1229 10:51:55.215817 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:51:55.255271 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:51:55.255841 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:51:55.256212 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:51:55.256958 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:51:55.257458 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 10:51:55.257918 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:51:55.258365 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:51:55.258802 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 10:51:55.259240 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 10:51:55.259605 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 10:51:55.298695 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:51:55.299535 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:51:55.299978 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:51:55.300418 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1244 10:51:55.300744 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1245 10:51:55.301051 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:51:55.301350 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 10:51:55.301641 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:51:55.301932 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 10:51:55.302275 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 10:51:55.303674 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:51:55.306989 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:51:55.310663 0 9 8 | B1->B0 | 2c2c 2a29 | 1 1 | (1 1) (1 1)
1253 10:51:55.317037 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 10:51:55.320740 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 10:51:55.324160 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 10:51:55.330416 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 10:51:55.333614 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 10:51:55.337511 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 10:51:55.340660 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1260 10:51:55.348019 0 10 8 | B1->B0 | 2727 2929 | 0 1 | (1 0) (0 0)
1261 10:51:55.351511 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 10:51:55.355360 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 10:51:55.359202 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 10:51:55.365617 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 10:51:55.369434 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 10:51:55.372595 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 10:51:55.375681 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1268 10:51:55.382311 0 11 8 | B1->B0 | 3a3a 3636 | 0 1 | (0 0) (0 0)
1269 10:51:55.386086 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 10:51:55.389149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 10:51:55.395593 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 10:51:55.398729 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 10:51:55.402319 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 10:51:55.409020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 10:51:55.412255 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 10:51:55.415894 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1277 10:51:55.422448 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:51:55.425911 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 10:51:55.428927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 10:51:55.435657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 10:51:55.438962 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 10:51:55.442771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 10:51:55.449111 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 10:51:55.452629 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 10:51:55.455600 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 10:51:55.462463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 10:51:55.465746 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 10:51:55.469700 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 10:51:55.472768 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 10:51:55.479178 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 10:51:55.483042 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 10:51:55.486292 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1293 10:51:55.492389 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1294 10:51:55.496410 Total UI for P1: 0, mck2ui 16
1295 10:51:55.499577 best dqsien dly found for B0: ( 0, 14, 8)
1296 10:51:55.500180 Total UI for P1: 0, mck2ui 16
1297 10:51:55.506487 best dqsien dly found for B1: ( 0, 14, 8)
1298 10:51:55.509373 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1299 10:51:55.512943 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1300 10:51:55.513421
1301 10:51:55.515933 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1302 10:51:55.519863 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1303 10:51:55.522956 [Gating] SW calibration Done
1304 10:51:55.523410 ==
1305 10:51:55.525975 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 10:51:55.529670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 10:51:55.530097 ==
1308 10:51:55.533165 RX Vref Scan: 0
1309 10:51:55.533586
1310 10:51:55.533913 RX Vref 0 -> 0, step: 1
1311 10:51:55.534222
1312 10:51:55.536639 RX Delay -130 -> 252, step: 16
1313 10:51:55.539508 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1314 10:51:55.546372 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1315 10:51:55.549775 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1316 10:51:55.552830 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1317 10:51:55.556581 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1318 10:51:55.559819 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1319 10:51:55.562847 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1320 10:51:55.569541 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1321 10:51:55.573252 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1322 10:51:55.576440 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1323 10:51:55.579360 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1324 10:51:55.583194 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1325 10:51:55.589512 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1326 10:51:55.593089 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1327 10:51:55.596274 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1328 10:51:55.600023 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1329 10:51:55.600153 ==
1330 10:51:55.603248 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 10:51:55.609608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 10:51:55.609703 ==
1333 10:51:55.609776 DQS Delay:
1334 10:51:55.609845 DQS0 = 0, DQS1 = 0
1335 10:51:55.613373 DQM Delay:
1336 10:51:55.613465 DQM0 = 91, DQM1 = 81
1337 10:51:55.616441 DQ Delay:
1338 10:51:55.619884 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1339 10:51:55.623082 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1340 10:51:55.623165 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1341 10:51:55.626817 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1342 10:51:55.629933
1343 10:51:55.630017
1344 10:51:55.630081 ==
1345 10:51:55.633036 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 10:51:55.636772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 10:51:55.636855 ==
1348 10:51:55.636920
1349 10:51:55.636980
1350 10:51:55.639648 TX Vref Scan disable
1351 10:51:55.639730 == TX Byte 0 ==
1352 10:51:55.646653 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1353 10:51:55.649955 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1354 10:51:55.650041 == TX Byte 1 ==
1355 10:51:55.656836 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1356 10:51:55.660062 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1357 10:51:55.660151 ==
1358 10:51:55.663208 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 10:51:55.666281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 10:51:55.666369 ==
1361 10:51:55.680375 TX Vref=22, minBit 8, minWin=27, winSum=447
1362 10:51:55.683531 TX Vref=24, minBit 1, minWin=28, winSum=451
1363 10:51:55.687303 TX Vref=26, minBit 9, minWin=27, winSum=455
1364 10:51:55.690727 TX Vref=28, minBit 8, minWin=27, winSum=457
1365 10:51:55.693805 TX Vref=30, minBit 2, minWin=28, winSum=455
1366 10:51:55.696972 TX Vref=32, minBit 10, minWin=27, winSum=450
1367 10:51:55.704075 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
1368 10:51:55.704157
1369 10:51:55.707143 Final TX Range 1 Vref 30
1370 10:51:55.707225
1371 10:51:55.707288 ==
1372 10:51:55.710269 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 10:51:55.713631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 10:51:55.713713 ==
1375 10:51:55.713776
1376 10:51:55.717443
1377 10:51:55.717524 TX Vref Scan disable
1378 10:51:55.720755 == TX Byte 0 ==
1379 10:51:55.723712 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1380 10:51:55.727342 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1381 10:51:55.730357 == TX Byte 1 ==
1382 10:51:55.733940 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1383 10:51:55.737076 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1384 10:51:55.740461
1385 10:51:55.740541 [DATLAT]
1386 10:51:55.740604 Freq=800, CH0 RK1
1387 10:51:55.740662
1388 10:51:55.743985 DATLAT Default: 0xa
1389 10:51:55.744065 0, 0xFFFF, sum = 0
1390 10:51:55.747197 1, 0xFFFF, sum = 0
1391 10:51:55.747279 2, 0xFFFF, sum = 0
1392 10:51:55.750540 3, 0xFFFF, sum = 0
1393 10:51:55.750621 4, 0xFFFF, sum = 0
1394 10:51:55.753895 5, 0xFFFF, sum = 0
1395 10:51:55.753975 6, 0xFFFF, sum = 0
1396 10:51:55.756800 7, 0xFFFF, sum = 0
1397 10:51:55.760905 8, 0xFFFF, sum = 0
1398 10:51:55.760986 9, 0x0, sum = 1
1399 10:51:55.761050 10, 0x0, sum = 2
1400 10:51:55.763729 11, 0x0, sum = 3
1401 10:51:55.763810 12, 0x0, sum = 4
1402 10:51:55.767564 best_step = 10
1403 10:51:55.767645
1404 10:51:55.767708 ==
1405 10:51:55.770489 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 10:51:55.773721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 10:51:55.773801 ==
1408 10:51:55.777458 RX Vref Scan: 0
1409 10:51:55.777551
1410 10:51:55.777614 RX Vref 0 -> 0, step: 1
1411 10:51:55.777674
1412 10:51:55.780483 RX Delay -95 -> 252, step: 8
1413 10:51:55.787691 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1414 10:51:55.790620 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1415 10:51:55.793765 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1416 10:51:55.797046 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1417 10:51:55.800745 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1418 10:51:55.807682 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1419 10:51:55.810747 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1420 10:51:55.814040 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1421 10:51:55.817302 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1422 10:51:55.821101 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1423 10:51:55.824278 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1424 10:51:55.831207 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1425 10:51:55.834203 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1426 10:51:55.837677 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1427 10:51:55.841283 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1428 10:51:55.844342 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1429 10:51:55.848087 ==
1430 10:51:55.848221 Dram Type= 6, Freq= 0, CH_0, rank 1
1431 10:51:55.854529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 10:51:55.854681 ==
1433 10:51:55.854800 DQS Delay:
1434 10:51:55.857563 DQS0 = 0, DQS1 = 0
1435 10:51:55.857757 DQM Delay:
1436 10:51:55.861087 DQM0 = 93, DQM1 = 83
1437 10:51:55.861258 DQ Delay:
1438 10:51:55.864760 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1439 10:51:55.867674 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1440 10:51:55.870997 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1441 10:51:55.874644 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1442 10:51:55.874967
1443 10:51:55.875209
1444 10:51:55.881091 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
1445 10:51:55.884852 CH0 RK1: MR19=606, MR18=3F0F
1446 10:51:55.891156 CH0_RK1: MR19=0x606, MR18=0x3F0F, DQSOSC=393, MR23=63, INC=95, DEC=63
1447 10:51:55.894710 [RxdqsGatingPostProcess] freq 800
1448 10:51:55.898199 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1449 10:51:55.901374 Pre-setting of DQS Precalculation
1450 10:51:55.908215 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1451 10:51:55.908643 ==
1452 10:51:55.911884 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 10:51:55.915037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 10:51:55.915508 ==
1455 10:51:55.922030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1456 10:51:55.928323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1457 10:51:55.936121 [CA 0] Center 36 (6~67) winsize 62
1458 10:51:55.938938 [CA 1] Center 36 (6~67) winsize 62
1459 10:51:55.942497 [CA 2] Center 35 (5~65) winsize 61
1460 10:51:55.945671 [CA 3] Center 35 (5~65) winsize 61
1461 10:51:55.949354 [CA 4] Center 35 (5~65) winsize 61
1462 10:51:55.952355 [CA 5] Center 34 (4~65) winsize 62
1463 10:51:55.952935
1464 10:51:55.956338 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1465 10:51:55.956783
1466 10:51:55.959510 [CATrainingPosCal] consider 1 rank data
1467 10:51:55.962761 u2DelayCellTimex100 = 270/100 ps
1468 10:51:55.965858 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1469 10:51:55.969578 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1470 10:51:55.972596 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1471 10:51:55.979791 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1472 10:51:55.982810 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1473 10:51:55.986164 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 10:51:55.986589
1475 10:51:55.989460 CA PerBit enable=1, Macro0, CA PI delay=34
1476 10:51:55.990003
1477 10:51:55.992558 [CBTSetCACLKResult] CA Dly = 34
1478 10:51:55.992983 CS Dly: 6 (0~37)
1479 10:51:55.993316 ==
1480 10:51:55.996255 Dram Type= 6, Freq= 0, CH_1, rank 1
1481 10:51:56.003249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 10:51:56.003846 ==
1483 10:51:56.007008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1484 10:51:56.013859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1485 10:51:56.022742 [CA 0] Center 36 (6~67) winsize 62
1486 10:51:56.026670 [CA 1] Center 37 (6~68) winsize 63
1487 10:51:56.030425 [CA 2] Center 35 (5~66) winsize 62
1488 10:51:56.033685 [CA 3] Center 35 (5~65) winsize 61
1489 10:51:56.037489 [CA 4] Center 35 (5~65) winsize 61
1490 10:51:56.037956 [CA 5] Center 34 (4~65) winsize 62
1491 10:51:56.038302
1492 10:51:56.044318 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1493 10:51:56.044766
1494 10:51:56.047792 [CATrainingPosCal] consider 2 rank data
1495 10:51:56.050837 u2DelayCellTimex100 = 270/100 ps
1496 10:51:56.054199 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1497 10:51:56.057576 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1498 10:51:56.060660 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1499 10:51:56.064473 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1500 10:51:56.067505 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1501 10:51:56.071007 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 10:51:56.071599
1503 10:51:56.074093 CA PerBit enable=1, Macro0, CA PI delay=34
1504 10:51:56.074543
1505 10:51:56.077876 [CBTSetCACLKResult] CA Dly = 34
1506 10:51:56.080937 CS Dly: 6 (0~38)
1507 10:51:56.081365
1508 10:51:56.084490 ----->DramcWriteLeveling(PI) begin...
1509 10:51:56.084945 ==
1510 10:51:56.087480 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 10:51:56.091253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 10:51:56.091728 ==
1513 10:51:56.094436 Write leveling (Byte 0): 26 => 26
1514 10:51:56.097602 Write leveling (Byte 1): 29 => 29
1515 10:51:56.100854 DramcWriteLeveling(PI) end<-----
1516 10:51:56.101281
1517 10:51:56.101641 ==
1518 10:51:56.104508 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 10:51:56.107514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 10:51:56.107964 ==
1521 10:51:56.111082 [Gating] SW mode calibration
1522 10:51:56.117694 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1523 10:51:56.124716 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1524 10:51:56.127698 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1525 10:51:56.130888 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1526 10:51:56.137948 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1527 10:51:56.141120 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:51:56.144237 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:51:56.150921 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:51:56.154006 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 10:51:56.157565 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:51:56.163747 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:51:56.167368 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 10:51:56.170544 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 10:51:56.177224 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 10:51:56.180725 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 10:51:56.184022 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 10:51:56.190254 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 10:51:56.193867 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:51:56.197492 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1541 10:51:56.200544 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1542 10:51:56.207560 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:51:56.210781 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:51:56.213862 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:51:56.220348 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:51:56.224027 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 10:51:56.226950 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:51:56.233848 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:51:56.237630 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1550 10:51:56.240948 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1551 10:51:56.247723 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 10:51:56.250781 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 10:51:56.253940 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 10:51:56.260844 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 10:51:56.264691 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 10:51:56.267963 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1557 10:51:56.271051 0 10 4 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (1 1)
1558 10:51:56.277946 0 10 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (1 0)
1559 10:51:56.281054 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 10:51:56.284526 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 10:51:56.291503 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 10:51:56.294546 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 10:51:56.297723 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 10:51:56.304465 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1565 10:51:56.308159 0 11 4 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
1566 10:51:56.311196 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1567 10:51:56.318340 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 10:51:56.321477 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 10:51:56.324438 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 10:51:56.331425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 10:51:56.335012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 10:51:56.338064 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1573 10:51:56.344473 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1574 10:51:56.348240 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:51:56.351342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 10:51:56.355088 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 10:51:56.361285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 10:51:56.365074 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 10:51:56.368162 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 10:51:56.375159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 10:51:56.378298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 10:51:56.381182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 10:51:56.387953 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 10:51:56.391369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 10:51:56.394601 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 10:51:56.401743 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 10:51:56.404906 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 10:51:56.408104 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 10:51:56.414848 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1590 10:51:56.417887 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 10:51:56.421095 Total UI for P1: 0, mck2ui 16
1592 10:51:56.424999 best dqsien dly found for B0: ( 0, 14, 4)
1593 10:51:56.428262 Total UI for P1: 0, mck2ui 16
1594 10:51:56.431233 best dqsien dly found for B1: ( 0, 14, 4)
1595 10:51:56.434318 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1596 10:51:56.437980 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1597 10:51:56.438428
1598 10:51:56.441363 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1599 10:51:56.444930 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1600 10:51:56.447687 [Gating] SW calibration Done
1601 10:51:56.448108 ==
1602 10:51:56.451472 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 10:51:56.454639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 10:51:56.455067 ==
1605 10:51:56.457858 RX Vref Scan: 0
1606 10:51:56.458281
1607 10:51:56.460990 RX Vref 0 -> 0, step: 1
1608 10:51:56.461412
1609 10:51:56.461744 RX Delay -130 -> 252, step: 16
1610 10:51:56.468314 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1611 10:51:56.471612 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1612 10:51:56.474788 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1613 10:51:56.477923 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1614 10:51:56.481538 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1615 10:51:56.487958 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1616 10:51:56.491451 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1617 10:51:56.495005 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1618 10:51:56.497911 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1619 10:51:56.501694 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1620 10:51:56.508098 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1621 10:51:56.511571 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1622 10:51:56.514950 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1623 10:51:56.518225 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1624 10:51:56.521287 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1625 10:51:56.528524 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1626 10:51:56.529093 ==
1627 10:51:56.531651 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 10:51:56.534785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 10:51:56.535234 ==
1630 10:51:56.535623 DQS Delay:
1631 10:51:56.537879 DQS0 = 0, DQS1 = 0
1632 10:51:56.538339 DQM Delay:
1633 10:51:56.541477 DQM0 = 93, DQM1 = 87
1634 10:51:56.541932 DQ Delay:
1635 10:51:56.544452 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1636 10:51:56.548286 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1637 10:51:56.551258 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1638 10:51:56.554715 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1639 10:51:56.555162
1640 10:51:56.555552
1641 10:51:56.555874 ==
1642 10:51:56.558190 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 10:51:56.561678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 10:51:56.562128 ==
1645 10:51:56.562465
1646 10:51:56.562801
1647 10:51:56.564671 TX Vref Scan disable
1648 10:51:56.567909 == TX Byte 0 ==
1649 10:51:56.571459 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1650 10:51:56.575074 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1651 10:51:56.578343 == TX Byte 1 ==
1652 10:51:56.582095 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1653 10:51:56.585384 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1654 10:51:56.585832 ==
1655 10:51:56.589187 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 10:51:56.592434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 10:51:56.592883 ==
1658 10:51:56.606822 TX Vref=22, minBit 1, minWin=26, winSum=435
1659 10:51:56.609922 TX Vref=24, minBit 1, minWin=26, winSum=436
1660 10:51:56.613046 TX Vref=26, minBit 1, minWin=26, winSum=442
1661 10:51:56.616942 TX Vref=28, minBit 1, minWin=27, winSum=446
1662 10:51:56.620127 TX Vref=30, minBit 0, minWin=27, winSum=447
1663 10:51:56.623283 TX Vref=32, minBit 7, minWin=26, winSum=445
1664 10:51:56.630112 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
1665 10:51:56.630578
1666 10:51:56.633298 Final TX Range 1 Vref 30
1667 10:51:56.633742
1668 10:51:56.634093 ==
1669 10:51:56.637237 Dram Type= 6, Freq= 0, CH_1, rank 0
1670 10:51:56.640473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1671 10:51:56.640902 ==
1672 10:51:56.641258
1673 10:51:56.641571
1674 10:51:56.643681 TX Vref Scan disable
1675 10:51:56.646798 == TX Byte 0 ==
1676 10:51:56.650503 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1677 10:51:56.653761 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1678 10:51:56.657005 == TX Byte 1 ==
1679 10:51:56.660084 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1680 10:51:56.663471 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1681 10:51:56.663920
1682 10:51:56.667055 [DATLAT]
1683 10:51:56.667533 Freq=800, CH1 RK0
1684 10:51:56.667908
1685 10:51:56.670380 DATLAT Default: 0xa
1686 10:51:56.670828 0, 0xFFFF, sum = 0
1687 10:51:56.673262 1, 0xFFFF, sum = 0
1688 10:51:56.673718 2, 0xFFFF, sum = 0
1689 10:51:56.676894 3, 0xFFFF, sum = 0
1690 10:51:56.677463 4, 0xFFFF, sum = 0
1691 10:51:56.680542 5, 0xFFFF, sum = 0
1692 10:51:56.681018 6, 0xFFFF, sum = 0
1693 10:51:56.683577 7, 0xFFFF, sum = 0
1694 10:51:56.684011 8, 0xFFFF, sum = 0
1695 10:51:56.686795 9, 0x0, sum = 1
1696 10:51:56.687253 10, 0x0, sum = 2
1697 10:51:56.690105 11, 0x0, sum = 3
1698 10:51:56.690554 12, 0x0, sum = 4
1699 10:51:56.693673 best_step = 10
1700 10:51:56.694122
1701 10:51:56.694462 ==
1702 10:51:56.696951 Dram Type= 6, Freq= 0, CH_1, rank 0
1703 10:51:56.700148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1704 10:51:56.700619 ==
1705 10:51:56.703407 RX Vref Scan: 1
1706 10:51:56.703849
1707 10:51:56.704196 Set Vref Range= 32 -> 127
1708 10:51:56.704512
1709 10:51:56.707159 RX Vref 32 -> 127, step: 1
1710 10:51:56.707645
1711 10:51:56.710144 RX Delay -79 -> 252, step: 8
1712 10:51:56.710590
1713 10:51:56.713665 Set Vref, RX VrefLevel [Byte0]: 32
1714 10:51:56.717262 [Byte1]: 32
1715 10:51:56.717693
1716 10:51:56.720206 Set Vref, RX VrefLevel [Byte0]: 33
1717 10:51:56.723492 [Byte1]: 33
1718 10:51:56.723941
1719 10:51:56.726684 Set Vref, RX VrefLevel [Byte0]: 34
1720 10:51:56.730568 [Byte1]: 34
1721 10:51:56.734270
1722 10:51:56.734692 Set Vref, RX VrefLevel [Byte0]: 35
1723 10:51:56.737982 [Byte1]: 35
1724 10:51:56.741762
1725 10:51:56.742276 Set Vref, RX VrefLevel [Byte0]: 36
1726 10:51:56.745089 [Byte1]: 36
1727 10:51:56.749308
1728 10:51:56.749742 Set Vref, RX VrefLevel [Byte0]: 37
1729 10:51:56.752977 [Byte1]: 37
1730 10:51:56.756947
1731 10:51:56.757500 Set Vref, RX VrefLevel [Byte0]: 38
1732 10:51:56.759973 [Byte1]: 38
1733 10:51:56.769104
1734 10:51:56.769530 Set Vref, RX VrefLevel [Byte0]: 39
1735 10:51:56.769886 [Byte1]: 39
1736 10:51:56.771755
1737 10:51:56.772209 Set Vref, RX VrefLevel [Byte0]: 40
1738 10:51:56.775215 [Byte1]: 40
1739 10:51:56.779521
1740 10:51:56.779966 Set Vref, RX VrefLevel [Byte0]: 41
1741 10:51:56.783055 [Byte1]: 41
1742 10:51:56.787038
1743 10:51:56.787569 Set Vref, RX VrefLevel [Byte0]: 42
1744 10:51:56.790491 [Byte1]: 42
1745 10:51:56.794972
1746 10:51:56.795453 Set Vref, RX VrefLevel [Byte0]: 43
1747 10:51:56.797818 [Byte1]: 43
1748 10:51:56.802223
1749 10:51:56.802733 Set Vref, RX VrefLevel [Byte0]: 44
1750 10:51:56.805344 [Byte1]: 44
1751 10:51:56.809821
1752 10:51:56.810295 Set Vref, RX VrefLevel [Byte0]: 45
1753 10:51:56.812912 [Byte1]: 45
1754 10:51:56.817085
1755 10:51:56.817556 Set Vref, RX VrefLevel [Byte0]: 46
1756 10:51:56.820963 [Byte1]: 46
1757 10:51:56.824638
1758 10:51:56.825106 Set Vref, RX VrefLevel [Byte0]: 47
1759 10:51:56.828767 [Byte1]: 47
1760 10:51:56.832286
1761 10:51:56.832715 Set Vref, RX VrefLevel [Byte0]: 48
1762 10:51:56.836124 [Byte1]: 48
1763 10:51:56.839902
1764 10:51:56.840332 Set Vref, RX VrefLevel [Byte0]: 49
1765 10:51:56.843613 [Byte1]: 49
1766 10:51:56.847286
1767 10:51:56.847816 Set Vref, RX VrefLevel [Byte0]: 50
1768 10:51:56.851029 [Byte1]: 50
1769 10:51:56.855280
1770 10:51:56.855852 Set Vref, RX VrefLevel [Byte0]: 51
1771 10:51:56.858287 [Byte1]: 51
1772 10:51:56.862631
1773 10:51:56.863106 Set Vref, RX VrefLevel [Byte0]: 52
1774 10:51:56.865799 [Byte1]: 52
1775 10:51:56.870205
1776 10:51:56.870645 Set Vref, RX VrefLevel [Byte0]: 53
1777 10:51:56.873413 [Byte1]: 53
1778 10:51:56.877740
1779 10:51:56.878213 Set Vref, RX VrefLevel [Byte0]: 54
1780 10:51:56.881374 [Byte1]: 54
1781 10:51:56.884891
1782 10:51:56.885316 Set Vref, RX VrefLevel [Byte0]: 55
1783 10:51:56.888712 [Byte1]: 55
1784 10:51:56.892819
1785 10:51:56.893185 Set Vref, RX VrefLevel [Byte0]: 56
1786 10:51:56.895747 [Byte1]: 56
1787 10:51:56.900382
1788 10:51:56.900635 Set Vref, RX VrefLevel [Byte0]: 57
1789 10:51:56.903198 [Byte1]: 57
1790 10:51:56.907708
1791 10:51:56.907926 Set Vref, RX VrefLevel [Byte0]: 58
1792 10:51:56.910790 [Byte1]: 58
1793 10:51:56.915189
1794 10:51:56.915322 Set Vref, RX VrefLevel [Byte0]: 59
1795 10:51:56.918339 [Byte1]: 59
1796 10:51:56.922769
1797 10:51:56.922872 Set Vref, RX VrefLevel [Byte0]: 60
1798 10:51:56.925755 [Byte1]: 60
1799 10:51:56.929941
1800 10:51:56.930034 Set Vref, RX VrefLevel [Byte0]: 61
1801 10:51:56.933425 [Byte1]: 61
1802 10:51:56.937503
1803 10:51:56.937586 Set Vref, RX VrefLevel [Byte0]: 62
1804 10:51:56.940807 [Byte1]: 62
1805 10:51:56.945190
1806 10:51:56.945273 Set Vref, RX VrefLevel [Byte0]: 63
1807 10:51:56.948401 [Byte1]: 63
1808 10:51:56.952485
1809 10:51:56.952570 Set Vref, RX VrefLevel [Byte0]: 64
1810 10:51:56.956204 [Byte1]: 64
1811 10:51:56.960489
1812 10:51:56.960573 Set Vref, RX VrefLevel [Byte0]: 65
1813 10:51:56.963512 [Byte1]: 65
1814 10:51:56.968103
1815 10:51:56.968186 Set Vref, RX VrefLevel [Byte0]: 66
1816 10:51:56.971132 [Byte1]: 66
1817 10:51:56.975515
1818 10:51:56.975607 Set Vref, RX VrefLevel [Byte0]: 67
1819 10:51:56.981690 [Byte1]: 67
1820 10:51:56.981775
1821 10:51:56.985308 Set Vref, RX VrefLevel [Byte0]: 68
1822 10:51:56.988473 [Byte1]: 68
1823 10:51:56.988557
1824 10:51:56.991675 Set Vref, RX VrefLevel [Byte0]: 69
1825 10:51:56.995488 [Byte1]: 69
1826 10:51:56.995570
1827 10:51:56.998559 Set Vref, RX VrefLevel [Byte0]: 70
1828 10:51:57.002208 [Byte1]: 70
1829 10:51:57.005961
1830 10:51:57.006044 Final RX Vref Byte 0 = 58 to rank0
1831 10:51:57.009032 Final RX Vref Byte 1 = 54 to rank0
1832 10:51:57.012354 Final RX Vref Byte 0 = 58 to rank1
1833 10:51:57.015606 Final RX Vref Byte 1 = 54 to rank1==
1834 10:51:57.018873 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 10:51:57.022598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 10:51:57.025682 ==
1837 10:51:57.025770 DQS Delay:
1838 10:51:57.025840 DQS0 = 0, DQS1 = 0
1839 10:51:57.029430 DQM Delay:
1840 10:51:57.029525 DQM0 = 95, DQM1 = 89
1841 10:51:57.032589 DQ Delay:
1842 10:51:57.035554 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1843 10:51:57.039091 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =96
1844 10:51:57.042184 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1845 10:51:57.045573 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1846 10:51:57.045697
1847 10:51:57.045792
1848 10:51:57.052658 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1849 10:51:57.055596 CH1 RK0: MR19=606, MR18=2E4A
1850 10:51:57.062691 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1851 10:51:57.062898
1852 10:51:57.066009 ----->DramcWriteLeveling(PI) begin...
1853 10:51:57.066218 ==
1854 10:51:57.069119 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 10:51:57.072907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 10:51:57.073283 ==
1857 10:51:57.076038 Write leveling (Byte 0): 25 => 25
1858 10:51:57.079264 Write leveling (Byte 1): 26 => 26
1859 10:51:57.083014 DramcWriteLeveling(PI) end<-----
1860 10:51:57.083486
1861 10:51:57.083916 ==
1862 10:51:57.086009 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 10:51:57.089174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 10:51:57.089637 ==
1865 10:51:57.092806 [Gating] SW mode calibration
1866 10:51:57.099606 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 10:51:57.105983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 10:51:57.109186 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 10:51:57.112933 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:51:57.119466 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:51:57.122966 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:51:57.125951 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:51:57.132591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:51:57.135808 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:51:57.139511 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:51:57.146015 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:51:57.149552 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:51:57.152428 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:51:57.159368 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:51:57.162560 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:51:57.165649 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:51:57.169268 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:51:57.175906 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:51:57.179077 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1885 10:51:57.182850 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1886 10:51:57.189184 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:51:57.192356 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:51:57.196202 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:51:57.202245 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:51:57.206000 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:51:57.209337 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:51:57.216258 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 10:51:57.219312 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1894 10:51:57.222628 0 9 8 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (0 0)
1895 10:51:57.229313 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 10:51:57.232714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 10:51:57.236203 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 10:51:57.242482 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 10:51:57.246237 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 10:51:57.249203 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1901 10:51:57.255812 0 10 4 | B1->B0 | 2d2d 3232 | 1 1 | (1 0) (1 1)
1902 10:51:57.259037 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1903 10:51:57.262851 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:51:57.269315 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:51:57.272813 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:51:57.275780 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:51:57.279425 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:51:57.285710 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1909 10:51:57.289480 0 11 4 | B1->B0 | 3c3c 2b2b | 0 0 | (0 0) (0 0)
1910 10:51:57.292623 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1911 10:51:57.299355 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 10:51:57.302411 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 10:51:57.305677 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 10:51:57.312526 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 10:51:57.315828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 10:51:57.319580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1917 10:51:57.325928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1918 10:51:57.329461 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:51:57.332561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:51:57.339080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:51:57.342456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:51:57.345865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:51:57.352782 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:51:57.355893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:51:57.359190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:51:57.366394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:51:57.369714 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:51:57.372989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:51:57.376093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:51:57.382722 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:51:57.386177 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 10:51:57.389429 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1933 10:51:57.396157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1934 10:51:57.396632 Total UI for P1: 0, mck2ui 16
1935 10:51:57.403128 best dqsien dly found for B1: ( 0, 14, 2)
1936 10:51:57.406197 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 10:51:57.409730 Total UI for P1: 0, mck2ui 16
1938 10:51:57.412902 best dqsien dly found for B0: ( 0, 14, 2)
1939 10:51:57.415929 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1940 10:51:57.419703 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1941 10:51:57.420127
1942 10:51:57.422834 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1943 10:51:57.425918 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1944 10:51:57.429746 [Gating] SW calibration Done
1945 10:51:57.430168 ==
1946 10:51:57.432723 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 10:51:57.435899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 10:51:57.436323 ==
1949 10:51:57.439767 RX Vref Scan: 0
1950 10:51:57.440188
1951 10:51:57.442717 RX Vref 0 -> 0, step: 1
1952 10:51:57.443137
1953 10:51:57.443525 RX Delay -130 -> 252, step: 16
1954 10:51:57.449429 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1955 10:51:57.452959 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1956 10:51:57.455863 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1957 10:51:57.459611 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1958 10:51:57.462717 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1959 10:51:57.469267 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1960 10:51:57.473311 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1961 10:51:57.476162 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1962 10:51:57.480082 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1963 10:51:57.483227 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1964 10:51:57.490110 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1965 10:51:57.493023 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1966 10:51:57.496416 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1967 10:51:57.499795 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1968 10:51:57.503443 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1969 10:51:57.509514 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1970 10:51:57.509939 ==
1971 10:51:57.513160 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 10:51:57.516800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 10:51:57.517229 ==
1974 10:51:57.517565 DQS Delay:
1975 10:51:57.519719 DQS0 = 0, DQS1 = 0
1976 10:51:57.520139 DQM Delay:
1977 10:51:57.522840 DQM0 = 93, DQM1 = 91
1978 10:51:57.523261 DQ Delay:
1979 10:51:57.526697 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1980 10:51:57.529903 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1981 10:51:57.533545 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1982 10:51:57.536743 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1983 10:51:57.537177
1984 10:51:57.537510
1985 10:51:57.537817 ==
1986 10:51:57.539947 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 10:51:57.543290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 10:51:57.543803 ==
1989 10:51:57.547005
1990 10:51:57.547456
1991 10:51:57.547795 TX Vref Scan disable
1992 10:51:57.550167 == TX Byte 0 ==
1993 10:51:57.553262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1994 10:51:57.556857 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1995 10:51:57.560367 == TX Byte 1 ==
1996 10:51:57.563472 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1997 10:51:57.567358 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1998 10:51:57.567914 ==
1999 10:51:57.570278 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 10:51:57.576459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 10:51:57.576881 ==
2002 10:51:57.588439 TX Vref=22, minBit 3, minWin=26, winSum=435
2003 10:51:57.591632 TX Vref=24, minBit 1, minWin=26, winSum=439
2004 10:51:57.595283 TX Vref=26, minBit 1, minWin=27, winSum=443
2005 10:51:57.598238 TX Vref=28, minBit 0, minWin=27, winSum=443
2006 10:51:57.601982 TX Vref=30, minBit 0, minWin=27, winSum=447
2007 10:51:57.605052 TX Vref=32, minBit 0, minWin=27, winSum=446
2008 10:51:57.611630 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
2009 10:51:57.612089
2010 10:51:57.615319 Final TX Range 1 Vref 30
2011 10:51:57.615773
2012 10:51:57.616143 ==
2013 10:51:57.618343 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 10:51:57.621857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 10:51:57.622288 ==
2016 10:51:57.622733
2017 10:51:57.624810
2018 10:51:57.625337 TX Vref Scan disable
2019 10:51:57.628722 == TX Byte 0 ==
2020 10:51:57.632036 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2021 10:51:57.635012 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2022 10:51:57.638904 == TX Byte 1 ==
2023 10:51:57.641915 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2024 10:51:57.645186 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2025 10:51:57.645737
2026 10:51:57.648363 [DATLAT]
2027 10:51:57.648877 Freq=800, CH1 RK1
2028 10:51:57.649238
2029 10:51:57.652077 DATLAT Default: 0xa
2030 10:51:57.652505 0, 0xFFFF, sum = 0
2031 10:51:57.655361 1, 0xFFFF, sum = 0
2032 10:51:57.656004 2, 0xFFFF, sum = 0
2033 10:51:57.658518 3, 0xFFFF, sum = 0
2034 10:51:57.658954 4, 0xFFFF, sum = 0
2035 10:51:57.661686 5, 0xFFFF, sum = 0
2036 10:51:57.662167 6, 0xFFFF, sum = 0
2037 10:51:57.665448 7, 0xFFFF, sum = 0
2038 10:51:57.665929 8, 0xFFFF, sum = 0
2039 10:51:57.668463 9, 0x0, sum = 1
2040 10:51:57.668905 10, 0x0, sum = 2
2041 10:51:57.672020 11, 0x0, sum = 3
2042 10:51:57.672639 12, 0x0, sum = 4
2043 10:51:57.675018 best_step = 10
2044 10:51:57.675466
2045 10:51:57.675798 ==
2046 10:51:57.678661 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 10:51:57.682091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 10:51:57.682514 ==
2049 10:51:57.685277 RX Vref Scan: 0
2050 10:51:57.685669
2051 10:51:57.685986 RX Vref 0 -> 0, step: 1
2052 10:51:57.686287
2053 10:51:57.688280 RX Delay -79 -> 252, step: 8
2054 10:51:57.695076 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2055 10:51:57.698760 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2056 10:51:57.701601 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2057 10:51:57.705175 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2058 10:51:57.708989 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2059 10:51:57.712052 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2060 10:51:57.718197 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2061 10:51:57.721827 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2062 10:51:57.725257 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2063 10:51:57.728830 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2064 10:51:57.731839 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2065 10:51:57.738780 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2066 10:51:57.742041 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2067 10:51:57.745177 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2068 10:51:57.748271 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2069 10:51:57.752086 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2070 10:51:57.752507 ==
2071 10:51:57.755319 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 10:51:57.761610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 10:51:57.762030 ==
2074 10:51:57.762360 DQS Delay:
2075 10:51:57.765158 DQS0 = 0, DQS1 = 0
2076 10:51:57.765575 DQM Delay:
2077 10:51:57.765904 DQM0 = 97, DQM1 = 90
2078 10:51:57.768199 DQ Delay:
2079 10:51:57.771847 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2080 10:51:57.775403 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2081 10:51:57.778686 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2082 10:51:57.781875 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2083 10:51:57.782294
2084 10:51:57.782626
2085 10:51:57.788616 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2086 10:51:57.791653 CH1 RK1: MR19=606, MR18=450F
2087 10:51:57.798805 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2088 10:51:57.801961 [RxdqsGatingPostProcess] freq 800
2089 10:51:57.805078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 10:51:57.808709 Pre-setting of DQS Precalculation
2091 10:51:57.815299 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 10:51:57.822122 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 10:51:57.828874 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 10:51:57.829321
2095 10:51:57.829647
2096 10:51:57.832205 [Calibration Summary] 1600 Mbps
2097 10:51:57.832762 CH 0, Rank 0
2098 10:51:57.835300 SW Impedance : PASS
2099 10:51:57.838829 DUTY Scan : NO K
2100 10:51:57.839293 ZQ Calibration : PASS
2101 10:51:57.841873 Jitter Meter : NO K
2102 10:51:57.845678 CBT Training : PASS
2103 10:51:57.846162 Write leveling : PASS
2104 10:51:57.848842 RX DQS gating : PASS
2105 10:51:57.852028 RX DQ/DQS(RDDQC) : PASS
2106 10:51:57.852510 TX DQ/DQS : PASS
2107 10:51:57.855322 RX DATLAT : PASS
2108 10:51:57.855858 RX DQ/DQS(Engine): PASS
2109 10:51:57.859241 TX OE : NO K
2110 10:51:57.859759 All Pass.
2111 10:51:57.860231
2112 10:51:57.862331 CH 0, Rank 1
2113 10:51:57.862792 SW Impedance : PASS
2114 10:51:57.865380 DUTY Scan : NO K
2115 10:51:57.868427 ZQ Calibration : PASS
2116 10:51:57.868902 Jitter Meter : NO K
2117 10:51:57.871931 CBT Training : PASS
2118 10:51:57.875079 Write leveling : PASS
2119 10:51:57.875648 RX DQS gating : PASS
2120 10:51:57.878676 RX DQ/DQS(RDDQC) : PASS
2121 10:51:57.882311 TX DQ/DQS : PASS
2122 10:51:57.882755 RX DATLAT : PASS
2123 10:51:57.885560 RX DQ/DQS(Engine): PASS
2124 10:51:57.888645 TX OE : NO K
2125 10:51:57.889067 All Pass.
2126 10:51:57.889396
2127 10:51:57.889808 CH 1, Rank 0
2128 10:51:57.892329 SW Impedance : PASS
2129 10:51:57.895357 DUTY Scan : NO K
2130 10:51:57.895803 ZQ Calibration : PASS
2131 10:51:57.898817 Jitter Meter : NO K
2132 10:51:57.899356 CBT Training : PASS
2133 10:51:57.902303 Write leveling : PASS
2134 10:51:57.905716 RX DQS gating : PASS
2135 10:51:57.906145 RX DQ/DQS(RDDQC) : PASS
2136 10:51:57.908730 TX DQ/DQS : PASS
2137 10:51:57.912575 RX DATLAT : PASS
2138 10:51:57.913061 RX DQ/DQS(Engine): PASS
2139 10:51:57.915576 TX OE : NO K
2140 10:51:57.916004 All Pass.
2141 10:51:57.916415
2142 10:51:57.918701 CH 1, Rank 1
2143 10:51:57.919186 SW Impedance : PASS
2144 10:51:57.922361 DUTY Scan : NO K
2145 10:51:57.925615 ZQ Calibration : PASS
2146 10:51:57.926076 Jitter Meter : NO K
2147 10:51:57.928785 CBT Training : PASS
2148 10:51:57.932475 Write leveling : PASS
2149 10:51:57.932899 RX DQS gating : PASS
2150 10:51:57.935617 RX DQ/DQS(RDDQC) : PASS
2151 10:51:57.939166 TX DQ/DQS : PASS
2152 10:51:57.939682 RX DATLAT : PASS
2153 10:51:57.942054 RX DQ/DQS(Engine): PASS
2154 10:51:57.942548 TX OE : NO K
2155 10:51:57.945565 All Pass.
2156 10:51:57.946051
2157 10:51:57.946397 DramC Write-DBI off
2158 10:51:57.948767 PER_BANK_REFRESH: Hybrid Mode
2159 10:51:57.952555 TX_TRACKING: ON
2160 10:51:57.955847 [GetDramInforAfterCalByMRR] Vendor 6.
2161 10:51:57.958956 [GetDramInforAfterCalByMRR] Revision 606.
2162 10:51:57.962062 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 10:51:57.962563 MR0 0x3b3b
2164 10:51:57.962919 MR8 0x5151
2165 10:51:57.968563 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 10:51:57.969061
2167 10:51:57.969446 MR0 0x3b3b
2168 10:51:57.969772 MR8 0x5151
2169 10:51:57.972100 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 10:51:57.972597
2171 10:51:57.982118 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 10:51:57.985445 [FAST_K] Save calibration result to emmc
2173 10:51:57.989031 [FAST_K] Save calibration result to emmc
2174 10:51:57.992547 dram_init: config_dvfs: 1
2175 10:51:57.995721 dramc_set_vcore_voltage set vcore to 662500
2176 10:51:57.998766 Read voltage for 1200, 2
2177 10:51:57.999186 Vio18 = 0
2178 10:51:57.999569 Vcore = 662500
2179 10:51:58.002230 Vdram = 0
2180 10:51:58.002676 Vddq = 0
2181 10:51:58.003129 Vmddr = 0
2182 10:51:58.009281 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 10:51:58.012151 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 10:51:58.015624 MEM_TYPE=3, freq_sel=15
2185 10:51:58.019311 sv_algorithm_assistance_LP4_1600
2186 10:51:58.022349 ============ PULL DRAM RESETB DOWN ============
2187 10:51:58.025495 ========== PULL DRAM RESETB DOWN end =========
2188 10:51:58.032520 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 10:51:58.035582 ===================================
2190 10:51:58.036053 LPDDR4 DRAM CONFIGURATION
2191 10:51:58.039400 ===================================
2192 10:51:58.042535 EX_ROW_EN[0] = 0x0
2193 10:51:58.045637 EX_ROW_EN[1] = 0x0
2194 10:51:58.046108 LP4Y_EN = 0x0
2195 10:51:58.049179 WORK_FSP = 0x0
2196 10:51:58.049660 WL = 0x4
2197 10:51:58.052713 RL = 0x4
2198 10:51:58.053290 BL = 0x2
2199 10:51:58.055888 RPST = 0x0
2200 10:51:58.056393 RD_PRE = 0x0
2201 10:51:58.059032 WR_PRE = 0x1
2202 10:51:58.059484 WR_PST = 0x0
2203 10:51:58.062268 DBI_WR = 0x0
2204 10:51:58.062681 DBI_RD = 0x0
2205 10:51:58.066147 OTF = 0x1
2206 10:51:58.069426 ===================================
2207 10:51:58.072384 ===================================
2208 10:51:58.072903 ANA top config
2209 10:51:58.076133 ===================================
2210 10:51:58.079176 DLL_ASYNC_EN = 0
2211 10:51:58.082868 ALL_SLAVE_EN = 0
2212 10:51:58.083285 NEW_RANK_MODE = 1
2213 10:51:58.086219 DLL_IDLE_MODE = 1
2214 10:51:58.089241 LP45_APHY_COMB_EN = 1
2215 10:51:58.092897 TX_ODT_DIS = 1
2216 10:51:58.096143 NEW_8X_MODE = 1
2217 10:51:58.099115 ===================================
2218 10:51:58.102635 ===================================
2219 10:51:58.103057 data_rate = 2400
2220 10:51:58.105821 CKR = 1
2221 10:51:58.109327 DQ_P2S_RATIO = 8
2222 10:51:58.112639 ===================================
2223 10:51:58.116057 CA_P2S_RATIO = 8
2224 10:51:58.119567 DQ_CA_OPEN = 0
2225 10:51:58.123230 DQ_SEMI_OPEN = 0
2226 10:51:58.123838 CA_SEMI_OPEN = 0
2227 10:51:58.126118 CA_FULL_RATE = 0
2228 10:51:58.129217 DQ_CKDIV4_EN = 0
2229 10:51:58.132614 CA_CKDIV4_EN = 0
2230 10:51:58.136304 CA_PREDIV_EN = 0
2231 10:51:58.136904 PH8_DLY = 17
2232 10:51:58.139430 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 10:51:58.142705 DQ_AAMCK_DIV = 4
2234 10:51:58.146503 CA_AAMCK_DIV = 4
2235 10:51:58.149593 CA_ADMCK_DIV = 4
2236 10:51:58.152775 DQ_TRACK_CA_EN = 0
2237 10:51:58.156308 CA_PICK = 1200
2238 10:51:58.156791 CA_MCKIO = 1200
2239 10:51:58.159518 MCKIO_SEMI = 0
2240 10:51:58.162704 PLL_FREQ = 2366
2241 10:51:58.166447 DQ_UI_PI_RATIO = 32
2242 10:51:58.169530 CA_UI_PI_RATIO = 0
2243 10:51:58.172848 ===================================
2244 10:51:58.176672 ===================================
2245 10:51:58.179747 memory_type:LPDDR4
2246 10:51:58.180191 GP_NUM : 10
2247 10:51:58.182785 SRAM_EN : 1
2248 10:51:58.183321 MD32_EN : 0
2249 10:51:58.186347 ===================================
2250 10:51:58.189478 [ANA_INIT] >>>>>>>>>>>>>>
2251 10:51:58.192795 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 10:51:58.196467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 10:51:58.199701 ===================================
2254 10:51:58.202703 data_rate = 2400,PCW = 0X5b00
2255 10:51:58.206289 ===================================
2256 10:51:58.209463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 10:51:58.213045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 10:51:58.220007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 10:51:58.223003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 10:51:58.226379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 10:51:58.229907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 10:51:58.232913 [ANA_INIT] flow start
2263 10:51:58.236631 [ANA_INIT] PLL >>>>>>>>
2264 10:51:58.237080 [ANA_INIT] PLL <<<<<<<<
2265 10:51:58.240133 [ANA_INIT] MIDPI >>>>>>>>
2266 10:51:58.243092 [ANA_INIT] MIDPI <<<<<<<<
2267 10:51:58.246273 [ANA_INIT] DLL >>>>>>>>
2268 10:51:58.246711 [ANA_INIT] DLL <<<<<<<<
2269 10:51:58.249888 [ANA_INIT] flow end
2270 10:51:58.253022 ============ LP4 DIFF to SE enter ============
2271 10:51:58.256275 ============ LP4 DIFF to SE exit ============
2272 10:51:58.260072 [ANA_INIT] <<<<<<<<<<<<<
2273 10:51:58.263036 [Flow] Enable top DCM control >>>>>
2274 10:51:58.266435 [Flow] Enable top DCM control <<<<<
2275 10:51:58.269740 Enable DLL master slave shuffle
2276 10:51:58.273191 ==============================================================
2277 10:51:58.276271 Gating Mode config
2278 10:51:58.283298 ==============================================================
2279 10:51:58.283785 Config description:
2280 10:51:58.292964 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 10:51:58.299849 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 10:51:58.306347 SELPH_MODE 0: By rank 1: By Phase
2283 10:51:58.310053 ==============================================================
2284 10:51:58.312982 GAT_TRACK_EN = 1
2285 10:51:58.316726 RX_GATING_MODE = 2
2286 10:51:58.319743 RX_GATING_TRACK_MODE = 2
2287 10:51:58.322759 SELPH_MODE = 1
2288 10:51:58.326152 PICG_EARLY_EN = 1
2289 10:51:58.329822 VALID_LAT_VALUE = 1
2290 10:51:58.333211 ==============================================================
2291 10:51:58.336657 Enter into Gating configuration >>>>
2292 10:51:58.339426 Exit from Gating configuration <<<<
2293 10:51:58.343271 Enter into DVFS_PRE_config >>>>>
2294 10:51:58.356686 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 10:51:58.357122 Exit from DVFS_PRE_config <<<<<
2296 10:51:58.359876 Enter into PICG configuration >>>>
2297 10:51:58.363034 Exit from PICG configuration <<<<
2298 10:51:58.366259 [RX_INPUT] configuration >>>>>
2299 10:51:58.369982 [RX_INPUT] configuration <<<<<
2300 10:51:58.376516 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 10:51:58.379546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 10:51:58.386780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 10:51:58.393750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 10:51:58.399938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 10:51:58.406367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 10:51:58.409998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 10:51:58.413330 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 10:51:58.416366 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 10:51:58.423040 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 10:51:58.426721 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 10:51:58.429738 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 10:51:58.433340 ===================================
2313 10:51:58.436730 LPDDR4 DRAM CONFIGURATION
2314 10:51:58.439787 ===================================
2315 10:51:58.440249 EX_ROW_EN[0] = 0x0
2316 10:51:58.443435 EX_ROW_EN[1] = 0x0
2317 10:51:58.443864 LP4Y_EN = 0x0
2318 10:51:58.446607 WORK_FSP = 0x0
2319 10:51:58.447054 WL = 0x4
2320 10:51:58.450382 RL = 0x4
2321 10:51:58.450896 BL = 0x2
2322 10:51:58.453282 RPST = 0x0
2323 10:51:58.453709 RD_PRE = 0x0
2324 10:51:58.456803 WR_PRE = 0x1
2325 10:51:58.459897 WR_PST = 0x0
2326 10:51:58.460345 DBI_WR = 0x0
2327 10:51:58.463488 DBI_RD = 0x0
2328 10:51:58.463915 OTF = 0x1
2329 10:51:58.466773 ===================================
2330 10:51:58.470402 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 10:51:58.473621 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 10:51:58.480404 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 10:51:58.483432 ===================================
2334 10:51:58.484000 LPDDR4 DRAM CONFIGURATION
2335 10:51:58.487158 ===================================
2336 10:51:58.490050 EX_ROW_EN[0] = 0x10
2337 10:51:58.493257 EX_ROW_EN[1] = 0x0
2338 10:51:58.493710 LP4Y_EN = 0x0
2339 10:51:58.497022 WORK_FSP = 0x0
2340 10:51:58.497480 WL = 0x4
2341 10:51:58.500119 RL = 0x4
2342 10:51:58.500559 BL = 0x2
2343 10:51:58.503715 RPST = 0x0
2344 10:51:58.504150 RD_PRE = 0x0
2345 10:51:58.506794 WR_PRE = 0x1
2346 10:51:58.507295 WR_PST = 0x0
2347 10:51:58.510141 DBI_WR = 0x0
2348 10:51:58.510666 DBI_RD = 0x0
2349 10:51:58.513300 OTF = 0x1
2350 10:51:58.516478 ===================================
2351 10:51:58.523382 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 10:51:58.523865 ==
2353 10:51:58.526941 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 10:51:58.529935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 10:51:58.530538 ==
2356 10:51:58.533558 [Duty_Offset_Calibration]
2357 10:51:58.533989 B0:2 B1:1 CA:1
2358 10:51:58.534504
2359 10:51:58.536631 [DutyScan_Calibration_Flow] k_type=0
2360 10:51:58.547390
2361 10:51:58.547866 ==CLK 0==
2362 10:51:58.550903 Final CLK duty delay cell = 0
2363 10:51:58.554267 [0] MAX Duty = 5187%(X100), DQS PI = 24
2364 10:51:58.557209 [0] MIN Duty = 4844%(X100), DQS PI = 48
2365 10:51:58.557626 [0] AVG Duty = 5015%(X100)
2366 10:51:58.560407
2367 10:51:58.560966 CH0 CLK Duty spec in!! Max-Min= 343%
2368 10:51:58.567525 [DutyScan_Calibration_Flow] ====Done====
2369 10:51:58.567944
2370 10:51:58.570612 [DutyScan_Calibration_Flow] k_type=1
2371 10:51:58.584660
2372 10:51:58.585096 ==DQS 0 ==
2373 10:51:58.588328 Final DQS duty delay cell = -4
2374 10:51:58.591518 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2375 10:51:58.595187 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2376 10:51:58.598111 [-4] AVG Duty = 4969%(X100)
2377 10:51:58.598666
2378 10:51:58.599188 ==DQS 1 ==
2379 10:51:58.601765 Final DQS duty delay cell = -4
2380 10:51:58.605393 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2381 10:51:58.608485 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2382 10:51:58.611626 [-4] AVG Duty = 4922%(X100)
2383 10:51:58.612045
2384 10:51:58.614801 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2385 10:51:58.615258
2386 10:51:58.618617 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2387 10:51:58.621745 [DutyScan_Calibration_Flow] ====Done====
2388 10:51:58.622184
2389 10:51:58.624812 [DutyScan_Calibration_Flow] k_type=3
2390 10:51:58.642037
2391 10:51:58.642552 ==DQM 0 ==
2392 10:51:58.645707 Final DQM duty delay cell = 0
2393 10:51:58.648836 [0] MAX Duty = 5156%(X100), DQS PI = 28
2394 10:51:58.651951 [0] MIN Duty = 4907%(X100), DQS PI = 58
2395 10:51:58.655312 [0] AVG Duty = 5031%(X100)
2396 10:51:58.655790
2397 10:51:58.656145 ==DQM 1 ==
2398 10:51:58.658903 Final DQM duty delay cell = 0
2399 10:51:58.662256 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 10:51:58.665242 [0] MIN Duty = 5031%(X100), DQS PI = 18
2401 10:51:58.665665 [0] AVG Duty = 5062%(X100)
2402 10:51:58.668895
2403 10:51:58.671837 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2404 10:51:58.672295
2405 10:51:58.675563 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2406 10:51:58.678823 [DutyScan_Calibration_Flow] ====Done====
2407 10:51:58.679369
2408 10:51:58.681957 [DutyScan_Calibration_Flow] k_type=2
2409 10:51:58.698481
2410 10:51:58.699024 ==DQ 0 ==
2411 10:51:58.702107 Final DQ duty delay cell = 0
2412 10:51:58.704924 [0] MAX Duty = 5062%(X100), DQS PI = 30
2413 10:51:58.709087 [0] MIN Duty = 4906%(X100), DQS PI = 0
2414 10:51:58.709504 [0] AVG Duty = 4984%(X100)
2415 10:51:58.709868
2416 10:51:58.711942 ==DQ 1 ==
2417 10:51:58.715280 Final DQ duty delay cell = 0
2418 10:51:58.719081 [0] MAX Duty = 5093%(X100), DQS PI = 24
2419 10:51:58.722280 [0] MIN Duty = 4938%(X100), DQS PI = 36
2420 10:51:58.722700 [0] AVG Duty = 5015%(X100)
2421 10:51:58.723067
2422 10:51:58.725351 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2423 10:51:58.725794
2424 10:51:58.729118 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2425 10:51:58.735399 [DutyScan_Calibration_Flow] ====Done====
2426 10:51:58.735859 ==
2427 10:51:58.738484 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 10:51:58.742261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 10:51:58.742702 ==
2430 10:51:58.745116 [Duty_Offset_Calibration]
2431 10:51:58.745553 B0:1 B1:0 CA:0
2432 10:51:58.745882
2433 10:51:58.748808 [DutyScan_Calibration_Flow] k_type=0
2434 10:51:58.758111
2435 10:51:58.758526 ==CLK 0==
2436 10:51:58.760942 Final CLK duty delay cell = -4
2437 10:51:58.764207 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2438 10:51:58.767833 [-4] MIN Duty = 4907%(X100), DQS PI = 14
2439 10:51:58.771428 [-4] AVG Duty = 4969%(X100)
2440 10:51:58.771846
2441 10:51:58.774270 CH1 CLK Duty spec in!! Max-Min= 124%
2442 10:51:58.777980 [DutyScan_Calibration_Flow] ====Done====
2443 10:51:58.778429
2444 10:51:58.780986 [DutyScan_Calibration_Flow] k_type=1
2445 10:51:58.797907
2446 10:51:58.798572 ==DQS 0 ==
2447 10:51:58.800944 Final DQS duty delay cell = 0
2448 10:51:58.804017 [0] MAX Duty = 5094%(X100), DQS PI = 26
2449 10:51:58.807868 [0] MIN Duty = 4875%(X100), DQS PI = 0
2450 10:51:58.808314 [0] AVG Duty = 4984%(X100)
2451 10:51:58.810633
2452 10:51:58.811083 ==DQS 1 ==
2453 10:51:58.814244 Final DQS duty delay cell = 0
2454 10:51:58.817283 [0] MAX Duty = 5187%(X100), DQS PI = 18
2455 10:51:58.821066 [0] MIN Duty = 4969%(X100), DQS PI = 8
2456 10:51:58.821517 [0] AVG Duty = 5078%(X100)
2457 10:51:58.821860
2458 10:51:58.827353 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2459 10:51:58.827868
2460 10:51:58.831177 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 10:51:58.834280 [DutyScan_Calibration_Flow] ====Done====
2462 10:51:58.834707
2463 10:51:58.837502 [DutyScan_Calibration_Flow] k_type=3
2464 10:51:58.853741
2465 10:51:58.854228 ==DQM 0 ==
2466 10:51:58.857100 Final DQM duty delay cell = 0
2467 10:51:58.860944 [0] MAX Duty = 5156%(X100), DQS PI = 6
2468 10:51:58.864155 [0] MIN Duty = 5031%(X100), DQS PI = 0
2469 10:51:58.864576 [0] AVG Duty = 5093%(X100)
2470 10:51:58.867038
2471 10:51:58.867488 ==DQM 1 ==
2472 10:51:58.870533 Final DQM duty delay cell = 0
2473 10:51:58.874078 [0] MAX Duty = 5031%(X100), DQS PI = 16
2474 10:51:58.877484 [0] MIN Duty = 4907%(X100), DQS PI = 36
2475 10:51:58.877905 [0] AVG Duty = 4969%(X100)
2476 10:51:58.880903
2477 10:51:58.883741 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 10:51:58.884159
2479 10:51:58.887240 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 10:51:58.890417 [DutyScan_Calibration_Flow] ====Done====
2481 10:51:58.890837
2482 10:51:58.894072 [DutyScan_Calibration_Flow] k_type=2
2483 10:51:58.909605
2484 10:51:58.910021 ==DQ 0 ==
2485 10:51:58.912881 Final DQ duty delay cell = -4
2486 10:51:58.916592 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2487 10:51:58.919663 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2488 10:51:58.920084 [-4] AVG Duty = 5000%(X100)
2489 10:51:58.923016
2490 10:51:58.923457 ==DQ 1 ==
2491 10:51:58.926721 Final DQ duty delay cell = 0
2492 10:51:58.929765 [0] MAX Duty = 5125%(X100), DQS PI = 20
2493 10:51:58.933018 [0] MIN Duty = 4969%(X100), DQS PI = 12
2494 10:51:58.933436 [0] AVG Duty = 5047%(X100)
2495 10:51:58.933783
2496 10:51:58.936793 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 10:51:58.939829
2498 10:51:58.942909 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 10:51:58.946699 [DutyScan_Calibration_Flow] ====Done====
2500 10:51:58.949771 nWR fixed to 30
2501 10:51:58.950191 [ModeRegInit_LP4] CH0 RK0
2502 10:51:58.953043 [ModeRegInit_LP4] CH0 RK1
2503 10:51:58.956776 [ModeRegInit_LP4] CH1 RK0
2504 10:51:58.957193 [ModeRegInit_LP4] CH1 RK1
2505 10:51:58.960082 match AC timing 7
2506 10:51:58.963056 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 10:51:58.966460 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 10:51:58.973264 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 10:51:58.976333 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 10:51:58.983181 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 10:51:58.983678 ==
2512 10:51:58.986508 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 10:51:58.989621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 10:51:58.990110 ==
2515 10:51:58.996693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 10:51:58.999773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 10:51:59.010078 [CA 0] Center 39 (8~70) winsize 63
2518 10:51:59.013274 [CA 1] Center 39 (9~70) winsize 62
2519 10:51:59.016410 [CA 2] Center 35 (5~66) winsize 62
2520 10:51:59.019740 [CA 3] Center 34 (4~65) winsize 62
2521 10:51:59.023493 [CA 4] Center 33 (3~64) winsize 62
2522 10:51:59.026553 [CA 5] Center 32 (3~62) winsize 60
2523 10:51:59.026976
2524 10:51:59.030014 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 10:51:59.030493
2526 10:51:59.033359 [CATrainingPosCal] consider 1 rank data
2527 10:51:59.036378 u2DelayCellTimex100 = 270/100 ps
2528 10:51:59.040004 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2529 10:51:59.043125 CA1 delay=39 (9~70),Diff = 7 PI (33 cell)
2530 10:51:59.050039 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2531 10:51:59.053215 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2532 10:51:59.056290 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2533 10:51:59.060064 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2534 10:51:59.060488
2535 10:51:59.063086 CA PerBit enable=1, Macro0, CA PI delay=32
2536 10:51:59.063544
2537 10:51:59.066359 [CBTSetCACLKResult] CA Dly = 32
2538 10:51:59.066821 CS Dly: 6 (0~37)
2539 10:51:59.067156 ==
2540 10:51:59.070044 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 10:51:59.076516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 10:51:59.076939 ==
2543 10:51:59.079677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 10:51:59.086291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 10:51:59.095382 [CA 0] Center 38 (8~69) winsize 62
2546 10:51:59.098732 [CA 1] Center 38 (8~69) winsize 62
2547 10:51:59.102071 [CA 2] Center 35 (5~66) winsize 62
2548 10:51:59.105590 [CA 3] Center 34 (4~65) winsize 62
2549 10:51:59.108779 [CA 4] Center 33 (3~64) winsize 62
2550 10:51:59.112174 [CA 5] Center 32 (3~62) winsize 60
2551 10:51:59.112605
2552 10:51:59.115946 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 10:51:59.116539
2554 10:51:59.119112 [CATrainingPosCal] consider 2 rank data
2555 10:51:59.122306 u2DelayCellTimex100 = 270/100 ps
2556 10:51:59.125447 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2557 10:51:59.129336 CA1 delay=39 (9~69),Diff = 7 PI (33 cell)
2558 10:51:59.135435 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2559 10:51:59.139183 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2560 10:51:59.142577 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2561 10:51:59.145911 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2562 10:51:59.146358
2563 10:51:59.149051 CA PerBit enable=1, Macro0, CA PI delay=32
2564 10:51:59.149483
2565 10:51:59.152895 [CBTSetCACLKResult] CA Dly = 32
2566 10:51:59.153457 CS Dly: 6 (0~38)
2567 10:51:59.153845
2568 10:51:59.156073 ----->DramcWriteLeveling(PI) begin...
2569 10:51:59.156531 ==
2570 10:51:59.159269 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 10:51:59.166225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 10:51:59.166687 ==
2573 10:51:59.169430 Write leveling (Byte 0): 32 => 32
2574 10:51:59.172490 Write leveling (Byte 1): 29 => 29
2575 10:51:59.172944 DramcWriteLeveling(PI) end<-----
2576 10:51:59.173283
2577 10:51:59.175518 ==
2578 10:51:59.179317 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 10:51:59.182696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 10:51:59.183121 ==
2581 10:51:59.185771 [Gating] SW mode calibration
2582 10:51:59.192564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 10:51:59.196150 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 10:51:59.202224 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2585 10:51:59.205791 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2586 10:51:59.209042 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 10:51:59.216127 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 10:51:59.218974 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 10:51:59.222876 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 10:51:59.229253 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2591 10:51:59.232961 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2592 10:51:59.236131 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
2593 10:51:59.242727 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 10:51:59.245796 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 10:51:59.249426 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 10:51:59.252414 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 10:51:59.259106 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 10:51:59.262818 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2599 10:51:59.265849 1 0 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2600 10:51:59.272787 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2601 10:51:59.275955 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 10:51:59.279089 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 10:51:59.285983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 10:51:59.289401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 10:51:59.292427 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 10:51:59.299276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 10:51:59.302538 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 10:51:59.305952 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 10:51:59.312403 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:51:59.315965 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:51:59.319287 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:51:59.325643 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:51:59.329161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:51:59.332320 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:51:59.339182 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:51:59.342310 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:51:59.345956 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:51:59.349446 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:51:59.355725 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:51:59.359406 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:51:59.362745 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 10:51:59.369578 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 10:51:59.372663 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2624 10:51:59.375897 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 10:51:59.379082 Total UI for P1: 0, mck2ui 16
2626 10:51:59.382790 best dqsien dly found for B0: ( 1, 3, 26)
2627 10:51:59.389122 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 10:51:59.389520 Total UI for P1: 0, mck2ui 16
2629 10:51:59.395785 best dqsien dly found for B1: ( 1, 3, 30)
2630 10:51:59.399423 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 10:51:59.402685 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2632 10:51:59.403106
2633 10:51:59.405773 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 10:51:59.409497 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2635 10:51:59.412373 [Gating] SW calibration Done
2636 10:51:59.412878 ==
2637 10:51:59.416136 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 10:51:59.419121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 10:51:59.419566 ==
2640 10:51:59.422652 RX Vref Scan: 0
2641 10:51:59.423103
2642 10:51:59.423489 RX Vref 0 -> 0, step: 1
2643 10:51:59.423861
2644 10:51:59.426286 RX Delay -40 -> 252, step: 8
2645 10:51:59.429075 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2646 10:51:59.436246 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2647 10:51:59.439385 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 10:51:59.442657 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2649 10:51:59.446325 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 10:51:59.449373 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2651 10:51:59.452708 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 10:51:59.459687 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 10:51:59.462639 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2654 10:51:59.466019 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2655 10:51:59.469444 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2656 10:51:59.473019 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2657 10:51:59.479903 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2658 10:51:59.483002 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2659 10:51:59.486143 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2660 10:51:59.489872 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2661 10:51:59.490243 ==
2662 10:51:59.492972 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 10:51:59.499957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 10:51:59.500355 ==
2665 10:51:59.500766 DQS Delay:
2666 10:51:59.501080 DQS0 = 0, DQS1 = 0
2667 10:51:59.503424 DQM Delay:
2668 10:51:59.503780 DQM0 = 121, DQM1 = 113
2669 10:51:59.506729 DQ Delay:
2670 10:51:59.509720 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2671 10:51:59.513369 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2672 10:51:59.516842 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2673 10:51:59.519896 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2674 10:51:59.520327
2675 10:51:59.520683
2676 10:51:59.520993 ==
2677 10:51:59.523693 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 10:51:59.526689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 10:51:59.527139 ==
2680 10:51:59.527556
2681 10:51:59.527882
2682 10:51:59.530039 TX Vref Scan disable
2683 10:51:59.533055 == TX Byte 0 ==
2684 10:51:59.536592 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2685 10:51:59.540115 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2686 10:51:59.543690 == TX Byte 1 ==
2687 10:51:59.546927 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2688 10:51:59.550074 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2689 10:51:59.550632 ==
2690 10:51:59.553113 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 10:51:59.560124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 10:51:59.560678 ==
2693 10:51:59.570820 TX Vref=22, minBit 0, minWin=25, winSum=412
2694 10:51:59.573873 TX Vref=24, minBit 0, minWin=25, winSum=418
2695 10:51:59.576830 TX Vref=26, minBit 7, minWin=25, winSum=423
2696 10:51:59.580342 TX Vref=28, minBit 4, minWin=26, winSum=429
2697 10:51:59.584042 TX Vref=30, minBit 0, minWin=26, winSum=429
2698 10:51:59.587245 TX Vref=32, minBit 12, minWin=25, winSum=422
2699 10:51:59.594124 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
2700 10:51:59.594556
2701 10:51:59.597175 Final TX Range 1 Vref 28
2702 10:51:59.597724
2703 10:51:59.598190 ==
2704 10:51:59.601103 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 10:51:59.603702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 10:51:59.604242 ==
2707 10:51:59.604705
2708 10:51:59.605036
2709 10:51:59.607302 TX Vref Scan disable
2710 10:51:59.610478 == TX Byte 0 ==
2711 10:51:59.614047 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2712 10:51:59.617161 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2713 10:51:59.620793 == TX Byte 1 ==
2714 10:51:59.624306 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2715 10:51:59.627379 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2716 10:51:59.627809
2717 10:51:59.630633 [DATLAT]
2718 10:51:59.631053 Freq=1200, CH0 RK0
2719 10:51:59.631432
2720 10:51:59.634265 DATLAT Default: 0xd
2721 10:51:59.634685 0, 0xFFFF, sum = 0
2722 10:51:59.637761 1, 0xFFFF, sum = 0
2723 10:51:59.638188 2, 0xFFFF, sum = 0
2724 10:51:59.640842 3, 0xFFFF, sum = 0
2725 10:51:59.641333 4, 0xFFFF, sum = 0
2726 10:51:59.644387 5, 0xFFFF, sum = 0
2727 10:51:59.644813 6, 0xFFFF, sum = 0
2728 10:51:59.647754 7, 0xFFFF, sum = 0
2729 10:51:59.648205 8, 0xFFFF, sum = 0
2730 10:51:59.650771 9, 0xFFFF, sum = 0
2731 10:51:59.651201 10, 0xFFFF, sum = 0
2732 10:51:59.654524 11, 0xFFFF, sum = 0
2733 10:51:59.654953 12, 0x0, sum = 1
2734 10:51:59.657622 13, 0x0, sum = 2
2735 10:51:59.658050 14, 0x0, sum = 3
2736 10:51:59.661215 15, 0x0, sum = 4
2737 10:51:59.661664 best_step = 13
2738 10:51:59.662002
2739 10:51:59.662313 ==
2740 10:51:59.664242 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 10:51:59.667926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 10:51:59.671093 ==
2743 10:51:59.671565 RX Vref Scan: 1
2744 10:51:59.672085
2745 10:51:59.674783 Set Vref Range= 32 -> 127
2746 10:51:59.675203
2747 10:51:59.677784 RX Vref 32 -> 127, step: 1
2748 10:51:59.678203
2749 10:51:59.678536 RX Delay -13 -> 252, step: 4
2750 10:51:59.678849
2751 10:51:59.681049 Set Vref, RX VrefLevel [Byte0]: 32
2752 10:51:59.684578 [Byte1]: 32
2753 10:51:59.688709
2754 10:51:59.689130 Set Vref, RX VrefLevel [Byte0]: 33
2755 10:51:59.692445 [Byte1]: 33
2756 10:51:59.696768
2757 10:51:59.697188 Set Vref, RX VrefLevel [Byte0]: 34
2758 10:51:59.699849 [Byte1]: 34
2759 10:51:59.704465
2760 10:51:59.704985 Set Vref, RX VrefLevel [Byte0]: 35
2761 10:51:59.707649 [Byte1]: 35
2762 10:51:59.712799
2763 10:51:59.713246 Set Vref, RX VrefLevel [Byte0]: 36
2764 10:51:59.715863 [Byte1]: 36
2765 10:51:59.720039
2766 10:51:59.720548 Set Vref, RX VrefLevel [Byte0]: 37
2767 10:51:59.723500 [Byte1]: 37
2768 10:51:59.727860
2769 10:51:59.728308 Set Vref, RX VrefLevel [Byte0]: 38
2770 10:51:59.731375 [Byte1]: 38
2771 10:51:59.735857
2772 10:51:59.736327 Set Vref, RX VrefLevel [Byte0]: 39
2773 10:51:59.738994 [Byte1]: 39
2774 10:51:59.743688
2775 10:51:59.744261 Set Vref, RX VrefLevel [Byte0]: 40
2776 10:51:59.747078 [Byte1]: 40
2777 10:51:59.752040
2778 10:51:59.752456 Set Vref, RX VrefLevel [Byte0]: 41
2779 10:51:59.754818 [Byte1]: 41
2780 10:51:59.759482
2781 10:51:59.759955 Set Vref, RX VrefLevel [Byte0]: 42
2782 10:51:59.763172 [Byte1]: 42
2783 10:51:59.767446
2784 10:51:59.767862 Set Vref, RX VrefLevel [Byte0]: 43
2785 10:51:59.771054 [Byte1]: 43
2786 10:51:59.775319
2787 10:51:59.775772 Set Vref, RX VrefLevel [Byte0]: 44
2788 10:51:59.778507 [Byte1]: 44
2789 10:51:59.783637
2790 10:51:59.784057 Set Vref, RX VrefLevel [Byte0]: 45
2791 10:51:59.786550 [Byte1]: 45
2792 10:51:59.790938
2793 10:51:59.791379 Set Vref, RX VrefLevel [Byte0]: 46
2794 10:51:59.794573 [Byte1]: 46
2795 10:51:59.799291
2796 10:51:59.799751 Set Vref, RX VrefLevel [Byte0]: 47
2797 10:51:59.802539 [Byte1]: 47
2798 10:51:59.806982
2799 10:51:59.807435 Set Vref, RX VrefLevel [Byte0]: 48
2800 10:51:59.810243 [Byte1]: 48
2801 10:51:59.814618
2802 10:51:59.815041 Set Vref, RX VrefLevel [Byte0]: 49
2803 10:51:59.818434 [Byte1]: 49
2804 10:51:59.822760
2805 10:51:59.823242 Set Vref, RX VrefLevel [Byte0]: 50
2806 10:51:59.826023 [Byte1]: 50
2807 10:51:59.830558
2808 10:51:59.830978 Set Vref, RX VrefLevel [Byte0]: 51
2809 10:51:59.834074 [Byte1]: 51
2810 10:51:59.838927
2811 10:51:59.839380 Set Vref, RX VrefLevel [Byte0]: 52
2812 10:51:59.842100 [Byte1]: 52
2813 10:51:59.846658
2814 10:51:59.847077 Set Vref, RX VrefLevel [Byte0]: 53
2815 10:51:59.850337 [Byte1]: 53
2816 10:51:59.854129
2817 10:51:59.854559 Set Vref, RX VrefLevel [Byte0]: 54
2818 10:51:59.857708 [Byte1]: 54
2819 10:51:59.862486
2820 10:51:59.862945 Set Vref, RX VrefLevel [Byte0]: 55
2821 10:51:59.865895 [Byte1]: 55
2822 10:51:59.870245
2823 10:51:59.870823 Set Vref, RX VrefLevel [Byte0]: 56
2824 10:51:59.873718 [Byte1]: 56
2825 10:51:59.877864
2826 10:51:59.878284 Set Vref, RX VrefLevel [Byte0]: 57
2827 10:51:59.881018 [Byte1]: 57
2828 10:51:59.886060
2829 10:51:59.886522 Set Vref, RX VrefLevel [Byte0]: 58
2830 10:51:59.889128 [Byte1]: 58
2831 10:51:59.894278
2832 10:51:59.894711 Set Vref, RX VrefLevel [Byte0]: 59
2833 10:51:59.897359 [Byte1]: 59
2834 10:51:59.901640
2835 10:51:59.902060 Set Vref, RX VrefLevel [Byte0]: 60
2836 10:51:59.905245 [Byte1]: 60
2837 10:51:59.909523
2838 10:51:59.909969 Set Vref, RX VrefLevel [Byte0]: 61
2839 10:51:59.912744 [Byte1]: 61
2840 10:51:59.917256
2841 10:51:59.917694 Set Vref, RX VrefLevel [Byte0]: 62
2842 10:51:59.921138 [Byte1]: 62
2843 10:51:59.925454
2844 10:51:59.925901 Set Vref, RX VrefLevel [Byte0]: 63
2845 10:51:59.928657 [Byte1]: 63
2846 10:51:59.933020
2847 10:51:59.933443 Set Vref, RX VrefLevel [Byte0]: 64
2848 10:51:59.936489 [Byte1]: 64
2849 10:51:59.941066
2850 10:51:59.941545 Set Vref, RX VrefLevel [Byte0]: 65
2851 10:51:59.944587 [Byte1]: 65
2852 10:51:59.949059
2853 10:51:59.949499 Set Vref, RX VrefLevel [Byte0]: 66
2854 10:51:59.952162 [Byte1]: 66
2855 10:51:59.957022
2856 10:51:59.957459 Set Vref, RX VrefLevel [Byte0]: 67
2857 10:51:59.959964 [Byte1]: 67
2858 10:51:59.964676
2859 10:51:59.965238 Set Vref, RX VrefLevel [Byte0]: 68
2860 10:51:59.968317 [Byte1]: 68
2861 10:51:59.972923
2862 10:51:59.973511 Final RX Vref Byte 0 = 56 to rank0
2863 10:51:59.975762 Final RX Vref Byte 1 = 49 to rank0
2864 10:51:59.979083 Final RX Vref Byte 0 = 56 to rank1
2865 10:51:59.982738 Final RX Vref Byte 1 = 49 to rank1==
2866 10:51:59.986109 Dram Type= 6, Freq= 0, CH_0, rank 0
2867 10:51:59.992422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 10:51:59.992896 ==
2869 10:51:59.993352 DQS Delay:
2870 10:51:59.993770 DQS0 = 0, DQS1 = 0
2871 10:51:59.996190 DQM Delay:
2872 10:51:59.996630 DQM0 = 120, DQM1 = 112
2873 10:51:59.999287 DQ Delay:
2874 10:52:00.002389 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
2875 10:52:00.006007 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2876 10:52:00.009181 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2877 10:52:00.012856 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2878 10:52:00.013301
2879 10:52:00.013713
2880 10:52:00.019153 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2881 10:52:00.022846 CH0 RK0: MR19=404, MR18=140D
2882 10:52:00.029151 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2883 10:52:00.029594
2884 10:52:00.032963 ----->DramcWriteLeveling(PI) begin...
2885 10:52:00.033394 ==
2886 10:52:00.036215 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 10:52:00.039351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 10:52:00.042384 ==
2889 10:52:00.042835 Write leveling (Byte 0): 34 => 34
2890 10:52:00.045741 Write leveling (Byte 1): 29 => 29
2891 10:52:00.049692 DramcWriteLeveling(PI) end<-----
2892 10:52:00.050081
2893 10:52:00.050470 ==
2894 10:52:00.052746 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 10:52:00.059765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 10:52:00.060219 ==
2897 10:52:00.060558 [Gating] SW mode calibration
2898 10:52:00.069419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2899 10:52:00.072889 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2900 10:52:00.076097 0 15 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
2901 10:52:00.083035 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 10:52:00.086389 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 10:52:00.089255 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 10:52:00.096321 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 10:52:00.099404 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 10:52:00.103138 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 10:52:00.109479 0 15 28 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
2908 10:52:00.113334 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2909 10:52:00.116370 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 10:52:00.123111 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 10:52:00.126197 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 10:52:00.129996 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 10:52:00.136298 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 10:52:00.139427 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
2915 10:52:00.143199 1 0 28 | B1->B0 | 3f3f 4040 | 0 1 | (0 0) (0 0)
2916 10:52:00.149739 1 1 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
2917 10:52:00.152702 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 10:52:00.156076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 10:52:00.159857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 10:52:00.166726 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 10:52:00.169657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 10:52:00.172880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 10:52:00.179780 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2924 10:52:00.183235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2925 10:52:00.186149 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 10:52:00.193088 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 10:52:00.196753 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:52:00.199579 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:52:00.206429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:52:00.209452 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:52:00.213226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:52:00.219576 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:52:00.223173 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 10:52:00.226859 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:52:00.229907 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:52:00.236378 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 10:52:00.240200 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 10:52:00.243195 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 10:52:00.250357 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2940 10:52:00.253403 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 10:52:00.256636 Total UI for P1: 0, mck2ui 16
2942 10:52:00.259703 best dqsien dly found for B0: ( 1, 3, 30)
2943 10:52:00.263381 Total UI for P1: 0, mck2ui 16
2944 10:52:00.266799 best dqsien dly found for B1: ( 1, 3, 28)
2945 10:52:00.269744 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2946 10:52:00.273443 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2947 10:52:00.273873
2948 10:52:00.276472 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2949 10:52:00.280203 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2950 10:52:00.283479 [Gating] SW calibration Done
2951 10:52:00.283908 ==
2952 10:52:00.286697 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 10:52:00.290354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 10:52:00.293320 ==
2955 10:52:00.293784 RX Vref Scan: 0
2956 10:52:00.294133
2957 10:52:00.296733 RX Vref 0 -> 0, step: 1
2958 10:52:00.297160
2959 10:52:00.297556 RX Delay -40 -> 252, step: 8
2960 10:52:00.303357 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2961 10:52:00.306876 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2962 10:52:00.310497 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2963 10:52:00.313718 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2964 10:52:00.317129 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2965 10:52:00.323812 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2966 10:52:00.327023 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2967 10:52:00.330067 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2968 10:52:00.333744 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2969 10:52:00.337351 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2970 10:52:00.343765 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2971 10:52:00.346964 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2972 10:52:00.350257 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2973 10:52:00.353869 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2974 10:52:00.357152 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2975 10:52:00.363973 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2976 10:52:00.364399 ==
2977 10:52:00.367107 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 10:52:00.370607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 10:52:00.371036 ==
2980 10:52:00.371412 DQS Delay:
2981 10:52:00.373667 DQS0 = 0, DQS1 = 0
2982 10:52:00.374088 DQM Delay:
2983 10:52:00.377370 DQM0 = 122, DQM1 = 112
2984 10:52:00.377798 DQ Delay:
2985 10:52:00.380788 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2986 10:52:00.383669 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2987 10:52:00.386967 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2988 10:52:00.390620 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2989 10:52:00.391045
2990 10:52:00.391416
2991 10:52:00.391736 ==
2992 10:52:00.393684 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 10:52:00.400450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 10:52:00.400874 ==
2995 10:52:00.401208
2996 10:52:00.401514
2997 10:52:00.401809 TX Vref Scan disable
2998 10:52:00.404251 == TX Byte 0 ==
2999 10:52:00.407830 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3000 10:52:00.410984 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3001 10:52:00.414433 == TX Byte 1 ==
3002 10:52:00.417524 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3003 10:52:00.421150 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3004 10:52:00.423959 ==
3005 10:52:00.427476 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 10:52:00.430616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 10:52:00.431041 ==
3008 10:52:00.442479 TX Vref=22, minBit 5, minWin=24, winSum=420
3009 10:52:00.445890 TX Vref=24, minBit 3, minWin=25, winSum=423
3010 10:52:00.449121 TX Vref=26, minBit 0, minWin=26, winSum=429
3011 10:52:00.452855 TX Vref=28, minBit 1, minWin=26, winSum=430
3012 10:52:00.456166 TX Vref=30, minBit 1, minWin=26, winSum=433
3013 10:52:00.459186 TX Vref=32, minBit 5, minWin=25, winSum=423
3014 10:52:00.466177 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3015 10:52:00.466603
3016 10:52:00.469421 Final TX Range 1 Vref 30
3017 10:52:00.469845
3018 10:52:00.470175 ==
3019 10:52:00.472347 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 10:52:00.476122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 10:52:00.476550 ==
3022 10:52:00.476881
3023 10:52:00.477196
3024 10:52:00.479223 TX Vref Scan disable
3025 10:52:00.482735 == TX Byte 0 ==
3026 10:52:00.486215 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3027 10:52:00.489409 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3028 10:52:00.492511 == TX Byte 1 ==
3029 10:52:00.496164 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3030 10:52:00.499321 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3031 10:52:00.499772
3032 10:52:00.502455 [DATLAT]
3033 10:52:00.502878 Freq=1200, CH0 RK1
3034 10:52:00.503211
3035 10:52:00.506172 DATLAT Default: 0xd
3036 10:52:00.506595 0, 0xFFFF, sum = 0
3037 10:52:00.509253 1, 0xFFFF, sum = 0
3038 10:52:00.509689 2, 0xFFFF, sum = 0
3039 10:52:00.512842 3, 0xFFFF, sum = 0
3040 10:52:00.513273 4, 0xFFFF, sum = 0
3041 10:52:00.515913 5, 0xFFFF, sum = 0
3042 10:52:00.516340 6, 0xFFFF, sum = 0
3043 10:52:00.518942 7, 0xFFFF, sum = 0
3044 10:52:00.519441 8, 0xFFFF, sum = 0
3045 10:52:00.522609 9, 0xFFFF, sum = 0
3046 10:52:00.525683 10, 0xFFFF, sum = 0
3047 10:52:00.526112 11, 0xFFFF, sum = 0
3048 10:52:00.529184 12, 0x0, sum = 1
3049 10:52:00.529611 13, 0x0, sum = 2
3050 10:52:00.529947 14, 0x0, sum = 3
3051 10:52:00.532772 15, 0x0, sum = 4
3052 10:52:00.533200 best_step = 13
3053 10:52:00.533533
3054 10:52:00.535968 ==
3055 10:52:00.536390 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 10:52:00.542924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 10:52:00.543383 ==
3058 10:52:00.543728 RX Vref Scan: 0
3059 10:52:00.544040
3060 10:52:00.546107 RX Vref 0 -> 0, step: 1
3061 10:52:00.546532
3062 10:52:00.549049 RX Delay -13 -> 252, step: 4
3063 10:52:00.552746 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3064 10:52:00.555687 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3065 10:52:00.562600 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3066 10:52:00.565664 iDelay=195, Bit 3, Center 120 (55 ~ 186) 132
3067 10:52:00.569526 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3068 10:52:00.572795 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3069 10:52:00.575749 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3070 10:52:00.582538 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3071 10:52:00.586178 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3072 10:52:00.589254 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3073 10:52:00.592731 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3074 10:52:00.596404 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3075 10:52:00.602712 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3076 10:52:00.605957 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3077 10:52:00.609705 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3078 10:52:00.612779 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3079 10:52:00.613204 ==
3080 10:52:00.616225 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 10:52:00.619476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 10:52:00.623296 ==
3083 10:52:00.623785 DQS Delay:
3084 10:52:00.624178 DQS0 = 0, DQS1 = 0
3085 10:52:00.626414 DQM Delay:
3086 10:52:00.626853 DQM0 = 121, DQM1 = 110
3087 10:52:00.629439 DQ Delay:
3088 10:52:00.632853 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
3089 10:52:00.636631 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3090 10:52:00.639517 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3091 10:52:00.643144 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3092 10:52:00.643657
3093 10:52:00.643998
3094 10:52:00.649809 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3095 10:52:00.652973 CH0 RK1: MR19=403, MR18=11F2
3096 10:52:00.659804 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3097 10:52:00.662683 [RxdqsGatingPostProcess] freq 1200
3098 10:52:00.669540 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3099 10:52:00.669993 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 10:52:00.673430 best DQS1 dly(2T, 0.5T) = (0, 11)
3101 10:52:00.676431 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 10:52:00.679547 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3103 10:52:00.683286 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 10:52:00.686302 best DQS1 dly(2T, 0.5T) = (0, 11)
3105 10:52:00.689511 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 10:52:00.692550 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3107 10:52:00.696327 Pre-setting of DQS Precalculation
3108 10:52:00.702627 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3109 10:52:00.703080 ==
3110 10:52:00.705830 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 10:52:00.709493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 10:52:00.709936 ==
3113 10:52:00.716320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3114 10:52:00.719394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3115 10:52:00.729110 [CA 0] Center 37 (7~68) winsize 62
3116 10:52:00.732184 [CA 1] Center 37 (7~68) winsize 62
3117 10:52:00.735400 [CA 2] Center 35 (5~65) winsize 61
3118 10:52:00.738925 [CA 3] Center 34 (4~64) winsize 61
3119 10:52:00.742545 [CA 4] Center 34 (4~64) winsize 61
3120 10:52:00.745450 [CA 5] Center 33 (3~63) winsize 61
3121 10:52:00.745880
3122 10:52:00.749068 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3123 10:52:00.749498
3124 10:52:00.752735 [CATrainingPosCal] consider 1 rank data
3125 10:52:00.755617 u2DelayCellTimex100 = 270/100 ps
3126 10:52:00.759535 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3127 10:52:00.762651 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3128 10:52:00.768773 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3129 10:52:00.772587 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3130 10:52:00.775648 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 10:52:00.779000 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3132 10:52:00.779633
3133 10:52:00.781987 CA PerBit enable=1, Macro0, CA PI delay=33
3134 10:52:00.782420
3135 10:52:00.785541 [CBTSetCACLKResult] CA Dly = 33
3136 10:52:00.786000 CS Dly: 7 (0~38)
3137 10:52:00.788589 ==
3138 10:52:00.789025 Dram Type= 6, Freq= 0, CH_1, rank 1
3139 10:52:00.795759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 10:52:00.796220 ==
3141 10:52:00.798757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3142 10:52:00.805548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3143 10:52:00.814384 [CA 0] Center 37 (7~68) winsize 62
3144 10:52:00.818090 [CA 1] Center 38 (8~68) winsize 61
3145 10:52:00.821144 [CA 2] Center 35 (5~66) winsize 62
3146 10:52:00.824817 [CA 3] Center 34 (4~65) winsize 62
3147 10:52:00.827821 [CA 4] Center 34 (4~65) winsize 62
3148 10:52:00.831659 [CA 5] Center 34 (4~64) winsize 61
3149 10:52:00.832104
3150 10:52:00.834682 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3151 10:52:00.835117
3152 10:52:00.837990 [CATrainingPosCal] consider 2 rank data
3153 10:52:00.841702 u2DelayCellTimex100 = 270/100 ps
3154 10:52:00.844931 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3155 10:52:00.847944 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3156 10:52:00.854391 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3157 10:52:00.857957 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 10:52:00.861481 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 10:52:00.864607 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3160 10:52:00.865056
3161 10:52:00.867764 CA PerBit enable=1, Macro0, CA PI delay=33
3162 10:52:00.868203
3163 10:52:00.871346 [CBTSetCACLKResult] CA Dly = 33
3164 10:52:00.871779 CS Dly: 8 (0~40)
3165 10:52:00.872143
3166 10:52:00.875041 ----->DramcWriteLeveling(PI) begin...
3167 10:52:00.877844 ==
3168 10:52:00.878272 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 10:52:00.884903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 10:52:00.885468 ==
3171 10:52:00.887977 Write leveling (Byte 0): 26 => 26
3172 10:52:00.891042 Write leveling (Byte 1): 28 => 28
3173 10:52:00.895026 DramcWriteLeveling(PI) end<-----
3174 10:52:00.895683
3175 10:52:00.896172 ==
3176 10:52:00.898043 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 10:52:00.901308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 10:52:00.901798 ==
3179 10:52:00.905043 [Gating] SW mode calibration
3180 10:52:00.911270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3181 10:52:00.914268 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3182 10:52:00.921249 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3183 10:52:00.924553 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 10:52:00.928341 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 10:52:00.934726 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 10:52:00.938084 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 10:52:00.941227 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 10:52:00.948278 0 15 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
3189 10:52:00.951380 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3190 10:52:00.954438 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 10:52:00.961610 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 10:52:00.964488 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 10:52:00.967921 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 10:52:00.974785 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 10:52:00.977899 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 10:52:00.980964 1 0 24 | B1->B0 | 2c2c 3b3a | 1 1 | (0 0) (0 0)
3197 10:52:00.987860 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 10:52:00.991614 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 10:52:00.994834 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 10:52:00.998253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 10:52:01.004658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 10:52:01.007703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 10:52:01.011629 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 10:52:01.017658 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3205 10:52:01.021562 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3206 10:52:01.024519 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 10:52:01.031592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 10:52:01.034856 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 10:52:01.038170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 10:52:01.044668 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:52:01.048323 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:52:01.051586 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:52:01.058534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:52:01.061532 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:52:01.064658 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:52:01.067968 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:52:01.075015 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:52:01.078006 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 10:52:01.081583 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 10:52:01.087671 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3221 10:52:01.091309 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 10:52:01.094459 Total UI for P1: 0, mck2ui 16
3223 10:52:01.098161 best dqsien dly found for B0: ( 1, 3, 24)
3224 10:52:01.101107 Total UI for P1: 0, mck2ui 16
3225 10:52:01.104810 best dqsien dly found for B1: ( 1, 3, 24)
3226 10:52:01.108083 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3227 10:52:01.110993 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3228 10:52:01.111099
3229 10:52:01.114856 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3230 10:52:01.118006 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3231 10:52:01.121123 [Gating] SW calibration Done
3232 10:52:01.121220 ==
3233 10:52:01.124885 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 10:52:01.128006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 10:52:01.131004 ==
3236 10:52:01.131115 RX Vref Scan: 0
3237 10:52:01.131208
3238 10:52:01.134626 RX Vref 0 -> 0, step: 1
3239 10:52:01.134715
3240 10:52:01.137738 RX Delay -40 -> 252, step: 8
3241 10:52:01.140770 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3242 10:52:01.144459 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3243 10:52:01.147866 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3244 10:52:01.150708 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3245 10:52:01.157955 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3246 10:52:01.160982 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3247 10:52:01.164240 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3248 10:52:01.167990 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3249 10:52:01.171111 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3250 10:52:01.174698 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3251 10:52:01.181283 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3252 10:52:01.184841 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3253 10:52:01.188028 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3254 10:52:01.191154 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3255 10:52:01.197832 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3256 10:52:01.200913 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3257 10:52:01.201006 ==
3258 10:52:01.204510 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 10:52:01.208084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 10:52:01.208172 ==
3261 10:52:01.208239 DQS Delay:
3262 10:52:01.211183 DQS0 = 0, DQS1 = 0
3263 10:52:01.211267 DQM Delay:
3264 10:52:01.214447 DQM0 = 119, DQM1 = 116
3265 10:52:01.214548 DQ Delay:
3266 10:52:01.217681 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3267 10:52:01.221507 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3268 10:52:01.224737 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3269 10:52:01.231483 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3270 10:52:01.231606
3271 10:52:01.231674
3272 10:52:01.231736 ==
3273 10:52:01.234561 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 10:52:01.238264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 10:52:01.238351 ==
3276 10:52:01.238416
3277 10:52:01.238475
3278 10:52:01.241359 TX Vref Scan disable
3279 10:52:01.241442 == TX Byte 0 ==
3280 10:52:01.248044 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3281 10:52:01.251109 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3282 10:52:01.251198 == TX Byte 1 ==
3283 10:52:01.258244 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3284 10:52:01.261282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3285 10:52:01.261404 ==
3286 10:52:01.264792 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 10:52:01.268031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 10:52:01.268161 ==
3289 10:52:01.280374 TX Vref=22, minBit 11, minWin=24, winSum=413
3290 10:52:01.283309 TX Vref=24, minBit 10, minWin=25, winSum=420
3291 10:52:01.286845 TX Vref=26, minBit 10, minWin=25, winSum=423
3292 10:52:01.289834 TX Vref=28, minBit 9, minWin=25, winSum=430
3293 10:52:01.293526 TX Vref=30, minBit 1, minWin=26, winSum=432
3294 10:52:01.300364 TX Vref=32, minBit 2, minWin=26, winSum=429
3295 10:52:01.303437 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3296 10:52:01.303521
3297 10:52:01.307106 Final TX Range 1 Vref 30
3298 10:52:01.307214
3299 10:52:01.307307 ==
3300 10:52:01.310135 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 10:52:01.313572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 10:52:01.316692 ==
3303 10:52:01.316779
3304 10:52:01.316848
3305 10:52:01.316913 TX Vref Scan disable
3306 10:52:01.319925 == TX Byte 0 ==
3307 10:52:01.323562 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3308 10:52:01.326730 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3309 10:52:01.329804 == TX Byte 1 ==
3310 10:52:01.333556 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 10:52:01.336835 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 10:52:01.340015
3313 10:52:01.340122 [DATLAT]
3314 10:52:01.340213 Freq=1200, CH1 RK0
3315 10:52:01.340300
3316 10:52:01.343432 DATLAT Default: 0xd
3317 10:52:01.343594 0, 0xFFFF, sum = 0
3318 10:52:01.346651 1, 0xFFFF, sum = 0
3319 10:52:01.346787 2, 0xFFFF, sum = 0
3320 10:52:01.350438 3, 0xFFFF, sum = 0
3321 10:52:01.350595 4, 0xFFFF, sum = 0
3322 10:52:01.353610 5, 0xFFFF, sum = 0
3323 10:52:01.356748 6, 0xFFFF, sum = 0
3324 10:52:01.356974 7, 0xFFFF, sum = 0
3325 10:52:01.360371 8, 0xFFFF, sum = 0
3326 10:52:01.360579 9, 0xFFFF, sum = 0
3327 10:52:01.363794 10, 0xFFFF, sum = 0
3328 10:52:01.364054 11, 0xFFFF, sum = 0
3329 10:52:01.366821 12, 0x0, sum = 1
3330 10:52:01.367150 13, 0x0, sum = 2
3331 10:52:01.370445 14, 0x0, sum = 3
3332 10:52:01.370823 15, 0x0, sum = 4
3333 10:52:01.371089 best_step = 13
3334 10:52:01.371322
3335 10:52:01.374072 ==
3336 10:52:01.377303 Dram Type= 6, Freq= 0, CH_1, rank 0
3337 10:52:01.380435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3338 10:52:01.380950 ==
3339 10:52:01.381300 RX Vref Scan: 1
3340 10:52:01.381744
3341 10:52:01.384162 Set Vref Range= 32 -> 127
3342 10:52:01.384600
3343 10:52:01.387153 RX Vref 32 -> 127, step: 1
3344 10:52:01.387642
3345 10:52:01.390751 RX Delay -5 -> 252, step: 4
3346 10:52:01.391207
3347 10:52:01.393746 Set Vref, RX VrefLevel [Byte0]: 32
3348 10:52:01.397333 [Byte1]: 32
3349 10:52:01.397780
3350 10:52:01.400420 Set Vref, RX VrefLevel [Byte0]: 33
3351 10:52:01.403663 [Byte1]: 33
3352 10:52:01.404091
3353 10:52:01.407234 Set Vref, RX VrefLevel [Byte0]: 34
3354 10:52:01.410858 [Byte1]: 34
3355 10:52:01.414540
3356 10:52:01.414970 Set Vref, RX VrefLevel [Byte0]: 35
3357 10:52:01.418035 [Byte1]: 35
3358 10:52:01.422410
3359 10:52:01.422850 Set Vref, RX VrefLevel [Byte0]: 36
3360 10:52:01.426068 [Byte1]: 36
3361 10:52:01.429930
3362 10:52:01.430342 Set Vref, RX VrefLevel [Byte0]: 37
3363 10:52:01.433704 [Byte1]: 37
3364 10:52:01.438077
3365 10:52:01.438536 Set Vref, RX VrefLevel [Byte0]: 38
3366 10:52:01.441230 [Byte1]: 38
3367 10:52:01.445669
3368 10:52:01.446111 Set Vref, RX VrefLevel [Byte0]: 39
3369 10:52:01.449229 [Byte1]: 39
3370 10:52:01.453402
3371 10:52:01.453691 Set Vref, RX VrefLevel [Byte0]: 40
3372 10:52:01.457238 [Byte1]: 40
3373 10:52:01.461561
3374 10:52:01.464778 Set Vref, RX VrefLevel [Byte0]: 41
3375 10:52:01.465070 [Byte1]: 41
3376 10:52:01.469309
3377 10:52:01.469596 Set Vref, RX VrefLevel [Byte0]: 42
3378 10:52:01.472822 [Byte1]: 42
3379 10:52:01.476930
3380 10:52:01.477222 Set Vref, RX VrefLevel [Byte0]: 43
3381 10:52:01.480481 [Byte1]: 43
3382 10:52:01.484929
3383 10:52:01.485217 Set Vref, RX VrefLevel [Byte0]: 44
3384 10:52:01.488128 [Byte1]: 44
3385 10:52:01.492943
3386 10:52:01.493380 Set Vref, RX VrefLevel [Byte0]: 45
3387 10:52:01.496169 [Byte1]: 45
3388 10:52:01.501298
3389 10:52:01.501918 Set Vref, RX VrefLevel [Byte0]: 46
3390 10:52:01.503903 [Byte1]: 46
3391 10:52:01.508490
3392 10:52:01.508896 Set Vref, RX VrefLevel [Byte0]: 47
3393 10:52:01.512108 [Byte1]: 47
3394 10:52:01.516715
3395 10:52:01.517144 Set Vref, RX VrefLevel [Byte0]: 48
3396 10:52:01.519726 [Byte1]: 48
3397 10:52:01.524587
3398 10:52:01.525027 Set Vref, RX VrefLevel [Byte0]: 49
3399 10:52:01.527692 [Byte1]: 49
3400 10:52:01.532024
3401 10:52:01.532449 Set Vref, RX VrefLevel [Byte0]: 50
3402 10:52:01.535793 [Byte1]: 50
3403 10:52:01.540318
3404 10:52:01.540738 Set Vref, RX VrefLevel [Byte0]: 51
3405 10:52:01.543397 [Byte1]: 51
3406 10:52:01.547634
3407 10:52:01.548102 Set Vref, RX VrefLevel [Byte0]: 52
3408 10:52:01.551393 [Byte1]: 52
3409 10:52:01.555637
3410 10:52:01.556166 Set Vref, RX VrefLevel [Byte0]: 53
3411 10:52:01.559399 [Byte1]: 53
3412 10:52:01.563777
3413 10:52:01.564192 Set Vref, RX VrefLevel [Byte0]: 54
3414 10:52:01.566958 [Byte1]: 54
3415 10:52:01.571276
3416 10:52:01.571750 Set Vref, RX VrefLevel [Byte0]: 55
3417 10:52:01.575093 [Byte1]: 55
3418 10:52:01.579380
3419 10:52:01.579871 Set Vref, RX VrefLevel [Byte0]: 56
3420 10:52:01.582285 [Byte1]: 56
3421 10:52:01.587264
3422 10:52:01.587805 Set Vref, RX VrefLevel [Byte0]: 57
3423 10:52:01.590318 [Byte1]: 57
3424 10:52:01.594773
3425 10:52:01.595284 Set Vref, RX VrefLevel [Byte0]: 58
3426 10:52:01.598441 [Byte1]: 58
3427 10:52:01.602696
3428 10:52:01.603245 Set Vref, RX VrefLevel [Byte0]: 59
3429 10:52:01.606150 [Byte1]: 59
3430 10:52:01.610973
3431 10:52:01.611441 Set Vref, RX VrefLevel [Byte0]: 60
3432 10:52:01.614006 [Byte1]: 60
3433 10:52:01.618558
3434 10:52:01.619041 Set Vref, RX VrefLevel [Byte0]: 61
3435 10:52:01.621597 [Byte1]: 61
3436 10:52:01.626501
3437 10:52:01.626912 Set Vref, RX VrefLevel [Byte0]: 62
3438 10:52:01.629466 [Byte1]: 62
3439 10:52:01.634198
3440 10:52:01.634609 Set Vref, RX VrefLevel [Byte0]: 63
3441 10:52:01.637349 [Byte1]: 63
3442 10:52:01.642461
3443 10:52:01.642872 Set Vref, RX VrefLevel [Byte0]: 64
3444 10:52:01.645552 [Byte1]: 64
3445 10:52:01.650063
3446 10:52:01.650471 Set Vref, RX VrefLevel [Byte0]: 65
3447 10:52:01.653224 [Byte1]: 65
3448 10:52:01.657647
3449 10:52:01.658053 Set Vref, RX VrefLevel [Byte0]: 66
3450 10:52:01.661174 [Byte1]: 66
3451 10:52:01.665731
3452 10:52:01.666141 Set Vref, RX VrefLevel [Byte0]: 67
3453 10:52:01.668719 [Byte1]: 67
3454 10:52:01.673745
3455 10:52:01.674154 Set Vref, RX VrefLevel [Byte0]: 68
3456 10:52:01.676893 [Byte1]: 68
3457 10:52:01.681302
3458 10:52:01.681713 Set Vref, RX VrefLevel [Byte0]: 69
3459 10:52:01.684993 [Byte1]: 69
3460 10:52:01.689132
3461 10:52:01.689711 Final RX Vref Byte 0 = 55 to rank0
3462 10:52:01.692554 Final RX Vref Byte 1 = 47 to rank0
3463 10:52:01.695629 Final RX Vref Byte 0 = 55 to rank1
3464 10:52:01.699500 Final RX Vref Byte 1 = 47 to rank1==
3465 10:52:01.702657 Dram Type= 6, Freq= 0, CH_1, rank 0
3466 10:52:01.705742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 10:52:01.709350 ==
3468 10:52:01.709790 DQS Delay:
3469 10:52:01.710138 DQS0 = 0, DQS1 = 0
3470 10:52:01.712324 DQM Delay:
3471 10:52:01.712735 DQM0 = 120, DQM1 = 116
3472 10:52:01.715990 DQ Delay:
3473 10:52:01.719394 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3474 10:52:01.722281 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3475 10:52:01.726180 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3476 10:52:01.729347 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3477 10:52:01.729769
3478 10:52:01.730098
3479 10:52:01.735734 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3480 10:52:01.739384 CH1 RK0: MR19=404, MR18=13
3481 10:52:01.746168 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3482 10:52:01.746591
3483 10:52:01.749301 ----->DramcWriteLeveling(PI) begin...
3484 10:52:01.749694 ==
3485 10:52:01.752463 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 10:52:01.756210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 10:52:01.756640 ==
3488 10:52:01.759317 Write leveling (Byte 0): 26 => 26
3489 10:52:01.763025 Write leveling (Byte 1): 29 => 29
3490 10:52:01.766007 DramcWriteLeveling(PI) end<-----
3491 10:52:01.766451
3492 10:52:01.766796 ==
3493 10:52:01.769538 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 10:52:01.772778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 10:52:01.773229 ==
3496 10:52:01.775947 [Gating] SW mode calibration
3497 10:52:01.783050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3498 10:52:01.789400 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3499 10:52:01.792483 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 10:52:01.799539 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 10:52:01.802993 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 10:52:01.806196 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 10:52:01.812482 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 10:52:01.816042 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3505 10:52:01.819703 0 15 24 | B1->B0 | 2929 3333 | 0 0 | (1 0) (0 1)
3506 10:52:01.826296 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3507 10:52:01.829729 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 10:52:01.833230 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 10:52:01.836316 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 10:52:01.843017 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 10:52:01.845943 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 10:52:01.849459 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 10:52:01.855673 1 0 24 | B1->B0 | 4040 2727 | 0 0 | (0 0) (0 0)
3514 10:52:01.859425 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 10:52:01.862585 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 10:52:01.869451 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 10:52:01.872500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 10:52:01.875901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 10:52:01.882378 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 10:52:01.886036 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3521 10:52:01.889218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3522 10:52:01.895561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3523 10:52:01.899385 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 10:52:01.902468 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 10:52:01.909009 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 10:52:01.912520 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 10:52:01.915664 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 10:52:01.922456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 10:52:01.926043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 10:52:01.929233 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 10:52:01.935619 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 10:52:01.938909 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 10:52:01.942323 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 10:52:01.945717 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:52:01.952143 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 10:52:01.955707 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3537 10:52:01.962305 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3538 10:52:01.965401 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 10:52:01.969097 Total UI for P1: 0, mck2ui 16
3540 10:52:01.972613 best dqsien dly found for B0: ( 1, 3, 24)
3541 10:52:01.975242 Total UI for P1: 0, mck2ui 16
3542 10:52:01.979013 best dqsien dly found for B1: ( 1, 3, 22)
3543 10:52:01.982588 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3544 10:52:01.985790 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3545 10:52:01.986236
3546 10:52:01.988935 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 10:52:01.992070 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3548 10:52:01.995938 [Gating] SW calibration Done
3549 10:52:01.996499 ==
3550 10:52:01.999006 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 10:52:02.002276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 10:52:02.002723 ==
3553 10:52:02.005464 RX Vref Scan: 0
3554 10:52:02.005899
3555 10:52:02.008704 RX Vref 0 -> 0, step: 1
3556 10:52:02.009167
3557 10:52:02.009722 RX Delay -40 -> 252, step: 8
3558 10:52:02.015292 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3559 10:52:02.018751 iDelay=200, Bit 1, Center 119 (56 ~ 183) 128
3560 10:52:02.021868 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3561 10:52:02.025555 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3562 10:52:02.028490 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3563 10:52:02.035407 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3564 10:52:02.039028 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3565 10:52:02.042198 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3566 10:52:02.045145 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3567 10:52:02.048496 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3568 10:52:02.055356 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3569 10:52:02.059054 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3570 10:52:02.062155 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3571 10:52:02.065347 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3572 10:52:02.068641 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3573 10:52:02.075728 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3574 10:52:02.076292 ==
3575 10:52:02.078720 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 10:52:02.082399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 10:52:02.082937 ==
3578 10:52:02.083282 DQS Delay:
3579 10:52:02.085497 DQS0 = 0, DQS1 = 0
3580 10:52:02.085929 DQM Delay:
3581 10:52:02.088623 DQM0 = 121, DQM1 = 119
3582 10:52:02.089088 DQ Delay:
3583 10:52:02.092044 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3584 10:52:02.095436 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3585 10:52:02.099031 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3586 10:52:02.102096 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3587 10:52:02.102517
3588 10:52:02.102846
3589 10:52:02.105386 ==
3590 10:52:02.108493 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 10:52:02.112176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 10:52:02.112600 ==
3593 10:52:02.112932
3594 10:52:02.113241
3595 10:52:02.115235 TX Vref Scan disable
3596 10:52:02.115682 == TX Byte 0 ==
3597 10:52:02.118972 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3598 10:52:02.125577 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3599 10:52:02.126087 == TX Byte 1 ==
3600 10:52:02.128625 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3601 10:52:02.135164 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3602 10:52:02.135641 ==
3603 10:52:02.138838 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 10:52:02.141980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 10:52:02.142406 ==
3606 10:52:02.153822 TX Vref=22, minBit 0, minWin=26, winSum=422
3607 10:52:02.157116 TX Vref=24, minBit 2, minWin=26, winSum=430
3608 10:52:02.160184 TX Vref=26, minBit 1, minWin=26, winSum=428
3609 10:52:02.163570 TX Vref=28, minBit 1, minWin=26, winSum=432
3610 10:52:02.167236 TX Vref=30, minBit 10, minWin=25, winSum=434
3611 10:52:02.173799 TX Vref=32, minBit 9, minWin=26, winSum=435
3612 10:52:02.177196 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32
3613 10:52:02.177629
3614 10:52:02.180260 Final TX Range 1 Vref 32
3615 10:52:02.180729
3616 10:52:02.181067 ==
3617 10:52:02.184007 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 10:52:02.187178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 10:52:02.187584 ==
3620 10:52:02.190067
3621 10:52:02.190369
3622 10:52:02.190639 TX Vref Scan disable
3623 10:52:02.193714 == TX Byte 0 ==
3624 10:52:02.196801 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3625 10:52:02.203129 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3626 10:52:02.203284 == TX Byte 1 ==
3627 10:52:02.206884 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3628 10:52:02.213203 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3629 10:52:02.213320
3630 10:52:02.213410 [DATLAT]
3631 10:52:02.213496 Freq=1200, CH1 RK1
3632 10:52:02.213592
3633 10:52:02.216352 DATLAT Default: 0xd
3634 10:52:02.216478 0, 0xFFFF, sum = 0
3635 10:52:02.219347 1, 0xFFFF, sum = 0
3636 10:52:02.223270 2, 0xFFFF, sum = 0
3637 10:52:02.223374 3, 0xFFFF, sum = 0
3638 10:52:02.226277 4, 0xFFFF, sum = 0
3639 10:52:02.226373 5, 0xFFFF, sum = 0
3640 10:52:02.229343 6, 0xFFFF, sum = 0
3641 10:52:02.229429 7, 0xFFFF, sum = 0
3642 10:52:02.233031 8, 0xFFFF, sum = 0
3643 10:52:02.233117 9, 0xFFFF, sum = 0
3644 10:52:02.236047 10, 0xFFFF, sum = 0
3645 10:52:02.236132 11, 0xFFFF, sum = 0
3646 10:52:02.239541 12, 0x0, sum = 1
3647 10:52:02.239625 13, 0x0, sum = 2
3648 10:52:02.242743 14, 0x0, sum = 3
3649 10:52:02.242828 15, 0x0, sum = 4
3650 10:52:02.246397 best_step = 13
3651 10:52:02.246480
3652 10:52:02.246545 ==
3653 10:52:02.249511 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 10:52:02.252591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 10:52:02.252673 ==
3656 10:52:02.252738 RX Vref Scan: 0
3657 10:52:02.255800
3658 10:52:02.255882 RX Vref 0 -> 0, step: 1
3659 10:52:02.255947
3660 10:52:02.259445 RX Delay -5 -> 252, step: 4
3661 10:52:02.262512 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3662 10:52:02.269673 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3663 10:52:02.272428 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3664 10:52:02.276158 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3665 10:52:02.279022 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3666 10:52:02.282498 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3667 10:52:02.289149 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3668 10:52:02.292651 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3669 10:52:02.296127 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3670 10:52:02.299146 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3671 10:52:02.302824 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3672 10:52:02.309097 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3673 10:52:02.312802 iDelay=195, Bit 12, Center 124 (59 ~ 190) 132
3674 10:52:02.316149 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3675 10:52:02.319276 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3676 10:52:02.325473 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3677 10:52:02.325561 ==
3678 10:52:02.329313 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 10:52:02.332523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 10:52:02.332634 ==
3681 10:52:02.332732 DQS Delay:
3682 10:52:02.336109 DQS0 = 0, DQS1 = 0
3683 10:52:02.336192 DQM Delay:
3684 10:52:02.338986 DQM0 = 120, DQM1 = 116
3685 10:52:02.339068 DQ Delay:
3686 10:52:02.342588 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3687 10:52:02.345617 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3688 10:52:02.349435 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3689 10:52:02.352418 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3690 10:52:02.352500
3691 10:52:02.352565
3692 10:52:02.362590 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3693 10:52:02.365538 CH1 RK1: MR19=403, MR18=10ED
3694 10:52:02.369354 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3695 10:52:02.372332 [RxdqsGatingPostProcess] freq 1200
3696 10:52:02.378989 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 10:52:02.381972 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 10:52:02.385688 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 10:52:02.388872 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 10:52:02.391932 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 10:52:02.395763 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 10:52:02.398750 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 10:52:02.402395 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 10:52:02.405195 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 10:52:02.408463 Pre-setting of DQS Precalculation
3706 10:52:02.412088 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 10:52:02.418505 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 10:52:02.425450 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 10:52:02.428417
3710 10:52:02.428504
3711 10:52:02.428569 [Calibration Summary] 2400 Mbps
3712 10:52:02.432284 CH 0, Rank 0
3713 10:52:02.432367 SW Impedance : PASS
3714 10:52:02.435368 DUTY Scan : NO K
3715 10:52:02.438531 ZQ Calibration : PASS
3716 10:52:02.438614 Jitter Meter : NO K
3717 10:52:02.442300 CBT Training : PASS
3718 10:52:02.445316 Write leveling : PASS
3719 10:52:02.445399 RX DQS gating : PASS
3720 10:52:02.448328 RX DQ/DQS(RDDQC) : PASS
3721 10:52:02.451788 TX DQ/DQS : PASS
3722 10:52:02.451881 RX DATLAT : PASS
3723 10:52:02.454899 RX DQ/DQS(Engine): PASS
3724 10:52:02.458589 TX OE : NO K
3725 10:52:02.458674 All Pass.
3726 10:52:02.458738
3727 10:52:02.458798 CH 0, Rank 1
3728 10:52:02.461670 SW Impedance : PASS
3729 10:52:02.464888 DUTY Scan : NO K
3730 10:52:02.464975 ZQ Calibration : PASS
3731 10:52:02.468645 Jitter Meter : NO K
3732 10:52:02.471753 CBT Training : PASS
3733 10:52:02.471836 Write leveling : PASS
3734 10:52:02.475333 RX DQS gating : PASS
3735 10:52:02.475447 RX DQ/DQS(RDDQC) : PASS
3736 10:52:02.478539 TX DQ/DQS : PASS
3737 10:52:02.481625 RX DATLAT : PASS
3738 10:52:02.481717 RX DQ/DQS(Engine): PASS
3739 10:52:02.485236 TX OE : NO K
3740 10:52:02.485320 All Pass.
3741 10:52:02.485385
3742 10:52:02.488161 CH 1, Rank 0
3743 10:52:02.488254 SW Impedance : PASS
3744 10:52:02.491647 DUTY Scan : NO K
3745 10:52:02.495295 ZQ Calibration : PASS
3746 10:52:02.495396 Jitter Meter : NO K
3747 10:52:02.498233 CBT Training : PASS
3748 10:52:02.501357 Write leveling : PASS
3749 10:52:02.501440 RX DQS gating : PASS
3750 10:52:02.505049 RX DQ/DQS(RDDQC) : PASS
3751 10:52:02.508062 TX DQ/DQS : PASS
3752 10:52:02.508149 RX DATLAT : PASS
3753 10:52:02.511531 RX DQ/DQS(Engine): PASS
3754 10:52:02.514725 TX OE : NO K
3755 10:52:02.514809 All Pass.
3756 10:52:02.514882
3757 10:52:02.514943 CH 1, Rank 1
3758 10:52:02.518466 SW Impedance : PASS
3759 10:52:02.521578 DUTY Scan : NO K
3760 10:52:02.521667 ZQ Calibration : PASS
3761 10:52:02.524801 Jitter Meter : NO K
3762 10:52:02.527975 CBT Training : PASS
3763 10:52:02.528057 Write leveling : PASS
3764 10:52:02.531581 RX DQS gating : PASS
3765 10:52:02.531674 RX DQ/DQS(RDDQC) : PASS
3766 10:52:02.534766 TX DQ/DQS : PASS
3767 10:52:02.537909 RX DATLAT : PASS
3768 10:52:02.537992 RX DQ/DQS(Engine): PASS
3769 10:52:02.541853 TX OE : NO K
3770 10:52:02.541936 All Pass.
3771 10:52:02.542002
3772 10:52:02.544864 DramC Write-DBI off
3773 10:52:02.548000 PER_BANK_REFRESH: Hybrid Mode
3774 10:52:02.548083 TX_TRACKING: ON
3775 10:52:02.558445 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 10:52:02.561336 [FAST_K] Save calibration result to emmc
3777 10:52:02.565040 dramc_set_vcore_voltage set vcore to 650000
3778 10:52:02.568198 Read voltage for 600, 5
3779 10:52:02.568283 Vio18 = 0
3780 10:52:02.568366 Vcore = 650000
3781 10:52:02.571244 Vdram = 0
3782 10:52:02.571386 Vddq = 0
3783 10:52:02.571470 Vmddr = 0
3784 10:52:02.577785 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 10:52:02.581506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 10:52:02.584714 MEM_TYPE=3, freq_sel=19
3787 10:52:02.587841 sv_algorithm_assistance_LP4_1600
3788 10:52:02.590816 ============ PULL DRAM RESETB DOWN ============
3789 10:52:02.597883 ========== PULL DRAM RESETB DOWN end =========
3790 10:52:02.600969 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 10:52:02.604365 ===================================
3792 10:52:02.607983 LPDDR4 DRAM CONFIGURATION
3793 10:52:02.611064 ===================================
3794 10:52:02.611149 EX_ROW_EN[0] = 0x0
3795 10:52:02.614662 EX_ROW_EN[1] = 0x0
3796 10:52:02.614748 LP4Y_EN = 0x0
3797 10:52:02.617553 WORK_FSP = 0x0
3798 10:52:02.617638 WL = 0x2
3799 10:52:02.621218 RL = 0x2
3800 10:52:02.621302 BL = 0x2
3801 10:52:02.624566 RPST = 0x0
3802 10:52:02.624650 RD_PRE = 0x0
3803 10:52:02.627784 WR_PRE = 0x1
3804 10:52:02.627866 WR_PST = 0x0
3805 10:52:02.631096 DBI_WR = 0x0
3806 10:52:02.631202 DBI_RD = 0x0
3807 10:52:02.634798 OTF = 0x1
3808 10:52:02.637830 ===================================
3809 10:52:02.640952 ===================================
3810 10:52:02.641034 ANA top config
3811 10:52:02.644744 ===================================
3812 10:52:02.647860 DLL_ASYNC_EN = 0
3813 10:52:02.651007 ALL_SLAVE_EN = 1
3814 10:52:02.654795 NEW_RANK_MODE = 1
3815 10:52:02.654877 DLL_IDLE_MODE = 1
3816 10:52:02.657892 LP45_APHY_COMB_EN = 1
3817 10:52:02.660951 TX_ODT_DIS = 1
3818 10:52:02.664459 NEW_8X_MODE = 1
3819 10:52:02.668030 ===================================
3820 10:52:02.671138 ===================================
3821 10:52:02.674302 data_rate = 1200
3822 10:52:02.674384 CKR = 1
3823 10:52:02.677976 DQ_P2S_RATIO = 8
3824 10:52:02.681010 ===================================
3825 10:52:02.684681 CA_P2S_RATIO = 8
3826 10:52:02.687821 DQ_CA_OPEN = 0
3827 10:52:02.690920 DQ_SEMI_OPEN = 0
3828 10:52:02.694627 CA_SEMI_OPEN = 0
3829 10:52:02.694709 CA_FULL_RATE = 0
3830 10:52:02.697650 DQ_CKDIV4_EN = 1
3831 10:52:02.700745 CA_CKDIV4_EN = 1
3832 10:52:02.704344 CA_PREDIV_EN = 0
3833 10:52:02.707467 PH8_DLY = 0
3834 10:52:02.710778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 10:52:02.710877 DQ_AAMCK_DIV = 4
3836 10:52:02.714421 CA_AAMCK_DIV = 4
3837 10:52:02.717570 CA_ADMCK_DIV = 4
3838 10:52:02.720996 DQ_TRACK_CA_EN = 0
3839 10:52:02.724560 CA_PICK = 600
3840 10:52:02.727636 CA_MCKIO = 600
3841 10:52:02.727718 MCKIO_SEMI = 0
3842 10:52:02.730907 PLL_FREQ = 2288
3843 10:52:02.733983 DQ_UI_PI_RATIO = 32
3844 10:52:02.737752 CA_UI_PI_RATIO = 0
3845 10:52:02.740876 ===================================
3846 10:52:02.744114 ===================================
3847 10:52:02.747877 memory_type:LPDDR4
3848 10:52:02.747959 GP_NUM : 10
3849 10:52:02.750985 SRAM_EN : 1
3850 10:52:02.754168 MD32_EN : 0
3851 10:52:02.757272 ===================================
3852 10:52:02.757354 [ANA_INIT] >>>>>>>>>>>>>>
3853 10:52:02.761107 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 10:52:02.764311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 10:52:02.767488 ===================================
3856 10:52:02.771007 data_rate = 1200,PCW = 0X5800
3857 10:52:02.773869 ===================================
3858 10:52:02.777476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 10:52:02.784298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 10:52:02.787320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 10:52:02.793803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 10:52:02.797451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 10:52:02.800597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 10:52:02.800679 [ANA_INIT] flow start
3865 10:52:02.803704 [ANA_INIT] PLL >>>>>>>>
3866 10:52:02.807460 [ANA_INIT] PLL <<<<<<<<
3867 10:52:02.810492 [ANA_INIT] MIDPI >>>>>>>>
3868 10:52:02.810602 [ANA_INIT] MIDPI <<<<<<<<
3869 10:52:02.814112 [ANA_INIT] DLL >>>>>>>>
3870 10:52:02.817294 [ANA_INIT] flow end
3871 10:52:02.820338 ============ LP4 DIFF to SE enter ============
3872 10:52:02.824079 ============ LP4 DIFF to SE exit ============
3873 10:52:02.827482 [ANA_INIT] <<<<<<<<<<<<<
3874 10:52:02.830672 [Flow] Enable top DCM control >>>>>
3875 10:52:02.834292 [Flow] Enable top DCM control <<<<<
3876 10:52:02.837416 Enable DLL master slave shuffle
3877 10:52:02.840544 ==============================================================
3878 10:52:02.843653 Gating Mode config
3879 10:52:02.847243 ==============================================================
3880 10:52:02.850436 Config description:
3881 10:52:02.860734 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 10:52:02.867042 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 10:52:02.870240 SELPH_MODE 0: By rank 1: By Phase
3884 10:52:02.877003 ==============================================================
3885 10:52:02.880381 GAT_TRACK_EN = 1
3886 10:52:02.883931 RX_GATING_MODE = 2
3887 10:52:02.886748 RX_GATING_TRACK_MODE = 2
3888 10:52:02.890452 SELPH_MODE = 1
3889 10:52:02.893492 PICG_EARLY_EN = 1
3890 10:52:02.893574 VALID_LAT_VALUE = 1
3891 10:52:02.900321 ==============================================================
3892 10:52:02.903398 Enter into Gating configuration >>>>
3893 10:52:02.906711 Exit from Gating configuration <<<<
3894 10:52:02.910373 Enter into DVFS_PRE_config >>>>>
3895 10:52:02.919997 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 10:52:02.923530 Exit from DVFS_PRE_config <<<<<
3897 10:52:02.926557 Enter into PICG configuration >>>>
3898 10:52:02.929829 Exit from PICG configuration <<<<
3899 10:52:02.933408 [RX_INPUT] configuration >>>>>
3900 10:52:02.936974 [RX_INPUT] configuration <<<<<
3901 10:52:02.943241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 10:52:02.946460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 10:52:02.953051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 10:52:02.960011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 10:52:02.966340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 10:52:02.973177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 10:52:02.976313 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 10:52:02.979507 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 10:52:02.982625 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 10:52:02.989343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 10:52:02.992991 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 10:52:02.996547 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 10:52:02.999882 ===================================
3914 10:52:03.002773 LPDDR4 DRAM CONFIGURATION
3915 10:52:03.006371 ===================================
3916 10:52:03.006455 EX_ROW_EN[0] = 0x0
3917 10:52:03.009452 EX_ROW_EN[1] = 0x0
3918 10:52:03.012561 LP4Y_EN = 0x0
3919 10:52:03.012644 WORK_FSP = 0x0
3920 10:52:03.016327 WL = 0x2
3921 10:52:03.016410 RL = 0x2
3922 10:52:03.019385 BL = 0x2
3923 10:52:03.019468 RPST = 0x0
3924 10:52:03.022539 RD_PRE = 0x0
3925 10:52:03.022623 WR_PRE = 0x1
3926 10:52:03.026014 WR_PST = 0x0
3927 10:52:03.026097 DBI_WR = 0x0
3928 10:52:03.029597 DBI_RD = 0x0
3929 10:52:03.029682 OTF = 0x1
3930 10:52:03.033123 ===================================
3931 10:52:03.036292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 10:52:03.043175 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 10:52:03.046364 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 10:52:03.049436 ===================================
3935 10:52:03.053218 LPDDR4 DRAM CONFIGURATION
3936 10:52:03.056310 ===================================
3937 10:52:03.056398 EX_ROW_EN[0] = 0x10
3938 10:52:03.059498 EX_ROW_EN[1] = 0x0
3939 10:52:03.059581 LP4Y_EN = 0x0
3940 10:52:03.062744 WORK_FSP = 0x0
3941 10:52:03.062827 WL = 0x2
3942 10:52:03.066442 RL = 0x2
3943 10:52:03.066528 BL = 0x2
3944 10:52:03.069597 RPST = 0x0
3945 10:52:03.072653 RD_PRE = 0x0
3946 10:52:03.072736 WR_PRE = 0x1
3947 10:52:03.075790 WR_PST = 0x0
3948 10:52:03.075874 DBI_WR = 0x0
3949 10:52:03.079783 DBI_RD = 0x0
3950 10:52:03.079866 OTF = 0x1
3951 10:52:03.082856 ===================================
3952 10:52:03.088970 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 10:52:03.093256 nWR fixed to 30
3954 10:52:03.096340 [ModeRegInit_LP4] CH0 RK0
3955 10:52:03.096423 [ModeRegInit_LP4] CH0 RK1
3956 10:52:03.099559 [ModeRegInit_LP4] CH1 RK0
3957 10:52:03.103270 [ModeRegInit_LP4] CH1 RK1
3958 10:52:03.103394 match AC timing 17
3959 10:52:03.109605 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 10:52:03.112890 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 10:52:03.116369 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 10:52:03.123285 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 10:52:03.126507 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 10:52:03.126595 ==
3965 10:52:03.129675 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 10:52:03.132862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 10:52:03.132945 ==
3968 10:52:03.139632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 10:52:03.146639 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3970 10:52:03.149599 [CA 0] Center 35 (5~66) winsize 62
3971 10:52:03.153100 [CA 1] Center 35 (5~66) winsize 62
3972 10:52:03.156195 [CA 2] Center 33 (3~64) winsize 62
3973 10:52:03.159272 [CA 3] Center 33 (2~64) winsize 63
3974 10:52:03.162890 [CA 4] Center 33 (2~64) winsize 63
3975 10:52:03.166109 [CA 5] Center 32 (2~63) winsize 62
3976 10:52:03.166207
3977 10:52:03.169351 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3978 10:52:03.169434
3979 10:52:03.173107 [CATrainingPosCal] consider 1 rank data
3980 10:52:03.176221 u2DelayCellTimex100 = 270/100 ps
3981 10:52:03.179399 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3982 10:52:03.182504 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3983 10:52:03.186315 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3984 10:52:03.189452 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3985 10:52:03.192442 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3986 10:52:03.199658 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3987 10:52:03.199744
3988 10:52:03.202761 CA PerBit enable=1, Macro0, CA PI delay=32
3989 10:52:03.202844
3990 10:52:03.205910 [CBTSetCACLKResult] CA Dly = 32
3991 10:52:03.205993 CS Dly: 4 (0~35)
3992 10:52:03.206057 ==
3993 10:52:03.208997 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 10:52:03.212572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 10:52:03.212655 ==
3996 10:52:03.219720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 10:52:03.225981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 10:52:03.229383 [CA 0] Center 35 (5~66) winsize 62
3999 10:52:03.232443 [CA 1] Center 35 (5~66) winsize 62
4000 10:52:03.236233 [CA 2] Center 34 (3~65) winsize 63
4001 10:52:03.239286 [CA 3] Center 33 (3~64) winsize 62
4002 10:52:03.242362 [CA 4] Center 33 (2~64) winsize 63
4003 10:52:03.246034 [CA 5] Center 32 (2~63) winsize 62
4004 10:52:03.246117
4005 10:52:03.249427 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 10:52:03.249510
4007 10:52:03.252464 [CATrainingPosCal] consider 2 rank data
4008 10:52:03.256108 u2DelayCellTimex100 = 270/100 ps
4009 10:52:03.259119 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4010 10:52:03.262629 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4011 10:52:03.266052 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4012 10:52:03.269006 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4013 10:52:03.275548 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4014 10:52:03.279421 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4015 10:52:03.279495
4016 10:52:03.282491 CA PerBit enable=1, Macro0, CA PI delay=32
4017 10:52:03.282573
4018 10:52:03.285779 [CBTSetCACLKResult] CA Dly = 32
4019 10:52:03.285873 CS Dly: 4 (0~36)
4020 10:52:03.285938
4021 10:52:03.288826 ----->DramcWriteLeveling(PI) begin...
4022 10:52:03.288899 ==
4023 10:52:03.292557 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 10:52:03.299256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 10:52:03.299398 ==
4026 10:52:03.302425 Write leveling (Byte 0): 33 => 33
4027 10:52:03.302529 Write leveling (Byte 1): 33 => 33
4028 10:52:03.305672 DramcWriteLeveling(PI) end<-----
4029 10:52:03.305771
4030 10:52:03.308862 ==
4031 10:52:03.308937 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 10:52:03.316003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 10:52:03.316080 ==
4034 10:52:03.319123 [Gating] SW mode calibration
4035 10:52:03.325295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 10:52:03.328976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 10:52:03.335568 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 10:52:03.338618 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 10:52:03.342432 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 10:52:03.349073 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
4041 10:52:03.352259 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
4042 10:52:03.355789 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 10:52:03.362520 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 10:52:03.365774 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 10:52:03.368857 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 10:52:03.372402 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 10:52:03.378536 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4048 10:52:03.382170 0 10 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
4049 10:52:03.385317 0 10 16 | B1->B0 | 3231 4646 | 1 0 | (0 0) (0 0)
4050 10:52:03.392304 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 10:52:03.395514 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 10:52:03.398773 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 10:52:03.405464 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 10:52:03.409009 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 10:52:03.412118 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 10:52:03.419097 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4057 10:52:03.422108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 10:52:03.425300 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 10:52:03.431934 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 10:52:03.435239 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 10:52:03.438333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 10:52:03.445169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 10:52:03.448749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 10:52:03.451781 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 10:52:03.458591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 10:52:03.462136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 10:52:03.465212 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 10:52:03.471520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 10:52:03.475207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 10:52:03.478304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 10:52:03.484913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:52:03.488348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 10:52:03.492008 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4074 10:52:03.495208 Total UI for P1: 0, mck2ui 16
4075 10:52:03.498509 best dqsien dly found for B0: ( 0, 13, 14)
4076 10:52:03.501607 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 10:52:03.504644 Total UI for P1: 0, mck2ui 16
4078 10:52:03.508526 best dqsien dly found for B1: ( 0, 13, 16)
4079 10:52:03.515092 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4080 10:52:03.518292 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4081 10:52:03.518378
4082 10:52:03.521328 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4083 10:52:03.525336 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4084 10:52:03.528409 [Gating] SW calibration Done
4085 10:52:03.528501 ==
4086 10:52:03.531701 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 10:52:03.534704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 10:52:03.534789 ==
4089 10:52:03.538346 RX Vref Scan: 0
4090 10:52:03.538429
4091 10:52:03.538493 RX Vref 0 -> 0, step: 1
4092 10:52:03.538553
4093 10:52:03.541284 RX Delay -230 -> 252, step: 16
4094 10:52:03.544731 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4095 10:52:03.551307 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4096 10:52:03.554825 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4097 10:52:03.557907 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4098 10:52:03.561860 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4099 10:52:03.568441 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4100 10:52:03.571276 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4101 10:52:03.574839 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4102 10:52:03.578073 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4103 10:52:03.581879 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4104 10:52:03.588098 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4105 10:52:03.591141 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4106 10:52:03.594583 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4107 10:52:03.598201 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4108 10:52:03.604689 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4109 10:52:03.608357 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4110 10:52:03.608441 ==
4111 10:52:03.611215 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 10:52:03.615022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 10:52:03.615105 ==
4114 10:52:03.615208 DQS Delay:
4115 10:52:03.617952 DQS0 = 0, DQS1 = 0
4116 10:52:03.618028 DQM Delay:
4117 10:52:03.621242 DQM0 = 53, DQM1 = 45
4118 10:52:03.621341 DQ Delay:
4119 10:52:03.625005 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4120 10:52:03.628145 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4121 10:52:03.631217 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4122 10:52:03.634439 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4123 10:52:03.634517
4124 10:52:03.634598
4125 10:52:03.634679 ==
4126 10:52:03.638115 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 10:52:03.641168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 10:52:03.644923 ==
4129 10:52:03.645002
4130 10:52:03.645083
4131 10:52:03.645180 TX Vref Scan disable
4132 10:52:03.647954 == TX Byte 0 ==
4133 10:52:03.651471 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4134 10:52:03.654303 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4135 10:52:03.657878 == TX Byte 1 ==
4136 10:52:03.661357 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4137 10:52:03.664524 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4138 10:52:03.667662 ==
4139 10:52:03.671287 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 10:52:03.674350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 10:52:03.674434 ==
4142 10:52:03.674498
4143 10:52:03.674557
4144 10:52:03.677689 TX Vref Scan disable
4145 10:52:03.677771 == TX Byte 0 ==
4146 10:52:03.684690 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4147 10:52:03.687774 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4148 10:52:03.687858 == TX Byte 1 ==
4149 10:52:03.694770 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4150 10:52:03.697990 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4151 10:52:03.698074
4152 10:52:03.698139 [DATLAT]
4153 10:52:03.701010 Freq=600, CH0 RK0
4154 10:52:03.701093
4155 10:52:03.701157 DATLAT Default: 0x9
4156 10:52:03.704511 0, 0xFFFF, sum = 0
4157 10:52:03.704596 1, 0xFFFF, sum = 0
4158 10:52:03.707646 2, 0xFFFF, sum = 0
4159 10:52:03.707729 3, 0xFFFF, sum = 0
4160 10:52:03.711260 4, 0xFFFF, sum = 0
4161 10:52:03.714311 5, 0xFFFF, sum = 0
4162 10:52:03.714395 6, 0xFFFF, sum = 0
4163 10:52:03.717937 7, 0xFFFF, sum = 0
4164 10:52:03.718021 8, 0x0, sum = 1
4165 10:52:03.718088 9, 0x0, sum = 2
4166 10:52:03.721015 10, 0x0, sum = 3
4167 10:52:03.721098 11, 0x0, sum = 4
4168 10:52:03.724188 best_step = 9
4169 10:52:03.724270
4170 10:52:03.724335 ==
4171 10:52:03.727747 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 10:52:03.730864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 10:52:03.730948 ==
4174 10:52:03.734670 RX Vref Scan: 1
4175 10:52:03.734752
4176 10:52:03.734817 RX Vref 0 -> 0, step: 1
4177 10:52:03.734877
4178 10:52:03.737733 RX Delay -179 -> 252, step: 8
4179 10:52:03.737816
4180 10:52:03.740818 Set Vref, RX VrefLevel [Byte0]: 56
4181 10:52:03.744451 [Byte1]: 49
4182 10:52:03.748292
4183 10:52:03.748374 Final RX Vref Byte 0 = 56 to rank0
4184 10:52:03.751514 Final RX Vref Byte 1 = 49 to rank0
4185 10:52:03.754624 Final RX Vref Byte 0 = 56 to rank1
4186 10:52:03.758313 Final RX Vref Byte 1 = 49 to rank1==
4187 10:52:03.761743 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 10:52:03.767927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 10:52:03.768012 ==
4190 10:52:03.768078 DQS Delay:
4191 10:52:03.768138 DQS0 = 0, DQS1 = 0
4192 10:52:03.771732 DQM Delay:
4193 10:52:03.771814 DQM0 = 53, DQM1 = 47
4194 10:52:03.774681 DQ Delay:
4195 10:52:03.777889 DQ0 =48, DQ1 =56, DQ2 =48, DQ3 =48
4196 10:52:03.781482 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4197 10:52:03.781569 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4198 10:52:03.787923 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4199 10:52:03.788007
4200 10:52:03.788072
4201 10:52:03.794968 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4202 10:52:03.798166 CH0 RK0: MR19=808, MR18=7164
4203 10:52:03.804519 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4204 10:52:03.804613
4205 10:52:03.808181 ----->DramcWriteLeveling(PI) begin...
4206 10:52:03.808266 ==
4207 10:52:03.811109 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 10:52:03.814690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 10:52:03.814775 ==
4210 10:52:03.817649 Write leveling (Byte 0): 35 => 35
4211 10:52:03.821303 Write leveling (Byte 1): 33 => 33
4212 10:52:03.824302 DramcWriteLeveling(PI) end<-----
4213 10:52:03.824386
4214 10:52:03.824451 ==
4215 10:52:03.827844 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 10:52:03.831102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 10:52:03.831210 ==
4218 10:52:03.834357 [Gating] SW mode calibration
4219 10:52:03.841442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 10:52:03.848197 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4221 10:52:03.851296 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 10:52:03.857729 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 10:52:03.860841 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 10:52:03.864580 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4225 10:52:03.871108 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
4226 10:52:03.874459 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 10:52:03.877914 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 10:52:03.881315 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 10:52:03.887578 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 10:52:03.891095 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 10:52:03.894358 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 10:52:03.900772 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4233 10:52:03.904338 0 10 16 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
4234 10:52:03.908109 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 10:52:03.914466 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 10:52:03.917531 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 10:52:03.920995 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 10:52:03.927383 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 10:52:03.931014 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 10:52:03.934382 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4241 10:52:03.940909 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 10:52:03.943941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 10:52:03.947647 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 10:52:03.953949 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 10:52:03.957844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 10:52:03.961047 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 10:52:03.967286 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 10:52:03.970889 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 10:52:03.973966 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 10:52:03.980864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 10:52:03.984273 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:52:03.987322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 10:52:03.991305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 10:52:03.997692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:52:04.000912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:52:04.004023 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4257 10:52:04.007797 Total UI for P1: 0, mck2ui 16
4258 10:52:04.010767 best dqsien dly found for B0: ( 0, 13, 10)
4259 10:52:04.017724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 10:52:04.020982 Total UI for P1: 0, mck2ui 16
4261 10:52:04.024014 best dqsien dly found for B1: ( 0, 13, 12)
4262 10:52:04.027533 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4263 10:52:04.030939 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4264 10:52:04.031285
4265 10:52:04.034151 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4266 10:52:04.037525 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4267 10:52:04.040996 [Gating] SW calibration Done
4268 10:52:04.041201 ==
4269 10:52:04.043955 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 10:52:04.047510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 10:52:04.047665 ==
4272 10:52:04.050901 RX Vref Scan: 0
4273 10:52:04.051043
4274 10:52:04.054041 RX Vref 0 -> 0, step: 1
4275 10:52:04.054164
4276 10:52:04.054261 RX Delay -230 -> 252, step: 16
4277 10:52:04.060951 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4278 10:52:04.063969 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4279 10:52:04.067263 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4280 10:52:04.070371 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4281 10:52:04.077216 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4282 10:52:04.080911 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4283 10:52:04.083964 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4284 10:52:04.086891 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4285 10:52:04.090676 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4286 10:52:04.097160 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4287 10:52:04.100348 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4288 10:52:04.103987 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4289 10:52:04.107163 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4290 10:52:04.113965 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4291 10:52:04.117147 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4292 10:52:04.120357 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4293 10:52:04.120465 ==
4294 10:52:04.123481 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 10:52:04.127193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 10:52:04.130199 ==
4297 10:52:04.130347 DQS Delay:
4298 10:52:04.130413 DQS0 = 0, DQS1 = 0
4299 10:52:04.133996 DQM Delay:
4300 10:52:04.134104 DQM0 = 51, DQM1 = 43
4301 10:52:04.134198 DQ Delay:
4302 10:52:04.137147 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4303 10:52:04.140211 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4304 10:52:04.143816 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4305 10:52:04.146848 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4306 10:52:04.146930
4307 10:52:04.146995
4308 10:52:04.150301 ==
4309 10:52:04.153880 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 10:52:04.156834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 10:52:04.156911 ==
4312 10:52:04.156973
4313 10:52:04.157032
4314 10:52:04.160518 TX Vref Scan disable
4315 10:52:04.160618 == TX Byte 0 ==
4316 10:52:04.167102 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4317 10:52:04.170343 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4318 10:52:04.170415 == TX Byte 1 ==
4319 10:52:04.177111 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4320 10:52:04.179954 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4321 10:52:04.180050 ==
4322 10:52:04.183784 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 10:52:04.186955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 10:52:04.187041 ==
4325 10:52:04.187107
4326 10:52:04.187166
4327 10:52:04.189994 TX Vref Scan disable
4328 10:52:04.193638 == TX Byte 0 ==
4329 10:52:04.196774 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4330 10:52:04.200297 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4331 10:52:04.203222 == TX Byte 1 ==
4332 10:52:04.206827 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 10:52:04.210470 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 10:52:04.210564
4335 10:52:04.213615 [DATLAT]
4336 10:52:04.213697 Freq=600, CH0 RK1
4337 10:52:04.213762
4338 10:52:04.216739 DATLAT Default: 0x9
4339 10:52:04.216831 0, 0xFFFF, sum = 0
4340 10:52:04.220490 1, 0xFFFF, sum = 0
4341 10:52:04.220573 2, 0xFFFF, sum = 0
4342 10:52:04.223430 3, 0xFFFF, sum = 0
4343 10:52:04.223540 4, 0xFFFF, sum = 0
4344 10:52:04.226621 5, 0xFFFF, sum = 0
4345 10:52:04.226731 6, 0xFFFF, sum = 0
4346 10:52:04.229832 7, 0xFFFF, sum = 0
4347 10:52:04.229925 8, 0x0, sum = 1
4348 10:52:04.233324 9, 0x0, sum = 2
4349 10:52:04.233407 10, 0x0, sum = 3
4350 10:52:04.236503 11, 0x0, sum = 4
4351 10:52:04.236600 best_step = 9
4352 10:52:04.236667
4353 10:52:04.236725 ==
4354 10:52:04.239614 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 10:52:04.246285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 10:52:04.246401 ==
4357 10:52:04.246494 RX Vref Scan: 0
4358 10:52:04.246582
4359 10:52:04.249993 RX Vref 0 -> 0, step: 1
4360 10:52:04.250073
4361 10:52:04.252993 RX Delay -163 -> 252, step: 8
4362 10:52:04.256389 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4363 10:52:04.259334 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4364 10:52:04.266679 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4365 10:52:04.269797 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4366 10:52:04.272873 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4367 10:52:04.276102 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4368 10:52:04.279840 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4369 10:52:04.286489 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4370 10:52:04.289693 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4371 10:52:04.292751 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4372 10:52:04.296330 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4373 10:52:04.299606 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4374 10:52:04.306294 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4375 10:52:04.309709 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4376 10:52:04.312572 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4377 10:52:04.316028 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4378 10:52:04.316109 ==
4379 10:52:04.319362 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 10:52:04.326112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 10:52:04.326191 ==
4382 10:52:04.326254 DQS Delay:
4383 10:52:04.329885 DQS0 = 0, DQS1 = 0
4384 10:52:04.329956 DQM Delay:
4385 10:52:04.330015 DQM0 = 55, DQM1 = 47
4386 10:52:04.332847 DQ Delay:
4387 10:52:04.335882 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4388 10:52:04.339455 DQ4 =56, DQ5 =48, DQ6 =60, DQ7 =64
4389 10:52:04.342490 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4390 10:52:04.346243 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4391 10:52:04.346323
4392 10:52:04.346386
4393 10:52:04.353064 [DQSOSCAuto] RK1, (LSB)MR18= 0x6727, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4394 10:52:04.356313 CH0 RK1: MR19=808, MR18=6727
4395 10:52:04.362418 CH0_RK1: MR19=0x808, MR18=0x6727, DQSOSC=390, MR23=63, INC=172, DEC=114
4396 10:52:04.365807 [RxdqsGatingPostProcess] freq 600
4397 10:52:04.369475 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4398 10:52:04.372612 Pre-setting of DQS Precalculation
4399 10:52:04.378846 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4400 10:52:04.378926 ==
4401 10:52:04.382738 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 10:52:04.385901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 10:52:04.385974 ==
4404 10:52:04.392668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 10:52:04.399305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4406 10:52:04.402592 [CA 0] Center 35 (5~66) winsize 62
4407 10:52:04.405781 [CA 1] Center 36 (6~67) winsize 62
4408 10:52:04.408948 [CA 2] Center 34 (4~65) winsize 62
4409 10:52:04.412520 [CA 3] Center 34 (4~65) winsize 62
4410 10:52:04.416106 [CA 4] Center 34 (4~65) winsize 62
4411 10:52:04.419068 [CA 5] Center 34 (4~64) winsize 61
4412 10:52:04.419147
4413 10:52:04.422591 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4414 10:52:04.422665
4415 10:52:04.425903 [CATrainingPosCal] consider 1 rank data
4416 10:52:04.428952 u2DelayCellTimex100 = 270/100 ps
4417 10:52:04.432543 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4418 10:52:04.435725 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4419 10:52:04.438756 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 10:52:04.442399 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 10:52:04.445302 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 10:52:04.448956 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4423 10:52:04.449032
4424 10:52:04.455770 CA PerBit enable=1, Macro0, CA PI delay=34
4425 10:52:04.455849
4426 10:52:04.455914 [CBTSetCACLKResult] CA Dly = 34
4427 10:52:04.458909 CS Dly: 6 (0~37)
4428 10:52:04.458981 ==
4429 10:52:04.461997 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 10:52:04.465297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 10:52:04.465380 ==
4432 10:52:04.471855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 10:52:04.478920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4434 10:52:04.481990 [CA 0] Center 36 (5~67) winsize 63
4435 10:52:04.485802 [CA 1] Center 36 (5~67) winsize 63
4436 10:52:04.488935 [CA 2] Center 35 (4~66) winsize 63
4437 10:52:04.492356 [CA 3] Center 34 (4~65) winsize 62
4438 10:52:04.495529 [CA 4] Center 35 (4~66) winsize 63
4439 10:52:04.498721 [CA 5] Center 34 (3~65) winsize 63
4440 10:52:04.498794
4441 10:52:04.502214 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4442 10:52:04.502287
4443 10:52:04.505288 [CATrainingPosCal] consider 2 rank data
4444 10:52:04.509166 u2DelayCellTimex100 = 270/100 ps
4445 10:52:04.512297 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4446 10:52:04.515502 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4447 10:52:04.518547 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4448 10:52:04.522404 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 10:52:04.525061 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4450 10:52:04.528257 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4451 10:52:04.528332
4452 10:52:04.535256 CA PerBit enable=1, Macro0, CA PI delay=34
4453 10:52:04.535352
4454 10:52:04.538159 [CBTSetCACLKResult] CA Dly = 34
4455 10:52:04.538226 CS Dly: 6 (0~38)
4456 10:52:04.538285
4457 10:52:04.541760 ----->DramcWriteLeveling(PI) begin...
4458 10:52:04.541845 ==
4459 10:52:04.544921 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 10:52:04.548635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 10:52:04.548719 ==
4462 10:52:04.551718 Write leveling (Byte 0): 31 => 31
4463 10:52:04.555294 Write leveling (Byte 1): 32 => 32
4464 10:52:04.558384 DramcWriteLeveling(PI) end<-----
4465 10:52:04.558467
4466 10:52:04.558536 ==
4467 10:52:04.561678 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 10:52:04.568507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 10:52:04.568604 ==
4470 10:52:04.568672 [Gating] SW mode calibration
4471 10:52:04.578501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 10:52:04.581635 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4473 10:52:04.584916 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 10:52:04.591508 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 10:52:04.595294 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4476 10:52:04.598358 0 9 12 | B1->B0 | 2d2d 2e2e | 1 1 | (0 1) (1 0)
4477 10:52:04.605126 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 10:52:04.608174 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 10:52:04.611276 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 10:52:04.618288 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 10:52:04.621462 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 10:52:04.625169 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 10:52:04.631691 0 10 8 | B1->B0 | 2424 2525 | 0 1 | (0 0) (0 0)
4484 10:52:04.634723 0 10 12 | B1->B0 | 3434 3939 | 0 0 | (0 0) (0 0)
4485 10:52:04.638385 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 10:52:04.644586 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 10:52:04.648018 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 10:52:04.651555 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 10:52:04.657949 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 10:52:04.661579 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 10:52:04.664701 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4492 10:52:04.671701 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4493 10:52:04.674681 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4494 10:52:04.677833 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 10:52:04.684764 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 10:52:04.687816 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 10:52:04.690897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 10:52:04.697514 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 10:52:04.701097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 10:52:04.704179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 10:52:04.710980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 10:52:04.714169 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 10:52:04.717870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 10:52:04.721098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 10:52:04.727323 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 10:52:04.730577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 10:52:04.734308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4508 10:52:04.740841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4509 10:52:04.743853 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 10:52:04.747719 Total UI for P1: 0, mck2ui 16
4511 10:52:04.750692 best dqsien dly found for B0: ( 0, 13, 10)
4512 10:52:04.753834 Total UI for P1: 0, mck2ui 16
4513 10:52:04.757408 best dqsien dly found for B1: ( 0, 13, 10)
4514 10:52:04.760931 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4515 10:52:04.764377 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4516 10:52:04.764459
4517 10:52:04.767761 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4518 10:52:04.770902 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4519 10:52:04.774091 [Gating] SW calibration Done
4520 10:52:04.774172 ==
4521 10:52:04.777248 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 10:52:04.784316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 10:52:04.784398 ==
4524 10:52:04.784463 RX Vref Scan: 0
4525 10:52:04.784522
4526 10:52:04.787622 RX Vref 0 -> 0, step: 1
4527 10:52:04.787704
4528 10:52:04.790501 RX Delay -230 -> 252, step: 16
4529 10:52:04.794189 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4530 10:52:04.797497 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4531 10:52:04.800945 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4532 10:52:04.807458 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4533 10:52:04.810674 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4534 10:52:04.813808 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4535 10:52:04.817422 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4536 10:52:04.820474 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4537 10:52:04.827285 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4538 10:52:04.830526 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4539 10:52:04.833684 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4540 10:52:04.837407 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4541 10:52:04.843596 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4542 10:52:04.847252 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4543 10:52:04.850208 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4544 10:52:04.853847 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4545 10:52:04.853951 ==
4546 10:52:04.856948 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 10:52:04.863602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 10:52:04.863677 ==
4549 10:52:04.863744 DQS Delay:
4550 10:52:04.867239 DQS0 = 0, DQS1 = 0
4551 10:52:04.867365 DQM Delay:
4552 10:52:04.867432 DQM0 = 50, DQM1 = 50
4553 10:52:04.870123 DQ Delay:
4554 10:52:04.873698 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4555 10:52:04.876633 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4556 10:52:04.880270 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4557 10:52:04.883545 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4558 10:52:04.883630
4559 10:52:04.883695
4560 10:52:04.883753 ==
4561 10:52:04.886698 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 10:52:04.890572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 10:52:04.890655 ==
4564 10:52:04.890721
4565 10:52:04.890780
4566 10:52:04.893674 TX Vref Scan disable
4567 10:52:04.893766 == TX Byte 0 ==
4568 10:52:04.900445 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4569 10:52:04.903671 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4570 10:52:04.903749 == TX Byte 1 ==
4571 10:52:04.910115 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4572 10:52:04.913693 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4573 10:52:04.913764 ==
4574 10:52:04.916818 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 10:52:04.920433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 10:52:04.920505 ==
4577 10:52:04.920566
4578 10:52:04.920622
4579 10:52:04.923406 TX Vref Scan disable
4580 10:52:04.927207 == TX Byte 0 ==
4581 10:52:04.930299 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4582 10:52:04.933380 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4583 10:52:04.937003 == TX Byte 1 ==
4584 10:52:04.940125 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4585 10:52:04.943259 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4586 10:52:04.947077
4587 10:52:04.947146 [DATLAT]
4588 10:52:04.947205 Freq=600, CH1 RK0
4589 10:52:04.947263
4590 10:52:04.950312 DATLAT Default: 0x9
4591 10:52:04.950386 0, 0xFFFF, sum = 0
4592 10:52:04.953354 1, 0xFFFF, sum = 0
4593 10:52:04.953478 2, 0xFFFF, sum = 0
4594 10:52:04.957050 3, 0xFFFF, sum = 0
4595 10:52:04.957134 4, 0xFFFF, sum = 0
4596 10:52:04.960047 5, 0xFFFF, sum = 0
4597 10:52:04.960131 6, 0xFFFF, sum = 0
4598 10:52:04.963926 7, 0xFFFF, sum = 0
4599 10:52:04.964010 8, 0x0, sum = 1
4600 10:52:04.966903 9, 0x0, sum = 2
4601 10:52:04.966987 10, 0x0, sum = 3
4602 10:52:04.970422 11, 0x0, sum = 4
4603 10:52:04.970507 best_step = 9
4604 10:52:04.970572
4605 10:52:04.970633 ==
4606 10:52:04.973299 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 10:52:04.979893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 10:52:04.979976 ==
4609 10:52:04.980041 RX Vref Scan: 1
4610 10:52:04.980100
4611 10:52:04.983530 RX Vref 0 -> 0, step: 1
4612 10:52:04.983612
4613 10:52:04.986528 RX Delay -163 -> 252, step: 8
4614 10:52:04.986610
4615 10:52:04.990280 Set Vref, RX VrefLevel [Byte0]: 55
4616 10:52:04.993488 [Byte1]: 47
4617 10:52:04.993570
4618 10:52:04.996630 Final RX Vref Byte 0 = 55 to rank0
4619 10:52:04.999739 Final RX Vref Byte 1 = 47 to rank0
4620 10:52:05.003300 Final RX Vref Byte 0 = 55 to rank1
4621 10:52:05.006536 Final RX Vref Byte 1 = 47 to rank1==
4622 10:52:05.009621 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 10:52:05.013095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 10:52:05.013177 ==
4625 10:52:05.016635 DQS Delay:
4626 10:52:05.016717 DQS0 = 0, DQS1 = 0
4627 10:52:05.016782 DQM Delay:
4628 10:52:05.020089 DQM0 = 48, DQM1 = 45
4629 10:52:05.020172 DQ Delay:
4630 10:52:05.023609 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4631 10:52:05.026551 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4632 10:52:05.030261 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4633 10:52:05.033425 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4634 10:52:05.033507
4635 10:52:05.033571
4636 10:52:05.043050 [DQSOSCAuto] RK0, (LSB)MR18= 0x486d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4637 10:52:05.043134 CH1 RK0: MR19=808, MR18=486D
4638 10:52:05.049902 CH1_RK0: MR19=0x808, MR18=0x486D, DQSOSC=389, MR23=63, INC=173, DEC=115
4639 10:52:05.049986
4640 10:52:05.053036 ----->DramcWriteLeveling(PI) begin...
4641 10:52:05.056639 ==
4642 10:52:05.056723 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 10:52:05.063034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 10:52:05.063146 ==
4645 10:52:05.066540 Write leveling (Byte 0): 29 => 29
4646 10:52:05.070161 Write leveling (Byte 1): 31 => 31
4647 10:52:05.073176 DramcWriteLeveling(PI) end<-----
4648 10:52:05.073259
4649 10:52:05.073342 ==
4650 10:52:05.076387 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 10:52:05.079823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 10:52:05.079908 ==
4653 10:52:05.083316 [Gating] SW mode calibration
4654 10:52:05.090050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 10:52:05.093021 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 10:52:05.099927 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 10:52:05.102980 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 10:52:05.106627 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4659 10:52:05.113436 0 9 12 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (1 1)
4660 10:52:05.116645 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 10:52:05.119928 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 10:52:05.126445 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 10:52:05.129728 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 10:52:05.133288 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 10:52:05.139784 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 10:52:05.142923 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 10:52:05.146774 0 10 12 | B1->B0 | 3c3c 3636 | 0 0 | (0 0) (0 0)
4668 10:52:05.152947 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 10:52:05.156173 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 10:52:05.159744 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 10:52:05.166153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 10:52:05.169797 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 10:52:05.172761 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 10:52:05.179970 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 10:52:05.183156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4676 10:52:05.186653 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 10:52:05.190208 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 10:52:05.196309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 10:52:05.199901 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 10:52:05.202868 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 10:52:05.209706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 10:52:05.212968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 10:52:05.216111 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 10:52:05.223119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 10:52:05.226347 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 10:52:05.229427 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 10:52:05.236579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 10:52:05.239498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 10:52:05.242958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:52:05.249396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4691 10:52:05.252645 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4692 10:52:05.256432 Total UI for P1: 0, mck2ui 16
4693 10:52:05.259613 best dqsien dly found for B1: ( 0, 13, 8)
4694 10:52:05.262567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 10:52:05.266481 Total UI for P1: 0, mck2ui 16
4696 10:52:05.269492 best dqsien dly found for B0: ( 0, 13, 10)
4697 10:52:05.272665 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4698 10:52:05.275805 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4699 10:52:05.275886
4700 10:52:05.282472 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 10:52:05.285868 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4702 10:52:05.285950 [Gating] SW calibration Done
4703 10:52:05.289623 ==
4704 10:52:05.292623 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 10:52:05.296379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 10:52:05.296461 ==
4707 10:52:05.296525 RX Vref Scan: 0
4708 10:52:05.296585
4709 10:52:05.299300 RX Vref 0 -> 0, step: 1
4710 10:52:05.299404
4711 10:52:05.302866 RX Delay -230 -> 252, step: 16
4712 10:52:05.305791 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4713 10:52:05.309752 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4714 10:52:05.315758 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4715 10:52:05.319441 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4716 10:52:05.322606 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4717 10:52:05.325897 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4718 10:52:05.329007 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4719 10:52:05.335763 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4720 10:52:05.338849 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4721 10:52:05.342601 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4722 10:52:05.345650 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4723 10:52:05.352427 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4724 10:52:05.355475 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4725 10:52:05.359253 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4726 10:52:05.362427 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4727 10:52:05.369157 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4728 10:52:05.369237 ==
4729 10:52:05.372148 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 10:52:05.375775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 10:52:05.375845 ==
4732 10:52:05.375909 DQS Delay:
4733 10:52:05.378897 DQS0 = 0, DQS1 = 0
4734 10:52:05.378966 DQM Delay:
4735 10:52:05.382727 DQM0 = 49, DQM1 = 46
4736 10:52:05.382795 DQ Delay:
4737 10:52:05.385893 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4738 10:52:05.388858 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4739 10:52:05.392425 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4740 10:52:05.395917 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4741 10:52:05.395987
4742 10:52:05.396046
4743 10:52:05.396103 ==
4744 10:52:05.399068 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 10:52:05.402271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 10:52:05.402345 ==
4747 10:52:05.402403
4748 10:52:05.402459
4749 10:52:05.405838 TX Vref Scan disable
4750 10:52:05.409319 == TX Byte 0 ==
4751 10:52:05.412233 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4752 10:52:05.415896 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4753 10:52:05.419086 == TX Byte 1 ==
4754 10:52:05.422160 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4755 10:52:05.425935 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4756 10:52:05.426035 ==
4757 10:52:05.429160 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 10:52:05.435543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 10:52:05.435616 ==
4760 10:52:05.435678
4761 10:52:05.435737
4762 10:52:05.435793 TX Vref Scan disable
4763 10:52:05.439831 == TX Byte 0 ==
4764 10:52:05.442895 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4765 10:52:05.446680 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4766 10:52:05.449838 == TX Byte 1 ==
4767 10:52:05.453510 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4768 10:52:05.456638 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4769 10:52:05.460128
4770 10:52:05.460226 [DATLAT]
4771 10:52:05.460315 Freq=600, CH1 RK1
4772 10:52:05.460402
4773 10:52:05.463075 DATLAT Default: 0x9
4774 10:52:05.463145 0, 0xFFFF, sum = 0
4775 10:52:05.466951 1, 0xFFFF, sum = 0
4776 10:52:05.467024 2, 0xFFFF, sum = 0
4777 10:52:05.470069 3, 0xFFFF, sum = 0
4778 10:52:05.470138 4, 0xFFFF, sum = 0
4779 10:52:05.473357 5, 0xFFFF, sum = 0
4780 10:52:05.473428 6, 0xFFFF, sum = 0
4781 10:52:05.476849 7, 0xFFFF, sum = 0
4782 10:52:05.476918 8, 0x0, sum = 1
4783 10:52:05.480008 9, 0x0, sum = 2
4784 10:52:05.480076 10, 0x0, sum = 3
4785 10:52:05.483167 11, 0x0, sum = 4
4786 10:52:05.483257 best_step = 9
4787 10:52:05.483367
4788 10:52:05.483441 ==
4789 10:52:05.487004 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 10:52:05.493025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 10:52:05.493101 ==
4792 10:52:05.493162 RX Vref Scan: 0
4793 10:52:05.493221
4794 10:52:05.496858 RX Vref 0 -> 0, step: 1
4795 10:52:05.496952
4796 10:52:05.499929 RX Delay -163 -> 252, step: 8
4797 10:52:05.503460 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4798 10:52:05.506777 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4799 10:52:05.513021 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4800 10:52:05.516670 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4801 10:52:05.519712 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4802 10:52:05.523077 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4803 10:52:05.526584 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4804 10:52:05.533063 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4805 10:52:05.536685 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4806 10:52:05.539751 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4807 10:52:05.543541 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4808 10:52:05.549693 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4809 10:52:05.553379 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4810 10:52:05.556478 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4811 10:52:05.559740 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4812 10:52:05.562727 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4813 10:52:05.566151 ==
4814 10:52:05.566247 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 10:52:05.573347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 10:52:05.573420 ==
4817 10:52:05.573481 DQS Delay:
4818 10:52:05.576418 DQS0 = 0, DQS1 = 0
4819 10:52:05.576485 DQM Delay:
4820 10:52:05.579551 DQM0 = 48, DQM1 = 44
4821 10:52:05.579621 DQ Delay:
4822 10:52:05.583150 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4823 10:52:05.586312 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4824 10:52:05.589414 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4825 10:52:05.593262 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4826 10:52:05.593332
4827 10:52:05.593391
4828 10:52:05.599532 [DQSOSCAuto] RK1, (LSB)MR18= 0x671e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4829 10:52:05.602714 CH1 RK1: MR19=808, MR18=671E
4830 10:52:05.609567 CH1_RK1: MR19=0x808, MR18=0x671E, DQSOSC=390, MR23=63, INC=172, DEC=114
4831 10:52:05.612625 [RxdqsGatingPostProcess] freq 600
4832 10:52:05.619452 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4833 10:52:05.619532 Pre-setting of DQS Precalculation
4834 10:52:05.626025 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4835 10:52:05.632938 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4836 10:52:05.639839 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4837 10:52:05.639918
4838 10:52:05.639981
4839 10:52:05.642906 [Calibration Summary] 1200 Mbps
4840 10:52:05.642975 CH 0, Rank 0
4841 10:52:05.646143 SW Impedance : PASS
4842 10:52:05.649589 DUTY Scan : NO K
4843 10:52:05.649662 ZQ Calibration : PASS
4844 10:52:05.652704 Jitter Meter : NO K
4845 10:52:05.655811 CBT Training : PASS
4846 10:52:05.655879 Write leveling : PASS
4847 10:52:05.659617 RX DQS gating : PASS
4848 10:52:05.662690 RX DQ/DQS(RDDQC) : PASS
4849 10:52:05.662759 TX DQ/DQS : PASS
4850 10:52:05.665875 RX DATLAT : PASS
4851 10:52:05.669496 RX DQ/DQS(Engine): PASS
4852 10:52:05.669565 TX OE : NO K
4853 10:52:05.672428 All Pass.
4854 10:52:05.672501
4855 10:52:05.672562 CH 0, Rank 1
4856 10:52:05.676018 SW Impedance : PASS
4857 10:52:05.676087 DUTY Scan : NO K
4858 10:52:05.679071 ZQ Calibration : PASS
4859 10:52:05.682474 Jitter Meter : NO K
4860 10:52:05.682543 CBT Training : PASS
4861 10:52:05.686223 Write leveling : PASS
4862 10:52:05.686317 RX DQS gating : PASS
4863 10:52:05.689325 RX DQ/DQS(RDDQC) : PASS
4864 10:52:05.692427 TX DQ/DQS : PASS
4865 10:52:05.692496 RX DATLAT : PASS
4866 10:52:05.695722 RX DQ/DQS(Engine): PASS
4867 10:52:05.699320 TX OE : NO K
4868 10:52:05.699396 All Pass.
4869 10:52:05.699456
4870 10:52:05.699512 CH 1, Rank 0
4871 10:52:05.702490 SW Impedance : PASS
4872 10:52:05.705782 DUTY Scan : NO K
4873 10:52:05.705853 ZQ Calibration : PASS
4874 10:52:05.709441 Jitter Meter : NO K
4875 10:52:05.712555 CBT Training : PASS
4876 10:52:05.712625 Write leveling : PASS
4877 10:52:05.716393 RX DQS gating : PASS
4878 10:52:05.719475 RX DQ/DQS(RDDQC) : PASS
4879 10:52:05.719544 TX DQ/DQS : PASS
4880 10:52:05.723165 RX DATLAT : PASS
4881 10:52:05.723264 RX DQ/DQS(Engine): PASS
4882 10:52:05.726335 TX OE : NO K
4883 10:52:05.726433 All Pass.
4884 10:52:05.726503
4885 10:52:05.729322 CH 1, Rank 1
4886 10:52:05.729423 SW Impedance : PASS
4887 10:52:05.732439 DUTY Scan : NO K
4888 10:52:05.736153 ZQ Calibration : PASS
4889 10:52:05.736230 Jitter Meter : NO K
4890 10:52:05.739721 CBT Training : PASS
4891 10:52:05.743065 Write leveling : PASS
4892 10:52:05.743166 RX DQS gating : PASS
4893 10:52:05.746187 RX DQ/DQS(RDDQC) : PASS
4894 10:52:05.749179 TX DQ/DQS : PASS
4895 10:52:05.749250 RX DATLAT : PASS
4896 10:52:05.753041 RX DQ/DQS(Engine): PASS
4897 10:52:05.756009 TX OE : NO K
4898 10:52:05.756079 All Pass.
4899 10:52:05.756139
4900 10:52:05.759099 DramC Write-DBI off
4901 10:52:05.759171 PER_BANK_REFRESH: Hybrid Mode
4902 10:52:05.762931 TX_TRACKING: ON
4903 10:52:05.769262 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4904 10:52:05.772414 [FAST_K] Save calibration result to emmc
4905 10:52:05.779219 dramc_set_vcore_voltage set vcore to 662500
4906 10:52:05.779320 Read voltage for 933, 3
4907 10:52:05.782985 Vio18 = 0
4908 10:52:05.783053 Vcore = 662500
4909 10:52:05.783113 Vdram = 0
4910 10:52:05.786046 Vddq = 0
4911 10:52:05.786113 Vmddr = 0
4912 10:52:05.789602 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4913 10:52:05.796269 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4914 10:52:05.799511 MEM_TYPE=3, freq_sel=17
4915 10:52:05.799583 sv_algorithm_assistance_LP4_1600
4916 10:52:05.806332 ============ PULL DRAM RESETB DOWN ============
4917 10:52:05.809564 ========== PULL DRAM RESETB DOWN end =========
4918 10:52:05.812758 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4919 10:52:05.815832 ===================================
4920 10:52:05.819608 LPDDR4 DRAM CONFIGURATION
4921 10:52:05.822696 ===================================
4922 10:52:05.826193 EX_ROW_EN[0] = 0x0
4923 10:52:05.826357 EX_ROW_EN[1] = 0x0
4924 10:52:05.829333 LP4Y_EN = 0x0
4925 10:52:05.829430 WORK_FSP = 0x0
4926 10:52:05.833022 WL = 0x3
4927 10:52:05.833124 RL = 0x3
4928 10:52:05.835947 BL = 0x2
4929 10:52:05.836017 RPST = 0x0
4930 10:52:05.839138 RD_PRE = 0x0
4931 10:52:05.839237 WR_PRE = 0x1
4932 10:52:05.842938 WR_PST = 0x0
4933 10:52:05.843013 DBI_WR = 0x0
4934 10:52:05.845959 DBI_RD = 0x0
4935 10:52:05.846057 OTF = 0x1
4936 10:52:05.849483 ===================================
4937 10:52:05.852270 ===================================
4938 10:52:05.855965 ANA top config
4939 10:52:05.858962 ===================================
4940 10:52:05.862660 DLL_ASYNC_EN = 0
4941 10:52:05.862757 ALL_SLAVE_EN = 1
4942 10:52:05.865854 NEW_RANK_MODE = 1
4943 10:52:05.869039 DLL_IDLE_MODE = 1
4944 10:52:05.872231 LP45_APHY_COMB_EN = 1
4945 10:52:05.875512 TX_ODT_DIS = 1
4946 10:52:05.875609 NEW_8X_MODE = 1
4947 10:52:05.879212 ===================================
4948 10:52:05.882309 ===================================
4949 10:52:05.886089 data_rate = 1866
4950 10:52:05.889125 CKR = 1
4951 10:52:05.892651 DQ_P2S_RATIO = 8
4952 10:52:05.895466 ===================================
4953 10:52:05.899016 CA_P2S_RATIO = 8
4954 10:52:05.899088 DQ_CA_OPEN = 0
4955 10:52:05.902641 DQ_SEMI_OPEN = 0
4956 10:52:05.905511 CA_SEMI_OPEN = 0
4957 10:52:05.909277 CA_FULL_RATE = 0
4958 10:52:05.912368 DQ_CKDIV4_EN = 1
4959 10:52:05.915516 CA_CKDIV4_EN = 1
4960 10:52:05.915615 CA_PREDIV_EN = 0
4961 10:52:05.919255 PH8_DLY = 0
4962 10:52:05.922531 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4963 10:52:05.925683 DQ_AAMCK_DIV = 4
4964 10:52:05.929286 CA_AAMCK_DIV = 4
4965 10:52:05.932274 CA_ADMCK_DIV = 4
4966 10:52:05.932352 DQ_TRACK_CA_EN = 0
4967 10:52:05.935836 CA_PICK = 933
4968 10:52:05.938851 CA_MCKIO = 933
4969 10:52:05.942108 MCKIO_SEMI = 0
4970 10:52:05.945974 PLL_FREQ = 3732
4971 10:52:05.949038 DQ_UI_PI_RATIO = 32
4972 10:52:05.952649 CA_UI_PI_RATIO = 0
4973 10:52:05.955763 ===================================
4974 10:52:05.958730 ===================================
4975 10:52:05.958800 memory_type:LPDDR4
4976 10:52:05.962249 GP_NUM : 10
4977 10:52:05.965346 SRAM_EN : 1
4978 10:52:05.965420 MD32_EN : 0
4979 10:52:05.969033 ===================================
4980 10:52:05.972209 [ANA_INIT] >>>>>>>>>>>>>>
4981 10:52:05.975297 <<<<<< [CONFIGURE PHASE]: ANA_TX
4982 10:52:05.979062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4983 10:52:05.982314 ===================================
4984 10:52:05.985742 data_rate = 1866,PCW = 0X8f00
4985 10:52:05.988983 ===================================
4986 10:52:05.992128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4987 10:52:05.995221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 10:52:06.001968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 10:52:06.005503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4990 10:52:06.008846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4991 10:52:06.012208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4992 10:52:06.015014 [ANA_INIT] flow start
4993 10:52:06.018828 [ANA_INIT] PLL >>>>>>>>
4994 10:52:06.018912 [ANA_INIT] PLL <<<<<<<<
4995 10:52:06.021951 [ANA_INIT] MIDPI >>>>>>>>
4996 10:52:06.025076 [ANA_INIT] MIDPI <<<<<<<<
4997 10:52:06.025149 [ANA_INIT] DLL >>>>>>>>
4998 10:52:06.028272 [ANA_INIT] flow end
4999 10:52:06.032023 ============ LP4 DIFF to SE enter ============
5000 10:52:06.038214 ============ LP4 DIFF to SE exit ============
5001 10:52:06.038316 [ANA_INIT] <<<<<<<<<<<<<
5002 10:52:06.042186 [Flow] Enable top DCM control >>>>>
5003 10:52:06.045160 [Flow] Enable top DCM control <<<<<
5004 10:52:06.048950 Enable DLL master slave shuffle
5005 10:52:06.055112 ==============================================================
5006 10:52:06.055212 Gating Mode config
5007 10:52:06.061934 ==============================================================
5008 10:52:06.062008 Config description:
5009 10:52:06.072068 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5010 10:52:06.078958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5011 10:52:06.085407 SELPH_MODE 0: By rank 1: By Phase
5012 10:52:06.088862 ==============================================================
5013 10:52:06.091927 GAT_TRACK_EN = 1
5014 10:52:06.095623 RX_GATING_MODE = 2
5015 10:52:06.098727 RX_GATING_TRACK_MODE = 2
5016 10:52:06.102568 SELPH_MODE = 1
5017 10:52:06.105616 PICG_EARLY_EN = 1
5018 10:52:06.109035 VALID_LAT_VALUE = 1
5019 10:52:06.115538 ==============================================================
5020 10:52:06.118513 Enter into Gating configuration >>>>
5021 10:52:06.121940 Exit from Gating configuration <<<<
5022 10:52:06.122016 Enter into DVFS_PRE_config >>>>>
5023 10:52:06.135644 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5024 10:52:06.138762 Exit from DVFS_PRE_config <<<<<
5025 10:52:06.141796 Enter into PICG configuration >>>>
5026 10:52:06.145417 Exit from PICG configuration <<<<
5027 10:52:06.145490 [RX_INPUT] configuration >>>>>
5028 10:52:06.148928 [RX_INPUT] configuration <<<<<
5029 10:52:06.155268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5030 10:52:06.158856 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5031 10:52:06.165584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 10:52:06.171861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 10:52:06.178409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 10:52:06.185165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 10:52:06.188269 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5036 10:52:06.192092 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5037 10:52:06.198757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5038 10:52:06.201855 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5039 10:52:06.205631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5040 10:52:06.208787 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 10:52:06.211920 ===================================
5042 10:52:06.215562 LPDDR4 DRAM CONFIGURATION
5043 10:52:06.218549 ===================================
5044 10:52:06.222171 EX_ROW_EN[0] = 0x0
5045 10:52:06.222250 EX_ROW_EN[1] = 0x0
5046 10:52:06.225022 LP4Y_EN = 0x0
5047 10:52:06.225095 WORK_FSP = 0x0
5048 10:52:06.228614 WL = 0x3
5049 10:52:06.228709 RL = 0x3
5050 10:52:06.231714 BL = 0x2
5051 10:52:06.231788 RPST = 0x0
5052 10:52:06.235474 RD_PRE = 0x0
5053 10:52:06.235545 WR_PRE = 0x1
5054 10:52:06.238607 WR_PST = 0x0
5055 10:52:06.238676 DBI_WR = 0x0
5056 10:52:06.241701 DBI_RD = 0x0
5057 10:52:06.241787 OTF = 0x1
5058 10:52:06.245470 ===================================
5059 10:52:06.252271 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5060 10:52:06.255040 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5061 10:52:06.258764 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 10:52:06.261813 ===================================
5063 10:52:06.264942 LPDDR4 DRAM CONFIGURATION
5064 10:52:06.268542 ===================================
5065 10:52:06.271666 EX_ROW_EN[0] = 0x10
5066 10:52:06.271742 EX_ROW_EN[1] = 0x0
5067 10:52:06.275456 LP4Y_EN = 0x0
5068 10:52:06.275553 WORK_FSP = 0x0
5069 10:52:06.278652 WL = 0x3
5070 10:52:06.278726 RL = 0x3
5071 10:52:06.281801 BL = 0x2
5072 10:52:06.281872 RPST = 0x0
5073 10:52:06.284782 RD_PRE = 0x0
5074 10:52:06.284901 WR_PRE = 0x1
5075 10:52:06.288499 WR_PST = 0x0
5076 10:52:06.288582 DBI_WR = 0x0
5077 10:52:06.291449 DBI_RD = 0x0
5078 10:52:06.291544 OTF = 0x1
5079 10:52:06.295058 ===================================
5080 10:52:06.301831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5081 10:52:06.306325 nWR fixed to 30
5082 10:52:06.309372 [ModeRegInit_LP4] CH0 RK0
5083 10:52:06.309454 [ModeRegInit_LP4] CH0 RK1
5084 10:52:06.313138 [ModeRegInit_LP4] CH1 RK0
5085 10:52:06.316127 [ModeRegInit_LP4] CH1 RK1
5086 10:52:06.316209 match AC timing 9
5087 10:52:06.322580 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5088 10:52:06.325655 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5089 10:52:06.329025 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5090 10:52:06.336181 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5091 10:52:06.339442 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5092 10:52:06.339525 ==
5093 10:52:06.342547 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 10:52:06.345717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 10:52:06.345800 ==
5096 10:52:06.352626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 10:52:06.358936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5098 10:52:06.362402 [CA 0] Center 37 (6~68) winsize 63
5099 10:52:06.365829 [CA 1] Center 37 (6~68) winsize 63
5100 10:52:06.369279 [CA 2] Center 34 (4~65) winsize 62
5101 10:52:06.372240 [CA 3] Center 34 (3~65) winsize 63
5102 10:52:06.375814 [CA 4] Center 33 (3~64) winsize 62
5103 10:52:06.378951 [CA 5] Center 32 (2~62) winsize 61
5104 10:52:06.379054
5105 10:52:06.382056 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5106 10:52:06.382182
5107 10:52:06.385379 [CATrainingPosCal] consider 1 rank data
5108 10:52:06.388829 u2DelayCellTimex100 = 270/100 ps
5109 10:52:06.391986 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5110 10:52:06.395632 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5111 10:52:06.399223 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5112 10:52:06.402174 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5113 10:52:06.405596 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5114 10:52:06.412542 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5115 10:52:06.412622
5116 10:52:06.415668 CA PerBit enable=1, Macro0, CA PI delay=32
5117 10:52:06.415751
5118 10:52:06.418857 [CBTSetCACLKResult] CA Dly = 32
5119 10:52:06.418933 CS Dly: 5 (0~36)
5120 10:52:06.418995 ==
5121 10:52:06.422639 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 10:52:06.425662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 10:52:06.425740 ==
5124 10:52:06.432061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 10:52:06.438719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 10:52:06.442391 [CA 0] Center 37 (6~68) winsize 63
5127 10:52:06.445251 [CA 1] Center 37 (7~68) winsize 62
5128 10:52:06.449044 [CA 2] Center 34 (4~65) winsize 62
5129 10:52:06.452206 [CA 3] Center 34 (3~65) winsize 63
5130 10:52:06.455454 [CA 4] Center 33 (3~63) winsize 61
5131 10:52:06.458719 [CA 5] Center 32 (2~62) winsize 61
5132 10:52:06.458794
5133 10:52:06.461776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 10:52:06.461875
5135 10:52:06.465575 [CATrainingPosCal] consider 2 rank data
5136 10:52:06.468537 u2DelayCellTimex100 = 270/100 ps
5137 10:52:06.472253 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5138 10:52:06.475296 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5139 10:52:06.478742 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5140 10:52:06.482047 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5141 10:52:06.488846 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5142 10:52:06.491930 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5143 10:52:06.492014
5144 10:52:06.495522 CA PerBit enable=1, Macro0, CA PI delay=32
5145 10:52:06.495606
5146 10:52:06.498552 [CBTSetCACLKResult] CA Dly = 32
5147 10:52:06.498636 CS Dly: 5 (0~37)
5148 10:52:06.498701
5149 10:52:06.502313 ----->DramcWriteLeveling(PI) begin...
5150 10:52:06.502415 ==
5151 10:52:06.505095 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 10:52:06.511723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 10:52:06.511808 ==
5154 10:52:06.515301 Write leveling (Byte 0): 32 => 32
5155 10:52:06.518412 Write leveling (Byte 1): 32 => 32
5156 10:52:06.518523 DramcWriteLeveling(PI) end<-----
5157 10:52:06.518591
5158 10:52:06.522251 ==
5159 10:52:06.522335 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 10:52:06.528474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 10:52:06.528559 ==
5162 10:52:06.532078 [Gating] SW mode calibration
5163 10:52:06.538390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 10:52:06.542085 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5165 10:52:06.548315 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5166 10:52:06.551688 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 10:52:06.555240 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 10:52:06.561662 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 10:52:06.565544 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 10:52:06.568651 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 10:52:06.575250 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5172 10:52:06.578312 0 14 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 1)
5173 10:52:06.582009 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5174 10:52:06.588101 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 10:52:06.591466 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 10:52:06.595139 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 10:52:06.598728 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 10:52:06.604877 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 10:52:06.608793 0 15 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
5180 10:52:06.611665 0 15 28 | B1->B0 | 2828 3e3d | 0 1 | (0 0) (0 0)
5181 10:52:06.618288 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5182 10:52:06.621629 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 10:52:06.624685 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 10:52:06.631439 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 10:52:06.634718 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 10:52:06.638333 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 10:52:06.644676 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 10:52:06.648449 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5189 10:52:06.651552 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5190 10:52:06.658263 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 10:52:06.661251 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 10:52:06.664446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 10:52:06.671346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 10:52:06.674913 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 10:52:06.677923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 10:52:06.684958 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 10:52:06.688162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 10:52:06.691250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 10:52:06.697895 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 10:52:06.701367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 10:52:06.704287 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 10:52:06.711038 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 10:52:06.714271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5204 10:52:06.717826 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5205 10:52:06.720824 Total UI for P1: 0, mck2ui 16
5206 10:52:06.724361 best dqsien dly found for B0: ( 1, 2, 24)
5207 10:52:06.731460 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 10:52:06.731576 Total UI for P1: 0, mck2ui 16
5209 10:52:06.737630 best dqsien dly found for B1: ( 1, 2, 30)
5210 10:52:06.740696 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5211 10:52:06.743915 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5212 10:52:06.743989
5213 10:52:06.747727 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5214 10:52:06.750907 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5215 10:52:06.754122 [Gating] SW calibration Done
5216 10:52:06.754194 ==
5217 10:52:06.757134 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 10:52:06.760850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 10:52:06.760926 ==
5220 10:52:06.763941 RX Vref Scan: 0
5221 10:52:06.764026
5222 10:52:06.764093 RX Vref 0 -> 0, step: 1
5223 10:52:06.764151
5224 10:52:06.767698 RX Delay -80 -> 252, step: 8
5225 10:52:06.770707 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5226 10:52:06.777648 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5227 10:52:06.780595 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5228 10:52:06.784202 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5229 10:52:06.787206 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5230 10:52:06.790969 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5231 10:52:06.794153 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5232 10:52:06.800886 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5233 10:52:06.804174 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5234 10:52:06.807127 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5235 10:52:06.810682 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5236 10:52:06.814070 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5237 10:52:06.817086 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5238 10:52:06.823775 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5239 10:52:06.827245 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5240 10:52:06.830778 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5241 10:52:06.830854 ==
5242 10:52:06.833806 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 10:52:06.837321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 10:52:06.837398 ==
5245 10:52:06.840374 DQS Delay:
5246 10:52:06.840448 DQS0 = 0, DQS1 = 0
5247 10:52:06.844096 DQM Delay:
5248 10:52:06.844168 DQM0 = 104, DQM1 = 96
5249 10:52:06.844228 DQ Delay:
5250 10:52:06.847092 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5251 10:52:06.850398 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5252 10:52:06.854210 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5253 10:52:06.857306 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5254 10:52:06.860419
5255 10:52:06.860500
5256 10:52:06.860565 ==
5257 10:52:06.863865 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 10:52:06.867099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 10:52:06.867182 ==
5260 10:52:06.867247
5261 10:52:06.867307
5262 10:52:06.870299 TX Vref Scan disable
5263 10:52:06.870390 == TX Byte 0 ==
5264 10:52:06.876947 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5265 10:52:06.880709 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5266 10:52:06.880793 == TX Byte 1 ==
5267 10:52:06.887231 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5268 10:52:06.890747 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5269 10:52:06.890859 ==
5270 10:52:06.893868 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 10:52:06.897183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 10:52:06.897265 ==
5273 10:52:06.897329
5274 10:52:06.897388
5275 10:52:06.900179 TX Vref Scan disable
5276 10:52:06.904005 == TX Byte 0 ==
5277 10:52:06.907187 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 10:52:06.910482 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 10:52:06.913478 == TX Byte 1 ==
5280 10:52:06.917075 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5281 10:52:06.919948 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5282 10:52:06.920024
5283 10:52:06.923633 [DATLAT]
5284 10:52:06.923736 Freq=933, CH0 RK0
5285 10:52:06.923826
5286 10:52:06.927040 DATLAT Default: 0xd
5287 10:52:06.927111 0, 0xFFFF, sum = 0
5288 10:52:06.930093 1, 0xFFFF, sum = 0
5289 10:52:06.930201 2, 0xFFFF, sum = 0
5290 10:52:06.933620 3, 0xFFFF, sum = 0
5291 10:52:06.933697 4, 0xFFFF, sum = 0
5292 10:52:06.936521 5, 0xFFFF, sum = 0
5293 10:52:06.936596 6, 0xFFFF, sum = 0
5294 10:52:06.940042 7, 0xFFFF, sum = 0
5295 10:52:06.940114 8, 0xFFFF, sum = 0
5296 10:52:06.943700 9, 0xFFFF, sum = 0
5297 10:52:06.943770 10, 0x0, sum = 1
5298 10:52:06.946578 11, 0x0, sum = 2
5299 10:52:06.946676 12, 0x0, sum = 3
5300 10:52:06.949954 13, 0x0, sum = 4
5301 10:52:06.950054 best_step = 11
5302 10:52:06.950142
5303 10:52:06.950230 ==
5304 10:52:06.953025 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 10:52:06.959815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 10:52:06.959916 ==
5307 10:52:06.959981 RX Vref Scan: 1
5308 10:52:06.960042
5309 10:52:06.963513 RX Vref 0 -> 0, step: 1
5310 10:52:06.963580
5311 10:52:06.966598 RX Delay -45 -> 252, step: 4
5312 10:52:06.966666
5313 10:52:06.970295 Set Vref, RX VrefLevel [Byte0]: 56
5314 10:52:06.973560 [Byte1]: 49
5315 10:52:06.973631
5316 10:52:06.976651 Final RX Vref Byte 0 = 56 to rank0
5317 10:52:06.980202 Final RX Vref Byte 1 = 49 to rank0
5318 10:52:06.983284 Final RX Vref Byte 0 = 56 to rank1
5319 10:52:06.987082 Final RX Vref Byte 1 = 49 to rank1==
5320 10:52:06.989952 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 10:52:06.993608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 10:52:06.993681 ==
5323 10:52:06.996690 DQS Delay:
5324 10:52:06.996761 DQS0 = 0, DQS1 = 0
5325 10:52:06.996824 DQM Delay:
5326 10:52:06.999783 DQM0 = 104, DQM1 = 95
5327 10:52:06.999877 DQ Delay:
5328 10:52:07.003538 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5329 10:52:07.006647 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5330 10:52:07.009887 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5331 10:52:07.013564 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5332 10:52:07.013635
5333 10:52:07.016622
5334 10:52:07.023607 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5335 10:52:07.026652 CH0 RK0: MR19=505, MR18=342C
5336 10:52:07.033248 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5337 10:52:07.033329
5338 10:52:07.036759 ----->DramcWriteLeveling(PI) begin...
5339 10:52:07.036833 ==
5340 10:52:07.039690 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 10:52:07.043302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 10:52:07.043396 ==
5343 10:52:07.046442 Write leveling (Byte 0): 33 => 33
5344 10:52:07.049944 Write leveling (Byte 1): 30 => 30
5345 10:52:07.053228 DramcWriteLeveling(PI) end<-----
5346 10:52:07.053302
5347 10:52:07.053364 ==
5348 10:52:07.056737 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 10:52:07.059550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 10:52:07.059622 ==
5351 10:52:07.063277 [Gating] SW mode calibration
5352 10:52:07.070256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 10:52:07.076680 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 10:52:07.079725 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5355 10:52:07.083335 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 10:52:07.089653 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 10:52:07.093268 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 10:52:07.096394 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 10:52:07.103222 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 10:52:07.106419 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5361 10:52:07.110079 0 14 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 1) (1 0)
5362 10:52:07.116335 0 15 0 | B1->B0 | 2525 2929 | 0 0 | (1 1) (1 1)
5363 10:52:07.119478 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 10:52:07.122689 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 10:52:07.129555 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 10:52:07.132708 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 10:52:07.135931 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 10:52:07.142623 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5369 10:52:07.146190 0 15 28 | B1->B0 | 3f3f 3736 | 0 1 | (0 0) (0 0)
5370 10:52:07.149417 1 0 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
5371 10:52:07.156284 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 10:52:07.159257 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 10:52:07.162688 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 10:52:07.166093 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 10:52:07.172673 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 10:52:07.176366 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 10:52:07.179656 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5378 10:52:07.186030 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 10:52:07.189757 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 10:52:07.192678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 10:52:07.199081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 10:52:07.202896 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 10:52:07.206135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 10:52:07.212787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 10:52:07.215829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 10:52:07.218927 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 10:52:07.225861 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 10:52:07.229041 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 10:52:07.232861 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 10:52:07.239436 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 10:52:07.242950 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 10:52:07.246145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5393 10:52:07.252817 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5394 10:52:07.255889 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 10:52:07.259306 Total UI for P1: 0, mck2ui 16
5396 10:52:07.262523 best dqsien dly found for B0: ( 1, 2, 26)
5397 10:52:07.266177 Total UI for P1: 0, mck2ui 16
5398 10:52:07.269235 best dqsien dly found for B1: ( 1, 2, 28)
5399 10:52:07.272794 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5400 10:52:07.275942 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5401 10:52:07.276025
5402 10:52:07.279377 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5403 10:52:07.282593 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5404 10:52:07.285762 [Gating] SW calibration Done
5405 10:52:07.285844 ==
5406 10:52:07.288967 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 10:52:07.292745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 10:52:07.292828 ==
5409 10:52:07.295780 RX Vref Scan: 0
5410 10:52:07.295863
5411 10:52:07.299448 RX Vref 0 -> 0, step: 1
5412 10:52:07.299531
5413 10:52:07.299615 RX Delay -80 -> 252, step: 8
5414 10:52:07.306031 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5415 10:52:07.309043 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5416 10:52:07.312244 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5417 10:52:07.315901 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5418 10:52:07.318946 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5419 10:52:07.325770 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5420 10:52:07.329055 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5421 10:52:07.332627 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5422 10:52:07.335788 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5423 10:52:07.338936 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5424 10:52:07.342049 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5425 10:52:07.348734 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5426 10:52:07.352477 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5427 10:52:07.355698 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5428 10:52:07.358694 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5429 10:52:07.362416 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5430 10:52:07.362500 ==
5431 10:52:07.365305 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 10:52:07.372092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 10:52:07.372175 ==
5434 10:52:07.372239 DQS Delay:
5435 10:52:07.375844 DQS0 = 0, DQS1 = 0
5436 10:52:07.375926 DQM Delay:
5437 10:52:07.375991 DQM0 = 105, DQM1 = 94
5438 10:52:07.378894 DQ Delay:
5439 10:52:07.382395 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =99
5440 10:52:07.385260 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5441 10:52:07.388773 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5442 10:52:07.391934 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5443 10:52:07.392018
5444 10:52:07.392083
5445 10:52:07.392142 ==
5446 10:52:07.395793 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 10:52:07.398902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 10:52:07.398984 ==
5449 10:52:07.399047
5450 10:52:07.399105
5451 10:52:07.402126 TX Vref Scan disable
5452 10:52:07.405799 == TX Byte 0 ==
5453 10:52:07.408730 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5454 10:52:07.412137 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5455 10:52:07.415148 == TX Byte 1 ==
5456 10:52:07.418301 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5457 10:52:07.422104 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5458 10:52:07.422199 ==
5459 10:52:07.425167 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 10:52:07.432105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 10:52:07.432188 ==
5462 10:52:07.432252
5463 10:52:07.432312
5464 10:52:07.432369 TX Vref Scan disable
5465 10:52:07.435967 == TX Byte 0 ==
5466 10:52:07.439231 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5467 10:52:07.446167 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5468 10:52:07.446252 == TX Byte 1 ==
5469 10:52:07.449300 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5470 10:52:07.456122 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5471 10:52:07.456208
5472 10:52:07.456293 [DATLAT]
5473 10:52:07.456373 Freq=933, CH0 RK1
5474 10:52:07.456461
5475 10:52:07.459292 DATLAT Default: 0xb
5476 10:52:07.459446 0, 0xFFFF, sum = 0
5477 10:52:07.462919 1, 0xFFFF, sum = 0
5478 10:52:07.463022 2, 0xFFFF, sum = 0
5479 10:52:07.465622 3, 0xFFFF, sum = 0
5480 10:52:07.465706 4, 0xFFFF, sum = 0
5481 10:52:07.469293 5, 0xFFFF, sum = 0
5482 10:52:07.472310 6, 0xFFFF, sum = 0
5483 10:52:07.472393 7, 0xFFFF, sum = 0
5484 10:52:07.475996 8, 0xFFFF, sum = 0
5485 10:52:07.476079 9, 0xFFFF, sum = 0
5486 10:52:07.479109 10, 0x0, sum = 1
5487 10:52:07.479191 11, 0x0, sum = 2
5488 10:52:07.479257 12, 0x0, sum = 3
5489 10:52:07.482301 13, 0x0, sum = 4
5490 10:52:07.482384 best_step = 11
5491 10:52:07.482449
5492 10:52:07.485978 ==
5493 10:52:07.486059 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 10:52:07.492146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 10:52:07.492229 ==
5496 10:52:07.492294 RX Vref Scan: 0
5497 10:52:07.492353
5498 10:52:07.495592 RX Vref 0 -> 0, step: 1
5499 10:52:07.495673
5500 10:52:07.499252 RX Delay -45 -> 252, step: 4
5501 10:52:07.502396 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5502 10:52:07.508782 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5503 10:52:07.512478 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5504 10:52:07.515539 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5505 10:52:07.518979 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5506 10:52:07.522640 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5507 10:52:07.528769 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5508 10:52:07.532426 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5509 10:52:07.535517 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5510 10:52:07.538712 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5511 10:52:07.541932 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5512 10:52:07.545696 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5513 10:52:07.551885 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5514 10:52:07.555486 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5515 10:52:07.558605 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5516 10:52:07.561746 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5517 10:52:07.561842 ==
5518 10:52:07.564922 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 10:52:07.572007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 10:52:07.572121 ==
5521 10:52:07.572202 DQS Delay:
5522 10:52:07.575185 DQS0 = 0, DQS1 = 0
5523 10:52:07.575268 DQM Delay:
5524 10:52:07.575357 DQM0 = 104, DQM1 = 94
5525 10:52:07.578816 DQ Delay:
5526 10:52:07.581799 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100
5527 10:52:07.585196 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5528 10:52:07.588230 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5529 10:52:07.591454 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5530 10:52:07.591549
5531 10:52:07.591623
5532 10:52:07.598274 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5533 10:52:07.601416 CH0 RK1: MR19=505, MR18=2D05
5534 10:52:07.608294 CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43
5535 10:52:07.611345 [RxdqsGatingPostProcess] freq 933
5536 10:52:07.618424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5537 10:52:07.621661 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 10:52:07.621834 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 10:52:07.625343 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 10:52:07.628095 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 10:52:07.631737 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 10:52:07.635360 best DQS1 dly(2T, 0.5T) = (0, 10)
5543 10:52:07.638326 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 10:52:07.641552 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5545 10:52:07.645438 Pre-setting of DQS Precalculation
5546 10:52:07.651925 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5547 10:52:07.652284 ==
5548 10:52:07.655087 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 10:52:07.658853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 10:52:07.659214 ==
5551 10:52:07.665553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 10:52:07.668613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5553 10:52:07.672472 [CA 0] Center 36 (6~67) winsize 62
5554 10:52:07.675636 [CA 1] Center 37 (6~68) winsize 63
5555 10:52:07.678838 [CA 2] Center 34 (4~65) winsize 62
5556 10:52:07.682599 [CA 3] Center 34 (4~65) winsize 62
5557 10:52:07.685531 [CA 4] Center 34 (4~65) winsize 62
5558 10:52:07.689051 [CA 5] Center 33 (3~64) winsize 62
5559 10:52:07.689378
5560 10:52:07.692126 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5561 10:52:07.692453
5562 10:52:07.695862 [CATrainingPosCal] consider 1 rank data
5563 10:52:07.699316 u2DelayCellTimex100 = 270/100 ps
5564 10:52:07.702363 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 10:52:07.708764 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5566 10:52:07.712295 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 10:52:07.715471 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 10:52:07.718598 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 10:52:07.722443 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 10:52:07.722806
5571 10:52:07.725629 CA PerBit enable=1, Macro0, CA PI delay=33
5572 10:52:07.726048
5573 10:52:07.728906 [CBTSetCACLKResult] CA Dly = 33
5574 10:52:07.729407 CS Dly: 7 (0~38)
5575 10:52:07.732092 ==
5576 10:52:07.735725 Dram Type= 6, Freq= 0, CH_1, rank 1
5577 10:52:07.738824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 10:52:07.739191 ==
5579 10:52:07.742286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 10:52:07.748844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5581 10:52:07.752739 [CA 0] Center 37 (6~68) winsize 63
5582 10:52:07.755926 [CA 1] Center 37 (6~68) winsize 63
5583 10:52:07.759268 [CA 2] Center 35 (5~66) winsize 62
5584 10:52:07.762727 [CA 3] Center 34 (4~65) winsize 62
5585 10:52:07.765579 [CA 4] Center 34 (4~65) winsize 62
5586 10:52:07.769255 [CA 5] Center 34 (4~64) winsize 61
5587 10:52:07.769621
5588 10:52:07.772235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5589 10:52:07.772601
5590 10:52:07.775433 [CATrainingPosCal] consider 2 rank data
5591 10:52:07.778836 u2DelayCellTimex100 = 270/100 ps
5592 10:52:07.782631 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5593 10:52:07.788940 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5594 10:52:07.791953 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5595 10:52:07.795522 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5596 10:52:07.798560 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5597 10:52:07.802431 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5598 10:52:07.802845
5599 10:52:07.805613 CA PerBit enable=1, Macro0, CA PI delay=34
5600 10:52:07.805978
5601 10:52:07.808779 [CBTSetCACLKResult] CA Dly = 34
5602 10:52:07.809183 CS Dly: 8 (0~40)
5603 10:52:07.809535
5604 10:52:07.811842 ----->DramcWriteLeveling(PI) begin...
5605 10:52:07.815839 ==
5606 10:52:07.818970 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 10:52:07.822463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 10:52:07.823054 ==
5609 10:52:07.825456 Write leveling (Byte 0): 26 => 26
5610 10:52:07.828738 Write leveling (Byte 1): 28 => 28
5611 10:52:07.831950 DramcWriteLeveling(PI) end<-----
5612 10:52:07.832355
5613 10:52:07.832650 ==
5614 10:52:07.835696 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 10:52:07.838826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 10:52:07.839185 ==
5617 10:52:07.842001 [Gating] SW mode calibration
5618 10:52:07.848829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5619 10:52:07.855474 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5620 10:52:07.858385 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 10:52:07.861751 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 10:52:07.868221 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 10:52:07.872022 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 10:52:07.875598 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 10:52:07.881968 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5626 10:52:07.885093 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
5627 10:52:07.888352 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5628 10:52:07.892271 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 10:52:07.898513 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 10:52:07.901699 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 10:52:07.905040 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 10:52:07.911475 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 10:52:07.915418 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5634 10:52:07.918702 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5635 10:52:07.924953 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5636 10:52:07.928226 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 10:52:07.931800 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 10:52:07.938691 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 10:52:07.941964 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 10:52:07.945004 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 10:52:07.951519 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5642 10:52:07.954811 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5643 10:52:07.958541 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 10:52:07.964774 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 10:52:07.968253 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 10:52:07.971819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 10:52:07.978664 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 10:52:07.981559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 10:52:07.984870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 10:52:07.991798 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 10:52:07.995111 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 10:52:07.998344 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 10:52:08.001603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 10:52:08.008488 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 10:52:08.011365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 10:52:08.014889 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 10:52:08.021737 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5658 10:52:08.024878 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5659 10:52:08.028125 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 10:52:08.031234 Total UI for P1: 0, mck2ui 16
5661 10:52:08.034984 best dqsien dly found for B0: ( 1, 2, 22)
5662 10:52:08.038029 Total UI for P1: 0, mck2ui 16
5663 10:52:08.041694 best dqsien dly found for B1: ( 1, 2, 26)
5664 10:52:08.044871 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5665 10:52:08.048186 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5666 10:52:08.048576
5667 10:52:08.055062 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5668 10:52:08.058291 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5669 10:52:08.061476 [Gating] SW calibration Done
5670 10:52:08.061829 ==
5671 10:52:08.064662 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 10:52:08.067900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 10:52:08.068257 ==
5674 10:52:08.068587 RX Vref Scan: 0
5675 10:52:08.068853
5676 10:52:08.071545 RX Vref 0 -> 0, step: 1
5677 10:52:08.071895
5678 10:52:08.074974 RX Delay -80 -> 252, step: 8
5679 10:52:08.078092 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5680 10:52:08.081378 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5681 10:52:08.084933 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5682 10:52:08.091550 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5683 10:52:08.094819 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5684 10:52:08.098016 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5685 10:52:08.101190 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5686 10:52:08.105058 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5687 10:52:08.108475 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5688 10:52:08.114887 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5689 10:52:08.117804 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5690 10:52:08.121403 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5691 10:52:08.124969 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5692 10:52:08.127957 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5693 10:52:08.134956 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5694 10:52:08.138325 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5695 10:52:08.138742 ==
5696 10:52:08.141438 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 10:52:08.144772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 10:52:08.145185 ==
5699 10:52:08.145494 DQS Delay:
5700 10:52:08.147802 DQS0 = 0, DQS1 = 0
5701 10:52:08.148193 DQM Delay:
5702 10:52:08.151446 DQM0 = 103, DQM1 = 98
5703 10:52:08.151840 DQ Delay:
5704 10:52:08.154631 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5705 10:52:08.158238 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5706 10:52:08.161525 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5707 10:52:08.164575 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5708 10:52:08.164966
5709 10:52:08.165295
5710 10:52:08.167853 ==
5711 10:52:08.168264 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 10:52:08.174836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 10:52:08.175267 ==
5714 10:52:08.175630
5715 10:52:08.175984
5716 10:52:08.178009 TX Vref Scan disable
5717 10:52:08.178371 == TX Byte 0 ==
5718 10:52:08.181159 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 10:52:08.187819 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 10:52:08.188184 == TX Byte 1 ==
5721 10:52:08.191231 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5722 10:52:08.197646 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5723 10:52:08.198089 ==
5724 10:52:08.201128 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 10:52:08.204453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 10:52:08.204898 ==
5727 10:52:08.205214
5728 10:52:08.205537
5729 10:52:08.207593 TX Vref Scan disable
5730 10:52:08.210899 == TX Byte 0 ==
5731 10:52:08.214320 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 10:52:08.218335 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 10:52:08.221152 == TX Byte 1 ==
5734 10:52:08.224354 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5735 10:52:08.227359 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5736 10:52:08.227810
5737 10:52:08.228168 [DATLAT]
5738 10:52:08.231059 Freq=933, CH1 RK0
5739 10:52:08.231561
5740 10:52:08.234585 DATLAT Default: 0xd
5741 10:52:08.235040 0, 0xFFFF, sum = 0
5742 10:52:08.237741 1, 0xFFFF, sum = 0
5743 10:52:08.238141 2, 0xFFFF, sum = 0
5744 10:52:08.240796 3, 0xFFFF, sum = 0
5745 10:52:08.241239 4, 0xFFFF, sum = 0
5746 10:52:08.244033 5, 0xFFFF, sum = 0
5747 10:52:08.244471 6, 0xFFFF, sum = 0
5748 10:52:08.247817 7, 0xFFFF, sum = 0
5749 10:52:08.248216 8, 0xFFFF, sum = 0
5750 10:52:08.250922 9, 0xFFFF, sum = 0
5751 10:52:08.251383 10, 0x0, sum = 1
5752 10:52:08.253911 11, 0x0, sum = 2
5753 10:52:08.254353 12, 0x0, sum = 3
5754 10:52:08.257669 13, 0x0, sum = 4
5755 10:52:08.258065 best_step = 11
5756 10:52:08.258413
5757 10:52:08.258706 ==
5758 10:52:08.260747 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 10:52:08.263928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 10:52:08.267806 ==
5761 10:52:08.268198 RX Vref Scan: 1
5762 10:52:08.268537
5763 10:52:08.271041 RX Vref 0 -> 0, step: 1
5764 10:52:08.271514
5765 10:52:08.271831 RX Delay -45 -> 252, step: 4
5766 10:52:08.274311
5767 10:52:08.274799 Set Vref, RX VrefLevel [Byte0]: 55
5768 10:52:08.277488 [Byte1]: 47
5769 10:52:08.282668
5770 10:52:08.283161 Final RX Vref Byte 0 = 55 to rank0
5771 10:52:08.285675 Final RX Vref Byte 1 = 47 to rank0
5772 10:52:08.288808 Final RX Vref Byte 0 = 55 to rank1
5773 10:52:08.291926 Final RX Vref Byte 1 = 47 to rank1==
5774 10:52:08.295862 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 10:52:08.302191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 10:52:08.302582 ==
5777 10:52:08.302892 DQS Delay:
5778 10:52:08.303178 DQS0 = 0, DQS1 = 0
5779 10:52:08.305642 DQM Delay:
5780 10:52:08.306025 DQM0 = 103, DQM1 = 98
5781 10:52:08.308709 DQ Delay:
5782 10:52:08.312318 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5783 10:52:08.315557 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5784 10:52:08.318807 DQ8 =86, DQ9 =90, DQ10 =98, DQ11 =90
5785 10:52:08.321992 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =108
5786 10:52:08.322397
5787 10:52:08.322699
5788 10:52:08.328692 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5789 10:52:08.332431 CH1 RK0: MR19=505, MR18=162D
5790 10:52:08.338693 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5791 10:52:08.339232
5792 10:52:08.342142 ----->DramcWriteLeveling(PI) begin...
5793 10:52:08.342530 ==
5794 10:52:08.345207 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 10:52:08.348627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 10:52:08.349014 ==
5797 10:52:08.351803 Write leveling (Byte 0): 28 => 28
5798 10:52:08.355043 Write leveling (Byte 1): 30 => 30
5799 10:52:08.358926 DramcWriteLeveling(PI) end<-----
5800 10:52:08.359448
5801 10:52:08.359760 ==
5802 10:52:08.361993 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 10:52:08.369017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 10:52:08.369570 ==
5805 10:52:08.369891 [Gating] SW mode calibration
5806 10:52:08.378500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5807 10:52:08.381803 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5808 10:52:08.384984 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 10:52:08.391975 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 10:52:08.395671 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 10:52:08.398550 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 10:52:08.405573 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 10:52:08.408804 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 10:52:08.411863 0 14 24 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
5815 10:52:08.418850 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5816 10:52:08.421871 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 10:52:08.425299 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 10:52:08.431551 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 10:52:08.435446 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 10:52:08.438622 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 10:52:08.444891 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5822 10:52:08.448575 0 15 24 | B1->B0 | 3434 2929 | 0 1 | (0 0) (0 0)
5823 10:52:08.451446 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
5824 10:52:08.458463 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 10:52:08.461729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 10:52:08.464895 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 10:52:08.471792 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 10:52:08.475192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 10:52:08.477893 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 10:52:08.484754 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5831 10:52:08.488114 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 10:52:08.491307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 10:52:08.498269 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 10:52:08.501212 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 10:52:08.504433 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 10:52:08.511470 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 10:52:08.514743 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 10:52:08.517879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 10:52:08.524644 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 10:52:08.527406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 10:52:08.531219 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 10:52:08.534493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 10:52:08.541295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 10:52:08.544360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 10:52:08.547666 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 10:52:08.554086 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5847 10:52:08.557818 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5848 10:52:08.560866 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 10:52:08.563896 Total UI for P1: 0, mck2ui 16
5850 10:52:08.567722 best dqsien dly found for B0: ( 1, 2, 26)
5851 10:52:08.571064 Total UI for P1: 0, mck2ui 16
5852 10:52:08.574172 best dqsien dly found for B1: ( 1, 2, 26)
5853 10:52:08.577177 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5854 10:52:08.580963 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5855 10:52:08.584102
5856 10:52:08.587652 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5857 10:52:08.590750 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5858 10:52:08.594107 [Gating] SW calibration Done
5859 10:52:08.594499 ==
5860 10:52:08.597215 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 10:52:08.601051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 10:52:08.601446 ==
5863 10:52:08.601796 RX Vref Scan: 0
5864 10:52:08.602090
5865 10:52:08.604110 RX Vref 0 -> 0, step: 1
5866 10:52:08.604543
5867 10:52:08.607647 RX Delay -80 -> 252, step: 8
5868 10:52:08.610918 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5869 10:52:08.614099 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5870 10:52:08.621081 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5871 10:52:08.624558 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5872 10:52:08.627449 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5873 10:52:08.631111 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5874 10:52:08.634061 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5875 10:52:08.637197 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5876 10:52:08.644030 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5877 10:52:08.647739 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5878 10:52:08.650395 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5879 10:52:08.654133 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5880 10:52:08.657332 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5881 10:52:08.664235 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5882 10:52:08.667032 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5883 10:52:08.670493 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5884 10:52:08.670889 ==
5885 10:52:08.673598 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 10:52:08.677463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 10:52:08.677856 ==
5888 10:52:08.680570 DQS Delay:
5889 10:52:08.680996 DQS0 = 0, DQS1 = 0
5890 10:52:08.683829 DQM Delay:
5891 10:52:08.684220 DQM0 = 105, DQM1 = 99
5892 10:52:08.684564 DQ Delay:
5893 10:52:08.686959 DQ0 =107, DQ1 =103, DQ2 =95, DQ3 =103
5894 10:52:08.690704 DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103
5895 10:52:08.694217 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =95
5896 10:52:08.700738 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5897 10:52:08.701168
5898 10:52:08.701477
5899 10:52:08.701793 ==
5900 10:52:08.703901 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 10:52:08.707042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 10:52:08.707506 ==
5903 10:52:08.707821
5904 10:52:08.708147
5905 10:52:08.710295 TX Vref Scan disable
5906 10:52:08.710727 == TX Byte 0 ==
5907 10:52:08.717012 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5908 10:52:08.720257 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5909 10:52:08.720721 == TX Byte 1 ==
5910 10:52:08.727242 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5911 10:52:08.730452 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5912 10:52:08.730889 ==
5913 10:52:08.734051 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 10:52:08.737187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 10:52:08.737659 ==
5916 10:52:08.737973
5917 10:52:08.738297
5918 10:52:08.740293 TX Vref Scan disable
5919 10:52:08.743854 == TX Byte 0 ==
5920 10:52:08.747128 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5921 10:52:08.750165 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5922 10:52:08.753876 == TX Byte 1 ==
5923 10:52:08.757082 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5924 10:52:08.760281 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5925 10:52:08.760693
5926 10:52:08.764372 [DATLAT]
5927 10:52:08.764863 Freq=933, CH1 RK1
5928 10:52:08.765181
5929 10:52:08.767396 DATLAT Default: 0xb
5930 10:52:08.767785 0, 0xFFFF, sum = 0
5931 10:52:08.770372 1, 0xFFFF, sum = 0
5932 10:52:08.770764 2, 0xFFFF, sum = 0
5933 10:52:08.773467 3, 0xFFFF, sum = 0
5934 10:52:08.773877 4, 0xFFFF, sum = 0
5935 10:52:08.777231 5, 0xFFFF, sum = 0
5936 10:52:08.777629 6, 0xFFFF, sum = 0
5937 10:52:08.780232 7, 0xFFFF, sum = 0
5938 10:52:08.780621 8, 0xFFFF, sum = 0
5939 10:52:08.783802 9, 0xFFFF, sum = 0
5940 10:52:08.784227 10, 0x0, sum = 1
5941 10:52:08.787116 11, 0x0, sum = 2
5942 10:52:08.787525 12, 0x0, sum = 3
5943 10:52:08.790354 13, 0x0, sum = 4
5944 10:52:08.790748 best_step = 11
5945 10:52:08.791050
5946 10:52:08.791356 ==
5947 10:52:08.793477 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 10:52:08.800194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 10:52:08.800584 ==
5950 10:52:08.800890 RX Vref Scan: 0
5951 10:52:08.801175
5952 10:52:08.804036 RX Vref 0 -> 0, step: 1
5953 10:52:08.804421
5954 10:52:08.806771 RX Delay -45 -> 252, step: 4
5955 10:52:08.810422 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5956 10:52:08.813554 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5957 10:52:08.820433 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5958 10:52:08.823547 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5959 10:52:08.827460 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5960 10:52:08.830569 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5961 10:52:08.833814 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5962 10:52:08.840165 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5963 10:52:08.844033 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5964 10:52:08.847256 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5965 10:52:08.850186 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5966 10:52:08.853742 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5967 10:52:08.856823 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5968 10:52:08.863570 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5969 10:52:08.866966 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5970 10:52:08.870157 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5971 10:52:08.870553 ==
5972 10:52:08.873908 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 10:52:08.876908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 10:52:08.880115 ==
5975 10:52:08.880667 DQS Delay:
5976 10:52:08.881017 DQS0 = 0, DQS1 = 0
5977 10:52:08.883727 DQM Delay:
5978 10:52:08.884165 DQM0 = 104, DQM1 = 99
5979 10:52:08.886758 DQ Delay:
5980 10:52:08.889815 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5981 10:52:08.893457 DQ4 =100, DQ5 =116, DQ6 =112, DQ7 =104
5982 10:52:08.896686 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5983 10:52:08.899849 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =108
5984 10:52:08.900285
5985 10:52:08.900625
5986 10:52:08.906744 [DQSOSCAuto] RK1, (LSB)MR18= 0x3004, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5987 10:52:08.909896 CH1 RK1: MR19=505, MR18=3004
5988 10:52:08.916636 CH1_RK1: MR19=0x505, MR18=0x3004, DQSOSC=406, MR23=63, INC=65, DEC=43
5989 10:52:08.920060 [RxdqsGatingPostProcess] freq 933
5990 10:52:08.926809 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5991 10:52:08.927240 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 10:52:08.929994 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 10:52:08.933230 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 10:52:08.936490 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 10:52:08.939689 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 10:52:08.942705 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 10:52:08.946500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 10:52:08.949686 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 10:52:08.952858 Pre-setting of DQS Precalculation
6000 10:52:08.959675 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6001 10:52:08.966401 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6002 10:52:08.972858 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6003 10:52:08.973283
6004 10:52:08.973635
6005 10:52:08.975955 [Calibration Summary] 1866 Mbps
6006 10:52:08.976395 CH 0, Rank 0
6007 10:52:08.979871 SW Impedance : PASS
6008 10:52:08.982908 DUTY Scan : NO K
6009 10:52:08.983471 ZQ Calibration : PASS
6010 10:52:08.986040 Jitter Meter : NO K
6011 10:52:08.986507 CBT Training : PASS
6012 10:52:08.989702 Write leveling : PASS
6013 10:52:08.992747 RX DQS gating : PASS
6014 10:52:08.993192 RX DQ/DQS(RDDQC) : PASS
6015 10:52:08.996452 TX DQ/DQS : PASS
6016 10:52:08.999389 RX DATLAT : PASS
6017 10:52:08.999859 RX DQ/DQS(Engine): PASS
6018 10:52:09.002558 TX OE : NO K
6019 10:52:09.002991 All Pass.
6020 10:52:09.003390
6021 10:52:09.005765 CH 0, Rank 1
6022 10:52:09.006211 SW Impedance : PASS
6023 10:52:09.009631 DUTY Scan : NO K
6024 10:52:09.012764 ZQ Calibration : PASS
6025 10:52:09.013273 Jitter Meter : NO K
6026 10:52:09.015627 CBT Training : PASS
6027 10:52:09.019602 Write leveling : PASS
6028 10:52:09.020150 RX DQS gating : PASS
6029 10:52:09.022813 RX DQ/DQS(RDDQC) : PASS
6030 10:52:09.025792 TX DQ/DQS : PASS
6031 10:52:09.026223 RX DATLAT : PASS
6032 10:52:09.029216 RX DQ/DQS(Engine): PASS
6033 10:52:09.032904 TX OE : NO K
6034 10:52:09.033482 All Pass.
6035 10:52:09.034071
6036 10:52:09.034471 CH 1, Rank 0
6037 10:52:09.036146 SW Impedance : PASS
6038 10:52:09.039226 DUTY Scan : NO K
6039 10:52:09.039704 ZQ Calibration : PASS
6040 10:52:09.042541 Jitter Meter : NO K
6041 10:52:09.042975 CBT Training : PASS
6042 10:52:09.045545 Write leveling : PASS
6043 10:52:09.049396 RX DQS gating : PASS
6044 10:52:09.049832 RX DQ/DQS(RDDQC) : PASS
6045 10:52:09.052677 TX DQ/DQS : PASS
6046 10:52:09.055747 RX DATLAT : PASS
6047 10:52:09.056225 RX DQ/DQS(Engine): PASS
6048 10:52:09.058996 TX OE : NO K
6049 10:52:09.059461 All Pass.
6050 10:52:09.059799
6051 10:52:09.062728 CH 1, Rank 1
6052 10:52:09.063149 SW Impedance : PASS
6053 10:52:09.065731 DUTY Scan : NO K
6054 10:52:09.069392 ZQ Calibration : PASS
6055 10:52:09.069826 Jitter Meter : NO K
6056 10:52:09.072314 CBT Training : PASS
6057 10:52:09.075733 Write leveling : PASS
6058 10:52:09.076162 RX DQS gating : PASS
6059 10:52:09.079453 RX DQ/DQS(RDDQC) : PASS
6060 10:52:09.082641 TX DQ/DQS : PASS
6061 10:52:09.083080 RX DATLAT : PASS
6062 10:52:09.085725 RX DQ/DQS(Engine): PASS
6063 10:52:09.088804 TX OE : NO K
6064 10:52:09.089241 All Pass.
6065 10:52:09.089673
6066 10:52:09.090086 DramC Write-DBI off
6067 10:52:09.092734 PER_BANK_REFRESH: Hybrid Mode
6068 10:52:09.095973 TX_TRACKING: ON
6069 10:52:09.102293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6070 10:52:09.105956 [FAST_K] Save calibration result to emmc
6071 10:52:09.112247 dramc_set_vcore_voltage set vcore to 650000
6072 10:52:09.112680 Read voltage for 400, 6
6073 10:52:09.113284 Vio18 = 0
6074 10:52:09.115363 Vcore = 650000
6075 10:52:09.115791 Vdram = 0
6076 10:52:09.116123 Vddq = 0
6077 10:52:09.118959 Vmddr = 0
6078 10:52:09.122024 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6079 10:52:09.128937 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6080 10:52:09.132041 MEM_TYPE=3, freq_sel=20
6081 10:52:09.132640 sv_algorithm_assistance_LP4_800
6082 10:52:09.138464 ============ PULL DRAM RESETB DOWN ============
6083 10:52:09.142281 ========== PULL DRAM RESETB DOWN end =========
6084 10:52:09.145522 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6085 10:52:09.148576 ===================================
6086 10:52:09.152207 LPDDR4 DRAM CONFIGURATION
6087 10:52:09.155243 ===================================
6088 10:52:09.158474 EX_ROW_EN[0] = 0x0
6089 10:52:09.158892 EX_ROW_EN[1] = 0x0
6090 10:52:09.162176 LP4Y_EN = 0x0
6091 10:52:09.162593 WORK_FSP = 0x0
6092 10:52:09.165469 WL = 0x2
6093 10:52:09.165886 RL = 0x2
6094 10:52:09.168818 BL = 0x2
6095 10:52:09.169235 RPST = 0x0
6096 10:52:09.171936 RD_PRE = 0x0
6097 10:52:09.172376 WR_PRE = 0x1
6098 10:52:09.175456 WR_PST = 0x0
6099 10:52:09.175899 DBI_WR = 0x0
6100 10:52:09.179069 DBI_RD = 0x0
6101 10:52:09.179665 OTF = 0x1
6102 10:52:09.182039 ===================================
6103 10:52:09.185282 ===================================
6104 10:52:09.188503 ANA top config
6105 10:52:09.191698 ===================================
6106 10:52:09.195313 DLL_ASYNC_EN = 0
6107 10:52:09.195769 ALL_SLAVE_EN = 1
6108 10:52:09.198361 NEW_RANK_MODE = 1
6109 10:52:09.201786 DLL_IDLE_MODE = 1
6110 10:52:09.209164 LP45_APHY_COMB_EN = 1
6111 10:52:09.209588 TX_ODT_DIS = 1
6112 10:52:09.209997 NEW_8X_MODE = 1
6113 10:52:09.211941 ===================================
6114 10:52:09.215458 ===================================
6115 10:52:09.218661 data_rate = 800
6116 10:52:09.222007 CKR = 1
6117 10:52:09.225044 DQ_P2S_RATIO = 4
6118 10:52:09.228711 ===================================
6119 10:52:09.231675 CA_P2S_RATIO = 4
6120 10:52:09.232091 DQ_CA_OPEN = 0
6121 10:52:09.234952 DQ_SEMI_OPEN = 1
6122 10:52:09.238843 CA_SEMI_OPEN = 1
6123 10:52:09.241882 CA_FULL_RATE = 0
6124 10:52:09.244891 DQ_CKDIV4_EN = 0
6125 10:52:09.248326 CA_CKDIV4_EN = 1
6126 10:52:09.248741 CA_PREDIV_EN = 0
6127 10:52:09.251608 PH8_DLY = 0
6128 10:52:09.255409 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6129 10:52:09.258477 DQ_AAMCK_DIV = 0
6130 10:52:09.261444 CA_AAMCK_DIV = 0
6131 10:52:09.264747 CA_ADMCK_DIV = 4
6132 10:52:09.265136 DQ_TRACK_CA_EN = 0
6133 10:52:09.268600 CA_PICK = 800
6134 10:52:09.271808 CA_MCKIO = 400
6135 10:52:09.274984 MCKIO_SEMI = 400
6136 10:52:09.278363 PLL_FREQ = 3016
6137 10:52:09.281398 DQ_UI_PI_RATIO = 32
6138 10:52:09.285070 CA_UI_PI_RATIO = 32
6139 10:52:09.288323 ===================================
6140 10:52:09.291876 ===================================
6141 10:52:09.292349 memory_type:LPDDR4
6142 10:52:09.295116 GP_NUM : 10
6143 10:52:09.298204 SRAM_EN : 1
6144 10:52:09.298675 MD32_EN : 0
6145 10:52:09.302041 ===================================
6146 10:52:09.304956 [ANA_INIT] >>>>>>>>>>>>>>
6147 10:52:09.308225 <<<<<< [CONFIGURE PHASE]: ANA_TX
6148 10:52:09.311319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6149 10:52:09.314689 ===================================
6150 10:52:09.317876 data_rate = 800,PCW = 0X7400
6151 10:52:09.321531 ===================================
6152 10:52:09.325061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6153 10:52:09.327877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 10:52:09.341349 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 10:52:09.344641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6156 10:52:09.347855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6157 10:52:09.351079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6158 10:52:09.354658 [ANA_INIT] flow start
6159 10:52:09.358095 [ANA_INIT] PLL >>>>>>>>
6160 10:52:09.358524 [ANA_INIT] PLL <<<<<<<<
6161 10:52:09.361209 [ANA_INIT] MIDPI >>>>>>>>
6162 10:52:09.364976 [ANA_INIT] MIDPI <<<<<<<<
6163 10:52:09.365515 [ANA_INIT] DLL >>>>>>>>
6164 10:52:09.367942 [ANA_INIT] flow end
6165 10:52:09.371189 ============ LP4 DIFF to SE enter ============
6166 10:52:09.374947 ============ LP4 DIFF to SE exit ============
6167 10:52:09.378109 [ANA_INIT] <<<<<<<<<<<<<
6168 10:52:09.381514 [Flow] Enable top DCM control >>>>>
6169 10:52:09.384397 [Flow] Enable top DCM control <<<<<
6170 10:52:09.387717 Enable DLL master slave shuffle
6171 10:52:09.394243 ==============================================================
6172 10:52:09.394670 Gating Mode config
6173 10:52:09.401200 ==============================================================
6174 10:52:09.401678 Config description:
6175 10:52:09.411138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6176 10:52:09.417859 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6177 10:52:09.424097 SELPH_MODE 0: By rank 1: By Phase
6178 10:52:09.427776 ==============================================================
6179 10:52:09.430971 GAT_TRACK_EN = 0
6180 10:52:09.434469 RX_GATING_MODE = 2
6181 10:52:09.437525 RX_GATING_TRACK_MODE = 2
6182 10:52:09.441232 SELPH_MODE = 1
6183 10:52:09.444460 PICG_EARLY_EN = 1
6184 10:52:09.447640 VALID_LAT_VALUE = 1
6185 10:52:09.454235 ==============================================================
6186 10:52:09.457769 Enter into Gating configuration >>>>
6187 10:52:09.461017 Exit from Gating configuration <<<<
6188 10:52:09.461433 Enter into DVFS_PRE_config >>>>>
6189 10:52:09.474365 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6190 10:52:09.477915 Exit from DVFS_PRE_config <<<<<
6191 10:52:09.481022 Enter into PICG configuration >>>>
6192 10:52:09.484219 Exit from PICG configuration <<<<
6193 10:52:09.484766 [RX_INPUT] configuration >>>>>
6194 10:52:09.487638 [RX_INPUT] configuration <<<<<
6195 10:52:09.494259 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6196 10:52:09.497762 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6197 10:52:09.504440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6198 10:52:09.510867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6199 10:52:09.517495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 10:52:09.524302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 10:52:09.527442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6202 10:52:09.530728 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6203 10:52:09.537746 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6204 10:52:09.540703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6205 10:52:09.544131 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6206 10:52:09.547804 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6207 10:52:09.550925 ===================================
6208 10:52:09.554075 LPDDR4 DRAM CONFIGURATION
6209 10:52:09.557349 ===================================
6210 10:52:09.560467 EX_ROW_EN[0] = 0x0
6211 10:52:09.560890 EX_ROW_EN[1] = 0x0
6212 10:52:09.564144 LP4Y_EN = 0x0
6213 10:52:09.564569 WORK_FSP = 0x0
6214 10:52:09.567276 WL = 0x2
6215 10:52:09.567743 RL = 0x2
6216 10:52:09.570538 BL = 0x2
6217 10:52:09.570958 RPST = 0x0
6218 10:52:09.574118 RD_PRE = 0x0
6219 10:52:09.574539 WR_PRE = 0x1
6220 10:52:09.577214 WR_PST = 0x0
6221 10:52:09.577640 DBI_WR = 0x0
6222 10:52:09.580779 DBI_RD = 0x0
6223 10:52:09.581207 OTF = 0x1
6224 10:52:09.583857 ===================================
6225 10:52:09.590279 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6226 10:52:09.593445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6227 10:52:09.596792 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 10:52:09.599985 ===================================
6229 10:52:09.603814 LPDDR4 DRAM CONFIGURATION
6230 10:52:09.606816 ===================================
6231 10:52:09.610566 EX_ROW_EN[0] = 0x10
6232 10:52:09.610988 EX_ROW_EN[1] = 0x0
6233 10:52:09.613644 LP4Y_EN = 0x0
6234 10:52:09.614066 WORK_FSP = 0x0
6235 10:52:09.616846 WL = 0x2
6236 10:52:09.617265 RL = 0x2
6237 10:52:09.620414 BL = 0x2
6238 10:52:09.620833 RPST = 0x0
6239 10:52:09.623678 RD_PRE = 0x0
6240 10:52:09.624098 WR_PRE = 0x1
6241 10:52:09.626771 WR_PST = 0x0
6242 10:52:09.627190 DBI_WR = 0x0
6243 10:52:09.630067 DBI_RD = 0x0
6244 10:52:09.630491 OTF = 0x1
6245 10:52:09.633730 ===================================
6246 10:52:09.640206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6247 10:52:09.644703 nWR fixed to 30
6248 10:52:09.648428 [ModeRegInit_LP4] CH0 RK0
6249 10:52:09.648850 [ModeRegInit_LP4] CH0 RK1
6250 10:52:09.651903 [ModeRegInit_LP4] CH1 RK0
6251 10:52:09.654885 [ModeRegInit_LP4] CH1 RK1
6252 10:52:09.655301 match AC timing 19
6253 10:52:09.661459 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6254 10:52:09.665508 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6255 10:52:09.668432 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6256 10:52:09.674844 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6257 10:52:09.678602 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6258 10:52:09.679024 ==
6259 10:52:09.681615 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 10:52:09.685270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 10:52:09.685743 ==
6262 10:52:09.691385 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 10:52:09.698575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6264 10:52:09.701779 [CA 0] Center 36 (8~64) winsize 57
6265 10:52:09.705002 [CA 1] Center 36 (8~64) winsize 57
6266 10:52:09.708211 [CA 2] Center 36 (8~64) winsize 57
6267 10:52:09.708683 [CA 3] Center 36 (8~64) winsize 57
6268 10:52:09.711282 [CA 4] Center 36 (8~64) winsize 57
6269 10:52:09.715060 [CA 5] Center 36 (8~64) winsize 57
6270 10:52:09.715553
6271 10:52:09.718105 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6272 10:52:09.721934
6273 10:52:09.725001 [CATrainingPosCal] consider 1 rank data
6274 10:52:09.725455 u2DelayCellTimex100 = 270/100 ps
6275 10:52:09.731110 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 10:52:09.734558 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 10:52:09.738338 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 10:52:09.741613 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 10:52:09.744831 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 10:52:09.747971 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 10:52:09.748403
6282 10:52:09.751123 CA PerBit enable=1, Macro0, CA PI delay=36
6283 10:52:09.751577
6284 10:52:09.754961 [CBTSetCACLKResult] CA Dly = 36
6285 10:52:09.758134 CS Dly: 1 (0~32)
6286 10:52:09.758674 ==
6287 10:52:09.761653 Dram Type= 6, Freq= 0, CH_0, rank 1
6288 10:52:09.764297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 10:52:09.764724 ==
6290 10:52:09.771266 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6291 10:52:09.774395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6292 10:52:09.778135 [CA 0] Center 36 (8~64) winsize 57
6293 10:52:09.781385 [CA 1] Center 36 (8~64) winsize 57
6294 10:52:09.784820 [CA 2] Center 36 (8~64) winsize 57
6295 10:52:09.787784 [CA 3] Center 36 (8~64) winsize 57
6296 10:52:09.791380 [CA 4] Center 36 (8~64) winsize 57
6297 10:52:09.794445 [CA 5] Center 36 (8~64) winsize 57
6298 10:52:09.794865
6299 10:52:09.798132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6300 10:52:09.798553
6301 10:52:09.801452 [CATrainingPosCal] consider 2 rank data
6302 10:52:09.804738 u2DelayCellTimex100 = 270/100 ps
6303 10:52:09.807966 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 10:52:09.811228 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 10:52:09.814477 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 10:52:09.821379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 10:52:09.824418 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 10:52:09.827671 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 10:52:09.828093
6310 10:52:09.831426 CA PerBit enable=1, Macro0, CA PI delay=36
6311 10:52:09.831849
6312 10:52:09.834490 [CBTSetCACLKResult] CA Dly = 36
6313 10:52:09.834914 CS Dly: 1 (0~32)
6314 10:52:09.835246
6315 10:52:09.837805 ----->DramcWriteLeveling(PI) begin...
6316 10:52:09.838234 ==
6317 10:52:09.840850 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 10:52:09.847780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 10:52:09.848208 ==
6320 10:52:09.851063 Write leveling (Byte 0): 40 => 8
6321 10:52:09.851510 Write leveling (Byte 1): 40 => 8
6322 10:52:09.854332 DramcWriteLeveling(PI) end<-----
6323 10:52:09.854751
6324 10:52:09.857556 ==
6325 10:52:09.857978 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 10:52:09.864603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 10:52:09.865026 ==
6328 10:52:09.867682 [Gating] SW mode calibration
6329 10:52:09.874052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6330 10:52:09.877973 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6331 10:52:09.884654 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 10:52:09.887811 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 10:52:09.891173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 10:52:09.897404 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 10:52:09.900832 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 10:52:09.904249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 10:52:09.910787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 10:52:09.914001 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 10:52:09.917795 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 10:52:09.920948 Total UI for P1: 0, mck2ui 16
6341 10:52:09.924123 best dqsien dly found for B0: ( 0, 14, 24)
6342 10:52:09.927825 Total UI for P1: 0, mck2ui 16
6343 10:52:09.931019 best dqsien dly found for B1: ( 0, 14, 24)
6344 10:52:09.934251 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6345 10:52:09.938056 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6346 10:52:09.938480
6347 10:52:09.941211 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 10:52:09.947553 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 10:52:09.948013 [Gating] SW calibration Done
6350 10:52:09.948372 ==
6351 10:52:09.950970 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 10:52:09.957739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 10:52:09.958174 ==
6354 10:52:09.958643 RX Vref Scan: 0
6355 10:52:09.959090
6356 10:52:09.960715 RX Vref 0 -> 0, step: 1
6357 10:52:09.961135
6358 10:52:09.964634 RX Delay -410 -> 252, step: 16
6359 10:52:09.967844 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6360 10:52:09.970977 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6361 10:52:09.977684 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6362 10:52:09.980746 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6363 10:52:09.984278 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6364 10:52:09.987752 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6365 10:52:09.994144 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6366 10:52:09.997368 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6367 10:52:10.000628 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6368 10:52:10.004380 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6369 10:52:10.010946 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6370 10:52:10.014472 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6371 10:52:10.017730 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6372 10:52:10.020824 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6373 10:52:10.027275 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6374 10:52:10.030945 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6375 10:52:10.031423 ==
6376 10:52:10.033969 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 10:52:10.037872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 10:52:10.038329 ==
6379 10:52:10.041103 DQS Delay:
6380 10:52:10.041529 DQS0 = 27, DQS1 = 35
6381 10:52:10.041896 DQM Delay:
6382 10:52:10.044179 DQM0 = 11, DQM1 = 12
6383 10:52:10.044665 DQ Delay:
6384 10:52:10.047433 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6385 10:52:10.050540 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6386 10:52:10.054464 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6387 10:52:10.057514 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6388 10:52:10.057989
6389 10:52:10.058494
6390 10:52:10.059027 ==
6391 10:52:10.060689 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 10:52:10.064271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 10:52:10.067821 ==
6394 10:52:10.068236
6395 10:52:10.068577
6396 10:52:10.068882 TX Vref Scan disable
6397 10:52:10.071065 == TX Byte 0 ==
6398 10:52:10.074170 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 10:52:10.077361 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 10:52:10.080920 == TX Byte 1 ==
6401 10:52:10.084170 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 10:52:10.087466 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 10:52:10.087989 ==
6404 10:52:10.091179 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 10:52:10.094372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 10:52:10.097661 ==
6407 10:52:10.098190
6408 10:52:10.098525
6409 10:52:10.099047 TX Vref Scan disable
6410 10:52:10.100588 == TX Byte 0 ==
6411 10:52:10.103826 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 10:52:10.107146 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 10:52:10.110228 == TX Byte 1 ==
6414 10:52:10.114009 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 10:52:10.117111 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 10:52:10.117639
6417 10:52:10.120652 [DATLAT]
6418 10:52:10.121243 Freq=400, CH0 RK0
6419 10:52:10.121719
6420 10:52:10.124138 DATLAT Default: 0xf
6421 10:52:10.124604 0, 0xFFFF, sum = 0
6422 10:52:10.127100 1, 0xFFFF, sum = 0
6423 10:52:10.127630 2, 0xFFFF, sum = 0
6424 10:52:10.130745 3, 0xFFFF, sum = 0
6425 10:52:10.131167 4, 0xFFFF, sum = 0
6426 10:52:10.134187 5, 0xFFFF, sum = 0
6427 10:52:10.134724 6, 0xFFFF, sum = 0
6428 10:52:10.137252 7, 0xFFFF, sum = 0
6429 10:52:10.137674 8, 0xFFFF, sum = 0
6430 10:52:10.140329 9, 0xFFFF, sum = 0
6431 10:52:10.140786 10, 0xFFFF, sum = 0
6432 10:52:10.144048 11, 0xFFFF, sum = 0
6433 10:52:10.144610 12, 0xFFFF, sum = 0
6434 10:52:10.147192 13, 0x0, sum = 1
6435 10:52:10.147725 14, 0x0, sum = 2
6436 10:52:10.150461 15, 0x0, sum = 3
6437 10:52:10.150881 16, 0x0, sum = 4
6438 10:52:10.153655 best_step = 14
6439 10:52:10.154088
6440 10:52:10.154598 ==
6441 10:52:10.157496 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 10:52:10.160577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 10:52:10.161039 ==
6444 10:52:10.163740 RX Vref Scan: 1
6445 10:52:10.164160
6446 10:52:10.164540 RX Vref 0 -> 0, step: 1
6447 10:52:10.164861
6448 10:52:10.167130 RX Delay -311 -> 252, step: 8
6449 10:52:10.167601
6450 10:52:10.170158 Set Vref, RX VrefLevel [Byte0]: 56
6451 10:52:10.173752 [Byte1]: 49
6452 10:52:10.178251
6453 10:52:10.178699 Final RX Vref Byte 0 = 56 to rank0
6454 10:52:10.181913 Final RX Vref Byte 1 = 49 to rank0
6455 10:52:10.184803 Final RX Vref Byte 0 = 56 to rank1
6456 10:52:10.188479 Final RX Vref Byte 1 = 49 to rank1==
6457 10:52:10.191746 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 10:52:10.198180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 10:52:10.198636 ==
6460 10:52:10.199155 DQS Delay:
6461 10:52:10.201310 DQS0 = 28, DQS1 = 32
6462 10:52:10.201737 DQM Delay:
6463 10:52:10.202115 DQM0 = 11, DQM1 = 9
6464 10:52:10.204368 DQ Delay:
6465 10:52:10.207977 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =12
6466 10:52:10.211065 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6467 10:52:10.211686 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6468 10:52:10.214375 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6469 10:52:10.217990
6470 10:52:10.218445
6471 10:52:10.224226 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6472 10:52:10.227872 CH0 RK0: MR19=C0C, MR18=D1BE
6473 10:52:10.234327 CH0_RK0: MR19=0xC0C, MR18=0xD1BE, DQSOSC=384, MR23=63, INC=400, DEC=267
6474 10:52:10.234760 ==
6475 10:52:10.237559 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 10:52:10.241388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 10:52:10.241831 ==
6478 10:52:10.244400 [Gating] SW mode calibration
6479 10:52:10.250798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6480 10:52:10.257924 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6481 10:52:10.261147 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 10:52:10.264271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 10:52:10.270780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 10:52:10.274048 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 10:52:10.277645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 10:52:10.284384 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 10:52:10.287387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 10:52:10.290965 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 10:52:10.297080 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 10:52:10.297601 Total UI for P1: 0, mck2ui 16
6491 10:52:10.304276 best dqsien dly found for B0: ( 0, 14, 24)
6492 10:52:10.304703 Total UI for P1: 0, mck2ui 16
6493 10:52:10.307425 best dqsien dly found for B1: ( 0, 14, 24)
6494 10:52:10.314184 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6495 10:52:10.317197 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6496 10:52:10.317645
6497 10:52:10.320385 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 10:52:10.324060 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 10:52:10.327186 [Gating] SW calibration Done
6500 10:52:10.327695 ==
6501 10:52:10.330315 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 10:52:10.333995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 10:52:10.334640 ==
6504 10:52:10.337228 RX Vref Scan: 0
6505 10:52:10.337655
6506 10:52:10.338031 RX Vref 0 -> 0, step: 1
6507 10:52:10.338352
6508 10:52:10.340884 RX Delay -410 -> 252, step: 16
6509 10:52:10.346968 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6510 10:52:10.350448 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6511 10:52:10.353484 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6512 10:52:10.357286 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6513 10:52:10.360484 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6514 10:52:10.366860 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6515 10:52:10.370701 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6516 10:52:10.373853 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6517 10:52:10.377030 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6518 10:52:10.383511 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6519 10:52:10.386956 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6520 10:52:10.390202 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6521 10:52:10.396675 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6522 10:52:10.400283 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6523 10:52:10.403385 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6524 10:52:10.406613 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6525 10:52:10.407039 ==
6526 10:52:10.410356 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 10:52:10.416900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 10:52:10.417467 ==
6529 10:52:10.417915 DQS Delay:
6530 10:52:10.420043 DQS0 = 27, DQS1 = 35
6531 10:52:10.420494 DQM Delay:
6532 10:52:10.423662 DQM0 = 11, DQM1 = 12
6533 10:52:10.424256 DQ Delay:
6534 10:52:10.426631 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6535 10:52:10.430313 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6536 10:52:10.430746 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6537 10:52:10.433345 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6538 10:52:10.437010
6539 10:52:10.437429
6540 10:52:10.437758 ==
6541 10:52:10.440643 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 10:52:10.443184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 10:52:10.443647 ==
6544 10:52:10.443982
6545 10:52:10.444326
6546 10:52:10.446909 TX Vref Scan disable
6547 10:52:10.447390 == TX Byte 0 ==
6548 10:52:10.450018 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6549 10:52:10.456731 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6550 10:52:10.457190 == TX Byte 1 ==
6551 10:52:10.459874 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6552 10:52:10.466759 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6553 10:52:10.467157 ==
6554 10:52:10.469965 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 10:52:10.473803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 10:52:10.474182 ==
6557 10:52:10.474523
6558 10:52:10.474822
6559 10:52:10.476503 TX Vref Scan disable
6560 10:52:10.476849 == TX Byte 0 ==
6561 10:52:10.480355 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6562 10:52:10.486864 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6563 10:52:10.487246 == TX Byte 1 ==
6564 10:52:10.490371 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6565 10:52:10.496758 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6566 10:52:10.497211
6567 10:52:10.497549 [DATLAT]
6568 10:52:10.497875 Freq=400, CH0 RK1
6569 10:52:10.498179
6570 10:52:10.499903 DATLAT Default: 0xe
6571 10:52:10.503621 0, 0xFFFF, sum = 0
6572 10:52:10.504076 1, 0xFFFF, sum = 0
6573 10:52:10.506661 2, 0xFFFF, sum = 0
6574 10:52:10.507100 3, 0xFFFF, sum = 0
6575 10:52:10.510018 4, 0xFFFF, sum = 0
6576 10:52:10.510471 5, 0xFFFF, sum = 0
6577 10:52:10.513099 6, 0xFFFF, sum = 0
6578 10:52:10.513529 7, 0xFFFF, sum = 0
6579 10:52:10.516903 8, 0xFFFF, sum = 0
6580 10:52:10.517353 9, 0xFFFF, sum = 0
6581 10:52:10.519973 10, 0xFFFF, sum = 0
6582 10:52:10.520425 11, 0xFFFF, sum = 0
6583 10:52:10.523224 12, 0xFFFF, sum = 0
6584 10:52:10.523753 13, 0x0, sum = 1
6585 10:52:10.526474 14, 0x0, sum = 2
6586 10:52:10.526969 15, 0x0, sum = 3
6587 10:52:10.529555 16, 0x0, sum = 4
6588 10:52:10.529986 best_step = 14
6589 10:52:10.530354
6590 10:52:10.530667 ==
6591 10:52:10.533220 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 10:52:10.539709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 10:52:10.540184 ==
6594 10:52:10.540528 RX Vref Scan: 0
6595 10:52:10.540882
6596 10:52:10.543364 RX Vref 0 -> 0, step: 1
6597 10:52:10.544038
6598 10:52:10.546522 RX Delay -311 -> 252, step: 8
6599 10:52:10.553003 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6600 10:52:10.556229 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6601 10:52:10.559441 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6602 10:52:10.563069 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6603 10:52:10.569553 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6604 10:52:10.572811 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6605 10:52:10.576028 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6606 10:52:10.579998 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6607 10:52:10.582558 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6608 10:52:10.589915 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6609 10:52:10.593052 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6610 10:52:10.596091 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6611 10:52:10.602711 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6612 10:52:10.605896 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6613 10:52:10.609910 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6614 10:52:10.613025 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6615 10:52:10.613473 ==
6616 10:52:10.616101 Dram Type= 6, Freq= 0, CH_0, rank 1
6617 10:52:10.622613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 10:52:10.623032 ==
6619 10:52:10.623425 DQS Delay:
6620 10:52:10.626136 DQS0 = 24, DQS1 = 32
6621 10:52:10.626616 DQM Delay:
6622 10:52:10.626969 DQM0 = 9, DQM1 = 10
6623 10:52:10.629435 DQ Delay:
6624 10:52:10.632722 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6625 10:52:10.633139 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6626 10:52:10.635939 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6627 10:52:10.639667 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6628 10:52:10.640134
6629 10:52:10.642510
6630 10:52:10.649584 [DQSOSCAuto] RK1, (LSB)MR18= 0xb756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6631 10:52:10.652604 CH0 RK1: MR19=C0C, MR18=B756
6632 10:52:10.659189 CH0_RK1: MR19=0xC0C, MR18=0xB756, DQSOSC=387, MR23=63, INC=394, DEC=262
6633 10:52:10.662263 [RxdqsGatingPostProcess] freq 400
6634 10:52:10.666073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6635 10:52:10.669056 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 10:52:10.672354 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 10:52:10.676055 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 10:52:10.679362 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 10:52:10.682567 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 10:52:10.685897 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 10:52:10.688990 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 10:52:10.692799 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 10:52:10.696119 Pre-setting of DQS Precalculation
6644 10:52:10.699182 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6645 10:52:10.699631 ==
6646 10:52:10.702352 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 10:52:10.708908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 10:52:10.709328 ==
6649 10:52:10.712186 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 10:52:10.719437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6651 10:52:10.722399 [CA 0] Center 36 (8~64) winsize 57
6652 10:52:10.725899 [CA 1] Center 36 (8~64) winsize 57
6653 10:52:10.728969 [CA 2] Center 36 (8~64) winsize 57
6654 10:52:10.732250 [CA 3] Center 36 (8~64) winsize 57
6655 10:52:10.735737 [CA 4] Center 36 (8~64) winsize 57
6656 10:52:10.739013 [CA 5] Center 36 (8~64) winsize 57
6657 10:52:10.739436
6658 10:52:10.742108 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6659 10:52:10.742513
6660 10:52:10.745376 [CATrainingPosCal] consider 1 rank data
6661 10:52:10.749170 u2DelayCellTimex100 = 270/100 ps
6662 10:52:10.752180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 10:52:10.755639 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 10:52:10.758549 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 10:52:10.762512 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 10:52:10.765758 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 10:52:10.768869 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 10:52:10.769297
6669 10:52:10.775220 CA PerBit enable=1, Macro0, CA PI delay=36
6670 10:52:10.775720
6671 10:52:10.776062 [CBTSetCACLKResult] CA Dly = 36
6672 10:52:10.778651 CS Dly: 1 (0~32)
6673 10:52:10.779215 ==
6674 10:52:10.782219 Dram Type= 6, Freq= 0, CH_1, rank 1
6675 10:52:10.785369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 10:52:10.785797 ==
6677 10:52:10.791688 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6678 10:52:10.798746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6679 10:52:10.801718 [CA 0] Center 36 (8~64) winsize 57
6680 10:52:10.805054 [CA 1] Center 36 (8~64) winsize 57
6681 10:52:10.808409 [CA 2] Center 36 (8~64) winsize 57
6682 10:52:10.811705 [CA 3] Center 36 (8~64) winsize 57
6683 10:52:10.814871 [CA 4] Center 36 (8~64) winsize 57
6684 10:52:10.815321 [CA 5] Center 36 (8~64) winsize 57
6685 10:52:10.815722
6686 10:52:10.822013 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6687 10:52:10.822464
6688 10:52:10.825230 [CATrainingPosCal] consider 2 rank data
6689 10:52:10.828246 u2DelayCellTimex100 = 270/100 ps
6690 10:52:10.832154 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 10:52:10.835154 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 10:52:10.838207 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 10:52:10.841745 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 10:52:10.844856 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 10:52:10.848068 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 10:52:10.848493
6697 10:52:10.851756 CA PerBit enable=1, Macro0, CA PI delay=36
6698 10:52:10.852179
6699 10:52:10.854960 [CBTSetCACLKResult] CA Dly = 36
6700 10:52:10.858109 CS Dly: 1 (0~32)
6701 10:52:10.858530
6702 10:52:10.861618 ----->DramcWriteLeveling(PI) begin...
6703 10:52:10.862064 ==
6704 10:52:10.864651 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 10:52:10.868237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 10:52:10.868853 ==
6707 10:52:10.871594 Write leveling (Byte 0): 40 => 8
6708 10:52:10.874849 Write leveling (Byte 1): 40 => 8
6709 10:52:10.878042 DramcWriteLeveling(PI) end<-----
6710 10:52:10.878476
6711 10:52:10.878809 ==
6712 10:52:10.881782 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 10:52:10.884777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 10:52:10.885201 ==
6715 10:52:10.888238 [Gating] SW mode calibration
6716 10:52:10.894519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6717 10:52:10.901747 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6718 10:52:10.904763 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 10:52:10.907956 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 10:52:10.914649 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 10:52:10.918369 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 10:52:10.921667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 10:52:10.927926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 10:52:10.931194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 10:52:10.934284 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 10:52:10.941196 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 10:52:10.944337 Total UI for P1: 0, mck2ui 16
6728 10:52:10.947897 best dqsien dly found for B0: ( 0, 14, 24)
6729 10:52:10.948322 Total UI for P1: 0, mck2ui 16
6730 10:52:10.954770 best dqsien dly found for B1: ( 0, 14, 24)
6731 10:52:10.958237 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6732 10:52:10.961369 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6733 10:52:10.961791
6734 10:52:10.964481 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 10:52:10.968102 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 10:52:10.971125 [Gating] SW calibration Done
6737 10:52:10.971590 ==
6738 10:52:10.974413 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 10:52:10.977915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 10:52:10.978338 ==
6741 10:52:10.981017 RX Vref Scan: 0
6742 10:52:10.981456
6743 10:52:10.981848 RX Vref 0 -> 0, step: 1
6744 10:52:10.982166
6745 10:52:10.984160 RX Delay -410 -> 252, step: 16
6746 10:52:10.991064 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6747 10:52:10.994411 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6748 10:52:10.998073 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6749 10:52:11.001391 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6750 10:52:11.007752 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6751 10:52:11.011653 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6752 10:52:11.014598 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6753 10:52:11.017821 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6754 10:52:11.020937 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6755 10:52:11.028064 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6756 10:52:11.031257 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6757 10:52:11.034451 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6758 10:52:11.038275 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6759 10:52:11.044333 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6760 10:52:11.048199 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6761 10:52:11.051245 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6762 10:52:11.051697 ==
6763 10:52:11.054893 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 10:52:11.061241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 10:52:11.061693 ==
6766 10:52:11.062033 DQS Delay:
6767 10:52:11.064393 DQS0 = 27, DQS1 = 35
6768 10:52:11.064815 DQM Delay:
6769 10:52:11.065144 DQM0 = 11, DQM1 = 17
6770 10:52:11.067971 DQ Delay:
6771 10:52:11.071225 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6772 10:52:11.071778 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6773 10:52:11.074977 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6774 10:52:11.078173 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6775 10:52:11.078595
6776 10:52:11.078929
6777 10:52:11.080957 ==
6778 10:52:11.084578 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 10:52:11.088110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 10:52:11.088576 ==
6781 10:52:11.088918
6782 10:52:11.089251
6783 10:52:11.091784 TX Vref Scan disable
6784 10:52:11.092236 == TX Byte 0 ==
6785 10:52:11.094530 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 10:52:11.101163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 10:52:11.101657 == TX Byte 1 ==
6788 10:52:11.104656 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 10:52:11.111486 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 10:52:11.111942 ==
6791 10:52:11.114812 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 10:52:11.117878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 10:52:11.118437 ==
6794 10:52:11.118810
6795 10:52:11.119131
6796 10:52:11.121101 TX Vref Scan disable
6797 10:52:11.121551 == TX Byte 0 ==
6798 10:52:11.124847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 10:52:11.131245 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 10:52:11.131697 == TX Byte 1 ==
6801 10:52:11.134441 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 10:52:11.141322 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 10:52:11.141743
6804 10:52:11.142072 [DATLAT]
6805 10:52:11.142378 Freq=400, CH1 RK0
6806 10:52:11.142673
6807 10:52:11.144551 DATLAT Default: 0xf
6808 10:52:11.147711 0, 0xFFFF, sum = 0
6809 10:52:11.148302 1, 0xFFFF, sum = 0
6810 10:52:11.150894 2, 0xFFFF, sum = 0
6811 10:52:11.151320 3, 0xFFFF, sum = 0
6812 10:52:11.154495 4, 0xFFFF, sum = 0
6813 10:52:11.154918 5, 0xFFFF, sum = 0
6814 10:52:11.157638 6, 0xFFFF, sum = 0
6815 10:52:11.158063 7, 0xFFFF, sum = 0
6816 10:52:11.161504 8, 0xFFFF, sum = 0
6817 10:52:11.161928 9, 0xFFFF, sum = 0
6818 10:52:11.164638 10, 0xFFFF, sum = 0
6819 10:52:11.165063 11, 0xFFFF, sum = 0
6820 10:52:11.167862 12, 0xFFFF, sum = 0
6821 10:52:11.168288 13, 0x0, sum = 1
6822 10:52:11.171136 14, 0x0, sum = 2
6823 10:52:11.171581 15, 0x0, sum = 3
6824 10:52:11.174112 16, 0x0, sum = 4
6825 10:52:11.174590 best_step = 14
6826 10:52:11.174927
6827 10:52:11.175237 ==
6828 10:52:11.177997 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 10:52:11.181270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 10:52:11.184441 ==
6831 10:52:11.184890 RX Vref Scan: 1
6832 10:52:11.185222
6833 10:52:11.187679 RX Vref 0 -> 0, step: 1
6834 10:52:11.188097
6835 10:52:11.190660 RX Delay -311 -> 252, step: 8
6836 10:52:11.191080
6837 10:52:11.194324 Set Vref, RX VrefLevel [Byte0]: 55
6838 10:52:11.197647 [Byte1]: 47
6839 10:52:11.198114
6840 10:52:11.200580 Final RX Vref Byte 0 = 55 to rank0
6841 10:52:11.204571 Final RX Vref Byte 1 = 47 to rank0
6842 10:52:11.207478 Final RX Vref Byte 0 = 55 to rank1
6843 10:52:11.210596 Final RX Vref Byte 1 = 47 to rank1==
6844 10:52:11.214138 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 10:52:11.217476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 10:52:11.217917 ==
6847 10:52:11.221119 DQS Delay:
6848 10:52:11.221587 DQS0 = 28, DQS1 = 32
6849 10:52:11.224243 DQM Delay:
6850 10:52:11.224667 DQM0 = 9, DQM1 = 11
6851 10:52:11.225079 DQ Delay:
6852 10:52:11.227934 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6853 10:52:11.231112 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6854 10:52:11.234335 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6855 10:52:11.237607 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6856 10:52:11.238028
6857 10:52:11.238438
6858 10:52:11.247798 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6859 10:52:11.248229 CH1 RK0: MR19=C0C, MR18=8EC6
6860 10:52:11.254017 CH1_RK0: MR19=0xC0C, MR18=0x8EC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6861 10:52:11.254438 ==
6862 10:52:11.257890 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 10:52:11.261073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 10:52:11.264563 ==
6865 10:52:11.264983 [Gating] SW mode calibration
6866 10:52:11.274004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6867 10:52:11.277280 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6868 10:52:11.281288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 10:52:11.287289 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 10:52:11.290485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 10:52:11.294122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 10:52:11.300795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 10:52:11.303941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 10:52:11.307667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 10:52:11.313989 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 10:52:11.316976 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 10:52:11.320752 Total UI for P1: 0, mck2ui 16
6878 10:52:11.323847 best dqsien dly found for B0: ( 0, 14, 24)
6879 10:52:11.327460 Total UI for P1: 0, mck2ui 16
6880 10:52:11.330494 best dqsien dly found for B1: ( 0, 14, 24)
6881 10:52:11.334208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6882 10:52:11.337673 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6883 10:52:11.338133
6884 10:52:11.340789 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 10:52:11.343970 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 10:52:11.347261 [Gating] SW calibration Done
6887 10:52:11.347770 ==
6888 10:52:11.350455 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 10:52:11.357311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 10:52:11.357761 ==
6891 10:52:11.358103 RX Vref Scan: 0
6892 10:52:11.358437
6893 10:52:11.360527 RX Vref 0 -> 0, step: 1
6894 10:52:11.360952
6895 10:52:11.363678 RX Delay -410 -> 252, step: 16
6896 10:52:11.367424 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6897 10:52:11.370461 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6898 10:52:11.373513 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6899 10:52:11.380598 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6900 10:52:11.383794 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6901 10:52:11.387033 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6902 10:52:11.390725 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6903 10:52:11.396828 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6904 10:52:11.400474 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6905 10:52:11.403810 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6906 10:52:11.406770 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6907 10:52:11.413526 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6908 10:52:11.416740 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6909 10:52:11.420495 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6910 10:52:11.426602 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6911 10:52:11.429739 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6912 10:52:11.430170 ==
6913 10:52:11.433430 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 10:52:11.436830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 10:52:11.437256 ==
6916 10:52:11.440026 DQS Delay:
6917 10:52:11.440449 DQS0 = 35, DQS1 = 35
6918 10:52:11.440781 DQM Delay:
6919 10:52:11.443203 DQM0 = 18, DQM1 = 13
6920 10:52:11.443667 DQ Delay:
6921 10:52:11.446388 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6922 10:52:11.449695 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6923 10:52:11.453006 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6924 10:52:11.456735 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6925 10:52:11.457155
6926 10:52:11.457483
6927 10:52:11.457788 ==
6928 10:52:11.459838 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 10:52:11.463385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 10:52:11.466526 ==
6931 10:52:11.466944
6932 10:52:11.467273
6933 10:52:11.467672 TX Vref Scan disable
6934 10:52:11.469731 == TX Byte 0 ==
6935 10:52:11.473516 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6936 10:52:11.476616 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6937 10:52:11.479929 == TX Byte 1 ==
6938 10:52:11.483071 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6939 10:52:11.486846 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6940 10:52:11.487268 ==
6941 10:52:11.490113 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 10:52:11.493297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 10:52:11.496281 ==
6944 10:52:11.496700
6945 10:52:11.497030
6946 10:52:11.497338 TX Vref Scan disable
6947 10:52:11.499885 == TX Byte 0 ==
6948 10:52:11.503009 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6949 10:52:11.506691 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6950 10:52:11.509751 == TX Byte 1 ==
6951 10:52:11.513086 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6952 10:52:11.516163 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6953 10:52:11.516730
6954 10:52:11.519654 [DATLAT]
6955 10:52:11.520122 Freq=400, CH1 RK1
6956 10:52:11.520526
6957 10:52:11.523269 DATLAT Default: 0xe
6958 10:52:11.523752 0, 0xFFFF, sum = 0
6959 10:52:11.526289 1, 0xFFFF, sum = 0
6960 10:52:11.526788 2, 0xFFFF, sum = 0
6961 10:52:11.529918 3, 0xFFFF, sum = 0
6962 10:52:11.530368 4, 0xFFFF, sum = 0
6963 10:52:11.533140 5, 0xFFFF, sum = 0
6964 10:52:11.533576 6, 0xFFFF, sum = 0
6965 10:52:11.536328 7, 0xFFFF, sum = 0
6966 10:52:11.536876 8, 0xFFFF, sum = 0
6967 10:52:11.539475 9, 0xFFFF, sum = 0
6968 10:52:11.539905 10, 0xFFFF, sum = 0
6969 10:52:11.543063 11, 0xFFFF, sum = 0
6970 10:52:11.543541 12, 0xFFFF, sum = 0
6971 10:52:11.545879 13, 0x0, sum = 1
6972 10:52:11.546300 14, 0x0, sum = 2
6973 10:52:11.549261 15, 0x0, sum = 3
6974 10:52:11.549698 16, 0x0, sum = 4
6975 10:52:11.553027 best_step = 14
6976 10:52:11.553443
6977 10:52:11.553770 ==
6978 10:52:11.556319 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 10:52:11.559399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 10:52:11.559818 ==
6981 10:52:11.562648 RX Vref Scan: 0
6982 10:52:11.563064
6983 10:52:11.563439 RX Vref 0 -> 0, step: 1
6984 10:52:11.563760
6985 10:52:11.566464 RX Delay -311 -> 252, step: 8
6986 10:52:11.574060 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6987 10:52:11.577439 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6988 10:52:11.580485 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6989 10:52:11.584310 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6990 10:52:11.590836 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6991 10:52:11.593802 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6992 10:52:11.597251 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6993 10:52:11.601125 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6994 10:52:11.607243 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6995 10:52:11.610673 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6996 10:52:11.613752 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6997 10:52:11.617458 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6998 10:52:11.623693 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6999 10:52:11.627424 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7000 10:52:11.630488 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7001 10:52:11.637079 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7002 10:52:11.637736 ==
7003 10:52:11.640804 Dram Type= 6, Freq= 0, CH_1, rank 1
7004 10:52:11.643994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7005 10:52:11.644425 ==
7006 10:52:11.644797 DQS Delay:
7007 10:52:11.647139 DQS0 = 28, DQS1 = 32
7008 10:52:11.647640 DQM Delay:
7009 10:52:11.650387 DQM0 = 10, DQM1 = 11
7010 10:52:11.650864 DQ Delay:
7011 10:52:11.653675 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7012 10:52:11.657406 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7013 10:52:11.660775 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7014 10:52:11.663903 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7015 10:52:11.664352
7016 10:52:11.664697
7017 10:52:11.670221 [DQSOSCAuto] RK1, (LSB)MR18= 0xca5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7018 10:52:11.673873 CH1 RK1: MR19=C0C, MR18=CA5B
7019 10:52:11.680139 CH1_RK1: MR19=0xC0C, MR18=0xCA5B, DQSOSC=384, MR23=63, INC=400, DEC=267
7020 10:52:11.683997 [RxdqsGatingPostProcess] freq 400
7021 10:52:11.687000 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7022 10:52:11.690722 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 10:52:11.693950 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 10:52:11.697139 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 10:52:11.700314 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 10:52:11.703549 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 10:52:11.706728 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 10:52:11.710659 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 10:52:11.713776 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 10:52:11.717218 Pre-setting of DQS Precalculation
7031 10:52:11.720308 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7032 10:52:11.730637 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7033 10:52:11.737648 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7034 10:52:11.738240
7035 10:52:11.738603
7036 10:52:11.740412 [Calibration Summary] 800 Mbps
7037 10:52:11.740851 CH 0, Rank 0
7038 10:52:11.744132 SW Impedance : PASS
7039 10:52:11.744682 DUTY Scan : NO K
7040 10:52:11.747150 ZQ Calibration : PASS
7041 10:52:11.750307 Jitter Meter : NO K
7042 10:52:11.750790 CBT Training : PASS
7043 10:52:11.754086 Write leveling : PASS
7044 10:52:11.754647 RX DQS gating : PASS
7045 10:52:11.757370 RX DQ/DQS(RDDQC) : PASS
7046 10:52:11.760952 TX DQ/DQS : PASS
7047 10:52:11.761487 RX DATLAT : PASS
7048 10:52:11.763950 RX DQ/DQS(Engine): PASS
7049 10:52:11.766968 TX OE : NO K
7050 10:52:11.767572 All Pass.
7051 10:52:11.767936
7052 10:52:11.768318 CH 0, Rank 1
7053 10:52:11.770918 SW Impedance : PASS
7054 10:52:11.774009 DUTY Scan : NO K
7055 10:52:11.774539 ZQ Calibration : PASS
7056 10:52:11.777049 Jitter Meter : NO K
7057 10:52:11.780115 CBT Training : PASS
7058 10:52:11.780541 Write leveling : NO K
7059 10:52:11.783425 RX DQS gating : PASS
7060 10:52:11.786722 RX DQ/DQS(RDDQC) : PASS
7061 10:52:11.787291 TX DQ/DQS : PASS
7062 10:52:11.790228 RX DATLAT : PASS
7063 10:52:11.793855 RX DQ/DQS(Engine): PASS
7064 10:52:11.794334 TX OE : NO K
7065 10:52:11.797118 All Pass.
7066 10:52:11.797560
7067 10:52:11.797925 CH 1, Rank 0
7068 10:52:11.800305 SW Impedance : PASS
7069 10:52:11.800751 DUTY Scan : NO K
7070 10:52:11.803565 ZQ Calibration : PASS
7071 10:52:11.806747 Jitter Meter : NO K
7072 10:52:11.807173 CBT Training : PASS
7073 10:52:11.810756 Write leveling : PASS
7074 10:52:11.811195 RX DQS gating : PASS
7075 10:52:11.813320 RX DQ/DQS(RDDQC) : PASS
7076 10:52:11.817091 TX DQ/DQS : PASS
7077 10:52:11.817655 RX DATLAT : PASS
7078 10:52:11.820314 RX DQ/DQS(Engine): PASS
7079 10:52:11.824101 TX OE : NO K
7080 10:52:11.824549 All Pass.
7081 10:52:11.824909
7082 10:52:11.825289 CH 1, Rank 1
7083 10:52:11.826958 SW Impedance : PASS
7084 10:52:11.830387 DUTY Scan : NO K
7085 10:52:11.830825 ZQ Calibration : PASS
7086 10:52:11.833310 Jitter Meter : NO K
7087 10:52:11.837126 CBT Training : PASS
7088 10:52:11.837559 Write leveling : NO K
7089 10:52:11.840258 RX DQS gating : PASS
7090 10:52:11.843483 RX DQ/DQS(RDDQC) : PASS
7091 10:52:11.843934 TX DQ/DQS : PASS
7092 10:52:11.847169 RX DATLAT : PASS
7093 10:52:11.850446 RX DQ/DQS(Engine): PASS
7094 10:52:11.850991 TX OE : NO K
7095 10:52:11.851553 All Pass.
7096 10:52:11.851891
7097 10:52:11.853606 DramC Write-DBI off
7098 10:52:11.856907 PER_BANK_REFRESH: Hybrid Mode
7099 10:52:11.857342 TX_TRACKING: ON
7100 10:52:11.866773 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7101 10:52:11.870121 [FAST_K] Save calibration result to emmc
7102 10:52:11.873676 dramc_set_vcore_voltage set vcore to 725000
7103 10:52:11.876772 Read voltage for 1600, 0
7104 10:52:11.877221 Vio18 = 0
7105 10:52:11.880007 Vcore = 725000
7106 10:52:11.880431 Vdram = 0
7107 10:52:11.880786 Vddq = 0
7108 10:52:11.881101 Vmddr = 0
7109 10:52:11.886640 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7110 10:52:11.893759 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7111 10:52:11.894290 MEM_TYPE=3, freq_sel=13
7112 10:52:11.896592 sv_algorithm_assistance_LP4_3733
7113 10:52:11.900235 ============ PULL DRAM RESETB DOWN ============
7114 10:52:11.906921 ========== PULL DRAM RESETB DOWN end =========
7115 10:52:11.909964 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7116 10:52:11.913224 ===================================
7117 10:52:11.917136 LPDDR4 DRAM CONFIGURATION
7118 10:52:11.920022 ===================================
7119 10:52:11.920452 EX_ROW_EN[0] = 0x0
7120 10:52:11.923454 EX_ROW_EN[1] = 0x0
7121 10:52:11.923880 LP4Y_EN = 0x0
7122 10:52:11.926638 WORK_FSP = 0x1
7123 10:52:11.927186 WL = 0x5
7124 10:52:11.930423 RL = 0x5
7125 10:52:11.930864 BL = 0x2
7126 10:52:11.933444 RPST = 0x0
7127 10:52:11.933874 RD_PRE = 0x0
7128 10:52:11.936539 WR_PRE = 0x1
7129 10:52:11.940062 WR_PST = 0x1
7130 10:52:11.940500 DBI_WR = 0x0
7131 10:52:11.943666 DBI_RD = 0x0
7132 10:52:11.944118 OTF = 0x1
7133 10:52:11.946515 ===================================
7134 10:52:11.949802 ===================================
7135 10:52:11.950416 ANA top config
7136 10:52:11.953548 ===================================
7137 10:52:11.956558 DLL_ASYNC_EN = 0
7138 10:52:11.959740 ALL_SLAVE_EN = 0
7139 10:52:11.963746 NEW_RANK_MODE = 1
7140 10:52:11.966667 DLL_IDLE_MODE = 1
7141 10:52:11.967096 LP45_APHY_COMB_EN = 1
7142 10:52:11.970406 TX_ODT_DIS = 0
7143 10:52:11.973500 NEW_8X_MODE = 1
7144 10:52:11.976693 ===================================
7145 10:52:11.979855 ===================================
7146 10:52:11.983303 data_rate = 3200
7147 10:52:11.986458 CKR = 1
7148 10:52:11.986899 DQ_P2S_RATIO = 8
7149 10:52:11.989954 ===================================
7150 10:52:11.993654 CA_P2S_RATIO = 8
7151 10:52:11.996832 DQ_CA_OPEN = 0
7152 10:52:11.999898 DQ_SEMI_OPEN = 0
7153 10:52:12.003556 CA_SEMI_OPEN = 0
7154 10:52:12.006850 CA_FULL_RATE = 0
7155 10:52:12.007464 DQ_CKDIV4_EN = 0
7156 10:52:12.010095 CA_CKDIV4_EN = 0
7157 10:52:12.013326 CA_PREDIV_EN = 0
7158 10:52:12.016477 PH8_DLY = 12
7159 10:52:12.020258 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7160 10:52:12.022963 DQ_AAMCK_DIV = 4
7161 10:52:12.023409 CA_AAMCK_DIV = 4
7162 10:52:12.026678 CA_ADMCK_DIV = 4
7163 10:52:12.030093 DQ_TRACK_CA_EN = 0
7164 10:52:12.033345 CA_PICK = 1600
7165 10:52:12.036482 CA_MCKIO = 1600
7166 10:52:12.039752 MCKIO_SEMI = 0
7167 10:52:12.043684 PLL_FREQ = 3068
7168 10:52:12.044199 DQ_UI_PI_RATIO = 32
7169 10:52:12.046749 CA_UI_PI_RATIO = 0
7170 10:52:12.049697 ===================================
7171 10:52:12.053476 ===================================
7172 10:52:12.056675 memory_type:LPDDR4
7173 10:52:12.059823 GP_NUM : 10
7174 10:52:12.060239 SRAM_EN : 1
7175 10:52:12.063027 MD32_EN : 0
7176 10:52:12.066504 ===================================
7177 10:52:12.066925 [ANA_INIT] >>>>>>>>>>>>>>
7178 10:52:12.070064 <<<<<< [CONFIGURE PHASE]: ANA_TX
7179 10:52:12.073630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7180 10:52:12.076852 ===================================
7181 10:52:12.080132 data_rate = 3200,PCW = 0X7600
7182 10:52:12.083361 ===================================
7183 10:52:12.086500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7184 10:52:12.093153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 10:52:12.099803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 10:52:12.102912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7187 10:52:12.106063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7188 10:52:12.109747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7189 10:52:12.112826 [ANA_INIT] flow start
7190 10:52:12.113229 [ANA_INIT] PLL >>>>>>>>
7191 10:52:12.116155 [ANA_INIT] PLL <<<<<<<<
7192 10:52:12.119427 [ANA_INIT] MIDPI >>>>>>>>
7193 10:52:12.119800 [ANA_INIT] MIDPI <<<<<<<<
7194 10:52:12.123242 [ANA_INIT] DLL >>>>>>>>
7195 10:52:12.126442 [ANA_INIT] DLL <<<<<<<<
7196 10:52:12.126853 [ANA_INIT] flow end
7197 10:52:12.132737 ============ LP4 DIFF to SE enter ============
7198 10:52:12.136557 ============ LP4 DIFF to SE exit ============
7199 10:52:12.139846 [ANA_INIT] <<<<<<<<<<<<<
7200 10:52:12.140236 [Flow] Enable top DCM control >>>>>
7201 10:52:12.142771 [Flow] Enable top DCM control <<<<<
7202 10:52:12.146409 Enable DLL master slave shuffle
7203 10:52:12.152624 ==============================================================
7204 10:52:12.156563 Gating Mode config
7205 10:52:12.159611 ==============================================================
7206 10:52:12.162870 Config description:
7207 10:52:12.172772 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7208 10:52:12.179682 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7209 10:52:12.182878 SELPH_MODE 0: By rank 1: By Phase
7210 10:52:12.189181 ==============================================================
7211 10:52:12.192964 GAT_TRACK_EN = 1
7212 10:52:12.196195 RX_GATING_MODE = 2
7213 10:52:12.198961 RX_GATING_TRACK_MODE = 2
7214 10:52:12.199044 SELPH_MODE = 1
7215 10:52:12.202012 PICG_EARLY_EN = 1
7216 10:52:12.205452 VALID_LAT_VALUE = 1
7217 10:52:12.213045 ==============================================================
7218 10:52:12.215976 Enter into Gating configuration >>>>
7219 10:52:12.219035 Exit from Gating configuration <<<<
7220 10:52:12.222303 Enter into DVFS_PRE_config >>>>>
7221 10:52:12.232073 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7222 10:52:12.235514 Exit from DVFS_PRE_config <<<<<
7223 10:52:12.238756 Enter into PICG configuration >>>>
7224 10:52:12.242559 Exit from PICG configuration <<<<
7225 10:52:12.245569 [RX_INPUT] configuration >>>>>
7226 10:52:12.248797 [RX_INPUT] configuration <<<<<
7227 10:52:12.252274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7228 10:52:12.258727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7229 10:52:12.265486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7230 10:52:12.272550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7231 10:52:12.278644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 10:52:12.282440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 10:52:12.288856 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7234 10:52:12.291932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7235 10:52:12.295413 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7236 10:52:12.298867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7237 10:52:12.305156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7238 10:52:12.308979 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7239 10:52:12.312010 ===================================
7240 10:52:12.315428 LPDDR4 DRAM CONFIGURATION
7241 10:52:12.319054 ===================================
7242 10:52:12.319504 EX_ROW_EN[0] = 0x0
7243 10:52:12.321998 EX_ROW_EN[1] = 0x0
7244 10:52:12.322414 LP4Y_EN = 0x0
7245 10:52:12.325655 WORK_FSP = 0x1
7246 10:52:12.326072 WL = 0x5
7247 10:52:12.328643 RL = 0x5
7248 10:52:12.329077 BL = 0x2
7249 10:52:12.331899 RPST = 0x0
7250 10:52:12.332315 RD_PRE = 0x0
7251 10:52:12.335067 WR_PRE = 0x1
7252 10:52:12.335510 WR_PST = 0x1
7253 10:52:12.338261 DBI_WR = 0x0
7254 10:52:12.342197 DBI_RD = 0x0
7255 10:52:12.342615 OTF = 0x1
7256 10:52:12.344955 ===================================
7257 10:52:12.348638 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7258 10:52:12.351967 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7259 10:52:12.358638 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 10:52:12.361810 ===================================
7261 10:52:12.364977 LPDDR4 DRAM CONFIGURATION
7262 10:52:12.368154 ===================================
7263 10:52:12.368574 EX_ROW_EN[0] = 0x10
7264 10:52:12.371801 EX_ROW_EN[1] = 0x0
7265 10:52:12.372222 LP4Y_EN = 0x0
7266 10:52:12.374918 WORK_FSP = 0x1
7267 10:52:12.375395 WL = 0x5
7268 10:52:12.378005 RL = 0x5
7269 10:52:12.378423 BL = 0x2
7270 10:52:12.381607 RPST = 0x0
7271 10:52:12.382083 RD_PRE = 0x0
7272 10:52:12.384789 WR_PRE = 0x1
7273 10:52:12.385256 WR_PST = 0x1
7274 10:52:12.388638 DBI_WR = 0x0
7275 10:52:12.389173 DBI_RD = 0x0
7276 10:52:12.391597 OTF = 0x1
7277 10:52:12.395117 ===================================
7278 10:52:12.401749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7279 10:52:12.402175 ==
7280 10:52:12.404897 Dram Type= 6, Freq= 0, CH_0, rank 0
7281 10:52:12.408055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7282 10:52:12.408641 ==
7283 10:52:12.411704 [Duty_Offset_Calibration]
7284 10:52:12.412124 B0:2 B1:1 CA:1
7285 10:52:12.412456
7286 10:52:12.414865 [DutyScan_Calibration_Flow] k_type=0
7287 10:52:12.425925
7288 10:52:12.426395 ==CLK 0==
7289 10:52:12.429519 Final CLK duty delay cell = 0
7290 10:52:12.432523 [0] MAX Duty = 5156%(X100), DQS PI = 22
7291 10:52:12.436221 [0] MIN Duty = 4876%(X100), DQS PI = 48
7292 10:52:12.436651 [0] AVG Duty = 5016%(X100)
7293 10:52:12.439428
7294 10:52:12.439887 CH0 CLK Duty spec in!! Max-Min= 280%
7295 10:52:12.445888 [DutyScan_Calibration_Flow] ====Done====
7296 10:52:12.446375
7297 10:52:12.449136 [DutyScan_Calibration_Flow] k_type=1
7298 10:52:12.465421
7299 10:52:12.465870 ==DQS 0 ==
7300 10:52:12.468732 Final DQS duty delay cell = -4
7301 10:52:12.471947 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7302 10:52:12.475069 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7303 10:52:12.478802 [-4] AVG Duty = 4906%(X100)
7304 10:52:12.479247
7305 10:52:12.479639 ==DQS 1 ==
7306 10:52:12.481651 Final DQS duty delay cell = 0
7307 10:52:12.485360 [0] MAX Duty = 5187%(X100), DQS PI = 4
7308 10:52:12.488442 [0] MIN Duty = 5062%(X100), DQS PI = 32
7309 10:52:12.491786 [0] AVG Duty = 5124%(X100)
7310 10:52:12.492208
7311 10:52:12.494995 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7312 10:52:12.495448
7313 10:52:12.498135 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7314 10:52:12.501885 [DutyScan_Calibration_Flow] ====Done====
7315 10:52:12.502305
7316 10:52:12.505142 [DutyScan_Calibration_Flow] k_type=3
7317 10:52:12.521461
7318 10:52:12.521892 ==DQM 0 ==
7319 10:52:12.525313 Final DQM duty delay cell = 0
7320 10:52:12.528304 [0] MAX Duty = 5218%(X100), DQS PI = 32
7321 10:52:12.532000 [0] MIN Duty = 4907%(X100), DQS PI = 54
7322 10:52:12.532425 [0] AVG Duty = 5062%(X100)
7323 10:52:12.535002
7324 10:52:12.535463 ==DQM 1 ==
7325 10:52:12.538505 Final DQM duty delay cell = -4
7326 10:52:12.541724 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7327 10:52:12.544933 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7328 10:52:12.548766 [-4] AVG Duty = 4891%(X100)
7329 10:52:12.549190
7330 10:52:12.551815 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7331 10:52:12.552238
7332 10:52:12.555003 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7333 10:52:12.558160 [DutyScan_Calibration_Flow] ====Done====
7334 10:52:12.558583
7335 10:52:12.561388 [DutyScan_Calibration_Flow] k_type=2
7336 10:52:12.579233
7337 10:52:12.579698 ==DQ 0 ==
7338 10:52:12.582397 Final DQ duty delay cell = 0
7339 10:52:12.586243 [0] MAX Duty = 5062%(X100), DQS PI = 26
7340 10:52:12.589129 [0] MIN Duty = 4907%(X100), DQS PI = 0
7341 10:52:12.589653 [0] AVG Duty = 4984%(X100)
7342 10:52:12.589998
7343 10:52:12.592780 ==DQ 1 ==
7344 10:52:12.595722 Final DQ duty delay cell = 0
7345 10:52:12.599414 [0] MAX Duty = 5156%(X100), DQS PI = 22
7346 10:52:12.602760 [0] MIN Duty = 4938%(X100), DQS PI = 36
7347 10:52:12.603188 [0] AVG Duty = 5047%(X100)
7348 10:52:12.603564
7349 10:52:12.605935 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7350 10:52:12.606361
7351 10:52:12.612718 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7352 10:52:12.615761 [DutyScan_Calibration_Flow] ====Done====
7353 10:52:12.616184 ==
7354 10:52:12.619369 Dram Type= 6, Freq= 0, CH_1, rank 0
7355 10:52:12.622528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7356 10:52:12.622954 ==
7357 10:52:12.625619 [Duty_Offset_Calibration]
7358 10:52:12.626037 B0:1 B1:0 CA:0
7359 10:52:12.626394
7360 10:52:12.629070 [DutyScan_Calibration_Flow] k_type=0
7361 10:52:12.638520
7362 10:52:12.638734 ==CLK 0==
7363 10:52:12.641773 Final CLK duty delay cell = -4
7364 10:52:12.645316 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7365 10:52:12.648353 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7366 10:52:12.651575 [-4] AVG Duty = 4937%(X100)
7367 10:52:12.651733
7368 10:52:12.655241 CH1 CLK Duty spec in!! Max-Min= 125%
7369 10:52:12.658476 [DutyScan_Calibration_Flow] ====Done====
7370 10:52:12.658582
7371 10:52:12.661634 [DutyScan_Calibration_Flow] k_type=1
7372 10:52:12.678066
7373 10:52:12.678220 ==DQS 0 ==
7374 10:52:12.681762 Final DQS duty delay cell = 0
7375 10:52:12.685060 [0] MAX Duty = 5094%(X100), DQS PI = 26
7376 10:52:12.688248 [0] MIN Duty = 4844%(X100), DQS PI = 50
7377 10:52:12.691381 [0] AVG Duty = 4969%(X100)
7378 10:52:12.691535
7379 10:52:12.691610 ==DQS 1 ==
7380 10:52:12.695169 Final DQS duty delay cell = 0
7381 10:52:12.698136 [0] MAX Duty = 5249%(X100), DQS PI = 16
7382 10:52:12.701572 [0] MIN Duty = 4969%(X100), DQS PI = 6
7383 10:52:12.704621 [0] AVG Duty = 5109%(X100)
7384 10:52:12.704701
7385 10:52:12.707982 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7386 10:52:12.708078
7387 10:52:12.711163 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7388 10:52:12.715035 [DutyScan_Calibration_Flow] ====Done====
7389 10:52:12.715149
7390 10:52:12.718194 [DutyScan_Calibration_Flow] k_type=3
7391 10:52:12.735021
7392 10:52:12.735141 ==DQM 0 ==
7393 10:52:12.738325 Final DQM duty delay cell = 0
7394 10:52:12.742043 [0] MAX Duty = 5218%(X100), DQS PI = 18
7395 10:52:12.745165 [0] MIN Duty = 4969%(X100), DQS PI = 48
7396 10:52:12.745341 [0] AVG Duty = 5093%(X100)
7397 10:52:12.748376
7398 10:52:12.748551 ==DQM 1 ==
7399 10:52:12.752068 Final DQM duty delay cell = 0
7400 10:52:12.755360 [0] MAX Duty = 5093%(X100), DQS PI = 18
7401 10:52:12.758557 [0] MIN Duty = 4907%(X100), DQS PI = 34
7402 10:52:12.761942 [0] AVG Duty = 5000%(X100)
7403 10:52:12.762345
7404 10:52:12.765169 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7405 10:52:12.765493
7406 10:52:12.768626 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7407 10:52:12.772215 [DutyScan_Calibration_Flow] ====Done====
7408 10:52:12.772675
7409 10:52:12.775274 [DutyScan_Calibration_Flow] k_type=2
7410 10:52:12.791767
7411 10:52:12.792198 ==DQ 0 ==
7412 10:52:12.794801 Final DQ duty delay cell = -4
7413 10:52:12.798132 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7414 10:52:12.801314 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7415 10:52:12.804923 [-4] AVG Duty = 4968%(X100)
7416 10:52:12.805374
7417 10:52:12.805790 ==DQ 1 ==
7418 10:52:12.807843 Final DQ duty delay cell = 0
7419 10:52:12.811197 [0] MAX Duty = 5124%(X100), DQS PI = 16
7420 10:52:12.814434 [0] MIN Duty = 4938%(X100), DQS PI = 8
7421 10:52:12.817586 [0] AVG Duty = 5031%(X100)
7422 10:52:12.818020
7423 10:52:12.821020 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7424 10:52:12.821458
7425 10:52:12.824960 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7426 10:52:12.827937 [DutyScan_Calibration_Flow] ====Done====
7427 10:52:12.830804 nWR fixed to 30
7428 10:52:12.834403 [ModeRegInit_LP4] CH0 RK0
7429 10:52:12.834843 [ModeRegInit_LP4] CH0 RK1
7430 10:52:12.837337 [ModeRegInit_LP4] CH1 RK0
7431 10:52:12.840873 [ModeRegInit_LP4] CH1 RK1
7432 10:52:12.841318 match AC timing 5
7433 10:52:12.847437 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7434 10:52:12.850764 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7435 10:52:12.854529 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7436 10:52:12.860778 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7437 10:52:12.864229 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7438 10:52:12.864678 [MiockJmeterHQA]
7439 10:52:12.867755
7440 10:52:12.868180 [DramcMiockJmeter] u1RxGatingPI = 0
7441 10:52:12.870983 0 : 4253, 4027
7442 10:52:12.871449 4 : 4363, 4137
7443 10:52:12.874176 8 : 4252, 4027
7444 10:52:12.874605 12 : 4250, 4026
7445 10:52:12.877350 16 : 4252, 4027
7446 10:52:12.877798 20 : 4252, 4026
7447 10:52:12.878136 24 : 4363, 4138
7448 10:52:12.881151 28 : 4363, 4137
7449 10:52:12.881580 32 : 4252, 4027
7450 10:52:12.884357 36 : 4253, 4027
7451 10:52:12.884786 40 : 4253, 4026
7452 10:52:12.887474 44 : 4252, 4027
7453 10:52:12.887906 48 : 4254, 4029
7454 10:52:12.890769 52 : 4363, 4138
7455 10:52:12.891196 56 : 4249, 4027
7456 10:52:12.891585 60 : 4250, 4027
7457 10:52:12.894443 64 : 4250, 4027
7458 10:52:12.894870 68 : 4252, 4029
7459 10:52:12.897695 72 : 4250, 4027
7460 10:52:12.898141 76 : 4360, 4138
7461 10:52:12.900891 80 : 4361, 4137
7462 10:52:12.901319 84 : 4250, 4027
7463 10:52:12.901657 88 : 4249, 105
7464 10:52:12.904170 92 : 4363, 0
7465 10:52:12.904600 96 : 4252, 0
7466 10:52:12.907448 100 : 4252, 0
7467 10:52:12.907877 104 : 4249, 0
7468 10:52:12.908232 108 : 4250, 0
7469 10:52:12.910538 112 : 4250, 0
7470 10:52:12.910991 116 : 4250, 0
7471 10:52:12.914150 120 : 4250, 0
7472 10:52:12.914634 124 : 4361, 0
7473 10:52:12.914982 128 : 4250, 0
7474 10:52:12.917782 132 : 4250, 0
7475 10:52:12.918249 136 : 4250, 0
7476 10:52:12.918604 140 : 4250, 0
7477 10:52:12.920744 144 : 4253, 0
7478 10:52:12.921176 148 : 4250, 0
7479 10:52:12.924262 152 : 4360, 0
7480 10:52:12.924699 156 : 4249, 0
7481 10:52:12.925061 160 : 4361, 0
7482 10:52:12.927277 164 : 4249, 0
7483 10:52:12.927864 168 : 4250, 0
7484 10:52:12.930597 172 : 4250, 0
7485 10:52:12.931031 176 : 4361, 0
7486 10:52:12.931438 180 : 4360, 0
7487 10:52:12.934370 184 : 4250, 0
7488 10:52:12.934814 188 : 4250, 0
7489 10:52:12.937728 192 : 4250, 0
7490 10:52:12.938342 196 : 4253, 0
7491 10:52:12.938849 200 : 4250, 0
7492 10:52:12.940645 204 : 4360, 1232
7493 10:52:12.941079 208 : 4250, 4018
7494 10:52:12.944173 212 : 4250, 4027
7495 10:52:12.944611 216 : 4250, 4027
7496 10:52:12.947669 220 : 4249, 4027
7497 10:52:12.948103 224 : 4250, 4026
7498 10:52:12.950527 228 : 4250, 4027
7499 10:52:12.950981 232 : 4360, 4138
7500 10:52:12.953854 236 : 4249, 4027
7501 10:52:12.954316 240 : 4250, 4026
7502 10:52:12.954665 244 : 4361, 4137
7503 10:52:12.957197 248 : 4250, 4027
7504 10:52:12.957653 252 : 4250, 4027
7505 10:52:12.960369 256 : 4363, 4140
7506 10:52:12.960942 260 : 4250, 4026
7507 10:52:12.964035 264 : 4250, 4027
7508 10:52:12.964467 268 : 4249, 4027
7509 10:52:12.967227 272 : 4252, 4029
7510 10:52:12.967726 276 : 4250, 4026
7511 10:52:12.970863 280 : 4250, 4027
7512 10:52:12.971437 284 : 4360, 4138
7513 10:52:12.974045 288 : 4250, 4027
7514 10:52:12.974788 292 : 4250, 4026
7515 10:52:12.977756 296 : 4361, 4137
7516 10:52:12.978232 300 : 4250, 4027
7517 10:52:12.978624 304 : 4250, 4027
7518 10:52:12.980913 308 : 4363, 4111
7519 10:52:12.981396 312 : 4250, 2130
7520 10:52:12.984066 316 : 4250, 4
7521 10:52:12.984534
7522 10:52:12.987194 MIOCK jitter meter ch=0
7523 10:52:12.987686
7524 10:52:12.988030 1T = (316-88) = 228 dly cells
7525 10:52:12.994110 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7526 10:52:12.994560 ==
7527 10:52:12.997308 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 10:52:13.000506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 10:52:13.001004 ==
7530 10:52:13.007547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 10:52:13.010726 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 10:52:13.017063 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 10:52:13.020151 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 10:52:13.030450 [CA 0] Center 42 (12~73) winsize 62
7535 10:52:13.034225 [CA 1] Center 42 (12~73) winsize 62
7536 10:52:13.037488 [CA 2] Center 38 (8~68) winsize 61
7537 10:52:13.040495 [CA 3] Center 37 (8~67) winsize 60
7538 10:52:13.043591 [CA 4] Center 36 (6~66) winsize 61
7539 10:52:13.046812 [CA 5] Center 35 (6~64) winsize 59
7540 10:52:13.047448
7541 10:52:13.050517 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7542 10:52:13.050957
7543 10:52:13.053655 [CATrainingPosCal] consider 1 rank data
7544 10:52:13.057146 u2DelayCellTimex100 = 285/100 ps
7545 10:52:13.060272 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7546 10:52:13.067362 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7547 10:52:13.070326 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7548 10:52:13.073491 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7549 10:52:13.077206 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7550 10:52:13.080365 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7551 10:52:13.080851
7552 10:52:13.083420 CA PerBit enable=1, Macro0, CA PI delay=35
7553 10:52:13.083864
7554 10:52:13.087237 [CBTSetCACLKResult] CA Dly = 35
7555 10:52:13.090448 CS Dly: 9 (0~40)
7556 10:52:13.093561 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 10:52:13.096848 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 10:52:13.097287 ==
7559 10:52:13.100631 Dram Type= 6, Freq= 0, CH_0, rank 1
7560 10:52:13.103828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 10:52:13.107108 ==
7562 10:52:13.110384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 10:52:13.113682 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 10:52:13.119973 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 10:52:13.123909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 10:52:13.133803 [CA 0] Center 42 (12~73) winsize 62
7567 10:52:13.137529 [CA 1] Center 42 (12~73) winsize 62
7568 10:52:13.140284 [CA 2] Center 38 (8~68) winsize 61
7569 10:52:13.144134 [CA 3] Center 37 (7~68) winsize 62
7570 10:52:13.147287 [CA 4] Center 35 (6~65) winsize 60
7571 10:52:13.150387 [CA 5] Center 35 (5~65) winsize 61
7572 10:52:13.150902
7573 10:52:13.153637 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7574 10:52:13.154111
7575 10:52:13.157408 [CATrainingPosCal] consider 2 rank data
7576 10:52:13.160140 u2DelayCellTimex100 = 285/100 ps
7577 10:52:13.163521 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7578 10:52:13.170480 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7579 10:52:13.173427 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7580 10:52:13.176614 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7581 10:52:13.180221 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7582 10:52:13.183321 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7583 10:52:13.183852
7584 10:52:13.186995 CA PerBit enable=1, Macro0, CA PI delay=35
7585 10:52:13.187454
7586 10:52:13.190013 [CBTSetCACLKResult] CA Dly = 35
7587 10:52:13.193785 CS Dly: 10 (0~42)
7588 10:52:13.196895 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 10:52:13.200117 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 10:52:13.200535
7591 10:52:13.203186 ----->DramcWriteLeveling(PI) begin...
7592 10:52:13.203663 ==
7593 10:52:13.206438 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 10:52:13.213602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 10:52:13.214028 ==
7596 10:52:13.216812 Write leveling (Byte 0): 34 => 34
7597 10:52:13.217237 Write leveling (Byte 1): 28 => 28
7598 10:52:13.220042 DramcWriteLeveling(PI) end<-----
7599 10:52:13.220462
7600 10:52:13.220794 ==
7601 10:52:13.223292 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 10:52:13.230075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 10:52:13.230543 ==
7604 10:52:13.233189 [Gating] SW mode calibration
7605 10:52:13.240362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7606 10:52:13.243581 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7607 10:52:13.250065 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 10:52:13.253282 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 10:52:13.256578 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7610 10:52:13.263804 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7611 10:52:13.266661 1 4 16 | B1->B0 | 2323 3938 | 0 1 | (0 0) (1 1)
7612 10:52:13.270259 1 4 20 | B1->B0 | 3333 3736 | 0 1 | (0 0) (1 1)
7613 10:52:13.276928 1 4 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 1)
7614 10:52:13.279960 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7615 10:52:13.283258 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7616 10:52:13.290108 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7617 10:52:13.293243 1 5 8 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 1)
7618 10:52:13.296247 1 5 12 | B1->B0 | 3434 302f | 1 1 | (1 1) (0 1)
7619 10:52:13.303318 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (0 1) (1 1)
7620 10:52:13.306418 1 5 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
7621 10:52:13.309610 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7622 10:52:13.312665 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7623 10:52:13.320005 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7624 10:52:13.323065 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
7625 10:52:13.326137 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7626 10:52:13.332815 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7627 10:52:13.335974 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
7628 10:52:13.339697 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 10:52:13.346167 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 10:52:13.349270 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 10:52:13.352975 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 10:52:13.359157 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 10:52:13.362881 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 10:52:13.366262 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 10:52:13.373087 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 10:52:13.376360 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 10:52:13.379420 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 10:52:13.386315 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 10:52:13.389473 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:52:13.392797 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 10:52:13.399260 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 10:52:13.402382 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 10:52:13.406168 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 10:52:13.412661 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 10:52:13.415854 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 10:52:13.419587 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 10:52:13.425880 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 10:52:13.429072 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 10:52:13.432268 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7650 10:52:13.439314 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 10:52:13.442343 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 10:52:13.445719 Total UI for P1: 0, mck2ui 16
7653 10:52:13.448852 best dqsien dly found for B0: ( 1, 9, 8)
7654 10:52:13.452720 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 10:52:13.455919 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 10:52:13.459086 Total UI for P1: 0, mck2ui 16
7657 10:52:13.462139 best dqsien dly found for B1: ( 1, 9, 18)
7658 10:52:13.465774 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7659 10:52:13.472166 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7660 10:52:13.472669
7661 10:52:13.475984 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7662 10:52:13.479191 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7663 10:52:13.482308 [Gating] SW calibration Done
7664 10:52:13.482760 ==
7665 10:52:13.485591 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 10:52:13.489269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 10:52:13.489735 ==
7668 10:52:13.492358 RX Vref Scan: 0
7669 10:52:13.492889
7670 10:52:13.493261 RX Vref 0 -> 0, step: 1
7671 10:52:13.493582
7672 10:52:13.495449 RX Delay 0 -> 252, step: 8
7673 10:52:13.498672 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7674 10:52:13.502393 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7675 10:52:13.509222 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7676 10:52:13.511964 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7677 10:52:13.515771 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7678 10:52:13.518793 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7679 10:52:13.522211 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7680 10:52:13.529140 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7681 10:52:13.532161 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7682 10:52:13.535413 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7683 10:52:13.538649 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7684 10:52:13.541961 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7685 10:52:13.548808 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7686 10:52:13.551791 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7687 10:52:13.555720 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7688 10:52:13.558756 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7689 10:52:13.559310 ==
7690 10:52:13.562097 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 10:52:13.568532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 10:52:13.568964 ==
7693 10:52:13.569303 DQS Delay:
7694 10:52:13.569622 DQS0 = 0, DQS1 = 0
7695 10:52:13.572163 DQM Delay:
7696 10:52:13.572706 DQM0 = 137, DQM1 = 131
7697 10:52:13.575048 DQ Delay:
7698 10:52:13.578869 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7699 10:52:13.582087 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7700 10:52:13.585201 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7701 10:52:13.588383 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7702 10:52:13.588807
7703 10:52:13.589139
7704 10:52:13.589451 ==
7705 10:52:13.591670 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 10:52:13.594870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 10:52:13.598649 ==
7708 10:52:13.599071
7709 10:52:13.599459
7710 10:52:13.599870 TX Vref Scan disable
7711 10:52:13.601749 == TX Byte 0 ==
7712 10:52:13.604842 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7713 10:52:13.608605 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7714 10:52:13.611803 == TX Byte 1 ==
7715 10:52:13.614950 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7716 10:52:13.618101 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7717 10:52:13.618524 ==
7718 10:52:13.621771 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 10:52:13.628464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 10:52:13.629027 ==
7721 10:52:13.640832
7722 10:52:13.643916 TX Vref early break, caculate TX vref
7723 10:52:13.647842 TX Vref=16, minBit 3, minWin=23, winSum=382
7724 10:52:13.650965 TX Vref=18, minBit 0, minWin=24, winSum=389
7725 10:52:13.654505 TX Vref=20, minBit 7, minWin=23, winSum=399
7726 10:52:13.657736 TX Vref=22, minBit 1, minWin=25, winSum=412
7727 10:52:13.660776 TX Vref=24, minBit 2, minWin=25, winSum=418
7728 10:52:13.667233 TX Vref=26, minBit 2, minWin=25, winSum=426
7729 10:52:13.670445 TX Vref=28, minBit 0, minWin=25, winSum=423
7730 10:52:13.674283 TX Vref=30, minBit 6, minWin=24, winSum=416
7731 10:52:13.677472 TX Vref=32, minBit 1, minWin=24, winSum=406
7732 10:52:13.680448 TX Vref=34, minBit 2, minWin=23, winSum=396
7733 10:52:13.687186 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 26
7734 10:52:13.687808
7735 10:52:13.690257 Final TX Range 0 Vref 26
7736 10:52:13.690676
7737 10:52:13.691002 ==
7738 10:52:13.694130 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 10:52:13.697283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 10:52:13.697708 ==
7741 10:52:13.698042
7742 10:52:13.698343
7743 10:52:13.700408 TX Vref Scan disable
7744 10:52:13.706815 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7745 10:52:13.707233 == TX Byte 0 ==
7746 10:52:13.710780 u2DelayCellOfst[0]=13 cells (4 PI)
7747 10:52:13.713774 u2DelayCellOfst[1]=13 cells (4 PI)
7748 10:52:13.716850 u2DelayCellOfst[2]=10 cells (3 PI)
7749 10:52:13.720715 u2DelayCellOfst[3]=6 cells (2 PI)
7750 10:52:13.723795 u2DelayCellOfst[4]=6 cells (2 PI)
7751 10:52:13.727624 u2DelayCellOfst[5]=0 cells (0 PI)
7752 10:52:13.728042 u2DelayCellOfst[6]=17 cells (5 PI)
7753 10:52:13.730267 u2DelayCellOfst[7]=17 cells (5 PI)
7754 10:52:13.737370 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7755 10:52:13.740420 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7756 10:52:13.740841 == TX Byte 1 ==
7757 10:52:13.743895 u2DelayCellOfst[8]=0 cells (0 PI)
7758 10:52:13.747251 u2DelayCellOfst[9]=3 cells (1 PI)
7759 10:52:13.750503 u2DelayCellOfst[10]=6 cells (2 PI)
7760 10:52:13.753503 u2DelayCellOfst[11]=3 cells (1 PI)
7761 10:52:13.757382 u2DelayCellOfst[12]=10 cells (3 PI)
7762 10:52:13.760406 u2DelayCellOfst[13]=13 cells (4 PI)
7763 10:52:13.763416 u2DelayCellOfst[14]=17 cells (5 PI)
7764 10:52:13.766632 u2DelayCellOfst[15]=10 cells (3 PI)
7765 10:52:13.770589 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7766 10:52:13.777114 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7767 10:52:13.777534 DramC Write-DBI on
7768 10:52:13.777861 ==
7769 10:52:13.780106 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 10:52:13.783400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 10:52:13.783831 ==
7772 10:52:13.787040
7773 10:52:13.787564
7774 10:52:13.787931 TX Vref Scan disable
7775 10:52:13.789964 == TX Byte 0 ==
7776 10:52:13.793642 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7777 10:52:13.796770 == TX Byte 1 ==
7778 10:52:13.799966 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7779 10:52:13.803926 DramC Write-DBI off
7780 10:52:13.804454
7781 10:52:13.804787 [DATLAT]
7782 10:52:13.805091 Freq=1600, CH0 RK0
7783 10:52:13.805486
7784 10:52:13.806897 DATLAT Default: 0xf
7785 10:52:13.807315 0, 0xFFFF, sum = 0
7786 10:52:13.810150 1, 0xFFFF, sum = 0
7787 10:52:13.810574 2, 0xFFFF, sum = 0
7788 10:52:13.813369 3, 0xFFFF, sum = 0
7789 10:52:13.816491 4, 0xFFFF, sum = 0
7790 10:52:13.816983 5, 0xFFFF, sum = 0
7791 10:52:13.819607 6, 0xFFFF, sum = 0
7792 10:52:13.820070 7, 0xFFFF, sum = 0
7793 10:52:13.823377 8, 0xFFFF, sum = 0
7794 10:52:13.823809 9, 0xFFFF, sum = 0
7795 10:52:13.826817 10, 0xFFFF, sum = 0
7796 10:52:13.827449 11, 0xFFFF, sum = 0
7797 10:52:13.829814 12, 0xFFFF, sum = 0
7798 10:52:13.830234 13, 0xFFFF, sum = 0
7799 10:52:13.832850 14, 0x0, sum = 1
7800 10:52:13.833310 15, 0x0, sum = 2
7801 10:52:13.836718 16, 0x0, sum = 3
7802 10:52:13.837182 17, 0x0, sum = 4
7803 10:52:13.839671 best_step = 15
7804 10:52:13.840086
7805 10:52:13.840458 ==
7806 10:52:13.843320 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 10:52:13.846369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 10:52:13.846793 ==
7809 10:52:13.849436 RX Vref Scan: 1
7810 10:52:13.849949
7811 10:52:13.850362 Set Vref Range= 24 -> 127
7812 10:52:13.850784
7813 10:52:13.853312 RX Vref 24 -> 127, step: 1
7814 10:52:13.853761
7815 10:52:13.856561 RX Delay 27 -> 252, step: 4
7816 10:52:13.856979
7817 10:52:13.859745 Set Vref, RX VrefLevel [Byte0]: 24
7818 10:52:13.862831 [Byte1]: 24
7819 10:52:13.863250
7820 10:52:13.865975 Set Vref, RX VrefLevel [Byte0]: 25
7821 10:52:13.869718 [Byte1]: 25
7822 10:52:13.870138
7823 10:52:13.872762 Set Vref, RX VrefLevel [Byte0]: 26
7824 10:52:13.876481 [Byte1]: 26
7825 10:52:13.880172
7826 10:52:13.880586 Set Vref, RX VrefLevel [Byte0]: 27
7827 10:52:13.883421 [Byte1]: 27
7828 10:52:13.887972
7829 10:52:13.888387 Set Vref, RX VrefLevel [Byte0]: 28
7830 10:52:13.890894 [Byte1]: 28
7831 10:52:13.895408
7832 10:52:13.896029 Set Vref, RX VrefLevel [Byte0]: 29
7833 10:52:13.898455 [Byte1]: 29
7834 10:52:13.902599
7835 10:52:13.903073 Set Vref, RX VrefLevel [Byte0]: 30
7836 10:52:13.906598 [Byte1]: 30
7837 10:52:13.910668
7838 10:52:13.911095 Set Vref, RX VrefLevel [Byte0]: 31
7839 10:52:13.913723 [Byte1]: 31
7840 10:52:13.918340
7841 10:52:13.918762 Set Vref, RX VrefLevel [Byte0]: 32
7842 10:52:13.921332 [Byte1]: 32
7843 10:52:13.925608
7844 10:52:13.926030 Set Vref, RX VrefLevel [Byte0]: 33
7845 10:52:13.928588 [Byte1]: 33
7846 10:52:13.933230
7847 10:52:13.933649 Set Vref, RX VrefLevel [Byte0]: 34
7848 10:52:13.936242 [Byte1]: 34
7849 10:52:13.940357
7850 10:52:13.940868 Set Vref, RX VrefLevel [Byte0]: 35
7851 10:52:13.943778 [Byte1]: 35
7852 10:52:13.948297
7853 10:52:13.948730 Set Vref, RX VrefLevel [Byte0]: 36
7854 10:52:13.951393 [Byte1]: 36
7855 10:52:13.955654
7856 10:52:13.956073 Set Vref, RX VrefLevel [Byte0]: 37
7857 10:52:13.959030 [Byte1]: 37
7858 10:52:13.963254
7859 10:52:13.963709 Set Vref, RX VrefLevel [Byte0]: 38
7860 10:52:13.966390 [Byte1]: 38
7861 10:52:13.970660
7862 10:52:13.971126 Set Vref, RX VrefLevel [Byte0]: 39
7863 10:52:13.973769 [Byte1]: 39
7864 10:52:13.978127
7865 10:52:13.978725 Set Vref, RX VrefLevel [Byte0]: 40
7866 10:52:13.981285 [Byte1]: 40
7867 10:52:13.985744
7868 10:52:13.986171 Set Vref, RX VrefLevel [Byte0]: 41
7869 10:52:13.988846 [Byte1]: 41
7870 10:52:13.993164
7871 10:52:13.993501 Set Vref, RX VrefLevel [Byte0]: 42
7872 10:52:13.996213 [Byte1]: 42
7873 10:52:14.000433
7874 10:52:14.000661 Set Vref, RX VrefLevel [Byte0]: 43
7875 10:52:14.003422 [Byte1]: 43
7876 10:52:14.008279
7877 10:52:14.008434 Set Vref, RX VrefLevel [Byte0]: 44
7878 10:52:14.011154 [Byte1]: 44
7879 10:52:14.015238
7880 10:52:14.015382 Set Vref, RX VrefLevel [Byte0]: 45
7881 10:52:14.018685 [Byte1]: 45
7882 10:52:14.023058
7883 10:52:14.023165 Set Vref, RX VrefLevel [Byte0]: 46
7884 10:52:14.026310 [Byte1]: 46
7885 10:52:14.030478
7886 10:52:14.030571 Set Vref, RX VrefLevel [Byte0]: 47
7887 10:52:14.034406 [Byte1]: 47
7888 10:52:14.038038
7889 10:52:14.038126 Set Vref, RX VrefLevel [Byte0]: 48
7890 10:52:14.041258 [Byte1]: 48
7891 10:52:14.045349
7892 10:52:14.045436 Set Vref, RX VrefLevel [Byte0]: 49
7893 10:52:14.048886 [Byte1]: 49
7894 10:52:14.052970
7895 10:52:14.053058 Set Vref, RX VrefLevel [Byte0]: 50
7896 10:52:14.056433 [Byte1]: 50
7897 10:52:14.060926
7898 10:52:14.061018 Set Vref, RX VrefLevel [Byte0]: 51
7899 10:52:14.064001 [Byte1]: 51
7900 10:52:14.068080
7901 10:52:14.068156 Set Vref, RX VrefLevel [Byte0]: 52
7902 10:52:14.071992 [Byte1]: 52
7903 10:52:14.075701
7904 10:52:14.075779 Set Vref, RX VrefLevel [Byte0]: 53
7905 10:52:14.079263 [Byte1]: 53
7906 10:52:14.082962
7907 10:52:14.083046 Set Vref, RX VrefLevel [Byte0]: 54
7908 10:52:14.086627 [Byte1]: 54
7909 10:52:14.091163
7910 10:52:14.091270 Set Vref, RX VrefLevel [Byte0]: 55
7911 10:52:14.094261 [Byte1]: 55
7912 10:52:14.098717
7913 10:52:14.098801 Set Vref, RX VrefLevel [Byte0]: 56
7914 10:52:14.101837 [Byte1]: 56
7915 10:52:14.105839
7916 10:52:14.105930 Set Vref, RX VrefLevel [Byte0]: 57
7917 10:52:14.109460 [Byte1]: 57
7918 10:52:14.113623
7919 10:52:14.113707 Set Vref, RX VrefLevel [Byte0]: 58
7920 10:52:14.116447 [Byte1]: 58
7921 10:52:14.120658
7922 10:52:14.120741 Set Vref, RX VrefLevel [Byte0]: 59
7923 10:52:14.124268 [Byte1]: 59
7924 10:52:14.128522
7925 10:52:14.128606 Set Vref, RX VrefLevel [Byte0]: 60
7926 10:52:14.132079 [Byte1]: 60
7927 10:52:14.136477
7928 10:52:14.136561 Set Vref, RX VrefLevel [Byte0]: 61
7929 10:52:14.139440 [Byte1]: 61
7930 10:52:14.143331
7931 10:52:14.143426 Set Vref, RX VrefLevel [Byte0]: 62
7932 10:52:14.147234 [Byte1]: 62
7933 10:52:14.151051
7934 10:52:14.151128 Set Vref, RX VrefLevel [Byte0]: 63
7935 10:52:14.154531 [Byte1]: 63
7936 10:52:14.158590
7937 10:52:14.158662 Set Vref, RX VrefLevel [Byte0]: 64
7938 10:52:14.161758 [Byte1]: 64
7939 10:52:14.166463
7940 10:52:14.166537 Set Vref, RX VrefLevel [Byte0]: 65
7941 10:52:14.169469 [Byte1]: 65
7942 10:52:14.173609
7943 10:52:14.173687 Set Vref, RX VrefLevel [Byte0]: 66
7944 10:52:14.177063 [Byte1]: 66
7945 10:52:14.181528
7946 10:52:14.181675 Set Vref, RX VrefLevel [Byte0]: 67
7947 10:52:14.184320 [Byte1]: 67
7948 10:52:14.188622
7949 10:52:14.188748 Set Vref, RX VrefLevel [Byte0]: 68
7950 10:52:14.191896 [Byte1]: 68
7951 10:52:14.196334
7952 10:52:14.196461 Set Vref, RX VrefLevel [Byte0]: 69
7953 10:52:14.199913 [Byte1]: 69
7954 10:52:14.203920
7955 10:52:14.204005 Set Vref, RX VrefLevel [Byte0]: 70
7956 10:52:14.206993 [Byte1]: 70
7957 10:52:14.211281
7958 10:52:14.211413 Set Vref, RX VrefLevel [Byte0]: 71
7959 10:52:14.218314 [Byte1]: 71
7960 10:52:14.218405
7961 10:52:14.221208 Set Vref, RX VrefLevel [Byte0]: 72
7962 10:52:14.224733 [Byte1]: 72
7963 10:52:14.224816
7964 10:52:14.228030 Set Vref, RX VrefLevel [Byte0]: 73
7965 10:52:14.231014 [Byte1]: 73
7966 10:52:14.231101
7967 10:52:14.234703 Final RX Vref Byte 0 = 57 to rank0
7968 10:52:14.237774 Final RX Vref Byte 1 = 62 to rank0
7969 10:52:14.241354 Final RX Vref Byte 0 = 57 to rank1
7970 10:52:14.244546 Final RX Vref Byte 1 = 62 to rank1==
7971 10:52:14.247775 Dram Type= 6, Freq= 0, CH_0, rank 0
7972 10:52:14.250996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 10:52:14.254215 ==
7974 10:52:14.254351 DQS Delay:
7975 10:52:14.254458 DQS0 = 0, DQS1 = 0
7976 10:52:14.257898 DQM Delay:
7977 10:52:14.258051 DQM0 = 133, DQM1 = 128
7978 10:52:14.260944 DQ Delay:
7979 10:52:14.264080 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =132
7980 10:52:14.267699 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7981 10:52:14.270612 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7982 10:52:14.274059 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7983 10:52:14.274301
7984 10:52:14.274492
7985 10:52:14.274668
7986 10:52:14.277974 [DramC_TX_OE_Calibration] TA2
7987 10:52:14.280984 Original DQ_B0 (3 6) =30, OEN = 27
7988 10:52:14.284793 Original DQ_B1 (3 6) =30, OEN = 27
7989 10:52:14.285181 24, 0x0, End_B0=24 End_B1=24
7990 10:52:14.287756 25, 0x0, End_B0=25 End_B1=25
7991 10:52:14.291174 26, 0x0, End_B0=26 End_B1=26
7992 10:52:14.294341 27, 0x0, End_B0=27 End_B1=27
7993 10:52:14.297611 28, 0x0, End_B0=28 End_B1=28
7994 10:52:14.298038 29, 0x0, End_B0=29 End_B1=29
7995 10:52:14.301445 30, 0x0, End_B0=30 End_B1=30
7996 10:52:14.304752 31, 0x4141, End_B0=30 End_B1=30
7997 10:52:14.307865 Byte0 end_step=30 best_step=27
7998 10:52:14.311687 Byte1 end_step=30 best_step=27
7999 10:52:14.312126 Byte0 TX OE(2T, 0.5T) = (3, 3)
8000 10:52:14.314871 Byte1 TX OE(2T, 0.5T) = (3, 3)
8001 10:52:14.315288
8002 10:52:14.315712
8003 10:52:14.324468 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8004 10:52:14.327994 CH0 RK0: MR19=303, MR18=2521
8005 10:52:14.331035 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8006 10:52:14.334401
8007 10:52:14.338088 ----->DramcWriteLeveling(PI) begin...
8008 10:52:14.338517 ==
8009 10:52:14.341447 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 10:52:14.344405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 10:52:14.344832 ==
8012 10:52:14.347879 Write leveling (Byte 0): 36 => 36
8013 10:52:14.351069 Write leveling (Byte 1): 29 => 29
8014 10:52:14.354763 DramcWriteLeveling(PI) end<-----
8015 10:52:14.355206
8016 10:52:14.355733 ==
8017 10:52:14.358092 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 10:52:14.361198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 10:52:14.361635 ==
8020 10:52:14.364935 [Gating] SW mode calibration
8021 10:52:14.371642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8022 10:52:14.377595 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8023 10:52:14.381357 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 10:52:14.384288 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8025 10:52:14.391147 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 10:52:14.394200 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8027 10:52:14.397913 1 4 16 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
8028 10:52:14.403970 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8029 10:52:14.407774 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8030 10:52:14.410829 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8031 10:52:14.414634 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8032 10:52:14.420905 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8033 10:52:14.424044 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8034 10:52:14.427775 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8035 10:52:14.434040 1 5 16 | B1->B0 | 2c2c 2727 | 1 0 | (1 0) (1 0)
8036 10:52:14.437742 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 10:52:14.440602 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8038 10:52:14.447377 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8039 10:52:14.450944 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 10:52:14.453631 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 10:52:14.460551 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 10:52:14.464446 1 6 12 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
8043 10:52:14.467645 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8044 10:52:14.474104 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 10:52:14.477194 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 10:52:14.480920 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 10:52:14.487033 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 10:52:14.490545 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 10:52:14.493666 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 10:52:14.500225 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8051 10:52:14.503969 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:52:14.507073 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:52:14.513566 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 10:52:14.517355 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 10:52:14.520436 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 10:52:14.527252 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:52:14.530470 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 10:52:14.533690 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:52:14.540606 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:52:14.543625 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:52:14.547381 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 10:52:14.553739 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 10:52:14.556910 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 10:52:14.560254 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 10:52:14.563596 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 10:52:14.570480 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8067 10:52:14.573664 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 10:52:14.577180 Total UI for P1: 0, mck2ui 16
8069 10:52:14.580365 best dqsien dly found for B0: ( 1, 9, 12)
8070 10:52:14.583285 Total UI for P1: 0, mck2ui 16
8071 10:52:14.587163 best dqsien dly found for B1: ( 1, 9, 12)
8072 10:52:14.590269 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8073 10:52:14.593447 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8074 10:52:14.593872
8075 10:52:14.596616 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8076 10:52:14.603763 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8077 10:52:14.604188 [Gating] SW calibration Done
8078 10:52:14.604523 ==
8079 10:52:14.606614 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 10:52:14.613644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 10:52:14.614070 ==
8082 10:52:14.614400 RX Vref Scan: 0
8083 10:52:14.614711
8084 10:52:14.616641 RX Vref 0 -> 0, step: 1
8085 10:52:14.617061
8086 10:52:14.620110 RX Delay 0 -> 252, step: 8
8087 10:52:14.623800 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8088 10:52:14.627068 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8089 10:52:14.630149 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8090 10:52:14.633296 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8091 10:52:14.639841 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8092 10:52:14.643432 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8093 10:52:14.646686 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8094 10:52:14.649839 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8095 10:52:14.653340 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8096 10:52:14.659707 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8097 10:52:14.663321 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8098 10:52:14.666525 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8099 10:52:14.669824 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8100 10:52:14.676089 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8101 10:52:14.679975 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8102 10:52:14.682872 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8103 10:52:14.683299 ==
8104 10:52:14.686484 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 10:52:14.689601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 10:52:14.690027 ==
8107 10:52:14.692864 DQS Delay:
8108 10:52:14.693282 DQS0 = 0, DQS1 = 0
8109 10:52:14.696101 DQM Delay:
8110 10:52:14.696525 DQM0 = 137, DQM1 = 129
8111 10:52:14.696864 DQ Delay:
8112 10:52:14.702691 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8113 10:52:14.706450 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8114 10:52:14.709478 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8115 10:52:14.713170 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8116 10:52:14.713596
8117 10:52:14.713931
8118 10:52:14.714238 ==
8119 10:52:14.716606 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 10:52:14.719458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 10:52:14.719887 ==
8122 10:52:14.720291
8123 10:52:14.720806
8124 10:52:14.723068 TX Vref Scan disable
8125 10:52:14.726073 == TX Byte 0 ==
8126 10:52:14.729795 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8127 10:52:14.732981 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8128 10:52:14.735931 == TX Byte 1 ==
8129 10:52:14.739857 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8130 10:52:14.742313 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8131 10:52:14.742736 ==
8132 10:52:14.746094 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 10:52:14.752426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 10:52:14.752910 ==
8135 10:52:14.764568
8136 10:52:14.768258 TX Vref early break, caculate TX vref
8137 10:52:14.771385 TX Vref=16, minBit 1, minWin=23, winSum=386
8138 10:52:14.774857 TX Vref=18, minBit 3, minWin=23, winSum=392
8139 10:52:14.778073 TX Vref=20, minBit 0, minWin=24, winSum=404
8140 10:52:14.781584 TX Vref=22, minBit 3, minWin=24, winSum=409
8141 10:52:14.784505 TX Vref=24, minBit 3, minWin=24, winSum=419
8142 10:52:14.791138 TX Vref=26, minBit 3, minWin=25, winSum=423
8143 10:52:14.794809 TX Vref=28, minBit 7, minWin=25, winSum=425
8144 10:52:14.798070 TX Vref=30, minBit 0, minWin=25, winSum=416
8145 10:52:14.801105 TX Vref=32, minBit 3, minWin=24, winSum=409
8146 10:52:14.805063 TX Vref=34, minBit 0, minWin=24, winSum=398
8147 10:52:14.810979 [TxChooseVref] Worse bit 7, Min win 25, Win sum 425, Final Vref 28
8148 10:52:14.811438
8149 10:52:14.814753 Final TX Range 0 Vref 28
8150 10:52:14.815170
8151 10:52:14.815550 ==
8152 10:52:14.817820 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 10:52:14.821474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 10:52:14.821898 ==
8155 10:52:14.822228
8156 10:52:14.822535
8157 10:52:14.824299 TX Vref Scan disable
8158 10:52:14.830885 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8159 10:52:14.831309 == TX Byte 0 ==
8160 10:52:14.834477 u2DelayCellOfst[0]=17 cells (5 PI)
8161 10:52:14.838086 u2DelayCellOfst[1]=17 cells (5 PI)
8162 10:52:14.841242 u2DelayCellOfst[2]=13 cells (4 PI)
8163 10:52:14.844337 u2DelayCellOfst[3]=10 cells (3 PI)
8164 10:52:14.847960 u2DelayCellOfst[4]=13 cells (4 PI)
8165 10:52:14.851243 u2DelayCellOfst[5]=0 cells (0 PI)
8166 10:52:14.854425 u2DelayCellOfst[6]=20 cells (6 PI)
8167 10:52:14.857564 u2DelayCellOfst[7]=20 cells (6 PI)
8168 10:52:14.860932 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8169 10:52:14.864665 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8170 10:52:14.867860 == TX Byte 1 ==
8171 10:52:14.868278 u2DelayCellOfst[8]=0 cells (0 PI)
8172 10:52:14.870824 u2DelayCellOfst[9]=0 cells (0 PI)
8173 10:52:14.874054 u2DelayCellOfst[10]=6 cells (2 PI)
8174 10:52:14.877834 u2DelayCellOfst[11]=3 cells (1 PI)
8175 10:52:14.881202 u2DelayCellOfst[12]=10 cells (3 PI)
8176 10:52:14.884194 u2DelayCellOfst[13]=10 cells (3 PI)
8177 10:52:14.887568 u2DelayCellOfst[14]=13 cells (4 PI)
8178 10:52:14.890921 u2DelayCellOfst[15]=10 cells (3 PI)
8179 10:52:14.894310 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8180 10:52:14.901006 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8181 10:52:14.901518 DramC Write-DBI on
8182 10:52:14.901850 ==
8183 10:52:14.904295 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 10:52:14.907375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 10:52:14.910643 ==
8186 10:52:14.911060
8187 10:52:14.911430
8188 10:52:14.911749 TX Vref Scan disable
8189 10:52:14.914151 == TX Byte 0 ==
8190 10:52:14.917743 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8191 10:52:14.920860 == TX Byte 1 ==
8192 10:52:14.924137 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8193 10:52:14.927854 DramC Write-DBI off
8194 10:52:14.928273
8195 10:52:14.928600 [DATLAT]
8196 10:52:14.928907 Freq=1600, CH0 RK1
8197 10:52:14.929205
8198 10:52:14.930891 DATLAT Default: 0xf
8199 10:52:14.931352 0, 0xFFFF, sum = 0
8200 10:52:14.934257 1, 0xFFFF, sum = 0
8201 10:52:14.934726 2, 0xFFFF, sum = 0
8202 10:52:14.937761 3, 0xFFFF, sum = 0
8203 10:52:14.940857 4, 0xFFFF, sum = 0
8204 10:52:14.941281 5, 0xFFFF, sum = 0
8205 10:52:14.944354 6, 0xFFFF, sum = 0
8206 10:52:14.944776 7, 0xFFFF, sum = 0
8207 10:52:14.947939 8, 0xFFFF, sum = 0
8208 10:52:14.948362 9, 0xFFFF, sum = 0
8209 10:52:14.950931 10, 0xFFFF, sum = 0
8210 10:52:14.951374 11, 0xFFFF, sum = 0
8211 10:52:14.954358 12, 0xFFFF, sum = 0
8212 10:52:14.955038 13, 0xFFFF, sum = 0
8213 10:52:14.958361 14, 0x0, sum = 1
8214 10:52:14.958894 15, 0x0, sum = 2
8215 10:52:14.961305 16, 0x0, sum = 3
8216 10:52:14.961733 17, 0x0, sum = 4
8217 10:52:14.964323 best_step = 15
8218 10:52:14.964737
8219 10:52:14.965066 ==
8220 10:52:14.967646 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 10:52:14.970728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 10:52:14.971149 ==
8223 10:52:14.971531 RX Vref Scan: 0
8224 10:52:14.974492
8225 10:52:14.974913 RX Vref 0 -> 0, step: 1
8226 10:52:14.975244
8227 10:52:14.977619 RX Delay 19 -> 252, step: 4
8228 10:52:14.980800 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8229 10:52:14.987533 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8230 10:52:14.990407 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8231 10:52:14.994081 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8232 10:52:14.997450 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8233 10:52:15.000721 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8234 10:52:15.007238 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8235 10:52:15.010798 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8236 10:52:15.013759 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8237 10:52:15.017601 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8238 10:52:15.021060 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8239 10:52:15.027347 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8240 10:52:15.030534 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8241 10:52:15.033795 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8242 10:52:15.037575 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8243 10:52:15.040419 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8244 10:52:15.040852 ==
8245 10:52:15.043843 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 10:52:15.051095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 10:52:15.051601 ==
8248 10:52:15.051952 DQS Delay:
8249 10:52:15.054036 DQS0 = 0, DQS1 = 0
8250 10:52:15.054482 DQM Delay:
8251 10:52:15.057573 DQM0 = 133, DQM1 = 127
8252 10:52:15.058121 DQ Delay:
8253 10:52:15.060652 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8254 10:52:15.063660 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140
8255 10:52:15.067476 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8256 10:52:15.070696 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8257 10:52:15.071113
8258 10:52:15.071486
8259 10:52:15.071801
8260 10:52:15.073876 [DramC_TX_OE_Calibration] TA2
8261 10:52:15.077098 Original DQ_B0 (3 6) =30, OEN = 27
8262 10:52:15.080810 Original DQ_B1 (3 6) =30, OEN = 27
8263 10:52:15.084003 24, 0x0, End_B0=24 End_B1=24
8264 10:52:15.087387 25, 0x0, End_B0=25 End_B1=25
8265 10:52:15.087816 26, 0x0, End_B0=26 End_B1=26
8266 10:52:15.090404 27, 0x0, End_B0=27 End_B1=27
8267 10:52:15.094087 28, 0x0, End_B0=28 End_B1=28
8268 10:52:15.097581 29, 0x0, End_B0=29 End_B1=29
8269 10:52:15.098005 30, 0x0, End_B0=30 End_B1=30
8270 10:52:15.100689 31, 0x4141, End_B0=30 End_B1=30
8271 10:52:15.104195 Byte0 end_step=30 best_step=27
8272 10:52:15.107119 Byte1 end_step=30 best_step=27
8273 10:52:15.110741 Byte0 TX OE(2T, 0.5T) = (3, 3)
8274 10:52:15.113667 Byte1 TX OE(2T, 0.5T) = (3, 3)
8275 10:52:15.114086
8276 10:52:15.114476
8277 10:52:15.120282 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8278 10:52:15.123966 CH0 RK1: MR19=303, MR18=220A
8279 10:52:15.130480 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8280 10:52:15.133793 [RxdqsGatingPostProcess] freq 1600
8281 10:52:15.137470 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8282 10:52:15.140580 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 10:52:15.143787 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 10:52:15.147230 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 10:52:15.150323 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 10:52:15.153477 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 10:52:15.157067 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 10:52:15.160563 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 10:52:15.163497 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 10:52:15.167096 Pre-setting of DQS Precalculation
8291 10:52:15.170313 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8292 10:52:15.170736 ==
8293 10:52:15.173452 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 10:52:15.180488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 10:52:15.180912 ==
8296 10:52:15.183671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 10:52:15.186702 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 10:52:15.193500 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 10:52:15.200206 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 10:52:15.207113 [CA 0] Center 41 (12~71) winsize 60
8301 10:52:15.210640 [CA 1] Center 41 (12~71) winsize 60
8302 10:52:15.214208 [CA 2] Center 38 (9~68) winsize 60
8303 10:52:15.217090 [CA 3] Center 37 (8~66) winsize 59
8304 10:52:15.220788 [CA 4] Center 37 (8~67) winsize 60
8305 10:52:15.224223 [CA 5] Center 36 (7~66) winsize 60
8306 10:52:15.224647
8307 10:52:15.227235 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8308 10:52:15.227738
8309 10:52:15.230755 [CATrainingPosCal] consider 1 rank data
8310 10:52:15.233862 u2DelayCellTimex100 = 285/100 ps
8311 10:52:15.237661 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8312 10:52:15.243842 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8313 10:52:15.247005 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8314 10:52:15.250546 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8315 10:52:15.253669 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8316 10:52:15.257306 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 10:52:15.257730
8318 10:52:15.260370 CA PerBit enable=1, Macro0, CA PI delay=36
8319 10:52:15.260795
8320 10:52:15.263920 [CBTSetCACLKResult] CA Dly = 36
8321 10:52:15.267321 CS Dly: 11 (0~42)
8322 10:52:15.270356 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 10:52:15.274058 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 10:52:15.274479 ==
8325 10:52:15.277222 Dram Type= 6, Freq= 0, CH_1, rank 1
8326 10:52:15.280318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 10:52:15.280741 ==
8328 10:52:15.287371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 10:52:15.290624 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 10:52:15.297671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 10:52:15.300691 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 10:52:15.310435 [CA 0] Center 42 (12~72) winsize 61
8333 10:52:15.313995 [CA 1] Center 41 (12~71) winsize 60
8334 10:52:15.316852 [CA 2] Center 38 (9~68) winsize 60
8335 10:52:15.320633 [CA 3] Center 37 (8~67) winsize 60
8336 10:52:15.323912 [CA 4] Center 38 (8~68) winsize 61
8337 10:52:15.326865 [CA 5] Center 37 (8~67) winsize 60
8338 10:52:15.327301
8339 10:52:15.330526 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8340 10:52:15.330987
8341 10:52:15.333600 [CATrainingPosCal] consider 2 rank data
8342 10:52:15.336993 u2DelayCellTimex100 = 285/100 ps
8343 10:52:15.340119 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8344 10:52:15.347149 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8345 10:52:15.350165 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8346 10:52:15.353343 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8347 10:52:15.356882 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 10:52:15.360633 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8349 10:52:15.361077
8350 10:52:15.363553 CA PerBit enable=1, Macro0, CA PI delay=37
8351 10:52:15.363992
8352 10:52:15.366478 [CBTSetCACLKResult] CA Dly = 37
8353 10:52:15.370393 CS Dly: 12 (0~45)
8354 10:52:15.373313 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 10:52:15.376711 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 10:52:15.377139
8357 10:52:15.380387 ----->DramcWriteLeveling(PI) begin...
8358 10:52:15.380818 ==
8359 10:52:15.383420 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 10:52:15.386701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 10:52:15.390371 ==
8362 10:52:15.390839 Write leveling (Byte 0): 24 => 24
8363 10:52:15.393514 Write leveling (Byte 1): 27 => 27
8364 10:52:15.396628 DramcWriteLeveling(PI) end<-----
8365 10:52:15.397119
8366 10:52:15.397475 ==
8367 10:52:15.400376 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 10:52:15.407027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 10:52:15.407345 ==
8370 10:52:15.407641 [Gating] SW mode calibration
8371 10:52:15.416521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8372 10:52:15.420130 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8373 10:52:15.426455 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 10:52:15.430033 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 10:52:15.433587 1 4 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
8376 10:52:15.436492 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8377 10:52:15.443451 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 10:52:15.446514 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 10:52:15.450322 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 10:52:15.456676 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 10:52:15.460292 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 10:52:15.463138 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 10:52:15.469995 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
8384 10:52:15.473155 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8385 10:52:15.476947 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 10:52:15.483679 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 10:52:15.486573 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 10:52:15.489645 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 10:52:15.496401 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 10:52:15.500295 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 10:52:15.503525 1 6 8 | B1->B0 | 2424 4342 | 0 1 | (0 0) (0 0)
8392 10:52:15.510202 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8393 10:52:15.514007 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 10:52:15.517030 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 10:52:15.520130 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 10:52:15.527042 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 10:52:15.530280 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 10:52:15.533643 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 10:52:15.540297 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 10:52:15.543733 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 10:52:15.546753 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:52:15.553324 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:52:15.556940 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:52:15.560150 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:52:15.567298 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:52:15.569961 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:52:15.573678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:52:15.579953 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:52:15.583067 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:52:15.586664 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:52:15.593387 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:52:15.597096 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:52:15.599936 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:52:15.606532 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 10:52:15.610286 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 10:52:15.613066 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 10:52:15.619792 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 10:52:15.620285 Total UI for P1: 0, mck2ui 16
8419 10:52:15.626729 best dqsien dly found for B0: ( 1, 9, 10)
8420 10:52:15.627209 Total UI for P1: 0, mck2ui 16
8421 10:52:15.632806 best dqsien dly found for B1: ( 1, 9, 10)
8422 10:52:15.636591 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8423 10:52:15.639544 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8424 10:52:15.640016
8425 10:52:15.643094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 10:52:15.646110 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8427 10:52:15.649820 [Gating] SW calibration Done
8428 10:52:15.650243 ==
8429 10:52:15.652889 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 10:52:15.656261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 10:52:15.656689 ==
8432 10:52:15.659885 RX Vref Scan: 0
8433 10:52:15.660307
8434 10:52:15.660637 RX Vref 0 -> 0, step: 1
8435 10:52:15.660948
8436 10:52:15.663072 RX Delay 0 -> 252, step: 8
8437 10:52:15.666294 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8438 10:52:15.673247 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8439 10:52:15.675902 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8440 10:52:15.679807 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 10:52:15.682937 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8442 10:52:15.686612 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8443 10:52:15.689737 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8444 10:52:15.696345 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8445 10:52:15.699297 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8446 10:52:15.702912 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8447 10:52:15.705939 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8448 10:52:15.709729 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8449 10:52:15.715904 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8450 10:52:15.719361 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8451 10:52:15.722473 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8452 10:52:15.726301 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8453 10:52:15.726728 ==
8454 10:52:15.729546 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 10:52:15.735891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 10:52:15.736324 ==
8457 10:52:15.736739 DQS Delay:
8458 10:52:15.739019 DQS0 = 0, DQS1 = 0
8459 10:52:15.739467 DQM Delay:
8460 10:52:15.742793 DQM0 = 136, DQM1 = 132
8461 10:52:15.743217 DQ Delay:
8462 10:52:15.745941 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8463 10:52:15.748940 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8464 10:52:15.752532 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8465 10:52:15.755999 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8466 10:52:15.756421
8467 10:52:15.756751
8468 10:52:15.757057 ==
8469 10:52:15.759422 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 10:52:15.765712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 10:52:15.766137 ==
8472 10:52:15.766589
8473 10:52:15.767036
8474 10:52:15.767383 TX Vref Scan disable
8475 10:52:15.769256 == TX Byte 0 ==
8476 10:52:15.772207 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8477 10:52:15.779133 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8478 10:52:15.779592 == TX Byte 1 ==
8479 10:52:15.782734 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8480 10:52:15.789022 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8481 10:52:15.789452 ==
8482 10:52:15.792850 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 10:52:15.795839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 10:52:15.796305 ==
8485 10:52:15.807752
8486 10:52:15.811430 TX Vref early break, caculate TX vref
8487 10:52:15.814525 TX Vref=16, minBit 0, minWin=23, winSum=380
8488 10:52:15.818379 TX Vref=18, minBit 1, minWin=23, winSum=392
8489 10:52:15.821531 TX Vref=20, minBit 1, minWin=23, winSum=397
8490 10:52:15.824688 TX Vref=22, minBit 0, minWin=25, winSum=411
8491 10:52:15.828137 TX Vref=24, minBit 0, minWin=25, winSum=421
8492 10:52:15.834497 TX Vref=26, minBit 0, minWin=25, winSum=425
8493 10:52:15.838211 TX Vref=28, minBit 0, minWin=25, winSum=428
8494 10:52:15.841434 TX Vref=30, minBit 0, minWin=25, winSum=423
8495 10:52:15.844469 TX Vref=32, minBit 2, minWin=24, winSum=414
8496 10:52:15.848211 TX Vref=34, minBit 0, minWin=24, winSum=402
8497 10:52:15.854882 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8498 10:52:15.855392
8499 10:52:15.857885 Final TX Range 0 Vref 28
8500 10:52:15.858323
8501 10:52:15.858676 ==
8502 10:52:15.861359 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 10:52:15.864888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 10:52:15.865326 ==
8505 10:52:15.865677
8506 10:52:15.865992
8507 10:52:15.867854 TX Vref Scan disable
8508 10:52:15.874782 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8509 10:52:15.875313 == TX Byte 0 ==
8510 10:52:15.877730 u2DelayCellOfst[0]=17 cells (5 PI)
8511 10:52:15.880966 u2DelayCellOfst[1]=13 cells (4 PI)
8512 10:52:15.884733 u2DelayCellOfst[2]=0 cells (0 PI)
8513 10:52:15.887821 u2DelayCellOfst[3]=10 cells (3 PI)
8514 10:52:15.890981 u2DelayCellOfst[4]=13 cells (4 PI)
8515 10:52:15.894261 u2DelayCellOfst[5]=20 cells (6 PI)
8516 10:52:15.898076 u2DelayCellOfst[6]=20 cells (6 PI)
8517 10:52:15.898499 u2DelayCellOfst[7]=10 cells (3 PI)
8518 10:52:15.904235 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8519 10:52:15.907807 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8520 10:52:15.911360 == TX Byte 1 ==
8521 10:52:15.911790 u2DelayCellOfst[8]=0 cells (0 PI)
8522 10:52:15.914432 u2DelayCellOfst[9]=3 cells (1 PI)
8523 10:52:15.917927 u2DelayCellOfst[10]=13 cells (4 PI)
8524 10:52:15.920967 u2DelayCellOfst[11]=3 cells (1 PI)
8525 10:52:15.924613 u2DelayCellOfst[12]=17 cells (5 PI)
8526 10:52:15.927837 u2DelayCellOfst[13]=17 cells (5 PI)
8527 10:52:15.930711 u2DelayCellOfst[14]=17 cells (5 PI)
8528 10:52:15.934482 u2DelayCellOfst[15]=17 cells (5 PI)
8529 10:52:15.937600 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8530 10:52:15.944642 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8531 10:52:15.945066 DramC Write-DBI on
8532 10:52:15.945397 ==
8533 10:52:15.947853 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 10:52:15.950924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 10:52:15.954111 ==
8536 10:52:15.954526
8537 10:52:15.954852
8538 10:52:15.955155 TX Vref Scan disable
8539 10:52:15.957928 == TX Byte 0 ==
8540 10:52:15.961142 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8541 10:52:15.964110 == TX Byte 1 ==
8542 10:52:15.967420 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8543 10:52:15.970924 DramC Write-DBI off
8544 10:52:15.971372
8545 10:52:15.971711 [DATLAT]
8546 10:52:15.972021 Freq=1600, CH1 RK0
8547 10:52:15.972317
8548 10:52:15.974259 DATLAT Default: 0xf
8549 10:52:15.974674 0, 0xFFFF, sum = 0
8550 10:52:15.977284 1, 0xFFFF, sum = 0
8551 10:52:15.980649 2, 0xFFFF, sum = 0
8552 10:52:15.981076 3, 0xFFFF, sum = 0
8553 10:52:15.984345 4, 0xFFFF, sum = 0
8554 10:52:15.984775 5, 0xFFFF, sum = 0
8555 10:52:15.987111 6, 0xFFFF, sum = 0
8556 10:52:15.987596 7, 0xFFFF, sum = 0
8557 10:52:15.990680 8, 0xFFFF, sum = 0
8558 10:52:15.991061 9, 0xFFFF, sum = 0
8559 10:52:15.993864 10, 0xFFFF, sum = 0
8560 10:52:15.994261 11, 0xFFFF, sum = 0
8561 10:52:15.997297 12, 0xFFFF, sum = 0
8562 10:52:15.997869 13, 0xFFFF, sum = 0
8563 10:52:16.000966 14, 0x0, sum = 1
8564 10:52:16.001422 15, 0x0, sum = 2
8565 10:52:16.003927 16, 0x0, sum = 3
8566 10:52:16.004385 17, 0x0, sum = 4
8567 10:52:16.007240 best_step = 15
8568 10:52:16.007727
8569 10:52:16.008083 ==
8570 10:52:16.010849 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 10:52:16.014048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 10:52:16.014510 ==
8573 10:52:16.017467 RX Vref Scan: 1
8574 10:52:16.017914
8575 10:52:16.018252 Set Vref Range= 24 -> 127
8576 10:52:16.018589
8577 10:52:16.020408 RX Vref 24 -> 127, step: 1
8578 10:52:16.020835
8579 10:52:16.023991 RX Delay 27 -> 252, step: 4
8580 10:52:16.024440
8581 10:52:16.027089 Set Vref, RX VrefLevel [Byte0]: 24
8582 10:52:16.030584 [Byte1]: 24
8583 10:52:16.031037
8584 10:52:16.033786 Set Vref, RX VrefLevel [Byte0]: 25
8585 10:52:16.037404 [Byte1]: 25
8586 10:52:16.037839
8587 10:52:16.040782 Set Vref, RX VrefLevel [Byte0]: 26
8588 10:52:16.043656 [Byte1]: 26
8589 10:52:16.047667
8590 10:52:16.048110 Set Vref, RX VrefLevel [Byte0]: 27
8591 10:52:16.051466 [Byte1]: 27
8592 10:52:16.055158
8593 10:52:16.055630 Set Vref, RX VrefLevel [Byte0]: 28
8594 10:52:16.058351 [Byte1]: 28
8595 10:52:16.062823
8596 10:52:16.063425 Set Vref, RX VrefLevel [Byte0]: 29
8597 10:52:16.066112 [Byte1]: 29
8598 10:52:16.070396
8599 10:52:16.070842 Set Vref, RX VrefLevel [Byte0]: 30
8600 10:52:16.073927 [Byte1]: 30
8601 10:52:16.077884
8602 10:52:16.078309 Set Vref, RX VrefLevel [Byte0]: 31
8603 10:52:16.081675 [Byte1]: 31
8604 10:52:16.085545
8605 10:52:16.086006 Set Vref, RX VrefLevel [Byte0]: 32
8606 10:52:16.088643 [Byte1]: 32
8607 10:52:16.092679
8608 10:52:16.093104 Set Vref, RX VrefLevel [Byte0]: 33
8609 10:52:16.096244 [Byte1]: 33
8610 10:52:16.100402
8611 10:52:16.100826 Set Vref, RX VrefLevel [Byte0]: 34
8612 10:52:16.104079 [Byte1]: 34
8613 10:52:16.107995
8614 10:52:16.108455 Set Vref, RX VrefLevel [Byte0]: 35
8615 10:52:16.111187 [Byte1]: 35
8616 10:52:16.115439
8617 10:52:16.115880 Set Vref, RX VrefLevel [Byte0]: 36
8618 10:52:16.118514 [Byte1]: 36
8619 10:52:16.123197
8620 10:52:16.123683 Set Vref, RX VrefLevel [Byte0]: 37
8621 10:52:16.126201 [Byte1]: 37
8622 10:52:16.130501
8623 10:52:16.130962 Set Vref, RX VrefLevel [Byte0]: 38
8624 10:52:16.134117 [Byte1]: 38
8625 10:52:16.137947
8626 10:52:16.138386 Set Vref, RX VrefLevel [Byte0]: 39
8627 10:52:16.141497 [Byte1]: 39
8628 10:52:16.145767
8629 10:52:16.146205 Set Vref, RX VrefLevel [Byte0]: 40
8630 10:52:16.148854 [Byte1]: 40
8631 10:52:16.153226
8632 10:52:16.153698 Set Vref, RX VrefLevel [Byte0]: 41
8633 10:52:16.156615 [Byte1]: 41
8634 10:52:16.160936
8635 10:52:16.161523 Set Vref, RX VrefLevel [Byte0]: 42
8636 10:52:16.164097 [Byte1]: 42
8637 10:52:16.168371
8638 10:52:16.168830 Set Vref, RX VrefLevel [Byte0]: 43
8639 10:52:16.171475 [Byte1]: 43
8640 10:52:16.175538
8641 10:52:16.176009 Set Vref, RX VrefLevel [Byte0]: 44
8642 10:52:16.179304 [Byte1]: 44
8643 10:52:16.183170
8644 10:52:16.183679 Set Vref, RX VrefLevel [Byte0]: 45
8645 10:52:16.186646 [Byte1]: 45
8646 10:52:16.190803
8647 10:52:16.191275 Set Vref, RX VrefLevel [Byte0]: 46
8648 10:52:16.194368 [Byte1]: 46
8649 10:52:16.198483
8650 10:52:16.198929 Set Vref, RX VrefLevel [Byte0]: 47
8651 10:52:16.201309 [Byte1]: 47
8652 10:52:16.205837
8653 10:52:16.206260 Set Vref, RX VrefLevel [Byte0]: 48
8654 10:52:16.208956 [Byte1]: 48
8655 10:52:16.213414
8656 10:52:16.213835 Set Vref, RX VrefLevel [Byte0]: 49
8657 10:52:16.216579 [Byte1]: 49
8658 10:52:16.220892
8659 10:52:16.221313 Set Vref, RX VrefLevel [Byte0]: 50
8660 10:52:16.224493 [Byte1]: 50
8661 10:52:16.228258
8662 10:52:16.228680 Set Vref, RX VrefLevel [Byte0]: 51
8663 10:52:16.231798 [Byte1]: 51
8664 10:52:16.236062
8665 10:52:16.236583 Set Vref, RX VrefLevel [Byte0]: 52
8666 10:52:16.239770 [Byte1]: 52
8667 10:52:16.243962
8668 10:52:16.244385 Set Vref, RX VrefLevel [Byte0]: 53
8669 10:52:16.246843 [Byte1]: 53
8670 10:52:16.251234
8671 10:52:16.251692 Set Vref, RX VrefLevel [Byte0]: 54
8672 10:52:16.254322 [Byte1]: 54
8673 10:52:16.258766
8674 10:52:16.259509 Set Vref, RX VrefLevel [Byte0]: 55
8675 10:52:16.262344 [Byte1]: 55
8676 10:52:16.265866
8677 10:52:16.266297 Set Vref, RX VrefLevel [Byte0]: 56
8678 10:52:16.269069 [Byte1]: 56
8679 10:52:16.273649
8680 10:52:16.274069 Set Vref, RX VrefLevel [Byte0]: 57
8681 10:52:16.276675 [Byte1]: 57
8682 10:52:16.281018
8683 10:52:16.281479 Set Vref, RX VrefLevel [Byte0]: 58
8684 10:52:16.284547 [Byte1]: 58
8685 10:52:16.288473
8686 10:52:16.288922 Set Vref, RX VrefLevel [Byte0]: 59
8687 10:52:16.291915 [Byte1]: 59
8688 10:52:16.296456
8689 10:52:16.296922 Set Vref, RX VrefLevel [Byte0]: 60
8690 10:52:16.299419 [Byte1]: 60
8691 10:52:16.303705
8692 10:52:16.304126 Set Vref, RX VrefLevel [Byte0]: 61
8693 10:52:16.307316 [Byte1]: 61
8694 10:52:16.311259
8695 10:52:16.311715 Set Vref, RX VrefLevel [Byte0]: 62
8696 10:52:16.314623 [Byte1]: 62
8697 10:52:16.318592
8698 10:52:16.319015 Set Vref, RX VrefLevel [Byte0]: 63
8699 10:52:16.322284 [Byte1]: 63
8700 10:52:16.326108
8701 10:52:16.326532 Set Vref, RX VrefLevel [Byte0]: 64
8702 10:52:16.329627 [Byte1]: 64
8703 10:52:16.334429
8704 10:52:16.334956 Set Vref, RX VrefLevel [Byte0]: 65
8705 10:52:16.337226 [Byte1]: 65
8706 10:52:16.341411
8707 10:52:16.341831 Set Vref, RX VrefLevel [Byte0]: 66
8708 10:52:16.344455 [Byte1]: 66
8709 10:52:16.349044
8710 10:52:16.349460 Set Vref, RX VrefLevel [Byte0]: 67
8711 10:52:16.352397 [Byte1]: 67
8712 10:52:16.356911
8713 10:52:16.357327 Set Vref, RX VrefLevel [Byte0]: 68
8714 10:52:16.360171 [Byte1]: 68
8715 10:52:16.364071
8716 10:52:16.364591 Set Vref, RX VrefLevel [Byte0]: 69
8717 10:52:16.367791 [Byte1]: 69
8718 10:52:16.371416
8719 10:52:16.371861 Set Vref, RX VrefLevel [Byte0]: 70
8720 10:52:16.374719 [Byte1]: 70
8721 10:52:16.379323
8722 10:52:16.379886 Set Vref, RX VrefLevel [Byte0]: 71
8723 10:52:16.382370 [Byte1]: 71
8724 10:52:16.386705
8725 10:52:16.387125 Set Vref, RX VrefLevel [Byte0]: 72
8726 10:52:16.389754 [Byte1]: 72
8727 10:52:16.394344
8728 10:52:16.394783 Set Vref, RX VrefLevel [Byte0]: 73
8729 10:52:16.397209 [Byte1]: 73
8730 10:52:16.401848
8731 10:52:16.402267 Set Vref, RX VrefLevel [Byte0]: 74
8732 10:52:16.404626 [Byte1]: 74
8733 10:52:16.409362
8734 10:52:16.409780 Set Vref, RX VrefLevel [Byte0]: 75
8735 10:52:16.412460 [Byte1]: 75
8736 10:52:16.416593
8737 10:52:16.417011 Set Vref, RX VrefLevel [Byte0]: 76
8738 10:52:16.420134 [Byte1]: 76
8739 10:52:16.424143
8740 10:52:16.424584 Set Vref, RX VrefLevel [Byte0]: 77
8741 10:52:16.427390 [Byte1]: 77
8742 10:52:16.431895
8743 10:52:16.432314 Final RX Vref Byte 0 = 58 to rank0
8744 10:52:16.435017 Final RX Vref Byte 1 = 58 to rank0
8745 10:52:16.438880 Final RX Vref Byte 0 = 58 to rank1
8746 10:52:16.442038 Final RX Vref Byte 1 = 58 to rank1==
8747 10:52:16.445073 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 10:52:16.451626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 10:52:16.452053 ==
8750 10:52:16.452388 DQS Delay:
8751 10:52:16.455282 DQS0 = 0, DQS1 = 0
8752 10:52:16.455779 DQM Delay:
8753 10:52:16.456115 DQM0 = 134, DQM1 = 131
8754 10:52:16.458213 DQ Delay:
8755 10:52:16.461492 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8756 10:52:16.465271 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8757 10:52:16.468426 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124
8758 10:52:16.471466 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8759 10:52:16.471893
8760 10:52:16.472254
8761 10:52:16.472567
8762 10:52:16.475166 [DramC_TX_OE_Calibration] TA2
8763 10:52:16.478407 Original DQ_B0 (3 6) =30, OEN = 27
8764 10:52:16.481636 Original DQ_B1 (3 6) =30, OEN = 27
8765 10:52:16.484762 24, 0x0, End_B0=24 End_B1=24
8766 10:52:16.485189 25, 0x0, End_B0=25 End_B1=25
8767 10:52:16.488603 26, 0x0, End_B0=26 End_B1=26
8768 10:52:16.491785 27, 0x0, End_B0=27 End_B1=27
8769 10:52:16.495315 28, 0x0, End_B0=28 End_B1=28
8770 10:52:16.495775 29, 0x0, End_B0=29 End_B1=29
8771 10:52:16.498463 30, 0x0, End_B0=30 End_B1=30
8772 10:52:16.501831 31, 0x4141, End_B0=30 End_B1=30
8773 10:52:16.505377 Byte0 end_step=30 best_step=27
8774 10:52:16.508508 Byte1 end_step=30 best_step=27
8775 10:52:16.511864 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 10:52:16.512296 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 10:52:16.515000
8778 10:52:16.515480
8779 10:52:16.521966 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8780 10:52:16.524905 CH1 RK0: MR19=303, MR18=1826
8781 10:52:16.531802 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8782 10:52:16.532234
8783 10:52:16.534889 ----->DramcWriteLeveling(PI) begin...
8784 10:52:16.535356 ==
8785 10:52:16.538591 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 10:52:16.541717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 10:52:16.542142 ==
8788 10:52:16.544979 Write leveling (Byte 0): 26 => 26
8789 10:52:16.548134 Write leveling (Byte 1): 28 => 28
8790 10:52:16.551905 DramcWriteLeveling(PI) end<-----
8791 10:52:16.552324
8792 10:52:16.552650 ==
8793 10:52:16.554933 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 10:52:16.558451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 10:52:16.558874 ==
8796 10:52:16.561572 [Gating] SW mode calibration
8797 10:52:16.568084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 10:52:16.575354 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 10:52:16.577957 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 10:52:16.581705 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 10:52:16.588097 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8802 10:52:16.591596 1 4 12 | B1->B0 | 3333 2d2c | 0 1 | (0 0) (0 0)
8803 10:52:16.594891 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 10:52:16.601274 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 10:52:16.604906 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 10:52:16.607957 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 10:52:16.614140 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 10:52:16.617658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8809 10:52:16.621125 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8810 10:52:16.627681 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8811 10:52:16.631140 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 10:52:16.633948 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 10:52:16.641031 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 10:52:16.644170 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 10:52:16.647317 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 10:52:16.654291 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 10:52:16.657333 1 6 8 | B1->B0 | 3939 2323 | 0 0 | (0 0) (0 0)
8818 10:52:16.660500 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 10:52:16.666956 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 10:52:16.670727 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 10:52:16.674251 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 10:52:16.680712 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 10:52:16.683860 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 10:52:16.687110 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 10:52:16.694062 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8826 10:52:16.697196 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8827 10:52:16.700243 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 10:52:16.707205 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 10:52:16.710325 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 10:52:16.714143 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 10:52:16.720808 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 10:52:16.723559 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 10:52:16.727109 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 10:52:16.730630 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 10:52:16.737658 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 10:52:16.740523 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 10:52:16.744053 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 10:52:16.750215 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 10:52:16.753576 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 10:52:16.757125 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8841 10:52:16.764081 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8842 10:52:16.767262 Total UI for P1: 0, mck2ui 16
8843 10:52:16.770298 best dqsien dly found for B1: ( 1, 9, 4)
8844 10:52:16.773741 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8845 10:52:16.776983 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 10:52:16.780736 Total UI for P1: 0, mck2ui 16
8847 10:52:16.783861 best dqsien dly found for B0: ( 1, 9, 10)
8848 10:52:16.787189 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8849 10:52:16.790411 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8850 10:52:16.790830
8851 10:52:16.797222 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 10:52:16.800433 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8853 10:52:16.800852 [Gating] SW calibration Done
8854 10:52:16.804083 ==
8855 10:52:16.807241 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 10:52:16.810565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 10:52:16.810987 ==
8858 10:52:16.811318 RX Vref Scan: 0
8859 10:52:16.811677
8860 10:52:16.813578 RX Vref 0 -> 0, step: 1
8861 10:52:16.813996
8862 10:52:16.817275 RX Delay 0 -> 252, step: 8
8863 10:52:16.820408 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8864 10:52:16.823389 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8865 10:52:16.826895 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8866 10:52:16.833489 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8867 10:52:16.836653 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8868 10:52:16.839983 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8869 10:52:16.843356 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8870 10:52:16.847006 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8871 10:52:16.853382 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8872 10:52:16.857006 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8873 10:52:16.859971 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8874 10:52:16.863169 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8875 10:52:16.867059 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8876 10:52:16.873161 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8877 10:52:16.876938 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8878 10:52:16.880400 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8879 10:52:16.880823 ==
8880 10:52:16.883536 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:52:16.886575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:52:16.887062 ==
8883 10:52:16.890497 DQS Delay:
8884 10:52:16.890958 DQS0 = 0, DQS1 = 0
8885 10:52:16.893501 DQM Delay:
8886 10:52:16.893930 DQM0 = 136, DQM1 = 133
8887 10:52:16.894307 DQ Delay:
8888 10:52:16.900139 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8889 10:52:16.904081 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8890 10:52:16.906674 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8891 10:52:16.910485 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8892 10:52:16.910912
8893 10:52:16.911285
8894 10:52:16.911654 ==
8895 10:52:16.913622 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 10:52:16.916682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 10:52:16.917128 ==
8898 10:52:16.917571
8899 10:52:16.917908
8900 10:52:16.920438 TX Vref Scan disable
8901 10:52:16.923644 == TX Byte 0 ==
8902 10:52:16.926681 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8903 10:52:16.930247 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 10:52:16.934088 == TX Byte 1 ==
8905 10:52:16.937147 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8906 10:52:16.940106 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8907 10:52:16.940660 ==
8908 10:52:16.943793 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 10:52:16.946618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 10:52:16.949901 ==
8911 10:52:16.961007
8912 10:52:16.964020 TX Vref early break, caculate TX vref
8913 10:52:16.967508 TX Vref=16, minBit 0, minWin=23, winSum=384
8914 10:52:16.970799 TX Vref=18, minBit 0, minWin=23, winSum=393
8915 10:52:16.974521 TX Vref=20, minBit 0, minWin=24, winSum=406
8916 10:52:16.977549 TX Vref=22, minBit 1, minWin=24, winSum=408
8917 10:52:16.980764 TX Vref=24, minBit 0, minWin=25, winSum=417
8918 10:52:16.987272 TX Vref=26, minBit 0, minWin=25, winSum=428
8919 10:52:16.990909 TX Vref=28, minBit 0, minWin=24, winSum=425
8920 10:52:16.994039 TX Vref=30, minBit 0, minWin=26, winSum=424
8921 10:52:16.997694 TX Vref=32, minBit 0, minWin=24, winSum=410
8922 10:52:17.000833 TX Vref=34, minBit 0, minWin=24, winSum=405
8923 10:52:17.007508 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
8924 10:52:17.008071
8925 10:52:17.010954 Final TX Range 0 Vref 30
8926 10:52:17.011466
8927 10:52:17.011812 ==
8928 10:52:17.014105 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 10:52:17.017846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 10:52:17.018297 ==
8931 10:52:17.018647
8932 10:52:17.019119
8933 10:52:17.021045 TX Vref Scan disable
8934 10:52:17.028050 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8935 10:52:17.028481 == TX Byte 0 ==
8936 10:52:17.030591 u2DelayCellOfst[0]=17 cells (5 PI)
8937 10:52:17.034352 u2DelayCellOfst[1]=13 cells (4 PI)
8938 10:52:17.037278 u2DelayCellOfst[2]=0 cells (0 PI)
8939 10:52:17.040518 u2DelayCellOfst[3]=6 cells (2 PI)
8940 10:52:17.044144 u2DelayCellOfst[4]=6 cells (2 PI)
8941 10:52:17.047744 u2DelayCellOfst[5]=17 cells (5 PI)
8942 10:52:17.048201 u2DelayCellOfst[6]=17 cells (5 PI)
8943 10:52:17.050716 u2DelayCellOfst[7]=6 cells (2 PI)
8944 10:52:17.057493 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8945 10:52:17.060505 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8946 10:52:17.060940 == TX Byte 1 ==
8947 10:52:17.064147 u2DelayCellOfst[8]=0 cells (0 PI)
8948 10:52:17.067121 u2DelayCellOfst[9]=3 cells (1 PI)
8949 10:52:17.070517 u2DelayCellOfst[10]=10 cells (3 PI)
8950 10:52:17.074096 u2DelayCellOfst[11]=3 cells (1 PI)
8951 10:52:17.077209 u2DelayCellOfst[12]=13 cells (4 PI)
8952 10:52:17.081052 u2DelayCellOfst[13]=13 cells (4 PI)
8953 10:52:17.084331 u2DelayCellOfst[14]=13 cells (4 PI)
8954 10:52:17.087272 u2DelayCellOfst[15]=17 cells (5 PI)
8955 10:52:17.090898 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8956 10:52:17.097338 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8957 10:52:17.097757 DramC Write-DBI on
8958 10:52:17.098091 ==
8959 10:52:17.100545 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 10:52:17.104269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 10:52:17.104692 ==
8962 10:52:17.105021
8963 10:52:17.107418
8964 10:52:17.107835 TX Vref Scan disable
8965 10:52:17.110921 == TX Byte 0 ==
8966 10:52:17.114097 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8967 10:52:17.116992 == TX Byte 1 ==
8968 10:52:17.120293 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8969 10:52:17.120767 DramC Write-DBI off
8970 10:52:17.121104
8971 10:52:17.123893 [DATLAT]
8972 10:52:17.124361 Freq=1600, CH1 RK1
8973 10:52:17.124731
8974 10:52:17.127103 DATLAT Default: 0xf
8975 10:52:17.127597 0, 0xFFFF, sum = 0
8976 10:52:17.130820 1, 0xFFFF, sum = 0
8977 10:52:17.131295 2, 0xFFFF, sum = 0
8978 10:52:17.134037 3, 0xFFFF, sum = 0
8979 10:52:17.134517 4, 0xFFFF, sum = 0
8980 10:52:17.137121 5, 0xFFFF, sum = 0
8981 10:52:17.137597 6, 0xFFFF, sum = 0
8982 10:52:17.140726 7, 0xFFFF, sum = 0
8983 10:52:17.141165 8, 0xFFFF, sum = 0
8984 10:52:17.143820 9, 0xFFFF, sum = 0
8985 10:52:17.147097 10, 0xFFFF, sum = 0
8986 10:52:17.147569 11, 0xFFFF, sum = 0
8987 10:52:17.150656 12, 0xFFFF, sum = 0
8988 10:52:17.151102 13, 0xFFFF, sum = 0
8989 10:52:17.154264 14, 0x0, sum = 1
8990 10:52:17.154704 15, 0x0, sum = 2
8991 10:52:17.156895 16, 0x0, sum = 3
8992 10:52:17.157337 17, 0x0, sum = 4
8993 10:52:17.157777 best_step = 15
8994 10:52:17.160498
8995 10:52:17.160934 ==
8996 10:52:17.163914 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 10:52:17.167420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 10:52:17.167858 ==
8999 10:52:17.168290 RX Vref Scan: 0
9000 10:52:17.168695
9001 10:52:17.170321 RX Vref 0 -> 0, step: 1
9002 10:52:17.170755
9003 10:52:17.173917 RX Delay 19 -> 252, step: 4
9004 10:52:17.177164 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9005 10:52:17.180813 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9006 10:52:17.187792 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9007 10:52:17.190787 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9008 10:52:17.194060 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9009 10:52:17.197254 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9010 10:52:17.201015 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9011 10:52:17.204011 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9012 10:52:17.210997 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9013 10:52:17.214057 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9014 10:52:17.217906 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9015 10:52:17.220800 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9016 10:52:17.224538 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9017 10:52:17.230818 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9018 10:52:17.234079 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9019 10:52:17.237353 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9020 10:52:17.237885 ==
9021 10:52:17.240928 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 10:52:17.243919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 10:52:17.244360 ==
9024 10:52:17.247831 DQS Delay:
9025 10:52:17.248266 DQS0 = 0, DQS1 = 0
9026 10:52:17.250876 DQM Delay:
9027 10:52:17.251309 DQM0 = 134, DQM1 = 130
9028 10:52:17.251768 DQ Delay:
9029 10:52:17.257617 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9030 10:52:17.260669 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9031 10:52:17.264167 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9032 10:52:17.267615 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9033 10:52:17.268051
9034 10:52:17.268482
9035 10:52:17.268890
9036 10:52:17.271155 [DramC_TX_OE_Calibration] TA2
9037 10:52:17.274188 Original DQ_B0 (3 6) =30, OEN = 27
9038 10:52:17.277331 Original DQ_B1 (3 6) =30, OEN = 27
9039 10:52:17.277769 24, 0x0, End_B0=24 End_B1=24
9040 10:52:17.280970 25, 0x0, End_B0=25 End_B1=25
9041 10:52:17.283794 26, 0x0, End_B0=26 End_B1=26
9042 10:52:17.287297 27, 0x0, End_B0=27 End_B1=27
9043 10:52:17.290951 28, 0x0, End_B0=28 End_B1=28
9044 10:52:17.291423 29, 0x0, End_B0=29 End_B1=29
9045 10:52:17.293605 30, 0x0, End_B0=30 End_B1=30
9046 10:52:17.297319 31, 0x4141, End_B0=30 End_B1=30
9047 10:52:17.300652 Byte0 end_step=30 best_step=27
9048 10:52:17.303700 Byte1 end_step=30 best_step=27
9049 10:52:17.307257 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 10:52:17.307742 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 10:52:17.308178
9052 10:52:17.308586
9053 10:52:17.316863 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9054 10:52:17.320787 CH1 RK1: MR19=303, MR18=2207
9055 10:52:17.323831 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9056 10:52:17.326936 [RxdqsGatingPostProcess] freq 1600
9057 10:52:17.333506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 10:52:17.337345 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 10:52:17.340543 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 10:52:17.343599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 10:52:17.346758 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 10:52:17.350264 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 10:52:17.353485 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 10:52:17.356641 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 10:52:17.360451 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 10:52:17.360869 Pre-setting of DQS Precalculation
9067 10:52:17.367108 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 10:52:17.373686 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 10:52:17.380160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 10:52:17.380585
9071 10:52:17.380918
9072 10:52:17.383643 [Calibration Summary] 3200 Mbps
9073 10:52:17.386520 CH 0, Rank 0
9074 10:52:17.387068 SW Impedance : PASS
9075 10:52:17.390156 DUTY Scan : NO K
9076 10:52:17.393564 ZQ Calibration : PASS
9077 10:52:17.393995 Jitter Meter : NO K
9078 10:52:17.397186 CBT Training : PASS
9079 10:52:17.397637 Write leveling : PASS
9080 10:52:17.400347 RX DQS gating : PASS
9081 10:52:17.403513 RX DQ/DQS(RDDQC) : PASS
9082 10:52:17.403928 TX DQ/DQS : PASS
9083 10:52:17.406811 RX DATLAT : PASS
9084 10:52:17.410434 RX DQ/DQS(Engine): PASS
9085 10:52:17.410879 TX OE : PASS
9086 10:52:17.413657 All Pass.
9087 10:52:17.414076
9088 10:52:17.414569 CH 0, Rank 1
9089 10:52:17.417104 SW Impedance : PASS
9090 10:52:17.417524 DUTY Scan : NO K
9091 10:52:17.420446 ZQ Calibration : PASS
9092 10:52:17.423389 Jitter Meter : NO K
9093 10:52:17.423808 CBT Training : PASS
9094 10:52:17.427383 Write leveling : PASS
9095 10:52:17.430591 RX DQS gating : PASS
9096 10:52:17.431011 RX DQ/DQS(RDDQC) : PASS
9097 10:52:17.433659 TX DQ/DQS : PASS
9098 10:52:17.434077 RX DATLAT : PASS
9099 10:52:17.436735 RX DQ/DQS(Engine): PASS
9100 10:52:17.440523 TX OE : PASS
9101 10:52:17.440989 All Pass.
9102 10:52:17.441407
9103 10:52:17.441836 CH 1, Rank 0
9104 10:52:17.443671 SW Impedance : PASS
9105 10:52:17.447307 DUTY Scan : NO K
9106 10:52:17.447800 ZQ Calibration : PASS
9107 10:52:17.450493 Jitter Meter : NO K
9108 10:52:17.453552 CBT Training : PASS
9109 10:52:17.453997 Write leveling : PASS
9110 10:52:17.457130 RX DQS gating : PASS
9111 10:52:17.460409 RX DQ/DQS(RDDQC) : PASS
9112 10:52:17.460947 TX DQ/DQS : PASS
9113 10:52:17.463456 RX DATLAT : PASS
9114 10:52:17.466739 RX DQ/DQS(Engine): PASS
9115 10:52:17.467210 TX OE : PASS
9116 10:52:17.467626 All Pass.
9117 10:52:17.470361
9118 10:52:17.470783 CH 1, Rank 1
9119 10:52:17.473605 SW Impedance : PASS
9120 10:52:17.474117 DUTY Scan : NO K
9121 10:52:17.477129 ZQ Calibration : PASS
9122 10:52:17.477618 Jitter Meter : NO K
9123 10:52:17.480303 CBT Training : PASS
9124 10:52:17.483782 Write leveling : PASS
9125 10:52:17.484221 RX DQS gating : PASS
9126 10:52:17.487263 RX DQ/DQS(RDDQC) : PASS
9127 10:52:17.490381 TX DQ/DQS : PASS
9128 10:52:17.490844 RX DATLAT : PASS
9129 10:52:17.493643 RX DQ/DQS(Engine): PASS
9130 10:52:17.497160 TX OE : PASS
9131 10:52:17.497587 All Pass.
9132 10:52:17.497917
9133 10:52:17.498226 DramC Write-DBI on
9134 10:52:17.499841 PER_BANK_REFRESH: Hybrid Mode
9135 10:52:17.503548 TX_TRACKING: ON
9136 10:52:17.510568 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 10:52:17.520066 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 10:52:17.526868 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 10:52:17.530402 [FAST_K] Save calibration result to emmc
9140 10:52:17.533840 sync common calibartion params.
9141 10:52:17.537123 sync cbt_mode0:1, 1:1
9142 10:52:17.537540 dram_init: ddr_geometry: 2
9143 10:52:17.540031 dram_init: ddr_geometry: 2
9144 10:52:17.543627 dram_init: ddr_geometry: 2
9145 10:52:17.544045 0:dram_rank_size:100000000
9146 10:52:17.547127 1:dram_rank_size:100000000
9147 10:52:17.553402 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 10:52:17.553869 DFS_SHUFFLE_HW_MODE: ON
9149 10:52:17.560151 dramc_set_vcore_voltage set vcore to 725000
9150 10:52:17.560572 Read voltage for 1600, 0
9151 10:52:17.563852 Vio18 = 0
9152 10:52:17.564267 Vcore = 725000
9153 10:52:17.564597 Vdram = 0
9154 10:52:17.567130 Vddq = 0
9155 10:52:17.567627 Vmddr = 0
9156 10:52:17.570187 switch to 3200 Mbps bootup
9157 10:52:17.570606 [DramcRunTimeConfig]
9158 10:52:17.570936 PHYPLL
9159 10:52:17.573962 DPM_CONTROL_AFTERK: ON
9160 10:52:17.576922 PER_BANK_REFRESH: ON
9161 10:52:17.577368 REFRESH_OVERHEAD_REDUCTION: ON
9162 10:52:17.580122 CMD_PICG_NEW_MODE: OFF
9163 10:52:17.583773 XRTWTW_NEW_MODE: ON
9164 10:52:17.584189 XRTRTR_NEW_MODE: ON
9165 10:52:17.586878 TX_TRACKING: ON
9166 10:52:17.587475 RDSEL_TRACKING: OFF
9167 10:52:17.589997 DQS Precalculation for DVFS: ON
9168 10:52:17.590418 RX_TRACKING: OFF
9169 10:52:17.593768 HW_GATING DBG: ON
9170 10:52:17.594187 ZQCS_ENABLE_LP4: ON
9171 10:52:17.596640 RX_PICG_NEW_MODE: ON
9172 10:52:17.600284 TX_PICG_NEW_MODE: ON
9173 10:52:17.600703 ENABLE_RX_DCM_DPHY: ON
9174 10:52:17.603661 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 10:52:17.606626 DUMMY_READ_FOR_TRACKING: OFF
9176 10:52:17.610291 !!! SPM_CONTROL_AFTERK: OFF
9177 10:52:17.610745 !!! SPM could not control APHY
9178 10:52:17.613586 IMPEDANCE_TRACKING: ON
9179 10:52:17.617189 TEMP_SENSOR: ON
9180 10:52:17.617609 HW_SAVE_FOR_SR: OFF
9181 10:52:17.620251 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 10:52:17.623389 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 10:52:17.626647 Read ODT Tracking: ON
9184 10:52:17.627064 Refresh Rate DeBounce: ON
9185 10:52:17.630281 DFS_NO_QUEUE_FLUSH: ON
9186 10:52:17.633521 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 10:52:17.636963 ENABLE_DFS_RUNTIME_MRW: OFF
9188 10:52:17.637394 DDR_RESERVE_NEW_MODE: ON
9189 10:52:17.640111 MR_CBT_SWITCH_FREQ: ON
9190 10:52:17.643224 =========================
9191 10:52:17.661560 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 10:52:17.664343 dram_init: ddr_geometry: 2
9193 10:52:17.683239 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 10:52:17.686354 dram_init: dram init end (result: 0)
9195 10:52:17.693061 DRAM-K: Full calibration passed in 24420 msecs
9196 10:52:17.696084 MRC: failed to locate region type 0.
9197 10:52:17.696547 DRAM rank0 size:0x100000000,
9198 10:52:17.699490 DRAM rank1 size=0x100000000
9199 10:52:17.709320 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 10:52:17.716090 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 10:52:17.722946 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 10:52:17.729187 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 10:52:17.732995 DRAM rank0 size:0x100000000,
9204 10:52:17.736021 DRAM rank1 size=0x100000000
9205 10:52:17.736499 CBMEM:
9206 10:52:17.739111 IMD: root @ 0xfffff000 254 entries.
9207 10:52:17.742709 IMD: root @ 0xffffec00 62 entries.
9208 10:52:17.746086 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 10:52:17.749600 WARNING: RO_VPD is uninitialized or empty.
9210 10:52:17.755853 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 10:52:17.762750 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 10:52:17.775531 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9213 10:52:17.787028 BS: romstage times (exec / console): total (unknown) / 23959 ms
9214 10:52:17.787632
9215 10:52:17.788003
9216 10:52:17.797294 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 10:52:17.800291 ARM64: Exception handlers installed.
9218 10:52:17.803724 ARM64: Testing exception
9219 10:52:17.806816 ARM64: Done test exception
9220 10:52:17.807234 Enumerating buses...
9221 10:52:17.810170 Show all devs... Before device enumeration.
9222 10:52:17.813650 Root Device: enabled 1
9223 10:52:17.816995 CPU_CLUSTER: 0: enabled 1
9224 10:52:17.817445 CPU: 00: enabled 1
9225 10:52:17.820552 Compare with tree...
9226 10:52:17.820969 Root Device: enabled 1
9227 10:52:17.823489 CPU_CLUSTER: 0: enabled 1
9228 10:52:17.826760 CPU: 00: enabled 1
9229 10:52:17.827178 Root Device scanning...
9230 10:52:17.830407 scan_static_bus for Root Device
9231 10:52:17.833621 CPU_CLUSTER: 0 enabled
9232 10:52:17.837482 scan_static_bus for Root Device done
9233 10:52:17.840609 scan_bus: bus Root Device finished in 8 msecs
9234 10:52:17.841056 done
9235 10:52:17.847419 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 10:52:17.850349 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 10:52:17.857126 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 10:52:17.860117 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 10:52:17.863411 Allocating resources...
9240 10:52:17.863894 Reading resources...
9241 10:52:17.870064 Root Device read_resources bus 0 link: 0
9242 10:52:17.870625 DRAM rank0 size:0x100000000,
9243 10:52:17.873633 DRAM rank1 size=0x100000000
9244 10:52:17.877017 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 10:52:17.879959 CPU: 00 missing read_resources
9246 10:52:17.883131 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 10:52:17.890147 Root Device read_resources bus 0 link: 0 done
9248 10:52:17.890577 Done reading resources.
9249 10:52:17.896679 Show resources in subtree (Root Device)...After reading.
9250 10:52:17.900171 Root Device child on link 0 CPU_CLUSTER: 0
9251 10:52:17.903502 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 10:52:17.913458 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 10:52:17.914023 CPU: 00
9254 10:52:17.916537 Root Device assign_resources, bus 0 link: 0
9255 10:52:17.919875 CPU_CLUSTER: 0 missing set_resources
9256 10:52:17.926285 Root Device assign_resources, bus 0 link: 0 done
9257 10:52:17.926852 Done setting resources.
9258 10:52:17.933428 Show resources in subtree (Root Device)...After assigning values.
9259 10:52:17.936244 Root Device child on link 0 CPU_CLUSTER: 0
9260 10:52:17.939517 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 10:52:17.949573 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 10:52:17.950076 CPU: 00
9263 10:52:17.952794 Done allocating resources.
9264 10:52:17.956420 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 10:52:17.960053 Enabling resources...
9266 10:52:17.960476 done.
9267 10:52:17.966144 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 10:52:17.966701 Initializing devices...
9269 10:52:17.969590 Root Device init
9270 10:52:17.970059 init hardware done!
9271 10:52:17.973310 0x00000018: ctrlr->caps
9272 10:52:17.976184 52.000 MHz: ctrlr->f_max
9273 10:52:17.976704 0.400 MHz: ctrlr->f_min
9274 10:52:17.979457 0x40ff8080: ctrlr->voltages
9275 10:52:17.980030 sclk: 390625
9276 10:52:17.983056 Bus Width = 1
9277 10:52:17.983516 sclk: 390625
9278 10:52:17.986207 Bus Width = 1
9279 10:52:17.986623 Early init status = 3
9280 10:52:17.992558 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 10:52:17.996321 in-header: 03 fc 00 00 01 00 00 00
9282 10:52:17.996740 in-data: 00
9283 10:52:18.002650 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9284 10:52:18.006364 in-header: 03 fd 00 00 00 00 00 00
9285 10:52:18.009412 in-data:
9286 10:52:18.012481 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9287 10:52:18.016106 in-header: 03 fc 00 00 01 00 00 00
9288 10:52:18.019431 in-data: 00
9289 10:52:18.022635 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9290 10:52:18.027839 in-header: 03 fd 00 00 00 00 00 00
9291 10:52:18.030600 in-data:
9292 10:52:18.034548 [SSUSB] Setting up USB HOST controller...
9293 10:52:18.037481 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9294 10:52:18.040844 [SSUSB] phy power-on done.
9295 10:52:18.044425 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9296 10:52:18.050891 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9297 10:52:18.053905 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9298 10:52:18.060365 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9299 10:52:18.067275 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9300 10:52:18.073816 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9301 10:52:18.080641 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9302 10:52:18.087612 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9303 10:52:18.090463 SPM: binary array size = 0x9dc
9304 10:52:18.093587 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9305 10:52:18.100693 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9306 10:52:18.107175 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9307 10:52:18.114213 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9308 10:52:18.116609 configure_display: Starting display init
9309 10:52:18.150477 anx7625_power_on_init: Init interface.
9310 10:52:18.154161 anx7625_disable_pd_protocol: Disabled PD feature.
9311 10:52:18.157170 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9312 10:52:18.185489 anx7625_start_dp_work: Secure OCM version=00
9313 10:52:18.188452 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9314 10:52:18.203480 sp_tx_get_edid_block: EDID Block = 1
9315 10:52:18.305988 Extracted contents:
9316 10:52:18.309348 header: 00 ff ff ff ff ff ff 00
9317 10:52:18.312398 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9318 10:52:18.315691 version: 01 04
9319 10:52:18.319467 basic params: 95 1f 11 78 0a
9320 10:52:18.322628 chroma info: 76 90 94 55 54 90 27 21 50 54
9321 10:52:18.325900 established: 00 00 00
9322 10:52:18.332592 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9323 10:52:18.335816 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9324 10:52:18.342340 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 10:52:18.349217 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9326 10:52:18.355858 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9327 10:52:18.358722 extensions: 00
9328 10:52:18.359187 checksum: fb
9329 10:52:18.359567
9330 10:52:18.362377 Manufacturer: IVO Model 57d Serial Number 0
9331 10:52:18.365333 Made week 0 of 2020
9332 10:52:18.365777 EDID version: 1.4
9333 10:52:18.368896 Digital display
9334 10:52:18.372595 6 bits per primary color channel
9335 10:52:18.373086 DisplayPort interface
9336 10:52:18.375429 Maximum image size: 31 cm x 17 cm
9337 10:52:18.378798 Gamma: 220%
9338 10:52:18.379286 Check DPMS levels
9339 10:52:18.382083 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9340 10:52:18.385896 First detailed timing is preferred timing
9341 10:52:18.389010 Established timings supported:
9342 10:52:18.392115 Standard timings supported:
9343 10:52:18.392544 Detailed timings
9344 10:52:18.398837 Hex of detail: 383680a07038204018303c0035ae10000019
9345 10:52:18.402066 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9346 10:52:18.408892 0780 0798 07c8 0820 hborder 0
9347 10:52:18.412309 0438 043b 0447 0458 vborder 0
9348 10:52:18.415276 -hsync -vsync
9349 10:52:18.415764 Did detailed timing
9350 10:52:18.422451 Hex of detail: 000000000000000000000000000000000000
9351 10:52:18.422979 Manufacturer-specified data, tag 0
9352 10:52:18.428610 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9353 10:52:18.431870 ASCII string: InfoVision
9354 10:52:18.435596 Hex of detail: 000000fe00523134304e574635205248200a
9355 10:52:18.438975 ASCII string: R140NWF5 RH
9356 10:52:18.439661 Checksum
9357 10:52:18.441872 Checksum: 0xfb (valid)
9358 10:52:18.445089 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9359 10:52:18.448238 DSI data_rate: 832800000 bps
9360 10:52:18.452035 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9361 10:52:18.458319 anx7625_parse_edid: pixelclock(138800).
9362 10:52:18.462128 hactive(1920), hsync(48), hfp(24), hbp(88)
9363 10:52:18.465080 vactive(1080), vsync(12), vfp(3), vbp(17)
9364 10:52:18.468457 anx7625_dsi_config: config dsi.
9365 10:52:18.475007 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9366 10:52:18.487894 anx7625_dsi_config: success to config DSI
9367 10:52:18.491105 anx7625_dp_start: MIPI phy setup OK.
9368 10:52:18.494734 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9369 10:52:18.497829 mtk_ddp_mode_set invalid vrefresh 60
9370 10:52:18.501289 main_disp_path_setup
9371 10:52:18.501703 ovl_layer_smi_id_en
9372 10:52:18.504411 ovl_layer_smi_id_en
9373 10:52:18.504822 ccorr_config
9374 10:52:18.505144 aal_config
9375 10:52:18.507985 gamma_config
9376 10:52:18.508394 postmask_config
9377 10:52:18.511531 dither_config
9378 10:52:18.514590 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9379 10:52:18.521735 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9380 10:52:18.524759 Root Device init finished in 552 msecs
9381 10:52:18.525192 CPU_CLUSTER: 0 init
9382 10:52:18.534757 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9383 10:52:18.537856 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9384 10:52:18.541502 APU_MBOX 0x190000b0 = 0x10001
9385 10:52:18.544767 APU_MBOX 0x190001b0 = 0x10001
9386 10:52:18.547851 APU_MBOX 0x190005b0 = 0x10001
9387 10:52:18.551473 APU_MBOX 0x190006b0 = 0x10001
9388 10:52:18.554590 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9389 10:52:18.567223 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9390 10:52:18.579177 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9391 10:52:18.585897 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9392 10:52:18.597246 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9393 10:52:18.606936 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9394 10:52:18.610226 CPU_CLUSTER: 0 init finished in 81 msecs
9395 10:52:18.613361 Devices initialized
9396 10:52:18.616864 Show all devs... After init.
9397 10:52:18.617335 Root Device: enabled 1
9398 10:52:18.620048 CPU_CLUSTER: 0: enabled 1
9399 10:52:18.623713 CPU: 00: enabled 1
9400 10:52:18.626556 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9401 10:52:18.630179 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9402 10:52:18.633302 ELOG: NV offset 0x57f000 size 0x1000
9403 10:52:18.640075 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9404 10:52:18.647123 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9405 10:52:18.650212 ELOG: Event(17) added with size 13 at 2023-06-05 10:52:06 UTC
9406 10:52:18.653256 out: cmd=0x121: 03 db 21 01 00 00 00 00
9407 10:52:18.657187 in-header: 03 01 00 00 2c 00 00 00
9408 10:52:18.670388 in-data: 5e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9409 10:52:18.676670 ELOG: Event(A1) added with size 10 at 2023-06-05 10:52:07 UTC
9410 10:52:18.683570 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9411 10:52:18.690135 ELOG: Event(A0) added with size 9 at 2023-06-05 10:52:07 UTC
9412 10:52:18.693618 elog_add_boot_reason: Logged dev mode boot
9413 10:52:18.696982 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9414 10:52:18.699799 Finalize devices...
9415 10:52:18.700220 Devices finalized
9416 10:52:18.706858 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9417 10:52:18.710342 Writing coreboot table at 0xffe64000
9418 10:52:18.713552 0. 000000000010a000-0000000000113fff: RAMSTAGE
9419 10:52:18.716226 1. 0000000040000000-00000000400fffff: RAM
9420 10:52:18.719397 2. 0000000040100000-000000004032afff: RAMSTAGE
9421 10:52:18.726589 3. 000000004032b000-00000000545fffff: RAM
9422 10:52:18.729699 4. 0000000054600000-000000005465ffff: BL31
9423 10:52:18.732937 5. 0000000054660000-00000000ffe63fff: RAM
9424 10:52:18.739654 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9425 10:52:18.742835 7. 0000000100000000-000000023fffffff: RAM
9426 10:52:18.742917 Passing 5 GPIOs to payload:
9427 10:52:18.749349 NAME | PORT | POLARITY | VALUE
9428 10:52:18.753011 EC in RW | 0x000000aa | low | undefined
9429 10:52:18.759372 EC interrupt | 0x00000005 | low | undefined
9430 10:52:18.763206 TPM interrupt | 0x000000ab | high | undefined
9431 10:52:18.766351 SD card detect | 0x00000011 | high | undefined
9432 10:52:18.773298 speaker enable | 0x00000093 | high | undefined
9433 10:52:18.776383 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9434 10:52:18.779345 in-header: 03 f9 00 00 02 00 00 00
9435 10:52:18.779441 in-data: 02 00
9436 10:52:18.782607 ADC[4]: Raw value=904726 ID=7
9437 10:52:18.786456 ADC[3]: Raw value=213441 ID=1
9438 10:52:18.786538 RAM Code: 0x71
9439 10:52:18.789430 ADC[6]: Raw value=75701 ID=0
9440 10:52:18.793153 ADC[5]: Raw value=213072 ID=1
9441 10:52:18.793235 SKU Code: 0x1
9442 10:52:18.799533 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9443 10:52:18.802927 coreboot table: 964 bytes.
9444 10:52:18.806035 IMD ROOT 0. 0xfffff000 0x00001000
9445 10:52:18.809324 IMD SMALL 1. 0xffffe000 0x00001000
9446 10:52:18.812997 RO MCACHE 2. 0xffffc000 0x00001104
9447 10:52:18.816353 CONSOLE 3. 0xfff7c000 0x00080000
9448 10:52:18.819664 FMAP 4. 0xfff7b000 0x00000452
9449 10:52:18.822637 TIME STAMP 5. 0xfff7a000 0x00000910
9450 10:52:18.826245 VBOOT WORK 6. 0xfff66000 0x00014000
9451 10:52:18.829794 RAMOOPS 7. 0xffe66000 0x00100000
9452 10:52:18.832791 COREBOOT 8. 0xffe64000 0x00002000
9453 10:52:18.832885 IMD small region:
9454 10:52:18.836573 IMD ROOT 0. 0xffffec00 0x00000400
9455 10:52:18.839528 VPD 1. 0xffffeba0 0x0000004c
9456 10:52:18.842650 MMC STATUS 2. 0xffffeb80 0x00000004
9457 10:52:18.849900 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9458 10:52:18.850023 Probing TPM: done!
9459 10:52:18.856746 Connected to device vid:did:rid of 1ae0:0028:00
9460 10:52:18.863044 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9461 10:52:18.870097 Initialized TPM device CR50 revision 0
9462 10:52:18.870298 Checking cr50 for pending updates
9463 10:52:18.876572 Reading cr50 TPM mode
9464 10:52:18.885566 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9465 10:52:18.891822 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9466 10:52:18.932299 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9467 10:52:18.935280 Checking segment from ROM address 0x40100000
9468 10:52:18.938645 Checking segment from ROM address 0x4010001c
9469 10:52:18.945009 Loading segment from ROM address 0x40100000
9470 10:52:18.945432 code (compression=0)
9471 10:52:18.951953 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9472 10:52:18.961700 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9473 10:52:18.962125 it's not compressed!
9474 10:52:18.968605 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9475 10:52:18.971803 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9476 10:52:18.992065 Loading segment from ROM address 0x4010001c
9477 10:52:18.992493 Entry Point 0x80000000
9478 10:52:18.995732 Loaded segments
9479 10:52:18.998874 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9480 10:52:19.005308 Jumping to boot code at 0x80000000(0xffe64000)
9481 10:52:19.012573 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9482 10:52:19.018964 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9483 10:52:19.026869 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9484 10:52:19.030011 Checking segment from ROM address 0x40100000
9485 10:52:19.033423 Checking segment from ROM address 0x4010001c
9486 10:52:19.040159 Loading segment from ROM address 0x40100000
9487 10:52:19.040585 code (compression=1)
9488 10:52:19.047012 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9489 10:52:19.056734 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9490 10:52:19.057162 using LZMA
9491 10:52:19.065000 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9492 10:52:19.071867 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9493 10:52:19.074953 Loading segment from ROM address 0x4010001c
9494 10:52:19.075408 Entry Point 0x54601000
9495 10:52:19.078126 Loaded segments
9496 10:52:19.082079 NOTICE: MT8192 bl31_setup
9497 10:52:19.088898 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9498 10:52:19.092126 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9499 10:52:19.095582 WARNING: region 0:
9500 10:52:19.098582 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 10:52:19.099009 WARNING: region 1:
9502 10:52:19.105360 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9503 10:52:19.108692 WARNING: region 2:
9504 10:52:19.111851 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9505 10:52:19.115621 WARNING: region 3:
9506 10:52:19.118611 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 10:52:19.121941 WARNING: region 4:
9508 10:52:19.125540 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 10:52:19.128574 WARNING: region 5:
9510 10:52:19.131729 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 10:52:19.135220 WARNING: region 6:
9512 10:52:19.138658 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 10:52:19.139055 WARNING: region 7:
9514 10:52:19.145409 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 10:52:19.152053 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9516 10:52:19.155411 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9517 10:52:19.158972 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9518 10:52:19.165515 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9519 10:52:19.168938 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9520 10:52:19.171868 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9521 10:52:19.178750 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9522 10:52:19.181846 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9523 10:52:19.185742 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9524 10:52:19.191967 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9525 10:52:19.195187 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9526 10:52:19.202147 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9527 10:52:19.205443 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9528 10:52:19.208619 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9529 10:52:19.215430 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9530 10:52:19.219095 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9531 10:52:19.222211 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9532 10:52:19.228814 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9533 10:52:19.232258 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9534 10:52:19.235894 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9535 10:52:19.242356 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9536 10:52:19.245835 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9537 10:52:19.252356 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9538 10:52:19.255481 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9539 10:52:19.259179 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9540 10:52:19.265439 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9541 10:52:19.268982 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9542 10:52:19.275610 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9543 10:52:19.278875 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9544 10:52:19.282541 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9545 10:52:19.288996 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9546 10:52:19.292740 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9547 10:52:19.295879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9548 10:52:19.302295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9549 10:52:19.306133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9550 10:52:19.309375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9551 10:52:19.312350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9552 10:52:19.319321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9553 10:52:19.322478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9554 10:52:19.326179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9555 10:52:19.329232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9556 10:52:19.335990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9557 10:52:19.339583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9558 10:52:19.342427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9559 10:52:19.346112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9560 10:52:19.352497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9561 10:52:19.355884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9562 10:52:19.359281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9563 10:52:19.366150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9564 10:52:19.369209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9565 10:52:19.372943 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9566 10:52:19.379587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9567 10:52:19.382572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9568 10:52:19.389623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9569 10:52:19.392624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9570 10:52:19.396312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9571 10:52:19.402740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9572 10:52:19.405788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9573 10:52:19.412686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9574 10:52:19.415922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9575 10:52:19.422759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9576 10:52:19.425931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9577 10:52:19.432906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9578 10:52:19.436054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9579 10:52:19.439657 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9580 10:52:19.446075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9581 10:52:19.449740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9582 10:52:19.455779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9583 10:52:19.459222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9584 10:52:19.466508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9585 10:52:19.469660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9586 10:52:19.472617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9587 10:52:19.479292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9588 10:52:19.482916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9589 10:52:19.489100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9590 10:52:19.492533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9591 10:52:19.499550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9592 10:52:19.502618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9593 10:52:19.505788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9594 10:52:19.512765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9595 10:52:19.515894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9596 10:52:19.522667 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9597 10:52:19.525869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9598 10:52:19.532921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9599 10:52:19.535868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9600 10:52:19.539372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9601 10:52:19.546151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9602 10:52:19.549203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9603 10:52:19.556065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9604 10:52:19.559420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9605 10:52:19.565740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9606 10:52:19.569123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9607 10:52:19.572690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9608 10:52:19.579550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9609 10:52:19.582440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9610 10:52:19.589542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9611 10:52:19.592632 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9612 10:52:19.596149 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9613 10:52:19.599320 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9614 10:52:19.606293 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9615 10:52:19.609201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9616 10:52:19.613048 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9617 10:52:19.619364 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9618 10:52:19.623057 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9619 10:52:19.629472 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9620 10:52:19.632997 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9621 10:52:19.636000 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9622 10:52:19.643200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9623 10:52:19.646300 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9624 10:52:19.653110 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9625 10:52:19.656416 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9626 10:52:19.659891 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9627 10:52:19.666085 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9628 10:52:19.669506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9629 10:52:19.676076 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9630 10:52:19.679596 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9631 10:52:19.683034 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9632 10:52:19.686385 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9633 10:52:19.692914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9634 10:52:19.696629 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9635 10:52:19.699669 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9636 10:52:19.702639 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9637 10:52:19.709619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9638 10:52:19.713097 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9639 10:52:19.716478 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9640 10:52:19.723193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9641 10:52:19.726370 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9642 10:52:19.732955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9643 10:52:19.736521 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9644 10:52:19.739712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9645 10:52:19.746876 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9646 10:52:19.749894 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9647 10:52:19.753023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9648 10:52:19.759772 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9649 10:52:19.763283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9650 10:52:19.769771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9651 10:52:19.773303 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9652 10:52:19.776217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9653 10:52:19.782968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9654 10:52:19.786455 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9655 10:52:19.793077 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9656 10:52:19.796583 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9657 10:52:19.799624 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9658 10:52:19.806539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9659 10:52:19.809554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9660 10:52:19.813331 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9661 10:52:19.819705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9662 10:52:19.823106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9663 10:52:19.829471 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9664 10:52:19.833295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9665 10:52:19.836345 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9666 10:52:19.843097 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9667 10:52:19.846336 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9668 10:52:19.849669 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9669 10:52:19.856647 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9670 10:52:19.859898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9671 10:52:19.866876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9672 10:52:19.869925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9673 10:52:19.873564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9674 10:52:19.880369 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9675 10:52:19.883116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9676 10:52:19.890080 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9677 10:52:19.893245 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9678 10:52:19.896818 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9679 10:52:19.903100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9680 10:52:19.906499 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9681 10:52:19.910089 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9682 10:52:19.916108 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9683 10:52:19.919725 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9684 10:52:19.926438 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9685 10:52:19.929413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9686 10:52:19.936111 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9687 10:52:19.939595 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9688 10:52:19.942816 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9689 10:52:19.949638 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9690 10:52:19.952901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9691 10:52:19.956045 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9692 10:52:19.962536 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9693 10:52:19.966280 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9694 10:52:19.972626 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9695 10:52:19.975730 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9696 10:52:19.979048 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9697 10:52:19.985844 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9698 10:52:19.989212 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9699 10:52:19.995845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9700 10:52:19.999166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9701 10:52:20.002710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9702 10:52:20.008886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9703 10:52:20.012435 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9704 10:52:20.018868 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9705 10:52:20.022280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9706 10:52:20.026025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9707 10:52:20.032368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9708 10:52:20.035786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9709 10:52:20.042438 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9710 10:52:20.045933 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9711 10:52:20.052670 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9712 10:52:20.055924 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9713 10:52:20.059149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9714 10:52:20.065786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9715 10:52:20.068829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9716 10:52:20.075928 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9717 10:52:20.079100 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9718 10:52:20.082248 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9719 10:52:20.088556 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9720 10:52:20.092268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9721 10:52:20.098870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9722 10:52:20.102441 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9723 10:52:20.105355 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9724 10:52:20.112408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9725 10:52:20.115479 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9726 10:52:20.122152 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9727 10:52:20.125870 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9728 10:52:20.132267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9729 10:52:20.135305 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9730 10:52:20.138686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9731 10:52:20.145622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9732 10:52:20.149201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9733 10:52:20.155608 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9734 10:52:20.158558 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9735 10:52:20.162331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9736 10:52:20.168694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9737 10:52:20.171916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9738 10:52:20.178877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9739 10:52:20.181922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9740 10:52:20.188465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9741 10:52:20.192125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9742 10:52:20.195174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9743 10:52:20.201932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9744 10:52:20.205239 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9745 10:52:20.208807 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9746 10:52:20.212382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9747 10:52:20.218412 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9748 10:52:20.221868 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9749 10:52:20.225118 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9750 10:52:20.231946 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9751 10:52:20.234919 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9752 10:52:20.238584 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9753 10:52:20.245543 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9754 10:52:20.248470 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9755 10:52:20.251986 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9756 10:52:20.258624 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9757 10:52:20.261613 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9758 10:52:20.265101 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9759 10:52:20.272232 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9760 10:52:20.275382 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9761 10:52:20.281694 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9762 10:52:20.285327 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9763 10:52:20.288680 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9764 10:52:20.295090 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9765 10:52:20.298726 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9766 10:52:20.301899 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9767 10:52:20.308157 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9768 10:52:20.311781 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9769 10:52:20.315577 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9770 10:52:20.321731 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9771 10:52:20.325537 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9772 10:52:20.331886 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9773 10:52:20.334944 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9774 10:52:20.338647 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9775 10:52:20.344891 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9776 10:52:20.348713 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9777 10:52:20.351850 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9778 10:52:20.358263 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9779 10:52:20.361866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9780 10:52:20.364537 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9781 10:52:20.371653 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9782 10:52:20.375212 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9783 10:52:20.378330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9784 10:52:20.384812 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9785 10:52:20.388041 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9786 10:52:20.391820 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9787 10:52:20.394919 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9788 10:52:20.398043 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9789 10:52:20.405129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9790 10:52:20.407993 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9791 10:52:20.411808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9792 10:52:20.418108 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9793 10:52:20.421586 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9794 10:52:20.425030 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9795 10:52:20.428087 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9796 10:52:20.435127 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9797 10:52:20.437879 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9798 10:52:20.444503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9799 10:52:20.448170 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9800 10:52:20.451698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9801 10:52:20.458019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9802 10:52:20.461803 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9803 10:52:20.468406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9804 10:52:20.471424 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9805 10:52:20.474371 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9806 10:52:20.481663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9807 10:52:20.484379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9808 10:52:20.491193 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9809 10:52:20.494425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9810 10:52:20.501441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9811 10:52:20.504741 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9812 10:52:20.507795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9813 10:52:20.514020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9814 10:52:20.517744 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9815 10:52:20.524078 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9816 10:52:20.527629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9817 10:52:20.531399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9818 10:52:20.537653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9819 10:52:20.541153 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9820 10:52:20.547534 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9821 10:52:20.550962 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9822 10:52:20.554215 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9823 10:52:20.560646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9824 10:52:20.564366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9825 10:52:20.571235 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9826 10:52:20.574724 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9827 10:52:20.577819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9828 10:52:20.584488 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9829 10:52:20.587453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9830 10:52:20.594081 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9831 10:52:20.597492 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9832 10:52:20.600501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9833 10:52:20.607480 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9834 10:52:20.610795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9835 10:52:20.617540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9836 10:52:20.620751 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9837 10:52:20.623978 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9838 10:52:20.630348 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9839 10:52:20.634230 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9840 10:52:20.640802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9841 10:52:20.644313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9842 10:52:20.650706 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9843 10:52:20.654322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9844 10:52:20.657196 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9845 10:52:20.664341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9846 10:52:20.667121 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9847 10:52:20.674144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9848 10:52:20.677227 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9849 10:52:20.680284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9850 10:52:20.687262 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9851 10:52:20.690267 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9852 10:52:20.697104 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9853 10:52:20.700658 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9854 10:52:20.703693 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9855 10:52:20.710625 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9856 10:52:20.713781 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9857 10:52:20.720704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9858 10:52:20.723763 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9859 10:52:20.726952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9860 10:52:20.733838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9861 10:52:20.736905 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9862 10:52:20.743770 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9863 10:52:20.747204 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9864 10:52:20.750183 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9865 10:52:20.757306 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9866 10:52:20.760160 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9867 10:52:20.767277 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9868 10:52:20.770038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9869 10:52:20.774022 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9870 10:52:20.780381 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9871 10:52:20.783678 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9872 10:52:20.790449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9873 10:52:20.793554 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9874 10:52:20.800208 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9875 10:52:20.803229 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9876 10:52:20.806767 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9877 10:52:20.813659 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9878 10:52:20.816919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9879 10:52:20.823214 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9880 10:52:20.826777 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9881 10:52:20.833545 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9882 10:52:20.836732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9883 10:52:20.843175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9884 10:52:20.846381 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9885 10:52:20.850072 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9886 10:52:20.856763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9887 10:52:20.859579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9888 10:52:20.866441 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9889 10:52:20.869782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9890 10:52:20.876768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9891 10:52:20.879617 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9892 10:52:20.883042 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9893 10:52:20.890014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9894 10:52:20.892929 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9895 10:52:20.900072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9896 10:52:20.903081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9897 10:52:20.909717 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9898 10:52:20.913143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9899 10:52:20.919620 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9900 10:52:20.923185 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9901 10:52:20.926349 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9902 10:52:20.933008 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9903 10:52:20.936076 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9904 10:52:20.942971 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9905 10:52:20.946438 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9906 10:52:20.952677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9907 10:52:20.956377 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9908 10:52:20.959424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9909 10:52:20.965943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9910 10:52:20.969271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9911 10:52:20.976307 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9912 10:52:20.979223 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9913 10:52:20.985806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9914 10:52:20.989125 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9915 10:52:20.996010 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9916 10:52:20.999221 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9917 10:52:21.002335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9918 10:52:21.009098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9919 10:52:21.012804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9920 10:52:21.019421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9921 10:52:21.022947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9922 10:52:21.026157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9923 10:52:21.032139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9924 10:52:21.035803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9925 10:52:21.042713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9926 10:52:21.045803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9927 10:52:21.051937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9928 10:52:21.055822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9929 10:52:21.062206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9930 10:52:21.065172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9931 10:52:21.072384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9932 10:52:21.075880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9933 10:52:21.082388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9934 10:52:21.085470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9935 10:52:21.092451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9936 10:52:21.095526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9937 10:52:21.102016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9938 10:52:21.105150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9939 10:52:21.112159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9940 10:52:21.115232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9941 10:52:21.121828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9942 10:52:21.125467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9943 10:52:21.132277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9944 10:52:21.135532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9945 10:52:21.142115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9946 10:52:21.145454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9947 10:52:21.152219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9948 10:52:21.155462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9949 10:52:21.158806 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9950 10:52:21.161934 INFO: [APUAPC] vio 0
9951 10:52:21.168718 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9952 10:52:21.171691 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9953 10:52:21.175283 INFO: [APUAPC] D0_APC_0: 0x400510
9954 10:52:21.178317 INFO: [APUAPC] D0_APC_1: 0x0
9955 10:52:21.181511 INFO: [APUAPC] D0_APC_2: 0x1540
9956 10:52:21.184994 INFO: [APUAPC] D0_APC_3: 0x0
9957 10:52:21.188413 INFO: [APUAPC] D1_APC_0: 0xffffffff
9958 10:52:21.191829 INFO: [APUAPC] D1_APC_1: 0xffffffff
9959 10:52:21.195316 INFO: [APUAPC] D1_APC_2: 0x3fffff
9960 10:52:21.198198 INFO: [APUAPC] D1_APC_3: 0x0
9961 10:52:21.201727 INFO: [APUAPC] D2_APC_0: 0xffffffff
9962 10:52:21.205279 INFO: [APUAPC] D2_APC_1: 0xffffffff
9963 10:52:21.208457 INFO: [APUAPC] D2_APC_2: 0x3fffff
9964 10:52:21.208597 INFO: [APUAPC] D2_APC_3: 0x0
9965 10:52:21.211566 INFO: [APUAPC] D3_APC_0: 0xffffffff
9966 10:52:21.218450 INFO: [APUAPC] D3_APC_1: 0xffffffff
9967 10:52:21.221652 INFO: [APUAPC] D3_APC_2: 0x3fffff
9968 10:52:21.221758 INFO: [APUAPC] D3_APC_3: 0x0
9969 10:52:21.224755 INFO: [APUAPC] D4_APC_0: 0xffffffff
9970 10:52:21.228167 INFO: [APUAPC] D4_APC_1: 0xffffffff
9971 10:52:21.231443 INFO: [APUAPC] D4_APC_2: 0x3fffff
9972 10:52:21.235032 INFO: [APUAPC] D4_APC_3: 0x0
9973 10:52:21.238247 INFO: [APUAPC] D5_APC_0: 0xffffffff
9974 10:52:21.241395 INFO: [APUAPC] D5_APC_1: 0xffffffff
9975 10:52:21.245143 INFO: [APUAPC] D5_APC_2: 0x3fffff
9976 10:52:21.248644 INFO: [APUAPC] D5_APC_3: 0x0
9977 10:52:21.251826 INFO: [APUAPC] D6_APC_0: 0xffffffff
9978 10:52:21.254951 INFO: [APUAPC] D6_APC_1: 0xffffffff
9979 10:52:21.258084 INFO: [APUAPC] D6_APC_2: 0x3fffff
9980 10:52:21.261322 INFO: [APUAPC] D6_APC_3: 0x0
9981 10:52:21.264655 INFO: [APUAPC] D7_APC_0: 0xffffffff
9982 10:52:21.268472 INFO: [APUAPC] D7_APC_1: 0xffffffff
9983 10:52:21.271706 INFO: [APUAPC] D7_APC_2: 0x3fffff
9984 10:52:21.274770 INFO: [APUAPC] D7_APC_3: 0x0
9985 10:52:21.277992 INFO: [APUAPC] D8_APC_0: 0xffffffff
9986 10:52:21.281727 INFO: [APUAPC] D8_APC_1: 0xffffffff
9987 10:52:21.284382 INFO: [APUAPC] D8_APC_2: 0x3fffff
9988 10:52:21.287796 INFO: [APUAPC] D8_APC_3: 0x0
9989 10:52:21.291133 INFO: [APUAPC] D9_APC_0: 0xffffffff
9990 10:52:21.294484 INFO: [APUAPC] D9_APC_1: 0xffffffff
9991 10:52:21.298025 INFO: [APUAPC] D9_APC_2: 0x3fffff
9992 10:52:21.301380 INFO: [APUAPC] D9_APC_3: 0x0
9993 10:52:21.304858 INFO: [APUAPC] D10_APC_0: 0xffffffff
9994 10:52:21.307884 INFO: [APUAPC] D10_APC_1: 0xffffffff
9995 10:52:21.311207 INFO: [APUAPC] D10_APC_2: 0x3fffff
9996 10:52:21.314905 INFO: [APUAPC] D10_APC_3: 0x0
9997 10:52:21.317932 INFO: [APUAPC] D11_APC_0: 0xffffffff
9998 10:52:21.321119 INFO: [APUAPC] D11_APC_1: 0xffffffff
9999 10:52:21.324419 INFO: [APUAPC] D11_APC_2: 0x3fffff
10000 10:52:21.327991 INFO: [APUAPC] D11_APC_3: 0x0
10001 10:52:21.331133 INFO: [APUAPC] D12_APC_0: 0xffffffff
10002 10:52:21.334506 INFO: [APUAPC] D12_APC_1: 0xffffffff
10003 10:52:21.337671 INFO: [APUAPC] D12_APC_2: 0x3fffff
10004 10:52:21.341368 INFO: [APUAPC] D12_APC_3: 0x0
10005 10:52:21.344477 INFO: [APUAPC] D13_APC_0: 0xffffffff
10006 10:52:21.348236 INFO: [APUAPC] D13_APC_1: 0xffffffff
10007 10:52:21.351185 INFO: [APUAPC] D13_APC_2: 0x3fffff
10008 10:52:21.354261 INFO: [APUAPC] D13_APC_3: 0x0
10009 10:52:21.358227 INFO: [APUAPC] D14_APC_0: 0xffffffff
10010 10:52:21.361347 INFO: [APUAPC] D14_APC_1: 0xffffffff
10011 10:52:21.364616 INFO: [APUAPC] D14_APC_2: 0x3fffff
10012 10:52:21.367705 INFO: [APUAPC] D14_APC_3: 0x0
10013 10:52:21.370932 INFO: [APUAPC] D15_APC_0: 0xffffffff
10014 10:52:21.374775 INFO: [APUAPC] D15_APC_1: 0xffffffff
10015 10:52:21.377872 INFO: [APUAPC] D15_APC_2: 0x3fffff
10016 10:52:21.380955 INFO: [APUAPC] D15_APC_3: 0x0
10017 10:52:21.384725 INFO: [APUAPC] APC_CON: 0x4
10018 10:52:21.387888 INFO: [NOCDAPC] D0_APC_0: 0x0
10019 10:52:21.391060 INFO: [NOCDAPC] D0_APC_1: 0x0
10020 10:52:21.394607 INFO: [NOCDAPC] D1_APC_0: 0x0
10021 10:52:21.394850 INFO: [NOCDAPC] D1_APC_1: 0xfff
10022 10:52:21.398065 INFO: [NOCDAPC] D2_APC_0: 0x0
10023 10:52:21.401201 INFO: [NOCDAPC] D2_APC_1: 0xfff
10024 10:52:21.404656 INFO: [NOCDAPC] D3_APC_0: 0x0
10025 10:52:21.408115 INFO: [NOCDAPC] D3_APC_1: 0xfff
10026 10:52:21.411213 INFO: [NOCDAPC] D4_APC_0: 0x0
10027 10:52:21.414521 INFO: [NOCDAPC] D4_APC_1: 0xfff
10028 10:52:21.418199 INFO: [NOCDAPC] D5_APC_0: 0x0
10029 10:52:21.421598 INFO: [NOCDAPC] D5_APC_1: 0xfff
10030 10:52:21.425017 INFO: [NOCDAPC] D6_APC_0: 0x0
10031 10:52:21.425450 INFO: [NOCDAPC] D6_APC_1: 0xfff
10032 10:52:21.428165 INFO: [NOCDAPC] D7_APC_0: 0x0
10033 10:52:21.431370 INFO: [NOCDAPC] D7_APC_1: 0xfff
10034 10:52:21.435021 INFO: [NOCDAPC] D8_APC_0: 0x0
10035 10:52:21.438067 INFO: [NOCDAPC] D8_APC_1: 0xfff
10036 10:52:21.441150 INFO: [NOCDAPC] D9_APC_0: 0x0
10037 10:52:21.444670 INFO: [NOCDAPC] D9_APC_1: 0xfff
10038 10:52:21.448488 INFO: [NOCDAPC] D10_APC_0: 0x0
10039 10:52:21.451429 INFO: [NOCDAPC] D10_APC_1: 0xfff
10040 10:52:21.455121 INFO: [NOCDAPC] D11_APC_0: 0x0
10041 10:52:21.457992 INFO: [NOCDAPC] D11_APC_1: 0xfff
10042 10:52:21.461218 INFO: [NOCDAPC] D12_APC_0: 0x0
10043 10:52:21.461684 INFO: [NOCDAPC] D12_APC_1: 0xfff
10044 10:52:21.465137 INFO: [NOCDAPC] D13_APC_0: 0x0
10045 10:52:21.468285 INFO: [NOCDAPC] D13_APC_1: 0xfff
10046 10:52:21.471429 INFO: [NOCDAPC] D14_APC_0: 0x0
10047 10:52:21.474761 INFO: [NOCDAPC] D14_APC_1: 0xfff
10048 10:52:21.477946 INFO: [NOCDAPC] D15_APC_0: 0x0
10049 10:52:21.481719 INFO: [NOCDAPC] D15_APC_1: 0xfff
10050 10:52:21.484831 INFO: [NOCDAPC] APC_CON: 0x4
10051 10:52:21.487896 INFO: [APUAPC] set_apusys_apc done
10052 10:52:21.491639 INFO: [DEVAPC] devapc_init done
10053 10:52:21.494737 INFO: GICv3 without legacy support detected.
10054 10:52:21.497998 INFO: ARM GICv3 driver initialized in EL3
10055 10:52:21.500961 INFO: Maximum SPI INTID supported: 639
10056 10:52:21.508115 INFO: BL31: Initializing runtime services
10057 10:52:21.510878 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10058 10:52:21.514590 INFO: SPM: enable CPC mode
10059 10:52:21.521023 INFO: mcdi ready for mcusys-off-idle and system suspend
10060 10:52:21.524656 INFO: BL31: Preparing for EL3 exit to normal world
10061 10:52:21.527773 INFO: Entry point address = 0x80000000
10062 10:52:21.531385 INFO: SPSR = 0x8
10063 10:52:21.536445
10064 10:52:21.536969
10065 10:52:21.537382
10066 10:52:21.539556 Starting depthcharge on Spherion...
10067 10:52:21.540070
10068 10:52:21.540601 Wipe memory regions:
10069 10:52:21.540949
10070 10:52:21.543520 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10071 10:52:21.544147 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10072 10:52:21.544686 Setting prompt string to ['asurada:']
10073 10:52:21.545170 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10074 10:52:21.545906 [0x00000040000000, 0x00000054600000)
10075 10:52:21.665736
10076 10:52:21.666252 [0x00000054660000, 0x00000080000000)
10077 10:52:21.925704
10078 10:52:21.926253 [0x000000821a7280, 0x000000ffe64000)
10079 10:52:22.670513
10080 10:52:22.670695 [0x00000100000000, 0x00000240000000)
10081 10:52:24.560995
10082 10:52:24.564031 Initializing XHCI USB controller at 0x11200000.
10083 10:52:25.602770
10084 10:52:25.605709 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10085 10:52:25.605838
10086 10:52:25.605937
10087 10:52:25.606030
10088 10:52:25.606363 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 10:52:25.706774 asurada: tftpboot 192.168.201.1 10590982/tftp-deploy-jn_vmrpw/kernel/image.itb 10590982/tftp-deploy-jn_vmrpw/kernel/cmdline
10091 10:52:25.706975 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 10:52:25.707128 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10093 10:52:25.711219 tftpboot 192.168.201.1 10590982/tftp-deploy-jn_vmrpw/kernel/image.ittp-deploy-jn_vmrpw/kernel/cmdline
10094 10:52:25.711362
10095 10:52:25.711461 Waiting for link
10096 10:52:25.871712
10097 10:52:25.871889 R8152: Initializing
10098 10:52:25.872032
10099 10:52:25.875424 Version 9 (ocp_data = 6010)
10100 10:52:25.875534
10101 10:52:25.878620 R8152: Done initializing
10102 10:52:25.878732
10103 10:52:25.878827 Adding net device
10104 10:52:27.824125
10105 10:52:27.824314 done.
10106 10:52:27.824418
10107 10:52:27.824514 MAC: 00:e0:4c:78:7a:aa
10108 10:52:27.824614
10109 10:52:27.827041 Sending DHCP discover... done.
10110 10:52:27.827151
10111 10:52:38.263801 Waiting for reply... R8152: Bulk read error 0xffffffbf
10112 10:52:38.263954
10113 10:52:38.267547 Receive failed.
10114 10:52:38.267671
10115 10:52:38.267768 done.
10116 10:52:38.267858
10117 10:52:38.270676 Sending DHCP request... done.
10118 10:52:38.270785
10119 10:52:38.275114 Waiting for reply... done.
10120 10:52:38.275234
10121 10:52:38.275341 My ip is 192.168.201.12
10122 10:52:38.275434
10123 10:52:38.278249 The DHCP server ip is 192.168.201.1
10124 10:52:38.278345
10125 10:52:38.284557 TFTP server IP predefined by user: 192.168.201.1
10126 10:52:38.284675
10127 10:52:38.291504 Bootfile predefined by user: 10590982/tftp-deploy-jn_vmrpw/kernel/image.itb
10128 10:52:38.291610
10129 10:52:38.294814 Sending tftp read request... done.
10130 10:52:38.294933
10131 10:52:38.297752 Waiting for the transfer...
10132 10:52:38.297865
10133 10:52:38.543237 00000000 ################################################################
10134 10:52:38.543407
10135 10:52:38.790173 00080000 ################################################################
10136 10:52:38.790365
10137 10:52:39.045063 00100000 ################################################################
10138 10:52:39.045271
10139 10:52:39.296827 00180000 ################################################################
10140 10:52:39.297029
10141 10:52:39.546531 00200000 ################################################################
10142 10:52:39.546719
10143 10:52:39.810653 00280000 ################################################################
10144 10:52:39.810815
10145 10:52:40.057393 00300000 ################################################################
10146 10:52:40.057560
10147 10:52:40.309545 00380000 ################################################################
10148 10:52:40.309701
10149 10:52:40.558647 00400000 ################################################################
10150 10:52:40.558834
10151 10:52:40.811141 00480000 ################################################################
10152 10:52:40.811338
10153 10:52:41.055114 00500000 ################################################################
10154 10:52:41.055310
10155 10:52:41.304359 00580000 ################################################################
10156 10:52:41.304564
10157 10:52:41.561340 00600000 ################################################################
10158 10:52:41.561542
10159 10:52:41.818424 00680000 ################################################################
10160 10:52:41.818621
10161 10:52:42.072780 00700000 ################################################################
10162 10:52:42.072981
10163 10:52:42.323387 00780000 ################################################################
10164 10:52:42.323585
10165 10:52:42.575733 00800000 ################################################################
10166 10:52:42.575892
10167 10:52:42.826425 00880000 ################################################################
10168 10:52:42.826575
10169 10:52:43.077176 00900000 ################################################################
10170 10:52:43.077370
10171 10:52:43.331239 00980000 ################################################################
10172 10:52:43.331436
10173 10:52:43.586772 00a00000 ################################################################
10174 10:52:43.586931
10175 10:52:43.835988 00a80000 ################################################################
10176 10:52:43.836180
10177 10:52:44.080830 00b00000 ################################################################
10178 10:52:44.081125
10179 10:52:44.327899 00b80000 ################################################################
10180 10:52:44.328167
10181 10:52:44.574424 00c00000 ################################################################
10182 10:52:44.574689
10183 10:52:44.823021 00c80000 ################################################################
10184 10:52:44.823178
10185 10:52:45.072046 00d00000 ################################################################
10186 10:52:45.072202
10187 10:52:45.320049 00d80000 ################################################################
10188 10:52:45.320231
10189 10:52:45.566332 00e00000 ################################################################
10190 10:52:45.566556
10191 10:52:45.811551 00e80000 ################################################################
10192 10:52:45.811808
10193 10:52:46.056156 00f00000 ################################################################
10194 10:52:46.056339
10195 10:52:46.301560 00f80000 ################################################################
10196 10:52:46.301754
10197 10:52:46.548709 01000000 ################################################################
10198 10:52:46.548978
10199 10:52:46.795751 01080000 ################################################################
10200 10:52:46.795903
10201 10:52:47.050032 01100000 ################################################################
10202 10:52:47.050224
10203 10:52:47.300389 01180000 ################################################################
10204 10:52:47.300540
10205 10:52:47.548461 01200000 ################################################################
10206 10:52:47.548647
10207 10:52:47.808727 01280000 ################################################################
10208 10:52:47.808874
10209 10:52:48.054241 01300000 ################################################################
10210 10:52:48.054396
10211 10:52:48.307203 01380000 ################################################################
10212 10:52:48.307406
10213 10:52:48.579677 01400000 ################################################################
10214 10:52:48.579835
10215 10:52:48.847121 01480000 ################################################################
10216 10:52:48.847285
10217 10:52:49.124084 01500000 ################################################################
10218 10:52:49.124230
10219 10:52:49.385947 01580000 ################################################################
10220 10:52:49.386096
10221 10:52:49.650687 01600000 ################################################################
10222 10:52:49.650842
10223 10:52:49.902743 01680000 ################################################################
10224 10:52:49.902880
10225 10:52:50.172929 01700000 ################################################################
10226 10:52:50.173084
10227 10:52:50.429153 01780000 ################################################################
10228 10:52:50.429300
10229 10:52:50.691675 01800000 ################################################################
10230 10:52:50.691827
10231 10:52:50.946620 01880000 ################################################################
10232 10:52:50.946773
10233 10:52:51.220343 01900000 ################################################################
10234 10:52:51.220482
10235 10:52:51.488947 01980000 ################################################################
10236 10:52:51.489090
10237 10:52:51.754787 01a00000 ############################################################### done.
10238 10:52:51.754969
10239 10:52:51.757977 The bootfile was 27771306 bytes long.
10240 10:52:51.758099
10241 10:52:51.761259 Sending tftp read request... done.
10242 10:52:51.761379
10243 10:52:51.761475 Waiting for the transfer...
10244 10:52:51.761567
10245 10:52:51.764567 00000000 # done.
10246 10:52:51.764686
10247 10:52:51.771380 Command line loaded dynamically from TFTP file: 10590982/tftp-deploy-jn_vmrpw/kernel/cmdline
10248 10:52:51.771518
10249 10:52:51.791220 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10250 10:52:51.791422
10251 10:52:51.794434 Loading FIT.
10252 10:52:51.794549
10253 10:52:51.797723 Image ramdisk-1 has 17640412 bytes.
10254 10:52:51.797835
10255 10:52:51.797929 Image fdt-1 has 46924 bytes.
10256 10:52:51.798020
10257 10:52:51.801010 Image kernel-1 has 10081937 bytes.
10258 10:52:51.801121
10259 10:52:51.810679 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 10:52:51.810840
10261 10:52:51.826905 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 10:52:51.830275
10263 10:52:51.833384 Choosing best match conf-1 for compat google,spherion-rev2.
10264 10:52:51.838337
10265 10:52:51.842709 Connected to device vid:did:rid of 1ae0:0028:00
10266 10:52:51.849529
10267 10:52:51.852756 tpm_get_response: command 0x17b, return code 0x0
10268 10:52:51.852885
10269 10:52:51.856479 ec_init: CrosEC protocol v3 supported (256, 248)
10270 10:52:51.860390
10271 10:52:51.863521 tpm_cleanup: add release locality here.
10272 10:52:51.863639
10273 10:52:51.863733 Shutting down all USB controllers.
10274 10:52:51.866763
10275 10:52:51.866872 Removing current net device
10276 10:52:51.866967
10277 10:52:51.873797 Exiting depthcharge with code 4 at timestamp: 59575587
10278 10:52:51.873938
10279 10:52:51.876843 LZMA decompressing kernel-1 to 0x821a6718
10280 10:52:51.876961
10281 10:52:51.879969 LZMA decompressing kernel-1 to 0x40000000
10282 10:52:53.146339
10283 10:52:53.146533 jumping to kernel
10284 10:52:53.147064 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10285 10:52:53.147204 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
10286 10:52:53.147342 Setting prompt string to ['Linux version [0-9]']
10287 10:52:53.147477 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 10:52:53.147579 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 10:52:53.228077
10290 10:52:53.231177 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 10:52:53.234589 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10292 10:52:53.234727 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 10:52:53.234849 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10294 10:52:53.234962 Using line separator: #'\n'#
10295 10:52:53.235054 No login prompt set.
10296 10:52:53.235147 Parsing kernel messages
10297 10:52:53.235234 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10298 10:52:53.235437 [login-action] Waiting for messages, (timeout 00:03:54)
10299 10:52:53.254075 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10300 10:52:53.257194 [ 0.000000] random: crng init done
10301 10:52:53.263814 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10302 10:52:53.267316 [ 0.000000] efi: UEFI not found.
10303 10:52:53.273760 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10304 10:52:53.280116 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10305 10:52:53.290511 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10306 10:52:53.300316 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10307 10:52:53.306385 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10308 10:52:53.313493 [ 0.000000] printk: bootconsole [mtk8250] enabled
10309 10:52:53.320027 [ 0.000000] NUMA: No NUMA configuration found
10310 10:52:53.326681 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10311 10:52:53.329953 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10312 10:52:53.333258 [ 0.000000] Zone ranges:
10313 10:52:53.339856 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10314 10:52:53.343304 [ 0.000000] DMA32 empty
10315 10:52:53.349629 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10316 10:52:53.352805 [ 0.000000] Movable zone start for each node
10317 10:52:53.355997 [ 0.000000] Early memory node ranges
10318 10:52:53.362570 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10319 10:52:53.369450 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10320 10:52:53.376027 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10321 10:52:53.382442 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10322 10:52:53.389119 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10323 10:52:53.396125 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10324 10:52:53.451827 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10325 10:52:53.458341 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10326 10:52:53.465472 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10327 10:52:53.468622 [ 0.000000] psci: probing for conduit method from DT.
10328 10:52:53.475308 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10329 10:52:53.478503 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10330 10:52:53.485018 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10331 10:52:53.488099 [ 0.000000] psci: SMC Calling Convention v1.2
10332 10:52:53.494815 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10333 10:52:53.498507 [ 0.000000] Detected VIPT I-cache on CPU0
10334 10:52:53.514856 [ 0.000000] CPU features: detected: GIC system register CPU interface
10335 10:52:53.515391 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10336 10:52:53.518354 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10337 10:52:53.524601 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10338 10:52:53.531844 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10339 10:52:53.538293 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10340 10:52:53.544754 [ 0.000000] alternatives: applying boot alternatives
10341 10:52:53.547929 [ 0.000000] Fallback order for Node 0: 0
10342 10:52:53.558410 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10343 10:52:53.558548 [ 0.000000] Policy zone: Normal
10344 10:52:53.581240 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10345 10:52:53.591087 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10346 10:52:53.602235 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10347 10:52:53.612578 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10348 10:52:53.618690 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10349 10:52:53.622015 <6>[ 0.000000] software IO TLB: area num 8.
10350 10:52:53.679059 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10351 10:52:53.828501 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10352 10:52:53.835086 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10353 10:52:53.841748 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10354 10:52:53.845113 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10355 10:52:53.851991 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10356 10:52:53.858552 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10357 10:52:53.861836 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10358 10:52:53.871729 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10359 10:52:53.878265 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10360 10:52:53.884696 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10361 10:52:53.891627 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10362 10:52:53.895029 <6>[ 0.000000] GICv3: 608 SPIs implemented
10363 10:52:53.898264 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10364 10:52:53.904854 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10365 10:52:53.907893 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10366 10:52:53.914655 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10367 10:52:53.928023 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10368 10:52:53.938062 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10369 10:52:53.948088 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10370 10:52:53.955147 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10371 10:52:53.968340 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10372 10:52:53.975055 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10373 10:52:53.981607 <6>[ 0.009175] Console: colour dummy device 80x25
10374 10:52:53.992002 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10375 10:52:53.995260 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10376 10:52:54.001652 <6>[ 0.029220] LSM: Security Framework initializing
10377 10:52:54.008718 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 10:52:54.018076 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 10:52:54.024985 <6>[ 0.051391] cblist_init_generic: Setting adjustable number of callback queues.
10380 10:52:54.031843 <6>[ 0.058890] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 10:52:54.038410 <6>[ 0.065267] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 10:52:54.044886 <6>[ 0.071677] rcu: Hierarchical SRCU implementation.
10383 10:52:54.048006 <6>[ 0.076691] rcu: Max phase no-delay instances is 1000.
10384 10:52:54.056345 <6>[ 0.083744] EFI services will not be available.
10385 10:52:54.059516 <6>[ 0.088716] smp: Bringing up secondary CPUs ...
10386 10:52:54.068665 <6>[ 0.093799] Detected VIPT I-cache on CPU1
10387 10:52:54.075521 <6>[ 0.093869] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10388 10:52:54.081888 <6>[ 0.093899] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10389 10:52:54.085392 <6>[ 0.094234] Detected VIPT I-cache on CPU2
10390 10:52:54.092062 <6>[ 0.094283] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10391 10:52:54.101864 <6>[ 0.094298] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10392 10:52:54.105249 <6>[ 0.094563] Detected VIPT I-cache on CPU3
10393 10:52:54.111626 <6>[ 0.094610] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10394 10:52:54.117912 <6>[ 0.094624] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10395 10:52:54.121095 <6>[ 0.094930] CPU features: detected: Spectre-v4
10396 10:52:54.128244 <6>[ 0.094936] CPU features: detected: Spectre-BHB
10397 10:52:54.131384 <6>[ 0.094942] Detected PIPT I-cache on CPU4
10398 10:52:54.138016 <6>[ 0.094997] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10399 10:52:54.144560 <6>[ 0.095015] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10400 10:52:54.151220 <6>[ 0.095310] Detected PIPT I-cache on CPU5
10401 10:52:54.157979 <6>[ 0.095372] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10402 10:52:54.164565 <6>[ 0.095388] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10403 10:52:54.167831 <6>[ 0.095672] Detected PIPT I-cache on CPU6
10404 10:52:54.174402 <6>[ 0.095738] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10405 10:52:54.181376 <6>[ 0.095755] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10406 10:52:54.187759 <6>[ 0.096052] Detected PIPT I-cache on CPU7
10407 10:52:54.194495 <6>[ 0.096117] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10408 10:52:54.201305 <6>[ 0.096133] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10409 10:52:54.204516 <6>[ 0.096181] smp: Brought up 1 node, 8 CPUs
10410 10:52:54.211161 <6>[ 0.237480] SMP: Total of 8 processors activated.
10411 10:52:54.214245 <6>[ 0.242401] CPU features: detected: 32-bit EL0 Support
10412 10:52:54.224164 <6>[ 0.247763] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10413 10:52:54.231138 <6>[ 0.256562] CPU features: detected: Common not Private translations
10414 10:52:54.234423 <6>[ 0.263038] CPU features: detected: CRC32 instructions
10415 10:52:54.240780 <6>[ 0.268422] CPU features: detected: RCpc load-acquire (LDAPR)
10416 10:52:54.247513 <6>[ 0.274418] CPU features: detected: LSE atomic instructions
10417 10:52:54.254618 <6>[ 0.280199] CPU features: detected: Privileged Access Never
10418 10:52:54.257711 <6>[ 0.285979] CPU features: detected: RAS Extension Support
10419 10:52:54.267512 <6>[ 0.291622] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10420 10:52:54.270934 <6>[ 0.298842] CPU: All CPU(s) started at EL2
10421 10:52:54.277918 <6>[ 0.303158] alternatives: applying system-wide alternatives
10422 10:52:54.286346 <6>[ 0.313863] devtmpfs: initialized
10423 10:52:54.301951 <6>[ 0.323009] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10424 10:52:54.308598 <6>[ 0.332970] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10425 10:52:54.311747 <6>[ 0.340572] pinctrl core: initialized pinctrl subsystem
10426 10:52:54.319498 <6>[ 0.347240] DMI not present or invalid.
10427 10:52:54.326363 <6>[ 0.351650] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10428 10:52:54.332722 <6>[ 0.358551] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10429 10:52:54.342682 <6>[ 0.366128] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10430 10:52:54.349599 <6>[ 0.374355] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10431 10:52:54.356181 <6>[ 0.382593] audit: initializing netlink subsys (disabled)
10432 10:52:54.362702 <5>[ 0.388286] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10433 10:52:54.369344 <6>[ 0.388985] thermal_sys: Registered thermal governor 'step_wise'
10434 10:52:54.376317 <6>[ 0.396250] thermal_sys: Registered thermal governor 'power_allocator'
10435 10:52:54.379137 <6>[ 0.402507] cpuidle: using governor menu
10436 10:52:54.386015 <6>[ 0.413468] NET: Registered PF_QIPCRTR protocol family
10437 10:52:54.392680 <6>[ 0.418951] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10438 10:52:54.399287 <6>[ 0.426048] ASID allocator initialised with 32768 entries
10439 10:52:54.402742 <6>[ 0.432620] Serial: AMBA PL011 UART driver
10440 10:52:54.413810 <4>[ 0.441306] Trying to register duplicate clock ID: 134
10441 10:52:54.467931 <6>[ 0.498755] KASLR enabled
10442 10:52:54.482412 <6>[ 0.506683] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10443 10:52:54.488773 <6>[ 0.513696] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10444 10:52:54.495837 <6>[ 0.520184] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10445 10:52:54.502541 <6>[ 0.527189] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10446 10:52:54.509087 <6>[ 0.533672] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10447 10:52:54.515541 <6>[ 0.540675] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10448 10:52:54.521883 <6>[ 0.547161] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10449 10:52:54.528757 <6>[ 0.554166] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10450 10:52:54.532068 <6>[ 0.561695] ACPI: Interpreter disabled.
10451 10:52:54.540168 <6>[ 0.568101] iommu: Default domain type: Translated
10452 10:52:54.547064 <6>[ 0.573212] iommu: DMA domain TLB invalidation policy: strict mode
10453 10:52:54.550197 <5>[ 0.579870] SCSI subsystem initialized
10454 10:52:54.557286 <6>[ 0.584036] usbcore: registered new interface driver usbfs
10455 10:52:54.563899 <6>[ 0.589767] usbcore: registered new interface driver hub
10456 10:52:54.566548 <6>[ 0.595318] usbcore: registered new device driver usb
10457 10:52:54.573873 <6>[ 0.601404] pps_core: LinuxPPS API ver. 1 registered
10458 10:52:54.583799 <6>[ 0.606597] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10459 10:52:54.587074 <6>[ 0.615944] PTP clock support registered
10460 10:52:54.590182 <6>[ 0.620185] EDAC MC: Ver: 3.0.0
10461 10:52:54.597808 <6>[ 0.625313] FPGA manager framework
10462 10:52:54.600898 <6>[ 0.628993] Advanced Linux Sound Architecture Driver Initialized.
10463 10:52:54.604741 <6>[ 0.635768] vgaarb: loaded
10464 10:52:54.611568 <6>[ 0.638945] clocksource: Switched to clocksource arch_sys_counter
10465 10:52:54.618281 <5>[ 0.645382] VFS: Disk quotas dquot_6.6.0
10466 10:52:54.624830 <6>[ 0.649568] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10467 10:52:54.628103 <6>[ 0.656757] pnp: PnP ACPI: disabled
10468 10:52:54.636107 <6>[ 0.663502] NET: Registered PF_INET protocol family
10469 10:52:54.645565 <6>[ 0.669098] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10470 10:52:54.657264 <6>[ 0.681419] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10471 10:52:54.666771 <6>[ 0.690234] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10472 10:52:54.673548 <6>[ 0.698206] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10473 10:52:54.680399 <6>[ 0.706902] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10474 10:52:54.692619 <6>[ 0.716642] TCP: Hash tables configured (established 65536 bind 65536)
10475 10:52:54.698740 <6>[ 0.723496] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 10:52:54.705892 <6>[ 0.730693] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10477 10:52:54.712220 <6>[ 0.738392] NET: Registered PF_UNIX/PF_LOCAL protocol family
10478 10:52:54.718717 <6>[ 0.744552] RPC: Registered named UNIX socket transport module.
10479 10:52:54.721987 <6>[ 0.750707] RPC: Registered udp transport module.
10480 10:52:54.728465 <6>[ 0.755641] RPC: Registered tcp transport module.
10481 10:52:54.735467 <6>[ 0.760572] RPC: Registered tcp NFSv4.1 backchannel transport module.
10482 10:52:54.738838 <6>[ 0.767242] PCI: CLS 0 bytes, default 64
10483 10:52:54.742192 <6>[ 0.771626] Unpacking initramfs...
10484 10:52:54.752260 <6>[ 0.775454] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10485 10:52:54.758462 <6>[ 0.784128] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10486 10:52:54.764956 <6>[ 0.792905] kvm [1]: IPA Size Limit: 40 bits
10487 10:52:54.768864 <6>[ 0.797431] kvm [1]: GICv3: no GICV resource entry
10488 10:52:54.774832 <6>[ 0.802449] kvm [1]: disabling GICv2 emulation
10489 10:52:54.781883 <6>[ 0.807137] kvm [1]: GIC system register CPU interface enabled
10490 10:52:54.785331 <6>[ 0.813301] kvm [1]: vgic interrupt IRQ18
10491 10:52:54.791788 <6>[ 0.817656] kvm [1]: VHE mode initialized successfully
10492 10:52:54.795181 <5>[ 0.824086] Initialise system trusted keyrings
10493 10:52:54.801218 <6>[ 0.828874] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10494 10:52:54.811492 <6>[ 0.839006] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10495 10:52:54.817656 <5>[ 0.845410] NFS: Registering the id_resolver key type
10496 10:52:54.820988 <5>[ 0.850715] Key type id_resolver registered
10497 10:52:54.827835 <5>[ 0.855129] Key type id_legacy registered
10498 10:52:54.834492 <6>[ 0.859413] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10499 10:52:54.841015 <6>[ 0.866334] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10500 10:52:54.847989 <6>[ 0.874061] 9p: Installing v9fs 9p2000 file system support
10501 10:52:54.884896 <5>[ 0.912227] Key type asymmetric registered
10502 10:52:54.888264 <5>[ 0.916565] Asymmetric key parser 'x509' registered
10503 10:52:54.898072 <6>[ 0.921711] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10504 10:52:54.901418 <6>[ 0.929325] io scheduler mq-deadline registered
10505 10:52:54.904670 <6>[ 0.934086] io scheduler kyber registered
10506 10:52:54.923311 <6>[ 0.950920] EINJ: ACPI disabled.
10507 10:52:54.955563 <4>[ 0.976222] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 10:52:54.964921 <4>[ 0.986874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10509 10:52:54.979830 <6>[ 1.007509] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10510 10:52:54.987989 <6>[ 1.015543] printk: console [ttyS0] disabled
10511 10:52:55.015988 <6>[ 1.040232] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10512 10:52:55.022513 <6>[ 1.049720] printk: console [ttyS0] enabled
10513 10:52:55.025610 <6>[ 1.049720] printk: console [ttyS0] enabled
10514 10:52:55.032865 <6>[ 1.058620] printk: bootconsole [mtk8250] disabled
10515 10:52:55.036120 <6>[ 1.058620] printk: bootconsole [mtk8250] disabled
10516 10:52:55.042501 <6>[ 1.069873] SuperH (H)SCI(F) driver initialized
10517 10:52:55.045869 <6>[ 1.075180] msm_serial: driver initialized
10518 10:52:55.059832 <6>[ 1.084258] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 10:52:55.070136 <6>[ 1.092810] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 10:52:55.076487 <6>[ 1.101352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 10:52:55.086056 <6>[ 1.109980] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 10:52:55.096107 <6>[ 1.118686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 10:52:55.103455 <6>[ 1.127402] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 10:52:55.112741 <6>[ 1.135942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 10:52:55.119321 <6>[ 1.144733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 10:52:55.129671 <6>[ 1.153276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 10:52:55.141514 <6>[ 1.169016] loop: module loaded
10528 10:52:55.147665 <6>[ 1.175137] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 10:52:55.170979 <4>[ 1.198534] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 10:52:55.177262 <6>[ 1.205364] megasas: 07.719.03.00-rc1
10531 10:52:55.187575 <6>[ 1.215105] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10532 10:52:55.194905 <6>[ 1.222326] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10533 10:52:55.211115 <6>[ 1.238992] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 10:52:55.268261 <6>[ 1.289324] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10535 10:52:55.472925 <6>[ 1.500692] Freeing initrd memory: 17220K
10536 10:52:55.482931 <6>[ 1.510870] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 10:52:55.494100 <6>[ 1.521955] tun: Universal TUN/TAP device driver, 1.6
10538 10:52:55.497315 <6>[ 1.528027] thunder_xcv, ver 1.0
10539 10:52:55.501306 <6>[ 1.531535] thunder_bgx, ver 1.0
10540 10:52:55.504455 <6>[ 1.535031] nicpf, ver 1.0
10541 10:52:55.514868 <6>[ 1.539060] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 10:52:55.518132 <6>[ 1.546536] hns3: Copyright (c) 2017 Huawei Corporation.
10543 10:52:55.521255 <6>[ 1.552123] hclge is initializing
10544 10:52:55.527772 <6>[ 1.555706] e1000: Intel(R) PRO/1000 Network Driver
10545 10:52:55.534519 <6>[ 1.560836] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 10:52:55.537856 <6>[ 1.566850] e1000e: Intel(R) PRO/1000 Network Driver
10547 10:52:55.544478 <6>[ 1.572066] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 10:52:55.551271 <6>[ 1.578254] igb: Intel(R) Gigabit Ethernet Network Driver
10549 10:52:55.557773 <6>[ 1.583904] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 10:52:55.564862 <6>[ 1.589742] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 10:52:55.571133 <6>[ 1.596260] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 10:52:55.574312 <6>[ 1.602720] sky2: driver version 1.30
10553 10:52:55.580871 <6>[ 1.607712] VFIO - User Level meta-driver version: 0.3
10554 10:52:55.587934 <6>[ 1.615884] usbcore: registered new interface driver usb-storage
10555 10:52:55.594555 <6>[ 1.622328] usbcore: registered new device driver onboard-usb-hub
10556 10:52:55.603700 <6>[ 1.631369] mt6397-rtc mt6359-rtc: registered as rtc0
10557 10:52:55.613589 <6>[ 1.636832] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:52:43 UTC (1685962363)
10558 10:52:55.617373 <6>[ 1.646397] i2c_dev: i2c /dev entries driver
10559 10:52:55.633647 <6>[ 1.658146] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10560 10:52:55.640836 <6>[ 1.668408] sdhci: Secure Digital Host Controller Interface driver
10561 10:52:55.647531 <6>[ 1.674846] sdhci: Copyright(c) Pierre Ossman
10562 10:52:55.654108 <6>[ 1.680241] Synopsys Designware Multimedia Card Interface Driver
10563 10:52:55.657259 <6>[ 1.686833] mmc0: CQHCI version 5.10
10564 10:52:55.663703 <6>[ 1.687394] sdhci-pltfm: SDHCI platform and OF driver helper
10565 10:52:55.670855 <6>[ 1.698764] ledtrig-cpu: registered to indicate activity on CPUs
10566 10:52:55.681661 <6>[ 1.706126] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10567 10:52:55.684873 <6>[ 1.713514] usbcore: registered new interface driver usbhid
10568 10:52:55.691232 <6>[ 1.719341] usbhid: USB HID core driver
10569 10:52:55.698057 <6>[ 1.723588] spi_master spi0: will run message pump with realtime priority
10570 10:52:55.739606 <6>[ 1.760652] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10571 10:52:55.758000 <6>[ 1.775515] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10572 10:52:55.761518 <6>[ 1.789083] mmc0: Command Queue Engine enabled
10573 10:52:55.768538 <6>[ 1.791358] cros-ec-spi spi0.0: Chrome EC device registered
10574 10:52:55.771859 <6>[ 1.793837] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10575 10:52:55.779170 <6>[ 1.806882] mmcblk0: mmc0:0001 DA4128 116 GiB
10576 10:52:55.791644 <6>[ 1.815852] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10577 10:52:55.797909 <6>[ 1.817107] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10578 10:52:55.804819 <6>[ 1.827236] NET: Registered PF_PACKET protocol family
10579 10:52:55.808129 <6>[ 1.832446] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10580 10:52:55.815052 <6>[ 1.836504] 9pnet: Installing 9P2000 support
10581 10:52:55.818236 <6>[ 1.842275] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10582 10:52:55.821532 <5>[ 1.846180] Key type dns_resolver registered
10583 10:52:55.828284 <6>[ 1.851974] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10584 10:52:55.834654 <6>[ 1.856395] registered taskstats version 1
10585 10:52:55.837930 <5>[ 1.866787] Loading compiled-in X.509 certificates
10586 10:52:55.873523 <4>[ 1.894414] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 10:52:55.883255 <4>[ 1.905107] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 10:52:55.893185 <3>[ 1.917703] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10589 10:52:55.905551 <6>[ 1.933409] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10590 10:52:55.912754 <6>[ 1.940225] xhci-mtk 11200000.usb: xHCI Host Controller
10591 10:52:55.918838 <6>[ 1.945742] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10592 10:52:55.929026 <6>[ 1.953691] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10593 10:52:55.935634 <6>[ 1.963162] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10594 10:52:55.942692 <6>[ 1.969252] xhci-mtk 11200000.usb: xHCI Host Controller
10595 10:52:55.949285 <6>[ 1.974742] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10596 10:52:55.955851 <6>[ 1.982403] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10597 10:52:55.962372 <6>[ 1.990325] hub 1-0:1.0: USB hub found
10598 10:52:55.965628 <6>[ 1.994366] hub 1-0:1.0: 1 port detected
10599 10:52:55.976013 <6>[ 1.998713] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10600 10:52:55.979492 <6>[ 2.007566] hub 2-0:1.0: USB hub found
10601 10:52:55.982672 <6>[ 2.011603] hub 2-0:1.0: 1 port detected
10602 10:52:55.990783 <6>[ 2.018658] mtk-msdc 11f70000.mmc: Got CD GPIO
10603 10:52:56.007678 <6>[ 2.031877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10604 10:52:56.014265 <6>[ 2.039929] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10605 10:52:56.024255 <4>[ 2.047911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10606 10:52:56.034319 <6>[ 2.057583] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10607 10:52:56.040793 <6>[ 2.065670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10608 10:52:56.047838 <6>[ 2.073698] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10609 10:52:56.057743 <6>[ 2.081613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10610 10:52:56.064228 <6>[ 2.089436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10611 10:52:56.074154 <6>[ 2.097258] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10612 10:52:56.084654 <6>[ 2.108032] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10613 10:52:56.090927 <6>[ 2.116402] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10614 10:52:56.100941 <6>[ 2.124748] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10615 10:52:56.107655 <6>[ 2.133090] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10616 10:52:56.117360 <6>[ 2.141433] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10617 10:52:56.124569 <6>[ 2.149776] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10618 10:52:56.134422 <6>[ 2.158118] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10619 10:52:56.140962 <6>[ 2.166461] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10620 10:52:56.151294 <6>[ 2.174803] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10621 10:52:56.157871 <6>[ 2.183149] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10622 10:52:56.167652 <6>[ 2.191493] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10623 10:52:56.174195 <6>[ 2.199836] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10624 10:52:56.184659 <6>[ 2.208179] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10625 10:52:56.191103 <6>[ 2.216524] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10626 10:52:56.201207 <6>[ 2.224873] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10627 10:52:56.207981 <6>[ 2.233807] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10628 10:52:56.214188 <6>[ 2.241235] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10629 10:52:56.220962 <6>[ 2.248287] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10630 10:52:56.230994 <6>[ 2.255400] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10631 10:52:56.237446 <6>[ 2.262684] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10632 10:52:56.244121 <6>[ 2.269593] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10633 10:52:56.254160 <6>[ 2.278732] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10634 10:52:56.263891 <6>[ 2.287860] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10635 10:52:56.274404 <6>[ 2.297163] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10636 10:52:56.283966 <6>[ 2.306640] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10637 10:52:56.293705 <6>[ 2.316127] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10638 10:52:56.300277 <6>[ 2.325260] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10639 10:52:56.310265 <6>[ 2.334735] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10640 10:52:56.320698 <6>[ 2.343861] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10641 10:52:56.330599 <6>[ 2.353163] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10642 10:52:56.340244 <6>[ 2.363329] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10643 10:52:56.350877 <6>[ 2.375194] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10644 10:52:56.357211 <6>[ 2.385121] Trying to probe devices needed for running init ...
10645 10:52:56.390403 <6>[ 2.415068] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10646 10:52:56.544806 <6>[ 2.572707] hub 1-1:1.0: USB hub found
10647 10:52:56.548590 <6>[ 2.577140] hub 1-1:1.0: 4 ports detected
10648 10:52:56.670604 <6>[ 2.695411] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 10:52:56.695783 <6>[ 2.723671] hub 2-1:1.0: USB hub found
10650 10:52:56.699035 <6>[ 2.728067] hub 2-1:1.0: 3 ports detected
10651 10:52:56.870542 <6>[ 2.895248] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10652 10:52:57.003808 <6>[ 3.031543] hub 1-1.4:1.0: USB hub found
10653 10:52:57.006838 <6>[ 3.036195] hub 1-1.4:1.0: 2 ports detected
10654 10:52:57.082588 <6>[ 3.107471] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10655 10:52:57.306639 <6>[ 3.331222] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10656 10:52:57.498873 <6>[ 3.523222] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10657 10:53:08.635055 <6>[ 14.667818] ALSA device list:
10658 10:53:08.642017 <6>[ 14.671082] No soundcards found.
10659 10:53:08.649068 <6>[ 14.678289] Freeing unused kernel memory: 8384K
10660 10:53:08.652409 <6>[ 14.683280] Run /init as init process
10661 10:53:08.661054 Loading, please wait...
10662 10:53:08.678572 Starting version 247.3-7+deb11u2
10663 10:53:09.017063 <6>[ 15.042861] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10664 10:53:09.029141 <3>[ 15.055247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 10:53:09.035875 <3>[ 15.063725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 10:53:09.042482 <6>[ 15.063968] remoteproc remoteproc0: scp is available
10667 10:53:09.049126 <3>[ 15.071865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 10:53:09.059262 <4>[ 15.077214] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10669 10:53:09.069064 <3>[ 15.086823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 10:53:09.072316 <6>[ 15.087010] mc: Linux media interface: v0.10
10671 10:53:09.078853 <6>[ 15.095177] remoteproc remoteproc0: powering up scp
10672 10:53:09.089149 <4>[ 15.095253] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10673 10:53:09.095775 <3>[ 15.103568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 10:53:09.102946 <3>[ 15.107871] remoteproc remoteproc0: request_firmware failed: -2
10675 10:53:09.109507 <6>[ 15.131351] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10676 10:53:09.119400 <3>[ 15.137211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 10:53:09.125675 <6>[ 15.145517] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10678 10:53:09.135814 <3>[ 15.152792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 10:53:09.145825 <6>[ 15.161494] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10680 10:53:09.149003 <6>[ 15.166268] videodev: Linux video capture interface: v2.00
10681 10:53:09.158588 <3>[ 15.169593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 10:53:09.165197 <3>[ 15.192251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 10:53:09.168334 <6>[ 15.193096] Bluetooth: Core ver 2.22
10684 10:53:09.178876 <3>[ 15.203044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 10:53:09.181616 <6>[ 15.205012] NET: Registered PF_BLUETOOTH protocol family
10686 10:53:09.191752 <3>[ 15.212293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 10:53:09.198179 <6>[ 15.217833] Bluetooth: HCI device and connection manager initialized
10688 10:53:09.204698 <6>[ 15.217866] Bluetooth: HCI socket layer initialized
10689 10:53:09.211461 <6>[ 15.218259] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10690 10:53:09.217980 <4>[ 15.221868] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10691 10:53:09.228572 <3>[ 15.226035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 10:53:09.235688 <4>[ 15.229300] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10693 10:53:09.238780 <6>[ 15.232591] Bluetooth: L2CAP socket layer initialized
10694 10:53:09.248480 <4>[ 15.239959] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10695 10:53:09.251816 <4>[ 15.239959] Fallback method does not support PEC.
10696 10:53:09.261913 <3>[ 15.244856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 10:53:09.268217 <3>[ 15.244905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 10:53:09.278212 <3>[ 15.244915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 10:53:09.284961 <3>[ 15.244930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 10:53:09.295285 <3>[ 15.244940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 10:53:09.298445 <6>[ 15.245442] Bluetooth: SCO socket layer initialized
10702 10:53:09.305845 <3>[ 15.250168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 10:53:09.312309 <6>[ 15.263295] usbcore: registered new interface driver r8152
10704 10:53:09.322101 <3>[ 15.273480] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 10:53:09.328748 <6>[ 15.296337] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10706 10:53:09.335876 <3>[ 15.338898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 10:53:09.342431 <6>[ 15.341227] pci_bus 0000:00: root bus resource [bus 00-ff]
10708 10:53:09.352076 <6>[ 15.351344] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10709 10:53:09.358738 <6>[ 15.355836] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10710 10:53:09.368696 <6>[ 15.363484] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10711 10:53:09.375116 <6>[ 15.363689] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10712 10:53:09.385279 <6>[ 15.365540] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10713 10:53:09.395442 <6>[ 15.371438] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10714 10:53:09.402066 <6>[ 15.371514] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10715 10:53:09.408670 <6>[ 15.395821] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10716 10:53:09.415439 <6>[ 15.401565] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10717 10:53:09.422036 <6>[ 15.401963] usbcore: registered new interface driver cdc_ether
10718 10:53:09.428809 <6>[ 15.411062] usbcore: registered new interface driver r8153_ecm
10719 10:53:09.435337 <6>[ 15.411937] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10720 10:53:09.448542 <6>[ 15.413072] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10721 10:53:09.451656 <6>[ 15.413569] usbcore: registered new interface driver uvcvideo
10722 10:53:09.458670 <6>[ 15.419970] pci 0000:00:00.0: supports D1 D2
10723 10:53:09.465129 <6>[ 15.420556] usbcore: registered new interface driver btusb
10724 10:53:09.471872 <4>[ 15.420624] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10725 10:53:09.481620 <4>[ 15.420635] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10726 10:53:09.491538 <4>[ 15.421143] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10727 10:53:09.498073 <3>[ 15.421152] Bluetooth: hci0: Failed to load firmware file (-2)
10728 10:53:09.501448 <3>[ 15.421157] Bluetooth: hci0: Failed to set up firmware (-2)
10729 10:53:09.515175 <4>[ 15.421160] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10730 10:53:09.518229 <6>[ 15.439248] r8152 2-1.3:1.0 eth0: v1.12.13
10731 10:53:09.525092 <6>[ 15.443087] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10732 10:53:09.531395 <6>[ 15.444875] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10733 10:53:09.538480 <6>[ 15.458420] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10734 10:53:09.545041 <6>[ 15.462907] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10735 10:53:09.551489 <6>[ 15.579728] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10736 10:53:09.561062 <6>[ 15.587221] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10737 10:53:09.568114 <6>[ 15.594710] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10738 10:53:09.571386 <6>[ 15.602303] pci 0000:01:00.0: supports D1 D2
10739 10:53:09.577975 <6>[ 15.606828] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10740 10:53:09.597326 <6>[ 15.623339] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10741 10:53:09.604397 <6>[ 15.630261] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10742 10:53:09.610977 <6>[ 15.638351] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10743 10:53:09.621072 <6>[ 15.646362] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10744 10:53:09.627297 <6>[ 15.654370] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10745 10:53:09.636816 <6>[ 15.662377] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10746 10:53:09.640639 <6>[ 15.670383] pci 0000:00:00.0: PCI bridge to [bus 01]
10747 10:53:09.650474 <6>[ 15.675605] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10748 10:53:09.656761 <6>[ 15.683765] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10749 10:53:09.663288 <6>[ 15.691042] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10750 10:53:09.669835 <6>[ 15.697772] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10751 10:53:09.688098 <5>[ 15.714296] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10752 10:53:09.708079 <5>[ 15.734321] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10753 10:53:09.715126 <4>[ 15.741215] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10754 10:53:09.721578 <6>[ 15.750096] cfg80211: failed to load regulatory.db
10755 10:53:09.771224 <6>[ 15.797242] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10756 10:53:09.777780 <6>[ 15.804831] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10757 10:53:09.801945 <6>[ 15.831545] mt7921e 0000:01:00.0: ASIC revision: 79610010
10758 10:53:09.907688 <4>[ 15.930507] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 10:53:09.925352 Begin: Loading essential drivers ... done.
10760 10:53:09.929236 Begin: Running /scripts/init-premount ... done.
10761 10:53:09.935883 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10762 10:53:09.945463 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10763 10:53:09.948552 Device /sys/class/net/enx00e04c787aaa found
10764 10:53:09.948636 done.
10765 10:53:10.013717 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10766 10:53:10.027807 <4>[ 16.050508] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 10:53:10.146462 <4>[ 16.168954] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 10:53:10.261742 <4>[ 16.284808] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 10:53:10.378034 <4>[ 16.400778] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 10:53:10.493393 <4>[ 16.516651] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 10:53:10.609369 <4>[ 16.632596] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 10:53:10.725605 <4>[ 16.748571] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 10:53:10.842133 <4>[ 16.864632] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 10:53:10.957634 <4>[ 16.980603] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 10:53:11.064774 <3>[ 17.094396] mt7921e 0000:01:00.0: hardware init failed
10776 10:53:11.071505 <6>[ 17.099061] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10777 10:53:11.107157 IP-Config: no response after 2 secs - giving up
10778 10:53:11.148871 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10779 10:53:11.152115 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10780 10:53:11.159176 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10781 10:53:11.165711 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10782 10:53:11.172519 host : mt8192-asurada-spherion-r0-cbg-0
10783 10:53:11.179405 domain : lava-rack
10784 10:53:11.182564 rootserver: 192.168.201.1 rootpath:
10785 10:53:11.185653 filename :
10786 10:53:11.213034 done.
10787 10:53:11.216374 Begin: Running /scripts/nfs-bottom ... done.
10788 10:53:11.236609 Begin: Running /scripts/init-bottom ... done.
10789 10:53:12.309958 <6>[ 18.339653] NET: Registered PF_INET6 protocol family
10790 10:53:12.316840 <6>[ 18.346328] Segment Routing with IPv6
10791 10:53:12.320086 <6>[ 18.350292] In-situ OAM (IOAM) with IPv6
10792 10:53:12.418566 <30>[ 18.431427] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10793 10:53:12.425517 <30>[ 18.455277] systemd[1]: Detected architecture arm64.
10794 10:53:12.443247
10795 10:53:12.446412 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10796 10:53:12.446523
10797 10:53:12.463476 <30>[ 18.493041] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10798 10:53:12.899791 <30>[ 18.926094] systemd[1]: Queued start job for default target Graphical Interface.
10799 10:53:12.934482 <30>[ 18.964219] systemd[1]: Created slice system-getty.slice.
10800 10:53:12.941180 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10801 10:53:12.957972 <30>[ 18.987797] systemd[1]: Created slice system-modprobe.slice.
10802 10:53:12.965005 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10803 10:53:12.982549 <30>[ 19.012375] systemd[1]: Created slice system-serial\x2dgetty.slice.
10804 10:53:12.992480 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10805 10:53:13.006026 <30>[ 19.035746] systemd[1]: Created slice User and Session Slice.
10806 10:53:13.012658 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10807 10:53:13.033047 <30>[ 19.059789] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10808 10:53:13.043011 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10809 10:53:13.060787 <30>[ 19.087396] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10810 10:53:13.067295 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10811 10:53:13.088362 <30>[ 19.111334] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10812 10:53:13.095151 <30>[ 19.123366] systemd[1]: Reached target Local Encrypted Volumes.
10813 10:53:13.101240 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10814 10:53:13.118055 <30>[ 19.147514] systemd[1]: Reached target Paths.
10815 10:53:13.121312 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10816 10:53:13.137699 <30>[ 19.167236] systemd[1]: Reached target Remote File Systems.
10817 10:53:13.144447 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10818 10:53:13.157596 <30>[ 19.187253] systemd[1]: Reached target Slices.
10819 10:53:13.160906 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10820 10:53:13.177189 <30>[ 19.207271] systemd[1]: Reached target Swap.
10821 10:53:13.180423 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10822 10:53:13.201397 <30>[ 19.227575] systemd[1]: Listening on initctl Compatibility Named Pipe.
10823 10:53:13.207941 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10824 10:53:13.214601 <30>[ 19.242870] systemd[1]: Listening on Journal Audit Socket.
10825 10:53:13.220910 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10826 10:53:13.234217 <30>[ 19.264138] systemd[1]: Listening on Journal Socket (/dev/log).
10827 10:53:13.241577 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10828 10:53:13.258059 <30>[ 19.288040] systemd[1]: Listening on Journal Socket.
10829 10:53:13.264500 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10830 10:53:13.281965 <30>[ 19.308408] systemd[1]: Listening on Network Service Netlink Socket.
10831 10:53:13.288502 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10832 10:53:13.304106 <30>[ 19.333610] systemd[1]: Listening on udev Control Socket.
10833 10:53:13.310208 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10834 10:53:13.325844 <30>[ 19.355510] systemd[1]: Listening on udev Kernel Socket.
10835 10:53:13.332150 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10836 10:53:13.381986 <30>[ 19.411532] systemd[1]: Mounting Huge Pages File System...
10837 10:53:13.388496 Mounting [0;1;39mHuge Pages File System[0m...
10838 10:53:13.404148 <30>[ 19.433553] systemd[1]: Mounting POSIX Message Queue File System...
10839 10:53:13.410791 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10840 10:53:13.428127 <30>[ 19.458110] systemd[1]: Mounting Kernel Debug File System...
10841 10:53:13.434774 Mounting [0;1;39mKernel Debug File System[0m...
10842 10:53:13.452968 <30>[ 19.479585] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10843 10:53:13.470968 <30>[ 19.497732] systemd[1]: Starting Create list of static device nodes for the current kernel...
10844 10:53:13.477565 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10845 10:53:13.496486 <30>[ 19.525817] systemd[1]: Starting Load Kernel Module configfs...
10846 10:53:13.502454 Starting [0;1;39mLoad Kernel Module configfs[0m...
10847 10:53:13.520127 <30>[ 19.549773] systemd[1]: Starting Load Kernel Module drm...
10848 10:53:13.526687 Starting [0;1;39mLoad Kernel Module drm[0m...
10849 10:53:13.544220 <30>[ 19.573849] systemd[1]: Starting Load Kernel Module fuse...
10850 10:53:13.551012 Starting [0;1;39mLoad Kernel Module fuse[0m...
10851 10:53:13.578445 <6>[ 19.608356] fuse: init (API version 7.37)
10852 10:53:13.588360 <30>[ 19.608601] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10853 10:53:13.610192 <30>[ 19.639864] systemd[1]: Starting Journal Service...
10854 10:53:13.613456 Starting [0;1;39mJournal Service[0m...
10855 10:53:13.635424 <30>[ 19.665566] systemd[1]: Starting Load Kernel Modules...
10856 10:53:13.642071 Starting [0;1;39mLoad Kernel Modules[0m...
10857 10:53:13.664119 <30>[ 19.690727] systemd[1]: Starting Remount Root and Kernel File Systems...
10858 10:53:13.670765 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10859 10:53:13.687887 <30>[ 19.717999] systemd[1]: Starting Coldplug All udev Devices...
10860 10:53:13.694406 Starting [0;1;39mColdplug All udev Devices[0m...
10861 10:53:13.712439 <30>[ 19.742283] systemd[1]: Mounted Huge Pages File System.
10862 10:53:13.719426 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10863 10:53:13.733963 <30>[ 19.763691] systemd[1]: Mounted POSIX Message Queue File System.
10864 10:53:13.740266 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10865 10:53:13.758323 <30>[ 19.787468] systemd[1]: Mounted Kernel Debug File System.
10866 10:53:13.771516 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 19.797702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 10:53:13.771616 m.
10868 10:53:13.794073 <30>[ 19.820151] systemd[1]: Finished Create list of static device nodes for the current kernel.
10869 10:53:13.803887 <3>[ 19.828452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 10:53:13.810403 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10871 10:53:13.826698 <30>[ 19.856409] systemd[1]: modprobe@configfs.service: Succeeded.
10872 10:53:13.833181 <30>[ 19.863121] systemd[1]: Finished Load Kernel Module configfs.
10873 10:53:13.840800 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10874 10:53:13.850585 <3>[ 19.875686] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 10:53:13.858200 <30>[ 19.888335] systemd[1]: modprobe@drm.service: Succeeded.
10876 10:53:13.865412 <30>[ 19.894582] systemd[1]: Finished Load Kernel Module drm.
10877 10:53:13.878454 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 19.905939] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 10:53:13.878569 .
10879 10:53:13.886663 <30>[ 19.916561] systemd[1]: modprobe@fuse.service: Succeeded.
10880 10:53:13.892935 <30>[ 19.922878] systemd[1]: Finished Load Kernel Module fuse.
10881 10:53:13.900740 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10882 10:53:13.910752 <3>[ 19.935482] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 10:53:13.917592 <30>[ 19.945819] systemd[1]: Finished Load Kernel Modules.
10884 10:53:13.920856 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10885 10:53:13.938599 <3>[ 19.965059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 10:53:13.949064 <30>[ 19.975676] systemd[1]: Finished Remount Root and Kernel File Systems.
10887 10:53:13.955582 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10888 10:53:13.967902 <3>[ 19.994489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 10:53:13.997993 <3>[ 20.024385] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 10:53:14.009571 <30>[ 20.039594] systemd[1]: Mounting FUSE Control File System...
10891 10:53:14.016743 Mounting [0;1;39mFUSE Control File System[0m...
10892 10:53:14.035315 <30>[ 20.061968] systemd[1]: Mounting Kernel Configuration File System...
10893 10:53:14.039289 Mounting [0;1;39mKernel Configuration File System[0m...
10894 10:53:14.063973 <30>[ 20.090894] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10895 10:53:14.074262 <30>[ 20.099878] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10896 10:53:14.082478 <30>[ 20.112399] systemd[1]: Starting Load/Save Random Seed...
10897 10:53:14.089280 Starting [0;1;39mLoad/Save Random Seed[0m...
10898 10:53:14.104260 <30>[ 20.134228] systemd[1]: Starting Apply Kernel Variables...
10899 10:53:14.110864 Starting [0;1;39mApply Kernel Variables[0m...
10900 10:53:14.129053 <30>[ 20.158904] systemd[1]: Starting Create System Users...
10901 10:53:14.135550 Starting [0;1;39mCreate System Users[0m...
10902 10:53:14.151508 <30>[ 20.180896] systemd[1]: Started Journal Service.
10903 10:53:14.154690 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10904 10:53:14.171022 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10905 10:53:14.185662 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10906 10:53:14.209422 <4>[ 20.229130] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10907 10:53:14.218939 <3>[ 20.244951] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10908 10:53:14.222292 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10909 10:53:14.239179 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10910 10:53:14.245764 <4>[ 20.275657] power_supply_show_property: 4 callbacks suppressed
10911 10:53:14.255789 <3>[ 20.275671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 10:53:14.265951 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10913 10:53:14.287912 See 'systemctl status systemd-udev-trigger.service' for details.<3>[ 20.312631] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 10:53:14.288048
10915 10:53:14.307023 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10916 10:53:14.316896 <3>[ 20.342317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 10:53:14.345353 <3>[ 20.372293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 10:53:14.353753 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10919 10:53:14.374721 <3>[ 20.401261] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 10:53:14.383878 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10921 10:53:14.406173 <3>[ 20.432873] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 10:53:14.435637 <3>[ 20.461965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 10:53:14.442057 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10924 10:53:14.464793 <3>[ 20.491015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 10:53:14.470900 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10926 10:53:14.495890 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[<3>[ 20.520463] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 10:53:14.495998 0m.
10928 10:53:14.523213 <3>[ 20.550142] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 10:53:14.552784 Starting [0;1;39mRule-based Manage…for Device Events<46>[ 20.579819] systemd-journald[303]: Received client request to flush runtime journal.
10930 10:53:14.555974 and Files[0m...
10931 10:53:15.926896 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10932 10:53:15.967113 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10933 10:53:15.985277 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10934 10:53:16.014106 Starting [0;1;39mNetwork Service[0m...
10935 10:53:16.323144 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10936 10:53:16.342248 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10937 10:53:16.385636 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10938 10:53:16.595097 <6>[ 22.625298] remoteproc remoteproc0: powering up scp
10939 10:53:16.620819 <4>[ 22.647830] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10940 10:53:16.627690 <3>[ 22.657733] remoteproc remoteproc0: request_firmware failed: -2
10941 10:53:16.637222 <3>[ 22.663925] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10942 10:53:16.721368 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10943 10:53:16.752624 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10944 10:53:16.777457 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10945 10:53:16.806676 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10946 10:53:16.824300 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10947 10:53:16.869632 Starting [0;1;39mNetwork Name Resolution[0m...
10948 10:53:16.891629 Starting [0;1;39mNetwork Time Synchronization[0m...
10949 10:53:16.907891 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10950 10:53:16.949607 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10951 10:53:16.979185 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10952 10:53:16.993937 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10953 10:53:17.141276 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10954 10:53:17.158070 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10955 10:53:17.176613 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10956 10:53:17.189235 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10957 10:53:17.205329 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10958 10:53:17.324743 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10959 10:53:17.367861 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10960 10:53:17.386296 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10961 10:53:17.408949 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10962 10:53:17.424755 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10963 10:53:17.448896 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10964 10:53:17.461124 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10965 10:53:17.477579 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 10:53:17.509305 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10967 10:53:17.544243 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10968 10:53:17.578884 Starting [0;1;39mUser Login Management[0m...
10969 10:53:17.598143 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10970 10:53:17.613585 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10971 10:53:17.632411 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10972 10:53:17.673719 Starting [0;1;39mPermit User Sessions[0m...
10973 10:53:17.797739 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10974 10:53:17.841985 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10975 10:53:17.859836 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10976 10:53:17.876857 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10977 10:53:17.901698 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10978 10:53:17.922945 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10979 10:53:17.938118 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10980 10:53:17.953248 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10981 10:53:17.997245 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10982 10:53:18.029762 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10983 10:53:18.080060
10984 10:53:18.080201
10985 10:53:18.083224 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10986 10:53:18.083309
10987 10:53:18.086455 debian-bullseye-arm64 login: root (automatic login)
10988 10:53:18.086538
10989 10:53:18.086603
10990 10:53:18.382863 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
10991 10:53:18.383022
10992 10:53:18.389534 The programs included with the Debian GNU/Linux system are free software;
10993 10:53:18.396235 the exact distribution terms for each program are described in the
10994 10:53:18.399996 individual files in /usr/share/doc/*/copyright.
10995 10:53:18.400093
10996 10:53:18.406472 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10997 10:53:18.406555 permitted by applicable law.
10998 10:53:19.146432 Matched prompt #10: / #
11000 10:53:19.146838 Setting prompt string to ['/ #']
11001 10:53:19.146984 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11003 10:53:19.147294 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11004 10:53:19.147494 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
11005 10:53:19.147574 Setting prompt string to ['/ #']
11006 10:53:19.147656 Forcing a shell prompt, looking for ['/ #']
11008 10:53:19.197907 / #
11009 10:53:19.198074 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11010 10:53:19.198187 Waiting using forced prompt support (timeout 00:02:30)
11011 10:53:19.202869
11012 10:53:19.203180 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11013 10:53:19.203304 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
11015 10:53:19.303674 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c'
11016 10:53:19.309260 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590982/extract-nfsrootfs-bh4nmb7c'
11018 10:53:19.409795 / # export NFS_SERVER_IP='192.168.201.1'
11019 10:53:19.414163 export NFS_SERVER_IP='192.168.201.1'
11020 10:53:19.414481 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11021 10:53:19.414620 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11022 10:53:19.414749 end: 2 depthcharge-action (duration 00:01:33) [common]
11023 10:53:19.414879 start: 3 lava-test-retry (timeout 00:07:43) [common]
11024 10:53:19.415003 start: 3.1 lava-test-shell (timeout 00:07:43) [common]
11025 10:53:19.415112 Using namespace: common
11027 10:53:19.515488 / # #
11028 10:53:19.515675 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11029 10:53:19.520640 #
11030 10:53:19.520938 Using /lava-10590982
11032 10:53:19.621290 / # export SHELL=/bin/bash
11033 10:53:19.626448 export SHELL=/bin/bash
11035 10:53:19.726990 / # . /lava-10590982/environment
11036 10:53:19.731866 . /lava-10590982/environment
11038 10:53:19.836700 / # /lava-10590982/bin/lava-test-runner /lava-10590982/0
11039 10:53:19.836833 Test shell timeout: 10s (minimum of the action and connection timeout)
11040 10:53:19.842142 /lava-10590982/bin/lava-test-runner /lava-10590982/0
11041 10:53:20.048727 + export TESTRUN_ID=0_timesync-off
11042 10:53:20.051982 + TESTRUN_ID=0_timesync-off
11043 10:53:20.055181 + cd /lava-10590982/0/tests/0_timesync-off
11044 10:53:20.058468 ++ cat uuid
11045 10:53:20.058551 + UUID=10590982_1.6.2.3.1
11046 10:53:20.061752 + set +x
11047 10:53:20.065061 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10590982_1.6.2.3.1>
11048 10:53:20.065365 Received signal: <STARTRUN> 0_timesync-off 10590982_1.6.2.3.1
11049 10:53:20.065439 Starting test lava.0_timesync-off (10590982_1.6.2.3.1)
11050 10:53:20.065527 Skipping test definition patterns.
11051 10:53:20.068695 + systemctl stop systemd-timesyncd
11052 10:53:20.088858 + set +x
11053 10:53:20.092154 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10590982_1.6.2.3.1>
11054 10:53:20.092428 Received signal: <ENDRUN> 0_timesync-off 10590982_1.6.2.3.1
11055 10:53:20.092518 Ending use of test pattern.
11056 10:53:20.092581 Ending test lava.0_timesync-off (10590982_1.6.2.3.1), duration 0.03
11058 10:53:20.130147 + export TESTRUN_ID=1_kselftest-rtc
11059 10:53:20.133590 + TESTRUN_ID=1_kselftest-rtc
11060 10:53:20.136547 + cd /lava-10590982/0/tests/1_kselftest-rtc
11061 10:53:20.140311 ++ cat uuid
11062 10:53:20.140391 + UUID=10590982_1.6.2.3.5
11063 10:53:20.143482 + set +x
11064 10:53:20.146713 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10590982_1.6.2.3.5>
11065 10:53:20.146966 Received signal: <STARTRUN> 1_kselftest-rtc 10590982_1.6.2.3.5
11066 10:53:20.147037 Starting test lava.1_kselftest-rtc (10590982_1.6.2.3.5)
11067 10:53:20.147117 Skipping test definition patterns.
11068 10:53:20.150503 + cd ./automated/linux/kselftest/
11069 10:53:20.179963 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11070 10:53:20.183059 INFO: install_deps skipped
11071 10:53:20.277821 --2023-06-05 10:53:08-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11072 10:53:20.284385 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11073 10:53:20.420103 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11074 10:53:20.570334 HTTP request sent, awaiting response... 200 OK
11075 10:53:20.573971 Length: 2712696 (2.6M) [application/octet-stream]
11076 10:53:20.581776 Saving to: 'kselftest.tar.xz'
11077 10:53:20.581861
11078 10:53:20.581932
11079 10:53:20.868572 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11080 10:53:21.157977 kselftest.tar.xz 1%[ ] 49.22K 168KB/s
11081 10:53:21.489040 kselftest.tar.xz 8%[> ] 217.50K 369KB/s
11082 10:53:21.738141 kselftest.tar.xz 31%[=====> ] 822.71K 887KB/s
11083 10:53:21.897058 kselftest.tar.xz 72%[=============> ] 1.87M 1.58MB/s
11084 10:53:21.902801 kselftest.tar.xz 100%[===================>] 2.59M 1.93MB/s in 1.3s
11085 10:53:21.902909
11086 10:53:22.137219 2023-06-05 10:53:10 (1.93 MB/s) - 'kselftest.tar.xz' saved [2712696/2712696]
11087 10:53:22.137385
11088 10:53:26.387945 skiplist:
11089 10:53:26.390964 ========================================
11090 10:53:26.394019 ========================================
11091 10:53:26.424011 rtc:rtctest
11092 10:53:26.438011 ============== Tests to run ===============
11093 10:53:26.438105 rtc:rtctest
11094 10:53:26.441156 ===========End Tests to run ===============
11095 10:53:26.512814 <12>[ 32.543910] kselftest: Running tests in rtc
11096 10:53:26.520012 TAP version 13
11097 10:53:26.531084 1..1
11098 10:53:26.554343 # selftests: rtc: rtctest
11099 10:53:26.893365 # TAP version 13
11100 10:53:26.893511 # 1..8
11101 10:53:26.897067 # # Starting 8 tests from 2 test cases.
11102 10:53:26.900236 # # RUN rtc.date_read ...
11103 10:53:26.906432 # # rtctest.c:49:date_read:Current RTC date/time is 05/06/2023 10:53:14.
11104 10:53:26.910111 # # OK rtc.date_read
11105 10:53:26.913045 # ok 1 rtc.date_read
11106 10:53:26.916734 # # RUN rtc.date_read_loop ...
11107 10:53:26.926331 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11108 10:53:39.892010 <6>[ 45.927804] vpu: disabling
11109 10:53:39.895174 <6>[ 45.930855] vproc2: disabling
11110 10:53:39.898113 <6>[ 45.934138] vproc1: disabling
11111 10:53:39.901647 <6>[ 45.937505] vaud18: disabling
11112 10:53:39.907946 <6>[ 45.940925] vsram_others: disabling
11113 10:53:39.911113 <6>[ 45.944808] va09: disabling
11114 10:53:39.914857 <6>[ 45.947922] vsram_md: disabling
11115 10:53:39.918023 <6>[ 45.951411] Vgpu: disabling
11116 10:53:57.085389 # # rtctest.c:115:date_read_loop:Performed 2697 RTC time reads.
11117 10:53:57.088468 # # OK rtc.date_read_loop
11118 10:53:57.092073 # ok 2 rtc.date_read_loop
11119 10:53:57.095124 # # RUN rtc.uie_read ...
11120 10:54:00.066332 # # OK rtc.uie_read
11121 10:54:00.070237 # ok 3 rtc.uie_read
11122 10:54:00.073360 # # RUN rtc.uie_select ...
11123 10:54:03.066403 # # OK rtc.uie_select
11124 10:54:03.069332 # ok 4 rtc.uie_select
11125 10:54:03.072421 # # RUN rtc.alarm_alm_set ...
11126 10:54:03.079477 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 10:53:54.
11127 10:54:03.082518 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11128 10:54:03.089451 # # alarm_alm_set: Test terminated by assertion
11129 10:54:03.092333 # # FAIL rtc.alarm_alm_set
11130 10:54:03.092421 # not ok 5 rtc.alarm_alm_set
11131 10:54:03.098993 # # RUN rtc.alarm_wkalm_set ...
11132 10:54:03.105919 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 05/06/2023 10:53:54.
11133 10:54:06.068949 # # OK rtc.alarm_wkalm_set
11134 10:54:06.069082 # ok 6 rtc.alarm_wkalm_set
11135 10:54:06.075553 # # RUN rtc.alarm_alm_set_minute ...
11136 10:54:06.078618 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 10:54:00.
11137 10:54:06.085310 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11138 10:54:06.091963 # # alarm_alm_set_minute: Test terminated by assertion
11139 10:54:06.095755 # # FAIL rtc.alarm_alm_set_minute
11140 10:54:06.098615 # not ok 7 rtc.alarm_alm_set_minute
11141 10:54:06.101705 # # RUN rtc.alarm_wkalm_set_minute ...
11142 10:54:06.108729 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 05/06/2023 10:54:00.
11143 10:54:12.068244 # # OK rtc.alarm_wkalm_set_minute
11144 10:54:12.071312 # ok 8 rtc.alarm_wkalm_set_minute
11145 10:54:12.074850 # # FAILED: 6 / 8 tests passed.
11146 10:54:12.077890 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11147 10:54:12.081103 not ok 1 selftests: rtc: rtctest # exit=1
11148 10:54:12.569964 rtc_rtctest_rtc_date_read pass
11149 10:54:12.573558 rtc_rtctest_rtc_date_read_loop pass
11150 10:54:12.576577 rtc_rtctest_rtc_uie_read pass
11151 10:54:12.579884 rtc_rtctest_rtc_uie_select pass
11152 10:54:12.583343 rtc_rtctest_rtc_alarm_alm_set fail
11153 10:54:12.586502 rtc_rtctest_rtc_alarm_wkalm_set pass
11154 10:54:12.589701 rtc_rtctest_rtc_alarm_alm_set_minute fail
11155 10:54:12.593029 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11156 10:54:12.596528 rtc_rtctest fail
11157 10:54:12.599712 + ../../utils/send-to-lava.sh ./output/result.txt
11158 10:54:12.639846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11159 10:54:12.640176 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11161 10:54:12.676826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11162 10:54:12.677174 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11164 10:54:12.712079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11165 10:54:12.712394 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11167 10:54:12.745088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11168 10:54:12.745401 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11170 10:54:12.785046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11171 10:54:12.785353 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11173 10:54:12.817202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11174 10:54:12.817499 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11176 10:54:12.857224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11177 10:54:12.857528 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11179 10:54:12.890201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11180 10:54:12.890530 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11182 10:54:12.918816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11183 10:54:12.918949 + set +x
11184 10:54:12.919195 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11186 10:54:12.925475 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10590982_1.6.2.3.5>
11187 10:54:12.925582 <LAVA_TEST_RUNNER EXIT>
11188 10:54:12.925849 Received signal: <ENDRUN> 1_kselftest-rtc 10590982_1.6.2.3.5
11189 10:54:12.925925 Ending use of test pattern.
11190 10:54:12.925987 Ending test lava.1_kselftest-rtc (10590982_1.6.2.3.5), duration 52.78
11192 10:54:12.926210 ok: lava_test_shell seems to have completed
11193 10:54:12.926340 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11194 10:54:12.926437 end: 3.1 lava-test-shell (duration 00:00:54) [common]
11195 10:54:12.926532 end: 3 lava-test-retry (duration 00:00:54) [common]
11196 10:54:12.926621 start: 4 finalize (timeout 00:06:49) [common]
11197 10:54:12.926713 start: 4.1 power-off (timeout 00:00:30) [common]
11198 10:54:12.926866 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11199 10:54:13.004413 >> Command sent successfully.
11200 10:54:13.006734 Returned 0 in 0 seconds
11201 10:54:13.107105 end: 4.1 power-off (duration 00:00:00) [common]
11203 10:54:13.107486 start: 4.2 read-feedback (timeout 00:06:49) [common]
11204 10:54:13.107750 Listened to connection for namespace 'common' for up to 1s
11205 10:54:13.108027 Listened to connection for namespace 'common' for up to 1s
11206 10:54:14.108660 Finalising connection for namespace 'common'
11207 10:54:14.108851 Disconnecting from shell: Finalise
11208 10:54:14.108963 / #
11209 10:54:14.209284 end: 4.2 read-feedback (duration 00:00:01) [common]
11210 10:54:14.209493 end: 4 finalize (duration 00:00:01) [common]
11211 10:54:14.209667 Cleaning after the job
11212 10:54:14.209794 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/ramdisk
11213 10:54:14.212140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/kernel
11214 10:54:14.221088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/dtb
11215 10:54:14.221290 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/nfsrootfs
11216 10:54:14.286736 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590982/tftp-deploy-jn_vmrpw/modules
11217 10:54:14.292082 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10590982
11218 10:54:14.817059 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10590982
11219 10:54:14.817231 Job finished correctly