Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 10:50:35.427701 lava-dispatcher, installed at version: 2023.05.1
2 10:50:35.427902 start: 0 validate
3 10:50:35.428042 Start time: 2023-06-05 10:50:35.428023+00:00 (UTC)
4 10:50:35.428198 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:50:35.428326 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:50:35.725558 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:50:35.725785 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:50:36.013953 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:50:36.014156 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:51:15.617674 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:51:15.618404 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:51:16.197873 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:51:16.198556 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:51:16.500331 validate duration: 41.07
16 10:51:16.501624 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:51:16.502158 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:51:16.502664 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:51:16.503290 Not decompressing ramdisk as can be used compressed.
20 10:51:16.503751 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 10:51:16.504132 saving as /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/ramdisk/initrd.cpio.gz
22 10:51:16.504473 total size: 4665273 (4MB)
23 10:51:19.288420 progress 0% (0MB)
24 10:51:19.289748 progress 5% (0MB)
25 10:51:19.290975 progress 10% (0MB)
26 10:51:19.292214 progress 15% (0MB)
27 10:51:19.293420 progress 20% (0MB)
28 10:51:19.294622 progress 25% (1MB)
29 10:51:19.295828 progress 30% (1MB)
30 10:51:19.297056 progress 35% (1MB)
31 10:51:19.298236 progress 40% (1MB)
32 10:51:19.299567 progress 45% (2MB)
33 10:51:19.300780 progress 50% (2MB)
34 10:51:19.301970 progress 55% (2MB)
35 10:51:19.303155 progress 60% (2MB)
36 10:51:19.304341 progress 65% (2MB)
37 10:51:19.305520 progress 70% (3MB)
38 10:51:19.306723 progress 75% (3MB)
39 10:51:19.307910 progress 80% (3MB)
40 10:51:19.309283 progress 85% (3MB)
41 10:51:19.310460 progress 90% (4MB)
42 10:51:19.311635 progress 95% (4MB)
43 10:51:19.312839 progress 100% (4MB)
44 10:51:19.312984 4MB downloaded in 2.81s (1.58MB/s)
45 10:51:19.313126 end: 1.1.1 http-download (duration 00:00:03) [common]
47 10:51:19.313361 end: 1.1 download-retry (duration 00:00:03) [common]
48 10:51:19.313447 start: 1.2 download-retry (timeout 00:09:57) [common]
49 10:51:19.313530 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 10:51:19.313657 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:51:19.313726 saving as /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/kernel/Image
52 10:51:19.313786 total size: 45746688 (43MB)
53 10:51:19.313844 No compression specified
54 10:51:19.601782 progress 0% (0MB)
55 10:51:19.645718 progress 5% (2MB)
56 10:51:19.662938 progress 10% (4MB)
57 10:51:19.675384 progress 15% (6MB)
58 10:51:19.686717 progress 20% (8MB)
59 10:51:19.698240 progress 25% (10MB)
60 10:51:19.709395 progress 30% (13MB)
61 10:51:19.720681 progress 35% (15MB)
62 10:51:19.731961 progress 40% (17MB)
63 10:51:19.743333 progress 45% (19MB)
64 10:51:19.754758 progress 50% (21MB)
65 10:51:19.765993 progress 55% (24MB)
66 10:51:19.777373 progress 60% (26MB)
67 10:51:19.788730 progress 65% (28MB)
68 10:51:19.800090 progress 70% (30MB)
69 10:51:19.811343 progress 75% (32MB)
70 10:51:19.822451 progress 80% (34MB)
71 10:51:19.833771 progress 85% (37MB)
72 10:51:19.845145 progress 90% (39MB)
73 10:51:19.856350 progress 95% (41MB)
74 10:51:19.867420 progress 100% (43MB)
75 10:51:19.867536 43MB downloaded in 0.55s (78.79MB/s)
76 10:51:19.867683 end: 1.2.1 http-download (duration 00:00:01) [common]
78 10:51:19.867911 end: 1.2 download-retry (duration 00:00:01) [common]
79 10:51:19.867997 start: 1.3 download-retry (timeout 00:09:57) [common]
80 10:51:19.868095 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 10:51:19.868225 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:51:19.868295 saving as /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/dtb/mt8192-asurada-spherion-r0.dtb
83 10:51:19.868357 total size: 46924 (0MB)
84 10:51:19.868416 No compression specified
85 10:51:19.869528 progress 69% (0MB)
86 10:51:19.869795 progress 100% (0MB)
87 10:51:19.869945 0MB downloaded in 0.00s (28.20MB/s)
88 10:51:19.870064 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:51:19.870280 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:51:19.870364 start: 1.4 download-retry (timeout 00:09:57) [common]
92 10:51:19.870445 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 10:51:19.870554 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 10:51:19.870622 saving as /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/nfsrootfs/full.rootfs.tar
95 10:51:19.870681 total size: 89386020 (85MB)
96 10:51:19.870740 Using unxz to decompress xz
97 10:51:19.874429 progress 0% (0MB)
98 10:51:20.079631 progress 5% (4MB)
99 10:51:20.290945 progress 10% (8MB)
100 10:51:20.536378 progress 15% (12MB)
101 10:51:20.726284 progress 20% (17MB)
102 10:51:20.819473 progress 25% (21MB)
103 10:51:21.062927 progress 30% (25MB)
104 10:51:21.408514 progress 35% (29MB)
105 10:51:21.665323 progress 40% (34MB)
106 10:51:21.917906 progress 45% (38MB)
107 10:51:22.159986 progress 50% (42MB)
108 10:51:22.416095 progress 55% (46MB)
109 10:51:22.660575 progress 60% (51MB)
110 10:51:22.921677 progress 65% (55MB)
111 10:51:23.212454 progress 70% (59MB)
112 10:51:23.502968 progress 75% (63MB)
113 10:51:23.790233 progress 80% (68MB)
114 10:51:24.035729 progress 85% (72MB)
115 10:51:24.258455 progress 90% (76MB)
116 10:51:24.510116 progress 95% (81MB)
117 10:51:24.764984 progress 100% (85MB)
118 10:51:24.771076 85MB downloaded in 4.90s (17.40MB/s)
119 10:51:24.771346 end: 1.4.1 http-download (duration 00:00:05) [common]
121 10:51:24.771606 end: 1.4 download-retry (duration 00:00:05) [common]
122 10:51:24.771698 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:51:24.771786 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:51:24.771934 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:51:24.772006 saving as /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/modules/modules.tar
126 10:51:24.772107 total size: 8542412 (8MB)
127 10:51:24.772171 Using unxz to decompress xz
128 10:51:24.775359 progress 0% (0MB)
129 10:51:24.796370 progress 5% (0MB)
130 10:51:24.820575 progress 10% (0MB)
131 10:51:24.846053 progress 15% (1MB)
132 10:51:24.870293 progress 20% (1MB)
133 10:51:24.895292 progress 25% (2MB)
134 10:51:24.919488 progress 30% (2MB)
135 10:51:24.944050 progress 35% (2MB)
136 10:51:24.968398 progress 40% (3MB)
137 10:51:24.992963 progress 45% (3MB)
138 10:51:25.016103 progress 50% (4MB)
139 10:51:25.038292 progress 55% (4MB)
140 10:51:25.062979 progress 60% (4MB)
141 10:51:25.087454 progress 65% (5MB)
142 10:51:25.111918 progress 70% (5MB)
143 10:51:25.137886 progress 75% (6MB)
144 10:51:25.166475 progress 80% (6MB)
145 10:51:25.188505 progress 85% (6MB)
146 10:51:25.212923 progress 90% (7MB)
147 10:51:25.235631 progress 95% (7MB)
148 10:51:25.258831 progress 100% (8MB)
149 10:51:25.264422 8MB downloaded in 0.49s (16.55MB/s)
150 10:51:25.264680 end: 1.5.1 http-download (duration 00:00:00) [common]
152 10:51:25.264960 end: 1.5 download-retry (duration 00:00:00) [common]
153 10:51:25.265055 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:51:25.265151 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:51:26.842435 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59
156 10:51:26.842635 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 10:51:26.842753 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 10:51:26.842928 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka
159 10:51:26.843055 makedir: /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin
160 10:51:26.843154 makedir: /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/tests
161 10:51:26.843250 makedir: /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/results
162 10:51:26.843350 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-add-keys
163 10:51:26.843487 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-add-sources
164 10:51:26.843611 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-background-process-start
165 10:51:26.843732 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-background-process-stop
166 10:51:26.843850 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-common-functions
167 10:51:26.843970 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-echo-ipv4
168 10:51:26.844129 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-install-packages
169 10:51:26.844245 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-installed-packages
170 10:51:26.844361 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-os-build
171 10:51:26.844478 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-probe-channel
172 10:51:26.844602 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-probe-ip
173 10:51:26.844718 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-target-ip
174 10:51:26.844837 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-target-mac
175 10:51:26.844958 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-target-storage
176 10:51:26.845081 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-case
177 10:51:26.845199 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-event
178 10:51:26.845315 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-feedback
179 10:51:26.845432 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-raise
180 10:51:26.845548 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-reference
181 10:51:26.845666 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-runner
182 10:51:26.845783 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-set
183 10:51:26.845899 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-test-shell
184 10:51:26.846016 Updating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-install-packages (oe)
185 10:51:26.846165 Updating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/bin/lava-installed-packages (oe)
186 10:51:26.846281 Creating /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/environment
187 10:51:26.846383 LAVA metadata
188 10:51:26.846452 - LAVA_JOB_ID=10590978
189 10:51:26.846514 - LAVA_DISPATCHER_IP=192.168.201.1
190 10:51:26.846611 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 10:51:26.846678 skipped lava-vland-overlay
192 10:51:26.846751 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 10:51:26.846828 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 10:51:26.846887 skipped lava-multinode-overlay
195 10:51:26.846958 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 10:51:26.847034 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 10:51:26.847105 Loading test definitions
198 10:51:26.847194 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 10:51:26.847264 Using /lava-10590978 at stage 0
200 10:51:26.847547 uuid=10590978_1.6.2.3.1 testdef=None
201 10:51:26.847635 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 10:51:26.847719 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 10:51:26.848333 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 10:51:26.848554 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 10:51:26.849164 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 10:51:26.849391 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 10:51:26.849971 runner path: /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/0/tests/0_lc-compliance test_uuid 10590978_1.6.2.3.1
210 10:51:26.850123 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 10:51:26.850324 Creating lava-test-runner.conf files
213 10:51:26.850385 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10590978/lava-overlay-ouvp8gka/lava-10590978/0 for stage 0
214 10:51:26.850470 - 0_lc-compliance
215 10:51:26.850563 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 10:51:26.850645 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
217 10:51:26.856472 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 10:51:26.856574 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
219 10:51:26.856659 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 10:51:26.856741 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 10:51:26.856824 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
222 10:51:26.971046 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 10:51:26.971418 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 10:51:26.971535 extracting modules file /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59
225 10:51:27.170223 extracting modules file /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590978/extract-overlay-ramdisk-gnyr5mg4/ramdisk
226 10:51:27.375765 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 10:51:27.375937 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
228 10:51:27.376035 [common] Applying overlay to NFS
229 10:51:27.376114 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590978/compress-overlay-c6tgefzx/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59
230 10:51:27.382349 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 10:51:27.382461 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
232 10:51:27.382552 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 10:51:27.382641 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
234 10:51:27.382721 Building ramdisk /var/lib/lava/dispatcher/tmp/10590978/extract-overlay-ramdisk-gnyr5mg4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10590978/extract-overlay-ramdisk-gnyr5mg4/ramdisk
235 10:51:27.648293 >> 117801 blocks
236 10:51:29.522515 rename /var/lib/lava/dispatcher/tmp/10590978/extract-overlay-ramdisk-gnyr5mg4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/ramdisk/ramdisk.cpio.gz
237 10:51:29.522940 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 10:51:29.523064 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
239 10:51:29.523163 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
240 10:51:29.523267 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/kernel/Image'
241 10:51:40.644363 Returned 0 in 11 seconds
242 10:51:40.745435 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/kernel/image.itb
243 10:51:41.105260 output: FIT description: Kernel Image image with one or more FDT blobs
244 10:51:41.105622 output: Created: Mon Jun 5 11:51:41 2023
245 10:51:41.105701 output: Image 0 (kernel-1)
246 10:51:41.105818 output: Description:
247 10:51:41.105927 output: Created: Mon Jun 5 11:51:41 2023
248 10:51:41.106067 output: Type: Kernel Image
249 10:51:41.106162 output: Compression: lzma compressed
250 10:51:41.106253 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
251 10:51:41.106315 output: Architecture: AArch64
252 10:51:41.106374 output: OS: Linux
253 10:51:41.106432 output: Load Address: 0x00000000
254 10:51:41.106491 output: Entry Point: 0x00000000
255 10:51:41.106550 output: Hash algo: crc32
256 10:51:41.106604 output: Hash value: 8ce42972
257 10:51:41.106659 output: Image 1 (fdt-1)
258 10:51:41.106713 output: Description: mt8192-asurada-spherion-r0
259 10:51:41.106766 output: Created: Mon Jun 5 11:51:41 2023
260 10:51:41.106821 output: Type: Flat Device Tree
261 10:51:41.106875 output: Compression: uncompressed
262 10:51:41.106930 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 10:51:41.106985 output: Architecture: AArch64
264 10:51:41.107039 output: Hash algo: crc32
265 10:51:41.107093 output: Hash value: 1df858fa
266 10:51:41.107146 output: Image 2 (ramdisk-1)
267 10:51:41.107199 output: Description: unavailable
268 10:51:41.107253 output: Created: Mon Jun 5 11:51:41 2023
269 10:51:41.107307 output: Type: RAMDisk Image
270 10:51:41.107360 output: Compression: Unknown Compression
271 10:51:41.107413 output: Data Size: 17638877 Bytes = 17225.47 KiB = 16.82 MiB
272 10:51:41.107467 output: Architecture: AArch64
273 10:51:41.107520 output: OS: Linux
274 10:51:41.107577 output: Load Address: unavailable
275 10:51:41.107631 output: Entry Point: unavailable
276 10:51:41.107684 output: Hash algo: crc32
277 10:51:41.107737 output: Hash value: a5e7dc8e
278 10:51:41.107798 output: Default Configuration: 'conf-1'
279 10:51:41.107871 output: Configuration 0 (conf-1)
280 10:51:41.107924 output: Description: mt8192-asurada-spherion-r0
281 10:51:41.107977 output: Kernel: kernel-1
282 10:51:41.108034 output: Init Ramdisk: ramdisk-1
283 10:51:41.108138 output: FDT: fdt-1
284 10:51:41.108190 output: Loadables: kernel-1
285 10:51:41.108243 output:
286 10:51:41.108433 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 10:51:41.108530 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 10:51:41.108631 end: 1.6 prepare-tftp-overlay (duration 00:00:16) [common]
289 10:51:41.108724 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 10:51:41.108803 No LXC device requested
291 10:51:41.108883 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 10:51:41.108969 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 10:51:41.109050 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 10:51:41.109120 Checking files for TFTP limit of 4294967296 bytes.
295 10:51:41.109594 end: 1 tftp-deploy (duration 00:00:25) [common]
296 10:51:41.109695 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 10:51:41.109788 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 10:51:41.109938 substitutions:
299 10:51:41.110006 - {DTB}: 10590978/tftp-deploy-55rc5d5u/dtb/mt8192-asurada-spherion-r0.dtb
300 10:51:41.110082 - {INITRD}: 10590978/tftp-deploy-55rc5d5u/ramdisk/ramdisk.cpio.gz
301 10:51:41.110141 - {KERNEL}: 10590978/tftp-deploy-55rc5d5u/kernel/Image
302 10:51:41.110198 - {LAVA_MAC}: None
303 10:51:41.110254 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59
304 10:51:41.110310 - {NFS_SERVER_IP}: 192.168.201.1
305 10:51:41.110364 - {PRESEED_CONFIG}: None
306 10:51:41.110418 - {PRESEED_LOCAL}: None
307 10:51:41.110472 - {RAMDISK}: 10590978/tftp-deploy-55rc5d5u/ramdisk/ramdisk.cpio.gz
308 10:51:41.110525 - {ROOT_PART}: None
309 10:51:41.110579 - {ROOT}: None
310 10:51:41.110632 - {SERVER_IP}: 192.168.201.1
311 10:51:41.110684 - {TEE}: None
312 10:51:41.110738 Parsed boot commands:
313 10:51:41.110791 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 10:51:41.110959 Parsed boot commands: tftpboot 192.168.201.1 10590978/tftp-deploy-55rc5d5u/kernel/image.itb 10590978/tftp-deploy-55rc5d5u/kernel/cmdline
315 10:51:41.111046 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 10:51:41.111134 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 10:51:41.111226 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 10:51:41.111312 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 10:51:41.111382 Not connected, no need to disconnect.
320 10:51:41.111456 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 10:51:41.111533 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 10:51:41.111600 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
323 10:51:41.114842 Setting prompt string to ['lava-test: # ']
324 10:51:41.115173 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 10:51:41.115275 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 10:51:41.115374 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 10:51:41.115465 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 10:51:41.115654 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
329 10:51:46.267007 >> Command sent successfully.
330 10:51:46.276954 Returned 0 in 5 seconds
331 10:51:46.378173 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 10:51:46.379763 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 10:51:46.380454 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 10:51:46.380973 Setting prompt string to 'Starting depthcharge on Spherion...'
336 10:51:46.381435 Changing prompt to 'Starting depthcharge on Spherion...'
337 10:51:46.381856 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 10:51:46.383194 [Enter `^Ec?' for help]
339 10:51:46.542555
340 10:51:46.543131
341 10:51:46.543519 F0: 102B 0000
342 10:51:46.543882
343 10:51:46.544281 F3: 1001 0000 [0200]
344 10:51:46.545610
345 10:51:46.546140 F3: 1001 0000
346 10:51:46.546528
347 10:51:46.546883 F7: 102D 0000
348 10:51:46.547225
349 10:51:46.548962 F1: 0000 0000
350 10:51:46.549436
351 10:51:46.549813 V0: 0000 0000 [0001]
352 10:51:46.550171
353 10:51:46.552515 00: 0007 8000
354 10:51:46.552968
355 10:51:46.553310 01: 0000 0000
356 10:51:46.553641
357 10:51:46.555501 BP: 0C00 0209 [0000]
358 10:51:46.555928
359 10:51:46.556317 G0: 1182 0000
360 10:51:46.556643
361 10:51:46.559760 EC: 0000 0021 [4000]
362 10:51:46.560330
363 10:51:46.560677 S7: 0000 0000 [0000]
364 10:51:46.560997
365 10:51:46.562337 CC: 0000 0000 [0001]
366 10:51:46.562765
367 10:51:46.563106 T0: 0000 0040 [010F]
368 10:51:46.563429
369 10:51:46.563738 Jump to BL
370 10:51:46.565654
371 10:51:46.589254
372 10:51:46.589809
373 10:51:46.590154
374 10:51:46.596604 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 10:51:46.599491 ARM64: Exception handlers installed.
376 10:51:46.603076 ARM64: Testing exception
377 10:51:46.606368 ARM64: Done test exception
378 10:51:46.613424 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 10:51:46.623811 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 10:51:46.630518 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 10:51:46.640728 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 10:51:46.647048 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 10:51:46.657295 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 10:51:46.667325 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 10:51:46.674347 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 10:51:46.692443 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 10:51:46.695970 WDT: Last reset was cold boot
388 10:51:46.699485 SPI1(PAD0) initialized at 2873684 Hz
389 10:51:46.702285 SPI5(PAD0) initialized at 992727 Hz
390 10:51:46.705529 VBOOT: Loading verstage.
391 10:51:46.712266 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 10:51:46.716168 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 10:51:46.718951 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 10:51:46.722899 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 10:51:46.729667 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 10:51:46.737730 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 10:51:46.747774 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 10:51:46.748421
399 10:51:46.748809
400 10:51:46.757107 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 10:51:46.760582 ARM64: Exception handlers installed.
402 10:51:46.764188 ARM64: Testing exception
403 10:51:46.764768 ARM64: Done test exception
404 10:51:46.771051 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 10:51:46.774091 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 10:51:46.788193 Probing TPM: . done!
407 10:51:46.788770 TPM ready after 0 ms
408 10:51:46.796458 Connected to device vid:did:rid of 1ae0:0028:00
409 10:51:46.802874 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 10:51:46.863067 Initialized TPM device CR50 revision 0
411 10:51:46.872505 tlcl_send_startup: Startup return code is 0
412 10:51:46.873078 TPM: setup succeeded
413 10:51:46.883750 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 10:51:46.893146 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 10:51:46.904726 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 10:51:46.914557 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 10:51:46.918611 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 10:51:46.923107 in-header: 03 07 00 00 08 00 00 00
419 10:51:46.926737 in-data: aa e4 47 04 13 02 00 00
420 10:51:46.930260 Chrome EC: UHEPI supported
421 10:51:46.937355 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 10:51:46.941197 in-header: 03 95 00 00 08 00 00 00
423 10:51:46.945418 in-data: 18 20 20 08 00 00 00 00
424 10:51:46.945944 Phase 1
425 10:51:46.948479 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 10:51:46.953238 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 10:51:46.959947 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 10:51:46.964172 Recovery requested (1009000e)
429 10:51:46.972357 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 10:51:46.977852 tlcl_extend: response is 0
431 10:51:46.987100 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 10:51:46.991902 tlcl_extend: response is 0
433 10:51:46.999028 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 10:51:47.018710 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 10:51:47.025911 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 10:51:47.026490
437 10:51:47.026869
438 10:51:47.035359 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 10:51:47.038904 ARM64: Exception handlers installed.
440 10:51:47.041982 ARM64: Testing exception
441 10:51:47.042555 ARM64: Done test exception
442 10:51:47.064557 pmic_efuse_setting: Set efuses in 11 msecs
443 10:51:47.067357 pmwrap_interface_init: Select PMIF_VLD_RDY
444 10:51:47.074628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 10:51:47.077503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 10:51:47.084712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 10:51:47.088802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 10:51:47.091981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 10:51:47.098607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 10:51:47.102472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 10:51:47.105968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 10:51:47.114264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 10:51:47.116865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 10:51:47.120288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 10:51:47.124028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 10:51:47.131523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 10:51:47.134832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 10:51:47.142237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 10:51:47.149278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 10:51:47.152987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 10:51:47.160573 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 10:51:47.163881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 10:51:47.171186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 10:51:47.176073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 10:51:47.182161 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 10:51:47.186262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 10:51:47.193687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 10:51:47.197516 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 10:51:47.204644 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 10:51:47.207843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 10:51:47.215665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 10:51:47.219109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 10:51:47.222616 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 10:51:47.230132 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 10:51:47.233450 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 10:51:47.236971 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 10:51:47.244801 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 10:51:47.248381 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 10:51:47.251815 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 10:51:47.260353 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 10:51:47.263876 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 10:51:47.267435 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 10:51:47.270569 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 10:51:47.278684 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 10:51:47.281333 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 10:51:47.285228 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 10:51:47.288909 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 10:51:47.292978 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 10:51:47.299693 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 10:51:47.303526 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 10:51:47.307012 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 10:51:47.310772 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 10:51:47.314968 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 10:51:47.318020 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 10:51:47.325632 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 10:51:47.336935 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 10:51:47.339670 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 10:51:47.347663 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 10:51:47.358129 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 10:51:47.361614 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 10:51:47.365370 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 10:51:47.368582 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 10:51:47.377343 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
504 10:51:47.384002 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 10:51:47.387839 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
506 10:51:47.391211 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 10:51:47.401567 [RTC]rtc_get_frequency_meter,154: input=15, output=853
508 10:51:47.411818 [RTC]rtc_get_frequency_meter,154: input=7, output=725
509 10:51:47.420535 [RTC]rtc_get_frequency_meter,154: input=11, output=788
510 10:51:47.430308 [RTC]rtc_get_frequency_meter,154: input=13, output=820
511 10:51:47.439071 [RTC]rtc_get_frequency_meter,154: input=12, output=804
512 10:51:47.449424 [RTC]rtc_get_frequency_meter,154: input=11, output=789
513 10:51:47.458965 [RTC]rtc_get_frequency_meter,154: input=12, output=804
514 10:51:47.462655 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
515 10:51:47.470062 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
516 10:51:47.473966 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 10:51:47.477751 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 10:51:47.481093 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 10:51:47.485331 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 10:51:47.488963 ADC[4]: Raw value=903325 ID=7
521 10:51:47.489581 ADC[3]: Raw value=213916 ID=1
522 10:51:47.492511 RAM Code: 0x71
523 10:51:47.496567 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 10:51:47.499992 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 10:51:47.510487 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 10:51:47.518183 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 10:51:47.518738 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 10:51:47.522802 in-header: 03 07 00 00 08 00 00 00
529 10:51:47.525889 in-data: aa e4 47 04 13 02 00 00
530 10:51:47.529744 Chrome EC: UHEPI supported
531 10:51:47.536599 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 10:51:47.540738 in-header: 03 95 00 00 08 00 00 00
533 10:51:47.544673 in-data: 18 20 20 08 00 00 00 00
534 10:51:47.547974 MRC: failed to locate region type 0.
535 10:51:47.554899 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 10:51:47.555670 DRAM-K: Running full calibration
537 10:51:47.562040 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 10:51:47.565426 header.status = 0x0
539 10:51:47.569108 header.version = 0x6 (expected: 0x6)
540 10:51:47.572666 header.size = 0xd00 (expected: 0xd00)
541 10:51:47.573193 header.flags = 0x0
542 10:51:47.580188 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 10:51:47.597468 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 10:51:47.605071 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 10:51:47.608540 dram_init: ddr_geometry: 2
546 10:51:47.608965 [EMI] MDL number = 2
547 10:51:47.611996 [EMI] Get MDL freq = 0
548 10:51:47.612451 dram_init: ddr_type: 0
549 10:51:47.615726 is_discrete_lpddr4: 1
550 10:51:47.619305 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 10:51:47.619858
552 10:51:47.620274
553 10:51:47.620598 [Bian_co] ETT version 0.0.0.1
554 10:51:47.626875 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 10:51:47.627405
556 10:51:47.630587 dramc_set_vcore_voltage set vcore to 650000
557 10:51:47.631136 Read voltage for 800, 4
558 10:51:47.633849 Vio18 = 0
559 10:51:47.634393 Vcore = 650000
560 10:51:47.634741 Vdram = 0
561 10:51:47.635061 Vddq = 0
562 10:51:47.637645 Vmddr = 0
563 10:51:47.638070 dram_init: config_dvfs: 1
564 10:51:47.645755 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 10:51:47.649164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 10:51:47.652150 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 10:51:47.655865 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 10:51:47.662030 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 10:51:47.666022 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 10:51:47.666602 MEM_TYPE=3, freq_sel=18
571 10:51:47.668669 sv_algorithm_assistance_LP4_1600
572 10:51:47.672560 ============ PULL DRAM RESETB DOWN ============
573 10:51:47.679548 ========== PULL DRAM RESETB DOWN end =========
574 10:51:47.683229 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 10:51:47.687004 ===================================
576 10:51:47.687486 LPDDR4 DRAM CONFIGURATION
577 10:51:47.690155 ===================================
578 10:51:47.694170 EX_ROW_EN[0] = 0x0
579 10:51:47.694739 EX_ROW_EN[1] = 0x0
580 10:51:47.698661 LP4Y_EN = 0x0
581 10:51:47.699163 WORK_FSP = 0x0
582 10:51:47.701029 WL = 0x2
583 10:51:47.703935 RL = 0x2
584 10:51:47.704616 BL = 0x2
585 10:51:47.706973 RPST = 0x0
586 10:51:47.707401 RD_PRE = 0x0
587 10:51:47.710785 WR_PRE = 0x1
588 10:51:47.711212 WR_PST = 0x0
589 10:51:47.713995 DBI_WR = 0x0
590 10:51:47.714523 DBI_RD = 0x0
591 10:51:47.716975 OTF = 0x1
592 10:51:47.720520 ===================================
593 10:51:47.723826 ===================================
594 10:51:47.724279 ANA top config
595 10:51:47.727685 ===================================
596 10:51:47.731005 DLL_ASYNC_EN = 0
597 10:51:47.734084 ALL_SLAVE_EN = 1
598 10:51:47.734617 NEW_RANK_MODE = 1
599 10:51:47.737113 DLL_IDLE_MODE = 1
600 10:51:47.740389 LP45_APHY_COMB_EN = 1
601 10:51:47.743989 TX_ODT_DIS = 1
602 10:51:47.744557 NEW_8X_MODE = 1
603 10:51:47.747399 ===================================
604 10:51:47.750625 ===================================
605 10:51:47.753758 data_rate = 1600
606 10:51:47.757247 CKR = 1
607 10:51:47.760440 DQ_P2S_RATIO = 8
608 10:51:47.763925 ===================================
609 10:51:47.767416 CA_P2S_RATIO = 8
610 10:51:47.771616 DQ_CA_OPEN = 0
611 10:51:47.772178 DQ_SEMI_OPEN = 0
612 10:51:47.775203 CA_SEMI_OPEN = 0
613 10:51:47.778349 CA_FULL_RATE = 0
614 10:51:47.780755 DQ_CKDIV4_EN = 1
615 10:51:47.784558 CA_CKDIV4_EN = 1
616 10:51:47.785083 CA_PREDIV_EN = 0
617 10:51:47.787216 PH8_DLY = 0
618 10:51:47.790766 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 10:51:47.793950 DQ_AAMCK_DIV = 4
620 10:51:47.797320 CA_AAMCK_DIV = 4
621 10:51:47.801391 CA_ADMCK_DIV = 4
622 10:51:47.804321 DQ_TRACK_CA_EN = 0
623 10:51:47.804907 CA_PICK = 800
624 10:51:47.807541 CA_MCKIO = 800
625 10:51:47.810607 MCKIO_SEMI = 0
626 10:51:47.814187 PLL_FREQ = 3068
627 10:51:47.817912 DQ_UI_PI_RATIO = 32
628 10:51:47.818467 CA_UI_PI_RATIO = 0
629 10:51:47.821939 ===================================
630 10:51:47.826273 ===================================
631 10:51:47.829766 memory_type:LPDDR4
632 10:51:47.833557 GP_NUM : 10
633 10:51:47.833985 SRAM_EN : 1
634 10:51:47.836413 MD32_EN : 0
635 10:51:47.836838 ===================================
636 10:51:47.840358 [ANA_INIT] >>>>>>>>>>>>>>
637 10:51:47.843598 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 10:51:47.847711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 10:51:47.851011 ===================================
640 10:51:47.853919 data_rate = 1600,PCW = 0X7600
641 10:51:47.857665 ===================================
642 10:51:47.861236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 10:51:47.864258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 10:51:47.870793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 10:51:47.874523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 10:51:47.877520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 10:51:47.880527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 10:51:47.884621 [ANA_INIT] flow start
649 10:51:47.887033 [ANA_INIT] PLL >>>>>>>>
650 10:51:47.887457 [ANA_INIT] PLL <<<<<<<<
651 10:51:47.890602 [ANA_INIT] MIDPI >>>>>>>>
652 10:51:47.894159 [ANA_INIT] MIDPI <<<<<<<<
653 10:51:47.897101 [ANA_INIT] DLL >>>>>>>>
654 10:51:47.897528 [ANA_INIT] flow end
655 10:51:47.900405 ============ LP4 DIFF to SE enter ============
656 10:51:47.908171 ============ LP4 DIFF to SE exit ============
657 10:51:47.908796 [ANA_INIT] <<<<<<<<<<<<<
658 10:51:47.910307 [Flow] Enable top DCM control >>>>>
659 10:51:47.913657 [Flow] Enable top DCM control <<<<<
660 10:51:47.917366 Enable DLL master slave shuffle
661 10:51:47.923682 ==============================================================
662 10:51:47.924148 Gating Mode config
663 10:51:47.931088 ==============================================================
664 10:51:47.933863 Config description:
665 10:51:47.940418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 10:51:47.947427 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 10:51:47.953962 SELPH_MODE 0: By rank 1: By Phase
668 10:51:47.960736 ==============================================================
669 10:51:47.961272 GAT_TRACK_EN = 1
670 10:51:47.964198 RX_GATING_MODE = 2
671 10:51:47.967599 RX_GATING_TRACK_MODE = 2
672 10:51:47.971141 SELPH_MODE = 1
673 10:51:47.973621 PICG_EARLY_EN = 1
674 10:51:47.977423 VALID_LAT_VALUE = 1
675 10:51:47.983518 ==============================================================
676 10:51:47.986829 Enter into Gating configuration >>>>
677 10:51:47.990851 Exit from Gating configuration <<<<
678 10:51:47.993646 Enter into DVFS_PRE_config >>>>>
679 10:51:48.004323 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 10:51:48.006502 Exit from DVFS_PRE_config <<<<<
681 10:51:48.010225 Enter into PICG configuration >>>>
682 10:51:48.013814 Exit from PICG configuration <<<<
683 10:51:48.016629 [RX_INPUT] configuration >>>>>
684 10:51:48.017181 [RX_INPUT] configuration <<<<<
685 10:51:48.023375 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 10:51:48.030274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 10:51:48.036902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 10:51:48.039772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 10:51:48.046510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 10:51:48.053083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 10:51:48.057480 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 10:51:48.060674 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 10:51:48.066715 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 10:51:48.069948 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 10:51:48.073052 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 10:51:48.079652 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 10:51:48.083528 ===================================
698 10:51:48.084135 LPDDR4 DRAM CONFIGURATION
699 10:51:48.086697 ===================================
700 10:51:48.089857 EX_ROW_EN[0] = 0x0
701 10:51:48.093358 EX_ROW_EN[1] = 0x0
702 10:51:48.093933 LP4Y_EN = 0x0
703 10:51:48.096725 WORK_FSP = 0x0
704 10:51:48.097298 WL = 0x2
705 10:51:48.099964 RL = 0x2
706 10:51:48.100560 BL = 0x2
707 10:51:48.103274 RPST = 0x0
708 10:51:48.103840 RD_PRE = 0x0
709 10:51:48.106165 WR_PRE = 0x1
710 10:51:48.106723 WR_PST = 0x0
711 10:51:48.109490 DBI_WR = 0x0
712 10:51:48.110061 DBI_RD = 0x0
713 10:51:48.112574 OTF = 0x1
714 10:51:48.116199 ===================================
715 10:51:48.119778 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 10:51:48.123206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 10:51:48.129188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 10:51:48.132658 ===================================
719 10:51:48.133085 LPDDR4 DRAM CONFIGURATION
720 10:51:48.136160 ===================================
721 10:51:48.139585 EX_ROW_EN[0] = 0x10
722 10:51:48.140179 EX_ROW_EN[1] = 0x0
723 10:51:48.142794 LP4Y_EN = 0x0
724 10:51:48.146934 WORK_FSP = 0x0
725 10:51:48.147466 WL = 0x2
726 10:51:48.149441 RL = 0x2
727 10:51:48.149971 BL = 0x2
728 10:51:48.152548 RPST = 0x0
729 10:51:48.152974 RD_PRE = 0x0
730 10:51:48.156516 WR_PRE = 0x1
731 10:51:48.157044 WR_PST = 0x0
732 10:51:48.159752 DBI_WR = 0x0
733 10:51:48.160317 DBI_RD = 0x0
734 10:51:48.163469 OTF = 0x1
735 10:51:48.165955 ===================================
736 10:51:48.172680 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 10:51:48.175854 nWR fixed to 40
738 10:51:48.176411 [ModeRegInit_LP4] CH0 RK0
739 10:51:48.179203 [ModeRegInit_LP4] CH0 RK1
740 10:51:48.183024 [ModeRegInit_LP4] CH1 RK0
741 10:51:48.183593 [ModeRegInit_LP4] CH1 RK1
742 10:51:48.186078 match AC timing 13
743 10:51:48.189359 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 10:51:48.192653 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 10:51:48.199110 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 10:51:48.202151 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 10:51:48.209421 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 10:51:48.210070 [EMI DOE] emi_dcm 0
749 10:51:48.215285 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 10:51:48.215758 ==
751 10:51:48.219149 Dram Type= 6, Freq= 0, CH_0, rank 0
752 10:51:48.223053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 10:51:48.223521 ==
754 10:51:48.228796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 10:51:48.231935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 10:51:48.242370 [CA 0] Center 37 (7~68) winsize 62
757 10:51:48.245891 [CA 1] Center 37 (7~68) winsize 62
758 10:51:48.248925 [CA 2] Center 34 (4~65) winsize 62
759 10:51:48.253006 [CA 3] Center 35 (4~66) winsize 63
760 10:51:48.255958 [CA 4] Center 33 (3~64) winsize 62
761 10:51:48.259020 [CA 5] Center 33 (3~64) winsize 62
762 10:51:48.259587
763 10:51:48.262494 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 10:51:48.263067
765 10:51:48.265993 [CATrainingPosCal] consider 1 rank data
766 10:51:48.268951 u2DelayCellTimex100 = 270/100 ps
767 10:51:48.272418 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 10:51:48.279657 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
769 10:51:48.282420 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 10:51:48.285851 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
771 10:51:48.288680 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 10:51:48.292858 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 10:51:48.293432
774 10:51:48.295833 CA PerBit enable=1, Macro0, CA PI delay=33
775 10:51:48.296443
776 10:51:48.299972 [CBTSetCACLKResult] CA Dly = 33
777 10:51:48.300595 CS Dly: 6 (0~37)
778 10:51:48.302831 ==
779 10:51:48.305964 Dram Type= 6, Freq= 0, CH_0, rank 1
780 10:51:48.308989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 10:51:48.309577 ==
782 10:51:48.312122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 10:51:48.319232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 10:51:48.328648 [CA 0] Center 38 (7~69) winsize 63
785 10:51:48.332213 [CA 1] Center 37 (7~68) winsize 62
786 10:51:48.335093 [CA 2] Center 35 (4~66) winsize 63
787 10:51:48.338884 [CA 3] Center 35 (4~66) winsize 63
788 10:51:48.341645 [CA 4] Center 34 (3~65) winsize 63
789 10:51:48.345335 [CA 5] Center 33 (3~64) winsize 62
790 10:51:48.345869
791 10:51:48.348401 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 10:51:48.348827
793 10:51:48.351987 [CATrainingPosCal] consider 2 rank data
794 10:51:48.355596 u2DelayCellTimex100 = 270/100 ps
795 10:51:48.358742 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 10:51:48.365259 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 10:51:48.368623 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 10:51:48.372276 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
799 10:51:48.375413 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 10:51:48.378874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 10:51:48.379448
802 10:51:48.381932 CA PerBit enable=1, Macro0, CA PI delay=33
803 10:51:48.382503
804 10:51:48.385354 [CBTSetCACLKResult] CA Dly = 33
805 10:51:48.389105 CS Dly: 6 (0~38)
806 10:51:48.389680
807 10:51:48.391635 ----->DramcWriteLeveling(PI) begin...
808 10:51:48.392150 ==
809 10:51:48.395395 Dram Type= 6, Freq= 0, CH_0, rank 0
810 10:51:48.399148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:51:48.399622 ==
812 10:51:48.402761 Write leveling (Byte 0): 30 => 30
813 10:51:48.403252 Write leveling (Byte 1): 27 => 27
814 10:51:48.406804 DramcWriteLeveling(PI) end<-----
815 10:51:48.407367
816 10:51:48.407739 ==
817 10:51:48.410837 Dram Type= 6, Freq= 0, CH_0, rank 0
818 10:51:48.413535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 10:51:48.416695 ==
820 10:51:48.417120 [Gating] SW mode calibration
821 10:51:48.424325 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 10:51:48.430827 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 10:51:48.435266 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 10:51:48.437153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 10:51:48.443771 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
826 10:51:48.447734 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:51:48.450634 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:51:48.457366 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 10:51:48.460414 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 10:51:48.464018 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 10:51:48.470707 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 10:51:48.474072 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 10:51:48.477343 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 10:51:48.483886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 10:51:48.487576 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 10:51:48.490450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 10:51:48.497064 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 10:51:48.500204 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 10:51:48.503387 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 10:51:48.510373 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 10:51:48.513330 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 10:51:48.516912 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 10:51:48.523201 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:51:48.528123 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 10:51:48.530906 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 10:51:48.536672 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 10:51:48.540443 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 10:51:48.544084 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 10:51:48.550395 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
850 10:51:48.553244 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
851 10:51:48.556538 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 10:51:48.563455 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 10:51:48.566297 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 10:51:48.570387 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 10:51:48.576642 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 10:51:48.579824 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
857 10:51:48.583207 0 10 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
858 10:51:48.590501 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
859 10:51:48.593211 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:51:48.596609 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:51:48.603065 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:51:48.606748 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:51:48.609796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:51:48.616002 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
865 10:51:48.619711 0 11 8 | B1->B0 | 2828 4040 | 0 0 | (0 0) (0 0)
866 10:51:48.622969 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
867 10:51:48.630187 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 10:51:48.633413 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 10:51:48.636467 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 10:51:48.643289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 10:51:48.646158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 10:51:48.649315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 10:51:48.652796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 10:51:48.659282 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 10:51:48.663912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 10:51:48.665950 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 10:51:48.672347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 10:51:48.676386 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 10:51:48.679201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 10:51:48.686171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 10:51:48.689182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 10:51:48.692870 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 10:51:48.698951 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 10:51:48.702046 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 10:51:48.706054 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 10:51:48.712712 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 10:51:48.715426 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 10:51:48.718774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 10:51:48.725280 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 10:51:48.728906 Total UI for P1: 0, mck2ui 16
891 10:51:48.733514 best dqsien dly found for B0: ( 0, 14, 6)
892 10:51:48.735981 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 10:51:48.738820 Total UI for P1: 0, mck2ui 16
894 10:51:48.742493 best dqsien dly found for B1: ( 0, 14, 8)
895 10:51:48.745558 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 10:51:48.748790 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 10:51:48.749263
898 10:51:48.752024 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 10:51:48.755301 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 10:51:48.759623 [Gating] SW calibration Done
901 10:51:48.760248 ==
902 10:51:48.763079 Dram Type= 6, Freq= 0, CH_0, rank 0
903 10:51:48.766253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 10:51:48.766722 ==
905 10:51:48.769221 RX Vref Scan: 0
906 10:51:48.769707
907 10:51:48.770083 RX Vref 0 -> 0, step: 1
908 10:51:48.770467
909 10:51:48.772632 RX Delay -130 -> 252, step: 16
910 10:51:48.779564 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
911 10:51:48.782928 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 10:51:48.785838 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 10:51:48.789715 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 10:51:48.792798 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 10:51:48.796213 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 10:51:48.802913 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 10:51:48.806572 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 10:51:48.809718 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 10:51:48.813131 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
920 10:51:48.816112 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 10:51:48.823135 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 10:51:48.826163 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 10:51:48.830175 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 10:51:48.833173 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 10:51:48.840437 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 10:51:48.841004 ==
927 10:51:48.842882 Dram Type= 6, Freq= 0, CH_0, rank 0
928 10:51:48.846458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 10:51:48.846984 ==
930 10:51:48.847364 DQS Delay:
931 10:51:48.850104 DQS0 = 0, DQS1 = 0
932 10:51:48.850671 DQM Delay:
933 10:51:48.853345 DQM0 = 90, DQM1 = 76
934 10:51:48.853769 DQ Delay:
935 10:51:48.856356 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
936 10:51:48.859465 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
937 10:51:48.862706 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
938 10:51:48.866179 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
939 10:51:48.866741
940 10:51:48.867085
941 10:51:48.867434 ==
942 10:51:48.869147 Dram Type= 6, Freq= 0, CH_0, rank 0
943 10:51:48.873008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 10:51:48.873535 ==
945 10:51:48.876569
946 10:51:48.877072
947 10:51:48.877417 TX Vref Scan disable
948 10:51:48.879275 == TX Byte 0 ==
949 10:51:48.882536 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 10:51:48.885705 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 10:51:48.889009 == TX Byte 1 ==
952 10:51:48.892830 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
953 10:51:48.896309 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
954 10:51:48.896784 ==
955 10:51:48.899573 Dram Type= 6, Freq= 0, CH_0, rank 0
956 10:51:48.905934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 10:51:48.906453 ==
958 10:51:48.917848 TX Vref=22, minBit 5, minWin=26, winSum=435
959 10:51:48.921397 TX Vref=24, minBit 0, minWin=27, winSum=441
960 10:51:48.924488 TX Vref=26, minBit 1, minWin=27, winSum=446
961 10:51:48.927979 TX Vref=28, minBit 1, minWin=27, winSum=448
962 10:51:48.931208 TX Vref=30, minBit 6, minWin=27, winSum=451
963 10:51:48.938885 TX Vref=32, minBit 0, minWin=28, winSum=451
964 10:51:48.940825 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
965 10:51:48.941293
966 10:51:48.944454 Final TX Range 1 Vref 32
967 10:51:48.945018
968 10:51:48.945394 ==
969 10:51:48.948181 Dram Type= 6, Freq= 0, CH_0, rank 0
970 10:51:48.951162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 10:51:48.951705 ==
972 10:51:48.954457
973 10:51:48.955020
974 10:51:48.955396 TX Vref Scan disable
975 10:51:48.958122 == TX Byte 0 ==
976 10:51:48.960818 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 10:51:48.964917 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 10:51:48.968217 == TX Byte 1 ==
979 10:51:48.971457 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
980 10:51:48.978047 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
981 10:51:48.978607
982 10:51:48.978986 [DATLAT]
983 10:51:48.979335 Freq=800, CH0 RK0
984 10:51:48.979675
985 10:51:48.980799 DATLAT Default: 0xa
986 10:51:48.981266 0, 0xFFFF, sum = 0
987 10:51:48.983988 1, 0xFFFF, sum = 0
988 10:51:48.984454 2, 0xFFFF, sum = 0
989 10:51:48.988027 3, 0xFFFF, sum = 0
990 10:51:48.991161 4, 0xFFFF, sum = 0
991 10:51:48.991602 5, 0xFFFF, sum = 0
992 10:51:48.994333 6, 0xFFFF, sum = 0
993 10:51:48.994872 7, 0xFFFF, sum = 0
994 10:51:48.997270 8, 0xFFFF, sum = 0
995 10:51:48.997724 9, 0x0, sum = 1
996 10:51:49.000902 10, 0x0, sum = 2
997 10:51:49.001332 11, 0x0, sum = 3
998 10:51:49.001679 12, 0x0, sum = 4
999 10:51:49.004136 best_step = 10
1000 10:51:49.004582
1001 10:51:49.004927 ==
1002 10:51:49.008009 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 10:51:49.010757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 10:51:49.011201 ==
1005 10:51:49.014002 RX Vref Scan: 1
1006 10:51:49.014445
1007 10:51:49.017402 Set Vref Range= 32 -> 127
1008 10:51:49.017851
1009 10:51:49.018427 RX Vref 32 -> 127, step: 1
1010 10:51:49.018846
1011 10:51:49.020351 RX Delay -95 -> 252, step: 8
1012 10:51:49.020778
1013 10:51:49.023990 Set Vref, RX VrefLevel [Byte0]: 32
1014 10:51:49.027271 [Byte1]: 32
1015 10:51:49.030632
1016 10:51:49.031175 Set Vref, RX VrefLevel [Byte0]: 33
1017 10:51:49.033870 [Byte1]: 33
1018 10:51:49.038566
1019 10:51:49.039079 Set Vref, RX VrefLevel [Byte0]: 34
1020 10:51:49.041494 [Byte1]: 34
1021 10:51:49.045794
1022 10:51:49.046358 Set Vref, RX VrefLevel [Byte0]: 35
1023 10:51:49.049131 [Byte1]: 35
1024 10:51:49.053682
1025 10:51:49.054268 Set Vref, RX VrefLevel [Byte0]: 36
1026 10:51:49.056273 [Byte1]: 36
1027 10:51:49.061035
1028 10:51:49.061738 Set Vref, RX VrefLevel [Byte0]: 37
1029 10:51:49.064258 [Byte1]: 37
1030 10:51:49.068379
1031 10:51:49.068864 Set Vref, RX VrefLevel [Byte0]: 38
1032 10:51:49.072150 [Byte1]: 38
1033 10:51:49.076623
1034 10:51:49.077155 Set Vref, RX VrefLevel [Byte0]: 39
1035 10:51:49.079341 [Byte1]: 39
1036 10:51:49.084019
1037 10:51:49.084595 Set Vref, RX VrefLevel [Byte0]: 40
1038 10:51:49.088191 [Byte1]: 40
1039 10:51:49.091580
1040 10:51:49.092204 Set Vref, RX VrefLevel [Byte0]: 41
1041 10:51:49.095032 [Byte1]: 41
1042 10:51:49.098677
1043 10:51:49.099096 Set Vref, RX VrefLevel [Byte0]: 42
1044 10:51:49.101893 [Byte1]: 42
1045 10:51:49.106262
1046 10:51:49.106679 Set Vref, RX VrefLevel [Byte0]: 43
1047 10:51:49.109701 [Byte1]: 43
1048 10:51:49.114020
1049 10:51:49.114642 Set Vref, RX VrefLevel [Byte0]: 44
1050 10:51:49.117194 [Byte1]: 44
1051 10:51:49.121615
1052 10:51:49.122033 Set Vref, RX VrefLevel [Byte0]: 45
1053 10:51:49.124629 [Byte1]: 45
1054 10:51:49.128984
1055 10:51:49.129405 Set Vref, RX VrefLevel [Byte0]: 46
1056 10:51:49.133195 [Byte1]: 46
1057 10:51:49.137129
1058 10:51:49.137644 Set Vref, RX VrefLevel [Byte0]: 47
1059 10:51:49.140632 [Byte1]: 47
1060 10:51:49.144497
1061 10:51:49.144917 Set Vref, RX VrefLevel [Byte0]: 48
1062 10:51:49.148229 [Byte1]: 48
1063 10:51:49.152451
1064 10:51:49.152959 Set Vref, RX VrefLevel [Byte0]: 49
1065 10:51:49.155679 [Byte1]: 49
1066 10:51:49.159947
1067 10:51:49.160540 Set Vref, RX VrefLevel [Byte0]: 50
1068 10:51:49.164138 [Byte1]: 50
1069 10:51:49.167484
1070 10:51:49.168002 Set Vref, RX VrefLevel [Byte0]: 51
1071 10:51:49.170563 [Byte1]: 51
1072 10:51:49.174990
1073 10:51:49.175502 Set Vref, RX VrefLevel [Byte0]: 52
1074 10:51:49.178935 [Byte1]: 52
1075 10:51:49.182887
1076 10:51:49.183402 Set Vref, RX VrefLevel [Byte0]: 53
1077 10:51:49.185699 [Byte1]: 53
1078 10:51:49.190462
1079 10:51:49.190982 Set Vref, RX VrefLevel [Byte0]: 54
1080 10:51:49.193682 [Byte1]: 54
1081 10:51:49.197517
1082 10:51:49.198035 Set Vref, RX VrefLevel [Byte0]: 55
1083 10:51:49.201348 [Byte1]: 55
1084 10:51:49.205362
1085 10:51:49.205875 Set Vref, RX VrefLevel [Byte0]: 56
1086 10:51:49.208474 [Byte1]: 56
1087 10:51:49.212910
1088 10:51:49.213413 Set Vref, RX VrefLevel [Byte0]: 57
1089 10:51:49.215844 [Byte1]: 57
1090 10:51:49.220292
1091 10:51:49.220712 Set Vref, RX VrefLevel [Byte0]: 58
1092 10:51:49.223555 [Byte1]: 58
1093 10:51:49.227759
1094 10:51:49.228218 Set Vref, RX VrefLevel [Byte0]: 59
1095 10:51:49.231016 [Byte1]: 59
1096 10:51:49.235699
1097 10:51:49.236259 Set Vref, RX VrefLevel [Byte0]: 60
1098 10:51:49.239290 [Byte1]: 60
1099 10:51:49.243598
1100 10:51:49.244182 Set Vref, RX VrefLevel [Byte0]: 61
1101 10:51:49.246699 [Byte1]: 61
1102 10:51:49.251142
1103 10:51:49.251655 Set Vref, RX VrefLevel [Byte0]: 62
1104 10:51:49.254643 [Byte1]: 62
1105 10:51:49.259491
1106 10:51:49.260004 Set Vref, RX VrefLevel [Byte0]: 63
1107 10:51:49.262049 [Byte1]: 63
1108 10:51:49.266006
1109 10:51:49.266525 Set Vref, RX VrefLevel [Byte0]: 64
1110 10:51:49.269459 [Byte1]: 64
1111 10:51:49.274210
1112 10:51:49.274774 Set Vref, RX VrefLevel [Byte0]: 65
1113 10:51:49.277135 [Byte1]: 65
1114 10:51:49.281470
1115 10:51:49.281983 Set Vref, RX VrefLevel [Byte0]: 66
1116 10:51:49.285042 [Byte1]: 66
1117 10:51:49.288663
1118 10:51:49.289218 Set Vref, RX VrefLevel [Byte0]: 67
1119 10:51:49.292839 [Byte1]: 67
1120 10:51:49.296841
1121 10:51:49.297366 Set Vref, RX VrefLevel [Byte0]: 68
1122 10:51:49.299774 [Byte1]: 68
1123 10:51:49.304153
1124 10:51:49.304765 Set Vref, RX VrefLevel [Byte0]: 69
1125 10:51:49.307114 [Byte1]: 69
1126 10:51:49.311609
1127 10:51:49.312056 Set Vref, RX VrefLevel [Byte0]: 70
1128 10:51:49.314683 [Byte1]: 70
1129 10:51:49.319163
1130 10:51:49.319673 Set Vref, RX VrefLevel [Byte0]: 71
1131 10:51:49.322133 [Byte1]: 71
1132 10:51:49.326827
1133 10:51:49.327238 Set Vref, RX VrefLevel [Byte0]: 72
1134 10:51:49.330217 [Byte1]: 72
1135 10:51:49.334187
1136 10:51:49.334747 Set Vref, RX VrefLevel [Byte0]: 73
1137 10:51:49.338321 [Byte1]: 73
1138 10:51:49.342113
1139 10:51:49.342565 Set Vref, RX VrefLevel [Byte0]: 74
1140 10:51:49.345351 [Byte1]: 74
1141 10:51:49.350352
1142 10:51:49.350893 Set Vref, RX VrefLevel [Byte0]: 75
1143 10:51:49.353434 [Byte1]: 75
1144 10:51:49.357098
1145 10:51:49.357552 Set Vref, RX VrefLevel [Byte0]: 76
1146 10:51:49.360986 [Byte1]: 76
1147 10:51:49.364907
1148 10:51:49.365453 Set Vref, RX VrefLevel [Byte0]: 77
1149 10:51:49.368394 [Byte1]: 77
1150 10:51:49.372578
1151 10:51:49.373122 Final RX Vref Byte 0 = 58 to rank0
1152 10:51:49.375971 Final RX Vref Byte 1 = 60 to rank0
1153 10:51:49.379447 Final RX Vref Byte 0 = 58 to rank1
1154 10:51:49.382208 Final RX Vref Byte 1 = 60 to rank1==
1155 10:51:49.385605 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 10:51:49.392011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 10:51:49.392610 ==
1158 10:51:49.392979 DQS Delay:
1159 10:51:49.395667 DQS0 = 0, DQS1 = 0
1160 10:51:49.396163 DQM Delay:
1161 10:51:49.396538 DQM0 = 88, DQM1 = 76
1162 10:51:49.398478 DQ Delay:
1163 10:51:49.402481 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1164 10:51:49.406481 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1165 10:51:49.407040 DQ8 =64, DQ9 =60, DQ10 =80, DQ11 =72
1166 10:51:49.412919 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1167 10:51:49.413475
1168 10:51:49.413836
1169 10:51:49.418996 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a23, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1170 10:51:49.422770 CH0 RK0: MR19=606, MR18=2A23
1171 10:51:49.428410 CH0_RK0: MR19=0x606, MR18=0x2A23, DQSOSC=399, MR23=63, INC=92, DEC=61
1172 10:51:49.428824
1173 10:51:49.432504 ----->DramcWriteLeveling(PI) begin...
1174 10:51:49.433021 ==
1175 10:51:49.435285 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 10:51:49.438761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 10:51:49.439318 ==
1178 10:51:49.442036 Write leveling (Byte 0): 28 => 28
1179 10:51:49.445115 Write leveling (Byte 1): 26 => 26
1180 10:51:49.448606 DramcWriteLeveling(PI) end<-----
1181 10:51:49.449061
1182 10:51:49.449422 ==
1183 10:51:49.451888 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 10:51:49.495968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 10:51:49.496627 ==
1186 10:51:49.497360 [Gating] SW mode calibration
1187 10:51:49.497787 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 10:51:49.498258 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 10:51:49.498614 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 10:51:49.498954 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 10:51:49.499313 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1192 10:51:49.499698 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:51:49.500059 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 10:51:49.540398 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 10:51:49.540970 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:51:49.541680 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:51:49.542163 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:51:49.542552 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:51:49.542930 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 10:51:49.543354 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:51:49.543732 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:51:49.544245 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 10:51:49.544582 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 10:51:49.544894 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 10:51:49.583467 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1206 10:51:49.584111 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1207 10:51:49.584840 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1208 10:51:49.585288 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 10:51:49.585652 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 10:51:49.585996 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 10:51:49.586401 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 10:51:49.586750 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 10:51:49.587071 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 10:51:49.587379 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1215 10:51:49.589042 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1216 10:51:49.596274 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1217 10:51:49.598991 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 10:51:49.602110 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 10:51:49.609463 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 10:51:49.612679 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 10:51:49.615565 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 10:51:49.622056 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1223 10:51:49.625234 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
1224 10:51:49.628603 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:51:49.635612 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:51:49.639575 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:51:49.642799 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:51:49.646866 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:51:49.650108 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:51:49.657148 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1231 10:51:49.660386 0 11 8 | B1->B0 | 3232 4444 | 1 0 | (0 0) (0 0)
1232 10:51:49.663842 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1233 10:51:49.667572 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 10:51:49.675178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 10:51:49.677838 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 10:51:49.680948 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 10:51:49.687653 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 10:51:49.690820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1239 10:51:49.693924 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 10:51:49.700940 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 10:51:49.704572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 10:51:49.707864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 10:51:49.714566 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 10:51:49.717547 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 10:51:49.720946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 10:51:49.727817 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 10:51:49.730525 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 10:51:49.734212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 10:51:49.740527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 10:51:49.743893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 10:51:49.747382 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 10:51:49.754495 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 10:51:49.756928 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 10:51:49.760396 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1255 10:51:49.767813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1256 10:51:49.768401 Total UI for P1: 0, mck2ui 16
1257 10:51:49.773552 best dqsien dly found for B0: ( 0, 14, 4)
1258 10:51:49.776837 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 10:51:49.780896 Total UI for P1: 0, mck2ui 16
1260 10:51:49.784227 best dqsien dly found for B1: ( 0, 14, 8)
1261 10:51:49.787052 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1262 10:51:49.790292 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1263 10:51:49.790850
1264 10:51:49.793820 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1265 10:51:49.798195 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 10:51:49.800340 [Gating] SW calibration Done
1267 10:51:49.800908 ==
1268 10:51:49.804874 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 10:51:49.807555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 10:51:49.808159 ==
1271 10:51:49.811021 RX Vref Scan: 0
1272 10:51:49.811586
1273 10:51:49.811959 RX Vref 0 -> 0, step: 1
1274 10:51:49.814142
1275 10:51:49.814725 RX Delay -130 -> 252, step: 16
1276 10:51:49.820669 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1277 10:51:49.823666 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1278 10:51:49.827181 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1279 10:51:49.830523 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1280 10:51:49.834278 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1281 10:51:49.840696 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1282 10:51:49.844247 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1283 10:51:49.846905 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1284 10:51:49.850936 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1285 10:51:49.853728 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1286 10:51:49.860211 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1287 10:51:49.863583 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1288 10:51:49.868612 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1289 10:51:49.870283 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1290 10:51:49.873838 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1291 10:51:49.880681 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1292 10:51:49.881274 ==
1293 10:51:49.884065 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 10:51:49.888397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 10:51:49.888870 ==
1296 10:51:49.889242 DQS Delay:
1297 10:51:49.890027 DQS0 = 0, DQS1 = 0
1298 10:51:49.890493 DQM Delay:
1299 10:51:49.893842 DQM0 = 89, DQM1 = 78
1300 10:51:49.894404 DQ Delay:
1301 10:51:49.896863 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1302 10:51:49.900691 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =101
1303 10:51:49.903417 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1304 10:51:49.906748 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1305 10:51:49.907215
1306 10:51:49.907583
1307 10:51:49.907925 ==
1308 10:51:49.910342 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 10:51:49.913432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 10:51:49.913904 ==
1311 10:51:49.916836
1312 10:51:49.917403
1313 10:51:49.917778 TX Vref Scan disable
1314 10:51:49.920409 == TX Byte 0 ==
1315 10:51:49.923314 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1316 10:51:49.926614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1317 10:51:49.930652 == TX Byte 1 ==
1318 10:51:49.933463 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1319 10:51:49.936543 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1320 10:51:49.937012 ==
1321 10:51:49.940239 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 10:51:49.946447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 10:51:49.947010 ==
1324 10:51:49.958844 TX Vref=22, minBit 0, minWin=27, winSum=443
1325 10:51:49.962030 TX Vref=24, minBit 0, minWin=27, winSum=446
1326 10:51:49.965458 TX Vref=26, minBit 6, minWin=27, winSum=447
1327 10:51:49.969815 TX Vref=28, minBit 6, minWin=27, winSum=453
1328 10:51:49.971949 TX Vref=30, minBit 6, minWin=27, winSum=451
1329 10:51:49.975063 TX Vref=32, minBit 6, minWin=27, winSum=448
1330 10:51:49.981674 [TxChooseVref] Worse bit 6, Min win 27, Win sum 453, Final Vref 28
1331 10:51:49.982123
1332 10:51:49.984824 Final TX Range 1 Vref 28
1333 10:51:49.985248
1334 10:51:49.985597 ==
1335 10:51:49.988186 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 10:51:49.992105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 10:51:49.992559 ==
1338 10:51:49.994781
1339 10:51:49.995183
1340 10:51:49.995503 TX Vref Scan disable
1341 10:51:49.998528 == TX Byte 0 ==
1342 10:51:50.001616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1343 10:51:50.008682 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1344 10:51:50.008989 == TX Byte 1 ==
1345 10:51:50.011502 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1346 10:51:50.018319 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1347 10:51:50.018629
1348 10:51:50.018805 [DATLAT]
1349 10:51:50.018969 Freq=800, CH0 RK1
1350 10:51:50.019124
1351 10:51:50.021555 DATLAT Default: 0xa
1352 10:51:50.021772 0, 0xFFFF, sum = 0
1353 10:51:50.024963 1, 0xFFFF, sum = 0
1354 10:51:50.028451 2, 0xFFFF, sum = 0
1355 10:51:50.028682 3, 0xFFFF, sum = 0
1356 10:51:50.031234 4, 0xFFFF, sum = 0
1357 10:51:50.031454 5, 0xFFFF, sum = 0
1358 10:51:50.034920 6, 0xFFFF, sum = 0
1359 10:51:50.035190 7, 0xFFFF, sum = 0
1360 10:51:50.038175 8, 0xFFFF, sum = 0
1361 10:51:50.038541 9, 0x0, sum = 1
1362 10:51:50.041976 10, 0x0, sum = 2
1363 10:51:50.042325 11, 0x0, sum = 3
1364 10:51:50.042603 12, 0x0, sum = 4
1365 10:51:50.045052 best_step = 10
1366 10:51:50.045452
1367 10:51:50.045773 ==
1368 10:51:50.048206 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 10:51:50.051298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 10:51:50.051808 ==
1371 10:51:50.055276 RX Vref Scan: 0
1372 10:51:50.055782
1373 10:51:50.056152 RX Vref 0 -> 0, step: 1
1374 10:51:50.057825
1375 10:51:50.058229 RX Delay -95 -> 252, step: 8
1376 10:51:50.065516 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1377 10:51:50.068682 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1378 10:51:50.071812 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1379 10:51:50.075169 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1380 10:51:50.082126 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1381 10:51:50.085395 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1382 10:51:50.088612 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1383 10:51:50.091174 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1384 10:51:50.095597 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1385 10:51:50.101334 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1386 10:51:50.104878 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1387 10:51:50.108482 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1388 10:51:50.111285 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1389 10:51:50.114677 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1390 10:51:50.121749 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1391 10:51:50.124717 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1392 10:51:50.125164 ==
1393 10:51:50.128029 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 10:51:50.131183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 10:51:50.131635 ==
1396 10:51:50.135164 DQS Delay:
1397 10:51:50.135665 DQS0 = 0, DQS1 = 0
1398 10:51:50.135992 DQM Delay:
1399 10:51:50.137972 DQM0 = 86, DQM1 = 76
1400 10:51:50.138481 DQ Delay:
1401 10:51:50.140816 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1402 10:51:50.144354 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1403 10:51:50.147819 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1404 10:51:50.151151 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1405 10:51:50.151650
1406 10:51:50.151967
1407 10:51:50.161143 [DQSOSCAuto] RK1, (LSB)MR18= 0x2622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1408 10:51:50.164249 CH0 RK1: MR19=606, MR18=2622
1409 10:51:50.167461 CH0_RK1: MR19=0x606, MR18=0x2622, DQSOSC=400, MR23=63, INC=92, DEC=61
1410 10:51:50.170912 [RxdqsGatingPostProcess] freq 800
1411 10:51:50.178751 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 10:51:50.181113 Pre-setting of DQS Precalculation
1413 10:51:50.184193 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 10:51:50.184705 ==
1415 10:51:50.187882 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 10:51:50.193813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 10:51:50.194318 ==
1418 10:51:50.197328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 10:51:50.204407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 10:51:50.213564 [CA 0] Center 36 (6~67) winsize 62
1421 10:51:50.217204 [CA 1] Center 37 (6~68) winsize 63
1422 10:51:50.219692 [CA 2] Center 35 (4~66) winsize 63
1423 10:51:50.223184 [CA 3] Center 34 (4~65) winsize 62
1424 10:51:50.226415 [CA 4] Center 35 (4~66) winsize 63
1425 10:51:50.229868 [CA 5] Center 34 (4~65) winsize 62
1426 10:51:50.230322
1427 10:51:50.234345 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 10:51:50.234965
1429 10:51:50.236363 [CATrainingPosCal] consider 1 rank data
1430 10:51:50.240202 u2DelayCellTimex100 = 270/100 ps
1431 10:51:50.244096 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 10:51:50.250772 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1433 10:51:50.253121 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1434 10:51:50.257077 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 10:51:50.259966 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1436 10:51:50.263292 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 10:51:50.263820
1438 10:51:50.266769 CA PerBit enable=1, Macro0, CA PI delay=34
1439 10:51:50.267230
1440 10:51:50.269939 [CBTSetCACLKResult] CA Dly = 34
1441 10:51:50.270355 CS Dly: 5 (0~36)
1442 10:51:50.273097 ==
1443 10:51:50.276612 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 10:51:50.279950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 10:51:50.280538 ==
1446 10:51:50.283733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 10:51:50.290090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 10:51:50.300676 [CA 0] Center 36 (6~67) winsize 62
1449 10:51:50.302736 [CA 1] Center 37 (6~68) winsize 63
1450 10:51:50.306512 [CA 2] Center 35 (4~66) winsize 63
1451 10:51:50.310651 [CA 3] Center 34 (4~65) winsize 62
1452 10:51:50.314646 [CA 4] Center 34 (4~65) winsize 62
1453 10:51:50.317746 [CA 5] Center 34 (4~65) winsize 62
1454 10:51:50.318320
1455 10:51:50.321051 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 10:51:50.321509
1457 10:51:50.324306 [CATrainingPosCal] consider 2 rank data
1458 10:51:50.328210 u2DelayCellTimex100 = 270/100 ps
1459 10:51:50.331375 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 10:51:50.335191 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1461 10:51:50.338772 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1462 10:51:50.342668 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 10:51:50.345867 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 10:51:50.350081 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 10:51:50.350643
1466 10:51:50.352806 CA PerBit enable=1, Macro0, CA PI delay=34
1467 10:51:50.353220
1468 10:51:50.356221 [CBTSetCACLKResult] CA Dly = 34
1469 10:51:50.356733 CS Dly: 5 (0~37)
1470 10:51:50.359629
1471 10:51:50.362629 ----->DramcWriteLeveling(PI) begin...
1472 10:51:50.363194 ==
1473 10:51:50.366280 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 10:51:50.369560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 10:51:50.369988 ==
1476 10:51:50.372885 Write leveling (Byte 0): 28 => 28
1477 10:51:50.375848 Write leveling (Byte 1): 28 => 28
1478 10:51:50.379441 DramcWriteLeveling(PI) end<-----
1479 10:51:50.380003
1480 10:51:50.380411 ==
1481 10:51:50.382890 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 10:51:50.386034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 10:51:50.386497 ==
1484 10:51:50.389286 [Gating] SW mode calibration
1485 10:51:50.395900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 10:51:50.402688 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 10:51:50.405912 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 10:51:50.409825 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 10:51:50.417579 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:51:50.418897 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:51:50.422395 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:51:50.428689 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 10:51:50.432916 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:51:50.435674 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:51:50.442213 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:51:50.445311 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:51:50.448618 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:51:50.455582 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 10:51:50.459314 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 10:51:50.462520 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:51:50.465541 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 10:51:50.472441 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 10:51:50.475431 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1504 10:51:50.479195 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1505 10:51:50.485114 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 10:51:50.488984 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 10:51:50.492475 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 10:51:50.498901 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 10:51:50.502353 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 10:51:50.505475 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 10:51:50.512375 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 10:51:50.514772 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1513 10:51:50.518631 0 9 8 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 1)
1514 10:51:50.525779 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 10:51:50.528367 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 10:51:50.531623 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 10:51:50.538181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 10:51:50.541525 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 10:51:50.545150 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 10:51:50.551737 0 10 4 | B1->B0 | 3333 3131 | 1 0 | (1 0) (1 0)
1521 10:51:50.554728 0 10 8 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
1522 10:51:50.558574 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:51:50.564684 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:51:50.568447 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:51:50.571786 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:51:50.578540 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:51:50.582166 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:51:50.584454 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1529 10:51:50.591341 0 11 8 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
1530 10:51:50.595035 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 10:51:50.598632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 10:51:50.604548 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 10:51:50.608201 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 10:51:50.611527 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 10:51:50.617849 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 10:51:50.620916 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1537 10:51:50.624782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1538 10:51:50.630745 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 10:51:50.634673 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 10:51:50.637801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 10:51:50.644105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 10:51:50.647773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 10:51:50.651105 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 10:51:50.654848 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 10:51:50.661175 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 10:51:50.664525 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 10:51:50.667703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 10:51:50.674459 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 10:51:50.677326 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 10:51:50.680591 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 10:51:50.687666 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 10:51:50.690586 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1553 10:51:50.693875 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1554 10:51:50.697361 Total UI for P1: 0, mck2ui 16
1555 10:51:50.700608 best dqsien dly found for B0: ( 0, 14, 4)
1556 10:51:50.707475 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 10:51:50.710686 Total UI for P1: 0, mck2ui 16
1558 10:51:50.713923 best dqsien dly found for B1: ( 0, 14, 6)
1559 10:51:50.717683 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1560 10:51:50.720352 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1561 10:51:50.720815
1562 10:51:50.723941 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 10:51:50.727085 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1564 10:51:50.730492 [Gating] SW calibration Done
1565 10:51:50.731050 ==
1566 10:51:50.733638 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 10:51:50.736797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 10:51:50.737260 ==
1569 10:51:50.740766 RX Vref Scan: 0
1570 10:51:50.741330
1571 10:51:50.741701 RX Vref 0 -> 0, step: 1
1572 10:51:50.743766
1573 10:51:50.744250 RX Delay -130 -> 252, step: 16
1574 10:51:50.749946 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1575 10:51:50.753381 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1576 10:51:50.756673 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1577 10:51:50.760780 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1578 10:51:50.763484 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1579 10:51:50.770750 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1580 10:51:50.773069 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1581 10:51:50.776438 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1582 10:51:50.780245 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1583 10:51:50.783767 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1584 10:51:50.789986 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1585 10:51:50.793179 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1586 10:51:50.797457 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1587 10:51:50.799984 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1588 10:51:50.806657 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1589 10:51:50.809523 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1590 10:51:50.810080 ==
1591 10:51:50.813133 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:51:50.816821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:51:50.817379 ==
1594 10:51:50.817746 DQS Delay:
1595 10:51:50.819621 DQS0 = 0, DQS1 = 0
1596 10:51:50.820218 DQM Delay:
1597 10:51:50.823042 DQM0 = 89, DQM1 = 84
1598 10:51:50.823511 DQ Delay:
1599 10:51:50.826219 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1600 10:51:50.829896 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1601 10:51:50.832766 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1602 10:51:50.837029 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1603 10:51:50.837545
1604 10:51:50.837911
1605 10:51:50.838253 ==
1606 10:51:50.839870 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 10:51:50.843253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 10:51:50.846943 ==
1609 10:51:50.847524
1610 10:51:50.847895
1611 10:51:50.848296 TX Vref Scan disable
1612 10:51:50.849973 == TX Byte 0 ==
1613 10:51:50.853201 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1614 10:51:50.856148 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1615 10:51:50.860517 == TX Byte 1 ==
1616 10:51:50.863215 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1617 10:51:50.865963 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1618 10:51:50.869852 ==
1619 10:51:50.872626 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 10:51:50.876170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 10:51:50.876631 ==
1622 10:51:50.888766 TX Vref=22, minBit 0, minWin=27, winSum=441
1623 10:51:50.892466 TX Vref=24, minBit 1, minWin=27, winSum=445
1624 10:51:50.896103 TX Vref=26, minBit 2, minWin=26, winSum=446
1625 10:51:50.899258 TX Vref=28, minBit 0, minWin=27, winSum=449
1626 10:51:50.902749 TX Vref=30, minBit 0, minWin=27, winSum=451
1627 10:51:50.906216 TX Vref=32, minBit 1, minWin=27, winSum=449
1628 10:51:50.912809 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 30
1629 10:51:50.913373
1630 10:51:50.915925 Final TX Range 1 Vref 30
1631 10:51:50.916518
1632 10:51:50.916889 ==
1633 10:51:50.919227 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 10:51:50.922878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 10:51:50.923445 ==
1636 10:51:50.923818
1637 10:51:50.924195
1638 10:51:50.926313 TX Vref Scan disable
1639 10:51:50.929042 == TX Byte 0 ==
1640 10:51:50.932327 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 10:51:50.936091 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 10:51:50.939747 == TX Byte 1 ==
1643 10:51:50.942682 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1644 10:51:50.945963 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1645 10:51:50.946526
1646 10:51:50.948997 [DATLAT]
1647 10:51:50.949452 Freq=800, CH1 RK0
1648 10:51:50.949823
1649 10:51:50.952489 DATLAT Default: 0xa
1650 10:51:50.952950 0, 0xFFFF, sum = 0
1651 10:51:50.956243 1, 0xFFFF, sum = 0
1652 10:51:50.956821 2, 0xFFFF, sum = 0
1653 10:51:50.958868 3, 0xFFFF, sum = 0
1654 10:51:50.959352 4, 0xFFFF, sum = 0
1655 10:51:50.961996 5, 0xFFFF, sum = 0
1656 10:51:50.962470 6, 0xFFFF, sum = 0
1657 10:51:50.965400 7, 0xFFFF, sum = 0
1658 10:51:50.965828 8, 0xFFFF, sum = 0
1659 10:51:50.968617 9, 0x0, sum = 1
1660 10:51:50.969049 10, 0x0, sum = 2
1661 10:51:50.971999 11, 0x0, sum = 3
1662 10:51:50.972523 12, 0x0, sum = 4
1663 10:51:50.975612 best_step = 10
1664 10:51:50.976168
1665 10:51:50.976608 ==
1666 10:51:50.978885 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 10:51:50.982685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 10:51:50.983339 ==
1669 10:51:50.985394 RX Vref Scan: 1
1670 10:51:50.985914
1671 10:51:50.986253 Set Vref Range= 32 -> 127
1672 10:51:50.986609
1673 10:51:50.989228 RX Vref 32 -> 127, step: 1
1674 10:51:50.989833
1675 10:51:50.992062 RX Delay -95 -> 252, step: 8
1676 10:51:50.992496
1677 10:51:50.995360 Set Vref, RX VrefLevel [Byte0]: 32
1678 10:51:50.998834 [Byte1]: 32
1679 10:51:50.999351
1680 10:51:51.001938 Set Vref, RX VrefLevel [Byte0]: 33
1681 10:51:51.005556 [Byte1]: 33
1682 10:51:51.009548
1683 10:51:51.010077 Set Vref, RX VrefLevel [Byte0]: 34
1684 10:51:51.011991 [Byte1]: 34
1685 10:51:51.016177
1686 10:51:51.016615 Set Vref, RX VrefLevel [Byte0]: 35
1687 10:51:51.019439 [Byte1]: 35
1688 10:51:51.024189
1689 10:51:51.024935 Set Vref, RX VrefLevel [Byte0]: 36
1690 10:51:51.027111 [Byte1]: 36
1691 10:51:51.030972
1692 10:51:51.031391 Set Vref, RX VrefLevel [Byte0]: 37
1693 10:51:51.034755 [Byte1]: 37
1694 10:51:51.039735
1695 10:51:51.040300 Set Vref, RX VrefLevel [Byte0]: 38
1696 10:51:51.042651 [Byte1]: 38
1697 10:51:51.047067
1698 10:51:51.047596 Set Vref, RX VrefLevel [Byte0]: 39
1699 10:51:51.049762 [Byte1]: 39
1700 10:51:51.054438
1701 10:51:51.054969 Set Vref, RX VrefLevel [Byte0]: 40
1702 10:51:51.057184 [Byte1]: 40
1703 10:51:51.061950
1704 10:51:51.062482 Set Vref, RX VrefLevel [Byte0]: 41
1705 10:51:51.065373 [Byte1]: 41
1706 10:51:51.069582
1707 10:51:51.070110 Set Vref, RX VrefLevel [Byte0]: 42
1708 10:51:51.072612 [Byte1]: 42
1709 10:51:51.077177
1710 10:51:51.077710 Set Vref, RX VrefLevel [Byte0]: 43
1711 10:51:51.080550 [Byte1]: 43
1712 10:51:51.084537
1713 10:51:51.085085 Set Vref, RX VrefLevel [Byte0]: 44
1714 10:51:51.087791 [Byte1]: 44
1715 10:51:51.092131
1716 10:51:51.092558 Set Vref, RX VrefLevel [Byte0]: 45
1717 10:51:51.095541 [Byte1]: 45
1718 10:51:51.099853
1719 10:51:51.100421 Set Vref, RX VrefLevel [Byte0]: 46
1720 10:51:51.103080 [Byte1]: 46
1721 10:51:51.107850
1722 10:51:51.108423 Set Vref, RX VrefLevel [Byte0]: 47
1723 10:51:51.110704 [Byte1]: 47
1724 10:51:51.115121
1725 10:51:51.115655 Set Vref, RX VrefLevel [Byte0]: 48
1726 10:51:51.118793 [Byte1]: 48
1727 10:51:51.122594
1728 10:51:51.123114 Set Vref, RX VrefLevel [Byte0]: 49
1729 10:51:51.125725 [Byte1]: 49
1730 10:51:51.130024
1731 10:51:51.130447 Set Vref, RX VrefLevel [Byte0]: 50
1732 10:51:51.133921 [Byte1]: 50
1733 10:51:51.139516
1734 10:51:51.140067 Set Vref, RX VrefLevel [Byte0]: 51
1735 10:51:51.141122 [Byte1]: 51
1736 10:51:51.145158
1737 10:51:51.145675 Set Vref, RX VrefLevel [Byte0]: 52
1738 10:51:51.148957 [Byte1]: 52
1739 10:51:51.153347
1740 10:51:51.153888 Set Vref, RX VrefLevel [Byte0]: 53
1741 10:51:51.156408 [Byte1]: 53
1742 10:51:51.160474
1743 10:51:51.160989 Set Vref, RX VrefLevel [Byte0]: 54
1744 10:51:51.164420 [Byte1]: 54
1745 10:51:51.168812
1746 10:51:51.169331 Set Vref, RX VrefLevel [Byte0]: 55
1747 10:51:51.171877 [Byte1]: 55
1748 10:51:51.176239
1749 10:51:51.176749 Set Vref, RX VrefLevel [Byte0]: 56
1750 10:51:51.179506 [Byte1]: 56
1751 10:51:51.183950
1752 10:51:51.184542 Set Vref, RX VrefLevel [Byte0]: 57
1753 10:51:51.186555 [Byte1]: 57
1754 10:51:51.191005
1755 10:51:51.191519 Set Vref, RX VrefLevel [Byte0]: 58
1756 10:51:51.193910 [Byte1]: 58
1757 10:51:51.198736
1758 10:51:51.199252 Set Vref, RX VrefLevel [Byte0]: 59
1759 10:51:51.202303 [Byte1]: 59
1760 10:51:51.206355
1761 10:51:51.206876 Set Vref, RX VrefLevel [Byte0]: 60
1762 10:51:51.209677 [Byte1]: 60
1763 10:51:51.213914
1764 10:51:51.214428 Set Vref, RX VrefLevel [Byte0]: 61
1765 10:51:51.216659 [Byte1]: 61
1766 10:51:51.221667
1767 10:51:51.222200 Set Vref, RX VrefLevel [Byte0]: 62
1768 10:51:51.224540 [Byte1]: 62
1769 10:51:51.228834
1770 10:51:51.229255 Set Vref, RX VrefLevel [Byte0]: 63
1771 10:51:51.232529 [Byte1]: 63
1772 10:51:51.236636
1773 10:51:51.237057 Set Vref, RX VrefLevel [Byte0]: 64
1774 10:51:51.240357 [Byte1]: 64
1775 10:51:51.244174
1776 10:51:51.244687 Set Vref, RX VrefLevel [Byte0]: 65
1777 10:51:51.247503 [Byte1]: 65
1778 10:51:51.251782
1779 10:51:51.252350 Set Vref, RX VrefLevel [Byte0]: 66
1780 10:51:51.255024 [Byte1]: 66
1781 10:51:51.259130
1782 10:51:51.259556 Set Vref, RX VrefLevel [Byte0]: 67
1783 10:51:51.263105 [Byte1]: 67
1784 10:51:51.268122
1785 10:51:51.268633 Set Vref, RX VrefLevel [Byte0]: 68
1786 10:51:51.270894 [Byte1]: 68
1787 10:51:51.275001
1788 10:51:51.275510 Set Vref, RX VrefLevel [Byte0]: 69
1789 10:51:51.277823 [Byte1]: 69
1790 10:51:51.282197
1791 10:51:51.282713 Set Vref, RX VrefLevel [Byte0]: 70
1792 10:51:51.285368 [Byte1]: 70
1793 10:51:51.289623
1794 10:51:51.290140 Set Vref, RX VrefLevel [Byte0]: 71
1795 10:51:51.292756 [Byte1]: 71
1796 10:51:51.296979
1797 10:51:51.297401 Set Vref, RX VrefLevel [Byte0]: 72
1798 10:51:51.300658 [Byte1]: 72
1799 10:51:51.304998
1800 10:51:51.305510 Set Vref, RX VrefLevel [Byte0]: 73
1801 10:51:51.308475 [Byte1]: 73
1802 10:51:51.312778
1803 10:51:51.313241 Set Vref, RX VrefLevel [Byte0]: 74
1804 10:51:51.315798 [Byte1]: 74
1805 10:51:51.320176
1806 10:51:51.320703 Set Vref, RX VrefLevel [Byte0]: 75
1807 10:51:51.323240 [Byte1]: 75
1808 10:51:51.327557
1809 10:51:51.327979 Set Vref, RX VrefLevel [Byte0]: 76
1810 10:51:51.330826 [Byte1]: 76
1811 10:51:51.335523
1812 10:51:51.336255 Final RX Vref Byte 0 = 59 to rank0
1813 10:51:51.338341 Final RX Vref Byte 1 = 57 to rank0
1814 10:51:51.342217 Final RX Vref Byte 0 = 59 to rank1
1815 10:51:51.345234 Final RX Vref Byte 1 = 57 to rank1==
1816 10:51:51.348814 Dram Type= 6, Freq= 0, CH_1, rank 0
1817 10:51:51.355163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 10:51:51.355677 ==
1819 10:51:51.356024 DQS Delay:
1820 10:51:51.356392 DQS0 = 0, DQS1 = 0
1821 10:51:51.358385 DQM Delay:
1822 10:51:51.358894 DQM0 = 87, DQM1 = 81
1823 10:51:51.361821 DQ Delay:
1824 10:51:51.365012 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1825 10:51:51.368498 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1826 10:51:51.371995 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1827 10:51:51.375475 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1828 10:51:51.375987
1829 10:51:51.376375
1830 10:51:51.381433 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1831 10:51:51.384615 CH1 RK0: MR19=606, MR18=1B2E
1832 10:51:51.391971 CH1_RK0: MR19=0x606, MR18=0x1B2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1833 10:51:51.392523
1834 10:51:51.395195 ----->DramcWriteLeveling(PI) begin...
1835 10:51:51.395810 ==
1836 10:51:51.398219 Dram Type= 6, Freq= 0, CH_1, rank 1
1837 10:51:51.401931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 10:51:51.402449 ==
1839 10:51:51.404590 Write leveling (Byte 0): 26 => 26
1840 10:51:51.408181 Write leveling (Byte 1): 30 => 30
1841 10:51:51.411747 DramcWriteLeveling(PI) end<-----
1842 10:51:51.412309
1843 10:51:51.412652 ==
1844 10:51:51.414959 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 10:51:51.418168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 10:51:51.418598 ==
1847 10:51:51.421269 [Gating] SW mode calibration
1848 10:51:51.427807 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1849 10:51:51.434559 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1850 10:51:51.438265 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1851 10:51:51.444283 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1852 10:51:51.448307 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1853 10:51:51.451034 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:51:51.457945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 10:51:51.461282 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 10:51:51.464540 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 10:51:51.471052 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:51:51.474844 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:51:51.477911 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 10:51:51.481180 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 10:51:51.487898 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:51:51.491474 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 10:51:51.494539 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 10:51:51.500935 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 10:51:51.504188 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 10:51:51.508114 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1867 10:51:51.514379 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1868 10:51:51.517572 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:51:51.520787 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:51:51.527321 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:51:51.532185 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:51:51.534653 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:51:51.540996 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:51:51.543842 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:51:51.547209 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1876 10:51:51.553925 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1877 10:51:51.557397 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 10:51:51.560941 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 10:51:51.567339 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 10:51:51.571660 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 10:51:51.574029 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 10:51:51.580562 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
1883 10:51:51.583944 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
1884 10:51:51.587222 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1885 10:51:51.594028 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:51:51.597016 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:51:51.600859 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:51:51.607032 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:51:51.610205 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:51:51.613647 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:51:51.619986 0 11 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
1892 10:51:51.623568 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1893 10:51:51.626791 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 10:51:51.633782 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 10:51:51.636267 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 10:51:51.639695 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 10:51:51.646623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 10:51:51.650296 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 10:51:51.653208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1900 10:51:51.660251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1901 10:51:51.663125 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 10:51:51.666842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 10:51:51.672761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 10:51:51.676200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 10:51:51.679639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 10:51:51.686461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 10:51:51.690016 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 10:51:51.692650 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 10:51:51.699426 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 10:51:51.702774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 10:51:51.706076 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 10:51:51.712795 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 10:51:51.716337 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 10:51:51.719661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1915 10:51:51.722781 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1916 10:51:51.726113 Total UI for P1: 0, mck2ui 16
1917 10:51:51.729335 best dqsien dly found for B0: ( 0, 14, 0)
1918 10:51:51.735849 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 10:51:51.739722 Total UI for P1: 0, mck2ui 16
1920 10:51:51.742551 best dqsien dly found for B1: ( 0, 14, 4)
1921 10:51:51.745658 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1922 10:51:51.749368 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1923 10:51:51.749943
1924 10:51:51.753254 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1925 10:51:51.755816 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1926 10:51:51.759475 [Gating] SW calibration Done
1927 10:51:51.760075 ==
1928 10:51:51.762409 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 10:51:51.765748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 10:51:51.766314 ==
1931 10:51:51.768791 RX Vref Scan: 0
1932 10:51:51.769334
1933 10:51:51.772166 RX Vref 0 -> 0, step: 1
1934 10:51:51.772633
1935 10:51:51.773005 RX Delay -130 -> 252, step: 16
1936 10:51:51.778825 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1937 10:51:51.782160 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1938 10:51:51.785739 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1939 10:51:51.788802 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1940 10:51:51.792262 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1941 10:51:51.798388 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1942 10:51:51.801774 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1943 10:51:51.804973 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1944 10:51:51.808458 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1945 10:51:51.812257 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1946 10:51:51.818602 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1947 10:51:51.821914 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1948 10:51:51.825489 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1949 10:51:51.828134 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1950 10:51:51.835370 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1951 10:51:51.838467 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1952 10:51:51.838697 ==
1953 10:51:51.841944 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 10:51:51.844801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 10:51:51.845007 ==
1956 10:51:51.845156 DQS Delay:
1957 10:51:51.848002 DQS0 = 0, DQS1 = 0
1958 10:51:51.848205 DQM Delay:
1959 10:51:51.852057 DQM0 = 83, DQM1 = 80
1960 10:51:51.852326 DQ Delay:
1961 10:51:51.855068 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1962 10:51:51.858211 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1963 10:51:51.862600 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1964 10:51:51.864600 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1965 10:51:51.865024
1966 10:51:51.865363
1967 10:51:51.865676 ==
1968 10:51:51.868224 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 10:51:51.871238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 10:51:51.874316 ==
1971 10:51:51.874545
1972 10:51:51.874728
1973 10:51:51.874897 TX Vref Scan disable
1974 10:51:51.877532 == TX Byte 0 ==
1975 10:51:51.881360 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1976 10:51:51.887960 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1977 10:51:51.888330 == TX Byte 1 ==
1978 10:51:51.891448 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1979 10:51:51.898087 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1980 10:51:51.898432 ==
1981 10:51:51.900903 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 10:51:51.904132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 10:51:51.904477 ==
1984 10:51:51.917284 TX Vref=22, minBit 1, minWin=26, winSum=440
1985 10:51:51.920384 TX Vref=24, minBit 5, minWin=26, winSum=443
1986 10:51:51.923943 TX Vref=26, minBit 2, minWin=27, winSum=449
1987 10:51:51.927353 TX Vref=28, minBit 2, minWin=27, winSum=451
1988 10:51:51.930412 TX Vref=30, minBit 2, minWin=27, winSum=451
1989 10:51:51.937493 TX Vref=32, minBit 2, minWin=27, winSum=452
1990 10:51:51.940289 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 32
1991 10:51:51.940478
1992 10:51:51.943709 Final TX Range 1 Vref 32
1993 10:51:51.943955
1994 10:51:51.944155 ==
1995 10:51:51.947156 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 10:51:51.950309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 10:51:51.953756 ==
1998 10:51:51.954028
1999 10:51:51.954190
2000 10:51:51.954339 TX Vref Scan disable
2001 10:51:51.957410 == TX Byte 0 ==
2002 10:51:51.960420 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2003 10:51:51.967297 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2004 10:51:51.967647 == TX Byte 1 ==
2005 10:51:51.970572 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2006 10:51:51.977027 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2007 10:51:51.977261
2008 10:51:51.977412 [DATLAT]
2009 10:51:51.977551 Freq=800, CH1 RK1
2010 10:51:51.977775
2011 10:51:51.980152 DATLAT Default: 0xa
2012 10:51:51.980340 0, 0xFFFF, sum = 0
2013 10:51:51.983962 1, 0xFFFF, sum = 0
2014 10:51:51.984186 2, 0xFFFF, sum = 0
2015 10:51:51.986979 3, 0xFFFF, sum = 0
2016 10:51:51.990010 4, 0xFFFF, sum = 0
2017 10:51:51.990200 5, 0xFFFF, sum = 0
2018 10:51:51.993801 6, 0xFFFF, sum = 0
2019 10:51:51.993991 7, 0xFFFF, sum = 0
2020 10:51:51.996722 8, 0xFFFF, sum = 0
2021 10:51:51.996913 9, 0x0, sum = 1
2022 10:51:52.000629 10, 0x0, sum = 2
2023 10:51:52.000820 11, 0x0, sum = 3
2024 10:51:52.000973 12, 0x0, sum = 4
2025 10:51:52.003661 best_step = 10
2026 10:51:52.003849
2027 10:51:52.003999 ==
2028 10:51:52.006807 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 10:51:52.010053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 10:51:52.010244 ==
2031 10:51:52.013184 RX Vref Scan: 0
2032 10:51:52.013372
2033 10:51:52.017036 RX Vref 0 -> 0, step: 1
2034 10:51:52.017536
2035 10:51:52.017875 RX Delay -95 -> 252, step: 8
2036 10:51:52.024398 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2037 10:51:52.027652 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2038 10:51:52.030747 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2039 10:51:52.034341 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2040 10:51:52.037449 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2041 10:51:52.044507 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2042 10:51:52.047575 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2043 10:51:52.051028 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2044 10:51:52.053820 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2045 10:51:52.057039 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2046 10:51:52.063928 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2047 10:51:52.067227 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2048 10:51:52.070887 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2049 10:51:52.074294 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2050 10:51:52.080433 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2051 10:51:52.083635 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2052 10:51:52.084242 ==
2053 10:51:52.087242 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 10:51:52.090790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 10:51:52.091366 ==
2056 10:51:52.094033 DQS Delay:
2057 10:51:52.094599 DQS0 = 0, DQS1 = 0
2058 10:51:52.095011 DQM Delay:
2059 10:51:52.097354 DQM0 = 87, DQM1 = 85
2060 10:51:52.097817 DQ Delay:
2061 10:51:52.100377 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2062 10:51:52.103534 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2063 10:51:52.107607 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
2064 10:51:52.110448 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =88
2065 10:51:52.111021
2066 10:51:52.111392
2067 10:51:52.120490 [DQSOSCAuto] RK1, (LSB)MR18= 0x1935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2068 10:51:52.121061 CH1 RK1: MR19=606, MR18=1935
2069 10:51:52.127302 CH1_RK1: MR19=0x606, MR18=0x1935, DQSOSC=396, MR23=63, INC=94, DEC=62
2070 10:51:52.130646 [RxdqsGatingPostProcess] freq 800
2071 10:51:52.136698 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2072 10:51:52.140472 Pre-setting of DQS Precalculation
2073 10:51:52.143514 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2074 10:51:52.150511 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2075 10:51:52.160337 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2076 10:51:52.160901
2077 10:51:52.161274
2078 10:51:52.163736 [Calibration Summary] 1600 Mbps
2079 10:51:52.164341 CH 0, Rank 0
2080 10:51:52.166995 SW Impedance : PASS
2081 10:51:52.167566 DUTY Scan : NO K
2082 10:51:52.170315 ZQ Calibration : PASS
2083 10:51:52.170880 Jitter Meter : NO K
2084 10:51:52.173575 CBT Training : PASS
2085 10:51:52.176985 Write leveling : PASS
2086 10:51:52.177552 RX DQS gating : PASS
2087 10:51:52.179961 RX DQ/DQS(RDDQC) : PASS
2088 10:51:52.183327 TX DQ/DQS : PASS
2089 10:51:52.183906 RX DATLAT : PASS
2090 10:51:52.186940 RX DQ/DQS(Engine): PASS
2091 10:51:52.190098 TX OE : NO K
2092 10:51:52.190679 All Pass.
2093 10:51:52.191057
2094 10:51:52.191435 CH 0, Rank 1
2095 10:51:52.193162 SW Impedance : PASS
2096 10:51:52.196420 DUTY Scan : NO K
2097 10:51:52.196884 ZQ Calibration : PASS
2098 10:51:52.199413 Jitter Meter : NO K
2099 10:51:52.203176 CBT Training : PASS
2100 10:51:52.203775 Write leveling : PASS
2101 10:51:52.206451 RX DQS gating : PASS
2102 10:51:52.209573 RX DQ/DQS(RDDQC) : PASS
2103 10:51:52.210188 TX DQ/DQS : PASS
2104 10:51:52.212980 RX DATLAT : PASS
2105 10:51:52.216921 RX DQ/DQS(Engine): PASS
2106 10:51:52.217450 TX OE : NO K
2107 10:51:52.219858 All Pass.
2108 10:51:52.220350
2109 10:51:52.220717 CH 1, Rank 0
2110 10:51:52.223072 SW Impedance : PASS
2111 10:51:52.223637 DUTY Scan : NO K
2112 10:51:52.226415 ZQ Calibration : PASS
2113 10:51:52.229307 Jitter Meter : NO K
2114 10:51:52.229789 CBT Training : PASS
2115 10:51:52.233134 Write leveling : PASS
2116 10:51:52.236679 RX DQS gating : PASS
2117 10:51:52.237144 RX DQ/DQS(RDDQC) : PASS
2118 10:51:52.239714 TX DQ/DQS : PASS
2119 10:51:52.240326 RX DATLAT : PASS
2120 10:51:52.243039 RX DQ/DQS(Engine): PASS
2121 10:51:52.246584 TX OE : NO K
2122 10:51:52.247053 All Pass.
2123 10:51:52.247424
2124 10:51:52.247768 CH 1, Rank 1
2125 10:51:52.249461 SW Impedance : PASS
2126 10:51:52.253304 DUTY Scan : NO K
2127 10:51:52.253869 ZQ Calibration : PASS
2128 10:51:52.256358 Jitter Meter : NO K
2129 10:51:52.259683 CBT Training : PASS
2130 10:51:52.260296 Write leveling : PASS
2131 10:51:52.262979 RX DQS gating : PASS
2132 10:51:52.267276 RX DQ/DQS(RDDQC) : PASS
2133 10:51:52.267842 TX DQ/DQS : PASS
2134 10:51:52.269380 RX DATLAT : PASS
2135 10:51:52.273348 RX DQ/DQS(Engine): PASS
2136 10:51:52.273914 TX OE : NO K
2137 10:51:52.276239 All Pass.
2138 10:51:52.276800
2139 10:51:52.277168 DramC Write-DBI off
2140 10:51:52.279408 PER_BANK_REFRESH: Hybrid Mode
2141 10:51:52.279969 TX_TRACKING: ON
2142 10:51:52.282764 [GetDramInforAfterCalByMRR] Vendor 6.
2143 10:51:52.290023 [GetDramInforAfterCalByMRR] Revision 606.
2144 10:51:52.292638 [GetDramInforAfterCalByMRR] Revision 2 0.
2145 10:51:52.293180 MR0 0x3b3b
2146 10:51:52.293553 MR8 0x5151
2147 10:51:52.295704 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 10:51:52.296270
2149 10:51:52.298991 MR0 0x3b3b
2150 10:51:52.299563 MR8 0x5151
2151 10:51:52.302665 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2152 10:51:52.303203
2153 10:51:52.312675 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2154 10:51:52.315788 [FAST_K] Save calibration result to emmc
2155 10:51:52.318777 [FAST_K] Save calibration result to emmc
2156 10:51:52.322487 dram_init: config_dvfs: 1
2157 10:51:52.325256 dramc_set_vcore_voltage set vcore to 662500
2158 10:51:52.328989 Read voltage for 1200, 2
2159 10:51:52.329553 Vio18 = 0
2160 10:51:52.329930 Vcore = 662500
2161 10:51:52.331950 Vdram = 0
2162 10:51:52.332617 Vddq = 0
2163 10:51:52.333000 Vmddr = 0
2164 10:51:52.338474 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2165 10:51:52.341930 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2166 10:51:52.345425 MEM_TYPE=3, freq_sel=15
2167 10:51:52.348772 sv_algorithm_assistance_LP4_1600
2168 10:51:52.352456 ============ PULL DRAM RESETB DOWN ============
2169 10:51:52.359421 ========== PULL DRAM RESETB DOWN end =========
2170 10:51:52.361907 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2171 10:51:52.364955 ===================================
2172 10:51:52.368733 LPDDR4 DRAM CONFIGURATION
2173 10:51:52.371986 ===================================
2174 10:51:52.372614 EX_ROW_EN[0] = 0x0
2175 10:51:52.375850 EX_ROW_EN[1] = 0x0
2176 10:51:52.376452 LP4Y_EN = 0x0
2177 10:51:52.378609 WORK_FSP = 0x0
2178 10:51:52.379175 WL = 0x4
2179 10:51:52.381771 RL = 0x4
2180 10:51:52.382334 BL = 0x2
2181 10:51:52.385244 RPST = 0x0
2182 10:51:52.385811 RD_PRE = 0x0
2183 10:51:52.388010 WR_PRE = 0x1
2184 10:51:52.391441 WR_PST = 0x0
2185 10:51:52.392007 DBI_WR = 0x0
2186 10:51:52.394745 DBI_RD = 0x0
2187 10:51:52.395205 OTF = 0x1
2188 10:51:52.398673 ===================================
2189 10:51:52.401723 ===================================
2190 10:51:52.402294 ANA top config
2191 10:51:52.404603 ===================================
2192 10:51:52.408133 DLL_ASYNC_EN = 0
2193 10:51:52.411393 ALL_SLAVE_EN = 0
2194 10:51:52.414449 NEW_RANK_MODE = 1
2195 10:51:52.417630 DLL_IDLE_MODE = 1
2196 10:51:52.418191 LP45_APHY_COMB_EN = 1
2197 10:51:52.421123 TX_ODT_DIS = 1
2198 10:51:52.425295 NEW_8X_MODE = 1
2199 10:51:52.427429 ===================================
2200 10:51:52.430956 ===================================
2201 10:51:52.434489 data_rate = 2400
2202 10:51:52.438286 CKR = 1
2203 10:51:52.438852 DQ_P2S_RATIO = 8
2204 10:51:52.441365 ===================================
2205 10:51:52.444525 CA_P2S_RATIO = 8
2206 10:51:52.448422 DQ_CA_OPEN = 0
2207 10:51:52.452400 DQ_SEMI_OPEN = 0
2208 10:51:52.454865 CA_SEMI_OPEN = 0
2209 10:51:52.457975 CA_FULL_RATE = 0
2210 10:51:52.458545 DQ_CKDIV4_EN = 0
2211 10:51:52.461083 CA_CKDIV4_EN = 0
2212 10:51:52.464579 CA_PREDIV_EN = 0
2213 10:51:52.467739 PH8_DLY = 17
2214 10:51:52.471319 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2215 10:51:52.474436 DQ_AAMCK_DIV = 4
2216 10:51:52.475004 CA_AAMCK_DIV = 4
2217 10:51:52.478152 CA_ADMCK_DIV = 4
2218 10:51:52.481340 DQ_TRACK_CA_EN = 0
2219 10:51:52.484385 CA_PICK = 1200
2220 10:51:52.487814 CA_MCKIO = 1200
2221 10:51:52.491102 MCKIO_SEMI = 0
2222 10:51:52.494183 PLL_FREQ = 2366
2223 10:51:52.498233 DQ_UI_PI_RATIO = 32
2224 10:51:52.498698 CA_UI_PI_RATIO = 0
2225 10:51:52.500724 ===================================
2226 10:51:52.503922 ===================================
2227 10:51:52.507606 memory_type:LPDDR4
2228 10:51:52.510919 GP_NUM : 10
2229 10:51:52.511483 SRAM_EN : 1
2230 10:51:52.514988 MD32_EN : 0
2231 10:51:52.517707 ===================================
2232 10:51:52.520639 [ANA_INIT] >>>>>>>>>>>>>>
2233 10:51:52.521105 <<<<<< [CONFIGURE PHASE]: ANA_TX
2234 10:51:52.527714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2235 10:51:52.530408 ===================================
2236 10:51:52.530882 data_rate = 2400,PCW = 0X5b00
2237 10:51:52.534849 ===================================
2238 10:51:52.537333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2239 10:51:52.544220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2240 10:51:52.550939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 10:51:52.554019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2242 10:51:52.556879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2243 10:51:52.560872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2244 10:51:52.563827 [ANA_INIT] flow start
2245 10:51:52.564421 [ANA_INIT] PLL >>>>>>>>
2246 10:51:52.567257 [ANA_INIT] PLL <<<<<<<<
2247 10:51:52.570790 [ANA_INIT] MIDPI >>>>>>>>
2248 10:51:52.573721 [ANA_INIT] MIDPI <<<<<<<<
2249 10:51:52.574287 [ANA_INIT] DLL >>>>>>>>
2250 10:51:52.576910 [ANA_INIT] DLL <<<<<<<<
2251 10:51:52.580843 [ANA_INIT] flow end
2252 10:51:52.583852 ============ LP4 DIFF to SE enter ============
2253 10:51:52.587755 ============ LP4 DIFF to SE exit ============
2254 10:51:52.590317 [ANA_INIT] <<<<<<<<<<<<<
2255 10:51:52.593978 [Flow] Enable top DCM control >>>>>
2256 10:51:52.597478 [Flow] Enable top DCM control <<<<<
2257 10:51:52.600363 Enable DLL master slave shuffle
2258 10:51:52.604113 ==============================================================
2259 10:51:52.607412 Gating Mode config
2260 10:51:52.610132 ==============================================================
2261 10:51:52.613566 Config description:
2262 10:51:52.624118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2263 10:51:52.630010 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2264 10:51:52.633401 SELPH_MODE 0: By rank 1: By Phase
2265 10:51:52.640126 ==============================================================
2266 10:51:52.642941 GAT_TRACK_EN = 1
2267 10:51:52.646802 RX_GATING_MODE = 2
2268 10:51:52.649994 RX_GATING_TRACK_MODE = 2
2269 10:51:52.653775 SELPH_MODE = 1
2270 10:51:52.656347 PICG_EARLY_EN = 1
2271 10:51:52.660672 VALID_LAT_VALUE = 1
2272 10:51:52.663170 ==============================================================
2273 10:51:52.667427 Enter into Gating configuration >>>>
2274 10:51:52.669953 Exit from Gating configuration <<<<
2275 10:51:52.673173 Enter into DVFS_PRE_config >>>>>
2276 10:51:52.686392 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2277 10:51:52.686963 Exit from DVFS_PRE_config <<<<<
2278 10:51:52.689698 Enter into PICG configuration >>>>
2279 10:51:52.693478 Exit from PICG configuration <<<<
2280 10:51:52.696254 [RX_INPUT] configuration >>>>>
2281 10:51:52.699597 [RX_INPUT] configuration <<<<<
2282 10:51:52.706366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2283 10:51:52.710611 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2284 10:51:52.716329 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 10:51:52.722859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 10:51:52.729529 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2287 10:51:52.735532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2288 10:51:52.739351 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2289 10:51:52.742278 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2290 10:51:52.745731 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2291 10:51:52.752242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2292 10:51:52.755708 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2293 10:51:52.759406 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2294 10:51:52.763123 ===================================
2295 10:51:52.765768 LPDDR4 DRAM CONFIGURATION
2296 10:51:52.769522 ===================================
2297 10:51:52.772420 EX_ROW_EN[0] = 0x0
2298 10:51:52.772881 EX_ROW_EN[1] = 0x0
2299 10:51:52.776488 LP4Y_EN = 0x0
2300 10:51:52.777044 WORK_FSP = 0x0
2301 10:51:52.779448 WL = 0x4
2302 10:51:52.780004 RL = 0x4
2303 10:51:52.782436 BL = 0x2
2304 10:51:52.782991 RPST = 0x0
2305 10:51:52.786455 RD_PRE = 0x0
2306 10:51:52.787022 WR_PRE = 0x1
2307 10:51:52.788951 WR_PST = 0x0
2308 10:51:52.789500 DBI_WR = 0x0
2309 10:51:52.792690 DBI_RD = 0x0
2310 10:51:52.793246 OTF = 0x1
2311 10:51:52.795707 ===================================
2312 10:51:52.799193 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2313 10:51:52.806054 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2314 10:51:52.808864 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 10:51:52.812391 ===================================
2316 10:51:52.815884 LPDDR4 DRAM CONFIGURATION
2317 10:51:52.819579 ===================================
2318 10:51:52.820172 EX_ROW_EN[0] = 0x10
2319 10:51:52.822155 EX_ROW_EN[1] = 0x0
2320 10:51:52.825273 LP4Y_EN = 0x0
2321 10:51:52.825829 WORK_FSP = 0x0
2322 10:51:52.828910 WL = 0x4
2323 10:51:52.829464 RL = 0x4
2324 10:51:52.832627 BL = 0x2
2325 10:51:52.833189 RPST = 0x0
2326 10:51:52.835124 RD_PRE = 0x0
2327 10:51:52.835581 WR_PRE = 0x1
2328 10:51:52.839230 WR_PST = 0x0
2329 10:51:52.839687 DBI_WR = 0x0
2330 10:51:52.841970 DBI_RD = 0x0
2331 10:51:52.842417 OTF = 0x1
2332 10:51:52.845614 ===================================
2333 10:51:52.851503 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2334 10:51:52.851954 ==
2335 10:51:52.855197 Dram Type= 6, Freq= 0, CH_0, rank 0
2336 10:51:52.858251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2337 10:51:52.861941 ==
2338 10:51:52.862347 [Duty_Offset_Calibration]
2339 10:51:52.864747 B0:2 B1:0 CA:4
2340 10:51:52.865033
2341 10:51:52.867824 [DutyScan_Calibration_Flow] k_type=0
2342 10:51:52.875891
2343 10:51:52.876294 ==CLK 0==
2344 10:51:52.879328 Final CLK duty delay cell = -4
2345 10:51:52.882730 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2346 10:51:52.885902 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2347 10:51:52.889135 [-4] AVG Duty = 4953%(X100)
2348 10:51:52.889516
2349 10:51:52.892672 CH0 CLK Duty spec in!! Max-Min= 218%
2350 10:51:52.896120 [DutyScan_Calibration_Flow] ====Done====
2351 10:51:52.896496
2352 10:51:52.899476 [DutyScan_Calibration_Flow] k_type=1
2353 10:51:52.914724
2354 10:51:52.915270 ==DQS 0 ==
2355 10:51:52.918675 Final DQS duty delay cell = -4
2356 10:51:52.921961 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2357 10:51:52.924931 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2358 10:51:52.928189 [-4] AVG Duty = 4922%(X100)
2359 10:51:52.928731
2360 10:51:52.929090 ==DQS 1 ==
2361 10:51:52.931537 Final DQS duty delay cell = 0
2362 10:51:52.934678 [0] MAX Duty = 5125%(X100), DQS PI = 6
2363 10:51:52.938204 [0] MIN Duty = 5000%(X100), DQS PI = 0
2364 10:51:52.941689 [0] AVG Duty = 5062%(X100)
2365 10:51:52.942233
2366 10:51:52.944724 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2367 10:51:52.945271
2368 10:51:52.948149 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2369 10:51:52.951115 [DutyScan_Calibration_Flow] ====Done====
2370 10:51:52.951663
2371 10:51:52.954668 [DutyScan_Calibration_Flow] k_type=3
2372 10:51:52.972126
2373 10:51:52.972720 ==DQM 0 ==
2374 10:51:52.975098 Final DQM duty delay cell = 0
2375 10:51:52.978226 [0] MAX Duty = 5093%(X100), DQS PI = 18
2376 10:51:52.981686 [0] MIN Duty = 4875%(X100), DQS PI = 44
2377 10:51:52.984739 [0] AVG Duty = 4984%(X100)
2378 10:51:52.985187
2379 10:51:52.985542 ==DQM 1 ==
2380 10:51:52.988186 Final DQM duty delay cell = 0
2381 10:51:52.992138 [0] MAX Duty = 4969%(X100), DQS PI = 2
2382 10:51:52.995059 [0] MIN Duty = 4876%(X100), DQS PI = 44
2383 10:51:52.997976 [0] AVG Duty = 4922%(X100)
2384 10:51:52.998429
2385 10:51:53.001755 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2386 10:51:53.002355
2387 10:51:53.005294 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2388 10:51:53.007975 [DutyScan_Calibration_Flow] ====Done====
2389 10:51:53.008558
2390 10:51:53.011716 [DutyScan_Calibration_Flow] k_type=2
2391 10:51:53.028189
2392 10:51:53.028733 ==DQ 0 ==
2393 10:51:53.031728 Final DQ duty delay cell = 0
2394 10:51:53.034212 [0] MAX Duty = 5125%(X100), DQS PI = 18
2395 10:51:53.037393 [0] MIN Duty = 4969%(X100), DQS PI = 50
2396 10:51:53.041170 [0] AVG Duty = 5047%(X100)
2397 10:51:53.041714
2398 10:51:53.042073 ==DQ 1 ==
2399 10:51:53.044613 Final DQ duty delay cell = 0
2400 10:51:53.048023 [0] MAX Duty = 5156%(X100), DQS PI = 4
2401 10:51:53.051099 [0] MIN Duty = 4938%(X100), DQS PI = 14
2402 10:51:53.051651 [0] AVG Duty = 5047%(X100)
2403 10:51:53.054506
2404 10:51:53.057523 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2405 10:51:53.058069
2406 10:51:53.060857 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2407 10:51:53.063958 [DutyScan_Calibration_Flow] ====Done====
2408 10:51:53.064537 ==
2409 10:51:53.067664 Dram Type= 6, Freq= 0, CH_1, rank 0
2410 10:51:53.070821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2411 10:51:53.071374 ==
2412 10:51:53.074074 [Duty_Offset_Calibration]
2413 10:51:53.074555 B0:0 B1:-1 CA:3
2414 10:51:53.074915
2415 10:51:53.077713 [DutyScan_Calibration_Flow] k_type=0
2416 10:51:53.087401
2417 10:51:53.087945 ==CLK 0==
2418 10:51:53.090230 Final CLK duty delay cell = -4
2419 10:51:53.093650 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2420 10:51:53.097403 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2421 10:51:53.100078 [-4] AVG Duty = 4938%(X100)
2422 10:51:53.100525
2423 10:51:53.104232 CH1 CLK Duty spec in!! Max-Min= 124%
2424 10:51:53.107112 [DutyScan_Calibration_Flow] ====Done====
2425 10:51:53.107524
2426 10:51:53.110210 [DutyScan_Calibration_Flow] k_type=1
2427 10:51:53.126501
2428 10:51:53.127047 ==DQS 0 ==
2429 10:51:53.128781 Final DQS duty delay cell = 0
2430 10:51:53.132639 [0] MAX Duty = 5187%(X100), DQS PI = 18
2431 10:51:53.135466 [0] MIN Duty = 4907%(X100), DQS PI = 38
2432 10:51:53.139259 [0] AVG Duty = 5047%(X100)
2433 10:51:53.139822
2434 10:51:53.140240 ==DQS 1 ==
2435 10:51:53.142842 Final DQS duty delay cell = -4
2436 10:51:53.145425 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2437 10:51:53.148884 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2438 10:51:53.152209 [-4] AVG Duty = 4953%(X100)
2439 10:51:53.152659
2440 10:51:53.155251 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2441 10:51:53.155699
2442 10:51:53.159041 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2443 10:51:53.162309 [DutyScan_Calibration_Flow] ====Done====
2444 10:51:53.162869
2445 10:51:53.166154 [DutyScan_Calibration_Flow] k_type=3
2446 10:51:53.183114
2447 10:51:53.183668 ==DQM 0 ==
2448 10:51:53.186603 Final DQM duty delay cell = 0
2449 10:51:53.188992 [0] MAX Duty = 5031%(X100), DQS PI = 28
2450 10:51:53.192858 [0] MIN Duty = 4782%(X100), DQS PI = 38
2451 10:51:53.196219 [0] AVG Duty = 4906%(X100)
2452 10:51:53.196769
2453 10:51:53.197135 ==DQM 1 ==
2454 10:51:53.199064 Final DQM duty delay cell = 0
2455 10:51:53.202951 [0] MAX Duty = 4969%(X100), DQS PI = 32
2456 10:51:53.206083 [0] MIN Duty = 4844%(X100), DQS PI = 0
2457 10:51:53.208990 [0] AVG Duty = 4906%(X100)
2458 10:51:53.209549
2459 10:51:53.213080 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2460 10:51:53.213637
2461 10:51:53.215686 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2462 10:51:53.219683 [DutyScan_Calibration_Flow] ====Done====
2463 10:51:53.220280
2464 10:51:53.222084 [DutyScan_Calibration_Flow] k_type=2
2465 10:51:53.239058
2466 10:51:53.239662 ==DQ 0 ==
2467 10:51:53.242244 Final DQ duty delay cell = -4
2468 10:51:53.244886 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2469 10:51:53.248395 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2470 10:51:53.251819 [-4] AVG Duty = 4922%(X100)
2471 10:51:53.252305
2472 10:51:53.252674 ==DQ 1 ==
2473 10:51:53.255065 Final DQ duty delay cell = 0
2474 10:51:53.258440 [0] MAX Duty = 5031%(X100), DQS PI = 34
2475 10:51:53.262225 [0] MIN Duty = 4844%(X100), DQS PI = 0
2476 10:51:53.264772 [0] AVG Duty = 4937%(X100)
2477 10:51:53.265230
2478 10:51:53.268195 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2479 10:51:53.268759
2480 10:51:53.271649 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2481 10:51:53.275175 [DutyScan_Calibration_Flow] ====Done====
2482 10:51:53.278406 nWR fixed to 30
2483 10:51:53.281191 [ModeRegInit_LP4] CH0 RK0
2484 10:51:53.281668 [ModeRegInit_LP4] CH0 RK1
2485 10:51:53.284680 [ModeRegInit_LP4] CH1 RK0
2486 10:51:53.289098 [ModeRegInit_LP4] CH1 RK1
2487 10:51:53.289658 match AC timing 7
2488 10:51:53.294192 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2489 10:51:53.297724 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2490 10:51:53.300906 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2491 10:51:53.308135 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2492 10:51:53.310809 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2493 10:51:53.311270 ==
2494 10:51:53.314936 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 10:51:53.317749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 10:51:53.318311 ==
2497 10:51:53.324665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 10:51:53.330784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 10:51:53.338855 [CA 0] Center 39 (9~70) winsize 62
2500 10:51:53.341879 [CA 1] Center 39 (9~70) winsize 62
2501 10:51:53.345148 [CA 2] Center 35 (5~66) winsize 62
2502 10:51:53.348631 [CA 3] Center 35 (5~66) winsize 62
2503 10:51:53.351907 [CA 4] Center 33 (3~64) winsize 62
2504 10:51:53.354998 [CA 5] Center 33 (3~64) winsize 62
2505 10:51:53.355559
2506 10:51:53.358473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 10:51:53.358930
2508 10:51:53.361871 [CATrainingPosCal] consider 1 rank data
2509 10:51:53.364879 u2DelayCellTimex100 = 270/100 ps
2510 10:51:53.368605 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 10:51:53.375098 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 10:51:53.378051 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 10:51:53.381799 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 10:51:53.385178 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2515 10:51:53.388301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2516 10:51:53.388864
2517 10:51:53.391653 CA PerBit enable=1, Macro0, CA PI delay=33
2518 10:51:53.392242
2519 10:51:53.394725 [CBTSetCACLKResult] CA Dly = 33
2520 10:51:53.395282 CS Dly: 7 (0~38)
2521 10:51:53.398142 ==
2522 10:51:53.401343 Dram Type= 6, Freq= 0, CH_0, rank 1
2523 10:51:53.404916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 10:51:53.405427 ==
2525 10:51:53.408457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 10:51:53.414600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 10:51:53.424366 [CA 0] Center 39 (9~70) winsize 62
2528 10:51:53.427394 [CA 1] Center 39 (9~70) winsize 62
2529 10:51:53.431072 [CA 2] Center 35 (5~66) winsize 62
2530 10:51:53.434081 [CA 3] Center 35 (5~66) winsize 62
2531 10:51:53.437231 [CA 4] Center 34 (4~65) winsize 62
2532 10:51:53.440692 [CA 5] Center 33 (3~64) winsize 62
2533 10:51:53.441307
2534 10:51:53.444411 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2535 10:51:53.444869
2536 10:51:53.447391 [CATrainingPosCal] consider 2 rank data
2537 10:51:53.450918 u2DelayCellTimex100 = 270/100 ps
2538 10:51:53.454530 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2539 10:51:53.461725 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2540 10:51:53.464127 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 10:51:53.467671 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 10:51:53.470647 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2543 10:51:53.473998 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2544 10:51:53.474561
2545 10:51:53.477006 CA PerBit enable=1, Macro0, CA PI delay=33
2546 10:51:53.477572
2547 10:51:53.480685 [CBTSetCACLKResult] CA Dly = 33
2548 10:51:53.481248 CS Dly: 8 (0~41)
2549 10:51:53.484141
2550 10:51:53.487007 ----->DramcWriteLeveling(PI) begin...
2551 10:51:53.487475 ==
2552 10:51:53.490195 Dram Type= 6, Freq= 0, CH_0, rank 0
2553 10:51:53.494394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 10:51:53.494959 ==
2555 10:51:53.497328 Write leveling (Byte 0): 32 => 32
2556 10:51:53.500488 Write leveling (Byte 1): 27 => 27
2557 10:51:53.503942 DramcWriteLeveling(PI) end<-----
2558 10:51:53.504559
2559 10:51:53.504931 ==
2560 10:51:53.507002 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 10:51:53.510155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 10:51:53.510777 ==
2563 10:51:53.513702 [Gating] SW mode calibration
2564 10:51:53.520154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2565 10:51:53.527019 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2566 10:51:53.530442 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2567 10:51:53.533584 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2568 10:51:53.540687 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 10:51:53.543678 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 10:51:53.547000 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 10:51:53.553713 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 10:51:53.557230 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 10:51:53.560417 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2574 10:51:53.566648 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2575 10:51:53.569997 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2576 10:51:53.573416 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 10:51:53.580169 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 10:51:53.583439 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 10:51:53.587059 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 10:51:53.593357 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
2581 10:51:53.596475 1 0 28 | B1->B0 | 2323 403f | 0 1 | (0 0) (0 0)
2582 10:51:53.600566 1 1 0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2583 10:51:53.606450 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 10:51:53.610265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 10:51:53.612832 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 10:51:53.619727 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 10:51:53.622793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 10:51:53.626661 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2589 10:51:53.629574 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2590 10:51:53.636634 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2591 10:51:53.639575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2592 10:51:53.643409 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 10:51:53.649656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 10:51:53.652703 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 10:51:53.656612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 10:51:53.663133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 10:51:53.666355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 10:51:53.669230 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 10:51:53.676211 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 10:51:53.679595 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 10:51:53.682837 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 10:51:53.690033 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 10:51:53.692828 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 10:51:53.696156 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 10:51:53.702392 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2606 10:51:53.702864 Total UI for P1: 0, mck2ui 16
2607 10:51:53.709835 best dqsien dly found for B0: ( 1, 3, 26)
2608 10:51:53.712366 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2609 10:51:53.716122 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2610 10:51:53.722504 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 10:51:53.723090 Total UI for P1: 0, mck2ui 16
2612 10:51:53.729002 best dqsien dly found for B1: ( 1, 4, 2)
2613 10:51:53.732543 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2614 10:51:53.736162 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2615 10:51:53.736636
2616 10:51:53.739102 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2617 10:51:53.742109 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2618 10:51:53.746759 [Gating] SW calibration Done
2619 10:51:53.747320 ==
2620 10:51:53.749041 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 10:51:53.752740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 10:51:53.753208 ==
2623 10:51:53.755628 RX Vref Scan: 0
2624 10:51:53.756125
2625 10:51:53.756502 RX Vref 0 -> 0, step: 1
2626 10:51:53.756852
2627 10:51:53.759074 RX Delay -40 -> 252, step: 8
2628 10:51:53.762961 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2629 10:51:53.769062 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2630 10:51:53.772461 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2631 10:51:53.776224 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2632 10:51:53.779169 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2633 10:51:53.782409 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2634 10:51:53.789345 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2635 10:51:53.792149 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2636 10:51:53.795973 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2637 10:51:53.798902 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2638 10:51:53.802180 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2639 10:51:53.805082 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2640 10:51:53.812747 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2641 10:51:53.816149 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2642 10:51:53.819119 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2643 10:51:53.822353 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2644 10:51:53.825232 ==
2645 10:51:53.825808 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 10:51:53.832286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 10:51:53.832856 ==
2648 10:51:53.833253 DQS Delay:
2649 10:51:53.834858 DQS0 = 0, DQS1 = 0
2650 10:51:53.835317 DQM Delay:
2651 10:51:53.838077 DQM0 = 117, DQM1 = 108
2652 10:51:53.838539 DQ Delay:
2653 10:51:53.841902 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2654 10:51:53.845389 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2655 10:51:53.848596 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2656 10:51:53.851632 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2657 10:51:53.852151
2658 10:51:53.852523
2659 10:51:53.852863 ==
2660 10:51:53.855185 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 10:51:53.861931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 10:51:53.862494 ==
2663 10:51:53.862865
2664 10:51:53.863208
2665 10:51:53.863541 TX Vref Scan disable
2666 10:51:53.865379 == TX Byte 0 ==
2667 10:51:53.868828 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 10:51:53.874955 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 10:51:53.875515 == TX Byte 1 ==
2670 10:51:53.878614 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2671 10:51:53.885552 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2672 10:51:53.886116 ==
2673 10:51:53.888698 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 10:51:53.891869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 10:51:53.892465 ==
2676 10:51:53.904083 TX Vref=22, minBit 3, minWin=25, winSum=411
2677 10:51:53.906952 TX Vref=24, minBit 4, minWin=25, winSum=420
2678 10:51:53.909966 TX Vref=26, minBit 4, minWin=25, winSum=424
2679 10:51:53.913881 TX Vref=28, minBit 5, minWin=26, winSum=429
2680 10:51:53.916915 TX Vref=30, minBit 0, minWin=26, winSum=426
2681 10:51:53.923213 TX Vref=32, minBit 5, minWin=26, winSum=427
2682 10:51:53.927486 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 28
2683 10:51:53.928101
2684 10:51:53.930359 Final TX Range 1 Vref 28
2685 10:51:53.930923
2686 10:51:53.931293 ==
2687 10:51:53.932959 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 10:51:53.936260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 10:51:53.939781 ==
2690 10:51:53.940448
2691 10:51:53.940833
2692 10:51:53.941180 TX Vref Scan disable
2693 10:51:53.943342 == TX Byte 0 ==
2694 10:51:53.946500 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2695 10:51:53.952856 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2696 10:51:53.953324 == TX Byte 1 ==
2697 10:51:53.956648 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2698 10:51:53.963325 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2699 10:51:53.963890
2700 10:51:53.964318 [DATLAT]
2701 10:51:53.964668 Freq=1200, CH0 RK0
2702 10:51:53.965007
2703 10:51:53.966373 DATLAT Default: 0xd
2704 10:51:53.969203 0, 0xFFFF, sum = 0
2705 10:51:53.969673 1, 0xFFFF, sum = 0
2706 10:51:53.973457 2, 0xFFFF, sum = 0
2707 10:51:53.974037 3, 0xFFFF, sum = 0
2708 10:51:53.976177 4, 0xFFFF, sum = 0
2709 10:51:53.976741 5, 0xFFFF, sum = 0
2710 10:51:53.979903 6, 0xFFFF, sum = 0
2711 10:51:53.980510 7, 0xFFFF, sum = 0
2712 10:51:53.982435 8, 0xFFFF, sum = 0
2713 10:51:53.982904 9, 0xFFFF, sum = 0
2714 10:51:53.986616 10, 0xFFFF, sum = 0
2715 10:51:53.987190 11, 0xFFFF, sum = 0
2716 10:51:53.989084 12, 0x0, sum = 1
2717 10:51:53.989509 13, 0x0, sum = 2
2718 10:51:53.992712 14, 0x0, sum = 3
2719 10:51:53.993239 15, 0x0, sum = 4
2720 10:51:53.996079 best_step = 13
2721 10:51:53.996611
2722 10:51:53.996947 ==
2723 10:51:53.999177 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 10:51:54.002758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 10:51:54.003180 ==
2726 10:51:54.003518 RX Vref Scan: 1
2727 10:51:54.006059
2728 10:51:54.006607 Set Vref Range= 32 -> 127
2729 10:51:54.006949
2730 10:51:54.009395 RX Vref 32 -> 127, step: 1
2731 10:51:54.009918
2732 10:51:54.013116 RX Delay -21 -> 252, step: 4
2733 10:51:54.013643
2734 10:51:54.016009 Set Vref, RX VrefLevel [Byte0]: 32
2735 10:51:54.019862 [Byte1]: 32
2736 10:51:54.020423
2737 10:51:54.022785 Set Vref, RX VrefLevel [Byte0]: 33
2738 10:51:54.025951 [Byte1]: 33
2739 10:51:54.029727
2740 10:51:54.030254 Set Vref, RX VrefLevel [Byte0]: 34
2741 10:51:54.033363 [Byte1]: 34
2742 10:51:54.037844
2743 10:51:54.038323 Set Vref, RX VrefLevel [Byte0]: 35
2744 10:51:54.040706 [Byte1]: 35
2745 10:51:54.045920
2746 10:51:54.046444 Set Vref, RX VrefLevel [Byte0]: 36
2747 10:51:54.049403 [Byte1]: 36
2748 10:51:54.053470
2749 10:51:54.054040 Set Vref, RX VrefLevel [Byte0]: 37
2750 10:51:54.056860 [Byte1]: 37
2751 10:51:54.061302
2752 10:51:54.061869 Set Vref, RX VrefLevel [Byte0]: 38
2753 10:51:54.064384 [Byte1]: 38
2754 10:51:54.069712
2755 10:51:54.070262 Set Vref, RX VrefLevel [Byte0]: 39
2756 10:51:54.072261 [Byte1]: 39
2757 10:51:54.077150
2758 10:51:54.077674 Set Vref, RX VrefLevel [Byte0]: 40
2759 10:51:54.080594 [Byte1]: 40
2760 10:51:54.085318
2761 10:51:54.085885 Set Vref, RX VrefLevel [Byte0]: 41
2762 10:51:54.088761 [Byte1]: 41
2763 10:51:54.093465
2764 10:51:54.094036 Set Vref, RX VrefLevel [Byte0]: 42
2765 10:51:54.096896 [Byte1]: 42
2766 10:51:54.101394
2767 10:51:54.101953 Set Vref, RX VrefLevel [Byte0]: 43
2768 10:51:54.104388 [Byte1]: 43
2769 10:51:54.108942
2770 10:51:54.109510 Set Vref, RX VrefLevel [Byte0]: 44
2771 10:51:54.112584 [Byte1]: 44
2772 10:51:54.116719
2773 10:51:54.117305 Set Vref, RX VrefLevel [Byte0]: 45
2774 10:51:54.120405 [Byte1]: 45
2775 10:51:54.125133
2776 10:51:54.125695 Set Vref, RX VrefLevel [Byte0]: 46
2777 10:51:54.128149 [Byte1]: 46
2778 10:51:54.132740
2779 10:51:54.133303 Set Vref, RX VrefLevel [Byte0]: 47
2780 10:51:54.136184 [Byte1]: 47
2781 10:51:54.140779
2782 10:51:54.141373 Set Vref, RX VrefLevel [Byte0]: 48
2783 10:51:54.144077 [Byte1]: 48
2784 10:51:54.148450
2785 10:51:54.149012 Set Vref, RX VrefLevel [Byte0]: 49
2786 10:51:54.151496 [Byte1]: 49
2787 10:51:54.156422
2788 10:51:54.156984 Set Vref, RX VrefLevel [Byte0]: 50
2789 10:51:54.159803 [Byte1]: 50
2790 10:51:54.164472
2791 10:51:54.165036 Set Vref, RX VrefLevel [Byte0]: 51
2792 10:51:54.167951 [Byte1]: 51
2793 10:51:54.172277
2794 10:51:54.172841 Set Vref, RX VrefLevel [Byte0]: 52
2795 10:51:54.175564 [Byte1]: 52
2796 10:51:54.181102
2797 10:51:54.181697 Set Vref, RX VrefLevel [Byte0]: 53
2798 10:51:54.183802 [Byte1]: 53
2799 10:51:54.188273
2800 10:51:54.188826 Set Vref, RX VrefLevel [Byte0]: 54
2801 10:51:54.192176 [Byte1]: 54
2802 10:51:54.196345
2803 10:51:54.196961 Set Vref, RX VrefLevel [Byte0]: 55
2804 10:51:54.199521 [Byte1]: 55
2805 10:51:54.204454
2806 10:51:54.205011 Set Vref, RX VrefLevel [Byte0]: 56
2807 10:51:54.207532 [Byte1]: 56
2808 10:51:54.212069
2809 10:51:54.212630 Set Vref, RX VrefLevel [Byte0]: 57
2810 10:51:54.215295 [Byte1]: 57
2811 10:51:54.219803
2812 10:51:54.220421 Set Vref, RX VrefLevel [Byte0]: 58
2813 10:51:54.223563 [Byte1]: 58
2814 10:51:54.228120
2815 10:51:54.228672 Set Vref, RX VrefLevel [Byte0]: 59
2816 10:51:54.231776 [Byte1]: 59
2817 10:51:54.236403
2818 10:51:54.236962 Set Vref, RX VrefLevel [Byte0]: 60
2819 10:51:54.238796 [Byte1]: 60
2820 10:51:54.243280
2821 10:51:54.243738 Set Vref, RX VrefLevel [Byte0]: 61
2822 10:51:54.247149 [Byte1]: 61
2823 10:51:54.251917
2824 10:51:54.254692 Set Vref, RX VrefLevel [Byte0]: 62
2825 10:51:54.258453 [Byte1]: 62
2826 10:51:54.259013
2827 10:51:54.261288 Set Vref, RX VrefLevel [Byte0]: 63
2828 10:51:54.264589 [Byte1]: 63
2829 10:51:54.265188
2830 10:51:54.267909 Set Vref, RX VrefLevel [Byte0]: 64
2831 10:51:54.270961 [Byte1]: 64
2832 10:51:54.275373
2833 10:51:54.275954 Set Vref, RX VrefLevel [Byte0]: 65
2834 10:51:54.279137 [Byte1]: 65
2835 10:51:54.284142
2836 10:51:54.284716 Set Vref, RX VrefLevel [Byte0]: 66
2837 10:51:54.286346 [Byte1]: 66
2838 10:51:54.291043
2839 10:51:54.291622 Final RX Vref Byte 0 = 51 to rank0
2840 10:51:54.295119 Final RX Vref Byte 1 = 49 to rank0
2841 10:51:54.297517 Final RX Vref Byte 0 = 51 to rank1
2842 10:51:54.300910 Final RX Vref Byte 1 = 49 to rank1==
2843 10:51:54.304423 Dram Type= 6, Freq= 0, CH_0, rank 0
2844 10:51:54.311122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 10:51:54.311663 ==
2846 10:51:54.312153 DQS Delay:
2847 10:51:54.314507 DQS0 = 0, DQS1 = 0
2848 10:51:54.315046 DQM Delay:
2849 10:51:54.315493 DQM0 = 117, DQM1 = 104
2850 10:51:54.317383 DQ Delay:
2851 10:51:54.320787 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2852 10:51:54.324318 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2853 10:51:54.328108 DQ8 =92, DQ9 =88, DQ10 =104, DQ11 =100
2854 10:51:54.332166 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
2855 10:51:54.332719
2856 10:51:54.333093
2857 10:51:54.340999 [DQSOSCAuto] RK0, (LSB)MR18= 0x2fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2858 10:51:54.341485 CH0 RK0: MR19=403, MR18=2FD
2859 10:51:54.347626 CH0_RK0: MR19=0x403, MR18=0x2FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2860 10:51:54.348086
2861 10:51:54.350519 ----->DramcWriteLeveling(PI) begin...
2862 10:51:54.351039 ==
2863 10:51:54.354629 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 10:51:54.360698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 10:51:54.361221 ==
2866 10:51:54.361564 Write leveling (Byte 0): 33 => 33
2867 10:51:54.364232 Write leveling (Byte 1): 25 => 25
2868 10:51:54.367030 DramcWriteLeveling(PI) end<-----
2869 10:51:54.367516
2870 10:51:54.367857 ==
2871 10:51:54.370489 Dram Type= 6, Freq= 0, CH_0, rank 1
2872 10:51:54.377272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 10:51:54.377809 ==
2874 10:51:54.380620 [Gating] SW mode calibration
2875 10:51:54.387549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2876 10:51:54.390504 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2877 10:51:54.397001 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2878 10:51:54.400837 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2879 10:51:54.404178 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 10:51:54.407624 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 10:51:54.414105 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 10:51:54.418018 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 10:51:54.423785 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2884 10:51:54.427160 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2885 10:51:54.431019 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2886 10:51:54.433479 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 10:51:54.440683 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 10:51:54.443591 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 10:51:54.447121 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 10:51:54.454009 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 10:51:54.457337 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2892 10:51:54.460492 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2893 10:51:54.467424 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
2894 10:51:54.470505 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 10:51:54.473789 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 10:51:54.479921 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 10:51:54.483658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 10:51:54.486926 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 10:51:54.494017 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2900 10:51:54.497451 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2901 10:51:54.500028 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2902 10:51:54.507024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 10:51:54.510693 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 10:51:54.513213 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 10:51:54.520083 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:51:54.524063 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:51:54.527055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 10:51:54.533749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 10:51:54.536676 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 10:51:54.539662 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 10:51:54.546598 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 10:51:54.550786 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 10:51:54.553056 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 10:51:54.559794 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 10:51:54.563963 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2916 10:51:54.566281 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2917 10:51:54.569859 Total UI for P1: 0, mck2ui 16
2918 10:51:54.573539 best dqsien dly found for B0: ( 1, 3, 24)
2919 10:51:54.576376 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2920 10:51:54.582897 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 10:51:54.586186 Total UI for P1: 0, mck2ui 16
2922 10:51:54.589655 best dqsien dly found for B1: ( 1, 3, 30)
2923 10:51:54.592848 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2924 10:51:54.596470 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2925 10:51:54.597024
2926 10:51:54.599633 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2927 10:51:54.602576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2928 10:51:54.605974 [Gating] SW calibration Done
2929 10:51:54.606447 ==
2930 10:51:54.609381 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 10:51:54.612520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 10:51:54.612955 ==
2933 10:51:54.616300 RX Vref Scan: 0
2934 10:51:54.616848
2935 10:51:54.619074 RX Vref 0 -> 0, step: 1
2936 10:51:54.619507
2937 10:51:54.619943 RX Delay -40 -> 252, step: 8
2938 10:51:54.625690 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2939 10:51:54.629425 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2940 10:51:54.632774 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2941 10:51:54.635941 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2942 10:51:54.638898 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2943 10:51:54.645966 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2944 10:51:54.649263 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2945 10:51:54.652454 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2946 10:51:54.655968 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2947 10:51:54.659145 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2948 10:51:54.665976 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2949 10:51:54.669141 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2950 10:51:54.672449 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2951 10:51:54.675753 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2952 10:51:54.682832 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2953 10:51:54.685358 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2954 10:51:54.685783 ==
2955 10:51:54.688714 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 10:51:54.692759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 10:51:54.693314 ==
2958 10:51:54.693693 DQS Delay:
2959 10:51:54.695391 DQS0 = 0, DQS1 = 0
2960 10:51:54.695943 DQM Delay:
2961 10:51:54.698416 DQM0 = 116, DQM1 = 106
2962 10:51:54.698885 DQ Delay:
2963 10:51:54.701613 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2964 10:51:54.705539 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2965 10:51:54.708971 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2966 10:51:54.715059 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2967 10:51:54.715484
2968 10:51:54.715820
2969 10:51:54.716217 ==
2970 10:51:54.718517 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 10:51:54.722272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 10:51:54.722795 ==
2973 10:51:54.723139
2974 10:51:54.723454
2975 10:51:54.725050 TX Vref Scan disable
2976 10:51:54.725475 == TX Byte 0 ==
2977 10:51:54.732200 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2978 10:51:54.734846 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2979 10:51:54.735291 == TX Byte 1 ==
2980 10:51:54.742131 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2981 10:51:54.745191 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2982 10:51:54.745816 ==
2983 10:51:54.748522 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 10:51:54.751889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 10:51:54.752469 ==
2986 10:51:54.765189 TX Vref=22, minBit 1, minWin=25, winSum=418
2987 10:51:54.768530 TX Vref=24, minBit 14, minWin=25, winSum=419
2988 10:51:54.771822 TX Vref=26, minBit 2, minWin=26, winSum=424
2989 10:51:54.775098 TX Vref=28, minBit 4, minWin=26, winSum=428
2990 10:51:54.778732 TX Vref=30, minBit 8, minWin=26, winSum=430
2991 10:51:54.784885 TX Vref=32, minBit 4, minWin=26, winSum=427
2992 10:51:54.788353 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
2993 10:51:54.788910
2994 10:51:54.791847 Final TX Range 1 Vref 30
2995 10:51:54.792428
2996 10:51:54.792801 ==
2997 10:51:54.795382 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 10:51:54.798540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 10:51:54.799097 ==
3000 10:51:54.801720
3001 10:51:54.802181
3002 10:51:54.802548 TX Vref Scan disable
3003 10:51:54.804864 == TX Byte 0 ==
3004 10:51:54.808018 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3005 10:51:54.815145 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3006 10:51:54.815731 == TX Byte 1 ==
3007 10:51:54.818651 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3008 10:51:54.824811 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3009 10:51:54.825375
3010 10:51:54.825747 [DATLAT]
3011 10:51:54.826115 Freq=1200, CH0 RK1
3012 10:51:54.826448
3013 10:51:54.828781 DATLAT Default: 0xd
3014 10:51:54.829242 0, 0xFFFF, sum = 0
3015 10:51:54.831539 1, 0xFFFF, sum = 0
3016 10:51:54.832138 2, 0xFFFF, sum = 0
3017 10:51:54.834635 3, 0xFFFF, sum = 0
3018 10:51:54.837841 4, 0xFFFF, sum = 0
3019 10:51:54.838281 5, 0xFFFF, sum = 0
3020 10:51:54.841131 6, 0xFFFF, sum = 0
3021 10:51:54.841555 7, 0xFFFF, sum = 0
3022 10:51:54.844806 8, 0xFFFF, sum = 0
3023 10:51:54.845360 9, 0xFFFF, sum = 0
3024 10:51:54.847965 10, 0xFFFF, sum = 0
3025 10:51:54.848425 11, 0xFFFF, sum = 0
3026 10:51:54.851940 12, 0x0, sum = 1
3027 10:51:54.852524 13, 0x0, sum = 2
3028 10:51:54.854840 14, 0x0, sum = 3
3029 10:51:54.855349 15, 0x0, sum = 4
3030 10:51:54.855691 best_step = 13
3031 10:51:54.858254
3032 10:51:54.858788 ==
3033 10:51:54.861630 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 10:51:54.864922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 10:51:54.865438 ==
3036 10:51:54.865781 RX Vref Scan: 0
3037 10:51:54.866092
3038 10:51:54.868179 RX Vref 0 -> 0, step: 1
3039 10:51:54.868685
3040 10:51:54.871650 RX Delay -21 -> 252, step: 4
3041 10:51:54.874692 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3042 10:51:54.881549 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3043 10:51:54.884679 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3044 10:51:54.888073 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3045 10:51:54.891166 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3046 10:51:54.894819 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3047 10:51:54.901404 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3048 10:51:54.904282 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3049 10:51:54.907688 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3050 10:51:54.911246 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3051 10:51:54.915128 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3052 10:51:54.921104 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3053 10:51:54.924333 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3054 10:51:54.927634 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3055 10:51:54.931008 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3056 10:51:54.934081 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3057 10:51:54.937673 ==
3058 10:51:54.940937 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 10:51:54.943970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 10:51:54.944416 ==
3061 10:51:54.944751 DQS Delay:
3062 10:51:54.947527 DQS0 = 0, DQS1 = 0
3063 10:51:54.947946 DQM Delay:
3064 10:51:54.951093 DQM0 = 115, DQM1 = 105
3065 10:51:54.951611 DQ Delay:
3066 10:51:54.954693 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3067 10:51:54.957444 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3068 10:51:54.960736 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3069 10:51:54.964451 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3070 10:51:54.964966
3071 10:51:54.965302
3072 10:51:54.974561 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3073 10:51:54.977587 CH0 RK1: MR19=303, MR18=FEFC
3074 10:51:54.980967 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3075 10:51:54.984286 [RxdqsGatingPostProcess] freq 1200
3076 10:51:54.991388 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3077 10:51:54.994768 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 10:51:54.997687 best DQS1 dly(2T, 0.5T) = (0, 12)
3079 10:51:55.000536 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 10:51:55.003827 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3081 10:51:55.007530 best DQS0 dly(2T, 0.5T) = (0, 11)
3082 10:51:55.010225 best DQS1 dly(2T, 0.5T) = (0, 11)
3083 10:51:55.013684 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3084 10:51:55.017463 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3085 10:51:55.020285 Pre-setting of DQS Precalculation
3086 10:51:55.024126 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3087 10:51:55.024684 ==
3088 10:51:55.027236 Dram Type= 6, Freq= 0, CH_1, rank 0
3089 10:51:55.031141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 10:51:55.031804 ==
3091 10:51:55.036664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 10:51:55.043561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 10:51:55.051490 [CA 0] Center 38 (8~68) winsize 61
3094 10:51:55.055017 [CA 1] Center 37 (7~68) winsize 62
3095 10:51:55.058232 [CA 2] Center 35 (5~65) winsize 61
3096 10:51:55.061388 [CA 3] Center 34 (4~64) winsize 61
3097 10:51:55.064510 [CA 4] Center 34 (5~64) winsize 60
3098 10:51:55.068113 [CA 5] Center 33 (3~63) winsize 61
3099 10:51:55.068669
3100 10:51:55.071210 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 10:51:55.071763
3102 10:51:55.074933 [CATrainingPosCal] consider 1 rank data
3103 10:51:55.077735 u2DelayCellTimex100 = 270/100 ps
3104 10:51:55.081565 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3105 10:51:55.084727 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 10:51:55.091164 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 10:51:55.094701 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 10:51:55.097935 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3109 10:51:55.101234 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3110 10:51:55.101795
3111 10:51:55.104781 CA PerBit enable=1, Macro0, CA PI delay=33
3112 10:51:55.105244
3113 10:51:55.107789 [CBTSetCACLKResult] CA Dly = 33
3114 10:51:55.108379 CS Dly: 4 (0~35)
3115 10:51:55.111237 ==
3116 10:51:55.111811 Dram Type= 6, Freq= 0, CH_1, rank 1
3117 10:51:55.117852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 10:51:55.118497 ==
3119 10:51:55.120751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 10:51:55.127483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 10:51:55.137101 [CA 0] Center 37 (7~68) winsize 62
3122 10:51:55.140222 [CA 1] Center 38 (8~68) winsize 61
3123 10:51:55.143711 [CA 2] Center 35 (5~65) winsize 61
3124 10:51:55.147098 [CA 3] Center 33 (3~64) winsize 62
3125 10:51:55.150524 [CA 4] Center 34 (4~64) winsize 61
3126 10:51:55.153241 [CA 5] Center 33 (3~63) winsize 61
3127 10:51:55.153697
3128 10:51:55.157256 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 10:51:55.157714
3130 10:51:55.159796 [CATrainingPosCal] consider 2 rank data
3131 10:51:55.163367 u2DelayCellTimex100 = 270/100 ps
3132 10:51:55.166358 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3133 10:51:55.174150 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3134 10:51:55.176529 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3135 10:51:55.180166 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 10:51:55.183924 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3137 10:51:55.186385 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3138 10:51:55.186802
3139 10:51:55.190049 CA PerBit enable=1, Macro0, CA PI delay=33
3140 10:51:55.190567
3141 10:51:55.193255 [CBTSetCACLKResult] CA Dly = 33
3142 10:51:55.193770 CS Dly: 6 (0~39)
3143 10:51:55.196707
3144 10:51:55.199857 ----->DramcWriteLeveling(PI) begin...
3145 10:51:55.200415 ==
3146 10:51:55.202873 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 10:51:55.206207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 10:51:55.206628 ==
3149 10:51:55.210182 Write leveling (Byte 0): 25 => 25
3150 10:51:55.212920 Write leveling (Byte 1): 28 => 28
3151 10:51:55.216138 DramcWriteLeveling(PI) end<-----
3152 10:51:55.216653
3153 10:51:55.216985 ==
3154 10:51:55.219986 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 10:51:55.222638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 10:51:55.223086 ==
3157 10:51:55.226626 [Gating] SW mode calibration
3158 10:51:55.233055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3159 10:51:55.239848 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3160 10:51:55.242455 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
3161 10:51:55.246085 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 10:51:55.252385 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 10:51:55.255752 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 10:51:55.259332 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 10:51:55.266587 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 10:51:55.269157 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3167 10:51:55.272699 0 15 28 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
3168 10:51:55.279477 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 10:51:55.282455 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 10:51:55.286010 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 10:51:55.292392 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 10:51:55.295758 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 10:51:55.299171 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 10:51:55.306207 1 0 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (1 1)
3175 10:51:55.309036 1 0 28 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
3176 10:51:55.312685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 10:51:55.319125 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 10:51:55.322788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 10:51:55.326268 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 10:51:55.332574 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 10:51:55.336288 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 10:51:55.338757 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3183 10:51:55.342489 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3184 10:51:55.349330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 10:51:55.351946 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 10:51:55.356068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 10:51:55.361969 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:51:55.366135 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:51:55.368498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 10:51:55.375534 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 10:51:55.378681 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 10:51:55.382428 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 10:51:55.389007 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 10:51:55.393059 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 10:51:55.395614 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 10:51:55.401900 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 10:51:55.405486 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 10:51:55.408235 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3199 10:51:55.415504 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3200 10:51:55.418389 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 10:51:55.421909 Total UI for P1: 0, mck2ui 16
3202 10:51:55.424819 best dqsien dly found for B0: ( 1, 3, 26)
3203 10:51:55.428686 Total UI for P1: 0, mck2ui 16
3204 10:51:55.431435 best dqsien dly found for B1: ( 1, 3, 28)
3205 10:51:55.434877 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3206 10:51:55.437703 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3207 10:51:55.438161
3208 10:51:55.441214 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3209 10:51:55.445122 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3210 10:51:55.447682 [Gating] SW calibration Done
3211 10:51:55.448306 ==
3212 10:51:55.451182 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 10:51:55.458369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 10:51:55.458875 ==
3215 10:51:55.459241 RX Vref Scan: 0
3216 10:51:55.459583
3217 10:51:55.460973 RX Vref 0 -> 0, step: 1
3218 10:51:55.461431
3219 10:51:55.464643 RX Delay -40 -> 252, step: 8
3220 10:51:55.467902 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3221 10:51:55.471496 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3222 10:51:55.474692 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3223 10:51:55.477944 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3224 10:51:55.484282 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3225 10:51:55.487878 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3226 10:51:55.491416 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3227 10:51:55.495146 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3228 10:51:55.498276 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3229 10:51:55.504514 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3230 10:51:55.507675 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3231 10:51:55.511363 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3232 10:51:55.514218 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3233 10:51:55.520970 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3234 10:51:55.524244 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3235 10:51:55.527488 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3236 10:51:55.528094 ==
3237 10:51:55.530728 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 10:51:55.534248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 10:51:55.534815 ==
3240 10:51:55.537364 DQS Delay:
3241 10:51:55.537827 DQS0 = 0, DQS1 = 0
3242 10:51:55.540392 DQM Delay:
3243 10:51:55.540855 DQM0 = 116, DQM1 = 113
3244 10:51:55.541223 DQ Delay:
3245 10:51:55.547488 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3246 10:51:55.550608 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3247 10:51:55.553916 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3248 10:51:55.557873 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3249 10:51:55.558356
3250 10:51:55.558846
3251 10:51:55.559306 ==
3252 10:51:55.560485 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 10:51:55.563795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 10:51:55.564269 ==
3255 10:51:55.564711
3256 10:51:55.565125
3257 10:51:55.567703 TX Vref Scan disable
3258 10:51:55.570424 == TX Byte 0 ==
3259 10:51:55.573403 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 10:51:55.576774 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 10:51:55.580654 == TX Byte 1 ==
3262 10:51:55.583280 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3263 10:51:55.586964 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3264 10:51:55.587509 ==
3265 10:51:55.590197 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 10:51:55.596382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 10:51:55.596922 ==
3268 10:51:55.607101 TX Vref=22, minBit 2, minWin=25, winSum=414
3269 10:51:55.610537 TX Vref=24, minBit 3, minWin=25, winSum=417
3270 10:51:55.613717 TX Vref=26, minBit 2, minWin=25, winSum=422
3271 10:51:55.617333 TX Vref=28, minBit 9, minWin=25, winSum=427
3272 10:51:55.620561 TX Vref=30, minBit 0, minWin=26, winSum=426
3273 10:51:55.627117 TX Vref=32, minBit 1, minWin=26, winSum=426
3274 10:51:55.630775 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
3275 10:51:55.631320
3276 10:51:55.633574 Final TX Range 1 Vref 30
3277 10:51:55.634114
3278 10:51:55.634564 ==
3279 10:51:55.637140 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 10:51:55.640494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 10:51:55.641007 ==
3282 10:51:55.643626
3283 10:51:55.644200
3284 10:51:55.644656 TX Vref Scan disable
3285 10:51:55.646993 == TX Byte 0 ==
3286 10:51:55.650088 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3287 10:51:55.653791 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3288 10:51:55.656969 == TX Byte 1 ==
3289 10:51:55.660374 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3290 10:51:55.666473 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3291 10:51:55.667018
3292 10:51:55.667471 [DATLAT]
3293 10:51:55.667891 Freq=1200, CH1 RK0
3294 10:51:55.668350
3295 10:51:55.671253 DATLAT Default: 0xd
3296 10:51:55.671793 0, 0xFFFF, sum = 0
3297 10:51:55.673426 1, 0xFFFF, sum = 0
3298 10:51:55.676159 2, 0xFFFF, sum = 0
3299 10:51:55.676604 3, 0xFFFF, sum = 0
3300 10:51:55.679584 4, 0xFFFF, sum = 0
3301 10:51:55.680179 5, 0xFFFF, sum = 0
3302 10:51:55.683226 6, 0xFFFF, sum = 0
3303 10:51:55.683773 7, 0xFFFF, sum = 0
3304 10:51:55.687140 8, 0xFFFF, sum = 0
3305 10:51:55.687685 9, 0xFFFF, sum = 0
3306 10:51:55.690227 10, 0xFFFF, sum = 0
3307 10:51:55.690774 11, 0xFFFF, sum = 0
3308 10:51:55.693002 12, 0x0, sum = 1
3309 10:51:55.693445 13, 0x0, sum = 2
3310 10:51:55.696646 14, 0x0, sum = 3
3311 10:51:55.697193 15, 0x0, sum = 4
3312 10:51:55.699990 best_step = 13
3313 10:51:55.700593
3314 10:51:55.701042 ==
3315 10:51:55.702898 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 10:51:55.706645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 10:51:55.707177 ==
3318 10:51:55.709425 RX Vref Scan: 1
3319 10:51:55.709983
3320 10:51:55.710329 Set Vref Range= 32 -> 127
3321 10:51:55.710647
3322 10:51:55.712711 RX Vref 32 -> 127, step: 1
3323 10:51:55.713149
3324 10:51:55.716351 RX Delay -13 -> 252, step: 4
3325 10:51:55.716773
3326 10:51:55.719968 Set Vref, RX VrefLevel [Byte0]: 32
3327 10:51:55.722898 [Byte1]: 32
3328 10:51:55.723414
3329 10:51:55.726244 Set Vref, RX VrefLevel [Byte0]: 33
3330 10:51:55.729137 [Byte1]: 33
3331 10:51:55.733744
3332 10:51:55.734183 Set Vref, RX VrefLevel [Byte0]: 34
3333 10:51:55.736512 [Byte1]: 34
3334 10:51:55.741229
3335 10:51:55.741639 Set Vref, RX VrefLevel [Byte0]: 35
3336 10:51:55.744219 [Byte1]: 35
3337 10:51:55.749283
3338 10:51:55.749811 Set Vref, RX VrefLevel [Byte0]: 36
3339 10:51:55.751929 [Byte1]: 36
3340 10:51:55.756933
3341 10:51:55.757429 Set Vref, RX VrefLevel [Byte0]: 37
3342 10:51:55.759803 [Byte1]: 37
3343 10:51:55.764710
3344 10:51:55.765119 Set Vref, RX VrefLevel [Byte0]: 38
3345 10:51:55.768072 [Byte1]: 38
3346 10:51:55.774143
3347 10:51:55.774688 Set Vref, RX VrefLevel [Byte0]: 39
3348 10:51:55.777782 [Byte1]: 39
3349 10:51:55.780115
3350 10:51:55.780525 Set Vref, RX VrefLevel [Byte0]: 40
3351 10:51:55.783865 [Byte1]: 40
3352 10:51:55.788759
3353 10:51:55.789171 Set Vref, RX VrefLevel [Byte0]: 41
3354 10:51:55.792597 [Byte1]: 41
3355 10:51:55.796092
3356 10:51:55.796626 Set Vref, RX VrefLevel [Byte0]: 42
3357 10:51:55.799733 [Byte1]: 42
3358 10:51:55.803852
3359 10:51:55.804340 Set Vref, RX VrefLevel [Byte0]: 43
3360 10:51:55.807255 [Byte1]: 43
3361 10:51:55.812095
3362 10:51:55.812621 Set Vref, RX VrefLevel [Byte0]: 44
3363 10:51:55.815478 [Byte1]: 44
3364 10:51:55.820619
3365 10:51:55.821121 Set Vref, RX VrefLevel [Byte0]: 45
3366 10:51:55.823783 [Byte1]: 45
3367 10:51:55.827772
3368 10:51:55.828318 Set Vref, RX VrefLevel [Byte0]: 46
3369 10:51:55.831482 [Byte1]: 46
3370 10:51:55.835840
3371 10:51:55.836422 Set Vref, RX VrefLevel [Byte0]: 47
3372 10:51:55.838687 [Byte1]: 47
3373 10:51:55.843453
3374 10:51:55.843905 Set Vref, RX VrefLevel [Byte0]: 48
3375 10:51:55.847222 [Byte1]: 48
3376 10:51:55.851298
3377 10:51:55.851846 Set Vref, RX VrefLevel [Byte0]: 49
3378 10:51:55.854664 [Byte1]: 49
3379 10:51:55.859382
3380 10:51:55.859933 Set Vref, RX VrefLevel [Byte0]: 50
3381 10:51:55.862638 [Byte1]: 50
3382 10:51:55.867747
3383 10:51:55.868382 Set Vref, RX VrefLevel [Byte0]: 51
3384 10:51:55.870745 [Byte1]: 51
3385 10:51:55.875602
3386 10:51:55.876195 Set Vref, RX VrefLevel [Byte0]: 52
3387 10:51:55.878341 [Byte1]: 52
3388 10:51:55.882924
3389 10:51:55.883477 Set Vref, RX VrefLevel [Byte0]: 53
3390 10:51:55.886083 [Byte1]: 53
3391 10:51:55.890767
3392 10:51:55.891306 Set Vref, RX VrefLevel [Byte0]: 54
3393 10:51:55.894075 [Byte1]: 54
3394 10:51:55.899303
3395 10:51:55.899987 Set Vref, RX VrefLevel [Byte0]: 55
3396 10:51:55.901717 [Byte1]: 55
3397 10:51:55.906513
3398 10:51:55.906963 Set Vref, RX VrefLevel [Byte0]: 56
3399 10:51:55.909805 [Byte1]: 56
3400 10:51:55.914608
3401 10:51:55.915285 Set Vref, RX VrefLevel [Byte0]: 57
3402 10:51:55.917659 [Byte1]: 57
3403 10:51:55.922577
3404 10:51:55.923075 Set Vref, RX VrefLevel [Byte0]: 58
3405 10:51:55.925410 [Byte1]: 58
3406 10:51:55.930843
3407 10:51:55.931347 Set Vref, RX VrefLevel [Byte0]: 59
3408 10:51:55.933986 [Byte1]: 59
3409 10:51:55.938078
3410 10:51:55.938580 Set Vref, RX VrefLevel [Byte0]: 60
3411 10:51:55.941362 [Byte1]: 60
3412 10:51:55.946005
3413 10:51:55.946507 Set Vref, RX VrefLevel [Byte0]: 61
3414 10:51:55.949445 [Byte1]: 61
3415 10:51:55.953459
3416 10:51:55.953870 Set Vref, RX VrefLevel [Byte0]: 62
3417 10:51:55.957138 [Byte1]: 62
3418 10:51:55.961614
3419 10:51:55.962116 Set Vref, RX VrefLevel [Byte0]: 63
3420 10:51:55.964671 [Byte1]: 63
3421 10:51:55.969372
3422 10:51:55.969916 Set Vref, RX VrefLevel [Byte0]: 64
3423 10:51:55.972855 [Byte1]: 64
3424 10:51:55.977532
3425 10:51:55.978092 Set Vref, RX VrefLevel [Byte0]: 65
3426 10:51:55.980821 [Byte1]: 65
3427 10:51:55.985713
3428 10:51:55.986255 Final RX Vref Byte 0 = 52 to rank0
3429 10:51:55.988546 Final RX Vref Byte 1 = 50 to rank0
3430 10:51:55.991950 Final RX Vref Byte 0 = 52 to rank1
3431 10:51:55.996258 Final RX Vref Byte 1 = 50 to rank1==
3432 10:51:56.000236 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 10:51:56.005128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 10:51:56.005592 ==
3435 10:51:56.005961 DQS Delay:
3436 10:51:56.006303 DQS0 = 0, DQS1 = 0
3437 10:51:56.008386 DQM Delay:
3438 10:51:56.008815 DQM0 = 115, DQM1 = 112
3439 10:51:56.011637 DQ Delay:
3440 10:51:56.015053 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3441 10:51:56.018116 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3442 10:51:56.021665 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =106
3443 10:51:56.025394 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3444 10:51:56.025906
3445 10:51:56.026242
3446 10:51:56.035624 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3447 10:51:56.036160 CH1 RK0: MR19=303, MR18=F1FD
3448 10:51:56.041596 CH1_RK0: MR19=0x303, MR18=0xF1FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3449 10:51:56.042062
3450 10:51:56.045081 ----->DramcWriteLeveling(PI) begin...
3451 10:51:56.045530 ==
3452 10:51:56.048309 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 10:51:56.055023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 10:51:56.055453 ==
3455 10:51:56.058470 Write leveling (Byte 0): 23 => 23
3456 10:51:56.058896 Write leveling (Byte 1): 27 => 27
3457 10:51:56.061690 DramcWriteLeveling(PI) end<-----
3458 10:51:56.062112
3459 10:51:56.062449 ==
3460 10:51:56.065333 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 10:51:56.071673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 10:51:56.072258 ==
3463 10:51:56.075320 [Gating] SW mode calibration
3464 10:51:56.081470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 10:51:56.085158 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 10:51:56.091771 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3467 10:51:56.094811 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 10:51:56.098489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 10:51:56.104823 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 10:51:56.108167 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 10:51:56.111403 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 10:51:56.118280 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
3473 10:51:56.121281 0 15 28 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
3474 10:51:56.124805 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 10:51:56.131273 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 10:51:56.134560 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 10:51:56.138042 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 10:51:56.144271 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 10:51:56.148203 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3480 10:51:56.150831 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3481 10:51:56.157624 1 0 28 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3482 10:51:56.160888 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 10:51:56.164688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 10:51:56.171060 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 10:51:56.174092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 10:51:56.177554 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 10:51:56.183989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 10:51:56.187663 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3489 10:51:56.190590 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3490 10:51:56.197662 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 10:51:56.200975 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 10:51:56.203787 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 10:51:56.210680 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 10:51:56.213522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 10:51:56.217416 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 10:51:56.223533 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 10:51:56.226637 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 10:51:56.230263 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 10:51:56.236871 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 10:51:56.240017 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 10:51:56.243208 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 10:51:56.250029 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 10:51:56.253303 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 10:51:56.256152 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3505 10:51:56.263287 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3506 10:51:56.263848 Total UI for P1: 0, mck2ui 16
3507 10:51:56.270172 best dqsien dly found for B0: ( 1, 3, 22)
3508 10:51:56.273160 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 10:51:56.276510 Total UI for P1: 0, mck2ui 16
3510 10:51:56.279620 best dqsien dly found for B1: ( 1, 3, 28)
3511 10:51:56.283211 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3512 10:51:56.286987 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3513 10:51:56.287544
3514 10:51:56.289380 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3515 10:51:56.292630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3516 10:51:56.296298 [Gating] SW calibration Done
3517 10:51:56.296855 ==
3518 10:51:56.300085 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 10:51:56.302474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 10:51:56.306317 ==
3521 10:51:56.306875 RX Vref Scan: 0
3522 10:51:56.307240
3523 10:51:56.308873 RX Vref 0 -> 0, step: 1
3524 10:51:56.309331
3525 10:51:56.312556 RX Delay -40 -> 252, step: 8
3526 10:51:56.315806 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3527 10:51:56.318897 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3528 10:51:56.322477 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3529 10:51:56.325501 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3530 10:51:56.332532 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3531 10:51:56.336010 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3532 10:51:56.338813 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3533 10:51:56.341836 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3534 10:51:56.345500 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3535 10:51:56.352026 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3536 10:51:56.354791 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3537 10:51:56.358163 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3538 10:51:56.361994 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3539 10:51:56.365892 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3540 10:51:56.372492 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3541 10:51:56.375407 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3542 10:51:56.375960 ==
3543 10:51:56.378303 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 10:51:56.382443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 10:51:56.383004 ==
3546 10:51:56.385345 DQS Delay:
3547 10:51:56.385893 DQS0 = 0, DQS1 = 0
3548 10:51:56.388793 DQM Delay:
3549 10:51:56.389338 DQM0 = 115, DQM1 = 111
3550 10:51:56.389707 DQ Delay:
3551 10:51:56.391459 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3552 10:51:56.398122 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3553 10:51:56.401616 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3554 10:51:56.404894 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3555 10:51:56.405446
3556 10:51:56.405815
3557 10:51:56.406152 ==
3558 10:51:56.408169 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 10:51:56.411042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 10:51:56.411623 ==
3561 10:51:56.411994
3562 10:51:56.412373
3563 10:51:56.414959 TX Vref Scan disable
3564 10:51:56.417796 == TX Byte 0 ==
3565 10:51:56.421520 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3566 10:51:56.425405 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3567 10:51:56.427823 == TX Byte 1 ==
3568 10:51:56.431347 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3569 10:51:56.434446 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3570 10:51:56.434909 ==
3571 10:51:56.437905 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 10:51:56.443978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 10:51:56.444489 ==
3574 10:51:56.454857 TX Vref=22, minBit 2, minWin=25, winSum=416
3575 10:51:56.457812 TX Vref=24, minBit 2, minWin=25, winSum=420
3576 10:51:56.461295 TX Vref=26, minBit 9, minWin=25, winSum=423
3577 10:51:56.464178 TX Vref=28, minBit 9, minWin=25, winSum=431
3578 10:51:56.467772 TX Vref=30, minBit 9, minWin=24, winSum=428
3579 10:51:56.474620 TX Vref=32, minBit 9, minWin=25, winSum=427
3580 10:51:56.478129 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 28
3581 10:51:56.478654
3582 10:51:56.481050 Final TX Range 1 Vref 28
3583 10:51:56.481473
3584 10:51:56.481804 ==
3585 10:51:56.484626 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 10:51:56.487139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 10:51:56.490517 ==
3588 10:51:56.490938
3589 10:51:56.491269
3590 10:51:56.491576 TX Vref Scan disable
3591 10:51:56.494242 == TX Byte 0 ==
3592 10:51:56.497877 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3593 10:51:56.504740 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3594 10:51:56.505353 == TX Byte 1 ==
3595 10:51:56.508222 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 10:51:56.514517 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 10:51:56.515092
3598 10:51:56.515463 [DATLAT]
3599 10:51:56.515803 Freq=1200, CH1 RK1
3600 10:51:56.516171
3601 10:51:56.517315 DATLAT Default: 0xd
3602 10:51:56.520983 0, 0xFFFF, sum = 0
3603 10:51:56.521555 1, 0xFFFF, sum = 0
3604 10:51:56.524136 2, 0xFFFF, sum = 0
3605 10:51:56.524707 3, 0xFFFF, sum = 0
3606 10:51:56.527898 4, 0xFFFF, sum = 0
3607 10:51:56.528406 5, 0xFFFF, sum = 0
3608 10:51:56.530240 6, 0xFFFF, sum = 0
3609 10:51:56.530708 7, 0xFFFF, sum = 0
3610 10:51:56.533837 8, 0xFFFF, sum = 0
3611 10:51:56.534260 9, 0xFFFF, sum = 0
3612 10:51:56.537126 10, 0xFFFF, sum = 0
3613 10:51:56.537550 11, 0xFFFF, sum = 0
3614 10:51:56.540103 12, 0x0, sum = 1
3615 10:51:56.540526 13, 0x0, sum = 2
3616 10:51:56.543362 14, 0x0, sum = 3
3617 10:51:56.543787 15, 0x0, sum = 4
3618 10:51:56.547576 best_step = 13
3619 10:51:56.548153
3620 10:51:56.548504 ==
3621 10:51:56.550514 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 10:51:56.553409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 10:51:56.553840 ==
3624 10:51:56.557135 RX Vref Scan: 0
3625 10:51:56.557556
3626 10:51:56.557947 RX Vref 0 -> 0, step: 1
3627 10:51:56.558263
3628 10:51:56.560137 RX Delay -13 -> 252, step: 4
3629 10:51:56.567025 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3630 10:51:56.570264 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3631 10:51:56.573603 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3632 10:51:56.576267 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3633 10:51:56.579982 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3634 10:51:56.586545 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3635 10:51:56.590196 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3636 10:51:56.592934 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3637 10:51:56.596807 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3638 10:51:56.599708 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3639 10:51:56.606037 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3640 10:51:56.609308 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3641 10:51:56.612850 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3642 10:51:56.616367 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3643 10:51:56.622826 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3644 10:51:56.625790 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3645 10:51:56.626310 ==
3646 10:51:56.629249 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 10:51:56.632893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 10:51:56.633414 ==
3649 10:51:56.635971 DQS Delay:
3650 10:51:56.636531 DQS0 = 0, DQS1 = 0
3651 10:51:56.636870 DQM Delay:
3652 10:51:56.638993 DQM0 = 115, DQM1 = 111
3653 10:51:56.639509 DQ Delay:
3654 10:51:56.642440 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3655 10:51:56.645675 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =114
3656 10:51:56.652157 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3657 10:51:56.655139 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3658 10:51:56.655818
3659 10:51:56.656423
3660 10:51:56.662002 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3661 10:51:56.665669 CH1 RK1: MR19=304, MR18=F709
3662 10:51:56.671764 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3663 10:51:56.675041 [RxdqsGatingPostProcess] freq 1200
3664 10:51:56.681677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3665 10:51:56.685168 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 10:51:56.685686 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 10:51:56.688324 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 10:51:56.691680 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 10:51:56.695061 best DQS0 dly(2T, 0.5T) = (0, 11)
3670 10:51:56.698498 best DQS1 dly(2T, 0.5T) = (0, 11)
3671 10:51:56.701290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3672 10:51:56.704808 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3673 10:51:56.707955 Pre-setting of DQS Precalculation
3674 10:51:56.714630 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3675 10:51:56.721497 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3676 10:51:56.727807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3677 10:51:56.728407
3678 10:51:56.728773
3679 10:51:56.730909 [Calibration Summary] 2400 Mbps
3680 10:51:56.731369 CH 0, Rank 0
3681 10:51:56.734070 SW Impedance : PASS
3682 10:51:56.737767 DUTY Scan : NO K
3683 10:51:56.738324 ZQ Calibration : PASS
3684 10:51:56.741191 Jitter Meter : NO K
3685 10:51:56.744564 CBT Training : PASS
3686 10:51:56.745028 Write leveling : PASS
3687 10:51:56.747503 RX DQS gating : PASS
3688 10:51:56.751012 RX DQ/DQS(RDDQC) : PASS
3689 10:51:56.751566 TX DQ/DQS : PASS
3690 10:51:56.754264 RX DATLAT : PASS
3691 10:51:56.756893 RX DQ/DQS(Engine): PASS
3692 10:51:56.757554 TX OE : NO K
3693 10:51:56.761512 All Pass.
3694 10:51:56.762075
3695 10:51:56.762441 CH 0, Rank 1
3696 10:51:56.764135 SW Impedance : PASS
3697 10:51:56.764592 DUTY Scan : NO K
3698 10:51:56.767289 ZQ Calibration : PASS
3699 10:51:56.770317 Jitter Meter : NO K
3700 10:51:56.770785 CBT Training : PASS
3701 10:51:56.773482 Write leveling : PASS
3702 10:51:56.776821 RX DQS gating : PASS
3703 10:51:56.777281 RX DQ/DQS(RDDQC) : PASS
3704 10:51:56.779955 TX DQ/DQS : PASS
3705 10:51:56.783696 RX DATLAT : PASS
3706 10:51:56.784312 RX DQ/DQS(Engine): PASS
3707 10:51:56.786707 TX OE : NO K
3708 10:51:56.787279 All Pass.
3709 10:51:56.787652
3710 10:51:56.789917 CH 1, Rank 0
3711 10:51:56.790385 SW Impedance : PASS
3712 10:51:56.793384 DUTY Scan : NO K
3713 10:51:56.796779 ZQ Calibration : PASS
3714 10:51:56.797248 Jitter Meter : NO K
3715 10:51:56.800069 CBT Training : PASS
3716 10:51:56.803872 Write leveling : PASS
3717 10:51:56.804493 RX DQS gating : PASS
3718 10:51:56.806189 RX DQ/DQS(RDDQC) : PASS
3719 10:51:56.806657 TX DQ/DQS : PASS
3720 10:51:56.810017 RX DATLAT : PASS
3721 10:51:56.813334 RX DQ/DQS(Engine): PASS
3722 10:51:56.813895 TX OE : NO K
3723 10:51:56.817907 All Pass.
3724 10:51:56.818462
3725 10:51:56.818835 CH 1, Rank 1
3726 10:51:56.819674 SW Impedance : PASS
3727 10:51:56.820159 DUTY Scan : NO K
3728 10:51:56.823074 ZQ Calibration : PASS
3729 10:51:56.826768 Jitter Meter : NO K
3730 10:51:56.827239 CBT Training : PASS
3731 10:51:56.829937 Write leveling : PASS
3732 10:51:56.832832 RX DQS gating : PASS
3733 10:51:56.833300 RX DQ/DQS(RDDQC) : PASS
3734 10:51:56.836429 TX DQ/DQS : PASS
3735 10:51:56.840236 RX DATLAT : PASS
3736 10:51:56.840792 RX DQ/DQS(Engine): PASS
3737 10:51:56.842982 TX OE : NO K
3738 10:51:56.843547 All Pass.
3739 10:51:56.843950
3740 10:51:56.845874 DramC Write-DBI off
3741 10:51:56.849748 PER_BANK_REFRESH: Hybrid Mode
3742 10:51:56.850401 TX_TRACKING: ON
3743 10:51:56.859906 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3744 10:51:56.862734 [FAST_K] Save calibration result to emmc
3745 10:51:56.866266 dramc_set_vcore_voltage set vcore to 650000
3746 10:51:56.869407 Read voltage for 600, 5
3747 10:51:56.869871 Vio18 = 0
3748 10:51:56.870246 Vcore = 650000
3749 10:51:56.872292 Vdram = 0
3750 10:51:56.872753 Vddq = 0
3751 10:51:56.873123 Vmddr = 0
3752 10:51:56.879481 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3753 10:51:56.882156 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3754 10:51:56.886068 MEM_TYPE=3, freq_sel=19
3755 10:51:56.888927 sv_algorithm_assistance_LP4_1600
3756 10:51:56.892586 ============ PULL DRAM RESETB DOWN ============
3757 10:51:56.898691 ========== PULL DRAM RESETB DOWN end =========
3758 10:51:56.902537 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 10:51:56.905501 ===================================
3760 10:51:56.908969 LPDDR4 DRAM CONFIGURATION
3761 10:51:56.912360 ===================================
3762 10:51:56.912914 EX_ROW_EN[0] = 0x0
3763 10:51:56.915837 EX_ROW_EN[1] = 0x0
3764 10:51:56.916497 LP4Y_EN = 0x0
3765 10:51:56.919572 WORK_FSP = 0x0
3766 10:51:56.919992 WL = 0x2
3767 10:51:56.922357 RL = 0x2
3768 10:51:56.922869 BL = 0x2
3769 10:51:56.925072 RPST = 0x0
3770 10:51:56.928857 RD_PRE = 0x0
3771 10:51:56.929371 WR_PRE = 0x1
3772 10:51:56.931687 WR_PST = 0x0
3773 10:51:56.932124 DBI_WR = 0x0
3774 10:51:56.935219 DBI_RD = 0x0
3775 10:51:56.935732 OTF = 0x1
3776 10:51:56.938706 ===================================
3777 10:51:56.942178 ===================================
3778 10:51:56.945697 ANA top config
3779 10:51:56.948611 ===================================
3780 10:51:56.949127 DLL_ASYNC_EN = 0
3781 10:51:56.952115 ALL_SLAVE_EN = 1
3782 10:51:56.955249 NEW_RANK_MODE = 1
3783 10:51:56.958226 DLL_IDLE_MODE = 1
3784 10:51:56.958654 LP45_APHY_COMB_EN = 1
3785 10:51:56.961885 TX_ODT_DIS = 1
3786 10:51:56.964706 NEW_8X_MODE = 1
3787 10:51:56.968106 ===================================
3788 10:51:56.971274 ===================================
3789 10:51:56.974951 data_rate = 1200
3790 10:51:56.977671 CKR = 1
3791 10:51:56.981145 DQ_P2S_RATIO = 8
3792 10:51:56.984725 ===================================
3793 10:51:56.987870 CA_P2S_RATIO = 8
3794 10:51:56.988424 DQ_CA_OPEN = 0
3795 10:51:56.990765 DQ_SEMI_OPEN = 0
3796 10:51:56.993939 CA_SEMI_OPEN = 0
3797 10:51:56.997374 CA_FULL_RATE = 0
3798 10:51:57.001378 DQ_CKDIV4_EN = 1
3799 10:51:57.004186 CA_CKDIV4_EN = 1
3800 10:51:57.005013 CA_PREDIV_EN = 0
3801 10:51:57.007093 PH8_DLY = 0
3802 10:51:57.010941 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3803 10:51:57.013662 DQ_AAMCK_DIV = 4
3804 10:51:57.017378 CA_AAMCK_DIV = 4
3805 10:51:57.020118 CA_ADMCK_DIV = 4
3806 10:51:57.020541 DQ_TRACK_CA_EN = 0
3807 10:51:57.023536 CA_PICK = 600
3808 10:51:57.026824 CA_MCKIO = 600
3809 10:51:57.030479 MCKIO_SEMI = 0
3810 10:51:57.033796 PLL_FREQ = 2288
3811 10:51:57.037062 DQ_UI_PI_RATIO = 32
3812 10:51:57.039985 CA_UI_PI_RATIO = 0
3813 10:51:57.043710 ===================================
3814 10:51:57.046573 ===================================
3815 10:51:57.047038 memory_type:LPDDR4
3816 10:51:57.050147 GP_NUM : 10
3817 10:51:57.053399 SRAM_EN : 1
3818 10:51:57.053953 MD32_EN : 0
3819 10:51:57.056499 ===================================
3820 10:51:57.059917 [ANA_INIT] >>>>>>>>>>>>>>
3821 10:51:57.063596 <<<<<< [CONFIGURE PHASE]: ANA_TX
3822 10:51:57.066383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3823 10:51:57.070381 ===================================
3824 10:51:57.073615 data_rate = 1200,PCW = 0X5800
3825 10:51:57.076936 ===================================
3826 10:51:57.079822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3827 10:51:57.083423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 10:51:57.089477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 10:51:57.093226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3830 10:51:57.099335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3831 10:51:57.102777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3832 10:51:57.103350 [ANA_INIT] flow start
3833 10:51:57.105853 [ANA_INIT] PLL >>>>>>>>
3834 10:51:57.108986 [ANA_INIT] PLL <<<<<<<<
3835 10:51:57.109474 [ANA_INIT] MIDPI >>>>>>>>
3836 10:51:57.112932 [ANA_INIT] MIDPI <<<<<<<<
3837 10:51:57.116162 [ANA_INIT] DLL >>>>>>>>
3838 10:51:57.116734 [ANA_INIT] flow end
3839 10:51:57.122264 ============ LP4 DIFF to SE enter ============
3840 10:51:57.125530 ============ LP4 DIFF to SE exit ============
3841 10:51:57.130335 [ANA_INIT] <<<<<<<<<<<<<
3842 10:51:57.132350 [Flow] Enable top DCM control >>>>>
3843 10:51:57.135454 [Flow] Enable top DCM control <<<<<
3844 10:51:57.136026 Enable DLL master slave shuffle
3845 10:51:57.141812 ==============================================================
3846 10:51:57.146077 Gating Mode config
3847 10:51:57.148726 ==============================================================
3848 10:51:57.152420 Config description:
3849 10:51:57.161871 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3850 10:51:57.167998 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3851 10:51:57.171390 SELPH_MODE 0: By rank 1: By Phase
3852 10:51:57.178358 ==============================================================
3853 10:51:57.181348 GAT_TRACK_EN = 1
3854 10:51:57.185289 RX_GATING_MODE = 2
3855 10:51:57.187595 RX_GATING_TRACK_MODE = 2
3856 10:51:57.191265 SELPH_MODE = 1
3857 10:51:57.194021 PICG_EARLY_EN = 1
3858 10:51:57.197801 VALID_LAT_VALUE = 1
3859 10:51:57.200821 ==============================================================
3860 10:51:57.204173 Enter into Gating configuration >>>>
3861 10:51:57.207442 Exit from Gating configuration <<<<
3862 10:51:57.210708 Enter into DVFS_PRE_config >>>>>
3863 10:51:57.223897 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3864 10:51:57.227313 Exit from DVFS_PRE_config <<<<<
3865 10:51:57.227611 Enter into PICG configuration >>>>
3866 10:51:57.230064 Exit from PICG configuration <<<<
3867 10:51:57.233517 [RX_INPUT] configuration >>>>>
3868 10:51:57.236845 [RX_INPUT] configuration <<<<<
3869 10:51:57.243566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3870 10:51:57.246749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3871 10:51:57.253200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 10:51:57.259886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 10:51:57.266902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3874 10:51:57.273021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3875 10:51:57.276673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3876 10:51:57.279580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3877 10:51:57.286174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3878 10:51:57.290161 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3879 10:51:57.292972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3880 10:51:57.295884 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 10:51:57.299417 ===================================
3882 10:51:57.302496 LPDDR4 DRAM CONFIGURATION
3883 10:51:57.305561 ===================================
3884 10:51:57.309351 EX_ROW_EN[0] = 0x0
3885 10:51:57.309433 EX_ROW_EN[1] = 0x0
3886 10:51:57.312550 LP4Y_EN = 0x0
3887 10:51:57.312632 WORK_FSP = 0x0
3888 10:51:57.315788 WL = 0x2
3889 10:51:57.315869 RL = 0x2
3890 10:51:57.318884 BL = 0x2
3891 10:51:57.318970 RPST = 0x0
3892 10:51:57.322195 RD_PRE = 0x0
3893 10:51:57.326483 WR_PRE = 0x1
3894 10:51:57.326566 WR_PST = 0x0
3895 10:51:57.329362 DBI_WR = 0x0
3896 10:51:57.329523 DBI_RD = 0x0
3897 10:51:57.332304 OTF = 0x1
3898 10:51:57.335887 ===================================
3899 10:51:57.338703 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3900 10:51:57.341804 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3901 10:51:57.345490 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3902 10:51:57.348890 ===================================
3903 10:51:57.352477 LPDDR4 DRAM CONFIGURATION
3904 10:51:57.355566 ===================================
3905 10:51:57.358335 EX_ROW_EN[0] = 0x10
3906 10:51:57.358418 EX_ROW_EN[1] = 0x0
3907 10:51:57.362077 LP4Y_EN = 0x0
3908 10:51:57.362234 WORK_FSP = 0x0
3909 10:51:57.364961 WL = 0x2
3910 10:51:57.368491 RL = 0x2
3911 10:51:57.368646 BL = 0x2
3912 10:51:57.371603 RPST = 0x0
3913 10:51:57.371684 RD_PRE = 0x0
3914 10:51:57.375161 WR_PRE = 0x1
3915 10:51:57.375243 WR_PST = 0x0
3916 10:51:57.378051 DBI_WR = 0x0
3917 10:51:57.378135 DBI_RD = 0x0
3918 10:51:57.382004 OTF = 0x1
3919 10:51:57.384559 ===================================
3920 10:51:57.391618 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3921 10:51:57.394776 nWR fixed to 30
3922 10:51:57.394860 [ModeRegInit_LP4] CH0 RK0
3923 10:51:57.398295 [ModeRegInit_LP4] CH0 RK1
3924 10:51:57.401804 [ModeRegInit_LP4] CH1 RK0
3925 10:51:57.404438 [ModeRegInit_LP4] CH1 RK1
3926 10:51:57.404579 match AC timing 17
3927 10:51:57.411093 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3928 10:51:57.414833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3929 10:51:57.417450 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3930 10:51:57.424288 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3931 10:51:57.427792 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3932 10:51:57.427880 ==
3933 10:51:57.431145 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 10:51:57.433893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 10:51:57.433997 ==
3936 10:51:57.440647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 10:51:57.447487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3938 10:51:57.450813 [CA 0] Center 36 (6~67) winsize 62
3939 10:51:57.454089 [CA 1] Center 36 (6~67) winsize 62
3940 10:51:57.457436 [CA 2] Center 34 (4~65) winsize 62
3941 10:51:57.460804 [CA 3] Center 34 (4~65) winsize 62
3942 10:51:57.464804 [CA 4] Center 33 (3~64) winsize 62
3943 10:51:57.467258 [CA 5] Center 33 (3~64) winsize 62
3944 10:51:57.467462
3945 10:51:57.470715 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3946 10:51:57.470920
3947 10:51:57.473781 [CATrainingPosCal] consider 1 rank data
3948 10:51:57.476888 u2DelayCellTimex100 = 270/100 ps
3949 10:51:57.480082 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 10:51:57.483657 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3951 10:51:57.486865 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 10:51:57.490579 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 10:51:57.493949 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 10:51:57.500209 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 10:51:57.500395
3956 10:51:57.504263 CA PerBit enable=1, Macro0, CA PI delay=33
3957 10:51:57.504510
3958 10:51:57.506945 [CBTSetCACLKResult] CA Dly = 33
3959 10:51:57.507139 CS Dly: 6 (0~37)
3960 10:51:57.507274 ==
3961 10:51:57.509907 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 10:51:57.513210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 10:51:57.516966 ==
3964 10:51:57.521048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 10:51:57.527162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3966 10:51:57.530722 [CA 0] Center 36 (6~67) winsize 62
3967 10:51:57.533644 [CA 1] Center 36 (6~67) winsize 62
3968 10:51:57.536878 [CA 2] Center 34 (4~65) winsize 62
3969 10:51:57.539730 [CA 3] Center 34 (4~65) winsize 62
3970 10:51:57.543203 [CA 4] Center 34 (3~65) winsize 63
3971 10:51:57.546499 [CA 5] Center 33 (3~64) winsize 62
3972 10:51:57.546736
3973 10:51:57.549429 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3974 10:51:57.549619
3975 10:51:57.552549 [CATrainingPosCal] consider 2 rank data
3976 10:51:57.556322 u2DelayCellTimex100 = 270/100 ps
3977 10:51:57.559381 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3978 10:51:57.562579 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3979 10:51:57.569054 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 10:51:57.572519 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 10:51:57.576373 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 10:51:57.578802 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 10:51:57.578911
3984 10:51:57.582818 CA PerBit enable=1, Macro0, CA PI delay=33
3985 10:51:57.582978
3986 10:51:57.586021 [CBTSetCACLKResult] CA Dly = 33
3987 10:51:57.586181 CS Dly: 6 (0~38)
3988 10:51:57.588996
3989 10:51:57.591974 ----->DramcWriteLeveling(PI) begin...
3990 10:51:57.592147 ==
3991 10:51:57.595472 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 10:51:57.598921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 10:51:57.599061 ==
3994 10:51:57.602248 Write leveling (Byte 0): 33 => 33
3995 10:51:57.605390 Write leveling (Byte 1): 29 => 29
3996 10:51:57.608577 DramcWriteLeveling(PI) end<-----
3997 10:51:57.608709
3998 10:51:57.608784 ==
3999 10:51:57.612022 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 10:51:57.615355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 10:51:57.615518 ==
4002 10:51:57.618449 [Gating] SW mode calibration
4003 10:51:57.625141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4004 10:51:57.631927 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4005 10:51:57.634946 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 10:51:57.638386 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 10:51:57.644775 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 10:51:57.648179 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4009 10:51:57.651812 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
4010 10:51:57.658324 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 10:51:57.662097 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 10:51:57.664764 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 10:51:57.671143 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 10:51:57.675050 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 10:51:57.677978 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 10:51:57.684726 0 10 12 | B1->B0 | 2424 2e2e | 1 0 | (0 0) (0 0)
4017 10:51:57.687958 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4018 10:51:57.691393 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 10:51:57.698103 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 10:51:57.701121 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 10:51:57.704380 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 10:51:57.710825 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 10:51:57.714642 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 10:51:57.717671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 10:51:57.724279 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4026 10:51:57.727791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 10:51:57.730686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 10:51:57.737279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 10:51:57.740435 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 10:51:57.747213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 10:51:57.750608 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 10:51:57.753720 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 10:51:57.759733 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 10:51:57.764021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 10:51:57.766275 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 10:51:57.773063 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 10:51:57.776543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 10:51:57.779833 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 10:51:57.786350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 10:51:57.789534 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4041 10:51:57.793066 Total UI for P1: 0, mck2ui 16
4042 10:51:57.796614 best dqsien dly found for B0: ( 0, 13, 10)
4043 10:51:57.799510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 10:51:57.803721 Total UI for P1: 0, mck2ui 16
4045 10:51:57.806440 best dqsien dly found for B1: ( 0, 13, 14)
4046 10:51:57.809551 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4047 10:51:57.812397 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4048 10:51:57.812859
4049 10:51:57.819324 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4050 10:51:57.822431 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4051 10:51:57.825940 [Gating] SW calibration Done
4052 10:51:57.826498 ==
4053 10:51:57.828735 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 10:51:57.832887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 10:51:57.833459 ==
4056 10:51:57.833830 RX Vref Scan: 0
4057 10:51:57.834169
4058 10:51:57.835682 RX Vref 0 -> 0, step: 1
4059 10:51:57.836258
4060 10:51:57.839363 RX Delay -230 -> 252, step: 16
4061 10:51:57.842426 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4062 10:51:57.845351 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4063 10:51:57.852381 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4064 10:51:57.856208 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4065 10:51:57.858881 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4066 10:51:57.862178 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4067 10:51:57.868458 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4068 10:51:57.871928 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4069 10:51:57.875577 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4070 10:51:57.878251 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4071 10:51:57.884895 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4072 10:51:57.888117 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4073 10:51:57.891227 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4074 10:51:57.894570 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4075 10:51:57.901669 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4076 10:51:57.904638 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4077 10:51:57.905194 ==
4078 10:51:57.907931 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 10:51:57.911444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 10:51:57.912001 ==
4081 10:51:57.914895 DQS Delay:
4082 10:51:57.915551 DQS0 = 0, DQS1 = 0
4083 10:51:57.915937 DQM Delay:
4084 10:51:57.917687 DQM0 = 43, DQM1 = 34
4085 10:51:57.918144 DQ Delay:
4086 10:51:57.921208 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4087 10:51:57.924481 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4088 10:51:57.928286 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4089 10:51:57.931224 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4090 10:51:57.931782
4091 10:51:57.932172
4092 10:51:57.932514 ==
4093 10:51:57.934089 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 10:51:57.941775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 10:51:57.942344 ==
4096 10:51:57.942719
4097 10:51:57.943061
4098 10:51:57.944110 TX Vref Scan disable
4099 10:51:57.944569 == TX Byte 0 ==
4100 10:51:57.947680 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4101 10:51:57.954084 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4102 10:51:57.954647 == TX Byte 1 ==
4103 10:51:57.960508 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4104 10:51:57.965589 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4105 10:51:57.966199 ==
4106 10:51:57.968834 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 10:51:57.970944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 10:51:57.971406 ==
4109 10:51:57.971772
4110 10:51:57.972149
4111 10:51:57.973731 TX Vref Scan disable
4112 10:51:57.977004 == TX Byte 0 ==
4113 10:51:57.980399 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4114 10:51:57.984019 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4115 10:51:57.987349 == TX Byte 1 ==
4116 10:51:57.990241 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4117 10:51:57.993824 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4118 10:51:57.994388
4119 10:51:57.997456 [DATLAT]
4120 10:51:57.998030 Freq=600, CH0 RK0
4121 10:51:57.998403
4122 10:51:58.000369 DATLAT Default: 0x9
4123 10:51:58.000828 0, 0xFFFF, sum = 0
4124 10:51:58.003901 1, 0xFFFF, sum = 0
4125 10:51:58.004514 2, 0xFFFF, sum = 0
4126 10:51:58.006990 3, 0xFFFF, sum = 0
4127 10:51:58.007553 4, 0xFFFF, sum = 0
4128 10:51:58.010374 5, 0xFFFF, sum = 0
4129 10:51:58.013330 6, 0xFFFF, sum = 0
4130 10:51:58.013912 7, 0xFFFF, sum = 0
4131 10:51:58.014285 8, 0x0, sum = 1
4132 10:51:58.016741 9, 0x0, sum = 2
4133 10:51:58.017309 10, 0x0, sum = 3
4134 10:51:58.019958 11, 0x0, sum = 4
4135 10:51:58.020577 best_step = 9
4136 10:51:58.020952
4137 10:51:58.021291 ==
4138 10:51:58.023203 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 10:51:58.029905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 10:51:58.030474 ==
4141 10:51:58.030844 RX Vref Scan: 1
4142 10:51:58.031186
4143 10:51:58.033717 RX Vref 0 -> 0, step: 1
4144 10:51:58.034177
4145 10:51:58.036097 RX Delay -195 -> 252, step: 8
4146 10:51:58.036555
4147 10:51:58.039609 Set Vref, RX VrefLevel [Byte0]: 51
4148 10:51:58.043608 [Byte1]: 49
4149 10:51:58.044019
4150 10:51:58.046006 Final RX Vref Byte 0 = 51 to rank0
4151 10:51:58.049341 Final RX Vref Byte 1 = 49 to rank0
4152 10:51:58.052326 Final RX Vref Byte 0 = 51 to rank1
4153 10:51:58.055881 Final RX Vref Byte 1 = 49 to rank1==
4154 10:51:58.059185 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 10:51:58.062094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 10:51:58.065839 ==
4157 10:51:58.066356 DQS Delay:
4158 10:51:58.066693 DQS0 = 0, DQS1 = 0
4159 10:51:58.069420 DQM Delay:
4160 10:51:58.069834 DQM0 = 41, DQM1 = 34
4161 10:51:58.072720 DQ Delay:
4162 10:51:58.073135 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4163 10:51:58.076103 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4164 10:51:58.079178 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4165 10:51:58.082715 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4166 10:51:58.083240
4167 10:51:58.086422
4168 10:51:58.092316 [DQSOSCAuto] RK0, (LSB)MR18= 0x483f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4169 10:51:58.095651 CH0 RK0: MR19=808, MR18=483F
4170 10:51:58.102776 CH0_RK0: MR19=0x808, MR18=0x483F, DQSOSC=396, MR23=63, INC=167, DEC=111
4171 10:51:58.103342
4172 10:51:58.105755 ----->DramcWriteLeveling(PI) begin...
4173 10:51:58.106226 ==
4174 10:51:58.108382 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 10:51:58.111931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 10:51:58.112458 ==
4177 10:51:58.115766 Write leveling (Byte 0): 34 => 34
4178 10:51:58.118891 Write leveling (Byte 1): 28 => 28
4179 10:51:58.122401 DramcWriteLeveling(PI) end<-----
4180 10:51:58.122966
4181 10:51:58.123338 ==
4182 10:51:58.124947 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 10:51:58.128227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 10:51:58.128692 ==
4185 10:51:58.131877 [Gating] SW mode calibration
4186 10:51:58.138326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 10:51:58.144977 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 10:51:58.147916 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 10:51:58.154763 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 10:51:58.158103 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 10:51:58.161986 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4192 10:51:58.167795 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 1) (0 0)
4193 10:51:58.171447 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 10:51:58.174693 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 10:51:58.180784 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 10:51:58.184103 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 10:51:58.187606 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 10:51:58.194267 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4199 10:51:58.197481 0 10 12 | B1->B0 | 2828 3434 | 1 0 | (0 0) (0 0)
4200 10:51:58.200678 0 10 16 | B1->B0 | 3c3c 4545 | 0 0 | (1 1) (0 0)
4201 10:51:58.207667 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 10:51:58.210432 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 10:51:58.213947 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 10:51:58.220124 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 10:51:58.223843 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 10:51:58.227395 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 10:51:58.233990 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4208 10:51:58.236697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4209 10:51:58.240560 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 10:51:58.246887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 10:51:58.250560 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 10:51:58.253366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 10:51:58.259999 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 10:51:58.263082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 10:51:58.267471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 10:51:58.272912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 10:51:58.276231 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 10:51:58.280131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 10:51:58.286199 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 10:51:58.289287 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 10:51:58.293012 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 10:51:58.299658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 10:51:58.302806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4224 10:51:58.306045 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4225 10:51:58.309506 Total UI for P1: 0, mck2ui 16
4226 10:51:58.313202 best dqsien dly found for B0: ( 0, 13, 12)
4227 10:51:58.319015 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 10:51:58.323174 Total UI for P1: 0, mck2ui 16
4229 10:51:58.326181 best dqsien dly found for B1: ( 0, 13, 16)
4230 10:51:58.329643 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4231 10:51:58.332584 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4232 10:51:58.333149
4233 10:51:58.335847 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4234 10:51:58.338819 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4235 10:51:58.341757 [Gating] SW calibration Done
4236 10:51:58.342226 ==
4237 10:51:58.345164 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 10:51:58.348973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 10:51:58.349445 ==
4240 10:51:58.352382 RX Vref Scan: 0
4241 10:51:58.352944
4242 10:51:58.355779 RX Vref 0 -> 0, step: 1
4243 10:51:58.356355
4244 10:51:58.358671 RX Delay -230 -> 252, step: 16
4245 10:51:58.361947 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4246 10:51:58.365221 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4247 10:51:58.368408 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4248 10:51:58.371873 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4249 10:51:58.378559 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4250 10:51:58.382250 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4251 10:51:58.384902 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4252 10:51:58.388018 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4253 10:51:58.396412 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4254 10:51:58.399175 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4255 10:51:58.401008 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4256 10:51:58.404519 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4257 10:51:58.411719 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4258 10:51:58.414984 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4259 10:51:58.417408 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4260 10:51:58.420588 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4261 10:51:58.424121 ==
4262 10:51:58.427515 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 10:51:58.430977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 10:51:58.431541 ==
4265 10:51:58.431909 DQS Delay:
4266 10:51:58.434370 DQS0 = 0, DQS1 = 0
4267 10:51:58.434851 DQM Delay:
4268 10:51:58.437618 DQM0 = 41, DQM1 = 31
4269 10:51:58.438174 DQ Delay:
4270 10:51:58.440568 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4271 10:51:58.444544 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4272 10:51:58.447812 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4273 10:51:58.450256 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4274 10:51:58.450718
4275 10:51:58.451083
4276 10:51:58.451423 ==
4277 10:51:58.453689 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 10:51:58.457273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 10:51:58.457834 ==
4280 10:51:58.458203
4281 10:51:58.458540
4282 10:51:58.460458 TX Vref Scan disable
4283 10:51:58.463620 == TX Byte 0 ==
4284 10:51:58.467473 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4285 10:51:58.470892 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4286 10:51:58.473384 == TX Byte 1 ==
4287 10:51:58.476857 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4288 10:51:58.480172 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4289 10:51:58.480745 ==
4290 10:51:58.483399 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 10:51:58.489778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 10:51:58.490343 ==
4293 10:51:58.490712
4294 10:51:58.491048
4295 10:51:58.493591 TX Vref Scan disable
4296 10:51:58.494146 == TX Byte 0 ==
4297 10:51:58.499796 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4298 10:51:58.503219 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4299 10:51:58.506249 == TX Byte 1 ==
4300 10:51:58.509417 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4301 10:51:58.513313 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4302 10:51:58.513777
4303 10:51:58.514144 [DATLAT]
4304 10:51:58.516989 Freq=600, CH0 RK1
4305 10:51:58.517541
4306 10:51:58.517907 DATLAT Default: 0x9
4307 10:51:58.519385 0, 0xFFFF, sum = 0
4308 10:51:58.522776 1, 0xFFFF, sum = 0
4309 10:51:58.523240 2, 0xFFFF, sum = 0
4310 10:51:58.526385 3, 0xFFFF, sum = 0
4311 10:51:58.526921 4, 0xFFFF, sum = 0
4312 10:51:58.529418 5, 0xFFFF, sum = 0
4313 10:51:58.529881 6, 0xFFFF, sum = 0
4314 10:51:58.532671 7, 0xFFFF, sum = 0
4315 10:51:58.533418 8, 0x0, sum = 1
4316 10:51:58.535781 9, 0x0, sum = 2
4317 10:51:58.536264 10, 0x0, sum = 3
4318 10:51:58.539258 11, 0x0, sum = 4
4319 10:51:58.539718 best_step = 9
4320 10:51:58.540108
4321 10:51:58.540450 ==
4322 10:51:58.542634 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 10:51:58.545709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 10:51:58.546218 ==
4325 10:51:58.549546 RX Vref Scan: 0
4326 10:51:58.549960
4327 10:51:58.552997 RX Vref 0 -> 0, step: 1
4328 10:51:58.553414
4329 10:51:58.553745 RX Delay -195 -> 252, step: 8
4330 10:51:58.560176 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4331 10:51:58.563177 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4332 10:51:58.566591 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4333 10:51:58.569826 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4334 10:51:58.576455 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4335 10:51:58.579857 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4336 10:51:58.583313 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4337 10:51:58.586421 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4338 10:51:58.593324 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4339 10:51:58.596465 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4340 10:51:58.600130 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4341 10:51:58.602950 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4342 10:51:58.609568 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4343 10:51:58.612686 iDelay=197, Bit 13, Center 44 (-107 ~ 196) 304
4344 10:51:58.616073 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4345 10:51:58.619745 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4346 10:51:58.620351 ==
4347 10:51:58.622481 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 10:51:58.629557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 10:51:58.630104 ==
4350 10:51:58.630466 DQS Delay:
4351 10:51:58.632501 DQS0 = 0, DQS1 = 0
4352 10:51:58.633089 DQM Delay:
4353 10:51:58.633522 DQM0 = 41, DQM1 = 34
4354 10:51:58.635820 DQ Delay:
4355 10:51:58.639747 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4356 10:51:58.642286 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4357 10:51:58.646028 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4358 10:51:58.648723 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4359 10:51:58.649172
4360 10:51:58.649529
4361 10:51:58.655384 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4362 10:51:58.659261 CH0 RK1: MR19=808, MR18=3C38
4363 10:51:58.665893 CH0_RK1: MR19=0x808, MR18=0x3C38, DQSOSC=398, MR23=63, INC=165, DEC=110
4364 10:51:58.668790 [RxdqsGatingPostProcess] freq 600
4365 10:51:58.675147 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4366 10:51:58.675595 Pre-setting of DQS Precalculation
4367 10:51:58.681722 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4368 10:51:58.682264 ==
4369 10:51:58.685452 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 10:51:58.688311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 10:51:58.688764 ==
4372 10:51:58.695551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 10:51:58.701537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 10:51:58.705295 [CA 0] Center 36 (6~66) winsize 61
4375 10:51:58.707875 [CA 1] Center 35 (5~66) winsize 62
4376 10:51:58.711514 [CA 2] Center 34 (4~65) winsize 62
4377 10:51:58.715394 [CA 3] Center 34 (3~65) winsize 63
4378 10:51:58.718707 [CA 4] Center 34 (4~65) winsize 62
4379 10:51:58.720996 [CA 5] Center 34 (3~65) winsize 63
4380 10:51:58.721447
4381 10:51:58.724817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 10:51:58.725362
4383 10:51:58.727823 [CATrainingPosCal] consider 1 rank data
4384 10:51:58.731496 u2DelayCellTimex100 = 270/100 ps
4385 10:51:58.734542 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4386 10:51:58.737748 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4387 10:51:58.740869 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 10:51:58.744346 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4389 10:51:58.747660 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 10:51:58.754273 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4391 10:51:58.754944
4392 10:51:58.757529 CA PerBit enable=1, Macro0, CA PI delay=34
4393 10:51:58.758083
4394 10:51:58.761106 [CBTSetCACLKResult] CA Dly = 34
4395 10:51:58.761650 CS Dly: 3 (0~34)
4396 10:51:58.762012 ==
4397 10:51:58.763992 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 10:51:58.767393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 10:51:58.771183 ==
4400 10:51:58.774086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 10:51:58.780761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4402 10:51:58.784545 [CA 0] Center 35 (5~66) winsize 62
4403 10:51:58.787423 [CA 1] Center 35 (5~66) winsize 62
4404 10:51:58.790291 [CA 2] Center 34 (4~65) winsize 62
4405 10:51:58.793775 [CA 3] Center 34 (3~65) winsize 63
4406 10:51:58.797429 [CA 4] Center 34 (4~65) winsize 62
4407 10:51:58.800674 [CA 5] Center 34 (3~65) winsize 63
4408 10:51:58.801221
4409 10:51:58.804158 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4410 10:51:58.804706
4411 10:51:58.806979 [CATrainingPosCal] consider 2 rank data
4412 10:51:58.810467 u2DelayCellTimex100 = 270/100 ps
4413 10:51:58.813417 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4414 10:51:58.816825 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4415 10:51:58.823798 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4416 10:51:58.827202 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4417 10:51:58.829926 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 10:51:58.833364 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4419 10:51:58.833914
4420 10:51:58.836551 CA PerBit enable=1, Macro0, CA PI delay=34
4421 10:51:58.837002
4422 10:51:58.839863 [CBTSetCACLKResult] CA Dly = 34
4423 10:51:58.840462 CS Dly: 4 (0~36)
4424 10:51:58.843101
4425 10:51:58.846842 ----->DramcWriteLeveling(PI) begin...
4426 10:51:58.847299 ==
4427 10:51:58.849645 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 10:51:58.852980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 10:51:58.853432 ==
4430 10:51:58.857078 Write leveling (Byte 0): 27 => 27
4431 10:51:58.860186 Write leveling (Byte 1): 27 => 27
4432 10:51:58.863299 DramcWriteLeveling(PI) end<-----
4433 10:51:58.863854
4434 10:51:58.864272 ==
4435 10:51:58.866176 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 10:51:58.870764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 10:51:58.871222 ==
4438 10:51:58.872867 [Gating] SW mode calibration
4439 10:51:58.880082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 10:51:58.885791 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4441 10:51:58.889469 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 10:51:58.892660 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 10:51:58.900009 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 10:51:58.902399 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (0 1) (0 0)
4445 10:51:58.905971 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 10:51:58.912496 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 10:51:58.915670 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 10:51:58.919290 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 10:51:58.925774 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 10:51:58.928912 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 10:51:58.931960 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4452 10:51:58.938666 0 10 12 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
4453 10:51:58.941698 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 10:51:58.945545 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 10:51:58.951318 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 10:51:58.955670 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 10:51:58.958057 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 10:51:58.964674 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 10:51:58.968256 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4460 10:51:58.971348 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4461 10:51:58.978262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 10:51:58.981810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 10:51:58.984641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 10:51:58.991405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 10:51:58.994677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 10:51:58.998027 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 10:51:59.004459 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 10:51:59.008247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 10:51:59.010598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 10:51:59.017811 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 10:51:59.020701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 10:51:59.024018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 10:51:59.030835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 10:51:59.034334 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 10:51:59.037459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:51:59.044229 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4477 10:51:59.047301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 10:51:59.051085 Total UI for P1: 0, mck2ui 16
4479 10:51:59.054204 best dqsien dly found for B0: ( 0, 13, 12)
4480 10:51:59.057017 Total UI for P1: 0, mck2ui 16
4481 10:51:59.060447 best dqsien dly found for B1: ( 0, 13, 12)
4482 10:51:59.063962 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4483 10:51:59.067073 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4484 10:51:59.067534
4485 10:51:59.071117 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4486 10:51:59.076922 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4487 10:51:59.077384 [Gating] SW calibration Done
4488 10:51:59.077778 ==
4489 10:51:59.079970 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 10:51:59.086647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 10:51:59.087209 ==
4492 10:51:59.087581 RX Vref Scan: 0
4493 10:51:59.087921
4494 10:51:59.089929 RX Vref 0 -> 0, step: 1
4495 10:51:59.090499
4496 10:51:59.092958 RX Delay -230 -> 252, step: 16
4497 10:51:59.096530 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4498 10:51:59.099820 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4499 10:51:59.106496 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4500 10:51:59.110109 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4501 10:51:59.112677 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4502 10:51:59.116443 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4503 10:51:59.119471 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4504 10:51:59.127016 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4505 10:51:59.129628 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4506 10:51:59.133404 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4507 10:51:59.135995 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4508 10:51:59.142872 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4509 10:51:59.145981 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4510 10:51:59.149010 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4511 10:51:59.152710 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4512 10:51:59.159632 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4513 10:51:59.160214 ==
4514 10:51:59.162858 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 10:51:59.165208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 10:51:59.165630 ==
4517 10:51:59.168933 DQS Delay:
4518 10:51:59.169346 DQS0 = 0, DQS1 = 0
4519 10:51:59.169674 DQM Delay:
4520 10:51:59.172363 DQM0 = 44, DQM1 = 38
4521 10:51:59.172913 DQ Delay:
4522 10:51:59.175789 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4523 10:51:59.178649 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4524 10:51:59.181891 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4525 10:51:59.185475 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4526 10:51:59.185951
4527 10:51:59.186417
4528 10:51:59.186825 ==
4529 10:51:59.188599 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 10:51:59.195364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 10:51:59.195795 ==
4532 10:51:59.196256
4533 10:51:59.196670
4534 10:51:59.197070 TX Vref Scan disable
4535 10:51:59.198918 == TX Byte 0 ==
4536 10:51:59.202856 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4537 10:51:59.208517 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4538 10:51:59.209069 == TX Byte 1 ==
4539 10:51:59.212021 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4540 10:51:59.218786 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4541 10:51:59.219350 ==
4542 10:51:59.221770 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 10:51:59.225159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 10:51:59.225722 ==
4545 10:51:59.226090
4546 10:51:59.226427
4547 10:51:59.228536 TX Vref Scan disable
4548 10:51:59.231781 == TX Byte 0 ==
4549 10:51:59.234757 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4550 10:51:59.238225 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4551 10:51:59.241883 == TX Byte 1 ==
4552 10:51:59.244598 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4553 10:51:59.248400 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4554 10:51:59.248957
4555 10:51:59.251259 [DATLAT]
4556 10:51:59.251719 Freq=600, CH1 RK0
4557 10:51:59.252125
4558 10:51:59.254339 DATLAT Default: 0x9
4559 10:51:59.254796 0, 0xFFFF, sum = 0
4560 10:51:59.258154 1, 0xFFFF, sum = 0
4561 10:51:59.258723 2, 0xFFFF, sum = 0
4562 10:51:59.261047 3, 0xFFFF, sum = 0
4563 10:51:59.261512 4, 0xFFFF, sum = 0
4564 10:51:59.264389 5, 0xFFFF, sum = 0
4565 10:51:59.264956 6, 0xFFFF, sum = 0
4566 10:51:59.267521 7, 0xFFFF, sum = 0
4567 10:51:59.268090 8, 0x0, sum = 1
4568 10:51:59.271207 9, 0x0, sum = 2
4569 10:51:59.271783 10, 0x0, sum = 3
4570 10:51:59.274178 11, 0x0, sum = 4
4571 10:51:59.274641 best_step = 9
4572 10:51:59.275004
4573 10:51:59.275338 ==
4574 10:51:59.277423 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 10:51:59.280884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 10:51:59.283882 ==
4577 10:51:59.284335 RX Vref Scan: 1
4578 10:51:59.284674
4579 10:51:59.287354 RX Vref 0 -> 0, step: 1
4580 10:51:59.287871
4581 10:51:59.291014 RX Delay -179 -> 252, step: 8
4582 10:51:59.291442
4583 10:51:59.293647 Set Vref, RX VrefLevel [Byte0]: 52
4584 10:51:59.297559 [Byte1]: 50
4585 10:51:59.298086
4586 10:51:59.300682 Final RX Vref Byte 0 = 52 to rank0
4587 10:51:59.304944 Final RX Vref Byte 1 = 50 to rank0
4588 10:51:59.306974 Final RX Vref Byte 0 = 52 to rank1
4589 10:51:59.309910 Final RX Vref Byte 1 = 50 to rank1==
4590 10:51:59.313420 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 10:51:59.316997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 10:51:59.317576 ==
4593 10:51:59.320278 DQS Delay:
4594 10:51:59.320847 DQS0 = 0, DQS1 = 0
4595 10:51:59.321218 DQM Delay:
4596 10:51:59.323117 DQM0 = 42, DQM1 = 34
4597 10:51:59.323580 DQ Delay:
4598 10:51:59.327199 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4599 10:51:59.329732 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4600 10:51:59.333165 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4601 10:51:59.336588 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4602 10:51:59.337219
4603 10:51:59.337612
4604 10:51:59.346317 [DQSOSCAuto] RK0, (LSB)MR18= 0x253e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
4605 10:51:59.349632 CH1 RK0: MR19=808, MR18=253E
4606 10:51:59.356670 CH1_RK0: MR19=0x808, MR18=0x253E, DQSOSC=398, MR23=63, INC=165, DEC=110
4607 10:51:59.357242
4608 10:51:59.360605 ----->DramcWriteLeveling(PI) begin...
4609 10:51:59.361076 ==
4610 10:51:59.362658 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 10:51:59.366415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 10:51:59.367116 ==
4613 10:51:59.369312 Write leveling (Byte 0): 30 => 30
4614 10:51:59.372483 Write leveling (Byte 1): 30 => 30
4615 10:51:59.375814 DramcWriteLeveling(PI) end<-----
4616 10:51:59.376365
4617 10:51:59.376741 ==
4618 10:51:59.379992 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 10:51:59.382809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 10:51:59.383379 ==
4621 10:51:59.385624 [Gating] SW mode calibration
4622 10:51:59.392711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4623 10:51:59.398596 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4624 10:51:59.402346 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 10:51:59.405572 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 10:51:59.411944 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4627 10:51:59.415018 0 9 12 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
4628 10:51:59.418533 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 10:51:59.425830 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 10:51:59.428497 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 10:51:59.432407 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 10:51:59.439003 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 10:51:59.442196 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 10:51:59.445225 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
4635 10:51:59.451409 0 10 12 | B1->B0 | 3030 4141 | 0 0 | (1 1) (0 0)
4636 10:51:59.455369 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 10:51:59.458110 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 10:51:59.464816 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 10:51:59.468015 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 10:51:59.474954 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 10:51:59.478360 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 10:51:59.481465 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 10:51:59.487845 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4644 10:51:59.491338 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 10:51:59.494508 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 10:51:59.501066 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 10:51:59.504576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 10:51:59.507543 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 10:51:59.514633 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 10:51:59.517322 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 10:51:59.520941 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 10:51:59.527623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 10:51:59.530562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 10:51:59.534540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 10:51:59.540903 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 10:51:59.543738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 10:51:59.548253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 10:51:59.553670 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4659 10:51:59.557068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4660 10:51:59.560019 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 10:51:59.563671 Total UI for P1: 0, mck2ui 16
4662 10:51:59.566786 best dqsien dly found for B0: ( 0, 13, 10)
4663 10:51:59.569874 Total UI for P1: 0, mck2ui 16
4664 10:51:59.573508 best dqsien dly found for B1: ( 0, 13, 12)
4665 10:51:59.577179 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4666 10:51:59.579796 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4667 10:51:59.580414
4668 10:51:59.586936 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4669 10:51:59.589718 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 10:51:59.590185 [Gating] SW calibration Done
4671 10:51:59.592943 ==
4672 10:51:59.597404 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 10:51:59.599910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 10:51:59.600519 ==
4675 10:51:59.600897 RX Vref Scan: 0
4676 10:51:59.601248
4677 10:51:59.603354 RX Vref 0 -> 0, step: 1
4678 10:51:59.603911
4679 10:51:59.606109 RX Delay -230 -> 252, step: 16
4680 10:51:59.610168 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4681 10:51:59.612710 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4682 10:51:59.619698 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4683 10:51:59.622667 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4684 10:51:59.626090 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4685 10:51:59.629488 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4686 10:51:59.636191 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4687 10:51:59.639433 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4688 10:51:59.643218 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4689 10:51:59.645698 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4690 10:51:59.652258 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4691 10:51:59.656351 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4692 10:51:59.659067 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4693 10:51:59.662291 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4694 10:51:59.668748 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4695 10:51:59.672029 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4696 10:51:59.672539 ==
4697 10:51:59.675462 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 10:51:59.678429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 10:51:59.678896 ==
4700 10:51:59.682207 DQS Delay:
4701 10:51:59.682763 DQS0 = 0, DQS1 = 0
4702 10:51:59.683138 DQM Delay:
4703 10:51:59.685481 DQM0 = 44, DQM1 = 39
4704 10:51:59.685949 DQ Delay:
4705 10:51:59.689319 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4706 10:51:59.691764 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4707 10:51:59.695185 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4708 10:51:59.698601 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4709 10:51:59.699162
4710 10:51:59.699620
4711 10:51:59.699976 ==
4712 10:51:59.702208 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 10:51:59.708850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 10:51:59.709412 ==
4715 10:51:59.709786
4716 10:51:59.710133
4717 10:51:59.710509 TX Vref Scan disable
4718 10:51:59.712355 == TX Byte 0 ==
4719 10:51:59.715415 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4720 10:51:59.722401 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4721 10:51:59.722985 == TX Byte 1 ==
4722 10:51:59.725163 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4723 10:51:59.731615 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4724 10:51:59.732232 ==
4725 10:51:59.735317 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 10:51:59.738476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 10:51:59.738975 ==
4728 10:51:59.739348
4729 10:51:59.739688
4730 10:51:59.741455 TX Vref Scan disable
4731 10:51:59.744849 == TX Byte 0 ==
4732 10:51:59.748825 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4733 10:51:59.751535 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4734 10:51:59.755092 == TX Byte 1 ==
4735 10:51:59.758473 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4736 10:51:59.761929 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4737 10:51:59.762503
4738 10:51:59.764732 [DATLAT]
4739 10:51:59.765282 Freq=600, CH1 RK1
4740 10:51:59.765655
4741 10:51:59.768236 DATLAT Default: 0x9
4742 10:51:59.768796 0, 0xFFFF, sum = 0
4743 10:51:59.771288 1, 0xFFFF, sum = 0
4744 10:51:59.771756 2, 0xFFFF, sum = 0
4745 10:51:59.775037 3, 0xFFFF, sum = 0
4746 10:51:59.775601 4, 0xFFFF, sum = 0
4747 10:51:59.778084 5, 0xFFFF, sum = 0
4748 10:51:59.778556 6, 0xFFFF, sum = 0
4749 10:51:59.780949 7, 0xFFFF, sum = 0
4750 10:51:59.781417 8, 0x0, sum = 1
4751 10:51:59.784959 9, 0x0, sum = 2
4752 10:51:59.785523 10, 0x0, sum = 3
4753 10:51:59.787661 11, 0x0, sum = 4
4754 10:51:59.788176 best_step = 9
4755 10:51:59.788552
4756 10:51:59.788899 ==
4757 10:51:59.790800 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 10:51:59.794496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 10:51:59.795068 ==
4760 10:51:59.798330 RX Vref Scan: 0
4761 10:51:59.798884
4762 10:51:59.801249 RX Vref 0 -> 0, step: 1
4763 10:51:59.801804
4764 10:51:59.802173 RX Delay -179 -> 252, step: 8
4765 10:51:59.809162 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4766 10:51:59.812353 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4767 10:51:59.815747 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4768 10:51:59.819577 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4769 10:51:59.826511 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4770 10:51:59.828760 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4771 10:51:59.831937 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4772 10:51:59.835416 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4773 10:51:59.841874 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4774 10:51:59.845069 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4775 10:51:59.849633 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4776 10:51:59.851751 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4777 10:51:59.858685 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4778 10:51:59.861806 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4779 10:51:59.865227 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4780 10:51:59.868323 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4781 10:51:59.868788 ==
4782 10:51:59.871839 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 10:51:59.878700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 10:51:59.879277 ==
4785 10:51:59.879651 DQS Delay:
4786 10:51:59.881722 DQS0 = 0, DQS1 = 0
4787 10:51:59.882276 DQM Delay:
4788 10:51:59.882647 DQM0 = 37, DQM1 = 34
4789 10:51:59.884760 DQ Delay:
4790 10:51:59.888428 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4791 10:51:59.891214 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4792 10:51:59.894950 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4793 10:51:59.898004 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4794 10:51:59.898558
4795 10:51:59.898925
4796 10:51:59.904574 [DQSOSCAuto] RK1, (LSB)MR18= 0x3459, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4797 10:51:59.908233 CH1 RK1: MR19=808, MR18=3459
4798 10:51:59.914881 CH1_RK1: MR19=0x808, MR18=0x3459, DQSOSC=393, MR23=63, INC=169, DEC=113
4799 10:51:59.918145 [RxdqsGatingPostProcess] freq 600
4800 10:51:59.925226 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4801 10:51:59.925785 Pre-setting of DQS Precalculation
4802 10:51:59.931051 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4803 10:51:59.937232 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4804 10:51:59.943870 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4805 10:51:59.944462
4806 10:51:59.944835
4807 10:51:59.947294 [Calibration Summary] 1200 Mbps
4808 10:51:59.950358 CH 0, Rank 0
4809 10:51:59.950815 SW Impedance : PASS
4810 10:51:59.954120 DUTY Scan : NO K
4811 10:51:59.957223 ZQ Calibration : PASS
4812 10:51:59.957783 Jitter Meter : NO K
4813 10:51:59.961419 CBT Training : PASS
4814 10:51:59.963907 Write leveling : PASS
4815 10:51:59.964556 RX DQS gating : PASS
4816 10:51:59.967176 RX DQ/DQS(RDDQC) : PASS
4817 10:51:59.970639 TX DQ/DQS : PASS
4818 10:51:59.971121 RX DATLAT : PASS
4819 10:51:59.973799 RX DQ/DQS(Engine): PASS
4820 10:51:59.974370 TX OE : NO K
4821 10:51:59.976851 All Pass.
4822 10:51:59.977341
4823 10:51:59.977711 CH 0, Rank 1
4824 10:51:59.980236 SW Impedance : PASS
4825 10:51:59.984141 DUTY Scan : NO K
4826 10:51:59.984698 ZQ Calibration : PASS
4827 10:51:59.986890 Jitter Meter : NO K
4828 10:51:59.987361 CBT Training : PASS
4829 10:51:59.990095 Write leveling : PASS
4830 10:51:59.994420 RX DQS gating : PASS
4831 10:51:59.994986 RX DQ/DQS(RDDQC) : PASS
4832 10:51:59.997192 TX DQ/DQS : PASS
4833 10:51:59.999610 RX DATLAT : PASS
4834 10:52:00.000104 RX DQ/DQS(Engine): PASS
4835 10:52:00.003517 TX OE : NO K
4836 10:52:00.004139 All Pass.
4837 10:52:00.004527
4838 10:52:00.006699 CH 1, Rank 0
4839 10:52:00.007268 SW Impedance : PASS
4840 10:52:00.009818 DUTY Scan : NO K
4841 10:52:00.012985 ZQ Calibration : PASS
4842 10:52:00.013455 Jitter Meter : NO K
4843 10:52:00.016467 CBT Training : PASS
4844 10:52:00.019684 Write leveling : PASS
4845 10:52:00.020293 RX DQS gating : PASS
4846 10:52:00.023140 RX DQ/DQS(RDDQC) : PASS
4847 10:52:00.027803 TX DQ/DQS : PASS
4848 10:52:00.028425 RX DATLAT : PASS
4849 10:52:00.029674 RX DQ/DQS(Engine): PASS
4850 10:52:00.032887 TX OE : NO K
4851 10:52:00.033457 All Pass.
4852 10:52:00.033834
4853 10:52:00.034180 CH 1, Rank 1
4854 10:52:00.036405 SW Impedance : PASS
4855 10:52:00.039454 DUTY Scan : NO K
4856 10:52:00.039922 ZQ Calibration : PASS
4857 10:52:00.043119 Jitter Meter : NO K
4858 10:52:00.045922 CBT Training : PASS
4859 10:52:00.046390 Write leveling : PASS
4860 10:52:00.049043 RX DQS gating : PASS
4861 10:52:00.052441 RX DQ/DQS(RDDQC) : PASS
4862 10:52:00.052907 TX DQ/DQS : PASS
4863 10:52:00.056356 RX DATLAT : PASS
4864 10:52:00.059157 RX DQ/DQS(Engine): PASS
4865 10:52:00.059723 TX OE : NO K
4866 10:52:00.060151 All Pass.
4867 10:52:00.062622
4868 10:52:00.063206 DramC Write-DBI off
4869 10:52:00.065960 PER_BANK_REFRESH: Hybrid Mode
4870 10:52:00.066521 TX_TRACKING: ON
4871 10:52:00.075504 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4872 10:52:00.079192 [FAST_K] Save calibration result to emmc
4873 10:52:00.082529 dramc_set_vcore_voltage set vcore to 662500
4874 10:52:00.085431 Read voltage for 933, 3
4875 10:52:00.085855 Vio18 = 0
4876 10:52:00.088888 Vcore = 662500
4877 10:52:00.089414 Vdram = 0
4878 10:52:00.089757 Vddq = 0
4879 10:52:00.090070 Vmddr = 0
4880 10:52:00.095520 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4881 10:52:00.102289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4882 10:52:00.102822 MEM_TYPE=3, freq_sel=17
4883 10:52:00.106539 sv_algorithm_assistance_LP4_1600
4884 10:52:00.108299 ============ PULL DRAM RESETB DOWN ============
4885 10:52:00.115342 ========== PULL DRAM RESETB DOWN end =========
4886 10:52:00.118867 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4887 10:52:00.122200 ===================================
4888 10:52:00.124953 LPDDR4 DRAM CONFIGURATION
4889 10:52:00.128399 ===================================
4890 10:52:00.128973 EX_ROW_EN[0] = 0x0
4891 10:52:00.131842 EX_ROW_EN[1] = 0x0
4892 10:52:00.135740 LP4Y_EN = 0x0
4893 10:52:00.136344 WORK_FSP = 0x0
4894 10:52:00.138109 WL = 0x3
4895 10:52:00.138571 RL = 0x3
4896 10:52:00.142024 BL = 0x2
4897 10:52:00.142592 RPST = 0x0
4898 10:52:00.144534 RD_PRE = 0x0
4899 10:52:00.144999 WR_PRE = 0x1
4900 10:52:00.148131 WR_PST = 0x0
4901 10:52:00.148601 DBI_WR = 0x0
4902 10:52:00.151366 DBI_RD = 0x0
4903 10:52:00.151940 OTF = 0x1
4904 10:52:00.155296 ===================================
4905 10:52:00.157812 ===================================
4906 10:52:00.161266 ANA top config
4907 10:52:00.164201 ===================================
4908 10:52:00.167403 DLL_ASYNC_EN = 0
4909 10:52:00.167867 ALL_SLAVE_EN = 1
4910 10:52:00.171034 NEW_RANK_MODE = 1
4911 10:52:00.174143 DLL_IDLE_MODE = 1
4912 10:52:00.177793 LP45_APHY_COMB_EN = 1
4913 10:52:00.178258 TX_ODT_DIS = 1
4914 10:52:00.181003 NEW_8X_MODE = 1
4915 10:52:00.184486 ===================================
4916 10:52:00.187750 ===================================
4917 10:52:00.190903 data_rate = 1866
4918 10:52:00.193876 CKR = 1
4919 10:52:00.198083 DQ_P2S_RATIO = 8
4920 10:52:00.200611 ===================================
4921 10:52:00.203865 CA_P2S_RATIO = 8
4922 10:52:00.204468 DQ_CA_OPEN = 0
4923 10:52:00.207809 DQ_SEMI_OPEN = 0
4924 10:52:00.210916 CA_SEMI_OPEN = 0
4925 10:52:00.213734 CA_FULL_RATE = 0
4926 10:52:00.217333 DQ_CKDIV4_EN = 1
4927 10:52:00.220765 CA_CKDIV4_EN = 1
4928 10:52:00.221232 CA_PREDIV_EN = 0
4929 10:52:00.223801 PH8_DLY = 0
4930 10:52:00.227071 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4931 10:52:00.230295 DQ_AAMCK_DIV = 4
4932 10:52:00.234033 CA_AAMCK_DIV = 4
4933 10:52:00.237308 CA_ADMCK_DIV = 4
4934 10:52:00.239974 DQ_TRACK_CA_EN = 0
4935 10:52:00.240465 CA_PICK = 933
4936 10:52:00.244253 CA_MCKIO = 933
4937 10:52:00.247176 MCKIO_SEMI = 0
4938 10:52:00.250151 PLL_FREQ = 3732
4939 10:52:00.253539 DQ_UI_PI_RATIO = 32
4940 10:52:00.256978 CA_UI_PI_RATIO = 0
4941 10:52:00.260120 ===================================
4942 10:52:00.264086 ===================================
4943 10:52:00.266700 memory_type:LPDDR4
4944 10:52:00.267226 GP_NUM : 10
4945 10:52:00.269742 SRAM_EN : 1
4946 10:52:00.270168 MD32_EN : 0
4947 10:52:00.272808 ===================================
4948 10:52:00.276412 [ANA_INIT] >>>>>>>>>>>>>>
4949 10:52:00.279499 <<<<<< [CONFIGURE PHASE]: ANA_TX
4950 10:52:00.283122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4951 10:52:00.286774 ===================================
4952 10:52:00.289589 data_rate = 1866,PCW = 0X8f00
4953 10:52:00.292735 ===================================
4954 10:52:00.296748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4955 10:52:00.299938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 10:52:00.306846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 10:52:00.313207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4958 10:52:00.316236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4959 10:52:00.319770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4960 10:52:00.320407 [ANA_INIT] flow start
4961 10:52:00.322757 [ANA_INIT] PLL >>>>>>>>
4962 10:52:00.326754 [ANA_INIT] PLL <<<<<<<<
4963 10:52:00.327324 [ANA_INIT] MIDPI >>>>>>>>
4964 10:52:00.329499 [ANA_INIT] MIDPI <<<<<<<<
4965 10:52:00.332396 [ANA_INIT] DLL >>>>>>>>
4966 10:52:00.332867 [ANA_INIT] flow end
4967 10:52:00.339306 ============ LP4 DIFF to SE enter ============
4968 10:52:00.342827 ============ LP4 DIFF to SE exit ============
4969 10:52:00.345754 [ANA_INIT] <<<<<<<<<<<<<
4970 10:52:00.349026 [Flow] Enable top DCM control >>>>>
4971 10:52:00.352403 [Flow] Enable top DCM control <<<<<
4972 10:52:00.352996 Enable DLL master slave shuffle
4973 10:52:00.358962 ==============================================================
4974 10:52:00.362408 Gating Mode config
4975 10:52:00.366171 ==============================================================
4976 10:52:00.369016 Config description:
4977 10:52:00.378595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4978 10:52:00.385354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4979 10:52:00.388629 SELPH_MODE 0: By rank 1: By Phase
4980 10:52:00.395355 ==============================================================
4981 10:52:00.398735 GAT_TRACK_EN = 1
4982 10:52:00.402373 RX_GATING_MODE = 2
4983 10:52:00.405225 RX_GATING_TRACK_MODE = 2
4984 10:52:00.408466 SELPH_MODE = 1
4985 10:52:00.412744 PICG_EARLY_EN = 1
4986 10:52:00.413468 VALID_LAT_VALUE = 1
4987 10:52:00.418957 ==============================================================
4988 10:52:00.422021 Enter into Gating configuration >>>>
4989 10:52:00.424900 Exit from Gating configuration <<<<
4990 10:52:00.427924 Enter into DVFS_PRE_config >>>>>
4991 10:52:00.441441 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4992 10:52:00.442015 Exit from DVFS_PRE_config <<<<<
4993 10:52:00.444491 Enter into PICG configuration >>>>
4994 10:52:00.447603 Exit from PICG configuration <<<<
4995 10:52:00.451139 [RX_INPUT] configuration >>>>>
4996 10:52:00.454496 [RX_INPUT] configuration <<<<<
4997 10:52:00.460926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4998 10:52:00.465051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4999 10:52:00.470539 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 10:52:00.477275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 10:52:00.483793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 10:52:00.490425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 10:52:00.493792 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5004 10:52:00.496526 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5005 10:52:00.503395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5006 10:52:00.506814 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5007 10:52:00.510197 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5008 10:52:00.513048 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 10:52:00.516732 ===================================
5010 10:52:00.519988 LPDDR4 DRAM CONFIGURATION
5011 10:52:00.523419 ===================================
5012 10:52:00.527009 EX_ROW_EN[0] = 0x0
5013 10:52:00.527477 EX_ROW_EN[1] = 0x0
5014 10:52:00.529988 LP4Y_EN = 0x0
5015 10:52:00.530561 WORK_FSP = 0x0
5016 10:52:00.533113 WL = 0x3
5017 10:52:00.536527 RL = 0x3
5018 10:52:00.536995 BL = 0x2
5019 10:52:00.539917 RPST = 0x0
5020 10:52:00.540416 RD_PRE = 0x0
5021 10:52:00.543375 WR_PRE = 0x1
5022 10:52:00.543959 WR_PST = 0x0
5023 10:52:00.546243 DBI_WR = 0x0
5024 10:52:00.546811 DBI_RD = 0x0
5025 10:52:00.549396 OTF = 0x1
5026 10:52:00.552788 ===================================
5027 10:52:00.556480 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5028 10:52:00.559416 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5029 10:52:00.566129 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 10:52:00.569315 ===================================
5031 10:52:00.569899 LPDDR4 DRAM CONFIGURATION
5032 10:52:00.572296 ===================================
5033 10:52:00.575952 EX_ROW_EN[0] = 0x10
5034 10:52:00.576463 EX_ROW_EN[1] = 0x0
5035 10:52:00.578875 LP4Y_EN = 0x0
5036 10:52:00.582616 WORK_FSP = 0x0
5037 10:52:00.583095 WL = 0x3
5038 10:52:00.586436 RL = 0x3
5039 10:52:00.587024 BL = 0x2
5040 10:52:00.589145 RPST = 0x0
5041 10:52:00.589728 RD_PRE = 0x0
5042 10:52:00.592275 WR_PRE = 0x1
5043 10:52:00.592720 WR_PST = 0x0
5044 10:52:00.595412 DBI_WR = 0x0
5045 10:52:00.595880 DBI_RD = 0x0
5046 10:52:00.598665 OTF = 0x1
5047 10:52:00.602423 ===================================
5048 10:52:00.608681 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5049 10:52:00.612132 nWR fixed to 30
5050 10:52:00.612604 [ModeRegInit_LP4] CH0 RK0
5051 10:52:00.615492 [ModeRegInit_LP4] CH0 RK1
5052 10:52:00.618414 [ModeRegInit_LP4] CH1 RK0
5053 10:52:00.622663 [ModeRegInit_LP4] CH1 RK1
5054 10:52:00.623229 match AC timing 9
5055 10:52:00.625127 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5056 10:52:00.632417 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5057 10:52:00.635028 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5058 10:52:00.641405 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5059 10:52:00.645775 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5060 10:52:00.646305 ==
5061 10:52:00.648547 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 10:52:00.652594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 10:52:00.653124 ==
5064 10:52:00.659134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 10:52:00.664995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5066 10:52:00.668684 [CA 0] Center 37 (7~68) winsize 62
5067 10:52:00.671690 [CA 1] Center 37 (7~68) winsize 62
5068 10:52:00.674607 [CA 2] Center 34 (4~64) winsize 61
5069 10:52:00.677779 [CA 3] Center 34 (4~65) winsize 62
5070 10:52:00.681084 [CA 4] Center 32 (2~63) winsize 62
5071 10:52:00.685132 [CA 5] Center 32 (2~63) winsize 62
5072 10:52:00.685658
5073 10:52:00.687628 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5074 10:52:00.688092
5075 10:52:00.690760 [CATrainingPosCal] consider 1 rank data
5076 10:52:00.694308 u2DelayCellTimex100 = 270/100 ps
5077 10:52:00.697477 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 10:52:00.700610 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 10:52:00.704148 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5080 10:52:00.707418 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 10:52:00.710668 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5082 10:52:00.717409 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5083 10:52:00.717943
5084 10:52:00.720537 CA PerBit enable=1, Macro0, CA PI delay=32
5085 10:52:00.721069
5086 10:52:00.723862 [CBTSetCACLKResult] CA Dly = 32
5087 10:52:00.724342 CS Dly: 5 (0~36)
5088 10:52:00.724683 ==
5089 10:52:00.727406 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 10:52:00.730307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 10:52:00.733867 ==
5092 10:52:00.737176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 10:52:00.743573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5094 10:52:00.747085 [CA 0] Center 38 (8~68) winsize 61
5095 10:52:00.750479 [CA 1] Center 37 (7~68) winsize 62
5096 10:52:00.753457 [CA 2] Center 34 (4~65) winsize 62
5097 10:52:00.756476 [CA 3] Center 34 (4~65) winsize 62
5098 10:52:00.760285 [CA 4] Center 33 (2~64) winsize 63
5099 10:52:00.763305 [CA 5] Center 32 (2~63) winsize 62
5100 10:52:00.763834
5101 10:52:00.766463 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5102 10:52:00.766990
5103 10:52:00.770612 [CATrainingPosCal] consider 2 rank data
5104 10:52:00.773571 u2DelayCellTimex100 = 270/100 ps
5105 10:52:00.776318 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5106 10:52:00.780254 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5107 10:52:00.786375 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5108 10:52:00.790301 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5109 10:52:00.792845 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5110 10:52:00.796408 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5111 10:52:00.796958
5112 10:52:00.799356 CA PerBit enable=1, Macro0, CA PI delay=32
5113 10:52:00.799780
5114 10:52:00.803003 [CBTSetCACLKResult] CA Dly = 32
5115 10:52:00.803539 CS Dly: 6 (0~39)
5116 10:52:00.806503
5117 10:52:00.809183 ----->DramcWriteLeveling(PI) begin...
5118 10:52:00.809615 ==
5119 10:52:00.812807 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 10:52:00.816405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 10:52:00.816949 ==
5122 10:52:00.819232 Write leveling (Byte 0): 33 => 33
5123 10:52:00.822801 Write leveling (Byte 1): 27 => 27
5124 10:52:00.826036 DramcWriteLeveling(PI) end<-----
5125 10:52:00.826462
5126 10:52:00.826827 ==
5127 10:52:00.829684 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 10:52:00.833848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 10:52:00.834379 ==
5130 10:52:00.835761 [Gating] SW mode calibration
5131 10:52:00.842391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5132 10:52:00.848882 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5133 10:52:00.851806 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5134 10:52:00.855660 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 10:52:00.862139 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 10:52:00.865301 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 10:52:00.868830 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 10:52:00.874965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 10:52:00.878783 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5140 10:52:00.882026 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
5141 10:52:00.888767 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
5142 10:52:00.891586 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 10:52:00.894855 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 10:52:00.901654 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 10:52:00.904917 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 10:52:00.908089 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 10:52:00.914924 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5148 10:52:00.917883 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5149 10:52:00.922372 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5150 10:52:00.928190 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 10:52:00.930835 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 10:52:00.934669 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 10:52:00.940914 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 10:52:00.943952 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 10:52:00.948090 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 10:52:00.954155 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 10:52:00.957935 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5158 10:52:00.961031 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 10:52:00.967341 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 10:52:00.970800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 10:52:00.974516 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 10:52:00.980361 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 10:52:00.983958 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 10:52:00.987057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 10:52:00.993643 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 10:52:00.996941 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 10:52:01.000248 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 10:52:01.006689 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 10:52:01.010161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 10:52:01.016588 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 10:52:01.019717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5172 10:52:01.023374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5173 10:52:01.026646 Total UI for P1: 0, mck2ui 16
5174 10:52:01.029803 best dqsien dly found for B0: ( 1, 2, 24)
5175 10:52:01.032918 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5176 10:52:01.039848 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5177 10:52:01.042693 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 10:52:01.046280 Total UI for P1: 0, mck2ui 16
5179 10:52:01.050362 best dqsien dly found for B1: ( 1, 3, 2)
5180 10:52:01.052873 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5181 10:52:01.055685 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5182 10:52:01.056190
5183 10:52:01.059023 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5184 10:52:01.065799 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5185 10:52:01.066364 [Gating] SW calibration Done
5186 10:52:01.066739 ==
5187 10:52:01.069326 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 10:52:01.075667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 10:52:01.076325 ==
5190 10:52:01.076874 RX Vref Scan: 0
5191 10:52:01.077235
5192 10:52:01.079130 RX Vref 0 -> 0, step: 1
5193 10:52:01.079592
5194 10:52:01.082444 RX Delay -80 -> 252, step: 8
5195 10:52:01.085195 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5196 10:52:01.088854 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5197 10:52:01.091769 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5198 10:52:01.099437 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5199 10:52:01.102455 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5200 10:52:01.105035 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5201 10:52:01.108121 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5202 10:52:01.111438 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5203 10:52:01.118340 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5204 10:52:01.121389 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5205 10:52:01.124959 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5206 10:52:01.127865 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5207 10:52:01.131229 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5208 10:52:01.138352 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5209 10:52:01.141569 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5210 10:52:01.145126 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5211 10:52:01.145686 ==
5212 10:52:01.147798 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 10:52:01.150998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 10:52:01.151568 ==
5215 10:52:01.154352 DQS Delay:
5216 10:52:01.154888 DQS0 = 0, DQS1 = 0
5217 10:52:01.155275 DQM Delay:
5218 10:52:01.158120 DQM0 = 101, DQM1 = 88
5219 10:52:01.158729 DQ Delay:
5220 10:52:01.160697 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5221 10:52:01.163798 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5222 10:52:01.167178 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5223 10:52:01.171049 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5224 10:52:01.174340
5225 10:52:01.174900
5226 10:52:01.175271 ==
5227 10:52:01.177390 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 10:52:01.180667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 10:52:01.181130 ==
5230 10:52:01.181497
5231 10:52:01.181835
5232 10:52:01.183632 TX Vref Scan disable
5233 10:52:01.184129 == TX Byte 0 ==
5234 10:52:01.190517 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5235 10:52:01.194082 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5236 10:52:01.194608 == TX Byte 1 ==
5237 10:52:01.200609 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5238 10:52:01.206018 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5239 10:52:01.206435 ==
5240 10:52:01.207061 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 10:52:01.210954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 10:52:01.211485 ==
5243 10:52:01.211821
5244 10:52:01.212182
5245 10:52:01.213996 TX Vref Scan disable
5246 10:52:01.217030 == TX Byte 0 ==
5247 10:52:01.220549 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5248 10:52:01.223518 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5249 10:52:01.226705 == TX Byte 1 ==
5250 10:52:01.230090 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5251 10:52:01.236411 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5252 10:52:01.236953
5253 10:52:01.237302 [DATLAT]
5254 10:52:01.237618 Freq=933, CH0 RK0
5255 10:52:01.237921
5256 10:52:01.240142 DATLAT Default: 0xd
5257 10:52:01.240663 0, 0xFFFF, sum = 0
5258 10:52:01.243048 1, 0xFFFF, sum = 0
5259 10:52:01.247240 2, 0xFFFF, sum = 0
5260 10:52:01.247776 3, 0xFFFF, sum = 0
5261 10:52:01.250002 4, 0xFFFF, sum = 0
5262 10:52:01.250457 5, 0xFFFF, sum = 0
5263 10:52:01.253396 6, 0xFFFF, sum = 0
5264 10:52:01.253927 7, 0xFFFF, sum = 0
5265 10:52:01.256176 8, 0xFFFF, sum = 0
5266 10:52:01.256700 9, 0xFFFF, sum = 0
5267 10:52:01.259743 10, 0x0, sum = 1
5268 10:52:01.260197 11, 0x0, sum = 2
5269 10:52:01.263373 12, 0x0, sum = 3
5270 10:52:01.263941 13, 0x0, sum = 4
5271 10:52:01.265844 best_step = 11
5272 10:52:01.266262
5273 10:52:01.266591 ==
5274 10:52:01.269326 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 10:52:01.272884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 10:52:01.273408 ==
5277 10:52:01.273750 RX Vref Scan: 1
5278 10:52:01.274066
5279 10:52:01.275872 RX Vref 0 -> 0, step: 1
5280 10:52:01.276310
5281 10:52:01.279307 RX Delay -61 -> 252, step: 4
5282 10:52:01.279740
5283 10:52:01.282667 Set Vref, RX VrefLevel [Byte0]: 51
5284 10:52:01.285715 [Byte1]: 49
5285 10:52:01.288977
5286 10:52:01.289397 Final RX Vref Byte 0 = 51 to rank0
5287 10:52:01.292137 Final RX Vref Byte 1 = 49 to rank0
5288 10:52:01.295953 Final RX Vref Byte 0 = 51 to rank1
5289 10:52:01.299291 Final RX Vref Byte 1 = 49 to rank1==
5290 10:52:01.302033 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 10:52:01.309182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 10:52:01.309707 ==
5293 10:52:01.310050 DQS Delay:
5294 10:52:01.312412 DQS0 = 0, DQS1 = 0
5295 10:52:01.312934 DQM Delay:
5296 10:52:01.313278 DQM0 = 99, DQM1 = 87
5297 10:52:01.315772 DQ Delay:
5298 10:52:01.319048 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5299 10:52:01.321935 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5300 10:52:01.325202 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5301 10:52:01.329043 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5302 10:52:01.329571
5303 10:52:01.329904
5304 10:52:01.335025 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5305 10:52:01.339028 CH0 RK0: MR19=505, MR18=1610
5306 10:52:01.344993 CH0_RK0: MR19=0x505, MR18=0x1610, DQSOSC=414, MR23=63, INC=63, DEC=42
5307 10:52:01.345519
5308 10:52:01.348392 ----->DramcWriteLeveling(PI) begin...
5309 10:52:01.348820 ==
5310 10:52:01.351319 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 10:52:01.354574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 10:52:01.358460 ==
5313 10:52:01.358970 Write leveling (Byte 0): 32 => 32
5314 10:52:01.362011 Write leveling (Byte 1): 29 => 29
5315 10:52:01.364872 DramcWriteLeveling(PI) end<-----
5316 10:52:01.365398
5317 10:52:01.365732 ==
5318 10:52:01.368121 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 10:52:01.375564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 10:52:01.376126 ==
5321 10:52:01.376472 [Gating] SW mode calibration
5322 10:52:01.385030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5323 10:52:01.388118 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5324 10:52:01.394562 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5325 10:52:01.397951 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 10:52:01.401104 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 10:52:01.407747 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 10:52:01.411662 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 10:52:01.414169 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 10:52:01.421192 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5331 10:52:01.424798 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 1) (1 0)
5332 10:52:01.427280 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5333 10:52:01.433970 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 10:52:01.437441 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 10:52:01.440512 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 10:52:01.447197 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 10:52:01.450273 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 10:52:01.453994 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 10:52:01.460555 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (1 1)
5340 10:52:01.463520 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5341 10:52:01.466453 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 10:52:01.473383 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 10:52:01.476772 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 10:52:01.480141 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 10:52:01.486840 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 10:52:01.489903 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5347 10:52:01.493381 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5348 10:52:01.499901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 10:52:01.503193 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 10:52:01.506338 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 10:52:01.513607 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 10:52:01.516121 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 10:52:01.520462 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 10:52:01.526819 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 10:52:01.529146 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 10:52:01.533011 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 10:52:01.539120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 10:52:01.542968 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 10:52:01.546078 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 10:52:01.552692 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 10:52:01.555598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 10:52:01.558933 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5363 10:52:01.565881 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5364 10:52:01.570332 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 10:52:01.572252 Total UI for P1: 0, mck2ui 16
5366 10:52:01.575439 best dqsien dly found for B0: ( 1, 2, 26)
5367 10:52:01.579200 Total UI for P1: 0, mck2ui 16
5368 10:52:01.581779 best dqsien dly found for B1: ( 1, 2, 28)
5369 10:52:01.585244 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5370 10:52:01.588789 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5371 10:52:01.589239
5372 10:52:01.591836 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5373 10:52:01.594926 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5374 10:52:01.599332 [Gating] SW calibration Done
5375 10:52:01.599881 ==
5376 10:52:01.602085 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 10:52:01.608153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 10:52:01.608692 ==
5379 10:52:01.609052 RX Vref Scan: 0
5380 10:52:01.609384
5381 10:52:01.611580 RX Vref 0 -> 0, step: 1
5382 10:52:01.612062
5383 10:52:01.615017 RX Delay -80 -> 252, step: 8
5384 10:52:01.618317 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5385 10:52:01.621611 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5386 10:52:01.625387 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5387 10:52:01.628310 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5388 10:52:01.634757 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5389 10:52:01.638193 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5390 10:52:01.641582 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5391 10:52:01.644608 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5392 10:52:01.647933 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5393 10:52:01.651723 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5394 10:52:01.657546 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5395 10:52:01.661192 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5396 10:52:01.664602 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5397 10:52:01.667556 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5398 10:52:01.671582 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5399 10:52:01.677353 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5400 10:52:01.677890 ==
5401 10:52:01.681320 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 10:52:01.683947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 10:52:01.684519 ==
5404 10:52:01.684886 DQS Delay:
5405 10:52:01.687576 DQS0 = 0, DQS1 = 0
5406 10:52:01.688028 DQM Delay:
5407 10:52:01.690691 DQM0 = 99, DQM1 = 88
5408 10:52:01.691143 DQ Delay:
5409 10:52:01.694128 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5410 10:52:01.697580 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =107
5411 10:52:01.700479 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5412 10:52:01.703549 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5413 10:52:01.704103
5414 10:52:01.704452
5415 10:52:01.704763 ==
5416 10:52:01.707215 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 10:52:01.710453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 10:52:01.714291 ==
5419 10:52:01.714812
5420 10:52:01.715149
5421 10:52:01.715465 TX Vref Scan disable
5422 10:52:01.717167 == TX Byte 0 ==
5423 10:52:01.719965 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5424 10:52:01.727544 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5425 10:52:01.728133 == TX Byte 1 ==
5426 10:52:01.730434 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5427 10:52:01.736887 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5428 10:52:01.737545 ==
5429 10:52:01.740204 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 10:52:01.743378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 10:52:01.743943 ==
5432 10:52:01.744378
5433 10:52:01.744724
5434 10:52:01.746559 TX Vref Scan disable
5435 10:52:01.750187 == TX Byte 0 ==
5436 10:52:01.753353 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5437 10:52:01.756852 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5438 10:52:01.759643 == TX Byte 1 ==
5439 10:52:01.763070 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5440 10:52:01.766239 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5441 10:52:01.766806
5442 10:52:01.767180 [DATLAT]
5443 10:52:01.770325 Freq=933, CH0 RK1
5444 10:52:01.770910
5445 10:52:01.772939 DATLAT Default: 0xb
5446 10:52:01.773405 0, 0xFFFF, sum = 0
5447 10:52:01.776192 1, 0xFFFF, sum = 0
5448 10:52:01.776825 2, 0xFFFF, sum = 0
5449 10:52:01.779255 3, 0xFFFF, sum = 0
5450 10:52:01.779824 4, 0xFFFF, sum = 0
5451 10:52:01.782293 5, 0xFFFF, sum = 0
5452 10:52:01.782910 6, 0xFFFF, sum = 0
5453 10:52:01.786333 7, 0xFFFF, sum = 0
5454 10:52:01.786900 8, 0xFFFF, sum = 0
5455 10:52:01.789135 9, 0xFFFF, sum = 0
5456 10:52:01.789607 10, 0x0, sum = 1
5457 10:52:01.792213 11, 0x0, sum = 2
5458 10:52:01.792773 12, 0x0, sum = 3
5459 10:52:01.795482 13, 0x0, sum = 4
5460 10:52:01.796138 best_step = 11
5461 10:52:01.796521
5462 10:52:01.796871 ==
5463 10:52:01.798940 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 10:52:01.802263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 10:52:01.805641 ==
5466 10:52:01.806185 RX Vref Scan: 0
5467 10:52:01.806554
5468 10:52:01.808851 RX Vref 0 -> 0, step: 1
5469 10:52:01.809310
5470 10:52:01.811973 RX Delay -61 -> 252, step: 4
5471 10:52:01.815559 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5472 10:52:01.818728 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5473 10:52:01.825017 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5474 10:52:01.828606 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5475 10:52:01.831831 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5476 10:52:01.835289 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5477 10:52:01.839321 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5478 10:52:01.841814 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5479 10:52:01.848868 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5480 10:52:01.851713 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5481 10:52:01.854901 iDelay=195, Bit 10, Center 86 (-5 ~ 178) 184
5482 10:52:01.857828 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5483 10:52:01.861814 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5484 10:52:01.868221 iDelay=195, Bit 13, Center 94 (7 ~ 182) 176
5485 10:52:01.871683 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5486 10:52:01.874865 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5487 10:52:01.875432 ==
5488 10:52:01.879500 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 10:52:01.881146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 10:52:01.881625 ==
5491 10:52:01.884660 DQS Delay:
5492 10:52:01.885127 DQS0 = 0, DQS1 = 0
5493 10:52:01.887868 DQM Delay:
5494 10:52:01.888473 DQM0 = 97, DQM1 = 88
5495 10:52:01.888851 DQ Delay:
5496 10:52:01.891909 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5497 10:52:01.894374 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =104
5498 10:52:01.898227 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =82
5499 10:52:01.900706 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5500 10:52:01.904138
5501 10:52:01.904601
5502 10:52:01.910750 [DQSOSCAuto] RK1, (LSB)MR18= 0x120f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5503 10:52:01.914197 CH0 RK1: MR19=505, MR18=120F
5504 10:52:01.921094 CH0_RK1: MR19=0x505, MR18=0x120F, DQSOSC=416, MR23=63, INC=62, DEC=41
5505 10:52:01.924002 [RxdqsGatingPostProcess] freq 933
5506 10:52:01.927978 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 10:52:01.930978 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 10:52:01.934664 best DQS1 dly(2T, 0.5T) = (0, 11)
5509 10:52:01.937424 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 10:52:01.940681 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5511 10:52:01.943890 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 10:52:01.947121 best DQS1 dly(2T, 0.5T) = (0, 10)
5513 10:52:01.950239 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 10:52:01.953847 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5515 10:52:01.957301 Pre-setting of DQS Precalculation
5516 10:52:01.960471 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 10:52:01.961048 ==
5518 10:52:01.963662 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 10:52:01.970374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 10:52:01.970948 ==
5521 10:52:01.974305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 10:52:01.979827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 10:52:01.983041 [CA 0] Center 37 (6~68) winsize 63
5524 10:52:01.986276 [CA 1] Center 37 (6~68) winsize 63
5525 10:52:01.990165 [CA 2] Center 35 (5~65) winsize 61
5526 10:52:01.993216 [CA 3] Center 34 (4~64) winsize 61
5527 10:52:01.996655 [CA 4] Center 34 (4~65) winsize 62
5528 10:52:01.999839 [CA 5] Center 33 (3~64) winsize 62
5529 10:52:02.000454
5530 10:52:02.002912 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 10:52:02.003468
5532 10:52:02.006459 [CATrainingPosCal] consider 1 rank data
5533 10:52:02.009370 u2DelayCellTimex100 = 270/100 ps
5534 10:52:02.012754 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5535 10:52:02.019223 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5536 10:52:02.022760 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5537 10:52:02.026094 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 10:52:02.029055 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 10:52:02.033598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 10:52:02.034162
5541 10:52:02.035558 CA PerBit enable=1, Macro0, CA PI delay=33
5542 10:52:02.036027
5543 10:52:02.038911 [CBTSetCACLKResult] CA Dly = 33
5544 10:52:02.042404 CS Dly: 5 (0~36)
5545 10:52:02.042967 ==
5546 10:52:02.046046 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 10:52:02.049426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 10:52:02.049991 ==
5549 10:52:02.055692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 10:52:02.062081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5551 10:52:02.065440 [CA 0] Center 36 (6~67) winsize 62
5552 10:52:02.068745 [CA 1] Center 36 (6~67) winsize 62
5553 10:52:02.071930 [CA 2] Center 34 (4~65) winsize 62
5554 10:52:02.075942 [CA 3] Center 33 (3~64) winsize 62
5555 10:52:02.079199 [CA 4] Center 34 (3~65) winsize 63
5556 10:52:02.081621 [CA 5] Center 33 (3~64) winsize 62
5557 10:52:02.082204
5558 10:52:02.084948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5559 10:52:02.085413
5560 10:52:02.087969 [CATrainingPosCal] consider 2 rank data
5561 10:52:02.091637 u2DelayCellTimex100 = 270/100 ps
5562 10:52:02.095060 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 10:52:02.098064 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 10:52:02.101767 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5565 10:52:02.104473 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 10:52:02.108029 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 10:52:02.111160 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 10:52:02.114235
5569 10:52:02.118051 CA PerBit enable=1, Macro0, CA PI delay=33
5570 10:52:02.118641
5571 10:52:02.120929 [CBTSetCACLKResult] CA Dly = 33
5572 10:52:02.121354 CS Dly: 6 (0~39)
5573 10:52:02.121696
5574 10:52:02.124163 ----->DramcWriteLeveling(PI) begin...
5575 10:52:02.124633 ==
5576 10:52:02.127697 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 10:52:02.131291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 10:52:02.134618 ==
5579 10:52:02.135140 Write leveling (Byte 0): 24 => 24
5580 10:52:02.137741 Write leveling (Byte 1): 29 => 29
5581 10:52:02.140514 DramcWriteLeveling(PI) end<-----
5582 10:52:02.140939
5583 10:52:02.141273 ==
5584 10:52:02.144412 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 10:52:02.151176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 10:52:02.151699 ==
5587 10:52:02.154049 [Gating] SW mode calibration
5588 10:52:02.160669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 10:52:02.164269 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 10:52:02.170296 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 10:52:02.173676 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 10:52:02.177172 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 10:52:02.183449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 10:52:02.187372 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 10:52:02.189815 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 10:52:02.197807 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
5597 10:52:02.199765 0 14 28 | B1->B0 | 2a2a 2727 | 0 0 | (0 1) (0 1)
5598 10:52:02.205140 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 10:52:02.209664 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 10:52:02.213217 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 10:52:02.216760 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 10:52:02.222793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 10:52:02.226136 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 10:52:02.229332 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 10:52:02.236263 0 15 28 | B1->B0 | 4040 3b3b | 0 0 | (0 0) (0 0)
5606 10:52:02.239194 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 10:52:02.242793 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 10:52:02.249292 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 10:52:02.253152 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 10:52:02.256458 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 10:52:02.262314 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 10:52:02.266129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 10:52:02.268960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 10:52:02.275711 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 10:52:02.279178 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 10:52:02.281803 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 10:52:02.288958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 10:52:02.291899 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 10:52:02.296444 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 10:52:02.301453 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 10:52:02.305813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 10:52:02.308592 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 10:52:02.315510 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 10:52:02.318408 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 10:52:02.321572 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 10:52:02.328105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 10:52:02.331264 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 10:52:02.334541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5629 10:52:02.340955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5630 10:52:02.344197 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 10:52:02.347779 Total UI for P1: 0, mck2ui 16
5632 10:52:02.351434 best dqsien dly found for B0: ( 1, 2, 26)
5633 10:52:02.354594 Total UI for P1: 0, mck2ui 16
5634 10:52:02.357671 best dqsien dly found for B1: ( 1, 2, 28)
5635 10:52:02.361112 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5636 10:52:02.364448 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5637 10:52:02.365009
5638 10:52:02.367822 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5639 10:52:02.374377 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5640 10:52:02.374934 [Gating] SW calibration Done
5641 10:52:02.375300 ==
5642 10:52:02.377678 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 10:52:02.384003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 10:52:02.384828 ==
5645 10:52:02.385217 RX Vref Scan: 0
5646 10:52:02.385743
5647 10:52:02.387133 RX Vref 0 -> 0, step: 1
5648 10:52:02.387592
5649 10:52:02.390705 RX Delay -80 -> 252, step: 8
5650 10:52:02.394282 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5651 10:52:02.397010 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5652 10:52:02.400696 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5653 10:52:02.407110 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5654 10:52:02.410445 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5655 10:52:02.413477 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5656 10:52:02.417030 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5657 10:52:02.420768 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5658 10:52:02.423190 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5659 10:52:02.429926 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5660 10:52:02.433265 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5661 10:52:02.437022 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5662 10:52:02.439863 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5663 10:52:02.443904 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5664 10:52:02.449637 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5665 10:52:02.453262 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5666 10:52:02.453825 ==
5667 10:52:02.456902 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 10:52:02.459465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 10:52:02.459926 ==
5670 10:52:02.460341 DQS Delay:
5671 10:52:02.463354 DQS0 = 0, DQS1 = 0
5672 10:52:02.463913 DQM Delay:
5673 10:52:02.466595 DQM0 = 98, DQM1 = 92
5674 10:52:02.467154 DQ Delay:
5675 10:52:02.469970 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5676 10:52:02.472758 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5677 10:52:02.476906 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5678 10:52:02.479668 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5679 10:52:02.480247
5680 10:52:02.480613
5681 10:52:02.480950 ==
5682 10:52:02.483248 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 10:52:02.489432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 10:52:02.489955 ==
5685 10:52:02.490329
5686 10:52:02.490669
5687 10:52:02.490994 TX Vref Scan disable
5688 10:52:02.492822 == TX Byte 0 ==
5689 10:52:02.496384 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5690 10:52:02.503400 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5691 10:52:02.503917 == TX Byte 1 ==
5692 10:52:02.506136 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5693 10:52:02.513124 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5694 10:52:02.513649 ==
5695 10:52:02.516257 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 10:52:02.519662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 10:52:02.520213 ==
5698 10:52:02.520558
5699 10:52:02.520867
5700 10:52:02.523521 TX Vref Scan disable
5701 10:52:02.525830 == TX Byte 0 ==
5702 10:52:02.528847 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5703 10:52:02.532445 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5704 10:52:02.536101 == TX Byte 1 ==
5705 10:52:02.539362 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 10:52:02.542461 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 10:52:02.542973
5708 10:52:02.543309 [DATLAT]
5709 10:52:02.545639 Freq=933, CH1 RK0
5710 10:52:02.546070
5711 10:52:02.549070 DATLAT Default: 0xd
5712 10:52:02.549598 0, 0xFFFF, sum = 0
5713 10:52:02.552213 1, 0xFFFF, sum = 0
5714 10:52:02.552636 2, 0xFFFF, sum = 0
5715 10:52:02.555581 3, 0xFFFF, sum = 0
5716 10:52:02.556151 4, 0xFFFF, sum = 0
5717 10:52:02.558853 5, 0xFFFF, sum = 0
5718 10:52:02.559277 6, 0xFFFF, sum = 0
5719 10:52:02.562168 7, 0xFFFF, sum = 0
5720 10:52:02.562658 8, 0xFFFF, sum = 0
5721 10:52:02.565475 9, 0xFFFF, sum = 0
5722 10:52:02.566148 10, 0x0, sum = 1
5723 10:52:02.569164 11, 0x0, sum = 2
5724 10:52:02.569681 12, 0x0, sum = 3
5725 10:52:02.572175 13, 0x0, sum = 4
5726 10:52:02.572694 best_step = 11
5727 10:52:02.573027
5728 10:52:02.573337 ==
5729 10:52:02.575632 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 10:52:02.578797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 10:52:02.582209 ==
5732 10:52:02.582644 RX Vref Scan: 1
5733 10:52:02.582971
5734 10:52:02.584993 RX Vref 0 -> 0, step: 1
5735 10:52:02.585407
5736 10:52:02.588581 RX Delay -61 -> 252, step: 4
5737 10:52:02.588992
5738 10:52:02.591841 Set Vref, RX VrefLevel [Byte0]: 52
5739 10:52:02.595121 [Byte1]: 50
5740 10:52:02.595633
5741 10:52:02.598426 Final RX Vref Byte 0 = 52 to rank0
5742 10:52:02.601866 Final RX Vref Byte 1 = 50 to rank0
5743 10:52:02.605261 Final RX Vref Byte 0 = 52 to rank1
5744 10:52:02.608255 Final RX Vref Byte 1 = 50 to rank1==
5745 10:52:02.611590 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 10:52:02.614744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 10:52:02.615262 ==
5748 10:52:02.617715 DQS Delay:
5749 10:52:02.618132 DQS0 = 0, DQS1 = 0
5750 10:52:02.621112 DQM Delay:
5751 10:52:02.621625 DQM0 = 96, DQM1 = 95
5752 10:52:02.621961 DQ Delay:
5753 10:52:02.625171 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5754 10:52:02.627651 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =90
5755 10:52:02.631234 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =86
5756 10:52:02.638170 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =104
5757 10:52:02.638690
5758 10:52:02.639026
5759 10:52:02.644284 [DQSOSCAuto] RK0, (LSB)MR18= 0x918, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5760 10:52:02.647381 CH1 RK0: MR19=505, MR18=918
5761 10:52:02.654080 CH1_RK0: MR19=0x505, MR18=0x918, DQSOSC=414, MR23=63, INC=63, DEC=42
5762 10:52:02.654598
5763 10:52:02.657497 ----->DramcWriteLeveling(PI) begin...
5764 10:52:02.658012 ==
5765 10:52:02.661151 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 10:52:02.663496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 10:52:02.663912 ==
5768 10:52:02.666958 Write leveling (Byte 0): 25 => 25
5769 10:52:02.670403 Write leveling (Byte 1): 26 => 26
5770 10:52:02.673934 DramcWriteLeveling(PI) end<-----
5771 10:52:02.674477
5772 10:52:02.674983 ==
5773 10:52:02.677041 Dram Type= 6, Freq= 0, CH_1, rank 1
5774 10:52:02.680453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 10:52:02.680971 ==
5776 10:52:02.683744 [Gating] SW mode calibration
5777 10:52:02.690401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5778 10:52:02.696803 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5779 10:52:02.700419 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 10:52:02.706785 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 10:52:02.710100 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 10:52:02.713770 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 10:52:02.720084 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 10:52:02.723237 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 10:52:02.726205 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (0 0) (0 0)
5786 10:52:02.733183 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5787 10:52:02.736892 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 10:52:02.739923 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 10:52:02.746265 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 10:52:02.749638 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 10:52:02.752906 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 10:52:02.759515 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 10:52:02.763713 0 15 24 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5794 10:52:02.765691 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5795 10:52:02.772732 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 10:52:02.775533 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 10:52:02.779375 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 10:52:02.785327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 10:52:02.788564 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 10:52:02.792097 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 10:52:02.799092 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5802 10:52:02.803010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5803 10:52:02.805001 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 10:52:02.811702 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 10:52:02.815342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 10:52:02.819753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 10:52:02.825228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 10:52:02.828317 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 10:52:02.832139 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 10:52:02.838361 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 10:52:02.841895 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 10:52:02.844947 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 10:52:02.851282 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 10:52:02.854995 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 10:52:02.857533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 10:52:02.864462 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5817 10:52:02.867577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5818 10:52:02.870654 Total UI for P1: 0, mck2ui 16
5819 10:52:02.874055 best dqsien dly found for B0: ( 1, 2, 20)
5820 10:52:02.877561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5821 10:52:02.883884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 10:52:02.884489 Total UI for P1: 0, mck2ui 16
5823 10:52:02.891422 best dqsien dly found for B1: ( 1, 2, 26)
5824 10:52:02.894044 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5825 10:52:02.897237 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5826 10:52:02.897812
5827 10:52:02.900355 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5828 10:52:02.904635 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5829 10:52:02.906949 [Gating] SW calibration Done
5830 10:52:02.907429 ==
5831 10:52:02.910517 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 10:52:02.913820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 10:52:02.914386 ==
5834 10:52:02.917472 RX Vref Scan: 0
5835 10:52:02.917979
5836 10:52:02.918412 RX Vref 0 -> 0, step: 1
5837 10:52:02.920607
5838 10:52:02.921073 RX Delay -80 -> 252, step: 8
5839 10:52:02.927586 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5840 10:52:02.930638 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5841 10:52:02.934450 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5842 10:52:02.937490 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5843 10:52:02.940167 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5844 10:52:02.943679 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5845 10:52:02.950951 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5846 10:52:02.953855 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5847 10:52:02.956797 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5848 10:52:02.959709 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5849 10:52:02.963347 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5850 10:52:02.967184 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5851 10:52:02.973194 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5852 10:52:02.976448 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5853 10:52:02.980088 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5854 10:52:02.983224 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5855 10:52:02.983775 ==
5856 10:52:02.986164 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 10:52:02.993497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 10:52:02.993966 ==
5859 10:52:02.994350 DQS Delay:
5860 10:52:02.994694 DQS0 = 0, DQS1 = 0
5861 10:52:02.996417 DQM Delay:
5862 10:52:02.996879 DQM0 = 95, DQM1 = 91
5863 10:52:02.999791 DQ Delay:
5864 10:52:03.002899 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5865 10:52:03.006221 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5866 10:52:03.009358 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5867 10:52:03.012689 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5868 10:52:03.013110
5869 10:52:03.013441
5870 10:52:03.013750 ==
5871 10:52:03.016008 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 10:52:03.018909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 10:52:03.019329 ==
5874 10:52:03.019659
5875 10:52:03.019964
5876 10:52:03.022266 TX Vref Scan disable
5877 10:52:03.022680 == TX Byte 0 ==
5878 10:52:03.030251 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5879 10:52:03.032543 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5880 10:52:03.035678 == TX Byte 1 ==
5881 10:52:03.039561 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5882 10:52:03.043169 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5883 10:52:03.043729 ==
5884 10:52:03.046050 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 10:52:03.049570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 10:52:03.052244 ==
5887 10:52:03.052795
5888 10:52:03.053167
5889 10:52:03.053508 TX Vref Scan disable
5890 10:52:03.055485 == TX Byte 0 ==
5891 10:52:03.058830 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5892 10:52:03.066057 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5893 10:52:03.066615 == TX Byte 1 ==
5894 10:52:03.068762 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5895 10:52:03.075751 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5896 10:52:03.076359
5897 10:52:03.076727 [DATLAT]
5898 10:52:03.077069 Freq=933, CH1 RK1
5899 10:52:03.077400
5900 10:52:03.079096 DATLAT Default: 0xb
5901 10:52:03.081794 0, 0xFFFF, sum = 0
5902 10:52:03.082263 1, 0xFFFF, sum = 0
5903 10:52:03.084948 2, 0xFFFF, sum = 0
5904 10:52:03.085417 3, 0xFFFF, sum = 0
5905 10:52:03.088457 4, 0xFFFF, sum = 0
5906 10:52:03.088928 5, 0xFFFF, sum = 0
5907 10:52:03.091758 6, 0xFFFF, sum = 0
5908 10:52:03.092273 7, 0xFFFF, sum = 0
5909 10:52:03.095098 8, 0xFFFF, sum = 0
5910 10:52:03.095523 9, 0xFFFF, sum = 0
5911 10:52:03.098479 10, 0x0, sum = 1
5912 10:52:03.099069 11, 0x0, sum = 2
5913 10:52:03.102506 12, 0x0, sum = 3
5914 10:52:03.103108 13, 0x0, sum = 4
5915 10:52:03.104926 best_step = 11
5916 10:52:03.105392
5917 10:52:03.105757 ==
5918 10:52:03.108115 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 10:52:03.111763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 10:52:03.112399 ==
5921 10:52:03.112788 RX Vref Scan: 0
5922 10:52:03.113141
5923 10:52:03.115092 RX Vref 0 -> 0, step: 1
5924 10:52:03.115552
5925 10:52:03.118758 RX Delay -61 -> 252, step: 4
5926 10:52:03.125015 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5927 10:52:03.128608 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5928 10:52:03.131492 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5929 10:52:03.135552 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5930 10:52:03.138389 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5931 10:52:03.141248 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5932 10:52:03.148160 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5933 10:52:03.151419 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5934 10:52:03.155162 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5935 10:52:03.158083 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5936 10:52:03.162066 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5937 10:52:03.167919 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5938 10:52:03.171263 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5939 10:52:03.174575 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5940 10:52:03.177518 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5941 10:52:03.181333 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5942 10:52:03.184239 ==
5943 10:52:03.187752 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 10:52:03.190845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 10:52:03.191327 ==
5946 10:52:03.191707 DQS Delay:
5947 10:52:03.195321 DQS0 = 0, DQS1 = 0
5948 10:52:03.196019 DQM Delay:
5949 10:52:03.197630 DQM0 = 96, DQM1 = 93
5950 10:52:03.198207 DQ Delay:
5951 10:52:03.200519 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =92
5952 10:52:03.203678 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
5953 10:52:03.207253 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =88
5954 10:52:03.210434 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5955 10:52:03.210907
5956 10:52:03.211279
5957 10:52:03.220437 [DQSOSCAuto] RK1, (LSB)MR18= 0x81f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5958 10:52:03.220865 CH1 RK1: MR19=505, MR18=81F
5959 10:52:03.227162 CH1_RK1: MR19=0x505, MR18=0x81F, DQSOSC=412, MR23=63, INC=63, DEC=42
5960 10:52:03.231711 [RxdqsGatingPostProcess] freq 933
5961 10:52:03.237186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5962 10:52:03.240390 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 10:52:03.243738 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 10:52:03.247535 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 10:52:03.250077 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 10:52:03.250631 best DQS0 dly(2T, 0.5T) = (0, 10)
5967 10:52:03.253717 best DQS1 dly(2T, 0.5T) = (0, 10)
5968 10:52:03.256883 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5969 10:52:03.259935 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5970 10:52:03.263453 Pre-setting of DQS Precalculation
5971 10:52:03.269787 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5972 10:52:03.276659 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5973 10:52:03.283019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5974 10:52:03.283586
5975 10:52:03.284005
5976 10:52:03.286648 [Calibration Summary] 1866 Mbps
5977 10:52:03.289696 CH 0, Rank 0
5978 10:52:03.290162 SW Impedance : PASS
5979 10:52:03.293176 DUTY Scan : NO K
5980 10:52:03.293636 ZQ Calibration : PASS
5981 10:52:03.296193 Jitter Meter : NO K
5982 10:52:03.299766 CBT Training : PASS
5983 10:52:03.300365 Write leveling : PASS
5984 10:52:03.303876 RX DQS gating : PASS
5985 10:52:03.306294 RX DQ/DQS(RDDQC) : PASS
5986 10:52:03.306849 TX DQ/DQS : PASS
5987 10:52:03.309055 RX DATLAT : PASS
5988 10:52:03.312370 RX DQ/DQS(Engine): PASS
5989 10:52:03.312825 TX OE : NO K
5990 10:52:03.316216 All Pass.
5991 10:52:03.316690
5992 10:52:03.317079 CH 0, Rank 1
5993 10:52:03.319744 SW Impedance : PASS
5994 10:52:03.320193 DUTY Scan : NO K
5995 10:52:03.322645 ZQ Calibration : PASS
5996 10:52:03.325686 Jitter Meter : NO K
5997 10:52:03.326103 CBT Training : PASS
5998 10:52:03.329084 Write leveling : PASS
5999 10:52:03.332267 RX DQS gating : PASS
6000 10:52:03.332818 RX DQ/DQS(RDDQC) : PASS
6001 10:52:03.336849 TX DQ/DQS : PASS
6002 10:52:03.339584 RX DATLAT : PASS
6003 10:52:03.340170 RX DQ/DQS(Engine): PASS
6004 10:52:03.342378 TX OE : NO K
6005 10:52:03.342837 All Pass.
6006 10:52:03.343204
6007 10:52:03.345352 CH 1, Rank 0
6008 10:52:03.345744 SW Impedance : PASS
6009 10:52:03.348851 DUTY Scan : NO K
6010 10:52:03.352344 ZQ Calibration : PASS
6011 10:52:03.352904 Jitter Meter : NO K
6012 10:52:03.355257 CBT Training : PASS
6013 10:52:03.359019 Write leveling : PASS
6014 10:52:03.359575 RX DQS gating : PASS
6015 10:52:03.362596 RX DQ/DQS(RDDQC) : PASS
6016 10:52:03.366484 TX DQ/DQS : PASS
6017 10:52:03.367042 RX DATLAT : PASS
6018 10:52:03.368876 RX DQ/DQS(Engine): PASS
6019 10:52:03.372237 TX OE : NO K
6020 10:52:03.372799 All Pass.
6021 10:52:03.373167
6022 10:52:03.373510 CH 1, Rank 1
6023 10:52:03.375466 SW Impedance : PASS
6024 10:52:03.378819 DUTY Scan : NO K
6025 10:52:03.379376 ZQ Calibration : PASS
6026 10:52:03.382178 Jitter Meter : NO K
6027 10:52:03.384805 CBT Training : PASS
6028 10:52:03.385362 Write leveling : PASS
6029 10:52:03.387926 RX DQS gating : PASS
6030 10:52:03.391128 RX DQ/DQS(RDDQC) : PASS
6031 10:52:03.391588 TX DQ/DQS : PASS
6032 10:52:03.395000 RX DATLAT : PASS
6033 10:52:03.395597 RX DQ/DQS(Engine): PASS
6034 10:52:03.398835 TX OE : NO K
6035 10:52:03.399396 All Pass.
6036 10:52:03.399983
6037 10:52:03.400946 DramC Write-DBI off
6038 10:52:03.404571 PER_BANK_REFRESH: Hybrid Mode
6039 10:52:03.405127 TX_TRACKING: ON
6040 10:52:03.414607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6041 10:52:03.417387 [FAST_K] Save calibration result to emmc
6042 10:52:03.421087 dramc_set_vcore_voltage set vcore to 650000
6043 10:52:03.424711 Read voltage for 400, 6
6044 10:52:03.425169 Vio18 = 0
6045 10:52:03.427737 Vcore = 650000
6046 10:52:03.428234 Vdram = 0
6047 10:52:03.428603 Vddq = 0
6048 10:52:03.428942 Vmddr = 0
6049 10:52:03.433894 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6050 10:52:03.440716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6051 10:52:03.441272 MEM_TYPE=3, freq_sel=20
6052 10:52:03.444312 sv_algorithm_assistance_LP4_800
6053 10:52:03.447898 ============ PULL DRAM RESETB DOWN ============
6054 10:52:03.454273 ========== PULL DRAM RESETB DOWN end =========
6055 10:52:03.457274 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6056 10:52:03.460419 ===================================
6057 10:52:03.463788 LPDDR4 DRAM CONFIGURATION
6058 10:52:03.467080 ===================================
6059 10:52:03.467635 EX_ROW_EN[0] = 0x0
6060 10:52:03.471015 EX_ROW_EN[1] = 0x0
6061 10:52:03.473783 LP4Y_EN = 0x0
6062 10:52:03.474338 WORK_FSP = 0x0
6063 10:52:03.477163 WL = 0x2
6064 10:52:03.477720 RL = 0x2
6065 10:52:03.480767 BL = 0x2
6066 10:52:03.481321 RPST = 0x0
6067 10:52:03.484398 RD_PRE = 0x0
6068 10:52:03.484955 WR_PRE = 0x1
6069 10:52:03.486784 WR_PST = 0x0
6070 10:52:03.487339 DBI_WR = 0x0
6071 10:52:03.490088 DBI_RD = 0x0
6072 10:52:03.490553 OTF = 0x1
6073 10:52:03.493690 ===================================
6074 10:52:03.497294 ===================================
6075 10:52:03.500002 ANA top config
6076 10:52:03.503274 ===================================
6077 10:52:03.506620 DLL_ASYNC_EN = 0
6078 10:52:03.507189 ALL_SLAVE_EN = 1
6079 10:52:03.509777 NEW_RANK_MODE = 1
6080 10:52:03.513208 DLL_IDLE_MODE = 1
6081 10:52:03.515994 LP45_APHY_COMB_EN = 1
6082 10:52:03.516509 TX_ODT_DIS = 1
6083 10:52:03.519393 NEW_8X_MODE = 1
6084 10:52:03.523269 ===================================
6085 10:52:03.525920 ===================================
6086 10:52:03.529735 data_rate = 800
6087 10:52:03.532582 CKR = 1
6088 10:52:03.535997 DQ_P2S_RATIO = 4
6089 10:52:03.539162 ===================================
6090 10:52:03.542506 CA_P2S_RATIO = 4
6091 10:52:03.546526 DQ_CA_OPEN = 0
6092 10:52:03.546989 DQ_SEMI_OPEN = 1
6093 10:52:03.549666 CA_SEMI_OPEN = 1
6094 10:52:03.552073 CA_FULL_RATE = 0
6095 10:52:03.555668 DQ_CKDIV4_EN = 0
6096 10:52:03.559302 CA_CKDIV4_EN = 1
6097 10:52:03.562721 CA_PREDIV_EN = 0
6098 10:52:03.563309 PH8_DLY = 0
6099 10:52:03.565221 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6100 10:52:03.568998 DQ_AAMCK_DIV = 0
6101 10:52:03.572928 CA_AAMCK_DIV = 0
6102 10:52:03.575593 CA_ADMCK_DIV = 4
6103 10:52:03.578678 DQ_TRACK_CA_EN = 0
6104 10:52:03.579236 CA_PICK = 800
6105 10:52:03.582897 CA_MCKIO = 400
6106 10:52:03.586466 MCKIO_SEMI = 400
6107 10:52:03.588331 PLL_FREQ = 3016
6108 10:52:03.592373 DQ_UI_PI_RATIO = 32
6109 10:52:03.595304 CA_UI_PI_RATIO = 32
6110 10:52:03.598285 ===================================
6111 10:52:03.602415 ===================================
6112 10:52:03.605293 memory_type:LPDDR4
6113 10:52:03.605755 GP_NUM : 10
6114 10:52:03.608351 SRAM_EN : 1
6115 10:52:03.608811 MD32_EN : 0
6116 10:52:03.612018 ===================================
6117 10:52:03.615117 [ANA_INIT] >>>>>>>>>>>>>>
6118 10:52:03.618123 <<<<<< [CONFIGURE PHASE]: ANA_TX
6119 10:52:03.622118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6120 10:52:03.624898 ===================================
6121 10:52:03.628012 data_rate = 800,PCW = 0X7400
6122 10:52:03.631503 ===================================
6123 10:52:03.635841 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6124 10:52:03.641688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 10:52:03.652102 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 10:52:03.654481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6127 10:52:03.661163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6128 10:52:03.664321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6129 10:52:03.664780 [ANA_INIT] flow start
6130 10:52:03.667798 [ANA_INIT] PLL >>>>>>>>
6131 10:52:03.671136 [ANA_INIT] PLL <<<<<<<<
6132 10:52:03.671702 [ANA_INIT] MIDPI >>>>>>>>
6133 10:52:03.674879 [ANA_INIT] MIDPI <<<<<<<<
6134 10:52:03.677514 [ANA_INIT] DLL >>>>>>>>
6135 10:52:03.678070 [ANA_INIT] flow end
6136 10:52:03.684507 ============ LP4 DIFF to SE enter ============
6137 10:52:03.687287 ============ LP4 DIFF to SE exit ============
6138 10:52:03.691068 [ANA_INIT] <<<<<<<<<<<<<
6139 10:52:03.694026 [Flow] Enable top DCM control >>>>>
6140 10:52:03.697444 [Flow] Enable top DCM control <<<<<
6141 10:52:03.697915 Enable DLL master slave shuffle
6142 10:52:03.703705 ==============================================================
6143 10:52:03.707542 Gating Mode config
6144 10:52:03.710076 ==============================================================
6145 10:52:03.714210 Config description:
6146 10:52:03.723797 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6147 10:52:03.730543 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6148 10:52:03.733702 SELPH_MODE 0: By rank 1: By Phase
6149 10:52:03.740651 ==============================================================
6150 10:52:03.743330 GAT_TRACK_EN = 0
6151 10:52:03.746714 RX_GATING_MODE = 2
6152 10:52:03.749728 RX_GATING_TRACK_MODE = 2
6153 10:52:03.753185 SELPH_MODE = 1
6154 10:52:03.756550 PICG_EARLY_EN = 1
6155 10:52:03.757017 VALID_LAT_VALUE = 1
6156 10:52:03.762922 ==============================================================
6157 10:52:03.766915 Enter into Gating configuration >>>>
6158 10:52:03.769568 Exit from Gating configuration <<<<
6159 10:52:03.773217 Enter into DVFS_PRE_config >>>>>
6160 10:52:03.783509 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6161 10:52:03.786750 Exit from DVFS_PRE_config <<<<<
6162 10:52:03.789527 Enter into PICG configuration >>>>
6163 10:52:03.792764 Exit from PICG configuration <<<<
6164 10:52:03.795886 [RX_INPUT] configuration >>>>>
6165 10:52:03.799422 [RX_INPUT] configuration <<<<<
6166 10:52:03.806026 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6167 10:52:03.809239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6168 10:52:03.815654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 10:52:03.822365 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 10:52:03.829079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 10:52:03.835514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 10:52:03.839665 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6173 10:52:03.842290 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6174 10:52:03.845550 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6175 10:52:03.852855 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6176 10:52:03.855339 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6177 10:52:03.858785 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6178 10:52:03.861850 ===================================
6179 10:52:03.864903 LPDDR4 DRAM CONFIGURATION
6180 10:52:03.868558 ===================================
6181 10:52:03.871722 EX_ROW_EN[0] = 0x0
6182 10:52:03.872312 EX_ROW_EN[1] = 0x0
6183 10:52:03.875433 LP4Y_EN = 0x0
6184 10:52:03.875999 WORK_FSP = 0x0
6185 10:52:03.878302 WL = 0x2
6186 10:52:03.878769 RL = 0x2
6187 10:52:03.881694 BL = 0x2
6188 10:52:03.882263 RPST = 0x0
6189 10:52:03.885082 RD_PRE = 0x0
6190 10:52:03.885543 WR_PRE = 0x1
6191 10:52:03.888160 WR_PST = 0x0
6192 10:52:03.888623 DBI_WR = 0x0
6193 10:52:03.891510 DBI_RD = 0x0
6194 10:52:03.892251 OTF = 0x1
6195 10:52:03.894891 ===================================
6196 10:52:03.901429 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6197 10:52:03.904970 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6198 10:52:03.908108 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6199 10:52:03.912646 ===================================
6200 10:52:03.914763 LPDDR4 DRAM CONFIGURATION
6201 10:52:03.918163 ===================================
6202 10:52:03.920980 EX_ROW_EN[0] = 0x10
6203 10:52:03.921443 EX_ROW_EN[1] = 0x0
6204 10:52:03.924686 LP4Y_EN = 0x0
6205 10:52:03.925240 WORK_FSP = 0x0
6206 10:52:03.927743 WL = 0x2
6207 10:52:03.928342 RL = 0x2
6208 10:52:03.930983 BL = 0x2
6209 10:52:03.931550 RPST = 0x0
6210 10:52:03.934460 RD_PRE = 0x0
6211 10:52:03.934921 WR_PRE = 0x1
6212 10:52:03.938872 WR_PST = 0x0
6213 10:52:03.939423 DBI_WR = 0x0
6214 10:52:03.940708 DBI_RD = 0x0
6215 10:52:03.944169 OTF = 0x1
6216 10:52:03.947715 ===================================
6217 10:52:03.950859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6218 10:52:03.956223 nWR fixed to 30
6219 10:52:03.959773 [ModeRegInit_LP4] CH0 RK0
6220 10:52:03.960478 [ModeRegInit_LP4] CH0 RK1
6221 10:52:03.963443 [ModeRegInit_LP4] CH1 RK0
6222 10:52:03.965703 [ModeRegInit_LP4] CH1 RK1
6223 10:52:03.966163 match AC timing 19
6224 10:52:03.972364 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6225 10:52:03.975647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6226 10:52:03.978989 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6227 10:52:03.985541 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6228 10:52:03.988652 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6229 10:52:03.989108 ==
6230 10:52:03.992232 Dram Type= 6, Freq= 0, CH_0, rank 0
6231 10:52:03.995486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 10:52:03.996132 ==
6233 10:52:04.001998 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 10:52:04.008977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6235 10:52:04.012239 [CA 0] Center 36 (8~64) winsize 57
6236 10:52:04.015230 [CA 1] Center 36 (8~64) winsize 57
6237 10:52:04.018831 [CA 2] Center 36 (8~64) winsize 57
6238 10:52:04.021389 [CA 3] Center 36 (8~64) winsize 57
6239 10:52:04.025432 [CA 4] Center 36 (8~64) winsize 57
6240 10:52:04.028694 [CA 5] Center 36 (8~64) winsize 57
6241 10:52:04.029382
6242 10:52:04.031804 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6243 10:52:04.032399
6244 10:52:04.035493 [CATrainingPosCal] consider 1 rank data
6245 10:52:04.038289 u2DelayCellTimex100 = 270/100 ps
6246 10:52:04.042250 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 10:52:04.044707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 10:52:04.048414 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 10:52:04.051542 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:52:04.054874 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 10:52:04.057696 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 10:52:04.058176
6253 10:52:04.064744 CA PerBit enable=1, Macro0, CA PI delay=36
6254 10:52:04.065325
6255 10:52:04.065814 [CBTSetCACLKResult] CA Dly = 36
6256 10:52:04.068380 CS Dly: 1 (0~32)
6257 10:52:04.068958 ==
6258 10:52:04.071206 Dram Type= 6, Freq= 0, CH_0, rank 1
6259 10:52:04.074327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 10:52:04.074885 ==
6261 10:52:04.080914 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 10:52:04.087503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6263 10:52:04.091226 [CA 0] Center 36 (8~64) winsize 57
6264 10:52:04.093933 [CA 1] Center 36 (8~64) winsize 57
6265 10:52:04.098283 [CA 2] Center 36 (8~64) winsize 57
6266 10:52:04.100752 [CA 3] Center 36 (8~64) winsize 57
6267 10:52:04.103725 [CA 4] Center 36 (8~64) winsize 57
6268 10:52:04.104221 [CA 5] Center 36 (8~64) winsize 57
6269 10:52:04.108176
6270 10:52:04.110663 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6271 10:52:04.111235
6272 10:52:04.114659 [CATrainingPosCal] consider 2 rank data
6273 10:52:04.117038 u2DelayCellTimex100 = 270/100 ps
6274 10:52:04.120273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 10:52:04.123780 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 10:52:04.127270 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 10:52:04.130640 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 10:52:04.133419 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 10:52:04.137152 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 10:52:04.137707
6281 10:52:04.140559 CA PerBit enable=1, Macro0, CA PI delay=36
6282 10:52:04.143741
6283 10:52:04.144342 [CBTSetCACLKResult] CA Dly = 36
6284 10:52:04.146779 CS Dly: 1 (0~32)
6285 10:52:04.147337
6286 10:52:04.151013 ----->DramcWriteLeveling(PI) begin...
6287 10:52:04.151636 ==
6288 10:52:04.153215 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 10:52:04.156407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 10:52:04.156900 ==
6291 10:52:04.160625 Write leveling (Byte 0): 40 => 8
6292 10:52:04.163455 Write leveling (Byte 1): 40 => 8
6293 10:52:04.167446 DramcWriteLeveling(PI) end<-----
6294 10:52:04.168001
6295 10:52:04.168412 ==
6296 10:52:04.169946 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 10:52:04.173001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 10:52:04.176585 ==
6299 10:52:04.177139 [Gating] SW mode calibration
6300 10:52:04.186141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6301 10:52:04.189383 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6302 10:52:04.192854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 10:52:04.199905 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 10:52:04.202996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 10:52:04.206206 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 10:52:04.212732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 10:52:04.216079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 10:52:04.218760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 10:52:04.225916 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 10:52:04.229239 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 10:52:04.232104 Total UI for P1: 0, mck2ui 16
6312 10:52:04.235422 best dqsien dly found for B0: ( 0, 14, 24)
6313 10:52:04.238733 Total UI for P1: 0, mck2ui 16
6314 10:52:04.242268 best dqsien dly found for B1: ( 0, 14, 24)
6315 10:52:04.246024 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6316 10:52:04.248930 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6317 10:52:04.249396
6318 10:52:04.251786 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 10:52:04.259457 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 10:52:04.260014 [Gating] SW calibration Done
6321 10:52:04.260424 ==
6322 10:52:04.261996 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 10:52:04.268103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 10:52:04.268573 ==
6325 10:52:04.268948 RX Vref Scan: 0
6326 10:52:04.269300
6327 10:52:04.271676 RX Vref 0 -> 0, step: 1
6328 10:52:04.272273
6329 10:52:04.274904 RX Delay -410 -> 252, step: 16
6330 10:52:04.278490 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6331 10:52:04.281843 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6332 10:52:04.287950 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6333 10:52:04.291047 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6334 10:52:04.294838 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6335 10:52:04.301264 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6336 10:52:04.304919 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6337 10:52:04.307905 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6338 10:52:04.311278 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6339 10:52:04.317995 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6340 10:52:04.320912 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6341 10:52:04.324633 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6342 10:52:04.327749 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6343 10:52:04.334782 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6344 10:52:04.337908 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6345 10:52:04.341192 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6346 10:52:04.341741 ==
6347 10:52:04.344295 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 10:52:04.351096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 10:52:04.351682 ==
6350 10:52:04.352158 DQS Delay:
6351 10:52:04.353767 DQS0 = 35, DQS1 = 51
6352 10:52:04.354276 DQM Delay:
6353 10:52:04.354646 DQM0 = 7, DQM1 = 12
6354 10:52:04.357468 DQ Delay:
6355 10:52:04.360849 DQ0 =0, DQ1 =8, DQ2 =8, DQ3 =0
6356 10:52:04.361394 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6357 10:52:04.363908 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6358 10:52:04.367179 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6359 10:52:04.367723
6360 10:52:04.368132
6361 10:52:04.370466 ==
6362 10:52:04.375120 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 10:52:04.377710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 10:52:04.378331 ==
6365 10:52:04.378697
6366 10:52:04.379035
6367 10:52:04.380665 TX Vref Scan disable
6368 10:52:04.381113 == TX Byte 0 ==
6369 10:52:04.383827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 10:52:04.390174 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 10:52:04.390719 == TX Byte 1 ==
6372 10:52:04.393932 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 10:52:04.400736 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 10:52:04.401186 ==
6375 10:52:04.403383 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 10:52:04.406722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 10:52:04.407173 ==
6378 10:52:04.407530
6379 10:52:04.407856
6380 10:52:04.409870 TX Vref Scan disable
6381 10:52:04.410321 == TX Byte 0 ==
6382 10:52:04.413429 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 10:52:04.420121 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 10:52:04.420694 == TX Byte 1 ==
6385 10:52:04.423581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 10:52:04.429812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 10:52:04.430367
6388 10:52:04.430730 [DATLAT]
6389 10:52:04.431063 Freq=400, CH0 RK0
6390 10:52:04.433502
6391 10:52:04.434048 DATLAT Default: 0xf
6392 10:52:04.437244 0, 0xFFFF, sum = 0
6393 10:52:04.437796 1, 0xFFFF, sum = 0
6394 10:52:04.440160 2, 0xFFFF, sum = 0
6395 10:52:04.440718 3, 0xFFFF, sum = 0
6396 10:52:04.443167 4, 0xFFFF, sum = 0
6397 10:52:04.443724 5, 0xFFFF, sum = 0
6398 10:52:04.446706 6, 0xFFFF, sum = 0
6399 10:52:04.447263 7, 0xFFFF, sum = 0
6400 10:52:04.450004 8, 0xFFFF, sum = 0
6401 10:52:04.450565 9, 0xFFFF, sum = 0
6402 10:52:04.452956 10, 0xFFFF, sum = 0
6403 10:52:04.453517 11, 0xFFFF, sum = 0
6404 10:52:04.457270 12, 0xFFFF, sum = 0
6405 10:52:04.457835 13, 0x0, sum = 1
6406 10:52:04.459861 14, 0x0, sum = 2
6407 10:52:04.460536 15, 0x0, sum = 3
6408 10:52:04.463277 16, 0x0, sum = 4
6409 10:52:04.463877 best_step = 14
6410 10:52:04.464319
6411 10:52:04.464657 ==
6412 10:52:04.465865 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 10:52:04.473261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 10:52:04.473824 ==
6415 10:52:04.474187 RX Vref Scan: 1
6416 10:52:04.474524
6417 10:52:04.476279 RX Vref 0 -> 0, step: 1
6418 10:52:04.476830
6419 10:52:04.479208 RX Delay -343 -> 252, step: 8
6420 10:52:04.479760
6421 10:52:04.482648 Set Vref, RX VrefLevel [Byte0]: 51
6422 10:52:04.486223 [Byte1]: 49
6423 10:52:04.489653
6424 10:52:04.490208 Final RX Vref Byte 0 = 51 to rank0
6425 10:52:04.492647 Final RX Vref Byte 1 = 49 to rank0
6426 10:52:04.495949 Final RX Vref Byte 0 = 51 to rank1
6427 10:52:04.499208 Final RX Vref Byte 1 = 49 to rank1==
6428 10:52:04.502591 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 10:52:04.509479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 10:52:04.510038 ==
6431 10:52:04.510402 DQS Delay:
6432 10:52:04.512601 DQS0 = 44, DQS1 = 60
6433 10:52:04.513183 DQM Delay:
6434 10:52:04.513549 DQM0 = 10, DQM1 = 18
6435 10:52:04.515966 DQ Delay:
6436 10:52:04.519298 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6437 10:52:04.522272 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6438 10:52:04.522755 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6439 10:52:04.528650 DQ12 =28, DQ13 =20, DQ14 =28, DQ15 =28
6440 10:52:04.529221
6441 10:52:04.529584
6442 10:52:04.535769 [DQSOSCAuto] RK0, (LSB)MR18= 0x9083, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6443 10:52:04.538585 CH0 RK0: MR19=C0C, MR18=9083
6444 10:52:04.545517 CH0_RK0: MR19=0xC0C, MR18=0x9083, DQSOSC=391, MR23=63, INC=386, DEC=257
6445 10:52:04.546087 ==
6446 10:52:04.548293 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 10:52:04.552253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 10:52:04.552838 ==
6449 10:52:04.555412 [Gating] SW mode calibration
6450 10:52:04.561854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6451 10:52:04.569365 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6452 10:52:04.571710 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 10:52:04.575150 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 10:52:04.581596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 10:52:04.584672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 10:52:04.588711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 10:52:04.594578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 10:52:04.597856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 10:52:04.601651 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 10:52:04.608400 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 10:52:04.611227 Total UI for P1: 0, mck2ui 16
6462 10:52:04.614357 best dqsien dly found for B0: ( 0, 14, 24)
6463 10:52:04.618037 Total UI for P1: 0, mck2ui 16
6464 10:52:04.620974 best dqsien dly found for B1: ( 0, 14, 24)
6465 10:52:04.624398 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6466 10:52:04.627820 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6467 10:52:04.628474
6468 10:52:04.630609 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 10:52:04.634380 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 10:52:04.637338 [Gating] SW calibration Done
6471 10:52:04.637806 ==
6472 10:52:04.640679 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 10:52:04.644264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 10:52:04.644851 ==
6475 10:52:04.648303 RX Vref Scan: 0
6476 10:52:04.648867
6477 10:52:04.651220 RX Vref 0 -> 0, step: 1
6478 10:52:04.651778
6479 10:52:04.653761 RX Delay -410 -> 252, step: 16
6480 10:52:04.657340 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6481 10:52:04.660546 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6482 10:52:04.663972 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6483 10:52:04.670623 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6484 10:52:04.673706 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6485 10:52:04.677047 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6486 10:52:04.680547 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6487 10:52:04.686696 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6488 10:52:04.690142 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6489 10:52:04.694376 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6490 10:52:04.696600 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6491 10:52:04.703903 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6492 10:52:04.707034 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6493 10:52:04.710012 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6494 10:52:04.716846 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6495 10:52:04.719559 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6496 10:52:04.720155 ==
6497 10:52:04.722848 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 10:52:04.726305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 10:52:04.726863 ==
6500 10:52:04.729425 DQS Delay:
6501 10:52:04.729881 DQS0 = 35, DQS1 = 59
6502 10:52:04.733422 DQM Delay:
6503 10:52:04.733978 DQM0 = 8, DQM1 = 17
6504 10:52:04.734345 DQ Delay:
6505 10:52:04.736215 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6506 10:52:04.739394 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6507 10:52:04.743310 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6508 10:52:04.745864 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6509 10:52:04.746324
6510 10:52:04.746687
6511 10:52:04.747023 ==
6512 10:52:04.749743 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 10:52:04.752446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 10:52:04.756164 ==
6515 10:52:04.756712
6516 10:52:04.757080
6517 10:52:04.757415 TX Vref Scan disable
6518 10:52:04.759665 == TX Byte 0 ==
6519 10:52:04.762902 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6520 10:52:04.765757 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6521 10:52:04.769301 == TX Byte 1 ==
6522 10:52:04.772387 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 10:52:04.776125 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 10:52:04.776584 ==
6525 10:52:04.779476 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 10:52:04.786103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 10:52:04.786618 ==
6528 10:52:04.787019
6529 10:52:04.787335
6530 10:52:04.787630 TX Vref Scan disable
6531 10:52:04.789003 == TX Byte 0 ==
6532 10:52:04.792318 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6533 10:52:04.796104 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6534 10:52:04.799335 == TX Byte 1 ==
6535 10:52:04.802369 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 10:52:04.805641 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 10:52:04.806205
6538 10:52:04.808843 [DATLAT]
6539 10:52:04.809302 Freq=400, CH0 RK1
6540 10:52:04.809672
6541 10:52:04.812406 DATLAT Default: 0xe
6542 10:52:04.812869 0, 0xFFFF, sum = 0
6543 10:52:04.815650 1, 0xFFFF, sum = 0
6544 10:52:04.816259 2, 0xFFFF, sum = 0
6545 10:52:04.818968 3, 0xFFFF, sum = 0
6546 10:52:04.819543 4, 0xFFFF, sum = 0
6547 10:52:04.821962 5, 0xFFFF, sum = 0
6548 10:52:04.822453 6, 0xFFFF, sum = 0
6549 10:52:04.824836 7, 0xFFFF, sum = 0
6550 10:52:04.825322 8, 0xFFFF, sum = 0
6551 10:52:04.828348 9, 0xFFFF, sum = 0
6552 10:52:04.831678 10, 0xFFFF, sum = 0
6553 10:52:04.832264 11, 0xFFFF, sum = 0
6554 10:52:04.834942 12, 0xFFFF, sum = 0
6555 10:52:04.835499 13, 0x0, sum = 1
6556 10:52:04.838297 14, 0x0, sum = 2
6557 10:52:04.838793 15, 0x0, sum = 3
6558 10:52:04.841675 16, 0x0, sum = 4
6559 10:52:04.842257 best_step = 14
6560 10:52:04.842629
6561 10:52:04.842969 ==
6562 10:52:04.844813 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 10:52:04.848118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 10:52:04.848583 ==
6565 10:52:04.851900 RX Vref Scan: 0
6566 10:52:04.852396
6567 10:52:04.854503 RX Vref 0 -> 0, step: 1
6568 10:52:04.854985
6569 10:52:04.855320 RX Delay -359 -> 252, step: 8
6570 10:52:04.864610 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6571 10:52:04.867010 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6572 10:52:04.870023 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6573 10:52:04.877347 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6574 10:52:04.880430 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6575 10:52:04.883395 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6576 10:52:04.887964 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6577 10:52:04.893623 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6578 10:52:04.896690 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6579 10:52:04.899604 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6580 10:52:04.903443 iDelay=209, Bit 10, Center -40 (-279 ~ 200) 480
6581 10:52:04.909854 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6582 10:52:04.912794 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6583 10:52:04.916416 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6584 10:52:04.923593 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6585 10:52:04.926353 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6586 10:52:04.926914 ==
6587 10:52:04.929375 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 10:52:04.932735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 10:52:04.933299 ==
6590 10:52:04.935779 DQS Delay:
6591 10:52:04.936271 DQS0 = 44, DQS1 = 60
6592 10:52:04.936662 DQM Delay:
6593 10:52:04.939041 DQM0 = 9, DQM1 = 14
6594 10:52:04.939597 DQ Delay:
6595 10:52:04.942285 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6596 10:52:04.945414 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6597 10:52:04.948984 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6598 10:52:04.952363 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6599 10:52:04.953045
6600 10:52:04.953537
6601 10:52:04.962081 [DQSOSCAuto] RK1, (LSB)MR18= 0x867e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6602 10:52:04.962643 CH0 RK1: MR19=C0C, MR18=867E
6603 10:52:04.969516 CH0_RK1: MR19=0xC0C, MR18=0x867E, DQSOSC=393, MR23=63, INC=382, DEC=254
6604 10:52:04.971759 [RxdqsGatingPostProcess] freq 400
6605 10:52:04.978250 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6606 10:52:04.981754 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 10:52:04.985748 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 10:52:04.987914 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 10:52:04.991512 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 10:52:04.995071 best DQS0 dly(2T, 0.5T) = (0, 10)
6611 10:52:04.997836 best DQS1 dly(2T, 0.5T) = (0, 10)
6612 10:52:05.001284 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6613 10:52:05.004564 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6614 10:52:05.008558 Pre-setting of DQS Precalculation
6615 10:52:05.011908 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6616 10:52:05.012518 ==
6617 10:52:05.014842 Dram Type= 6, Freq= 0, CH_1, rank 0
6618 10:52:05.017977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 10:52:05.018542 ==
6620 10:52:05.024712 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 10:52:05.031725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 10:52:05.034550 [CA 0] Center 36 (8~64) winsize 57
6623 10:52:05.037344 [CA 1] Center 36 (8~64) winsize 57
6624 10:52:05.040969 [CA 2] Center 36 (8~64) winsize 57
6625 10:52:05.045254 [CA 3] Center 36 (8~64) winsize 57
6626 10:52:05.047264 [CA 4] Center 36 (8~64) winsize 57
6627 10:52:05.051493 [CA 5] Center 36 (8~64) winsize 57
6628 10:52:05.052091
6629 10:52:05.054205 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 10:52:05.054672
6631 10:52:05.057076 [CATrainingPosCal] consider 1 rank data
6632 10:52:05.060618 u2DelayCellTimex100 = 270/100 ps
6633 10:52:05.063621 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 10:52:05.067453 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 10:52:05.070588 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 10:52:05.074608 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:52:05.077284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 10:52:05.080294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 10:52:05.080859
6640 10:52:05.087102 CA PerBit enable=1, Macro0, CA PI delay=36
6641 10:52:05.087721
6642 10:52:05.090094 [CBTSetCACLKResult] CA Dly = 36
6643 10:52:05.090560 CS Dly: 1 (0~32)
6644 10:52:05.090930 ==
6645 10:52:05.093627 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 10:52:05.096792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 10:52:05.097376 ==
6648 10:52:05.103576 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 10:52:05.109526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6650 10:52:05.113138 [CA 0] Center 36 (8~64) winsize 57
6651 10:52:05.116426 [CA 1] Center 36 (8~64) winsize 57
6652 10:52:05.120093 [CA 2] Center 36 (8~64) winsize 57
6653 10:52:05.122810 [CA 3] Center 36 (8~64) winsize 57
6654 10:52:05.126806 [CA 4] Center 36 (8~64) winsize 57
6655 10:52:05.129591 [CA 5] Center 36 (8~64) winsize 57
6656 10:52:05.130176
6657 10:52:05.133150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6658 10:52:05.133723
6659 10:52:05.136205 [CATrainingPosCal] consider 2 rank data
6660 10:52:05.139663 u2DelayCellTimex100 = 270/100 ps
6661 10:52:05.142709 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 10:52:05.145891 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 10:52:05.149101 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 10:52:05.153085 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 10:52:05.155475 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 10:52:05.158862 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 10:52:05.159334
6668 10:52:05.166063 CA PerBit enable=1, Macro0, CA PI delay=36
6669 10:52:05.166575
6670 10:52:05.168930 [CBTSetCACLKResult] CA Dly = 36
6671 10:52:05.169417 CS Dly: 1 (0~32)
6672 10:52:05.169772
6673 10:52:05.172221 ----->DramcWriteLeveling(PI) begin...
6674 10:52:05.172752 ==
6675 10:52:05.175488 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 10:52:05.179188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 10:52:05.181903 ==
6678 10:52:05.182447 Write leveling (Byte 0): 40 => 8
6679 10:52:05.185386 Write leveling (Byte 1): 40 => 8
6680 10:52:05.188132 DramcWriteLeveling(PI) end<-----
6681 10:52:05.188556
6682 10:52:05.188895 ==
6683 10:52:05.191703 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 10:52:05.198347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 10:52:05.199128 ==
6686 10:52:05.202510 [Gating] SW mode calibration
6687 10:52:05.208404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6688 10:52:05.211820 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6689 10:52:05.218343 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 10:52:05.222166 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 10:52:05.224552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 10:52:05.231280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 10:52:05.234530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 10:52:05.238506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 10:52:05.244951 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 10:52:05.247606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 10:52:05.251405 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 10:52:05.254334 Total UI for P1: 0, mck2ui 16
6699 10:52:05.257904 best dqsien dly found for B0: ( 0, 14, 24)
6700 10:52:05.261207 Total UI for P1: 0, mck2ui 16
6701 10:52:05.264174 best dqsien dly found for B1: ( 0, 14, 24)
6702 10:52:05.267531 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6703 10:52:05.270572 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6704 10:52:05.271039
6705 10:52:05.277379 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 10:52:05.280465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 10:52:05.284636 [Gating] SW calibration Done
6708 10:52:05.285165 ==
6709 10:52:05.286879 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 10:52:05.290114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 10:52:05.290505 ==
6712 10:52:05.290833 RX Vref Scan: 0
6713 10:52:05.291141
6714 10:52:05.294051 RX Vref 0 -> 0, step: 1
6715 10:52:05.294704
6716 10:52:05.297129 RX Delay -410 -> 252, step: 16
6717 10:52:05.300078 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6718 10:52:05.306809 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6719 10:52:05.310123 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6720 10:52:05.313276 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6721 10:52:05.317992 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6722 10:52:05.323076 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6723 10:52:05.326769 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6724 10:52:05.330075 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6725 10:52:05.333902 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6726 10:52:05.339868 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6727 10:52:05.343085 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6728 10:52:05.346342 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6729 10:52:05.353001 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6730 10:52:05.356264 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6731 10:52:05.359623 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6732 10:52:05.362983 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6733 10:52:05.363543 ==
6734 10:52:05.365798 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 10:52:05.372663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 10:52:05.373253 ==
6737 10:52:05.373741 DQS Delay:
6738 10:52:05.375860 DQS0 = 43, DQS1 = 51
6739 10:52:05.376359 DQM Delay:
6740 10:52:05.379052 DQM0 = 13, DQM1 = 13
6741 10:52:05.379535 DQ Delay:
6742 10:52:05.382248 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6743 10:52:05.385649 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6744 10:52:05.388948 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6745 10:52:05.392876 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6746 10:52:05.393405
6747 10:52:05.393848
6748 10:52:05.394282 ==
6749 10:52:05.395450 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 10:52:05.398561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 10:52:05.399094 ==
6752 10:52:05.399669
6753 10:52:05.400137
6754 10:52:05.401880 TX Vref Scan disable
6755 10:52:05.402298 == TX Byte 0 ==
6756 10:52:05.409007 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 10:52:05.412283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 10:52:05.412707 == TX Byte 1 ==
6759 10:52:05.419370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 10:52:05.421715 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 10:52:05.422138 ==
6762 10:52:05.424816 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 10:52:05.428281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 10:52:05.428703 ==
6765 10:52:05.429033
6766 10:52:05.429344
6767 10:52:05.431895 TX Vref Scan disable
6768 10:52:05.435456 == TX Byte 0 ==
6769 10:52:05.438430 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 10:52:05.441913 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 10:52:05.442430 == TX Byte 1 ==
6772 10:52:05.448000 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 10:52:05.452550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 10:52:05.453072
6775 10:52:05.453403 [DATLAT]
6776 10:52:05.455103 Freq=400, CH1 RK0
6777 10:52:05.455520
6778 10:52:05.455895 DATLAT Default: 0xf
6779 10:52:05.458307 0, 0xFFFF, sum = 0
6780 10:52:05.458834 1, 0xFFFF, sum = 0
6781 10:52:05.461883 2, 0xFFFF, sum = 0
6782 10:52:05.465045 3, 0xFFFF, sum = 0
6783 10:52:05.465568 4, 0xFFFF, sum = 0
6784 10:52:05.468084 5, 0xFFFF, sum = 0
6785 10:52:05.468639 6, 0xFFFF, sum = 0
6786 10:52:05.471453 7, 0xFFFF, sum = 0
6787 10:52:05.472007 8, 0xFFFF, sum = 0
6788 10:52:05.474445 9, 0xFFFF, sum = 0
6789 10:52:05.474963 10, 0xFFFF, sum = 0
6790 10:52:05.478494 11, 0xFFFF, sum = 0
6791 10:52:05.479014 12, 0xFFFF, sum = 0
6792 10:52:05.482350 13, 0x0, sum = 1
6793 10:52:05.482875 14, 0x0, sum = 2
6794 10:52:05.484199 15, 0x0, sum = 3
6795 10:52:05.484623 16, 0x0, sum = 4
6796 10:52:05.487965 best_step = 14
6797 10:52:05.488400
6798 10:52:05.488731 ==
6799 10:52:05.490994 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 10:52:05.494364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 10:52:05.494882 ==
6802 10:52:05.497470 RX Vref Scan: 1
6803 10:52:05.497992
6804 10:52:05.498329 RX Vref 0 -> 0, step: 1
6805 10:52:05.498638
6806 10:52:05.500745 RX Delay -343 -> 252, step: 8
6807 10:52:05.501173
6808 10:52:05.504067 Set Vref, RX VrefLevel [Byte0]: 52
6809 10:52:05.506911 [Byte1]: 50
6810 10:52:05.512685
6811 10:52:05.513213 Final RX Vref Byte 0 = 52 to rank0
6812 10:52:05.515218 Final RX Vref Byte 1 = 50 to rank0
6813 10:52:05.518488 Final RX Vref Byte 0 = 52 to rank1
6814 10:52:05.522299 Final RX Vref Byte 1 = 50 to rank1==
6815 10:52:05.525280 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 10:52:05.532263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 10:52:05.532793 ==
6818 10:52:05.533139 DQS Delay:
6819 10:52:05.535548 DQS0 = 44, DQS1 = 56
6820 10:52:05.536125 DQM Delay:
6821 10:52:05.536481 DQM0 = 11, DQM1 = 14
6822 10:52:05.538387 DQ Delay:
6823 10:52:05.541622 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6824 10:52:05.545167 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6825 10:52:05.545738 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6826 10:52:05.548406 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6827 10:52:05.551570
6828 10:52:05.552167
6829 10:52:05.558393 [DQSOSCAuto] RK0, (LSB)MR18= 0x688f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6830 10:52:05.561353 CH1 RK0: MR19=C0C, MR18=688F
6831 10:52:05.568819 CH1_RK0: MR19=0xC0C, MR18=0x688F, DQSOSC=391, MR23=63, INC=386, DEC=257
6832 10:52:05.569397 ==
6833 10:52:05.571550 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 10:52:05.575226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 10:52:05.575802 ==
6836 10:52:05.578435 [Gating] SW mode calibration
6837 10:52:05.584888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6838 10:52:05.591353 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6839 10:52:05.594479 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 10:52:05.597696 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 10:52:05.604137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 10:52:05.607559 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 10:52:05.611001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 10:52:05.617277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 10:52:05.620663 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 10:52:05.624266 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 10:52:05.631057 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 10:52:05.631590 Total UI for P1: 0, mck2ui 16
6849 10:52:05.637294 best dqsien dly found for B0: ( 0, 14, 24)
6850 10:52:05.637806 Total UI for P1: 0, mck2ui 16
6851 10:52:05.644072 best dqsien dly found for B1: ( 0, 14, 24)
6852 10:52:05.647409 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6853 10:52:05.650453 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6854 10:52:05.651008
6855 10:52:05.653760 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 10:52:05.657817 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 10:52:05.660578 [Gating] SW calibration Done
6858 10:52:05.661135 ==
6859 10:52:05.663582 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 10:52:05.666832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 10:52:05.667307 ==
6862 10:52:05.670071 RX Vref Scan: 0
6863 10:52:05.670526
6864 10:52:05.673267 RX Vref 0 -> 0, step: 1
6865 10:52:05.673807
6866 10:52:05.674181 RX Delay -410 -> 252, step: 16
6867 10:52:05.680339 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6868 10:52:05.683835 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6869 10:52:05.687230 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6870 10:52:05.693710 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6871 10:52:05.696985 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6872 10:52:05.700091 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6873 10:52:05.703308 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6874 10:52:05.709366 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6875 10:52:05.713144 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6876 10:52:05.717458 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6877 10:52:05.719935 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6878 10:52:05.726196 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6879 10:52:05.729281 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6880 10:52:05.732986 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6881 10:52:05.735943 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6882 10:52:05.743326 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6883 10:52:05.743912 ==
6884 10:52:05.745784 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 10:52:05.748893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 10:52:05.749367 ==
6887 10:52:05.752687 DQS Delay:
6888 10:52:05.753255 DQS0 = 43, DQS1 = 51
6889 10:52:05.753631 DQM Delay:
6890 10:52:05.756372 DQM0 = 11, DQM1 = 13
6891 10:52:05.756837 DQ Delay:
6892 10:52:05.759116 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6893 10:52:05.762509 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6894 10:52:05.765647 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6895 10:52:05.768924 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6896 10:52:05.769503
6897 10:52:05.769874
6898 10:52:05.770221 ==
6899 10:52:05.772352 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 10:52:05.775654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 10:52:05.778685 ==
6902 10:52:05.779252
6903 10:52:05.779621
6904 10:52:05.779962 TX Vref Scan disable
6905 10:52:05.782338 == TX Byte 0 ==
6906 10:52:05.785148 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6907 10:52:05.788688 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6908 10:52:05.792166 == TX Byte 1 ==
6909 10:52:05.795113 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 10:52:05.798440 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 10:52:05.799008 ==
6912 10:52:05.802091 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 10:52:05.807945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 10:52:05.808532 ==
6915 10:52:05.808909
6916 10:52:05.809257
6917 10:52:05.809589 TX Vref Scan disable
6918 10:52:05.812084 == TX Byte 0 ==
6919 10:52:05.814489 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6920 10:52:05.818392 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6921 10:52:05.821676 == TX Byte 1 ==
6922 10:52:05.824916 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 10:52:05.828357 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 10:52:05.828783
6925 10:52:05.831115 [DATLAT]
6926 10:52:05.831540 Freq=400, CH1 RK1
6927 10:52:05.831879
6928 10:52:05.834642 DATLAT Default: 0xe
6929 10:52:05.835062 0, 0xFFFF, sum = 0
6930 10:52:05.837783 1, 0xFFFF, sum = 0
6931 10:52:05.838217 2, 0xFFFF, sum = 0
6932 10:52:05.841284 3, 0xFFFF, sum = 0
6933 10:52:05.841832 4, 0xFFFF, sum = 0
6934 10:52:05.844749 5, 0xFFFF, sum = 0
6935 10:52:05.845178 6, 0xFFFF, sum = 0
6936 10:52:05.848403 7, 0xFFFF, sum = 0
6937 10:52:05.850992 8, 0xFFFF, sum = 0
6938 10:52:05.851525 9, 0xFFFF, sum = 0
6939 10:52:05.854290 10, 0xFFFF, sum = 0
6940 10:52:05.854721 11, 0xFFFF, sum = 0
6941 10:52:05.857492 12, 0xFFFF, sum = 0
6942 10:52:05.858030 13, 0x0, sum = 1
6943 10:52:05.862341 14, 0x0, sum = 2
6944 10:52:05.862873 15, 0x0, sum = 3
6945 10:52:05.863859 16, 0x0, sum = 4
6946 10:52:05.864326 best_step = 14
6947 10:52:05.864664
6948 10:52:05.864975 ==
6949 10:52:05.868139 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 10:52:05.870603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 10:52:05.874204 ==
6952 10:52:05.874739 RX Vref Scan: 0
6953 10:52:05.875082
6954 10:52:05.877180 RX Vref 0 -> 0, step: 1
6955 10:52:05.877605
6956 10:52:05.880665 RX Delay -343 -> 252, step: 8
6957 10:52:05.887348 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6958 10:52:05.890282 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6959 10:52:05.893410 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6960 10:52:05.896990 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6961 10:52:05.903813 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6962 10:52:05.906489 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6963 10:52:05.909745 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6964 10:52:05.913304 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6965 10:52:05.919747 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6966 10:52:05.923436 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6967 10:52:05.925896 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6968 10:52:05.930460 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6969 10:52:05.936346 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6970 10:52:05.939201 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6971 10:52:05.942454 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6972 10:52:05.949531 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6973 10:52:05.950129 ==
6974 10:52:05.953215 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 10:52:05.955918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 10:52:05.956619 ==
6977 10:52:05.957068 DQS Delay:
6978 10:52:05.959373 DQS0 = 48, DQS1 = 56
6979 10:52:05.959929 DQM Delay:
6980 10:52:05.963074 DQM0 = 12, DQM1 = 14
6981 10:52:05.963606 DQ Delay:
6982 10:52:05.966535 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6983 10:52:05.968658 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6984 10:52:05.972418 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6985 10:52:05.976254 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6986 10:52:05.976808
6987 10:52:05.977174
6988 10:52:05.981937 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ba2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6989 10:52:05.985498 CH1 RK1: MR19=C0C, MR18=6BA2
6990 10:52:05.992495 CH1_RK1: MR19=0xC0C, MR18=0x6BA2, DQSOSC=389, MR23=63, INC=390, DEC=260
6991 10:52:05.995484 [RxdqsGatingPostProcess] freq 400
6992 10:52:06.002452 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6993 10:52:06.006374 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 10:52:06.008137 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 10:52:06.011774 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 10:52:06.014901 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 10:52:06.018121 best DQS0 dly(2T, 0.5T) = (0, 10)
6998 10:52:06.018680 best DQS1 dly(2T, 0.5T) = (0, 10)
6999 10:52:06.021638 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7000 10:52:06.024756 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7001 10:52:06.028661 Pre-setting of DQS Precalculation
7002 10:52:06.034285 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7003 10:52:06.041250 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7004 10:52:06.048082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7005 10:52:06.048718
7006 10:52:06.049098
7007 10:52:06.051315 [Calibration Summary] 800 Mbps
7008 10:52:06.054013 CH 0, Rank 0
7009 10:52:06.054478 SW Impedance : PASS
7010 10:52:06.057396 DUTY Scan : NO K
7011 10:52:06.061137 ZQ Calibration : PASS
7012 10:52:06.061557 Jitter Meter : NO K
7013 10:52:06.064193 CBT Training : PASS
7014 10:52:06.064713 Write leveling : PASS
7015 10:52:06.067551 RX DQS gating : PASS
7016 10:52:06.071027 RX DQ/DQS(RDDQC) : PASS
7017 10:52:06.071541 TX DQ/DQS : PASS
7018 10:52:06.074220 RX DATLAT : PASS
7019 10:52:06.077361 RX DQ/DQS(Engine): PASS
7020 10:52:06.077825 TX OE : NO K
7021 10:52:06.080631 All Pass.
7022 10:52:06.081176
7023 10:52:06.081545 CH 0, Rank 1
7024 10:52:06.084209 SW Impedance : PASS
7025 10:52:06.084626 DUTY Scan : NO K
7026 10:52:06.088168 ZQ Calibration : PASS
7027 10:52:06.090193 Jitter Meter : NO K
7028 10:52:06.090617 CBT Training : PASS
7029 10:52:06.093656 Write leveling : NO K
7030 10:52:06.097590 RX DQS gating : PASS
7031 10:52:06.098108 RX DQ/DQS(RDDQC) : PASS
7032 10:52:06.100261 TX DQ/DQS : PASS
7033 10:52:06.103724 RX DATLAT : PASS
7034 10:52:06.104183 RX DQ/DQS(Engine): PASS
7035 10:52:06.106945 TX OE : NO K
7036 10:52:06.107507 All Pass.
7037 10:52:06.108027
7038 10:52:06.110430 CH 1, Rank 0
7039 10:52:06.110960 SW Impedance : PASS
7040 10:52:06.114087 DUTY Scan : NO K
7041 10:52:06.116554 ZQ Calibration : PASS
7042 10:52:06.116975 Jitter Meter : NO K
7043 10:52:06.120010 CBT Training : PASS
7044 10:52:06.123908 Write leveling : PASS
7045 10:52:06.124660 RX DQS gating : PASS
7046 10:52:06.126844 RX DQ/DQS(RDDQC) : PASS
7047 10:52:06.130032 TX DQ/DQS : PASS
7048 10:52:06.130550 RX DATLAT : PASS
7049 10:52:06.133388 RX DQ/DQS(Engine): PASS
7050 10:52:06.136943 TX OE : NO K
7051 10:52:06.137519 All Pass.
7052 10:52:06.137860
7053 10:52:06.138211 CH 1, Rank 1
7054 10:52:06.140541 SW Impedance : PASS
7055 10:52:06.143491 DUTY Scan : NO K
7056 10:52:06.144077 ZQ Calibration : PASS
7057 10:52:06.146971 Jitter Meter : NO K
7058 10:52:06.149970 CBT Training : PASS
7059 10:52:06.150429 Write leveling : NO K
7060 10:52:06.153019 RX DQS gating : PASS
7061 10:52:06.153543 RX DQ/DQS(RDDQC) : PASS
7062 10:52:06.156196 TX DQ/DQS : PASS
7063 10:52:06.159969 RX DATLAT : PASS
7064 10:52:06.160455 RX DQ/DQS(Engine): PASS
7065 10:52:06.162995 TX OE : NO K
7066 10:52:06.163413 All Pass.
7067 10:52:06.163744
7068 10:52:06.166061 DramC Write-DBI off
7069 10:52:06.169573 PER_BANK_REFRESH: Hybrid Mode
7070 10:52:06.169990 TX_TRACKING: ON
7071 10:52:06.180507 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7072 10:52:06.183369 [FAST_K] Save calibration result to emmc
7073 10:52:06.186120 dramc_set_vcore_voltage set vcore to 725000
7074 10:52:06.189288 Read voltage for 1600, 0
7075 10:52:06.189856 Vio18 = 0
7076 10:52:06.192609 Vcore = 725000
7077 10:52:06.193165 Vdram = 0
7078 10:52:06.193534 Vddq = 0
7079 10:52:06.193872 Vmddr = 0
7080 10:52:06.199600 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7081 10:52:06.206036 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7082 10:52:06.206538 MEM_TYPE=3, freq_sel=13
7083 10:52:06.209351 sv_algorithm_assistance_LP4_3733
7084 10:52:06.212232 ============ PULL DRAM RESETB DOWN ============
7085 10:52:06.218941 ========== PULL DRAM RESETB DOWN end =========
7086 10:52:06.222189 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7087 10:52:06.225746 ===================================
7088 10:52:06.228682 LPDDR4 DRAM CONFIGURATION
7089 10:52:06.232171 ===================================
7090 10:52:06.232731 EX_ROW_EN[0] = 0x0
7091 10:52:06.235509 EX_ROW_EN[1] = 0x0
7092 10:52:06.238894 LP4Y_EN = 0x0
7093 10:52:06.239456 WORK_FSP = 0x1
7094 10:52:06.242636 WL = 0x5
7095 10:52:06.243195 RL = 0x5
7096 10:52:06.245071 BL = 0x2
7097 10:52:06.245534 RPST = 0x0
7098 10:52:06.248887 RD_PRE = 0x0
7099 10:52:06.249469 WR_PRE = 0x1
7100 10:52:06.251861 WR_PST = 0x1
7101 10:52:06.252465 DBI_WR = 0x0
7102 10:52:06.255049 DBI_RD = 0x0
7103 10:52:06.255507 OTF = 0x1
7104 10:52:06.258221 ===================================
7105 10:52:06.262120 ===================================
7106 10:52:06.265108 ANA top config
7107 10:52:06.268302 ===================================
7108 10:52:06.268772 DLL_ASYNC_EN = 0
7109 10:52:06.271557 ALL_SLAVE_EN = 0
7110 10:52:06.275636 NEW_RANK_MODE = 1
7111 10:52:06.277992 DLL_IDLE_MODE = 1
7112 10:52:06.282169 LP45_APHY_COMB_EN = 1
7113 10:52:06.282709 TX_ODT_DIS = 0
7114 10:52:06.284872 NEW_8X_MODE = 1
7115 10:52:06.288003 ===================================
7116 10:52:06.291457 ===================================
7117 10:52:06.294740 data_rate = 3200
7118 10:52:06.297750 CKR = 1
7119 10:52:06.301661 DQ_P2S_RATIO = 8
7120 10:52:06.304331 ===================================
7121 10:52:06.308393 CA_P2S_RATIO = 8
7122 10:52:06.308967 DQ_CA_OPEN = 0
7123 10:52:06.311383 DQ_SEMI_OPEN = 0
7124 10:52:06.314583 CA_SEMI_OPEN = 0
7125 10:52:06.318017 CA_FULL_RATE = 0
7126 10:52:06.320971 DQ_CKDIV4_EN = 0
7127 10:52:06.324569 CA_CKDIV4_EN = 0
7128 10:52:06.325221 CA_PREDIV_EN = 0
7129 10:52:06.327852 PH8_DLY = 12
7130 10:52:06.330792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7131 10:52:06.333865 DQ_AAMCK_DIV = 4
7132 10:52:06.337718 CA_AAMCK_DIV = 4
7133 10:52:06.341399 CA_ADMCK_DIV = 4
7134 10:52:06.343880 DQ_TRACK_CA_EN = 0
7135 10:52:06.344415 CA_PICK = 1600
7136 10:52:06.347568 CA_MCKIO = 1600
7137 10:52:06.350315 MCKIO_SEMI = 0
7138 10:52:06.353828 PLL_FREQ = 3068
7139 10:52:06.357135 DQ_UI_PI_RATIO = 32
7140 10:52:06.360689 CA_UI_PI_RATIO = 0
7141 10:52:06.363644 ===================================
7142 10:52:06.366704 ===================================
7143 10:52:06.370212 memory_type:LPDDR4
7144 10:52:06.370637 GP_NUM : 10
7145 10:52:06.374252 SRAM_EN : 1
7146 10:52:06.374781 MD32_EN : 0
7147 10:52:06.376711 ===================================
7148 10:52:06.380585 [ANA_INIT] >>>>>>>>>>>>>>
7149 10:52:06.383948 <<<<<< [CONFIGURE PHASE]: ANA_TX
7150 10:52:06.386666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7151 10:52:06.389853 ===================================
7152 10:52:06.393242 data_rate = 3200,PCW = 0X7600
7153 10:52:06.396952 ===================================
7154 10:52:06.400146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7155 10:52:06.406777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 10:52:06.409877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 10:52:06.416561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7158 10:52:06.419438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7159 10:52:06.422786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7160 10:52:06.423318 [ANA_INIT] flow start
7161 10:52:06.425638 [ANA_INIT] PLL >>>>>>>>
7162 10:52:06.429207 [ANA_INIT] PLL <<<<<<<<
7163 10:52:06.432808 [ANA_INIT] MIDPI >>>>>>>>
7164 10:52:06.433335 [ANA_INIT] MIDPI <<<<<<<<
7165 10:52:06.436020 [ANA_INIT] DLL >>>>>>>>
7166 10:52:06.439244 [ANA_INIT] DLL <<<<<<<<
7167 10:52:06.439767 [ANA_INIT] flow end
7168 10:52:06.443017 ============ LP4 DIFF to SE enter ============
7169 10:52:06.449196 ============ LP4 DIFF to SE exit ============
7170 10:52:06.449763 [ANA_INIT] <<<<<<<<<<<<<
7171 10:52:06.452675 [Flow] Enable top DCM control >>>>>
7172 10:52:06.455954 [Flow] Enable top DCM control <<<<<
7173 10:52:06.459192 Enable DLL master slave shuffle
7174 10:52:06.465554 ==============================================================
7175 10:52:06.469262 Gating Mode config
7176 10:52:06.471741 ==============================================================
7177 10:52:06.475387 Config description:
7178 10:52:06.485859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7179 10:52:06.491571 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7180 10:52:06.495229 SELPH_MODE 0: By rank 1: By Phase
7181 10:52:06.502470 ==============================================================
7182 10:52:06.504930 GAT_TRACK_EN = 1
7183 10:52:06.508189 RX_GATING_MODE = 2
7184 10:52:06.511751 RX_GATING_TRACK_MODE = 2
7185 10:52:06.512376 SELPH_MODE = 1
7186 10:52:06.515172 PICG_EARLY_EN = 1
7187 10:52:06.518460 VALID_LAT_VALUE = 1
7188 10:52:06.524860 ==============================================================
7189 10:52:06.528669 Enter into Gating configuration >>>>
7190 10:52:06.531376 Exit from Gating configuration <<<<
7191 10:52:06.534337 Enter into DVFS_PRE_config >>>>>
7192 10:52:06.545619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7193 10:52:06.547879 Exit from DVFS_PRE_config <<<<<
7194 10:52:06.551454 Enter into PICG configuration >>>>
7195 10:52:06.554936 Exit from PICG configuration <<<<
7196 10:52:06.558053 [RX_INPUT] configuration >>>>>
7197 10:52:06.560926 [RX_INPUT] configuration <<<<<
7198 10:52:06.567690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7199 10:52:06.570958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7200 10:52:06.577824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 10:52:06.584646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 10:52:06.590744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 10:52:06.597184 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 10:52:06.601055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7205 10:52:06.603846 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7206 10:52:06.607114 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7207 10:52:06.614774 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7208 10:52:06.616773 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7209 10:52:06.620649 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7210 10:52:06.623864 ===================================
7211 10:52:06.627158 LPDDR4 DRAM CONFIGURATION
7212 10:52:06.630299 ===================================
7213 10:52:06.633506 EX_ROW_EN[0] = 0x0
7214 10:52:06.634077 EX_ROW_EN[1] = 0x0
7215 10:52:06.636611 LP4Y_EN = 0x0
7216 10:52:06.637080 WORK_FSP = 0x1
7217 10:52:06.640684 WL = 0x5
7218 10:52:06.641149 RL = 0x5
7219 10:52:06.643645 BL = 0x2
7220 10:52:06.644344 RPST = 0x0
7221 10:52:06.648193 RD_PRE = 0x0
7222 10:52:06.648747 WR_PRE = 0x1
7223 10:52:06.649661 WR_PST = 0x1
7224 10:52:06.650124 DBI_WR = 0x0
7225 10:52:06.653476 DBI_RD = 0x0
7226 10:52:06.654032 OTF = 0x1
7227 10:52:06.656817 ===================================
7228 10:52:06.663663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7229 10:52:06.666498 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7230 10:52:06.669605 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7231 10:52:06.673109 ===================================
7232 10:52:06.676799 LPDDR4 DRAM CONFIGURATION
7233 10:52:06.680159 ===================================
7234 10:52:06.682970 EX_ROW_EN[0] = 0x10
7235 10:52:06.683641 EX_ROW_EN[1] = 0x0
7236 10:52:06.686449 LP4Y_EN = 0x0
7237 10:52:06.687002 WORK_FSP = 0x1
7238 10:52:06.689324 WL = 0x5
7239 10:52:06.689786 RL = 0x5
7240 10:52:06.692478 BL = 0x2
7241 10:52:06.692939 RPST = 0x0
7242 10:52:06.695839 RD_PRE = 0x0
7243 10:52:06.696441 WR_PRE = 0x1
7244 10:52:06.699295 WR_PST = 0x1
7245 10:52:06.699801 DBI_WR = 0x0
7246 10:52:06.702436 DBI_RD = 0x0
7247 10:52:06.702896 OTF = 0x1
7248 10:52:06.705624 ===================================
7249 10:52:06.712791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7250 10:52:06.713217 ==
7251 10:52:06.715305 Dram Type= 6, Freq= 0, CH_0, rank 0
7252 10:52:06.722199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7253 10:52:06.722715 ==
7254 10:52:06.723046 [Duty_Offset_Calibration]
7255 10:52:06.726002 B0:2 B1:0 CA:4
7256 10:52:06.726417
7257 10:52:06.729463 [DutyScan_Calibration_Flow] k_type=0
7258 10:52:06.737925
7259 10:52:06.738477 ==CLK 0==
7260 10:52:06.740619 Final CLK duty delay cell = -4
7261 10:52:06.744198 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7262 10:52:06.747745 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7263 10:52:06.750747 [-4] AVG Duty = 4937%(X100)
7264 10:52:06.751414
7265 10:52:06.754074 CH0 CLK Duty spec in!! Max-Min= 187%
7266 10:52:06.757146 [DutyScan_Calibration_Flow] ====Done====
7267 10:52:06.757603
7268 10:52:06.760732 [DutyScan_Calibration_Flow] k_type=1
7269 10:52:06.776904
7270 10:52:06.777451 ==DQS 0 ==
7271 10:52:06.780182 Final DQS duty delay cell = -4
7272 10:52:06.784115 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7273 10:52:06.786908 [-4] MIN Duty = 4782%(X100), DQS PI = 2
7274 10:52:06.790241 [-4] AVG Duty = 4860%(X100)
7275 10:52:06.790832
7276 10:52:06.791211 ==DQS 1 ==
7277 10:52:06.793654 Final DQS duty delay cell = 0
7278 10:52:06.796909 [0] MAX Duty = 5187%(X100), DQS PI = 2
7279 10:52:06.800015 [0] MIN Duty = 5000%(X100), DQS PI = 10
7280 10:52:06.803302 [0] AVG Duty = 5093%(X100)
7281 10:52:06.803856
7282 10:52:06.806640 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7283 10:52:06.807103
7284 10:52:06.809748 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7285 10:52:06.812759 [DutyScan_Calibration_Flow] ====Done====
7286 10:52:06.813275
7287 10:52:06.816251 [DutyScan_Calibration_Flow] k_type=3
7288 10:52:06.834683
7289 10:52:06.835225 ==DQM 0 ==
7290 10:52:06.837387 Final DQM duty delay cell = 0
7291 10:52:06.840741 [0] MAX Duty = 5156%(X100), DQS PI = 22
7292 10:52:06.844252 [0] MIN Duty = 4875%(X100), DQS PI = 52
7293 10:52:06.847614 [0] AVG Duty = 5015%(X100)
7294 10:52:06.848194
7295 10:52:06.848563 ==DQM 1 ==
7296 10:52:06.850930 Final DQM duty delay cell = 0
7297 10:52:06.854014 [0] MAX Duty = 4969%(X100), DQS PI = 2
7298 10:52:06.857738 [0] MIN Duty = 4875%(X100), DQS PI = 8
7299 10:52:06.860669 [0] AVG Duty = 4922%(X100)
7300 10:52:06.861126
7301 10:52:06.863882 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7302 10:52:06.864362
7303 10:52:06.867111 CH0 DQM 1 Duty spec in!! Max-Min= 94%
7304 10:52:06.870377 [DutyScan_Calibration_Flow] ====Done====
7305 10:52:06.870857
7306 10:52:06.873777 [DutyScan_Calibration_Flow] k_type=2
7307 10:52:06.892141
7308 10:52:06.892693 ==DQ 0 ==
7309 10:52:06.894780 Final DQ duty delay cell = 0
7310 10:52:06.898337 [0] MAX Duty = 5124%(X100), DQS PI = 22
7311 10:52:06.901314 [0] MIN Duty = 4969%(X100), DQS PI = 10
7312 10:52:06.901873 [0] AVG Duty = 5046%(X100)
7313 10:52:06.904684
7314 10:52:06.905242 ==DQ 1 ==
7315 10:52:06.908558 Final DQ duty delay cell = 0
7316 10:52:06.910842 [0] MAX Duty = 5187%(X100), DQS PI = 2
7317 10:52:06.914438 [0] MIN Duty = 4907%(X100), DQS PI = 32
7318 10:52:06.915016 [0] AVG Duty = 5047%(X100)
7319 10:52:06.917433
7320 10:52:06.921149 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7321 10:52:06.921699
7322 10:52:06.924244 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7323 10:52:06.927599 [DutyScan_Calibration_Flow] ====Done====
7324 10:52:06.928094 ==
7325 10:52:06.930885 Dram Type= 6, Freq= 0, CH_1, rank 0
7326 10:52:06.933826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7327 10:52:06.934283 ==
7328 10:52:06.937315 [Duty_Offset_Calibration]
7329 10:52:06.937770 B0:0 B1:-1 CA:3
7330 10:52:06.938145
7331 10:52:06.940591 [DutyScan_Calibration_Flow] k_type=0
7332 10:52:06.951418
7333 10:52:06.951892 ==CLK 0==
7334 10:52:06.954100 Final CLK duty delay cell = -4
7335 10:52:06.958548 [-4] MAX Duty = 5031%(X100), DQS PI = 28
7336 10:52:06.961057 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7337 10:52:06.963857 [-4] AVG Duty = 4953%(X100)
7338 10:52:06.964286
7339 10:52:06.967371 CH1 CLK Duty spec in!! Max-Min= 156%
7340 10:52:06.970435 [DutyScan_Calibration_Flow] ====Done====
7341 10:52:06.970844
7342 10:52:06.974193 [DutyScan_Calibration_Flow] k_type=1
7343 10:52:06.990345
7344 10:52:06.990889 ==DQS 0 ==
7345 10:52:06.993767 Final DQS duty delay cell = 0
7346 10:52:06.996685 [0] MAX Duty = 5250%(X100), DQS PI = 28
7347 10:52:07.000168 [0] MIN Duty = 4907%(X100), DQS PI = 58
7348 10:52:07.003651 [0] AVG Duty = 5078%(X100)
7349 10:52:07.004230
7350 10:52:07.004593 ==DQS 1 ==
7351 10:52:07.006802 Final DQS duty delay cell = -4
7352 10:52:07.009837 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7353 10:52:07.013374 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7354 10:52:07.016773 [-4] AVG Duty = 4922%(X100)
7355 10:52:07.017317
7356 10:52:07.019482 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7357 10:52:07.019929
7358 10:52:07.022769 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7359 10:52:07.025999 [DutyScan_Calibration_Flow] ====Done====
7360 10:52:07.026606
7361 10:52:07.029367 [DutyScan_Calibration_Flow] k_type=3
7362 10:52:07.047701
7363 10:52:07.048249 ==DQM 0 ==
7364 10:52:07.050580 Final DQM duty delay cell = 0
7365 10:52:07.053941 [0] MAX Duty = 5062%(X100), DQS PI = 30
7366 10:52:07.057266 [0] MIN Duty = 4782%(X100), DQS PI = 38
7367 10:52:07.062719 [0] AVG Duty = 4922%(X100)
7368 10:52:07.063228
7369 10:52:07.063554 ==DQM 1 ==
7370 10:52:07.064233 Final DQM duty delay cell = 0
7371 10:52:07.067852 [0] MAX Duty = 5000%(X100), DQS PI = 30
7372 10:52:07.070178 [0] MIN Duty = 4813%(X100), DQS PI = 0
7373 10:52:07.073567 [0] AVG Duty = 4906%(X100)
7374 10:52:07.073993
7375 10:52:07.077880 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7376 10:52:07.078388
7377 10:52:07.080490 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7378 10:52:07.083517 [DutyScan_Calibration_Flow] ====Done====
7379 10:52:07.084016
7380 10:52:07.086729 [DutyScan_Calibration_Flow] k_type=2
7381 10:52:07.103574
7382 10:52:07.104150 ==DQ 0 ==
7383 10:52:07.106870 Final DQ duty delay cell = -4
7384 10:52:07.109778 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7385 10:52:07.113616 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7386 10:52:07.116839 [-4] AVG Duty = 4875%(X100)
7387 10:52:07.117380
7388 10:52:07.117732 ==DQ 1 ==
7389 10:52:07.120542 Final DQ duty delay cell = 0
7390 10:52:07.123264 [0] MAX Duty = 5062%(X100), DQS PI = 30
7391 10:52:07.126537 [0] MIN Duty = 4844%(X100), DQS PI = 60
7392 10:52:07.129884 [0] AVG Duty = 4953%(X100)
7393 10:52:07.130335
7394 10:52:07.132910 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7395 10:52:07.133468
7396 10:52:07.136100 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7397 10:52:07.139905 [DutyScan_Calibration_Flow] ====Done====
7398 10:52:07.142581 nWR fixed to 30
7399 10:52:07.146824 [ModeRegInit_LP4] CH0 RK0
7400 10:52:07.147376 [ModeRegInit_LP4] CH0 RK1
7401 10:52:07.149942 [ModeRegInit_LP4] CH1 RK0
7402 10:52:07.152540 [ModeRegInit_LP4] CH1 RK1
7403 10:52:07.153001 match AC timing 5
7404 10:52:07.159479 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7405 10:52:07.163022 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7406 10:52:07.166085 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7407 10:52:07.172898 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7408 10:52:07.175785 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7409 10:52:07.179370 [MiockJmeterHQA]
7410 10:52:07.179944
7411 10:52:07.182476 [DramcMiockJmeter] u1RxGatingPI = 0
7412 10:52:07.183057 0 : 4363, 4137
7413 10:52:07.183551 4 : 4363, 4138
7414 10:52:07.185664 8 : 4255, 4030
7415 10:52:07.186251 12 : 4363, 4138
7416 10:52:07.188900 16 : 4254, 4029
7417 10:52:07.189508 20 : 4252, 4027
7418 10:52:07.192350 24 : 4253, 4027
7419 10:52:07.192828 28 : 4255, 4029
7420 10:52:07.195510 32 : 4360, 4138
7421 10:52:07.196137 36 : 4252, 4027
7422 10:52:07.196633 40 : 4250, 4027
7423 10:52:07.198702 44 : 4252, 4027
7424 10:52:07.199284 48 : 4253, 4029
7425 10:52:07.202014 52 : 4250, 4027
7426 10:52:07.202497 56 : 4360, 4137
7427 10:52:07.205673 60 : 4361, 4137
7428 10:52:07.206256 64 : 4249, 4027
7429 10:52:07.208369 68 : 4252, 4029
7430 10:52:07.208879 72 : 4250, 4027
7431 10:52:07.209407 76 : 4249, 4027
7432 10:52:07.211628 80 : 4253, 4029
7433 10:52:07.212148 84 : 4360, 4138
7434 10:52:07.215566 88 : 4250, 4027
7435 10:52:07.216199 92 : 4250, 4027
7436 10:52:07.219206 96 : 4250, 3000
7437 10:52:07.219687 100 : 4253, 0
7438 10:52:07.220293 104 : 4250, 0
7439 10:52:07.222464 108 : 4250, 0
7440 10:52:07.223048 112 : 4252, 0
7441 10:52:07.225212 116 : 4250, 0
7442 10:52:07.225697 120 : 4360, 0
7443 10:52:07.226181 124 : 4361, 0
7444 10:52:07.228162 128 : 4250, 0
7445 10:52:07.228627 132 : 4249, 0
7446 10:52:07.232472 136 : 4250, 0
7447 10:52:07.233033 140 : 4250, 0
7448 10:52:07.233405 144 : 4249, 0
7449 10:52:07.235049 148 : 4250, 0
7450 10:52:07.235513 152 : 4253, 0
7451 10:52:07.238592 156 : 4249, 0
7452 10:52:07.239159 160 : 4250, 0
7453 10:52:07.239532 164 : 4250, 0
7454 10:52:07.241891 168 : 4360, 0
7455 10:52:07.242457 172 : 4360, 0
7456 10:52:07.244523 176 : 4363, 0
7457 10:52:07.244986 180 : 4250, 0
7458 10:52:07.245357 184 : 4360, 0
7459 10:52:07.248241 188 : 4250, 0
7460 10:52:07.248829 192 : 4250, 0
7461 10:52:07.249206 196 : 4250, 0
7462 10:52:07.252672 200 : 4361, 0
7463 10:52:07.253144 204 : 4360, 0
7464 10:52:07.255370 208 : 4250, 0
7465 10:52:07.255940 212 : 4250, 0
7466 10:52:07.256343 216 : 4252, 0
7467 10:52:07.257648 220 : 4250, 785
7468 10:52:07.258117 224 : 4360, 4112
7469 10:52:07.261203 228 : 4250, 4027
7470 10:52:07.261670 232 : 4249, 4027
7471 10:52:07.264447 236 : 4250, 4027
7472 10:52:07.264873 240 : 4253, 4029
7473 10:52:07.267592 244 : 4250, 4027
7474 10:52:07.268151 248 : 4249, 4027
7475 10:52:07.270806 252 : 4361, 4137
7476 10:52:07.271238 256 : 4250, 4026
7477 10:52:07.274554 260 : 4250, 4027
7478 10:52:07.275090 264 : 4361, 4137
7479 10:52:07.277979 268 : 4249, 4027
7480 10:52:07.278511 272 : 4250, 4027
7481 10:52:07.278857 276 : 4363, 4140
7482 10:52:07.281854 280 : 4250, 4027
7483 10:52:07.282386 284 : 4249, 4027
7484 10:52:07.284449 288 : 4250, 4027
7485 10:52:07.285022 292 : 4250, 4026
7486 10:52:07.288136 296 : 4250, 4027
7487 10:52:07.288710 300 : 4250, 4027
7488 10:52:07.291765 304 : 4361, 4137
7489 10:52:07.292397 308 : 4250, 4026
7490 10:52:07.294068 312 : 4250, 4027
7491 10:52:07.294547 316 : 4360, 4138
7492 10:52:07.297669 320 : 4249, 4027
7493 10:52:07.298240 324 : 4250, 4026
7494 10:52:07.300871 328 : 4363, 4140
7495 10:52:07.301450 332 : 4250, 4006
7496 10:52:07.303762 336 : 4250, 1860
7497 10:52:07.304270
7498 10:52:07.304641 MIOCK jitter meter ch=0
7499 10:52:07.304989
7500 10:52:07.307981 1T = (336-100) = 236 dly cells
7501 10:52:07.314740 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7502 10:52:07.315315 ==
7503 10:52:07.317203 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 10:52:07.320607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 10:52:07.321033 ==
7506 10:52:07.327138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 10:52:07.330362 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 10:52:07.333979 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 10:52:07.340404 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 10:52:07.350801 [CA 0] Center 43 (13~73) winsize 61
7511 10:52:07.353597 [CA 1] Center 42 (12~73) winsize 62
7512 10:52:07.359050 [CA 2] Center 37 (8~67) winsize 60
7513 10:52:07.360103 [CA 3] Center 37 (8~67) winsize 60
7514 10:52:07.363187 [CA 4] Center 36 (6~66) winsize 61
7515 10:52:07.366515 [CA 5] Center 35 (5~66) winsize 62
7516 10:52:07.367107
7517 10:52:07.369401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 10:52:07.369872
7519 10:52:07.376838 [CATrainingPosCal] consider 1 rank data
7520 10:52:07.377433 u2DelayCellTimex100 = 275/100 ps
7521 10:52:07.383159 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7522 10:52:07.386069 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7523 10:52:07.389723 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7524 10:52:07.392598 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7525 10:52:07.395965 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7526 10:52:07.399313 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7527 10:52:07.399870
7528 10:52:07.403101 CA PerBit enable=1, Macro0, CA PI delay=35
7529 10:52:07.403659
7530 10:52:07.405682 [CBTSetCACLKResult] CA Dly = 35
7531 10:52:07.409485 CS Dly: 10 (0~41)
7532 10:52:07.412709 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 10:52:07.416397 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 10:52:07.416993 ==
7535 10:52:07.419232 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 10:52:07.425881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 10:52:07.426445 ==
7538 10:52:07.429144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 10:52:07.436150 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 10:52:07.438928 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 10:52:07.445753 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 10:52:07.453264 [CA 0] Center 43 (13~74) winsize 62
7543 10:52:07.457169 [CA 1] Center 43 (13~73) winsize 61
7544 10:52:07.461412 [CA 2] Center 38 (9~68) winsize 60
7545 10:52:07.463299 [CA 3] Center 38 (9~68) winsize 60
7546 10:52:07.466941 [CA 4] Center 37 (7~67) winsize 61
7547 10:52:07.469839 [CA 5] Center 36 (6~66) winsize 61
7548 10:52:07.470425
7549 10:52:07.473258 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 10:52:07.473741
7551 10:52:07.480668 [CATrainingPosCal] consider 2 rank data
7552 10:52:07.481232 u2DelayCellTimex100 = 275/100 ps
7553 10:52:07.486371 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7554 10:52:07.489407 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7555 10:52:07.493177 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7556 10:52:07.496126 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7557 10:52:07.499913 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7558 10:52:07.503034 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7559 10:52:07.503592
7560 10:52:07.506584 CA PerBit enable=1, Macro0, CA PI delay=36
7561 10:52:07.507139
7562 10:52:07.509692 [CBTSetCACLKResult] CA Dly = 36
7563 10:52:07.512453 CS Dly: 11 (0~43)
7564 10:52:07.516598 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 10:52:07.519542 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 10:52:07.520129
7567 10:52:07.522518 ----->DramcWriteLeveling(PI) begin...
7568 10:52:07.523081 ==
7569 10:52:07.525773 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 10:52:07.532836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 10:52:07.533397 ==
7572 10:52:07.535920 Write leveling (Byte 0): 34 => 34
7573 10:52:07.538919 Write leveling (Byte 1): 26 => 26
7574 10:52:07.542414 DramcWriteLeveling(PI) end<-----
7575 10:52:07.542976
7576 10:52:07.543352 ==
7577 10:52:07.545687 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 10:52:07.548827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 10:52:07.549387 ==
7580 10:52:07.552461 [Gating] SW mode calibration
7581 10:52:07.559144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 10:52:07.565166 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 10:52:07.568467 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 10:52:07.572012 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 10:52:07.578661 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7586 10:52:07.581935 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7587 10:52:07.585409 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7588 10:52:07.591680 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7589 10:52:07.594841 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 10:52:07.598328 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 10:52:07.604758 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 10:52:07.608539 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 10:52:07.612674 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7594 10:52:07.618348 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7595 10:52:07.622215 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7596 10:52:07.624325 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
7597 10:52:07.631510 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7598 10:52:07.635123 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 10:52:07.637671 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:52:07.644710 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 10:52:07.647645 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7602 10:52:07.650823 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7603 10:52:07.657434 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7604 10:52:07.660383 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7605 10:52:07.665624 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7606 10:52:07.670864 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 10:52:07.673841 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 10:52:07.677128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 10:52:07.683717 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 10:52:07.687670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 10:52:07.690332 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7612 10:52:07.697298 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 10:52:07.700477 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 10:52:07.703681 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 10:52:07.710275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 10:52:07.713236 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 10:52:07.717066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 10:52:07.723039 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 10:52:07.726589 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 10:52:07.729594 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 10:52:07.736420 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:52:07.739865 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:52:07.742849 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:52:07.749823 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:52:07.752718 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 10:52:07.756550 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 10:52:07.763159 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7628 10:52:07.763724 Total UI for P1: 0, mck2ui 16
7629 10:52:07.769600 best dqsien dly found for B0: ( 1, 9, 10)
7630 10:52:07.773038 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 10:52:07.775894 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 10:52:07.779413 Total UI for P1: 0, mck2ui 16
7633 10:52:07.782874 best dqsien dly found for B1: ( 1, 9, 20)
7634 10:52:07.786050 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7635 10:52:07.788851 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7636 10:52:07.789316
7637 10:52:07.795559 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7638 10:52:07.798981 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7639 10:52:07.802357 [Gating] SW calibration Done
7640 10:52:07.802915 ==
7641 10:52:07.805631 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 10:52:07.808904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 10:52:07.809465 ==
7644 10:52:07.809841 RX Vref Scan: 0
7645 10:52:07.812112
7646 10:52:07.812610 RX Vref 0 -> 0, step: 1
7647 10:52:07.813033
7648 10:52:07.815168 RX Delay 0 -> 252, step: 8
7649 10:52:07.818935 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7650 10:52:07.822401 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7651 10:52:07.828758 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7652 10:52:07.831720 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7653 10:52:07.834993 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7654 10:52:07.837974 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7655 10:52:07.841771 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7656 10:52:07.848436 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7657 10:52:07.851580 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7658 10:52:07.854826 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7659 10:52:07.858887 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7660 10:52:07.864510 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7661 10:52:07.868331 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7662 10:52:07.872075 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7663 10:52:07.874217 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7664 10:52:07.877554 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7665 10:52:07.880887 ==
7666 10:52:07.884197 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 10:52:07.887376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 10:52:07.887938 ==
7669 10:52:07.888344 DQS Delay:
7670 10:52:07.891481 DQS0 = 0, DQS1 = 0
7671 10:52:07.892066 DQM Delay:
7672 10:52:07.894205 DQM0 = 132, DQM1 = 127
7673 10:52:07.894787 DQ Delay:
7674 10:52:07.897502 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7675 10:52:07.900798 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7676 10:52:07.904077 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7677 10:52:07.907283 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7678 10:52:07.907838
7679 10:52:07.908250
7680 10:52:07.910520 ==
7681 10:52:07.911096 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 10:52:07.916908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 10:52:07.917391 ==
7684 10:52:07.917866
7685 10:52:07.918306
7686 10:52:07.920473 TX Vref Scan disable
7687 10:52:07.920941 == TX Byte 0 ==
7688 10:52:07.923404 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7689 10:52:07.930323 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7690 10:52:07.930896 == TX Byte 1 ==
7691 10:52:07.936941 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7692 10:52:07.940227 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7693 10:52:07.940700 ==
7694 10:52:07.943380 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 10:52:07.946635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 10:52:07.947206 ==
7697 10:52:07.960684
7698 10:52:07.964332 TX Vref early break, caculate TX vref
7699 10:52:07.967175 TX Vref=16, minBit 1, minWin=20, winSum=358
7700 10:52:07.970443 TX Vref=18, minBit 1, minWin=21, winSum=369
7701 10:52:07.974419 TX Vref=20, minBit 1, minWin=22, winSum=377
7702 10:52:07.976858 TX Vref=22, minBit 1, minWin=23, winSum=390
7703 10:52:07.980614 TX Vref=24, minBit 0, minWin=24, winSum=402
7704 10:52:07.987019 TX Vref=26, minBit 1, minWin=24, winSum=405
7705 10:52:07.990503 TX Vref=28, minBit 2, minWin=24, winSum=410
7706 10:52:07.994083 TX Vref=30, minBit 4, minWin=23, winSum=405
7707 10:52:07.996960 TX Vref=32, minBit 0, minWin=23, winSum=396
7708 10:52:07.999767 TX Vref=34, minBit 4, minWin=22, winSum=384
7709 10:52:08.006991 [TxChooseVref] Worse bit 2, Min win 24, Win sum 410, Final Vref 28
7710 10:52:08.007563
7711 10:52:08.010176 Final TX Range 0 Vref 28
7712 10:52:08.010749
7713 10:52:08.011122 ==
7714 10:52:08.013108 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 10:52:08.016684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 10:52:08.017157 ==
7717 10:52:08.017529
7718 10:52:08.017917
7719 10:52:08.019827 TX Vref Scan disable
7720 10:52:08.026880 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7721 10:52:08.027448 == TX Byte 0 ==
7722 10:52:08.029824 u2DelayCellOfst[0]=14 cells (4 PI)
7723 10:52:08.033530 u2DelayCellOfst[1]=17 cells (5 PI)
7724 10:52:08.036139 u2DelayCellOfst[2]=10 cells (3 PI)
7725 10:52:08.039516 u2DelayCellOfst[3]=14 cells (4 PI)
7726 10:52:08.043156 u2DelayCellOfst[4]=10 cells (3 PI)
7727 10:52:08.046019 u2DelayCellOfst[5]=0 cells (0 PI)
7728 10:52:08.049287 u2DelayCellOfst[6]=21 cells (6 PI)
7729 10:52:08.052653 u2DelayCellOfst[7]=17 cells (5 PI)
7730 10:52:08.056136 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7731 10:52:08.059708 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7732 10:52:08.063036 == TX Byte 1 ==
7733 10:52:08.065820 u2DelayCellOfst[8]=0 cells (0 PI)
7734 10:52:08.069297 u2DelayCellOfst[9]=0 cells (0 PI)
7735 10:52:08.072763 u2DelayCellOfst[10]=3 cells (1 PI)
7736 10:52:08.076380 u2DelayCellOfst[11]=3 cells (1 PI)
7737 10:52:08.079436 u2DelayCellOfst[12]=10 cells (3 PI)
7738 10:52:08.082500 u2DelayCellOfst[13]=10 cells (3 PI)
7739 10:52:08.083056 u2DelayCellOfst[14]=14 cells (4 PI)
7740 10:52:08.085755 u2DelayCellOfst[15]=10 cells (3 PI)
7741 10:52:08.092077 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7742 10:52:08.095328 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7743 10:52:08.099270 DramC Write-DBI on
7744 10:52:08.099827 ==
7745 10:52:08.102264 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 10:52:08.105212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 10:52:08.105770 ==
7748 10:52:08.106228
7749 10:52:08.106776
7750 10:52:08.109204 TX Vref Scan disable
7751 10:52:08.109757 == TX Byte 0 ==
7752 10:52:08.115613 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7753 10:52:08.116330 == TX Byte 1 ==
7754 10:52:08.118886 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7755 10:52:08.121695 DramC Write-DBI off
7756 10:52:08.122175
7757 10:52:08.122543 [DATLAT]
7758 10:52:08.125129 Freq=1600, CH0 RK0
7759 10:52:08.125595
7760 10:52:08.125964 DATLAT Default: 0xf
7761 10:52:08.128358 0, 0xFFFF, sum = 0
7762 10:52:08.131812 1, 0xFFFF, sum = 0
7763 10:52:08.132404 2, 0xFFFF, sum = 0
7764 10:52:08.135415 3, 0xFFFF, sum = 0
7765 10:52:08.135885 4, 0xFFFF, sum = 0
7766 10:52:08.137962 5, 0xFFFF, sum = 0
7767 10:52:08.138409 6, 0xFFFF, sum = 0
7768 10:52:08.141563 7, 0xFFFF, sum = 0
7769 10:52:08.141986 8, 0xFFFF, sum = 0
7770 10:52:08.144671 9, 0xFFFF, sum = 0
7771 10:52:08.145089 10, 0xFFFF, sum = 0
7772 10:52:08.148176 11, 0xFFFF, sum = 0
7773 10:52:08.148785 12, 0xFFFF, sum = 0
7774 10:52:08.151190 13, 0xFFFF, sum = 0
7775 10:52:08.151714 14, 0x0, sum = 1
7776 10:52:08.155024 15, 0x0, sum = 2
7777 10:52:08.155554 16, 0x0, sum = 3
7778 10:52:08.158094 17, 0x0, sum = 4
7779 10:52:08.158612 best_step = 15
7780 10:52:08.158942
7781 10:52:08.159249 ==
7782 10:52:08.161095 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 10:52:08.168537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 10:52:08.169054 ==
7785 10:52:08.169389 RX Vref Scan: 1
7786 10:52:08.169699
7787 10:52:08.171164 Set Vref Range= 24 -> 127
7788 10:52:08.171577
7789 10:52:08.174825 RX Vref 24 -> 127, step: 1
7790 10:52:08.175239
7791 10:52:08.177637 RX Delay 11 -> 252, step: 4
7792 10:52:08.178053
7793 10:52:08.180959 Set Vref, RX VrefLevel [Byte0]: 24
7794 10:52:08.184439 [Byte1]: 24
7795 10:52:08.184953
7796 10:52:08.187639 Set Vref, RX VrefLevel [Byte0]: 25
7797 10:52:08.191521 [Byte1]: 25
7798 10:52:08.192078
7799 10:52:08.193968 Set Vref, RX VrefLevel [Byte0]: 26
7800 10:52:08.197584 [Byte1]: 26
7801 10:52:08.201028
7802 10:52:08.201542 Set Vref, RX VrefLevel [Byte0]: 27
7803 10:52:08.204465 [Byte1]: 27
7804 10:52:08.208505
7805 10:52:08.208942 Set Vref, RX VrefLevel [Byte0]: 28
7806 10:52:08.211611 [Byte1]: 28
7807 10:52:08.216192
7808 10:52:08.216605 Set Vref, RX VrefLevel [Byte0]: 29
7809 10:52:08.218882 [Byte1]: 29
7810 10:52:08.223631
7811 10:52:08.224186 Set Vref, RX VrefLevel [Byte0]: 30
7812 10:52:08.227176 [Byte1]: 30
7813 10:52:08.231069
7814 10:52:08.231579 Set Vref, RX VrefLevel [Byte0]: 31
7815 10:52:08.234406 [Byte1]: 31
7816 10:52:08.238778
7817 10:52:08.239333 Set Vref, RX VrefLevel [Byte0]: 32
7818 10:52:08.242416 [Byte1]: 32
7819 10:52:08.246062
7820 10:52:08.246541 Set Vref, RX VrefLevel [Byte0]: 33
7821 10:52:08.249443 [Byte1]: 33
7822 10:52:08.254107
7823 10:52:08.254662 Set Vref, RX VrefLevel [Byte0]: 34
7824 10:52:08.257229 [Byte1]: 34
7825 10:52:08.261611
7826 10:52:08.262188 Set Vref, RX VrefLevel [Byte0]: 35
7827 10:52:08.265456 [Byte1]: 35
7828 10:52:08.270035
7829 10:52:08.270603 Set Vref, RX VrefLevel [Byte0]: 36
7830 10:52:08.272467 [Byte1]: 36
7831 10:52:08.276558
7832 10:52:08.277016 Set Vref, RX VrefLevel [Byte0]: 37
7833 10:52:08.280176 [Byte1]: 37
7834 10:52:08.284680
7835 10:52:08.285232 Set Vref, RX VrefLevel [Byte0]: 38
7836 10:52:08.289056 [Byte1]: 38
7837 10:52:08.292071
7838 10:52:08.292632 Set Vref, RX VrefLevel [Byte0]: 39
7839 10:52:08.295011 [Byte1]: 39
7840 10:52:08.299810
7841 10:52:08.300573 Set Vref, RX VrefLevel [Byte0]: 40
7842 10:52:08.303130 [Byte1]: 40
7843 10:52:08.307226
7844 10:52:08.307785 Set Vref, RX VrefLevel [Byte0]: 41
7845 10:52:08.311010 [Byte1]: 41
7846 10:52:08.314519
7847 10:52:08.314979 Set Vref, RX VrefLevel [Byte0]: 42
7848 10:52:08.318122 [Byte1]: 42
7849 10:52:08.322917
7850 10:52:08.323473 Set Vref, RX VrefLevel [Byte0]: 43
7851 10:52:08.325781 [Byte1]: 43
7852 10:52:08.329862
7853 10:52:08.330321 Set Vref, RX VrefLevel [Byte0]: 44
7854 10:52:08.333422 [Byte1]: 44
7855 10:52:08.338137
7856 10:52:08.338672 Set Vref, RX VrefLevel [Byte0]: 45
7857 10:52:08.340800 [Byte1]: 45
7858 10:52:08.345103
7859 10:52:08.345562 Set Vref, RX VrefLevel [Byte0]: 46
7860 10:52:08.348586 [Byte1]: 46
7861 10:52:08.353596
7862 10:52:08.354151 Set Vref, RX VrefLevel [Byte0]: 47
7863 10:52:08.355969 [Byte1]: 47
7864 10:52:08.360818
7865 10:52:08.361381 Set Vref, RX VrefLevel [Byte0]: 48
7866 10:52:08.363743 [Byte1]: 48
7867 10:52:08.368436
7868 10:52:08.369016 Set Vref, RX VrefLevel [Byte0]: 49
7869 10:52:08.371729 [Byte1]: 49
7870 10:52:08.376126
7871 10:52:08.376691 Set Vref, RX VrefLevel [Byte0]: 50
7872 10:52:08.379140 [Byte1]: 50
7873 10:52:08.383674
7874 10:52:08.384271 Set Vref, RX VrefLevel [Byte0]: 51
7875 10:52:08.387068 [Byte1]: 51
7876 10:52:08.391411
7877 10:52:08.391980 Set Vref, RX VrefLevel [Byte0]: 52
7878 10:52:08.394210 [Byte1]: 52
7879 10:52:08.398733
7880 10:52:08.399296 Set Vref, RX VrefLevel [Byte0]: 53
7881 10:52:08.401810 [Byte1]: 53
7882 10:52:08.406477
7883 10:52:08.407053 Set Vref, RX VrefLevel [Byte0]: 54
7884 10:52:08.409568 [Byte1]: 54
7885 10:52:08.413786
7886 10:52:08.414368 Set Vref, RX VrefLevel [Byte0]: 55
7887 10:52:08.417138 [Byte1]: 55
7888 10:52:08.421247
7889 10:52:08.421801 Set Vref, RX VrefLevel [Byte0]: 56
7890 10:52:08.425085 [Byte1]: 56
7891 10:52:08.429267
7892 10:52:08.429864 Set Vref, RX VrefLevel [Byte0]: 57
7893 10:52:08.432283 [Byte1]: 57
7894 10:52:08.436689
7895 10:52:08.437348 Set Vref, RX VrefLevel [Byte0]: 58
7896 10:52:08.440274 [Byte1]: 58
7897 10:52:08.444207
7898 10:52:08.444674 Set Vref, RX VrefLevel [Byte0]: 59
7899 10:52:08.447539 [Byte1]: 59
7900 10:52:08.451993
7901 10:52:08.452612 Set Vref, RX VrefLevel [Byte0]: 60
7902 10:52:08.455838 [Byte1]: 60
7903 10:52:08.459849
7904 10:52:08.460511 Set Vref, RX VrefLevel [Byte0]: 61
7905 10:52:08.462983 [Byte1]: 61
7906 10:52:08.467153
7907 10:52:08.467902 Set Vref, RX VrefLevel [Byte0]: 62
7908 10:52:08.471004 [Byte1]: 62
7909 10:52:08.474531
7910 10:52:08.475055 Set Vref, RX VrefLevel [Byte0]: 63
7911 10:52:08.478168 [Byte1]: 63
7912 10:52:08.482763
7913 10:52:08.483319 Set Vref, RX VrefLevel [Byte0]: 64
7914 10:52:08.485458 [Byte1]: 64
7915 10:52:08.490205
7916 10:52:08.490764 Set Vref, RX VrefLevel [Byte0]: 65
7917 10:52:08.493451 [Byte1]: 65
7918 10:52:08.497504
7919 10:52:08.498060 Set Vref, RX VrefLevel [Byte0]: 66
7920 10:52:08.500953 [Byte1]: 66
7921 10:52:08.505274
7922 10:52:08.505825 Set Vref, RX VrefLevel [Byte0]: 67
7923 10:52:08.508670 [Byte1]: 67
7924 10:52:08.513024
7925 10:52:08.513583 Set Vref, RX VrefLevel [Byte0]: 68
7926 10:52:08.516004 [Byte1]: 68
7927 10:52:08.520962
7928 10:52:08.521517 Set Vref, RX VrefLevel [Byte0]: 69
7929 10:52:08.523718 [Byte1]: 69
7930 10:52:08.528273
7931 10:52:08.528821 Set Vref, RX VrefLevel [Byte0]: 70
7932 10:52:08.531357 [Byte1]: 70
7933 10:52:08.535996
7934 10:52:08.536618 Set Vref, RX VrefLevel [Byte0]: 71
7935 10:52:08.539139 [Byte1]: 71
7936 10:52:08.543609
7937 10:52:08.544229 Set Vref, RX VrefLevel [Byte0]: 72
7938 10:52:08.546695 [Byte1]: 72
7939 10:52:08.551133
7940 10:52:08.551689 Set Vref, RX VrefLevel [Byte0]: 73
7941 10:52:08.554089 [Byte1]: 73
7942 10:52:08.558639
7943 10:52:08.559208 Set Vref, RX VrefLevel [Byte0]: 74
7944 10:52:08.562195 [Byte1]: 74
7945 10:52:08.566546
7946 10:52:08.567100 Set Vref, RX VrefLevel [Byte0]: 75
7947 10:52:08.569737 [Byte1]: 75
7948 10:52:08.573784
7949 10:52:08.574424 Set Vref, RX VrefLevel [Byte0]: 76
7950 10:52:08.576789 [Byte1]: 76
7951 10:52:08.581111
7952 10:52:08.584690 Set Vref, RX VrefLevel [Byte0]: 77
7953 10:52:08.587872 [Byte1]: 77
7954 10:52:08.588468
7955 10:52:08.591330 Final RX Vref Byte 0 = 57 to rank0
7956 10:52:08.593979 Final RX Vref Byte 1 = 57 to rank0
7957 10:52:08.597944 Final RX Vref Byte 0 = 57 to rank1
7958 10:52:08.601229 Final RX Vref Byte 1 = 57 to rank1==
7959 10:52:08.604595 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 10:52:08.608123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 10:52:08.608681 ==
7962 10:52:08.609055 DQS Delay:
7963 10:52:08.610503 DQS0 = 0, DQS1 = 0
7964 10:52:08.610963 DQM Delay:
7965 10:52:08.614557 DQM0 = 129, DQM1 = 124
7966 10:52:08.615114 DQ Delay:
7967 10:52:08.617452 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7968 10:52:08.620609 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
7969 10:52:08.624093 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7970 10:52:08.627145 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =132
7971 10:52:08.630506
7972 10:52:08.630963
7973 10:52:08.631322
7974 10:52:08.631659 [DramC_TX_OE_Calibration] TA2
7975 10:52:08.633754 Original DQ_B0 (3 6) =30, OEN = 27
7976 10:52:08.637600 Original DQ_B1 (3 6) =30, OEN = 27
7977 10:52:08.641823 24, 0x0, End_B0=24 End_B1=24
7978 10:52:08.643793 25, 0x0, End_B0=25 End_B1=25
7979 10:52:08.646884 26, 0x0, End_B0=26 End_B1=26
7980 10:52:08.647448 27, 0x0, End_B0=27 End_B1=27
7981 10:52:08.650725 28, 0x0, End_B0=28 End_B1=28
7982 10:52:08.653384 29, 0x0, End_B0=29 End_B1=29
7983 10:52:08.656765 30, 0x0, End_B0=30 End_B1=30
7984 10:52:08.660406 31, 0x4141, End_B0=30 End_B1=30
7985 10:52:08.663365 Byte0 end_step=30 best_step=27
7986 10:52:08.663928 Byte1 end_step=30 best_step=27
7987 10:52:08.666881 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 10:52:08.670144 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 10:52:08.670702
7990 10:52:08.671069
7991 10:52:08.680574 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7992 10:52:08.681269 CH0 RK0: MR19=303, MR18=1714
7993 10:52:08.686345 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7994 10:52:08.686932
7995 10:52:08.689791 ----->DramcWriteLeveling(PI) begin...
7996 10:52:08.692841 ==
7997 10:52:08.693432 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 10:52:08.699530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 10:52:08.700128 ==
8000 10:52:08.703370 Write leveling (Byte 0): 35 => 35
8001 10:52:08.706163 Write leveling (Byte 1): 28 => 28
8002 10:52:08.709903 DramcWriteLeveling(PI) end<-----
8003 10:52:08.710483
8004 10:52:08.710858 ==
8005 10:52:08.712712 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 10:52:08.716201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 10:52:08.716663 ==
8008 10:52:08.719483 [Gating] SW mode calibration
8009 10:52:08.726255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 10:52:08.732566 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 10:52:08.735645 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 10:52:08.738921 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 10:52:08.746256 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8014 10:52:08.748952 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8015 10:52:08.751851 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8016 10:52:08.759454 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
8017 10:52:08.762014 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 10:52:08.766051 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 10:52:08.772678 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 10:52:08.775154 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 10:52:08.778428 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8022 10:52:08.784944 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8023 10:52:08.788547 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8024 10:52:08.791432 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8025 10:52:08.798363 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 10:52:08.801877 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 10:52:08.804924 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 10:52:08.811604 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8029 10:52:08.814734 1 6 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
8030 10:52:08.817957 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8031 10:52:08.824791 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8032 10:52:08.827711 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 10:52:08.831041 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 10:52:08.837732 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 10:52:08.840754 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 10:52:08.844303 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8037 10:52:08.850671 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 10:52:08.853926 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 10:52:08.857346 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 10:52:08.864025 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 10:52:08.867338 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 10:52:08.870381 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 10:52:08.877237 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 10:52:08.880409 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 10:52:08.883580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 10:52:08.890036 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 10:52:08.893750 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 10:52:08.896617 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 10:52:08.903512 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 10:52:08.907111 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 10:52:08.910581 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:52:08.917071 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:52:08.920219 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 10:52:08.923390 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8055 10:52:08.926608 Total UI for P1: 0, mck2ui 16
8056 10:52:08.929445 best dqsien dly found for B0: ( 1, 9, 8)
8057 10:52:08.937272 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 10:52:08.939357 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 10:52:08.942561 Total UI for P1: 0, mck2ui 16
8060 10:52:08.946086 best dqsien dly found for B1: ( 1, 9, 16)
8061 10:52:08.949347 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8062 10:52:08.953171 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8063 10:52:08.953730
8064 10:52:08.955990 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8065 10:52:08.962180 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8066 10:52:08.962746 [Gating] SW calibration Done
8067 10:52:08.963121 ==
8068 10:52:08.966042 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 10:52:08.972599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 10:52:08.973175 ==
8071 10:52:08.973547 RX Vref Scan: 0
8072 10:52:08.973887
8073 10:52:08.975575 RX Vref 0 -> 0, step: 1
8074 10:52:08.976062
8075 10:52:08.978985 RX Delay 0 -> 252, step: 8
8076 10:52:08.982977 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8077 10:52:08.985992 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8078 10:52:08.988662 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8079 10:52:08.995064 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8080 10:52:08.998637 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8081 10:52:09.002046 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8082 10:52:09.005058 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8083 10:52:09.008500 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8084 10:52:09.015073 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8085 10:52:09.018327 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8086 10:52:09.021731 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8087 10:52:09.024872 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8088 10:52:09.028823 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8089 10:52:09.034911 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8090 10:52:09.038502 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8091 10:52:09.041244 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8092 10:52:09.041710 ==
8093 10:52:09.044945 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 10:52:09.048821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 10:52:09.051479 ==
8096 10:52:09.052072 DQS Delay:
8097 10:52:09.052445 DQS0 = 0, DQS1 = 0
8098 10:52:09.054598 DQM Delay:
8099 10:52:09.055158 DQM0 = 132, DQM1 = 128
8100 10:52:09.057838 DQ Delay:
8101 10:52:09.061469 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8102 10:52:09.064318 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8103 10:52:09.068249 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8104 10:52:09.071276 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8105 10:52:09.071841
8106 10:52:09.072250
8107 10:52:09.072593 ==
8108 10:52:09.074657 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 10:52:09.078162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 10:52:09.081296 ==
8111 10:52:09.081860
8112 10:52:09.082231
8113 10:52:09.082569 TX Vref Scan disable
8114 10:52:09.083928 == TX Byte 0 ==
8115 10:52:09.087659 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8116 10:52:09.091970 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8117 10:52:09.095095 == TX Byte 1 ==
8118 10:52:09.097394 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8119 10:52:09.100610 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8120 10:52:09.104157 ==
8121 10:52:09.107250 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 10:52:09.111303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 10:52:09.111880 ==
8124 10:52:09.123915
8125 10:52:09.127282 TX Vref early break, caculate TX vref
8126 10:52:09.129885 TX Vref=16, minBit 0, minWin=22, winSum=373
8127 10:52:09.133455 TX Vref=18, minBit 3, minWin=23, winSum=387
8128 10:52:09.137038 TX Vref=20, minBit 5, minWin=23, winSum=394
8129 10:52:09.140486 TX Vref=22, minBit 1, minWin=24, winSum=401
8130 10:52:09.143280 TX Vref=24, minBit 3, minWin=24, winSum=410
8131 10:52:09.149899 TX Vref=26, minBit 2, minWin=24, winSum=414
8132 10:52:09.153246 TX Vref=28, minBit 2, minWin=24, winSum=418
8133 10:52:09.156661 TX Vref=30, minBit 0, minWin=24, winSum=410
8134 10:52:09.159903 TX Vref=32, minBit 0, minWin=24, winSum=402
8135 10:52:09.163461 TX Vref=34, minBit 2, minWin=23, winSum=395
8136 10:52:09.169882 [TxChooseVref] Worse bit 2, Min win 24, Win sum 418, Final Vref 28
8137 10:52:09.170457
8138 10:52:09.173648 Final TX Range 0 Vref 28
8139 10:52:09.174216
8140 10:52:09.174588 ==
8141 10:52:09.176516 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 10:52:09.179787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 10:52:09.180290 ==
8144 10:52:09.180660
8145 10:52:09.181005
8146 10:52:09.182897 TX Vref Scan disable
8147 10:52:09.189682 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8148 10:52:09.190210 == TX Byte 0 ==
8149 10:52:09.192908 u2DelayCellOfst[0]=10 cells (3 PI)
8150 10:52:09.196498 u2DelayCellOfst[1]=14 cells (4 PI)
8151 10:52:09.199425 u2DelayCellOfst[2]=10 cells (3 PI)
8152 10:52:09.202627 u2DelayCellOfst[3]=10 cells (3 PI)
8153 10:52:09.206079 u2DelayCellOfst[4]=7 cells (2 PI)
8154 10:52:09.208827 u2DelayCellOfst[5]=0 cells (0 PI)
8155 10:52:09.212342 u2DelayCellOfst[6]=14 cells (4 PI)
8156 10:52:09.215696 u2DelayCellOfst[7]=14 cells (4 PI)
8157 10:52:09.219561 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8158 10:52:09.222127 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8159 10:52:09.225872 == TX Byte 1 ==
8160 10:52:09.228930 u2DelayCellOfst[8]=0 cells (0 PI)
8161 10:52:09.232374 u2DelayCellOfst[9]=0 cells (0 PI)
8162 10:52:09.236007 u2DelayCellOfst[10]=7 cells (2 PI)
8163 10:52:09.236575 u2DelayCellOfst[11]=3 cells (1 PI)
8164 10:52:09.239127 u2DelayCellOfst[12]=10 cells (3 PI)
8165 10:52:09.242092 u2DelayCellOfst[13]=10 cells (3 PI)
8166 10:52:09.245519 u2DelayCellOfst[14]=17 cells (5 PI)
8167 10:52:09.248596 u2DelayCellOfst[15]=14 cells (4 PI)
8168 10:52:09.255561 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8169 10:52:09.258510 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8170 10:52:09.258938 DramC Write-DBI on
8171 10:52:09.261565 ==
8172 10:52:09.265221 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 10:52:09.268633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 10:52:09.269151 ==
8175 10:52:09.269494
8176 10:52:09.269808
8177 10:52:09.271933 TX Vref Scan disable
8178 10:52:09.272504 == TX Byte 0 ==
8179 10:52:09.278077 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8180 10:52:09.278583 == TX Byte 1 ==
8181 10:52:09.281425 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8182 10:52:09.284612 DramC Write-DBI off
8183 10:52:09.285126
8184 10:52:09.285463 [DATLAT]
8185 10:52:09.288388 Freq=1600, CH0 RK1
8186 10:52:09.288905
8187 10:52:09.289243 DATLAT Default: 0xf
8188 10:52:09.291711 0, 0xFFFF, sum = 0
8189 10:52:09.292311 1, 0xFFFF, sum = 0
8190 10:52:09.295083 2, 0xFFFF, sum = 0
8191 10:52:09.297971 3, 0xFFFF, sum = 0
8192 10:52:09.298538 4, 0xFFFF, sum = 0
8193 10:52:09.301583 5, 0xFFFF, sum = 0
8194 10:52:09.302177 6, 0xFFFF, sum = 0
8195 10:52:09.304558 7, 0xFFFF, sum = 0
8196 10:52:09.305141 8, 0xFFFF, sum = 0
8197 10:52:09.308814 9, 0xFFFF, sum = 0
8198 10:52:09.309504 10, 0xFFFF, sum = 0
8199 10:52:09.311164 11, 0xFFFF, sum = 0
8200 10:52:09.311636 12, 0xFFFF, sum = 0
8201 10:52:09.314040 13, 0xFFFF, sum = 0
8202 10:52:09.314538 14, 0x0, sum = 1
8203 10:52:09.317708 15, 0x0, sum = 2
8204 10:52:09.318277 16, 0x0, sum = 3
8205 10:52:09.320885 17, 0x0, sum = 4
8206 10:52:09.321619 best_step = 15
8207 10:52:09.322123
8208 10:52:09.322479 ==
8209 10:52:09.323959 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 10:52:09.331229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 10:52:09.331798 ==
8212 10:52:09.332216 RX Vref Scan: 0
8213 10:52:09.332568
8214 10:52:09.334316 RX Vref 0 -> 0, step: 1
8215 10:52:09.334776
8216 10:52:09.338207 RX Delay 19 -> 252, step: 4
8217 10:52:09.340998 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8218 10:52:09.344437 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8219 10:52:09.347722 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8220 10:52:09.354359 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8221 10:52:09.356665 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8222 10:52:09.360736 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8223 10:52:09.363695 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8224 10:52:09.370403 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8225 10:52:09.373929 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8226 10:52:09.377040 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8227 10:52:09.379829 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8228 10:52:09.383475 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8229 10:52:09.390714 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8230 10:52:09.392811 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8231 10:52:09.396915 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8232 10:52:09.399669 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8233 10:52:09.400270 ==
8234 10:52:09.403348 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 10:52:09.409664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 10:52:09.410230 ==
8237 10:52:09.410625 DQS Delay:
8238 10:52:09.413679 DQS0 = 0, DQS1 = 0
8239 10:52:09.414239 DQM Delay:
8240 10:52:09.416678 DQM0 = 129, DQM1 = 124
8241 10:52:09.417244 DQ Delay:
8242 10:52:09.420859 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8243 10:52:09.423738 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8244 10:52:09.425877 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8245 10:52:09.429570 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8246 10:52:09.430137
8247 10:52:09.430506
8248 10:52:09.430846
8249 10:52:09.432469 [DramC_TX_OE_Calibration] TA2
8250 10:52:09.436107 Original DQ_B0 (3 6) =30, OEN = 27
8251 10:52:09.439762 Original DQ_B1 (3 6) =30, OEN = 27
8252 10:52:09.443112 24, 0x0, End_B0=24 End_B1=24
8253 10:52:09.445801 25, 0x0, End_B0=25 End_B1=25
8254 10:52:09.446452 26, 0x0, End_B0=26 End_B1=26
8255 10:52:09.448947 27, 0x0, End_B0=27 End_B1=27
8256 10:52:09.452736 28, 0x0, End_B0=28 End_B1=28
8257 10:52:09.456084 29, 0x0, End_B0=29 End_B1=29
8258 10:52:09.459154 30, 0x0, End_B0=30 End_B1=30
8259 10:52:09.459724 31, 0x4141, End_B0=30 End_B1=30
8260 10:52:09.462856 Byte0 end_step=30 best_step=27
8261 10:52:09.465337 Byte1 end_step=30 best_step=27
8262 10:52:09.469267 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 10:52:09.472379 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 10:52:09.472941
8265 10:52:09.473308
8266 10:52:09.479045 [DQSOSCAuto] RK1, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8267 10:52:09.482243 CH0 RK1: MR19=303, MR18=1413
8268 10:52:09.488834 CH0_RK1: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
8269 10:52:09.492422 [RxdqsGatingPostProcess] freq 1600
8270 10:52:09.498875 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 10:52:09.499434 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 10:52:09.502856 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 10:52:09.505996 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 10:52:09.508735 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 10:52:09.512281 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 10:52:09.515864 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 10:52:09.518415 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 10:52:09.521619 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 10:52:09.525242 Pre-setting of DQS Precalculation
8280 10:52:09.528270 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 10:52:09.531435 ==
8282 10:52:09.534827 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 10:52:09.537975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 10:52:09.538459 ==
8285 10:52:09.541671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 10:52:09.547794 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 10:52:09.551516 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 10:52:09.557901 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 10:52:09.566245 [CA 0] Center 42 (13~72) winsize 60
8290 10:52:09.569680 [CA 1] Center 42 (12~73) winsize 62
8291 10:52:09.572538 [CA 2] Center 39 (10~68) winsize 59
8292 10:52:09.575854 [CA 3] Center 37 (8~67) winsize 60
8293 10:52:09.579482 [CA 4] Center 38 (8~68) winsize 61
8294 10:52:09.582635 [CA 5] Center 37 (7~67) winsize 61
8295 10:52:09.583204
8296 10:52:09.586025 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8297 10:52:09.586585
8298 10:52:09.592834 [CATrainingPosCal] consider 1 rank data
8299 10:52:09.593383 u2DelayCellTimex100 = 275/100 ps
8300 10:52:09.598836 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8301 10:52:09.602696 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8302 10:52:09.606234 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8303 10:52:09.608911 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8304 10:52:09.612164 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8305 10:52:09.615727 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8306 10:52:09.616324
8307 10:52:09.619175 CA PerBit enable=1, Macro0, CA PI delay=37
8308 10:52:09.619732
8309 10:52:09.622583 [CBTSetCACLKResult] CA Dly = 37
8310 10:52:09.625559 CS Dly: 8 (0~39)
8311 10:52:09.629625 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 10:52:09.632582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 10:52:09.633041 ==
8314 10:52:09.635995 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 10:52:09.641982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 10:52:09.642529 ==
8317 10:52:09.645538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 10:52:09.652410 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 10:52:09.654681 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 10:52:09.661657 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 10:52:09.669451 [CA 0] Center 41 (12~71) winsize 60
8322 10:52:09.672910 [CA 1] Center 41 (12~71) winsize 60
8323 10:52:09.675996 [CA 2] Center 37 (8~67) winsize 60
8324 10:52:09.679049 [CA 3] Center 36 (7~66) winsize 60
8325 10:52:09.682977 [CA 4] Center 37 (7~67) winsize 61
8326 10:52:09.686094 [CA 5] Center 36 (7~66) winsize 60
8327 10:52:09.686652
8328 10:52:09.689350 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 10:52:09.689810
8330 10:52:09.692250 [CATrainingPosCal] consider 2 rank data
8331 10:52:09.696539 u2DelayCellTimex100 = 275/100 ps
8332 10:52:09.702086 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8333 10:52:09.705287 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8334 10:52:09.708663 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
8335 10:52:09.712254 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8336 10:52:09.715329 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8337 10:52:09.718848 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 10:52:09.719360
8339 10:52:09.721814 CA PerBit enable=1, Macro0, CA PI delay=36
8340 10:52:09.722333
8341 10:52:09.725389 [CBTSetCACLKResult] CA Dly = 36
8342 10:52:09.728597 CS Dly: 9 (0~42)
8343 10:52:09.732312 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 10:52:09.735253 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 10:52:09.735780
8346 10:52:09.738514 ----->DramcWriteLeveling(PI) begin...
8347 10:52:09.739191 ==
8348 10:52:09.741869 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 10:52:09.747990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 10:52:09.748631 ==
8351 10:52:09.751336 Write leveling (Byte 0): 25 => 25
8352 10:52:09.755598 Write leveling (Byte 1): 29 => 29
8353 10:52:09.758650 DramcWriteLeveling(PI) end<-----
8354 10:52:09.759217
8355 10:52:09.759689 ==
8356 10:52:09.761650 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 10:52:09.764911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 10:52:09.765371 ==
8359 10:52:09.767897 [Gating] SW mode calibration
8360 10:52:09.774842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 10:52:09.781757 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 10:52:09.784454 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 10:52:09.788101 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 10:52:09.794412 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 10:52:09.797477 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8366 10:52:09.800903 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8367 10:52:09.807623 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 10:52:09.810755 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 10:52:09.814108 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 10:52:09.820688 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 10:52:09.823947 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 10:52:09.827292 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8373 10:52:09.833622 1 5 12 | B1->B0 | 3030 2525 | 0 0 | (1 0) (1 0)
8374 10:52:09.837468 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8375 10:52:09.840515 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 10:52:09.846632 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 10:52:09.849898 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 10:52:09.853270 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 10:52:09.859730 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 10:52:09.863656 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8381 10:52:09.866479 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8382 10:52:09.873360 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8383 10:52:09.876395 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 10:52:09.879396 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 10:52:09.886523 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 10:52:09.890343 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 10:52:09.893598 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 10:52:09.899902 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8389 10:52:09.902870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8390 10:52:09.905819 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 10:52:09.912929 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 10:52:09.916385 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 10:52:09.919272 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 10:52:09.925324 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 10:52:09.928722 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 10:52:09.932213 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 10:52:09.938869 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 10:52:09.942683 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 10:52:09.945295 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 10:52:09.952364 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 10:52:09.955310 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:52:09.958610 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:52:09.964855 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:52:09.968012 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8405 10:52:09.971389 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 10:52:09.978151 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8407 10:52:09.981425 Total UI for P1: 0, mck2ui 16
8408 10:52:09.984881 best dqsien dly found for B0: ( 1, 9, 10)
8409 10:52:09.987876 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 10:52:09.991260 Total UI for P1: 0, mck2ui 16
8411 10:52:09.995009 best dqsien dly found for B1: ( 1, 9, 14)
8412 10:52:09.997754 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8413 10:52:10.001328 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8414 10:52:10.001898
8415 10:52:10.007862 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8416 10:52:10.011406 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8417 10:52:10.011973 [Gating] SW calibration Done
8418 10:52:10.013974 ==
8419 10:52:10.017792 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 10:52:10.021498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 10:52:10.022066 ==
8422 10:52:10.022441 RX Vref Scan: 0
8423 10:52:10.022784
8424 10:52:10.024324 RX Vref 0 -> 0, step: 1
8425 10:52:10.024875
8426 10:52:10.026947 RX Delay 0 -> 252, step: 8
8427 10:52:10.031030 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8428 10:52:10.034028 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8429 10:52:10.041454 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8430 10:52:10.044135 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8431 10:52:10.046766 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8432 10:52:10.050424 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8433 10:52:10.053379 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8434 10:52:10.060284 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8435 10:52:10.064366 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8436 10:52:10.066944 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8437 10:52:10.070137 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8438 10:52:10.073241 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8439 10:52:10.080072 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8440 10:52:10.083537 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8441 10:52:10.086678 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8442 10:52:10.090019 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8443 10:52:10.090586 ==
8444 10:52:10.092987 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 10:52:10.099607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 10:52:10.100196 ==
8447 10:52:10.100574 DQS Delay:
8448 10:52:10.102895 DQS0 = 0, DQS1 = 0
8449 10:52:10.103458 DQM Delay:
8450 10:52:10.107101 DQM0 = 135, DQM1 = 131
8451 10:52:10.107669 DQ Delay:
8452 10:52:10.109363 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8453 10:52:10.112752 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8454 10:52:10.116626 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8455 10:52:10.119740 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8456 10:52:10.120347
8457 10:52:10.120721
8458 10:52:10.121064 ==
8459 10:52:10.122748 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 10:52:10.129686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 10:52:10.130254 ==
8462 10:52:10.130628
8463 10:52:10.130971
8464 10:52:10.131304 TX Vref Scan disable
8465 10:52:10.132484 == TX Byte 0 ==
8466 10:52:10.136842 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8467 10:52:10.143063 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 10:52:10.143841 == TX Byte 1 ==
8469 10:52:10.146101 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8470 10:52:10.152344 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8471 10:52:10.152826 ==
8472 10:52:10.155543 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 10:52:10.159235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 10:52:10.159809 ==
8475 10:52:10.172105
8476 10:52:10.175027 TX Vref early break, caculate TX vref
8477 10:52:10.178491 TX Vref=16, minBit 8, minWin=21, winSum=367
8478 10:52:10.181466 TX Vref=18, minBit 8, minWin=22, winSum=379
8479 10:52:10.184911 TX Vref=20, minBit 8, minWin=22, winSum=386
8480 10:52:10.188009 TX Vref=22, minBit 3, minWin=24, winSum=400
8481 10:52:10.191672 TX Vref=24, minBit 13, minWin=24, winSum=410
8482 10:52:10.198281 TX Vref=26, minBit 3, minWin=25, winSum=415
8483 10:52:10.201350 TX Vref=28, minBit 0, minWin=25, winSum=420
8484 10:52:10.204520 TX Vref=30, minBit 15, minWin=24, winSum=411
8485 10:52:10.207970 TX Vref=32, minBit 0, minWin=25, winSum=406
8486 10:52:10.211792 TX Vref=34, minBit 9, minWin=23, winSum=398
8487 10:52:10.218172 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8488 10:52:10.218738
8489 10:52:10.220842 Final TX Range 0 Vref 28
8490 10:52:10.221307
8491 10:52:10.221672 ==
8492 10:52:10.224456 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 10:52:10.227634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 10:52:10.228142 ==
8495 10:52:10.228519
8496 10:52:10.231192
8497 10:52:10.231648 TX Vref Scan disable
8498 10:52:10.238097 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8499 10:52:10.238664 == TX Byte 0 ==
8500 10:52:10.240704 u2DelayCellOfst[0]=17 cells (5 PI)
8501 10:52:10.244811 u2DelayCellOfst[1]=14 cells (4 PI)
8502 10:52:10.247829 u2DelayCellOfst[2]=0 cells (0 PI)
8503 10:52:10.251263 u2DelayCellOfst[3]=7 cells (2 PI)
8504 10:52:10.254426 u2DelayCellOfst[4]=10 cells (3 PI)
8505 10:52:10.258119 u2DelayCellOfst[5]=17 cells (5 PI)
8506 10:52:10.260894 u2DelayCellOfst[6]=17 cells (5 PI)
8507 10:52:10.264156 u2DelayCellOfst[7]=7 cells (2 PI)
8508 10:52:10.267114 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8509 10:52:10.271029 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8510 10:52:10.273988 == TX Byte 1 ==
8511 10:52:10.276928 u2DelayCellOfst[8]=0 cells (0 PI)
8512 10:52:10.280457 u2DelayCellOfst[9]=7 cells (2 PI)
8513 10:52:10.284144 u2DelayCellOfst[10]=14 cells (4 PI)
8514 10:52:10.287417 u2DelayCellOfst[11]=7 cells (2 PI)
8515 10:52:10.290041 u2DelayCellOfst[12]=17 cells (5 PI)
8516 10:52:10.293475 u2DelayCellOfst[13]=21 cells (6 PI)
8517 10:52:10.296781 u2DelayCellOfst[14]=21 cells (6 PI)
8518 10:52:10.300098 u2DelayCellOfst[15]=17 cells (5 PI)
8519 10:52:10.303105 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8520 10:52:10.306162 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8521 10:52:10.309625 DramC Write-DBI on
8522 10:52:10.310126 ==
8523 10:52:10.312726 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 10:52:10.316390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 10:52:10.316948 ==
8526 10:52:10.317315
8527 10:52:10.317651
8528 10:52:10.320280 TX Vref Scan disable
8529 10:52:10.320832 == TX Byte 0 ==
8530 10:52:10.326657 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8531 10:52:10.327286 == TX Byte 1 ==
8532 10:52:10.332926 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8533 10:52:10.333564 DramC Write-DBI off
8534 10:52:10.333944
8535 10:52:10.334296 [DATLAT]
8536 10:52:10.336572 Freq=1600, CH1 RK0
8537 10:52:10.337036
8538 10:52:10.339553 DATLAT Default: 0xf
8539 10:52:10.340141 0, 0xFFFF, sum = 0
8540 10:52:10.343566 1, 0xFFFF, sum = 0
8541 10:52:10.344202 2, 0xFFFF, sum = 0
8542 10:52:10.346475 3, 0xFFFF, sum = 0
8543 10:52:10.346946 4, 0xFFFF, sum = 0
8544 10:52:10.349701 5, 0xFFFF, sum = 0
8545 10:52:10.350172 6, 0xFFFF, sum = 0
8546 10:52:10.352509 7, 0xFFFF, sum = 0
8547 10:52:10.352981 8, 0xFFFF, sum = 0
8548 10:52:10.356319 9, 0xFFFF, sum = 0
8549 10:52:10.356890 10, 0xFFFF, sum = 0
8550 10:52:10.359142 11, 0xFFFF, sum = 0
8551 10:52:10.359716 12, 0xFFFF, sum = 0
8552 10:52:10.362759 13, 0xFFFF, sum = 0
8553 10:52:10.363331 14, 0x0, sum = 1
8554 10:52:10.365572 15, 0x0, sum = 2
8555 10:52:10.366044 16, 0x0, sum = 3
8556 10:52:10.368990 17, 0x0, sum = 4
8557 10:52:10.369562 best_step = 15
8558 10:52:10.369935
8559 10:52:10.370279 ==
8560 10:52:10.372087 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 10:52:10.379043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 10:52:10.379614 ==
8563 10:52:10.379995 RX Vref Scan: 1
8564 10:52:10.380392
8565 10:52:10.382024 Set Vref Range= 24 -> 127
8566 10:52:10.382488
8567 10:52:10.385174 RX Vref 24 -> 127, step: 1
8568 10:52:10.385638
8569 10:52:10.388734 RX Delay 19 -> 252, step: 4
8570 10:52:10.389299
8571 10:52:10.392200 Set Vref, RX VrefLevel [Byte0]: 24
8572 10:52:10.395273 [Byte1]: 24
8573 10:52:10.395742
8574 10:52:10.398816 Set Vref, RX VrefLevel [Byte0]: 25
8575 10:52:10.401731 [Byte1]: 25
8576 10:52:10.402157
8577 10:52:10.404988 Set Vref, RX VrefLevel [Byte0]: 26
8578 10:52:10.408871 [Byte1]: 26
8579 10:52:10.411617
8580 10:52:10.412101 Set Vref, RX VrefLevel [Byte0]: 27
8581 10:52:10.414899 [Byte1]: 27
8582 10:52:10.419642
8583 10:52:10.420090 Set Vref, RX VrefLevel [Byte0]: 28
8584 10:52:10.423069 [Byte1]: 28
8585 10:52:10.426640
8586 10:52:10.427068 Set Vref, RX VrefLevel [Byte0]: 29
8587 10:52:10.429902 [Byte1]: 29
8588 10:52:10.434743
8589 10:52:10.435165 Set Vref, RX VrefLevel [Byte0]: 30
8590 10:52:10.438285 [Byte1]: 30
8591 10:52:10.442197
8592 10:52:10.442721 Set Vref, RX VrefLevel [Byte0]: 31
8593 10:52:10.445446 [Byte1]: 31
8594 10:52:10.449617
8595 10:52:10.450145 Set Vref, RX VrefLevel [Byte0]: 32
8596 10:52:10.452646 [Byte1]: 32
8597 10:52:10.457119
8598 10:52:10.457646 Set Vref, RX VrefLevel [Byte0]: 33
8599 10:52:10.460289 [Byte1]: 33
8600 10:52:10.465192
8601 10:52:10.465763 Set Vref, RX VrefLevel [Byte0]: 34
8602 10:52:10.468147 [Byte1]: 34
8603 10:52:10.472470
8604 10:52:10.473035 Set Vref, RX VrefLevel [Byte0]: 35
8605 10:52:10.475846 [Byte1]: 35
8606 10:52:10.479822
8607 10:52:10.480425 Set Vref, RX VrefLevel [Byte0]: 36
8608 10:52:10.483318 [Byte1]: 36
8609 10:52:10.487644
8610 10:52:10.490858 Set Vref, RX VrefLevel [Byte0]: 37
8611 10:52:10.491427 [Byte1]: 37
8612 10:52:10.495405
8613 10:52:10.495875 Set Vref, RX VrefLevel [Byte0]: 38
8614 10:52:10.498256 [Byte1]: 38
8615 10:52:10.502696
8616 10:52:10.503263 Set Vref, RX VrefLevel [Byte0]: 39
8617 10:52:10.505564 [Byte1]: 39
8618 10:52:10.510334
8619 10:52:10.510753 Set Vref, RX VrefLevel [Byte0]: 40
8620 10:52:10.513076 [Byte1]: 40
8621 10:52:10.517695
8622 10:52:10.518119 Set Vref, RX VrefLevel [Byte0]: 41
8623 10:52:10.521622 [Byte1]: 41
8624 10:52:10.525232
8625 10:52:10.525657 Set Vref, RX VrefLevel [Byte0]: 42
8626 10:52:10.528365 [Byte1]: 42
8627 10:52:10.532783
8628 10:52:10.533208 Set Vref, RX VrefLevel [Byte0]: 43
8629 10:52:10.535984 [Byte1]: 43
8630 10:52:10.540261
8631 10:52:10.540783 Set Vref, RX VrefLevel [Byte0]: 44
8632 10:52:10.544026 [Byte1]: 44
8633 10:52:10.548610
8634 10:52:10.549135 Set Vref, RX VrefLevel [Byte0]: 45
8635 10:52:10.551197 [Byte1]: 45
8636 10:52:10.555482
8637 10:52:10.556011 Set Vref, RX VrefLevel [Byte0]: 46
8638 10:52:10.559191 [Byte1]: 46
8639 10:52:10.563388
8640 10:52:10.563914 Set Vref, RX VrefLevel [Byte0]: 47
8641 10:52:10.566446 [Byte1]: 47
8642 10:52:10.570761
8643 10:52:10.571287 Set Vref, RX VrefLevel [Byte0]: 48
8644 10:52:10.573972 [Byte1]: 48
8645 10:52:10.578730
8646 10:52:10.579256 Set Vref, RX VrefLevel [Byte0]: 49
8647 10:52:10.582208 [Byte1]: 49
8648 10:52:10.585891
8649 10:52:10.586417 Set Vref, RX VrefLevel [Byte0]: 50
8650 10:52:10.589781 [Byte1]: 50
8651 10:52:10.593554
8652 10:52:10.594084 Set Vref, RX VrefLevel [Byte0]: 51
8653 10:52:10.596855 [Byte1]: 51
8654 10:52:10.600729
8655 10:52:10.601158 Set Vref, RX VrefLevel [Byte0]: 52
8656 10:52:10.603973 [Byte1]: 52
8657 10:52:10.608522
8658 10:52:10.609069 Set Vref, RX VrefLevel [Byte0]: 53
8659 10:52:10.612013 [Byte1]: 53
8660 10:52:10.616314
8661 10:52:10.616827 Set Vref, RX VrefLevel [Byte0]: 54
8662 10:52:10.618983 [Byte1]: 54
8663 10:52:10.623860
8664 10:52:10.624468 Set Vref, RX VrefLevel [Byte0]: 55
8665 10:52:10.626943 [Byte1]: 55
8666 10:52:10.631097
8667 10:52:10.631551 Set Vref, RX VrefLevel [Byte0]: 56
8668 10:52:10.634396 [Byte1]: 56
8669 10:52:10.639752
8670 10:52:10.640323 Set Vref, RX VrefLevel [Byte0]: 57
8671 10:52:10.642862 [Byte1]: 57
8672 10:52:10.646436
8673 10:52:10.647020 Set Vref, RX VrefLevel [Byte0]: 58
8674 10:52:10.649521 [Byte1]: 58
8675 10:52:10.654158
8676 10:52:10.654676 Set Vref, RX VrefLevel [Byte0]: 59
8677 10:52:10.658021 [Byte1]: 59
8678 10:52:10.661603
8679 10:52:10.662196 Set Vref, RX VrefLevel [Byte0]: 60
8680 10:52:10.664873 [Byte1]: 60
8681 10:52:10.669135
8682 10:52:10.669693 Set Vref, RX VrefLevel [Byte0]: 61
8683 10:52:10.672485 [Byte1]: 61
8684 10:52:10.676866
8685 10:52:10.677375 Set Vref, RX VrefLevel [Byte0]: 62
8686 10:52:10.680394 [Byte1]: 62
8687 10:52:10.684068
8688 10:52:10.684563 Set Vref, RX VrefLevel [Byte0]: 63
8689 10:52:10.687738 [Byte1]: 63
8690 10:52:10.692543
8691 10:52:10.693103 Set Vref, RX VrefLevel [Byte0]: 64
8692 10:52:10.695034 [Byte1]: 64
8693 10:52:10.699357
8694 10:52:10.699820 Set Vref, RX VrefLevel [Byte0]: 65
8695 10:52:10.702754 [Byte1]: 65
8696 10:52:10.707226
8697 10:52:10.707792 Set Vref, RX VrefLevel [Byte0]: 66
8698 10:52:10.710673 [Byte1]: 66
8699 10:52:10.714912
8700 10:52:10.715472 Set Vref, RX VrefLevel [Byte0]: 67
8701 10:52:10.717529 [Byte1]: 67
8702 10:52:10.722259
8703 10:52:10.722822 Set Vref, RX VrefLevel [Byte0]: 68
8704 10:52:10.725384 [Byte1]: 68
8705 10:52:10.729669
8706 10:52:10.730090 Set Vref, RX VrefLevel [Byte0]: 69
8707 10:52:10.732627 [Byte1]: 69
8708 10:52:10.737502
8709 10:52:10.738024 Set Vref, RX VrefLevel [Byte0]: 70
8710 10:52:10.740366 [Byte1]: 70
8711 10:52:10.744964
8712 10:52:10.745383 Set Vref, RX VrefLevel [Byte0]: 71
8713 10:52:10.747833 [Byte1]: 71
8714 10:52:10.752227
8715 10:52:10.752643 Final RX Vref Byte 0 = 56 to rank0
8716 10:52:10.756368 Final RX Vref Byte 1 = 62 to rank0
8717 10:52:10.759961 Final RX Vref Byte 0 = 56 to rank1
8718 10:52:10.762393 Final RX Vref Byte 1 = 62 to rank1==
8719 10:52:10.765460 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 10:52:10.772354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 10:52:10.772882 ==
8722 10:52:10.773225 DQS Delay:
8723 10:52:10.775900 DQS0 = 0, DQS1 = 0
8724 10:52:10.776459 DQM Delay:
8725 10:52:10.776802 DQM0 = 133, DQM1 = 130
8726 10:52:10.779005 DQ Delay:
8727 10:52:10.781735 DQ0 =140, DQ1 =130, DQ2 =120, DQ3 =132
8728 10:52:10.785289 DQ4 =126, DQ5 =144, DQ6 =146, DQ7 =128
8729 10:52:10.788463 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8730 10:52:10.792261 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8731 10:52:10.792786
8732 10:52:10.793128
8733 10:52:10.793444
8734 10:52:10.796215 [DramC_TX_OE_Calibration] TA2
8735 10:52:10.798809 Original DQ_B0 (3 6) =30, OEN = 27
8736 10:52:10.801696 Original DQ_B1 (3 6) =30, OEN = 27
8737 10:52:10.805366 24, 0x0, End_B0=24 End_B1=24
8738 10:52:10.808528 25, 0x0, End_B0=25 End_B1=25
8739 10:52:10.809047 26, 0x0, End_B0=26 End_B1=26
8740 10:52:10.811927 27, 0x0, End_B0=27 End_B1=27
8741 10:52:10.814851 28, 0x0, End_B0=28 End_B1=28
8742 10:52:10.818503 29, 0x0, End_B0=29 End_B1=29
8743 10:52:10.819070 30, 0x0, End_B0=30 End_B1=30
8744 10:52:10.821874 31, 0x4141, End_B0=30 End_B1=30
8745 10:52:10.824821 Byte0 end_step=30 best_step=27
8746 10:52:10.828363 Byte1 end_step=30 best_step=27
8747 10:52:10.831406 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 10:52:10.834623 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 10:52:10.835085
8750 10:52:10.835451
8751 10:52:10.841238 [DQSOSCAuto] RK0, (LSB)MR18= 0xb15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8752 10:52:10.844482 CH1 RK0: MR19=303, MR18=B15
8753 10:52:10.851075 CH1_RK0: MR19=0x303, MR18=0xB15, DQSOSC=399, MR23=63, INC=23, DEC=15
8754 10:52:10.851494
8755 10:52:10.854234 ----->DramcWriteLeveling(PI) begin...
8756 10:52:10.854887 ==
8757 10:52:10.857349 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 10:52:10.861104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 10:52:10.861522 ==
8760 10:52:10.864778 Write leveling (Byte 0): 24 => 24
8761 10:52:10.867760 Write leveling (Byte 1): 25 => 25
8762 10:52:10.870953 DramcWriteLeveling(PI) end<-----
8763 10:52:10.871370
8764 10:52:10.871699 ==
8765 10:52:10.874729 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 10:52:10.877506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 10:52:10.880859 ==
8768 10:52:10.881281 [Gating] SW mode calibration
8769 10:52:10.890923 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 10:52:10.894239 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 10:52:10.897464 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 10:52:10.903877 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 10:52:10.907736 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8774 10:52:10.910703 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
8775 10:52:10.917285 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8776 10:52:10.920067 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 10:52:10.923648 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 10:52:10.930084 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 10:52:10.933777 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 10:52:10.936765 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8781 10:52:10.943734 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8782 10:52:10.946591 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
8783 10:52:10.949766 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 10:52:10.956297 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 10:52:10.960093 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 10:52:10.962866 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 10:52:10.970120 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 10:52:10.973533 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8789 10:52:10.976516 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8790 10:52:10.982714 1 6 12 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
8791 10:52:10.986902 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 10:52:10.989550 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 10:52:10.996273 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 10:52:10.999640 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 10:52:11.002602 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 10:52:11.009168 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 10:52:11.012231 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8798 10:52:11.015922 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8799 10:52:11.022462 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 10:52:11.026291 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:52:11.028713 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:52:11.035607 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:52:11.038931 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 10:52:11.042359 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 10:52:11.049472 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 10:52:11.051886 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 10:52:11.055458 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 10:52:11.061898 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 10:52:11.065669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 10:52:11.068972 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:52:11.075749 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:52:11.078289 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 10:52:11.081785 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 10:52:11.089231 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 10:52:11.091639 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 10:52:11.095227 Total UI for P1: 0, mck2ui 16
8817 10:52:11.098962 best dqsien dly found for B0: ( 1, 9, 8)
8818 10:52:11.101754 Total UI for P1: 0, mck2ui 16
8819 10:52:11.104525 best dqsien dly found for B1: ( 1, 9, 12)
8820 10:52:11.108315 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8821 10:52:11.111847 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8822 10:52:11.112433
8823 10:52:11.114731 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8824 10:52:11.120976 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8825 10:52:11.121491 [Gating] SW calibration Done
8826 10:52:11.121832 ==
8827 10:52:11.124403 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 10:52:11.131838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 10:52:11.132465 ==
8830 10:52:11.132836 RX Vref Scan: 0
8831 10:52:11.133178
8832 10:52:11.134510 RX Vref 0 -> 0, step: 1
8833 10:52:11.134998
8834 10:52:11.137839 RX Delay 0 -> 252, step: 8
8835 10:52:11.140719 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8836 10:52:11.144106 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8837 10:52:11.147397 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8838 10:52:11.154577 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8839 10:52:11.157240 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8840 10:52:11.160909 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8841 10:52:11.163549 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8842 10:52:11.167610 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8843 10:52:11.174803 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8844 10:52:11.177368 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8845 10:52:11.180363 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 10:52:11.184023 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8847 10:52:11.189858 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8848 10:52:11.193468 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 10:52:11.196670 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8850 10:52:11.200363 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8851 10:52:11.200921 ==
8852 10:52:11.203849 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 10:52:11.210226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 10:52:11.210790 ==
8855 10:52:11.211162 DQS Delay:
8856 10:52:11.211507 DQS0 = 0, DQS1 = 0
8857 10:52:11.213324 DQM Delay:
8858 10:52:11.213882 DQM0 = 135, DQM1 = 129
8859 10:52:11.216781 DQ Delay:
8860 10:52:11.219870 DQ0 =135, DQ1 =135, DQ2 =123, DQ3 =135
8861 10:52:11.223452 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8862 10:52:11.226362 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8863 10:52:11.229586 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8864 10:52:11.230142
8865 10:52:11.230510
8866 10:52:11.230851 ==
8867 10:52:11.232941 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 10:52:11.239438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 10:52:11.239995 ==
8870 10:52:11.240422
8871 10:52:11.240770
8872 10:52:11.241099 TX Vref Scan disable
8873 10:52:11.242514 == TX Byte 0 ==
8874 10:52:11.246086 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8875 10:52:11.252609 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8876 10:52:11.253030 == TX Byte 1 ==
8877 10:52:11.256121 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8878 10:52:11.262119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8879 10:52:11.262628 ==
8880 10:52:11.266173 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:52:11.268933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:52:11.269402 ==
8883 10:52:11.282685
8884 10:52:11.285695 TX Vref early break, caculate TX vref
8885 10:52:11.288833 TX Vref=16, minBit 9, minWin=22, winSum=381
8886 10:52:11.292525 TX Vref=18, minBit 9, minWin=22, winSum=390
8887 10:52:11.295574 TX Vref=20, minBit 9, minWin=23, winSum=398
8888 10:52:11.299224 TX Vref=22, minBit 9, minWin=23, winSum=405
8889 10:52:11.302233 TX Vref=24, minBit 9, minWin=24, winSum=415
8890 10:52:11.308963 TX Vref=26, minBit 15, minWin=25, winSum=422
8891 10:52:11.312316 TX Vref=28, minBit 9, minWin=25, winSum=427
8892 10:52:11.315488 TX Vref=30, minBit 9, minWin=25, winSum=422
8893 10:52:11.318982 TX Vref=32, minBit 0, minWin=25, winSum=416
8894 10:52:11.322474 TX Vref=34, minBit 8, minWin=24, winSum=408
8895 10:52:11.328534 TX Vref=36, minBit 9, minWin=23, winSum=395
8896 10:52:11.331856 [TxChooseVref] Worse bit 9, Min win 25, Win sum 427, Final Vref 28
8897 10:52:11.332548
8898 10:52:11.335102 Final TX Range 0 Vref 28
8899 10:52:11.335560
8900 10:52:11.335921 ==
8901 10:52:11.338030 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 10:52:11.342028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 10:52:11.344721 ==
8904 10:52:11.345271
8905 10:52:11.345635
8906 10:52:11.345974 TX Vref Scan disable
8907 10:52:11.351646 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8908 10:52:11.352239 == TX Byte 0 ==
8909 10:52:11.355408 u2DelayCellOfst[0]=14 cells (4 PI)
8910 10:52:11.358479 u2DelayCellOfst[1]=10 cells (3 PI)
8911 10:52:11.361578 u2DelayCellOfst[2]=0 cells (0 PI)
8912 10:52:11.365715 u2DelayCellOfst[3]=7 cells (2 PI)
8913 10:52:11.368538 u2DelayCellOfst[4]=7 cells (2 PI)
8914 10:52:11.371449 u2DelayCellOfst[5]=17 cells (5 PI)
8915 10:52:11.374546 u2DelayCellOfst[6]=17 cells (5 PI)
8916 10:52:11.378199 u2DelayCellOfst[7]=7 cells (2 PI)
8917 10:52:11.381722 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8918 10:52:11.384985 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8919 10:52:11.387964 == TX Byte 1 ==
8920 10:52:11.391425 u2DelayCellOfst[8]=0 cells (0 PI)
8921 10:52:11.394793 u2DelayCellOfst[9]=3 cells (1 PI)
8922 10:52:11.397983 u2DelayCellOfst[10]=10 cells (3 PI)
8923 10:52:11.401291 u2DelayCellOfst[11]=3 cells (1 PI)
8924 10:52:11.404255 u2DelayCellOfst[12]=14 cells (4 PI)
8925 10:52:11.408208 u2DelayCellOfst[13]=17 cells (5 PI)
8926 10:52:11.410784 u2DelayCellOfst[14]=17 cells (5 PI)
8927 10:52:11.411243 u2DelayCellOfst[15]=17 cells (5 PI)
8928 10:52:11.418277 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8929 10:52:11.421950 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8930 10:52:11.424218 DramC Write-DBI on
8931 10:52:11.424775 ==
8932 10:52:11.427911 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 10:52:11.430622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 10:52:11.431094 ==
8935 10:52:11.431462
8936 10:52:11.431804
8937 10:52:11.434333 TX Vref Scan disable
8938 10:52:11.434793 == TX Byte 0 ==
8939 10:52:11.440321 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8940 10:52:11.440873 == TX Byte 1 ==
8941 10:52:11.443983 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8942 10:52:11.447231 DramC Write-DBI off
8943 10:52:11.447746
8944 10:52:11.448120 [DATLAT]
8945 10:52:11.450519 Freq=1600, CH1 RK1
8946 10:52:11.451048
8947 10:52:11.451385 DATLAT Default: 0xf
8948 10:52:11.453826 0, 0xFFFF, sum = 0
8949 10:52:11.457766 1, 0xFFFF, sum = 0
8950 10:52:11.458200 2, 0xFFFF, sum = 0
8951 10:52:11.460428 3, 0xFFFF, sum = 0
8952 10:52:11.460902 4, 0xFFFF, sum = 0
8953 10:52:11.463628 5, 0xFFFF, sum = 0
8954 10:52:11.464230 6, 0xFFFF, sum = 0
8955 10:52:11.466850 7, 0xFFFF, sum = 0
8956 10:52:11.467278 8, 0xFFFF, sum = 0
8957 10:52:11.470627 9, 0xFFFF, sum = 0
8958 10:52:11.471167 10, 0xFFFF, sum = 0
8959 10:52:11.473388 11, 0xFFFF, sum = 0
8960 10:52:11.473820 12, 0xFFFF, sum = 0
8961 10:52:11.477261 13, 0xFFFF, sum = 0
8962 10:52:11.477804 14, 0x0, sum = 1
8963 10:52:11.480555 15, 0x0, sum = 2
8964 10:52:11.481090 16, 0x0, sum = 3
8965 10:52:11.483446 17, 0x0, sum = 4
8966 10:52:11.483889 best_step = 15
8967 10:52:11.484281
8968 10:52:11.484605 ==
8969 10:52:11.486996 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 10:52:11.493347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 10:52:11.493892 ==
8972 10:52:11.494246 RX Vref Scan: 0
8973 10:52:11.494558
8974 10:52:11.496261 RX Vref 0 -> 0, step: 1
8975 10:52:11.496684
8976 10:52:11.499845 RX Delay 11 -> 252, step: 4
8977 10:52:11.504878 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8978 10:52:11.506141 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8979 10:52:11.513117 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8980 10:52:11.516466 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8981 10:52:11.519978 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8982 10:52:11.523651 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8983 10:52:11.526415 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8984 10:52:11.532895 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8985 10:52:11.535842 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8986 10:52:11.539184 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8987 10:52:11.542641 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8988 10:52:11.546137 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8989 10:52:11.552673 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8990 10:52:11.556107 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8991 10:52:11.559358 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8992 10:52:11.562316 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8993 10:52:11.562841 ==
8994 10:52:11.565725 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 10:52:11.572154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 10:52:11.572661 ==
8997 10:52:11.573004 DQS Delay:
8998 10:52:11.574979 DQS0 = 0, DQS1 = 0
8999 10:52:11.575399 DQM Delay:
9000 10:52:11.578637 DQM0 = 133, DQM1 = 128
9001 10:52:11.579169 DQ Delay:
9002 10:52:11.582380 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =128
9003 10:52:11.584979 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
9004 10:52:11.588740 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9005 10:52:11.591576 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9006 10:52:11.592141
9007 10:52:11.592494
9008 10:52:11.592808
9009 10:52:11.595910 [DramC_TX_OE_Calibration] TA2
9010 10:52:11.598607 Original DQ_B0 (3 6) =30, OEN = 27
9011 10:52:11.601251 Original DQ_B1 (3 6) =30, OEN = 27
9012 10:52:11.605146 24, 0x0, End_B0=24 End_B1=24
9013 10:52:11.608269 25, 0x0, End_B0=25 End_B1=25
9014 10:52:11.608811 26, 0x0, End_B0=26 End_B1=26
9015 10:52:11.611611 27, 0x0, End_B0=27 End_B1=27
9016 10:52:11.614890 28, 0x0, End_B0=28 End_B1=28
9017 10:52:11.618207 29, 0x0, End_B0=29 End_B1=29
9018 10:52:11.621319 30, 0x0, End_B0=30 End_B1=30
9019 10:52:11.621870 31, 0x4141, End_B0=30 End_B1=30
9020 10:52:11.624736 Byte0 end_step=30 best_step=27
9021 10:52:11.627731 Byte1 end_step=30 best_step=27
9022 10:52:11.631526 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 10:52:11.634329 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 10:52:11.634834
9025 10:52:11.635178
9026 10:52:11.641623 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9027 10:52:11.644249 CH1 RK1: MR19=303, MR18=D1B
9028 10:52:11.651002 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9029 10:52:11.654564 [RxdqsGatingPostProcess] freq 1600
9030 10:52:11.660936 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 10:52:11.664605 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 10:52:11.665073 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 10:52:11.667791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 10:52:11.670877 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 10:52:11.674338 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 10:52:11.677576 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 10:52:11.680955 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 10:52:11.684848 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 10:52:11.687060 Pre-setting of DQS Precalculation
9040 10:52:11.693807 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 10:52:11.700779 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 10:52:11.706865 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 10:52:11.707436
9044 10:52:11.707809
9045 10:52:11.709823 [Calibration Summary] 3200 Mbps
9046 10:52:11.710289 CH 0, Rank 0
9047 10:52:11.714527 SW Impedance : PASS
9048 10:52:11.716520 DUTY Scan : NO K
9049 10:52:11.716985 ZQ Calibration : PASS
9050 10:52:11.720078 Jitter Meter : NO K
9051 10:52:11.723757 CBT Training : PASS
9052 10:52:11.724365 Write leveling : PASS
9053 10:52:11.726584 RX DQS gating : PASS
9054 10:52:11.729990 RX DQ/DQS(RDDQC) : PASS
9055 10:52:11.730555 TX DQ/DQS : PASS
9056 10:52:11.733102 RX DATLAT : PASS
9057 10:52:11.733680 RX DQ/DQS(Engine): PASS
9058 10:52:11.736465 TX OE : PASS
9059 10:52:11.736933 All Pass.
9060 10:52:11.737307
9061 10:52:11.739592 CH 0, Rank 1
9062 10:52:11.743060 SW Impedance : PASS
9063 10:52:11.743626 DUTY Scan : NO K
9064 10:52:11.746802 ZQ Calibration : PASS
9065 10:52:11.747371 Jitter Meter : NO K
9066 10:52:11.749633 CBT Training : PASS
9067 10:52:11.753109 Write leveling : PASS
9068 10:52:11.753554 RX DQS gating : PASS
9069 10:52:11.756334 RX DQ/DQS(RDDQC) : PASS
9070 10:52:11.760617 TX DQ/DQS : PASS
9071 10:52:11.761143 RX DATLAT : PASS
9072 10:52:11.762498 RX DQ/DQS(Engine): PASS
9073 10:52:11.766853 TX OE : PASS
9074 10:52:11.767384 All Pass.
9075 10:52:11.767723
9076 10:52:11.768056 CH 1, Rank 0
9077 10:52:11.769240 SW Impedance : PASS
9078 10:52:11.772459 DUTY Scan : NO K
9079 10:52:11.772879 ZQ Calibration : PASS
9080 10:52:11.775749 Jitter Meter : NO K
9081 10:52:11.779722 CBT Training : PASS
9082 10:52:11.780282 Write leveling : PASS
9083 10:52:11.782375 RX DQS gating : PASS
9084 10:52:11.785948 RX DQ/DQS(RDDQC) : PASS
9085 10:52:11.786473 TX DQ/DQS : PASS
9086 10:52:11.789129 RX DATLAT : PASS
9087 10:52:11.792382 RX DQ/DQS(Engine): PASS
9088 10:52:11.792908 TX OE : PASS
9089 10:52:11.795324 All Pass.
9090 10:52:11.795826
9091 10:52:11.796360 CH 1, Rank 1
9092 10:52:11.799272 SW Impedance : PASS
9093 10:52:11.799807 DUTY Scan : NO K
9094 10:52:11.803040 ZQ Calibration : PASS
9095 10:52:11.805548 Jitter Meter : NO K
9096 10:52:11.806079 CBT Training : PASS
9097 10:52:11.808514 Write leveling : PASS
9098 10:52:11.812222 RX DQS gating : PASS
9099 10:52:11.812642 RX DQ/DQS(RDDQC) : PASS
9100 10:52:11.815545 TX DQ/DQS : PASS
9101 10:52:11.818477 RX DATLAT : PASS
9102 10:52:11.818903 RX DQ/DQS(Engine): PASS
9103 10:52:11.822065 TX OE : PASS
9104 10:52:11.822491 All Pass.
9105 10:52:11.822828
9106 10:52:11.824877 DramC Write-DBI on
9107 10:52:11.828717 PER_BANK_REFRESH: Hybrid Mode
9108 10:52:11.829147 TX_TRACKING: ON
9109 10:52:11.838373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 10:52:11.844797 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 10:52:11.851764 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 10:52:11.854843 [FAST_K] Save calibration result to emmc
9113 10:52:11.858062 sync common calibartion params.
9114 10:52:11.861201 sync cbt_mode0:1, 1:1
9115 10:52:11.865256 dram_init: ddr_geometry: 2
9116 10:52:11.865811 dram_init: ddr_geometry: 2
9117 10:52:11.868366 dram_init: ddr_geometry: 2
9118 10:52:11.871094 0:dram_rank_size:100000000
9119 10:52:11.874893 1:dram_rank_size:100000000
9120 10:52:11.878379 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 10:52:11.881131 DFS_SHUFFLE_HW_MODE: ON
9122 10:52:11.884171 dramc_set_vcore_voltage set vcore to 725000
9123 10:52:11.887966 Read voltage for 1600, 0
9124 10:52:11.888552 Vio18 = 0
9125 10:52:11.891123 Vcore = 725000
9126 10:52:11.891679 Vdram = 0
9127 10:52:11.892102 Vddq = 0
9128 10:52:11.892463 Vmddr = 0
9129 10:52:11.894424 switch to 3200 Mbps bootup
9130 10:52:11.897363 [DramcRunTimeConfig]
9131 10:52:11.897946 PHYPLL
9132 10:52:11.900704 DPM_CONTROL_AFTERK: ON
9133 10:52:11.901274 PER_BANK_REFRESH: ON
9134 10:52:11.903710 REFRESH_OVERHEAD_REDUCTION: ON
9135 10:52:11.909677 CMD_PICG_NEW_MODE: OFF
9136 10:52:11.910286 XRTWTW_NEW_MODE: ON
9137 10:52:11.911004 XRTRTR_NEW_MODE: ON
9138 10:52:11.911382 TX_TRACKING: ON
9139 10:52:11.913547 RDSEL_TRACKING: OFF
9140 10:52:11.916967 DQS Precalculation for DVFS: ON
9141 10:52:11.917523 RX_TRACKING: OFF
9142 10:52:11.920414 HW_GATING DBG: ON
9143 10:52:11.921084 ZQCS_ENABLE_LP4: ON
9144 10:52:11.923808 RX_PICG_NEW_MODE: ON
9145 10:52:11.924513 TX_PICG_NEW_MODE: ON
9146 10:52:11.926975 ENABLE_RX_DCM_DPHY: ON
9147 10:52:11.929956 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 10:52:11.933640 DUMMY_READ_FOR_TRACKING: OFF
9149 10:52:11.934215 !!! SPM_CONTROL_AFTERK: OFF
9150 10:52:11.936736 !!! SPM could not control APHY
9151 10:52:11.939966 IMPEDANCE_TRACKING: ON
9152 10:52:11.940574 TEMP_SENSOR: ON
9153 10:52:11.943868 HW_SAVE_FOR_SR: OFF
9154 10:52:11.946932 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 10:52:11.950268 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 10:52:11.950824 Read ODT Tracking: ON
9157 10:52:11.953407 Refresh Rate DeBounce: ON
9158 10:52:11.956967 DFS_NO_QUEUE_FLUSH: ON
9159 10:52:11.960260 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 10:52:11.960814 ENABLE_DFS_RUNTIME_MRW: OFF
9161 10:52:11.963423 DDR_RESERVE_NEW_MODE: ON
9162 10:52:11.967074 MR_CBT_SWITCH_FREQ: ON
9163 10:52:11.967628 =========================
9164 10:52:11.987354 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 10:52:11.989981 dram_init: ddr_geometry: 2
9166 10:52:12.008596 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 10:52:12.011717 dram_init: dram init end (result: 0)
9168 10:52:12.018429 DRAM-K: Full calibration passed in 24450 msecs
9169 10:52:12.021937 MRC: failed to locate region type 0.
9170 10:52:12.022496 DRAM rank0 size:0x100000000,
9171 10:52:12.024715 DRAM rank1 size=0x100000000
9172 10:52:12.035102 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 10:52:12.041177 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 10:52:12.047954 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 10:52:12.057711 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 10:52:12.058268 DRAM rank0 size:0x100000000,
9177 10:52:12.061070 DRAM rank1 size=0x100000000
9178 10:52:12.061531 CBMEM:
9179 10:52:12.064401 IMD: root @ 0xfffff000 254 entries.
9180 10:52:12.068125 IMD: root @ 0xffffec00 62 entries.
9181 10:52:12.071073 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 10:52:12.077868 WARNING: RO_VPD is uninitialized or empty.
9183 10:52:12.081331 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 10:52:12.088499 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 10:52:12.101198 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9186 10:52:12.113859 BS: romstage times (exec / console): total (unknown) / 23979 ms
9187 10:52:12.114418
9188 10:52:12.114781
9189 10:52:12.122941 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 10:52:12.126327 ARM64: Exception handlers installed.
9191 10:52:12.129298 ARM64: Testing exception
9192 10:52:12.132058 ARM64: Done test exception
9193 10:52:12.132669 Enumerating buses...
9194 10:52:12.136328 Show all devs... Before device enumeration.
9195 10:52:12.138644 Root Device: enabled 1
9196 10:52:12.142043 CPU_CLUSTER: 0: enabled 1
9197 10:52:12.142498 CPU: 00: enabled 1
9198 10:52:12.145489 Compare with tree...
9199 10:52:12.145945 Root Device: enabled 1
9200 10:52:12.148907 CPU_CLUSTER: 0: enabled 1
9201 10:52:12.152212 CPU: 00: enabled 1
9202 10:52:12.152630 Root Device scanning...
9203 10:52:12.155117 scan_static_bus for Root Device
9204 10:52:12.158775 CPU_CLUSTER: 0 enabled
9205 10:52:12.162065 scan_static_bus for Root Device done
9206 10:52:12.164730 scan_bus: bus Root Device finished in 8 msecs
9207 10:52:12.165146 done
9208 10:52:12.171394 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 10:52:12.175046 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 10:52:12.181448 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 10:52:12.188656 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 10:52:12.189217 Allocating resources...
9213 10:52:12.191834 Reading resources...
9214 10:52:12.195275 Root Device read_resources bus 0 link: 0
9215 10:52:12.198122 DRAM rank0 size:0x100000000,
9216 10:52:12.198680 DRAM rank1 size=0x100000000
9217 10:52:12.204742 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 10:52:12.205296 CPU: 00 missing read_resources
9219 10:52:12.211454 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 10:52:12.215031 Root Device read_resources bus 0 link: 0 done
9221 10:52:12.217607 Done reading resources.
9222 10:52:12.221392 Show resources in subtree (Root Device)...After reading.
9223 10:52:12.224215 Root Device child on link 0 CPU_CLUSTER: 0
9224 10:52:12.230935 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 10:52:12.237243 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 10:52:12.237813 CPU: 00
9227 10:52:12.243900 Root Device assign_resources, bus 0 link: 0
9228 10:52:12.247472 CPU_CLUSTER: 0 missing set_resources
9229 10:52:12.250551 Root Device assign_resources, bus 0 link: 0 done
9230 10:52:12.253585 Done setting resources.
9231 10:52:12.257371 Show resources in subtree (Root Device)...After assigning values.
9232 10:52:12.263506 Root Device child on link 0 CPU_CLUSTER: 0
9233 10:52:12.266941 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 10:52:12.273950 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 10:52:12.276562 CPU: 00
9236 10:52:12.277022 Done allocating resources.
9237 10:52:12.283335 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 10:52:12.287115 Enabling resources...
9239 10:52:12.287679 done.
9240 10:52:12.289991 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 10:52:12.293391 Initializing devices...
9242 10:52:12.293951 Root Device init
9243 10:52:12.297462 init hardware done!
9244 10:52:12.299786 0x00000018: ctrlr->caps
9245 10:52:12.300393 52.000 MHz: ctrlr->f_max
9246 10:52:12.303304 0.400 MHz: ctrlr->f_min
9247 10:52:12.306523 0x40ff8080: ctrlr->voltages
9248 10:52:12.307101 sclk: 390625
9249 10:52:12.307471 Bus Width = 1
9250 10:52:12.309979 sclk: 390625
9251 10:52:12.310436 Bus Width = 1
9252 10:52:12.312998 Early init status = 3
9253 10:52:12.317601 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 10:52:12.322105 in-header: 03 fc 00 00 01 00 00 00
9255 10:52:12.324790 in-data: 00
9256 10:52:12.327758 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 10:52:12.333613 in-header: 03 fd 00 00 00 00 00 00
9258 10:52:12.336939 in-data:
9259 10:52:12.340340 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 10:52:12.344610 in-header: 03 fc 00 00 01 00 00 00
9261 10:52:12.347880 in-data: 00
9262 10:52:12.350737 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 10:52:12.356307 in-header: 03 fd 00 00 00 00 00 00
9264 10:52:12.359731 in-data:
9265 10:52:12.363572 [SSUSB] Setting up USB HOST controller...
9266 10:52:12.366485 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 10:52:12.370127 [SSUSB] phy power-on done.
9268 10:52:12.373189 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 10:52:12.380528 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 10:52:12.382913 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 10:52:12.390093 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 10:52:12.396951 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9273 10:52:12.403501 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 10:52:12.409646 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 10:52:12.416771 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9276 10:52:12.419480 SPM: binary array size = 0x9dc
9277 10:52:12.422858 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 10:52:12.429513 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 10:52:12.436248 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 10:52:12.442179 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 10:52:12.446060 configure_display: Starting display init
9282 10:52:12.479972 anx7625_power_on_init: Init interface.
9283 10:52:12.483750 anx7625_disable_pd_protocol: Disabled PD feature.
9284 10:52:12.486293 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 10:52:12.514111 anx7625_start_dp_work: Secure OCM version=00
9286 10:52:12.517663 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 10:52:12.532612 sp_tx_get_edid_block: EDID Block = 1
9288 10:52:12.635723 Extracted contents:
9289 10:52:12.638039 header: 00 ff ff ff ff ff ff 00
9290 10:52:12.641293 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 10:52:12.645288 version: 01 04
9292 10:52:12.648578 basic params: 95 1f 11 78 0a
9293 10:52:12.651287 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 10:52:12.655117 established: 00 00 00
9295 10:52:12.661332 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 10:52:12.665295 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 10:52:12.671233 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 10:52:12.677781 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 10:52:12.684584 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 10:52:12.687534 extensions: 00
9301 10:52:12.687998 checksum: fb
9302 10:52:12.688423
9303 10:52:12.691684 Manufacturer: IVO Model 57d Serial Number 0
9304 10:52:12.694098 Made week 0 of 2020
9305 10:52:12.697349 EDID version: 1.4
9306 10:52:12.697810 Digital display
9307 10:52:12.700708 6 bits per primary color channel
9308 10:52:12.701178 DisplayPort interface
9309 10:52:12.703926 Maximum image size: 31 cm x 17 cm
9310 10:52:12.707253 Gamma: 220%
9311 10:52:12.707670 Check DPMS levels
9312 10:52:12.714146 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 10:52:12.717207 First detailed timing is preferred timing
9314 10:52:12.717732 Established timings supported:
9315 10:52:12.720248 Standard timings supported:
9316 10:52:12.723858 Detailed timings
9317 10:52:12.727409 Hex of detail: 383680a07038204018303c0035ae10000019
9318 10:52:12.733855 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 10:52:12.737612 0780 0798 07c8 0820 hborder 0
9320 10:52:12.740681 0438 043b 0447 0458 vborder 0
9321 10:52:12.744410 -hsync -vsync
9322 10:52:12.744984 Did detailed timing
9323 10:52:12.750855 Hex of detail: 000000000000000000000000000000000000
9324 10:52:12.754001 Manufacturer-specified data, tag 0
9325 10:52:12.757105 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 10:52:12.760340 ASCII string: InfoVision
9327 10:52:12.763585 Hex of detail: 000000fe00523134304e574635205248200a
9328 10:52:12.766626 ASCII string: R140NWF5 RH
9329 10:52:12.767190 Checksum
9330 10:52:12.770041 Checksum: 0xfb (valid)
9331 10:52:12.772863 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 10:52:12.776476 DSI data_rate: 832800000 bps
9333 10:52:12.783575 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 10:52:12.786062 anx7625_parse_edid: pixelclock(138800).
9335 10:52:12.789432 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 10:52:12.792545 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 10:52:12.796077 anx7625_dsi_config: config dsi.
9338 10:52:12.802630 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 10:52:12.816922 anx7625_dsi_config: success to config DSI
9340 10:52:12.820715 anx7625_dp_start: MIPI phy setup OK.
9341 10:52:12.823079 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 10:52:12.826969 mtk_ddp_mode_set invalid vrefresh 60
9343 10:52:12.830832 main_disp_path_setup
9344 10:52:12.831369 ovl_layer_smi_id_en
9345 10:52:12.833690 ovl_layer_smi_id_en
9346 10:52:12.834205 ccorr_config
9347 10:52:12.834531 aal_config
9348 10:52:12.836389 gamma_config
9349 10:52:12.836794 postmask_config
9350 10:52:12.839927 dither_config
9351 10:52:12.843053 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 10:52:12.850321 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 10:52:12.852941 Root Device init finished in 555 msecs
9354 10:52:12.857699 CPU_CLUSTER: 0 init
9355 10:52:12.863616 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 10:52:12.869583 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 10:52:12.870132 APU_MBOX 0x190000b0 = 0x10001
9358 10:52:12.872958 APU_MBOX 0x190001b0 = 0x10001
9359 10:52:12.876112 APU_MBOX 0x190005b0 = 0x10001
9360 10:52:12.879716 APU_MBOX 0x190006b0 = 0x10001
9361 10:52:12.886448 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 10:52:12.895707 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9363 10:52:12.908022 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 10:52:12.914701 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 10:52:12.926804 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9366 10:52:12.936399 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 10:52:12.938957 CPU_CLUSTER: 0 init finished in 81 msecs
9368 10:52:12.942221 Devices initialized
9369 10:52:12.945223 Show all devs... After init.
9370 10:52:12.945670 Root Device: enabled 1
9371 10:52:12.948955 CPU_CLUSTER: 0: enabled 1
9372 10:52:12.952251 CPU: 00: enabled 1
9373 10:52:12.955739 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9374 10:52:12.958324 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 10:52:12.962035 ELOG: NV offset 0x57f000 size 0x1000
9376 10:52:12.968760 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9377 10:52:12.975332 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 10:52:12.978910 ELOG: Event(17) added with size 13 at 2023-06-05 10:52:16 UTC
9379 10:52:12.985796 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 10:52:12.988609 in-header: 03 0e 00 00 2c 00 00 00
9381 10:52:12.998618 in-data: 51 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 10:52:13.004799 ELOG: Event(A1) added with size 10 at 2023-06-05 10:52:16 UTC
9383 10:52:13.011597 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 10:52:13.018244 ELOG: Event(A0) added with size 9 at 2023-06-05 10:52:16 UTC
9385 10:52:13.021381 elog_add_boot_reason: Logged dev mode boot
9386 10:52:13.028209 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9387 10:52:13.028626 Finalize devices...
9388 10:52:13.031532 Devices finalized
9389 10:52:13.035212 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 10:52:13.037854 Writing coreboot table at 0xffe64000
9391 10:52:13.042554 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 10:52:13.047633 1. 0000000040000000-00000000400fffff: RAM
9393 10:52:13.051448 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 10:52:13.054604 3. 000000004032b000-00000000545fffff: RAM
9395 10:52:13.057702 4. 0000000054600000-000000005465ffff: BL31
9396 10:52:13.060926 5. 0000000054660000-00000000ffe63fff: RAM
9397 10:52:13.067940 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 10:52:13.070726 7. 0000000100000000-000000023fffffff: RAM
9399 10:52:13.075186 Passing 5 GPIOs to payload:
9400 10:52:13.077808 NAME | PORT | POLARITY | VALUE
9401 10:52:13.084213 EC in RW | 0x000000aa | low | undefined
9402 10:52:13.087364 EC interrupt | 0x00000005 | low | undefined
9403 10:52:13.091198 TPM interrupt | 0x000000ab | high | undefined
9404 10:52:13.097947 SD card detect | 0x00000011 | high | undefined
9405 10:52:13.100927 speaker enable | 0x00000093 | high | undefined
9406 10:52:13.104361 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 10:52:13.107361 in-header: 03 f9 00 00 02 00 00 00
9408 10:52:13.111211 in-data: 02 00
9409 10:52:13.114090 ADC[4]: Raw value=902955 ID=7
9410 10:52:13.116957 ADC[3]: Raw value=213546 ID=1
9411 10:52:13.117492 RAM Code: 0x71
9412 10:52:13.120436 ADC[6]: Raw value=75000 ID=0
9413 10:52:13.123913 ADC[5]: Raw value=213916 ID=1
9414 10:52:13.124361 SKU Code: 0x1
9415 10:52:13.130551 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9416 10:52:13.131070 coreboot table: 964 bytes.
9417 10:52:13.133440 IMD ROOT 0. 0xfffff000 0x00001000
9418 10:52:13.137241 IMD SMALL 1. 0xffffe000 0x00001000
9419 10:52:13.140222 RO MCACHE 2. 0xffffc000 0x00001104
9420 10:52:13.143636 CONSOLE 3. 0xfff7c000 0x00080000
9421 10:52:13.146670 FMAP 4. 0xfff7b000 0x00000452
9422 10:52:13.150025 TIME STAMP 5. 0xfff7a000 0x00000910
9423 10:52:13.153442 VBOOT WORK 6. 0xfff66000 0x00014000
9424 10:52:13.156559 RAMOOPS 7. 0xffe66000 0x00100000
9425 10:52:13.159832 COREBOOT 8. 0xffe64000 0x00002000
9426 10:52:13.163172 IMD small region:
9427 10:52:13.166457 IMD ROOT 0. 0xffffec00 0x00000400
9428 10:52:13.170366 VPD 1. 0xffffeba0 0x0000004c
9429 10:52:13.173115 MMC STATUS 2. 0xffffeb80 0x00000004
9430 10:52:13.180242 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 10:52:13.180758 Probing TPM: done!
9432 10:52:13.186209 Connected to device vid:did:rid of 1ae0:0028:00
9433 10:52:13.192730 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9434 10:52:13.196424 Initialized TPM device CR50 revision 0
9435 10:52:13.200405 Checking cr50 for pending updates
9436 10:52:13.205277 Reading cr50 TPM mode
9437 10:52:13.214152 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 10:52:13.220773 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 10:52:13.260807 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9440 10:52:13.264711 Checking segment from ROM address 0x40100000
9441 10:52:13.267534 Checking segment from ROM address 0x4010001c
9442 10:52:13.274378 Loading segment from ROM address 0x40100000
9443 10:52:13.274935 code (compression=0)
9444 10:52:13.284189 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 10:52:13.290807 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 10:52:13.291367 it's not compressed!
9447 10:52:13.297432 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 10:52:13.303975 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 10:52:13.321350 Loading segment from ROM address 0x4010001c
9450 10:52:13.321911 Entry Point 0x80000000
9451 10:52:13.324321 Loaded segments
9452 10:52:13.327860 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 10:52:13.334351 Jumping to boot code at 0x80000000(0xffe64000)
9454 10:52:13.341175 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 10:52:13.347623 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 10:52:13.355671 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9457 10:52:13.358791 Checking segment from ROM address 0x40100000
9458 10:52:13.362141 Checking segment from ROM address 0x4010001c
9459 10:52:13.369786 Loading segment from ROM address 0x40100000
9460 10:52:13.370203 code (compression=1)
9461 10:52:13.375318 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 10:52:13.385252 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 10:52:13.385812 using LZMA
9464 10:52:13.394041 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 10:52:13.401067 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 10:52:13.404435 Loading segment from ROM address 0x4010001c
9467 10:52:13.404989 Entry Point 0x54601000
9468 10:52:13.407460 Loaded segments
9469 10:52:13.410933 NOTICE: MT8192 bl31_setup
9470 10:52:13.417482 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 10:52:13.420991 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 10:52:13.424118 WARNING: region 0:
9473 10:52:13.427568 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 10:52:13.428158 WARNING: region 1:
9475 10:52:13.434035 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 10:52:13.437458 WARNING: region 2:
9477 10:52:13.440853 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 10:52:13.443685 WARNING: region 3:
9479 10:52:13.450399 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 10:52:13.450958 WARNING: region 4:
9481 10:52:13.457167 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 10:52:13.457627 WARNING: region 5:
9483 10:52:13.460616 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 10:52:13.463757 WARNING: region 6:
9485 10:52:13.466935 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 10:52:13.469986 WARNING: region 7:
9487 10:52:13.473392 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 10:52:13.480940 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 10:52:13.483438 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 10:52:13.490147 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 10:52:13.493348 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 10:52:13.497049 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 10:52:13.503790 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 10:52:13.507452 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 10:52:13.510053 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 10:52:13.516822 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 10:52:13.519814 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 10:52:13.526418 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 10:52:13.529604 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 10:52:13.533110 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 10:52:13.539704 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 10:52:13.543009 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 10:52:13.549203 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 10:52:13.552594 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 10:52:13.555972 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 10:52:13.562309 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 10:52:13.566624 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 10:52:13.572200 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 10:52:13.576117 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 10:52:13.579350 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 10:52:13.585164 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 10:52:13.589007 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 10:52:13.595369 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 10:52:13.598910 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 10:52:13.601928 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 10:52:13.608871 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 10:52:13.612016 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 10:52:13.619042 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 10:52:13.621823 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 10:52:13.625179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 10:52:13.631814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 10:52:13.634912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 10:52:13.638606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 10:52:13.641990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 10:52:13.647982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 10:52:13.651503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 10:52:13.654791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 10:52:13.658350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 10:52:13.665075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 10:52:13.668243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 10:52:13.671232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 10:52:13.674798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 10:52:13.681326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 10:52:13.684636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 10:52:13.688286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 10:52:13.695373 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 10:52:13.698216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 10:52:13.701268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 10:52:13.708021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 10:52:13.711126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 10:52:13.717655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 10:52:13.720961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 10:52:13.728440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 10:52:13.731833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 10:52:13.734453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 10:52:13.741538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 10:52:13.744376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 10:52:13.751435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 10:52:13.754413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 10:52:13.761418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 10:52:13.764225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 10:52:13.771189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 10:52:13.775308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 10:52:13.777420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 10:52:13.784156 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 10:52:13.787913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 10:52:13.794256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 10:52:13.797129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 10:52:13.803933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 10:52:13.807802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 10:52:13.810418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 10:52:13.817554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 10:52:13.820758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 10:52:13.827337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 10:52:13.830859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 10:52:13.837104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 10:52:13.840206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 10:52:13.846852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 10:52:13.849979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 10:52:13.856695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 10:52:13.860400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 10:52:13.863826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 10:52:13.870268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 10:52:13.873894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 10:52:13.880647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 10:52:13.884228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 10:52:13.890508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 10:52:13.893469 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 10:52:13.897209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 10:52:13.903478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 10:52:13.906252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 10:52:13.912985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 10:52:13.916752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 10:52:13.923248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 10:52:13.926697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 10:52:13.929747 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 10:52:13.932734 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 10:52:13.939696 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 10:52:13.943214 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 10:52:13.946579 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 10:52:13.953189 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 10:52:13.956194 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 10:52:13.963144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 10:52:13.966463 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 10:52:13.970211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 10:52:13.976525 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 10:52:13.979580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 10:52:13.986036 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 10:52:13.989230 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 10:52:13.996013 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 10:52:13.999505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 10:52:14.002823 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 10:52:14.009325 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 10:52:14.012706 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 10:52:14.015900 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 10:52:14.022693 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 10:52:14.026000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 10:52:14.029006 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 10:52:14.032657 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 10:52:14.036273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 10:52:14.042735 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 10:52:14.046073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 10:52:14.052394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 10:52:14.056126 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 10:52:14.058989 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 10:52:14.065508 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 10:52:14.068994 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 10:52:14.075309 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 10:52:14.078714 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 10:52:14.082252 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 10:52:14.088941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 10:52:14.091970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 10:52:14.098649 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 10:52:14.102097 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 10:52:14.105385 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 10:52:14.111722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 10:52:14.115654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 10:52:14.122183 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 10:52:14.125931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 10:52:14.128769 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 10:52:14.135033 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 10:52:14.138747 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 10:52:14.142189 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 10:52:14.148983 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 10:52:14.151590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 10:52:14.158476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 10:52:14.161729 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 10:52:14.165124 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 10:52:14.171738 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 10:52:14.175863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 10:52:14.181908 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 10:52:14.185133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 10:52:14.187986 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 10:52:14.194987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 10:52:14.198185 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 10:52:14.204670 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 10:52:14.207983 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 10:52:14.211173 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 10:52:14.217348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 10:52:14.221176 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 10:52:14.227806 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 10:52:14.231273 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 10:52:14.234979 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 10:52:14.240899 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 10:52:14.244130 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 10:52:14.251142 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 10:52:14.253976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 10:52:14.257328 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 10:52:14.264700 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 10:52:14.267359 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 10:52:14.273635 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 10:52:14.276879 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 10:52:14.280019 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 10:52:14.287293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 10:52:14.290116 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 10:52:14.297124 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 10:52:14.300606 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 10:52:14.303418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 10:52:14.310197 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 10:52:14.313314 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 10:52:14.320155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 10:52:14.323196 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 10:52:14.326902 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 10:52:14.333916 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 10:52:14.336960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 10:52:14.343144 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 10:52:14.346641 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 10:52:14.353088 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 10:52:14.356587 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 10:52:14.359502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 10:52:14.366530 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 10:52:14.369374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 10:52:14.376137 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 10:52:14.379552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 10:52:14.386345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 10:52:14.389114 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 10:52:14.392422 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 10:52:14.399366 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 10:52:14.402760 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 10:52:14.409577 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 10:52:14.412594 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 10:52:14.420126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 10:52:14.421854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 10:52:14.425150 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 10:52:14.432397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 10:52:14.435476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 10:52:14.441746 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 10:52:14.445914 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 10:52:14.448530 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 10:52:14.455234 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 10:52:14.458694 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 10:52:14.464712 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 10:52:14.468769 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 10:52:14.474749 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 10:52:14.478216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 10:52:14.484871 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 10:52:14.488192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 10:52:14.491938 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 10:52:14.497876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 10:52:14.500916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 10:52:14.507874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 10:52:14.511305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 10:52:14.518312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 10:52:14.521712 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 10:52:14.524477 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 10:52:14.531155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 10:52:14.533949 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 10:52:14.537283 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 10:52:14.540959 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 10:52:14.547163 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 10:52:14.550460 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 10:52:14.553915 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 10:52:14.560384 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 10:52:14.563613 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 10:52:14.570856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 10:52:14.573843 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 10:52:14.576704 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 10:52:14.583350 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 10:52:14.587092 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 10:52:14.590067 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 10:52:14.596457 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 10:52:14.600361 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 10:52:14.607113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 10:52:14.609957 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 10:52:14.613842 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 10:52:14.619732 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 10:52:14.623131 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 10:52:14.626314 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 10:52:14.632593 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 10:52:14.636364 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 10:52:14.639436 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 10:52:14.645706 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 10:52:14.649104 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 10:52:14.655879 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 10:52:14.659505 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 10:52:14.663113 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 10:52:14.669006 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 10:52:14.672483 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 10:52:14.678772 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 10:52:14.682398 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 10:52:14.685583 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 10:52:14.692414 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 10:52:14.695616 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 10:52:14.699136 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 10:52:14.705642 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 10:52:14.708330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 10:52:14.711804 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 10:52:14.718430 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 10:52:14.721468 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 10:52:14.725007 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 10:52:14.728552 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 10:52:14.735259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 10:52:14.738312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 10:52:14.741473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 10:52:14.745288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 10:52:14.751371 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 10:52:14.754528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 10:52:14.757944 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 10:52:14.760816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 10:52:14.767583 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 10:52:14.770904 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 10:52:14.777513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 10:52:14.781131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 10:52:14.787698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 10:52:14.790983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 10:52:14.797869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 10:52:14.800598 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 10:52:14.804428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 10:52:14.810680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 10:52:14.813897 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 10:52:14.820550 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 10:52:14.824140 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 10:52:14.827327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 10:52:14.833450 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 10:52:14.836679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 10:52:14.843492 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 10:52:14.846592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 10:52:14.853015 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 10:52:14.856366 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 10:52:14.859718 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 10:52:14.866122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 10:52:14.869784 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 10:52:14.875907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 10:52:14.879621 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 10:52:14.882844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 10:52:14.889770 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 10:52:14.892994 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 10:52:14.899214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 10:52:14.902537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 10:52:14.908874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 10:52:14.912163 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 10:52:14.915818 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 10:52:14.922181 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 10:52:14.925255 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 10:52:14.931887 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 10:52:14.935669 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 10:52:14.941892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 10:52:14.945484 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 10:52:14.948772 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 10:52:14.955069 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 10:52:14.958162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 10:52:14.964825 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 10:52:14.968156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 10:52:14.974416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 10:52:14.978077 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 10:52:14.981497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 10:52:14.987811 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 10:52:14.991060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 10:52:14.998381 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 10:52:15.001060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 10:52:15.007888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 10:52:15.010992 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 10:52:15.014128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 10:52:15.020766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 10:52:15.023652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 10:52:15.031349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 10:52:15.034082 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 10:52:15.037434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 10:52:15.043740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 10:52:15.047731 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 10:52:15.053604 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 10:52:15.056718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 10:52:15.063679 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 10:52:15.066846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 10:52:15.069885 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 10:52:15.076436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 10:52:15.079800 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 10:52:15.086562 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 10:52:15.089345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 10:52:15.096394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 10:52:15.099300 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 10:52:15.105269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 10:52:15.109184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 10:52:15.112776 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 10:52:15.119258 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 10:52:15.122549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 10:52:15.129041 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 10:52:15.132669 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 10:52:15.136232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 10:52:15.142890 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 10:52:15.145560 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 10:52:15.152106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 10:52:15.155560 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 10:52:15.162272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 10:52:15.165730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 10:52:15.172289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 10:52:15.175312 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 10:52:15.182234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 10:52:15.184977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 10:52:15.188138 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 10:52:15.194809 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 10:52:15.198164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 10:52:15.204959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 10:52:15.208824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 10:52:15.214569 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 10:52:15.217760 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 10:52:15.224670 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 10:52:15.228403 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 10:52:15.231628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 10:52:15.237960 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 10:52:15.241481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 10:52:15.248100 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 10:52:15.251106 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 10:52:15.257896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 10:52:15.260893 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 10:52:15.267309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 10:52:15.270775 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 10:52:15.277084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 10:52:15.280441 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 10:52:15.283827 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 10:52:15.290257 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 10:52:15.293272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 10:52:15.300241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 10:52:15.303155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 10:52:15.309969 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 10:52:15.313510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 10:52:15.319797 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 10:52:15.322951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 10:52:15.326226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 10:52:15.332986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 10:52:15.335648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 10:52:15.342279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 10:52:15.346397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 10:52:15.352011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 10:52:15.355582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 10:52:15.362083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 10:52:15.365985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 10:52:15.372238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 10:52:15.375072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 10:52:15.382166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 10:52:15.385390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 10:52:15.391854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 10:52:15.395241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 10:52:15.401742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 10:52:15.404712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 10:52:15.411488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 10:52:15.415343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 10:52:15.420994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 10:52:15.424638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 10:52:15.431442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 10:52:15.434971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 10:52:15.441258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 10:52:15.444952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 10:52:15.451135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 10:52:15.454386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 10:52:15.460891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 10:52:15.464078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 10:52:15.470771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 10:52:15.474089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 10:52:15.480662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 10:52:15.483789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 10:52:15.487710 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 10:52:15.491045 INFO: [APUAPC] vio 0
9924 10:52:15.497224 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 10:52:15.500568 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 10:52:15.503945 INFO: [APUAPC] D0_APC_0: 0x400510
9927 10:52:15.507066 INFO: [APUAPC] D0_APC_1: 0x0
9928 10:52:15.510466 INFO: [APUAPC] D0_APC_2: 0x1540
9929 10:52:15.513388 INFO: [APUAPC] D0_APC_3: 0x0
9930 10:52:15.517974 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 10:52:15.520001 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 10:52:15.523659 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 10:52:15.526620 INFO: [APUAPC] D1_APC_3: 0x0
9934 10:52:15.530700 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 10:52:15.533397 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 10:52:15.537013 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 10:52:15.540190 INFO: [APUAPC] D2_APC_3: 0x0
9938 10:52:15.543353 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 10:52:15.547085 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 10:52:15.549852 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 10:52:15.553491 INFO: [APUAPC] D3_APC_3: 0x0
9942 10:52:15.556637 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 10:52:15.560105 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 10:52:15.563348 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 10:52:15.563444 INFO: [APUAPC] D4_APC_3: 0x0
9946 10:52:15.569672 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 10:52:15.573173 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 10:52:15.576431 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 10:52:15.576547 INFO: [APUAPC] D5_APC_3: 0x0
9950 10:52:15.579527 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 10:52:15.586217 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 10:52:15.589556 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 10:52:15.589644 INFO: [APUAPC] D6_APC_3: 0x0
9954 10:52:15.593009 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 10:52:15.596105 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 10:52:15.599447 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 10:52:15.603112 INFO: [APUAPC] D7_APC_3: 0x0
9958 10:52:15.605839 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 10:52:15.609145 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 10:52:15.612736 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 10:52:15.615670 INFO: [APUAPC] D8_APC_3: 0x0
9962 10:52:15.619931 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 10:52:15.622544 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 10:52:15.625591 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 10:52:15.629287 INFO: [APUAPC] D9_APC_3: 0x0
9966 10:52:15.632496 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 10:52:15.635737 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 10:52:15.639370 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 10:52:15.643471 INFO: [APUAPC] D10_APC_3: 0x0
9970 10:52:15.645642 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 10:52:15.649260 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 10:52:15.652240 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 10:52:15.655248 INFO: [APUAPC] D11_APC_3: 0x0
9974 10:52:15.658534 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 10:52:15.665350 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 10:52:15.668405 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 10:52:15.668552 INFO: [APUAPC] D12_APC_3: 0x0
9978 10:52:15.675149 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 10:52:15.678477 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 10:52:15.682220 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 10:52:15.685108 INFO: [APUAPC] D13_APC_3: 0x0
9982 10:52:15.688901 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 10:52:15.692341 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 10:52:15.694972 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 10:52:15.698286 INFO: [APUAPC] D14_APC_3: 0x0
9986 10:52:15.701637 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 10:52:15.705411 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 10:52:15.708558 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 10:52:15.712180 INFO: [APUAPC] D15_APC_3: 0x0
9990 10:52:15.712661 INFO: [APUAPC] APC_CON: 0x4
9991 10:52:15.715172 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 10:52:15.718433 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 10:52:15.721989 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 10:52:15.725578 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 10:52:15.729399 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 10:52:15.731824 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 10:52:15.735302 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 10:52:15.738684 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 10:52:15.741963 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 10:52:15.742410 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 10:52:15.744728 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 10:52:15.748206 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 10:52:15.751678 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 10:52:15.754478 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 10:52:15.757825 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 10:52:15.762549 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 10:52:15.764726 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 10:52:15.767637 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 10:52:15.771528 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 10:52:15.774666 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 10:52:15.778520 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 10:52:15.780826 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 10:52:15.781286 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 10:52:15.784457 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 10:52:15.787317 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 10:52:15.791196 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 10:52:15.794402 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 10:52:15.797454 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 10:52:15.800939 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 10:52:15.803743 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 10:52:15.807153 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 10:52:15.810914 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 10:52:15.813949 INFO: [NOCDAPC] APC_CON: 0x4
10024 10:52:15.817134 INFO: [APUAPC] set_apusys_apc done
10025 10:52:15.820641 INFO: [DEVAPC] devapc_init done
10026 10:52:15.824175 INFO: GICv3 without legacy support detected.
10027 10:52:15.827377 INFO: ARM GICv3 driver initialized in EL3
10028 10:52:15.830623 INFO: Maximum SPI INTID supported: 639
10029 10:52:15.836841 INFO: BL31: Initializing runtime services
10030 10:52:15.839919 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 10:52:15.843310 INFO: SPM: enable CPC mode
10032 10:52:15.850106 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 10:52:15.853614 INFO: BL31: Preparing for EL3 exit to normal world
10034 10:52:15.856297 INFO: Entry point address = 0x80000000
10035 10:52:15.859700 INFO: SPSR = 0x8
10036 10:52:15.865960
10037 10:52:15.866518
10038 10:52:15.866891
10039 10:52:15.868879 Starting depthcharge on Spherion...
10040 10:52:15.869341
10041 10:52:15.869705 Wipe memory regions:
10042 10:52:15.870049
10043 10:52:15.872617 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10044 10:52:15.873165 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 10:52:15.873644 Setting prompt string to ['asurada:']
10046 10:52:15.874076 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 10:52:15.874792 [0x00000040000000, 0x00000054600000)
10048 10:52:15.994972
10049 10:52:15.995535 [0x00000054660000, 0x00000080000000)
10050 10:52:16.255955
10051 10:52:16.256254 [0x000000821a7280, 0x000000ffe64000)
10052 10:52:17.000331
10053 10:52:17.000895 [0x00000100000000, 0x00000240000000)
10054 10:52:18.889960
10055 10:52:18.893175 Initializing XHCI USB controller at 0x11200000.
10056 10:52:19.930839
10057 10:52:19.934143 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 10:52:19.934230
10059 10:52:19.934297
10060 10:52:19.934358
10061 10:52:19.934636 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 10:52:20.035019 asurada: tftpboot 192.168.201.1 10590978/tftp-deploy-55rc5d5u/kernel/image.itb 10590978/tftp-deploy-55rc5d5u/kernel/cmdline
10064 10:52:20.035200 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 10:52:20.035317 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 10:52:20.040140 tftpboot 192.168.201.1 10590978/tftp-deploy-55rc5d5u/kernel/image.itp-deploy-55rc5d5u/kernel/cmdline
10067 10:52:20.040226
10068 10:52:20.040292 Waiting for link
10069 10:52:20.200397
10070 10:52:20.200537 R8152: Initializing
10071 10:52:20.200606
10072 10:52:20.203748 Version 6 (ocp_data = 5c30)
10073 10:52:20.203847
10074 10:52:20.206696 R8152: Done initializing
10075 10:52:20.206778
10076 10:52:20.206843 Adding net device
10077 10:52:22.077965
10078 10:52:22.078132 done.
10079 10:52:22.078201
10080 10:52:22.078316 MAC: 00:24:32:30:7c:7b
10081 10:52:22.078374
10082 10:52:22.081165 Sending DHCP discover... done.
10083 10:52:22.081274
10084 10:52:22.084417 Waiting for reply... done.
10085 10:52:22.084535
10086 10:52:22.087597 Sending DHCP request... done.
10087 10:52:22.087713
10088 10:52:22.087778 Waiting for reply... done.
10089 10:52:22.087838
10090 10:52:22.090977 My ip is 192.168.201.14
10091 10:52:22.091059
10092 10:52:22.094521 The DHCP server ip is 192.168.201.1
10093 10:52:22.094604
10094 10:52:22.097814 TFTP server IP predefined by user: 192.168.201.1
10095 10:52:22.097897
10096 10:52:22.104000 Bootfile predefined by user: 10590978/tftp-deploy-55rc5d5u/kernel/image.itb
10097 10:52:22.104124
10098 10:52:22.107566 Sending tftp read request... done.
10099 10:52:22.107649
10100 10:52:22.111016 Waiting for the transfer...
10101 10:52:22.111103
10102 10:52:22.644820 00000000 ################################################################
10103 10:52:22.644993
10104 10:52:23.172472 00080000 ################################################################
10105 10:52:23.172605
10106 10:52:23.712831 00100000 ################################################################
10107 10:52:23.712982
10108 10:52:24.269160 00180000 ################################################################
10109 10:52:24.269294
10110 10:52:24.837522 00200000 ################################################################
10111 10:52:24.837687
10112 10:52:25.422269 00280000 ################################################################
10113 10:52:25.422416
10114 10:52:26.005803 00300000 ################################################################
10115 10:52:26.005954
10116 10:52:26.587733 00380000 ################################################################
10117 10:52:26.587886
10118 10:52:27.150741 00400000 ################################################################
10119 10:52:27.150893
10120 10:52:27.697232 00480000 ################################################################
10121 10:52:27.697500
10122 10:52:28.263415 00500000 ################################################################
10123 10:52:28.263566
10124 10:52:28.829355 00580000 ################################################################
10125 10:52:28.829530
10126 10:52:29.390298 00600000 ################################################################
10127 10:52:29.390457
10128 10:52:29.951554 00680000 ################################################################
10129 10:52:29.951761
10130 10:52:30.516243 00700000 ################################################################
10131 10:52:30.516446
10132 10:52:31.076663 00780000 ################################################################
10133 10:52:31.076866
10134 10:52:31.639329 00800000 ################################################################
10135 10:52:31.639533
10136 10:52:32.201354 00880000 ################################################################
10137 10:52:32.201522
10138 10:52:32.756337 00900000 ################################################################
10139 10:52:32.756506
10140 10:52:33.314464 00980000 ################################################################
10141 10:52:33.314633
10142 10:52:33.879674 00a00000 ################################################################
10143 10:52:33.879834
10144 10:52:34.461905 00a80000 ################################################################
10145 10:52:34.462072
10146 10:52:35.041536 00b00000 ################################################################
10147 10:52:35.041704
10148 10:52:35.598557 00b80000 ################################################################
10149 10:52:35.598773
10150 10:52:36.177672 00c00000 ################################################################
10151 10:52:36.177831
10152 10:52:36.741320 00c80000 ################################################################
10153 10:52:36.741473
10154 10:52:37.318090 00d00000 ################################################################
10155 10:52:37.318249
10156 10:52:37.894007 00d80000 ################################################################
10157 10:52:37.894162
10158 10:52:38.456467 00e00000 ################################################################
10159 10:52:38.456625
10160 10:52:39.017566 00e80000 ################################################################
10161 10:52:39.017714
10162 10:52:39.600725 00f00000 ################################################################
10163 10:52:39.600895
10164 10:52:40.156012 00f80000 ################################################################
10165 10:52:40.156189
10166 10:52:40.728736 01000000 ################################################################
10167 10:52:40.728884
10168 10:52:41.330691 01080000 ################################################################
10169 10:52:41.330853
10170 10:52:41.931586 01100000 ################################################################
10171 10:52:41.931737
10172 10:52:42.556077 01180000 ################################################################
10173 10:52:42.556716
10174 10:52:43.273925 01200000 ################################################################
10175 10:52:43.274462
10176 10:52:44.009275 01280000 ################################################################
10177 10:52:44.009806
10178 10:52:44.718951 01300000 ################################################################
10179 10:52:44.719465
10180 10:52:45.431584 01380000 ################################################################
10181 10:52:45.432157
10182 10:52:46.149622 01400000 ################################################################
10183 10:52:46.150144
10184 10:52:46.839482 01480000 ################################################################
10185 10:52:46.839974
10186 10:52:47.475359 01500000 ################################################################
10187 10:52:47.475566
10188 10:52:48.086664 01580000 ################################################################
10189 10:52:48.086794
10190 10:52:48.684447 01600000 ################################################################
10191 10:52:48.684595
10192 10:52:49.235238 01680000 ################################################################
10193 10:52:49.235464
10194 10:52:49.895506 01700000 ################################################################
10195 10:52:49.896110
10196 10:52:50.614232 01780000 ################################################################
10197 10:52:50.614776
10198 10:52:51.314114 01800000 ################################################################
10199 10:52:51.314670
10200 10:52:51.898526 01880000 ################################################################
10201 10:52:51.898670
10202 10:52:52.437754 01900000 ################################################################
10203 10:52:52.437893
10204 10:52:52.974886 01980000 ################################################################
10205 10:52:52.975016
10206 10:52:53.491622 01a00000 ############################################################## done.
10207 10:52:53.491757
10208 10:52:53.495170 The bootfile was 27769774 bytes long.
10209 10:52:53.495253
10210 10:52:53.498726 Sending tftp read request... done.
10211 10:52:53.498808
10212 10:52:53.498872 Waiting for the transfer...
10213 10:52:53.498933
10214 10:52:53.501944 00000000 # done.
10215 10:52:53.502026
10216 10:52:53.508294 Command line loaded dynamically from TFTP file: 10590978/tftp-deploy-55rc5d5u/kernel/cmdline
10217 10:52:53.508376
10218 10:52:53.528212 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10219 10:52:53.528300
10220 10:52:53.531609 Loading FIT.
10221 10:52:53.531689
10222 10:52:53.534596 Image ramdisk-1 has 17638877 bytes.
10223 10:52:53.534676
10224 10:52:53.534740 Image fdt-1 has 46924 bytes.
10225 10:52:53.534799
10226 10:52:53.537855 Image kernel-1 has 10081937 bytes.
10227 10:52:53.537949
10228 10:52:53.547962 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10229 10:52:53.548052
10230 10:52:53.564944 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10231 10:52:53.565047
10232 10:52:53.571348 Choosing best match conf-1 for compat google,spherion-rev2.
10233 10:52:53.574879
10234 10:52:53.580047 Connected to device vid:did:rid of 1ae0:0028:00
10235 10:52:53.586705
10236 10:52:53.589924 tpm_get_response: command 0x17b, return code 0x0
10237 10:52:53.590007
10238 10:52:53.593212 ec_init: CrosEC protocol v3 supported (256, 248)
10239 10:52:53.597289
10240 10:52:53.600226 tpm_cleanup: add release locality here.
10241 10:52:53.600308
10242 10:52:53.600373 Shutting down all USB controllers.
10243 10:52:53.603629
10244 10:52:53.603720 Removing current net device
10245 10:52:53.603789
10246 10:52:53.610163 Exiting depthcharge with code 4 at timestamp: 67017950
10247 10:52:53.610246
10248 10:52:53.613679 LZMA decompressing kernel-1 to 0x821a6718
10249 10:52:53.613762
10250 10:52:53.617328 LZMA decompressing kernel-1 to 0x40000000
10251 10:52:54.883005
10252 10:52:54.883144 jumping to kernel
10253 10:52:54.883543 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10254 10:52:54.883642 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10255 10:52:54.883718 Setting prompt string to ['Linux version [0-9]']
10256 10:52:54.883803 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10257 10:52:54.883887 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10258 10:52:54.964747
10259 10:52:54.967652 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10260 10:52:54.971574 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10261 10:52:54.971667 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10262 10:52:54.971749 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10263 10:52:54.971823 Using line separator: #'\n'#
10264 10:52:54.971885 No login prompt set.
10265 10:52:54.971945 Parsing kernel messages
10266 10:52:54.971999 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10267 10:52:54.972149 [login-action] Waiting for messages, (timeout 00:03:46)
10268 10:52:54.990553 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10269 10:52:54.994137 [ 0.000000] random: crng init done
10270 10:52:55.000535 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10271 10:52:55.003939 [ 0.000000] efi: UEFI not found.
10272 10:52:55.010367 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10273 10:52:55.016879 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10274 10:52:55.026863 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10275 10:52:55.036838 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10276 10:52:55.043182 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10277 10:52:55.049681 [ 0.000000] printk: bootconsole [mtk8250] enabled
10278 10:52:55.056446 [ 0.000000] NUMA: No NUMA configuration found
10279 10:52:55.062757 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10280 10:52:55.066009 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10281 10:52:55.069852 [ 0.000000] Zone ranges:
10282 10:52:55.075991 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10283 10:52:55.079328 [ 0.000000] DMA32 empty
10284 10:52:55.086359 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10285 10:52:55.089133 [ 0.000000] Movable zone start for each node
10286 10:52:55.092663 [ 0.000000] Early memory node ranges
10287 10:52:55.099104 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10288 10:52:55.105650 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10289 10:52:55.112580 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10290 10:52:55.118771 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10291 10:52:55.125505 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10292 10:52:55.131738 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10293 10:52:55.188544 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10294 10:52:55.194841 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10295 10:52:55.201902 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10296 10:52:55.204983 [ 0.000000] psci: probing for conduit method from DT.
10297 10:52:55.211324 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10298 10:52:55.214725 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10299 10:52:55.221213 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10300 10:52:55.224699 [ 0.000000] psci: SMC Calling Convention v1.2
10301 10:52:55.231133 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10302 10:52:55.234700 [ 0.000000] Detected VIPT I-cache on CPU0
10303 10:52:55.241277 [ 0.000000] CPU features: detected: GIC system register CPU interface
10304 10:52:55.247843 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10305 10:52:55.254240 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10306 10:52:55.260948 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10307 10:52:55.270552 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10308 10:52:55.277148 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10309 10:52:55.281222 [ 0.000000] alternatives: applying boot alternatives
10310 10:52:55.287192 [ 0.000000] Fallback order for Node 0: 0
10311 10:52:55.294093 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10312 10:52:55.297243 [ 0.000000] Policy zone: Normal
10313 10:52:55.317099 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10314 10:52:55.326481 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10315 10:52:55.339236 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10316 10:52:55.348884 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10317 10:52:55.355460 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10318 10:52:55.358798 <6>[ 0.000000] software IO TLB: area num 8.
10319 10:52:55.414737 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10320 10:52:55.563638 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10321 10:52:55.570303 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10322 10:52:55.577012 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10323 10:52:55.580093 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10324 10:52:55.586894 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10325 10:52:55.593184 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10326 10:52:55.596472 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10327 10:52:55.606924 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10328 10:52:55.613156 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10329 10:52:55.619610 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10330 10:52:55.626363 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10331 10:52:55.629617 <6>[ 0.000000] GICv3: 608 SPIs implemented
10332 10:52:55.633048 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10333 10:52:55.639823 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10334 10:52:55.642920 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10335 10:52:55.649443 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10336 10:52:55.662936 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10337 10:52:55.676170 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10338 10:52:55.682726 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10339 10:52:55.690731 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10340 10:52:55.703525 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10341 10:52:55.710336 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10342 10:52:55.716544 <6>[ 0.009178] Console: colour dummy device 80x25
10343 10:52:55.727183 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10344 10:52:55.733490 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10345 10:52:55.736726 <6>[ 0.029284] LSM: Security Framework initializing
10346 10:52:55.743485 <6>[ 0.034224] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10347 10:52:55.753092 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10348 10:52:55.763192 <6>[ 0.051517] cblist_init_generic: Setting adjustable number of callback queues.
10349 10:52:55.766274 <6>[ 0.058970] cblist_init_generic: Setting shift to 3 and lim to 1.
10350 10:52:55.773317 <6>[ 0.065308] cblist_init_generic: Setting shift to 3 and lim to 1.
10351 10:52:55.779818 <6>[ 0.071755] rcu: Hierarchical SRCU implementation.
10352 10:52:55.786014 <6>[ 0.076799] rcu: Max phase no-delay instances is 1000.
10353 10:52:55.793124 <6>[ 0.083819] EFI services will not be available.
10354 10:52:55.795928 <6>[ 0.088819] smp: Bringing up secondary CPUs ...
10355 10:52:55.803648 <6>[ 0.093902] Detected VIPT I-cache on CPU1
10356 10:52:55.810580 <6>[ 0.093976] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10357 10:52:55.817052 <6>[ 0.094008] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10358 10:52:55.820258 <6>[ 0.094344] Detected VIPT I-cache on CPU2
10359 10:52:55.830514 <6>[ 0.094396] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10360 10:52:55.836717 <6>[ 0.094412] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10361 10:52:55.839948 <6>[ 0.094668] Detected VIPT I-cache on CPU3
10362 10:52:55.847018 <6>[ 0.094714] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10363 10:52:55.853368 <6>[ 0.094728] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10364 10:52:55.860211 <6>[ 0.095032] CPU features: detected: Spectre-v4
10365 10:52:55.863349 <6>[ 0.095038] CPU features: detected: Spectre-BHB
10366 10:52:55.866388 <6>[ 0.095043] Detected PIPT I-cache on CPU4
10367 10:52:55.872775 <6>[ 0.095102] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10368 10:52:55.879503 <6>[ 0.095118] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10369 10:52:55.886303 <6>[ 0.095417] Detected PIPT I-cache on CPU5
10370 10:52:55.892934 <6>[ 0.095482] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10371 10:52:55.899405 <6>[ 0.095499] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10372 10:52:55.902427 <6>[ 0.095784] Detected PIPT I-cache on CPU6
10373 10:52:55.912365 <6>[ 0.095849] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10374 10:52:55.919428 <6>[ 0.095865] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10375 10:52:55.922515 <6>[ 0.096162] Detected PIPT I-cache on CPU7
10376 10:52:55.928937 <6>[ 0.096229] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10377 10:52:55.935779 <6>[ 0.096246] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10378 10:52:55.938744 <6>[ 0.096294] smp: Brought up 1 node, 8 CPUs
10379 10:52:55.945521 <6>[ 0.237631] SMP: Total of 8 processors activated.
10380 10:52:55.952407 <6>[ 0.242552] CPU features: detected: 32-bit EL0 Support
10381 10:52:55.959109 <6>[ 0.247948] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10382 10:52:55.965526 <6>[ 0.256747] CPU features: detected: Common not Private translations
10383 10:52:55.971920 <6>[ 0.263223] CPU features: detected: CRC32 instructions
10384 10:52:55.979010 <6>[ 0.268574] CPU features: detected: RCpc load-acquire (LDAPR)
10385 10:52:55.981805 <6>[ 0.274533] CPU features: detected: LSE atomic instructions
10386 10:52:55.988296 <6>[ 0.280314] CPU features: detected: Privileged Access Never
10387 10:52:55.994766 <6>[ 0.286130] CPU features: detected: RAS Extension Support
10388 10:52:56.001646 <6>[ 0.291738] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10389 10:52:56.004781 <6>[ 0.298960] CPU: All CPU(s) started at EL2
10390 10:52:56.011277 <6>[ 0.303276] alternatives: applying system-wide alternatives
10391 10:52:56.021276 <6>[ 0.313979] devtmpfs: initialized
10392 10:52:56.037110 <6>[ 0.323188] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10393 10:52:56.043858 <6>[ 0.333151] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10394 10:52:56.047451 <6>[ 0.340760] pinctrl core: initialized pinctrl subsystem
10395 10:52:56.055115 <6>[ 0.347435] DMI not present or invalid.
10396 10:52:56.061902 <6>[ 0.351849] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10397 10:52:56.068206 <6>[ 0.358753] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10398 10:52:56.078028 <6>[ 0.366333] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10399 10:52:56.084373 <6>[ 0.374561] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10400 10:52:56.090959 <6>[ 0.382805] audit: initializing netlink subsys (disabled)
10401 10:52:56.097563 <5>[ 0.388503] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10402 10:52:56.104305 <6>[ 0.389227] thermal_sys: Registered thermal governor 'step_wise'
10403 10:52:56.111535 <6>[ 0.396470] thermal_sys: Registered thermal governor 'power_allocator'
10404 10:52:56.117630 <6>[ 0.402725] cpuidle: using governor menu
10405 10:52:56.120934 <6>[ 0.413683] NET: Registered PF_QIPCRTR protocol family
10406 10:52:56.127553 <6>[ 0.419179] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10407 10:52:56.134009 <6>[ 0.426283] ASID allocator initialised with 32768 entries
10408 10:52:56.140876 <6>[ 0.432867] Serial: AMBA PL011 UART driver
10409 10:52:56.149295 <4>[ 0.441587] Trying to register duplicate clock ID: 134
10410 10:52:56.203307 <6>[ 0.499047] KASLR enabled
10411 10:52:56.218023 <6>[ 0.506883] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10412 10:52:56.224294 <6>[ 0.513897] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10413 10:52:56.230735 <6>[ 0.520388] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10414 10:52:56.237333 <6>[ 0.527394] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10415 10:52:56.243934 <6>[ 0.533878] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10416 10:52:56.250742 <6>[ 0.540884] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10417 10:52:56.257341 <6>[ 0.547372] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10418 10:52:56.263740 <6>[ 0.554377] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10419 10:52:56.266839 <6>[ 0.561892] ACPI: Interpreter disabled.
10420 10:52:56.275770 <6>[ 0.568289] iommu: Default domain type: Translated
10421 10:52:56.282448 <6>[ 0.573401] iommu: DMA domain TLB invalidation policy: strict mode
10422 10:52:56.285608 <5>[ 0.580049] SCSI subsystem initialized
10423 10:52:56.292163 <6>[ 0.584218] usbcore: registered new interface driver usbfs
10424 10:52:56.298716 <6>[ 0.589951] usbcore: registered new interface driver hub
10425 10:52:56.301950 <6>[ 0.595503] usbcore: registered new device driver usb
10426 10:52:56.308766 <6>[ 0.601581] pps_core: LinuxPPS API ver. 1 registered
10427 10:52:56.318830 <6>[ 0.606776] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10428 10:52:56.322532 <6>[ 0.616122] PTP clock support registered
10429 10:52:56.325513 <6>[ 0.620361] EDAC MC: Ver: 3.0.0
10430 10:52:56.332876 <6>[ 0.625494] FPGA manager framework
10431 10:52:56.339700 <6>[ 0.629173] Advanced Linux Sound Architecture Driver Initialized.
10432 10:52:56.342625 <6>[ 0.635949] vgaarb: loaded
10433 10:52:56.349536 <6>[ 0.639126] clocksource: Switched to clocksource arch_sys_counter
10434 10:52:56.353016 <5>[ 0.645559] VFS: Disk quotas dquot_6.6.0
10435 10:52:56.359362 <6>[ 0.649742] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10436 10:52:56.362258 <6>[ 0.656928] pnp: PnP ACPI: disabled
10437 10:52:56.370917 <6>[ 0.663672] NET: Registered PF_INET protocol family
10438 10:52:56.380907 <6>[ 0.669259] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10439 10:52:56.392336 <6>[ 0.681548] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10440 10:52:56.402235 <6>[ 0.690360] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10441 10:52:56.408662 <6>[ 0.698331] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10442 10:52:56.418462 <6>[ 0.707030] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10443 10:52:56.425013 <6>[ 0.716774] TCP: Hash tables configured (established 65536 bind 65536)
10444 10:52:56.431742 <6>[ 0.723630] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10445 10:52:56.441669 <6>[ 0.730830] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10446 10:52:56.448283 <6>[ 0.738530] NET: Registered PF_UNIX/PF_LOCAL protocol family
10447 10:52:56.454818 <6>[ 0.744699] RPC: Registered named UNIX socket transport module.
10448 10:52:56.457924 <6>[ 0.750856] RPC: Registered udp transport module.
10449 10:52:56.465150 <6>[ 0.755789] RPC: Registered tcp transport module.
10450 10:52:56.471383 <6>[ 0.760718] RPC: Registered tcp NFSv4.1 backchannel transport module.
10451 10:52:56.474799 <6>[ 0.767386] PCI: CLS 0 bytes, default 64
10452 10:52:56.477838 <6>[ 0.771741] Unpacking initramfs...
10453 10:52:56.494572 <6>[ 0.783773] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10454 10:52:56.504615 <6>[ 0.792417] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10455 10:52:56.508267 <6>[ 0.801262] kvm [1]: IPA Size Limit: 40 bits
10456 10:52:56.514686 <6>[ 0.805794] kvm [1]: GICv3: no GICV resource entry
10457 10:52:56.517597 <6>[ 0.810815] kvm [1]: disabling GICv2 emulation
10458 10:52:56.524352 <6>[ 0.815500] kvm [1]: GIC system register CPU interface enabled
10459 10:52:56.527501 <6>[ 0.821667] kvm [1]: vgic interrupt IRQ18
10460 10:52:56.534593 <6>[ 0.827188] kvm [1]: VHE mode initialized successfully
10461 10:52:56.541202 <5>[ 0.833591] Initialise system trusted keyrings
10462 10:52:56.547871 <6>[ 0.838418] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10463 10:52:56.556408 <6>[ 0.848568] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10464 10:52:56.563229 <5>[ 0.854957] NFS: Registering the id_resolver key type
10465 10:52:56.566089 <5>[ 0.860253] Key type id_resolver registered
10466 10:52:56.572541 <5>[ 0.864669] Key type id_legacy registered
10467 10:52:56.579116 <6>[ 0.868949] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10468 10:52:56.585877 <6>[ 0.875874] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10469 10:52:56.591892 <6>[ 0.883614] 9p: Installing v9fs 9p2000 file system support
10470 10:52:56.629461 <5>[ 0.921776] Key type asymmetric registered
10471 10:52:56.632612 <5>[ 0.926108] Asymmetric key parser 'x509' registered
10472 10:52:56.642475 <6>[ 0.931260] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10473 10:52:56.645682 <6>[ 0.938876] io scheduler mq-deadline registered
10474 10:52:56.649137 <6>[ 0.943638] io scheduler kyber registered
10475 10:52:56.667919 <6>[ 0.960509] EINJ: ACPI disabled.
10476 10:52:56.700270 <4>[ 0.986065] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 10:52:56.709850 <4>[ 0.996689] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10478 10:52:56.724577 <6>[ 1.017158] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10479 10:52:56.732427 <6>[ 1.025265] printk: console [ttyS0] disabled
10480 10:52:56.760793 <6>[ 1.049915] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10481 10:52:56.767034 <6>[ 1.059393] printk: console [ttyS0] enabled
10482 10:52:56.770346 <6>[ 1.059393] printk: console [ttyS0] enabled
10483 10:52:56.777387 <6>[ 1.068287] printk: bootconsole [mtk8250] disabled
10484 10:52:56.780609 <6>[ 1.068287] printk: bootconsole [mtk8250] disabled
10485 10:52:56.786885 <6>[ 1.079514] SuperH (H)SCI(F) driver initialized
10486 10:52:56.790372 <6>[ 1.084773] msm_serial: driver initialized
10487 10:52:56.804417 <6>[ 1.093765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10488 10:52:56.814214 <6>[ 1.102315] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10489 10:52:56.821518 <6>[ 1.110857] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10490 10:52:56.830812 <6>[ 1.119485] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10491 10:52:56.837737 <6>[ 1.128191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10492 10:52:56.847641 <6>[ 1.136904] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10493 10:52:56.857895 <6>[ 1.145445] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10494 10:52:56.864102 <6>[ 1.154255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10495 10:52:56.874120 <6>[ 1.162804] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10496 10:52:56.885888 <6>[ 1.178361] loop: module loaded
10497 10:52:56.892168 <6>[ 1.184496] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10498 10:52:56.915372 <4>[ 1.207918] mtk-pmic-keys: Failed to locate of_node [id: -1]
10499 10:52:56.921874 <6>[ 1.214736] megasas: 07.719.03.00-rc1
10500 10:52:56.931762 <6>[ 1.224298] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10501 10:52:56.941855 <6>[ 1.234508] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10502 10:52:56.958563 <6>[ 1.251268] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10503 10:52:57.015321 <6>[ 1.301482] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10504 10:52:57.210272 <6>[ 1.502863] Freeing initrd memory: 17220K
10505 10:52:57.220502 <6>[ 1.513100] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10506 10:52:57.231061 <6>[ 1.523975] tun: Universal TUN/TAP device driver, 1.6
10507 10:52:57.234698 <6>[ 1.530017] thunder_xcv, ver 1.0
10508 10:52:57.237674 <6>[ 1.533521] thunder_bgx, ver 1.0
10509 10:52:57.241426 <6>[ 1.537020] nicpf, ver 1.0
10510 10:52:57.252061 <6>[ 1.541021] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10511 10:52:57.254933 <6>[ 1.548497] hns3: Copyright (c) 2017 Huawei Corporation.
10512 10:52:57.261610 <6>[ 1.554085] hclge is initializing
10513 10:52:57.265172 <6>[ 1.557666] e1000: Intel(R) PRO/1000 Network Driver
10514 10:52:57.271275 <6>[ 1.562797] e1000: Copyright (c) 1999-2006 Intel Corporation.
10515 10:52:57.274728 <6>[ 1.568814] e1000e: Intel(R) PRO/1000 Network Driver
10516 10:52:57.281583 <6>[ 1.574030] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10517 10:52:57.288251 <6>[ 1.580215] igb: Intel(R) Gigabit Ethernet Network Driver
10518 10:52:57.294969 <6>[ 1.585866] igb: Copyright (c) 2007-2014 Intel Corporation.
10519 10:52:57.301689 <6>[ 1.591704] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10520 10:52:57.307944 <6>[ 1.598221] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10521 10:52:57.311231 <6>[ 1.604683] sky2: driver version 1.30
10522 10:52:57.318390 <6>[ 1.609669] VFIO - User Level meta-driver version: 0.3
10523 10:52:57.325232 <6>[ 1.617825] usbcore: registered new interface driver usb-storage
10524 10:52:57.331306 <6>[ 1.624269] usbcore: registered new device driver onboard-usb-hub
10525 10:52:57.340717 <6>[ 1.633314] mt6397-rtc mt6359-rtc: registered as rtc0
10526 10:52:57.350701 <6>[ 1.638782] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:53:00 UTC (1685962380)
10527 10:52:57.353764 <6>[ 1.648355] i2c_dev: i2c /dev entries driver
10528 10:52:57.370372 <6>[ 1.659945] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10529 10:52:57.377550 <6>[ 1.670160] sdhci: Secure Digital Host Controller Interface driver
10530 10:52:57.384277 <6>[ 1.676597] sdhci: Copyright(c) Pierre Ossman
10531 10:52:57.390765 <6>[ 1.681993] Synopsys Designware Multimedia Card Interface Driver
10532 10:52:57.394305 <6>[ 1.688617] mmc0: CQHCI version 5.10
10533 10:52:57.401181 <6>[ 1.689140] sdhci-pltfm: SDHCI platform and OF driver helper
10534 10:52:57.408025 <6>[ 1.700788] ledtrig-cpu: registered to indicate activity on CPUs
10535 10:52:57.418879 <6>[ 1.708204] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10536 10:52:57.425325 <6>[ 1.715623] usbcore: registered new interface driver usbhid
10537 10:52:57.428861 <6>[ 1.721450] usbhid: USB HID core driver
10538 10:52:57.435319 <6>[ 1.725705] spi_master spi0: will run message pump with realtime priority
10539 10:52:57.481404 <6>[ 1.767483] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10540 10:52:57.500344 <6>[ 1.782940] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10541 10:52:57.503791 <6>[ 1.796518] mmc0: Command Queue Engine enabled
10542 10:52:57.511006 <6>[ 1.798072] cros-ec-spi spi0.0: Chrome EC device registered
10543 10:52:57.517633 <6>[ 1.801265] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10544 10:52:57.521371 <6>[ 1.814379] mmcblk0: mmc0:0001 DA4128 116 GiB
10545 10:52:57.534738 <6>[ 1.824235] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10546 10:52:57.541497 <6>[ 1.827416] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10547 10:52:57.548147 <6>[ 1.835729] NET: Registered PF_PACKET protocol family
10548 10:52:57.551295 <6>[ 1.840839] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10549 10:52:57.557905 <6>[ 1.844904] 9pnet: Installing 9P2000 support
10550 10:52:57.561505 <6>[ 1.850639] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10551 10:52:57.568127 <5>[ 1.854598] Key type dns_resolver registered
10552 10:52:57.574524 <6>[ 1.860406] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10553 10:52:57.577897 <6>[ 1.864920] registered taskstats version 1
10554 10:52:57.581485 <5>[ 1.875227] Loading compiled-in X.509 certificates
10555 10:52:57.616474 <4>[ 1.902576] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 10:52:57.626706 <4>[ 1.913280] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 10:52:57.636711 <3>[ 1.926067] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10558 10:52:57.648800 <6>[ 1.941544] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10559 10:52:57.655606 <6>[ 1.948423] xhci-mtk 11200000.usb: xHCI Host Controller
10560 10:52:57.662247 <6>[ 1.953926] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10561 10:52:57.672303 <6>[ 1.961779] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10562 10:52:57.679120 <6>[ 1.971236] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10563 10:52:57.685715 <6>[ 1.977314] xhci-mtk 11200000.usb: xHCI Host Controller
10564 10:52:57.692316 <6>[ 1.982797] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10565 10:52:57.698999 <6>[ 1.990456] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10566 10:52:57.705642 <6>[ 1.998185] hub 1-0:1.0: USB hub found
10567 10:52:57.709357 <6>[ 2.002205] hub 1-0:1.0: 1 port detected
10568 10:52:57.715982 <6>[ 2.006547] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10569 10:52:57.722723 <6>[ 2.015155] hub 2-0:1.0: USB hub found
10570 10:52:57.725511 <6>[ 2.019169] hub 2-0:1.0: 1 port detected
10571 10:52:57.733991 <6>[ 2.026372] mtk-msdc 11f70000.mmc: Got CD GPIO
10572 10:52:57.751048 <6>[ 2.040250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10573 10:52:57.757269 <6>[ 2.048297] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10574 10:52:57.767161 <4>[ 2.056296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10575 10:52:57.777271 <6>[ 2.065966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10576 10:52:57.784084 <6>[ 2.074050] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10577 10:52:57.793846 <6>[ 2.082077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10578 10:52:57.800682 <6>[ 2.089995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10579 10:52:57.807503 <6>[ 2.097817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10580 10:52:57.817145 <6>[ 2.105638] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10581 10:52:57.827246 <6>[ 2.116394] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10582 10:52:57.836725 <6>[ 2.124764] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10583 10:52:57.843911 <6>[ 2.133108] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10584 10:52:57.853284 <6>[ 2.141452] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10585 10:52:57.859779 <6>[ 2.149795] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10586 10:52:57.869700 <6>[ 2.158138] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10587 10:52:57.876686 <6>[ 2.166481] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10588 10:52:57.886502 <6>[ 2.174824] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10589 10:52:57.893531 <6>[ 2.183169] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10590 10:52:57.903118 <6>[ 2.191529] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10591 10:52:57.910081 <6>[ 2.199873] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10592 10:52:57.919566 <6>[ 2.208215] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10593 10:52:57.926626 <6>[ 2.216559] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10594 10:52:57.936222 <6>[ 2.224904] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10595 10:52:57.942722 <6>[ 2.233251] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10596 10:52:57.950171 <6>[ 2.242168] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10597 10:52:57.957052 <6>[ 2.249613] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10598 10:52:57.964163 <6>[ 2.256653] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10599 10:52:57.974841 <6>[ 2.263747] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10600 10:52:57.980904 <6>[ 2.271009] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10601 10:52:57.990672 <6>[ 2.277918] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10602 10:52:57.997169 <6>[ 2.287059] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10603 10:52:58.007244 <6>[ 2.296189] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10604 10:52:58.017234 <6>[ 2.305491] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10605 10:52:58.027400 <6>[ 2.314967] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10606 10:52:58.037009 <6>[ 2.324440] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10607 10:52:58.046962 <6>[ 2.333567] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10608 10:52:58.053418 <6>[ 2.343041] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10609 10:52:58.063535 <6>[ 2.352168] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10610 10:52:58.073749 <6>[ 2.361470] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10611 10:52:58.083207 <6>[ 2.371635] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10612 10:52:58.093581 <6>[ 2.383157] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10613 10:52:58.100479 <6>[ 2.393139] Trying to probe devices needed for running init ...
10614 10:52:58.138029 <6>[ 2.427427] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10615 10:52:58.292795 <6>[ 2.584869] hub 1-1:1.0: USB hub found
10616 10:52:58.295301 <6>[ 2.589328] hub 1-1:1.0: 4 ports detected
10617 10:52:58.418334 <6>[ 2.707605] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10618 10:52:58.442937 <6>[ 2.735719] hub 2-1:1.0: USB hub found
10619 10:52:58.446554 <6>[ 2.740116] hub 2-1:1.0: 3 ports detected
10620 10:52:58.617901 <6>[ 2.907428] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10621 10:52:58.750614 <6>[ 3.043608] hub 1-1.4:1.0: USB hub found
10622 10:52:58.754182 <6>[ 3.048288] hub 1-1.4:1.0: 2 ports detected
10623 10:52:58.830330 <6>[ 3.119641] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10624 10:52:59.054103 <6>[ 3.343402] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10625 10:52:59.245813 <6>[ 3.535401] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10626 10:53:10.403516 <6>[ 14.699995] ALSA device list:
10627 10:53:10.409979 <6>[ 14.703248] No soundcards found.
10628 10:53:10.422854 <6>[ 14.715683] Freeing unused kernel memory: 8384K
10629 10:53:10.425436 <6>[ 14.720615] Run /init as init process
10630 10:53:10.435084 Loading, please wait...
10631 10:53:10.455036 Starting version 247.3-7+deb11u2
10632 10:53:10.779790 <6>[ 15.070245] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10633 10:53:10.792333 <6>[ 15.085683] remoteproc remoteproc0: scp is available
10634 10:53:10.802427 <4>[ 15.091085] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10635 10:53:10.808887 <6>[ 15.100932] remoteproc remoteproc0: powering up scp
10636 10:53:10.815729 <6>[ 15.103572] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10637 10:53:10.824958 <4>[ 15.106139] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10638 10:53:10.832012 <6>[ 15.125142] mc: Linux media interface: v0.10
10639 10:53:10.838601 <3>[ 15.126750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 10:53:10.844919 <3>[ 15.127176] remoteproc remoteproc0: request_firmware failed: -2
10641 10:53:10.851579 <6>[ 15.136011] usbcore: registered new interface driver r8152
10642 10:53:10.858256 <3>[ 15.137873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10643 10:53:10.868120 <6>[ 15.154162] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10644 10:53:10.874924 <3>[ 15.157874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10645 10:53:10.885133 <6>[ 15.165477] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10646 10:53:10.887700 <6>[ 15.166807] videodev: Linux video capture interface: v2.00
10647 10:53:10.897999 <4>[ 15.183938] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10648 10:53:10.904842 <4>[ 15.183938] Fallback method does not support PEC.
10649 10:53:10.911684 <6>[ 15.187952] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10650 10:53:10.914762 <6>[ 15.188839] Bluetooth: Core ver 2.22
10651 10:53:10.924960 <4>[ 15.214478] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10652 10:53:10.928186 <6>[ 15.215499] NET: Registered PF_BLUETOOTH protocol family
10653 10:53:10.938796 <3>[ 15.222109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 10:53:10.944917 <6>[ 15.227435] Bluetooth: HCI device and connection manager initialized
10655 10:53:10.952550 <3>[ 15.229019] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 10:53:10.959041 <3>[ 15.235508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 10:53:10.969129 <4>[ 15.236137] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10658 10:53:10.971844 <6>[ 15.242109] Bluetooth: HCI socket layer initialized
10659 10:53:10.982163 <3>[ 15.250871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 10:53:10.989011 <3>[ 15.251821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 10:53:10.994853 <6>[ 15.258965] Bluetooth: L2CAP socket layer initialized
10662 10:53:11.001871 <3>[ 15.266259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 10:53:11.008394 <6>[ 15.271400] Bluetooth: SCO socket layer initialized
10664 10:53:11.014915 <3>[ 15.279464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 10:53:11.024956 <6>[ 15.288012] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10666 10:53:11.034926 <6>[ 15.288642] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10667 10:53:11.044751 <3>[ 15.293580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 10:53:11.051549 <6>[ 15.295466] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10669 10:53:11.057737 <6>[ 15.315070] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10670 10:53:11.068260 <4>[ 15.318711] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10671 10:53:11.074871 <4>[ 15.318720] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10672 10:53:11.080882 <3>[ 15.324957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 10:53:11.087690 <6>[ 15.333960] pci_bus 0000:00: root bus resource [bus 00-ff]
10674 10:53:11.097653 <3>[ 15.342045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 10:53:11.103924 <6>[ 15.347373] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10676 10:53:11.114498 <6>[ 15.349165] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10677 10:53:11.123923 <6>[ 15.349171] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10678 10:53:11.130935 <3>[ 15.356060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 10:53:11.137723 <6>[ 15.365231] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10680 10:53:11.143914 <6>[ 15.365648] usbcore: registered new interface driver cdc_ether
10681 10:53:11.150834 <3>[ 15.373257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 10:53:11.157539 <6>[ 15.373322] r8152 2-1.3:1.0 eth0: v1.12.13
10683 10:53:11.164079 <6>[ 15.373561] usbcore: registered new interface driver r8153_ecm
10684 10:53:11.170542 <6>[ 15.381298] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10685 10:53:11.177050 <6>[ 15.382186] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10686 10:53:11.183535 <3>[ 15.387043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 10:53:11.190308 <3>[ 15.387051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 10:53:11.200136 <3>[ 15.387061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 10:53:11.207136 <6>[ 15.388825] usbcore: registered new interface driver btusb
10690 10:53:11.216954 <4>[ 15.389506] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10691 10:53:11.223484 <3>[ 15.389518] Bluetooth: hci0: Failed to load firmware file (-2)
10692 10:53:11.226717 <3>[ 15.389523] Bluetooth: hci0: Failed to set up firmware (-2)
10693 10:53:11.239295 <4>[ 15.389527] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10694 10:53:11.243011 <6>[ 15.395361] pci 0000:00:00.0: supports D1 D2
10695 10:53:11.249706 <3>[ 15.404439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 10:53:11.259275 <3>[ 15.404472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 10:53:11.265987 <6>[ 15.405639] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10698 10:53:11.279178 <6>[ 15.406751] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10699 10:53:11.285591 <6>[ 15.406886] usbcore: registered new interface driver uvcvideo
10700 10:53:11.292464 <6>[ 15.411586] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10701 10:53:11.298631 <6>[ 15.430408] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10702 10:53:11.308532 <6>[ 15.598674] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10703 10:53:11.315389 <6>[ 15.607204] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10704 10:53:11.321954 <6>[ 15.613511] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10705 10:53:11.328329 <6>[ 15.621005] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10706 10:53:11.338821 <6>[ 15.628495] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10707 10:53:11.341645 <6>[ 15.636085] pci 0000:01:00.0: supports D1 D2
10708 10:53:11.348396 <6>[ 15.640621] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10709 10:53:11.368832 <6>[ 15.659390] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10710 10:53:11.375910 <6>[ 15.666309] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10711 10:53:11.382174 <6>[ 15.674403] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10712 10:53:11.391994 <6>[ 15.682412] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10713 10:53:11.398940 <6>[ 15.690419] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10714 10:53:11.409578 <6>[ 15.698427] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10715 10:53:11.411846 <6>[ 15.706434] pci 0000:00:00.0: PCI bridge to [bus 01]
10716 10:53:11.421922 <6>[ 15.711656] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10717 10:53:11.428522 <6>[ 15.719815] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10718 10:53:11.435554 <6>[ 15.727079] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10719 10:53:11.441685 <6>[ 15.733743] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10720 10:53:11.459493 <5>[ 15.749775] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10721 10:53:11.478421 <5>[ 15.768569] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10722 10:53:11.484861 <4>[ 15.775455] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10723 10:53:11.491486 <6>[ 15.784402] cfg80211: failed to load regulatory.db
10724 10:53:11.538053 <6>[ 15.827580] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10725 10:53:11.543645 <6>[ 15.835091] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10726 10:53:11.568123 <6>[ 15.861791] mt7921e 0000:01:00.0: ASIC revision: 79610010
10727 10:53:11.676777 <4>[ 15.963410] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 10:53:11.679525 Begin: Loading essential drivers ... done.
10729 10:53:11.686468 Begin: Running /scripts/init-premount ... done.
10730 10:53:11.692850 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10731 10:53:11.702787 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10732 10:53:11.706603 Device /sys/class/net/enx002432307c7b found
10733 10:53:11.707166 done.
10734 10:53:11.756723 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10735 10:53:11.798437 <4>[ 16.085533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10736 10:53:11.917934 <4>[ 16.205051] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 10:53:12.033493 <4>[ 16.320935] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 10:53:12.149589 <4>[ 16.436711] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 10:53:12.266020 <4>[ 16.552739] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10740 10:53:12.381326 <4>[ 16.668782] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10741 10:53:12.497504 <4>[ 16.784665] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10742 10:53:12.613103 <4>[ 16.900636] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 10:53:12.729414 <4>[ 17.016556] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 10:53:12.778869 <6>[ 17.072915] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10745 10:53:12.836874 <3>[ 17.130493] mt7921e 0000:01:00.0: hardware init failed
10746 10:53:12.844728 IP-Config: no response after 2 secs - giving up
10747 10:53:12.896875 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10748 10:53:12.900380 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10749 10:53:12.906735 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10750 10:53:12.916764 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10751 10:53:12.923262 host : mt8192-asurada-spherion-r0-cbg-2
10752 10:53:12.929656 domain : lava-rack
10753 10:53:12.932745 rootserver: 192.168.201.1 rootpath:
10754 10:53:12.932827 filename :
10755 10:53:12.957534 done.
10756 10:53:12.966927 Begin: Running /scripts/nfs-bottom ... done.
10757 10:53:12.985529 Begin: Running /scripts/init-bottom ... done.
10758 10:53:14.180724 <6>[ 18.474877] NET: Registered PF_INET6 protocol family
10759 10:53:14.187954 <6>[ 18.481929] Segment Routing with IPv6
10760 10:53:14.191294 <6>[ 18.485963] In-situ OAM (IOAM) with IPv6
10761 10:53:14.319155 <30>[ 18.593288] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10762 10:53:14.322248 <30>[ 18.617100] systemd[1]: Detected architecture arm64.
10763 10:53:14.345824
10764 10:53:14.349515 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10765 10:53:14.350046
10766 10:53:14.368636 <30>[ 18.662637] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10767 10:53:15.077997 <30>[ 19.369022] systemd[1]: Queued start job for default target Graphical Interface.
10768 10:53:15.114480 <30>[ 19.408413] systemd[1]: Created slice system-getty.slice.
10769 10:53:15.120802 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10770 10:53:15.137614 <30>[ 19.432020] systemd[1]: Created slice system-modprobe.slice.
10771 10:53:15.144651 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10772 10:53:15.162222 <30>[ 19.456553] systemd[1]: Created slice system-serial\x2dgetty.slice.
10773 10:53:15.172476 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10774 10:53:15.185737 <30>[ 19.479919] systemd[1]: Created slice User and Session Slice.
10775 10:53:15.192336 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10776 10:53:15.213577 <30>[ 19.503971] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10777 10:53:15.222725 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10778 10:53:15.241227 <30>[ 19.531571] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10779 10:53:15.247488 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10780 10:53:15.268138 <30>[ 19.555520] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10781 10:53:15.274622 <30>[ 19.567552] systemd[1]: Reached target Local Encrypted Volumes.
10782 10:53:15.281236 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10783 10:53:15.297606 <30>[ 19.591763] systemd[1]: Reached target Paths.
10784 10:53:15.300926 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10785 10:53:15.317190 <30>[ 19.611444] systemd[1]: Reached target Remote File Systems.
10786 10:53:15.323979 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10787 10:53:15.337718 <30>[ 19.631393] systemd[1]: Reached target Slices.
10788 10:53:15.340234 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10789 10:53:15.357623 <30>[ 19.651386] systemd[1]: Reached target Swap.
10790 10:53:15.360772 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10791 10:53:15.381056 <30>[ 19.671756] systemd[1]: Listening on initctl Compatibility Named Pipe.
10792 10:53:15.387672 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10793 10:53:15.394913 <30>[ 19.687502] systemd[1]: Listening on Journal Audit Socket.
10794 10:53:15.400826 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10795 10:53:15.415195 <30>[ 19.708647] systemd[1]: Listening on Journal Socket (/dev/log).
10796 10:53:15.420804 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10797 10:53:15.438063 <30>[ 19.732135] systemd[1]: Listening on Journal Socket.
10798 10:53:15.444329 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10799 10:53:15.462305 <30>[ 19.753002] systemd[1]: Listening on Network Service Netlink Socket.
10800 10:53:15.469040 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10801 10:53:15.484378 <30>[ 19.778462] systemd[1]: Listening on udev Control Socket.
10802 10:53:15.491299 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10803 10:53:15.505618 <30>[ 19.799674] systemd[1]: Listening on udev Kernel Socket.
10804 10:53:15.512349 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10805 10:53:15.561720 <30>[ 19.855730] systemd[1]: Mounting Huge Pages File System...
10806 10:53:15.567920 Mounting [0;1;39mHuge Pages File System[0m...
10807 10:53:15.586472 <30>[ 19.877873] systemd[1]: Mounting POSIX Message Queue File System...
10808 10:53:15.589589 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10809 10:53:15.607229 <30>[ 19.901711] systemd[1]: Mounting Kernel Debug File System...
10810 10:53:15.614245 Mounting [0;1;39mKernel Debug File System[0m...
10811 10:53:15.632272 <30>[ 19.923735] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10812 10:53:15.646846 <30>[ 19.938003] systemd[1]: Starting Create list of static device nodes for the current kernel...
10813 10:53:15.652977 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10814 10:53:15.676218 <30>[ 19.970621] systemd[1]: Starting Load Kernel Module configfs...
10815 10:53:15.682401 Starting [0;1;39mLoad Kernel Module configfs[0m...
10816 10:53:15.699662 <30>[ 19.994213] systemd[1]: Starting Load Kernel Module drm...
10817 10:53:15.706273 Starting [0;1;39mLoad Kernel Module drm[0m...
10818 10:53:15.723449 <30>[ 20.018071] systemd[1]: Starting Load Kernel Module fuse...
10819 10:53:15.730486 Starting [0;1;39mLoad Kernel Module fuse[0m...
10820 10:53:15.770142 <6>[ 20.064426] fuse: init (API version 7.37)
10821 10:53:15.780188 <30>[ 20.064717] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10822 10:53:15.789044 <30>[ 20.083014] systemd[1]: Starting Journal Service...
10823 10:53:15.795241 Starting [0;1;39mJournal Service[0m...
10824 10:53:15.841426 <30>[ 20.135928] systemd[1]: Starting Load Kernel Modules...
10825 10:53:15.847799 Starting [0;1;39mLoad Kernel Modules[0m...
10826 10:53:15.867358 <30>[ 20.158314] systemd[1]: Starting Remount Root and Kernel File Systems...
10827 10:53:15.874459 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10828 10:53:15.892227 <30>[ 20.186393] systemd[1]: Starting Coldplug All udev Devices...
10829 10:53:15.898788 Starting [0;1;39mColdplug All udev Devices[0m...
10830 10:53:15.916022 <30>[ 20.210348] systemd[1]: Mounted Huge Pages File System.
10831 10:53:15.922566 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10832 10:53:15.937710 <30>[ 20.231993] systemd[1]: Mounted POSIX Message Queue File System.
10833 10:53:15.944877 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10834 10:53:15.956437 <3>[ 20.247459] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 10:53:15.963237 <30>[ 20.257057] systemd[1]: Mounted Kernel Debug File System.
10836 10:53:15.969289 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10837 10:53:15.986595 <3>[ 20.277796] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 10:53:15.996826 <30>[ 20.287717] systemd[1]: Finished Create list of static device nodes for the current kernel.
10839 10:53:16.006309 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10840 10:53:16.022218 <30>[ 20.316362] systemd[1]: modprobe@configfs.service: Succeeded.
10841 10:53:16.028976 <30>[ 20.323293] systemd[1]: Finished Load Kernel Module configfs.
10842 10:53:16.038832 <3>[ 20.324843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 10:53:16.045701 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10844 10:53:16.062742 <30>[ 20.356254] systemd[1]: modprobe@drm.service: Succeeded.
10845 10:53:16.071937 <3>[ 20.359854] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 10:53:16.075422 <30>[ 20.362546] systemd[1]: Finished Load Kernel Module drm.
10847 10:53:16.083002 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10848 10:53:16.098603 <30>[ 20.392551] systemd[1]: modprobe@fuse.service: Succeeded.
10849 10:53:16.108465 <3>[ 20.394594] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 10:53:16.114720 <30>[ 20.398882] systemd[1]: Finished Load Kernel Module fuse.
10851 10:53:16.118002 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10852 10:53:16.134890 <30>[ 20.428640] systemd[1]: Finished Load Kernel Modules.
10853 10:53:16.144180 <3>[ 20.429773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 10:53:16.151440 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10855 10:53:16.167405 <30>[ 20.460715] systemd[1]: Finished Remount Root and Kernel File Systems.
10856 10:53:16.177490 <3>[ 20.467425] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 10:53:16.184109 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10858 10:53:16.208434 <3>[ 20.499529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 10:53:16.221256 <30>[ 20.515668] systemd[1]: Mounting FUSE Control File System...
10860 10:53:16.228082 Mounting [0;1;39mFUSE Control File System[0m...
10861 10:53:16.242075 <3>[ 20.532836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 10:53:16.253917 <30>[ 20.544664] systemd[1]: Mounting Kernel Configuration File System...
10863 10:53:16.257111 Mounting [0;1;39mKernel Configuration File System[0m...
10864 10:53:16.272084 <3>[ 20.563184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 10:53:16.290494 <30>[ 20.580507] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10866 10:53:16.299930 <30>[ 20.589530] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10867 10:53:16.321740 <30>[ 20.616031] systemd[1]: Starting Load/Save Random Seed...
10868 10:53:16.328340 Starting [0;1;39mLoad/Save Random Seed[0m...
10869 10:53:16.343588 <30>[ 20.637910] systemd[1]: Starting Apply Kernel Variables...
10870 10:53:16.349952 Starting [0;1;39mApply Kernel Variables[0m...
10871 10:53:16.374271 <30>[ 20.667732] systemd[1]: Starting Create System Users...
10872 10:53:16.377415 Starting [0;1;39mCreate System Users[0m...
10873 10:53:16.394533 <30>[ 20.689038] systemd[1]: Started Journal Service.
10874 10:53:16.401464 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10875 10:53:16.416009 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10876 10:53:16.440777 <4>[ 20.725126] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10877 10:53:16.447168 <3>[ 20.740801] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10878 10:53:16.454966 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10879 10:53:16.470873 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10880 10:53:16.490084 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10881 10:53:16.501082 See 'systemctl status systemd-udev-trigger.service' for details.
10882 10:53:16.518339 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10883 10:53:16.534027 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10884 10:53:16.570217 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10885 10:53:16.587361 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10886 10:53:16.632677 <46>[ 20.924205] systemd-journald[294]: Received client request to flush runtime journal.
10887 10:53:17.396758 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10888 10:53:17.413215 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10889 10:53:17.432928 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10890 10:53:17.488774 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10891 10:53:18.022431 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10892 10:53:18.061079 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10893 10:53:18.133686 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10894 10:53:18.193846 Starting [0;1;39mNetwork Service[0m...
10895 10:53:18.409755 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10896 10:53:18.481209 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10897 10:53:18.505303 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10898 10:53:18.707106 <6>[ 23.002278] remoteproc remoteproc0: powering up scp
10899 10:53:18.747975 <4>[ 23.039046] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10900 10:53:18.753969 <3>[ 23.049037] remoteproc remoteproc0: request_firmware failed: -2
10901 10:53:18.765026 <3>[ 23.055229] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10902 10:53:18.899735 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10903 10:53:18.916982 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10904 10:53:18.965786 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10905 10:53:18.981473 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10906 10:53:19.001391 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10907 10:53:19.021684 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10908 10:53:19.041424 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10909 10:53:19.093431 Starting [0;1;39mNetwork Name Resolution[0m...
10910 10:53:19.119920 Starting [0;1;39mNetwork Time Synchronization[0m...
10911 10:53:19.135546 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10912 10:53:19.189760 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10913 10:53:19.378244 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10914 10:53:19.393283 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10915 10:53:19.412477 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10916 10:53:19.424771 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10917 10:53:19.440718 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10918 10:53:19.580522 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10919 10:53:19.615236 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10920 10:53:19.647487 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10921 10:53:19.854695 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10922 10:53:19.868079 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10923 10:53:20.122470 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10924 10:53:20.136654 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10925 10:53:20.152403 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10926 10:53:20.184473 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10927 10:53:20.420330 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10928 10:53:20.777059 Starting [0;1;39mUser Login Management[0m...
10929 10:53:20.793263 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10930 10:53:20.809668 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10931 10:53:20.827524 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10932 10:53:20.869079 Starting [0;1;39mPermit User Sessions[0m...
10933 10:53:20.984815 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10934 10:53:21.037009 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10935 10:53:21.068413 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10936 10:53:21.086417 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10937 10:53:21.106086 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10938 10:53:21.122498 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10939 10:53:21.142291 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10940 10:53:21.156957 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10941 10:53:21.213084 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10942 10:53:21.263106 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10943 10:53:21.323288
10944 10:53:21.323800
10945 10:53:21.326479 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10946 10:53:21.326911
10947 10:53:21.360404 debian-bullseye-arm64 login: root (automatic login)
10948 10:53:21.360845
10949 10:53:21.361182
10950 10:53:21.688939 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
10951 10:53:21.689431
10952 10:53:21.694986 The programs included with the Debian GNU/Linux system are free software;
10953 10:53:21.701718 the exact distribution terms for each program are described in the
10954 10:53:21.705454 individual files in /usr/share/doc/*/copyright.
10955 10:53:21.705873
10956 10:53:21.711538 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10957 10:53:21.711959 permitted by applicable law.
10958 10:53:21.820621 Matched prompt #10: / #
10960 10:53:21.821763 Setting prompt string to ['/ #']
10961 10:53:21.822199 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10963 10:53:21.823186 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10964 10:53:21.823627 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10965 10:53:21.823988 Setting prompt string to ['/ #']
10966 10:53:21.824322 Forcing a shell prompt, looking for ['/ #']
10968 10:53:21.875130 / #
10969 10:53:21.875804 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10970 10:53:21.876410 Waiting using forced prompt support (timeout 00:02:30)
10971 10:53:21.881433
10972 10:53:21.882358 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10973 10:53:21.882892 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
10975 10:53:21.984167 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59'
10976 10:53:21.991078 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590978/extract-nfsrootfs-vq1g6h59'
10978 10:53:22.092897 / # export NFS_SERVER_IP='192.168.201.1'
10979 10:53:22.099762 export NFS_SERVER_IP='192.168.201.1'
10980 10:53:22.100719 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10981 10:53:22.101243 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
10982 10:53:22.101715 end: 2 depthcharge-action (duration 00:01:41) [common]
10983 10:53:22.102216 start: 3 lava-test-retry (timeout 00:30:00) [common]
10984 10:53:22.102691 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10985 10:53:22.103099 Using namespace: common
10987 10:53:22.204229 / # #
10988 10:53:22.204415 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10989 10:53:22.209288 #
10990 10:53:22.209556 Using /lava-10590978
10992 10:53:22.310109 / # export SHELL=/bin/sh
10993 10:53:22.316844 export SHELL=/bin/sh
10995 10:53:22.418438 / # . /lava-10590978/environment
10996 10:53:22.424782 . /lava-10590978/environment
10998 10:53:22.532780 / # /lava-10590978/bin/lava-test-runner /lava-10590978/0
10999 10:53:22.533407 Test shell timeout: 10s (minimum of the action and connection timeout)
11000 10:53:22.539343 /lava-10590978/bin/lava-test-runner /lava-10590978/0
11001 10:53:22.812669 + export TESTRUN_ID=0_lc-compliance
11002 10:53:22.819547 + cd /lava-10590978/0/tests/0_lc-compliance
11003 10:53:22.819979 + cat uuid
11004 10:53:22.828433 + UUID=10590978_1.6.2.3.1
11005 10:53:22.828922 + set +x
11006 10:53:22.835106 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10590978_1.6.2.3.1>
11007 10:53:22.835790 Received signal: <STARTRUN> 0_lc-compliance 10590978_1.6.2.3.1
11008 10:53:22.836198 Starting test lava.0_lc-compliance (10590978_1.6.2.3.1)
11009 10:53:22.836610 Skipping test definition patterns.
11010 10:53:22.838323 + /usr/bin/lc-compliance-parser.sh
11011 10:53:24.054517 [0:00:28.231730385] [400] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11012 10:53:24.057595 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11013 10:53:24.067321 [0:00:28.245793000] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11014 10:53:24.120197 [0:00:28.298217923] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11015 10:53:24.155508 [==========] Running 120 tests from 1 test suite.
11016 10:53:24.171769 [0:00:28.349591539] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11017 10:53:24.222230 [0:00:28.399738923] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11018 10:53:24.242893 [----------] Global test environment set-up.
11019 10:53:24.328676 [----------] 120 tests from CaptureTests/SingleStream
11020 10:53:24.407959 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11021 10:53:24.473914 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11022 10:53:24.474211 Received signal: <TESTSET> START CaptureTests/SingleStream
11023 10:53:24.474297 Starting test_set CaptureTests/SingleStream
11024 10:53:24.477204 Camera needs 4 requests, can't test only 1
11025 10:53:24.582817 [0:00:28.760676231] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11026 10:53:24.586211 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11027 10:53:24.670859
11028 10:53:24.770870 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (53 ms)
11029 10:53:24.894135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11030 10:53:24.894888 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11032 10:53:24.916368 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11033 10:53:24.983006 Camera needs 4 requests, can't test only 2
11034 10:53:25.045297 [0:00:29.223018693] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11035 10:53:25.085873 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11036 10:53:25.175836
11037 10:53:25.278206 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (51 ms)
11038 10:53:25.406610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11039 10:53:25.407407 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11041 10:53:25.429837 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11042 10:53:25.501566 Camera needs 4 requests, can't test only 3
11043 10:53:25.597796 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11044 10:53:25.699287
11045 10:53:25.769852 [0:00:29.947194462] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11046 10:53:25.807505 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (50 ms)
11047 10:53:25.920804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11048 10:53:25.921573 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11050 10:53:25.941887 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11051 10:53:26.005730 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (361 ms)
11052 10:53:26.115310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11053 10:53:26.116138 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11055 10:53:26.136580 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11056 10:53:26.203235 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (461 ms)
11057 10:53:26.326801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11058 10:53:26.327644 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11060 10:53:26.345916 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11061 10:53:26.409249 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (723 ms)
11062 10:53:26.507112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11063 10:53:26.507424 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11065 10:53:26.525916 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11066 10:53:26.656933 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (896 ms)
11067 10:53:26.666608 [0:00:30.844933231] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11068 10:53:26.763345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11069 10:53:26.764182 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11071 10:53:26.780730 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11072 10:53:28.052435 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1396 ms)
11073 10:53:28.062270 [0:00:32.240578462] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11074 10:53:28.150408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11075 10:53:28.150704 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11077 10:53:28.164915 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11078 10:53:30.147415 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2095 ms)
11079 10:53:30.157091 [0:00:34.335603155] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11080 10:53:30.260413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11081 10:53:30.260706 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11083 10:53:30.276455 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11084 10:53:33.407779 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3261 ms)
11085 10:53:33.417375 [0:00:37.596359924] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11086 10:53:33.471788 [0:00:37.650552386] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11087 10:53:33.507145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11088 10:53:33.507438 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11090 10:53:33.522174 [0:00:37.701191539] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 10:53:33.525532 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11092 10:53:33.572986 [0:00:37.751912924] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11093 10:53:33.575992 Camera needs 4 requests, can't test only 1
11094 10:53:33.646910 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11095 10:53:33.721096
11096 10:53:33.808967 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11097 10:53:33.898249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11098 10:53:33.898584 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11100 10:53:33.915348 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11101 10:53:33.934376 [0:00:38.113075001] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11102 10:53:33.969309 Camera needs 4 requests, can't test only 2
11103 10:53:34.046227 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11104 10:53:34.126173
11105 10:53:34.208250 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (52 ms)
11106 10:53:34.310872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11107 10:53:34.311179 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11109 10:53:34.329119 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11110 10:53:34.396523 [0:00:38.575582616] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11111 10:53:34.400001 Camera needs 4 requests, can't test only 3
11112 10:53:34.475744 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11113 10:53:34.547244
11114 10:53:34.642380 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (50 ms)
11115 10:53:34.738053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11116 10:53:34.738379 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11118 10:53:34.754737 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11119 10:53:34.811703 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (361 ms)
11120 10:53:34.909993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11121 10:53:34.910298 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11123 10:53:34.926894 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11124 10:53:34.982134 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (462 ms)
11125 10:53:35.074645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11126 10:53:35.074939 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11128 10:53:35.091715 [0:00:39.270914847] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 10:53:35.095196 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11130 10:53:35.141498 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (694 ms)
11131 10:53:35.230828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11132 10:53:35.231157 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11134 10:53:35.249465 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11135 10:53:35.978474 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (896 ms)
11136 10:53:35.991719 [0:00:40.167480463] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 10:53:36.071812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11138 10:53:36.072116 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11140 10:53:36.087816 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11141 10:53:37.372494 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1394 ms)
11142 10:53:37.386139 [0:00:41.562059924] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11143 10:53:37.473487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11144 10:53:37.474211 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11146 10:53:37.493280 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11147 10:53:39.466952 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2095 ms)
11148 10:53:39.480014 [0:00:43.656568001] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 10:53:39.579396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11150 10:53:39.580122 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11152 10:53:39.595999 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11153 10:53:41.855153 <6>[ 46.155368] vpu: disabling
11154 10:53:41.857765 <6>[ 46.158419] vproc2: disabling
11155 10:53:41.861856 <6>[ 46.161689] vproc1: disabling
11156 10:53:41.864512 <6>[ 46.164950] vaud18: disabling
11157 10:53:41.871024 <6>[ 46.168351] vsram_others: disabling
11158 10:53:41.874452 <6>[ 46.172220] va09: disabling
11159 10:53:41.877919 <6>[ 46.175327] vsram_md: disabling
11160 10:53:41.878380 <6>[ 46.178810] Vgpu: disabling
11161 10:53:42.663354 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3197 ms)
11162 10:53:42.676402 [0:00:46.853396078] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11163 10:53:42.724676 [0:00:46.904474694] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11164 10:53:42.776379 [0:00:46.956487617] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 10:53:42.782991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11166 10:53:42.783249 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11168 10:53:42.800336 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11169 10:53:42.828215 [0:00:47.007961309] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11170 10:53:42.863998 Camera needs 4 requests, can't test only 1
11171 10:53:42.946301 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11172 10:53:43.031114
11173 10:53:43.131497 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
11174 10:53:43.189202 [0:00:47.368945309] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 10:53:43.249803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11176 10:53:43.250546 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11178 10:53:43.267853 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11179 10:53:43.326263 Camera needs 4 requests, can't test only 2
11180 10:53:43.406862 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11181 10:53:43.485697
11182 10:53:43.571417 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (51 ms)
11183 10:53:43.651877 [0:00:47.832109925] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 10:53:43.670258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11185 10:53:43.670532 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11187 10:53:43.685710 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11188 10:53:43.741496 Camera needs 4 requests, can't test only 3
11189 10:53:43.825408 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11190 10:53:43.910592
11191 10:53:44.003052 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (53 ms)
11192 10:53:44.102238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11193 10:53:44.102637 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11195 10:53:44.120682 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11196 10:53:44.177011 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (361 ms)
11197 10:53:44.281006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11198 10:53:44.281288 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11200 10:53:44.299757 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11201 10:53:44.344351 [0:00:48.524256155] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11202 10:53:44.363315 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (462 ms)
11203 10:53:44.457656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11204 10:53:44.457955 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11206 10:53:44.471748 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11207 10:53:44.522767 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (693 ms)
11208 10:53:44.615939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11209 10:53:44.616252 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11211 10:53:44.633226 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11212 10:53:45.232018 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (895 ms)
11213 10:53:45.244763 [0:00:49.422261002] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 10:53:45.331619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11215 10:53:45.332383 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11217 10:53:45.350634 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11218 10:53:46.627002 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1396 ms)
11219 10:53:46.639733 [0:00:50.816577694] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11220 10:53:46.723359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11221 10:53:46.723682 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11223 10:53:46.740907 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11224 10:53:48.692902 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2063 ms)
11225 10:53:48.703065 [0:00:52.879417848] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 10:53:48.803330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11227 10:53:48.804148 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11229 10:53:48.823078 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11230 10:53:51.916702 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3227 ms)
11231 10:53:51.929973 [0:00:56.107320541] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 10:53:51.977898 [0:00:56.158785079] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11233 10:53:52.029850 [0:00:56.210519975] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 10:53:52.045909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11235 10:53:52.046599 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11237 10:53:52.066231 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11238 10:53:52.081397 [0:00:56.262211879] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11239 10:53:52.128750 Camera needs 4 requests, can't test only 1
11240 10:53:52.219142 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11241 10:53:52.312175
11242 10:53:52.414806 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11243 10:53:52.442957 [0:00:56.623771359] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 10:53:52.538045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11245 10:53:52.538819 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11247 10:53:52.559213 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11248 10:53:52.621417 Camera needs 4 requests, can't test only 2
11249 10:53:52.722579 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11250 10:53:52.813166
11251 10:53:52.906725 [0:00:57.087775726] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11252 10:53:52.923643 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (50 ms)
11253 10:53:53.028208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11254 10:53:53.028536 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11256 10:53:53.045026 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11257 10:53:53.104165 Camera needs 4 requests, can't test only 3
11258 10:53:53.199821 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11259 10:53:53.294221
11260 10:53:53.395484 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (52 ms)
11261 10:53:53.506728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11262 10:53:53.507025 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11264 10:53:53.524139 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11265 10:53:53.583367 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (362 ms)
11266 10:53:53.601263 [0:00:57.782570423] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 10:53:53.691577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11268 10:53:53.691887 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11270 10:53:53.712741 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11271 10:53:53.773492 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (464 ms)
11272 10:53:53.870369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11273 10:53:53.870695 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11275 10:53:53.887330 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11276 10:53:53.946205 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (695 ms)
11277 10:53:54.052470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11278 10:53:54.052783 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11280 10:53:54.072399 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11281 10:53:54.487344 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (894 ms)
11282 10:53:54.500247 [0:00:58.677994143] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 10:53:54.610239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11284 10:53:54.611054 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11286 10:53:54.632990 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11287 10:53:55.818992 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1332 ms)
11288 10:53:55.832269 [0:01:00.009972199] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 10:53:55.940424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11290 10:53:55.941185 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11292 10:53:55.958449 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11293 10:53:57.946237 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2127 ms)
11294 10:53:57.959126 [0:01:02.136950283] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 10:53:58.070025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11296 10:53:58.070846 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11298 10:53:58.089295 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11299 10:54:01.172898 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3227 ms)
11300 10:54:01.185888 [0:01:05.365149312] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 10:54:01.235491 [0:01:05.417448565] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11302 10:54:01.288862 [0:01:05.469773280] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 10:54:01.299510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11304 10:54:01.300204 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11306 10:54:01.316552 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11307 10:54:01.338371 [0:01:05.520316458] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 10:54:01.383157 Camera needs 4 requests, can't test only 1
11309 10:54:01.471882 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11310 10:54:01.562612
11311 10:54:01.662698 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (55 ms)
11312 10:54:01.787628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11313 10:54:01.788464 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11315 10:54:01.810112 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11316 10:54:01.866216 Camera needs 4 requests, can't test only 2
11317 10:54:01.967247 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11318 10:54:02.062497
11319 10:54:02.171458 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (51 ms)
11320 10:54:02.274934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11321 10:54:02.275707 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11323 10:54:02.293872 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11324 10:54:02.354666 Camera needs 4 requests, can't test only 3
11325 10:54:02.456518 [0:01:06.638354014] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 10:54:02.459390 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11327 10:54:02.547836
11328 10:54:02.640352 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11329 10:54:02.757692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11330 10:54:02.758529 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11332 10:54:02.777059 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11333 10:54:02.847899 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1117 ms)
11334 10:54:02.968481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11335 10:54:02.969272 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11337 10:54:02.988369 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11338 10:54:03.890355 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1442 ms)
11339 10:54:03.902711 [0:01:08.082381350] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11340 10:54:04.006843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11341 10:54:04.007607 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11343 10:54:04.026800 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11344 10:54:05.935765 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2045 ms)
11345 10:54:05.947507 [0:01:10.125878331] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 10:54:06.051130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11347 10:54:06.051888 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11349 10:54:06.071933 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11350 10:54:08.612850 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2679 ms)
11351 10:54:08.625484 [0:01:12.805275870] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 10:54:08.736129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11353 10:54:08.736932 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11355 10:54:08.759213 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11356 10:54:12.721961 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4110 ms)
11357 10:54:12.734699 [0:01:16.913008800] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 10:54:12.844101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11359 10:54:12.844855 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11361 10:54:12.865633 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11362 10:54:19.023572 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6302 ms)
11363 10:54:19.036600 [0:01:23.215301951] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 10:54:19.144501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11365 10:54:19.145270 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11367 10:54:19.165287 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11368 10:54:28.757727 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9734 ms)
11369 10:54:28.770173 [0:01:32.950043445] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 10:54:28.816185 [0:01:33.001029051] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11371 10:54:28.866150 [0:01:33.051493272] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11372 10:54:28.876530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11373 10:54:28.877239 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11375 10:54:28.898052 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11376 10:54:28.917297 [0:01:33.102169648] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11377 10:54:28.963585 Camera needs 4 requests, can't test only 1
11378 10:54:29.061243 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11379 10:54:29.157658
11380 10:54:29.264562 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (52 ms)
11381 10:54:29.388369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11382 10:54:29.389151 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11384 10:54:29.407029 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11385 10:54:29.471808 Camera needs 4 requests, can't test only 2
11386 10:54:29.569894 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11387 10:54:29.667681
11388 10:54:29.778678 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (50 ms)
11389 10:54:29.895241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11390 10:54:29.896077 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11392 10:54:29.913236 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11393 10:54:29.978658 Camera needs 4 requests, can't test only 3
11394 10:54:30.072488 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11395 10:54:30.095351 [0:01:34.280230677] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11396 10:54:30.164512
11397 10:54:30.263919 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (50 ms)
11398 10:54:30.374997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11399 10:54:30.375803 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11401 10:54:30.392643 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11402 10:54:30.464180 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1178 ms)
11403 10:54:30.579545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11404 10:54:30.580354 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11406 10:54:30.594186 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11407 10:54:31.471575 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1381 ms)
11408 10:54:31.481436 [0:01:35.662985152] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 10:54:31.574963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11410 10:54:31.575402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11412 10:54:31.587297 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11413 10:54:33.545411 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2074 ms)
11414 10:54:33.555831 [0:01:37.738475706] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 10:54:33.667979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11416 10:54:33.668795 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11418 10:54:33.682943 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11419 10:54:36.259971 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2715 ms)
11420 10:54:36.269415 [0:01:40.451901531] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 10:54:36.374623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11422 10:54:36.374973 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11424 10:54:36.388345 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11425 10:54:40.303824 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4044 ms)
11426 10:54:40.313409 [0:01:44.495931446] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 10:54:40.391914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11428 10:54:40.392271 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11430 10:54:40.403348 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11431 10:54:46.542925 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6241 ms)
11432 10:54:46.553379 [0:01:50.736423932] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 10:54:46.642695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11434 10:54:46.643030 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11436 10:54:46.654572 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11437 10:54:56.247146 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9704 ms)
11438 10:54:56.257321 [0:02:00.441592654] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 10:54:56.303821 [0:02:00.492192825] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11440 10:54:56.354976 [0:02:00.543045296] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11441 10:54:56.361698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11442 10:54:56.362033 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11444 10:54:56.372671 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11445 10:54:56.405624 [0:02:00.594393676] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11446 10:54:56.427380 Camera needs 4 requests, can't test only 1
11447 10:54:56.502773 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11448 10:54:56.576437
11449 10:54:56.665677 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11450 10:54:56.765616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11451 10:54:56.765941 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11453 10:54:56.778484 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11454 10:54:56.829064 Camera needs 4 requests, can't test only 2
11455 10:54:56.909072 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11456 10:54:56.982998
11457 10:54:57.064023 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (50 ms)
11458 10:54:57.157266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11459 10:54:57.157597 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11461 10:54:57.169065 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11462 10:54:57.217594 Camera needs 4 requests, can't test only 3
11463 10:54:57.290216 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11464 10:54:57.365498
11465 10:54:57.454032 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (51 ms)
11466 10:54:57.486914 [0:02:01.675565113] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11467 10:54:57.554343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11468 10:54:57.554736 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11470 10:54:57.568961 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11471 10:54:57.623165 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1080 ms)
11472 10:54:57.718218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11473 10:54:57.718535 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11475 10:54:57.731398 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11476 10:54:58.862189 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1381 ms)
11477 10:54:58.871880 [0:02:03.057650114] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 10:54:58.963084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11479 10:54:58.963441 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11481 10:54:58.975925 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11482 10:55:00.938137 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2075 ms)
11483 10:55:00.947976 [0:02:05.133677741] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 10:55:01.039108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11485 10:55:01.039429 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11487 10:55:01.051043 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11488 10:55:03.618093 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2680 ms)
11489 10:55:03.628208 [0:02:07.812723429] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 10:55:03.711504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11491 10:55:03.711862 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11493 10:55:03.723550 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11494 10:55:07.728798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4111 ms)
11495 10:55:07.738473 [0:02:11.923411414] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 10:55:07.820159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11497 10:55:07.820550 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11499 10:55:07.833845 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11500 10:55:13.971141 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6241 ms)
11501 10:55:13.980815 [0:02:18.164862998] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 10:55:14.061969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11503 10:55:14.062346 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11505 10:55:14.073193 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11506 10:55:23.708730 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9738 ms)
11507 10:55:23.718654 [0:02:27.902155683] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 10:55:23.765785 [0:02:27.952345620] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11509 10:55:23.798436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11510 10:55:23.798740 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11512 10:55:23.816263 [0:02:28.003136248] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 10:55:23.822950 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11514 10:55:23.860692 Camera needs 4 requests, can't test only 1
11515 10:55:23.870427 [0:02:28.055883933] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 10:55:23.941788 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11517 10:55:24.014003
11518 10:55:24.099464 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (52 ms)
11519 10:55:24.193769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11520 10:55:24.194081 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11522 10:55:24.206871 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11523 10:55:24.260271 Camera needs 4 requests, can't test only 2
11524 10:55:24.335832 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11525 10:55:24.406770
11526 10:55:24.500208 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (51 ms)
11527 10:55:24.593880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11528 10:55:24.594226 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11530 10:55:24.607349 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11531 10:55:24.656656 Camera needs 4 requests, can't test only 3
11532 10:55:24.730899 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11533 10:55:24.801942
11534 10:55:24.885276 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11535 10:55:24.949418 [0:02:29.136339215] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11536 10:55:24.975248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11537 10:55:24.975554 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11539 10:55:24.986180 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11540 10:55:25.037140 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1081 ms)
11541 10:55:25.132887 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11543 10:55:25.135563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11544 10:55:25.149725 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11545 10:55:26.695674 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1750 ms)
11546 10:55:26.705598 [0:02:30.888638806] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 10:55:26.852916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11548 10:55:26.853258 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11550 10:55:26.863544 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11551 10:55:29.076638 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2382 ms)
11552 10:55:29.086537 [0:02:33.270222553] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 10:55:29.168813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11554 10:55:29.169135 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11556 10:55:29.180619 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11557 10:55:31.790836 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2714 ms)
11558 10:55:31.800800 [0:02:35.984700456] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 10:55:31.881278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11560 10:55:31.881603 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11562 10:55:31.892408 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11563 10:55:35.869500 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4079 ms)
11564 10:55:35.879288 [0:02:40.062888885] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 10:55:35.961084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11566 10:55:35.961425 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11568 10:55:35.973322 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11569 10:55:42.141973 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6272 ms)
11570 10:55:42.152342 [0:02:46.335860853] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 10:55:42.237296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11572 10:55:42.237578 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11574 10:55:42.249751 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11575 10:55:51.813149 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9671 ms)
11576 10:55:51.822874 [0:02:56.004870338] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 10:55:51.926309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11578 10:55:51.927074 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11580 10:55:51.940796 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11581 10:55:52.072183 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (263 ms)
11582 10:55:52.085213 [0:02:56.268627995] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 10:55:52.185625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11584 10:55:52.186356 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11586 10:55:52.203612 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11587 10:55:52.336321 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (264 ms)
11588 10:55:52.345569 [0:02:56.533238455] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 10:55:52.436597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11590 10:55:52.436877 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11592 10:55:52.451921 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11593 10:55:52.633316 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (297 ms)
11594 10:55:52.646061 [0:02:56.830617522] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11595 10:55:52.730825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11596 10:55:52.731101 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11598 10:55:52.747357 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11599 10:55:52.997447 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (364 ms)
11600 10:55:53.009931 [0:02:57.194266600] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11601 10:55:53.098206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11602 10:55:53.098495 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11604 10:55:53.116503 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11605 10:55:53.460305 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (463 ms)
11606 10:55:53.473224 [0:02:57.658367466] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11607 10:55:53.567797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11608 10:55:53.568080 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11610 10:55:53.584158 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11611 10:55:54.156958 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (697 ms)
11612 10:55:54.170188 [0:02:58.354359971] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11613 10:55:54.263089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11614 10:55:54.263374 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11616 10:55:54.282040 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11617 10:55:55.054478 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (897 ms)
11618 10:55:55.067323 [0:02:59.251303335] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 10:55:55.156784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11620 10:55:55.157079 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11622 10:55:55.173001 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11623 10:55:56.448987 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1395 ms)
11624 10:55:56.461574 [0:03:00.646130128] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11625 10:55:56.558496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11626 10:55:56.558788 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11628 10:55:56.577314 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11629 10:55:58.574818 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2125 ms)
11630 10:55:58.587361 [0:03:02.772119997] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11631 10:55:58.683131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11632 10:55:58.683418 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11634 10:55:58.701909 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11635 10:56:01.803000 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3228 ms)
11636 10:56:01.815692 [0:03:05.998405909] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 10:56:01.908299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11638 10:56:01.908592 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11640 10:56:01.923699 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11641 10:56:02.407927 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (602 ms)
11642 10:56:02.417480 [0:03:06.599674308] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11643 10:56:02.531015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11644 10:56:02.531852 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11646 10:56:02.550950 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11647 10:56:02.670120 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (262 ms)
11648 10:56:02.679892 [0:03:06.862445585] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11649 10:56:02.785634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11650 10:56:02.786381 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11652 10:56:02.803306 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11653 10:56:02.965291 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (295 ms)
11654 10:56:02.974876 [0:03:07.157122181] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11655 10:56:03.083673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11656 10:56:03.084454 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11658 10:56:03.101365 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11659 10:56:03.326913 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (361 ms)
11660 10:56:03.336297 [0:03:07.518828908] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11661 10:56:03.446494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11662 10:56:03.447251 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11664 10:56:03.464901 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11665 10:56:03.788685 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (462 ms)
11666 10:56:03.798136 [0:03:07.980327946] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11667 10:56:03.910229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11668 10:56:03.911020 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11670 10:56:03.928078 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11671 10:56:04.481471 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (693 ms)
11672 10:56:04.491268 [0:03:08.674144718] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11673 10:56:04.601144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11674 10:56:04.601460 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11676 10:56:04.617800 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11677 10:56:05.411526 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (931 ms)
11678 10:56:05.421403 [0:03:09.603655357] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11679 10:56:05.526322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11680 10:56:05.527059 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11682 10:56:05.544804 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11683 10:56:06.803781 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1392 ms)
11684 10:56:06.813891 [0:03:10.997878218] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11685 10:56:06.900004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11686 10:56:06.900364 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11688 10:56:06.910737 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11689 10:56:08.897730 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2094 ms)
11690 10:56:08.907631 [0:03:13.092772986] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11691 10:56:08.988001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11692 10:56:08.988337 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11694 10:56:08.999576 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11695 10:56:12.158623 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3261 ms)
11696 10:56:12.168401 [0:03:16.354356245] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11697 10:56:12.251299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11698 10:56:12.251609 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11700 10:56:12.263778 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11701 10:56:12.488628 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (330 ms)
11702 10:56:12.497976 [0:03:16.683573143] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11703 10:56:12.579454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11704 10:56:12.579758 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11706 10:56:12.591075 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11707 10:56:12.783122 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (294 ms)
11708 10:56:12.792784 [0:03:16.978669041] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11709 10:56:12.897315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11710 10:56:12.897638 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11712 10:56:12.911317 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11713 10:56:13.111167 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (329 ms)
11714 10:56:13.120920 [0:03:17.306108637] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11715 10:56:13.228530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11716 10:56:13.229418 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11718 10:56:13.242747 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11719 10:56:13.474529 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (364 ms)
11720 10:56:13.484441 [0:03:17.669772835] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11721 10:56:13.565308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11722 10:56:13.565651 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11724 10:56:13.575451 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11725 10:56:13.937594 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (463 ms)
11726 10:56:13.947555 [0:03:18.134198330] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11727 10:56:14.034714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11728 10:56:14.035060 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11730 10:56:14.045884 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11731 10:56:14.667520 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (729 ms)
11732 10:56:14.677406 [0:03:18.863180839] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11733 10:56:14.774636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11734 10:56:14.774992 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11736 10:56:14.786383 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11737 10:56:15.565774 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (897 ms)
11738 10:56:15.575215 [0:03:19.761573246] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11739 10:56:15.668414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11740 10:56:15.668724 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11742 10:56:15.682826 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11743 10:56:16.961979 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1396 ms)
11744 10:56:16.971125 [0:03:21.157154489] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11745 10:56:17.051274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11746 10:56:17.051620 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11748 10:56:17.065083 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11749 10:56:19.056526 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2095 ms)
11750 10:56:19.066204 [0:03:23.252289162] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11751 10:56:19.150057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11752 10:56:19.150370 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11754 10:56:19.161529 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11755 10:56:22.317127 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3261 ms)
11756 10:56:22.327222 [0:03:26.514238633] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11757 10:56:22.419665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11758 10:56:22.419963 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11760 10:56:22.431851 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11761 10:56:22.647323 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (330 ms)
11762 10:56:22.656932 [0:03:26.843442266] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11763 10:56:22.742431 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11765 10:56:22.745352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11766 10:56:22.758741 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11767 10:56:22.942208 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (295 ms)
11768 10:56:22.952128 [0:03:27.137164995] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11769 10:56:23.057123 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11771 10:56:23.059652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11772 10:56:23.074088 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11773 10:56:23.269504 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (327 ms)
11774 10:56:23.279578 [0:03:27.465718478] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11775 10:56:23.376164 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11777 10:56:23.379271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11778 10:56:23.394387 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11779 10:56:23.634134 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (365 ms)
11780 10:56:23.643692 [0:03:27.829691068] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11781 10:56:23.732003 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11783 10:56:23.734979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11784 10:56:23.748759 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11785 10:56:24.098270 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (463 ms)
11786 10:56:24.107622 [0:03:28.292805553] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11787 10:56:24.211667 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11789 10:56:24.214123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11790 10:56:24.230317 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11791 10:56:24.792930 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (695 ms)
11792 10:56:24.802449 [0:03:28.988736753] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11793 10:56:24.891648 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11795 10:56:24.894773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11796 10:56:24.906422 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11797 10:56:25.690238 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (897 ms)
11798 10:56:25.699823 [0:03:29.886195227] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11799 10:56:25.801357 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11801 10:56:25.804392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11802 10:56:25.823980 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11803 10:56:27.085192 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1396 ms)
11804 10:56:27.095163 [0:03:31.281602687] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11805 10:56:27.184089 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11807 10:56:27.187307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11808 10:56:27.198457 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11809 10:56:29.180651 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2095 ms)
11810 10:56:29.189788 [0:03:33.377042563] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11811 10:56:29.280880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11812 10:56:29.281189 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11814 10:56:29.294923 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11815 10:56:32.376777 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3197 ms)
11816 10:56:32.477129 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11818 10:56:32.480256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11819 10:56:32.494391 [----------] 120 tests from CaptureTests/SingleStream (188326 ms total)
11820 10:56:32.576564
11821 10:56:32.667445 [----------] Global test environment tear-down
11822 10:56:32.753346 [==========] 120 tests from 1 test suite ran. (188326 ms total)
11823 10:56:32.843503 <LAVA_SIGNAL_TESTSET STOP>
11824 10:56:32.843863 Received signal: <TESTSET> STOP
11825 10:56:32.843946 Closing test_set CaptureTests/SingleStream
11826 10:56:32.856278 + set +x
11827 10:56:32.859397 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10590978_1.6.2.3.1>
11828 10:56:32.859652 Received signal: <ENDRUN> 0_lc-compliance 10590978_1.6.2.3.1
11829 10:56:32.859741 Ending use of test pattern.
11830 10:56:32.859817 Ending test lava.0_lc-compliance (10590978_1.6.2.3.1), duration 190.02
11832 10:56:32.862710 <LAVA_TEST_RUNNER EXIT>
11833 10:56:32.862964 ok: lava_test_shell seems to have completed
11834 10:56:32.864850 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11835 10:56:32.865039 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11836 10:56:32.865142 end: 3 lava-test-retry (duration 00:03:11) [common]
11837 10:56:32.865247 start: 4 finalize (timeout 00:10:00) [common]
11838 10:56:32.865353 start: 4.1 power-off (timeout 00:00:30) [common]
11839 10:56:32.865518 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11840 10:56:32.939968 >> Command sent successfully.
11841 10:56:32.942282 Returned 0 in 0 seconds
11842 10:56:33.042651 end: 4.1 power-off (duration 00:00:00) [common]
11844 10:56:33.042995 start: 4.2 read-feedback (timeout 00:10:00) [common]
11845 10:56:33.043263 Listened to connection for namespace 'common' for up to 1s
11846 10:56:34.044165 Finalising connection for namespace 'common'
11847 10:56:34.044392 Disconnecting from shell: Finalise
11848 10:56:34.044513 / #
11849 10:56:34.144918 end: 4.2 read-feedback (duration 00:00:01) [common]
11850 10:56:34.145102 end: 4 finalize (duration 00:00:01) [common]
11851 10:56:34.145237 Cleaning after the job
11852 10:56:34.145345 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/ramdisk
11853 10:56:34.147414 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/kernel
11854 10:56:34.156348 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/dtb
11855 10:56:34.156567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/nfsrootfs
11856 10:56:34.200330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590978/tftp-deploy-55rc5d5u/modules
11857 10:56:34.206865 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10590978
11858 10:56:34.472145 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10590978
11859 10:56:34.472310 Job finished correctly