Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 10:54:23.835287 lava-dispatcher, installed at version: 2023.05.1
2 10:54:23.835509 start: 0 validate
3 10:54:23.835644 Start time: 2023-06-05 10:54:23.835636+00:00 (UTC)
4 10:54:23.835773 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:54:23.835905 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:54:24.126799 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:54:24.127564 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:54:24.418225 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:54:24.418949 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:54:24.717256 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:54:24.717980 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:54:25.014512 validate duration: 1.18
14 10:54:25.015707 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:54:25.016223 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:54:25.016671 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:54:25.017264 Not decompressing ramdisk as can be used compressed.
18 10:54:25.017702 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 10:54:25.018032 saving as /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/ramdisk/rootfs.cpio.gz
20 10:54:25.018346 total size: 34405874 (32MB)
21 10:54:25.027382 progress 0% (0MB)
22 10:54:25.059104 progress 5% (1MB)
23 10:54:25.072986 progress 10% (3MB)
24 10:54:25.083595 progress 15% (4MB)
25 10:54:25.092440 progress 20% (6MB)
26 10:54:25.101289 progress 25% (8MB)
27 10:54:25.109763 progress 30% (9MB)
28 10:54:25.118483 progress 35% (11MB)
29 10:54:25.126891 progress 40% (13MB)
30 10:54:25.135404 progress 45% (14MB)
31 10:54:25.143805 progress 50% (16MB)
32 10:54:25.152870 progress 55% (18MB)
33 10:54:25.161673 progress 60% (19MB)
34 10:54:25.170683 progress 65% (21MB)
35 10:54:25.179766 progress 70% (22MB)
36 10:54:25.188957 progress 75% (24MB)
37 10:54:25.197910 progress 80% (26MB)
38 10:54:25.206867 progress 85% (27MB)
39 10:54:25.215400 progress 90% (29MB)
40 10:54:25.224030 progress 95% (31MB)
41 10:54:25.232383 progress 100% (32MB)
42 10:54:25.232633 32MB downloaded in 0.21s (153.12MB/s)
43 10:54:25.232786 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:54:25.233029 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:54:25.233115 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:54:25.233199 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:54:25.233335 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:54:25.233408 saving as /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/kernel/Image
50 10:54:25.233470 total size: 45746688 (43MB)
51 10:54:25.233530 No compression specified
52 10:54:25.234620 progress 0% (0MB)
53 10:54:25.245830 progress 5% (2MB)
54 10:54:25.257279 progress 10% (4MB)
55 10:54:25.268888 progress 15% (6MB)
56 10:54:25.280627 progress 20% (8MB)
57 10:54:25.292356 progress 25% (10MB)
58 10:54:25.304074 progress 30% (13MB)
59 10:54:25.315760 progress 35% (15MB)
60 10:54:25.327191 progress 40% (17MB)
61 10:54:25.338546 progress 45% (19MB)
62 10:54:25.349894 progress 50% (21MB)
63 10:54:25.361364 progress 55% (24MB)
64 10:54:25.372963 progress 60% (26MB)
65 10:54:25.384782 progress 65% (28MB)
66 10:54:25.396447 progress 70% (30MB)
67 10:54:25.408283 progress 75% (32MB)
68 10:54:25.419728 progress 80% (34MB)
69 10:54:25.431164 progress 85% (37MB)
70 10:54:25.442515 progress 90% (39MB)
71 10:54:25.453836 progress 95% (41MB)
72 10:54:25.465243 progress 100% (43MB)
73 10:54:25.465391 43MB downloaded in 0.23s (188.12MB/s)
74 10:54:25.465540 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:54:25.465771 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:54:25.465857 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:54:25.465941 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:54:25.466093 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:54:25.466167 saving as /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/dtb/mt8192-asurada-spherion-r0.dtb
81 10:54:25.466231 total size: 46924 (0MB)
82 10:54:25.466292 No compression specified
83 10:54:25.467423 progress 69% (0MB)
84 10:54:25.467690 progress 100% (0MB)
85 10:54:25.467840 0MB downloaded in 0.00s (27.85MB/s)
86 10:54:25.467959 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:54:25.468180 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:54:25.468265 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:54:25.468347 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:54:25.468461 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:54:25.468533 saving as /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/modules/modules.tar
93 10:54:25.468595 total size: 8542412 (8MB)
94 10:54:25.468655 Using unxz to decompress xz
95 10:54:25.472112 progress 0% (0MB)
96 10:54:25.493436 progress 5% (0MB)
97 10:54:25.518248 progress 10% (0MB)
98 10:54:25.544198 progress 15% (1MB)
99 10:54:25.568419 progress 20% (1MB)
100 10:54:25.593746 progress 25% (2MB)
101 10:54:25.618476 progress 30% (2MB)
102 10:54:25.643774 progress 35% (2MB)
103 10:54:25.667965 progress 40% (3MB)
104 10:54:25.692707 progress 45% (3MB)
105 10:54:25.716250 progress 50% (4MB)
106 10:54:25.738630 progress 55% (4MB)
107 10:54:25.763459 progress 60% (4MB)
108 10:54:25.787957 progress 65% (5MB)
109 10:54:25.813012 progress 70% (5MB)
110 10:54:25.839394 progress 75% (6MB)
111 10:54:25.868214 progress 80% (6MB)
112 10:54:25.890451 progress 85% (6MB)
113 10:54:25.915632 progress 90% (7MB)
114 10:54:25.938742 progress 95% (7MB)
115 10:54:25.961971 progress 100% (8MB)
116 10:54:25.967505 8MB downloaded in 0.50s (16.33MB/s)
117 10:54:25.967775 end: 1.4.1 http-download (duration 00:00:00) [common]
119 10:54:25.968033 end: 1.4 download-retry (duration 00:00:00) [common]
120 10:54:25.968126 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:54:25.968223 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:54:25.968307 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:54:25.968393 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:54:25.968614 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9
125 10:54:25.968748 makedir: /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin
126 10:54:25.968851 makedir: /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/tests
127 10:54:25.968949 makedir: /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/results
128 10:54:25.969063 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-add-keys
129 10:54:25.969208 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-add-sources
130 10:54:25.969335 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-background-process-start
131 10:54:25.969466 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-background-process-stop
132 10:54:25.969598 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-common-functions
133 10:54:25.969719 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-echo-ipv4
134 10:54:25.969841 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-install-packages
135 10:54:25.969961 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-installed-packages
136 10:54:25.970082 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-os-build
137 10:54:25.970202 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-probe-channel
138 10:54:25.970323 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-probe-ip
139 10:54:25.970443 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-target-ip
140 10:54:25.970563 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-target-mac
141 10:54:25.970682 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-target-storage
142 10:54:25.970805 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-case
143 10:54:25.970926 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-event
144 10:54:25.971044 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-feedback
145 10:54:25.971163 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-raise
146 10:54:25.971284 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-reference
147 10:54:25.971439 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-runner
148 10:54:25.971559 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-set
149 10:54:25.971679 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-test-shell
150 10:54:25.971803 Updating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-install-packages (oe)
151 10:54:25.971952 Updating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/bin/lava-installed-packages (oe)
152 10:54:25.972070 Creating /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/environment
153 10:54:25.972167 LAVA metadata
154 10:54:25.972241 - LAVA_JOB_ID=10591003
155 10:54:25.972306 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:54:25.972408 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:54:25.972474 skipped lava-vland-overlay
158 10:54:25.972550 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:54:25.972631 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:54:25.972694 skipped lava-multinode-overlay
161 10:54:25.972769 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:54:25.972851 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:54:25.972924 Loading test definitions
164 10:54:25.973015 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:54:25.973090 Using /lava-10591003 at stage 0
166 10:54:25.973398 uuid=10591003_1.5.2.3.1 testdef=None
167 10:54:25.973487 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:54:25.973571 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:54:25.974072 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:54:25.974295 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:54:25.974909 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:54:25.975145 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:54:25.975766 runner path: /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/0/tests/0_cros-ec test_uuid 10591003_1.5.2.3.1
176 10:54:25.975920 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:54:25.976129 Creating lava-test-runner.conf files
179 10:54:25.976195 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591003/lava-overlay-wh_fl8d9/lava-10591003/0 for stage 0
180 10:54:25.976281 - 0_cros-ec
181 10:54:25.976377 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:54:25.976461 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:54:25.982982 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:54:25.983086 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:54:25.983174 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:54:25.983260 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:54:25.983375 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:54:26.918572 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:54:26.918940 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:54:26.919056 extracting modules file /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591003/extract-overlay-ramdisk-5nui6a2a/ramdisk
191 10:54:27.126356 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:54:27.126532 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:54:27.126625 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591003/compress-overlay-4rxmgbjd/overlay-1.5.2.4.tar.gz to ramdisk
194 10:54:27.126701 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591003/compress-overlay-4rxmgbjd/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591003/extract-overlay-ramdisk-5nui6a2a/ramdisk
195 10:54:27.133385 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:54:27.133510 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:54:27.133603 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:54:27.133694 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:54:27.133775 Building ramdisk /var/lib/lava/dispatcher/tmp/10591003/extract-overlay-ramdisk-5nui6a2a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591003/extract-overlay-ramdisk-5nui6a2a/ramdisk
200 10:54:27.770261 >> 269469 blocks
201 10:54:32.462412 rename /var/lib/lava/dispatcher/tmp/10591003/extract-overlay-ramdisk-5nui6a2a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/ramdisk/ramdisk.cpio.gz
202 10:54:32.462919 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:54:32.463087 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 10:54:32.463231 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 10:54:32.463425 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/kernel/Image'
206 10:54:44.091429 Returned 0 in 11 seconds
207 10:54:44.192088 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/kernel/image.itb
208 10:54:44.831692 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:54:44.832054 output: Created: Mon Jun 5 11:54:44 2023
210 10:54:44.832129 output: Image 0 (kernel-1)
211 10:54:44.832194 output: Description:
212 10:54:44.832259 output: Created: Mon Jun 5 11:54:44 2023
213 10:54:44.832320 output: Type: Kernel Image
214 10:54:44.832378 output: Compression: lzma compressed
215 10:54:44.832438 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
216 10:54:44.832498 output: Architecture: AArch64
217 10:54:44.832557 output: OS: Linux
218 10:54:44.832612 output: Load Address: 0x00000000
219 10:54:44.832669 output: Entry Point: 0x00000000
220 10:54:44.832727 output: Hash algo: crc32
221 10:54:44.832793 output: Hash value: 8ce42972
222 10:54:44.832848 output: Image 1 (fdt-1)
223 10:54:44.832901 output: Description: mt8192-asurada-spherion-r0
224 10:54:44.832966 output: Created: Mon Jun 5 11:54:44 2023
225 10:54:44.833023 output: Type: Flat Device Tree
226 10:54:44.833077 output: Compression: uncompressed
227 10:54:44.833141 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:54:44.833232 output: Architecture: AArch64
229 10:54:44.833317 output: Hash algo: crc32
230 10:54:44.833400 output: Hash value: 1df858fa
231 10:54:44.833491 output: Image 2 (ramdisk-1)
232 10:54:44.833576 output: Description: unavailable
233 10:54:44.833634 output: Created: Mon Jun 5 11:54:44 2023
234 10:54:44.833689 output: Type: RAMDisk Image
235 10:54:44.833743 output: Compression: Unknown Compression
236 10:54:44.833797 output: Data Size: 47379755 Bytes = 46269.29 KiB = 45.18 MiB
237 10:54:44.833852 output: Architecture: AArch64
238 10:54:44.833905 output: OS: Linux
239 10:54:44.833959 output: Load Address: unavailable
240 10:54:44.834011 output: Entry Point: unavailable
241 10:54:44.834065 output: Hash algo: crc32
242 10:54:44.834127 output: Hash value: 612616f3
243 10:54:44.834182 output: Default Configuration: 'conf-1'
244 10:54:44.834236 output: Configuration 0 (conf-1)
245 10:54:44.834299 output: Description: mt8192-asurada-spherion-r0
246 10:54:44.834380 output: Kernel: kernel-1
247 10:54:44.834448 output: Init Ramdisk: ramdisk-1
248 10:54:44.834514 output: FDT: fdt-1
249 10:54:44.834568 output: Loadables: kernel-1
250 10:54:44.834622 output:
251 10:54:44.834815 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 10:54:44.834915 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 10:54:44.835020 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 10:54:44.835107 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 10:54:44.835183 No LXC device requested
256 10:54:44.835262 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:54:44.835362 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 10:54:44.835480 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:54:44.835552 Checking files for TFTP limit of 4294967296 bytes.
260 10:54:44.836051 end: 1 tftp-deploy (duration 00:00:20) [common]
261 10:54:44.836167 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:54:44.836258 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:54:44.836383 substitutions:
264 10:54:44.836451 - {DTB}: 10591003/tftp-deploy-gzo4hxez/dtb/mt8192-asurada-spherion-r0.dtb
265 10:54:44.836519 - {INITRD}: 10591003/tftp-deploy-gzo4hxez/ramdisk/ramdisk.cpio.gz
266 10:54:44.836579 - {KERNEL}: 10591003/tftp-deploy-gzo4hxez/kernel/Image
267 10:54:44.836637 - {LAVA_MAC}: None
268 10:54:44.836694 - {PRESEED_CONFIG}: None
269 10:54:44.836768 - {PRESEED_LOCAL}: None
270 10:54:44.836828 - {RAMDISK}: 10591003/tftp-deploy-gzo4hxez/ramdisk/ramdisk.cpio.gz
271 10:54:44.836885 - {ROOT_PART}: None
272 10:54:44.836941 - {ROOT}: None
273 10:54:44.836997 - {SERVER_IP}: 192.168.201.1
274 10:54:44.837052 - {TEE}: None
275 10:54:44.837107 Parsed boot commands:
276 10:54:44.837162 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:54:44.837345 Parsed boot commands: tftpboot 192.168.201.1 10591003/tftp-deploy-gzo4hxez/kernel/image.itb 10591003/tftp-deploy-gzo4hxez/kernel/cmdline
278 10:54:44.837435 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:54:44.837524 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:54:44.837641 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:54:44.837739 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:54:44.837811 Not connected, no need to disconnect.
283 10:54:44.837886 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:54:44.837965 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:54:44.838033 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 10:54:44.841350 Setting prompt string to ['lava-test: # ']
287 10:54:44.841707 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:54:44.841850 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:54:44.841946 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:54:44.842043 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:54:44.842245 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 10:54:49.977696 >> Command sent successfully.
293 10:54:49.980101 Returned 0 in 5 seconds
294 10:54:50.080460 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:54:50.081031 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:54:50.081136 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:54:50.081226 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:54:50.081295 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:54:50.081368 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:54:50.081620 [Enter `^Ec?' for help]
302 10:54:50.256304
303 10:54:50.256450
304 10:54:50.256523 F0: 102B 0000
305 10:54:50.256587
306 10:54:50.256647 F3: 1001 0000 [0200]
307 10:54:50.256706
308 10:54:50.259543 F3: 1001 0000
309 10:54:50.259628
310 10:54:50.259695 F7: 102D 0000
311 10:54:50.259755
312 10:54:50.262317 F1: 0000 0000
313 10:54:50.262400
314 10:54:50.262465 V0: 0000 0000 [0001]
315 10:54:50.262527
316 10:54:50.265684 00: 0007 8000
317 10:54:50.265768
318 10:54:50.265833 01: 0000 0000
319 10:54:50.265896
320 10:54:50.265953 BP: 0C00 0209 [0000]
321 10:54:50.269817
322 10:54:50.269899 G0: 1182 0000
323 10:54:50.269966
324 10:54:50.270027 EC: 0000 0021 [4000]
325 10:54:50.270085
326 10:54:50.273461 S7: 0000 0000 [0000]
327 10:54:50.273544
328 10:54:50.273609 CC: 0000 0000 [0001]
329 10:54:50.273672
330 10:54:50.276866 T0: 0000 0040 [010F]
331 10:54:50.276950
332 10:54:50.277016 Jump to BL
333 10:54:50.277076
334 10:54:50.302652
335 10:54:50.302774
336 10:54:50.302841
337 10:54:50.310417 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:54:50.313884 ARM64: Exception handlers installed.
339 10:54:50.317234 ARM64: Testing exception
340 10:54:50.321041 ARM64: Done test exception
341 10:54:50.328143 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:54:50.335311 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:54:50.345613 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:54:50.355677 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:54:50.362104 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:54:50.369109 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:54:50.379188 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:54:50.386124 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:54:50.405470 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:54:50.408996 WDT: Last reset was cold boot
351 10:54:50.412306 SPI1(PAD0) initialized at 2873684 Hz
352 10:54:50.415491 SPI5(PAD0) initialized at 992727 Hz
353 10:54:50.419466 VBOOT: Loading verstage.
354 10:54:50.425631 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:54:50.428779 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:54:50.432005 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:54:50.435499 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:54:50.442903 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:54:50.449766 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:54:50.460265 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 10:54:50.460356
362 10:54:50.460424
363 10:54:50.470238 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:54:50.473655 ARM64: Exception handlers installed.
365 10:54:50.477158 ARM64: Testing exception
366 10:54:50.477244 ARM64: Done test exception
367 10:54:50.483775 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:54:50.487065 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:54:50.501104 Probing TPM: . done!
370 10:54:50.501198 TPM ready after 0 ms
371 10:54:50.507622 Connected to device vid:did:rid of 1ae0:0028:00
372 10:54:50.515031 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 10:54:50.575149 Initialized TPM device CR50 revision 0
374 10:54:50.586631 tlcl_send_startup: Startup return code is 0
375 10:54:50.586747 TPM: setup succeeded
376 10:54:50.598563 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:54:50.606882 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:54:50.619569 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:54:50.629306 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:54:50.633246 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:54:50.637753 in-header: 03 07 00 00 08 00 00 00
382 10:54:50.640655 in-data: aa e4 47 04 13 02 00 00
383 10:54:50.643919 Chrome EC: UHEPI supported
384 10:54:50.651458 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:54:50.655103 in-header: 03 ad 00 00 08 00 00 00
386 10:54:50.658600 in-data: 00 20 20 08 00 00 00 00
387 10:54:50.658686 Phase 1
388 10:54:50.662440 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:54:50.670696 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:54:50.673678 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:54:50.677191 Recovery requested (1009000e)
392 10:54:50.686408 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:54:50.692139 tlcl_extend: response is 0
394 10:54:50.702100 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:54:50.708347 tlcl_extend: response is 0
396 10:54:50.715473 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:54:50.735629 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 10:54:50.741620 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:54:50.741720
400 10:54:50.741787
401 10:54:50.752840 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:54:50.756666 ARM64: Exception handlers installed.
403 10:54:50.756754 ARM64: Testing exception
404 10:54:50.759543 ARM64: Done test exception
405 10:54:50.780579 pmic_efuse_setting: Set efuses in 11 msecs
406 10:54:50.783909 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:54:50.790674 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:54:50.794163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:54:50.800953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:54:50.804797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:54:50.808405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:54:50.815739 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:54:50.819667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:54:50.822828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:54:50.826658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:54:50.834174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:54:50.837794 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:54:50.841176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:54:50.845440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:54:50.852953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:54:50.859860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:54:50.863607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:54:50.870699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:54:50.874803 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:54:50.881738 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:54:50.885560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:54:50.893350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:54:50.896800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:54:50.904486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:54:50.908121 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:54:50.915055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:54:50.919248 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:54:50.926591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:54:50.929907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:54:50.933623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:54:50.941232 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:54:50.944884 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:54:50.948554 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:54:50.955783 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:54:50.959115 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:54:50.966107 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:54:50.970176 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:54:50.973825 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:54:50.980785 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:54:50.984570 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:54:50.988271 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:54:50.992174 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:54:50.996099 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:54:51.002845 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:54:51.006634 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:54:51.010715 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:54:51.013831 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:54:51.017351 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:54:51.024810 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:54:51.028325 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:54:51.032603 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:54:51.035741 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:54:51.042876 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:54:51.050401 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:54:51.058348 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:54:51.065337 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:54:51.072116 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:54:51.079745 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:54:51.083396 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:54:51.087245 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:54:51.094644 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 10:54:51.098175 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:54:51.105256 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 10:54:51.108623 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:54:51.118062 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 10:54:51.127271 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 10:54:51.137008 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 10:54:51.147035 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 10:54:51.155687 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 10:54:51.165838 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 10:54:51.175812 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 10:54:51.179160 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 10:54:51.182996 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 10:54:51.186522 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:54:51.194091 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:54:51.198387 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:54:51.201444 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:54:51.205156 ADC[4]: Raw value=900959 ID=7
484 10:54:51.205240 ADC[3]: Raw value=213336 ID=1
485 10:54:51.209241 RAM Code: 0x71
486 10:54:51.212692 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:54:51.216308 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:54:51.227145 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:54:51.230935 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:54:51.234411 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:54:51.239095 in-header: 03 07 00 00 08 00 00 00
492 10:54:51.242303 in-data: aa e4 47 04 13 02 00 00
493 10:54:51.246217 Chrome EC: UHEPI supported
494 10:54:51.253499 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:54:51.257201 in-header: 03 ed 00 00 08 00 00 00
496 10:54:51.260559 in-data: 80 20 60 08 00 00 00 00
497 10:54:51.264297 MRC: failed to locate region type 0.
498 10:54:51.267968 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:54:51.271834 DRAM-K: Running full calibration
500 10:54:51.278943 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:54:51.279026 header.status = 0x0
502 10:54:51.282273 header.version = 0x6 (expected: 0x6)
503 10:54:51.286869 header.size = 0xd00 (expected: 0xd00)
504 10:54:51.290150 header.flags = 0x0
505 10:54:51.293587 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:54:51.313591 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
507 10:54:51.320913 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:54:51.320998 dram_init: ddr_geometry: 2
509 10:54:51.324567 [EMI] MDL number = 2
510 10:54:51.328415 [EMI] Get MDL freq = 0
511 10:54:51.328499 dram_init: ddr_type: 0
512 10:54:51.332048 is_discrete_lpddr4: 1
513 10:54:51.332131 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:54:51.335611
515 10:54:51.335694
516 10:54:51.335762 [Bian_co] ETT version 0.0.0.1
517 10:54:51.342944 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:54:51.343028
519 10:54:51.346534 dramc_set_vcore_voltage set vcore to 650000
520 10:54:51.346618 Read voltage for 800, 4
521 10:54:51.350240 Vio18 = 0
522 10:54:51.350324 Vcore = 650000
523 10:54:51.350391 Vdram = 0
524 10:54:51.350453 Vddq = 0
525 10:54:51.353653 Vmddr = 0
526 10:54:51.353737 dram_init: config_dvfs: 1
527 10:54:51.360770 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:54:51.364527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:54:51.368379 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 10:54:51.371654 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 10:54:51.375067 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 10:54:51.381815 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 10:54:51.381898 MEM_TYPE=3, freq_sel=18
534 10:54:51.385104 sv_algorithm_assistance_LP4_1600
535 10:54:51.388301 ============ PULL DRAM RESETB DOWN ============
536 10:54:51.395538 ========== PULL DRAM RESETB DOWN end =========
537 10:54:51.398714 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:54:51.401773 ===================================
539 10:54:51.405088 LPDDR4 DRAM CONFIGURATION
540 10:54:51.408411 ===================================
541 10:54:51.408495 EX_ROW_EN[0] = 0x0
542 10:54:51.411671 EX_ROW_EN[1] = 0x0
543 10:54:51.411754 LP4Y_EN = 0x0
544 10:54:51.415237 WORK_FSP = 0x0
545 10:54:51.415321 WL = 0x2
546 10:54:51.418285 RL = 0x2
547 10:54:51.422531 BL = 0x2
548 10:54:51.422614 RPST = 0x0
549 10:54:51.425153 RD_PRE = 0x0
550 10:54:51.425236 WR_PRE = 0x1
551 10:54:51.428562 WR_PST = 0x0
552 10:54:51.428645 DBI_WR = 0x0
553 10:54:51.432333 DBI_RD = 0x0
554 10:54:51.432417 OTF = 0x1
555 10:54:51.435261 ===================================
556 10:54:51.438520 ===================================
557 10:54:51.441644 ANA top config
558 10:54:51.445092 ===================================
559 10:54:51.445176 DLL_ASYNC_EN = 0
560 10:54:51.448188 ALL_SLAVE_EN = 1
561 10:54:51.452343 NEW_RANK_MODE = 1
562 10:54:51.454823 DLL_IDLE_MODE = 1
563 10:54:51.454897 LP45_APHY_COMB_EN = 1
564 10:54:51.458816 TX_ODT_DIS = 1
565 10:54:51.461671 NEW_8X_MODE = 1
566 10:54:51.465140 ===================================
567 10:54:51.468662 ===================================
568 10:54:51.471685 data_rate = 1600
569 10:54:51.474970 CKR = 1
570 10:54:51.475052 DQ_P2S_RATIO = 8
571 10:54:51.478408 ===================================
572 10:54:51.482532 CA_P2S_RATIO = 8
573 10:54:51.484861 DQ_CA_OPEN = 0
574 10:54:51.488651 DQ_SEMI_OPEN = 0
575 10:54:51.492370 CA_SEMI_OPEN = 0
576 10:54:51.495166 CA_FULL_RATE = 0
577 10:54:51.495276 DQ_CKDIV4_EN = 1
578 10:54:51.498371 CA_CKDIV4_EN = 1
579 10:54:51.502072 CA_PREDIV_EN = 0
580 10:54:51.505360 PH8_DLY = 0
581 10:54:51.508888 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:54:51.511618 DQ_AAMCK_DIV = 4
583 10:54:51.511701 CA_AAMCK_DIV = 4
584 10:54:51.515268 CA_ADMCK_DIV = 4
585 10:54:51.518351 DQ_TRACK_CA_EN = 0
586 10:54:51.522597 CA_PICK = 800
587 10:54:51.525258 CA_MCKIO = 800
588 10:54:51.528545 MCKIO_SEMI = 0
589 10:54:51.528628 PLL_FREQ = 3068
590 10:54:51.532250 DQ_UI_PI_RATIO = 32
591 10:54:51.535815 CA_UI_PI_RATIO = 0
592 10:54:51.540006 ===================================
593 10:54:51.542915 ===================================
594 10:54:51.546172 memory_type:LPDDR4
595 10:54:51.546256 GP_NUM : 10
596 10:54:51.549589 SRAM_EN : 1
597 10:54:51.549672 MD32_EN : 0
598 10:54:51.553758 ===================================
599 10:54:51.557063 [ANA_INIT] >>>>>>>>>>>>>>
600 10:54:51.560468 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:54:51.564488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:54:51.567980 ===================================
603 10:54:51.568071 data_rate = 1600,PCW = 0X7600
604 10:54:51.571123 ===================================
605 10:54:51.574813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:54:51.580777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:54:51.587615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:54:51.591006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:54:51.594339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:54:51.597605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:54:51.601105 [ANA_INIT] flow start
612 10:54:51.601191 [ANA_INIT] PLL >>>>>>>>
613 10:54:51.605019 [ANA_INIT] PLL <<<<<<<<
614 10:54:51.608104 [ANA_INIT] MIDPI >>>>>>>>
615 10:54:51.608191 [ANA_INIT] MIDPI <<<<<<<<
616 10:54:51.611676 [ANA_INIT] DLL >>>>>>>>
617 10:54:51.614615 [ANA_INIT] flow end
618 10:54:51.617772 ============ LP4 DIFF to SE enter ============
619 10:54:51.621301 ============ LP4 DIFF to SE exit ============
620 10:54:51.624382 [ANA_INIT] <<<<<<<<<<<<<
621 10:54:51.628203 [Flow] Enable top DCM control >>>>>
622 10:54:51.631809 [Flow] Enable top DCM control <<<<<
623 10:54:51.634543 Enable DLL master slave shuffle
624 10:54:51.638483 ==============================================================
625 10:54:51.640969 Gating Mode config
626 10:54:51.648066 ==============================================================
627 10:54:51.648154 Config description:
628 10:54:51.657825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:54:51.665040 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:54:51.668161 SELPH_MODE 0: By rank 1: By Phase
631 10:54:51.674916 ==============================================================
632 10:54:51.678341 GAT_TRACK_EN = 1
633 10:54:51.681378 RX_GATING_MODE = 2
634 10:54:51.684909 RX_GATING_TRACK_MODE = 2
635 10:54:51.688547 SELPH_MODE = 1
636 10:54:51.691558 PICG_EARLY_EN = 1
637 10:54:51.694750 VALID_LAT_VALUE = 1
638 10:54:51.698540 ==============================================================
639 10:54:51.701472 Enter into Gating configuration >>>>
640 10:54:51.704884 Exit from Gating configuration <<<<
641 10:54:51.708092 Enter into DVFS_PRE_config >>>>>
642 10:54:51.718217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:54:51.721555 Exit from DVFS_PRE_config <<<<<
644 10:54:51.724773 Enter into PICG configuration >>>>
645 10:54:51.728504 Exit from PICG configuration <<<<
646 10:54:51.731920 [RX_INPUT] configuration >>>>>
647 10:54:51.734816 [RX_INPUT] configuration <<<<<
648 10:54:51.738197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:54:51.744766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:54:51.752077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:54:51.758840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:54:51.762282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:54:51.769126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:54:51.772040 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:54:51.778598 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:54:51.782079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:54:51.785178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:54:51.788888 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:54:51.795463 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:54:51.798633 ===================================
661 10:54:51.798721 LPDDR4 DRAM CONFIGURATION
662 10:54:51.802261 ===================================
663 10:54:51.805781 EX_ROW_EN[0] = 0x0
664 10:54:51.808666 EX_ROW_EN[1] = 0x0
665 10:54:51.808754 LP4Y_EN = 0x0
666 10:54:51.812313 WORK_FSP = 0x0
667 10:54:51.812400 WL = 0x2
668 10:54:51.815609 RL = 0x2
669 10:54:51.815696 BL = 0x2
670 10:54:51.818849 RPST = 0x0
671 10:54:51.818935 RD_PRE = 0x0
672 10:54:51.822027 WR_PRE = 0x1
673 10:54:51.822114 WR_PST = 0x0
674 10:54:51.825286 DBI_WR = 0x0
675 10:54:51.825374 DBI_RD = 0x0
676 10:54:51.829288 OTF = 0x1
677 10:54:51.832487 ===================================
678 10:54:51.835834 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:54:51.838895 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:54:51.845746 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:54:51.848928 ===================================
682 10:54:51.849015 LPDDR4 DRAM CONFIGURATION
683 10:54:51.852319 ===================================
684 10:54:51.855975 EX_ROW_EN[0] = 0x10
685 10:54:51.856062 EX_ROW_EN[1] = 0x0
686 10:54:51.859354 LP4Y_EN = 0x0
687 10:54:51.859483 WORK_FSP = 0x0
688 10:54:51.862411 WL = 0x2
689 10:54:51.865751 RL = 0x2
690 10:54:51.865835 BL = 0x2
691 10:54:51.868712 RPST = 0x0
692 10:54:51.868796 RD_PRE = 0x0
693 10:54:51.872041 WR_PRE = 0x1
694 10:54:51.872126 WR_PST = 0x0
695 10:54:51.875507 DBI_WR = 0x0
696 10:54:51.875591 DBI_RD = 0x0
697 10:54:51.878802 OTF = 0x1
698 10:54:51.882130 ===================================
699 10:54:51.888584 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:54:51.891940 nWR fixed to 40
701 10:54:51.892025 [ModeRegInit_LP4] CH0 RK0
702 10:54:51.895258 [ModeRegInit_LP4] CH0 RK1
703 10:54:51.898826 [ModeRegInit_LP4] CH1 RK0
704 10:54:51.898910 [ModeRegInit_LP4] CH1 RK1
705 10:54:51.902158 match AC timing 13
706 10:54:51.905829 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:54:51.908713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:54:51.915067 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:54:51.919214 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:54:51.925185 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:54:51.925269 [EMI DOE] emi_dcm 0
712 10:54:51.928330 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:54:51.931827 ==
714 10:54:51.935331 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:54:51.939091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:54:51.939176 ==
717 10:54:51.941697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:54:51.948422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:54:51.958336 [CA 0] Center 37 (7~68) winsize 62
720 10:54:51.961804 [CA 1] Center 37 (6~68) winsize 63
721 10:54:51.965613 [CA 2] Center 35 (4~66) winsize 63
722 10:54:51.968576 [CA 3] Center 34 (4~65) winsize 62
723 10:54:51.971925 [CA 4] Center 33 (3~64) winsize 62
724 10:54:51.975203 [CA 5] Center 33 (3~64) winsize 62
725 10:54:51.975287
726 10:54:51.978398 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:54:51.978482
728 10:54:51.981636 [CATrainingPosCal] consider 1 rank data
729 10:54:51.985360 u2DelayCellTimex100 = 270/100 ps
730 10:54:51.988196 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 10:54:51.991788 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 10:54:51.998809 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 10:54:52.001736 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 10:54:52.005130 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 10:54:52.008344 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 10:54:52.008428
737 10:54:52.011556 CA PerBit enable=1, Macro0, CA PI delay=33
738 10:54:52.011639
739 10:54:52.014915 [CBTSetCACLKResult] CA Dly = 33
740 10:54:52.014999 CS Dly: 5 (0~36)
741 10:54:52.018367 ==
742 10:54:52.018450 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:54:52.025097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:54:52.025182 ==
745 10:54:52.028318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:54:52.034906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:54:52.044432 [CA 0] Center 37 (6~68) winsize 63
748 10:54:52.048036 [CA 1] Center 37 (7~68) winsize 62
749 10:54:52.051330 [CA 2] Center 35 (4~66) winsize 63
750 10:54:52.055120 [CA 3] Center 35 (5~66) winsize 62
751 10:54:52.058103 [CA 4] Center 34 (3~65) winsize 63
752 10:54:52.061732 [CA 5] Center 33 (3~64) winsize 62
753 10:54:52.061816
754 10:54:52.064724 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:54:52.064809
756 10:54:52.068820 [CATrainingPosCal] consider 2 rank data
757 10:54:52.071682 u2DelayCellTimex100 = 270/100 ps
758 10:54:52.074586 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 10:54:52.077896 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 10:54:52.084654 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
761 10:54:52.088185 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 10:54:52.091114 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 10:54:52.095323 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 10:54:52.095445
765 10:54:52.098117 CA PerBit enable=1, Macro0, CA PI delay=33
766 10:54:52.098201
767 10:54:52.101126 [CBTSetCACLKResult] CA Dly = 33
768 10:54:52.101210 CS Dly: 6 (0~38)
769 10:54:52.101277
770 10:54:52.104595 ----->DramcWriteLeveling(PI) begin...
771 10:54:52.108261 ==
772 10:54:52.111782 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:54:52.114924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:54:52.115008 ==
775 10:54:52.118806 Write leveling (Byte 0): 31 => 31
776 10:54:52.122389 Write leveling (Byte 1): 30 => 30
777 10:54:52.122472 DramcWriteLeveling(PI) end<-----
778 10:54:52.122540
779 10:54:52.122602 ==
780 10:54:52.126236 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:54:52.132603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:54:52.132687 ==
783 10:54:52.132754 [Gating] SW mode calibration
784 10:54:52.139780 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:54:52.146915 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:54:52.150029 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:54:52.156690 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 10:54:52.159980 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 10:54:52.163301 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:54:52.167305 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:54:52.173773 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:54:52.176827 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:54:52.180296 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:54:52.186840 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:54:52.189872 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:54:52.193606 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:54:52.200418 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:54:52.203639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:54:52.206585 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:54:52.213586 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:54:52.216626 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:54:52.220624 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:54:52.226962 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:54:52.230650 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 10:54:52.233761 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:54:52.237577 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:54:52.244427 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:54:52.247316 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:54:52.250755 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:54:52.257624 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:54:52.260714 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:54:52.263750 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 10:54:52.270274 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
814 10:54:52.273828 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:54:52.276686 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:54:52.283643 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:54:52.286773 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:54:52.290113 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:54:52.296650 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 10:54:52.300144 0 10 8 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
821 10:54:52.303841 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
822 10:54:52.310380 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:54:52.313447 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:54:52.316945 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:54:52.323874 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:54:52.326656 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:54:52.329921 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:54:52.337143 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
829 10:54:52.340210 0 11 12 | B1->B0 | 3232 4040 | 1 0 | (0 0) (1 1)
830 10:54:52.343309 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:54:52.346708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:54:52.353632 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:54:52.356884 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:54:52.360171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:54:52.366685 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 10:54:52.370168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 10:54:52.373342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 10:54:52.380167 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:54:52.383300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:54:52.387162 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:54:52.393304 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:54:52.396628 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:54:52.399983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:54:52.406587 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:54:52.410255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:54:52.414367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:54:52.420195 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:54:52.423159 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:54:52.426838 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:54:52.433490 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:54:52.436970 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:54:52.440323 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 10:54:52.446690 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 10:54:52.446775 Total UI for P1: 0, mck2ui 16
855 10:54:52.452916 best dqsien dly found for B0: ( 0, 14, 8)
856 10:54:52.456565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 10:54:52.459758 Total UI for P1: 0, mck2ui 16
858 10:54:52.463155 best dqsien dly found for B1: ( 0, 14, 12)
859 10:54:52.466641 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 10:54:52.470045 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 10:54:52.470129
862 10:54:52.473309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:54:52.476372 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 10:54:52.480029 [Gating] SW calibration Done
865 10:54:52.480113 ==
866 10:54:52.483125 Dram Type= 6, Freq= 0, CH_0, rank 0
867 10:54:52.486513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 10:54:52.486597 ==
869 10:54:52.489730 RX Vref Scan: 0
870 10:54:52.489814
871 10:54:52.493417 RX Vref 0 -> 0, step: 1
872 10:54:52.493501
873 10:54:52.493568 RX Delay -130 -> 252, step: 16
874 10:54:52.499486 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
875 10:54:52.503172 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
876 10:54:52.506920 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 10:54:52.509674 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 10:54:52.512849 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
879 10:54:52.519635 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
880 10:54:52.522916 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
881 10:54:52.526295 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
882 10:54:52.529701 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
883 10:54:52.533237 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
884 10:54:52.539619 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 10:54:52.542821 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
886 10:54:52.546434 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 10:54:52.549898 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
888 10:54:52.553003 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
889 10:54:52.560333 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 10:54:52.560417 ==
891 10:54:52.563385 Dram Type= 6, Freq= 0, CH_0, rank 0
892 10:54:52.566428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 10:54:52.566512 ==
894 10:54:52.566579 DQS Delay:
895 10:54:52.569667 DQS0 = 0, DQS1 = 0
896 10:54:52.569752 DQM Delay:
897 10:54:52.572933 DQM0 = 83, DQM1 = 78
898 10:54:52.573016 DQ Delay:
899 10:54:52.576373 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 10:54:52.579331 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
901 10:54:52.583071 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 10:54:52.586349 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 10:54:52.586433
904 10:54:52.586499
905 10:54:52.586560 ==
906 10:54:52.589910 Dram Type= 6, Freq= 0, CH_0, rank 0
907 10:54:52.593128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 10:54:52.593213 ==
909 10:54:52.593280
910 10:54:52.596388
911 10:54:52.596472 TX Vref Scan disable
912 10:54:52.599982 == TX Byte 0 ==
913 10:54:52.603340 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 10:54:52.606795 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 10:54:52.609415 == TX Byte 1 ==
916 10:54:52.612703 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 10:54:52.616080 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 10:54:52.616164 ==
919 10:54:52.619512 Dram Type= 6, Freq= 0, CH_0, rank 0
920 10:54:52.626663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 10:54:52.626747 ==
922 10:54:52.638842 TX Vref=22, minBit 5, minWin=27, winSum=442
923 10:54:52.641611 TX Vref=24, minBit 7, minWin=27, winSum=445
924 10:54:52.644906 TX Vref=26, minBit 5, minWin=27, winSum=448
925 10:54:52.647910 TX Vref=28, minBit 12, minWin=27, winSum=452
926 10:54:52.651589 TX Vref=30, minBit 2, minWin=28, winSum=455
927 10:54:52.658844 TX Vref=32, minBit 12, minWin=27, winSum=454
928 10:54:52.661342 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
929 10:54:52.661427
930 10:54:52.664813 Final TX Range 1 Vref 30
931 10:54:52.664896
932 10:54:52.664961 ==
933 10:54:52.668109 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:54:52.671282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:54:52.674802 ==
936 10:54:52.674885
937 10:54:52.674950
938 10:54:52.675013 TX Vref Scan disable
939 10:54:52.678424 == TX Byte 0 ==
940 10:54:52.681825 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 10:54:52.688698 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 10:54:52.688781 == TX Byte 1 ==
943 10:54:52.691643 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 10:54:52.694888 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 10:54:52.698273
946 10:54:52.698355 [DATLAT]
947 10:54:52.698420 Freq=800, CH0 RK0
948 10:54:52.698480
949 10:54:52.701570 DATLAT Default: 0xa
950 10:54:52.701652 0, 0xFFFF, sum = 0
951 10:54:52.705236 1, 0xFFFF, sum = 0
952 10:54:52.705323 2, 0xFFFF, sum = 0
953 10:54:52.709002 3, 0xFFFF, sum = 0
954 10:54:52.709085 4, 0xFFFF, sum = 0
955 10:54:52.712038 5, 0xFFFF, sum = 0
956 10:54:52.715014 6, 0xFFFF, sum = 0
957 10:54:52.715098 7, 0xFFFF, sum = 0
958 10:54:52.718678 8, 0xFFFF, sum = 0
959 10:54:52.718763 9, 0x0, sum = 1
960 10:54:52.718831 10, 0x0, sum = 2
961 10:54:52.722044 11, 0x0, sum = 3
962 10:54:52.722128 12, 0x0, sum = 4
963 10:54:52.725208 best_step = 10
964 10:54:52.725291
965 10:54:52.725357 ==
966 10:54:52.728271 Dram Type= 6, Freq= 0, CH_0, rank 0
967 10:54:52.731602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 10:54:52.731685 ==
969 10:54:52.734960 RX Vref Scan: 1
970 10:54:52.735044
971 10:54:52.735110 Set Vref Range= 32 -> 127
972 10:54:52.735172
973 10:54:52.738497 RX Vref 32 -> 127, step: 1
974 10:54:52.738580
975 10:54:52.741589 RX Delay -95 -> 252, step: 8
976 10:54:52.741680
977 10:54:52.745009 Set Vref, RX VrefLevel [Byte0]: 32
978 10:54:52.748397 [Byte1]: 32
979 10:54:52.748480
980 10:54:52.751764 Set Vref, RX VrefLevel [Byte0]: 33
981 10:54:52.755567 [Byte1]: 33
982 10:54:52.755650
983 10:54:52.758696 Set Vref, RX VrefLevel [Byte0]: 34
984 10:54:52.762175 [Byte1]: 34
985 10:54:52.766517
986 10:54:52.766600 Set Vref, RX VrefLevel [Byte0]: 35
987 10:54:52.769575 [Byte1]: 35
988 10:54:52.774109
989 10:54:52.774192 Set Vref, RX VrefLevel [Byte0]: 36
990 10:54:52.777501 [Byte1]: 36
991 10:54:52.781917
992 10:54:52.782000 Set Vref, RX VrefLevel [Byte0]: 37
993 10:54:52.785266 [Byte1]: 37
994 10:54:52.789229
995 10:54:52.789319 Set Vref, RX VrefLevel [Byte0]: 38
996 10:54:52.792793 [Byte1]: 38
997 10:54:52.796890
998 10:54:52.797019 Set Vref, RX VrefLevel [Byte0]: 39
999 10:54:52.800674 [Byte1]: 39
1000 10:54:52.804644
1001 10:54:52.804758 Set Vref, RX VrefLevel [Byte0]: 40
1002 10:54:52.807816 [Byte1]: 40
1003 10:54:52.811687
1004 10:54:52.815295 Set Vref, RX VrefLevel [Byte0]: 41
1005 10:54:52.815424 [Byte1]: 41
1006 10:54:52.819127
1007 10:54:52.819210 Set Vref, RX VrefLevel [Byte0]: 42
1008 10:54:52.822624 [Byte1]: 42
1009 10:54:52.826748
1010 10:54:52.826833 Set Vref, RX VrefLevel [Byte0]: 43
1011 10:54:52.830580 [Byte1]: 43
1012 10:54:52.834718
1013 10:54:52.834804 Set Vref, RX VrefLevel [Byte0]: 44
1014 10:54:52.837714 [Byte1]: 44
1015 10:54:52.842070
1016 10:54:52.842157 Set Vref, RX VrefLevel [Byte0]: 45
1017 10:54:52.845827 [Byte1]: 45
1018 10:54:52.849819
1019 10:54:52.849905 Set Vref, RX VrefLevel [Byte0]: 46
1020 10:54:52.853016 [Byte1]: 46
1021 10:54:52.857537
1022 10:54:52.857622 Set Vref, RX VrefLevel [Byte0]: 47
1023 10:54:52.860890 [Byte1]: 47
1024 10:54:52.864836
1025 10:54:52.864924 Set Vref, RX VrefLevel [Byte0]: 48
1026 10:54:52.868688 [Byte1]: 48
1027 10:54:52.872383
1028 10:54:52.872465 Set Vref, RX VrefLevel [Byte0]: 49
1029 10:54:52.875676 [Byte1]: 49
1030 10:54:52.880043
1031 10:54:52.880129 Set Vref, RX VrefLevel [Byte0]: 50
1032 10:54:52.883323 [Byte1]: 50
1033 10:54:52.887586
1034 10:54:52.887669 Set Vref, RX VrefLevel [Byte0]: 51
1035 10:54:52.891386 [Byte1]: 51
1036 10:54:52.895219
1037 10:54:52.895311 Set Vref, RX VrefLevel [Byte0]: 52
1038 10:54:52.898755 [Byte1]: 52
1039 10:54:52.903134
1040 10:54:52.903217 Set Vref, RX VrefLevel [Byte0]: 53
1041 10:54:52.906246 [Byte1]: 53
1042 10:54:52.910596
1043 10:54:52.910679 Set Vref, RX VrefLevel [Byte0]: 54
1044 10:54:52.913833 [Byte1]: 54
1045 10:54:52.917947
1046 10:54:52.918030 Set Vref, RX VrefLevel [Byte0]: 55
1047 10:54:52.921618 [Byte1]: 55
1048 10:54:52.925670
1049 10:54:52.925753 Set Vref, RX VrefLevel [Byte0]: 56
1050 10:54:52.929130 [Byte1]: 56
1051 10:54:52.933035
1052 10:54:52.933119 Set Vref, RX VrefLevel [Byte0]: 57
1053 10:54:52.936471 [Byte1]: 57
1054 10:54:52.940598
1055 10:54:52.940684 Set Vref, RX VrefLevel [Byte0]: 58
1056 10:54:52.944069 [Byte1]: 58
1057 10:54:52.948702
1058 10:54:52.948788 Set Vref, RX VrefLevel [Byte0]: 59
1059 10:54:52.951779 [Byte1]: 59
1060 10:54:52.955824
1061 10:54:52.955931 Set Vref, RX VrefLevel [Byte0]: 60
1062 10:54:52.959335 [Byte1]: 60
1063 10:54:52.963634
1064 10:54:52.963718 Set Vref, RX VrefLevel [Byte0]: 61
1065 10:54:52.967220 [Byte1]: 61
1066 10:54:52.971647
1067 10:54:52.971736 Set Vref, RX VrefLevel [Byte0]: 62
1068 10:54:52.974349 [Byte1]: 62
1069 10:54:52.979109
1070 10:54:52.979200 Set Vref, RX VrefLevel [Byte0]: 63
1071 10:54:52.982335 [Byte1]: 63
1072 10:54:52.986265
1073 10:54:52.986351 Set Vref, RX VrefLevel [Byte0]: 64
1074 10:54:52.990160 [Byte1]: 64
1075 10:54:52.994134
1076 10:54:52.994220 Set Vref, RX VrefLevel [Byte0]: 65
1077 10:54:52.997308 [Byte1]: 65
1078 10:54:53.001848
1079 10:54:53.001935 Set Vref, RX VrefLevel [Byte0]: 66
1080 10:54:53.004795 [Byte1]: 66
1081 10:54:53.009369
1082 10:54:53.009454 Set Vref, RX VrefLevel [Byte0]: 67
1083 10:54:53.012851 [Byte1]: 67
1084 10:54:53.016677
1085 10:54:53.016776 Set Vref, RX VrefLevel [Byte0]: 68
1086 10:54:53.020064 [Byte1]: 68
1087 10:54:53.024523
1088 10:54:53.024613 Set Vref, RX VrefLevel [Byte0]: 69
1089 10:54:53.027607 [Byte1]: 69
1090 10:54:53.032142
1091 10:54:53.032248 Set Vref, RX VrefLevel [Byte0]: 70
1092 10:54:53.035607 [Byte1]: 70
1093 10:54:53.039875
1094 10:54:53.039971 Set Vref, RX VrefLevel [Byte0]: 71
1095 10:54:53.043184 [Byte1]: 71
1096 10:54:53.047244
1097 10:54:53.047333 Set Vref, RX VrefLevel [Byte0]: 72
1098 10:54:53.050329 [Byte1]: 72
1099 10:54:53.054588
1100 10:54:53.054682 Set Vref, RX VrefLevel [Byte0]: 73
1101 10:54:53.057952 [Byte1]: 73
1102 10:54:53.062600
1103 10:54:53.062688 Set Vref, RX VrefLevel [Byte0]: 74
1104 10:54:53.065516 [Byte1]: 74
1105 10:54:53.069962
1106 10:54:53.070060 Set Vref, RX VrefLevel [Byte0]: 75
1107 10:54:53.073002 [Byte1]: 75
1108 10:54:53.078260
1109 10:54:53.078355 Set Vref, RX VrefLevel [Byte0]: 76
1110 10:54:53.080672 [Byte1]: 76
1111 10:54:53.085532
1112 10:54:53.085638 Final RX Vref Byte 0 = 58 to rank0
1113 10:54:53.088638 Final RX Vref Byte 1 = 58 to rank0
1114 10:54:53.091976 Final RX Vref Byte 0 = 58 to rank1
1115 10:54:53.095545 Final RX Vref Byte 1 = 58 to rank1==
1116 10:54:53.098647 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 10:54:53.105359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 10:54:53.105456 ==
1119 10:54:53.105525 DQS Delay:
1120 10:54:53.105586 DQS0 = 0, DQS1 = 0
1121 10:54:53.108592 DQM Delay:
1122 10:54:53.108676 DQM0 = 86, DQM1 = 79
1123 10:54:53.111833 DQ Delay:
1124 10:54:53.115364 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1125 10:54:53.115466 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1126 10:54:53.118588 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1127 10:54:53.121686 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1128 10:54:53.125847
1129 10:54:53.125940
1130 10:54:53.132059 [DQSOSCAuto] RK0, (LSB)MR18= 0x270d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1131 10:54:53.135304 CH0 RK0: MR19=606, MR18=270D
1132 10:54:53.141722 CH0_RK0: MR19=0x606, MR18=0x270D, DQSOSC=400, MR23=63, INC=92, DEC=61
1133 10:54:53.141824
1134 10:54:53.145658 ----->DramcWriteLeveling(PI) begin...
1135 10:54:53.145747 ==
1136 10:54:53.148940 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 10:54:53.152118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 10:54:53.152212 ==
1139 10:54:53.155345 Write leveling (Byte 0): 30 => 30
1140 10:54:53.158954 Write leveling (Byte 1): 31 => 31
1141 10:54:53.161739 DramcWriteLeveling(PI) end<-----
1142 10:54:53.161829
1143 10:54:53.161895 ==
1144 10:54:53.165260 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 10:54:53.168749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 10:54:53.168836 ==
1147 10:54:53.172055 [Gating] SW mode calibration
1148 10:54:53.178906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 10:54:53.185571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 10:54:53.188592 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 10:54:53.232895 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1152 10:54:53.233431 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 10:54:53.233841 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 10:54:53.233948 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 10:54:53.234413 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:54:53.234704 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:54:53.234955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:54:53.235239 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:54:53.235312 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:54:53.235575 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:54:53.277274 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:54:53.278148 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:54:53.278415 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:54:53.278486 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:54:53.278548 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:54:53.278787 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:54:53.279030 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1168 10:54:53.279493 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1169 10:54:53.279576 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:54:53.279820 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:54:53.288809 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:54:53.289110 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:54:53.292540 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:54:53.295366 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:54:53.298636 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1176 10:54:53.302068 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1177 10:54:53.308521 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1178 10:54:53.312214 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 10:54:53.315651 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:54:53.322018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:54:53.325398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:54:53.329312 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:54:53.332415 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1184 10:54:53.338425 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
1185 10:54:53.342327 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1186 10:54:53.345291 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:54:53.352216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:54:53.355157 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:54:53.359238 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:54:53.362630 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:54:53.369955 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1192 10:54:53.373489 0 11 8 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
1193 10:54:53.376590 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1194 10:54:53.383242 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 10:54:53.386629 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 10:54:53.390247 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:54:53.394090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:54:53.400592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:54:53.404082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 10:54:53.406974 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1201 10:54:53.414321 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 10:54:53.417498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 10:54:53.420623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:54:53.427575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:54:53.430910 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:54:53.434180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:54:53.437351 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:54:53.443838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:54:53.447465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:54:53.450499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:54:53.457112 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:54:53.461067 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:54:53.463980 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:54:53.470963 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:54:53.473662 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 10:54:53.477446 Total UI for P1: 0, mck2ui 16
1217 10:54:53.480504 best dqsien dly found for B0: ( 0, 14, 2)
1218 10:54:53.483774 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 10:54:53.490441 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 10:54:53.494027 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 10:54:53.497295 Total UI for P1: 0, mck2ui 16
1222 10:54:53.500377 best dqsien dly found for B1: ( 0, 14, 8)
1223 10:54:53.504265 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1224 10:54:53.507156 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 10:54:53.507246
1226 10:54:53.510631 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1227 10:54:53.513888 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 10:54:53.517009 [Gating] SW calibration Done
1229 10:54:53.517095 ==
1230 10:54:53.520711 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 10:54:53.523704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 10:54:53.523792 ==
1233 10:54:53.527049 RX Vref Scan: 0
1234 10:54:53.527133
1235 10:54:53.530735 RX Vref 0 -> 0, step: 1
1236 10:54:53.530850
1237 10:54:53.534103 RX Delay -130 -> 252, step: 16
1238 10:54:53.537012 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1239 10:54:53.540627 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1240 10:54:53.543892 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1241 10:54:53.547167 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1242 10:54:53.550672 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1243 10:54:53.557265 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1244 10:54:53.560823 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1245 10:54:53.564062 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1246 10:54:53.567320 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1247 10:54:53.570919 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1248 10:54:53.576903 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 10:54:53.580495 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1250 10:54:53.583859 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1251 10:54:53.587123 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1252 10:54:53.593750 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1253 10:54:53.597398 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1254 10:54:53.597496 ==
1255 10:54:53.600310 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 10:54:53.603533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 10:54:53.603613 ==
1258 10:54:53.606901 DQS Delay:
1259 10:54:53.606987 DQS0 = 0, DQS1 = 0
1260 10:54:53.607053 DQM Delay:
1261 10:54:53.610413 DQM0 = 90, DQM1 = 78
1262 10:54:53.610499 DQ Delay:
1263 10:54:53.613855 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1264 10:54:53.617320 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1265 10:54:53.620867 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1266 10:54:53.623608 DQ12 =69, DQ13 =93, DQ14 =93, DQ15 =93
1267 10:54:53.623696
1268 10:54:53.623763
1269 10:54:53.623823 ==
1270 10:54:53.627212 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 10:54:53.633898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 10:54:53.634004 ==
1273 10:54:53.634073
1274 10:54:53.634135
1275 10:54:53.634194 TX Vref Scan disable
1276 10:54:53.636907 == TX Byte 0 ==
1277 10:54:53.640645 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 10:54:53.643894 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 10:54:53.647047 == TX Byte 1 ==
1280 10:54:53.650783 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1281 10:54:53.657456 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1282 10:54:53.657581 ==
1283 10:54:53.660541 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 10:54:53.663569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 10:54:53.663658 ==
1286 10:54:53.676002 TX Vref=22, minBit 0, minWin=27, winSum=446
1287 10:54:53.679255 TX Vref=24, minBit 3, minWin=27, winSum=445
1288 10:54:53.683163 TX Vref=26, minBit 3, minWin=27, winSum=450
1289 10:54:53.686227 TX Vref=28, minBit 3, minWin=27, winSum=449
1290 10:54:53.689466 TX Vref=30, minBit 3, minWin=27, winSum=452
1291 10:54:53.693130 TX Vref=32, minBit 0, minWin=28, winSum=453
1292 10:54:53.699364 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1293 10:54:53.699500
1294 10:54:53.703259 Final TX Range 1 Vref 32
1295 10:54:53.703429
1296 10:54:53.703508 ==
1297 10:54:53.706089 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 10:54:53.709446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 10:54:53.709532 ==
1300 10:54:53.709598
1301 10:54:53.712639
1302 10:54:53.712722 TX Vref Scan disable
1303 10:54:53.716658 == TX Byte 0 ==
1304 10:54:53.719487 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 10:54:53.722778 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 10:54:53.726308 == TX Byte 1 ==
1307 10:54:53.729464 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1308 10:54:53.732618 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1309 10:54:53.732706
1310 10:54:53.736495 [DATLAT]
1311 10:54:53.736581 Freq=800, CH0 RK1
1312 10:54:53.736646
1313 10:54:53.740139 DATLAT Default: 0xa
1314 10:54:53.740222 0, 0xFFFF, sum = 0
1315 10:54:53.742961 1, 0xFFFF, sum = 0
1316 10:54:53.743044 2, 0xFFFF, sum = 0
1317 10:54:53.746426 3, 0xFFFF, sum = 0
1318 10:54:53.746509 4, 0xFFFF, sum = 0
1319 10:54:53.749564 5, 0xFFFF, sum = 0
1320 10:54:53.749650 6, 0xFFFF, sum = 0
1321 10:54:53.753100 7, 0xFFFF, sum = 0
1322 10:54:53.753191 8, 0xFFFF, sum = 0
1323 10:54:53.756201 9, 0x0, sum = 1
1324 10:54:53.756285 10, 0x0, sum = 2
1325 10:54:53.759794 11, 0x0, sum = 3
1326 10:54:53.759905 12, 0x0, sum = 4
1327 10:54:53.763059 best_step = 10
1328 10:54:53.763152
1329 10:54:53.763216 ==
1330 10:54:53.766175 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 10:54:53.769557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 10:54:53.769641 ==
1333 10:54:53.773165 RX Vref Scan: 0
1334 10:54:53.773249
1335 10:54:53.773314 RX Vref 0 -> 0, step: 1
1336 10:54:53.773373
1337 10:54:53.776293 RX Delay -95 -> 252, step: 8
1338 10:54:53.782988 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1339 10:54:53.786094 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1340 10:54:53.789372 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1341 10:54:53.792662 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1342 10:54:53.796210 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1343 10:54:53.802862 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1344 10:54:53.806191 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1345 10:54:53.809586 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1346 10:54:53.813182 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1347 10:54:53.815940 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1348 10:54:53.822592 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1349 10:54:53.826384 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1350 10:54:53.829917 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1351 10:54:53.833039 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1352 10:54:53.835956 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1353 10:54:53.842617 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1354 10:54:53.842720 ==
1355 10:54:53.845961 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 10:54:53.849987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 10:54:53.850075 ==
1358 10:54:53.850151 DQS Delay:
1359 10:54:53.852750 DQS0 = 0, DQS1 = 0
1360 10:54:53.852831 DQM Delay:
1361 10:54:53.855958 DQM0 = 87, DQM1 = 77
1362 10:54:53.856042 DQ Delay:
1363 10:54:53.859581 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1364 10:54:53.862843 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1365 10:54:53.866245 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1366 10:54:53.869129 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1367 10:54:53.869214
1368 10:54:53.869278
1369 10:54:53.875937 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1370 10:54:53.879285 CH0 RK1: MR19=606, MR18=2E16
1371 10:54:53.886185 CH0_RK1: MR19=0x606, MR18=0x2E16, DQSOSC=398, MR23=63, INC=93, DEC=62
1372 10:54:53.889028 [RxdqsGatingPostProcess] freq 800
1373 10:54:53.895840 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 10:54:53.899285 Pre-setting of DQS Precalculation
1375 10:54:53.902828 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 10:54:53.902932 ==
1377 10:54:53.905986 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 10:54:53.909451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 10:54:53.909537 ==
1380 10:54:53.915981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 10:54:53.922683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 10:54:53.930880 [CA 0] Center 36 (6~66) winsize 61
1383 10:54:53.934254 [CA 1] Center 36 (6~66) winsize 61
1384 10:54:53.937545 [CA 2] Center 34 (4~65) winsize 62
1385 10:54:53.940773 [CA 3] Center 33 (3~64) winsize 62
1386 10:54:53.944243 [CA 4] Center 34 (4~65) winsize 62
1387 10:54:53.947788 [CA 5] Center 33 (3~64) winsize 62
1388 10:54:53.947875
1389 10:54:53.951118 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1390 10:54:53.951201
1391 10:54:53.953896 [CATrainingPosCal] consider 1 rank data
1392 10:54:53.957142 u2DelayCellTimex100 = 270/100 ps
1393 10:54:53.960487 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 10:54:53.967034 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1395 10:54:53.970656 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 10:54:53.973888 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 10:54:53.977404 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 10:54:53.980386 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 10:54:53.980478
1400 10:54:53.983669 CA PerBit enable=1, Macro0, CA PI delay=33
1401 10:54:53.983751
1402 10:54:53.987051 [CBTSetCACLKResult] CA Dly = 33
1403 10:54:53.990145 CS Dly: 4 (0~35)
1404 10:54:53.990229 ==
1405 10:54:53.993838 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 10:54:53.996744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 10:54:53.996838 ==
1408 10:54:54.000156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 10:54:54.007055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 10:54:54.016764 [CA 0] Center 36 (6~66) winsize 61
1411 10:54:54.020104 [CA 1] Center 36 (6~66) winsize 61
1412 10:54:54.023622 [CA 2] Center 34 (4~64) winsize 61
1413 10:54:54.027061 [CA 3] Center 33 (3~64) winsize 62
1414 10:54:54.031173 [CA 4] Center 34 (3~65) winsize 63
1415 10:54:54.035053 [CA 5] Center 33 (3~64) winsize 62
1416 10:54:54.035155
1417 10:54:54.038627 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 10:54:54.038724
1419 10:54:54.043042 [CATrainingPosCal] consider 2 rank data
1420 10:54:54.046056 u2DelayCellTimex100 = 270/100 ps
1421 10:54:54.050205 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 10:54:54.053065 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1423 10:54:54.056562 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1424 10:54:54.060592 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 10:54:54.064168 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1426 10:54:54.067768 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 10:54:54.067865
1428 10:54:54.070775 CA PerBit enable=1, Macro0, CA PI delay=33
1429 10:54:54.070861
1430 10:54:54.074872 [CBTSetCACLKResult] CA Dly = 33
1431 10:54:54.074961 CS Dly: 5 (0~37)
1432 10:54:54.075028
1433 10:54:54.077584 ----->DramcWriteLeveling(PI) begin...
1434 10:54:54.077669 ==
1435 10:54:54.080592 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 10:54:54.087133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 10:54:54.087247 ==
1438 10:54:54.090601 Write leveling (Byte 0): 28 => 28
1439 10:54:54.090692 Write leveling (Byte 1): 28 => 28
1440 10:54:54.093995 DramcWriteLeveling(PI) end<-----
1441 10:54:54.094082
1442 10:54:54.094148 ==
1443 10:54:54.097269 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 10:54:54.104122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 10:54:54.104223 ==
1446 10:54:54.107699 [Gating] SW mode calibration
1447 10:54:54.114028 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 10:54:54.117747 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 10:54:54.124166 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 10:54:54.127288 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 10:54:54.130739 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1452 10:54:54.133985 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:54:54.140758 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:54:54.144031 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:54:54.147292 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:54:54.154161 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:54:54.157409 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:54:54.160824 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:54:54.167180 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:54:54.171261 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:54:54.174249 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:54:54.180920 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:54:54.184070 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 10:54:54.187576 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1465 10:54:54.194727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:54:54.198300 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 10:54:54.200952 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 10:54:54.207811 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:54:54.210840 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:54:54.214282 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:54:54.218062 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:54:54.224647 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1473 10:54:54.228130 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:54:54.231251 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 10:54:54.237816 0 9 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1476 10:54:54.241665 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 10:54:54.244940 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 10:54:54.251205 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:54:54.254556 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:54:54.257792 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 10:54:54.264583 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1482 10:54:54.268391 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 10:54:54.271414 0 10 8 | B1->B0 | 2e2e 2f2f | 0 0 | (1 0) (0 0)
1484 10:54:54.277642 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 10:54:54.280945 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:54:54.284512 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:54:54.291708 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:54:54.294728 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 10:54:54.297590 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:54:54.301515 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1491 10:54:54.308028 0 11 8 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
1492 10:54:54.311229 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 10:54:54.314641 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 10:54:54.321443 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:54:54.325100 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:54:54.328088 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 10:54:54.334538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 10:54:54.337759 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 10:54:54.341600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 10:54:54.348528 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1501 10:54:54.351162 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:54:54.354945 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:54:54.361426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:54:54.364843 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:54:54.368251 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:54:54.371376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:54:54.378138 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:54:54.381179 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:54:54.384865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:54:54.391120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:54:54.394791 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:54:54.397889 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:54:54.404610 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:54:54.407851 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:54:54.411918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 10:54:54.414513 Total UI for P1: 0, mck2ui 16
1517 10:54:54.418540 best dqsien dly found for B0: ( 0, 14, 6)
1518 10:54:54.424805 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 10:54:54.427951 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 10:54:54.431405 Total UI for P1: 0, mck2ui 16
1521 10:54:54.434562 best dqsien dly found for B1: ( 0, 14, 10)
1522 10:54:54.438016 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 10:54:54.441148 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1524 10:54:54.441242
1525 10:54:54.444814 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 10:54:54.448079 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1527 10:54:54.451767 [Gating] SW calibration Done
1528 10:54:54.451860 ==
1529 10:54:54.454666 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 10:54:54.457879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 10:54:54.460987 ==
1532 10:54:54.461089 RX Vref Scan: 0
1533 10:54:54.461176
1534 10:54:54.464603 RX Vref 0 -> 0, step: 1
1535 10:54:54.464716
1536 10:54:54.467753 RX Delay -130 -> 252, step: 16
1537 10:54:54.471996 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 10:54:54.474657 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1539 10:54:54.477897 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 10:54:54.481237 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1541 10:54:54.487901 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1542 10:54:54.491265 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 10:54:54.494496 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1544 10:54:54.497730 iDelay=222, Bit 7, Center 69 (-50 ~ 189) 240
1545 10:54:54.501429 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 10:54:54.504657 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1547 10:54:54.511210 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 10:54:54.514600 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 10:54:54.518089 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 10:54:54.521204 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 10:54:54.527802 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 10:54:54.530980 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 10:54:54.531080 ==
1554 10:54:54.534355 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 10:54:54.537612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 10:54:54.537702 ==
1557 10:54:54.537769 DQS Delay:
1558 10:54:54.541349 DQS0 = 0, DQS1 = 0
1559 10:54:54.541434 DQM Delay:
1560 10:54:54.544486 DQM0 = 81, DQM1 = 75
1561 10:54:54.544571 DQ Delay:
1562 10:54:54.548117 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1563 10:54:54.551249 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1564 10:54:54.554382 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1565 10:54:54.558043 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 10:54:54.558139
1567 10:54:54.558205
1568 10:54:54.558265 ==
1569 10:54:54.561283 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 10:54:54.564533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 10:54:54.567674 ==
1572 10:54:54.567766
1573 10:54:54.567832
1574 10:54:54.567891 TX Vref Scan disable
1575 10:54:54.570894 == TX Byte 0 ==
1576 10:54:54.574486 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 10:54:54.578008 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 10:54:54.581372 == TX Byte 1 ==
1579 10:54:54.584404 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1580 10:54:54.587688 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1581 10:54:54.590954 ==
1582 10:54:54.591051 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 10:54:54.597979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 10:54:54.598090 ==
1585 10:54:54.610302 TX Vref=22, minBit 0, minWin=27, winSum=442
1586 10:54:54.614264 TX Vref=24, minBit 0, minWin=27, winSum=442
1587 10:54:54.617499 TX Vref=26, minBit 0, minWin=27, winSum=443
1588 10:54:54.620663 TX Vref=28, minBit 9, minWin=27, winSum=450
1589 10:54:54.623838 TX Vref=30, minBit 11, minWin=27, winSum=454
1590 10:54:54.627556 TX Vref=32, minBit 1, minWin=28, winSum=456
1591 10:54:54.634258 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1592 10:54:54.634365
1593 10:54:54.637170 Final TX Range 1 Vref 32
1594 10:54:54.637258
1595 10:54:54.637324 ==
1596 10:54:54.640639 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 10:54:54.644149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 10:54:54.644240 ==
1599 10:54:54.644308
1600 10:54:54.644369
1601 10:54:54.648127 TX Vref Scan disable
1602 10:54:54.650665 == TX Byte 0 ==
1603 10:54:54.654360 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1604 10:54:54.657489 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1605 10:54:54.661115 == TX Byte 1 ==
1606 10:54:54.664576 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 10:54:54.667259 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 10:54:54.667361
1609 10:54:54.670738 [DATLAT]
1610 10:54:54.670823 Freq=800, CH1 RK0
1611 10:54:54.670891
1612 10:54:54.674020 DATLAT Default: 0xa
1613 10:54:54.674105 0, 0xFFFF, sum = 0
1614 10:54:54.677482 1, 0xFFFF, sum = 0
1615 10:54:54.677571 2, 0xFFFF, sum = 0
1616 10:54:54.681305 3, 0xFFFF, sum = 0
1617 10:54:54.681394 4, 0xFFFF, sum = 0
1618 10:54:54.684285 5, 0xFFFF, sum = 0
1619 10:54:54.684372 6, 0xFFFF, sum = 0
1620 10:54:54.687346 7, 0xFFFF, sum = 0
1621 10:54:54.687457 8, 0xFFFF, sum = 0
1622 10:54:54.690489 9, 0x0, sum = 1
1623 10:54:54.690576 10, 0x0, sum = 2
1624 10:54:54.694053 11, 0x0, sum = 3
1625 10:54:54.694141 12, 0x0, sum = 4
1626 10:54:54.697207 best_step = 10
1627 10:54:54.697293
1628 10:54:54.697359 ==
1629 10:54:54.701448 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 10:54:54.703927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 10:54:54.704017 ==
1632 10:54:54.704084 RX Vref Scan: 1
1633 10:54:54.707285
1634 10:54:54.707397 Set Vref Range= 32 -> 127
1635 10:54:54.707465
1636 10:54:54.710646 RX Vref 32 -> 127, step: 1
1637 10:54:54.710732
1638 10:54:54.714001 RX Delay -111 -> 252, step: 8
1639 10:54:54.714087
1640 10:54:54.717124 Set Vref, RX VrefLevel [Byte0]: 32
1641 10:54:54.720820 [Byte1]: 32
1642 10:54:54.720911
1643 10:54:54.724033 Set Vref, RX VrefLevel [Byte0]: 33
1644 10:54:54.727213 [Byte1]: 33
1645 10:54:54.727302
1646 10:54:54.730546 Set Vref, RX VrefLevel [Byte0]: 34
1647 10:54:54.733852 [Byte1]: 34
1648 10:54:54.738381
1649 10:54:54.738478 Set Vref, RX VrefLevel [Byte0]: 35
1650 10:54:54.741651 [Byte1]: 35
1651 10:54:54.745611
1652 10:54:54.745708 Set Vref, RX VrefLevel [Byte0]: 36
1653 10:54:54.749078 [Byte1]: 36
1654 10:54:54.753185
1655 10:54:54.753279 Set Vref, RX VrefLevel [Byte0]: 37
1656 10:54:54.756506 [Byte1]: 37
1657 10:54:54.760953
1658 10:54:54.761065 Set Vref, RX VrefLevel [Byte0]: 38
1659 10:54:54.764408 [Byte1]: 38
1660 10:54:54.768404
1661 10:54:54.768492 Set Vref, RX VrefLevel [Byte0]: 39
1662 10:54:54.772209 [Byte1]: 39
1663 10:54:54.776520
1664 10:54:54.776610 Set Vref, RX VrefLevel [Byte0]: 40
1665 10:54:54.779715 [Byte1]: 40
1666 10:54:54.784134
1667 10:54:54.787263 Set Vref, RX VrefLevel [Byte0]: 41
1668 10:54:54.790205 [Byte1]: 41
1669 10:54:54.790295
1670 10:54:54.793743 Set Vref, RX VrefLevel [Byte0]: 42
1671 10:54:54.797326 [Byte1]: 42
1672 10:54:54.797420
1673 10:54:54.800406 Set Vref, RX VrefLevel [Byte0]: 43
1674 10:54:54.803735 [Byte1]: 43
1675 10:54:54.803822
1676 10:54:54.807386 Set Vref, RX VrefLevel [Byte0]: 44
1677 10:54:54.810580 [Byte1]: 44
1678 10:54:54.814767
1679 10:54:54.814859 Set Vref, RX VrefLevel [Byte0]: 45
1680 10:54:54.821056 [Byte1]: 45
1681 10:54:54.821156
1682 10:54:54.824423 Set Vref, RX VrefLevel [Byte0]: 46
1683 10:54:54.828015 [Byte1]: 46
1684 10:54:54.828111
1685 10:54:54.831823 Set Vref, RX VrefLevel [Byte0]: 47
1686 10:54:54.834956 [Byte1]: 47
1687 10:54:54.835047
1688 10:54:54.837578 Set Vref, RX VrefLevel [Byte0]: 48
1689 10:54:54.840879 [Byte1]: 48
1690 10:54:54.845432
1691 10:54:54.845534 Set Vref, RX VrefLevel [Byte0]: 49
1692 10:54:54.848494 [Byte1]: 49
1693 10:54:54.853032
1694 10:54:54.853156 Set Vref, RX VrefLevel [Byte0]: 50
1695 10:54:54.855831 [Byte1]: 50
1696 10:54:54.860669
1697 10:54:54.860761 Set Vref, RX VrefLevel [Byte0]: 51
1698 10:54:54.863667 [Byte1]: 51
1699 10:54:54.868197
1700 10:54:54.868290 Set Vref, RX VrefLevel [Byte0]: 52
1701 10:54:54.871542 [Byte1]: 52
1702 10:54:54.876006
1703 10:54:54.876099 Set Vref, RX VrefLevel [Byte0]: 53
1704 10:54:54.879030 [Byte1]: 53
1705 10:54:54.883091
1706 10:54:54.883180 Set Vref, RX VrefLevel [Byte0]: 54
1707 10:54:54.886917 [Byte1]: 54
1708 10:54:54.891287
1709 10:54:54.891439 Set Vref, RX VrefLevel [Byte0]: 55
1710 10:54:54.894352 [Byte1]: 55
1711 10:54:54.898940
1712 10:54:54.899035 Set Vref, RX VrefLevel [Byte0]: 56
1713 10:54:54.901762 [Byte1]: 56
1714 10:54:54.906345
1715 10:54:54.906440 Set Vref, RX VrefLevel [Byte0]: 57
1716 10:54:54.909918 [Byte1]: 57
1717 10:54:54.914122
1718 10:54:54.914213 Set Vref, RX VrefLevel [Byte0]: 58
1719 10:54:54.920235 [Byte1]: 58
1720 10:54:54.920337
1721 10:54:54.924415 Set Vref, RX VrefLevel [Byte0]: 59
1722 10:54:54.926992 [Byte1]: 59
1723 10:54:54.927081
1724 10:54:54.930268 Set Vref, RX VrefLevel [Byte0]: 60
1725 10:54:54.934282 [Byte1]: 60
1726 10:54:54.934375
1727 10:54:54.937809 Set Vref, RX VrefLevel [Byte0]: 61
1728 10:54:54.940493 [Byte1]: 61
1729 10:54:54.944510
1730 10:54:54.944600 Set Vref, RX VrefLevel [Byte0]: 62
1731 10:54:54.947795 [Byte1]: 62
1732 10:54:54.952614
1733 10:54:54.952759 Set Vref, RX VrefLevel [Byte0]: 63
1734 10:54:54.955726 [Byte1]: 63
1735 10:54:54.959931
1736 10:54:54.960026 Set Vref, RX VrefLevel [Byte0]: 64
1737 10:54:54.963309 [Byte1]: 64
1738 10:54:54.967997
1739 10:54:54.968087 Set Vref, RX VrefLevel [Byte0]: 65
1740 10:54:54.970706 [Byte1]: 65
1741 10:54:54.975048
1742 10:54:54.975137 Set Vref, RX VrefLevel [Byte0]: 66
1743 10:54:54.978509 [Byte1]: 66
1744 10:54:54.982927
1745 10:54:54.983023 Set Vref, RX VrefLevel [Byte0]: 67
1746 10:54:54.986308 [Byte1]: 67
1747 10:54:54.990219
1748 10:54:54.990311 Set Vref, RX VrefLevel [Byte0]: 68
1749 10:54:54.993994 [Byte1]: 68
1750 10:54:54.998168
1751 10:54:54.998262 Set Vref, RX VrefLevel [Byte0]: 69
1752 10:54:55.001772 [Byte1]: 69
1753 10:54:55.005713
1754 10:54:55.005804 Set Vref, RX VrefLevel [Byte0]: 70
1755 10:54:55.009655 [Byte1]: 70
1756 10:54:55.013989
1757 10:54:55.014083 Set Vref, RX VrefLevel [Byte0]: 71
1758 10:54:55.016926 [Byte1]: 71
1759 10:54:55.020906
1760 10:54:55.021001 Set Vref, RX VrefLevel [Byte0]: 72
1761 10:54:55.024173 [Byte1]: 72
1762 10:54:55.028587
1763 10:54:55.028681 Set Vref, RX VrefLevel [Byte0]: 73
1764 10:54:55.032112 [Byte1]: 73
1765 10:54:55.036304
1766 10:54:55.036398 Set Vref, RX VrefLevel [Byte0]: 74
1767 10:54:55.039829 [Byte1]: 74
1768 10:54:55.044095
1769 10:54:55.044187 Set Vref, RX VrefLevel [Byte0]: 75
1770 10:54:55.047639 [Byte1]: 75
1771 10:54:55.051939
1772 10:54:55.052043 Set Vref, RX VrefLevel [Byte0]: 76
1773 10:54:55.054874 [Byte1]: 76
1774 10:54:55.060342
1775 10:54:55.060443 Set Vref, RX VrefLevel [Byte0]: 77
1776 10:54:55.062665 [Byte1]: 77
1777 10:54:55.066656
1778 10:54:55.066746 Set Vref, RX VrefLevel [Byte0]: 78
1779 10:54:55.070221 [Byte1]: 78
1780 10:54:55.075205
1781 10:54:55.075303 Set Vref, RX VrefLevel [Byte0]: 79
1782 10:54:55.078131 [Byte1]: 79
1783 10:54:55.081930
1784 10:54:55.082015 Final RX Vref Byte 0 = 61 to rank0
1785 10:54:55.085823 Final RX Vref Byte 1 = 58 to rank0
1786 10:54:55.088590 Final RX Vref Byte 0 = 61 to rank1
1787 10:54:55.091994 Final RX Vref Byte 1 = 58 to rank1==
1788 10:54:55.095615 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 10:54:55.098890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 10:54:55.102115 ==
1791 10:54:55.102207 DQS Delay:
1792 10:54:55.102274 DQS0 = 0, DQS1 = 0
1793 10:54:55.105881 DQM Delay:
1794 10:54:55.105968 DQM0 = 83, DQM1 = 74
1795 10:54:55.109047 DQ Delay:
1796 10:54:55.112289 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1797 10:54:55.112375 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1798 10:54:55.115571 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1799 10:54:55.118929 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1800 10:54:55.119040
1801 10:54:55.122030
1802 10:54:55.128960 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1803 10:54:55.132798 CH1 RK0: MR19=605, MR18=26FB
1804 10:54:55.138975 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1805 10:54:55.139085
1806 10:54:55.142262 ----->DramcWriteLeveling(PI) begin...
1807 10:54:55.142360 ==
1808 10:54:55.146013 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 10:54:55.148569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 10:54:55.148657 ==
1811 10:54:55.152363 Write leveling (Byte 0): 27 => 27
1812 10:54:55.156020 Write leveling (Byte 1): 28 => 28
1813 10:54:55.159060 DramcWriteLeveling(PI) end<-----
1814 10:54:55.159147
1815 10:54:55.159212 ==
1816 10:54:55.162186 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 10:54:55.165263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 10:54:55.165349 ==
1819 10:54:55.168822 [Gating] SW mode calibration
1820 10:54:55.176020 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 10:54:55.182284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 10:54:55.185378 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1823 10:54:55.189207 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1824 10:54:55.195407 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:54:55.198819 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:54:55.202251 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:54:55.208629 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:54:55.212261 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:54:55.215208 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:54:55.222117 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:54:55.225371 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:54:55.228675 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:54:55.235899 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 10:54:55.238512 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:54:55.241847 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:54:55.248648 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:54:55.251701 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:54:55.255210 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 10:54:55.258481 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1840 10:54:55.265327 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:54:55.268729 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:54:55.271991 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:54:55.278658 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:54:55.282158 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:54:55.285358 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:54:55.291628 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:54:55.295217 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1848 10:54:55.299064 0 9 8 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
1849 10:54:55.305071 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 10:54:55.308740 0 9 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1851 10:54:55.311726 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 10:54:55.318379 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 10:54:55.321894 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 10:54:55.325207 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1855 10:54:55.331883 0 10 4 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (0 1)
1856 10:54:55.335273 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1857 10:54:55.338955 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:54:55.345007 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:54:55.348163 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 10:54:55.351564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 10:54:55.358266 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:54:55.361674 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 10:54:55.364947 0 11 4 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
1864 10:54:55.371601 0 11 8 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
1865 10:54:55.374708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 10:54:55.378452 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 10:54:55.382113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 10:54:55.388248 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 10:54:55.391900 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 10:54:55.394860 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1871 10:54:55.401786 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1872 10:54:55.405244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:54:55.408178 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:54:55.414825 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:54:55.418548 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:54:55.421703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:54:55.428192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:54:55.431765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:54:55.434989 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 10:54:55.441413 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 10:54:55.444865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 10:54:55.448070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 10:54:55.454927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 10:54:55.458185 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 10:54:55.461295 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 10:54:55.468054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 10:54:55.471867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1888 10:54:55.475277 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1889 10:54:55.478647 Total UI for P1: 0, mck2ui 16
1890 10:54:55.482077 best dqsien dly found for B0: ( 0, 14, 2)
1891 10:54:55.484704 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 10:54:55.488670 Total UI for P1: 0, mck2ui 16
1893 10:54:55.491410 best dqsien dly found for B1: ( 0, 14, 8)
1894 10:54:55.494717 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1895 10:54:55.501350 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1896 10:54:55.501459
1897 10:54:55.504957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1898 10:54:55.508159 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1899 10:54:55.511992 [Gating] SW calibration Done
1900 10:54:55.512086 ==
1901 10:54:55.515243 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 10:54:55.518387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 10:54:55.518476 ==
1904 10:54:55.518543 RX Vref Scan: 0
1905 10:54:55.518606
1906 10:54:55.521397 RX Vref 0 -> 0, step: 1
1907 10:54:55.521482
1908 10:54:55.524794 RX Delay -130 -> 252, step: 16
1909 10:54:55.528354 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1910 10:54:55.531690 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1911 10:54:55.538221 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1912 10:54:55.542280 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1913 10:54:55.545148 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1914 10:54:55.548547 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1915 10:54:55.551497 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1916 10:54:55.558115 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1917 10:54:55.561671 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1918 10:54:55.564715 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1919 10:54:55.568072 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1920 10:54:55.571604 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1921 10:54:55.578011 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1922 10:54:55.581572 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1923 10:54:55.584985 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 10:54:55.588096 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1925 10:54:55.588187 ==
1926 10:54:55.591824 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 10:54:55.597991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 10:54:55.598097 ==
1929 10:54:55.598168 DQS Delay:
1930 10:54:55.598230 DQS0 = 0, DQS1 = 0
1931 10:54:55.601613 DQM Delay:
1932 10:54:55.601699 DQM0 = 80, DQM1 = 76
1933 10:54:55.604860 DQ Delay:
1934 10:54:55.608279 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1935 10:54:55.608368 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =69
1936 10:54:55.611931 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1937 10:54:55.614849 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1938 10:54:55.617988
1939 10:54:55.618075
1940 10:54:55.618143 ==
1941 10:54:55.621606 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 10:54:55.624762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 10:54:55.624850 ==
1944 10:54:55.624918
1945 10:54:55.624980
1946 10:54:55.628326 TX Vref Scan disable
1947 10:54:55.628411 == TX Byte 0 ==
1948 10:54:55.635406 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 10:54:55.638114 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 10:54:55.638207 == TX Byte 1 ==
1951 10:54:55.645098 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 10:54:55.648437 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 10:54:55.648534 ==
1954 10:54:55.651760 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 10:54:55.654758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 10:54:55.654854 ==
1957 10:54:55.668457 TX Vref=22, minBit 1, minWin=27, winSum=444
1958 10:54:55.671311 TX Vref=24, minBit 1, minWin=27, winSum=444
1959 10:54:55.675264 TX Vref=26, minBit 1, minWin=27, winSum=445
1960 10:54:55.678228 TX Vref=28, minBit 0, minWin=28, winSum=450
1961 10:54:55.681608 TX Vref=30, minBit 0, minWin=28, winSum=450
1962 10:54:55.688170 TX Vref=32, minBit 0, minWin=28, winSum=451
1963 10:54:55.691726 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1964 10:54:55.691827
1965 10:54:55.695120 Final TX Range 1 Vref 32
1966 10:54:55.695208
1967 10:54:55.695274 ==
1968 10:54:55.697942 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 10:54:55.701671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 10:54:55.701762 ==
1971 10:54:55.704714
1972 10:54:55.704799
1973 10:54:55.704865 TX Vref Scan disable
1974 10:54:55.708445 == TX Byte 0 ==
1975 10:54:55.711744 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1976 10:54:55.718786 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1977 10:54:55.718896 == TX Byte 1 ==
1978 10:54:55.721506 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1979 10:54:55.724991 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1980 10:54:55.727994
1981 10:54:55.728083 [DATLAT]
1982 10:54:55.728149 Freq=800, CH1 RK1
1983 10:54:55.728211
1984 10:54:55.731913 DATLAT Default: 0xa
1985 10:54:55.732000 0, 0xFFFF, sum = 0
1986 10:54:55.734855 1, 0xFFFF, sum = 0
1987 10:54:55.734942 2, 0xFFFF, sum = 0
1988 10:54:55.738148 3, 0xFFFF, sum = 0
1989 10:54:55.738234 4, 0xFFFF, sum = 0
1990 10:54:55.741401 5, 0xFFFF, sum = 0
1991 10:54:55.741491 6, 0xFFFF, sum = 0
1992 10:54:55.744809 7, 0xFFFF, sum = 0
1993 10:54:55.747860 8, 0xFFFF, sum = 0
1994 10:54:55.747951 9, 0x0, sum = 1
1995 10:54:55.748021 10, 0x0, sum = 2
1996 10:54:55.751788 11, 0x0, sum = 3
1997 10:54:55.751876 12, 0x0, sum = 4
1998 10:54:55.755150 best_step = 10
1999 10:54:55.755264
2000 10:54:55.755385 ==
2001 10:54:55.757732 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 10:54:55.761264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 10:54:55.761354 ==
2004 10:54:55.764860 RX Vref Scan: 0
2005 10:54:55.764948
2006 10:54:55.765015 RX Vref 0 -> 0, step: 1
2007 10:54:55.765078
2008 10:54:55.768073 RX Delay -111 -> 252, step: 8
2009 10:54:55.775249 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2010 10:54:55.778072 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2011 10:54:55.781636 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2012 10:54:55.785098 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2013 10:54:55.788562 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2014 10:54:55.795042 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2015 10:54:55.798367 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2016 10:54:55.801819 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2017 10:54:55.804996 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2018 10:54:55.808360 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2019 10:54:55.814742 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2020 10:54:55.817839 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2021 10:54:55.821080 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2022 10:54:55.824428 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2023 10:54:55.831893 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2024 10:54:55.834633 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2025 10:54:55.834733 ==
2026 10:54:55.838260 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 10:54:55.841595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 10:54:55.841686 ==
2029 10:54:55.841754 DQS Delay:
2030 10:54:55.844699 DQS0 = 0, DQS1 = 0
2031 10:54:55.844784 DQM Delay:
2032 10:54:55.848170 DQM0 = 80, DQM1 = 76
2033 10:54:55.848256 DQ Delay:
2034 10:54:55.851275 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2035 10:54:55.854826 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2036 10:54:55.857913 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2037 10:54:55.861203 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2038 10:54:55.861294
2039 10:54:55.861361
2040 10:54:55.871305 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2041 10:54:55.871465 CH1 RK1: MR19=606, MR18=1C27
2042 10:54:55.878163 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2043 10:54:55.880969 [RxdqsGatingPostProcess] freq 800
2044 10:54:55.887578 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 10:54:55.890821 Pre-setting of DQS Precalculation
2046 10:54:55.894671 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 10:54:55.901611 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 10:54:55.910666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 10:54:55.910793
2050 10:54:55.910864
2051 10:54:55.914441 [Calibration Summary] 1600 Mbps
2052 10:54:55.914526 CH 0, Rank 0
2053 10:54:55.917376 SW Impedance : PASS
2054 10:54:55.917461 DUTY Scan : NO K
2055 10:54:55.920607 ZQ Calibration : PASS
2056 10:54:55.924103 Jitter Meter : NO K
2057 10:54:55.924188 CBT Training : PASS
2058 10:54:55.927562 Write leveling : PASS
2059 10:54:55.927647 RX DQS gating : PASS
2060 10:54:55.930801 RX DQ/DQS(RDDQC) : PASS
2061 10:54:55.934183 TX DQ/DQS : PASS
2062 10:54:55.934269 RX DATLAT : PASS
2063 10:54:55.937277 RX DQ/DQS(Engine): PASS
2064 10:54:55.940591 TX OE : NO K
2065 10:54:55.940680 All Pass.
2066 10:54:55.940747
2067 10:54:55.940807 CH 0, Rank 1
2068 10:54:55.944070 SW Impedance : PASS
2069 10:54:55.947129 DUTY Scan : NO K
2070 10:54:55.947214 ZQ Calibration : PASS
2071 10:54:55.950491 Jitter Meter : NO K
2072 10:54:55.953733 CBT Training : PASS
2073 10:54:55.953820 Write leveling : PASS
2074 10:54:55.957432 RX DQS gating : PASS
2075 10:54:55.960626 RX DQ/DQS(RDDQC) : PASS
2076 10:54:55.960739 TX DQ/DQS : PASS
2077 10:54:55.964134 RX DATLAT : PASS
2078 10:54:55.964224 RX DQ/DQS(Engine): PASS
2079 10:54:55.967314 TX OE : NO K
2080 10:54:55.967430 All Pass.
2081 10:54:55.967496
2082 10:54:55.970741 CH 1, Rank 0
2083 10:54:55.970824 SW Impedance : PASS
2084 10:54:55.973957 DUTY Scan : NO K
2085 10:54:55.977516 ZQ Calibration : PASS
2086 10:54:55.977603 Jitter Meter : NO K
2087 10:54:55.980887 CBT Training : PASS
2088 10:54:55.983873 Write leveling : PASS
2089 10:54:55.983959 RX DQS gating : PASS
2090 10:54:55.987212 RX DQ/DQS(RDDQC) : PASS
2091 10:54:55.990406 TX DQ/DQS : PASS
2092 10:54:55.990494 RX DATLAT : PASS
2093 10:54:55.994059 RX DQ/DQS(Engine): PASS
2094 10:54:55.997169 TX OE : NO K
2095 10:54:55.997256 All Pass.
2096 10:54:55.997323
2097 10:54:55.997383 CH 1, Rank 1
2098 10:54:56.000762 SW Impedance : PASS
2099 10:54:56.003901 DUTY Scan : NO K
2100 10:54:56.003985 ZQ Calibration : PASS
2101 10:54:56.007889 Jitter Meter : NO K
2102 10:54:56.010697 CBT Training : PASS
2103 10:54:56.010783 Write leveling : PASS
2104 10:54:56.013594 RX DQS gating : PASS
2105 10:54:56.017313 RX DQ/DQS(RDDQC) : PASS
2106 10:54:56.017399 TX DQ/DQS : PASS
2107 10:54:56.020537 RX DATLAT : PASS
2108 10:54:56.020622 RX DQ/DQS(Engine): PASS
2109 10:54:56.024251 TX OE : NO K
2110 10:54:56.024336 All Pass.
2111 10:54:56.024401
2112 10:54:56.027812 DramC Write-DBI off
2113 10:54:56.030580 PER_BANK_REFRESH: Hybrid Mode
2114 10:54:56.030666 TX_TRACKING: ON
2115 10:54:56.033658 [GetDramInforAfterCalByMRR] Vendor 6.
2116 10:54:56.037506 [GetDramInforAfterCalByMRR] Revision 606.
2117 10:54:56.044262 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 10:54:56.044370 MR0 0x3b3b
2119 10:54:56.044440 MR8 0x5151
2120 10:54:56.047055 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 10:54:56.047139
2122 10:54:56.050390 MR0 0x3b3b
2123 10:54:56.050474 MR8 0x5151
2124 10:54:56.053459 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 10:54:56.053542
2126 10:54:56.063651 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 10:54:56.067081 [FAST_K] Save calibration result to emmc
2128 10:54:56.070283 [FAST_K] Save calibration result to emmc
2129 10:54:56.074119 dram_init: config_dvfs: 1
2130 10:54:56.076713 dramc_set_vcore_voltage set vcore to 662500
2131 10:54:56.080161 Read voltage for 1200, 2
2132 10:54:56.080250 Vio18 = 0
2133 10:54:56.080316 Vcore = 662500
2134 10:54:56.083314 Vdram = 0
2135 10:54:56.083446 Vddq = 0
2136 10:54:56.083512 Vmddr = 0
2137 10:54:56.089880 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 10:54:56.093085 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 10:54:56.096940 MEM_TYPE=3, freq_sel=15
2140 10:54:56.099836 sv_algorithm_assistance_LP4_1600
2141 10:54:56.103342 ============ PULL DRAM RESETB DOWN ============
2142 10:54:56.106779 ========== PULL DRAM RESETB DOWN end =========
2143 10:54:56.113245 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 10:54:56.116457 ===================================
2145 10:54:56.116555 LPDDR4 DRAM CONFIGURATION
2146 10:54:56.119876 ===================================
2147 10:54:56.123259 EX_ROW_EN[0] = 0x0
2148 10:54:56.126605 EX_ROW_EN[1] = 0x0
2149 10:54:56.126694 LP4Y_EN = 0x0
2150 10:54:56.129907 WORK_FSP = 0x0
2151 10:54:56.129994 WL = 0x4
2152 10:54:56.133369 RL = 0x4
2153 10:54:56.133455 BL = 0x2
2154 10:54:56.136917 RPST = 0x0
2155 10:54:56.137002 RD_PRE = 0x0
2156 10:54:56.139680 WR_PRE = 0x1
2157 10:54:56.139765 WR_PST = 0x0
2158 10:54:56.142850 DBI_WR = 0x0
2159 10:54:56.142936 DBI_RD = 0x0
2160 10:54:56.146132 OTF = 0x1
2161 10:54:56.149385 ===================================
2162 10:54:56.153058 ===================================
2163 10:54:56.153147 ANA top config
2164 10:54:56.156549 ===================================
2165 10:54:56.160119 DLL_ASYNC_EN = 0
2166 10:54:56.162687 ALL_SLAVE_EN = 0
2167 10:54:56.166466 NEW_RANK_MODE = 1
2168 10:54:56.166556 DLL_IDLE_MODE = 1
2169 10:54:56.169473 LP45_APHY_COMB_EN = 1
2170 10:54:56.173287 TX_ODT_DIS = 1
2171 10:54:56.176263 NEW_8X_MODE = 1
2172 10:54:56.179581 ===================================
2173 10:54:56.182934 ===================================
2174 10:54:56.186055 data_rate = 2400
2175 10:54:56.186144 CKR = 1
2176 10:54:56.189558 DQ_P2S_RATIO = 8
2177 10:54:56.192661 ===================================
2178 10:54:56.196969 CA_P2S_RATIO = 8
2179 10:54:56.199854 DQ_CA_OPEN = 0
2180 10:54:56.203233 DQ_SEMI_OPEN = 0
2181 10:54:56.203323 CA_SEMI_OPEN = 0
2182 10:54:56.206084 CA_FULL_RATE = 0
2183 10:54:56.209369 DQ_CKDIV4_EN = 0
2184 10:54:56.212582 CA_CKDIV4_EN = 0
2185 10:54:56.216257 CA_PREDIV_EN = 0
2186 10:54:56.219299 PH8_DLY = 17
2187 10:54:56.219431 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 10:54:56.222964 DQ_AAMCK_DIV = 4
2189 10:54:56.226454 CA_AAMCK_DIV = 4
2190 10:54:56.229514 CA_ADMCK_DIV = 4
2191 10:54:56.233110 DQ_TRACK_CA_EN = 0
2192 10:54:56.236107 CA_PICK = 1200
2193 10:54:56.239130 CA_MCKIO = 1200
2194 10:54:56.239216 MCKIO_SEMI = 0
2195 10:54:56.242636 PLL_FREQ = 2366
2196 10:54:56.246255 DQ_UI_PI_RATIO = 32
2197 10:54:56.249358 CA_UI_PI_RATIO = 0
2198 10:54:56.252365 ===================================
2199 10:54:56.256344 ===================================
2200 10:54:56.259176 memory_type:LPDDR4
2201 10:54:56.259291 GP_NUM : 10
2202 10:54:56.262947 SRAM_EN : 1
2203 10:54:56.265727 MD32_EN : 0
2204 10:54:56.269515 ===================================
2205 10:54:56.269604 [ANA_INIT] >>>>>>>>>>>>>>
2206 10:54:56.272503 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 10:54:56.275558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 10:54:56.279179 ===================================
2209 10:54:56.282478 data_rate = 2400,PCW = 0X5b00
2210 10:54:56.286332 ===================================
2211 10:54:56.289526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 10:54:56.296349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 10:54:56.299024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 10:54:56.305659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 10:54:56.308963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 10:54:56.312707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 10:54:56.312800 [ANA_INIT] flow start
2218 10:54:56.316011 [ANA_INIT] PLL >>>>>>>>
2219 10:54:56.319203 [ANA_INIT] PLL <<<<<<<<
2220 10:54:56.319290 [ANA_INIT] MIDPI >>>>>>>>
2221 10:54:56.322638 [ANA_INIT] MIDPI <<<<<<<<
2222 10:54:56.325640 [ANA_INIT] DLL >>>>>>>>
2223 10:54:56.328936 [ANA_INIT] DLL <<<<<<<<
2224 10:54:56.329025 [ANA_INIT] flow end
2225 10:54:56.332657 ============ LP4 DIFF to SE enter ============
2226 10:54:56.339486 ============ LP4 DIFF to SE exit ============
2227 10:54:56.339590 [ANA_INIT] <<<<<<<<<<<<<
2228 10:54:56.342964 [Flow] Enable top DCM control >>>>>
2229 10:54:56.346037 [Flow] Enable top DCM control <<<<<
2230 10:54:56.349175 Enable DLL master slave shuffle
2231 10:54:56.356255 ==============================================================
2232 10:54:56.356362 Gating Mode config
2233 10:54:56.362377 ==============================================================
2234 10:54:56.365437 Config description:
2235 10:54:56.375798 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 10:54:56.379289 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 10:54:56.385625 SELPH_MODE 0: By rank 1: By Phase
2238 10:54:56.392285 ==============================================================
2239 10:54:56.392417 GAT_TRACK_EN = 1
2240 10:54:56.396184 RX_GATING_MODE = 2
2241 10:54:56.399279 RX_GATING_TRACK_MODE = 2
2242 10:54:56.402480 SELPH_MODE = 1
2243 10:54:56.405786 PICG_EARLY_EN = 1
2244 10:54:56.409034 VALID_LAT_VALUE = 1
2245 10:54:56.415850 ==============================================================
2246 10:54:56.419171 Enter into Gating configuration >>>>
2247 10:54:56.422462 Exit from Gating configuration <<<<
2248 10:54:56.425725 Enter into DVFS_PRE_config >>>>>
2249 10:54:56.435747 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 10:54:56.439184 Exit from DVFS_PRE_config <<<<<
2251 10:54:56.442257 Enter into PICG configuration >>>>
2252 10:54:56.445452 Exit from PICG configuration <<<<
2253 10:54:56.449696 [RX_INPUT] configuration >>>>>
2254 10:54:56.449788 [RX_INPUT] configuration <<<<<
2255 10:54:56.455641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 10:54:56.462349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 10:54:56.465529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 10:54:56.472633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 10:54:56.478813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 10:54:56.485870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 10:54:56.488842 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 10:54:56.492580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 10:54:56.499314 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 10:54:56.502027 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 10:54:56.505805 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 10:54:56.512088 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 10:54:56.512199 ===================================
2268 10:54:56.515748 LPDDR4 DRAM CONFIGURATION
2269 10:54:56.519153 ===================================
2270 10:54:56.522573 EX_ROW_EN[0] = 0x0
2271 10:54:56.522664 EX_ROW_EN[1] = 0x0
2272 10:54:56.525526 LP4Y_EN = 0x0
2273 10:54:56.525610 WORK_FSP = 0x0
2274 10:54:56.529104 WL = 0x4
2275 10:54:56.529190 RL = 0x4
2276 10:54:56.532312 BL = 0x2
2277 10:54:56.532398 RPST = 0x0
2278 10:54:56.535991 RD_PRE = 0x0
2279 10:54:56.536079 WR_PRE = 0x1
2280 10:54:56.538944 WR_PST = 0x0
2281 10:54:56.542576 DBI_WR = 0x0
2282 10:54:56.542667 DBI_RD = 0x0
2283 10:54:56.545274 OTF = 0x1
2284 10:54:56.548642 ===================================
2285 10:54:56.552508 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 10:54:56.555275 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 10:54:56.558664 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 10:54:56.561869 ===================================
2289 10:54:56.565614 LPDDR4 DRAM CONFIGURATION
2290 10:54:56.568877 ===================================
2291 10:54:56.571999 EX_ROW_EN[0] = 0x10
2292 10:54:56.572086 EX_ROW_EN[1] = 0x0
2293 10:54:56.575185 LP4Y_EN = 0x0
2294 10:54:56.575270 WORK_FSP = 0x0
2295 10:54:56.578718 WL = 0x4
2296 10:54:56.578808 RL = 0x4
2297 10:54:56.582218 BL = 0x2
2298 10:54:56.582302 RPST = 0x0
2299 10:54:56.585685 RD_PRE = 0x0
2300 10:54:56.585769 WR_PRE = 0x1
2301 10:54:56.589142 WR_PST = 0x0
2302 10:54:56.589226 DBI_WR = 0x0
2303 10:54:56.592305 DBI_RD = 0x0
2304 10:54:56.592388 OTF = 0x1
2305 10:54:56.595530 ===================================
2306 10:54:56.601918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 10:54:56.602015 ==
2308 10:54:56.605423 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 10:54:56.611792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 10:54:56.611894 ==
2311 10:54:56.611963 [Duty_Offset_Calibration]
2312 10:54:56.615297 B0:2 B1:-1 CA:1
2313 10:54:56.615432
2314 10:54:56.618778 [DutyScan_Calibration_Flow] k_type=0
2315 10:54:56.627167
2316 10:54:56.627308 ==CLK 0==
2317 10:54:56.629981 Final CLK duty delay cell = -4
2318 10:54:56.633780 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2319 10:54:56.637022 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2320 10:54:56.640322 [-4] AVG Duty = 4953%(X100)
2321 10:54:56.640410
2322 10:54:56.643659 CH0 CLK Duty spec in!! Max-Min= 156%
2323 10:54:56.646847 [DutyScan_Calibration_Flow] ====Done====
2324 10:54:56.646934
2325 10:54:56.650386 [DutyScan_Calibration_Flow] k_type=1
2326 10:54:56.665212
2327 10:54:56.665342 ==DQS 0 ==
2328 10:54:56.668175 Final DQS duty delay cell = -4
2329 10:54:56.672029 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2330 10:54:56.675084 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2331 10:54:56.678253 [-4] AVG Duty = 4938%(X100)
2332 10:54:56.678344
2333 10:54:56.678409 ==DQS 1 ==
2334 10:54:56.681855 Final DQS duty delay cell = -4
2335 10:54:56.685367 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2336 10:54:56.688346 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2337 10:54:56.691447 [-4] AVG Duty = 5062%(X100)
2338 10:54:56.691533
2339 10:54:56.694925 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2340 10:54:56.695010
2341 10:54:56.698669 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2342 10:54:56.702092 [DutyScan_Calibration_Flow] ====Done====
2343 10:54:56.702179
2344 10:54:56.705433 [DutyScan_Calibration_Flow] k_type=3
2345 10:54:56.722456
2346 10:54:56.722609 ==DQM 0 ==
2347 10:54:56.725464 Final DQM duty delay cell = 0
2348 10:54:56.729058 [0] MAX Duty = 5000%(X100), DQS PI = 54
2349 10:54:56.732026 [0] MIN Duty = 4876%(X100), DQS PI = 24
2350 10:54:56.735618 [0] AVG Duty = 4938%(X100)
2351 10:54:56.735707
2352 10:54:56.735772 ==DQM 1 ==
2353 10:54:56.738965 Final DQM duty delay cell = 0
2354 10:54:56.742250 [0] MAX Duty = 5156%(X100), DQS PI = 62
2355 10:54:56.745463 [0] MIN Duty = 5000%(X100), DQS PI = 8
2356 10:54:56.745559 [0] AVG Duty = 5078%(X100)
2357 10:54:56.749226
2358 10:54:56.752697 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2359 10:54:56.752785
2360 10:54:56.756066 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2361 10:54:56.759515 [DutyScan_Calibration_Flow] ====Done====
2362 10:54:56.759604
2363 10:54:56.762494 [DutyScan_Calibration_Flow] k_type=2
2364 10:54:56.778047
2365 10:54:56.778171 ==DQ 0 ==
2366 10:54:56.781261 Final DQ duty delay cell = -4
2367 10:54:56.784797 [-4] MAX Duty = 5062%(X100), DQS PI = 56
2368 10:54:56.787949 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2369 10:54:56.791153 [-4] AVG Duty = 4969%(X100)
2370 10:54:56.791239
2371 10:54:56.791304 ==DQ 1 ==
2372 10:54:56.795104 Final DQ duty delay cell = 0
2373 10:54:56.797655 [0] MAX Duty = 5031%(X100), DQS PI = 18
2374 10:54:56.801466 [0] MIN Duty = 4907%(X100), DQS PI = 62
2375 10:54:56.804605 [0] AVG Duty = 4969%(X100)
2376 10:54:56.804690
2377 10:54:56.807796 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2378 10:54:56.807881
2379 10:54:56.811280 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2380 10:54:56.814348 [DutyScan_Calibration_Flow] ====Done====
2381 10:54:56.814430 ==
2382 10:54:56.818980 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 10:54:56.821198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 10:54:56.821282 ==
2385 10:54:56.824732 [Duty_Offset_Calibration]
2386 10:54:56.824884 B0:1 B1:1 CA:2
2387 10:54:56.824948
2388 10:54:56.827742 [DutyScan_Calibration_Flow] k_type=0
2389 10:54:56.838328
2390 10:54:56.838458 ==CLK 0==
2391 10:54:56.841587 Final CLK duty delay cell = 0
2392 10:54:56.845007 [0] MAX Duty = 5125%(X100), DQS PI = 24
2393 10:54:56.848155 [0] MIN Duty = 4938%(X100), DQS PI = 40
2394 10:54:56.852129 [0] AVG Duty = 5031%(X100)
2395 10:54:56.852221
2396 10:54:56.854864 CH1 CLK Duty spec in!! Max-Min= 187%
2397 10:54:56.858371 [DutyScan_Calibration_Flow] ====Done====
2398 10:54:56.858458
2399 10:54:56.861310 [DutyScan_Calibration_Flow] k_type=1
2400 10:54:56.877357
2401 10:54:56.877510 ==DQS 0 ==
2402 10:54:56.881267 Final DQS duty delay cell = 0
2403 10:54:56.884095 [0] MAX Duty = 5031%(X100), DQS PI = 18
2404 10:54:56.887780 [0] MIN Duty = 4813%(X100), DQS PI = 50
2405 10:54:56.890880 [0] AVG Duty = 4922%(X100)
2406 10:54:56.890970
2407 10:54:56.891068 ==DQS 1 ==
2408 10:54:56.894009 Final DQS duty delay cell = 0
2409 10:54:56.897529 [0] MAX Duty = 5062%(X100), DQS PI = 36
2410 10:54:56.900652 [0] MIN Duty = 4907%(X100), DQS PI = 8
2411 10:54:56.904567 [0] AVG Duty = 4984%(X100)
2412 10:54:56.904658
2413 10:54:56.907913 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2414 10:54:56.907999
2415 10:54:56.911054 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2416 10:54:56.914016 [DutyScan_Calibration_Flow] ====Done====
2417 10:54:56.914102
2418 10:54:56.917763 [DutyScan_Calibration_Flow] k_type=3
2419 10:54:56.934282
2420 10:54:56.934436 ==DQM 0 ==
2421 10:54:56.937334 Final DQM duty delay cell = 0
2422 10:54:56.941016 [0] MAX Duty = 5093%(X100), DQS PI = 18
2423 10:54:56.944444 [0] MIN Duty = 4907%(X100), DQS PI = 48
2424 10:54:56.944538 [0] AVG Duty = 5000%(X100)
2425 10:54:56.947423
2426 10:54:56.947510 ==DQM 1 ==
2427 10:54:56.950670 Final DQM duty delay cell = 0
2428 10:54:56.954177 [0] MAX Duty = 5156%(X100), DQS PI = 62
2429 10:54:56.957621 [0] MIN Duty = 4938%(X100), DQS PI = 24
2430 10:54:56.957712 [0] AVG Duty = 5047%(X100)
2431 10:54:56.961458
2432 10:54:56.964726 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2433 10:54:56.964815
2434 10:54:56.967951 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2435 10:54:56.970550 [DutyScan_Calibration_Flow] ====Done====
2436 10:54:56.970635
2437 10:54:56.974176 [DutyScan_Calibration_Flow] k_type=2
2438 10:54:56.991011
2439 10:54:56.991162 ==DQ 0 ==
2440 10:54:56.994077 Final DQ duty delay cell = 0
2441 10:54:56.997165 [0] MAX Duty = 5124%(X100), DQS PI = 18
2442 10:54:57.000605 [0] MIN Duty = 4969%(X100), DQS PI = 14
2443 10:54:57.000697 [0] AVG Duty = 5046%(X100)
2444 10:54:57.000763
2445 10:54:57.003834 ==DQ 1 ==
2446 10:54:57.007454 Final DQ duty delay cell = 0
2447 10:54:57.011015 [0] MAX Duty = 5124%(X100), DQS PI = 58
2448 10:54:57.013610 [0] MIN Duty = 5031%(X100), DQS PI = 2
2449 10:54:57.013696 [0] AVG Duty = 5077%(X100)
2450 10:54:57.013763
2451 10:54:57.020600 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2452 10:54:57.020696
2453 10:54:57.024220 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2454 10:54:57.027045 [DutyScan_Calibration_Flow] ====Done====
2455 10:54:57.030170 nWR fixed to 30
2456 10:54:57.030259 [ModeRegInit_LP4] CH0 RK0
2457 10:54:57.033755 [ModeRegInit_LP4] CH0 RK1
2458 10:54:57.037686 [ModeRegInit_LP4] CH1 RK0
2459 10:54:57.037781 [ModeRegInit_LP4] CH1 RK1
2460 10:54:57.040509 match AC timing 7
2461 10:54:57.043873 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 10:54:57.047388 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 10:54:57.053576 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 10:54:57.057106 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 10:54:57.063896 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 10:54:57.064016 ==
2467 10:54:57.067400 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 10:54:57.070753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 10:54:57.070842 ==
2470 10:54:57.077073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 10:54:57.080645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 10:54:57.090677 [CA 0] Center 40 (10~71) winsize 62
2473 10:54:57.093947 [CA 1] Center 39 (9~70) winsize 62
2474 10:54:57.097693 [CA 2] Center 36 (6~67) winsize 62
2475 10:54:57.100460 [CA 3] Center 36 (5~67) winsize 63
2476 10:54:57.104046 [CA 4] Center 35 (5~65) winsize 61
2477 10:54:57.107563 [CA 5] Center 34 (4~64) winsize 61
2478 10:54:57.107650
2479 10:54:57.110619 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2480 10:54:57.110710
2481 10:54:57.113979 [CATrainingPosCal] consider 1 rank data
2482 10:54:57.117372 u2DelayCellTimex100 = 270/100 ps
2483 10:54:57.120615 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2484 10:54:57.127556 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2485 10:54:57.130255 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2486 10:54:57.133715 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2487 10:54:57.137051 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2488 10:54:57.140776 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2489 10:54:57.140866
2490 10:54:57.143852 CA PerBit enable=1, Macro0, CA PI delay=34
2491 10:54:57.143938
2492 10:54:57.146902 [CBTSetCACLKResult] CA Dly = 34
2493 10:54:57.146987 CS Dly: 7 (0~38)
2494 10:54:57.150668 ==
2495 10:54:57.153919 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 10:54:57.157419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 10:54:57.157509 ==
2498 10:54:57.160497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 10:54:57.167102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 10:54:57.176489 [CA 0] Center 39 (9~70) winsize 62
2501 10:54:57.180680 [CA 1] Center 39 (9~70) winsize 62
2502 10:54:57.183165 [CA 2] Center 36 (6~67) winsize 62
2503 10:54:57.186379 [CA 3] Center 36 (5~67) winsize 63
2504 10:54:57.190044 [CA 4] Center 34 (4~65) winsize 62
2505 10:54:57.193250 [CA 5] Center 34 (4~64) winsize 61
2506 10:54:57.193338
2507 10:54:57.196516 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 10:54:57.196602
2509 10:54:57.200170 [CATrainingPosCal] consider 2 rank data
2510 10:54:57.203888 u2DelayCellTimex100 = 270/100 ps
2511 10:54:57.206618 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2512 10:54:57.210122 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2513 10:54:57.216866 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2514 10:54:57.220170 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2515 10:54:57.223398 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2516 10:54:57.227408 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2517 10:54:57.227504
2518 10:54:57.230571 CA PerBit enable=1, Macro0, CA PI delay=34
2519 10:54:57.230656
2520 10:54:57.233274 [CBTSetCACLKResult] CA Dly = 34
2521 10:54:57.233360 CS Dly: 8 (0~41)
2522 10:54:57.233426
2523 10:54:57.237343 ----->DramcWriteLeveling(PI) begin...
2524 10:54:57.237431 ==
2525 10:54:57.240050 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 10:54:57.246589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 10:54:57.246695 ==
2528 10:54:57.250080 Write leveling (Byte 0): 31 => 31
2529 10:54:57.253076 Write leveling (Byte 1): 29 => 29
2530 10:54:57.256448 DramcWriteLeveling(PI) end<-----
2531 10:54:57.256536
2532 10:54:57.256602 ==
2533 10:54:57.260163 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 10:54:57.263321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 10:54:57.263453 ==
2536 10:54:57.266709 [Gating] SW mode calibration
2537 10:54:57.273500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 10:54:57.276717 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 10:54:57.283007 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 10:54:57.287174 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2541 10:54:57.289894 0 15 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2542 10:54:57.296700 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 10:54:57.299624 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 10:54:57.303060 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 10:54:57.309833 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 10:54:57.313066 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 10:54:57.316420 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
2548 10:54:57.322977 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2549 10:54:57.326771 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2550 10:54:57.330248 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 10:54:57.336858 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 10:54:57.339952 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 10:54:57.343325 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 10:54:57.350120 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 10:54:57.353347 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2556 10:54:57.356676 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2557 10:54:57.362834 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 10:54:57.366303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 10:54:57.369907 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 10:54:57.373249 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 10:54:57.380068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 10:54:57.383026 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 10:54:57.386421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2564 10:54:57.393137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2565 10:54:57.396067 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:54:57.399690 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:54:57.407008 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:54:57.409697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 10:54:57.413054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 10:54:57.419732 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 10:54:57.423211 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 10:54:57.426341 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 10:54:57.433059 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 10:54:57.436423 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 10:54:57.439627 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 10:54:57.446191 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 10:54:57.449486 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 10:54:57.453032 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 10:54:57.460107 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 10:54:57.462916 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 10:54:57.466244 Total UI for P1: 0, mck2ui 16
2582 10:54:57.470393 best dqsien dly found for B0: ( 1, 4, 0)
2583 10:54:57.473088 Total UI for P1: 0, mck2ui 16
2584 10:54:57.476739 best dqsien dly found for B1: ( 1, 4, 2)
2585 10:54:57.479797 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2586 10:54:57.483087 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 10:54:57.483176
2588 10:54:57.486165 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 10:54:57.490068 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 10:54:57.493070 [Gating] SW calibration Done
2591 10:54:57.493157 ==
2592 10:54:57.496328 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 10:54:57.500157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 10:54:57.500248 ==
2595 10:54:57.502916 RX Vref Scan: 0
2596 10:54:57.502999
2597 10:54:57.503064 RX Vref 0 -> 0, step: 1
2598 10:54:57.503126
2599 10:54:57.506410 RX Delay -40 -> 252, step: 8
2600 10:54:57.512843 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 10:54:57.516541 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 10:54:57.519720 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2603 10:54:57.523007 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2604 10:54:57.526240 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 10:54:57.529471 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2606 10:54:57.536688 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 10:54:57.540010 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 10:54:57.542652 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 10:54:57.546573 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 10:54:57.549402 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 10:54:57.556247 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 10:54:57.559242 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2613 10:54:57.562885 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2614 10:54:57.566001 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 10:54:57.569584 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2616 10:54:57.573337 ==
2617 10:54:57.575899 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 10:54:57.579409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 10:54:57.579499 ==
2620 10:54:57.579566 DQS Delay:
2621 10:54:57.583025 DQS0 = 0, DQS1 = 0
2622 10:54:57.583111 DQM Delay:
2623 10:54:57.585759 DQM0 = 115, DQM1 = 106
2624 10:54:57.585843 DQ Delay:
2625 10:54:57.589410 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2626 10:54:57.592695 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2627 10:54:57.596106 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 10:54:57.599178 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2629 10:54:57.599269
2630 10:54:57.599334
2631 10:54:57.599439 ==
2632 10:54:57.602819 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 10:54:57.609404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 10:54:57.609508 ==
2635 10:54:57.609577
2636 10:54:57.609639
2637 10:54:57.609698 TX Vref Scan disable
2638 10:54:57.612883 == TX Byte 0 ==
2639 10:54:57.616018 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 10:54:57.619502 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 10:54:57.622963 == TX Byte 1 ==
2642 10:54:57.625990 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2643 10:54:57.629488 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2644 10:54:57.632641 ==
2645 10:54:57.636076 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 10:54:57.639313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 10:54:57.639452 ==
2648 10:54:57.651031 TX Vref=22, minBit 7, minWin=24, winSum=417
2649 10:54:57.653939 TX Vref=24, minBit 0, minWin=26, winSum=423
2650 10:54:57.657187 TX Vref=26, minBit 1, minWin=25, winSum=423
2651 10:54:57.660622 TX Vref=28, minBit 1, minWin=25, winSum=428
2652 10:54:57.664594 TX Vref=30, minBit 0, minWin=26, winSum=432
2653 10:54:57.667964 TX Vref=32, minBit 0, minWin=26, winSum=429
2654 10:54:57.674561 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2655 10:54:57.674674
2656 10:54:57.677274 Final TX Range 1 Vref 30
2657 10:54:57.677362
2658 10:54:57.677432 ==
2659 10:54:57.680813 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 10:54:57.683937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 10:54:57.684026 ==
2662 10:54:57.684094
2663 10:54:57.684154
2664 10:54:57.687709 TX Vref Scan disable
2665 10:54:57.690631 == TX Byte 0 ==
2666 10:54:57.694422 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 10:54:57.697644 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 10:54:57.700893 == TX Byte 1 ==
2669 10:54:57.704279 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2670 10:54:57.707500 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2671 10:54:57.707588
2672 10:54:57.710774 [DATLAT]
2673 10:54:57.710859 Freq=1200, CH0 RK0
2674 10:54:57.710926
2675 10:54:57.713993 DATLAT Default: 0xd
2676 10:54:57.714080 0, 0xFFFF, sum = 0
2677 10:54:57.717803 1, 0xFFFF, sum = 0
2678 10:54:57.717890 2, 0xFFFF, sum = 0
2679 10:54:57.721198 3, 0xFFFF, sum = 0
2680 10:54:57.721285 4, 0xFFFF, sum = 0
2681 10:54:57.724399 5, 0xFFFF, sum = 0
2682 10:54:57.724487 6, 0xFFFF, sum = 0
2683 10:54:57.727469 7, 0xFFFF, sum = 0
2684 10:54:57.727555 8, 0xFFFF, sum = 0
2685 10:54:57.730861 9, 0xFFFF, sum = 0
2686 10:54:57.733993 10, 0xFFFF, sum = 0
2687 10:54:57.734082 11, 0xFFFF, sum = 0
2688 10:54:57.737301 12, 0x0, sum = 1
2689 10:54:57.737390 13, 0x0, sum = 2
2690 10:54:57.737458 14, 0x0, sum = 3
2691 10:54:57.740705 15, 0x0, sum = 4
2692 10:54:57.740793 best_step = 13
2693 10:54:57.740859
2694 10:54:57.744453 ==
2695 10:54:57.744541 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 10:54:57.750427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 10:54:57.750520 ==
2698 10:54:57.750588 RX Vref Scan: 1
2699 10:54:57.750649
2700 10:54:57.753804 Set Vref Range= 32 -> 127
2701 10:54:57.753890
2702 10:54:57.757214 RX Vref 32 -> 127, step: 1
2703 10:54:57.757299
2704 10:54:57.760474 RX Delay -21 -> 252, step: 4
2705 10:54:57.760562
2706 10:54:57.763789 Set Vref, RX VrefLevel [Byte0]: 32
2707 10:54:57.767139 [Byte1]: 32
2708 10:54:57.767225
2709 10:54:57.770669 Set Vref, RX VrefLevel [Byte0]: 33
2710 10:54:57.773701 [Byte1]: 33
2711 10:54:57.773787
2712 10:54:57.777291 Set Vref, RX VrefLevel [Byte0]: 34
2713 10:54:57.780337 [Byte1]: 34
2714 10:54:57.784551
2715 10:54:57.784640 Set Vref, RX VrefLevel [Byte0]: 35
2716 10:54:57.788378 [Byte1]: 35
2717 10:54:57.792782
2718 10:54:57.792873 Set Vref, RX VrefLevel [Byte0]: 36
2719 10:54:57.795746 [Byte1]: 36
2720 10:54:57.800734
2721 10:54:57.800831 Set Vref, RX VrefLevel [Byte0]: 37
2722 10:54:57.803875 [Byte1]: 37
2723 10:54:57.808340
2724 10:54:57.811730 Set Vref, RX VrefLevel [Byte0]: 38
2725 10:54:57.811823 [Byte1]: 38
2726 10:54:57.816196
2727 10:54:57.816288 Set Vref, RX VrefLevel [Byte0]: 39
2728 10:54:57.819652 [Byte1]: 39
2729 10:54:57.824926
2730 10:54:57.825026 Set Vref, RX VrefLevel [Byte0]: 40
2731 10:54:57.827610 [Byte1]: 40
2732 10:54:57.832582
2733 10:54:57.832679 Set Vref, RX VrefLevel [Byte0]: 41
2734 10:54:57.835717 [Byte1]: 41
2735 10:54:57.840025
2736 10:54:57.840117 Set Vref, RX VrefLevel [Byte0]: 42
2737 10:54:57.844317 [Byte1]: 42
2738 10:54:57.847883
2739 10:54:57.847974 Set Vref, RX VrefLevel [Byte0]: 43
2740 10:54:57.851316 [Byte1]: 43
2741 10:54:57.856171
2742 10:54:57.856262 Set Vref, RX VrefLevel [Byte0]: 44
2743 10:54:57.859764 [Byte1]: 44
2744 10:54:57.864035
2745 10:54:57.864126 Set Vref, RX VrefLevel [Byte0]: 45
2746 10:54:57.867538 [Byte1]: 45
2747 10:54:57.871887
2748 10:54:57.871977 Set Vref, RX VrefLevel [Byte0]: 46
2749 10:54:57.875151 [Byte1]: 46
2750 10:54:57.879951
2751 10:54:57.880044 Set Vref, RX VrefLevel [Byte0]: 47
2752 10:54:57.883490 [Byte1]: 47
2753 10:54:57.887772
2754 10:54:57.887862 Set Vref, RX VrefLevel [Byte0]: 48
2755 10:54:57.891325 [Byte1]: 48
2756 10:54:57.895820
2757 10:54:57.895913 Set Vref, RX VrefLevel [Byte0]: 49
2758 10:54:57.899291 [Byte1]: 49
2759 10:54:57.904087
2760 10:54:57.904179 Set Vref, RX VrefLevel [Byte0]: 50
2761 10:54:57.906844 [Byte1]: 50
2762 10:54:57.911669
2763 10:54:57.911762 Set Vref, RX VrefLevel [Byte0]: 51
2764 10:54:57.915105 [Byte1]: 51
2765 10:54:57.919262
2766 10:54:57.919366 Set Vref, RX VrefLevel [Byte0]: 52
2767 10:54:57.922826 [Byte1]: 52
2768 10:54:57.927543
2769 10:54:57.927636 Set Vref, RX VrefLevel [Byte0]: 53
2770 10:54:57.930606 [Byte1]: 53
2771 10:54:57.935455
2772 10:54:57.935551 Set Vref, RX VrefLevel [Byte0]: 54
2773 10:54:57.938634 [Byte1]: 54
2774 10:54:57.943247
2775 10:54:57.943338 Set Vref, RX VrefLevel [Byte0]: 55
2776 10:54:57.946659 [Byte1]: 55
2777 10:54:57.951001
2778 10:54:57.951094 Set Vref, RX VrefLevel [Byte0]: 56
2779 10:54:57.954269 [Byte1]: 56
2780 10:54:57.959202
2781 10:54:57.959293 Set Vref, RX VrefLevel [Byte0]: 57
2782 10:54:57.962785 [Byte1]: 57
2783 10:54:57.967409
2784 10:54:57.967501 Set Vref, RX VrefLevel [Byte0]: 58
2785 10:54:57.970624 [Byte1]: 58
2786 10:54:57.974999
2787 10:54:57.975087 Set Vref, RX VrefLevel [Byte0]: 59
2788 10:54:57.978184 [Byte1]: 59
2789 10:54:57.983032
2790 10:54:57.983123 Set Vref, RX VrefLevel [Byte0]: 60
2791 10:54:57.986179 [Byte1]: 60
2792 10:54:57.990836
2793 10:54:57.990924 Set Vref, RX VrefLevel [Byte0]: 61
2794 10:54:57.994230 [Byte1]: 61
2795 10:54:57.998564
2796 10:54:57.998653 Set Vref, RX VrefLevel [Byte0]: 62
2797 10:54:58.002093 [Byte1]: 62
2798 10:54:58.006382
2799 10:54:58.006470 Set Vref, RX VrefLevel [Byte0]: 63
2800 10:54:58.009970 [Byte1]: 63
2801 10:54:58.014484
2802 10:54:58.014576 Set Vref, RX VrefLevel [Byte0]: 64
2803 10:54:58.018541 [Byte1]: 64
2804 10:54:58.022216
2805 10:54:58.022309 Set Vref, RX VrefLevel [Byte0]: 65
2806 10:54:58.025998 [Byte1]: 65
2807 10:54:58.030479
2808 10:54:58.030575 Set Vref, RX VrefLevel [Byte0]: 66
2809 10:54:58.033655 [Byte1]: 66
2810 10:54:58.038243
2811 10:54:58.038342 Set Vref, RX VrefLevel [Byte0]: 67
2812 10:54:58.042173 [Byte1]: 67
2813 10:54:58.046153
2814 10:54:58.046245 Set Vref, RX VrefLevel [Byte0]: 68
2815 10:54:58.049588 [Byte1]: 68
2816 10:54:58.054281
2817 10:54:58.054370 Final RX Vref Byte 0 = 54 to rank0
2818 10:54:58.057643 Final RX Vref Byte 1 = 51 to rank0
2819 10:54:58.060665 Final RX Vref Byte 0 = 54 to rank1
2820 10:54:58.064190 Final RX Vref Byte 1 = 51 to rank1==
2821 10:54:58.067656 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 10:54:58.070944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 10:54:58.074145 ==
2824 10:54:58.074230 DQS Delay:
2825 10:54:58.074296 DQS0 = 0, DQS1 = 0
2826 10:54:58.078313 DQM Delay:
2827 10:54:58.078397 DQM0 = 115, DQM1 = 104
2828 10:54:58.081340 DQ Delay:
2829 10:54:58.084790 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =112
2830 10:54:58.087666 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2831 10:54:58.090843 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2832 10:54:58.094500 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2833 10:54:58.094587
2834 10:54:58.094656
2835 10:54:58.101276 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbeb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
2836 10:54:58.104247 CH0 RK0: MR19=303, MR18=FBEB
2837 10:54:58.111235 CH0_RK0: MR19=0x303, MR18=0xFBEB, DQSOSC=412, MR23=63, INC=38, DEC=25
2838 10:54:58.111337
2839 10:54:58.114155 ----->DramcWriteLeveling(PI) begin...
2840 10:54:58.114241 ==
2841 10:54:58.117722 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 10:54:58.120994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 10:54:58.121081 ==
2844 10:54:58.124144 Write leveling (Byte 0): 32 => 32
2845 10:54:58.127649 Write leveling (Byte 1): 29 => 29
2846 10:54:58.131135 DramcWriteLeveling(PI) end<-----
2847 10:54:58.131225
2848 10:54:58.131291 ==
2849 10:54:58.134281 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 10:54:58.141162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 10:54:58.141275 ==
2852 10:54:58.141343 [Gating] SW mode calibration
2853 10:54:58.151001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 10:54:58.154152 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 10:54:58.157725 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2856 10:54:58.164575 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2857 10:54:58.168182 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 10:54:58.170777 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 10:54:58.177685 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 10:54:58.181033 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 10:54:58.183973 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 10:54:58.191075 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2863 10:54:58.194572 1 0 0 | B1->B0 | 2d2d 2525 | 1 1 | (1 0) (1 0)
2864 10:54:58.197756 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2865 10:54:58.204264 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 10:54:58.207317 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 10:54:58.211094 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 10:54:58.218296 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 10:54:58.221007 1 0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2870 10:54:58.223936 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2871 10:54:58.230561 1 1 0 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (1 1)
2872 10:54:58.233979 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 10:54:58.237236 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 10:54:58.243980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 10:54:58.247269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 10:54:58.251149 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 10:54:58.254026 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 10:54:58.260405 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 10:54:58.263879 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 10:54:58.267498 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 10:54:58.274480 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 10:54:58.277365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 10:54:58.280934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 10:54:58.287192 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 10:54:58.290959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 10:54:58.294463 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 10:54:58.300807 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 10:54:58.304000 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 10:54:58.307662 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 10:54:58.314676 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 10:54:58.318173 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 10:54:58.320810 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 10:54:58.324151 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 10:54:58.331142 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2895 10:54:58.334587 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 10:54:58.337944 Total UI for P1: 0, mck2ui 16
2897 10:54:58.340893 best dqsien dly found for B0: ( 1, 3, 28)
2898 10:54:58.344600 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 10:54:58.348239 Total UI for P1: 0, mck2ui 16
2900 10:54:58.351006 best dqsien dly found for B1: ( 1, 3, 30)
2901 10:54:58.354335 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2902 10:54:58.357993 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2903 10:54:58.358085
2904 10:54:58.365175 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2905 10:54:58.368202 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2906 10:54:58.368299 [Gating] SW calibration Done
2907 10:54:58.371720 ==
2908 10:54:58.371811 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 10:54:58.378295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 10:54:58.378397 ==
2911 10:54:58.378468 RX Vref Scan: 0
2912 10:54:58.378529
2913 10:54:58.381278 RX Vref 0 -> 0, step: 1
2914 10:54:58.381364
2915 10:54:58.384527 RX Delay -40 -> 252, step: 8
2916 10:54:58.387876 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2917 10:54:58.391513 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2918 10:54:58.394884 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2919 10:54:58.401902 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2920 10:54:58.405076 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 10:54:58.408342 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2922 10:54:58.411527 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2923 10:54:58.414740 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 10:54:58.418150 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2925 10:54:58.424603 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 10:54:58.428269 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2927 10:54:58.431800 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2928 10:54:58.434658 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 10:54:58.438721 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 10:54:58.444967 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 10:54:58.448149 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2932 10:54:58.448248 ==
2933 10:54:58.451267 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 10:54:58.454868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 10:54:58.454955 ==
2936 10:54:58.458105 DQS Delay:
2937 10:54:58.458190 DQS0 = 0, DQS1 = 0
2938 10:54:58.458256 DQM Delay:
2939 10:54:58.461570 DQM0 = 115, DQM1 = 106
2940 10:54:58.461704 DQ Delay:
2941 10:54:58.464546 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2942 10:54:58.468144 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2943 10:54:58.471150 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2944 10:54:58.478483 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2945 10:54:58.478602
2946 10:54:58.478673
2947 10:54:58.478734 ==
2948 10:54:58.482206 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 10:54:58.484668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 10:54:58.484756 ==
2951 10:54:58.484823
2952 10:54:58.484884
2953 10:54:58.488226 TX Vref Scan disable
2954 10:54:58.488311 == TX Byte 0 ==
2955 10:54:58.494835 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2956 10:54:58.498189 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2957 10:54:58.498280 == TX Byte 1 ==
2958 10:54:58.504865 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2959 10:54:58.508195 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2960 10:54:58.508292 ==
2961 10:54:58.511084 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 10:54:58.514895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 10:54:58.514994 ==
2964 10:54:58.527821 TX Vref=22, minBit 5, minWin=25, winSum=426
2965 10:54:58.531052 TX Vref=24, minBit 1, minWin=26, winSum=429
2966 10:54:58.534270 TX Vref=26, minBit 0, minWin=26, winSum=433
2967 10:54:58.537670 TX Vref=28, minBit 3, minWin=26, winSum=435
2968 10:54:58.540744 TX Vref=30, minBit 0, minWin=27, winSum=438
2969 10:54:58.547598 TX Vref=32, minBit 12, minWin=26, winSum=436
2970 10:54:58.551048 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
2971 10:54:58.551149
2972 10:54:58.554477 Final TX Range 1 Vref 30
2973 10:54:58.554565
2974 10:54:58.554631 ==
2975 10:54:58.557858 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 10:54:58.560905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 10:54:58.560995 ==
2978 10:54:58.564429
2979 10:54:58.564516
2980 10:54:58.564582 TX Vref Scan disable
2981 10:54:58.567188 == TX Byte 0 ==
2982 10:54:58.570636 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2983 10:54:58.577287 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2984 10:54:58.577395 == TX Byte 1 ==
2985 10:54:58.580829 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2986 10:54:58.587603 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2987 10:54:58.587710
2988 10:54:58.587778 [DATLAT]
2989 10:54:58.587840 Freq=1200, CH0 RK1
2990 10:54:58.587900
2991 10:54:58.590634 DATLAT Default: 0xd
2992 10:54:58.590718 0, 0xFFFF, sum = 0
2993 10:54:58.594549 1, 0xFFFF, sum = 0
2994 10:54:58.594638 2, 0xFFFF, sum = 0
2995 10:54:58.597234 3, 0xFFFF, sum = 0
2996 10:54:58.600760 4, 0xFFFF, sum = 0
2997 10:54:58.600850 5, 0xFFFF, sum = 0
2998 10:54:58.604327 6, 0xFFFF, sum = 0
2999 10:54:58.604415 7, 0xFFFF, sum = 0
3000 10:54:58.607253 8, 0xFFFF, sum = 0
3001 10:54:58.607339 9, 0xFFFF, sum = 0
3002 10:54:58.610566 10, 0xFFFF, sum = 0
3003 10:54:58.610652 11, 0xFFFF, sum = 0
3004 10:54:58.614227 12, 0x0, sum = 1
3005 10:54:58.614314 13, 0x0, sum = 2
3006 10:54:58.617212 14, 0x0, sum = 3
3007 10:54:58.617297 15, 0x0, sum = 4
3008 10:54:58.617364 best_step = 13
3009 10:54:58.621083
3010 10:54:58.621172 ==
3011 10:54:58.624030 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 10:54:58.627192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 10:54:58.627279 ==
3014 10:54:58.627352 RX Vref Scan: 0
3015 10:54:58.627451
3016 10:54:58.630629 RX Vref 0 -> 0, step: 1
3017 10:54:58.630713
3018 10:54:58.633704 RX Delay -21 -> 252, step: 4
3019 10:54:58.637780 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3020 10:54:58.643944 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3021 10:54:58.647155 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3022 10:54:58.650900 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3023 10:54:58.653919 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3024 10:54:58.657252 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3025 10:54:58.664030 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3026 10:54:58.667543 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3027 10:54:58.670917 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3028 10:54:58.674073 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3029 10:54:58.677865 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3030 10:54:58.680417 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3031 10:54:58.687143 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3032 10:54:58.691074 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3033 10:54:58.694003 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3034 10:54:58.697672 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3035 10:54:58.697762 ==
3036 10:54:58.700839 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 10:54:58.707212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 10:54:58.707312 ==
3039 10:54:58.707392 DQS Delay:
3040 10:54:58.710658 DQS0 = 0, DQS1 = 0
3041 10:54:58.710743 DQM Delay:
3042 10:54:58.710809 DQM0 = 114, DQM1 = 104
3043 10:54:58.713770 DQ Delay:
3044 10:54:58.717723 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3045 10:54:58.720650 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3046 10:54:58.723960 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3047 10:54:58.727085 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3048 10:54:58.727171
3049 10:54:58.727237
3050 10:54:58.733884 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3051 10:54:58.737589 CH0 RK1: MR19=403, MR18=1F2
3052 10:54:58.744106 CH0_RK1: MR19=0x403, MR18=0x1F2, DQSOSC=409, MR23=63, INC=39, DEC=26
3053 10:54:58.747082 [RxdqsGatingPostProcess] freq 1200
3054 10:54:58.754616 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 10:54:58.757432 best DQS0 dly(2T, 0.5T) = (0, 12)
3056 10:54:58.757529 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 10:54:58.760972 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3058 10:54:58.764119 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 10:54:58.767181 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 10:54:58.770589 best DQS1 dly(2T, 0.5T) = (0, 11)
3061 10:54:58.773799 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 10:54:58.777215 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3063 10:54:58.780683 Pre-setting of DQS Precalculation
3064 10:54:58.787461 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 10:54:58.787572 ==
3066 10:54:58.790405 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 10:54:58.793787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 10:54:58.793878 ==
3069 10:54:58.800605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 10:54:58.804271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 10:54:58.813764 [CA 0] Center 38 (9~68) winsize 60
3072 10:54:58.816669 [CA 1] Center 38 (8~68) winsize 61
3073 10:54:58.819813 [CA 2] Center 35 (5~65) winsize 61
3074 10:54:58.823297 [CA 3] Center 34 (3~65) winsize 63
3075 10:54:58.826581 [CA 4] Center 34 (4~65) winsize 62
3076 10:54:58.829896 [CA 5] Center 33 (3~64) winsize 62
3077 10:54:58.830018
3078 10:54:58.833773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3079 10:54:58.833858
3080 10:54:58.836655 [CATrainingPosCal] consider 1 rank data
3081 10:54:58.840121 u2DelayCellTimex100 = 270/100 ps
3082 10:54:58.843268 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3083 10:54:58.846961 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3084 10:54:58.853597 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 10:54:58.856717 CA3 delay=34 (3~65),Diff = 1 PI (4 cell)
3086 10:54:58.860253 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3087 10:54:58.863647 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 10:54:58.863740
3089 10:54:58.867095 CA PerBit enable=1, Macro0, CA PI delay=33
3090 10:54:58.867179
3091 10:54:58.870032 [CBTSetCACLKResult] CA Dly = 33
3092 10:54:58.870115 CS Dly: 6 (0~37)
3093 10:54:58.870180 ==
3094 10:54:58.873399 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 10:54:58.880466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 10:54:58.880573 ==
3097 10:54:58.883304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 10:54:58.889997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3099 10:54:58.898908 [CA 0] Center 38 (8~68) winsize 61
3100 10:54:58.902247 [CA 1] Center 38 (9~68) winsize 60
3101 10:54:58.905515 [CA 2] Center 35 (5~65) winsize 61
3102 10:54:58.908923 [CA 3] Center 34 (4~65) winsize 62
3103 10:54:58.912773 [CA 4] Center 34 (4~65) winsize 62
3104 10:54:58.915939 [CA 5] Center 33 (3~64) winsize 62
3105 10:54:58.916028
3106 10:54:58.919228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 10:54:58.919313
3108 10:54:58.922514 [CATrainingPosCal] consider 2 rank data
3109 10:54:58.925487 u2DelayCellTimex100 = 270/100 ps
3110 10:54:58.928841 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3111 10:54:58.932132 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3112 10:54:58.938704 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 10:54:58.942275 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 10:54:58.945811 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3115 10:54:58.948611 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 10:54:58.948699
3117 10:54:58.951985 CA PerBit enable=1, Macro0, CA PI delay=33
3118 10:54:58.952072
3119 10:54:58.955298 [CBTSetCACLKResult] CA Dly = 33
3120 10:54:58.955429 CS Dly: 7 (0~40)
3121 10:54:58.955497
3122 10:54:58.958694 ----->DramcWriteLeveling(PI) begin...
3123 10:54:58.962407 ==
3124 10:54:58.962496 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 10:54:58.969242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 10:54:58.969344 ==
3127 10:54:58.972153 Write leveling (Byte 0): 26 => 26
3128 10:54:58.975592 Write leveling (Byte 1): 30 => 30
3129 10:54:58.975679 DramcWriteLeveling(PI) end<-----
3130 10:54:58.979083
3131 10:54:58.979167 ==
3132 10:54:58.982013 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 10:54:58.985813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 10:54:58.985902 ==
3135 10:54:58.988839 [Gating] SW mode calibration
3136 10:54:58.995737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 10:54:58.998885 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 10:54:59.005335 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3139 10:54:59.008784 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 10:54:59.012218 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 10:54:59.019075 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 10:54:59.022634 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 10:54:59.025588 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 10:54:59.032397 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3145 10:54:59.035738 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3146 10:54:59.038942 1 0 0 | B1->B0 | 2424 2c2c | 1 1 | (1 0) (1 0)
3147 10:54:59.045598 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 10:54:59.048986 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 10:54:59.052287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 10:54:59.059038 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 10:54:59.062468 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 10:54:59.065773 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 10:54:59.072367 1 0 28 | B1->B0 | 2c2c 2626 | 0 0 | (1 1) (0 0)
3154 10:54:59.075542 1 1 0 | B1->B0 | 4242 3737 | 0 0 | (0 0) (0 0)
3155 10:54:59.078873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 10:54:59.082540 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 10:54:59.089280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 10:54:59.092216 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 10:54:59.095567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 10:54:59.102218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 10:54:59.105693 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 10:54:59.109506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 10:54:59.115905 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 10:54:59.119058 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 10:54:59.122545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 10:54:59.129095 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 10:54:59.132125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 10:54:59.135640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 10:54:59.142663 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 10:54:59.145975 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 10:54:59.149227 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 10:54:59.155645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 10:54:59.159104 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 10:54:59.162472 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 10:54:59.169363 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 10:54:59.172083 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3177 10:54:59.175564 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 10:54:59.179390 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3179 10:54:59.182374 Total UI for P1: 0, mck2ui 16
3180 10:54:59.185454 best dqsien dly found for B1: ( 1, 3, 30)
3181 10:54:59.192187 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 10:54:59.195343 Total UI for P1: 0, mck2ui 16
3183 10:54:59.198548 best dqsien dly found for B0: ( 1, 3, 28)
3184 10:54:59.202446 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3185 10:54:59.205510 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3186 10:54:59.205598
3187 10:54:59.208680 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 10:54:59.211906 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3189 10:54:59.215660 [Gating] SW calibration Done
3190 10:54:59.215750 ==
3191 10:54:59.218883 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 10:54:59.222567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 10:54:59.222658 ==
3194 10:54:59.225305 RX Vref Scan: 0
3195 10:54:59.225390
3196 10:54:59.225455 RX Vref 0 -> 0, step: 1
3197 10:54:59.229019
3198 10:54:59.229104 RX Delay -40 -> 252, step: 8
3199 10:54:59.235556 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3200 10:54:59.239277 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3201 10:54:59.242069 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3202 10:54:59.245356 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3203 10:54:59.248515 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3204 10:54:59.252539 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3205 10:54:59.258744 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3206 10:54:59.262212 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3207 10:54:59.265467 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 10:54:59.269023 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3209 10:54:59.272521 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3210 10:54:59.278618 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 10:54:59.282320 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3212 10:54:59.285693 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3213 10:54:59.289572 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3214 10:54:59.292662 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3215 10:54:59.295663 ==
3216 10:54:59.295752 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 10:54:59.301978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 10:54:59.302082 ==
3219 10:54:59.302151 DQS Delay:
3220 10:54:59.305387 DQS0 = 0, DQS1 = 0
3221 10:54:59.305474 DQM Delay:
3222 10:54:59.308669 DQM0 = 115, DQM1 = 109
3223 10:54:59.308755 DQ Delay:
3224 10:54:59.311993 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3225 10:54:59.315175 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3226 10:54:59.318726 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3227 10:54:59.322146 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3228 10:54:59.322239
3229 10:54:59.322305
3230 10:54:59.322365 ==
3231 10:54:59.325051 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 10:54:59.332153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 10:54:59.332264 ==
3234 10:54:59.332334
3235 10:54:59.332395
3236 10:54:59.332452 TX Vref Scan disable
3237 10:54:59.335507 == TX Byte 0 ==
3238 10:54:59.338827 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3239 10:54:59.345456 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3240 10:54:59.345565 == TX Byte 1 ==
3241 10:54:59.348915 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3242 10:54:59.355737 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3243 10:54:59.355845 ==
3244 10:54:59.358416 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 10:54:59.361894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 10:54:59.361984 ==
3247 10:54:59.373581 TX Vref=22, minBit 1, minWin=25, winSum=412
3248 10:54:59.376725 TX Vref=24, minBit 15, minWin=24, winSum=416
3249 10:54:59.380250 TX Vref=26, minBit 0, minWin=26, winSum=423
3250 10:54:59.383890 TX Vref=28, minBit 0, minWin=26, winSum=429
3251 10:54:59.387147 TX Vref=30, minBit 0, minWin=26, winSum=431
3252 10:54:59.390444 TX Vref=32, minBit 3, minWin=26, winSum=430
3253 10:54:59.396931 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
3254 10:54:59.397037
3255 10:54:59.400207 Final TX Range 1 Vref 30
3256 10:54:59.400299
3257 10:54:59.400365 ==
3258 10:54:59.403656 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 10:54:59.407168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 10:54:59.407260 ==
3261 10:54:59.407325
3262 10:54:59.407445
3263 10:54:59.410304 TX Vref Scan disable
3264 10:54:59.413527 == TX Byte 0 ==
3265 10:54:59.417130 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3266 10:54:59.420227 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3267 10:54:59.423778 == TX Byte 1 ==
3268 10:54:59.427195 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3269 10:54:59.430221 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3270 10:54:59.430314
3271 10:54:59.433916 [DATLAT]
3272 10:54:59.434005 Freq=1200, CH1 RK0
3273 10:54:59.434072
3274 10:54:59.436706 DATLAT Default: 0xd
3275 10:54:59.436829 0, 0xFFFF, sum = 0
3276 10:54:59.440059 1, 0xFFFF, sum = 0
3277 10:54:59.440150 2, 0xFFFF, sum = 0
3278 10:54:59.443808 3, 0xFFFF, sum = 0
3279 10:54:59.443902 4, 0xFFFF, sum = 0
3280 10:54:59.446897 5, 0xFFFF, sum = 0
3281 10:54:59.446989 6, 0xFFFF, sum = 0
3282 10:54:59.450205 7, 0xFFFF, sum = 0
3283 10:54:59.450296 8, 0xFFFF, sum = 0
3284 10:54:59.453769 9, 0xFFFF, sum = 0
3285 10:54:59.457047 10, 0xFFFF, sum = 0
3286 10:54:59.457141 11, 0xFFFF, sum = 0
3287 10:54:59.460115 12, 0x0, sum = 1
3288 10:54:59.460205 13, 0x0, sum = 2
3289 10:54:59.460293 14, 0x0, sum = 3
3290 10:54:59.463881 15, 0x0, sum = 4
3291 10:54:59.463974 best_step = 13
3292 10:54:59.464062
3293 10:54:59.466750 ==
3294 10:54:59.466857 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 10:54:59.473449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 10:54:59.473561 ==
3297 10:54:59.473630 RX Vref Scan: 1
3298 10:54:59.473690
3299 10:54:59.476772 Set Vref Range= 32 -> 127
3300 10:54:59.476855
3301 10:54:59.480106 RX Vref 32 -> 127, step: 1
3302 10:54:59.480203
3303 10:54:59.483567 RX Delay -21 -> 252, step: 4
3304 10:54:59.483653
3305 10:54:59.487133 Set Vref, RX VrefLevel [Byte0]: 32
3306 10:54:59.490113 [Byte1]: 32
3307 10:54:59.490197
3308 10:54:59.493936 Set Vref, RX VrefLevel [Byte0]: 33
3309 10:54:59.497084 [Byte1]: 33
3310 10:54:59.497170
3311 10:54:59.500372 Set Vref, RX VrefLevel [Byte0]: 34
3312 10:54:59.503671 [Byte1]: 34
3313 10:54:59.507508
3314 10:54:59.507600 Set Vref, RX VrefLevel [Byte0]: 35
3315 10:54:59.511215 [Byte1]: 35
3316 10:54:59.515428
3317 10:54:59.515520 Set Vref, RX VrefLevel [Byte0]: 36
3318 10:54:59.518867 [Byte1]: 36
3319 10:54:59.523527
3320 10:54:59.523619 Set Vref, RX VrefLevel [Byte0]: 37
3321 10:54:59.526616 [Byte1]: 37
3322 10:54:59.531568
3323 10:54:59.531662 Set Vref, RX VrefLevel [Byte0]: 38
3324 10:54:59.534943 [Byte1]: 38
3325 10:54:59.539139
3326 10:54:59.539228 Set Vref, RX VrefLevel [Byte0]: 39
3327 10:54:59.542646 [Byte1]: 39
3328 10:54:59.547554
3329 10:54:59.547639 Set Vref, RX VrefLevel [Byte0]: 40
3330 10:54:59.550278 [Byte1]: 40
3331 10:54:59.555180
3332 10:54:59.555260 Set Vref, RX VrefLevel [Byte0]: 41
3333 10:54:59.558360 [Byte1]: 41
3334 10:54:59.563103
3335 10:54:59.563184 Set Vref, RX VrefLevel [Byte0]: 42
3336 10:54:59.566973 [Byte1]: 42
3337 10:54:59.570996
3338 10:54:59.571077 Set Vref, RX VrefLevel [Byte0]: 43
3339 10:54:59.575010 [Byte1]: 43
3340 10:54:59.578675
3341 10:54:59.578756 Set Vref, RX VrefLevel [Byte0]: 44
3342 10:54:59.582240 [Byte1]: 44
3343 10:54:59.586672
3344 10:54:59.586752 Set Vref, RX VrefLevel [Byte0]: 45
3345 10:54:59.590245 [Byte1]: 45
3346 10:54:59.595173
3347 10:54:59.595254 Set Vref, RX VrefLevel [Byte0]: 46
3348 10:54:59.598335 [Byte1]: 46
3349 10:54:59.602849
3350 10:54:59.602930 Set Vref, RX VrefLevel [Byte0]: 47
3351 10:54:59.606176 [Byte1]: 47
3352 10:54:59.610764
3353 10:54:59.610845 Set Vref, RX VrefLevel [Byte0]: 48
3354 10:54:59.614078 [Byte1]: 48
3355 10:54:59.618760
3356 10:54:59.618839 Set Vref, RX VrefLevel [Byte0]: 49
3357 10:54:59.622226 [Byte1]: 49
3358 10:54:59.626726
3359 10:54:59.626806 Set Vref, RX VrefLevel [Byte0]: 50
3360 10:54:59.629584 [Byte1]: 50
3361 10:54:59.634131
3362 10:54:59.634211 Set Vref, RX VrefLevel [Byte0]: 51
3363 10:54:59.637795 [Byte1]: 51
3364 10:54:59.642032
3365 10:54:59.642113 Set Vref, RX VrefLevel [Byte0]: 52
3366 10:54:59.645911 [Byte1]: 52
3367 10:54:59.650437
3368 10:54:59.650520 Set Vref, RX VrefLevel [Byte0]: 53
3369 10:54:59.653358 [Byte1]: 53
3370 10:54:59.658307
3371 10:54:59.658395 Set Vref, RX VrefLevel [Byte0]: 54
3372 10:54:59.661155 [Byte1]: 54
3373 10:54:59.666140
3374 10:54:59.666222 Set Vref, RX VrefLevel [Byte0]: 55
3375 10:54:59.669350 [Byte1]: 55
3376 10:54:59.673941
3377 10:54:59.674022 Set Vref, RX VrefLevel [Byte0]: 56
3378 10:54:59.677263 [Byte1]: 56
3379 10:54:59.681942
3380 10:54:59.682022 Set Vref, RX VrefLevel [Byte0]: 57
3381 10:54:59.685616 [Byte1]: 57
3382 10:54:59.690361
3383 10:54:59.690442 Set Vref, RX VrefLevel [Byte0]: 58
3384 10:54:59.693080 [Byte1]: 58
3385 10:54:59.697533
3386 10:54:59.697614 Set Vref, RX VrefLevel [Byte0]: 59
3387 10:54:59.704147 [Byte1]: 59
3388 10:54:59.704229
3389 10:54:59.707893 Set Vref, RX VrefLevel [Byte0]: 60
3390 10:54:59.710952 [Byte1]: 60
3391 10:54:59.711033
3392 10:54:59.714121 Set Vref, RX VrefLevel [Byte0]: 61
3393 10:54:59.717267 [Byte1]: 61
3394 10:54:59.721674
3395 10:54:59.721755 Set Vref, RX VrefLevel [Byte0]: 62
3396 10:54:59.724565 [Byte1]: 62
3397 10:54:59.729263
3398 10:54:59.729343 Set Vref, RX VrefLevel [Byte0]: 63
3399 10:54:59.733084 [Byte1]: 63
3400 10:54:59.737573
3401 10:54:59.737654 Set Vref, RX VrefLevel [Byte0]: 64
3402 10:54:59.740551 [Byte1]: 64
3403 10:54:59.745154
3404 10:54:59.745261 Set Vref, RX VrefLevel [Byte0]: 65
3405 10:54:59.748723 [Byte1]: 65
3406 10:54:59.753540
3407 10:54:59.753621 Set Vref, RX VrefLevel [Byte0]: 66
3408 10:54:59.756581 [Byte1]: 66
3409 10:54:59.761112
3410 10:54:59.761209 Set Vref, RX VrefLevel [Byte0]: 67
3411 10:54:59.764330 [Byte1]: 67
3412 10:54:59.768952
3413 10:54:59.769034 Set Vref, RX VrefLevel [Byte0]: 68
3414 10:54:59.772942 [Byte1]: 68
3415 10:54:59.777255
3416 10:54:59.777337 Set Vref, RX VrefLevel [Byte0]: 69
3417 10:54:59.780385 [Byte1]: 69
3418 10:54:59.784777
3419 10:54:59.784864 Set Vref, RX VrefLevel [Byte0]: 70
3420 10:54:59.788406 [Byte1]: 70
3421 10:54:59.792792
3422 10:54:59.792874 Set Vref, RX VrefLevel [Byte0]: 71
3423 10:54:59.796608 [Byte1]: 71
3424 10:54:59.800437
3425 10:54:59.803812 Final RX Vref Byte 0 = 57 to rank0
3426 10:54:59.803895 Final RX Vref Byte 1 = 54 to rank0
3427 10:54:59.807140 Final RX Vref Byte 0 = 57 to rank1
3428 10:54:59.810392 Final RX Vref Byte 1 = 54 to rank1==
3429 10:54:59.813840 Dram Type= 6, Freq= 0, CH_1, rank 0
3430 10:54:59.820459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 10:54:59.820542 ==
3432 10:54:59.820607 DQS Delay:
3433 10:54:59.823692 DQS0 = 0, DQS1 = 0
3434 10:54:59.823774 DQM Delay:
3435 10:54:59.823839 DQM0 = 116, DQM1 = 109
3436 10:54:59.827773 DQ Delay:
3437 10:54:59.830689 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3438 10:54:59.833481 DQ4 =114, DQ5 =126, DQ6 =128, DQ7 =114
3439 10:54:59.837054 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3440 10:54:59.840404 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =114
3441 10:54:59.840486
3442 10:54:59.840550
3443 10:54:59.850122 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3444 10:54:59.850234 CH1 RK0: MR19=303, MR18=FEE2
3445 10:54:59.857221 CH1_RK0: MR19=0x303, MR18=0xFEE2, DQSOSC=410, MR23=63, INC=39, DEC=26
3446 10:54:59.857344
3447 10:54:59.860661 ----->DramcWriteLeveling(PI) begin...
3448 10:54:59.860744 ==
3449 10:54:59.863995 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 10:54:59.867013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 10:54:59.870330 ==
3452 10:54:59.870411 Write leveling (Byte 0): 27 => 27
3453 10:54:59.873492 Write leveling (Byte 1): 28 => 28
3454 10:54:59.877052 DramcWriteLeveling(PI) end<-----
3455 10:54:59.877133
3456 10:54:59.877198 ==
3457 10:54:59.880647 Dram Type= 6, Freq= 0, CH_1, rank 1
3458 10:54:59.887138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 10:54:59.887246 ==
3460 10:54:59.890148 [Gating] SW mode calibration
3461 10:54:59.896860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3462 10:54:59.900590 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3463 10:54:59.907340 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3464 10:54:59.910854 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 10:54:59.913537 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 10:54:59.917144 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 10:54:59.923867 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3468 10:54:59.927141 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3469 10:54:59.930334 0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 1)
3470 10:54:59.937250 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3471 10:54:59.940564 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 10:54:59.943687 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 10:54:59.950330 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 10:54:59.954049 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 10:54:59.957201 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 10:54:59.963622 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 10:54:59.966995 1 0 24 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3478 10:54:59.970256 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 10:54:59.976820 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 10:54:59.980399 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 10:54:59.983486 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 10:54:59.990555 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 10:54:59.993404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 10:54:59.996907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3485 10:55:00.003468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3486 10:55:00.006841 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3487 10:55:00.010106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 10:55:00.016744 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 10:55:00.020007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 10:55:00.023165 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 10:55:00.029737 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 10:55:00.033443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 10:55:00.036579 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 10:55:00.043132 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 10:55:00.046762 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 10:55:00.050073 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 10:55:00.056597 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 10:55:00.059982 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 10:55:00.063307 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 10:55:00.066480 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3501 10:55:00.073314 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 10:55:00.076290 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3503 10:55:00.080178 Total UI for P1: 0, mck2ui 16
3504 10:55:00.082941 best dqsien dly found for B0: ( 1, 3, 22)
3505 10:55:00.086320 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 10:55:00.089542 Total UI for P1: 0, mck2ui 16
3507 10:55:00.092983 best dqsien dly found for B1: ( 1, 3, 28)
3508 10:55:00.096225 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3509 10:55:00.102821 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3510 10:55:00.102906
3511 10:55:00.106562 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3512 10:55:00.109884 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3513 10:55:00.113294 [Gating] SW calibration Done
3514 10:55:00.113376 ==
3515 10:55:00.116310 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 10:55:00.119566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 10:55:00.119650 ==
3518 10:55:00.119716 RX Vref Scan: 0
3519 10:55:00.122603
3520 10:55:00.122687 RX Vref 0 -> 0, step: 1
3521 10:55:00.122753
3522 10:55:00.125988 RX Delay -40 -> 252, step: 8
3523 10:55:00.129310 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3524 10:55:00.132581 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3525 10:55:00.139549 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3526 10:55:00.142901 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3527 10:55:00.146141 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3528 10:55:00.149359 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3529 10:55:00.153005 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3530 10:55:00.159688 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3531 10:55:00.162842 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3532 10:55:00.166316 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3533 10:55:00.169205 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3534 10:55:00.172865 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3535 10:55:00.179264 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3536 10:55:00.182943 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3537 10:55:00.186504 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3538 10:55:00.189289 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3539 10:55:00.189372 ==
3540 10:55:00.192402 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 10:55:00.199314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 10:55:00.199437 ==
3543 10:55:00.199503 DQS Delay:
3544 10:55:00.199563 DQS0 = 0, DQS1 = 0
3545 10:55:00.202440 DQM Delay:
3546 10:55:00.202521 DQM0 = 113, DQM1 = 111
3547 10:55:00.206139 DQ Delay:
3548 10:55:00.209355 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3549 10:55:00.212626 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3550 10:55:00.216252 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3551 10:55:00.219296 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3552 10:55:00.219417
3553 10:55:00.219482
3554 10:55:00.219542 ==
3555 10:55:00.222557 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 10:55:00.225887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 10:55:00.225969 ==
3558 10:55:00.229589
3559 10:55:00.229670
3560 10:55:00.229735 TX Vref Scan disable
3561 10:55:00.232630 == TX Byte 0 ==
3562 10:55:00.236671 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3563 10:55:00.238961 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3564 10:55:00.242287 == TX Byte 1 ==
3565 10:55:00.245811 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 10:55:00.249457 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 10:55:00.249539 ==
3568 10:55:00.252275 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 10:55:00.259190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 10:55:00.259272 ==
3571 10:55:00.269429 TX Vref=22, minBit 1, minWin=25, winSum=416
3572 10:55:00.272830 TX Vref=24, minBit 3, minWin=25, winSum=421
3573 10:55:00.276111 TX Vref=26, minBit 1, minWin=25, winSum=428
3574 10:55:00.279290 TX Vref=28, minBit 2, minWin=26, winSum=430
3575 10:55:00.283122 TX Vref=30, minBit 4, minWin=26, winSum=432
3576 10:55:00.289401 TX Vref=32, minBit 2, minWin=26, winSum=430
3577 10:55:00.292988 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 30
3578 10:55:00.293071
3579 10:55:00.296111 Final TX Range 1 Vref 30
3580 10:55:00.296193
3581 10:55:00.296258 ==
3582 10:55:00.299769 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 10:55:00.302668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 10:55:00.305727 ==
3585 10:55:00.305808
3586 10:55:00.305872
3587 10:55:00.305942 TX Vref Scan disable
3588 10:55:00.309214 == TX Byte 0 ==
3589 10:55:00.312549 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3590 10:55:00.319613 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3591 10:55:00.319697 == TX Byte 1 ==
3592 10:55:00.322444 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 10:55:00.329109 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 10:55:00.329192
3595 10:55:00.329257 [DATLAT]
3596 10:55:00.329317 Freq=1200, CH1 RK1
3597 10:55:00.329375
3598 10:55:00.332380 DATLAT Default: 0xd
3599 10:55:00.332461 0, 0xFFFF, sum = 0
3600 10:55:00.335632 1, 0xFFFF, sum = 0
3601 10:55:00.339189 2, 0xFFFF, sum = 0
3602 10:55:00.339271 3, 0xFFFF, sum = 0
3603 10:55:00.342484 4, 0xFFFF, sum = 0
3604 10:55:00.342567 5, 0xFFFF, sum = 0
3605 10:55:00.345868 6, 0xFFFF, sum = 0
3606 10:55:00.345978 7, 0xFFFF, sum = 0
3607 10:55:00.349032 8, 0xFFFF, sum = 0
3608 10:55:00.349115 9, 0xFFFF, sum = 0
3609 10:55:00.352631 10, 0xFFFF, sum = 0
3610 10:55:00.352715 11, 0xFFFF, sum = 0
3611 10:55:00.356081 12, 0x0, sum = 1
3612 10:55:00.356164 13, 0x0, sum = 2
3613 10:55:00.359001 14, 0x0, sum = 3
3614 10:55:00.359089 15, 0x0, sum = 4
3615 10:55:00.362535 best_step = 13
3616 10:55:00.362616
3617 10:55:00.362680 ==
3618 10:55:00.365838 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 10:55:00.369312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 10:55:00.369394 ==
3621 10:55:00.369459 RX Vref Scan: 0
3622 10:55:00.369519
3623 10:55:00.372455 RX Vref 0 -> 0, step: 1
3624 10:55:00.372536
3625 10:55:00.375501 RX Delay -21 -> 252, step: 4
3626 10:55:00.382024 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3627 10:55:00.385682 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3628 10:55:00.388916 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3629 10:55:00.392084 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3630 10:55:00.395554 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3631 10:55:00.398842 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3632 10:55:00.405583 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3633 10:55:00.408574 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3634 10:55:00.411825 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3635 10:55:00.415147 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3636 10:55:00.418444 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3637 10:55:00.425167 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3638 10:55:00.428567 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3639 10:55:00.431581 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3640 10:55:00.435263 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3641 10:55:00.441913 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3642 10:55:00.441997 ==
3643 10:55:00.445270 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 10:55:00.448335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 10:55:00.448450 ==
3646 10:55:00.448556 DQS Delay:
3647 10:55:00.451971 DQS0 = 0, DQS1 = 0
3648 10:55:00.452054 DQM Delay:
3649 10:55:00.455130 DQM0 = 113, DQM1 = 110
3650 10:55:00.455213 DQ Delay:
3651 10:55:00.458806 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3652 10:55:00.461640 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3653 10:55:00.464868 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3654 10:55:00.468632 DQ12 =116, DQ13 =120, DQ14 =118, DQ15 =120
3655 10:55:00.468717
3656 10:55:00.468783
3657 10:55:00.478671 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3658 10:55:00.481606 CH1 RK1: MR19=303, MR18=F7FE
3659 10:55:00.485107 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3660 10:55:00.487962 [RxdqsGatingPostProcess] freq 1200
3661 10:55:00.494543 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3662 10:55:00.497926 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 10:55:00.501390 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 10:55:00.504558 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 10:55:00.508366 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 10:55:00.511756 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 10:55:00.514916 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 10:55:00.518312 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 10:55:00.521591 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 10:55:00.524593 Pre-setting of DQS Precalculation
3671 10:55:00.527932 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3672 10:55:00.534565 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3673 10:55:00.541145 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3674 10:55:00.544293
3675 10:55:00.544401
3676 10:55:00.544497 [Calibration Summary] 2400 Mbps
3677 10:55:00.548241 CH 0, Rank 0
3678 10:55:00.548323 SW Impedance : PASS
3679 10:55:00.551279 DUTY Scan : NO K
3680 10:55:00.554903 ZQ Calibration : PASS
3681 10:55:00.554985 Jitter Meter : NO K
3682 10:55:00.558216 CBT Training : PASS
3683 10:55:00.560959 Write leveling : PASS
3684 10:55:00.561041 RX DQS gating : PASS
3685 10:55:00.564403 RX DQ/DQS(RDDQC) : PASS
3686 10:55:00.567687 TX DQ/DQS : PASS
3687 10:55:00.567769 RX DATLAT : PASS
3688 10:55:00.570904 RX DQ/DQS(Engine): PASS
3689 10:55:00.574609 TX OE : NO K
3690 10:55:00.574691 All Pass.
3691 10:55:00.574755
3692 10:55:00.574815 CH 0, Rank 1
3693 10:55:00.577788 SW Impedance : PASS
3694 10:55:00.581116 DUTY Scan : NO K
3695 10:55:00.581198 ZQ Calibration : PASS
3696 10:55:00.584190 Jitter Meter : NO K
3697 10:55:00.587898 CBT Training : PASS
3698 10:55:00.587979 Write leveling : PASS
3699 10:55:00.591019 RX DQS gating : PASS
3700 10:55:00.591101 RX DQ/DQS(RDDQC) : PASS
3701 10:55:00.594258 TX DQ/DQS : PASS
3702 10:55:00.597692 RX DATLAT : PASS
3703 10:55:00.597775 RX DQ/DQS(Engine): PASS
3704 10:55:00.601121 TX OE : NO K
3705 10:55:00.601205 All Pass.
3706 10:55:00.601270
3707 10:55:00.604050 CH 1, Rank 0
3708 10:55:00.604132 SW Impedance : PASS
3709 10:55:00.607468 DUTY Scan : NO K
3710 10:55:00.610957 ZQ Calibration : PASS
3711 10:55:00.611039 Jitter Meter : NO K
3712 10:55:00.614152 CBT Training : PASS
3713 10:55:00.617749 Write leveling : PASS
3714 10:55:00.617832 RX DQS gating : PASS
3715 10:55:00.620982 RX DQ/DQS(RDDQC) : PASS
3716 10:55:00.624180 TX DQ/DQS : PASS
3717 10:55:00.624289 RX DATLAT : PASS
3718 10:55:00.627988 RX DQ/DQS(Engine): PASS
3719 10:55:00.630721 TX OE : NO K
3720 10:55:00.630804 All Pass.
3721 10:55:00.630870
3722 10:55:00.630930 CH 1, Rank 1
3723 10:55:00.634230 SW Impedance : PASS
3724 10:55:00.637366 DUTY Scan : NO K
3725 10:55:00.637448 ZQ Calibration : PASS
3726 10:55:00.640594 Jitter Meter : NO K
3727 10:55:00.644232 CBT Training : PASS
3728 10:55:00.644314 Write leveling : PASS
3729 10:55:00.647336 RX DQS gating : PASS
3730 10:55:00.647428 RX DQ/DQS(RDDQC) : PASS
3731 10:55:00.650882 TX DQ/DQS : PASS
3732 10:55:00.654715 RX DATLAT : PASS
3733 10:55:00.654798 RX DQ/DQS(Engine): PASS
3734 10:55:00.658194 TX OE : NO K
3735 10:55:00.658277 All Pass.
3736 10:55:00.658342
3737 10:55:00.661184 DramC Write-DBI off
3738 10:55:00.664702 PER_BANK_REFRESH: Hybrid Mode
3739 10:55:00.664785 TX_TRACKING: ON
3740 10:55:00.673926 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3741 10:55:00.677648 [FAST_K] Save calibration result to emmc
3742 10:55:00.680982 dramc_set_vcore_voltage set vcore to 650000
3743 10:55:00.684077 Read voltage for 600, 5
3744 10:55:00.684161 Vio18 = 0
3745 10:55:00.684227 Vcore = 650000
3746 10:55:00.687638 Vdram = 0
3747 10:55:00.687721 Vddq = 0
3748 10:55:00.687788 Vmddr = 0
3749 10:55:00.694737 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3750 10:55:00.697706 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3751 10:55:00.701033 MEM_TYPE=3, freq_sel=19
3752 10:55:00.704054 sv_algorithm_assistance_LP4_1600
3753 10:55:00.707868 ============ PULL DRAM RESETB DOWN ============
3754 10:55:00.710967 ========== PULL DRAM RESETB DOWN end =========
3755 10:55:00.717852 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3756 10:55:00.720851 ===================================
3757 10:55:00.724010 LPDDR4 DRAM CONFIGURATION
3758 10:55:00.727210 ===================================
3759 10:55:00.727295 EX_ROW_EN[0] = 0x0
3760 10:55:00.730329 EX_ROW_EN[1] = 0x0
3761 10:55:00.730412 LP4Y_EN = 0x0
3762 10:55:00.733774 WORK_FSP = 0x0
3763 10:55:00.733857 WL = 0x2
3764 10:55:00.737175 RL = 0x2
3765 10:55:00.737258 BL = 0x2
3766 10:55:00.740425 RPST = 0x0
3767 10:55:00.740508 RD_PRE = 0x0
3768 10:55:00.744009 WR_PRE = 0x1
3769 10:55:00.744092 WR_PST = 0x0
3770 10:55:00.746859 DBI_WR = 0x0
3771 10:55:00.746942 DBI_RD = 0x0
3772 10:55:00.750428 OTF = 0x1
3773 10:55:00.753793 ===================================
3774 10:55:00.757004 ===================================
3775 10:55:00.757087 ANA top config
3776 10:55:00.760416 ===================================
3777 10:55:00.763594 DLL_ASYNC_EN = 0
3778 10:55:00.766631 ALL_SLAVE_EN = 1
3779 10:55:00.770147 NEW_RANK_MODE = 1
3780 10:55:00.773825 DLL_IDLE_MODE = 1
3781 10:55:00.773909 LP45_APHY_COMB_EN = 1
3782 10:55:00.776902 TX_ODT_DIS = 1
3783 10:55:00.780268 NEW_8X_MODE = 1
3784 10:55:00.783578 ===================================
3785 10:55:00.786770 ===================================
3786 10:55:00.790081 data_rate = 1200
3787 10:55:00.793501 CKR = 1
3788 10:55:00.793584 DQ_P2S_RATIO = 8
3789 10:55:00.796638 ===================================
3790 10:55:00.799977 CA_P2S_RATIO = 8
3791 10:55:00.803471 DQ_CA_OPEN = 0
3792 10:55:00.806759 DQ_SEMI_OPEN = 0
3793 10:55:00.810797 CA_SEMI_OPEN = 0
3794 10:55:00.813570 CA_FULL_RATE = 0
3795 10:55:00.813654 DQ_CKDIV4_EN = 1
3796 10:55:00.816521 CA_CKDIV4_EN = 1
3797 10:55:00.820031 CA_PREDIV_EN = 0
3798 10:55:00.823807 PH8_DLY = 0
3799 10:55:00.826601 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3800 10:55:00.826685 DQ_AAMCK_DIV = 4
3801 10:55:00.829933 CA_AAMCK_DIV = 4
3802 10:55:00.833741 CA_ADMCK_DIV = 4
3803 10:55:00.836616 DQ_TRACK_CA_EN = 0
3804 10:55:00.839824 CA_PICK = 600
3805 10:55:00.843099 CA_MCKIO = 600
3806 10:55:00.846752 MCKIO_SEMI = 0
3807 10:55:00.846834 PLL_FREQ = 2288
3808 10:55:00.850220 DQ_UI_PI_RATIO = 32
3809 10:55:00.853132 CA_UI_PI_RATIO = 0
3810 10:55:00.856606 ===================================
3811 10:55:00.860025 ===================================
3812 10:55:00.863897 memory_type:LPDDR4
3813 10:55:00.866665 GP_NUM : 10
3814 10:55:00.866749 SRAM_EN : 1
3815 10:55:00.869688 MD32_EN : 0
3816 10:55:00.873311 ===================================
3817 10:55:00.873395 [ANA_INIT] >>>>>>>>>>>>>>
3818 10:55:00.876476 <<<<<< [CONFIGURE PHASE]: ANA_TX
3819 10:55:00.879707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3820 10:55:00.883571 ===================================
3821 10:55:00.886469 data_rate = 1200,PCW = 0X5800
3822 10:55:00.889602 ===================================
3823 10:55:00.893374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3824 10:55:00.899886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 10:55:00.903286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 10:55:00.909574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3827 10:55:00.913327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3828 10:55:00.916495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3829 10:55:00.920309 [ANA_INIT] flow start
3830 10:55:00.920394 [ANA_INIT] PLL >>>>>>>>
3831 10:55:00.923423 [ANA_INIT] PLL <<<<<<<<
3832 10:55:00.926399 [ANA_INIT] MIDPI >>>>>>>>
3833 10:55:00.926482 [ANA_INIT] MIDPI <<<<<<<<
3834 10:55:00.929516 [ANA_INIT] DLL >>>>>>>>
3835 10:55:00.933125 [ANA_INIT] flow end
3836 10:55:00.936110 ============ LP4 DIFF to SE enter ============
3837 10:55:00.939481 ============ LP4 DIFF to SE exit ============
3838 10:55:00.942610 [ANA_INIT] <<<<<<<<<<<<<
3839 10:55:00.946104 [Flow] Enable top DCM control >>>>>
3840 10:55:00.949123 [Flow] Enable top DCM control <<<<<
3841 10:55:00.953325 Enable DLL master slave shuffle
3842 10:55:00.955789 ==============================================================
3843 10:55:00.959267 Gating Mode config
3844 10:55:00.966345 ==============================================================
3845 10:55:00.966431 Config description:
3846 10:55:00.975933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3847 10:55:00.982538 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3848 10:55:00.989038 SELPH_MODE 0: By rank 1: By Phase
3849 10:55:00.992596 ==============================================================
3850 10:55:00.995598 GAT_TRACK_EN = 1
3851 10:55:00.999632 RX_GATING_MODE = 2
3852 10:55:01.002546 RX_GATING_TRACK_MODE = 2
3853 10:55:01.005991 SELPH_MODE = 1
3854 10:55:01.008980 PICG_EARLY_EN = 1
3855 10:55:01.012422 VALID_LAT_VALUE = 1
3856 10:55:01.015790 ==============================================================
3857 10:55:01.019244 Enter into Gating configuration >>>>
3858 10:55:01.022396 Exit from Gating configuration <<<<
3859 10:55:01.025718 Enter into DVFS_PRE_config >>>>>
3860 10:55:01.038948 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3861 10:55:01.042322 Exit from DVFS_PRE_config <<<<<
3862 10:55:01.042410 Enter into PICG configuration >>>>
3863 10:55:01.045312 Exit from PICG configuration <<<<
3864 10:55:01.048713 [RX_INPUT] configuration >>>>>
3865 10:55:01.052253 [RX_INPUT] configuration <<<<<
3866 10:55:01.058960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3867 10:55:01.062307 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3868 10:55:01.068769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 10:55:01.075827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 10:55:01.081808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 10:55:01.088656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 10:55:01.091945 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3873 10:55:01.095327 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3874 10:55:01.098435 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3875 10:55:01.105116 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3876 10:55:01.108332 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3877 10:55:01.112002 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 10:55:01.115081 ===================================
3879 10:55:01.118416 LPDDR4 DRAM CONFIGURATION
3880 10:55:01.121667 ===================================
3881 10:55:01.124986 EX_ROW_EN[0] = 0x0
3882 10:55:01.125073 EX_ROW_EN[1] = 0x0
3883 10:55:01.128565 LP4Y_EN = 0x0
3884 10:55:01.128650 WORK_FSP = 0x0
3885 10:55:01.131688 WL = 0x2
3886 10:55:01.131773 RL = 0x2
3887 10:55:01.135120 BL = 0x2
3888 10:55:01.135207 RPST = 0x0
3889 10:55:01.138181 RD_PRE = 0x0
3890 10:55:01.138266 WR_PRE = 0x1
3891 10:55:01.141560 WR_PST = 0x0
3892 10:55:01.141645 DBI_WR = 0x0
3893 10:55:01.145107 DBI_RD = 0x0
3894 10:55:01.145194 OTF = 0x1
3895 10:55:01.147997 ===================================
3896 10:55:01.154971 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3897 10:55:01.158179 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3898 10:55:01.161423 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 10:55:01.165023 ===================================
3900 10:55:01.168306 LPDDR4 DRAM CONFIGURATION
3901 10:55:01.171296 ===================================
3902 10:55:01.174826 EX_ROW_EN[0] = 0x10
3903 10:55:01.174912 EX_ROW_EN[1] = 0x0
3904 10:55:01.178466 LP4Y_EN = 0x0
3905 10:55:01.178551 WORK_FSP = 0x0
3906 10:55:01.181384 WL = 0x2
3907 10:55:01.181469 RL = 0x2
3908 10:55:01.184652 BL = 0x2
3909 10:55:01.184737 RPST = 0x0
3910 10:55:01.188014 RD_PRE = 0x0
3911 10:55:01.188099 WR_PRE = 0x1
3912 10:55:01.191260 WR_PST = 0x0
3913 10:55:01.191376 DBI_WR = 0x0
3914 10:55:01.194644 DBI_RD = 0x0
3915 10:55:01.194729 OTF = 0x1
3916 10:55:01.197629 ===================================
3917 10:55:01.204832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3918 10:55:01.209380 nWR fixed to 30
3919 10:55:01.212248 [ModeRegInit_LP4] CH0 RK0
3920 10:55:01.212334 [ModeRegInit_LP4] CH0 RK1
3921 10:55:01.215776 [ModeRegInit_LP4] CH1 RK0
3922 10:55:01.218955 [ModeRegInit_LP4] CH1 RK1
3923 10:55:01.219038 match AC timing 17
3924 10:55:01.225267 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3925 10:55:01.228800 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3926 10:55:01.232273 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3927 10:55:01.238658 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3928 10:55:01.242122 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3929 10:55:01.242211 ==
3930 10:55:01.245549 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 10:55:01.248821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 10:55:01.248907 ==
3933 10:55:01.255263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 10:55:01.262152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3935 10:55:01.265948 [CA 0] Center 36 (6~66) winsize 61
3936 10:55:01.268661 [CA 1] Center 36 (6~66) winsize 61
3937 10:55:01.271886 [CA 2] Center 34 (4~65) winsize 62
3938 10:55:01.275659 [CA 3] Center 34 (4~64) winsize 61
3939 10:55:01.278494 [CA 4] Center 33 (3~64) winsize 62
3940 10:55:01.281906 [CA 5] Center 33 (3~64) winsize 62
3941 10:55:01.281990
3942 10:55:01.285396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3943 10:55:01.285479
3944 10:55:01.288593 [CATrainingPosCal] consider 1 rank data
3945 10:55:01.291918 u2DelayCellTimex100 = 270/100 ps
3946 10:55:01.295284 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3947 10:55:01.298626 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3948 10:55:01.302108 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 10:55:01.305197 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3950 10:55:01.308431 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 10:55:01.315345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 10:55:01.315477
3953 10:55:01.318271 CA PerBit enable=1, Macro0, CA PI delay=33
3954 10:55:01.318357
3955 10:55:01.321858 [CBTSetCACLKResult] CA Dly = 33
3956 10:55:01.321943 CS Dly: 4 (0~35)
3957 10:55:01.322011 ==
3958 10:55:01.325023 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 10:55:01.328291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 10:55:01.331754 ==
3961 10:55:01.335220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 10:55:01.341782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3963 10:55:01.345187 [CA 0] Center 36 (6~66) winsize 61
3964 10:55:01.348372 [CA 1] Center 36 (6~66) winsize 61
3965 10:55:01.351910 [CA 2] Center 34 (4~65) winsize 62
3966 10:55:01.355053 [CA 3] Center 34 (4~65) winsize 62
3967 10:55:01.358469 [CA 4] Center 33 (3~64) winsize 62
3968 10:55:01.362291 [CA 5] Center 33 (3~64) winsize 62
3969 10:55:01.362384
3970 10:55:01.364839 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3971 10:55:01.364926
3972 10:55:01.368765 [CATrainingPosCal] consider 2 rank data
3973 10:55:01.371364 u2DelayCellTimex100 = 270/100 ps
3974 10:55:01.375713 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 10:55:01.378428 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 10:55:01.381694 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 10:55:01.384971 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3978 10:55:01.391670 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 10:55:01.394935 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 10:55:01.395026
3981 10:55:01.398083 CA PerBit enable=1, Macro0, CA PI delay=33
3982 10:55:01.398167
3983 10:55:01.401542 [CBTSetCACLKResult] CA Dly = 33
3984 10:55:01.401625 CS Dly: 5 (0~37)
3985 10:55:01.401690
3986 10:55:01.405076 ----->DramcWriteLeveling(PI) begin...
3987 10:55:01.405165 ==
3988 10:55:01.408041 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 10:55:01.414771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 10:55:01.414869 ==
3991 10:55:01.418293 Write leveling (Byte 0): 32 => 32
3992 10:55:01.421289 Write leveling (Byte 1): 29 => 29
3993 10:55:01.421376 DramcWriteLeveling(PI) end<-----
3994 10:55:01.421442
3995 10:55:01.425255 ==
3996 10:55:01.428548 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 10:55:01.431312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 10:55:01.431402 ==
3999 10:55:01.435247 [Gating] SW mode calibration
4000 10:55:01.441653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4001 10:55:01.445028 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4002 10:55:01.451561 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 10:55:01.454540 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 10:55:01.458025 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 10:55:01.464592 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 10:55:01.468308 0 9 16 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (0 0)
4007 10:55:01.471223 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4008 10:55:01.477947 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 10:55:01.481023 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 10:55:01.484453 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 10:55:01.491471 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 10:55:01.494642 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 10:55:01.498079 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 10:55:01.501639 0 10 16 | B1->B0 | 3030 4040 | 1 1 | (0 0) (0 0)
4015 10:55:01.508244 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4016 10:55:01.511286 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 10:55:01.514334 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 10:55:01.521295 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 10:55:01.524671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 10:55:01.527852 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 10:55:01.534592 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 10:55:01.537822 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 10:55:01.540970 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4024 10:55:01.547747 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 10:55:01.551129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 10:55:01.554329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 10:55:01.561342 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 10:55:01.564549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 10:55:01.568071 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 10:55:01.574153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 10:55:01.577969 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 10:55:01.580930 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 10:55:01.587820 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 10:55:01.590482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 10:55:01.594288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 10:55:01.600413 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 10:55:01.603744 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 10:55:01.607867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4039 10:55:01.610675 Total UI for P1: 0, mck2ui 16
4040 10:55:01.614121 best dqsien dly found for B0: ( 0, 13, 14)
4041 10:55:01.621005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 10:55:01.621093 Total UI for P1: 0, mck2ui 16
4043 10:55:01.626848 best dqsien dly found for B1: ( 0, 13, 16)
4044 10:55:01.630374 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4045 10:55:01.633808 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4046 10:55:01.633894
4047 10:55:01.636783 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4048 10:55:01.640592 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 10:55:01.643322 [Gating] SW calibration Done
4050 10:55:01.643432 ==
4051 10:55:01.646903 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 10:55:01.650122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 10:55:01.650209 ==
4054 10:55:01.653733 RX Vref Scan: 0
4055 10:55:01.653819
4056 10:55:01.653904 RX Vref 0 -> 0, step: 1
4057 10:55:01.653985
4058 10:55:01.657110 RX Delay -230 -> 252, step: 16
4059 10:55:01.663509 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4060 10:55:01.667230 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4061 10:55:01.670081 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4062 10:55:01.673340 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4063 10:55:01.676801 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4064 10:55:01.683919 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4065 10:55:01.686793 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4066 10:55:01.690475 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4067 10:55:01.693858 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4068 10:55:01.700852 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4069 10:55:01.703623 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4070 10:55:01.706687 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4071 10:55:01.710072 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4072 10:55:01.713655 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4073 10:55:01.720242 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4074 10:55:01.723302 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4075 10:55:01.723430 ==
4076 10:55:01.726760 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 10:55:01.730059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 10:55:01.730145 ==
4079 10:55:01.733166 DQS Delay:
4080 10:55:01.733251 DQS0 = 0, DQS1 = 0
4081 10:55:01.736981 DQM Delay:
4082 10:55:01.737066 DQM0 = 42, DQM1 = 32
4083 10:55:01.737151 DQ Delay:
4084 10:55:01.740276 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4085 10:55:01.743376 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4086 10:55:01.747172 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4087 10:55:01.750139 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4088 10:55:01.750225
4089 10:55:01.750310
4090 10:55:01.750390 ==
4091 10:55:01.753447 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 10:55:01.760103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 10:55:01.760189 ==
4094 10:55:01.760274
4095 10:55:01.760354
4096 10:55:01.763337 TX Vref Scan disable
4097 10:55:01.763458 == TX Byte 0 ==
4098 10:55:01.766691 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 10:55:01.773455 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 10:55:01.773541 == TX Byte 1 ==
4101 10:55:01.780079 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4102 10:55:01.783245 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4103 10:55:01.783330 ==
4104 10:55:01.786264 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 10:55:01.789636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 10:55:01.789721 ==
4107 10:55:01.789807
4108 10:55:01.789887
4109 10:55:01.793187 TX Vref Scan disable
4110 10:55:01.796095 == TX Byte 0 ==
4111 10:55:01.799590 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4112 10:55:01.802868 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4113 10:55:01.806182 == TX Byte 1 ==
4114 10:55:01.809981 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4115 10:55:01.812856 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4116 10:55:01.812941
4117 10:55:01.815970 [DATLAT]
4118 10:55:01.816054 Freq=600, CH0 RK0
4119 10:55:01.816141
4120 10:55:01.819534 DATLAT Default: 0x9
4121 10:55:01.819619 0, 0xFFFF, sum = 0
4122 10:55:01.822986 1, 0xFFFF, sum = 0
4123 10:55:01.823071 2, 0xFFFF, sum = 0
4124 10:55:01.826159 3, 0xFFFF, sum = 0
4125 10:55:01.826245 4, 0xFFFF, sum = 0
4126 10:55:01.829706 5, 0xFFFF, sum = 0
4127 10:55:01.829792 6, 0xFFFF, sum = 0
4128 10:55:01.832534 7, 0xFFFF, sum = 0
4129 10:55:01.832620 8, 0x0, sum = 1
4130 10:55:01.835775 9, 0x0, sum = 2
4131 10:55:01.835861 10, 0x0, sum = 3
4132 10:55:01.839611 11, 0x0, sum = 4
4133 10:55:01.839697 best_step = 9
4134 10:55:01.839781
4135 10:55:01.839861 ==
4136 10:55:01.842370 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 10:55:01.849259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 10:55:01.849345 ==
4139 10:55:01.849431 RX Vref Scan: 1
4140 10:55:01.849512
4141 10:55:01.853018 RX Vref 0 -> 0, step: 1
4142 10:55:01.853102
4143 10:55:01.855739 RX Delay -195 -> 252, step: 8
4144 10:55:01.855824
4145 10:55:01.858963 Set Vref, RX VrefLevel [Byte0]: 54
4146 10:55:01.862512 [Byte1]: 51
4147 10:55:01.862597
4148 10:55:01.865620 Final RX Vref Byte 0 = 54 to rank0
4149 10:55:01.869354 Final RX Vref Byte 1 = 51 to rank0
4150 10:55:01.872540 Final RX Vref Byte 0 = 54 to rank1
4151 10:55:01.875805 Final RX Vref Byte 1 = 51 to rank1==
4152 10:55:01.879024 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 10:55:01.882591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 10:55:01.882674 ==
4155 10:55:01.886295 DQS Delay:
4156 10:55:01.886376 DQS0 = 0, DQS1 = 0
4157 10:55:01.886441 DQM Delay:
4158 10:55:01.889290 DQM0 = 42, DQM1 = 33
4159 10:55:01.889372 DQ Delay:
4160 10:55:01.892702 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4161 10:55:01.895772 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4162 10:55:01.899263 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4163 10:55:01.902216 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4164 10:55:01.902297
4165 10:55:01.902361
4166 10:55:01.912139 [DQSOSCAuto] RK0, (LSB)MR18= 0x3918, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
4167 10:55:01.912239 CH0 RK0: MR19=808, MR18=3918
4168 10:55:01.919238 CH0_RK0: MR19=0x808, MR18=0x3918, DQSOSC=399, MR23=63, INC=164, DEC=109
4169 10:55:01.919346
4170 10:55:01.922220 ----->DramcWriteLeveling(PI) begin...
4171 10:55:01.925492 ==
4172 10:55:01.929029 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 10:55:01.931995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 10:55:01.932078 ==
4175 10:55:01.935346 Write leveling (Byte 0): 30 => 30
4176 10:55:01.939283 Write leveling (Byte 1): 31 => 31
4177 10:55:01.941904 DramcWriteLeveling(PI) end<-----
4178 10:55:01.941985
4179 10:55:01.942049 ==
4180 10:55:01.945608 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 10:55:01.948744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 10:55:01.948826 ==
4183 10:55:01.952325 [Gating] SW mode calibration
4184 10:55:01.958767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4185 10:55:01.965243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4186 10:55:01.969288 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 10:55:01.972116 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 10:55:01.975517 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 10:55:01.981921 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4190 10:55:01.985646 0 9 16 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
4191 10:55:01.989074 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 10:55:01.995478 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 10:55:01.998446 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 10:55:02.002192 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 10:55:02.008533 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 10:55:02.011608 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 10:55:02.015016 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4198 10:55:02.022245 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4199 10:55:02.025287 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 10:55:02.028988 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 10:55:02.035620 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 10:55:02.038462 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 10:55:02.041979 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 10:55:02.048406 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 10:55:02.051675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4206 10:55:02.054860 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4207 10:55:02.061664 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4208 10:55:02.064550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 10:55:02.068149 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 10:55:02.074680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 10:55:02.077815 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 10:55:02.081590 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 10:55:02.088117 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 10:55:02.091117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 10:55:02.094849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 10:55:02.101214 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 10:55:02.104704 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 10:55:02.107865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 10:55:02.115022 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 10:55:02.117826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4221 10:55:02.121080 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4222 10:55:02.127899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4223 10:55:02.127982 Total UI for P1: 0, mck2ui 16
4224 10:55:02.134570 best dqsien dly found for B0: ( 0, 13, 10)
4225 10:55:02.137883 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 10:55:02.141350 Total UI for P1: 0, mck2ui 16
4227 10:55:02.144356 best dqsien dly found for B1: ( 0, 13, 16)
4228 10:55:02.147678 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4229 10:55:02.150704 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4230 10:55:02.150785
4231 10:55:02.153989 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4232 10:55:02.157664 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4233 10:55:02.161138 [Gating] SW calibration Done
4234 10:55:02.161219 ==
4235 10:55:02.163970 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 10:55:02.167621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 10:55:02.170684 ==
4238 10:55:02.170765 RX Vref Scan: 0
4239 10:55:02.170829
4240 10:55:02.174158 RX Vref 0 -> 0, step: 1
4241 10:55:02.174239
4242 10:55:02.177241 RX Delay -230 -> 252, step: 16
4243 10:55:02.180952 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4244 10:55:02.183816 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4245 10:55:02.187373 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4246 10:55:02.193641 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4247 10:55:02.197714 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4248 10:55:02.200353 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4249 10:55:02.203593 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4250 10:55:02.207283 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4251 10:55:02.213823 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4252 10:55:02.217139 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4253 10:55:02.220848 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4254 10:55:02.223685 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4255 10:55:02.230422 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4256 10:55:02.233873 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4257 10:55:02.237103 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4258 10:55:02.240014 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4259 10:55:02.240097 ==
4260 10:55:02.243622 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 10:55:02.250282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 10:55:02.250366 ==
4263 10:55:02.250432 DQS Delay:
4264 10:55:02.253589 DQS0 = 0, DQS1 = 0
4265 10:55:02.253672 DQM Delay:
4266 10:55:02.253738 DQM0 = 39, DQM1 = 33
4267 10:55:02.256968 DQ Delay:
4268 10:55:02.260253 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4269 10:55:02.263291 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4270 10:55:02.266980 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4271 10:55:02.270240 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4272 10:55:02.270323
4273 10:55:02.270388
4274 10:55:02.270448 ==
4275 10:55:02.273894 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 10:55:02.276576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 10:55:02.276663 ==
4278 10:55:02.276729
4279 10:55:02.276788
4280 10:55:02.280262 TX Vref Scan disable
4281 10:55:02.283510 == TX Byte 0 ==
4282 10:55:02.286655 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4283 10:55:02.290901 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4284 10:55:02.293686 == TX Byte 1 ==
4285 10:55:02.296849 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4286 10:55:02.300267 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4287 10:55:02.300351 ==
4288 10:55:02.303101 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 10:55:02.306422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 10:55:02.310372 ==
4291 10:55:02.310454
4292 10:55:02.310520
4293 10:55:02.310580 TX Vref Scan disable
4294 10:55:02.314133 == TX Byte 0 ==
4295 10:55:02.316988 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4296 10:55:02.323476 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4297 10:55:02.323558 == TX Byte 1 ==
4298 10:55:02.326874 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4299 10:55:02.333308 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4300 10:55:02.333389
4301 10:55:02.333453 [DATLAT]
4302 10:55:02.333514 Freq=600, CH0 RK1
4303 10:55:02.333573
4304 10:55:02.336545 DATLAT Default: 0x9
4305 10:55:02.336626 0, 0xFFFF, sum = 0
4306 10:55:02.340126 1, 0xFFFF, sum = 0
4307 10:55:02.344049 2, 0xFFFF, sum = 0
4308 10:55:02.344132 3, 0xFFFF, sum = 0
4309 10:55:02.346753 4, 0xFFFF, sum = 0
4310 10:55:02.346835 5, 0xFFFF, sum = 0
4311 10:55:02.349885 6, 0xFFFF, sum = 0
4312 10:55:02.349969 7, 0xFFFF, sum = 0
4313 10:55:02.353234 8, 0x0, sum = 1
4314 10:55:02.353308 9, 0x0, sum = 2
4315 10:55:02.353371 10, 0x0, sum = 3
4316 10:55:02.356713 11, 0x0, sum = 4
4317 10:55:02.356794 best_step = 9
4318 10:55:02.356858
4319 10:55:02.356917 ==
4320 10:55:02.359997 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 10:55:02.366972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 10:55:02.367054 ==
4323 10:55:02.367117 RX Vref Scan: 0
4324 10:55:02.367177
4325 10:55:02.369864 RX Vref 0 -> 0, step: 1
4326 10:55:02.369945
4327 10:55:02.373359 RX Delay -195 -> 252, step: 8
4328 10:55:02.376638 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4329 10:55:02.383359 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4330 10:55:02.386499 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4331 10:55:02.389872 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4332 10:55:02.393133 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4333 10:55:02.399836 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4334 10:55:02.403295 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4335 10:55:02.406310 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4336 10:55:02.409462 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4337 10:55:02.416310 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4338 10:55:02.419313 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4339 10:55:02.422617 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4340 10:55:02.426145 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4341 10:55:02.432812 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4342 10:55:02.436071 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4343 10:55:02.440192 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4344 10:55:02.440273 ==
4345 10:55:02.442768 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 10:55:02.446104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 10:55:02.446186 ==
4348 10:55:02.449672 DQS Delay:
4349 10:55:02.449752 DQS0 = 0, DQS1 = 0
4350 10:55:02.452773 DQM Delay:
4351 10:55:02.452853 DQM0 = 39, DQM1 = 33
4352 10:55:02.452917 DQ Delay:
4353 10:55:02.455896 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4354 10:55:02.459093 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4355 10:55:02.462654 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4356 10:55:02.466152 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4357 10:55:02.466232
4358 10:55:02.466296
4359 10:55:02.475897 [DQSOSCAuto] RK1, (LSB)MR18= 0x4628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4360 10:55:02.478935 CH0 RK1: MR19=808, MR18=4628
4361 10:55:02.486286 CH0_RK1: MR19=0x808, MR18=0x4628, DQSOSC=396, MR23=63, INC=167, DEC=111
4362 10:55:02.486371 [RxdqsGatingPostProcess] freq 600
4363 10:55:02.492796 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4364 10:55:02.496088 Pre-setting of DQS Precalculation
4365 10:55:02.499014 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4366 10:55:02.502588 ==
4367 10:55:02.505619 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 10:55:02.509108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 10:55:02.509200 ==
4370 10:55:02.512621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 10:55:02.518962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4372 10:55:02.522554 [CA 0] Center 35 (5~65) winsize 61
4373 10:55:02.525962 [CA 1] Center 35 (5~65) winsize 61
4374 10:55:02.529842 [CA 2] Center 34 (4~64) winsize 61
4375 10:55:02.532993 [CA 3] Center 33 (3~64) winsize 62
4376 10:55:02.536693 [CA 4] Center 34 (3~65) winsize 63
4377 10:55:02.539607 [CA 5] Center 33 (3~64) winsize 62
4378 10:55:02.539693
4379 10:55:02.542715 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4380 10:55:02.542802
4381 10:55:02.546121 [CATrainingPosCal] consider 1 rank data
4382 10:55:02.549218 u2DelayCellTimex100 = 270/100 ps
4383 10:55:02.552367 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4384 10:55:02.558988 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4385 10:55:02.562384 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4386 10:55:02.565618 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 10:55:02.568939 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4388 10:55:02.572595 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 10:55:02.572680
4390 10:55:02.576140 CA PerBit enable=1, Macro0, CA PI delay=33
4391 10:55:02.576226
4392 10:55:02.578948 [CBTSetCACLKResult] CA Dly = 33
4393 10:55:02.579033 CS Dly: 5 (0~36)
4394 10:55:02.582806 ==
4395 10:55:02.582891 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 10:55:02.588814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 10:55:02.588900 ==
4398 10:55:02.592719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 10:55:02.599160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4400 10:55:02.603001 [CA 0] Center 35 (5~66) winsize 62
4401 10:55:02.606255 [CA 1] Center 35 (5~66) winsize 62
4402 10:55:02.609428 [CA 2] Center 34 (3~65) winsize 63
4403 10:55:02.612775 [CA 3] Center 34 (3~65) winsize 63
4404 10:55:02.616554 [CA 4] Center 34 (3~65) winsize 63
4405 10:55:02.619253 [CA 5] Center 33 (3~64) winsize 62
4406 10:55:02.619336
4407 10:55:02.622656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4408 10:55:02.622740
4409 10:55:02.625785 [CATrainingPosCal] consider 2 rank data
4410 10:55:02.629440 u2DelayCellTimex100 = 270/100 ps
4411 10:55:02.632774 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4412 10:55:02.638946 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4413 10:55:02.642535 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4414 10:55:02.645546 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 10:55:02.649251 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4416 10:55:02.652319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 10:55:02.652408
4418 10:55:02.655791 CA PerBit enable=1, Macro0, CA PI delay=33
4419 10:55:02.655876
4420 10:55:02.659078 [CBTSetCACLKResult] CA Dly = 33
4421 10:55:02.662831 CS Dly: 6 (0~38)
4422 10:55:02.662920
4423 10:55:02.665386 ----->DramcWriteLeveling(PI) begin...
4424 10:55:02.665466 ==
4425 10:55:02.668999 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 10:55:02.672164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 10:55:02.672251 ==
4428 10:55:02.675905 Write leveling (Byte 0): 31 => 31
4429 10:55:02.678957 Write leveling (Byte 1): 30 => 30
4430 10:55:02.682438 DramcWriteLeveling(PI) end<-----
4431 10:55:02.682522
4432 10:55:02.682608 ==
4433 10:55:02.685331 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 10:55:02.688597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 10:55:02.688684 ==
4436 10:55:02.692312 [Gating] SW mode calibration
4437 10:55:02.698766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4438 10:55:02.705256 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4439 10:55:02.708571 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4440 10:55:02.711877 0 9 4 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
4441 10:55:02.718851 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 10:55:02.721792 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
4443 10:55:02.724988 0 9 16 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
4444 10:55:02.731529 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4445 10:55:02.735200 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 10:55:02.738365 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 10:55:02.745242 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4448 10:55:02.748388 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 10:55:02.751280 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 10:55:02.758095 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4451 10:55:02.761589 0 10 16 | B1->B0 | 3e3e 3e3e | 0 1 | (0 0) (0 0)
4452 10:55:02.764595 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 10:55:02.771318 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 10:55:02.774579 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 10:55:02.778054 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 10:55:02.784485 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 10:55:02.787781 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 10:55:02.791259 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4459 10:55:02.798158 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 10:55:02.801022 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 10:55:02.804428 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 10:55:02.811023 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 10:55:02.814522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 10:55:02.817791 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 10:55:02.824057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 10:55:02.827392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 10:55:02.830870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 10:55:02.837545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 10:55:02.841249 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 10:55:02.844444 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 10:55:02.848058 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 10:55:02.854249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 10:55:02.857462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 10:55:02.861424 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4475 10:55:02.867288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 10:55:02.870471 Total UI for P1: 0, mck2ui 16
4477 10:55:02.874228 best dqsien dly found for B0: ( 0, 13, 12)
4478 10:55:02.877327 Total UI for P1: 0, mck2ui 16
4479 10:55:02.881117 best dqsien dly found for B1: ( 0, 13, 14)
4480 10:55:02.884036 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4481 10:55:02.887078 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4482 10:55:02.887160
4483 10:55:02.890381 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4484 10:55:02.894074 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4485 10:55:02.897186 [Gating] SW calibration Done
4486 10:55:02.897274 ==
4487 10:55:02.900839 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 10:55:02.903604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 10:55:02.903687 ==
4490 10:55:02.907499 RX Vref Scan: 0
4491 10:55:02.907580
4492 10:55:02.910363 RX Vref 0 -> 0, step: 1
4493 10:55:02.910444
4494 10:55:02.910509 RX Delay -230 -> 252, step: 16
4495 10:55:02.917111 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4496 10:55:02.920366 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4497 10:55:02.923638 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4498 10:55:02.927094 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4499 10:55:02.934079 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4500 10:55:02.936839 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4501 10:55:02.940882 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4502 10:55:02.943334 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4503 10:55:02.950059 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4504 10:55:02.953111 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4505 10:55:02.956860 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4506 10:55:02.960241 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4507 10:55:02.966689 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4508 10:55:02.970238 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4509 10:55:02.973142 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4510 10:55:02.976596 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4511 10:55:02.976678 ==
4512 10:55:02.980185 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 10:55:02.986279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 10:55:02.986368 ==
4515 10:55:02.986434 DQS Delay:
4516 10:55:02.989575 DQS0 = 0, DQS1 = 0
4517 10:55:02.989657 DQM Delay:
4518 10:55:02.989722 DQM0 = 44, DQM1 = 36
4519 10:55:02.992807 DQ Delay:
4520 10:55:02.996495 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4521 10:55:02.999511 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4522 10:55:03.003302 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4523 10:55:03.006037 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4524 10:55:03.006119
4525 10:55:03.006183
4526 10:55:03.006243 ==
4527 10:55:03.009288 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 10:55:03.013256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 10:55:03.013339 ==
4530 10:55:03.013404
4531 10:55:03.013464
4532 10:55:03.016364 TX Vref Scan disable
4533 10:55:03.019673 == TX Byte 0 ==
4534 10:55:03.023061 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4535 10:55:03.026205 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4536 10:55:03.029364 == TX Byte 1 ==
4537 10:55:03.032763 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4538 10:55:03.035918 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4539 10:55:03.036001 ==
4540 10:55:03.039644 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 10:55:03.042744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 10:55:03.045971 ==
4543 10:55:03.046054
4544 10:55:03.046119
4545 10:55:03.046179 TX Vref Scan disable
4546 10:55:03.050574 == TX Byte 0 ==
4547 10:55:03.053002 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4548 10:55:03.060056 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4549 10:55:03.060141 == TX Byte 1 ==
4550 10:55:03.063156 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4551 10:55:03.069632 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4552 10:55:03.069717
4553 10:55:03.069782 [DATLAT]
4554 10:55:03.069841 Freq=600, CH1 RK0
4555 10:55:03.069901
4556 10:55:03.073096 DATLAT Default: 0x9
4557 10:55:03.073178 0, 0xFFFF, sum = 0
4558 10:55:03.076259 1, 0xFFFF, sum = 0
4559 10:55:03.076344 2, 0xFFFF, sum = 0
4560 10:55:03.079902 3, 0xFFFF, sum = 0
4561 10:55:03.082941 4, 0xFFFF, sum = 0
4562 10:55:03.083025 5, 0xFFFF, sum = 0
4563 10:55:03.086333 6, 0xFFFF, sum = 0
4564 10:55:03.086421 7, 0xFFFF, sum = 0
4565 10:55:03.089363 8, 0x0, sum = 1
4566 10:55:03.089447 9, 0x0, sum = 2
4567 10:55:03.089514 10, 0x0, sum = 3
4568 10:55:03.093010 11, 0x0, sum = 4
4569 10:55:03.093093 best_step = 9
4570 10:55:03.093159
4571 10:55:03.093218 ==
4572 10:55:03.095953 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 10:55:03.102823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 10:55:03.102907 ==
4575 10:55:03.102973 RX Vref Scan: 1
4576 10:55:03.103036
4577 10:55:03.105861 RX Vref 0 -> 0, step: 1
4578 10:55:03.105943
4579 10:55:03.109431 RX Delay -195 -> 252, step: 8
4580 10:55:03.109514
4581 10:55:03.112833 Set Vref, RX VrefLevel [Byte0]: 57
4582 10:55:03.116051 [Byte1]: 54
4583 10:55:03.116134
4584 10:55:03.119632 Final RX Vref Byte 0 = 57 to rank0
4585 10:55:03.122641 Final RX Vref Byte 1 = 54 to rank0
4586 10:55:03.126211 Final RX Vref Byte 0 = 57 to rank1
4587 10:55:03.129794 Final RX Vref Byte 1 = 54 to rank1==
4588 10:55:03.132645 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 10:55:03.136108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 10:55:03.136191 ==
4591 10:55:03.139376 DQS Delay:
4592 10:55:03.139474 DQS0 = 0, DQS1 = 0
4593 10:55:03.142612 DQM Delay:
4594 10:55:03.142694 DQM0 = 40, DQM1 = 33
4595 10:55:03.142760 DQ Delay:
4596 10:55:03.145761 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4597 10:55:03.149215 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4598 10:55:03.152190 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4599 10:55:03.155742 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4600 10:55:03.155825
4601 10:55:03.155890
4602 10:55:03.165751 [DQSOSCAuto] RK0, (LSB)MR18= 0x440b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4603 10:55:03.169314 CH1 RK0: MR19=808, MR18=440B
4604 10:55:03.175858 CH1_RK0: MR19=0x808, MR18=0x440B, DQSOSC=396, MR23=63, INC=167, DEC=111
4605 10:55:03.175943
4606 10:55:03.179011 ----->DramcWriteLeveling(PI) begin...
4607 10:55:03.179095 ==
4608 10:55:03.182364 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 10:55:03.185454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 10:55:03.185538 ==
4611 10:55:03.188645 Write leveling (Byte 0): 31 => 31
4612 10:55:03.192363 Write leveling (Byte 1): 30 => 30
4613 10:55:03.195627 DramcWriteLeveling(PI) end<-----
4614 10:55:03.195711
4615 10:55:03.195777 ==
4616 10:55:03.199021 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 10:55:03.202033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 10:55:03.202117 ==
4619 10:55:03.205469 [Gating] SW mode calibration
4620 10:55:03.212745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4621 10:55:03.219335 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4622 10:55:03.222163 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4623 10:55:03.225667 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 10:55:03.232760 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4625 10:55:03.235328 0 9 12 | B1->B0 | 3131 2d2d | 0 1 | (0 0) (1 0)
4626 10:55:03.239262 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4627 10:55:03.245981 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 10:55:03.248993 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4629 10:55:03.252960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 10:55:03.255711 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 10:55:03.262562 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 10:55:03.265592 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4633 10:55:03.268877 0 10 12 | B1->B0 | 3333 3c3c | 0 0 | (0 0) (0 0)
4634 10:55:03.275657 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 10:55:03.279279 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 10:55:03.282001 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 10:55:03.288511 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 10:55:03.291958 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 10:55:03.295632 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 10:55:03.301713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4641 10:55:03.305534 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 10:55:03.308657 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 10:55:03.315676 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 10:55:03.318613 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 10:55:03.322509 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 10:55:03.328898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 10:55:03.331821 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 10:55:03.335247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 10:55:03.342391 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 10:55:03.345072 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 10:55:03.348329 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 10:55:03.355014 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 10:55:03.358009 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 10:55:03.361782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 10:55:03.368253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 10:55:03.371565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4657 10:55:03.374913 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4658 10:55:03.381551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 10:55:03.381637 Total UI for P1: 0, mck2ui 16
4660 10:55:03.387921 best dqsien dly found for B0: ( 0, 13, 10)
4661 10:55:03.388007 Total UI for P1: 0, mck2ui 16
4662 10:55:03.395504 best dqsien dly found for B1: ( 0, 13, 14)
4663 10:55:03.398365 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4664 10:55:03.401369 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4665 10:55:03.401454
4666 10:55:03.404455 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4667 10:55:03.407977 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4668 10:55:03.411039 [Gating] SW calibration Done
4669 10:55:03.411124 ==
4670 10:55:03.414272 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 10:55:03.417786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 10:55:03.417873 ==
4673 10:55:03.420975 RX Vref Scan: 0
4674 10:55:03.421058
4675 10:55:03.421125 RX Vref 0 -> 0, step: 1
4676 10:55:03.421188
4677 10:55:03.424747 RX Delay -230 -> 252, step: 16
4678 10:55:03.431013 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4679 10:55:03.434323 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4680 10:55:03.437458 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4681 10:55:03.441325 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4682 10:55:03.447777 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4683 10:55:03.451263 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4684 10:55:03.454098 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4685 10:55:03.457836 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4686 10:55:03.461000 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4687 10:55:03.467542 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4688 10:55:03.471112 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4689 10:55:03.474320 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4690 10:55:03.477463 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4691 10:55:03.484496 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4692 10:55:03.487621 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4693 10:55:03.490892 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4694 10:55:03.490976 ==
4695 10:55:03.494053 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 10:55:03.497606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 10:55:03.497691 ==
4698 10:55:03.501111 DQS Delay:
4699 10:55:03.501193 DQS0 = 0, DQS1 = 0
4700 10:55:03.504301 DQM Delay:
4701 10:55:03.504387 DQM0 = 40, DQM1 = 37
4702 10:55:03.504454 DQ Delay:
4703 10:55:03.507109 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4704 10:55:03.510904 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4705 10:55:03.514186 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4706 10:55:03.517418 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4707 10:55:03.517503
4708 10:55:03.517569
4709 10:55:03.520915 ==
4710 10:55:03.523815 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 10:55:03.527135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 10:55:03.527220 ==
4713 10:55:03.527285
4714 10:55:03.527353
4715 10:55:03.530617 TX Vref Scan disable
4716 10:55:03.530700 == TX Byte 0 ==
4717 10:55:03.537643 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4718 10:55:03.540549 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4719 10:55:03.540633 == TX Byte 1 ==
4720 10:55:03.547479 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 10:55:03.550153 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 10:55:03.550264 ==
4723 10:55:03.553572 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 10:55:03.557021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 10:55:03.557105 ==
4726 10:55:03.557171
4727 10:55:03.557233
4728 10:55:03.560667 TX Vref Scan disable
4729 10:55:03.563601 == TX Byte 0 ==
4730 10:55:03.566983 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4731 10:55:03.570025 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4732 10:55:03.573844 == TX Byte 1 ==
4733 10:55:03.577230 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4734 10:55:03.580024 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4735 10:55:03.580108
4736 10:55:03.583516 [DATLAT]
4737 10:55:03.583599 Freq=600, CH1 RK1
4738 10:55:03.583666
4739 10:55:03.586768 DATLAT Default: 0x9
4740 10:55:03.586851 0, 0xFFFF, sum = 0
4741 10:55:03.590281 1, 0xFFFF, sum = 0
4742 10:55:03.590366 2, 0xFFFF, sum = 0
4743 10:55:03.593471 3, 0xFFFF, sum = 0
4744 10:55:03.593554 4, 0xFFFF, sum = 0
4745 10:55:03.596903 5, 0xFFFF, sum = 0
4746 10:55:03.596987 6, 0xFFFF, sum = 0
4747 10:55:03.600176 7, 0xFFFF, sum = 0
4748 10:55:03.600260 8, 0x0, sum = 1
4749 10:55:03.603217 9, 0x0, sum = 2
4750 10:55:03.603301 10, 0x0, sum = 3
4751 10:55:03.607093 11, 0x0, sum = 4
4752 10:55:03.607177 best_step = 9
4753 10:55:03.607242
4754 10:55:03.607303 ==
4755 10:55:03.610264 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 10:55:03.617190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 10:55:03.617272 ==
4758 10:55:03.617337 RX Vref Scan: 0
4759 10:55:03.617396
4760 10:55:03.620557 RX Vref 0 -> 0, step: 1
4761 10:55:03.620638
4762 10:55:03.623277 RX Delay -195 -> 252, step: 8
4763 10:55:03.626739 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4764 10:55:03.633059 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4765 10:55:03.636320 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4766 10:55:03.639758 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4767 10:55:03.643024 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4768 10:55:03.646270 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4769 10:55:03.653174 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4770 10:55:03.656291 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4771 10:55:03.659668 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4772 10:55:03.662948 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4773 10:55:03.669729 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4774 10:55:03.672783 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4775 10:55:03.676839 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4776 10:55:03.679827 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4777 10:55:03.686085 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4778 10:55:03.689598 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4779 10:55:03.689704 ==
4780 10:55:03.692941 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 10:55:03.696211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 10:55:03.696297 ==
4783 10:55:03.699285 DQS Delay:
4784 10:55:03.699396 DQS0 = 0, DQS1 = 0
4785 10:55:03.699491 DQM Delay:
4786 10:55:03.702952 DQM0 = 38, DQM1 = 33
4787 10:55:03.703052 DQ Delay:
4788 10:55:03.706040 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4789 10:55:03.709627 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4790 10:55:03.712531 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4791 10:55:03.716265 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4792 10:55:03.716368
4793 10:55:03.716435
4794 10:55:03.725852 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
4795 10:55:03.725955 CH1 RK1: MR19=808, MR18=2E3E
4796 10:55:03.733068 CH1_RK1: MR19=0x808, MR18=0x2E3E, DQSOSC=398, MR23=63, INC=165, DEC=110
4797 10:55:03.736123 [RxdqsGatingPostProcess] freq 600
4798 10:55:03.742259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4799 10:55:03.745831 Pre-setting of DQS Precalculation
4800 10:55:03.748873 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4801 10:55:03.759015 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4802 10:55:03.765741 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4803 10:55:03.765888
4804 10:55:03.765965
4805 10:55:03.768662 [Calibration Summary] 1200 Mbps
4806 10:55:03.768757 CH 0, Rank 0
4807 10:55:03.772291 SW Impedance : PASS
4808 10:55:03.772399 DUTY Scan : NO K
4809 10:55:03.775391 ZQ Calibration : PASS
4810 10:55:03.778644 Jitter Meter : NO K
4811 10:55:03.778733 CBT Training : PASS
4812 10:55:03.781772 Write leveling : PASS
4813 10:55:03.785073 RX DQS gating : PASS
4814 10:55:03.785172 RX DQ/DQS(RDDQC) : PASS
4815 10:55:03.788751 TX DQ/DQS : PASS
4816 10:55:03.791677 RX DATLAT : PASS
4817 10:55:03.791774 RX DQ/DQS(Engine): PASS
4818 10:55:03.795271 TX OE : NO K
4819 10:55:03.795428 All Pass.
4820 10:55:03.795498
4821 10:55:03.798359 CH 0, Rank 1
4822 10:55:03.798447 SW Impedance : PASS
4823 10:55:03.801653 DUTY Scan : NO K
4824 10:55:03.801744 ZQ Calibration : PASS
4825 10:55:03.805420 Jitter Meter : NO K
4826 10:55:03.808849 CBT Training : PASS
4827 10:55:03.808959 Write leveling : PASS
4828 10:55:03.812154 RX DQS gating : PASS
4829 10:55:03.815264 RX DQ/DQS(RDDQC) : PASS
4830 10:55:03.815387 TX DQ/DQS : PASS
4831 10:55:03.818638 RX DATLAT : PASS
4832 10:55:03.821676 RX DQ/DQS(Engine): PASS
4833 10:55:03.821765 TX OE : NO K
4834 10:55:03.825346 All Pass.
4835 10:55:03.825434
4836 10:55:03.825500 CH 1, Rank 0
4837 10:55:03.828238 SW Impedance : PASS
4838 10:55:03.828325 DUTY Scan : NO K
4839 10:55:03.831834 ZQ Calibration : PASS
4840 10:55:03.835449 Jitter Meter : NO K
4841 10:55:03.835561 CBT Training : PASS
4842 10:55:03.838388 Write leveling : PASS
4843 10:55:03.841763 RX DQS gating : PASS
4844 10:55:03.841856 RX DQ/DQS(RDDQC) : PASS
4845 10:55:03.845573 TX DQ/DQS : PASS
4846 10:55:03.845659 RX DATLAT : PASS
4847 10:55:03.848456 RX DQ/DQS(Engine): PASS
4848 10:55:03.852192 TX OE : NO K
4849 10:55:03.852277 All Pass.
4850 10:55:03.852344
4851 10:55:03.852408 CH 1, Rank 1
4852 10:55:03.855278 SW Impedance : PASS
4853 10:55:03.858968 DUTY Scan : NO K
4854 10:55:03.859055 ZQ Calibration : PASS
4855 10:55:03.861978 Jitter Meter : NO K
4856 10:55:03.865116 CBT Training : PASS
4857 10:55:03.865216 Write leveling : PASS
4858 10:55:03.868619 RX DQS gating : PASS
4859 10:55:03.871708 RX DQ/DQS(RDDQC) : PASS
4860 10:55:03.871799 TX DQ/DQS : PASS
4861 10:55:03.874952 RX DATLAT : PASS
4862 10:55:03.878497 RX DQ/DQS(Engine): PASS
4863 10:55:03.878584 TX OE : NO K
4864 10:55:03.881960 All Pass.
4865 10:55:03.882044
4866 10:55:03.882109 DramC Write-DBI off
4867 10:55:03.884975 PER_BANK_REFRESH: Hybrid Mode
4868 10:55:03.885058 TX_TRACKING: ON
4869 10:55:03.895066 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4870 10:55:03.898771 [FAST_K] Save calibration result to emmc
4871 10:55:03.901821 dramc_set_vcore_voltage set vcore to 662500
4872 10:55:03.905408 Read voltage for 933, 3
4873 10:55:03.905494 Vio18 = 0
4874 10:55:03.908448 Vcore = 662500
4875 10:55:03.908537 Vdram = 0
4876 10:55:03.908604 Vddq = 0
4877 10:55:03.908665 Vmddr = 0
4878 10:55:03.914963 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4879 10:55:03.921751 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4880 10:55:03.921846 MEM_TYPE=3, freq_sel=17
4881 10:55:03.925080 sv_algorithm_assistance_LP4_1600
4882 10:55:03.928048 ============ PULL DRAM RESETB DOWN ============
4883 10:55:03.934893 ========== PULL DRAM RESETB DOWN end =========
4884 10:55:03.938067 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4885 10:55:03.941767 ===================================
4886 10:55:03.945308 LPDDR4 DRAM CONFIGURATION
4887 10:55:03.948375 ===================================
4888 10:55:03.948462 EX_ROW_EN[0] = 0x0
4889 10:55:03.951797 EX_ROW_EN[1] = 0x0
4890 10:55:03.951881 LP4Y_EN = 0x0
4891 10:55:03.954941 WORK_FSP = 0x0
4892 10:55:03.955032 WL = 0x3
4893 10:55:03.958175 RL = 0x3
4894 10:55:03.961781 BL = 0x2
4895 10:55:03.961872 RPST = 0x0
4896 10:55:03.964708 RD_PRE = 0x0
4897 10:55:03.964791 WR_PRE = 0x1
4898 10:55:03.968534 WR_PST = 0x0
4899 10:55:03.968621 DBI_WR = 0x0
4900 10:55:03.971595 DBI_RD = 0x0
4901 10:55:03.971680 OTF = 0x1
4902 10:55:03.974681 ===================================
4903 10:55:03.978072 ===================================
4904 10:55:03.981493 ANA top config
4905 10:55:03.981579 ===================================
4906 10:55:03.985584 DLL_ASYNC_EN = 0
4907 10:55:03.988290 ALL_SLAVE_EN = 1
4908 10:55:03.991652 NEW_RANK_MODE = 1
4909 10:55:03.994639 DLL_IDLE_MODE = 1
4910 10:55:03.994726 LP45_APHY_COMB_EN = 1
4911 10:55:03.997937 TX_ODT_DIS = 1
4912 10:55:04.001608 NEW_8X_MODE = 1
4913 10:55:04.004798 ===================================
4914 10:55:04.007915 ===================================
4915 10:55:04.011432 data_rate = 1866
4916 10:55:04.014626 CKR = 1
4917 10:55:04.017796 DQ_P2S_RATIO = 8
4918 10:55:04.017880 ===================================
4919 10:55:04.021524 CA_P2S_RATIO = 8
4920 10:55:04.024325 DQ_CA_OPEN = 0
4921 10:55:04.027904 DQ_SEMI_OPEN = 0
4922 10:55:04.031062 CA_SEMI_OPEN = 0
4923 10:55:04.034255 CA_FULL_RATE = 0
4924 10:55:04.037794 DQ_CKDIV4_EN = 1
4925 10:55:04.037878 CA_CKDIV4_EN = 1
4926 10:55:04.041516 CA_PREDIV_EN = 0
4927 10:55:04.044357 PH8_DLY = 0
4928 10:55:04.048080 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4929 10:55:04.051307 DQ_AAMCK_DIV = 4
4930 10:55:04.054553 CA_AAMCK_DIV = 4
4931 10:55:04.054637 CA_ADMCK_DIV = 4
4932 10:55:04.057952 DQ_TRACK_CA_EN = 0
4933 10:55:04.060763 CA_PICK = 933
4934 10:55:04.064447 CA_MCKIO = 933
4935 10:55:04.067809 MCKIO_SEMI = 0
4936 10:55:04.070713 PLL_FREQ = 3732
4937 10:55:04.074330 DQ_UI_PI_RATIO = 32
4938 10:55:04.074411 CA_UI_PI_RATIO = 0
4939 10:55:04.077627 ===================================
4940 10:55:04.080950 ===================================
4941 10:55:04.084154 memory_type:LPDDR4
4942 10:55:04.087633 GP_NUM : 10
4943 10:55:04.087716 SRAM_EN : 1
4944 10:55:04.090840 MD32_EN : 0
4945 10:55:04.093852 ===================================
4946 10:55:04.097376 [ANA_INIT] >>>>>>>>>>>>>>
4947 10:55:04.100553 <<<<<< [CONFIGURE PHASE]: ANA_TX
4948 10:55:04.104323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4949 10:55:04.107607 ===================================
4950 10:55:04.107690 data_rate = 1866,PCW = 0X8f00
4951 10:55:04.110673 ===================================
4952 10:55:04.114112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4953 10:55:04.120861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 10:55:04.127029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 10:55:04.130539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4956 10:55:04.133729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4957 10:55:04.137410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4958 10:55:04.140991 [ANA_INIT] flow start
4959 10:55:04.141097 [ANA_INIT] PLL >>>>>>>>
4960 10:55:04.143900 [ANA_INIT] PLL <<<<<<<<
4961 10:55:04.147090 [ANA_INIT] MIDPI >>>>>>>>
4962 10:55:04.150161 [ANA_INIT] MIDPI <<<<<<<<
4963 10:55:04.150249 [ANA_INIT] DLL >>>>>>>>
4964 10:55:04.154301 [ANA_INIT] flow end
4965 10:55:04.156742 ============ LP4 DIFF to SE enter ============
4966 10:55:04.160993 ============ LP4 DIFF to SE exit ============
4967 10:55:04.164130 [ANA_INIT] <<<<<<<<<<<<<
4968 10:55:04.167362 [Flow] Enable top DCM control >>>>>
4969 10:55:04.170582 [Flow] Enable top DCM control <<<<<
4970 10:55:04.173974 Enable DLL master slave shuffle
4971 10:55:04.180151 ==============================================================
4972 10:55:04.180265 Gating Mode config
4973 10:55:04.186836 ==============================================================
4974 10:55:04.186964 Config description:
4975 10:55:04.197170 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4976 10:55:04.203526 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4977 10:55:04.209799 SELPH_MODE 0: By rank 1: By Phase
4978 10:55:04.213425 ==============================================================
4979 10:55:04.216518 GAT_TRACK_EN = 1
4980 10:55:04.219982 RX_GATING_MODE = 2
4981 10:55:04.223593 RX_GATING_TRACK_MODE = 2
4982 10:55:04.226768 SELPH_MODE = 1
4983 10:55:04.229881 PICG_EARLY_EN = 1
4984 10:55:04.233130 VALID_LAT_VALUE = 1
4985 10:55:04.240019 ==============================================================
4986 10:55:04.243254 Enter into Gating configuration >>>>
4987 10:55:04.246353 Exit from Gating configuration <<<<
4988 10:55:04.246445 Enter into DVFS_PRE_config >>>>>
4989 10:55:04.259496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4990 10:55:04.263008 Exit from DVFS_PRE_config <<<<<
4991 10:55:04.266625 Enter into PICG configuration >>>>
4992 10:55:04.269477 Exit from PICG configuration <<<<
4993 10:55:04.269567 [RX_INPUT] configuration >>>>>
4994 10:55:04.273029 [RX_INPUT] configuration <<<<<
4995 10:55:04.279324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4996 10:55:04.282872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4997 10:55:04.289568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 10:55:04.296622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 10:55:04.302772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 10:55:04.309776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 10:55:04.313023 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5002 10:55:04.316118 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5003 10:55:04.322854 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5004 10:55:04.326020 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5005 10:55:04.329311 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5006 10:55:04.332647 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 10:55:04.336234 ===================================
5008 10:55:04.339242 LPDDR4 DRAM CONFIGURATION
5009 10:55:04.342776 ===================================
5010 10:55:04.345896 EX_ROW_EN[0] = 0x0
5011 10:55:04.345994 EX_ROW_EN[1] = 0x0
5012 10:55:04.349181 LP4Y_EN = 0x0
5013 10:55:04.349269 WORK_FSP = 0x0
5014 10:55:04.352690 WL = 0x3
5015 10:55:04.352778 RL = 0x3
5016 10:55:04.355836 BL = 0x2
5017 10:55:04.355924 RPST = 0x0
5018 10:55:04.359324 RD_PRE = 0x0
5019 10:55:04.362512 WR_PRE = 0x1
5020 10:55:04.362607 WR_PST = 0x0
5021 10:55:04.365656 DBI_WR = 0x0
5022 10:55:04.365748 DBI_RD = 0x0
5023 10:55:04.368982 OTF = 0x1
5024 10:55:04.372378 ===================================
5025 10:55:04.375577 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5026 10:55:04.379089 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5027 10:55:04.382670 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 10:55:04.385759 ===================================
5029 10:55:04.389050 LPDDR4 DRAM CONFIGURATION
5030 10:55:04.392865 ===================================
5031 10:55:04.395580 EX_ROW_EN[0] = 0x10
5032 10:55:04.395689 EX_ROW_EN[1] = 0x0
5033 10:55:04.399004 LP4Y_EN = 0x0
5034 10:55:04.399102 WORK_FSP = 0x0
5035 10:55:04.402064 WL = 0x3
5036 10:55:04.402162 RL = 0x3
5037 10:55:04.405630 BL = 0x2
5038 10:55:04.405731 RPST = 0x0
5039 10:55:04.408648 RD_PRE = 0x0
5040 10:55:04.412323 WR_PRE = 0x1
5041 10:55:04.412435 WR_PST = 0x0
5042 10:55:04.415315 DBI_WR = 0x0
5043 10:55:04.415454 DBI_RD = 0x0
5044 10:55:04.418701 OTF = 0x1
5045 10:55:04.422531 ===================================
5046 10:55:04.425056 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5047 10:55:04.431030 nWR fixed to 30
5048 10:55:04.433760 [ModeRegInit_LP4] CH0 RK0
5049 10:55:04.433871 [ModeRegInit_LP4] CH0 RK1
5050 10:55:04.437094 [ModeRegInit_LP4] CH1 RK0
5051 10:55:04.440896 [ModeRegInit_LP4] CH1 RK1
5052 10:55:04.441004 match AC timing 9
5053 10:55:04.447066 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5054 10:55:04.450440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5055 10:55:04.453715 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5056 10:55:04.460219 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5057 10:55:04.464143 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5058 10:55:04.464263 ==
5059 10:55:04.467044 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 10:55:04.470259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 10:55:04.470364 ==
5062 10:55:04.477032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 10:55:04.483634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5064 10:55:04.487191 [CA 0] Center 38 (8~69) winsize 62
5065 10:55:04.490086 [CA 1] Center 38 (7~69) winsize 63
5066 10:55:04.493695 [CA 2] Center 35 (5~66) winsize 62
5067 10:55:04.497123 [CA 3] Center 34 (4~65) winsize 62
5068 10:55:04.500196 [CA 4] Center 34 (4~65) winsize 62
5069 10:55:04.503304 [CA 5] Center 34 (4~64) winsize 61
5070 10:55:04.503501
5071 10:55:04.507363 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5072 10:55:04.507505
5073 10:55:04.510580 [CATrainingPosCal] consider 1 rank data
5074 10:55:04.513429 u2DelayCellTimex100 = 270/100 ps
5075 10:55:04.516739 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5076 10:55:04.520046 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5077 10:55:04.523218 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5078 10:55:04.526659 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5079 10:55:04.530070 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5080 10:55:04.536356 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 10:55:04.536517
5082 10:55:04.540019 CA PerBit enable=1, Macro0, CA PI delay=34
5083 10:55:04.540129
5084 10:55:04.543249 [CBTSetCACLKResult] CA Dly = 34
5085 10:55:04.543364 CS Dly: 6 (0~37)
5086 10:55:04.543447 ==
5087 10:55:04.546497 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 10:55:04.550207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 10:55:04.553500 ==
5090 10:55:04.556552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 10:55:04.563178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 10:55:04.566258 [CA 0] Center 38 (7~69) winsize 63
5093 10:55:04.569895 [CA 1] Center 38 (8~69) winsize 62
5094 10:55:04.573291 [CA 2] Center 35 (5~66) winsize 62
5095 10:55:04.576124 [CA 3] Center 35 (4~66) winsize 63
5096 10:55:04.580078 [CA 4] Center 33 (3~64) winsize 62
5097 10:55:04.583029 [CA 5] Center 33 (3~64) winsize 62
5098 10:55:04.583214
5099 10:55:04.586340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 10:55:04.586508
5101 10:55:04.589762 [CATrainingPosCal] consider 2 rank data
5102 10:55:04.592614 u2DelayCellTimex100 = 270/100 ps
5103 10:55:04.596311 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5104 10:55:04.599319 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5105 10:55:04.603160 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5106 10:55:04.606424 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5107 10:55:04.613221 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 10:55:04.616206 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5109 10:55:04.616405
5110 10:55:04.619458 CA PerBit enable=1, Macro0, CA PI delay=34
5111 10:55:04.619633
5112 10:55:04.623376 [CBTSetCACLKResult] CA Dly = 34
5113 10:55:04.623575 CS Dly: 7 (0~39)
5114 10:55:04.623722
5115 10:55:04.626571 ----->DramcWriteLeveling(PI) begin...
5116 10:55:04.626745 ==
5117 10:55:04.629397 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 10:55:04.636364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 10:55:04.636594 ==
5120 10:55:04.639390 Write leveling (Byte 0): 33 => 33
5121 10:55:04.639585 Write leveling (Byte 1): 28 => 28
5122 10:55:04.642781 DramcWriteLeveling(PI) end<-----
5123 10:55:04.642972
5124 10:55:04.646834 ==
5125 10:55:04.647020 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 10:55:04.652996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 10:55:04.653222 ==
5128 10:55:04.656009 [Gating] SW mode calibration
5129 10:55:04.662917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5130 10:55:04.666104 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5131 10:55:04.672793 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5132 10:55:04.676474 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 10:55:04.679594 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 10:55:04.685915 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 10:55:04.689666 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 10:55:04.692783 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 10:55:04.699695 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 10:55:04.703298 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5139 10:55:04.706214 0 15 0 | B1->B0 | 3232 2929 | 1 0 | (1 0) (0 0)
5140 10:55:04.712558 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5141 10:55:04.716354 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 10:55:04.719338 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 10:55:04.725813 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 10:55:04.729359 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 10:55:04.732746 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 10:55:04.738836 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5147 10:55:04.742342 1 0 0 | B1->B0 | 3232 4141 | 0 0 | (0 0) (1 1)
5148 10:55:04.745621 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5149 10:55:04.748984 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 10:55:04.755744 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 10:55:04.759246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 10:55:04.762958 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 10:55:04.769569 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 10:55:04.772507 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5155 10:55:04.775557 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 10:55:04.782255 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 10:55:04.785733 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 10:55:04.789098 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 10:55:04.795844 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 10:55:04.798920 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 10:55:04.802167 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 10:55:04.809223 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 10:55:04.812215 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 10:55:04.815628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 10:55:04.822544 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 10:55:04.825266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 10:55:04.829069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 10:55:04.835767 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 10:55:04.839362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 10:55:04.841898 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 10:55:04.848638 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5172 10:55:04.851640 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 10:55:04.855132 Total UI for P1: 0, mck2ui 16
5174 10:55:04.858405 best dqsien dly found for B0: ( 1, 3, 0)
5175 10:55:04.862027 Total UI for P1: 0, mck2ui 16
5176 10:55:04.864944 best dqsien dly found for B1: ( 1, 3, 2)
5177 10:55:04.868575 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5178 10:55:04.871860 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5179 10:55:04.871959
5180 10:55:04.875247 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5181 10:55:04.878545 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5182 10:55:04.881891 [Gating] SW calibration Done
5183 10:55:04.881990 ==
5184 10:55:04.885039 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 10:55:04.888829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 10:55:04.888932 ==
5187 10:55:04.891591 RX Vref Scan: 0
5188 10:55:04.891679
5189 10:55:04.894669 RX Vref 0 -> 0, step: 1
5190 10:55:04.894758
5191 10:55:04.894826 RX Delay -80 -> 252, step: 8
5192 10:55:04.901432 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5193 10:55:04.904750 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5194 10:55:04.908137 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5195 10:55:04.911549 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5196 10:55:04.914356 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5197 10:55:04.921102 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5198 10:55:04.924535 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5199 10:55:04.928002 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5200 10:55:04.931215 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5201 10:55:04.934793 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5202 10:55:04.937701 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5203 10:55:04.944352 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5204 10:55:04.947717 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5205 10:55:04.951847 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5206 10:55:04.954372 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5207 10:55:04.957949 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5208 10:55:04.958064 ==
5209 10:55:04.960843 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 10:55:04.967923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 10:55:04.968074 ==
5212 10:55:04.968177 DQS Delay:
5213 10:55:04.971220 DQS0 = 0, DQS1 = 0
5214 10:55:04.971333 DQM Delay:
5215 10:55:04.971458 DQM0 = 96, DQM1 = 87
5216 10:55:04.974930 DQ Delay:
5217 10:55:04.977937 DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91
5218 10:55:04.981474 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5219 10:55:04.984214 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5220 10:55:04.987948 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5221 10:55:04.988072
5222 10:55:04.988162
5223 10:55:04.988257 ==
5224 10:55:04.991184 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 10:55:04.994601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 10:55:04.994708 ==
5227 10:55:04.994806
5228 10:55:04.994894
5229 10:55:04.997428 TX Vref Scan disable
5230 10:55:05.001129 == TX Byte 0 ==
5231 10:55:05.004213 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5232 10:55:05.007663 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5233 10:55:05.010969 == TX Byte 1 ==
5234 10:55:05.014548 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5235 10:55:05.017534 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5236 10:55:05.017648 ==
5237 10:55:05.020936 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 10:55:05.024305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 10:55:05.024419 ==
5240 10:55:05.027832
5241 10:55:05.027953
5242 10:55:05.028044 TX Vref Scan disable
5243 10:55:05.031584 == TX Byte 0 ==
5244 10:55:05.034179 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5245 10:55:05.041387 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5246 10:55:05.041532 == TX Byte 1 ==
5247 10:55:05.044216 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5248 10:55:05.051194 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5249 10:55:05.051341
5250 10:55:05.051479 [DATLAT]
5251 10:55:05.051571 Freq=933, CH0 RK0
5252 10:55:05.051661
5253 10:55:05.054220 DATLAT Default: 0xd
5254 10:55:05.054318 0, 0xFFFF, sum = 0
5255 10:55:05.057635 1, 0xFFFF, sum = 0
5256 10:55:05.057724 2, 0xFFFF, sum = 0
5257 10:55:05.061187 3, 0xFFFF, sum = 0
5258 10:55:05.064526 4, 0xFFFF, sum = 0
5259 10:55:05.064619 5, 0xFFFF, sum = 0
5260 10:55:05.067565 6, 0xFFFF, sum = 0
5261 10:55:05.067655 7, 0xFFFF, sum = 0
5262 10:55:05.071115 8, 0xFFFF, sum = 0
5263 10:55:05.071207 9, 0xFFFF, sum = 0
5264 10:55:05.074039 10, 0x0, sum = 1
5265 10:55:05.074129 11, 0x0, sum = 2
5266 10:55:05.077731 12, 0x0, sum = 3
5267 10:55:05.077829 13, 0x0, sum = 4
5268 10:55:05.077899 best_step = 11
5269 10:55:05.077962
5270 10:55:05.081521 ==
5271 10:55:05.083815 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 10:55:05.087463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 10:55:05.087553 ==
5274 10:55:05.087620 RX Vref Scan: 1
5275 10:55:05.087682
5276 10:55:05.090817 RX Vref 0 -> 0, step: 1
5277 10:55:05.090905
5278 10:55:05.094404 RX Delay -61 -> 252, step: 4
5279 10:55:05.094491
5280 10:55:05.097203 Set Vref, RX VrefLevel [Byte0]: 54
5281 10:55:05.100537 [Byte1]: 51
5282 10:55:05.100625
5283 10:55:05.104228 Final RX Vref Byte 0 = 54 to rank0
5284 10:55:05.107337 Final RX Vref Byte 1 = 51 to rank0
5285 10:55:05.110862 Final RX Vref Byte 0 = 54 to rank1
5286 10:55:05.113913 Final RX Vref Byte 1 = 51 to rank1==
5287 10:55:05.117289 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 10:55:05.120707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 10:55:05.123638 ==
5290 10:55:05.123731 DQS Delay:
5291 10:55:05.123798 DQS0 = 0, DQS1 = 0
5292 10:55:05.127048 DQM Delay:
5293 10:55:05.127131 DQM0 = 96, DQM1 = 87
5294 10:55:05.130625 DQ Delay:
5295 10:55:05.130708 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5296 10:55:05.134070 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5297 10:55:05.137020 DQ8 =78, DQ9 =74, DQ10 =92, DQ11 =80
5298 10:55:05.140823 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5299 10:55:05.140919
5300 10:55:05.143899
5301 10:55:05.150670 [DQSOSCAuto] RK0, (LSB)MR18= 0x1500, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5302 10:55:05.153861 CH0 RK0: MR19=505, MR18=1500
5303 10:55:05.160468 CH0_RK0: MR19=0x505, MR18=0x1500, DQSOSC=415, MR23=63, INC=62, DEC=41
5304 10:55:05.160587
5305 10:55:05.163928 ----->DramcWriteLeveling(PI) begin...
5306 10:55:05.164020 ==
5307 10:55:05.167125 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 10:55:05.170856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 10:55:05.170949 ==
5310 10:55:05.173976 Write leveling (Byte 0): 30 => 30
5311 10:55:05.177136 Write leveling (Byte 1): 29 => 29
5312 10:55:05.180653 DramcWriteLeveling(PI) end<-----
5313 10:55:05.180745
5314 10:55:05.180811 ==
5315 10:55:05.183988 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 10:55:05.187143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 10:55:05.187232 ==
5318 10:55:05.190515 [Gating] SW mode calibration
5319 10:55:05.197585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5320 10:55:05.203857 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5321 10:55:05.207204 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5322 10:55:05.210829 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5323 10:55:05.216996 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 10:55:05.220323 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 10:55:05.223786 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 10:55:05.230185 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 10:55:05.233790 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5328 10:55:05.237164 0 14 28 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5329 10:55:05.243642 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
5330 10:55:05.246742 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 10:55:05.250001 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 10:55:05.256648 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 10:55:05.260386 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 10:55:05.263225 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 10:55:05.270115 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 10:55:05.273712 0 15 28 | B1->B0 | 2525 3333 | 1 0 | (0 0) (1 1)
5337 10:55:05.276883 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
5338 10:55:05.283104 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 10:55:05.287057 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 10:55:05.289668 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 10:55:05.296833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 10:55:05.299815 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 10:55:05.303689 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 10:55:05.309962 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 10:55:05.313782 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 10:55:05.316298 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5347 10:55:05.319930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 10:55:05.326618 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 10:55:05.330420 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 10:55:05.333108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 10:55:05.339606 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 10:55:05.342870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 10:55:05.346323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 10:55:05.352856 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 10:55:05.356413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 10:55:05.359384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 10:55:05.366396 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 10:55:05.369380 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 10:55:05.372744 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5360 10:55:05.379630 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5361 10:55:05.382588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5362 10:55:05.385907 Total UI for P1: 0, mck2ui 16
5363 10:55:05.389276 best dqsien dly found for B0: ( 1, 2, 26)
5364 10:55:05.392570 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 10:55:05.396099 Total UI for P1: 0, mck2ui 16
5366 10:55:05.399197 best dqsien dly found for B1: ( 1, 3, 0)
5367 10:55:05.402964 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5368 10:55:05.406038 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5369 10:55:05.406135
5370 10:55:05.412775 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5371 10:55:05.416641 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5372 10:55:05.416739 [Gating] SW calibration Done
5373 10:55:05.419568 ==
5374 10:55:05.423336 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 10:55:05.426017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 10:55:05.426106 ==
5377 10:55:05.426171 RX Vref Scan: 0
5378 10:55:05.426233
5379 10:55:05.429400 RX Vref 0 -> 0, step: 1
5380 10:55:05.429482
5381 10:55:05.432827 RX Delay -80 -> 252, step: 8
5382 10:55:05.435701 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5383 10:55:05.439191 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5384 10:55:05.442538 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5385 10:55:05.449777 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5386 10:55:05.452692 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5387 10:55:05.455925 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5388 10:55:05.458823 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5389 10:55:05.462633 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5390 10:55:05.465744 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5391 10:55:05.472741 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5392 10:55:05.476057 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5393 10:55:05.478952 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5394 10:55:05.482157 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5395 10:55:05.485844 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5396 10:55:05.488852 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5397 10:55:05.495666 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5398 10:55:05.495792 ==
5399 10:55:05.498795 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 10:55:05.502053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 10:55:05.502153 ==
5402 10:55:05.502243 DQS Delay:
5403 10:55:05.505049 DQS0 = 0, DQS1 = 0
5404 10:55:05.505137 DQM Delay:
5405 10:55:05.508687 DQM0 = 98, DQM1 = 88
5406 10:55:05.508782 DQ Delay:
5407 10:55:05.511913 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5408 10:55:05.515233 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5409 10:55:05.518800 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5410 10:55:05.522278 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5411 10:55:05.522381
5412 10:55:05.522468
5413 10:55:05.522568 ==
5414 10:55:05.524951 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 10:55:05.529206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 10:55:05.531921 ==
5417 10:55:05.532019
5418 10:55:05.532107
5419 10:55:05.532189 TX Vref Scan disable
5420 10:55:05.534972 == TX Byte 0 ==
5421 10:55:05.538500 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5422 10:55:05.541515 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5423 10:55:05.545441 == TX Byte 1 ==
5424 10:55:05.548306 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5425 10:55:05.551718 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5426 10:55:05.554805 ==
5427 10:55:05.558711 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 10:55:05.561787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 10:55:05.561882 ==
5430 10:55:05.561948
5431 10:55:05.562008
5432 10:55:05.565229 TX Vref Scan disable
5433 10:55:05.565325 == TX Byte 0 ==
5434 10:55:05.571283 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5435 10:55:05.574591 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5436 10:55:05.574688 == TX Byte 1 ==
5437 10:55:05.581799 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5438 10:55:05.585977 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5439 10:55:05.586075
5440 10:55:05.586142 [DATLAT]
5441 10:55:05.588070 Freq=933, CH0 RK1
5442 10:55:05.588154
5443 10:55:05.588219 DATLAT Default: 0xb
5444 10:55:05.591397 0, 0xFFFF, sum = 0
5445 10:55:05.591483 1, 0xFFFF, sum = 0
5446 10:55:05.595185 2, 0xFFFF, sum = 0
5447 10:55:05.595276 3, 0xFFFF, sum = 0
5448 10:55:05.597998 4, 0xFFFF, sum = 0
5449 10:55:05.598090 5, 0xFFFF, sum = 0
5450 10:55:05.601902 6, 0xFFFF, sum = 0
5451 10:55:05.601994 7, 0xFFFF, sum = 0
5452 10:55:05.604594 8, 0xFFFF, sum = 0
5453 10:55:05.608267 9, 0xFFFF, sum = 0
5454 10:55:05.608365 10, 0x0, sum = 1
5455 10:55:05.608436 11, 0x0, sum = 2
5456 10:55:05.611292 12, 0x0, sum = 3
5457 10:55:05.611433 13, 0x0, sum = 4
5458 10:55:05.614505 best_step = 11
5459 10:55:05.614590
5460 10:55:05.614655 ==
5461 10:55:05.618290 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 10:55:05.621712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 10:55:05.621801 ==
5464 10:55:05.624877 RX Vref Scan: 0
5465 10:55:05.624962
5466 10:55:05.625027 RX Vref 0 -> 0, step: 1
5467 10:55:05.625089
5468 10:55:05.627855 RX Delay -61 -> 252, step: 4
5469 10:55:05.635182 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5470 10:55:05.638689 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5471 10:55:05.641661 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5472 10:55:05.645402 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5473 10:55:05.648348 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5474 10:55:05.651692 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5475 10:55:05.658545 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5476 10:55:05.661756 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5477 10:55:05.665207 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5478 10:55:05.668573 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5479 10:55:05.672041 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5480 10:55:05.678220 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5481 10:55:05.681665 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5482 10:55:05.685209 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5483 10:55:05.688651 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5484 10:55:05.691760 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5485 10:55:05.691853 ==
5486 10:55:05.695236 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 10:55:05.701624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 10:55:05.701740 ==
5489 10:55:05.701812 DQS Delay:
5490 10:55:05.701875 DQS0 = 0, DQS1 = 0
5491 10:55:05.704842 DQM Delay:
5492 10:55:05.704928 DQM0 = 95, DQM1 = 87
5493 10:55:05.708023 DQ Delay:
5494 10:55:05.711607 DQ0 =96, DQ1 =94, DQ2 =92, DQ3 =94
5495 10:55:05.714665 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104
5496 10:55:05.718307 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5497 10:55:05.721424 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5498 10:55:05.721514
5499 10:55:05.721581
5500 10:55:05.728058 [DQSOSCAuto] RK1, (LSB)MR18= 0x1502, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 415 ps
5501 10:55:05.731445 CH0 RK1: MR19=505, MR18=1502
5502 10:55:05.738142 CH0_RK1: MR19=0x505, MR18=0x1502, DQSOSC=415, MR23=63, INC=62, DEC=41
5503 10:55:05.741576 [RxdqsGatingPostProcess] freq 933
5504 10:55:05.744845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5505 10:55:05.748280 best DQS0 dly(2T, 0.5T) = (0, 11)
5506 10:55:05.751109 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 10:55:05.754604 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5508 10:55:05.757840 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 10:55:05.761218 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 10:55:05.764292 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 10:55:05.768419 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 10:55:05.770986 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 10:55:05.774410 Pre-setting of DQS Precalculation
5514 10:55:05.777855 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5515 10:55:05.777951 ==
5516 10:55:05.781012 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 10:55:05.787780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 10:55:05.787884 ==
5519 10:55:05.791187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 10:55:05.797716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 10:55:05.801208 [CA 0] Center 36 (6~67) winsize 62
5522 10:55:05.804553 [CA 1] Center 36 (6~67) winsize 62
5523 10:55:05.807768 [CA 2] Center 34 (4~64) winsize 61
5524 10:55:05.811570 [CA 3] Center 33 (3~64) winsize 62
5525 10:55:05.814423 [CA 4] Center 33 (3~64) winsize 62
5526 10:55:05.817590 [CA 5] Center 33 (3~64) winsize 62
5527 10:55:05.817684
5528 10:55:05.820816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 10:55:05.820911
5530 10:55:05.824387 [CATrainingPosCal] consider 1 rank data
5531 10:55:05.827304 u2DelayCellTimex100 = 270/100 ps
5532 10:55:05.830897 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 10:55:05.837361 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 10:55:05.841100 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 10:55:05.844798 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 10:55:05.847250 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 10:55:05.850695 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 10:55:05.850788
5539 10:55:05.854030 CA PerBit enable=1, Macro0, CA PI delay=33
5540 10:55:05.854122
5541 10:55:05.857484 [CBTSetCACLKResult] CA Dly = 33
5542 10:55:05.857571 CS Dly: 4 (0~35)
5543 10:55:05.861051 ==
5544 10:55:05.863859 Dram Type= 6, Freq= 0, CH_1, rank 1
5545 10:55:05.867648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 10:55:05.867746 ==
5547 10:55:05.870452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 10:55:05.877530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 10:55:05.880984 [CA 0] Center 36 (6~67) winsize 62
5550 10:55:05.884782 [CA 1] Center 36 (6~67) winsize 62
5551 10:55:05.887535 [CA 2] Center 33 (3~64) winsize 62
5552 10:55:05.890701 [CA 3] Center 33 (3~64) winsize 62
5553 10:55:05.894607 [CA 4] Center 34 (4~64) winsize 61
5554 10:55:05.897404 [CA 5] Center 32 (2~63) winsize 62
5555 10:55:05.897496
5556 10:55:05.901523 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 10:55:05.901615
5558 10:55:05.904127 [CATrainingPosCal] consider 2 rank data
5559 10:55:05.907710 u2DelayCellTimex100 = 270/100 ps
5560 10:55:05.910736 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 10:55:05.917572 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 10:55:05.920599 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 10:55:05.924073 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 10:55:05.927445 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 10:55:05.930637 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5566 10:55:05.930736
5567 10:55:05.934172 CA PerBit enable=1, Macro0, CA PI delay=33
5568 10:55:05.934267
5569 10:55:05.937320 [CBTSetCACLKResult] CA Dly = 33
5570 10:55:05.937410 CS Dly: 5 (0~38)
5571 10:55:05.940849
5572 10:55:05.943854 ----->DramcWriteLeveling(PI) begin...
5573 10:55:05.943950 ==
5574 10:55:05.947137 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 10:55:05.950644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 10:55:05.950740 ==
5577 10:55:05.954153 Write leveling (Byte 0): 27 => 27
5578 10:55:05.957633 Write leveling (Byte 1): 28 => 28
5579 10:55:05.960519 DramcWriteLeveling(PI) end<-----
5580 10:55:05.960613
5581 10:55:05.960680 ==
5582 10:55:05.963949 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 10:55:05.967279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 10:55:05.967395 ==
5585 10:55:05.971008 [Gating] SW mode calibration
5586 10:55:05.977335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5587 10:55:05.984095 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5588 10:55:05.987503 0 14 0 | B1->B0 | 2f2f 3333 | 1 1 | (0 0) (1 1)
5589 10:55:05.990999 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 10:55:05.997627 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 10:55:06.000457 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5592 10:55:06.004139 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 10:55:06.007170 0 14 20 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
5594 10:55:06.014076 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5595 10:55:06.017647 0 14 28 | B1->B0 | 3030 3131 | 1 1 | (1 1) (1 0)
5596 10:55:06.020467 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5597 10:55:06.027187 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 10:55:06.030161 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 10:55:06.033895 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 10:55:06.040270 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 10:55:06.043341 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 10:55:06.046861 0 15 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5603 10:55:06.053373 0 15 28 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
5604 10:55:06.056846 1 0 0 | B1->B0 | 4444 3f3f | 0 0 | (0 0) (0 0)
5605 10:55:06.060242 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 10:55:06.066634 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 10:55:06.069918 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 10:55:06.073274 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 10:55:06.079717 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 10:55:06.083584 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 10:55:06.086466 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 10:55:06.093242 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5613 10:55:06.096624 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 10:55:06.100113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 10:55:06.106544 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 10:55:06.109817 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 10:55:06.113208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 10:55:06.119830 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 10:55:06.123563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 10:55:06.126527 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 10:55:06.133261 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 10:55:06.136963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 10:55:06.139930 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 10:55:06.146382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 10:55:06.149830 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 10:55:06.153078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 10:55:06.160305 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5628 10:55:06.160427 Total UI for P1: 0, mck2ui 16
5629 10:55:06.166256 best dqsien dly found for B1: ( 1, 2, 26)
5630 10:55:06.169727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 10:55:06.173007 Total UI for P1: 0, mck2ui 16
5632 10:55:06.176407 best dqsien dly found for B0: ( 1, 2, 28)
5633 10:55:06.180101 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5634 10:55:06.182684 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5635 10:55:06.182774
5636 10:55:06.186415 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5637 10:55:06.189567 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5638 10:55:06.192960 [Gating] SW calibration Done
5639 10:55:06.193053 ==
5640 10:55:06.196297 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 10:55:06.199629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 10:55:06.199722 ==
5643 10:55:06.202811 RX Vref Scan: 0
5644 10:55:06.202898
5645 10:55:06.206290 RX Vref 0 -> 0, step: 1
5646 10:55:06.206378
5647 10:55:06.206445 RX Delay -80 -> 252, step: 8
5648 10:55:06.212551 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5649 10:55:06.215908 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5650 10:55:06.219702 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5651 10:55:06.222675 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5652 10:55:06.226445 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5653 10:55:06.229526 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5654 10:55:06.236589 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5655 10:55:06.239081 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5656 10:55:06.242952 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5657 10:55:06.246064 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5658 10:55:06.249449 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5659 10:55:06.255818 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5660 10:55:06.258857 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5661 10:55:06.262407 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5662 10:55:06.266012 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5663 10:55:06.269090 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5664 10:55:06.269185 ==
5665 10:55:06.272252 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 10:55:06.279323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 10:55:06.279477 ==
5668 10:55:06.279549 DQS Delay:
5669 10:55:06.282171 DQS0 = 0, DQS1 = 0
5670 10:55:06.282258 DQM Delay:
5671 10:55:06.282326 DQM0 = 96, DQM1 = 89
5672 10:55:06.285495 DQ Delay:
5673 10:55:06.289075 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5674 10:55:06.292156 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5675 10:55:06.295900 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5676 10:55:06.298694 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5677 10:55:06.298784
5678 10:55:06.298851
5679 10:55:06.298928 ==
5680 10:55:06.302446 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 10:55:06.305641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 10:55:06.305730 ==
5683 10:55:06.305797
5684 10:55:06.305858
5685 10:55:06.309081 TX Vref Scan disable
5686 10:55:06.309166 == TX Byte 0 ==
5687 10:55:06.315671 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5688 10:55:06.319135 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5689 10:55:06.319231 == TX Byte 1 ==
5690 10:55:06.325605 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 10:55:06.329202 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 10:55:06.329299 ==
5693 10:55:06.332020 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 10:55:06.336265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 10:55:06.336365 ==
5696 10:55:06.336436
5697 10:55:06.338843
5698 10:55:06.338929 TX Vref Scan disable
5699 10:55:06.342730 == TX Byte 0 ==
5700 10:55:06.345615 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5701 10:55:06.349011 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5702 10:55:06.352028 == TX Byte 1 ==
5703 10:55:06.355618 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5704 10:55:06.358928 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5705 10:55:06.362096
5706 10:55:06.362193 [DATLAT]
5707 10:55:06.362262 Freq=933, CH1 RK0
5708 10:55:06.362324
5709 10:55:06.365539 DATLAT Default: 0xd
5710 10:55:06.365630 0, 0xFFFF, sum = 0
5711 10:55:06.368878 1, 0xFFFF, sum = 0
5712 10:55:06.368987 2, 0xFFFF, sum = 0
5713 10:55:06.372026 3, 0xFFFF, sum = 0
5714 10:55:06.372120 4, 0xFFFF, sum = 0
5715 10:55:06.375532 5, 0xFFFF, sum = 0
5716 10:55:06.378412 6, 0xFFFF, sum = 0
5717 10:55:06.378506 7, 0xFFFF, sum = 0
5718 10:55:06.382002 8, 0xFFFF, sum = 0
5719 10:55:06.382091 9, 0xFFFF, sum = 0
5720 10:55:06.385650 10, 0x0, sum = 1
5721 10:55:06.385740 11, 0x0, sum = 2
5722 10:55:06.385808 12, 0x0, sum = 3
5723 10:55:06.388573 13, 0x0, sum = 4
5724 10:55:06.388661 best_step = 11
5725 10:55:06.388728
5726 10:55:06.392390 ==
5727 10:55:06.392480 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 10:55:06.398826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 10:55:06.398931 ==
5730 10:55:06.399000 RX Vref Scan: 1
5731 10:55:06.399063
5732 10:55:06.401664 RX Vref 0 -> 0, step: 1
5733 10:55:06.401749
5734 10:55:06.405033 RX Delay -61 -> 252, step: 4
5735 10:55:06.405120
5736 10:55:06.408518 Set Vref, RX VrefLevel [Byte0]: 57
5737 10:55:06.411751 [Byte1]: 54
5738 10:55:06.411854
5739 10:55:06.415553 Final RX Vref Byte 0 = 57 to rank0
5740 10:55:06.418799 Final RX Vref Byte 1 = 54 to rank0
5741 10:55:06.421762 Final RX Vref Byte 0 = 57 to rank1
5742 10:55:06.425418 Final RX Vref Byte 1 = 54 to rank1==
5743 10:55:06.428822 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 10:55:06.432121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 10:55:06.432210 ==
5746 10:55:06.435596 DQS Delay:
5747 10:55:06.435682 DQS0 = 0, DQS1 = 0
5748 10:55:06.438389 DQM Delay:
5749 10:55:06.438474 DQM0 = 97, DQM1 = 91
5750 10:55:06.438541 DQ Delay:
5751 10:55:06.442029 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5752 10:55:06.444925 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5753 10:55:06.448693 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =86
5754 10:55:06.451633 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =96
5755 10:55:06.454917
5756 10:55:06.455003
5757 10:55:06.462137 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5758 10:55:06.465084 CH1 RK0: MR19=504, MR18=17F4
5759 10:55:06.471982 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5760 10:55:06.472102
5761 10:55:06.474970 ----->DramcWriteLeveling(PI) begin...
5762 10:55:06.475074 ==
5763 10:55:06.478249 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 10:55:06.482149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 10:55:06.482241 ==
5766 10:55:06.485011 Write leveling (Byte 0): 28 => 28
5767 10:55:06.488328 Write leveling (Byte 1): 30 => 30
5768 10:55:06.491671 DramcWriteLeveling(PI) end<-----
5769 10:55:06.491761
5770 10:55:06.491829 ==
5771 10:55:06.495057 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 10:55:06.498146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 10:55:06.498235 ==
5774 10:55:06.501536 [Gating] SW mode calibration
5775 10:55:06.508469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5776 10:55:06.515075 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5777 10:55:06.518538 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5778 10:55:06.521463 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5779 10:55:06.528193 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 10:55:06.531387 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 10:55:06.534525 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 10:55:06.541164 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 10:55:06.545000 0 14 24 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
5784 10:55:06.548373 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5785 10:55:06.554638 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5786 10:55:06.557782 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 10:55:06.560952 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 10:55:06.567746 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 10:55:06.571297 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 10:55:06.574566 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 10:55:06.581027 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (1 1)
5792 10:55:06.584163 0 15 28 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
5793 10:55:06.587663 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 10:55:06.594482 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 10:55:06.597260 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 10:55:06.600904 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 10:55:06.607581 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 10:55:06.610932 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 10:55:06.614033 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5800 10:55:06.620832 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 10:55:06.624454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 10:55:06.627200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 10:55:06.634475 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 10:55:06.637443 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 10:55:06.640716 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 10:55:06.647336 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 10:55:06.650678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 10:55:06.653872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 10:55:06.657580 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 10:55:06.664461 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 10:55:06.667514 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 10:55:06.670894 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 10:55:06.677210 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 10:55:06.681122 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5815 10:55:06.684219 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5816 10:55:06.690356 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 10:55:06.693925 Total UI for P1: 0, mck2ui 16
5818 10:55:06.697801 best dqsien dly found for B0: ( 1, 2, 22)
5819 10:55:06.697901 Total UI for P1: 0, mck2ui 16
5820 10:55:06.703746 best dqsien dly found for B1: ( 1, 2, 24)
5821 10:55:06.707144 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5822 10:55:06.710517 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5823 10:55:06.710610
5824 10:55:06.713718 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5825 10:55:06.717259 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5826 10:55:06.720584 [Gating] SW calibration Done
5827 10:55:06.720681 ==
5828 10:55:06.724075 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 10:55:06.727572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 10:55:06.727667 ==
5831 10:55:06.730467 RX Vref Scan: 0
5832 10:55:06.730553
5833 10:55:06.730620 RX Vref 0 -> 0, step: 1
5834 10:55:06.730683
5835 10:55:06.733700 RX Delay -80 -> 252, step: 8
5836 10:55:06.737091 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5837 10:55:06.743955 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5838 10:55:06.747018 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5839 10:55:06.750280 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5840 10:55:06.753455 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5841 10:55:06.757132 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5842 10:55:06.760634 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5843 10:55:06.766750 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5844 10:55:06.770126 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5845 10:55:06.773888 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5846 10:55:06.777214 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5847 10:55:06.780376 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5848 10:55:06.787002 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5849 10:55:06.790407 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5850 10:55:06.793793 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5851 10:55:06.797306 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5852 10:55:06.797405 ==
5853 10:55:06.799969 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 10:55:06.803463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 10:55:06.803555 ==
5856 10:55:06.807088 DQS Delay:
5857 10:55:06.807174 DQS0 = 0, DQS1 = 0
5858 10:55:06.810317 DQM Delay:
5859 10:55:06.810405 DQM0 = 93, DQM1 = 89
5860 10:55:06.810474 DQ Delay:
5861 10:55:06.813911 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5862 10:55:06.816591 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5863 10:55:06.820304 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5864 10:55:06.823503 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5865 10:55:06.823606
5866 10:55:06.823675
5867 10:55:06.826873 ==
5868 10:55:06.830110 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 10:55:06.833471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 10:55:06.833566 ==
5871 10:55:06.833634
5872 10:55:06.833696
5873 10:55:06.836512 TX Vref Scan disable
5874 10:55:06.836598 == TX Byte 0 ==
5875 10:55:06.843326 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5876 10:55:06.847070 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5877 10:55:06.847170 == TX Byte 1 ==
5878 10:55:06.853173 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5879 10:55:06.856926 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5880 10:55:06.857029 ==
5881 10:55:06.860266 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 10:55:06.863538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 10:55:06.863633 ==
5884 10:55:06.863702
5885 10:55:06.863764
5886 10:55:06.866582 TX Vref Scan disable
5887 10:55:06.870132 == TX Byte 0 ==
5888 10:55:06.873493 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5889 10:55:06.876624 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5890 10:55:06.880463 == TX Byte 1 ==
5891 10:55:06.883372 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5892 10:55:06.886439 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5893 10:55:06.886530
5894 10:55:06.889786 [DATLAT]
5895 10:55:06.889875 Freq=933, CH1 RK1
5896 10:55:06.889943
5897 10:55:06.892962 DATLAT Default: 0xb
5898 10:55:06.893049 0, 0xFFFF, sum = 0
5899 10:55:06.896358 1, 0xFFFF, sum = 0
5900 10:55:06.896448 2, 0xFFFF, sum = 0
5901 10:55:06.899591 3, 0xFFFF, sum = 0
5902 10:55:06.899701 4, 0xFFFF, sum = 0
5903 10:55:06.903229 5, 0xFFFF, sum = 0
5904 10:55:06.903321 6, 0xFFFF, sum = 0
5905 10:55:06.906766 7, 0xFFFF, sum = 0
5906 10:55:06.906854 8, 0xFFFF, sum = 0
5907 10:55:06.909910 9, 0xFFFF, sum = 0
5908 10:55:06.910000 10, 0x0, sum = 1
5909 10:55:06.912987 11, 0x0, sum = 2
5910 10:55:06.913081 12, 0x0, sum = 3
5911 10:55:06.916546 13, 0x0, sum = 4
5912 10:55:06.916635 best_step = 11
5913 10:55:06.916701
5914 10:55:06.916762 ==
5915 10:55:06.919889 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 10:55:06.923465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 10:55:06.926715 ==
5918 10:55:06.926808 RX Vref Scan: 0
5919 10:55:06.926875
5920 10:55:06.930123 RX Vref 0 -> 0, step: 1
5921 10:55:06.930212
5922 10:55:06.932938 RX Delay -61 -> 252, step: 4
5923 10:55:06.936622 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5924 10:55:06.939525 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5925 10:55:06.943310 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5926 10:55:06.949524 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5927 10:55:06.952789 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5928 10:55:06.956266 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5929 10:55:06.959491 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5930 10:55:06.963112 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5931 10:55:06.966152 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5932 10:55:06.973110 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5933 10:55:06.977107 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5934 10:55:06.980015 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5935 10:55:06.982777 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5936 10:55:06.986442 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5937 10:55:06.992728 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5938 10:55:06.995889 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5939 10:55:06.995994 ==
5940 10:55:06.999624 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 10:55:07.002956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 10:55:07.003071 ==
5943 10:55:07.006342 DQS Delay:
5944 10:55:07.006431 DQS0 = 0, DQS1 = 0
5945 10:55:07.006497 DQM Delay:
5946 10:55:07.009486 DQM0 = 95, DQM1 = 91
5947 10:55:07.009574 DQ Delay:
5948 10:55:07.012811 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
5949 10:55:07.016162 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =90
5950 10:55:07.019706 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5951 10:55:07.022435 DQ12 =98, DQ13 =100, DQ14 =102, DQ15 =100
5952 10:55:07.022521
5953 10:55:07.022586
5954 10:55:07.032938 [DQSOSCAuto] RK1, (LSB)MR18= 0xc16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 418 ps
5955 10:55:07.035641 CH1 RK1: MR19=505, MR18=C16
5956 10:55:07.039222 CH1_RK1: MR19=0x505, MR18=0xC16, DQSOSC=414, MR23=63, INC=63, DEC=42
5957 10:55:07.042405 [RxdqsGatingPostProcess] freq 933
5958 10:55:07.048854 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5959 10:55:07.053191 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 10:55:07.055689 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 10:55:07.059293 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 10:55:07.062410 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 10:55:07.065821 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 10:55:07.068946 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 10:55:07.072213 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 10:55:07.075799 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 10:55:07.078859 Pre-setting of DQS Precalculation
5968 10:55:07.082292 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5969 10:55:07.088880 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5970 10:55:07.095369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5971 10:55:07.098399
5972 10:55:07.098503
5973 10:55:07.098569 [Calibration Summary] 1866 Mbps
5974 10:55:07.102070 CH 0, Rank 0
5975 10:55:07.102160 SW Impedance : PASS
5976 10:55:07.105068 DUTY Scan : NO K
5977 10:55:07.108706 ZQ Calibration : PASS
5978 10:55:07.108801 Jitter Meter : NO K
5979 10:55:07.112232 CBT Training : PASS
5980 10:55:07.115276 Write leveling : PASS
5981 10:55:07.115425 RX DQS gating : PASS
5982 10:55:07.118620 RX DQ/DQS(RDDQC) : PASS
5983 10:55:07.122070 TX DQ/DQS : PASS
5984 10:55:07.122163 RX DATLAT : PASS
5985 10:55:07.125359 RX DQ/DQS(Engine): PASS
5986 10:55:07.128653 TX OE : NO K
5987 10:55:07.128744 All Pass.
5988 10:55:07.128811
5989 10:55:07.128872 CH 0, Rank 1
5990 10:55:07.131995 SW Impedance : PASS
5991 10:55:07.134919 DUTY Scan : NO K
5992 10:55:07.135008 ZQ Calibration : PASS
5993 10:55:07.138788 Jitter Meter : NO K
5994 10:55:07.141621 CBT Training : PASS
5995 10:55:07.141715 Write leveling : PASS
5996 10:55:07.145649 RX DQS gating : PASS
5997 10:55:07.145747 RX DQ/DQS(RDDQC) : PASS
5998 10:55:07.148691 TX DQ/DQS : PASS
5999 10:55:07.151587 RX DATLAT : PASS
6000 10:55:07.151678 RX DQ/DQS(Engine): PASS
6001 10:55:07.154894 TX OE : NO K
6002 10:55:07.154982 All Pass.
6003 10:55:07.155050
6004 10:55:07.158621 CH 1, Rank 0
6005 10:55:07.158710 SW Impedance : PASS
6006 10:55:07.161796 DUTY Scan : NO K
6007 10:55:07.165258 ZQ Calibration : PASS
6008 10:55:07.165355 Jitter Meter : NO K
6009 10:55:07.168556 CBT Training : PASS
6010 10:55:07.171525 Write leveling : PASS
6011 10:55:07.171617 RX DQS gating : PASS
6012 10:55:07.174908 RX DQ/DQS(RDDQC) : PASS
6013 10:55:07.178372 TX DQ/DQS : PASS
6014 10:55:07.178472 RX DATLAT : PASS
6015 10:55:07.181778 RX DQ/DQS(Engine): PASS
6016 10:55:07.185478 TX OE : NO K
6017 10:55:07.185576 All Pass.
6018 10:55:07.185644
6019 10:55:07.185704 CH 1, Rank 1
6020 10:55:07.188941 SW Impedance : PASS
6021 10:55:07.191591 DUTY Scan : NO K
6022 10:55:07.191680 ZQ Calibration : PASS
6023 10:55:07.194941 Jitter Meter : NO K
6024 10:55:07.198075 CBT Training : PASS
6025 10:55:07.198170 Write leveling : PASS
6026 10:55:07.201551 RX DQS gating : PASS
6027 10:55:07.201641 RX DQ/DQS(RDDQC) : PASS
6028 10:55:07.204651 TX DQ/DQS : PASS
6029 10:55:07.207809 RX DATLAT : PASS
6030 10:55:07.207903 RX DQ/DQS(Engine): PASS
6031 10:55:07.211487 TX OE : NO K
6032 10:55:07.211580 All Pass.
6033 10:55:07.211647
6034 10:55:07.214715 DramC Write-DBI off
6035 10:55:07.217829 PER_BANK_REFRESH: Hybrid Mode
6036 10:55:07.217939 TX_TRACKING: ON
6037 10:55:07.227554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6038 10:55:07.230994 [FAST_K] Save calibration result to emmc
6039 10:55:07.234713 dramc_set_vcore_voltage set vcore to 650000
6040 10:55:07.237662 Read voltage for 400, 6
6041 10:55:07.237757 Vio18 = 0
6042 10:55:07.240710 Vcore = 650000
6043 10:55:07.240796 Vdram = 0
6044 10:55:07.240861 Vddq = 0
6045 10:55:07.240921 Vmddr = 0
6046 10:55:07.247822 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6047 10:55:07.254716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6048 10:55:07.254839 MEM_TYPE=3, freq_sel=20
6049 10:55:07.257458 sv_algorithm_assistance_LP4_800
6050 10:55:07.260942 ============ PULL DRAM RESETB DOWN ============
6051 10:55:07.267690 ========== PULL DRAM RESETB DOWN end =========
6052 10:55:07.271056 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6053 10:55:07.274645 ===================================
6054 10:55:07.277616 LPDDR4 DRAM CONFIGURATION
6055 10:55:07.280785 ===================================
6056 10:55:07.280885 EX_ROW_EN[0] = 0x0
6057 10:55:07.284726 EX_ROW_EN[1] = 0x0
6058 10:55:07.284813 LP4Y_EN = 0x0
6059 10:55:07.287390 WORK_FSP = 0x0
6060 10:55:07.287472 WL = 0x2
6061 10:55:07.290946 RL = 0x2
6062 10:55:07.291028 BL = 0x2
6063 10:55:07.294417 RPST = 0x0
6064 10:55:07.294499 RD_PRE = 0x0
6065 10:55:07.298335 WR_PRE = 0x1
6066 10:55:07.301270 WR_PST = 0x0
6067 10:55:07.301351 DBI_WR = 0x0
6068 10:55:07.304068 DBI_RD = 0x0
6069 10:55:07.304150 OTF = 0x1
6070 10:55:07.307206 ===================================
6071 10:55:07.311124 ===================================
6072 10:55:07.311206 ANA top config
6073 10:55:07.313897 ===================================
6074 10:55:07.317339 DLL_ASYNC_EN = 0
6075 10:55:07.320965 ALL_SLAVE_EN = 1
6076 10:55:07.323995 NEW_RANK_MODE = 1
6077 10:55:07.327543 DLL_IDLE_MODE = 1
6078 10:55:07.327624 LP45_APHY_COMB_EN = 1
6079 10:55:07.330646 TX_ODT_DIS = 1
6080 10:55:07.333844 NEW_8X_MODE = 1
6081 10:55:07.337355 ===================================
6082 10:55:07.340890 ===================================
6083 10:55:07.344218 data_rate = 800
6084 10:55:07.347672 CKR = 1
6085 10:55:07.347753 DQ_P2S_RATIO = 4
6086 10:55:07.350686 ===================================
6087 10:55:07.354248 CA_P2S_RATIO = 4
6088 10:55:07.357170 DQ_CA_OPEN = 0
6089 10:55:07.360460 DQ_SEMI_OPEN = 1
6090 10:55:07.363926 CA_SEMI_OPEN = 1
6091 10:55:07.367093 CA_FULL_RATE = 0
6092 10:55:07.367179 DQ_CKDIV4_EN = 0
6093 10:55:07.370558 CA_CKDIV4_EN = 1
6094 10:55:07.374026 CA_PREDIV_EN = 0
6095 10:55:07.377361 PH8_DLY = 0
6096 10:55:07.380121 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6097 10:55:07.383681 DQ_AAMCK_DIV = 0
6098 10:55:07.383762 CA_AAMCK_DIV = 0
6099 10:55:07.387234 CA_ADMCK_DIV = 4
6100 10:55:07.390492 DQ_TRACK_CA_EN = 0
6101 10:55:07.393521 CA_PICK = 800
6102 10:55:07.396793 CA_MCKIO = 400
6103 10:55:07.400332 MCKIO_SEMI = 400
6104 10:55:07.403563 PLL_FREQ = 3016
6105 10:55:07.403646 DQ_UI_PI_RATIO = 32
6106 10:55:07.406863 CA_UI_PI_RATIO = 32
6107 10:55:07.410361 ===================================
6108 10:55:07.413883 ===================================
6109 10:55:07.416855 memory_type:LPDDR4
6110 10:55:07.420241 GP_NUM : 10
6111 10:55:07.420324 SRAM_EN : 1
6112 10:55:07.423361 MD32_EN : 0
6113 10:55:07.427072 ===================================
6114 10:55:07.430187 [ANA_INIT] >>>>>>>>>>>>>>
6115 10:55:07.433311 <<<<<< [CONFIGURE PHASE]: ANA_TX
6116 10:55:07.436551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6117 10:55:07.440062 ===================================
6118 10:55:07.440145 data_rate = 800,PCW = 0X7400
6119 10:55:07.443308 ===================================
6120 10:55:07.446718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6121 10:55:07.453511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 10:55:07.463153 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 10:55:07.470103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6124 10:55:07.473371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6125 10:55:07.476284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6126 10:55:07.479709 [ANA_INIT] flow start
6127 10:55:07.479845 [ANA_INIT] PLL >>>>>>>>
6128 10:55:07.483224 [ANA_INIT] PLL <<<<<<<<
6129 10:55:07.486686 [ANA_INIT] MIDPI >>>>>>>>
6130 10:55:07.486769 [ANA_INIT] MIDPI <<<<<<<<
6131 10:55:07.489897 [ANA_INIT] DLL >>>>>>>>
6132 10:55:07.493231 [ANA_INIT] flow end
6133 10:55:07.495999 ============ LP4 DIFF to SE enter ============
6134 10:55:07.499460 ============ LP4 DIFF to SE exit ============
6135 10:55:07.503132 [ANA_INIT] <<<<<<<<<<<<<
6136 10:55:07.506570 [Flow] Enable top DCM control >>>>>
6137 10:55:07.509803 [Flow] Enable top DCM control <<<<<
6138 10:55:07.513034 Enable DLL master slave shuffle
6139 10:55:07.516096 ==============================================================
6140 10:55:07.519244 Gating Mode config
6141 10:55:07.526163 ==============================================================
6142 10:55:07.526247 Config description:
6143 10:55:07.535708 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6144 10:55:07.542456 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6145 10:55:07.545770 SELPH_MODE 0: By rank 1: By Phase
6146 10:55:07.552775 ==============================================================
6147 10:55:07.555911 GAT_TRACK_EN = 0
6148 10:55:07.559197 RX_GATING_MODE = 2
6149 10:55:07.562324 RX_GATING_TRACK_MODE = 2
6150 10:55:07.566250 SELPH_MODE = 1
6151 10:55:07.569214 PICG_EARLY_EN = 1
6152 10:55:07.572717 VALID_LAT_VALUE = 1
6153 10:55:07.576138 ==============================================================
6154 10:55:07.579022 Enter into Gating configuration >>>>
6155 10:55:07.582472 Exit from Gating configuration <<<<
6156 10:55:07.585927 Enter into DVFS_PRE_config >>>>>
6157 10:55:07.599276 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6158 10:55:07.599385 Exit from DVFS_PRE_config <<<<<
6159 10:55:07.602754 Enter into PICG configuration >>>>
6160 10:55:07.605498 Exit from PICG configuration <<<<
6161 10:55:07.608954 [RX_INPUT] configuration >>>>>
6162 10:55:07.612294 [RX_INPUT] configuration <<<<<
6163 10:55:07.619070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6164 10:55:07.622259 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6165 10:55:07.629115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 10:55:07.635625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 10:55:07.642390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 10:55:07.648539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 10:55:07.652213 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6170 10:55:07.655552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6171 10:55:07.658825 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6172 10:55:07.665767 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6173 10:55:07.668560 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6174 10:55:07.672077 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 10:55:07.675536 ===================================
6176 10:55:07.678183 LPDDR4 DRAM CONFIGURATION
6177 10:55:07.682052 ===================================
6178 10:55:07.685033 EX_ROW_EN[0] = 0x0
6179 10:55:07.685116 EX_ROW_EN[1] = 0x0
6180 10:55:07.688469 LP4Y_EN = 0x0
6181 10:55:07.688552 WORK_FSP = 0x0
6182 10:55:07.691797 WL = 0x2
6183 10:55:07.691880 RL = 0x2
6184 10:55:07.695304 BL = 0x2
6185 10:55:07.695428 RPST = 0x0
6186 10:55:07.698229 RD_PRE = 0x0
6187 10:55:07.698311 WR_PRE = 0x1
6188 10:55:07.701709 WR_PST = 0x0
6189 10:55:07.701791 DBI_WR = 0x0
6190 10:55:07.705166 DBI_RD = 0x0
6191 10:55:07.705249 OTF = 0x1
6192 10:55:07.708700 ===================================
6193 10:55:07.714994 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6194 10:55:07.718092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6195 10:55:07.721984 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 10:55:07.725393 ===================================
6197 10:55:07.728221 LPDDR4 DRAM CONFIGURATION
6198 10:55:07.731518 ===================================
6199 10:55:07.731601 EX_ROW_EN[0] = 0x10
6200 10:55:07.734930 EX_ROW_EN[1] = 0x0
6201 10:55:07.738310 LP4Y_EN = 0x0
6202 10:55:07.738393 WORK_FSP = 0x0
6203 10:55:07.741754 WL = 0x2
6204 10:55:07.741837 RL = 0x2
6205 10:55:07.745010 BL = 0x2
6206 10:55:07.745092 RPST = 0x0
6207 10:55:07.748264 RD_PRE = 0x0
6208 10:55:07.748348 WR_PRE = 0x1
6209 10:55:07.751294 WR_PST = 0x0
6210 10:55:07.751427 DBI_WR = 0x0
6211 10:55:07.755193 DBI_RD = 0x0
6212 10:55:07.755276 OTF = 0x1
6213 10:55:07.758077 ===================================
6214 10:55:07.764748 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6215 10:55:07.769301 nWR fixed to 30
6216 10:55:07.772493 [ModeRegInit_LP4] CH0 RK0
6217 10:55:07.772575 [ModeRegInit_LP4] CH0 RK1
6218 10:55:07.775950 [ModeRegInit_LP4] CH1 RK0
6219 10:55:07.779320 [ModeRegInit_LP4] CH1 RK1
6220 10:55:07.779445 match AC timing 19
6221 10:55:07.786038 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6222 10:55:07.788897 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6223 10:55:07.792201 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6224 10:55:07.799274 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6225 10:55:07.802123 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6226 10:55:07.802206 ==
6227 10:55:07.805801 Dram Type= 6, Freq= 0, CH_0, rank 0
6228 10:55:07.808882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 10:55:07.808966 ==
6230 10:55:07.815326 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 10:55:07.822110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6232 10:55:07.825613 [CA 0] Center 36 (8~64) winsize 57
6233 10:55:07.828902 [CA 1] Center 36 (8~64) winsize 57
6234 10:55:07.832328 [CA 2] Center 36 (8~64) winsize 57
6235 10:55:07.835558 [CA 3] Center 36 (8~64) winsize 57
6236 10:55:07.835641 [CA 4] Center 36 (8~64) winsize 57
6237 10:55:07.838552 [CA 5] Center 36 (8~64) winsize 57
6238 10:55:07.838635
6239 10:55:07.845020 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6240 10:55:07.845104
6241 10:55:07.849016 [CATrainingPosCal] consider 1 rank data
6242 10:55:07.852309 u2DelayCellTimex100 = 270/100 ps
6243 10:55:07.855507 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:55:07.859000 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:55:07.861921 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 10:55:07.865223 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 10:55:07.868597 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 10:55:07.871683 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 10:55:07.871767
6250 10:55:07.874985 CA PerBit enable=1, Macro0, CA PI delay=36
6251 10:55:07.875068
6252 10:55:07.878493 [CBTSetCACLKResult] CA Dly = 36
6253 10:55:07.881810 CS Dly: 1 (0~32)
6254 10:55:07.881893 ==
6255 10:55:07.885214 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 10:55:07.888188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 10:55:07.888272 ==
6258 10:55:07.894796 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 10:55:07.901419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 10:55:07.904948 [CA 0] Center 36 (8~64) winsize 57
6261 10:55:07.905032 [CA 1] Center 36 (8~64) winsize 57
6262 10:55:07.907958 [CA 2] Center 36 (8~64) winsize 57
6263 10:55:07.911278 [CA 3] Center 36 (8~64) winsize 57
6264 10:55:07.914709 [CA 4] Center 36 (8~64) winsize 57
6265 10:55:07.918460 [CA 5] Center 36 (8~64) winsize 57
6266 10:55:07.918542
6267 10:55:07.921577 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 10:55:07.921659
6269 10:55:07.928283 [CATrainingPosCal] consider 2 rank data
6270 10:55:07.928366 u2DelayCellTimex100 = 270/100 ps
6271 10:55:07.935151 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 10:55:07.937834 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 10:55:07.941531 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 10:55:07.944292 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 10:55:07.947897 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 10:55:07.951277 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 10:55:07.951384
6278 10:55:07.954487 CA PerBit enable=1, Macro0, CA PI delay=36
6279 10:55:07.954570
6280 10:55:07.957565 [CBTSetCACLKResult] CA Dly = 36
6281 10:55:07.961042 CS Dly: 1 (0~32)
6282 10:55:07.961125
6283 10:55:07.964303 ----->DramcWriteLeveling(PI) begin...
6284 10:55:07.964388 ==
6285 10:55:07.967333 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 10:55:07.970846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 10:55:07.970929 ==
6288 10:55:07.973996 Write leveling (Byte 0): 40 => 8
6289 10:55:07.977903 Write leveling (Byte 1): 32 => 0
6290 10:55:07.980893 DramcWriteLeveling(PI) end<-----
6291 10:55:07.980977
6292 10:55:07.981042 ==
6293 10:55:07.984246 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 10:55:07.987775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 10:55:07.987857 ==
6296 10:55:07.990613 [Gating] SW mode calibration
6297 10:55:07.997365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6298 10:55:08.003839 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6299 10:55:08.007077 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 10:55:08.010304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 10:55:08.016851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 10:55:08.020244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 10:55:08.023483 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 10:55:08.030596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 10:55:08.033327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 10:55:08.037181 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 10:55:08.043936 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 10:55:08.044018 Total UI for P1: 0, mck2ui 16
6309 10:55:08.050088 best dqsien dly found for B0: ( 0, 14, 24)
6310 10:55:08.050172 Total UI for P1: 0, mck2ui 16
6311 10:55:08.056900 best dqsien dly found for B1: ( 0, 14, 24)
6312 10:55:08.060055 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6313 10:55:08.063488 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6314 10:55:08.063570
6315 10:55:08.066897 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 10:55:08.070259 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 10:55:08.073707 [Gating] SW calibration Done
6318 10:55:08.073789 ==
6319 10:55:08.076900 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 10:55:08.080112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 10:55:08.080194 ==
6322 10:55:08.083568 RX Vref Scan: 0
6323 10:55:08.083650
6324 10:55:08.083713 RX Vref 0 -> 0, step: 1
6325 10:55:08.083773
6326 10:55:08.086592 RX Delay -410 -> 252, step: 16
6327 10:55:08.093721 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6328 10:55:08.097127 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6329 10:55:08.100062 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6330 10:55:08.103657 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6331 10:55:08.110274 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6332 10:55:08.113574 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6333 10:55:08.116721 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6334 10:55:08.119925 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6335 10:55:08.126761 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6336 10:55:08.129685 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6337 10:55:08.133276 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6338 10:55:08.136221 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6339 10:55:08.142826 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6340 10:55:08.146280 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6341 10:55:08.150212 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6342 10:55:08.156701 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6343 10:55:08.156783 ==
6344 10:55:08.159596 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 10:55:08.162956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 10:55:08.163038 ==
6347 10:55:08.163102 DQS Delay:
6348 10:55:08.166203 DQS0 = 35, DQS1 = 51
6349 10:55:08.166283 DQM Delay:
6350 10:55:08.169808 DQM0 = 6, DQM1 = 10
6351 10:55:08.169889 DQ Delay:
6352 10:55:08.172891 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6353 10:55:08.176756 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6354 10:55:08.179738 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6355 10:55:08.182923 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6356 10:55:08.183006
6357 10:55:08.183071
6358 10:55:08.183132 ==
6359 10:55:08.186032 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 10:55:08.189517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 10:55:08.189602 ==
6362 10:55:08.189669
6363 10:55:08.189730
6364 10:55:08.192951 TX Vref Scan disable
6365 10:55:08.193034 == TX Byte 0 ==
6366 10:55:08.199197 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 10:55:08.202714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 10:55:08.202798 == TX Byte 1 ==
6369 10:55:08.209303 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6370 10:55:08.212786 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6371 10:55:08.212870 ==
6372 10:55:08.215706 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 10:55:08.218879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 10:55:08.218962 ==
6375 10:55:08.219028
6376 10:55:08.219088
6377 10:55:08.222780 TX Vref Scan disable
6378 10:55:08.225706 == TX Byte 0 ==
6379 10:55:08.229140 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 10:55:08.232824 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 10:55:08.235324 == TX Byte 1 ==
6382 10:55:08.238830 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6383 10:55:08.242363 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6384 10:55:08.242447
6385 10:55:08.242513 [DATLAT]
6386 10:55:08.245779 Freq=400, CH0 RK0
6387 10:55:08.245862
6388 10:55:08.245928 DATLAT Default: 0xf
6389 10:55:08.248640 0, 0xFFFF, sum = 0
6390 10:55:08.252523 1, 0xFFFF, sum = 0
6391 10:55:08.252609 2, 0xFFFF, sum = 0
6392 10:55:08.255309 3, 0xFFFF, sum = 0
6393 10:55:08.255455 4, 0xFFFF, sum = 0
6394 10:55:08.258765 5, 0xFFFF, sum = 0
6395 10:55:08.258849 6, 0xFFFF, sum = 0
6396 10:55:08.262139 7, 0xFFFF, sum = 0
6397 10:55:08.262223 8, 0xFFFF, sum = 0
6398 10:55:08.265684 9, 0xFFFF, sum = 0
6399 10:55:08.265768 10, 0xFFFF, sum = 0
6400 10:55:08.268679 11, 0xFFFF, sum = 0
6401 10:55:08.268764 12, 0xFFFF, sum = 0
6402 10:55:08.272568 13, 0x0, sum = 1
6403 10:55:08.272652 14, 0x0, sum = 2
6404 10:55:08.275332 15, 0x0, sum = 3
6405 10:55:08.275440 16, 0x0, sum = 4
6406 10:55:08.278975 best_step = 14
6407 10:55:08.279058
6408 10:55:08.279123 ==
6409 10:55:08.282042 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 10:55:08.285672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 10:55:08.285756 ==
6412 10:55:08.285823 RX Vref Scan: 1
6413 10:55:08.289011
6414 10:55:08.289121 RX Vref 0 -> 0, step: 1
6415 10:55:08.289215
6416 10:55:08.292114 RX Delay -343 -> 252, step: 8
6417 10:55:08.292196
6418 10:55:08.295312 Set Vref, RX VrefLevel [Byte0]: 54
6419 10:55:08.298882 [Byte1]: 51
6420 10:55:08.302633
6421 10:55:08.302716 Final RX Vref Byte 0 = 54 to rank0
6422 10:55:08.306091 Final RX Vref Byte 1 = 51 to rank0
6423 10:55:08.309401 Final RX Vref Byte 0 = 54 to rank1
6424 10:55:08.313313 Final RX Vref Byte 1 = 51 to rank1==
6425 10:55:08.316062 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 10:55:08.322782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 10:55:08.322866 ==
6428 10:55:08.322932 DQS Delay:
6429 10:55:08.326064 DQS0 = 44, DQS1 = 60
6430 10:55:08.326147 DQM Delay:
6431 10:55:08.326213 DQM0 = 11, DQM1 = 14
6432 10:55:08.329491 DQ Delay:
6433 10:55:08.332879 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6434 10:55:08.332962 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6435 10:55:08.335983 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6436 10:55:08.339381 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6437 10:55:08.339477
6438 10:55:08.342965
6439 10:55:08.349224 [DQSOSCAuto] RK0, (LSB)MR18= 0x7b48, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
6440 10:55:08.352744 CH0 RK0: MR19=C0C, MR18=7B48
6441 10:55:08.359230 CH0_RK0: MR19=0xC0C, MR18=0x7B48, DQSOSC=394, MR23=63, INC=380, DEC=253
6442 10:55:08.359314 ==
6443 10:55:08.362236 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 10:55:08.365653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 10:55:08.365737 ==
6446 10:55:08.369460 [Gating] SW mode calibration
6447 10:55:08.375663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6448 10:55:08.382234 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6449 10:55:08.385993 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 10:55:08.388561 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 10:55:08.395836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 10:55:08.398821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 10:55:08.402021 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 10:55:08.408796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 10:55:08.411970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 10:55:08.415462 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 10:55:08.421741 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 10:55:08.421827 Total UI for P1: 0, mck2ui 16
6459 10:55:08.428635 best dqsien dly found for B0: ( 0, 14, 24)
6460 10:55:08.428719 Total UI for P1: 0, mck2ui 16
6461 10:55:08.434842 best dqsien dly found for B1: ( 0, 14, 24)
6462 10:55:08.438178 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6463 10:55:08.442266 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6464 10:55:08.442349
6465 10:55:08.445170 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 10:55:08.448620 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 10:55:08.451907 [Gating] SW calibration Done
6468 10:55:08.451990 ==
6469 10:55:08.454781 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 10:55:08.458120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 10:55:08.458203 ==
6472 10:55:08.461805 RX Vref Scan: 0
6473 10:55:08.461887
6474 10:55:08.461951 RX Vref 0 -> 0, step: 1
6475 10:55:08.462011
6476 10:55:08.465476 RX Delay -410 -> 252, step: 16
6477 10:55:08.471932 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6478 10:55:08.474769 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6479 10:55:08.478284 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6480 10:55:08.481436 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6481 10:55:08.487854 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6482 10:55:08.491590 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6483 10:55:08.494598 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6484 10:55:08.498226 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6485 10:55:08.504513 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6486 10:55:08.508271 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6487 10:55:08.511674 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6488 10:55:08.514532 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6489 10:55:08.521583 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6490 10:55:08.524749 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6491 10:55:08.528248 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6492 10:55:08.534648 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6493 10:55:08.534730 ==
6494 10:55:08.537790 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 10:55:08.541011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 10:55:08.541094 ==
6497 10:55:08.541160 DQS Delay:
6498 10:55:08.544569 DQS0 = 43, DQS1 = 51
6499 10:55:08.544651 DQM Delay:
6500 10:55:08.548439 DQM0 = 11, DQM1 = 10
6501 10:55:08.548526 DQ Delay:
6502 10:55:08.550936 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6503 10:55:08.554368 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6504 10:55:08.557901 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6505 10:55:08.560716 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6506 10:55:08.560798
6507 10:55:08.560867
6508 10:55:08.560928 ==
6509 10:55:08.564133 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 10:55:08.567857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 10:55:08.567941 ==
6512 10:55:08.568007
6513 10:55:08.568068
6514 10:55:08.571025 TX Vref Scan disable
6515 10:55:08.571111 == TX Byte 0 ==
6516 10:55:08.577869 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6517 10:55:08.581541 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6518 10:55:08.581624 == TX Byte 1 ==
6519 10:55:08.587257 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6520 10:55:08.590766 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6521 10:55:08.590849 ==
6522 10:55:08.593808 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 10:55:08.597323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 10:55:08.597407 ==
6525 10:55:08.597472
6526 10:55:08.597532
6527 10:55:08.600863 TX Vref Scan disable
6528 10:55:08.600945 == TX Byte 0 ==
6529 10:55:08.607032 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6530 10:55:08.610730 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6531 10:55:08.610813 == TX Byte 1 ==
6532 10:55:08.616845 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6533 10:55:08.620205 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6534 10:55:08.620287
6535 10:55:08.620352 [DATLAT]
6536 10:55:08.623711 Freq=400, CH0 RK1
6537 10:55:08.623793
6538 10:55:08.623858 DATLAT Default: 0xe
6539 10:55:08.626860 0, 0xFFFF, sum = 0
6540 10:55:08.626944 1, 0xFFFF, sum = 0
6541 10:55:08.630244 2, 0xFFFF, sum = 0
6542 10:55:08.630327 3, 0xFFFF, sum = 0
6543 10:55:08.633569 4, 0xFFFF, sum = 0
6544 10:55:08.633653 5, 0xFFFF, sum = 0
6545 10:55:08.637113 6, 0xFFFF, sum = 0
6546 10:55:08.637196 7, 0xFFFF, sum = 0
6547 10:55:08.640750 8, 0xFFFF, sum = 0
6548 10:55:08.644302 9, 0xFFFF, sum = 0
6549 10:55:08.644414 10, 0xFFFF, sum = 0
6550 10:55:08.646687 11, 0xFFFF, sum = 0
6551 10:55:08.646771 12, 0xFFFF, sum = 0
6552 10:55:08.650357 13, 0x0, sum = 1
6553 10:55:08.650439 14, 0x0, sum = 2
6554 10:55:08.653567 15, 0x0, sum = 3
6555 10:55:08.653650 16, 0x0, sum = 4
6556 10:55:08.653716 best_step = 14
6557 10:55:08.657056
6558 10:55:08.657138 ==
6559 10:55:08.659978 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 10:55:08.663395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 10:55:08.663492 ==
6562 10:55:08.663558 RX Vref Scan: 0
6563 10:55:08.663618
6564 10:55:08.666896 RX Vref 0 -> 0, step: 1
6565 10:55:08.666978
6566 10:55:08.669917 RX Delay -343 -> 252, step: 8
6567 10:55:08.677221 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6568 10:55:08.680850 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6569 10:55:08.684046 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6570 10:55:08.690711 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6571 10:55:08.693858 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6572 10:55:08.697358 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6573 10:55:08.700515 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6574 10:55:08.707029 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6575 10:55:08.710530 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6576 10:55:08.713549 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6577 10:55:08.716790 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6578 10:55:08.723288 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6579 10:55:08.726859 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6580 10:55:08.730399 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6581 10:55:08.733253 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6582 10:55:08.739822 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6583 10:55:08.739905 ==
6584 10:55:08.743132 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 10:55:08.747124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 10:55:08.747208 ==
6587 10:55:08.747274 DQS Delay:
6588 10:55:08.749832 DQS0 = 48, DQS1 = 60
6589 10:55:08.749914 DQM Delay:
6590 10:55:08.753218 DQM0 = 13, DQM1 = 13
6591 10:55:08.753301 DQ Delay:
6592 10:55:08.756794 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6593 10:55:08.760043 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6594 10:55:08.763022 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6595 10:55:08.766423 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6596 10:55:08.766505
6597 10:55:08.766571
6598 10:55:08.773202 [DQSOSCAuto] RK1, (LSB)MR18= 0x9769, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6599 10:55:08.776775 CH0 RK1: MR19=C0C, MR18=9769
6600 10:55:08.783509 CH0_RK1: MR19=0xC0C, MR18=0x9769, DQSOSC=390, MR23=63, INC=388, DEC=258
6601 10:55:08.786497 [RxdqsGatingPostProcess] freq 400
6602 10:55:08.793206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6603 10:55:08.796722 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 10:55:08.799746 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 10:55:08.802972 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 10:55:08.803054 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 10:55:08.806666 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 10:55:08.809844 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 10:55:08.813165 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 10:55:08.816734 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 10:55:08.819732 Pre-setting of DQS Precalculation
6612 10:55:08.826433 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6613 10:55:08.826516 ==
6614 10:55:08.829907 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 10:55:08.832727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 10:55:08.832810 ==
6617 10:55:08.839299 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 10:55:08.846498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6619 10:55:08.849226 [CA 0] Center 36 (8~64) winsize 57
6620 10:55:08.849309 [CA 1] Center 36 (8~64) winsize 57
6621 10:55:08.853032 [CA 2] Center 36 (8~64) winsize 57
6622 10:55:08.856194 [CA 3] Center 36 (8~64) winsize 57
6623 10:55:08.859480 [CA 4] Center 36 (8~64) winsize 57
6624 10:55:08.862393 [CA 5] Center 36 (8~64) winsize 57
6625 10:55:08.862475
6626 10:55:08.865898 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6627 10:55:08.865981
6628 10:55:08.869226 [CATrainingPosCal] consider 1 rank data
6629 10:55:08.872791 u2DelayCellTimex100 = 270/100 ps
6630 10:55:08.875572 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:55:08.882732 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:55:08.885485 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 10:55:08.888965 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 10:55:08.892594 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 10:55:08.895595 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 10:55:08.895679
6637 10:55:08.898910 CA PerBit enable=1, Macro0, CA PI delay=36
6638 10:55:08.898995
6639 10:55:08.902645 [CBTSetCACLKResult] CA Dly = 36
6640 10:55:08.905529 CS Dly: 1 (0~32)
6641 10:55:08.905613 ==
6642 10:55:08.908638 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 10:55:08.912443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 10:55:08.912538 ==
6645 10:55:08.918660 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 10:55:08.921991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6647 10:55:08.925286 [CA 0] Center 36 (8~64) winsize 57
6648 10:55:08.928945 [CA 1] Center 36 (8~64) winsize 57
6649 10:55:08.932245 [CA 2] Center 36 (8~64) winsize 57
6650 10:55:08.935616 [CA 3] Center 36 (8~64) winsize 57
6651 10:55:08.938438 [CA 4] Center 36 (8~64) winsize 57
6652 10:55:08.941760 [CA 5] Center 36 (8~64) winsize 57
6653 10:55:08.941850
6654 10:55:08.945218 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6655 10:55:08.945305
6656 10:55:08.948595 [CATrainingPosCal] consider 2 rank data
6657 10:55:08.951922 u2DelayCellTimex100 = 270/100 ps
6658 10:55:08.955285 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 10:55:08.959112 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 10:55:08.962316 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 10:55:08.965322 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 10:55:08.972161 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 10:55:08.975014 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 10:55:08.975106
6665 10:55:08.978442 CA PerBit enable=1, Macro0, CA PI delay=36
6666 10:55:08.978527
6667 10:55:08.982500 [CBTSetCACLKResult] CA Dly = 36
6668 10:55:08.982589 CS Dly: 1 (0~32)
6669 10:55:08.982676
6670 10:55:08.985931 ----->DramcWriteLeveling(PI) begin...
6671 10:55:08.986017 ==
6672 10:55:08.988607 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 10:55:08.995017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 10:55:08.995104 ==
6675 10:55:08.998775 Write leveling (Byte 0): 40 => 8
6676 10:55:08.998861 Write leveling (Byte 1): 40 => 8
6677 10:55:09.001449 DramcWriteLeveling(PI) end<-----
6678 10:55:09.001533
6679 10:55:09.005567 ==
6680 10:55:09.008371 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 10:55:09.011945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 10:55:09.012032 ==
6683 10:55:09.014821 [Gating] SW mode calibration
6684 10:55:09.021931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6685 10:55:09.025326 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6686 10:55:09.031879 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6687 10:55:09.035052 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 10:55:09.038537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 10:55:09.044796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 10:55:09.048226 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 10:55:09.051929 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 10:55:09.058479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 10:55:09.061733 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 10:55:09.064991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 10:55:09.068495 Total UI for P1: 0, mck2ui 16
6696 10:55:09.071755 best dqsien dly found for B0: ( 0, 14, 24)
6697 10:55:09.074728 Total UI for P1: 0, mck2ui 16
6698 10:55:09.078084 best dqsien dly found for B1: ( 0, 14, 24)
6699 10:55:09.081634 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6700 10:55:09.084666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6701 10:55:09.084748
6702 10:55:09.088058 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 10:55:09.094902 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 10:55:09.094988 [Gating] SW calibration Done
6705 10:55:09.098571 ==
6706 10:55:09.098653 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 10:55:09.104611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 10:55:09.104694 ==
6709 10:55:09.104759 RX Vref Scan: 0
6710 10:55:09.104819
6711 10:55:09.108115 RX Vref 0 -> 0, step: 1
6712 10:55:09.108197
6713 10:55:09.111145 RX Delay -410 -> 252, step: 16
6714 10:55:09.114663 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6715 10:55:09.118327 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6716 10:55:09.124684 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6717 10:55:09.127809 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6718 10:55:09.131327 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6719 10:55:09.134558 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6720 10:55:09.141151 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6721 10:55:09.144701 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6722 10:55:09.147646 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6723 10:55:09.151151 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6724 10:55:09.157984 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6725 10:55:09.161288 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6726 10:55:09.164073 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6727 10:55:09.171064 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6728 10:55:09.174430 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6729 10:55:09.177435 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6730 10:55:09.177523 ==
6731 10:55:09.181090 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 10:55:09.184259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 10:55:09.184369 ==
6734 10:55:09.187598 DQS Delay:
6735 10:55:09.187701 DQS0 = 43, DQS1 = 59
6736 10:55:09.190830 DQM Delay:
6737 10:55:09.190903 DQM0 = 12, DQM1 = 16
6738 10:55:09.194032 DQ Delay:
6739 10:55:09.194102 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6740 10:55:09.197358 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6741 10:55:09.200646 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6742 10:55:09.203957 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6743 10:55:09.204039
6744 10:55:09.204104
6745 10:55:09.207423 ==
6746 10:55:09.207544 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 10:55:09.213825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 10:55:09.213909 ==
6749 10:55:09.213974
6750 10:55:09.214034
6751 10:55:09.217408 TX Vref Scan disable
6752 10:55:09.217490 == TX Byte 0 ==
6753 10:55:09.220453 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 10:55:09.224029 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 10:55:09.227296 == TX Byte 1 ==
6756 10:55:09.230652 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 10:55:09.233722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 10:55:09.237412 ==
6759 10:55:09.237494 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 10:55:09.243868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 10:55:09.243951 ==
6762 10:55:09.244016
6763 10:55:09.244077
6764 10:55:09.247382 TX Vref Scan disable
6765 10:55:09.247479 == TX Byte 0 ==
6766 10:55:09.250404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 10:55:09.257077 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 10:55:09.257160 == TX Byte 1 ==
6769 10:55:09.260600 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 10:55:09.263899 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 10:55:09.267132
6772 10:55:09.267229 [DATLAT]
6773 10:55:09.267295 Freq=400, CH1 RK0
6774 10:55:09.267367
6775 10:55:09.270600 DATLAT Default: 0xf
6776 10:55:09.270681 0, 0xFFFF, sum = 0
6777 10:55:09.274101 1, 0xFFFF, sum = 0
6778 10:55:09.274185 2, 0xFFFF, sum = 0
6779 10:55:09.276908 3, 0xFFFF, sum = 0
6780 10:55:09.276990 4, 0xFFFF, sum = 0
6781 10:55:09.280590 5, 0xFFFF, sum = 0
6782 10:55:09.284157 6, 0xFFFF, sum = 0
6783 10:55:09.284240 7, 0xFFFF, sum = 0
6784 10:55:09.286886 8, 0xFFFF, sum = 0
6785 10:55:09.286967 9, 0xFFFF, sum = 0
6786 10:55:09.290230 10, 0xFFFF, sum = 0
6787 10:55:09.290313 11, 0xFFFF, sum = 0
6788 10:55:09.293674 12, 0xFFFF, sum = 0
6789 10:55:09.293760 13, 0x0, sum = 1
6790 10:55:09.297031 14, 0x0, sum = 2
6791 10:55:09.297122 15, 0x0, sum = 3
6792 10:55:09.300255 16, 0x0, sum = 4
6793 10:55:09.300361 best_step = 14
6794 10:55:09.300441
6795 10:55:09.300532 ==
6796 10:55:09.303812 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 10:55:09.307173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 10:55:09.307258 ==
6799 10:55:09.310526 RX Vref Scan: 1
6800 10:55:09.310609
6801 10:55:09.313555 RX Vref 0 -> 0, step: 1
6802 10:55:09.313639
6803 10:55:09.313704 RX Delay -359 -> 252, step: 8
6804 10:55:09.317464
6805 10:55:09.317546 Set Vref, RX VrefLevel [Byte0]: 57
6806 10:55:09.320276 [Byte1]: 54
6807 10:55:09.325679
6808 10:55:09.325761 Final RX Vref Byte 0 = 57 to rank0
6809 10:55:09.329101 Final RX Vref Byte 1 = 54 to rank0
6810 10:55:09.332425 Final RX Vref Byte 0 = 57 to rank1
6811 10:55:09.335881 Final RX Vref Byte 1 = 54 to rank1==
6812 10:55:09.339697 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 10:55:09.345501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 10:55:09.345584 ==
6815 10:55:09.345651 DQS Delay:
6816 10:55:09.348809 DQS0 = 48, DQS1 = 60
6817 10:55:09.348891 DQM Delay:
6818 10:55:09.348957 DQM0 = 12, DQM1 = 13
6819 10:55:09.352737 DQ Delay:
6820 10:55:09.355712 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6821 10:55:09.359278 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =4
6822 10:55:09.359367 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6823 10:55:09.362451 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6824 10:55:09.365449
6825 10:55:09.365531
6826 10:55:09.372051 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d34, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6827 10:55:09.375638 CH1 RK0: MR19=C0C, MR18=8D34
6828 10:55:09.382037 CH1_RK0: MR19=0xC0C, MR18=0x8D34, DQSOSC=392, MR23=63, INC=384, DEC=256
6829 10:55:09.382121 ==
6830 10:55:09.385679 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 10:55:09.389133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 10:55:09.389217 ==
6833 10:55:09.392458 [Gating] SW mode calibration
6834 10:55:09.398565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6835 10:55:09.405479 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6836 10:55:09.408439 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6837 10:55:09.411973 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6838 10:55:09.419213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 10:55:09.422233 0 12 16 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
6840 10:55:09.425259 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 10:55:09.431829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 10:55:09.435214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 10:55:09.438497 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 10:55:09.445182 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 10:55:09.445268 Total UI for P1: 0, mck2ui 16
6846 10:55:09.449370 best dqsien dly found for B0: ( 0, 14, 24)
6847 10:55:09.451681 Total UI for P1: 0, mck2ui 16
6848 10:55:09.455244 best dqsien dly found for B1: ( 0, 14, 24)
6849 10:55:09.462075 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6850 10:55:09.465310 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6851 10:55:09.465393
6852 10:55:09.468060 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 10:55:09.471948 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 10:55:09.475069 [Gating] SW calibration Done
6855 10:55:09.475151 ==
6856 10:55:09.478579 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 10:55:09.481826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 10:55:09.481909 ==
6859 10:55:09.485733 RX Vref Scan: 0
6860 10:55:09.485814
6861 10:55:09.485879 RX Vref 0 -> 0, step: 1
6862 10:55:09.485939
6863 10:55:09.488552 RX Delay -410 -> 252, step: 16
6864 10:55:09.494893 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6865 10:55:09.498299 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6866 10:55:09.501771 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6867 10:55:09.505298 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6868 10:55:09.508223 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6869 10:55:09.514939 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6870 10:55:09.518272 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6871 10:55:09.521693 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6872 10:55:09.525410 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6873 10:55:09.531794 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6874 10:55:09.534571 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6875 10:55:09.538054 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6876 10:55:09.544942 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6877 10:55:09.547820 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6878 10:55:09.551136 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6879 10:55:09.554935 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6880 10:55:09.555018 ==
6881 10:55:09.558439 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 10:55:09.564592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 10:55:09.564675 ==
6884 10:55:09.564740 DQS Delay:
6885 10:55:09.568182 DQS0 = 43, DQS1 = 59
6886 10:55:09.568264 DQM Delay:
6887 10:55:09.571233 DQM0 = 9, DQM1 = 18
6888 10:55:09.571315 DQ Delay:
6889 10:55:09.574671 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6890 10:55:09.577798 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6891 10:55:09.577880 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6892 10:55:09.581311 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =32
6893 10:55:09.584352
6894 10:55:09.584433
6895 10:55:09.584499 ==
6896 10:55:09.587630 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 10:55:09.591014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 10:55:09.591097 ==
6899 10:55:09.591162
6900 10:55:09.591224
6901 10:55:09.594371 TX Vref Scan disable
6902 10:55:09.594453 == TX Byte 0 ==
6903 10:55:09.598151 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6904 10:55:09.604534 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6905 10:55:09.604626 == TX Byte 1 ==
6906 10:55:09.607916 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6907 10:55:09.614618 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6908 10:55:09.614703 ==
6909 10:55:09.618278 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 10:55:09.621104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 10:55:09.621187 ==
6912 10:55:09.621253
6913 10:55:09.621314
6914 10:55:09.624378 TX Vref Scan disable
6915 10:55:09.624459 == TX Byte 0 ==
6916 10:55:09.628328 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6917 10:55:09.634746 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6918 10:55:09.634827 == TX Byte 1 ==
6919 10:55:09.637475 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6920 10:55:09.644226 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6921 10:55:09.644308
6922 10:55:09.644372 [DATLAT]
6923 10:55:09.644430 Freq=400, CH1 RK1
6924 10:55:09.647855
6925 10:55:09.647936 DATLAT Default: 0xe
6926 10:55:09.650856 0, 0xFFFF, sum = 0
6927 10:55:09.650938 1, 0xFFFF, sum = 0
6928 10:55:09.654024 2, 0xFFFF, sum = 0
6929 10:55:09.654107 3, 0xFFFF, sum = 0
6930 10:55:09.657640 4, 0xFFFF, sum = 0
6931 10:55:09.657726 5, 0xFFFF, sum = 0
6932 10:55:09.660966 6, 0xFFFF, sum = 0
6933 10:55:09.661051 7, 0xFFFF, sum = 0
6934 10:55:09.664619 8, 0xFFFF, sum = 0
6935 10:55:09.664704 9, 0xFFFF, sum = 0
6936 10:55:09.667705 10, 0xFFFF, sum = 0
6937 10:55:09.667804 11, 0xFFFF, sum = 0
6938 10:55:09.670898 12, 0xFFFF, sum = 0
6939 10:55:09.670982 13, 0x0, sum = 1
6940 10:55:09.674380 14, 0x0, sum = 2
6941 10:55:09.674465 15, 0x0, sum = 3
6942 10:55:09.677226 16, 0x0, sum = 4
6943 10:55:09.677310 best_step = 14
6944 10:55:09.677376
6945 10:55:09.677439 ==
6946 10:55:09.680978 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 10:55:09.687211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 10:55:09.687295 ==
6949 10:55:09.687387 RX Vref Scan: 0
6950 10:55:09.687493
6951 10:55:09.690922 RX Vref 0 -> 0, step: 1
6952 10:55:09.691005
6953 10:55:09.694041 RX Delay -359 -> 252, step: 8
6954 10:55:09.700713 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6955 10:55:09.703628 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6956 10:55:09.706929 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6957 10:55:09.710582 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6958 10:55:09.717256 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6959 10:55:09.720259 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6960 10:55:09.723563 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6961 10:55:09.726910 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6962 10:55:09.733680 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6963 10:55:09.737172 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6964 10:55:09.740406 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6965 10:55:09.744157 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6966 10:55:09.750552 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6967 10:55:09.754041 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6968 10:55:09.756956 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6969 10:55:09.764333 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6970 10:55:09.764416 ==
6971 10:55:09.766851 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 10:55:09.770118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 10:55:09.770201 ==
6974 10:55:09.770268 DQS Delay:
6975 10:55:09.773332 DQS0 = 48, DQS1 = 56
6976 10:55:09.773415 DQM Delay:
6977 10:55:09.776664 DQM0 = 9, DQM1 = 9
6978 10:55:09.776747 DQ Delay:
6979 10:55:09.780671 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6980 10:55:09.783308 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6981 10:55:09.786432 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6982 10:55:09.790305 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6983 10:55:09.790387
6984 10:55:09.790453
6985 10:55:09.796621 [DQSOSCAuto] RK1, (LSB)MR18= 0x7186, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6986 10:55:09.799925 CH1 RK1: MR19=C0C, MR18=7186
6987 10:55:09.806576 CH1_RK1: MR19=0xC0C, MR18=0x7186, DQSOSC=393, MR23=63, INC=382, DEC=254
6988 10:55:09.809728 [RxdqsGatingPostProcess] freq 400
6989 10:55:09.814026 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6990 10:55:09.816691 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 10:55:09.820219 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 10:55:09.823230 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 10:55:09.826694 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 10:55:09.830084 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 10:55:09.833466 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 10:55:09.836683 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 10:55:09.839685 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 10:55:09.843136 Pre-setting of DQS Precalculation
6999 10:55:09.846723 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7000 10:55:09.856827 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7001 10:55:09.863030 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7002 10:55:09.863113
7003 10:55:09.863179
7004 10:55:09.866411 [Calibration Summary] 800 Mbps
7005 10:55:09.866494 CH 0, Rank 0
7006 10:55:09.869917 SW Impedance : PASS
7007 10:55:09.870000 DUTY Scan : NO K
7008 10:55:09.873128 ZQ Calibration : PASS
7009 10:55:09.876037 Jitter Meter : NO K
7010 10:55:09.876120 CBT Training : PASS
7011 10:55:09.879263 Write leveling : PASS
7012 10:55:09.882631 RX DQS gating : PASS
7013 10:55:09.882714 RX DQ/DQS(RDDQC) : PASS
7014 10:55:09.885893 TX DQ/DQS : PASS
7015 10:55:09.889599 RX DATLAT : PASS
7016 10:55:09.889682 RX DQ/DQS(Engine): PASS
7017 10:55:09.892888 TX OE : NO K
7018 10:55:09.892970 All Pass.
7019 10:55:09.893036
7020 10:55:09.895728 CH 0, Rank 1
7021 10:55:09.895837 SW Impedance : PASS
7022 10:55:09.899599 DUTY Scan : NO K
7023 10:55:09.902915 ZQ Calibration : PASS
7024 10:55:09.902996 Jitter Meter : NO K
7025 10:55:09.906078 CBT Training : PASS
7026 10:55:09.909170 Write leveling : NO K
7027 10:55:09.909252 RX DQS gating : PASS
7028 10:55:09.912632 RX DQ/DQS(RDDQC) : PASS
7029 10:55:09.912714 TX DQ/DQS : PASS
7030 10:55:09.916029 RX DATLAT : PASS
7031 10:55:09.919183 RX DQ/DQS(Engine): PASS
7032 10:55:09.919265 TX OE : NO K
7033 10:55:09.922689 All Pass.
7034 10:55:09.922773
7035 10:55:09.922837 CH 1, Rank 0
7036 10:55:09.926211 SW Impedance : PASS
7037 10:55:09.926293 DUTY Scan : NO K
7038 10:55:09.928825 ZQ Calibration : PASS
7039 10:55:09.932195 Jitter Meter : NO K
7040 10:55:09.932276 CBT Training : PASS
7041 10:55:09.935864 Write leveling : PASS
7042 10:55:09.938852 RX DQS gating : PASS
7043 10:55:09.938934 RX DQ/DQS(RDDQC) : PASS
7044 10:55:09.942769 TX DQ/DQS : PASS
7045 10:55:09.945449 RX DATLAT : PASS
7046 10:55:09.945556 RX DQ/DQS(Engine): PASS
7047 10:55:09.949104 TX OE : NO K
7048 10:55:09.949211 All Pass.
7049 10:55:09.949303
7050 10:55:09.952442 CH 1, Rank 1
7051 10:55:09.952525 SW Impedance : PASS
7052 10:55:09.955620 DUTY Scan : NO K
7053 10:55:09.958981 ZQ Calibration : PASS
7054 10:55:09.959088 Jitter Meter : NO K
7055 10:55:09.962057 CBT Training : PASS
7056 10:55:09.965403 Write leveling : NO K
7057 10:55:09.965520 RX DQS gating : PASS
7058 10:55:09.968844 RX DQ/DQS(RDDQC) : PASS
7059 10:55:09.968928 TX DQ/DQS : PASS
7060 10:55:09.972534 RX DATLAT : PASS
7061 10:55:09.975731 RX DQ/DQS(Engine): PASS
7062 10:55:09.975825 TX OE : NO K
7063 10:55:09.978612 All Pass.
7064 10:55:09.978696
7065 10:55:09.978780 DramC Write-DBI off
7066 10:55:09.982084 PER_BANK_REFRESH: Hybrid Mode
7067 10:55:09.985441 TX_TRACKING: ON
7068 10:55:09.992334 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7069 10:55:09.995282 [FAST_K] Save calibration result to emmc
7070 10:55:09.998562 dramc_set_vcore_voltage set vcore to 725000
7071 10:55:10.002240 Read voltage for 1600, 0
7072 10:55:10.002323 Vio18 = 0
7073 10:55:10.005361 Vcore = 725000
7074 10:55:10.005444 Vdram = 0
7075 10:55:10.005528 Vddq = 0
7076 10:55:10.008730 Vmddr = 0
7077 10:55:10.012539 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7078 10:55:10.018858 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7079 10:55:10.018943 MEM_TYPE=3, freq_sel=13
7080 10:55:10.022167 sv_algorithm_assistance_LP4_3733
7081 10:55:10.029100 ============ PULL DRAM RESETB DOWN ============
7082 10:55:10.031880 ========== PULL DRAM RESETB DOWN end =========
7083 10:55:10.035326 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7084 10:55:10.038641 ===================================
7085 10:55:10.041873 LPDDR4 DRAM CONFIGURATION
7086 10:55:10.045505 ===================================
7087 10:55:10.048744 EX_ROW_EN[0] = 0x0
7088 10:55:10.048827 EX_ROW_EN[1] = 0x0
7089 10:55:10.052051 LP4Y_EN = 0x0
7090 10:55:10.052142 WORK_FSP = 0x1
7091 10:55:10.055301 WL = 0x5
7092 10:55:10.055402 RL = 0x5
7093 10:55:10.058652 BL = 0x2
7094 10:55:10.058746 RPST = 0x0
7095 10:55:10.061893 RD_PRE = 0x0
7096 10:55:10.061976 WR_PRE = 0x1
7097 10:55:10.064907 WR_PST = 0x1
7098 10:55:10.064992 DBI_WR = 0x0
7099 10:55:10.068325 DBI_RD = 0x0
7100 10:55:10.068408 OTF = 0x1
7101 10:55:10.071726 ===================================
7102 10:55:10.074927 ===================================
7103 10:55:10.078687 ANA top config
7104 10:55:10.081481 ===================================
7105 10:55:10.084868 DLL_ASYNC_EN = 0
7106 10:55:10.084952 ALL_SLAVE_EN = 0
7107 10:55:10.088206 NEW_RANK_MODE = 1
7108 10:55:10.091593 DLL_IDLE_MODE = 1
7109 10:55:10.095145 LP45_APHY_COMB_EN = 1
7110 10:55:10.095229 TX_ODT_DIS = 0
7111 10:55:10.098375 NEW_8X_MODE = 1
7112 10:55:10.101516 ===================================
7113 10:55:10.104670 ===================================
7114 10:55:10.108443 data_rate = 3200
7115 10:55:10.111618 CKR = 1
7116 10:55:10.114863 DQ_P2S_RATIO = 8
7117 10:55:10.118483 ===================================
7118 10:55:10.121863 CA_P2S_RATIO = 8
7119 10:55:10.121944 DQ_CA_OPEN = 0
7120 10:55:10.124525 DQ_SEMI_OPEN = 0
7121 10:55:10.128092 CA_SEMI_OPEN = 0
7122 10:55:10.131501 CA_FULL_RATE = 0
7123 10:55:10.134740 DQ_CKDIV4_EN = 0
7124 10:55:10.138003 CA_CKDIV4_EN = 0
7125 10:55:10.138084 CA_PREDIV_EN = 0
7126 10:55:10.141670 PH8_DLY = 12
7127 10:55:10.145206 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7128 10:55:10.147909 DQ_AAMCK_DIV = 4
7129 10:55:10.151469 CA_AAMCK_DIV = 4
7130 10:55:10.154818 CA_ADMCK_DIV = 4
7131 10:55:10.154899 DQ_TRACK_CA_EN = 0
7132 10:55:10.158154 CA_PICK = 1600
7133 10:55:10.161544 CA_MCKIO = 1600
7134 10:55:10.164677 MCKIO_SEMI = 0
7135 10:55:10.168306 PLL_FREQ = 3068
7136 10:55:10.171141 DQ_UI_PI_RATIO = 32
7137 10:55:10.174465 CA_UI_PI_RATIO = 0
7138 10:55:10.177666 ===================================
7139 10:55:10.181115 ===================================
7140 10:55:10.181197 memory_type:LPDDR4
7141 10:55:10.184354 GP_NUM : 10
7142 10:55:10.187659 SRAM_EN : 1
7143 10:55:10.187740 MD32_EN : 0
7144 10:55:10.191147 ===================================
7145 10:55:10.194831 [ANA_INIT] >>>>>>>>>>>>>>
7146 10:55:10.197602 <<<<<< [CONFIGURE PHASE]: ANA_TX
7147 10:55:10.201089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7148 10:55:10.204132 ===================================
7149 10:55:10.207499 data_rate = 3200,PCW = 0X7600
7150 10:55:10.211107 ===================================
7151 10:55:10.214331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7152 10:55:10.217428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 10:55:10.224396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 10:55:10.227739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7155 10:55:10.230841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7156 10:55:10.237158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7157 10:55:10.237243 [ANA_INIT] flow start
7158 10:55:10.240809 [ANA_INIT] PLL >>>>>>>>
7159 10:55:10.244151 [ANA_INIT] PLL <<<<<<<<
7160 10:55:10.244233 [ANA_INIT] MIDPI >>>>>>>>
7161 10:55:10.247060 [ANA_INIT] MIDPI <<<<<<<<
7162 10:55:10.250539 [ANA_INIT] DLL >>>>>>>>
7163 10:55:10.250621 [ANA_INIT] DLL <<<<<<<<
7164 10:55:10.254366 [ANA_INIT] flow end
7165 10:55:10.256925 ============ LP4 DIFF to SE enter ============
7166 10:55:10.260430 ============ LP4 DIFF to SE exit ============
7167 10:55:10.263913 [ANA_INIT] <<<<<<<<<<<<<
7168 10:55:10.267213 [Flow] Enable top DCM control >>>>>
7169 10:55:10.270483 [Flow] Enable top DCM control <<<<<
7170 10:55:10.273612 Enable DLL master slave shuffle
7171 10:55:10.280574 ==============================================================
7172 10:55:10.280655 Gating Mode config
7173 10:55:10.287284 ==============================================================
7174 10:55:10.287406 Config description:
7175 10:55:10.297029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7176 10:55:10.303615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7177 10:55:10.309988 SELPH_MODE 0: By rank 1: By Phase
7178 10:55:10.313542 ==============================================================
7179 10:55:10.316701 GAT_TRACK_EN = 1
7180 10:55:10.320365 RX_GATING_MODE = 2
7181 10:55:10.323529 RX_GATING_TRACK_MODE = 2
7182 10:55:10.326674 SELPH_MODE = 1
7183 10:55:10.330069 PICG_EARLY_EN = 1
7184 10:55:10.333613 VALID_LAT_VALUE = 1
7185 10:55:10.339981 ==============================================================
7186 10:55:10.343164 Enter into Gating configuration >>>>
7187 10:55:10.346618 Exit from Gating configuration <<<<
7188 10:55:10.349941 Enter into DVFS_PRE_config >>>>>
7189 10:55:10.359695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7190 10:55:10.363376 Exit from DVFS_PRE_config <<<<<
7191 10:55:10.366502 Enter into PICG configuration >>>>
7192 10:55:10.369893 Exit from PICG configuration <<<<
7193 10:55:10.372936 [RX_INPUT] configuration >>>>>
7194 10:55:10.373019 [RX_INPUT] configuration <<<<<
7195 10:55:10.379778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7196 10:55:10.386601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7197 10:55:10.389731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 10:55:10.396442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 10:55:10.403309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 10:55:10.409769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 10:55:10.412714 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7202 10:55:10.416088 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7203 10:55:10.422843 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7204 10:55:10.426028 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7205 10:55:10.429559 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7206 10:55:10.436556 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 10:55:10.439280 ===================================
7208 10:55:10.439403 LPDDR4 DRAM CONFIGURATION
7209 10:55:10.443255 ===================================
7210 10:55:10.446275 EX_ROW_EN[0] = 0x0
7211 10:55:10.446358 EX_ROW_EN[1] = 0x0
7212 10:55:10.450016 LP4Y_EN = 0x0
7213 10:55:10.450099 WORK_FSP = 0x1
7214 10:55:10.452776 WL = 0x5
7215 10:55:10.452859 RL = 0x5
7216 10:55:10.456031 BL = 0x2
7217 10:55:10.459607 RPST = 0x0
7218 10:55:10.459689 RD_PRE = 0x0
7219 10:55:10.463469 WR_PRE = 0x1
7220 10:55:10.463552 WR_PST = 0x1
7221 10:55:10.465831 DBI_WR = 0x0
7222 10:55:10.465913 DBI_RD = 0x0
7223 10:55:10.469711 OTF = 0x1
7224 10:55:10.472952 ===================================
7225 10:55:10.476735 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7226 10:55:10.479303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7227 10:55:10.482737 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 10:55:10.486069 ===================================
7229 10:55:10.489338 LPDDR4 DRAM CONFIGURATION
7230 10:55:10.492461 ===================================
7231 10:55:10.495956 EX_ROW_EN[0] = 0x10
7232 10:55:10.496039 EX_ROW_EN[1] = 0x0
7233 10:55:10.499215 LP4Y_EN = 0x0
7234 10:55:10.499298 WORK_FSP = 0x1
7235 10:55:10.502353 WL = 0x5
7236 10:55:10.502435 RL = 0x5
7237 10:55:10.506179 BL = 0x2
7238 10:55:10.506261 RPST = 0x0
7239 10:55:10.509015 RD_PRE = 0x0
7240 10:55:10.509098 WR_PRE = 0x1
7241 10:55:10.512592 WR_PST = 0x1
7242 10:55:10.515730 DBI_WR = 0x0
7243 10:55:10.515813 DBI_RD = 0x0
7244 10:55:10.518948 OTF = 0x1
7245 10:55:10.522250 ===================================
7246 10:55:10.525554 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7247 10:55:10.529080 ==
7248 10:55:10.532069 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 10:55:10.535813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7250 10:55:10.535897 ==
7251 10:55:10.539329 [Duty_Offset_Calibration]
7252 10:55:10.539449 B0:2 B1:-1 CA:1
7253 10:55:10.539516
7254 10:55:10.542173 [DutyScan_Calibration_Flow] k_type=0
7255 10:55:10.551330
7256 10:55:10.551457 ==CLK 0==
7257 10:55:10.554582 Final CLK duty delay cell = -4
7258 10:55:10.557913 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7259 10:55:10.561066 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7260 10:55:10.564280 [-4] AVG Duty = 4937%(X100)
7261 10:55:10.564363
7262 10:55:10.567968 CH0 CLK Duty spec in!! Max-Min= 187%
7263 10:55:10.571567 [DutyScan_Calibration_Flow] ====Done====
7264 10:55:10.571650
7265 10:55:10.574289 [DutyScan_Calibration_Flow] k_type=1
7266 10:55:10.590843
7267 10:55:10.590924 ==DQS 0 ==
7268 10:55:10.594202 Final DQS duty delay cell = 0
7269 10:55:10.597809 [0] MAX Duty = 5125%(X100), DQS PI = 20
7270 10:55:10.600714 [0] MIN Duty = 5031%(X100), DQS PI = 12
7271 10:55:10.604568 [0] AVG Duty = 5078%(X100)
7272 10:55:10.604650
7273 10:55:10.604714 ==DQS 1 ==
7274 10:55:10.607243 Final DQS duty delay cell = -4
7275 10:55:10.611009 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7276 10:55:10.613977 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7277 10:55:10.617254 [-4] AVG Duty = 5046%(X100)
7278 10:55:10.617337
7279 10:55:10.620748 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7280 10:55:10.620830
7281 10:55:10.624282 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7282 10:55:10.627677 [DutyScan_Calibration_Flow] ====Done====
7283 10:55:10.627762
7284 10:55:10.630390 [DutyScan_Calibration_Flow] k_type=3
7285 10:55:10.648159
7286 10:55:10.648253 ==DQM 0 ==
7287 10:55:10.651251 Final DQM duty delay cell = 0
7288 10:55:10.654693 [0] MAX Duty = 5000%(X100), DQS PI = 18
7289 10:55:10.658371 [0] MIN Duty = 4875%(X100), DQS PI = 4
7290 10:55:10.661223 [0] AVG Duty = 4937%(X100)
7291 10:55:10.661308
7292 10:55:10.661391 ==DQM 1 ==
7293 10:55:10.665095 Final DQM duty delay cell = 0
7294 10:55:10.667737 [0] MAX Duty = 5218%(X100), DQS PI = 58
7295 10:55:10.671061 [0] MIN Duty = 4969%(X100), DQS PI = 20
7296 10:55:10.674495 [0] AVG Duty = 5093%(X100)
7297 10:55:10.674574
7298 10:55:10.677711 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7299 10:55:10.677790
7300 10:55:10.681351 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7301 10:55:10.684747 [DutyScan_Calibration_Flow] ====Done====
7302 10:55:10.684827
7303 10:55:10.687682 [DutyScan_Calibration_Flow] k_type=2
7304 10:55:10.704269
7305 10:55:10.704349 ==DQ 0 ==
7306 10:55:10.707524 Final DQ duty delay cell = -4
7307 10:55:10.710785 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7308 10:55:10.714239 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7309 10:55:10.717723 [-4] AVG Duty = 4937%(X100)
7310 10:55:10.717803
7311 10:55:10.717865 ==DQ 1 ==
7312 10:55:10.721055 Final DQ duty delay cell = 0
7313 10:55:10.724641 [0] MAX Duty = 5031%(X100), DQS PI = 30
7314 10:55:10.727622 [0] MIN Duty = 4907%(X100), DQS PI = 26
7315 10:55:10.731169 [0] AVG Duty = 4969%(X100)
7316 10:55:10.731249
7317 10:55:10.734004 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7318 10:55:10.734083
7319 10:55:10.737745 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7320 10:55:10.740719 [DutyScan_Calibration_Flow] ====Done====
7321 10:55:10.740800 ==
7322 10:55:10.743967 Dram Type= 6, Freq= 0, CH_1, rank 0
7323 10:55:10.747159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 10:55:10.747241 ==
7325 10:55:10.750541 [Duty_Offset_Calibration]
7326 10:55:10.750622 B0:1 B1:1 CA:2
7327 10:55:10.750686
7328 10:55:10.754055 [DutyScan_Calibration_Flow] k_type=0
7329 10:55:10.764936
7330 10:55:10.765021 ==CLK 0==
7331 10:55:10.768396 Final CLK duty delay cell = 0
7332 10:55:10.771500 [0] MAX Duty = 5187%(X100), DQS PI = 24
7333 10:55:10.774552 [0] MIN Duty = 4938%(X100), DQS PI = 50
7334 10:55:10.774633 [0] AVG Duty = 5062%(X100)
7335 10:55:10.778228
7336 10:55:10.781770 CH1 CLK Duty spec in!! Max-Min= 249%
7337 10:55:10.784683 [DutyScan_Calibration_Flow] ====Done====
7338 10:55:10.784763
7339 10:55:10.788076 [DutyScan_Calibration_Flow] k_type=1
7340 10:55:10.804788
7341 10:55:10.804867 ==DQS 0 ==
7342 10:55:10.807938 Final DQS duty delay cell = 0
7343 10:55:10.811280 [0] MAX Duty = 5062%(X100), DQS PI = 22
7344 10:55:10.814874 [0] MIN Duty = 4813%(X100), DQS PI = 52
7345 10:55:10.814954 [0] AVG Duty = 4937%(X100)
7346 10:55:10.817733
7347 10:55:10.817812 ==DQS 1 ==
7348 10:55:10.821548 Final DQS duty delay cell = 0
7349 10:55:10.824795 [0] MAX Duty = 5062%(X100), DQS PI = 34
7350 10:55:10.827632 [0] MIN Duty = 4938%(X100), DQS PI = 12
7351 10:55:10.831045 [0] AVG Duty = 5000%(X100)
7352 10:55:10.831124
7353 10:55:10.834507 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7354 10:55:10.834591
7355 10:55:10.837763 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7356 10:55:10.840743 [DutyScan_Calibration_Flow] ====Done====
7357 10:55:10.840827
7358 10:55:10.843924 [DutyScan_Calibration_Flow] k_type=3
7359 10:55:10.861660
7360 10:55:10.861745 ==DQM 0 ==
7361 10:55:10.864512 Final DQM duty delay cell = 0
7362 10:55:10.868113 [0] MAX Duty = 5156%(X100), DQS PI = 20
7363 10:55:10.871117 [0] MIN Duty = 4813%(X100), DQS PI = 50
7364 10:55:10.874565 [0] AVG Duty = 4984%(X100)
7365 10:55:10.874649
7366 10:55:10.874732 ==DQM 1 ==
7367 10:55:10.877663 Final DQM duty delay cell = 0
7368 10:55:10.881208 [0] MAX Duty = 5125%(X100), DQS PI = 8
7369 10:55:10.884661 [0] MIN Duty = 4907%(X100), DQS PI = 20
7370 10:55:10.888697 [0] AVG Duty = 5016%(X100)
7371 10:55:10.888780
7372 10:55:10.891621 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7373 10:55:10.891704
7374 10:55:10.894510 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7375 10:55:10.897794 [DutyScan_Calibration_Flow] ====Done====
7376 10:55:10.897903
7377 10:55:10.901187 [DutyScan_Calibration_Flow] k_type=2
7378 10:55:10.918067
7379 10:55:10.918150 ==DQ 0 ==
7380 10:55:10.921688 Final DQ duty delay cell = 0
7381 10:55:10.924710 [0] MAX Duty = 5156%(X100), DQS PI = 20
7382 10:55:10.927850 [0] MIN Duty = 4938%(X100), DQS PI = 50
7383 10:55:10.931469 [0] AVG Duty = 5047%(X100)
7384 10:55:10.931551
7385 10:55:10.931617 ==DQ 1 ==
7386 10:55:10.934790 Final DQ duty delay cell = 0
7387 10:55:10.938257 [0] MAX Duty = 5093%(X100), DQS PI = 6
7388 10:55:10.940976 [0] MIN Duty = 5031%(X100), DQS PI = 0
7389 10:55:10.941059 [0] AVG Duty = 5062%(X100)
7390 10:55:10.944481
7391 10:55:10.947712 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7392 10:55:10.947795
7393 10:55:10.951093 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7394 10:55:10.954529 [DutyScan_Calibration_Flow] ====Done====
7395 10:55:10.957745 nWR fixed to 30
7396 10:55:10.957829 [ModeRegInit_LP4] CH0 RK0
7397 10:55:10.960860 [ModeRegInit_LP4] CH0 RK1
7398 10:55:10.964350 [ModeRegInit_LP4] CH1 RK0
7399 10:55:10.967540 [ModeRegInit_LP4] CH1 RK1
7400 10:55:10.967622 match AC timing 5
7401 10:55:10.971267 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7402 10:55:10.977468 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7403 10:55:10.980785 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7404 10:55:10.987357 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7405 10:55:10.990741 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7406 10:55:10.990825 [MiockJmeterHQA]
7407 10:55:10.990892
7408 10:55:10.994080 [DramcMiockJmeter] u1RxGatingPI = 0
7409 10:55:10.997514 0 : 4260, 4032
7410 10:55:10.997598 4 : 4252, 4026
7411 10:55:11.000821 8 : 4255, 4030
7412 10:55:11.000905 12 : 4257, 4029
7413 10:55:11.000973 16 : 4366, 4140
7414 10:55:11.004175 20 : 4368, 4139
7415 10:55:11.004270 24 : 4257, 4029
7416 10:55:11.007842 28 : 4253, 4027
7417 10:55:11.007926 32 : 4257, 4029
7418 10:55:11.010489 36 : 4365, 4140
7419 10:55:11.010572 40 : 4250, 4027
7420 10:55:11.013728 44 : 4250, 4027
7421 10:55:11.013812 48 : 4366, 4142
7422 10:55:11.013880 52 : 4250, 4027
7423 10:55:11.017491 56 : 4255, 4030
7424 10:55:11.017575 60 : 4253, 4029
7425 10:55:11.020763 64 : 4250, 4026
7426 10:55:11.020847 68 : 4252, 4029
7427 10:55:11.023751 72 : 4252, 4029
7428 10:55:11.023835 76 : 4252, 4027
7429 10:55:11.027144 80 : 4250, 4026
7430 10:55:11.027227 84 : 4252, 4029
7431 10:55:11.027295 88 : 4361, 4137
7432 10:55:11.030558 92 : 4250, 4026
7433 10:55:11.030642 96 : 4250, 3332
7434 10:55:11.034166 100 : 4360, 0
7435 10:55:11.034250 104 : 4250, 0
7436 10:55:11.034317 108 : 4252, 0
7437 10:55:11.037769 112 : 4250, 0
7438 10:55:11.037853 116 : 4257, 0
7439 10:55:11.040193 120 : 4366, 0
7440 10:55:11.040277 124 : 4366, 0
7441 10:55:11.040345 128 : 4247, 0
7442 10:55:11.043442 132 : 4360, 0
7443 10:55:11.043526 136 : 4252, 0
7444 10:55:11.047224 140 : 4363, 0
7445 10:55:11.047312 144 : 4252, 0
7446 10:55:11.047403 148 : 4361, 0
7447 10:55:11.050054 152 : 4250, 0
7448 10:55:11.050138 156 : 4361, 0
7449 10:55:11.053466 160 : 4250, 0
7450 10:55:11.053550 164 : 4250, 0
7451 10:55:11.053617 168 : 4255, 0
7452 10:55:11.057307 172 : 4253, 0
7453 10:55:11.057390 176 : 4254, 0
7454 10:55:11.057457 180 : 4257, 0
7455 10:55:11.060192 184 : 4253, 0
7456 10:55:11.060277 188 : 4250, 0
7457 10:55:11.063281 192 : 4254, 0
7458 10:55:11.063446 196 : 4365, 0
7459 10:55:11.063528 200 : 4255, 0
7460 10:55:11.067220 204 : 4250, 0
7461 10:55:11.067331 208 : 4250, 0
7462 10:55:11.070378 212 : 4250, 32
7463 10:55:11.070462 216 : 4257, 3641
7464 10:55:11.074045 220 : 4250, 4027
7465 10:55:11.074129 224 : 4250, 4026
7466 10:55:11.074195 228 : 4365, 4140
7467 10:55:11.077218 232 : 4252, 4029
7468 10:55:11.077302 236 : 4255, 4029
7469 10:55:11.080055 240 : 4363, 4137
7470 10:55:11.080139 244 : 4255, 4030
7471 10:55:11.083472 248 : 4255, 4029
7472 10:55:11.083589 252 : 4365, 4139
7473 10:55:11.086927 256 : 4362, 4140
7474 10:55:11.087011 260 : 4255, 4030
7475 10:55:11.090676 264 : 4250, 4027
7476 10:55:11.090761 268 : 4257, 4031
7477 10:55:11.093503 272 : 4250, 4027
7478 10:55:11.093588 276 : 4252, 4029
7479 10:55:11.096955 280 : 4255, 4029
7480 10:55:11.097040 284 : 4255, 4029
7481 10:55:11.097126 288 : 4255, 4029
7482 10:55:11.100030 292 : 4366, 4140
7483 10:55:11.100115 296 : 4249, 4027
7484 10:55:11.103964 300 : 4250, 4027
7485 10:55:11.104049 304 : 4368, 4145
7486 10:55:11.107182 308 : 4250, 4026
7487 10:55:11.107266 312 : 4360, 4138
7488 10:55:11.110304 316 : 4249, 4027
7489 10:55:11.110389 320 : 4250, 4027
7490 10:55:11.113506 324 : 4253, 4029
7491 10:55:11.113590 328 : 4363, 4140
7492 10:55:11.116520 332 : 4255, 3000
7493 10:55:11.116604 336 : 4255, 151
7494 10:55:11.116689
7495 10:55:11.120100 MIOCK jitter meter ch=0
7496 10:55:11.120183
7497 10:55:11.123338 1T = (336-100) = 236 dly cells
7498 10:55:11.126463 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7499 10:55:11.129946 ==
7500 10:55:11.130030 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 10:55:11.136692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 10:55:11.136777 ==
7503 10:55:11.139830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 10:55:11.146648 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 10:55:11.150487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 10:55:11.156560 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 10:55:11.164495 [CA 0] Center 44 (14~75) winsize 62
7508 10:55:11.168153 [CA 1] Center 43 (13~74) winsize 62
7509 10:55:11.171342 [CA 2] Center 39 (11~68) winsize 58
7510 10:55:11.174476 [CA 3] Center 39 (10~68) winsize 59
7511 10:55:11.177690 [CA 4] Center 37 (8~67) winsize 60
7512 10:55:11.181229 [CA 5] Center 37 (7~67) winsize 61
7513 10:55:11.181312
7514 10:55:11.185012 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 10:55:11.185095
7516 10:55:11.187907 [CATrainingPosCal] consider 1 rank data
7517 10:55:11.191528 u2DelayCellTimex100 = 275/100 ps
7518 10:55:11.197606 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7519 10:55:11.201179 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7520 10:55:11.204639 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7521 10:55:11.207794 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7522 10:55:11.210855 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7523 10:55:11.214409 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7524 10:55:11.214493
7525 10:55:11.217499 CA PerBit enable=1, Macro0, CA PI delay=37
7526 10:55:11.217582
7527 10:55:11.220861 [CBTSetCACLKResult] CA Dly = 37
7528 10:55:11.224661 CS Dly: 11 (0~42)
7529 10:55:11.227297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 10:55:11.230747 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 10:55:11.230830 ==
7532 10:55:11.234227 Dram Type= 6, Freq= 0, CH_0, rank 1
7533 10:55:11.240622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 10:55:11.240705 ==
7535 10:55:11.244100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7536 10:55:11.250900 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7537 10:55:11.253894 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7538 10:55:11.260299 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7539 10:55:11.268387 [CA 0] Center 44 (14~75) winsize 62
7540 10:55:11.271966 [CA 1] Center 44 (14~75) winsize 62
7541 10:55:11.275250 [CA 2] Center 40 (11~69) winsize 59
7542 10:55:11.278563 [CA 3] Center 39 (10~69) winsize 60
7543 10:55:11.281628 [CA 4] Center 38 (9~68) winsize 60
7544 10:55:11.284827 [CA 5] Center 37 (7~67) winsize 61
7545 10:55:11.284910
7546 10:55:11.288731 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7547 10:55:11.288814
7548 10:55:11.291660 [CATrainingPosCal] consider 2 rank data
7549 10:55:11.295402 u2DelayCellTimex100 = 275/100 ps
7550 10:55:11.298190 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7551 10:55:11.304841 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7552 10:55:11.308449 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7553 10:55:11.311591 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7554 10:55:11.314766 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7555 10:55:11.318748 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7556 10:55:11.318831
7557 10:55:11.321968 CA PerBit enable=1, Macro0, CA PI delay=37
7558 10:55:11.322061
7559 10:55:11.325100 [CBTSetCACLKResult] CA Dly = 37
7560 10:55:11.328205 CS Dly: 12 (0~44)
7561 10:55:11.331691 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7562 10:55:11.335155 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7563 10:55:11.335238
7564 10:55:11.338484 ----->DramcWriteLeveling(PI) begin...
7565 10:55:11.338568 ==
7566 10:55:11.341393 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 10:55:11.347929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 10:55:11.348013 ==
7569 10:55:11.351295 Write leveling (Byte 0): 33 => 33
7570 10:55:11.351428 Write leveling (Byte 1): 29 => 29
7571 10:55:11.354878 DramcWriteLeveling(PI) end<-----
7572 10:55:11.354986
7573 10:55:11.358373 ==
7574 10:55:11.358456 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 10:55:11.364355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 10:55:11.364438 ==
7577 10:55:11.367893 [Gating] SW mode calibration
7578 10:55:11.374685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7579 10:55:11.378017 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7580 10:55:11.384690 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 10:55:11.388036 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 10:55:11.391815 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 10:55:11.397837 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 10:55:11.400936 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 10:55:11.404220 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7586 10:55:11.410892 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7587 10:55:11.414583 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 10:55:11.418014 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 10:55:11.424145 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 10:55:11.427543 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 10:55:11.430794 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7592 10:55:11.437632 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7593 10:55:11.440786 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7594 10:55:11.444449 1 5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7595 10:55:11.450650 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 10:55:11.454087 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 10:55:11.456995 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 10:55:11.464052 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 10:55:11.466852 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 10:55:11.470348 1 6 16 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7601 10:55:11.477235 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7602 10:55:11.480572 1 6 24 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7603 10:55:11.483448 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 10:55:11.490313 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 10:55:11.493826 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 10:55:11.496682 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 10:55:11.503714 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 10:55:11.507095 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 10:55:11.510177 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7610 10:55:11.516709 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7611 10:55:11.520015 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 10:55:11.523564 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 10:55:11.526940 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 10:55:11.534157 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 10:55:11.536781 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 10:55:11.540120 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 10:55:11.547473 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 10:55:11.550443 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 10:55:11.553770 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 10:55:11.560068 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 10:55:11.563283 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:55:11.566485 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:55:11.574173 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7624 10:55:11.577038 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7625 10:55:11.579866 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7626 10:55:11.586637 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 10:55:11.586739 Total UI for P1: 0, mck2ui 16
7628 10:55:11.593077 best dqsien dly found for B0: ( 1, 9, 16)
7629 10:55:11.596723 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 10:55:11.599920 Total UI for P1: 0, mck2ui 16
7631 10:55:11.602975 best dqsien dly found for B1: ( 1, 9, 20)
7632 10:55:11.606275 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7633 10:55:11.609988 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7634 10:55:11.610078
7635 10:55:11.613694 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7636 10:55:11.616629 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7637 10:55:11.619897 [Gating] SW calibration Done
7638 10:55:11.620010 ==
7639 10:55:11.622923 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 10:55:11.629639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 10:55:11.629741 ==
7642 10:55:11.629810 RX Vref Scan: 0
7643 10:55:11.629871
7644 10:55:11.633137 RX Vref 0 -> 0, step: 1
7645 10:55:11.633221
7646 10:55:11.636546 RX Delay 0 -> 252, step: 8
7647 10:55:11.639843 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7648 10:55:11.642734 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7649 10:55:11.646162 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7650 10:55:11.650066 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7651 10:55:11.656470 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7652 10:55:11.659481 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7653 10:55:11.662634 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7654 10:55:11.665997 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7655 10:55:11.669295 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7656 10:55:11.676629 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7657 10:55:11.679551 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7658 10:55:11.683092 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7659 10:55:11.686021 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7660 10:55:11.689385 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7661 10:55:11.696127 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7662 10:55:11.699323 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7663 10:55:11.699459 ==
7664 10:55:11.702441 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 10:55:11.705987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 10:55:11.706073 ==
7667 10:55:11.709516 DQS Delay:
7668 10:55:11.709601 DQS0 = 0, DQS1 = 0
7669 10:55:11.709667 DQM Delay:
7670 10:55:11.713084 DQM0 = 131, DQM1 = 125
7671 10:55:11.713169 DQ Delay:
7672 10:55:11.716620 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7673 10:55:11.719534 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7674 10:55:11.722704 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
7675 10:55:11.729254 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7676 10:55:11.729352
7677 10:55:11.729420
7678 10:55:11.729480 ==
7679 10:55:11.732574 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 10:55:11.735682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 10:55:11.735770 ==
7682 10:55:11.735836
7683 10:55:11.735897
7684 10:55:11.739356 TX Vref Scan disable
7685 10:55:11.739471 == TX Byte 0 ==
7686 10:55:11.745872 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7687 10:55:11.749178 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7688 10:55:11.749272 == TX Byte 1 ==
7689 10:55:11.756122 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7690 10:55:11.759665 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7691 10:55:11.759752 ==
7692 10:55:11.762629 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 10:55:11.765788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 10:55:11.765873 ==
7695 10:55:11.781538
7696 10:55:11.784313 TX Vref early break, caculate TX vref
7697 10:55:11.787858 TX Vref=16, minBit 1, minWin=21, winSum=362
7698 10:55:11.791218 TX Vref=18, minBit 0, minWin=22, winSum=371
7699 10:55:11.794209 TX Vref=20, minBit 4, minWin=22, winSum=385
7700 10:55:11.797701 TX Vref=22, minBit 1, minWin=23, winSum=397
7701 10:55:11.801040 TX Vref=24, minBit 0, minWin=24, winSum=405
7702 10:55:11.808044 TX Vref=26, minBit 1, minWin=24, winSum=409
7703 10:55:11.811237 TX Vref=28, minBit 1, minWin=24, winSum=415
7704 10:55:11.814734 TX Vref=30, minBit 0, minWin=25, winSum=420
7705 10:55:11.817596 TX Vref=32, minBit 4, minWin=24, winSum=415
7706 10:55:11.821317 TX Vref=34, minBit 4, minWin=23, winSum=402
7707 10:55:11.824242 TX Vref=36, minBit 0, minWin=23, winSum=394
7708 10:55:11.831505 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 30
7709 10:55:11.831592
7710 10:55:11.834571 Final TX Range 0 Vref 30
7711 10:55:11.834652
7712 10:55:11.834717 ==
7713 10:55:11.837896 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 10:55:11.840931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 10:55:11.841015 ==
7716 10:55:11.841081
7717 10:55:11.841140
7718 10:55:11.844478 TX Vref Scan disable
7719 10:55:11.851252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7720 10:55:11.851371 == TX Byte 0 ==
7721 10:55:11.854506 u2DelayCellOfst[0]=14 cells (4 PI)
7722 10:55:11.858263 u2DelayCellOfst[1]=21 cells (6 PI)
7723 10:55:11.861041 u2DelayCellOfst[2]=10 cells (3 PI)
7724 10:55:11.863949 u2DelayCellOfst[3]=10 cells (3 PI)
7725 10:55:11.867554 u2DelayCellOfst[4]=10 cells (3 PI)
7726 10:55:11.870745 u2DelayCellOfst[5]=0 cells (0 PI)
7727 10:55:11.874234 u2DelayCellOfst[6]=17 cells (5 PI)
7728 10:55:11.877803 u2DelayCellOfst[7]=17 cells (5 PI)
7729 10:55:11.880988 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7730 10:55:11.883842 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7731 10:55:11.887301 == TX Byte 1 ==
7732 10:55:11.891063 u2DelayCellOfst[8]=3 cells (1 PI)
7733 10:55:11.893704 u2DelayCellOfst[9]=0 cells (0 PI)
7734 10:55:11.897276 u2DelayCellOfst[10]=10 cells (3 PI)
7735 10:55:11.897372 u2DelayCellOfst[11]=3 cells (1 PI)
7736 10:55:11.900648 u2DelayCellOfst[12]=14 cells (4 PI)
7737 10:55:11.904624 u2DelayCellOfst[13]=14 cells (4 PI)
7738 10:55:11.907490 u2DelayCellOfst[14]=17 cells (5 PI)
7739 10:55:11.910896 u2DelayCellOfst[15]=10 cells (3 PI)
7740 10:55:11.917270 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7741 10:55:11.920549 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7742 10:55:11.920653 DramC Write-DBI on
7743 10:55:11.920796 ==
7744 10:55:11.923970 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 10:55:11.930617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 10:55:11.930737 ==
7747 10:55:11.930836
7748 10:55:11.930896
7749 10:55:11.930955 TX Vref Scan disable
7750 10:55:11.934738 == TX Byte 0 ==
7751 10:55:11.937910 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7752 10:55:11.941675 == TX Byte 1 ==
7753 10:55:11.945044 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7754 10:55:11.947848 DramC Write-DBI off
7755 10:55:11.947931
7756 10:55:11.947997 [DATLAT]
7757 10:55:11.948058 Freq=1600, CH0 RK0
7758 10:55:11.948118
7759 10:55:11.951303 DATLAT Default: 0xf
7760 10:55:11.951438 0, 0xFFFF, sum = 0
7761 10:55:11.954929 1, 0xFFFF, sum = 0
7762 10:55:11.958134 2, 0xFFFF, sum = 0
7763 10:55:11.958245 3, 0xFFFF, sum = 0
7764 10:55:11.960998 4, 0xFFFF, sum = 0
7765 10:55:11.961086 5, 0xFFFF, sum = 0
7766 10:55:11.964602 6, 0xFFFF, sum = 0
7767 10:55:11.964687 7, 0xFFFF, sum = 0
7768 10:55:11.967992 8, 0xFFFF, sum = 0
7769 10:55:11.968076 9, 0xFFFF, sum = 0
7770 10:55:11.970848 10, 0xFFFF, sum = 0
7771 10:55:11.970933 11, 0xFFFF, sum = 0
7772 10:55:11.975080 12, 0xFFFF, sum = 0
7773 10:55:11.975190 13, 0xFFFF, sum = 0
7774 10:55:11.977659 14, 0x0, sum = 1
7775 10:55:11.977743 15, 0x0, sum = 2
7776 10:55:11.981429 16, 0x0, sum = 3
7777 10:55:11.981515 17, 0x0, sum = 4
7778 10:55:11.984382 best_step = 15
7779 10:55:11.984465
7780 10:55:11.984531 ==
7781 10:55:11.987988 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 10:55:11.991112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 10:55:11.991229 ==
7784 10:55:11.991324 RX Vref Scan: 1
7785 10:55:11.995228
7786 10:55:11.995316 Set Vref Range= 24 -> 127
7787 10:55:11.995425
7788 10:55:11.997850 RX Vref 24 -> 127, step: 1
7789 10:55:11.997935
7790 10:55:12.001125 RX Delay 11 -> 252, step: 4
7791 10:55:12.001213
7792 10:55:12.004628 Set Vref, RX VrefLevel [Byte0]: 24
7793 10:55:12.007841 [Byte1]: 24
7794 10:55:12.007930
7795 10:55:12.011170 Set Vref, RX VrefLevel [Byte0]: 25
7796 10:55:12.014488 [Byte1]: 25
7797 10:55:12.014574
7798 10:55:12.018156 Set Vref, RX VrefLevel [Byte0]: 26
7799 10:55:12.021069 [Byte1]: 26
7800 10:55:12.025482
7801 10:55:12.025565 Set Vref, RX VrefLevel [Byte0]: 27
7802 10:55:12.028109 [Byte1]: 27
7803 10:55:12.032494
7804 10:55:12.032577 Set Vref, RX VrefLevel [Byte0]: 28
7805 10:55:12.036002 [Byte1]: 28
7806 10:55:12.040614
7807 10:55:12.040698 Set Vref, RX VrefLevel [Byte0]: 29
7808 10:55:12.043772 [Byte1]: 29
7809 10:55:12.048067
7810 10:55:12.048149 Set Vref, RX VrefLevel [Byte0]: 30
7811 10:55:12.051242 [Byte1]: 30
7812 10:55:12.055894
7813 10:55:12.055977 Set Vref, RX VrefLevel [Byte0]: 31
7814 10:55:12.058735 [Byte1]: 31
7815 10:55:12.063485
7816 10:55:12.063568 Set Vref, RX VrefLevel [Byte0]: 32
7817 10:55:12.066208 [Byte1]: 32
7818 10:55:12.070656
7819 10:55:12.070740 Set Vref, RX VrefLevel [Byte0]: 33
7820 10:55:12.073875 [Byte1]: 33
7821 10:55:12.078175
7822 10:55:12.078257 Set Vref, RX VrefLevel [Byte0]: 34
7823 10:55:12.081524 [Byte1]: 34
7824 10:55:12.085993
7825 10:55:12.086076 Set Vref, RX VrefLevel [Byte0]: 35
7826 10:55:12.089449 [Byte1]: 35
7827 10:55:12.093614
7828 10:55:12.093695 Set Vref, RX VrefLevel [Byte0]: 36
7829 10:55:12.096806 [Byte1]: 36
7830 10:55:12.101371
7831 10:55:12.104471 Set Vref, RX VrefLevel [Byte0]: 37
7832 10:55:12.107830 [Byte1]: 37
7833 10:55:12.107912
7834 10:55:12.111296 Set Vref, RX VrefLevel [Byte0]: 38
7835 10:55:12.114397 [Byte1]: 38
7836 10:55:12.114479
7837 10:55:12.117792 Set Vref, RX VrefLevel [Byte0]: 39
7838 10:55:12.120812 [Byte1]: 39
7839 10:55:12.120920
7840 10:55:12.124279 Set Vref, RX VrefLevel [Byte0]: 40
7841 10:55:12.127697 [Byte1]: 40
7842 10:55:12.132161
7843 10:55:12.132243 Set Vref, RX VrefLevel [Byte0]: 41
7844 10:55:12.135251 [Byte1]: 41
7845 10:55:12.139158
7846 10:55:12.139241 Set Vref, RX VrefLevel [Byte0]: 42
7847 10:55:12.142606 [Byte1]: 42
7848 10:55:12.147140
7849 10:55:12.147223 Set Vref, RX VrefLevel [Byte0]: 43
7850 10:55:12.150195 [Byte1]: 43
7851 10:55:12.154574
7852 10:55:12.154656 Set Vref, RX VrefLevel [Byte0]: 44
7853 10:55:12.157779 [Byte1]: 44
7854 10:55:12.161952
7855 10:55:12.162035 Set Vref, RX VrefLevel [Byte0]: 45
7856 10:55:12.165650 [Byte1]: 45
7857 10:55:12.170141
7858 10:55:12.170227 Set Vref, RX VrefLevel [Byte0]: 46
7859 10:55:12.173065 [Byte1]: 46
7860 10:55:12.177176
7861 10:55:12.177261 Set Vref, RX VrefLevel [Byte0]: 47
7862 10:55:12.180908 [Byte1]: 47
7863 10:55:12.185156
7864 10:55:12.185257 Set Vref, RX VrefLevel [Byte0]: 48
7865 10:55:12.188358 [Byte1]: 48
7866 10:55:12.192358
7867 10:55:12.192440 Set Vref, RX VrefLevel [Byte0]: 49
7868 10:55:12.196098 [Byte1]: 49
7869 10:55:12.200194
7870 10:55:12.200277 Set Vref, RX VrefLevel [Byte0]: 50
7871 10:55:12.203633 [Byte1]: 50
7872 10:55:12.207696
7873 10:55:12.207777 Set Vref, RX VrefLevel [Byte0]: 51
7874 10:55:12.211091 [Byte1]: 51
7875 10:55:12.215623
7876 10:55:12.215704 Set Vref, RX VrefLevel [Byte0]: 52
7877 10:55:12.219032 [Byte1]: 52
7878 10:55:12.223212
7879 10:55:12.223294 Set Vref, RX VrefLevel [Byte0]: 53
7880 10:55:12.226022 [Byte1]: 53
7881 10:55:12.230574
7882 10:55:12.230656 Set Vref, RX VrefLevel [Byte0]: 54
7883 10:55:12.236908 [Byte1]: 54
7884 10:55:12.237022
7885 10:55:12.240809 Set Vref, RX VrefLevel [Byte0]: 55
7886 10:55:12.243508 [Byte1]: 55
7887 10:55:12.243589
7888 10:55:12.246904 Set Vref, RX VrefLevel [Byte0]: 56
7889 10:55:12.250714 [Byte1]: 56
7890 10:55:12.253410
7891 10:55:12.253492 Set Vref, RX VrefLevel [Byte0]: 57
7892 10:55:12.257012 [Byte1]: 57
7893 10:55:12.261022
7894 10:55:12.261103 Set Vref, RX VrefLevel [Byte0]: 58
7895 10:55:12.264504 [Byte1]: 58
7896 10:55:12.268742
7897 10:55:12.268824 Set Vref, RX VrefLevel [Byte0]: 59
7898 10:55:12.272158 [Byte1]: 59
7899 10:55:12.276212
7900 10:55:12.276294 Set Vref, RX VrefLevel [Byte0]: 60
7901 10:55:12.279713 [Byte1]: 60
7902 10:55:12.284027
7903 10:55:12.284108 Set Vref, RX VrefLevel [Byte0]: 61
7904 10:55:12.287049 [Byte1]: 61
7905 10:55:12.291602
7906 10:55:12.291691 Set Vref, RX VrefLevel [Byte0]: 62
7907 10:55:12.295488 [Byte1]: 62
7908 10:55:12.299300
7909 10:55:12.299440 Set Vref, RX VrefLevel [Byte0]: 63
7910 10:55:12.302799 [Byte1]: 63
7911 10:55:12.306861
7912 10:55:12.306944 Set Vref, RX VrefLevel [Byte0]: 64
7913 10:55:12.309863 [Byte1]: 64
7914 10:55:12.314379
7915 10:55:12.314462 Set Vref, RX VrefLevel [Byte0]: 65
7916 10:55:12.317850 [Byte1]: 65
7917 10:55:12.322129
7918 10:55:12.322214 Set Vref, RX VrefLevel [Byte0]: 66
7919 10:55:12.325402 [Byte1]: 66
7920 10:55:12.329739
7921 10:55:12.329822 Set Vref, RX VrefLevel [Byte0]: 67
7922 10:55:12.332962 [Byte1]: 67
7923 10:55:12.337103
7924 10:55:12.337186 Set Vref, RX VrefLevel [Byte0]: 68
7925 10:55:12.340491 [Byte1]: 68
7926 10:55:12.344983
7927 10:55:12.345066 Set Vref, RX VrefLevel [Byte0]: 69
7928 10:55:12.348124 [Byte1]: 69
7929 10:55:12.352571
7930 10:55:12.352654 Set Vref, RX VrefLevel [Byte0]: 70
7931 10:55:12.355534 [Byte1]: 70
7932 10:55:12.359977
7933 10:55:12.360060 Set Vref, RX VrefLevel [Byte0]: 71
7934 10:55:12.363553 [Byte1]: 71
7935 10:55:12.367483
7936 10:55:12.367565 Set Vref, RX VrefLevel [Byte0]: 72
7937 10:55:12.371561 [Byte1]: 72
7938 10:55:12.375460
7939 10:55:12.375542 Set Vref, RX VrefLevel [Byte0]: 73
7940 10:55:12.378393 [Byte1]: 73
7941 10:55:12.382686
7942 10:55:12.382770 Set Vref, RX VrefLevel [Byte0]: 74
7943 10:55:12.386435 [Byte1]: 74
7944 10:55:12.390916
7945 10:55:12.391001 Set Vref, RX VrefLevel [Byte0]: 75
7946 10:55:12.393876 [Byte1]: 75
7947 10:55:12.398470
7948 10:55:12.398553 Set Vref, RX VrefLevel [Byte0]: 76
7949 10:55:12.401492 [Byte1]: 76
7950 10:55:12.405823
7951 10:55:12.405907 Final RX Vref Byte 0 = 60 to rank0
7952 10:55:12.409123 Final RX Vref Byte 1 = 60 to rank0
7953 10:55:12.412172 Final RX Vref Byte 0 = 60 to rank1
7954 10:55:12.415910 Final RX Vref Byte 1 = 60 to rank1==
7955 10:55:12.419073 Dram Type= 6, Freq= 0, CH_0, rank 0
7956 10:55:12.425455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 10:55:12.425539 ==
7958 10:55:12.425605 DQS Delay:
7959 10:55:12.425668 DQS0 = 0, DQS1 = 0
7960 10:55:12.428853 DQM Delay:
7961 10:55:12.428936 DQM0 = 130, DQM1 = 122
7962 10:55:12.432484 DQ Delay:
7963 10:55:12.435468 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =128
7964 10:55:12.438837 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7965 10:55:12.441795 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7966 10:55:12.445258 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =134
7967 10:55:12.445341
7968 10:55:12.445407
7969 10:55:12.445466
7970 10:55:12.448715 [DramC_TX_OE_Calibration] TA2
7971 10:55:12.452057 Original DQ_B0 (3 6) =30, OEN = 27
7972 10:55:12.455641 Original DQ_B1 (3 6) =30, OEN = 27
7973 10:55:12.458737 24, 0x0, End_B0=24 End_B1=24
7974 10:55:12.458848 25, 0x0, End_B0=25 End_B1=25
7975 10:55:12.462022 26, 0x0, End_B0=26 End_B1=26
7976 10:55:12.465278 27, 0x0, End_B0=27 End_B1=27
7977 10:55:12.468681 28, 0x0, End_B0=28 End_B1=28
7978 10:55:12.472468 29, 0x0, End_B0=29 End_B1=29
7979 10:55:12.472552 30, 0x0, End_B0=30 End_B1=30
7980 10:55:12.475250 31, 0x4141, End_B0=30 End_B1=30
7981 10:55:12.478707 Byte0 end_step=30 best_step=27
7982 10:55:12.481892 Byte1 end_step=30 best_step=27
7983 10:55:12.484895 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 10:55:12.488264 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 10:55:12.488347
7986 10:55:12.488413
7987 10:55:12.494960 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7988 10:55:12.498282 CH0 RK0: MR19=303, MR18=1206
7989 10:55:12.504889 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7990 10:55:12.504972
7991 10:55:12.508373 ----->DramcWriteLeveling(PI) begin...
7992 10:55:12.508458 ==
7993 10:55:12.511927 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 10:55:12.514736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 10:55:12.514820 ==
7996 10:55:12.518613 Write leveling (Byte 0): 34 => 34
7997 10:55:12.521543 Write leveling (Byte 1): 26 => 26
7998 10:55:12.524900 DramcWriteLeveling(PI) end<-----
7999 10:55:12.524982
8000 10:55:12.525048 ==
8001 10:55:12.528556 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 10:55:12.531801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 10:55:12.531913 ==
8004 10:55:12.535060 [Gating] SW mode calibration
8005 10:55:12.541778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8006 10:55:12.548181 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8007 10:55:12.551301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 10:55:12.558307 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 10:55:12.561609 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8010 10:55:12.564803 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8011 10:55:12.570960 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8012 10:55:12.574335 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8013 10:55:12.577813 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 10:55:12.584286 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 10:55:12.587567 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 10:55:12.591137 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8017 10:55:12.597655 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8018 10:55:12.600926 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8019 10:55:12.604239 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8020 10:55:12.610964 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8021 10:55:12.614643 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8022 10:55:12.617584 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 10:55:12.624201 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 10:55:12.627296 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 10:55:12.631011 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8026 10:55:12.633997 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8027 10:55:12.640812 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 10:55:12.643957 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8029 10:55:12.647260 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 10:55:12.654136 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 10:55:12.657475 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 10:55:12.660487 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 10:55:12.667033 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 10:55:12.670832 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 10:55:12.673698 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 10:55:12.680890 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 10:55:12.684485 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 10:55:12.687683 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 10:55:12.693909 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 10:55:12.697397 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 10:55:12.700841 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 10:55:12.707697 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 10:55:12.710545 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 10:55:12.713905 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 10:55:12.720923 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 10:55:12.723660 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 10:55:12.726997 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 10:55:12.733759 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 10:55:12.737284 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 10:55:12.740699 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 10:55:12.747690 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 10:55:12.747774 Total UI for P1: 0, mck2ui 16
8053 10:55:12.750300 best dqsien dly found for B0: ( 1, 9, 8)
8054 10:55:12.756944 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 10:55:12.760371 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 10:55:12.763933 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 10:55:12.767342 Total UI for P1: 0, mck2ui 16
8058 10:55:12.770081 best dqsien dly found for B1: ( 1, 9, 20)
8059 10:55:12.773513 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8060 10:55:12.780444 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8061 10:55:12.780529
8062 10:55:12.783311 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8063 10:55:12.786747 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8064 10:55:12.790078 [Gating] SW calibration Done
8065 10:55:12.790161 ==
8066 10:55:12.793642 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 10:55:12.796736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 10:55:12.796820 ==
8069 10:55:12.796887 RX Vref Scan: 0
8070 10:55:12.800196
8071 10:55:12.800279 RX Vref 0 -> 0, step: 1
8072 10:55:12.800345
8073 10:55:12.803656 RX Delay 0 -> 252, step: 8
8074 10:55:12.806761 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8075 10:55:12.810528 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8076 10:55:12.816614 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8077 10:55:12.820258 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8078 10:55:12.823456 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8079 10:55:12.826889 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8080 10:55:12.830199 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8081 10:55:12.837011 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 10:55:12.840271 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8083 10:55:12.843502 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8084 10:55:12.847153 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8085 10:55:12.850195 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8086 10:55:12.856881 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8087 10:55:12.859784 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8088 10:55:12.863070 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8089 10:55:12.866609 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8090 10:55:12.866692 ==
8091 10:55:12.869986 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 10:55:12.876594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 10:55:12.876679 ==
8094 10:55:12.876745 DQS Delay:
8095 10:55:12.880095 DQS0 = 0, DQS1 = 0
8096 10:55:12.880181 DQM Delay:
8097 10:55:12.880246 DQM0 = 131, DQM1 = 125
8098 10:55:12.883462 DQ Delay:
8099 10:55:12.886326 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8100 10:55:12.889695 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8101 10:55:12.893162 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8102 10:55:12.896737 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8103 10:55:12.896819
8104 10:55:12.896884
8105 10:55:12.896944 ==
8106 10:55:12.899631 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 10:55:12.903242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 10:55:12.906499 ==
8109 10:55:12.906582
8110 10:55:12.906646
8111 10:55:12.906706 TX Vref Scan disable
8112 10:55:12.910446 == TX Byte 0 ==
8113 10:55:12.913274 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8114 10:55:12.916983 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8115 10:55:12.920074 == TX Byte 1 ==
8116 10:55:12.923358 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8117 10:55:12.926782 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8118 10:55:12.926865 ==
8119 10:55:12.929888 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 10:55:12.936462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 10:55:12.936548 ==
8122 10:55:12.950708
8123 10:55:12.953916 TX Vref early break, caculate TX vref
8124 10:55:12.957394 TX Vref=16, minBit 8, minWin=22, winSum=375
8125 10:55:12.960288 TX Vref=18, minBit 9, minWin=22, winSum=378
8126 10:55:12.963628 TX Vref=20, minBit 8, minWin=23, winSum=388
8127 10:55:12.966808 TX Vref=22, minBit 9, minWin=23, winSum=393
8128 10:55:12.970705 TX Vref=24, minBit 4, minWin=24, winSum=399
8129 10:55:12.976953 TX Vref=26, minBit 4, minWin=24, winSum=413
8130 10:55:12.980293 TX Vref=28, minBit 0, minWin=25, winSum=415
8131 10:55:12.983880 TX Vref=30, minBit 1, minWin=25, winSum=415
8132 10:55:12.987104 TX Vref=32, minBit 4, minWin=24, winSum=408
8133 10:55:12.990320 TX Vref=34, minBit 0, minWin=24, winSum=400
8134 10:55:12.993913 TX Vref=36, minBit 4, minWin=23, winSum=392
8135 10:55:13.000326 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8136 10:55:13.000413
8137 10:55:13.003503 Final TX Range 0 Vref 28
8138 10:55:13.003587
8139 10:55:13.003654 ==
8140 10:55:13.006798 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 10:55:13.010343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 10:55:13.010428 ==
8143 10:55:13.010494
8144 10:55:13.013347
8145 10:55:13.013430 TX Vref Scan disable
8146 10:55:13.020353 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8147 10:55:13.020438 == TX Byte 0 ==
8148 10:55:13.023690 u2DelayCellOfst[0]=10 cells (3 PI)
8149 10:55:13.027031 u2DelayCellOfst[1]=17 cells (5 PI)
8150 10:55:13.030204 u2DelayCellOfst[2]=7 cells (2 PI)
8151 10:55:13.033066 u2DelayCellOfst[3]=7 cells (2 PI)
8152 10:55:13.036798 u2DelayCellOfst[4]=7 cells (2 PI)
8153 10:55:13.039935 u2DelayCellOfst[5]=0 cells (0 PI)
8154 10:55:13.043532 u2DelayCellOfst[6]=14 cells (4 PI)
8155 10:55:13.046403 u2DelayCellOfst[7]=14 cells (4 PI)
8156 10:55:13.049842 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8157 10:55:13.053259 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8158 10:55:13.056533 == TX Byte 1 ==
8159 10:55:13.059755 u2DelayCellOfst[8]=0 cells (0 PI)
8160 10:55:13.062970 u2DelayCellOfst[9]=0 cells (0 PI)
8161 10:55:13.066567 u2DelayCellOfst[10]=7 cells (2 PI)
8162 10:55:13.066650 u2DelayCellOfst[11]=0 cells (0 PI)
8163 10:55:13.069653 u2DelayCellOfst[12]=10 cells (3 PI)
8164 10:55:13.073216 u2DelayCellOfst[13]=10 cells (3 PI)
8165 10:55:13.076255 u2DelayCellOfst[14]=14 cells (4 PI)
8166 10:55:13.079920 u2DelayCellOfst[15]=10 cells (3 PI)
8167 10:55:13.086250 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8168 10:55:13.089396 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8169 10:55:13.089481 DramC Write-DBI on
8170 10:55:13.089567 ==
8171 10:55:13.092896 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 10:55:13.098961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 10:55:13.099047 ==
8174 10:55:13.099134
8175 10:55:13.099214
8176 10:55:13.102414 TX Vref Scan disable
8177 10:55:13.102501 == TX Byte 0 ==
8178 10:55:13.109199 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8179 10:55:13.109284 == TX Byte 1 ==
8180 10:55:13.112568 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8181 10:55:13.115951 DramC Write-DBI off
8182 10:55:13.116036
8183 10:55:13.116120 [DATLAT]
8184 10:55:13.119211 Freq=1600, CH0 RK1
8185 10:55:13.119296
8186 10:55:13.119428 DATLAT Default: 0xf
8187 10:55:13.122475 0, 0xFFFF, sum = 0
8188 10:55:13.122561 1, 0xFFFF, sum = 0
8189 10:55:13.125679 2, 0xFFFF, sum = 0
8190 10:55:13.125765 3, 0xFFFF, sum = 0
8191 10:55:13.128856 4, 0xFFFF, sum = 0
8192 10:55:13.128942 5, 0xFFFF, sum = 0
8193 10:55:13.132429 6, 0xFFFF, sum = 0
8194 10:55:13.135592 7, 0xFFFF, sum = 0
8195 10:55:13.135678 8, 0xFFFF, sum = 0
8196 10:55:13.138964 9, 0xFFFF, sum = 0
8197 10:55:13.139050 10, 0xFFFF, sum = 0
8198 10:55:13.142039 11, 0xFFFF, sum = 0
8199 10:55:13.142126 12, 0xFFFF, sum = 0
8200 10:55:13.145293 13, 0xFFFF, sum = 0
8201 10:55:13.145380 14, 0x0, sum = 1
8202 10:55:13.148498 15, 0x0, sum = 2
8203 10:55:13.148584 16, 0x0, sum = 3
8204 10:55:13.152307 17, 0x0, sum = 4
8205 10:55:13.152394 best_step = 15
8206 10:55:13.152479
8207 10:55:13.152559 ==
8208 10:55:13.155657 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 10:55:13.158767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 10:55:13.158854 ==
8211 10:55:13.162220 RX Vref Scan: 0
8212 10:55:13.162305
8213 10:55:13.165675 RX Vref 0 -> 0, step: 1
8214 10:55:13.165760
8215 10:55:13.165844 RX Delay 11 -> 252, step: 4
8216 10:55:13.173015 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8217 10:55:13.175746 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8218 10:55:13.179751 iDelay=191, Bit 2, Center 124 (67 ~ 182) 116
8219 10:55:13.182643 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8220 10:55:13.186039 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8221 10:55:13.192840 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8222 10:55:13.196577 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8223 10:55:13.199685 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8224 10:55:13.202498 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8225 10:55:13.205710 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8226 10:55:13.212657 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8227 10:55:13.215638 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8228 10:55:13.219115 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8229 10:55:13.222555 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8230 10:55:13.228980 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8231 10:55:13.232086 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8232 10:55:13.232172 ==
8233 10:55:13.235387 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 10:55:13.239423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 10:55:13.239509 ==
8236 10:55:13.242285 DQS Delay:
8237 10:55:13.242372 DQS0 = 0, DQS1 = 0
8238 10:55:13.242456 DQM Delay:
8239 10:55:13.245577 DQM0 = 127, DQM1 = 122
8240 10:55:13.245662 DQ Delay:
8241 10:55:13.248927 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8242 10:55:13.252782 DQ4 =128, DQ5 =114, DQ6 =134, DQ7 =134
8243 10:55:13.255478 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8244 10:55:13.262280 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8245 10:55:13.262366
8246 10:55:13.262451
8247 10:55:13.262531
8248 10:55:13.265287 [DramC_TX_OE_Calibration] TA2
8249 10:55:13.265372 Original DQ_B0 (3 6) =30, OEN = 27
8250 10:55:13.269045 Original DQ_B1 (3 6) =30, OEN = 27
8251 10:55:13.271853 24, 0x0, End_B0=24 End_B1=24
8252 10:55:13.275534 25, 0x0, End_B0=25 End_B1=25
8253 10:55:13.278840 26, 0x0, End_B0=26 End_B1=26
8254 10:55:13.282426 27, 0x0, End_B0=27 End_B1=27
8255 10:55:13.282512 28, 0x0, End_B0=28 End_B1=28
8256 10:55:13.285340 29, 0x0, End_B0=29 End_B1=29
8257 10:55:13.288936 30, 0x0, End_B0=30 End_B1=30
8258 10:55:13.292270 31, 0x4141, End_B0=30 End_B1=30
8259 10:55:13.295107 Byte0 end_step=30 best_step=27
8260 10:55:13.295191 Byte1 end_step=30 best_step=27
8261 10:55:13.298808 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 10:55:13.301800 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 10:55:13.301885
8264 10:55:13.301971
8265 10:55:13.312112 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8266 10:55:13.312198 CH0 RK1: MR19=303, MR18=150A
8267 10:55:13.318995 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8268 10:55:13.321770 [RxdqsGatingPostProcess] freq 1600
8269 10:55:13.328841 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 10:55:13.331890 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 10:55:13.335753 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 10:55:13.338454 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 10:55:13.341659 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 10:55:13.341745 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 10:55:13.345196 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 10:55:13.348324 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 10:55:13.351807 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 10:55:13.354842 Pre-setting of DQS Precalculation
8279 10:55:13.361604 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 10:55:13.361691 ==
8281 10:55:13.364852 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 10:55:13.368880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 10:55:13.368966 ==
8284 10:55:13.375170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 10:55:13.378274 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 10:55:13.381764 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 10:55:13.388616 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 10:55:13.396819 [CA 0] Center 43 (15~72) winsize 58
8289 10:55:13.400447 [CA 1] Center 43 (14~72) winsize 59
8290 10:55:13.403283 [CA 2] Center 38 (9~67) winsize 59
8291 10:55:13.406851 [CA 3] Center 37 (8~66) winsize 59
8292 10:55:13.409787 [CA 4] Center 38 (9~68) winsize 60
8293 10:55:13.413141 [CA 5] Center 37 (9~66) winsize 58
8294 10:55:13.413223
8295 10:55:13.416506 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8296 10:55:13.416587
8297 10:55:13.419916 [CATrainingPosCal] consider 1 rank data
8298 10:55:13.423284 u2DelayCellTimex100 = 275/100 ps
8299 10:55:13.429920 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8300 10:55:13.432999 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8301 10:55:13.437119 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8302 10:55:13.439763 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8303 10:55:13.442686 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8304 10:55:13.446074 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8305 10:55:13.446206
8306 10:55:13.449446 CA PerBit enable=1, Macro0, CA PI delay=37
8307 10:55:13.449578
8308 10:55:13.453346 [CBTSetCACLKResult] CA Dly = 37
8309 10:55:13.456676 CS Dly: 9 (0~40)
8310 10:55:13.459664 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 10:55:13.462809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 10:55:13.462943 ==
8313 10:55:13.466283 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 10:55:13.472827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 10:55:13.472963 ==
8316 10:55:13.476273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 10:55:13.479509 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 10:55:13.485936 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 10:55:13.492948 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 10:55:13.500240 [CA 0] Center 43 (14~72) winsize 59
8321 10:55:13.503519 [CA 1] Center 43 (14~72) winsize 59
8322 10:55:13.506525 [CA 2] Center 38 (9~67) winsize 59
8323 10:55:13.510049 [CA 3] Center 37 (8~67) winsize 60
8324 10:55:13.512951 [CA 4] Center 38 (9~68) winsize 60
8325 10:55:13.516502 [CA 5] Center 37 (8~66) winsize 59
8326 10:55:13.516583
8327 10:55:13.519927 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8328 10:55:13.520009
8329 10:55:13.522917 [CATrainingPosCal] consider 2 rank data
8330 10:55:13.526213 u2DelayCellTimex100 = 275/100 ps
8331 10:55:13.533237 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8332 10:55:13.536141 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8333 10:55:13.539852 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8334 10:55:13.542648 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8335 10:55:13.546094 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8336 10:55:13.549402 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8337 10:55:13.549483
8338 10:55:13.552987 CA PerBit enable=1, Macro0, CA PI delay=37
8339 10:55:13.553068
8340 10:55:13.556380 [CBTSetCACLKResult] CA Dly = 37
8341 10:55:13.559365 CS Dly: 10 (0~43)
8342 10:55:13.562868 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 10:55:13.565750 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 10:55:13.565831
8345 10:55:13.569647 ----->DramcWriteLeveling(PI) begin...
8346 10:55:13.569730 ==
8347 10:55:13.572688 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 10:55:13.579465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 10:55:13.579550 ==
8350 10:55:13.582545 Write leveling (Byte 0): 25 => 25
8351 10:55:13.585571 Write leveling (Byte 1): 28 => 28
8352 10:55:13.585653 DramcWriteLeveling(PI) end<-----
8353 10:55:13.585717
8354 10:55:13.588898 ==
8355 10:55:13.592611 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 10:55:13.596511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 10:55:13.596595 ==
8358 10:55:13.598850 [Gating] SW mode calibration
8359 10:55:13.605757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 10:55:13.608997 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 10:55:13.615884 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 10:55:13.618743 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 10:55:13.622365 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 10:55:13.629093 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 10:55:13.632279 1 4 16 | B1->B0 | 2c2b 2525 | 1 0 | (0 0) (0 0)
8366 10:55:13.635643 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8367 10:55:13.641926 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 10:55:13.645265 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 10:55:13.648721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 10:55:13.655280 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 10:55:13.658869 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 10:55:13.662024 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 10:55:13.669099 1 5 16 | B1->B0 | 2e2e 3232 | 1 0 | (1 0) (0 0)
8374 10:55:13.671699 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 10:55:13.674998 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 10:55:13.681660 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 10:55:13.684793 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 10:55:13.688415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 10:55:13.695354 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 10:55:13.698412 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 10:55:13.702259 1 6 16 | B1->B0 | 3e3e 3131 | 0 0 | (0 0) (0 0)
8382 10:55:13.708250 1 6 20 | B1->B0 | 4444 4545 | 0 0 | (0 0) (1 1)
8383 10:55:13.711790 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 10:55:13.714918 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 10:55:13.721364 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 10:55:13.724591 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 10:55:13.728003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 10:55:13.735289 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 10:55:13.737942 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 10:55:13.741548 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8391 10:55:13.747727 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 10:55:13.751123 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 10:55:13.754655 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 10:55:13.761443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 10:55:13.764665 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 10:55:13.767841 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 10:55:13.771650 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 10:55:13.778266 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 10:55:13.781372 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 10:55:13.784575 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 10:55:13.791203 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:55:13.794494 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:55:13.797653 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:55:13.804601 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 10:55:13.808071 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 10:55:13.811317 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 10:55:13.814629 Total UI for P1: 0, mck2ui 16
8408 10:55:13.818244 best dqsien dly found for B0: ( 1, 9, 14)
8409 10:55:13.821509 Total UI for P1: 0, mck2ui 16
8410 10:55:13.824452 best dqsien dly found for B1: ( 1, 9, 14)
8411 10:55:13.827905 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8412 10:55:13.831264 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8413 10:55:13.831371
8414 10:55:13.838080 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8415 10:55:13.840954 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 10:55:13.844232 [Gating] SW calibration Done
8417 10:55:13.844328 ==
8418 10:55:13.847672 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 10:55:13.851206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 10:55:13.851302 ==
8421 10:55:13.851387 RX Vref Scan: 0
8422 10:55:13.851454
8423 10:55:13.854235 RX Vref 0 -> 0, step: 1
8424 10:55:13.854320
8425 10:55:13.857540 RX Delay 0 -> 252, step: 8
8426 10:55:13.861057 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8427 10:55:13.864736 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8428 10:55:13.870994 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8429 10:55:13.874205 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8430 10:55:13.877580 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8431 10:55:13.880537 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8432 10:55:13.884975 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8433 10:55:13.890885 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8434 10:55:13.894192 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8435 10:55:13.897053 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8436 10:55:13.900472 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8437 10:55:13.903980 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8438 10:55:13.910513 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8439 10:55:13.913841 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8440 10:55:13.917702 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 10:55:13.920331 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 10:55:13.920416 ==
8443 10:55:13.924223 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 10:55:13.930613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 10:55:13.930698 ==
8446 10:55:13.930766 DQS Delay:
8447 10:55:13.930829 DQS0 = 0, DQS1 = 0
8448 10:55:13.934147 DQM Delay:
8449 10:55:13.934230 DQM0 = 135, DQM1 = 128
8450 10:55:13.937190 DQ Delay:
8451 10:55:13.940643 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8452 10:55:13.943522 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8453 10:55:13.947017 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8454 10:55:13.950869 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8455 10:55:13.950952
8456 10:55:13.951018
8457 10:55:13.951081 ==
8458 10:55:13.953693 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 10:55:13.957227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 10:55:13.960502 ==
8461 10:55:13.960585
8462 10:55:13.960651
8463 10:55:13.960710 TX Vref Scan disable
8464 10:55:13.963745 == TX Byte 0 ==
8465 10:55:13.966765 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8466 10:55:13.970468 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8467 10:55:13.973436 == TX Byte 1 ==
8468 10:55:13.977040 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8469 10:55:13.980193 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8470 10:55:13.983626 ==
8471 10:55:13.983709 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 10:55:13.989969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 10:55:13.990055 ==
8474 10:55:14.002335
8475 10:55:14.005492 TX Vref early break, caculate TX vref
8476 10:55:14.008662 TX Vref=16, minBit 8, minWin=21, winSum=366
8477 10:55:14.012253 TX Vref=18, minBit 8, minWin=21, winSum=373
8478 10:55:14.015322 TX Vref=20, minBit 8, minWin=21, winSum=380
8479 10:55:14.019123 TX Vref=22, minBit 8, minWin=23, winSum=393
8480 10:55:14.021983 TX Vref=24, minBit 8, minWin=23, winSum=402
8481 10:55:14.029071 TX Vref=26, minBit 11, minWin=24, winSum=411
8482 10:55:14.032820 TX Vref=28, minBit 8, minWin=24, winSum=416
8483 10:55:14.035491 TX Vref=30, minBit 8, minWin=24, winSum=418
8484 10:55:14.038838 TX Vref=32, minBit 11, minWin=24, winSum=408
8485 10:55:14.042120 TX Vref=34, minBit 8, minWin=23, winSum=395
8486 10:55:14.048909 [TxChooseVref] Worse bit 8, Min win 24, Win sum 418, Final Vref 30
8487 10:55:14.048995
8488 10:55:14.052199 Final TX Range 0 Vref 30
8489 10:55:14.052282
8490 10:55:14.052347 ==
8491 10:55:14.055543 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 10:55:14.059023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 10:55:14.059107 ==
8494 10:55:14.059174
8495 10:55:14.059235
8496 10:55:14.062211 TX Vref Scan disable
8497 10:55:14.068722 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8498 10:55:14.068831 == TX Byte 0 ==
8499 10:55:14.071822 u2DelayCellOfst[0]=17 cells (5 PI)
8500 10:55:14.075293 u2DelayCellOfst[1]=14 cells (4 PI)
8501 10:55:14.078821 u2DelayCellOfst[2]=0 cells (0 PI)
8502 10:55:14.082403 u2DelayCellOfst[3]=7 cells (2 PI)
8503 10:55:14.085047 u2DelayCellOfst[4]=7 cells (2 PI)
8504 10:55:14.088956 u2DelayCellOfst[5]=17 cells (5 PI)
8505 10:55:14.092396 u2DelayCellOfst[6]=17 cells (5 PI)
8506 10:55:14.092508 u2DelayCellOfst[7]=7 cells (2 PI)
8507 10:55:14.099043 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8508 10:55:14.102228 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8509 10:55:14.102336 == TX Byte 1 ==
8510 10:55:14.105375 u2DelayCellOfst[8]=0 cells (0 PI)
8511 10:55:14.108731 u2DelayCellOfst[9]=3 cells (1 PI)
8512 10:55:14.111753 u2DelayCellOfst[10]=10 cells (3 PI)
8513 10:55:14.115476 u2DelayCellOfst[11]=7 cells (2 PI)
8514 10:55:14.118636 u2DelayCellOfst[12]=14 cells (4 PI)
8515 10:55:14.122101 u2DelayCellOfst[13]=17 cells (5 PI)
8516 10:55:14.124996 u2DelayCellOfst[14]=17 cells (5 PI)
8517 10:55:14.128703 u2DelayCellOfst[15]=17 cells (5 PI)
8518 10:55:14.131936 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8519 10:55:14.138752 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8520 10:55:14.138893 DramC Write-DBI on
8521 10:55:14.138966 ==
8522 10:55:14.141591 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 10:55:14.145401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 10:55:14.145500 ==
8525 10:55:14.148269
8526 10:55:14.148356
8527 10:55:14.148423 TX Vref Scan disable
8528 10:55:14.151752 == TX Byte 0 ==
8529 10:55:14.155102 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8530 10:55:14.158495 == TX Byte 1 ==
8531 10:55:14.161457 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8532 10:55:14.164698 DramC Write-DBI off
8533 10:55:14.164787
8534 10:55:14.164854 [DATLAT]
8535 10:55:14.164917 Freq=1600, CH1 RK0
8536 10:55:14.164977
8537 10:55:14.168384 DATLAT Default: 0xf
8538 10:55:14.168468 0, 0xFFFF, sum = 0
8539 10:55:14.171955 1, 0xFFFF, sum = 0
8540 10:55:14.175051 2, 0xFFFF, sum = 0
8541 10:55:14.175136 3, 0xFFFF, sum = 0
8542 10:55:14.178581 4, 0xFFFF, sum = 0
8543 10:55:14.178666 5, 0xFFFF, sum = 0
8544 10:55:14.181296 6, 0xFFFF, sum = 0
8545 10:55:14.181381 7, 0xFFFF, sum = 0
8546 10:55:14.184989 8, 0xFFFF, sum = 0
8547 10:55:14.185074 9, 0xFFFF, sum = 0
8548 10:55:14.188220 10, 0xFFFF, sum = 0
8549 10:55:14.188307 11, 0xFFFF, sum = 0
8550 10:55:14.191254 12, 0xFFFF, sum = 0
8551 10:55:14.191339 13, 0xFFFF, sum = 0
8552 10:55:14.194681 14, 0x0, sum = 1
8553 10:55:14.194766 15, 0x0, sum = 2
8554 10:55:14.198109 16, 0x0, sum = 3
8555 10:55:14.198195 17, 0x0, sum = 4
8556 10:55:14.201393 best_step = 15
8557 10:55:14.201478
8558 10:55:14.201545 ==
8559 10:55:14.204873 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 10:55:14.207893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 10:55:14.207986 ==
8562 10:55:14.211668 RX Vref Scan: 1
8563 10:55:14.211758
8564 10:55:14.211826 Set Vref Range= 24 -> 127
8565 10:55:14.211889
8566 10:55:14.215012 RX Vref 24 -> 127, step: 1
8567 10:55:14.215099
8568 10:55:14.217751 RX Delay 19 -> 252, step: 4
8569 10:55:14.217838
8570 10:55:14.220894 Set Vref, RX VrefLevel [Byte0]: 24
8571 10:55:14.224547 [Byte1]: 24
8572 10:55:14.224646
8573 10:55:14.228225 Set Vref, RX VrefLevel [Byte0]: 25
8574 10:55:14.231009 [Byte1]: 25
8575 10:55:14.234235
8576 10:55:14.234334 Set Vref, RX VrefLevel [Byte0]: 26
8577 10:55:14.237563 [Byte1]: 26
8578 10:55:14.241557
8579 10:55:14.241643 Set Vref, RX VrefLevel [Byte0]: 27
8580 10:55:14.244971 [Byte1]: 27
8581 10:55:14.249189
8582 10:55:14.249277 Set Vref, RX VrefLevel [Byte0]: 28
8583 10:55:14.252590 [Byte1]: 28
8584 10:55:14.257276
8585 10:55:14.257375 Set Vref, RX VrefLevel [Byte0]: 29
8586 10:55:14.260071 [Byte1]: 29
8587 10:55:14.264369
8588 10:55:14.264474 Set Vref, RX VrefLevel [Byte0]: 30
8589 10:55:14.267790 [Byte1]: 30
8590 10:55:14.272200
8591 10:55:14.272289 Set Vref, RX VrefLevel [Byte0]: 31
8592 10:55:14.275635 [Byte1]: 31
8593 10:55:14.279541
8594 10:55:14.279638 Set Vref, RX VrefLevel [Byte0]: 32
8595 10:55:14.283065 [Byte1]: 32
8596 10:55:14.287369
8597 10:55:14.287489 Set Vref, RX VrefLevel [Byte0]: 33
8598 10:55:14.290712 [Byte1]: 33
8599 10:55:14.294894
8600 10:55:14.294998 Set Vref, RX VrefLevel [Byte0]: 34
8601 10:55:14.298165 [Byte1]: 34
8602 10:55:14.302190
8603 10:55:14.302290 Set Vref, RX VrefLevel [Byte0]: 35
8604 10:55:14.305866 [Byte1]: 35
8605 10:55:14.309861
8606 10:55:14.309944 Set Vref, RX VrefLevel [Byte0]: 36
8607 10:55:14.313708 [Byte1]: 36
8608 10:55:14.317635
8609 10:55:14.317719 Set Vref, RX VrefLevel [Byte0]: 37
8610 10:55:14.321118 [Byte1]: 37
8611 10:55:14.324952
8612 10:55:14.325036 Set Vref, RX VrefLevel [Byte0]: 38
8613 10:55:14.328161 [Byte1]: 38
8614 10:55:14.333380
8615 10:55:14.333464 Set Vref, RX VrefLevel [Byte0]: 39
8616 10:55:14.335977 [Byte1]: 39
8617 10:55:14.340297
8618 10:55:14.340383 Set Vref, RX VrefLevel [Byte0]: 40
8619 10:55:14.343492 [Byte1]: 40
8620 10:55:14.348052
8621 10:55:14.348136 Set Vref, RX VrefLevel [Byte0]: 41
8622 10:55:14.351058 [Byte1]: 41
8623 10:55:14.355212
8624 10:55:14.355301 Set Vref, RX VrefLevel [Byte0]: 42
8625 10:55:14.358636 [Byte1]: 42
8626 10:55:14.363136
8627 10:55:14.363221 Set Vref, RX VrefLevel [Byte0]: 43
8628 10:55:14.366649 [Byte1]: 43
8629 10:55:14.370532
8630 10:55:14.370619 Set Vref, RX VrefLevel [Byte0]: 44
8631 10:55:14.374242 [Byte1]: 44
8632 10:55:14.378109
8633 10:55:14.378194 Set Vref, RX VrefLevel [Byte0]: 45
8634 10:55:14.381631 [Byte1]: 45
8635 10:55:14.386058
8636 10:55:14.386142 Set Vref, RX VrefLevel [Byte0]: 46
8637 10:55:14.389348 [Byte1]: 46
8638 10:55:14.393613
8639 10:55:14.393699 Set Vref, RX VrefLevel [Byte0]: 47
8640 10:55:14.396801 [Byte1]: 47
8641 10:55:14.400934
8642 10:55:14.401024 Set Vref, RX VrefLevel [Byte0]: 48
8643 10:55:14.404139 [Byte1]: 48
8644 10:55:14.408769
8645 10:55:14.408854 Set Vref, RX VrefLevel [Byte0]: 49
8646 10:55:14.411972 [Byte1]: 49
8647 10:55:14.416053
8648 10:55:14.416136 Set Vref, RX VrefLevel [Byte0]: 50
8649 10:55:14.419632 [Byte1]: 50
8650 10:55:14.423517
8651 10:55:14.423601 Set Vref, RX VrefLevel [Byte0]: 51
8652 10:55:14.426851 [Byte1]: 51
8653 10:55:14.431110
8654 10:55:14.431194 Set Vref, RX VrefLevel [Byte0]: 52
8655 10:55:14.434268 [Byte1]: 52
8656 10:55:14.438553
8657 10:55:14.438637 Set Vref, RX VrefLevel [Byte0]: 53
8658 10:55:14.441789 [Byte1]: 53
8659 10:55:14.446103
8660 10:55:14.446185 Set Vref, RX VrefLevel [Byte0]: 54
8661 10:55:14.449510 [Byte1]: 54
8662 10:55:14.454264
8663 10:55:14.454346 Set Vref, RX VrefLevel [Byte0]: 55
8664 10:55:14.457323 [Byte1]: 55
8665 10:55:14.461203
8666 10:55:14.461287 Set Vref, RX VrefLevel [Byte0]: 56
8667 10:55:14.465258 [Byte1]: 56
8668 10:55:14.468894
8669 10:55:14.468975 Set Vref, RX VrefLevel [Byte0]: 57
8670 10:55:14.472026 [Byte1]: 57
8671 10:55:14.476419
8672 10:55:14.476511 Set Vref, RX VrefLevel [Byte0]: 58
8673 10:55:14.479699 [Byte1]: 58
8674 10:55:14.484283
8675 10:55:14.484386 Set Vref, RX VrefLevel [Byte0]: 59
8676 10:55:14.487670 [Byte1]: 59
8677 10:55:14.491775
8678 10:55:14.491876 Set Vref, RX VrefLevel [Byte0]: 60
8679 10:55:14.495193 [Byte1]: 60
8680 10:55:14.499893
8681 10:55:14.500001 Set Vref, RX VrefLevel [Byte0]: 61
8682 10:55:14.502814 [Byte1]: 61
8683 10:55:14.507056
8684 10:55:14.507161 Set Vref, RX VrefLevel [Byte0]: 62
8685 10:55:14.510339 [Byte1]: 62
8686 10:55:14.514267
8687 10:55:14.514381 Set Vref, RX VrefLevel [Byte0]: 63
8688 10:55:14.517643 [Byte1]: 63
8689 10:55:14.522276
8690 10:55:14.522389 Set Vref, RX VrefLevel [Byte0]: 64
8691 10:55:14.525736 [Byte1]: 64
8692 10:55:14.529454
8693 10:55:14.529568 Set Vref, RX VrefLevel [Byte0]: 65
8694 10:55:14.532715 [Byte1]: 65
8695 10:55:14.536982
8696 10:55:14.537091 Set Vref, RX VrefLevel [Byte0]: 66
8697 10:55:14.540731 [Byte1]: 66
8698 10:55:14.544698
8699 10:55:14.544800 Set Vref, RX VrefLevel [Byte0]: 67
8700 10:55:14.547779 [Byte1]: 67
8701 10:55:14.552136
8702 10:55:14.552278 Set Vref, RX VrefLevel [Byte0]: 68
8703 10:55:14.555911 [Byte1]: 68
8704 10:55:14.559719
8705 10:55:14.559829 Set Vref, RX VrefLevel [Byte0]: 69
8706 10:55:14.563534 [Byte1]: 69
8707 10:55:14.567240
8708 10:55:14.567357 Set Vref, RX VrefLevel [Byte0]: 70
8709 10:55:14.570461 [Byte1]: 70
8710 10:55:14.574918
8711 10:55:14.575012 Set Vref, RX VrefLevel [Byte0]: 71
8712 10:55:14.578458 [Byte1]: 71
8713 10:55:14.582300
8714 10:55:14.582440 Set Vref, RX VrefLevel [Byte0]: 72
8715 10:55:14.585747 [Byte1]: 72
8716 10:55:14.590437
8717 10:55:14.590597 Set Vref, RX VrefLevel [Byte0]: 73
8718 10:55:14.593839 [Byte1]: 73
8719 10:55:14.597855
8720 10:55:14.597979 Set Vref, RX VrefLevel [Byte0]: 74
8721 10:55:14.601120 [Byte1]: 74
8722 10:55:14.605380
8723 10:55:14.605501 Set Vref, RX VrefLevel [Byte0]: 75
8724 10:55:14.608537 [Byte1]: 75
8725 10:55:14.613000
8726 10:55:14.613125 Final RX Vref Byte 0 = 59 to rank0
8727 10:55:14.616155 Final RX Vref Byte 1 = 56 to rank0
8728 10:55:14.619734 Final RX Vref Byte 0 = 59 to rank1
8729 10:55:14.622961 Final RX Vref Byte 1 = 56 to rank1==
8730 10:55:14.626121 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 10:55:14.632563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 10:55:14.632674 ==
8733 10:55:14.632748 DQS Delay:
8734 10:55:14.636122 DQS0 = 0, DQS1 = 0
8735 10:55:14.636208 DQM Delay:
8736 10:55:14.636276 DQM0 = 131, DQM1 = 124
8737 10:55:14.639202 DQ Delay:
8738 10:55:14.642532 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8739 10:55:14.645742 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8740 10:55:14.648825 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8741 10:55:14.652724 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8742 10:55:14.652823
8743 10:55:14.652896
8744 10:55:14.652989
8745 10:55:14.655560 [DramC_TX_OE_Calibration] TA2
8746 10:55:14.659522 Original DQ_B0 (3 6) =30, OEN = 27
8747 10:55:14.662686 Original DQ_B1 (3 6) =30, OEN = 27
8748 10:55:14.665885 24, 0x0, End_B0=24 End_B1=24
8749 10:55:14.665970 25, 0x0, End_B0=25 End_B1=25
8750 10:55:14.669084 26, 0x0, End_B0=26 End_B1=26
8751 10:55:14.672284 27, 0x0, End_B0=27 End_B1=27
8752 10:55:14.675595 28, 0x0, End_B0=28 End_B1=28
8753 10:55:14.679129 29, 0x0, End_B0=29 End_B1=29
8754 10:55:14.679243 30, 0x0, End_B0=30 End_B1=30
8755 10:55:14.682219 31, 0x4141, End_B0=30 End_B1=30
8756 10:55:14.685692 Byte0 end_step=30 best_step=27
8757 10:55:14.689118 Byte1 end_step=30 best_step=27
8758 10:55:14.692011 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 10:55:14.695523 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 10:55:14.695616
8761 10:55:14.695685
8762 10:55:14.702438 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8763 10:55:14.705811 CH1 RK0: MR19=302, MR18=13FD
8764 10:55:14.712495 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8765 10:55:14.712601
8766 10:55:14.715870 ----->DramcWriteLeveling(PI) begin...
8767 10:55:14.715959 ==
8768 10:55:14.718633 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 10:55:14.722434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 10:55:14.722519 ==
8771 10:55:14.725502 Write leveling (Byte 0): 25 => 25
8772 10:55:14.728933 Write leveling (Byte 1): 28 => 28
8773 10:55:14.732159 DramcWriteLeveling(PI) end<-----
8774 10:55:14.732244
8775 10:55:14.732310 ==
8776 10:55:14.735976 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 10:55:14.739234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 10:55:14.739318 ==
8779 10:55:14.742340 [Gating] SW mode calibration
8780 10:55:14.748914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 10:55:14.755722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 10:55:14.758993 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 10:55:14.762262 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 10:55:14.768694 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8785 10:55:14.772007 1 4 12 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
8786 10:55:14.775541 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 10:55:14.782227 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 10:55:14.785639 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 10:55:14.789021 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 10:55:14.795202 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 10:55:14.798463 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8792 10:55:14.801987 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8793 10:55:14.808826 1 5 12 | B1->B0 | 2929 2424 | 0 0 | (1 0) (0 0)
8794 10:55:14.811588 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 10:55:14.814887 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 10:55:14.821835 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 10:55:14.825021 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 10:55:14.828055 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 10:55:14.834668 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 10:55:14.838214 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8801 10:55:14.841550 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8802 10:55:14.848311 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 10:55:14.851965 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 10:55:14.854635 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 10:55:14.861398 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 10:55:14.865227 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 10:55:14.868437 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8808 10:55:14.874661 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8809 10:55:14.878866 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 10:55:14.881495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:55:14.887778 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:55:14.891691 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 10:55:14.895036 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 10:55:14.901314 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 10:55:14.904548 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 10:55:14.907971 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 10:55:14.914438 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 10:55:14.918523 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 10:55:14.921199 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 10:55:14.928102 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:55:14.931191 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 10:55:14.934532 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 10:55:14.937903 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8824 10:55:14.944920 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8825 10:55:14.949081 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 10:55:14.951498 Total UI for P1: 0, mck2ui 16
8827 10:55:14.954478 best dqsien dly found for B0: ( 1, 9, 6)
8828 10:55:14.957908 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 10:55:14.961168 Total UI for P1: 0, mck2ui 16
8830 10:55:14.964151 best dqsien dly found for B1: ( 1, 9, 10)
8831 10:55:14.967569 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8832 10:55:14.971229 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8833 10:55:14.974454
8834 10:55:14.978037 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8835 10:55:14.981007 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8836 10:55:14.984414 [Gating] SW calibration Done
8837 10:55:14.984502 ==
8838 10:55:14.987511 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 10:55:14.991485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 10:55:14.991573 ==
8841 10:55:14.991659 RX Vref Scan: 0
8842 10:55:14.991738
8843 10:55:14.994614 RX Vref 0 -> 0, step: 1
8844 10:55:14.994702
8845 10:55:14.997533 RX Delay 0 -> 252, step: 8
8846 10:55:15.000890 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8847 10:55:15.004214 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8848 10:55:15.011097 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8849 10:55:15.014217 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8850 10:55:15.017452 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8851 10:55:15.020943 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8852 10:55:15.024265 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8853 10:55:15.031193 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8854 10:55:15.034429 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8855 10:55:15.037349 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8856 10:55:15.041151 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8857 10:55:15.044538 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8858 10:55:15.051131 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8859 10:55:15.054208 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8860 10:55:15.057281 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8861 10:55:15.060625 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8862 10:55:15.060726 ==
8863 10:55:15.063838 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 10:55:15.070438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 10:55:15.070566 ==
8866 10:55:15.070667 DQS Delay:
8867 10:55:15.070748 DQS0 = 0, DQS1 = 0
8868 10:55:15.073906 DQM Delay:
8869 10:55:15.073994 DQM0 = 132, DQM1 = 127
8870 10:55:15.077663 DQ Delay:
8871 10:55:15.080786 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8872 10:55:15.084443 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8873 10:55:15.087359 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8874 10:55:15.090763 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8875 10:55:15.090861
8876 10:55:15.090950
8877 10:55:15.091029 ==
8878 10:55:15.094140 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 10:55:15.097086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 10:55:15.097182 ==
8881 10:55:15.100431
8882 10:55:15.100523
8883 10:55:15.100608 TX Vref Scan disable
8884 10:55:15.104015 == TX Byte 0 ==
8885 10:55:15.107521 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8886 10:55:15.110358 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 10:55:15.113772 == TX Byte 1 ==
8888 10:55:15.117396 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8889 10:55:15.120444 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8890 10:55:15.120534 ==
8891 10:55:15.123905 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 10:55:15.130798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 10:55:15.130908 ==
8894 10:55:15.143467
8895 10:55:15.146621 TX Vref early break, caculate TX vref
8896 10:55:15.150355 TX Vref=16, minBit 8, minWin=21, winSum=375
8897 10:55:15.153770 TX Vref=18, minBit 9, minWin=22, winSum=386
8898 10:55:15.157058 TX Vref=20, minBit 8, minWin=23, winSum=396
8899 10:55:15.160256 TX Vref=22, minBit 6, minWin=24, winSum=403
8900 10:55:15.163554 TX Vref=24, minBit 10, minWin=24, winSum=411
8901 10:55:15.170199 TX Vref=26, minBit 8, minWin=25, winSum=417
8902 10:55:15.173594 TX Vref=28, minBit 5, minWin=25, winSum=422
8903 10:55:15.176770 TX Vref=30, minBit 9, minWin=25, winSum=419
8904 10:55:15.179938 TX Vref=32, minBit 15, minWin=24, winSum=411
8905 10:55:15.183215 TX Vref=34, minBit 8, minWin=24, winSum=405
8906 10:55:15.186512 TX Vref=36, minBit 4, minWin=24, winSum=397
8907 10:55:15.193900 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 28
8908 10:55:15.194031
8909 10:55:15.196319 Final TX Range 0 Vref 28
8910 10:55:15.196404
8911 10:55:15.196469 ==
8912 10:55:15.200607 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 10:55:15.202997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 10:55:15.203084 ==
8915 10:55:15.203150
8916 10:55:15.206624
8917 10:55:15.206706 TX Vref Scan disable
8918 10:55:15.213440 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8919 10:55:15.213561 == TX Byte 0 ==
8920 10:55:15.216286 u2DelayCellOfst[0]=17 cells (5 PI)
8921 10:55:15.219782 u2DelayCellOfst[1]=10 cells (3 PI)
8922 10:55:15.223056 u2DelayCellOfst[2]=0 cells (0 PI)
8923 10:55:15.226292 u2DelayCellOfst[3]=7 cells (2 PI)
8924 10:55:15.229724 u2DelayCellOfst[4]=7 cells (2 PI)
8925 10:55:15.233086 u2DelayCellOfst[5]=21 cells (6 PI)
8926 10:55:15.236754 u2DelayCellOfst[6]=17 cells (5 PI)
8927 10:55:15.240006 u2DelayCellOfst[7]=7 cells (2 PI)
8928 10:55:15.243244 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8929 10:55:15.246665 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 10:55:15.249556 == TX Byte 1 ==
8931 10:55:15.252843 u2DelayCellOfst[8]=0 cells (0 PI)
8932 10:55:15.256052 u2DelayCellOfst[9]=3 cells (1 PI)
8933 10:55:15.259604 u2DelayCellOfst[10]=10 cells (3 PI)
8934 10:55:15.259720 u2DelayCellOfst[11]=7 cells (2 PI)
8935 10:55:15.262750 u2DelayCellOfst[12]=14 cells (4 PI)
8936 10:55:15.266953 u2DelayCellOfst[13]=14 cells (4 PI)
8937 10:55:15.269308 u2DelayCellOfst[14]=17 cells (5 PI)
8938 10:55:15.272720 u2DelayCellOfst[15]=14 cells (4 PI)
8939 10:55:15.279087 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8940 10:55:15.282753 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8941 10:55:15.282852 DramC Write-DBI on
8942 10:55:15.286180 ==
8943 10:55:15.286267 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 10:55:15.292650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 10:55:15.292752 ==
8946 10:55:15.292821
8947 10:55:15.292882
8948 10:55:15.295669 TX Vref Scan disable
8949 10:55:15.295755 == TX Byte 0 ==
8950 10:55:15.302810 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 10:55:15.302922 == TX Byte 1 ==
8952 10:55:15.305648 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8953 10:55:15.308965 DramC Write-DBI off
8954 10:55:15.309053
8955 10:55:15.309119 [DATLAT]
8956 10:55:15.312358 Freq=1600, CH1 RK1
8957 10:55:15.312447
8958 10:55:15.312514 DATLAT Default: 0xf
8959 10:55:15.315869 0, 0xFFFF, sum = 0
8960 10:55:15.315959 1, 0xFFFF, sum = 0
8961 10:55:15.318800 2, 0xFFFF, sum = 0
8962 10:55:15.318888 3, 0xFFFF, sum = 0
8963 10:55:15.322438 4, 0xFFFF, sum = 0
8964 10:55:15.322526 5, 0xFFFF, sum = 0
8965 10:55:15.326211 6, 0xFFFF, sum = 0
8966 10:55:15.326299 7, 0xFFFF, sum = 0
8967 10:55:15.329065 8, 0xFFFF, sum = 0
8968 10:55:15.329153 9, 0xFFFF, sum = 0
8969 10:55:15.332380 10, 0xFFFF, sum = 0
8970 10:55:15.335854 11, 0xFFFF, sum = 0
8971 10:55:15.335943 12, 0xFFFF, sum = 0
8972 10:55:15.338591 13, 0xFFFF, sum = 0
8973 10:55:15.338675 14, 0x0, sum = 1
8974 10:55:15.342035 15, 0x0, sum = 2
8975 10:55:15.342121 16, 0x0, sum = 3
8976 10:55:15.345860 17, 0x0, sum = 4
8977 10:55:15.345947 best_step = 15
8978 10:55:15.346014
8979 10:55:15.346074 ==
8980 10:55:15.348741 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 10:55:15.352119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 10:55:15.352212 ==
8983 10:55:15.355535 RX Vref Scan: 0
8984 10:55:15.355622
8985 10:55:15.358517 RX Vref 0 -> 0, step: 1
8986 10:55:15.358603
8987 10:55:15.358668 RX Delay 11 -> 252, step: 4
8988 10:55:15.365482 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8989 10:55:15.369060 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8990 10:55:15.372214 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8991 10:55:15.375341 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8992 10:55:15.378702 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8993 10:55:15.385398 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8994 10:55:15.388953 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8995 10:55:15.392142 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8996 10:55:15.395638 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8997 10:55:15.398909 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8998 10:55:15.405286 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8999 10:55:15.408704 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9000 10:55:15.412130 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9001 10:55:15.416003 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9002 10:55:15.422471 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
9003 10:55:15.425861 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9004 10:55:15.425971 ==
9005 10:55:15.428949 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 10:55:15.432425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 10:55:15.432509 ==
9008 10:55:15.432575 DQS Delay:
9009 10:55:15.435162 DQS0 = 0, DQS1 = 0
9010 10:55:15.435245 DQM Delay:
9011 10:55:15.439107 DQM0 = 129, DQM1 = 126
9012 10:55:15.439192 DQ Delay:
9013 10:55:15.441945 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9014 10:55:15.445279 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9015 10:55:15.448747 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9016 10:55:15.455535 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9017 10:55:15.455626
9018 10:55:15.455692
9019 10:55:15.455753
9020 10:55:15.455812 [DramC_TX_OE_Calibration] TA2
9021 10:55:15.458890 Original DQ_B0 (3 6) =30, OEN = 27
9022 10:55:15.461889 Original DQ_B1 (3 6) =30, OEN = 27
9023 10:55:15.465653 24, 0x0, End_B0=24 End_B1=24
9024 10:55:15.468559 25, 0x0, End_B0=25 End_B1=25
9025 10:55:15.472114 26, 0x0, End_B0=26 End_B1=26
9026 10:55:15.472201 27, 0x0, End_B0=27 End_B1=27
9027 10:55:15.475334 28, 0x0, End_B0=28 End_B1=28
9028 10:55:15.478575 29, 0x0, End_B0=29 End_B1=29
9029 10:55:15.482844 30, 0x0, End_B0=30 End_B1=30
9030 10:55:15.485635 31, 0x4141, End_B0=30 End_B1=30
9031 10:55:15.485752 Byte0 end_step=30 best_step=27
9032 10:55:15.488981 Byte1 end_step=30 best_step=27
9033 10:55:15.492117 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 10:55:15.495218 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 10:55:15.495302
9036 10:55:15.495410
9037 10:55:15.505633 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9038 10:55:15.505733 CH1 RK1: MR19=303, MR18=1016
9039 10:55:15.511870 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9040 10:55:15.515080 [RxdqsGatingPostProcess] freq 1600
9041 10:55:15.521959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 10:55:15.525357 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 10:55:15.529014 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 10:55:15.531566 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 10:55:15.531653 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 10:55:15.534990 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 10:55:15.538490 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 10:55:15.542182 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 10:55:15.544932 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 10:55:15.548689 Pre-setting of DQS Precalculation
9051 10:55:15.555246 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 10:55:15.561546 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 10:55:15.568460 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 10:55:15.568559
9055 10:55:15.568627
9056 10:55:15.571979 [Calibration Summary] 3200 Mbps
9057 10:55:15.572064 CH 0, Rank 0
9058 10:55:15.575000 SW Impedance : PASS
9059 10:55:15.578302 DUTY Scan : NO K
9060 10:55:15.578388 ZQ Calibration : PASS
9061 10:55:15.581537 Jitter Meter : NO K
9062 10:55:15.585036 CBT Training : PASS
9063 10:55:15.585121 Write leveling : PASS
9064 10:55:15.588339 RX DQS gating : PASS
9065 10:55:15.588424 RX DQ/DQS(RDDQC) : PASS
9066 10:55:15.591305 TX DQ/DQS : PASS
9067 10:55:15.595306 RX DATLAT : PASS
9068 10:55:15.595408 RX DQ/DQS(Engine): PASS
9069 10:55:15.597811 TX OE : PASS
9070 10:55:15.597898 All Pass.
9071 10:55:15.597966
9072 10:55:15.601356 CH 0, Rank 1
9073 10:55:15.601443 SW Impedance : PASS
9074 10:55:15.604730 DUTY Scan : NO K
9075 10:55:15.607683 ZQ Calibration : PASS
9076 10:55:15.607817 Jitter Meter : NO K
9077 10:55:15.611529 CBT Training : PASS
9078 10:55:15.614481 Write leveling : PASS
9079 10:55:15.614589 RX DQS gating : PASS
9080 10:55:15.617824 RX DQ/DQS(RDDQC) : PASS
9081 10:55:15.621172 TX DQ/DQS : PASS
9082 10:55:15.621260 RX DATLAT : PASS
9083 10:55:15.624805 RX DQ/DQS(Engine): PASS
9084 10:55:15.628023 TX OE : PASS
9085 10:55:15.628110 All Pass.
9086 10:55:15.628177
9087 10:55:15.628237 CH 1, Rank 0
9088 10:55:15.631451 SW Impedance : PASS
9089 10:55:15.634909 DUTY Scan : NO K
9090 10:55:15.634992 ZQ Calibration : PASS
9091 10:55:15.637753 Jitter Meter : NO K
9092 10:55:15.641481 CBT Training : PASS
9093 10:55:15.641564 Write leveling : PASS
9094 10:55:15.644574 RX DQS gating : PASS
9095 10:55:15.644656 RX DQ/DQS(RDDQC) : PASS
9096 10:55:15.648096 TX DQ/DQS : PASS
9097 10:55:15.651215 RX DATLAT : PASS
9098 10:55:15.651298 RX DQ/DQS(Engine): PASS
9099 10:55:15.654620 TX OE : PASS
9100 10:55:15.654704 All Pass.
9101 10:55:15.654769
9102 10:55:15.658146 CH 1, Rank 1
9103 10:55:15.658230 SW Impedance : PASS
9104 10:55:15.661040 DUTY Scan : NO K
9105 10:55:15.664506 ZQ Calibration : PASS
9106 10:55:15.664598 Jitter Meter : NO K
9107 10:55:15.667999 CBT Training : PASS
9108 10:55:15.671325 Write leveling : PASS
9109 10:55:15.671460 RX DQS gating : PASS
9110 10:55:15.674120 RX DQ/DQS(RDDQC) : PASS
9111 10:55:15.677992 TX DQ/DQS : PASS
9112 10:55:15.678078 RX DATLAT : PASS
9113 10:55:15.680751 RX DQ/DQS(Engine): PASS
9114 10:55:15.684222 TX OE : PASS
9115 10:55:15.684307 All Pass.
9116 10:55:15.684374
9117 10:55:15.684435 DramC Write-DBI on
9118 10:55:15.687686 PER_BANK_REFRESH: Hybrid Mode
9119 10:55:15.691112 TX_TRACKING: ON
9120 10:55:15.697750 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 10:55:15.707617 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 10:55:15.714125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 10:55:15.717719 [FAST_K] Save calibration result to emmc
9124 10:55:15.720806 sync common calibartion params.
9125 10:55:15.720888 sync cbt_mode0:1, 1:1
9126 10:55:15.724438 dram_init: ddr_geometry: 2
9127 10:55:15.727284 dram_init: ddr_geometry: 2
9128 10:55:15.731310 dram_init: ddr_geometry: 2
9129 10:55:15.731446 0:dram_rank_size:100000000
9130 10:55:15.734666 1:dram_rank_size:100000000
9131 10:55:15.740599 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 10:55:15.740686 DFS_SHUFFLE_HW_MODE: ON
9133 10:55:15.747203 dramc_set_vcore_voltage set vcore to 725000
9134 10:55:15.747288 Read voltage for 1600, 0
9135 10:55:15.750706 Vio18 = 0
9136 10:55:15.750788 Vcore = 725000
9137 10:55:15.750853 Vdram = 0
9138 10:55:15.753915 Vddq = 0
9139 10:55:15.753996 Vmddr = 0
9140 10:55:15.757507 switch to 3200 Mbps bootup
9141 10:55:15.757589 [DramcRunTimeConfig]
9142 10:55:15.757654 PHYPLL
9143 10:55:15.760644 DPM_CONTROL_AFTERK: ON
9144 10:55:15.764135 PER_BANK_REFRESH: ON
9145 10:55:15.764216 REFRESH_OVERHEAD_REDUCTION: ON
9146 10:55:15.767061 CMD_PICG_NEW_MODE: OFF
9147 10:55:15.770852 XRTWTW_NEW_MODE: ON
9148 10:55:15.770933 XRTRTR_NEW_MODE: ON
9149 10:55:15.774298 TX_TRACKING: ON
9150 10:55:15.774379 RDSEL_TRACKING: OFF
9151 10:55:15.777271 DQS Precalculation for DVFS: ON
9152 10:55:15.777353 RX_TRACKING: OFF
9153 10:55:15.780841 HW_GATING DBG: ON
9154 10:55:15.780923 ZQCS_ENABLE_LP4: ON
9155 10:55:15.783555 RX_PICG_NEW_MODE: ON
9156 10:55:15.787063 TX_PICG_NEW_MODE: ON
9157 10:55:15.787145 ENABLE_RX_DCM_DPHY: ON
9158 10:55:15.790431 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 10:55:15.793540 DUMMY_READ_FOR_TRACKING: OFF
9160 10:55:15.796930 !!! SPM_CONTROL_AFTERK: OFF
9161 10:55:15.800189 !!! SPM could not control APHY
9162 10:55:15.800270 IMPEDANCE_TRACKING: ON
9163 10:55:15.804032 TEMP_SENSOR: ON
9164 10:55:15.804122 HW_SAVE_FOR_SR: OFF
9165 10:55:15.806724 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 10:55:15.810406 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 10:55:15.813563 Read ODT Tracking: ON
9168 10:55:15.813645 Refresh Rate DeBounce: ON
9169 10:55:15.817036 DFS_NO_QUEUE_FLUSH: ON
9170 10:55:15.819944 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 10:55:15.823677 ENABLE_DFS_RUNTIME_MRW: OFF
9172 10:55:15.823759 DDR_RESERVE_NEW_MODE: ON
9173 10:55:15.826763 MR_CBT_SWITCH_FREQ: ON
9174 10:55:15.830061 =========================
9175 10:55:15.848516 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 10:55:15.851685 dram_init: ddr_geometry: 2
9177 10:55:15.869693 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 10:55:15.873085 dram_init: dram init end (result: 0)
9179 10:55:15.879981 DRAM-K: Full calibration passed in 24595 msecs
9180 10:55:15.883250 MRC: failed to locate region type 0.
9181 10:55:15.883384 DRAM rank0 size:0x100000000,
9182 10:55:15.886750 DRAM rank1 size=0x100000000
9183 10:55:15.896561 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 10:55:15.903026 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 10:55:15.909641 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 10:55:15.916341 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 10:55:15.919450 DRAM rank0 size:0x100000000,
9188 10:55:15.922668 DRAM rank1 size=0x100000000
9189 10:55:15.922749 CBMEM:
9190 10:55:15.926678 IMD: root @ 0xfffff000 254 entries.
9191 10:55:15.929775 IMD: root @ 0xffffec00 62 entries.
9192 10:55:15.932883 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 10:55:15.936229 WARNING: RO_VPD is uninitialized or empty.
9194 10:55:15.942742 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 10:55:15.950188 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 10:55:15.962420 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9197 10:55:15.974024 BS: romstage times (exec / console): total (unknown) / 24100 ms
9198 10:55:15.974125
9199 10:55:15.974190
9200 10:55:15.984473 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 10:55:15.987213 ARM64: Exception handlers installed.
9202 10:55:15.990735 ARM64: Testing exception
9203 10:55:15.993551 ARM64: Done test exception
9204 10:55:15.993632 Enumerating buses...
9205 10:55:15.996926 Show all devs... Before device enumeration.
9206 10:55:16.000198 Root Device: enabled 1
9207 10:55:16.003660 CPU_CLUSTER: 0: enabled 1
9208 10:55:16.003740 CPU: 00: enabled 1
9209 10:55:16.006993 Compare with tree...
9210 10:55:16.007073 Root Device: enabled 1
9211 10:55:16.010509 CPU_CLUSTER: 0: enabled 1
9212 10:55:16.013650 CPU: 00: enabled 1
9213 10:55:16.013732 Root Device scanning...
9214 10:55:16.016698 scan_static_bus for Root Device
9215 10:55:16.020056 CPU_CLUSTER: 0 enabled
9216 10:55:16.023886 scan_static_bus for Root Device done
9217 10:55:16.026699 scan_bus: bus Root Device finished in 8 msecs
9218 10:55:16.026810 done
9219 10:55:16.033687 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 10:55:16.036966 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 10:55:16.043368 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 10:55:16.047072 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 10:55:16.050462 Allocating resources...
9224 10:55:16.053495 Reading resources...
9225 10:55:16.057048 Root Device read_resources bus 0 link: 0
9226 10:55:16.060726 DRAM rank0 size:0x100000000,
9227 10:55:16.060808 DRAM rank1 size=0x100000000
9228 10:55:16.063323 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 10:55:16.066644 CPU: 00 missing read_resources
9230 10:55:16.073304 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 10:55:16.076409 Root Device read_resources bus 0 link: 0 done
9232 10:55:16.076504 Done reading resources.
9233 10:55:16.083160 Show resources in subtree (Root Device)...After reading.
9234 10:55:16.086602 Root Device child on link 0 CPU_CLUSTER: 0
9235 10:55:16.090640 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 10:55:16.100069 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 10:55:16.100166 CPU: 00
9238 10:55:16.103366 Root Device assign_resources, bus 0 link: 0
9239 10:55:16.106195 CPU_CLUSTER: 0 missing set_resources
9240 10:55:16.113069 Root Device assign_resources, bus 0 link: 0 done
9241 10:55:16.113153 Done setting resources.
9242 10:55:16.119732 Show resources in subtree (Root Device)...After assigning values.
9243 10:55:16.123757 Root Device child on link 0 CPU_CLUSTER: 0
9244 10:55:16.126309 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 10:55:16.136687 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 10:55:16.136794 CPU: 00
9247 10:55:16.139561 Done allocating resources.
9248 10:55:16.146257 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 10:55:16.146349 Enabling resources...
9250 10:55:16.146417 done.
9251 10:55:16.152913 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 10:55:16.153000 Initializing devices...
9253 10:55:16.156746 Root Device init
9254 10:55:16.156828 init hardware done!
9255 10:55:16.159868 0x00000018: ctrlr->caps
9256 10:55:16.162722 52.000 MHz: ctrlr->f_max
9257 10:55:16.162806 0.400 MHz: ctrlr->f_min
9258 10:55:16.166187 0x40ff8080: ctrlr->voltages
9259 10:55:16.169851 sclk: 390625
9260 10:55:16.169932 Bus Width = 1
9261 10:55:16.169997 sclk: 390625
9262 10:55:16.172839 Bus Width = 1
9263 10:55:16.172920 Early init status = 3
9264 10:55:16.179755 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 10:55:16.182799 in-header: 03 fc 00 00 01 00 00 00
9266 10:55:16.186025 in-data: 00
9267 10:55:16.189361 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 10:55:16.194482 in-header: 03 fd 00 00 00 00 00 00
9269 10:55:16.198586 in-data:
9270 10:55:16.201670 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 10:55:16.206119 in-header: 03 fc 00 00 01 00 00 00
9272 10:55:16.209650 in-data: 00
9273 10:55:16.212174 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 10:55:16.217885 in-header: 03 fd 00 00 00 00 00 00
9275 10:55:16.221318 in-data:
9276 10:55:16.224749 [SSUSB] Setting up USB HOST controller...
9277 10:55:16.228442 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 10:55:16.231213 [SSUSB] phy power-on done.
9279 10:55:16.234677 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 10:55:16.241257 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 10:55:16.244923 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 10:55:16.250987 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 10:55:16.258231 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9284 10:55:16.264315 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 10:55:16.271478 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 10:55:16.277675 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9287 10:55:16.281477 SPM: binary array size = 0x9dc
9288 10:55:16.284453 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 10:55:16.291272 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 10:55:16.297972 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 10:55:16.301162 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 10:55:16.307242 configure_display: Starting display init
9293 10:55:16.341345 anx7625_power_on_init: Init interface.
9294 10:55:16.344825 anx7625_disable_pd_protocol: Disabled PD feature.
9295 10:55:16.347697 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 10:55:16.375914 anx7625_start_dp_work: Secure OCM version=00
9297 10:55:16.379185 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 10:55:16.394238 sp_tx_get_edid_block: EDID Block = 1
9299 10:55:16.496361 Extracted contents:
9300 10:55:16.499995 header: 00 ff ff ff ff ff ff 00
9301 10:55:16.503018 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 10:55:16.506244 version: 01 04
9303 10:55:16.509703 basic params: 95 1f 11 78 0a
9304 10:55:16.513068 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 10:55:16.516406 established: 00 00 00
9306 10:55:16.522721 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 10:55:16.526144 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 10:55:16.532764 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 10:55:16.539377 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 10:55:16.545899 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 10:55:16.549034 extensions: 00
9312 10:55:16.549124 checksum: fb
9313 10:55:16.549189
9314 10:55:16.552623 Manufacturer: IVO Model 57d Serial Number 0
9315 10:55:16.555996 Made week 0 of 2020
9316 10:55:16.556107 EDID version: 1.4
9317 10:55:16.559391 Digital display
9318 10:55:16.562510 6 bits per primary color channel
9319 10:55:16.562596 DisplayPort interface
9320 10:55:16.565654 Maximum image size: 31 cm x 17 cm
9321 10:55:16.569468 Gamma: 220%
9322 10:55:16.569558 Check DPMS levels
9323 10:55:16.572414 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 10:55:16.579585 First detailed timing is preferred timing
9325 10:55:16.579739 Established timings supported:
9326 10:55:16.582207 Standard timings supported:
9327 10:55:16.585528 Detailed timings
9328 10:55:16.589226 Hex of detail: 383680a07038204018303c0035ae10000019
9329 10:55:16.592637 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 10:55:16.599138 0780 0798 07c8 0820 hborder 0
9331 10:55:16.602745 0438 043b 0447 0458 vborder 0
9332 10:55:16.605488 -hsync -vsync
9333 10:55:16.605573 Did detailed timing
9334 10:55:16.612538 Hex of detail: 000000000000000000000000000000000000
9335 10:55:16.615866 Manufacturer-specified data, tag 0
9336 10:55:16.619175 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 10:55:16.622182 ASCII string: InfoVision
9338 10:55:16.625433 Hex of detail: 000000fe00523134304e574635205248200a
9339 10:55:16.628794 ASCII string: R140NWF5 RH
9340 10:55:16.628884 Checksum
9341 10:55:16.632349 Checksum: 0xfb (valid)
9342 10:55:16.635455 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 10:55:16.639045 DSI data_rate: 832800000 bps
9344 10:55:16.645406 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 10:55:16.649072 anx7625_parse_edid: pixelclock(138800).
9346 10:55:16.652104 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 10:55:16.655550 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 10:55:16.658693 anx7625_dsi_config: config dsi.
9349 10:55:16.665213 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 10:55:16.678496 anx7625_dsi_config: success to config DSI
9351 10:55:16.681691 anx7625_dp_start: MIPI phy setup OK.
9352 10:55:16.684865 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 10:55:16.688074 mtk_ddp_mode_set invalid vrefresh 60
9354 10:55:16.691961 main_disp_path_setup
9355 10:55:16.692051 ovl_layer_smi_id_en
9356 10:55:16.695164 ovl_layer_smi_id_en
9357 10:55:16.695249 ccorr_config
9358 10:55:16.695315 aal_config
9359 10:55:16.698661 gamma_config
9360 10:55:16.698746 postmask_config
9361 10:55:16.701541 dither_config
9362 10:55:16.704824 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 10:55:16.711463 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 10:55:16.714847 Root Device init finished in 555 msecs
9365 10:55:16.718148 CPU_CLUSTER: 0 init
9366 10:55:16.724881 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 10:55:16.728154 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 10:55:16.731206 APU_MBOX 0x190000b0 = 0x10001
9369 10:55:16.734544 APU_MBOX 0x190001b0 = 0x10001
9370 10:55:16.738059 APU_MBOX 0x190005b0 = 0x10001
9371 10:55:16.741881 APU_MBOX 0x190006b0 = 0x10001
9372 10:55:16.744455 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 10:55:16.757853 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9374 10:55:16.769783 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 10:55:16.776550 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 10:55:16.788051 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9377 10:55:16.797130 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 10:55:16.800719 CPU_CLUSTER: 0 init finished in 81 msecs
9379 10:55:16.804186 Devices initialized
9380 10:55:16.807072 Show all devs... After init.
9381 10:55:16.807159 Root Device: enabled 1
9382 10:55:16.810606 CPU_CLUSTER: 0: enabled 1
9383 10:55:16.814157 CPU: 00: enabled 1
9384 10:55:16.817078 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9385 10:55:16.820821 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 10:55:16.823563 ELOG: NV offset 0x57f000 size 0x1000
9387 10:55:16.830717 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9388 10:55:16.836880 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 10:55:16.840271 ELOG: Event(17) added with size 13 at 2023-06-05 10:55:16 UTC
9390 10:55:16.846898 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 10:55:16.850523 in-header: 03 ba 00 00 2c 00 00 00
9392 10:55:16.860524 in-data: a5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 10:55:16.867167 ELOG: Event(A1) added with size 10 at 2023-06-05 10:55:16 UTC
9394 10:55:16.873600 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9395 10:55:16.880882 ELOG: Event(A0) added with size 9 at 2023-06-05 10:55:16 UTC
9396 10:55:16.883690 elog_add_boot_reason: Logged dev mode boot
9397 10:55:16.890285 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9398 10:55:16.890395 Finalize devices...
9399 10:55:16.893821 Devices finalized
9400 10:55:16.896804 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 10:55:16.900159 Writing coreboot table at 0xffe64000
9402 10:55:16.903404 0. 000000000010a000-0000000000113fff: RAMSTAGE
9403 10:55:16.910126 1. 0000000040000000-00000000400fffff: RAM
9404 10:55:16.913503 2. 0000000040100000-000000004032afff: RAMSTAGE
9405 10:55:16.916414 3. 000000004032b000-00000000545fffff: RAM
9406 10:55:16.920354 4. 0000000054600000-000000005465ffff: BL31
9407 10:55:16.923143 5. 0000000054660000-00000000ffe63fff: RAM
9408 10:55:16.930374 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9409 10:55:16.933912 7. 0000000100000000-000000023fffffff: RAM
9410 10:55:16.936408 Passing 5 GPIOs to payload:
9411 10:55:16.939779 NAME | PORT | POLARITY | VALUE
9412 10:55:16.946857 EC in RW | 0x000000aa | low | undefined
9413 10:55:16.949934 EC interrupt | 0x00000005 | low | undefined
9414 10:55:16.953249 TPM interrupt | 0x000000ab | high | undefined
9415 10:55:16.959710 SD card detect | 0x00000011 | high | undefined
9416 10:55:16.963507 speaker enable | 0x00000093 | high | undefined
9417 10:55:16.966553 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9418 10:55:16.969535 in-header: 03 f9 00 00 02 00 00 00
9419 10:55:16.973487 in-data: 02 00
9420 10:55:16.973576 ADC[4]: Raw value=899483 ID=7
9421 10:55:16.976415 ADC[3]: Raw value=213336 ID=1
9422 10:55:16.979859 RAM Code: 0x71
9423 10:55:16.983066 ADC[6]: Raw value=74926 ID=0
9424 10:55:16.983155 ADC[5]: Raw value=212229 ID=1
9425 10:55:16.986368 SKU Code: 0x1
9426 10:55:16.989921 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9427 10:55:16.992799 coreboot table: 964 bytes.
9428 10:55:16.996532 IMD ROOT 0. 0xfffff000 0x00001000
9429 10:55:16.999477 IMD SMALL 1. 0xffffe000 0x00001000
9430 10:55:17.003198 RO MCACHE 2. 0xffffc000 0x00001104
9431 10:55:17.006360 CONSOLE 3. 0xfff7c000 0x00080000
9432 10:55:17.009936 FMAP 4. 0xfff7b000 0x00000452
9433 10:55:17.012824 TIME STAMP 5. 0xfff7a000 0x00000910
9434 10:55:17.016190 VBOOT WORK 6. 0xfff66000 0x00014000
9435 10:55:17.019711 RAMOOPS 7. 0xffe66000 0x00100000
9436 10:55:17.022686 COREBOOT 8. 0xffe64000 0x00002000
9437 10:55:17.026034 IMD small region:
9438 10:55:17.029651 IMD ROOT 0. 0xffffec00 0x00000400
9439 10:55:17.033546 VPD 1. 0xffffeba0 0x0000004c
9440 10:55:17.035988 MMC STATUS 2. 0xffffeb80 0x00000004
9441 10:55:17.039222 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9442 10:55:17.042911 Probing TPM: done!
9443 10:55:17.046250 Connected to device vid:did:rid of 1ae0:0028:00
9444 10:55:17.057097 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9445 10:55:17.060053 Initialized TPM device CR50 revision 0
9446 10:55:17.063535 Checking cr50 for pending updates
9447 10:55:17.067321 Reading cr50 TPM mode
9448 10:55:17.076310 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9449 10:55:17.083072 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9450 10:55:17.122695 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9451 10:55:17.125977 Checking segment from ROM address 0x40100000
9452 10:55:17.129511 Checking segment from ROM address 0x4010001c
9453 10:55:17.135787 Loading segment from ROM address 0x40100000
9454 10:55:17.135891 code (compression=0)
9455 10:55:17.145918 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9456 10:55:17.153073 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9457 10:55:17.153185 it's not compressed!
9458 10:55:17.158994 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9459 10:55:17.165655 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9460 10:55:17.183169 Loading segment from ROM address 0x4010001c
9461 10:55:17.183321 Entry Point 0x80000000
9462 10:55:17.186482 Loaded segments
9463 10:55:17.189897 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9464 10:55:17.196509 Jumping to boot code at 0x80000000(0xffe64000)
9465 10:55:17.203074 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9466 10:55:17.209557 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9467 10:55:17.217397 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9468 10:55:17.220796 Checking segment from ROM address 0x40100000
9469 10:55:17.224494 Checking segment from ROM address 0x4010001c
9470 10:55:17.230799 Loading segment from ROM address 0x40100000
9471 10:55:17.230907 code (compression=1)
9472 10:55:17.237581 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9473 10:55:17.248075 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9474 10:55:17.248198 using LZMA
9475 10:55:17.255829 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9476 10:55:17.262883 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9477 10:55:17.266310 Loading segment from ROM address 0x4010001c
9478 10:55:17.266408 Entry Point 0x54601000
9479 10:55:17.269581 Loaded segments
9480 10:55:17.272412 NOTICE: MT8192 bl31_setup
9481 10:55:17.279574 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9482 10:55:17.282878 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9483 10:55:17.286253 WARNING: region 0:
9484 10:55:17.289773 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 10:55:17.289862 WARNING: region 1:
9486 10:55:17.296375 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9487 10:55:17.300006 WARNING: region 2:
9488 10:55:17.303216 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9489 10:55:17.306595 WARNING: region 3:
9490 10:55:17.309934 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 10:55:17.312755 WARNING: region 4:
9492 10:55:17.316510 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 10:55:17.319994 WARNING: region 5:
9494 10:55:17.322965 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 10:55:17.326124 WARNING: region 6:
9496 10:55:17.329842 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 10:55:17.329933 WARNING: region 7:
9498 10:55:17.336460 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 10:55:17.343253 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9500 10:55:17.346372 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9501 10:55:17.349887 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9502 10:55:17.356349 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9503 10:55:17.359615 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9504 10:55:17.362990 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9505 10:55:17.369679 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9506 10:55:17.373204 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9507 10:55:17.376588 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9508 10:55:17.383023 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9509 10:55:17.386595 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9510 10:55:17.393438 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9511 10:55:17.396576 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9512 10:55:17.399668 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9513 10:55:17.406654 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9514 10:55:17.409903 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9515 10:55:17.413092 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9516 10:55:17.419792 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9517 10:55:17.422910 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9518 10:55:17.426389 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9519 10:55:17.433339 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9520 10:55:17.436514 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9521 10:55:17.443066 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9522 10:55:17.446701 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9523 10:55:17.449989 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9524 10:55:17.456898 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9525 10:55:17.460111 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9526 10:55:17.466745 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9527 10:55:17.470112 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9528 10:55:17.473796 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9529 10:55:17.479815 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9530 10:55:17.482908 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9531 10:55:17.486746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9532 10:55:17.493125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9533 10:55:17.496540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9534 10:55:17.499637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9535 10:55:17.503024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9536 10:55:17.509566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9537 10:55:17.513331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9538 10:55:17.516374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9539 10:55:17.519775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9540 10:55:17.527003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9541 10:55:17.530271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9542 10:55:17.533214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9543 10:55:17.536415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9544 10:55:17.543297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9545 10:55:17.546433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9546 10:55:17.550079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9547 10:55:17.556413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9548 10:55:17.560101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9549 10:55:17.563343 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9550 10:55:17.570072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9551 10:55:17.573486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9552 10:55:17.579754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9553 10:55:17.583569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9554 10:55:17.589892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9555 10:55:17.593255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9556 10:55:17.596522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9557 10:55:17.603384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9558 10:55:17.606539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9559 10:55:17.613399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9560 10:55:17.616223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9561 10:55:17.623216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9562 10:55:17.626910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9563 10:55:17.633412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9564 10:55:17.636372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9565 10:55:17.640022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9566 10:55:17.646518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9567 10:55:17.649586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9568 10:55:17.656295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9569 10:55:17.659598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9570 10:55:17.666682 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9571 10:55:17.670110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9572 10:55:17.672994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9573 10:55:17.680247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9574 10:55:17.683790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9575 10:55:17.689716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9576 10:55:17.693430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9577 10:55:17.700138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9578 10:55:17.703638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9579 10:55:17.706654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9580 10:55:17.713584 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9581 10:55:17.716511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9582 10:55:17.723642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9583 10:55:17.727039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9584 10:55:17.730207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9585 10:55:17.736751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9586 10:55:17.740134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9587 10:55:17.746725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9588 10:55:17.750080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9589 10:55:17.757244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9590 10:55:17.760343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9591 10:55:17.763541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9592 10:55:17.770045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9593 10:55:17.773252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9594 10:55:17.780521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9595 10:55:17.783818 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9596 10:55:17.786443 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9597 10:55:17.793703 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9598 10:55:17.796532 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9599 10:55:17.799934 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9600 10:55:17.803516 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9601 10:55:17.809994 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9602 10:55:17.813271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9603 10:55:17.820336 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9604 10:55:17.823208 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9605 10:55:17.826553 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9606 10:55:17.833492 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9607 10:55:17.836773 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9608 10:55:17.843556 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9609 10:55:17.846865 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9610 10:55:17.850173 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9611 10:55:17.856550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9612 10:55:17.859989 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9613 10:55:17.867086 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9614 10:55:17.869817 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9615 10:55:17.873522 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9616 10:55:17.880310 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9617 10:55:17.883758 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9618 10:55:17.886841 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9619 10:55:17.890320 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9620 10:55:17.896983 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9621 10:55:17.900588 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9622 10:55:17.903484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9623 10:55:17.909919 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9624 10:55:17.913477 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9625 10:55:17.917069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9626 10:55:17.923162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9627 10:55:17.926260 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9628 10:55:17.933649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9629 10:55:17.936519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9630 10:55:17.939878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9631 10:55:17.946688 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9632 10:55:17.950272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9633 10:55:17.953112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9634 10:55:17.959648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9635 10:55:17.963032 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9636 10:55:17.969993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9637 10:55:17.973116 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9638 10:55:17.976804 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9639 10:55:17.983192 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9640 10:55:17.986150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9641 10:55:17.993000 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9642 10:55:17.996302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9643 10:55:18.000035 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9644 10:55:18.006201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9645 10:55:18.009680 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9646 10:55:18.013032 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9647 10:55:18.019653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9648 10:55:18.023071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9649 10:55:18.030111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9650 10:55:18.033139 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9651 10:55:18.036521 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9652 10:55:18.043267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9653 10:55:18.046148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9654 10:55:18.053369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9655 10:55:18.056293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9656 10:55:18.059910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9657 10:55:18.066408 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9658 10:55:18.069763 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9659 10:55:18.073201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9660 10:55:18.079764 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9661 10:55:18.082759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9662 10:55:18.089772 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9663 10:55:18.093242 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9664 10:55:18.096306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9665 10:55:18.102609 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9666 10:55:18.105995 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9667 10:55:18.112983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9668 10:55:18.116251 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9669 10:55:18.119721 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9670 10:55:18.126150 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9671 10:55:18.129666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9672 10:55:18.136424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9673 10:55:18.139719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9674 10:55:18.142932 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9675 10:55:18.149920 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9676 10:55:18.152543 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9677 10:55:18.159143 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9678 10:55:18.162619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9679 10:55:18.165629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9680 10:55:18.172846 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9681 10:55:18.175655 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9682 10:55:18.182895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9683 10:55:18.185574 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9684 10:55:18.189233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9685 10:55:18.195338 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9686 10:55:18.199118 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9687 10:55:18.205823 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9688 10:55:18.209015 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9689 10:55:18.212475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9690 10:55:18.219166 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9691 10:55:18.222152 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9692 10:55:18.228940 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9693 10:55:18.232430 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9694 10:55:18.235752 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9695 10:55:18.242800 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9696 10:55:18.245499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9697 10:55:18.251963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9698 10:55:18.255541 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9699 10:55:18.262078 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9700 10:55:18.265475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9701 10:55:18.268492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9702 10:55:18.275410 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9703 10:55:18.278384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9704 10:55:18.285276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9705 10:55:18.288334 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9706 10:55:18.291913 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9707 10:55:18.298290 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9708 10:55:18.301941 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9709 10:55:18.308246 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9710 10:55:18.311459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9711 10:55:18.318120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9712 10:55:18.321173 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9713 10:55:18.325495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9714 10:55:18.331691 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9715 10:55:18.334524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9716 10:55:18.341462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9717 10:55:18.344595 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9718 10:55:18.351169 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9719 10:55:18.354501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9720 10:55:18.357659 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9721 10:55:18.364414 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9722 10:55:18.367651 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9723 10:55:18.374806 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9724 10:55:18.377540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9725 10:55:18.384807 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9726 10:55:18.387970 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9727 10:55:18.391034 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9728 10:55:18.397912 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9729 10:55:18.401110 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9730 10:55:18.404609 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9731 10:55:18.407772 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9732 10:55:18.411168 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9733 10:55:18.417605 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9734 10:55:18.421123 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9735 10:55:18.427490 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9736 10:55:18.431295 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9737 10:55:18.434003 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9738 10:55:18.441381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9739 10:55:18.444300 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9740 10:55:18.447599 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9741 10:55:18.454409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9742 10:55:18.458077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9743 10:55:18.460921 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9744 10:55:18.467459 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9745 10:55:18.471167 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9746 10:55:18.477466 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9747 10:55:18.480937 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9748 10:55:18.484291 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9749 10:55:18.490786 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9750 10:55:18.494246 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9751 10:55:18.497280 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9752 10:55:18.503903 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9753 10:55:18.507008 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9754 10:55:18.513614 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9755 10:55:18.517285 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9756 10:55:18.520405 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9757 10:55:18.527248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9758 10:55:18.530508 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9759 10:55:18.534088 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9760 10:55:18.540191 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9761 10:55:18.543726 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9762 10:55:18.547009 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9763 10:55:18.553735 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9764 10:55:18.557388 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9765 10:55:18.563763 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9766 10:55:18.566962 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9767 10:55:18.570193 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9768 10:55:18.573878 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9769 10:55:18.580497 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9770 10:55:18.583838 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9771 10:55:18.587177 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9772 10:55:18.590537 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9773 10:55:18.596987 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9774 10:55:18.600216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9775 10:55:18.603459 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9776 10:55:18.607167 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9777 10:55:18.613468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9778 10:55:18.616760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9779 10:55:18.620349 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9780 10:55:18.623563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9781 10:55:18.630159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9782 10:55:18.633337 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9783 10:55:18.640173 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9784 10:55:18.643314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9785 10:55:18.649678 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9786 10:55:18.653249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9787 10:55:18.656751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9788 10:55:18.663319 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9789 10:55:18.666637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9790 10:55:18.673121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9791 10:55:18.676591 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9792 10:55:18.680135 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9793 10:55:18.686321 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9794 10:55:18.689705 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9795 10:55:18.696524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9796 10:55:18.699818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9797 10:55:18.703368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9798 10:55:18.709713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9799 10:55:18.712720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9800 10:55:18.719524 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9801 10:55:18.723010 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9802 10:55:18.729431 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9803 10:55:18.733188 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9804 10:55:18.736685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9805 10:55:18.743065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9806 10:55:18.746174 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9807 10:55:18.752602 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9808 10:55:18.755796 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9809 10:55:18.759676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9810 10:55:18.765925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9811 10:55:18.769526 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9812 10:55:18.776073 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9813 10:55:18.779653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9814 10:55:18.782843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9815 10:55:18.789205 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9816 10:55:18.793033 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9817 10:55:18.799108 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9818 10:55:18.802757 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9819 10:55:18.806190 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9820 10:55:18.812636 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9821 10:55:18.816050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9822 10:55:18.822734 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9823 10:55:18.826003 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9824 10:55:18.828863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9825 10:55:18.835931 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9826 10:55:18.839053 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9827 10:55:18.845687 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9828 10:55:18.849472 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9829 10:55:18.852289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9830 10:55:18.859198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9831 10:55:18.862424 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9832 10:55:18.868819 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9833 10:55:18.872719 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9834 10:55:18.879270 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9835 10:55:18.882136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9836 10:55:18.885420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9837 10:55:18.892197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9838 10:55:18.895597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9839 10:55:18.902459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9840 10:55:18.905558 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9841 10:55:18.908655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9842 10:55:18.915947 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9843 10:55:18.918999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9844 10:55:18.925351 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9845 10:55:18.928475 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9846 10:55:18.932132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9847 10:55:18.939139 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9848 10:55:18.941898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9849 10:55:18.948667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9850 10:55:18.951715 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9851 10:55:18.958639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9852 10:55:18.961812 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9853 10:55:18.965240 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9854 10:55:18.971718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9855 10:55:18.974871 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9856 10:55:18.981778 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9857 10:55:18.985293 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9858 10:55:18.991574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9859 10:55:18.994912 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9860 10:55:18.998271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9861 10:55:19.004868 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9862 10:55:19.008428 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9863 10:55:19.015323 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9864 10:55:19.018298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9865 10:55:19.024933 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9866 10:55:19.028429 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9867 10:55:19.034941 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9868 10:55:19.038096 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9869 10:55:19.041494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9870 10:55:19.048166 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9871 10:55:19.051510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9872 10:55:19.058128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9873 10:55:19.061287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9874 10:55:19.067989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9875 10:55:19.071224 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9876 10:55:19.074460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9877 10:55:19.081605 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9878 10:55:19.084686 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9879 10:55:19.091294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9880 10:55:19.094687 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9881 10:55:19.101162 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9882 10:55:19.104439 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9883 10:55:19.107689 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9884 10:55:19.114681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9885 10:55:19.117604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9886 10:55:19.123967 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9887 10:55:19.127343 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9888 10:55:19.134040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9889 10:55:19.137582 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9890 10:55:19.144262 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9891 10:55:19.147546 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9892 10:55:19.151120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9893 10:55:19.157330 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9894 10:55:19.160899 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9895 10:55:19.167354 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9896 10:55:19.170705 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9897 10:55:19.177387 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9898 10:55:19.180406 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9899 10:55:19.183767 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9900 10:55:19.190568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9901 10:55:19.194105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9902 10:55:19.200667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9903 10:55:19.203893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9904 10:55:19.210120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9905 10:55:19.213418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9906 10:55:19.217606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9907 10:55:19.223365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9908 10:55:19.226701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9909 10:55:19.234123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9910 10:55:19.237152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9911 10:55:19.243664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9912 10:55:19.246890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9913 10:55:19.253386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9914 10:55:19.256726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9915 10:55:19.263540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9916 10:55:19.267055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9917 10:55:19.273683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9918 10:55:19.276830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9919 10:55:19.283263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9920 10:55:19.286937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9921 10:55:19.293695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9922 10:55:19.296618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9923 10:55:19.303288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9924 10:55:19.306722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9925 10:55:19.313508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9926 10:55:19.316336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9927 10:55:19.323468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9928 10:55:19.326270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9929 10:55:19.333488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9930 10:55:19.336255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9931 10:55:19.342729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9932 10:55:19.346610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9933 10:55:19.353186 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9934 10:55:19.353299 INFO: [APUAPC] vio 0
9935 10:55:19.359695 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9936 10:55:19.363681 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9937 10:55:19.366196 INFO: [APUAPC] D0_APC_0: 0x400510
9938 10:55:19.369426 INFO: [APUAPC] D0_APC_1: 0x0
9939 10:55:19.373120 INFO: [APUAPC] D0_APC_2: 0x1540
9940 10:55:19.376190 INFO: [APUAPC] D0_APC_3: 0x0
9941 10:55:19.379228 INFO: [APUAPC] D1_APC_0: 0xffffffff
9942 10:55:19.382774 INFO: [APUAPC] D1_APC_1: 0xffffffff
9943 10:55:19.386193 INFO: [APUAPC] D1_APC_2: 0x3fffff
9944 10:55:19.389291 INFO: [APUAPC] D1_APC_3: 0x0
9945 10:55:19.392663 INFO: [APUAPC] D2_APC_0: 0xffffffff
9946 10:55:19.396238 INFO: [APUAPC] D2_APC_1: 0xffffffff
9947 10:55:19.399468 INFO: [APUAPC] D2_APC_2: 0x3fffff
9948 10:55:19.402405 INFO: [APUAPC] D2_APC_3: 0x0
9949 10:55:19.405788 INFO: [APUAPC] D3_APC_0: 0xffffffff
9950 10:55:19.409240 INFO: [APUAPC] D3_APC_1: 0xffffffff
9951 10:55:19.412862 INFO: [APUAPC] D3_APC_2: 0x3fffff
9952 10:55:19.416546 INFO: [APUAPC] D3_APC_3: 0x0
9953 10:55:19.419447 INFO: [APUAPC] D4_APC_0: 0xffffffff
9954 10:55:19.422406 INFO: [APUAPC] D4_APC_1: 0xffffffff
9955 10:55:19.426000 INFO: [APUAPC] D4_APC_2: 0x3fffff
9956 10:55:19.426089 INFO: [APUAPC] D4_APC_3: 0x0
9957 10:55:19.429056 INFO: [APUAPC] D5_APC_0: 0xffffffff
9958 10:55:19.435668 INFO: [APUAPC] D5_APC_1: 0xffffffff
9959 10:55:19.439007 INFO: [APUAPC] D5_APC_2: 0x3fffff
9960 10:55:19.439100 INFO: [APUAPC] D5_APC_3: 0x0
9961 10:55:19.442565 INFO: [APUAPC] D6_APC_0: 0xffffffff
9962 10:55:19.445515 INFO: [APUAPC] D6_APC_1: 0xffffffff
9963 10:55:19.449202 INFO: [APUAPC] D6_APC_2: 0x3fffff
9964 10:55:19.452496 INFO: [APUAPC] D6_APC_3: 0x0
9965 10:55:19.455721 INFO: [APUAPC] D7_APC_0: 0xffffffff
9966 10:55:19.458953 INFO: [APUAPC] D7_APC_1: 0xffffffff
9967 10:55:19.462397 INFO: [APUAPC] D7_APC_2: 0x3fffff
9968 10:55:19.465647 INFO: [APUAPC] D7_APC_3: 0x0
9969 10:55:19.469136 INFO: [APUAPC] D8_APC_0: 0xffffffff
9970 10:55:19.472342 INFO: [APUAPC] D8_APC_1: 0xffffffff
9971 10:55:19.475340 INFO: [APUAPC] D8_APC_2: 0x3fffff
9972 10:55:19.479270 INFO: [APUAPC] D8_APC_3: 0x0
9973 10:55:19.482050 INFO: [APUAPC] D9_APC_0: 0xffffffff
9974 10:55:19.485452 INFO: [APUAPC] D9_APC_1: 0xffffffff
9975 10:55:19.489084 INFO: [APUAPC] D9_APC_2: 0x3fffff
9976 10:55:19.492072 INFO: [APUAPC] D9_APC_3: 0x0
9977 10:55:19.495829 INFO: [APUAPC] D10_APC_0: 0xffffffff
9978 10:55:19.498497 INFO: [APUAPC] D10_APC_1: 0xffffffff
9979 10:55:19.502144 INFO: [APUAPC] D10_APC_2: 0x3fffff
9980 10:55:19.505397 INFO: [APUAPC] D10_APC_3: 0x0
9981 10:55:19.508762 INFO: [APUAPC] D11_APC_0: 0xffffffff
9982 10:55:19.512271 INFO: [APUAPC] D11_APC_1: 0xffffffff
9983 10:55:19.515141 INFO: [APUAPC] D11_APC_2: 0x3fffff
9984 10:55:19.518673 INFO: [APUAPC] D11_APC_3: 0x0
9985 10:55:19.522084 INFO: [APUAPC] D12_APC_0: 0xffffffff
9986 10:55:19.525211 INFO: [APUAPC] D12_APC_1: 0xffffffff
9987 10:55:19.528878 INFO: [APUAPC] D12_APC_2: 0x3fffff
9988 10:55:19.531677 INFO: [APUAPC] D12_APC_3: 0x0
9989 10:55:19.535290 INFO: [APUAPC] D13_APC_0: 0xffffffff
9990 10:55:19.538685 INFO: [APUAPC] D13_APC_1: 0xffffffff
9991 10:55:19.542025 INFO: [APUAPC] D13_APC_2: 0x3fffff
9992 10:55:19.545323 INFO: [APUAPC] D13_APC_3: 0x0
9993 10:55:19.548610 INFO: [APUAPC] D14_APC_0: 0xffffffff
9994 10:55:19.552010 INFO: [APUAPC] D14_APC_1: 0xffffffff
9995 10:55:19.554993 INFO: [APUAPC] D14_APC_2: 0x3fffff
9996 10:55:19.558552 INFO: [APUAPC] D14_APC_3: 0x0
9997 10:55:19.561406 INFO: [APUAPC] D15_APC_0: 0xffffffff
9998 10:55:19.565157 INFO: [APUAPC] D15_APC_1: 0xffffffff
9999 10:55:19.568390 INFO: [APUAPC] D15_APC_2: 0x3fffff
10000 10:55:19.571913 INFO: [APUAPC] D15_APC_3: 0x0
10001 10:55:19.575081 INFO: [APUAPC] APC_CON: 0x4
10002 10:55:19.578706 INFO: [NOCDAPC] D0_APC_0: 0x0
10003 10:55:19.581917 INFO: [NOCDAPC] D0_APC_1: 0x0
10004 10:55:19.584837 INFO: [NOCDAPC] D1_APC_0: 0x0
10005 10:55:19.588233 INFO: [NOCDAPC] D1_APC_1: 0xfff
10006 10:55:19.591788 INFO: [NOCDAPC] D2_APC_0: 0x0
10007 10:55:19.591878 INFO: [NOCDAPC] D2_APC_1: 0xfff
10008 10:55:19.595270 INFO: [NOCDAPC] D3_APC_0: 0x0
10009 10:55:19.599067 INFO: [NOCDAPC] D3_APC_1: 0xfff
10010 10:55:19.601428 INFO: [NOCDAPC] D4_APC_0: 0x0
10011 10:55:19.605212 INFO: [NOCDAPC] D4_APC_1: 0xfff
10012 10:55:19.608234 INFO: [NOCDAPC] D5_APC_0: 0x0
10013 10:55:19.611618 INFO: [NOCDAPC] D5_APC_1: 0xfff
10014 10:55:19.614672 INFO: [NOCDAPC] D6_APC_0: 0x0
10015 10:55:19.617892 INFO: [NOCDAPC] D6_APC_1: 0xfff
10016 10:55:19.621700 INFO: [NOCDAPC] D7_APC_0: 0x0
10017 10:55:19.624520 INFO: [NOCDAPC] D7_APC_1: 0xfff
10018 10:55:19.624607 INFO: [NOCDAPC] D8_APC_0: 0x0
10019 10:55:19.627963 INFO: [NOCDAPC] D8_APC_1: 0xfff
10020 10:55:19.631257 INFO: [NOCDAPC] D9_APC_0: 0x0
10021 10:55:19.634478 INFO: [NOCDAPC] D9_APC_1: 0xfff
10022 10:55:19.637828 INFO: [NOCDAPC] D10_APC_0: 0x0
10023 10:55:19.641298 INFO: [NOCDAPC] D10_APC_1: 0xfff
10024 10:55:19.644385 INFO: [NOCDAPC] D11_APC_0: 0x0
10025 10:55:19.647847 INFO: [NOCDAPC] D11_APC_1: 0xfff
10026 10:55:19.651033 INFO: [NOCDAPC] D12_APC_0: 0x0
10027 10:55:19.654538 INFO: [NOCDAPC] D12_APC_1: 0xfff
10028 10:55:19.658251 INFO: [NOCDAPC] D13_APC_0: 0x0
10029 10:55:19.661389 INFO: [NOCDAPC] D13_APC_1: 0xfff
10030 10:55:19.664642 INFO: [NOCDAPC] D14_APC_0: 0x0
10031 10:55:19.668022 INFO: [NOCDAPC] D14_APC_1: 0xfff
10032 10:55:19.668121 INFO: [NOCDAPC] D15_APC_0: 0x0
10033 10:55:19.671557 INFO: [NOCDAPC] D15_APC_1: 0xfff
10034 10:55:19.674708 INFO: [NOCDAPC] APC_CON: 0x4
10035 10:55:19.678039 INFO: [APUAPC] set_apusys_apc done
10036 10:55:19.681192 INFO: [DEVAPC] devapc_init done
10037 10:55:19.684821 INFO: GICv3 without legacy support detected.
10038 10:55:19.691385 INFO: ARM GICv3 driver initialized in EL3
10039 10:55:19.694393 INFO: Maximum SPI INTID supported: 639
10040 10:55:19.698654 INFO: BL31: Initializing runtime services
10041 10:55:19.704354 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10042 10:55:19.707666 INFO: SPM: enable CPC mode
10043 10:55:19.711471 INFO: mcdi ready for mcusys-off-idle and system suspend
10044 10:55:19.717809 INFO: BL31: Preparing for EL3 exit to normal world
10045 10:55:19.721154 INFO: Entry point address = 0x80000000
10046 10:55:19.721251 INFO: SPSR = 0x8
10047 10:55:19.727303
10048 10:55:19.727443
10049 10:55:19.727511
10050 10:55:19.730868 Starting depthcharge on Spherion...
10051 10:55:19.730951
10052 10:55:19.731016 Wipe memory regions:
10053 10:55:19.731076
10054 10:55:19.731729 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10055 10:55:19.731831 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10056 10:55:19.731914 Setting prompt string to ['asurada:']
10057 10:55:19.731990 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10058 10:55:19.734287 [0x00000040000000, 0x00000054600000)
10059 10:55:19.856779
10060 10:55:19.856935 [0x00000054660000, 0x00000080000000)
10061 10:55:20.117316
10062 10:55:20.117500 [0x000000821a7280, 0x000000ffe64000)
10063 10:55:20.862123
10064 10:55:20.862281 [0x00000100000000, 0x00000240000000)
10065 10:55:22.752864
10066 10:55:22.755778 Initializing XHCI USB controller at 0x11200000.
10067 10:55:23.794003
10068 10:55:23.796894 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10069 10:55:23.796984
10070 10:55:23.797065
10071 10:55:23.797129
10072 10:55:23.797403 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 10:55:23.897735 asurada: tftpboot 192.168.201.1 10591003/tftp-deploy-gzo4hxez/kernel/image.itb 10591003/tftp-deploy-gzo4hxez/kernel/cmdline
10075 10:55:23.897911 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 10:55:23.898072 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10077 10:55:23.902946 tftpboot 192.168.201.1 10591003/tftp-deploy-gzo4hxez/kernel/image.itp-deploy-gzo4hxez/kernel/cmdline
10078 10:55:23.903093
10079 10:55:23.903191 Waiting for link
10080 10:55:24.063607
10081 10:55:24.063760 R8152: Initializing
10082 10:55:24.063831
10083 10:55:24.066632 Version 6 (ocp_data = 5c30)
10084 10:55:24.066740
10085 10:55:24.069770 R8152: Done initializing
10086 10:55:24.069872
10087 10:55:24.069974 Adding net device
10088 10:55:25.940926
10089 10:55:25.941123 done.
10090 10:55:25.941230
10091 10:55:25.941330 MAC: 00:24:32:30:78:52
10092 10:55:25.941428
10093 10:55:25.944395 Sending DHCP discover... done.
10094 10:55:25.944520
10095 10:55:25.947463 Waiting for reply... done.
10096 10:55:25.947559
10097 10:55:25.950731 Sending DHCP request... done.
10098 10:55:25.950843
10099 10:55:25.955771 Waiting for reply... done.
10100 10:55:25.955859
10101 10:55:25.955924 My ip is 192.168.201.14
10102 10:55:25.955985
10103 10:55:25.959494 The DHCP server ip is 192.168.201.1
10104 10:55:25.959579
10105 10:55:25.965720 TFTP server IP predefined by user: 192.168.201.1
10106 10:55:25.965815
10107 10:55:25.972850 Bootfile predefined by user: 10591003/tftp-deploy-gzo4hxez/kernel/image.itb
10108 10:55:25.972948
10109 10:55:25.973016 Sending tftp read request... done.
10110 10:55:25.975938
10111 10:55:25.979262 Waiting for the transfer...
10112 10:55:25.979361
10113 10:55:26.498769 00000000 ################################################################
10114 10:55:26.498942
10115 10:55:27.026035 00080000 ################################################################
10116 10:55:27.026220
10117 10:55:27.547918 00100000 ################################################################
10118 10:55:27.548064
10119 10:55:28.074498 00180000 ################################################################
10120 10:55:28.074645
10121 10:55:28.597417 00200000 ################################################################
10122 10:55:28.597592
10123 10:55:29.115564 00280000 ################################################################
10124 10:55:29.115714
10125 10:55:29.641216 00300000 ################################################################
10126 10:55:29.641365
10127 10:55:30.164381 00380000 ################################################################
10128 10:55:30.164539
10129 10:55:30.701280 00400000 ################################################################
10130 10:55:30.701433
10131 10:55:31.228719 00480000 ################################################################
10132 10:55:31.228865
10133 10:55:31.747745 00500000 ################################################################
10134 10:55:31.747896
10135 10:55:32.263019 00580000 ################################################################
10136 10:55:32.263174
10137 10:55:32.779776 00600000 ################################################################
10138 10:55:32.779944
10139 10:55:33.296471 00680000 ################################################################
10140 10:55:33.296613
10141 10:55:33.818677 00700000 ################################################################
10142 10:55:33.818823
10143 10:55:34.340075 00780000 ################################################################
10144 10:55:34.340214
10145 10:55:34.866450 00800000 ################################################################
10146 10:55:34.866616
10147 10:55:35.381016 00880000 ################################################################
10148 10:55:35.381160
10149 10:55:35.890323 00900000 ################################################################
10150 10:55:35.890487
10151 10:55:36.400818 00980000 ################################################################
10152 10:55:36.400980
10153 10:55:36.922223 00a00000 ################################################################
10154 10:55:36.922411
10155 10:55:37.478182 00a80000 ################################################################
10156 10:55:37.478326
10157 10:55:38.027334 00b00000 ################################################################
10158 10:55:38.027533
10159 10:55:38.572109 00b80000 ################################################################
10160 10:55:38.572274
10161 10:55:39.122025 00c00000 ################################################################
10162 10:55:39.122169
10163 10:55:39.690359 00c80000 ################################################################
10164 10:55:39.690501
10165 10:55:40.266900 00d00000 ################################################################
10166 10:55:40.267042
10167 10:55:40.835782 00d80000 ################################################################
10168 10:55:40.835933
10169 10:55:41.389265 00e00000 ################################################################
10170 10:55:41.389404
10171 10:55:41.940697 00e80000 ################################################################
10172 10:55:41.940849
10173 10:55:42.496674 00f00000 ################################################################
10174 10:55:42.496816
10175 10:55:43.040431 00f80000 ################################################################
10176 10:55:43.040603
10177 10:55:43.581559 01000000 ################################################################
10178 10:55:43.581715
10179 10:55:44.137811 01080000 ################################################################
10180 10:55:44.137966
10181 10:55:44.693853 01100000 ################################################################
10182 10:55:44.693996
10183 10:55:45.245852 01180000 ################################################################
10184 10:55:45.245995
10185 10:55:45.800947 01200000 ################################################################
10186 10:55:45.801097
10187 10:55:46.351263 01280000 ################################################################
10188 10:55:46.351466
10189 10:55:46.900979 01300000 ################################################################
10190 10:55:46.901169
10191 10:55:47.433833 01380000 ################################################################
10192 10:55:47.433991
10193 10:55:47.967012 01400000 ################################################################
10194 10:55:47.967165
10195 10:55:48.499758 01480000 ################################################################
10196 10:55:48.499908
10197 10:55:49.064927 01500000 ################################################################
10198 10:55:49.065373
10199 10:55:49.654132 01580000 ################################################################
10200 10:55:49.654282
10201 10:55:50.230615 01600000 ################################################################
10202 10:55:50.230752
10203 10:55:50.790629 01680000 ################################################################
10204 10:55:50.790767
10205 10:55:51.339929 01700000 ################################################################
10206 10:55:51.340095
10207 10:55:51.905933 01780000 ################################################################
10208 10:55:51.906435
10209 10:55:52.495028 01800000 ################################################################
10210 10:55:52.495157
10211 10:55:53.151894 01880000 ################################################################
10212 10:55:53.152560
10213 10:55:53.830256 01900000 ################################################################
10214 10:55:53.830812
10215 10:55:54.463688 01980000 ################################################################
10216 10:55:54.464220
10217 10:55:55.158350 01a00000 ################################################################
10218 10:55:55.158842
10219 10:55:55.830247 01a80000 ################################################################
10220 10:55:55.830738
10221 10:55:56.485309 01b00000 ################################################################
10222 10:55:56.485933
10223 10:55:57.132230 01b80000 ################################################################
10224 10:55:57.132377
10225 10:55:57.707816 01c00000 ################################################################
10226 10:55:57.707951
10227 10:55:58.331888 01c80000 ################################################################
10228 10:55:58.332507
10229 10:55:58.980028 01d00000 ################################################################
10230 10:55:58.980540
10231 10:55:59.640413 01d80000 ################################################################
10232 10:55:59.640568
10233 10:56:00.361882 01e00000 ################################################################
10234 10:56:00.362373
10235 10:56:01.185577 01e80000 ################################################################
10236 10:56:01.186141
10237 10:56:01.652365 01f00000 ################################################################
10238 10:56:01.652496
10239 10:56:02.253568 01f80000 ################################################################
10240 10:56:02.254077
10241 10:56:02.817908 02000000 ################################################################
10242 10:56:02.818080
10243 10:56:03.356301 02080000 ################################################################
10244 10:56:03.356438
10245 10:56:03.881593 02100000 ################################################################
10246 10:56:03.881761
10247 10:56:04.410255 02180000 ################################################################
10248 10:56:04.410402
10249 10:56:04.931252 02200000 ################################################################
10250 10:56:04.931416
10251 10:56:05.449982 02280000 ################################################################
10252 10:56:05.450144
10253 10:56:05.972957 02300000 ################################################################
10254 10:56:05.973123
10255 10:56:06.501356 02380000 ################################################################
10256 10:56:06.501500
10257 10:56:07.019123 02400000 ################################################################
10258 10:56:07.019285
10259 10:56:07.547156 02480000 ################################################################
10260 10:56:07.547320
10261 10:56:08.070855 02500000 ################################################################
10262 10:56:08.071060
10263 10:56:08.601838 02580000 ################################################################
10264 10:56:08.602001
10265 10:56:09.123233 02600000 ################################################################
10266 10:56:09.123417
10267 10:56:09.657319 02680000 ################################################################
10268 10:56:09.657458
10269 10:56:10.208849 02700000 ################################################################
10270 10:56:10.208997
10271 10:56:10.748974 02780000 ################################################################
10272 10:56:10.749168
10273 10:56:11.269743 02800000 ################################################################
10274 10:56:11.269906
10275 10:56:11.791113 02880000 ################################################################
10276 10:56:11.791246
10277 10:56:12.313030 02900000 ################################################################
10278 10:56:12.313164
10279 10:56:12.835869 02980000 ################################################################
10280 10:56:12.836004
10281 10:56:13.364556 02a00000 ################################################################
10282 10:56:13.364739
10283 10:56:13.884927 02a80000 ################################################################
10284 10:56:13.885066
10285 10:56:14.402200 02b00000 ################################################################
10286 10:56:14.402346
10287 10:56:14.919555 02b80000 ################################################################
10288 10:56:14.919695
10289 10:56:15.435045 02c00000 ################################################################
10290 10:56:15.435184
10291 10:56:15.952818 02c80000 ################################################################
10292 10:56:15.952952
10293 10:56:16.471493 02d00000 ################################################################
10294 10:56:16.471630
10295 10:56:16.989536 02d80000 ################################################################
10296 10:56:16.989703
10297 10:56:17.556192 02e00000 ################################################################
10298 10:56:17.556711
10299 10:56:18.200111 02e80000 ################################################################
10300 10:56:18.200817
10301 10:56:18.844038 02f00000 ################################################################
10302 10:56:18.844639
10303 10:56:19.475711 02f80000 ################################################################
10304 10:56:19.475842
10305 10:56:20.025179 03000000 ################################################################
10306 10:56:20.025335
10307 10:56:20.571895 03080000 ################################################################
10308 10:56:20.572028
10309 10:56:21.128685 03100000 ################################################################
10310 10:56:21.128817
10311 10:56:21.683916 03180000 ################################################################
10312 10:56:21.684070
10313 10:56:22.239917 03200000 ################################################################
10314 10:56:22.240056
10315 10:56:22.763846 03280000 ################################################################
10316 10:56:22.763998
10317 10:56:23.295442 03300000 ################################################################
10318 10:56:23.295608
10319 10:56:23.830636 03380000 ################################################################
10320 10:56:23.830768
10321 10:56:24.359950 03400000 ################################################################
10322 10:56:24.360096
10323 10:56:24.902642 03480000 ################################################################
10324 10:56:24.902802
10325 10:56:25.433636 03500000 ################################################################
10326 10:56:25.433807
10327 10:56:25.957259 03580000 ################################################################
10328 10:56:25.957443
10329 10:56:26.479741 03600000 ################################################################
10330 10:56:26.479881
10331 10:56:26.839845 03680000 ############################################# done.
10332 10:56:26.840067
10333 10:56:26.842940 The bootfile was 57510650 bytes long.
10334 10:56:26.846500
10335 10:56:26.846599 Sending tftp read request... done.
10336 10:56:26.846696
10337 10:56:26.849834 Waiting for the transfer...
10338 10:56:26.849938
10339 10:56:26.853052 00000000 # done.
10340 10:56:26.853162
10341 10:56:26.859609 Command line loaded dynamically from TFTP file: 10591003/tftp-deploy-gzo4hxez/kernel/cmdline
10342 10:56:26.859690
10343 10:56:26.869700 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10344 10:56:26.872700
10345 10:56:26.872803 Loading FIT.
10346 10:56:26.872895
10347 10:56:26.876002 Image ramdisk-1 has 47379755 bytes.
10348 10:56:26.876105
10349 10:56:26.879192 Image fdt-1 has 46924 bytes.
10350 10:56:26.879293
10351 10:56:26.882854 Image kernel-1 has 10081937 bytes.
10352 10:56:26.882957
10353 10:56:26.889648 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10354 10:56:26.889752
10355 10:56:26.909541 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10356 10:56:26.909640
10357 10:56:26.912998 Choosing best match conf-1 for compat google,spherion-rev2.
10358 10:56:26.916981
10359 10:56:26.921177 Connected to device vid:did:rid of 1ae0:0028:00
10360 10:56:26.928892
10361 10:56:26.931767 tpm_get_response: command 0x17b, return code 0x0
10362 10:56:26.931853
10363 10:56:26.935458 ec_init: CrosEC protocol v3 supported (256, 248)
10364 10:56:26.940467
10365 10:56:26.943587 tpm_cleanup: add release locality here.
10366 10:56:26.943672
10367 10:56:26.943738 Shutting down all USB controllers.
10368 10:56:26.946606
10369 10:56:26.946693 Removing current net device
10370 10:56:26.946790
10371 10:56:26.953318 Exiting depthcharge with code 4 at timestamp: 96647550
10372 10:56:26.953407
10373 10:56:26.956409 LZMA decompressing kernel-1 to 0x821a6718
10374 10:56:26.956492
10375 10:56:26.960078 LZMA decompressing kernel-1 to 0x40000000
10376 10:56:28.226074
10377 10:56:28.226230 jumping to kernel
10378 10:56:28.226665 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10379 10:56:28.226782 start: 2.2.5 auto-login-action (timeout 00:03:17) [common]
10380 10:56:28.226895 Setting prompt string to ['Linux version [0-9]']
10381 10:56:28.226995 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10382 10:56:28.227095 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10383 10:56:28.308041
10384 10:56:28.311556 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10385 10:56:28.314740 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10386 10:56:28.314828 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10387 10:56:28.314915 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10388 10:56:28.314995 Using line separator: #'\n'#
10389 10:56:28.315058 No login prompt set.
10390 10:56:28.315120 Parsing kernel messages
10391 10:56:28.315210 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10392 10:56:28.315312 [login-action] Waiting for messages, (timeout 00:03:17)
10393 10:56:28.334519 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10394 10:56:28.338152 [ 0.000000] random: crng init done
10395 10:56:28.341120 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10396 10:56:28.344666 [ 0.000000] efi: UEFI not found.
10397 10:56:28.354510 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10398 10:56:28.361019 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10399 10:56:28.370962 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10400 10:56:28.381402 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10401 10:56:28.387833 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10402 10:56:28.390884 [ 0.000000] printk: bootconsole [mtk8250] enabled
10403 10:56:28.399594 [ 0.000000] NUMA: No NUMA configuration found
10404 10:56:28.406212 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10405 10:56:28.412913 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10406 10:56:28.413015 [ 0.000000] Zone ranges:
10407 10:56:28.418825 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10408 10:56:28.422509 [ 0.000000] DMA32 empty
10409 10:56:28.428834 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10410 10:56:28.432236 [ 0.000000] Movable zone start for each node
10411 10:56:28.435904 [ 0.000000] Early memory node ranges
10412 10:56:28.442494 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10413 10:56:28.448946 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10414 10:56:28.455702 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10415 10:56:28.462172 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10416 10:56:28.469475 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10417 10:56:28.475525 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10418 10:56:28.532386 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10419 10:56:28.538292 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10420 10:56:28.544753 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10421 10:56:28.548647 [ 0.000000] psci: probing for conduit method from DT.
10422 10:56:28.554988 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10423 10:56:28.558341 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10424 10:56:28.564982 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10425 10:56:28.567996 [ 0.000000] psci: SMC Calling Convention v1.2
10426 10:56:28.574658 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10427 10:56:28.578001 [ 0.000000] Detected VIPT I-cache on CPU0
10428 10:56:28.584376 [ 0.000000] CPU features: detected: GIC system register CPU interface
10429 10:56:28.590765 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10430 10:56:28.597638 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10431 10:56:28.604215 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10432 10:56:28.614253 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10433 10:56:28.620604 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10434 10:56:28.624139 [ 0.000000] alternatives: applying boot alternatives
10435 10:56:28.630884 [ 0.000000] Fallback order for Node 0: 0
10436 10:56:28.637456 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10437 10:56:28.640422 [ 0.000000] Policy zone: Normal
10438 10:56:28.650406 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10439 10:56:28.663434 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10440 10:56:28.673833 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10441 10:56:28.683645 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10442 10:56:28.690499 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10443 10:56:28.693991 <6>[ 0.000000] software IO TLB: area num 8.
10444 10:56:28.751102 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10445 10:56:28.901114 <6>[ 0.000000] Memory: 7926668K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426100K reserved, 32768K cma-reserved)
10446 10:56:28.906964 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10447 10:56:28.914199 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10448 10:56:28.916900 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10449 10:56:28.923618 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10450 10:56:28.930428 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10451 10:56:28.933939 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10452 10:56:28.943425 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10453 10:56:28.950425 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10454 10:56:28.956652 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10455 10:56:28.963227 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10456 10:56:28.966751 <6>[ 0.000000] GICv3: 608 SPIs implemented
10457 10:56:28.970202 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10458 10:56:28.976935 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10459 10:56:28.979835 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10460 10:56:28.986364 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10461 10:56:28.999705 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10462 10:56:29.009602 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10463 10:56:29.019584 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10464 10:56:29.026977 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10465 10:56:29.040191 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10466 10:56:29.046966 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10467 10:56:29.053627 <6>[ 0.009174] Console: colour dummy device 80x25
10468 10:56:29.063714 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10469 10:56:29.070194 <6>[ 0.024407] pid_max: default: 32768 minimum: 301
10470 10:56:29.073159 <6>[ 0.029281] LSM: Security Framework initializing
10471 10:56:29.080055 <6>[ 0.034221] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 10:56:29.089954 <6>[ 0.042084] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 10:56:29.099593 <6>[ 0.051512] cblist_init_generic: Setting adjustable number of callback queues.
10474 10:56:29.102842 <6>[ 0.058966] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 10:56:29.109681 <6>[ 0.065343] cblist_init_generic: Setting shift to 3 and lim to 1.
10476 10:56:29.116085 <6>[ 0.071789] rcu: Hierarchical SRCU implementation.
10477 10:56:29.123145 <6>[ 0.076833] rcu: Max phase no-delay instances is 1000.
10478 10:56:29.129487 <6>[ 0.083881] EFI services will not be available.
10479 10:56:29.132842 <6>[ 0.088852] smp: Bringing up secondary CPUs ...
10480 10:56:29.140331 <6>[ 0.093907] Detected VIPT I-cache on CPU1
10481 10:56:29.147376 <6>[ 0.093978] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10482 10:56:29.153836 <6>[ 0.094008] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10483 10:56:29.157334 <6>[ 0.094348] Detected VIPT I-cache on CPU2
10484 10:56:29.163752 <6>[ 0.094397] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10485 10:56:29.173319 <6>[ 0.094413] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10486 10:56:29.177461 <6>[ 0.094672] Detected VIPT I-cache on CPU3
10487 10:56:29.183242 <6>[ 0.094719] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10488 10:56:29.190386 <6>[ 0.094733] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10489 10:56:29.193704 <6>[ 0.095036] CPU features: detected: Spectre-v4
10490 10:56:29.199927 <6>[ 0.095042] CPU features: detected: Spectre-BHB
10491 10:56:29.203297 <6>[ 0.095049] Detected PIPT I-cache on CPU4
10492 10:56:29.210024 <6>[ 0.095106] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10493 10:56:29.216231 <6>[ 0.095123] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10494 10:56:29.223292 <6>[ 0.095416] Detected PIPT I-cache on CPU5
10495 10:56:29.229384 <6>[ 0.095479] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10496 10:56:29.236239 <6>[ 0.095495] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10497 10:56:29.239627 <6>[ 0.095781] Detected PIPT I-cache on CPU6
10498 10:56:29.246385 <6>[ 0.095846] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10499 10:56:29.255814 <6>[ 0.095863] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10500 10:56:29.259514 <6>[ 0.096163] Detected PIPT I-cache on CPU7
10501 10:56:29.265719 <6>[ 0.096228] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10502 10:56:29.272399 <6>[ 0.096243] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10503 10:56:29.276107 <6>[ 0.096290] smp: Brought up 1 node, 8 CPUs
10504 10:56:29.282368 <6>[ 0.237641] SMP: Total of 8 processors activated.
10505 10:56:29.285751 <6>[ 0.242562] CPU features: detected: 32-bit EL0 Support
10506 10:56:29.295498 <6>[ 0.247925] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10507 10:56:29.302126 <6>[ 0.256725] CPU features: detected: Common not Private translations
10508 10:56:29.308942 <6>[ 0.263200] CPU features: detected: CRC32 instructions
10509 10:56:29.315811 <6>[ 0.268551] CPU features: detected: RCpc load-acquire (LDAPR)
10510 10:56:29.318576 <6>[ 0.274511] CPU features: detected: LSE atomic instructions
10511 10:56:29.325075 <6>[ 0.280328] CPU features: detected: Privileged Access Never
10512 10:56:29.331570 <6>[ 0.286143] CPU features: detected: RAS Extension Support
10513 10:56:29.338724 <6>[ 0.291786] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10514 10:56:29.341627 <6>[ 0.299049] CPU: All CPU(s) started at EL2
10515 10:56:29.348303 <6>[ 0.303392] alternatives: applying system-wide alternatives
10516 10:56:29.358121 <6>[ 0.314100] devtmpfs: initialized
10517 10:56:29.370598 <6>[ 0.323165] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10518 10:56:29.380821 <6>[ 0.333121] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10519 10:56:29.383721 <6>[ 0.340808] pinctrl core: initialized pinctrl subsystem
10520 10:56:29.392018 <6>[ 0.347474] DMI not present or invalid.
10521 10:56:29.398501 <6>[ 0.351880] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10522 10:56:29.405121 <6>[ 0.358758] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10523 10:56:29.415344 <6>[ 0.366335] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10524 10:56:29.421733 <6>[ 0.374545] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10525 10:56:29.428560 <6>[ 0.382786] audit: initializing netlink subsys (disabled)
10526 10:56:29.435385 <5>[ 0.388479] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10527 10:56:29.441684 <6>[ 0.389186] thermal_sys: Registered thermal governor 'step_wise'
10528 10:56:29.448522 <6>[ 0.396443] thermal_sys: Registered thermal governor 'power_allocator'
10529 10:56:29.451704 <6>[ 0.402698] cpuidle: using governor menu
10530 10:56:29.458088 <6>[ 0.413656] NET: Registered PF_QIPCRTR protocol family
10531 10:56:29.464797 <6>[ 0.419130] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10532 10:56:29.471322 <6>[ 0.426232] ASID allocator initialised with 32768 entries
10533 10:56:29.474736 <6>[ 0.432797] Serial: AMBA PL011 UART driver
10534 10:56:29.485356 <4>[ 0.441464] Trying to register duplicate clock ID: 134
10535 10:56:29.539843 <6>[ 0.498893] KASLR enabled
10536 10:56:29.554352 <6>[ 0.506798] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10537 10:56:29.560841 <6>[ 0.513811] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10538 10:56:29.567465 <6>[ 0.520300] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10539 10:56:29.574125 <6>[ 0.527306] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10540 10:56:29.580921 <6>[ 0.533795] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10541 10:56:29.587528 <6>[ 0.540799] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10542 10:56:29.594150 <6>[ 0.547286] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10543 10:56:29.600877 <6>[ 0.554288] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10544 10:56:29.604019 <6>[ 0.561803] ACPI: Interpreter disabled.
10545 10:56:29.612643 <6>[ 0.568194] iommu: Default domain type: Translated
10546 10:56:29.619314 <6>[ 0.573304] iommu: DMA domain TLB invalidation policy: strict mode
10547 10:56:29.622136 <5>[ 0.579956] SCSI subsystem initialized
10548 10:56:29.629140 <6>[ 0.584123] usbcore: registered new interface driver usbfs
10549 10:56:29.635326 <6>[ 0.589853] usbcore: registered new interface driver hub
10550 10:56:29.638955 <6>[ 0.595402] usbcore: registered new device driver usb
10551 10:56:29.645490 <6>[ 0.601480] pps_core: LinuxPPS API ver. 1 registered
10552 10:56:29.656313 <6>[ 0.606673] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10553 10:56:29.658981 <6>[ 0.616016] PTP clock support registered
10554 10:56:29.662034 <6>[ 0.620257] EDAC MC: Ver: 3.0.0
10555 10:56:29.669738 <6>[ 0.625395] FPGA manager framework
10556 10:56:29.676377 <6>[ 0.629074] Advanced Linux Sound Architecture Driver Initialized.
10557 10:56:29.679283 <6>[ 0.635843] vgaarb: loaded
10558 10:56:29.686314 <6>[ 0.639011] clocksource: Switched to clocksource arch_sys_counter
10559 10:56:29.689245 <5>[ 0.645448] VFS: Disk quotas dquot_6.6.0
10560 10:56:29.695946 <6>[ 0.649631] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10561 10:56:29.699302 <6>[ 0.656821] pnp: PnP ACPI: disabled
10562 10:56:29.707968 <6>[ 0.663557] NET: Registered PF_INET protocol family
10563 10:56:29.717906 <6>[ 0.669155] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10564 10:56:29.729137 <6>[ 0.681461] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10565 10:56:29.739037 <6>[ 0.690275] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10566 10:56:29.745520 <6>[ 0.698247] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10567 10:56:29.752534 <6>[ 0.706944] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10568 10:56:29.764265 <6>[ 0.716686] TCP: Hash tables configured (established 65536 bind 65536)
10569 10:56:29.770524 <6>[ 0.723541] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10570 10:56:29.778007 <6>[ 0.730736] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 10:56:29.784199 <6>[ 0.738436] NET: Registered PF_UNIX/PF_LOCAL protocol family
10572 10:56:29.790569 <6>[ 0.744607] RPC: Registered named UNIX socket transport module.
10573 10:56:29.794201 <6>[ 0.750762] RPC: Registered udp transport module.
10574 10:56:29.800884 <6>[ 0.755693] RPC: Registered tcp transport module.
10575 10:56:29.807111 <6>[ 0.760625] RPC: Registered tcp NFSv4.1 backchannel transport module.
10576 10:56:29.810210 <6>[ 0.767293] PCI: CLS 0 bytes, default 64
10577 10:56:29.813719 <6>[ 0.771688] Unpacking initramfs...
10578 10:56:29.838909 <6>[ 0.791245] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10579 10:56:29.848839 <6>[ 0.799926] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10580 10:56:29.852497 <6>[ 0.808777] kvm [1]: IPA Size Limit: 40 bits
10581 10:56:29.858715 <6>[ 0.813309] kvm [1]: GICv3: no GICV resource entry
10582 10:56:29.862207 <6>[ 0.818330] kvm [1]: disabling GICv2 emulation
10583 10:56:29.868538 <6>[ 0.823019] kvm [1]: GIC system register CPU interface enabled
10584 10:56:29.872225 <6>[ 0.829193] kvm [1]: vgic interrupt IRQ18
10585 10:56:29.878496 <6>[ 0.833548] kvm [1]: VHE mode initialized successfully
10586 10:56:29.885146 <5>[ 0.839959] Initialise system trusted keyrings
10587 10:56:29.891524 <6>[ 0.844761] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10588 10:56:29.899386 <6>[ 0.854926] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10589 10:56:29.905697 <5>[ 0.861302] NFS: Registering the id_resolver key type
10590 10:56:29.909150 <5>[ 0.866609] Key type id_resolver registered
10591 10:56:29.915444 <5>[ 0.871025] Key type id_legacy registered
10592 10:56:29.922311 <6>[ 0.875302] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10593 10:56:29.928680 <6>[ 0.882224] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10594 10:56:29.935607 <6>[ 0.889933] 9p: Installing v9fs 9p2000 file system support
10595 10:56:29.972094 <5>[ 0.928044] Key type asymmetric registered
10596 10:56:29.975536 <5>[ 0.932375] Asymmetric key parser 'x509' registered
10597 10:56:29.985696 <6>[ 0.937519] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10598 10:56:29.988693 <6>[ 0.945134] io scheduler mq-deadline registered
10599 10:56:29.991786 <6>[ 0.949911] io scheduler kyber registered
10600 10:56:30.010752 <6>[ 0.966694] EINJ: ACPI disabled.
10601 10:56:30.042847 <4>[ 0.991932] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 10:56:30.052817 <4>[ 1.002552] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 10:56:30.067823 <6>[ 1.023202] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10604 10:56:30.075580 <6>[ 1.031193] printk: console [ttyS0] disabled
10605 10:56:30.103582 <6>[ 1.055837] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10606 10:56:30.110434 <6>[ 1.065307] printk: console [ttyS0] enabled
10607 10:56:30.113365 <6>[ 1.065307] printk: console [ttyS0] enabled
10608 10:56:30.120102 <6>[ 1.074201] printk: bootconsole [mtk8250] disabled
10609 10:56:30.123332 <6>[ 1.074201] printk: bootconsole [mtk8250] disabled
10610 10:56:30.129877 <6>[ 1.085427] SuperH (H)SCI(F) driver initialized
10611 10:56:30.133262 <6>[ 1.090691] msm_serial: driver initialized
10612 10:56:30.147617 <6>[ 1.099574] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10613 10:56:30.157111 <6>[ 1.108119] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10614 10:56:30.163555 <6>[ 1.116660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10615 10:56:30.173493 <6>[ 1.125288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10616 10:56:30.183750 <6>[ 1.133993] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10617 10:56:30.190896 <6>[ 1.142712] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10618 10:56:30.200381 <6>[ 1.151253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10619 10:56:30.207061 <6>[ 1.160060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10620 10:56:30.216856 <6>[ 1.168604] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10621 10:56:30.228939 <6>[ 1.184219] loop: module loaded
10622 10:56:30.235207 <6>[ 1.190272] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10623 10:56:30.258073 <4>[ 1.213550] mtk-pmic-keys: Failed to locate of_node [id: -1]
10624 10:56:30.265042 <6>[ 1.220669] megasas: 07.719.03.00-rc1
10625 10:56:30.274997 <6>[ 1.230456] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10626 10:56:30.287449 <6>[ 1.242399] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10627 10:56:30.304057 <6>[ 1.259190] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10628 10:56:30.364896 <6>[ 1.313419] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10629 10:56:31.833840 <6>[ 2.789876] Freeing initrd memory: 46264K
10630 10:56:31.844205 <6>[ 2.800152] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10631 10:56:31.855140 <6>[ 2.811332] tun: Universal TUN/TAP device driver, 1.6
10632 10:56:31.858587 <6>[ 2.817394] thunder_xcv, ver 1.0
10633 10:56:31.862258 <6>[ 2.820900] thunder_bgx, ver 1.0
10634 10:56:31.865205 <6>[ 2.824394] nicpf, ver 1.0
10635 10:56:31.875615 <6>[ 2.828409] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10636 10:56:31.878964 <6>[ 2.835885] hns3: Copyright (c) 2017 Huawei Corporation.
10637 10:56:31.885612 <6>[ 2.841473] hclge is initializing
10638 10:56:31.888761 <6>[ 2.845053] e1000: Intel(R) PRO/1000 Network Driver
10639 10:56:31.895410 <6>[ 2.850181] e1000: Copyright (c) 1999-2006 Intel Corporation.
10640 10:56:31.898890 <6>[ 2.856195] e1000e: Intel(R) PRO/1000 Network Driver
10641 10:56:31.905364 <6>[ 2.861410] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10642 10:56:31.912522 <6>[ 2.867598] igb: Intel(R) Gigabit Ethernet Network Driver
10643 10:56:31.918847 <6>[ 2.873248] igb: Copyright (c) 2007-2014 Intel Corporation.
10644 10:56:31.925488 <6>[ 2.879084] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10645 10:56:31.931965 <6>[ 2.885602] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10646 10:56:31.935249 <6>[ 2.892064] sky2: driver version 1.30
10647 10:56:31.941893 <6>[ 2.897037] VFIO - User Level meta-driver version: 0.3
10648 10:56:31.949189 <6>[ 2.905214] usbcore: registered new interface driver usb-storage
10649 10:56:31.955924 <6>[ 2.911656] usbcore: registered new device driver onboard-usb-hub
10650 10:56:31.964719 <6>[ 2.920707] mt6397-rtc mt6359-rtc: registered as rtc0
10651 10:56:31.974362 <6>[ 2.926169] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:56:31 UTC (1685962591)
10652 10:56:31.977846 <6>[ 2.935737] i2c_dev: i2c /dev entries driver
10653 10:56:31.994713 <6>[ 2.947484] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10654 10:56:32.001800 <6>[ 2.957736] sdhci: Secure Digital Host Controller Interface driver
10655 10:56:32.008069 <6>[ 2.964173] sdhci: Copyright(c) Pierre Ossman
10656 10:56:32.014854 <6>[ 2.969563] Synopsys Designware Multimedia Card Interface Driver
10657 10:56:32.018076 <6>[ 2.976137] mmc0: CQHCI version 5.10
10658 10:56:32.024439 <6>[ 2.976709] sdhci-pltfm: SDHCI platform and OF driver helper
10659 10:56:32.031947 <6>[ 2.988295] ledtrig-cpu: registered to indicate activity on CPUs
10660 10:56:32.043234 <6>[ 2.995787] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10661 10:56:32.049546 <6>[ 3.003190] usbcore: registered new interface driver usbhid
10662 10:56:32.052798 <6>[ 3.009016] usbhid: USB HID core driver
10663 10:56:32.059611 <6>[ 3.013273] spi_master spi0: will run message pump with realtime priority
10664 10:56:32.110384 <6>[ 3.059720] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10665 10:56:32.128909 <6>[ 3.074967] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10666 10:56:32.132435 <6>[ 3.088556] mmc0: Command Queue Engine enabled
10667 10:56:32.139450 <6>[ 3.090412] cros-ec-spi spi0.0: Chrome EC device registered
10668 10:56:32.145722 <6>[ 3.093303] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10669 10:56:32.148852 <6>[ 3.106323] mmcblk0: mmc0:0001 DA4128 116 GiB
10670 10:56:32.163594 <6>[ 3.116309] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10671 10:56:32.169979 <6>[ 3.119931] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10672 10:56:32.177074 <6>[ 3.127709] NET: Registered PF_PACKET protocol family
10673 10:56:32.180132 <6>[ 3.133183] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10674 10:56:32.187139 <6>[ 3.136948] 9pnet: Installing 9P2000 support
10675 10:56:32.190359 <6>[ 3.142715] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10676 10:56:32.197282 <5>[ 3.146645] Key type dns_resolver registered
10677 10:56:32.203757 <6>[ 3.152450] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10678 10:56:32.207058 <6>[ 3.156827] registered taskstats version 1
10679 10:56:32.209966 <5>[ 3.167254] Loading compiled-in X.509 certificates
10680 10:56:32.246026 <4>[ 3.194726] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10681 10:56:32.255411 <4>[ 3.205421] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10682 10:56:32.266053 <3>[ 3.218172] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10683 10:56:32.277928 <6>[ 3.233704] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10684 10:56:32.284952 <6>[ 3.240420] xhci-mtk 11200000.usb: xHCI Host Controller
10685 10:56:32.291150 <6>[ 3.245918] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10686 10:56:32.301422 <6>[ 3.253772] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10687 10:56:32.308144 <6>[ 3.263199] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10688 10:56:32.314825 <6>[ 3.269371] xhci-mtk 11200000.usb: xHCI Host Controller
10689 10:56:32.321661 <6>[ 3.274868] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10690 10:56:32.328051 <6>[ 3.282530] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10691 10:56:32.334690 <6>[ 3.290329] hub 1-0:1.0: USB hub found
10692 10:56:32.337844 <6>[ 3.294361] hub 1-0:1.0: 1 port detected
10693 10:56:32.347886 <6>[ 3.298714] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10694 10:56:32.351225 <6>[ 3.307499] hub 2-0:1.0: USB hub found
10695 10:56:32.354673 <6>[ 3.311534] hub 2-0:1.0: 1 port detected
10696 10:56:32.362889 <6>[ 3.318728] mtk-msdc 11f70000.mmc: Got CD GPIO
10697 10:56:32.384685 <6>[ 3.336707] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10698 10:56:32.390897 <6>[ 3.344773] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10699 10:56:32.400671 <4>[ 3.352741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10700 10:56:32.410561 <6>[ 3.362394] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10701 10:56:32.417256 <6>[ 3.370476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10702 10:56:32.426891 <6>[ 3.378510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10703 10:56:32.433529 <6>[ 3.386433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10704 10:56:32.440350 <6>[ 3.394255] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10705 10:56:32.449893 <6>[ 3.402077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10706 10:56:32.460004 <6>[ 3.412797] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10707 10:56:32.469947 <6>[ 3.421172] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10708 10:56:32.476861 <6>[ 3.429526] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10709 10:56:32.486462 <6>[ 3.437869] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10710 10:56:32.492870 <6>[ 3.446212] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10711 10:56:32.502875 <6>[ 3.454554] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10712 10:56:32.509923 <6>[ 3.462897] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10713 10:56:32.519540 <6>[ 3.471240] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10714 10:56:32.526301 <6>[ 3.479587] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10715 10:56:32.535821 <6>[ 3.487937] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10716 10:56:32.542864 <6>[ 3.496281] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10717 10:56:32.552481 <6>[ 3.504625] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10718 10:56:32.559482 <6>[ 3.512968] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10719 10:56:32.568953 <6>[ 3.521312] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10720 10:56:32.576136 <6>[ 3.529662] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10721 10:56:32.582880 <6>[ 3.538555] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10722 10:56:32.589544 <6>[ 3.545957] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10723 10:56:32.596912 <6>[ 3.553008] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10724 10:56:32.607106 <6>[ 3.560104] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10725 10:56:32.613669 <6>[ 3.567414] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10726 10:56:32.624172 <6>[ 3.574334] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10727 10:56:32.630377 <6>[ 3.583484] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10728 10:56:32.640791 <6>[ 3.592614] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10729 10:56:32.650229 <6>[ 3.601916] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10730 10:56:32.660654 <6>[ 3.611392] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10731 10:56:32.670358 <6>[ 3.620867] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10732 10:56:32.676811 <6>[ 3.629993] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10733 10:56:32.686597 <6>[ 3.639466] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10734 10:56:32.696699 <6>[ 3.648594] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10735 10:56:32.706798 <6>[ 3.657896] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10736 10:56:32.716702 <6>[ 3.668061] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10737 10:56:32.727298 <6>[ 3.679939] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10738 10:56:32.758152 <6>[ 3.711130] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10739 10:56:32.912526 <6>[ 3.868693] hub 1-1:1.0: USB hub found
10740 10:56:32.915589 <6>[ 3.873166] hub 1-1:1.0: 4 ports detected
10741 10:56:33.038464 <6>[ 3.991344] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 10:56:33.062855 <6>[ 4.018868] hub 2-1:1.0: USB hub found
10743 10:56:33.066189 <6>[ 4.023287] hub 2-1:1.0: 3 ports detected
10744 10:56:33.238198 <6>[ 4.191287] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10745 10:56:33.371729 <6>[ 4.327471] hub 1-1.4:1.0: USB hub found
10746 10:56:33.374294 <6>[ 4.332178] hub 1-1.4:1.0: 2 ports detected
10747 10:56:33.450505 <6>[ 4.403519] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10748 10:56:33.674376 <6>[ 4.627286] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10749 10:56:33.866519 <6>[ 4.819287] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10750 10:56:45.018880 <6>[ 15.979835] ALSA device list:
10751 10:56:45.025180 <6>[ 15.983091] No soundcards found.
10752 10:56:45.037655 <6>[ 15.995463] Freeing unused kernel memory: 8384K
10753 10:56:45.041284 <6>[ 16.000379] Run /init as init process
10754 10:56:45.071588 <6>[ 16.029204] NET: Registered PF_INET6 protocol family
10755 10:56:45.078391 <6>[ 16.035768] Segment Routing with IPv6
10756 10:56:45.081491 <6>[ 16.039722] In-situ OAM (IOAM) with IPv6
10757 10:56:45.116368 <30>[ 16.054078] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10758 10:56:45.119495 <30>[ 16.077896] systemd[1]: Detected architecture arm64.
10759 10:56:45.119615
10760 10:56:45.126502 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10761 10:56:45.126611
10762 10:56:45.141798 <30>[ 16.099440] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10763 10:56:45.273433 <30>[ 16.227719] systemd[1]: Queued start job for default target Graphical Interface.
10764 10:56:45.319033 <30>[ 16.276621] systemd[1]: Created slice system-getty.slice.
10765 10:56:45.325538 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10766 10:56:45.342559 <30>[ 16.299884] systemd[1]: Created slice system-modprobe.slice.
10767 10:56:45.348910 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10768 10:56:45.366406 <30>[ 16.323749] systemd[1]: Created slice system-serial\x2dgetty.slice.
10769 10:56:45.375897 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10770 10:56:45.390508 <30>[ 16.348318] systemd[1]: Created slice User and Session Slice.
10771 10:56:45.397531 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10772 10:56:45.417761 <30>[ 16.371810] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10773 10:56:45.427560 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10774 10:56:45.444760 <30>[ 16.399373] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10775 10:56:45.451788 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10776 10:56:45.472412 <30>[ 16.423378] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10777 10:56:45.478722 <30>[ 16.435413] systemd[1]: Reached target Local Encrypted Volumes.
10778 10:56:45.485368 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10779 10:56:45.502082 <30>[ 16.459643] systemd[1]: Reached target Paths.
10780 10:56:45.505514 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10781 10:56:45.521927 <30>[ 16.479326] systemd[1]: Reached target Remote File Systems.
10782 10:56:45.527931 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10783 10:56:45.542127 <30>[ 16.499313] systemd[1]: Reached target Slices.
10784 10:56:45.544927 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10785 10:56:45.561784 <30>[ 16.519327] systemd[1]: Reached target Swap.
10786 10:56:45.565229 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10787 10:56:45.585045 <30>[ 16.539645] systemd[1]: Listening on initctl Compatibility Named Pipe.
10788 10:56:45.591803 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10789 10:56:45.598230 <30>[ 16.554390] systemd[1]: Listening on Journal Audit Socket.
10790 10:56:45.604557 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10791 10:56:45.617580 <30>[ 16.575582] systemd[1]: Listening on Journal Socket (/dev/log).
10792 10:56:45.624570 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10793 10:56:45.641956 <30>[ 16.599608] systemd[1]: Listening on Journal Socket.
10794 10:56:45.648554 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10795 10:56:45.665545 <30>[ 16.619628] systemd[1]: Listening on Network Service Netlink Socket.
10796 10:56:45.671998 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10797 10:56:45.686596 <30>[ 16.644054] systemd[1]: Listening on udev Control Socket.
10798 10:56:45.692974 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10799 10:56:45.710283 <30>[ 16.668001] systemd[1]: Listening on udev Kernel Socket.
10800 10:56:45.716683 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10801 10:56:45.753914 <30>[ 16.711497] systemd[1]: Mounting Huge Pages File System...
10802 10:56:45.760159 Mounting [0;1;39mHuge Pages File System[0m...
10803 10:56:45.776005 <30>[ 16.733296] systemd[1]: Mounting POSIX Message Queue File System...
10804 10:56:45.782367 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10805 10:56:45.799433 <30>[ 16.757187] systemd[1]: Mounting Kernel Debug File System...
10806 10:56:45.806448 Mounting [0;1;39mKernel Debug File System[0m...
10807 10:56:45.825088 <30>[ 16.779501] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10808 10:56:45.865637 <30>[ 16.819628] systemd[1]: Starting Create list of static device nodes for the current kernel...
10809 10:56:45.871674 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10810 10:56:45.892109 <30>[ 16.849418] systemd[1]: Starting Load Kernel Module configfs...
10811 10:56:45.898313 Starting [0;1;39mLoad Kernel Module configfs[0m...
10812 10:56:45.915727 <30>[ 16.873465] systemd[1]: Starting Load Kernel Module drm...
10813 10:56:45.922181 Starting [0;1;39mLoad Kernel Module drm[0m...
10814 10:56:45.940824 <30>[ 16.895480] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10815 10:56:45.951821 <30>[ 16.909005] systemd[1]: Starting Journal Service...
10816 10:56:45.954747 Starting [0;1;39mJournal Service[0m...
10817 10:56:45.972441 <30>[ 16.929849] systemd[1]: Starting Load Kernel Modules...
10818 10:56:45.978975 Starting [0;1;39mLoad Kernel Modules[0m...
10819 10:56:45.999776 <30>[ 16.953709] systemd[1]: Starting Remount Root and Kernel File Systems...
10820 10:56:46.005815 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10821 10:56:46.020887 <30>[ 16.978407] systemd[1]: Starting Coldplug All udev Devices...
10822 10:56:46.027111 Starting [0;1;39mColdplug All udev Devices[0m...
10823 10:56:46.044725 <30>[ 17.002213] systemd[1]: Mounted Huge Pages File System.
10824 10:56:46.050868 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10825 10:56:46.067201 <30>[ 17.024874] systemd[1]: Started Journal Service.
10826 10:56:46.073543 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10827 10:56:46.087203 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10828 10:56:46.102209 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10829 10:56:46.122388 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10830 10:56:46.139756 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10831 10:56:46.155904 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10832 10:56:46.178804 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10833 10:56:46.202893 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10834 10:56:46.221499 See 'systemctl status systemd-remount-fs.service' for details.
10835 10:56:46.274484 Mounting [0;1;39mKernel Configuration File System[0m...
10836 10:56:46.292179 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10837 10:56:46.309677 <46>[ 17.264299] systemd-journald[177]: Received client request to flush runtime journal.
10838 10:56:46.318612 Starting [0;1;39mLoad/Save Random Seed[0m...
10839 10:56:46.336797 Starting [0;1;39mApply Kernel Variables[0m...
10840 10:56:46.352835 Starting [0;1;39mCreate System Users[0m...
10841 10:56:46.371260 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10842 10:56:46.394281 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10843 10:56:46.411135 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10844 10:56:46.427024 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10845 10:56:46.446845 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10846 10:56:46.462426 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10847 10:56:46.497995 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10848 10:56:46.522398 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10849 10:56:46.534262 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10850 10:56:46.549582 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10851 10:56:46.598318 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10852 10:56:46.621374 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10853 10:56:46.638501 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10854 10:56:46.658237 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10855 10:56:46.714581 Starting [0;1;39mNetwork Service[0m...
10856 10:56:46.739745 Starting [0;1;39mNetwork Time Synchronization[0m...
10857 10:56:46.757554 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10858 10:56:46.795163 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10859 10:56:46.810811 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10860 10:56:46.870594 <6>[ 17.824978] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10861 10:56:46.873779 Starting [0;1;39mNetwork Name Resolution[0m...
10862 10:56:46.881529 <6>[ 17.839191] remoteproc remoteproc0: scp is available
10863 10:56:46.891699 <4>[ 17.844674] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10864 10:56:46.898140 <6>[ 17.856220] remoteproc remoteproc0: powering up scp
10865 10:56:46.904967 <6>[ 17.856518] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10866 10:56:46.915060 <4>[ 17.862225] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10867 10:56:46.924870 <6>[ 17.872553] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10868 10:56:46.931537 <3>[ 17.882560] remoteproc remoteproc0: request_firmware failed: -2
10869 10:56:46.938419 <3>[ 17.883441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 10:56:46.948365 <3>[ 17.883459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 10:56:46.954805 <3>[ 17.883468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 10:56:46.964705 <3>[ 17.883596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 10:56:46.971329 <3>[ 17.883605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 10:56:46.981230 <3>[ 17.883612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 10:56:46.987865 <3>[ 17.883622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 10:56:46.994377 <3>[ 17.883629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 10:56:47.004401 <3>[ 17.883673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 10:56:47.011144 <3>[ 17.883712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 10:56:47.021118 <3>[ 17.883720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 10:56:47.027900 <3>[ 17.883727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 10:56:47.037487 <3>[ 17.883775] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 10:56:47.044048 <3>[ 17.883783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 10:56:47.053984 <3>[ 17.883790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 10:56:47.060999 <3>[ 17.883797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 10:56:47.070889 <3>[ 17.883804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 10:56:47.077158 <3>[ 17.883832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 10:56:47.087155 <6>[ 17.891727] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10888 10:56:47.090744 <6>[ 17.939339] mc: Linux media interface: v0.10
10889 10:56:47.097289 <4>[ 17.962838] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10890 10:56:47.103600 <6>[ 17.989203] usbcore: registered new interface driver r8152
10891 10:56:47.110427 <4>[ 17.994900] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10892 10:56:47.117216 <6>[ 18.002075] videodev: Linux video capture interface: v2.00
10893 10:56:47.123754 <6>[ 18.035243] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10894 10:56:47.129834 <6>[ 18.060590] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10895 10:56:47.140341 <4>[ 18.081433] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10896 10:56:47.146550 <4>[ 18.081433] Fallback method does not support PEC.
10897 10:56:47.150086 <6>[ 18.087447] pci_bus 0000:00: root bus resource [bus 00-ff]
10898 10:56:47.160647 <6>[ 18.104159] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10899 10:56:47.167056 <6>[ 18.108639] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10900 10:56:47.177319 <6>[ 18.117312] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10901 10:56:47.187187 <3>[ 18.121220] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 10:56:47.197221 <6>[ 18.122256] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10903 10:56:47.206720 <6>[ 18.124076] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10904 10:56:47.210447 <6>[ 18.149514] usbcore: registered new interface driver cdc_ether
10905 10:56:47.220020 <6>[ 18.158249] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10906 10:56:47.223291 <6>[ 18.159136] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10907 10:56:47.233374 <6>[ 18.159166] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10908 10:56:47.236823 <6>[ 18.159311] pci 0000:00:00.0: supports D1 D2
10909 10:56:47.243313 <6>[ 18.159316] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10910 10:56:47.253067 <6>[ 18.162088] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10911 10:56:47.259736 <6>[ 18.162280] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10912 10:56:47.266540 <6>[ 18.162311] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10913 10:56:47.273043 <6>[ 18.162332] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10914 10:56:47.279904 <6>[ 18.162350] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10915 10:56:47.286450 <6>[ 18.162470] pci 0000:01:00.0: supports D1 D2
10916 10:56:47.293245 <6>[ 18.162475] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10917 10:56:47.299923 <6>[ 18.171082] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10918 10:56:47.303477 <6>[ 18.175945] Bluetooth: Core ver 2.22
10919 10:56:47.310071 <6>[ 18.181433] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10920 10:56:47.317001 <6>[ 18.181621] usbcore: registered new interface driver r8153_ecm
10921 10:56:47.323807 <6>[ 18.187823] NET: Registered PF_BLUETOOTH protocol family
10922 10:56:47.330518 <6>[ 18.189016] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10923 10:56:47.340760 <6>[ 18.190143] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10924 10:56:47.347384 <6>[ 18.190289] usbcore: registered new interface driver uvcvideo
10925 10:56:47.357176 <4>[ 18.194818] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10926 10:56:47.363731 <4>[ 18.194831] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10927 10:56:47.373792 <6>[ 18.195625] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10928 10:56:47.380359 <6>[ 18.199777] Bluetooth: HCI device and connection manager initialized
10929 10:56:47.386977 <6>[ 18.206615] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10930 10:56:47.393528 <6>[ 18.207482] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10931 10:56:47.400425 <6>[ 18.211499] remoteproc remoteproc0: powering up scp
10932 10:56:47.410293 <4>[ 18.211551] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10933 10:56:47.416920 <3>[ 18.211559] remoteproc remoteproc0: request_firmware failed: -2
10934 10:56:47.423546 <3>[ 18.211563] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10935 10:56:47.426603 <6>[ 18.214965] Bluetooth: HCI socket layer initialized
10936 10:56:47.436568 <6>[ 18.221192] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10937 10:56:47.439787 <6>[ 18.228620] Bluetooth: L2CAP socket layer initialized
10938 10:56:47.449605 <6>[ 18.236078] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10939 10:56:47.453262 <6>[ 18.243331] r8152 2-1.3:1.0 eth0: v1.12.13
10940 10:56:47.460111 <6>[ 18.243673] Bluetooth: SCO socket layer initialized
10941 10:56:47.462992 <6>[ 18.248072] pci 0000:00:00.0: PCI bridge to [bus 01]
10942 10:56:47.473038 <6>[ 18.248080] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10943 10:56:47.479950 <6>[ 18.255070] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10944 10:56:47.483042 <6>[ 18.262028] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10945 10:56:47.492798 <3>[ 18.290467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 10:56:47.499253 <6>[ 18.293201] usbcore: registered new interface driver btusb
10947 10:56:47.505963 <6>[ 18.293467] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10948 10:56:47.512793 <6>[ 18.293737] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10949 10:56:47.519221 <3>[ 18.305353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10950 10:56:47.529047 <4>[ 18.305570] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10951 10:56:47.536010 <3>[ 18.305582] Bluetooth: hci0: Failed to load firmware file (-2)
10952 10:56:47.542449 <3>[ 18.305587] Bluetooth: hci0: Failed to set up firmware (-2)
10953 10:56:47.552445 <4>[ 18.305592] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10954 10:56:47.559076 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10955 10:56:47.580672 [[0;32m OK [0m] Started [0;<3>[ 18.534126] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 10:56:47.590988 1;39mNetwork Nam<3>[ 18.534829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10957 10:56:47.601031 e Resolution[0m<5>[ 18.550064] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10958 10:56:47.601121 .
10959 10:56:47.611139 <3>[ 18.565712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 10:56:47.622990 <5>[ 18.577770] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10961 10:56:47.629987 <4>[ 18.584749] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10962 10:56:47.636912 <6>[ 18.593643] cfg80211: failed to load regulatory.db
10963 10:56:47.644033 <3>[ 18.599106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 10:56:47.650337 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10965 10:56:47.679801 <3>[ 18.634103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 10:56:47.691660 <6>[ 18.645995] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10967 10:56:47.698142 <6>[ 18.653603] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10968 10:56:47.709700 <3>[ 18.664257] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 10:56:47.722891 <6>[ 18.680300] mt7921e 0000:01:00.0: ASIC revision: 79610010
10970 10:56:47.738864 <3>[ 18.693591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 10:56:47.828378 <4>[ 18.779866] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10972 10:56:47.841269 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10973 10:56:47.853539 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10974 10:56:47.869369 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10975 10:56:47.888902 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10976 10:56:47.906375 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10977 10:56:47.921901 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10978 10:56:47.951749 [[0;32m OK [0m] Listening on<4>[ 18.901643] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 10:56:47.955191 [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10980 10:56:48.013703 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10981 10:56:48.034681 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10982 10:56:48.058197 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10983 10:56:48.071005 <4>[ 19.022107] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 10:56:48.077541 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10985 10:56:48.101025 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10986 10:56:48.117138 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10987 10:56:48.137011 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10988 10:56:48.149435 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10989 10:56:48.165587 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10990 10:56:48.189940 <4>[ 19.141322] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 10:56:48.218237 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10992 10:56:48.243519 Starting [0;1;39mUser Login Management[0m...
10993 10:56:48.259922 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10994 10:56:48.280126 Starting [0;1;39mPermit User Sessions[0m...
10995 10:56:48.312989 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch St<4>[ 19.262972] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 10:56:48.313095 atus[0m.
10997 10:56:48.335378 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10998 10:56:48.386273 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10999 10:56:48.404264 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11000 10:56:48.433315 [[0;32m OK [<4>[ 19.385491] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 10:56:48.439301 0m] Reached target [0;1;39mLogin Prompts[0m.
11002 10:56:48.455903 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11003 10:56:48.474437 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11004 10:56:48.489327 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11005 10:56:48.533224 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11006 10:56:48.555007 <4>[ 19.506379] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 10:56:48.564805 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11008 10:56:48.584354
11009 10:56:48.584439
11010 10:56:48.587722 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11011 10:56:48.587807
11012 10:56:48.591301 debian-bullseye-arm64 login: root (automatic login)
11013 10:56:48.591419
11014 10:56:48.591485
11015 10:56:48.607816 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11016 10:56:48.607923
11017 10:56:48.614215 The programs included with the Debian GNU/Linux system are free software;
11018 10:56:48.620559 the exact distribution terms for each program are described in the
11019 10:56:48.624088 individual files in /usr/share/doc/*/copyright.
11020 10:56:48.624172
11021 10:56:48.630623 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11022 10:56:48.634007 permitted by applicable law.
11023 10:56:48.634344 Matched prompt #10: / #
11025 10:56:48.634552 Setting prompt string to ['/ #']
11026 10:56:48.634644 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11028 10:56:48.634842 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11029 10:56:48.634931 start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
11030 10:56:48.635038 Setting prompt string to ['/ #']
11031 10:56:48.635100 Forcing a shell prompt, looking for ['/ #']
11033 10:56:48.685318 / #
11034 10:56:48.685428 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11035 10:56:48.685508 Waiting using forced prompt support (timeout 00:02:30)
11036 10:56:48.685607 <4>[ 19.625552] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11037 10:56:48.690903
11038 10:56:48.691174 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11039 10:56:48.691268 start: 2.2.7 export-device-env (timeout 00:02:56) [common]
11040 10:56:48.691404 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11041 10:56:48.691494 end: 2.2 depthcharge-retry (duration 00:02:04) [common]
11042 10:56:48.691580 end: 2 depthcharge-action (duration 00:02:04) [common]
11043 10:56:48.691666 start: 3 lava-test-retry (timeout 00:05:00) [common]
11044 10:56:48.691752 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11045 10:56:48.691825 Using namespace: common
11047 10:56:48.792152 / # #
11048 10:56:48.792285 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11049 10:56:48.793830 #<4>[ 19.745334] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 10:56:48.835480
11051 10:56:48.835756 Using /lava-10591003
11053 10:56:48.936061 / # export SHELL=/bin/sh
11054 10:56:48.936235 export SHELL=/bin/sh<4>[ 19.865700] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11055 10:56:48.941037
11057 10:56:49.041482 / # . /lava-10591003/environment
11058 10:56:49.041667 . /lava-10591003/environment<6>[ 19.981559] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11059 10:56:49.041815 <3>[ 19.983161] mt7921e 0000:01:00.0: hardware init failed
11060 10:56:49.041929 <6>[ 19.989571] r8152 2-1.3:1.0 enx002432307852: carrier on
11061 10:56:49.045962
11063 10:56:49.146420 / # /lava-10591003/bin/lava-test-runner /lava-10591003/0
11064 10:56:49.146556 Test shell timeout: 10s (minimum of the action and connection timeout)
11065 10:56:49.152123 /lava-10591003/bin/lava-test-runner /lava-10591003/0
11066 10:56:49.170101 + export TESTRUN_ID=0_cros-ec
11067 10:56:49.177160 + c<8>[ 20.133266] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10591003_1.5.2.3.1>
11068 10:56:49.177415 Received signal: <STARTRUN> 0_cros-ec 10591003_1.5.2.3.1
11069 10:56:49.177489 Starting test lava.0_cros-ec (10591003_1.5.2.3.1)
11070 10:56:49.177572 Skipping test definition patterns.
11071 10:56:49.180168 d /lava-10591003/0/tests/0_cros-ec
11072 10:56:49.183777 + cat uuid
11073 10:56:49.183851 + UUID=10591003_1.5.2.3.1
11074 10:56:49.183919 + set +x
11075 10:56:49.190277 + python3 -m cros.runners.lava_runner -v
11076 10:56:49.884506 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11077 10:56:49.891648 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11078 10:56:49.891750
11079 10:56:49.898183 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11081 10:56:49.900728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11082 10:56:49.907523 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11083 10:56:49.914392 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11084 10:56:49.914472
11085 10:56:49.924485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11086 10:56:49.924732 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11088 10:56:49.927577 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11089 10:56:49.937231 Checks the cros-ec gyros<8>[ 20.893360] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10591003_1.5.2.3.1>
11090 10:56:49.937479 Received signal: <ENDRUN> 0_cros-ec 10591003_1.5.2.3.1
11091 10:56:49.937560 Ending use of test pattern.
11092 10:56:49.937625 Ending test lava.0_cros-ec (10591003_1.5.2.3.1), duration 0.76
11094 10:56:49.940738 cope IIO ABI. ... skipped 'No cros-ec-gyro found'
11095 10:56:49.940812
11096 10:56:49.947111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11097 10:56:49.947399 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11099 10:56:49.953819 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11100 10:56:49.957214 Checks the standard ABI for the main Embedded Controller. ... ok
11101 10:56:49.957316
11102 10:56:49.963532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11103 10:56:49.963758 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11105 10:56:49.970761 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11106 10:56:49.973942 Checks the main Embedded controller character device. ... ok
11107 10:56:49.976955
11108 10:56:49.980322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11109 10:56:49.980582 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11111 10:56:49.986991 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11112 10:56:49.993513 Checks basic comunication with the main Embedded controller. ... ok
11113 10:56:49.993591
11114 10:56:49.997116 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11116 10:56:50.000404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11117 10:56:50.003182 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11118 10:56:50.010348 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11119 10:56:50.010459
11120 10:56:50.016728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11121 10:56:50.016979 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11123 10:56:50.023130 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11124 10:56:50.029725 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11125 10:56:50.029819
11126 10:56:50.036628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11127 10:56:50.036884 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11129 10:56:50.042884 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11130 10:56:50.049711 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11131 10:56:50.049795
11132 10:56:50.053132 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11134 10:56:50.056389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11135 10:56:50.060017 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11136 10:56:50.065920 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11137 10:56:50.066001
11138 10:56:50.073125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11139 10:56:50.073369 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11141 10:56:50.079221 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11142 10:56:50.086397 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11143 10:56:50.086500
11144 10:56:50.092860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11145 10:56:50.093107 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11147 10:56:50.099294 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11148 10:56:50.106191 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11149 10:56:50.106282
11150 10:56:50.112649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11151 10:56:50.112900 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11153 10:56:50.115672 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11154 10:56:50.125852 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11155 10:56:50.125931
11156 10:56:50.132213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11157 10:56:50.132464 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11159 10:56:50.135785 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11160 10:56:50.145750 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11161 10:56:50.145837
11162 10:56:50.152021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11163 10:56:50.152289 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11165 10:56:50.158910 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11166 10:56:50.162388 Check the cros battery ABI. ... skipped 'No BAT found'
11167 10:56:50.162500
11168 10:56:50.168751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11169 10:56:50.169007 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11171 10:56:50.175621 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11172 10:56:50.181759 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11173 10:56:50.181861
11174 10:56:50.189040 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11176 10:56:50.191797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11177 10:56:50.195251 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11178 10:56:50.202041 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11179 10:56:50.202124
11180 10:56:50.208468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11181 10:56:50.208722 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11183 10:56:50.215036 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11184 10:56:50.221568 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11185 10:56:50.221700
11186 10:56:50.228288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11187 10:56:50.228372
11188 10:56:50.228606 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11190 10:56:50.234877 ----------------------------------------------------------------------
11191 10:56:50.234987 Ran 18 tests in 0.011s
11192 10:56:50.238300
11193 10:56:50.238372 OK (skipped=15)
11194 10:56:50.238434 + set +x
11195 10:56:50.241358 <LAVA_TEST_RUNNER EXIT>
11196 10:56:50.241609 ok: lava_test_shell seems to have completed
11197 10:56:50.241793 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11198 10:56:50.241890 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11199 10:56:50.241976 end: 3 lava-test-retry (duration 00:00:02) [common]
11200 10:56:50.242062 start: 4 finalize (timeout 00:07:35) [common]
11201 10:56:50.242155 start: 4.1 power-off (timeout 00:00:30) [common]
11202 10:56:50.242305 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11203 10:56:50.317682 >> Command sent successfully.
11204 10:56:50.320180 Returned 0 in 0 seconds
11205 10:56:50.420563 end: 4.1 power-off (duration 00:00:00) [common]
11207 10:56:50.420884 start: 4.2 read-feedback (timeout 00:07:35) [common]
11208 10:56:50.421135 Listened to connection for namespace 'common' for up to 1s
11209 10:56:51.422098 Finalising connection for namespace 'common'
11210 10:56:51.422266 Disconnecting from shell: Finalise
11211 10:56:51.422353 / #
11212 10:56:51.522635 end: 4.2 read-feedback (duration 00:00:01) [common]
11213 10:56:51.522781 end: 4 finalize (duration 00:00:01) [common]
11214 10:56:51.522901 Cleaning after the job
11215 10:56:51.522999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/ramdisk
11216 10:56:51.527951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/kernel
11217 10:56:51.533897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/dtb
11218 10:56:51.534062 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591003/tftp-deploy-gzo4hxez/modules
11219 10:56:51.539356 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591003
11220 10:56:51.635424 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591003
11221 10:56:51.635593 Job finished correctly