Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 34
1 10:50:33.307698 lava-dispatcher, installed at version: 2023.05.1
2 10:50:33.307904 start: 0 validate
3 10:50:33.308072 Start time: 2023-06-05 10:50:33.308065+00:00 (UTC)
4 10:50:33.308201 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:50:33.308330 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:50:33.601108 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:50:33.601944 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:50:33.900576 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:50:33.901400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:51:22.847298 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:51:22.848040 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:51:23.432191 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:51:23.432942 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:51:23.726055 validate duration: 50.42
16 10:51:23.727331 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:51:23.727870 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:51:23.728378 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:51:23.729043 Not decompressing ramdisk as can be used compressed.
20 10:51:23.729531 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:51:23.729913 saving as /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/ramdisk/initrd.cpio.gz
22 10:51:23.730264 total size: 5624321 (5MB)
23 10:51:31.918141 progress 0% (0MB)
24 10:51:31.922667 progress 5% (0MB)
25 10:51:31.924171 progress 10% (0MB)
26 10:51:31.925558 progress 15% (0MB)
27 10:51:31.927066 progress 20% (1MB)
28 10:51:31.928404 progress 25% (1MB)
29 10:51:31.929912 progress 30% (1MB)
30 10:51:31.931386 progress 35% (1MB)
31 10:51:31.932705 progress 40% (2MB)
32 10:51:31.934171 progress 45% (2MB)
33 10:51:31.935481 progress 50% (2MB)
34 10:51:31.936951 progress 55% (2MB)
35 10:51:31.938263 progress 60% (3MB)
36 10:51:31.939764 progress 65% (3MB)
37 10:51:31.941275 progress 70% (3MB)
38 10:51:31.942592 progress 75% (4MB)
39 10:51:31.944054 progress 80% (4MB)
40 10:51:31.945470 progress 85% (4MB)
41 10:51:31.946961 progress 90% (4MB)
42 10:51:31.948517 progress 95% (5MB)
43 10:51:31.949927 progress 100% (5MB)
44 10:51:31.950142 5MB downloaded in 8.22s (0.65MB/s)
45 10:51:31.950287 end: 1.1.1 http-download (duration 00:00:08) [common]
47 10:51:31.950517 end: 1.1 download-retry (duration 00:00:08) [common]
48 10:51:31.950602 start: 1.2 download-retry (timeout 00:09:52) [common]
49 10:51:31.950684 start: 1.2.1 http-download (timeout 00:09:52) [common]
50 10:51:31.950812 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:51:31.950882 saving as /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/kernel/Image
52 10:51:31.950942 total size: 45746688 (43MB)
53 10:51:31.951000 No compression specified
54 10:51:31.952064 progress 0% (0MB)
55 10:51:31.963387 progress 5% (2MB)
56 10:51:31.974932 progress 10% (4MB)
57 10:51:31.986319 progress 15% (6MB)
58 10:51:31.997727 progress 20% (8MB)
59 10:51:32.008907 progress 25% (10MB)
60 10:51:32.019845 progress 30% (13MB)
61 10:51:32.031065 progress 35% (15MB)
62 10:51:32.042206 progress 40% (17MB)
63 10:51:32.053578 progress 45% (19MB)
64 10:51:32.064892 progress 50% (21MB)
65 10:51:32.076145 progress 55% (24MB)
66 10:51:32.087645 progress 60% (26MB)
67 10:51:32.099195 progress 65% (28MB)
68 10:51:32.110550 progress 70% (30MB)
69 10:51:32.121782 progress 75% (32MB)
70 10:51:32.132991 progress 80% (34MB)
71 10:51:32.144378 progress 85% (37MB)
72 10:51:32.155966 progress 90% (39MB)
73 10:51:32.167140 progress 95% (41MB)
74 10:51:32.178276 progress 100% (43MB)
75 10:51:32.178394 43MB downloaded in 0.23s (191.81MB/s)
76 10:51:32.178554 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:51:32.178827 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:51:32.178917 start: 1.3 download-retry (timeout 00:09:52) [common]
80 10:51:32.179004 start: 1.3.1 http-download (timeout 00:09:52) [common]
81 10:51:32.179135 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:51:32.179203 saving as /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/dtb/mt8192-asurada-spherion-r0.dtb
83 10:51:32.179266 total size: 46924 (0MB)
84 10:51:32.179325 No compression specified
85 10:51:32.180418 progress 69% (0MB)
86 10:51:32.180782 progress 100% (0MB)
87 10:51:32.180930 0MB downloaded in 0.00s (26.93MB/s)
88 10:51:32.181047 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:51:32.181265 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:51:32.181348 start: 1.4 download-retry (timeout 00:09:52) [common]
92 10:51:32.181428 start: 1.4.1 http-download (timeout 00:09:52) [common]
93 10:51:32.181533 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:51:32.181599 saving as /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/nfsrootfs/full.rootfs.tar
95 10:51:32.181658 total size: 195125384 (186MB)
96 10:51:32.181716 Using unxz to decompress xz
97 10:51:32.185200 progress 0% (0MB)
98 10:51:32.723492 progress 5% (9MB)
99 10:51:33.214381 progress 10% (18MB)
100 10:51:33.782382 progress 15% (27MB)
101 10:51:34.054856 progress 20% (37MB)
102 10:51:34.497446 progress 25% (46MB)
103 10:51:35.054469 progress 30% (55MB)
104 10:51:35.596085 progress 35% (65MB)
105 10:51:36.138562 progress 40% (74MB)
106 10:51:36.695525 progress 45% (83MB)
107 10:51:37.287673 progress 50% (93MB)
108 10:51:37.874169 progress 55% (102MB)
109 10:51:38.506404 progress 60% (111MB)
110 10:51:38.892674 progress 65% (120MB)
111 10:51:38.970223 progress 70% (130MB)
112 10:51:39.117934 progress 75% (139MB)
113 10:51:39.188972 progress 80% (148MB)
114 10:51:39.233610 progress 85% (158MB)
115 10:51:39.320658 progress 90% (167MB)
116 10:51:39.680650 progress 95% (176MB)
117 10:51:40.238724 progress 100% (186MB)
118 10:51:40.244787 186MB downloaded in 8.06s (23.08MB/s)
119 10:51:40.245073 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:51:40.245332 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:51:40.245423 start: 1.5 download-retry (timeout 00:09:43) [common]
123 10:51:40.245512 start: 1.5.1 http-download (timeout 00:09:43) [common]
124 10:51:40.245661 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:51:40.245734 saving as /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/modules/modules.tar
126 10:51:40.245796 total size: 8542412 (8MB)
127 10:51:40.245858 Using unxz to decompress xz
128 10:51:40.249371 progress 0% (0MB)
129 10:51:40.270633 progress 5% (0MB)
130 10:51:40.295337 progress 10% (0MB)
131 10:51:40.321396 progress 15% (1MB)
132 10:51:40.345834 progress 20% (1MB)
133 10:51:40.371022 progress 25% (2MB)
134 10:51:40.395550 progress 30% (2MB)
135 10:51:40.420281 progress 35% (2MB)
136 10:51:40.444615 progress 40% (3MB)
137 10:51:40.469396 progress 45% (3MB)
138 10:51:40.492990 progress 50% (4MB)
139 10:51:40.515360 progress 55% (4MB)
140 10:51:40.539788 progress 60% (4MB)
141 10:51:40.564254 progress 65% (5MB)
142 10:51:40.589285 progress 70% (5MB)
143 10:51:40.615378 progress 75% (6MB)
144 10:51:40.643731 progress 80% (6MB)
145 10:51:40.665994 progress 85% (6MB)
146 10:51:40.690762 progress 90% (7MB)
147 10:51:40.713614 progress 95% (7MB)
148 10:51:40.736801 progress 100% (8MB)
149 10:51:40.742315 8MB downloaded in 0.50s (16.41MB/s)
150 10:51:40.742577 end: 1.5.1 http-download (duration 00:00:00) [common]
152 10:51:40.742836 end: 1.5 download-retry (duration 00:00:00) [common]
153 10:51:40.742930 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 10:51:40.743023 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 10:51:46.288545 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby
156 10:51:46.288772 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
157 10:51:46.288874 start: 1.6.2 lava-overlay (timeout 00:09:37) [common]
158 10:51:46.289038 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv
159 10:51:46.289162 makedir: /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin
160 10:51:46.289264 makedir: /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/tests
161 10:51:46.289360 makedir: /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/results
162 10:51:46.289461 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-add-keys
163 10:51:46.289599 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-add-sources
164 10:51:46.289724 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-background-process-start
165 10:51:46.289848 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-background-process-stop
166 10:51:46.289971 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-common-functions
167 10:51:46.290092 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-echo-ipv4
168 10:51:46.290213 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-install-packages
169 10:51:46.290333 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-installed-packages
170 10:51:46.290451 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-os-build
171 10:51:46.290572 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-probe-channel
172 10:51:46.290695 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-probe-ip
173 10:51:46.290820 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-target-ip
174 10:51:46.290941 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-target-mac
175 10:51:46.291066 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-target-storage
176 10:51:46.291189 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-case
177 10:51:46.291310 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-event
178 10:51:46.291429 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-feedback
179 10:51:46.291550 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-raise
180 10:51:46.291668 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-reference
181 10:51:46.291787 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-runner
182 10:51:46.291906 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-set
183 10:51:46.292024 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-test-shell
184 10:51:46.292176 Updating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-add-keys (debian)
185 10:51:46.303725 Updating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-add-sources (debian)
186 10:51:46.303886 Updating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-install-packages (debian)
187 10:51:46.304072 Updating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-installed-packages (debian)
188 10:51:46.304240 Updating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/bin/lava-os-build (debian)
189 10:51:46.304382 Creating /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/environment
190 10:51:46.304482 LAVA metadata
191 10:51:46.304598 - LAVA_JOB_ID=10590974
192 10:51:46.304666 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:51:46.304771 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:37) [common]
194 10:51:46.304841 skipped lava-vland-overlay
195 10:51:46.304924 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:51:46.305006 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:37) [common]
197 10:51:46.305081 skipped lava-multinode-overlay
198 10:51:46.305192 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:51:46.305291 start: 1.6.2.3 test-definition (timeout 00:09:37) [common]
200 10:51:46.305370 Loading test definitions
201 10:51:46.305466 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:37) [common]
202 10:51:46.305538 Using /lava-10590974 at stage 0
203 10:51:46.305815 uuid=10590974_1.6.2.3.1 testdef=None
204 10:51:46.305906 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:51:46.305996 start: 1.6.2.3.2 test-overlay (timeout 00:09:37) [common]
206 10:51:46.306441 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:51:46.306673 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:37) [common]
209 10:51:46.307266 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:51:46.307539 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:37) [common]
212 10:51:46.393345 runner path: /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/0/tests/0_timesync-off test_uuid 10590974_1.6.2.3.1
213 10:51:46.393563 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:51:46.393805 start: 1.6.2.3.5 git-repo-action (timeout 00:09:37) [common]
216 10:51:46.393880 Using /lava-10590974 at stage 0
217 10:51:46.393982 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:51:46.394074 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/0/tests/1_kselftest-alsa'
219 10:51:54.596848 Running '/usr/bin/git checkout kernelci.org
220 10:51:54.739659 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 10:51:54.740403 uuid=10590974_1.6.2.3.5 testdef=None
222 10:51:54.740618 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 10:51:54.740901 start: 1.6.2.3.6 test-overlay (timeout 00:09:29) [common]
225 10:51:54.741655 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:51:54.741918 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:29) [common]
228 10:51:54.742887 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:51:54.743154 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:29) [common]
231 10:51:54.744634 runner path: /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/0/tests/1_kselftest-alsa test_uuid 10590974_1.6.2.3.5
232 10:51:54.744736 BOARD='mt8192-asurada-spherion-r0'
233 10:51:54.744815 BRANCH='cip-gitlab'
234 10:51:54.744895 SKIPFILE='/dev/null'
235 10:51:54.744974 SKIP_INSTALL='True'
236 10:51:54.745051 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:51:54.745130 TST_CASENAME=''
238 10:51:54.745207 TST_CMDFILES='alsa'
239 10:51:54.745406 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:51:54.745766 Creating lava-test-runner.conf files
242 10:51:54.745869 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10590974/lava-overlay-fzrq7sjv/lava-10590974/0 for stage 0
243 10:51:54.746009 - 0_timesync-off
244 10:51:54.746115 - 1_kselftest-alsa
245 10:51:54.746235 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 10:51:54.746340 start: 1.6.2.4 compress-overlay (timeout 00:09:29) [common]
247 10:52:02.231642 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 10:52:02.231805 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:21) [common]
249 10:52:02.231948 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:52:02.232068 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 10:52:02.232175 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:21) [common]
252 10:52:02.390276 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:52:02.390657 start: 1.6.4 extract-modules (timeout 00:09:21) [common]
254 10:52:02.390791 extracting modules file /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby
255 10:52:02.587230 extracting modules file /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590974/extract-overlay-ramdisk-wthb2_f7/ramdisk
256 10:52:02.787884 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:52:02.788059 start: 1.6.5 apply-overlay-tftp (timeout 00:09:21) [common]
258 10:52:02.788170 [common] Applying overlay to NFS
259 10:52:02.788252 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590974/compress-overlay-ojc5z_iz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby
260 10:52:03.666517 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:52:03.666685 start: 1.6.6 configure-preseed-file (timeout 00:09:20) [common]
262 10:52:03.666786 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:52:03.666879 start: 1.6.7 compress-ramdisk (timeout 00:09:20) [common]
264 10:52:03.666964 Building ramdisk /var/lib/lava/dispatcher/tmp/10590974/extract-overlay-ramdisk-wthb2_f7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10590974/extract-overlay-ramdisk-wthb2_f7/ramdisk
265 10:52:04.057657 >> 128923 blocks
266 10:52:06.026294 rename /var/lib/lava/dispatcher/tmp/10590974/extract-overlay-ramdisk-wthb2_f7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/ramdisk/ramdisk.cpio.gz
267 10:52:06.026718 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:52:06.026838 start: 1.6.8 prepare-kernel (timeout 00:09:18) [common]
269 10:52:06.026944 start: 1.6.8.1 prepare-fit (timeout 00:09:18) [common]
270 10:52:06.027053 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/kernel/Image'
271 10:52:17.376409 Returned 0 in 11 seconds
272 10:52:17.477030 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/kernel/image.itb
273 10:52:17.805812 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:52:17.806178 output: Created: Mon Jun 5 11:52:17 2023
275 10:52:17.806261 output: Image 0 (kernel-1)
276 10:52:17.806325 output: Description:
277 10:52:17.806428 output: Created: Mon Jun 5 11:52:17 2023
278 10:52:17.806491 output: Type: Kernel Image
279 10:52:17.806553 output: Compression: lzma compressed
280 10:52:17.806614 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
281 10:52:17.806675 output: Architecture: AArch64
282 10:52:17.806736 output: OS: Linux
283 10:52:17.806796 output: Load Address: 0x00000000
284 10:52:17.806852 output: Entry Point: 0x00000000
285 10:52:17.806977 output: Hash algo: crc32
286 10:52:17.807086 output: Hash value: 8ce42972
287 10:52:17.807181 output: Image 1 (fdt-1)
288 10:52:17.807274 output: Description: mt8192-asurada-spherion-r0
289 10:52:17.807407 output: Created: Mon Jun 5 11:52:17 2023
290 10:52:17.807520 output: Type: Flat Device Tree
291 10:52:17.807619 output: Compression: uncompressed
292 10:52:17.807702 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:52:17.807785 output: Architecture: AArch64
294 10:52:17.807885 output: Hash algo: crc32
295 10:52:17.807969 output: Hash value: 1df858fa
296 10:52:17.808054 output: Image 2 (ramdisk-1)
297 10:52:17.808150 output: Description: unavailable
298 10:52:17.808232 output: Created: Mon Jun 5 11:52:17 2023
299 10:52:17.808330 output: Type: RAMDisk Image
300 10:52:17.808414 output: Compression: Unknown Compression
301 10:52:17.808498 output: Data Size: 18604104 Bytes = 18168.07 KiB = 17.74 MiB
302 10:52:17.808607 output: Architecture: AArch64
303 10:52:17.808690 output: OS: Linux
304 10:52:17.808773 output: Load Address: unavailable
305 10:52:17.808883 output: Entry Point: unavailable
306 10:52:17.809012 output: Hash algo: crc32
307 10:52:17.809096 output: Hash value: fd6992d4
308 10:52:17.809179 output: Default Configuration: 'conf-1'
309 10:52:17.809261 output: Configuration 0 (conf-1)
310 10:52:17.809372 output: Description: mt8192-asurada-spherion-r0
311 10:52:17.809455 output: Kernel: kernel-1
312 10:52:17.809537 output: Init Ramdisk: ramdisk-1
313 10:52:17.809619 output: FDT: fdt-1
314 10:52:17.809701 output: Loadables: kernel-1
315 10:52:17.809798 output:
316 10:52:17.810048 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:52:17.810176 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:52:17.810335 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 10:52:17.810481 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
320 10:52:17.810605 No LXC device requested
321 10:52:17.810726 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:52:17.810843 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
323 10:52:17.810945 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:52:17.811033 Checking files for TFTP limit of 4294967296 bytes.
325 10:52:17.811584 end: 1 tftp-deploy (duration 00:00:54) [common]
326 10:52:17.811696 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:52:17.811802 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:52:17.811946 substitutions:
329 10:52:17.812013 - {DTB}: 10590974/tftp-deploy-5p_k0bha/dtb/mt8192-asurada-spherion-r0.dtb
330 10:52:17.812093 - {INITRD}: 10590974/tftp-deploy-5p_k0bha/ramdisk/ramdisk.cpio.gz
331 10:52:17.812154 - {KERNEL}: 10590974/tftp-deploy-5p_k0bha/kernel/Image
332 10:52:17.812229 - {LAVA_MAC}: None
333 10:52:17.812317 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby
334 10:52:17.812389 - {NFS_SERVER_IP}: 192.168.201.1
335 10:52:17.812459 - {PRESEED_CONFIG}: None
336 10:52:17.812524 - {PRESEED_LOCAL}: None
337 10:52:17.812596 - {RAMDISK}: 10590974/tftp-deploy-5p_k0bha/ramdisk/ramdisk.cpio.gz
338 10:52:17.812652 - {ROOT_PART}: None
339 10:52:17.812706 - {ROOT}: None
340 10:52:17.812760 - {SERVER_IP}: 192.168.201.1
341 10:52:17.812818 - {TEE}: None
342 10:52:17.812872 Parsed boot commands:
343 10:52:17.812934 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:52:17.813155 Parsed boot commands: tftpboot 192.168.201.1 10590974/tftp-deploy-5p_k0bha/kernel/image.itb 10590974/tftp-deploy-5p_k0bha/kernel/cmdline
345 10:52:17.813247 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:52:17.813333 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:52:17.813425 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:52:17.813510 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:52:17.813581 Not connected, no need to disconnect.
350 10:52:17.813656 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:52:17.813738 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:52:17.813804 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 10:52:17.817336 Setting prompt string to ['lava-test: # ']
354 10:52:17.817855 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:52:17.818031 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:52:17.818173 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:52:17.818310 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:52:17.818640 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 10:52:22.954219 >> Command sent successfully.
360 10:52:22.956689 Returned 0 in 5 seconds
361 10:52:23.057048 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:52:23.057361 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:52:23.057463 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:52:23.057551 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:52:23.057624 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:52:23.057746 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:52:23.058108 [Enter `^Ec?' for help]
369 10:52:23.230163
370 10:52:23.230308
371 10:52:23.230378 F0: 102B 0000
372 10:52:23.230441
373 10:52:23.230503 F3: 1001 0000 [0200]
374 10:52:23.230563
375 10:52:23.233944 F3: 1001 0000
376 10:52:23.234021
377 10:52:23.234085 F7: 102D 0000
378 10:52:23.234144
379 10:52:23.237311 F1: 0000 0000
380 10:52:23.237386
381 10:52:23.237448 V0: 0000 0000 [0001]
382 10:52:23.237507
383 10:52:23.237563 00: 0007 8000
384 10:52:23.237622
385 10:52:23.240165 01: 0000 0000
386 10:52:23.240243
387 10:52:23.240305 BP: 0C00 0209 [0000]
388 10:52:23.240362
389 10:52:23.243755 G0: 1182 0000
390 10:52:23.243831
391 10:52:23.243890 EC: 0000 0021 [4000]
392 10:52:23.243947
393 10:52:23.247309 S7: 0000 0000 [0000]
394 10:52:23.247396
395 10:52:23.247462 CC: 0000 0000 [0001]
396 10:52:23.247524
397 10:52:23.251087 T0: 0000 0040 [010F]
398 10:52:23.251172
399 10:52:23.251239 Jump to BL
400 10:52:23.251300
401 10:52:23.276498
402 10:52:23.276654
403 10:52:23.276734
404 10:52:23.284291 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:52:23.287652 ARM64: Exception handlers installed.
406 10:52:23.291400 ARM64: Testing exception
407 10:52:23.294925 ARM64: Done test exception
408 10:52:23.301894 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:52:23.312466 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:52:23.319624 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:52:23.326740 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:52:23.336915 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:52:23.343888 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:52:23.353536 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:52:23.360372 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:52:23.380123 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:52:23.382776 WDT: Last reset was cold boot
418 10:52:23.386334 SPI1(PAD0) initialized at 2873684 Hz
419 10:52:23.389746 SPI5(PAD0) initialized at 992727 Hz
420 10:52:23.393199 VBOOT: Loading verstage.
421 10:52:23.399505 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:52:23.402876 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:52:23.406215 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:52:23.409970 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:52:23.416878 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:52:23.423791 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:52:23.434639 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 10:52:23.434761
429 10:52:23.434861
430 10:52:23.444768 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:52:23.448058 ARM64: Exception handlers installed.
432 10:52:23.451121 ARM64: Testing exception
433 10:52:23.451230 ARM64: Done test exception
434 10:52:23.457817 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:52:23.461696 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:52:23.475614 Probing TPM: . done!
437 10:52:23.475718 TPM ready after 0 ms
438 10:52:23.482053 Connected to device vid:did:rid of 1ae0:0028:00
439 10:52:23.492152 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:52:23.530589 Initialized TPM device CR50 revision 0
441 10:52:23.542795 tlcl_send_startup: Startup return code is 0
442 10:52:23.542930 TPM: setup succeeded
443 10:52:23.555122 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:52:23.563379 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:52:23.574951 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:52:23.583732 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:52:23.586868 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:52:23.590138 in-header: 03 07 00 00 08 00 00 00
449 10:52:23.593882 in-data: aa e4 47 04 13 02 00 00
450 10:52:23.596916 Chrome EC: UHEPI supported
451 10:52:23.603448 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:52:23.606792 in-header: 03 ad 00 00 08 00 00 00
453 10:52:23.610741 in-data: 00 20 20 08 00 00 00 00
454 10:52:23.610844 Phase 1
455 10:52:23.613917 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:52:23.620019 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:52:23.627043 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:52:23.629884 Recovery requested (1009000e)
459 10:52:23.633937 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:52:23.642669 tlcl_extend: response is 0
461 10:52:23.651064 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:52:23.655732 tlcl_extend: response is 0
463 10:52:23.662205 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:52:23.682937 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:52:23.689600 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:52:23.689706
467 10:52:23.689800
468 10:52:23.700758 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:52:23.703599 ARM64: Exception handlers installed.
470 10:52:23.707621 ARM64: Testing exception
471 10:52:23.707726 ARM64: Done test exception
472 10:52:23.728687 pmic_efuse_setting: Set efuses in 11 msecs
473 10:52:23.732529 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:52:23.739382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:52:23.742542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:52:23.745760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:52:23.752652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:52:23.755837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:52:23.762346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:52:23.765807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:52:23.772182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:52:23.776063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:52:23.779181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:52:23.785994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:52:23.789254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:52:23.795523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:52:23.802114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:52:23.805782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:52:23.812210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:52:23.819002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:52:23.822475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:52:23.828657 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:52:23.835160 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:52:23.838654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:52:23.845640 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:52:23.852836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:52:23.857461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:52:23.863591 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:52:23.866952 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:52:23.873906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:52:23.877538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:52:23.884053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:52:23.887517 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:52:23.891173 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:52:23.898057 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:52:23.901600 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:52:23.907835 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:52:23.911331 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:52:23.918156 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:52:23.921314 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:52:23.927871 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:52:23.931955 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:52:23.935311 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:52:23.939209 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:52:23.946337 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:52:23.949138 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:52:23.952468 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:52:23.959797 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:52:23.962837 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:52:23.966284 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:52:23.969250 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:52:23.975868 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:52:23.979026 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:52:23.982837 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:52:23.992890 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:52:23.999506 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:52:24.006259 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:52:24.012318 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:52:24.022801 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:52:24.025965 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:52:24.028997 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:52:24.035714 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:52:24.042590 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 10:52:24.045499 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:52:24.052903 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 10:52:24.056132 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:52:24.065597 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 10:52:24.075103 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 10:52:24.084494 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 10:52:24.094058 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 10:52:24.103575 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 10:52:24.112950 [RTC]rtc_get_frequency_meter,154: input=12, output=789
543 10:52:24.122413 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 10:52:24.125808 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 10:52:24.133151 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 10:52:24.136435 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:52:24.139380 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 10:52:24.146074 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:52:24.149461 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:52:24.152773 ADC[4]: Raw value=905988 ID=7
551 10:52:24.152857 ADC[3]: Raw value=213652 ID=1
552 10:52:24.156373 RAM Code: 0x71
553 10:52:24.159546 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:52:24.166371 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:52:24.172768 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:52:24.179477 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:52:24.182688 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:52:24.186079 in-header: 03 07 00 00 08 00 00 00
559 10:52:24.189513 in-data: aa e4 47 04 13 02 00 00
560 10:52:24.192712 Chrome EC: UHEPI supported
561 10:52:24.199365 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:52:24.202264 in-header: 03 dd 00 00 08 00 00 00
563 10:52:24.205671 in-data: 90 20 60 08 00 00 00 00
564 10:52:24.209227 MRC: failed to locate region type 0.
565 10:52:24.215886 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:52:24.218912 DRAM-K: Running full calibration
567 10:52:24.225553 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:52:24.228549 header.status = 0x0
569 10:52:24.228654 header.version = 0x6 (expected: 0x6)
570 10:52:24.232925 header.size = 0xd00 (expected: 0xd00)
571 10:52:24.235234 header.flags = 0x0
572 10:52:24.242128 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:52:24.259112 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 10:52:24.265805 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:52:24.269703 dram_init: ddr_geometry: 2
576 10:52:24.272394 [EMI] MDL number = 2
577 10:52:24.272497 [EMI] Get MDL freq = 0
578 10:52:24.276239 dram_init: ddr_type: 0
579 10:52:24.276341 is_discrete_lpddr4: 1
580 10:52:24.279403 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:52:24.279480
582 10:52:24.279544
583 10:52:24.282388 [Bian_co] ETT version 0.0.0.1
584 10:52:24.289547 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:52:24.289631
586 10:52:24.292849 dramc_set_vcore_voltage set vcore to 650000
587 10:52:24.292924 Read voltage for 800, 4
588 10:52:24.296026 Vio18 = 0
589 10:52:24.296127 Vcore = 650000
590 10:52:24.296219 Vdram = 0
591 10:52:24.299390 Vddq = 0
592 10:52:24.299467 Vmddr = 0
593 10:52:24.302752 dram_init: config_dvfs: 1
594 10:52:24.306172 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:52:24.312731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:52:24.315711 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 10:52:24.319215 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 10:52:24.322321 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 10:52:24.325864 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 10:52:24.328909 MEM_TYPE=3, freq_sel=18
601 10:52:24.332469 sv_algorithm_assistance_LP4_1600
602 10:52:24.335741 ============ PULL DRAM RESETB DOWN ============
603 10:52:24.342542 ========== PULL DRAM RESETB DOWN end =========
604 10:52:24.345765 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:52:24.349212 ===================================
606 10:52:24.352121 LPDDR4 DRAM CONFIGURATION
607 10:52:24.356376 ===================================
608 10:52:24.356486 EX_ROW_EN[0] = 0x0
609 10:52:24.358895 EX_ROW_EN[1] = 0x0
610 10:52:24.358981 LP4Y_EN = 0x0
611 10:52:24.362751 WORK_FSP = 0x0
612 10:52:24.362855 WL = 0x2
613 10:52:24.365385 RL = 0x2
614 10:52:24.365462 BL = 0x2
615 10:52:24.369030 RPST = 0x0
616 10:52:24.369109 RD_PRE = 0x0
617 10:52:24.372296 WR_PRE = 0x1
618 10:52:24.372393 WR_PST = 0x0
619 10:52:24.375906 DBI_WR = 0x0
620 10:52:24.376004 DBI_RD = 0x0
621 10:52:24.378856 OTF = 0x1
622 10:52:24.382292 ===================================
623 10:52:24.385497 ===================================
624 10:52:24.385578 ANA top config
625 10:52:24.388680 ===================================
626 10:52:24.392360 DLL_ASYNC_EN = 0
627 10:52:24.395471 ALL_SLAVE_EN = 1
628 10:52:24.399175 NEW_RANK_MODE = 1
629 10:52:24.402146 DLL_IDLE_MODE = 1
630 10:52:24.402220 LP45_APHY_COMB_EN = 1
631 10:52:24.405984 TX_ODT_DIS = 1
632 10:52:24.408706 NEW_8X_MODE = 1
633 10:52:24.412550 ===================================
634 10:52:24.415459 ===================================
635 10:52:24.419487 data_rate = 1600
636 10:52:24.421859 CKR = 1
637 10:52:24.421943 DQ_P2S_RATIO = 8
638 10:52:24.425182 ===================================
639 10:52:24.429022 CA_P2S_RATIO = 8
640 10:52:24.432183 DQ_CA_OPEN = 0
641 10:52:24.435073 DQ_SEMI_OPEN = 0
642 10:52:24.438591 CA_SEMI_OPEN = 0
643 10:52:24.441701 CA_FULL_RATE = 0
644 10:52:24.441785 DQ_CKDIV4_EN = 1
645 10:52:24.445066 CA_CKDIV4_EN = 1
646 10:52:24.448435 CA_PREDIV_EN = 0
647 10:52:24.451711 PH8_DLY = 0
648 10:52:24.455703 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:52:24.458758 DQ_AAMCK_DIV = 4
650 10:52:24.458837 CA_AAMCK_DIV = 4
651 10:52:24.462129 CA_ADMCK_DIV = 4
652 10:52:24.464915 DQ_TRACK_CA_EN = 0
653 10:52:24.468442 CA_PICK = 800
654 10:52:24.471572 CA_MCKIO = 800
655 10:52:24.475320 MCKIO_SEMI = 0
656 10:52:24.478124 PLL_FREQ = 3068
657 10:52:24.478200 DQ_UI_PI_RATIO = 32
658 10:52:24.481683 CA_UI_PI_RATIO = 0
659 10:52:24.484762 ===================================
660 10:52:24.488441 ===================================
661 10:52:24.491768 memory_type:LPDDR4
662 10:52:24.495277 GP_NUM : 10
663 10:52:24.495352 SRAM_EN : 1
664 10:52:24.498422 MD32_EN : 0
665 10:52:24.501616 ===================================
666 10:52:24.501692 [ANA_INIT] >>>>>>>>>>>>>>
667 10:52:24.505213 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:52:24.508304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:52:24.511617 ===================================
670 10:52:24.514917 data_rate = 1600,PCW = 0X7600
671 10:52:24.518406 ===================================
672 10:52:24.522053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:52:24.528093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:52:24.534914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:52:24.538009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:52:24.541388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:52:24.545064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:52:24.548325 [ANA_INIT] flow start
679 10:52:24.548404 [ANA_INIT] PLL >>>>>>>>
680 10:52:24.551434 [ANA_INIT] PLL <<<<<<<<
681 10:52:24.554614 [ANA_INIT] MIDPI >>>>>>>>
682 10:52:24.554696 [ANA_INIT] MIDPI <<<<<<<<
683 10:52:24.558633 [ANA_INIT] DLL >>>>>>>>
684 10:52:24.561837 [ANA_INIT] flow end
685 10:52:24.564621 ============ LP4 DIFF to SE enter ============
686 10:52:24.568166 ============ LP4 DIFF to SE exit ============
687 10:52:24.571668 [ANA_INIT] <<<<<<<<<<<<<
688 10:52:24.574773 [Flow] Enable top DCM control >>>>>
689 10:52:24.578076 [Flow] Enable top DCM control <<<<<
690 10:52:24.581353 Enable DLL master slave shuffle
691 10:52:24.584352 ==============================================================
692 10:52:24.588023 Gating Mode config
693 10:52:24.594605 ==============================================================
694 10:52:24.594689 Config description:
695 10:52:24.604670 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:52:24.611437 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:52:24.614337 SELPH_MODE 0: By rank 1: By Phase
698 10:52:24.621156 ==============================================================
699 10:52:24.624663 GAT_TRACK_EN = 1
700 10:52:24.628434 RX_GATING_MODE = 2
701 10:52:24.630849 RX_GATING_TRACK_MODE = 2
702 10:52:24.634103 SELPH_MODE = 1
703 10:52:24.637715 PICG_EARLY_EN = 1
704 10:52:24.640912 VALID_LAT_VALUE = 1
705 10:52:24.644883 ==============================================================
706 10:52:24.647354 Enter into Gating configuration >>>>
707 10:52:24.650978 Exit from Gating configuration <<<<
708 10:52:24.654495 Enter into DVFS_PRE_config >>>>>
709 10:52:24.667627 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:52:24.667718 Exit from DVFS_PRE_config <<<<<
711 10:52:24.671201 Enter into PICG configuration >>>>
712 10:52:24.674062 Exit from PICG configuration <<<<
713 10:52:24.677104 [RX_INPUT] configuration >>>>>
714 10:52:24.680665 [RX_INPUT] configuration <<<<<
715 10:52:24.687930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:52:24.691158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:52:24.697838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:52:24.705084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:52:24.708939 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:52:24.716023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:52:24.720072 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:52:24.723008 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:52:24.730954 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:52:24.733981 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:52:24.737515 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:52:24.741289 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:52:24.745011 ===================================
728 10:52:24.748256 LPDDR4 DRAM CONFIGURATION
729 10:52:24.751536 ===================================
730 10:52:24.751625 EX_ROW_EN[0] = 0x0
731 10:52:24.754825 EX_ROW_EN[1] = 0x0
732 10:52:24.754913 LP4Y_EN = 0x0
733 10:52:24.758765 WORK_FSP = 0x0
734 10:52:24.758852 WL = 0x2
735 10:52:24.762337 RL = 0x2
736 10:52:24.762424 BL = 0x2
737 10:52:24.765996 RPST = 0x0
738 10:52:24.766083 RD_PRE = 0x0
739 10:52:24.769992 WR_PRE = 0x1
740 10:52:24.770079 WR_PST = 0x0
741 10:52:24.770166 DBI_WR = 0x0
742 10:52:24.773510 DBI_RD = 0x0
743 10:52:24.773597 OTF = 0x1
744 10:52:24.777010 ===================================
745 10:52:24.780661 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:52:24.788666 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:52:24.792270 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:52:24.795228 ===================================
749 10:52:24.795316 LPDDR4 DRAM CONFIGURATION
750 10:52:24.799549 ===================================
751 10:52:24.802298 EX_ROW_EN[0] = 0x10
752 10:52:24.802385 EX_ROW_EN[1] = 0x0
753 10:52:24.806153 LP4Y_EN = 0x0
754 10:52:24.806239 WORK_FSP = 0x0
755 10:52:24.810163 WL = 0x2
756 10:52:24.810250 RL = 0x2
757 10:52:24.813444 BL = 0x2
758 10:52:24.813530 RPST = 0x0
759 10:52:24.817663 RD_PRE = 0x0
760 10:52:24.817750 WR_PRE = 0x1
761 10:52:24.821088 WR_PST = 0x0
762 10:52:24.821175 DBI_WR = 0x0
763 10:52:24.824721 DBI_RD = 0x0
764 10:52:24.824807 OTF = 0x1
765 10:52:24.827772 ===================================
766 10:52:24.834849 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:52:24.838712 nWR fixed to 40
768 10:52:24.838792 [ModeRegInit_LP4] CH0 RK0
769 10:52:24.842811 [ModeRegInit_LP4] CH0 RK1
770 10:52:24.846307 [ModeRegInit_LP4] CH1 RK0
771 10:52:24.846384 [ModeRegInit_LP4] CH1 RK1
772 10:52:24.849491 match AC timing 13
773 10:52:24.853053 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:52:24.856418 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:52:24.863371 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:52:24.866775 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:52:24.870384 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:52:24.873732 [EMI DOE] emi_dcm 0
779 10:52:24.876668 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:52:24.876742 ==
781 10:52:24.879752 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:52:24.883273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:52:24.883348 ==
784 10:52:24.889822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:52:24.896155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:52:24.905117 [CA 0] Center 37 (7~68) winsize 62
787 10:52:24.908534 [CA 1] Center 37 (6~68) winsize 63
788 10:52:24.911892 [CA 2] Center 34 (4~65) winsize 62
789 10:52:24.914929 [CA 3] Center 34 (4~65) winsize 62
790 10:52:24.918676 [CA 4] Center 33 (3~64) winsize 62
791 10:52:24.922171 [CA 5] Center 33 (3~64) winsize 62
792 10:52:24.922284
793 10:52:24.925415 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 10:52:24.925524
795 10:52:24.929176 [CATrainingPosCal] consider 1 rank data
796 10:52:24.932486 u2DelayCellTimex100 = 270/100 ps
797 10:52:24.935660 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 10:52:24.938674 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 10:52:24.941942 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 10:52:24.948910 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 10:52:24.952106 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 10:52:24.955259 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 10:52:24.955363
804 10:52:24.959159 CA PerBit enable=1, Macro0, CA PI delay=33
805 10:52:24.959271
806 10:52:24.962068 [CBTSetCACLKResult] CA Dly = 33
807 10:52:24.962170 CS Dly: 6 (0~37)
808 10:52:24.962269 ==
809 10:52:24.965348 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:52:24.972291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:52:24.972396 ==
812 10:52:24.975672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:52:24.982278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:52:24.991513 [CA 0] Center 37 (6~68) winsize 63
815 10:52:24.995201 [CA 1] Center 37 (7~68) winsize 62
816 10:52:24.997943 [CA 2] Center 34 (4~65) winsize 62
817 10:52:25.001090 [CA 3] Center 34 (4~65) winsize 62
818 10:52:25.004735 [CA 4] Center 33 (3~64) winsize 62
819 10:52:25.007660 [CA 5] Center 33 (3~64) winsize 62
820 10:52:25.007767
821 10:52:25.011677 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:52:25.011785
823 10:52:25.014355 [CATrainingPosCal] consider 2 rank data
824 10:52:25.018070 u2DelayCellTimex100 = 270/100 ps
825 10:52:25.021306 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 10:52:25.027785 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 10:52:25.031292 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 10:52:25.035097 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 10:52:25.038948 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 10:52:25.042674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 10:52:25.042777
832 10:52:25.046111 CA PerBit enable=1, Macro0, CA PI delay=33
833 10:52:25.046228
834 10:52:25.046323 [CBTSetCACLKResult] CA Dly = 33
835 10:52:25.049674 CS Dly: 6 (0~38)
836 10:52:25.049779
837 10:52:25.054069 ----->DramcWriteLeveling(PI) begin...
838 10:52:25.054157 ==
839 10:52:25.057026 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:52:25.060942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:52:25.061027 ==
842 10:52:25.064146 Write leveling (Byte 0): 32 => 32
843 10:52:25.068399 Write leveling (Byte 1): 29 => 29
844 10:52:25.071190 DramcWriteLeveling(PI) end<-----
845 10:52:25.071290
846 10:52:25.071381 ==
847 10:52:25.073951 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:52:25.077523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:52:25.077596 ==
850 10:52:25.080934 [Gating] SW mode calibration
851 10:52:25.087206 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:52:25.093823 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:52:25.097090 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:52:25.100467 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
855 10:52:25.107337 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 10:52:25.110476 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 10:52:25.113472 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:52:25.120602 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:52:25.123644 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:52:25.126899 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:52:25.133713 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:52:25.137085 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:52:25.140050 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:52:25.147036 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:52:25.150175 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:52:25.153422 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:52:25.160434 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:52:25.163734 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:52:25.167140 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:52:25.173688 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 10:52:25.176397 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 10:52:25.179833 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 10:52:25.183747 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:52:25.190005 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:52:25.192970 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:52:25.196511 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:52:25.203114 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:52:25.206293 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:52:25.210166 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 10:52:25.216414 0 9 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
881 10:52:25.220128 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:52:25.222944 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:52:25.230074 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:52:25.233019 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:52:25.236382 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:52:25.243356 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
887 10:52:25.246731 0 10 8 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
888 10:52:25.249471 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 10:52:25.256095 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:52:25.259813 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:52:25.263048 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:52:25.269415 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:52:25.272656 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:52:25.276448 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 10:52:25.283410 0 11 8 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
896 10:52:25.286100 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
897 10:52:25.289269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:52:25.296722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:52:25.299403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:52:25.302515 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:52:25.309488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:52:25.312445 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 10:52:25.316340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
904 10:52:25.322920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 10:52:25.325868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:52:25.329189 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:52:25.336268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:52:25.339395 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:52:25.342482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:52:25.345917 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:52:25.352213 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:52:25.355895 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:52:25.358869 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:52:25.366056 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:52:25.369036 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:52:25.372292 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:52:25.378800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:52:25.382571 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 10:52:25.385629 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 10:52:25.392351 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 10:52:25.395665 Total UI for P1: 0, mck2ui 16
922 10:52:25.399008 best dqsien dly found for B0: ( 0, 14, 6)
923 10:52:25.402781 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 10:52:25.405391 Total UI for P1: 0, mck2ui 16
925 10:52:25.408804 best dqsien dly found for B1: ( 0, 14, 12)
926 10:52:25.412830 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 10:52:25.415746 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 10:52:25.415825
929 10:52:25.419146 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 10:52:25.422914 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 10:52:25.426229 [Gating] SW calibration Done
932 10:52:25.426315 ==
933 10:52:25.429961 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:52:25.432675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:52:25.432777 ==
936 10:52:25.435978 RX Vref Scan: 0
937 10:52:25.436063
938 10:52:25.439771 RX Vref 0 -> 0, step: 1
939 10:52:25.439856
940 10:52:25.439922 RX Delay -130 -> 252, step: 16
941 10:52:25.446556 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 10:52:25.450230 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 10:52:25.453924 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
944 10:52:25.457099 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
945 10:52:25.461178 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 10:52:25.464416 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 10:52:25.467835 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 10:52:25.471381 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 10:52:25.475367 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 10:52:25.482147 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 10:52:25.485916 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 10:52:25.489266 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 10:52:25.492763 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
954 10:52:25.496483 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
955 10:52:25.500046 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 10:52:25.506975 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
957 10:52:25.507061 ==
958 10:52:25.510122 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:52:25.512897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:52:25.512983 ==
961 10:52:25.513079 DQS Delay:
962 10:52:25.516038 DQS0 = 0, DQS1 = 0
963 10:52:25.516122 DQM Delay:
964 10:52:25.519807 DQM0 = 84, DQM1 = 73
965 10:52:25.519892 DQ Delay:
966 10:52:25.522969 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
967 10:52:25.526217 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
968 10:52:25.530000 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
969 10:52:25.532773 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
970 10:52:25.532858
971 10:52:25.532923
972 10:52:25.532985 ==
973 10:52:25.535983 Dram Type= 6, Freq= 0, CH_0, rank 0
974 10:52:25.539815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 10:52:25.539900 ==
976 10:52:25.542834
977 10:52:25.542918
978 10:52:25.542984 TX Vref Scan disable
979 10:52:25.546321 == TX Byte 0 ==
980 10:52:25.549419 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 10:52:25.553078 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 10:52:25.556483 == TX Byte 1 ==
983 10:52:25.560062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 10:52:25.564163 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 10:52:25.564249 ==
986 10:52:25.567805 Dram Type= 6, Freq= 0, CH_0, rank 0
987 10:52:25.570997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 10:52:25.571083 ==
989 10:52:25.585032 TX Vref=22, minBit 4, minWin=27, winSum=442
990 10:52:25.588329 TX Vref=24, minBit 5, minWin=27, winSum=443
991 10:52:25.591576 TX Vref=26, minBit 8, minWin=27, winSum=446
992 10:52:25.594513 TX Vref=28, minBit 8, minWin=27, winSum=450
993 10:52:25.598146 TX Vref=30, minBit 8, minWin=27, winSum=447
994 10:52:25.604585 TX Vref=32, minBit 9, minWin=26, winSum=441
995 10:52:25.608382 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
996 10:52:25.608467
997 10:52:25.611422 Final TX Range 1 Vref 28
998 10:52:25.611508
999 10:52:25.611576 ==
1000 10:52:25.614477 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 10:52:25.618053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 10:52:25.618145 ==
1003 10:52:25.621037
1004 10:52:25.621122
1005 10:52:25.621189 TX Vref Scan disable
1006 10:52:25.624872 == TX Byte 0 ==
1007 10:52:25.628760 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 10:52:25.634856 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 10:52:25.634944 == TX Byte 1 ==
1010 10:52:25.637935 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 10:52:25.644483 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 10:52:25.644600
1013 10:52:25.644706 [DATLAT]
1014 10:52:25.644767 Freq=800, CH0 RK0
1015 10:52:25.644831
1016 10:52:25.648061 DATLAT Default: 0xa
1017 10:52:25.648162 0, 0xFFFF, sum = 0
1018 10:52:25.651152 1, 0xFFFF, sum = 0
1019 10:52:25.654295 2, 0xFFFF, sum = 0
1020 10:52:25.654382 3, 0xFFFF, sum = 0
1021 10:52:25.657593 4, 0xFFFF, sum = 0
1022 10:52:25.657680 5, 0xFFFF, sum = 0
1023 10:52:25.661708 6, 0xFFFF, sum = 0
1024 10:52:25.661796 7, 0xFFFF, sum = 0
1025 10:52:25.664479 8, 0xFFFF, sum = 0
1026 10:52:25.664596 9, 0x0, sum = 1
1027 10:52:25.667782 10, 0x0, sum = 2
1028 10:52:25.667885 11, 0x0, sum = 3
1029 10:52:25.667968 12, 0x0, sum = 4
1030 10:52:25.671527 best_step = 10
1031 10:52:25.671626
1032 10:52:25.671693 ==
1033 10:52:25.674209 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 10:52:25.677349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 10:52:25.677439 ==
1036 10:52:25.680833 RX Vref Scan: 1
1037 10:52:25.680921
1038 10:52:25.684176 Set Vref Range= 32 -> 127
1039 10:52:25.684274
1040 10:52:25.684366 RX Vref 32 -> 127, step: 1
1041 10:52:25.684455
1042 10:52:25.687294 RX Delay -95 -> 252, step: 8
1043 10:52:25.687396
1044 10:52:25.691062 Set Vref, RX VrefLevel [Byte0]: 32
1045 10:52:25.694271 [Byte1]: 32
1046 10:52:25.694348
1047 10:52:25.697820 Set Vref, RX VrefLevel [Byte0]: 33
1048 10:52:25.700968 [Byte1]: 33
1049 10:52:25.704779
1050 10:52:25.704849 Set Vref, RX VrefLevel [Byte0]: 34
1051 10:52:25.708417 [Byte1]: 34
1052 10:52:25.712792
1053 10:52:25.712873 Set Vref, RX VrefLevel [Byte0]: 35
1054 10:52:25.716144 [Byte1]: 35
1055 10:52:25.720709
1056 10:52:25.720784 Set Vref, RX VrefLevel [Byte0]: 36
1057 10:52:25.724073 [Byte1]: 36
1058 10:52:25.727902
1059 10:52:25.727976 Set Vref, RX VrefLevel [Byte0]: 37
1060 10:52:25.731035 [Byte1]: 37
1061 10:52:25.735321
1062 10:52:25.735400 Set Vref, RX VrefLevel [Byte0]: 38
1063 10:52:25.738670 [Byte1]: 38
1064 10:52:25.742944
1065 10:52:25.743033 Set Vref, RX VrefLevel [Byte0]: 39
1066 10:52:25.746193 [Byte1]: 39
1067 10:52:25.750326
1068 10:52:25.750409 Set Vref, RX VrefLevel [Byte0]: 40
1069 10:52:25.753662 [Byte1]: 40
1070 10:52:25.758173
1071 10:52:25.758290 Set Vref, RX VrefLevel [Byte0]: 41
1072 10:52:25.761442 [Byte1]: 41
1073 10:52:25.766070
1074 10:52:25.766186 Set Vref, RX VrefLevel [Byte0]: 42
1075 10:52:25.769164 [Byte1]: 42
1076 10:52:25.773289
1077 10:52:25.773378 Set Vref, RX VrefLevel [Byte0]: 43
1078 10:52:25.776586 [Byte1]: 43
1079 10:52:25.781254
1080 10:52:25.781332 Set Vref, RX VrefLevel [Byte0]: 44
1081 10:52:25.787201 [Byte1]: 44
1082 10:52:25.787281
1083 10:52:25.790522 Set Vref, RX VrefLevel [Byte0]: 45
1084 10:52:25.794230 [Byte1]: 45
1085 10:52:25.794307
1086 10:52:25.797727 Set Vref, RX VrefLevel [Byte0]: 46
1087 10:52:25.801060 [Byte1]: 46
1088 10:52:25.801136
1089 10:52:25.803853 Set Vref, RX VrefLevel [Byte0]: 47
1090 10:52:25.807138 [Byte1]: 47
1091 10:52:25.811365
1092 10:52:25.811439 Set Vref, RX VrefLevel [Byte0]: 48
1093 10:52:25.815175 [Byte1]: 48
1094 10:52:25.818841
1095 10:52:25.818925 Set Vref, RX VrefLevel [Byte0]: 49
1096 10:52:25.822107 [Byte1]: 49
1097 10:52:25.826512
1098 10:52:25.826595 Set Vref, RX VrefLevel [Byte0]: 50
1099 10:52:25.830155 [Byte1]: 50
1100 10:52:25.834542
1101 10:52:25.834628 Set Vref, RX VrefLevel [Byte0]: 51
1102 10:52:25.837338 [Byte1]: 51
1103 10:52:25.841907
1104 10:52:25.841987 Set Vref, RX VrefLevel [Byte0]: 52
1105 10:52:25.845175 [Byte1]: 52
1106 10:52:25.849343
1107 10:52:25.849421 Set Vref, RX VrefLevel [Byte0]: 53
1108 10:52:25.853229 [Byte1]: 53
1109 10:52:25.856927
1110 10:52:25.857019 Set Vref, RX VrefLevel [Byte0]: 54
1111 10:52:25.860288 [Byte1]: 54
1112 10:52:25.864929
1113 10:52:25.865006 Set Vref, RX VrefLevel [Byte0]: 55
1114 10:52:25.867666 [Byte1]: 55
1115 10:52:25.872062
1116 10:52:25.872145 Set Vref, RX VrefLevel [Byte0]: 56
1117 10:52:25.875161 [Byte1]: 56
1118 10:52:25.880062
1119 10:52:25.880145 Set Vref, RX VrefLevel [Byte0]: 57
1120 10:52:25.882800 [Byte1]: 57
1121 10:52:25.887160
1122 10:52:25.887299 Set Vref, RX VrefLevel [Byte0]: 58
1123 10:52:25.890516 [Byte1]: 58
1124 10:52:25.894835
1125 10:52:25.894971 Set Vref, RX VrefLevel [Byte0]: 59
1126 10:52:25.898081 [Byte1]: 59
1127 10:52:25.902714
1128 10:52:25.902847 Set Vref, RX VrefLevel [Byte0]: 60
1129 10:52:25.905899 [Byte1]: 60
1130 10:52:25.910235
1131 10:52:25.910369 Set Vref, RX VrefLevel [Byte0]: 61
1132 10:52:25.913580 [Byte1]: 61
1133 10:52:25.917940
1134 10:52:25.918072 Set Vref, RX VrefLevel [Byte0]: 62
1135 10:52:25.920931 [Byte1]: 62
1136 10:52:25.925309
1137 10:52:25.925445 Set Vref, RX VrefLevel [Byte0]: 63
1138 10:52:25.928467 [Byte1]: 63
1139 10:52:25.932885
1140 10:52:25.933024 Set Vref, RX VrefLevel [Byte0]: 64
1141 10:52:25.936253 [Byte1]: 64
1142 10:52:25.940772
1143 10:52:25.940918 Set Vref, RX VrefLevel [Byte0]: 65
1144 10:52:25.943988 [Byte1]: 65
1145 10:52:25.948062
1146 10:52:25.948194 Set Vref, RX VrefLevel [Byte0]: 66
1147 10:52:25.951918 [Byte1]: 66
1148 10:52:25.955465
1149 10:52:25.955607 Set Vref, RX VrefLevel [Byte0]: 67
1150 10:52:25.959183 [Byte1]: 67
1151 10:52:25.963562
1152 10:52:25.963699 Set Vref, RX VrefLevel [Byte0]: 68
1153 10:52:25.967646 [Byte1]: 68
1154 10:52:25.971370
1155 10:52:25.971523 Set Vref, RX VrefLevel [Byte0]: 69
1156 10:52:25.974438 [Byte1]: 69
1157 10:52:25.978475
1158 10:52:25.978618 Set Vref, RX VrefLevel [Byte0]: 70
1159 10:52:25.981832 [Byte1]: 70
1160 10:52:25.985994
1161 10:52:25.986135 Set Vref, RX VrefLevel [Byte0]: 71
1162 10:52:25.989158 [Byte1]: 71
1163 10:52:25.993566
1164 10:52:25.993715 Set Vref, RX VrefLevel [Byte0]: 72
1165 10:52:25.996879 [Byte1]: 72
1166 10:52:26.001358
1167 10:52:26.001496 Set Vref, RX VrefLevel [Byte0]: 73
1168 10:52:26.004683 [Byte1]: 73
1169 10:52:26.008761
1170 10:52:26.008896 Set Vref, RX VrefLevel [Byte0]: 74
1171 10:52:26.012114 [Byte1]: 74
1172 10:52:26.016296
1173 10:52:26.016437 Set Vref, RX VrefLevel [Byte0]: 75
1174 10:52:26.019677 [Byte1]: 75
1175 10:52:26.024722
1176 10:52:26.024878 Set Vref, RX VrefLevel [Byte0]: 76
1177 10:52:26.027872 [Byte1]: 76
1178 10:52:26.031737
1179 10:52:26.031877 Set Vref, RX VrefLevel [Byte0]: 77
1180 10:52:26.034890 [Byte1]: 77
1181 10:52:26.039737
1182 10:52:26.039881 Set Vref, RX VrefLevel [Byte0]: 78
1183 10:52:26.045898 [Byte1]: 78
1184 10:52:26.046046
1185 10:52:26.049688 Set Vref, RX VrefLevel [Byte0]: 79
1186 10:52:26.053339 [Byte1]: 79
1187 10:52:26.053491
1188 10:52:26.056966 Set Vref, RX VrefLevel [Byte0]: 80
1189 10:52:26.060391 [Byte1]: 80
1190 10:52:26.060558
1191 10:52:26.063647 Set Vref, RX VrefLevel [Byte0]: 81
1192 10:52:26.067422 [Byte1]: 81
1193 10:52:26.067571
1194 10:52:26.071509 Set Vref, RX VrefLevel [Byte0]: 82
1195 10:52:26.074725 [Byte1]: 82
1196 10:52:26.074858
1197 10:52:26.078955 Set Vref, RX VrefLevel [Byte0]: 83
1198 10:52:26.082338 [Byte1]: 83
1199 10:52:26.082482
1200 10:52:26.086102 Final RX Vref Byte 0 = 61 to rank0
1201 10:52:26.089617 Final RX Vref Byte 1 = 57 to rank0
1202 10:52:26.093385 Final RX Vref Byte 0 = 61 to rank1
1203 10:52:26.097355 Final RX Vref Byte 1 = 57 to rank1==
1204 10:52:26.100528 Dram Type= 6, Freq= 0, CH_0, rank 0
1205 10:52:26.103966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 10:52:26.104104 ==
1207 10:52:26.104232 DQS Delay:
1208 10:52:26.108169 DQS0 = 0, DQS1 = 0
1209 10:52:26.108348 DQM Delay:
1210 10:52:26.108418 DQM0 = 87, DQM1 = 75
1211 10:52:26.111456 DQ Delay:
1212 10:52:26.115387 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1213 10:52:26.115501 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1214 10:52:26.118709 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1215 10:52:26.123343 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1216 10:52:26.123430
1217 10:52:26.123497
1218 10:52:26.129870 [DQSOSCAuto] RK0, (LSB)MR18= 0x4324, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1219 10:52:26.133416 CH0 RK0: MR19=606, MR18=4324
1220 10:52:26.140301 CH0_RK0: MR19=0x606, MR18=0x4324, DQSOSC=393, MR23=63, INC=95, DEC=63
1221 10:52:26.140411
1222 10:52:26.143887 ----->DramcWriteLeveling(PI) begin...
1223 10:52:26.143977 ==
1224 10:52:26.147682 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 10:52:26.151270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 10:52:26.151361 ==
1227 10:52:26.195394 Write leveling (Byte 0): 31 => 31
1228 10:52:26.195584 Write leveling (Byte 1): 30 => 30
1229 10:52:26.196099 DramcWriteLeveling(PI) end<-----
1230 10:52:26.196189
1231 10:52:26.196280 ==
1232 10:52:26.196574 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 10:52:26.196643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 10:52:26.196705 ==
1235 10:52:26.197170 [Gating] SW mode calibration
1236 10:52:26.197466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1237 10:52:26.198135 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1238 10:52:26.198466 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 10:52:26.198581 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1240 10:52:26.198650 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 10:52:26.221289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:52:26.221680 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:52:26.221789 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:52:26.221867 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:52:26.221932 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:52:26.224842 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 10:52:26.228280 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:52:26.231696 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 10:52:26.234918 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 10:52:26.241826 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:52:26.245566 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:52:26.248090 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:52:26.255134 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:52:26.258358 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 10:52:26.261430 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1256 10:52:26.267795 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1257 10:52:26.271322 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1258 10:52:26.274723 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 10:52:26.281242 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 10:52:26.284582 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 10:52:26.288042 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 10:52:26.294780 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 10:52:26.297732 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 10:52:26.301378 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1265 10:52:26.307711 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 10:52:26.311127 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 10:52:26.314842 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 10:52:26.320938 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 10:52:26.324113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 10:52:26.327974 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 10:52:26.334143 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1272 10:52:26.337770 0 10 8 | B1->B0 | 3232 2929 | 0 0 | (0 1) (1 1)
1273 10:52:26.340483 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1274 10:52:26.347142 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 10:52:26.350648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 10:52:26.353847 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 10:52:26.360413 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 10:52:26.364147 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 10:52:26.367178 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1280 10:52:26.374004 0 11 8 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
1281 10:52:26.377257 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
1282 10:52:26.380579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 10:52:26.386906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 10:52:26.390087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 10:52:26.394013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 10:52:26.400043 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 10:52:26.404321 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 10:52:26.406759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1289 10:52:26.413697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1290 10:52:26.416744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 10:52:26.420587 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 10:52:26.426855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 10:52:26.430082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 10:52:26.433813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 10:52:26.440152 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 10:52:26.443503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 10:52:26.446455 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 10:52:26.453325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 10:52:26.456391 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 10:52:26.460269 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 10:52:26.466741 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 10:52:26.469882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 10:52:26.473290 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1304 10:52:26.476930 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1305 10:52:26.479878 Total UI for P1: 0, mck2ui 16
1306 10:52:26.483275 best dqsien dly found for B0: ( 0, 14, 6)
1307 10:52:26.486618 Total UI for P1: 0, mck2ui 16
1308 10:52:26.489590 best dqsien dly found for B1: ( 0, 14, 6)
1309 10:52:26.493289 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1310 10:52:26.499692 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1311 10:52:26.499772
1312 10:52:26.503536 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1313 10:52:26.506228 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1314 10:52:26.511016 [Gating] SW calibration Done
1315 10:52:26.511089 ==
1316 10:52:26.512890 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 10:52:26.516828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 10:52:26.516914 ==
1319 10:52:26.516978 RX Vref Scan: 0
1320 10:52:26.517038
1321 10:52:26.519700 RX Vref 0 -> 0, step: 1
1322 10:52:26.519769
1323 10:52:26.523097 RX Delay -130 -> 252, step: 16
1324 10:52:26.526653 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1325 10:52:26.529438 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1326 10:52:26.536397 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1327 10:52:26.540400 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1328 10:52:26.543259 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1329 10:52:26.546302 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1330 10:52:26.549490 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1331 10:52:26.556048 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1332 10:52:26.559482 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1333 10:52:26.562574 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1334 10:52:26.565806 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1335 10:52:26.569263 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1336 10:52:26.575949 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1337 10:52:26.579012 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1338 10:52:26.582596 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1339 10:52:26.586240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1340 10:52:26.586358 ==
1341 10:52:26.588834 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 10:52:26.595583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 10:52:26.595699 ==
1344 10:52:26.595770 DQS Delay:
1345 10:52:26.598914 DQS0 = 0, DQS1 = 0
1346 10:52:26.598993 DQM Delay:
1347 10:52:26.602624 DQM0 = 85, DQM1 = 78
1348 10:52:26.602710 DQ Delay:
1349 10:52:26.605282 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1350 10:52:26.608834 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1351 10:52:26.612295 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1352 10:52:26.615835 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1353 10:52:26.615981
1354 10:52:26.616077
1355 10:52:26.616165 ==
1356 10:52:26.618570 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 10:52:26.622263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 10:52:26.622357 ==
1359 10:52:26.622422
1360 10:52:26.622480
1361 10:52:26.624931 TX Vref Scan disable
1362 10:52:26.628701 == TX Byte 0 ==
1363 10:52:26.631649 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1364 10:52:26.635111 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1365 10:52:26.638407 == TX Byte 1 ==
1366 10:52:26.641886 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1367 10:52:26.645223 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1368 10:52:26.645324 ==
1369 10:52:26.648688 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 10:52:26.654953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 10:52:26.655146 ==
1372 10:52:26.666809 TX Vref=22, minBit 8, minWin=27, winSum=443
1373 10:52:26.669957 TX Vref=24, minBit 9, minWin=27, winSum=447
1374 10:52:26.673691 TX Vref=26, minBit 9, minWin=27, winSum=447
1375 10:52:26.676353 TX Vref=28, minBit 0, minWin=28, winSum=451
1376 10:52:26.680629 TX Vref=30, minBit 9, minWin=27, winSum=448
1377 10:52:26.683162 TX Vref=32, minBit 9, minWin=27, winSum=447
1378 10:52:26.689983 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
1379 10:52:26.690061
1380 10:52:26.693983 Final TX Range 1 Vref 28
1381 10:52:26.694107
1382 10:52:26.694189 ==
1383 10:52:26.697690 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 10:52:26.701144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 10:52:26.701216 ==
1386 10:52:26.701277
1387 10:52:26.701337
1388 10:52:26.704454 TX Vref Scan disable
1389 10:52:26.707947 == TX Byte 0 ==
1390 10:52:26.711663 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1391 10:52:26.715482 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1392 10:52:26.715572 == TX Byte 1 ==
1393 10:52:26.719100 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1394 10:52:26.726079 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1395 10:52:26.726210
1396 10:52:26.726279 [DATLAT]
1397 10:52:26.726340 Freq=800, CH0 RK1
1398 10:52:26.726398
1399 10:52:26.729658 DATLAT Default: 0xa
1400 10:52:26.729758 0, 0xFFFF, sum = 0
1401 10:52:26.733821 1, 0xFFFF, sum = 0
1402 10:52:26.733911 2, 0xFFFF, sum = 0
1403 10:52:26.737594 3, 0xFFFF, sum = 0
1404 10:52:26.737677 4, 0xFFFF, sum = 0
1405 10:52:26.741058 5, 0xFFFF, sum = 0
1406 10:52:26.741142 6, 0xFFFF, sum = 0
1407 10:52:26.744743 7, 0xFFFF, sum = 0
1408 10:52:26.744835 8, 0xFFFF, sum = 0
1409 10:52:26.747750 9, 0x0, sum = 1
1410 10:52:26.747842 10, 0x0, sum = 2
1411 10:52:26.751620 11, 0x0, sum = 3
1412 10:52:26.751740 12, 0x0, sum = 4
1413 10:52:26.751849 best_step = 10
1414 10:52:26.751915
1415 10:52:26.751977 ==
1416 10:52:26.755284 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 10:52:26.758400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 10:52:26.762118 ==
1419 10:52:26.762260 RX Vref Scan: 0
1420 10:52:26.762332
1421 10:52:26.765962 RX Vref 0 -> 0, step: 1
1422 10:52:26.766065
1423 10:52:26.766169 RX Delay -111 -> 252, step: 8
1424 10:52:26.773638 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1425 10:52:26.777245 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1426 10:52:26.780637 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1427 10:52:26.784643 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1428 10:52:26.788361 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1429 10:52:26.791863 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1430 10:52:26.795246 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1431 10:52:26.799773 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1432 10:52:26.802809 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1433 10:52:26.806789 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1434 10:52:26.814132 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1435 10:52:26.817453 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1436 10:52:26.820729 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1437 10:52:26.824297 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1438 10:52:26.828613 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1439 10:52:26.832145 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1440 10:52:26.832259 ==
1441 10:52:26.835423 Dram Type= 6, Freq= 0, CH_0, rank 1
1442 10:52:26.838649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 10:52:26.838745 ==
1444 10:52:26.842388 DQS Delay:
1445 10:52:26.842521 DQS0 = 0, DQS1 = 0
1446 10:52:26.842634 DQM Delay:
1447 10:52:26.845712 DQM0 = 85, DQM1 = 76
1448 10:52:26.845806 DQ Delay:
1449 10:52:26.849813 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1450 10:52:26.853606 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1451 10:52:26.856706 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1452 10:52:26.860369 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1453 10:52:26.860484
1454 10:52:26.860586
1455 10:52:26.868076 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1456 10:52:26.871149 CH0 RK1: MR19=606, MR18=3B02
1457 10:52:26.878554 CH0_RK1: MR19=0x606, MR18=0x3B02, DQSOSC=394, MR23=63, INC=95, DEC=63
1458 10:52:26.878642 [RxdqsGatingPostProcess] freq 800
1459 10:52:26.885509 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1460 10:52:26.889858 Pre-setting of DQS Precalculation
1461 10:52:26.892801 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1462 10:52:26.892891 ==
1463 10:52:26.897100 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 10:52:26.900530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 10:52:26.900625 ==
1466 10:52:26.907990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 10:52:26.911074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 10:52:26.921883 [CA 0] Center 36 (6~67) winsize 62
1469 10:52:26.925515 [CA 1] Center 36 (6~67) winsize 62
1470 10:52:26.929555 [CA 2] Center 34 (4~65) winsize 62
1471 10:52:26.932811 [CA 3] Center 34 (3~65) winsize 63
1472 10:52:26.936838 [CA 4] Center 34 (4~65) winsize 62
1473 10:52:26.940480 [CA 5] Center 34 (3~65) winsize 63
1474 10:52:26.940578
1475 10:52:26.943895 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1476 10:52:26.943969
1477 10:52:26.947714 [CATrainingPosCal] consider 1 rank data
1478 10:52:26.947788 u2DelayCellTimex100 = 270/100 ps
1479 10:52:26.951259 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 10:52:26.957792 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 10:52:26.961661 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 10:52:26.965540 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 10:52:26.968754 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 10:52:26.972498 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 10:52:26.972601
1486 10:52:26.976068 CA PerBit enable=1, Macro0, CA PI delay=34
1487 10:52:26.976149
1488 10:52:26.976211 [CBTSetCACLKResult] CA Dly = 34
1489 10:52:26.979573 CS Dly: 5 (0~36)
1490 10:52:26.979652 ==
1491 10:52:26.983283 Dram Type= 6, Freq= 0, CH_1, rank 1
1492 10:52:26.986124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 10:52:26.986197 ==
1494 10:52:26.994179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1495 10:52:26.997007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1496 10:52:27.008134 [CA 0] Center 36 (6~67) winsize 62
1497 10:52:27.011016 [CA 1] Center 36 (6~67) winsize 62
1498 10:52:27.014291 [CA 2] Center 34 (4~65) winsize 62
1499 10:52:27.017580 [CA 3] Center 34 (4~65) winsize 62
1500 10:52:27.020945 [CA 4] Center 34 (4~65) winsize 62
1501 10:52:27.024431 [CA 5] Center 34 (3~65) winsize 63
1502 10:52:27.024528
1503 10:52:27.027696 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1504 10:52:27.027770
1505 10:52:27.030504 [CATrainingPosCal] consider 2 rank data
1506 10:52:27.034377 u2DelayCellTimex100 = 270/100 ps
1507 10:52:27.037331 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1508 10:52:27.044269 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1509 10:52:27.047386 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 10:52:27.050451 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1511 10:52:27.054799 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1512 10:52:27.057357 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1513 10:52:27.057437
1514 10:52:27.061245 CA PerBit enable=1, Macro0, CA PI delay=34
1515 10:52:27.061324
1516 10:52:27.064054 [CBTSetCACLKResult] CA Dly = 34
1517 10:52:27.064135 CS Dly: 6 (0~38)
1518 10:52:27.067155
1519 10:52:27.070548 ----->DramcWriteLeveling(PI) begin...
1520 10:52:27.070632 ==
1521 10:52:27.073721 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 10:52:27.077317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 10:52:27.077400 ==
1524 10:52:27.080262 Write leveling (Byte 0): 26 => 26
1525 10:52:27.084220 Write leveling (Byte 1): 26 => 26
1526 10:52:27.087016 DramcWriteLeveling(PI) end<-----
1527 10:52:27.087090
1528 10:52:27.087152 ==
1529 10:52:27.090305 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 10:52:27.093993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 10:52:27.094068 ==
1532 10:52:27.097186 [Gating] SW mode calibration
1533 10:52:27.103659 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1534 10:52:27.110620 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1535 10:52:27.113820 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1536 10:52:27.116830 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 10:52:27.123427 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1538 10:52:27.127067 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 10:52:27.130022 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:52:27.137362 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:52:27.140188 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:52:27.143906 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:52:27.150146 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:52:27.153681 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:52:27.157585 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:52:27.160951 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 10:52:27.168474 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:52:27.171685 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:52:27.175372 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:52:27.179031 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:52:27.182447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:52:27.189373 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1553 10:52:27.193100 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1554 10:52:27.196586 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 10:52:27.200702 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 10:52:27.207507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 10:52:27.211373 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 10:52:27.215272 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 10:52:27.218968 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 10:52:27.222452 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 10:52:27.229902 0 9 8 | B1->B0 | 2c2c 3434 | 1 0 | (1 1) (0 0)
1562 10:52:27.232691 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 10:52:27.236756 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 10:52:27.240669 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 10:52:27.244165 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 10:52:27.251489 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 10:52:27.255225 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 10:52:27.258688 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1569 10:52:27.262412 0 10 8 | B1->B0 | 2c2c 2626 | 0 0 | (1 1) (0 0)
1570 10:52:27.266054 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 10:52:27.273026 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 10:52:27.277180 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 10:52:27.280955 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 10:52:27.284083 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 10:52:27.288022 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 10:52:27.295173 0 11 4 | B1->B0 | 2323 2424 | 1 0 | (0 0) (0 0)
1577 10:52:27.298291 0 11 8 | B1->B0 | 3838 4444 | 1 0 | (0 0) (0 0)
1578 10:52:27.302661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 10:52:27.305668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 10:52:27.309980 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 10:52:27.317422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 10:52:27.320928 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 10:52:27.325060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 10:52:27.328436 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 10:52:27.332058 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 10:52:27.339286 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 10:52:27.342681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 10:52:27.346624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 10:52:27.350139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 10:52:27.353440 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 10:52:27.360979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 10:52:27.364823 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 10:52:27.368625 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 10:52:27.371736 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 10:52:27.375918 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 10:52:27.382964 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 10:52:27.386334 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 10:52:27.390206 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 10:52:27.393513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 10:52:27.397263 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1601 10:52:27.404674 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1602 10:52:27.404763 Total UI for P1: 0, mck2ui 16
1603 10:52:27.408369 best dqsien dly found for B0: ( 0, 14, 4)
1604 10:52:27.412403 Total UI for P1: 0, mck2ui 16
1605 10:52:27.415804 best dqsien dly found for B1: ( 0, 14, 4)
1606 10:52:27.418686 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1607 10:52:27.422525 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1608 10:52:27.422609
1609 10:52:27.426064 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1610 10:52:27.429448 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1611 10:52:27.433531 [Gating] SW calibration Done
1612 10:52:27.433614 ==
1613 10:52:27.436350 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 10:52:27.440159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 10:52:27.443129 ==
1616 10:52:27.443212 RX Vref Scan: 0
1617 10:52:27.443278
1618 10:52:27.446065 RX Vref 0 -> 0, step: 1
1619 10:52:27.446148
1620 10:52:27.449834 RX Delay -130 -> 252, step: 16
1621 10:52:27.453292 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1622 10:52:27.456128 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1623 10:52:27.460035 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1624 10:52:27.462598 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1625 10:52:27.469633 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1626 10:52:27.472740 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1627 10:52:27.475974 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1628 10:52:27.479466 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1629 10:52:27.483134 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1630 10:52:27.489191 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1631 10:52:27.492283 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1632 10:52:27.495706 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1633 10:52:27.499469 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1634 10:52:27.506065 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1635 10:52:27.509225 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1636 10:52:27.512340 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1637 10:52:27.512424 ==
1638 10:52:27.516089 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 10:52:27.518993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 10:52:27.519078 ==
1641 10:52:27.522113 DQS Delay:
1642 10:52:27.522196 DQS0 = 0, DQS1 = 0
1643 10:52:27.525426 DQM Delay:
1644 10:52:27.525509 DQM0 = 89, DQM1 = 79
1645 10:52:27.525575 DQ Delay:
1646 10:52:27.528807 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1647 10:52:27.532488 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1648 10:52:27.535666 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1649 10:52:27.538835 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1650 10:52:27.538933
1651 10:52:27.538998
1652 10:52:27.542325 ==
1653 10:52:27.545663 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 10:52:27.548679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 10:52:27.548762 ==
1656 10:52:27.548828
1657 10:52:27.548888
1658 10:52:27.552381 TX Vref Scan disable
1659 10:52:27.552488 == TX Byte 0 ==
1660 10:52:27.558749 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1661 10:52:27.562610 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1662 10:52:27.562694 == TX Byte 1 ==
1663 10:52:27.568898 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1664 10:52:27.571850 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1665 10:52:27.571934 ==
1666 10:52:27.575500 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 10:52:27.579034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 10:52:27.579118 ==
1669 10:52:27.592228 TX Vref=22, minBit 3, minWin=27, winSum=445
1670 10:52:27.595337 TX Vref=24, minBit 10, minWin=27, winSum=445
1671 10:52:27.598466 TX Vref=26, minBit 12, minWin=27, winSum=451
1672 10:52:27.601893 TX Vref=28, minBit 1, minWin=28, winSum=455
1673 10:52:27.605437 TX Vref=30, minBit 8, minWin=27, winSum=451
1674 10:52:27.612427 TX Vref=32, minBit 9, minWin=27, winSum=448
1675 10:52:27.615598 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 28
1676 10:52:27.615684
1677 10:52:27.618797 Final TX Range 1 Vref 28
1678 10:52:27.618881
1679 10:52:27.618990 ==
1680 10:52:27.622125 Dram Type= 6, Freq= 0, CH_1, rank 0
1681 10:52:27.625840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1682 10:52:27.628455 ==
1683 10:52:27.628576
1684 10:52:27.628673
1685 10:52:27.628748 TX Vref Scan disable
1686 10:52:27.631920 == TX Byte 0 ==
1687 10:52:27.635982 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1688 10:52:27.642349 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1689 10:52:27.642511 == TX Byte 1 ==
1690 10:52:27.645261 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1691 10:52:27.651899 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1692 10:52:27.652000
1693 10:52:27.652090 [DATLAT]
1694 10:52:27.652177 Freq=800, CH1 RK0
1695 10:52:27.652262
1696 10:52:27.655875 DATLAT Default: 0xa
1697 10:52:27.655962 0, 0xFFFF, sum = 0
1698 10:52:27.658952 1, 0xFFFF, sum = 0
1699 10:52:27.659092 2, 0xFFFF, sum = 0
1700 10:52:27.662108 3, 0xFFFF, sum = 0
1701 10:52:27.665507 4, 0xFFFF, sum = 0
1702 10:52:27.665606 5, 0xFFFF, sum = 0
1703 10:52:27.669242 6, 0xFFFF, sum = 0
1704 10:52:27.669326 7, 0xFFFF, sum = 0
1705 10:52:27.671920 8, 0xFFFF, sum = 0
1706 10:52:27.672007 9, 0x0, sum = 1
1707 10:52:27.672075 10, 0x0, sum = 2
1708 10:52:27.675331 11, 0x0, sum = 3
1709 10:52:27.675447 12, 0x0, sum = 4
1710 10:52:27.678614 best_step = 10
1711 10:52:27.678696
1712 10:52:27.678761 ==
1713 10:52:27.681807 Dram Type= 6, Freq= 0, CH_1, rank 0
1714 10:52:27.685371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1715 10:52:27.685454 ==
1716 10:52:27.688646 RX Vref Scan: 1
1717 10:52:27.688755
1718 10:52:27.691995 Set Vref Range= 32 -> 127
1719 10:52:27.692078
1720 10:52:27.692144 RX Vref 32 -> 127, step: 1
1721 10:52:27.692205
1722 10:52:27.695470 RX Delay -95 -> 252, step: 8
1723 10:52:27.695555
1724 10:52:27.698812 Set Vref, RX VrefLevel [Byte0]: 32
1725 10:52:27.702000 [Byte1]: 32
1726 10:52:27.705371
1727 10:52:27.705471 Set Vref, RX VrefLevel [Byte0]: 33
1728 10:52:27.708453 [Byte1]: 33
1729 10:52:27.712679
1730 10:52:27.712764 Set Vref, RX VrefLevel [Byte0]: 34
1731 10:52:27.715913 [Byte1]: 34
1732 10:52:27.720243
1733 10:52:27.720328 Set Vref, RX VrefLevel [Byte0]: 35
1734 10:52:27.723202 [Byte1]: 35
1735 10:52:27.727917
1736 10:52:27.728002 Set Vref, RX VrefLevel [Byte0]: 36
1737 10:52:27.731133 [Byte1]: 36
1738 10:52:27.735530
1739 10:52:27.735609 Set Vref, RX VrefLevel [Byte0]: 37
1740 10:52:27.738442 [Byte1]: 37
1741 10:52:27.743114
1742 10:52:27.743208 Set Vref, RX VrefLevel [Byte0]: 38
1743 10:52:27.746119 [Byte1]: 38
1744 10:52:27.750662
1745 10:52:27.750738 Set Vref, RX VrefLevel [Byte0]: 39
1746 10:52:27.754031 [Byte1]: 39
1747 10:52:27.758443
1748 10:52:27.758521 Set Vref, RX VrefLevel [Byte0]: 40
1749 10:52:27.761494 [Byte1]: 40
1750 10:52:27.766174
1751 10:52:27.766260 Set Vref, RX VrefLevel [Byte0]: 41
1752 10:52:27.768872 [Byte1]: 41
1753 10:52:27.773641
1754 10:52:27.773724 Set Vref, RX VrefLevel [Byte0]: 42
1755 10:52:27.777309 [Byte1]: 42
1756 10:52:27.781548
1757 10:52:27.781623 Set Vref, RX VrefLevel [Byte0]: 43
1758 10:52:27.784213 [Byte1]: 43
1759 10:52:27.788747
1760 10:52:27.788822 Set Vref, RX VrefLevel [Byte0]: 44
1761 10:52:27.792073 [Byte1]: 44
1762 10:52:27.796242
1763 10:52:27.796322 Set Vref, RX VrefLevel [Byte0]: 45
1764 10:52:27.800353 [Byte1]: 45
1765 10:52:27.804154
1766 10:52:27.804235 Set Vref, RX VrefLevel [Byte0]: 46
1767 10:52:27.806909 [Byte1]: 46
1768 10:52:27.811352
1769 10:52:27.811434 Set Vref, RX VrefLevel [Byte0]: 47
1770 10:52:27.814836 [Byte1]: 47
1771 10:52:27.819176
1772 10:52:27.819253 Set Vref, RX VrefLevel [Byte0]: 48
1773 10:52:27.821932 [Byte1]: 48
1774 10:52:27.826522
1775 10:52:27.826603 Set Vref, RX VrefLevel [Byte0]: 49
1776 10:52:27.830335 [Byte1]: 49
1777 10:52:27.833853
1778 10:52:27.833933 Set Vref, RX VrefLevel [Byte0]: 50
1779 10:52:27.837435 [Byte1]: 50
1780 10:52:27.841673
1781 10:52:27.841757 Set Vref, RX VrefLevel [Byte0]: 51
1782 10:52:27.844957 [Byte1]: 51
1783 10:52:27.849321
1784 10:52:27.849429 Set Vref, RX VrefLevel [Byte0]: 52
1785 10:52:27.852880 [Byte1]: 52
1786 10:52:27.856706
1787 10:52:27.856815 Set Vref, RX VrefLevel [Byte0]: 53
1788 10:52:27.860036 [Byte1]: 53
1789 10:52:27.864280
1790 10:52:27.864396 Set Vref, RX VrefLevel [Byte0]: 54
1791 10:52:27.867819 [Byte1]: 54
1792 10:52:27.872151
1793 10:52:27.872236 Set Vref, RX VrefLevel [Byte0]: 55
1794 10:52:27.875583 [Byte1]: 55
1795 10:52:27.879704
1796 10:52:27.879831 Set Vref, RX VrefLevel [Byte0]: 56
1797 10:52:27.883261 [Byte1]: 56
1798 10:52:27.887466
1799 10:52:27.887559 Set Vref, RX VrefLevel [Byte0]: 57
1800 10:52:27.890707 [Byte1]: 57
1801 10:52:27.895453
1802 10:52:27.895537 Set Vref, RX VrefLevel [Byte0]: 58
1803 10:52:27.898336 [Byte1]: 58
1804 10:52:27.902493
1805 10:52:27.902620 Set Vref, RX VrefLevel [Byte0]: 59
1806 10:52:27.905574 [Byte1]: 59
1807 10:52:27.910162
1808 10:52:27.910268 Set Vref, RX VrefLevel [Byte0]: 60
1809 10:52:27.913338 [Byte1]: 60
1810 10:52:27.917552
1811 10:52:27.917666 Set Vref, RX VrefLevel [Byte0]: 61
1812 10:52:27.920998 [Byte1]: 61
1813 10:52:27.925287
1814 10:52:27.925391 Set Vref, RX VrefLevel [Byte0]: 62
1815 10:52:27.928699 [Byte1]: 62
1816 10:52:27.932964
1817 10:52:27.933088 Set Vref, RX VrefLevel [Byte0]: 63
1818 10:52:27.936421 [Byte1]: 63
1819 10:52:27.940311
1820 10:52:27.940392 Set Vref, RX VrefLevel [Byte0]: 64
1821 10:52:27.944378 [Byte1]: 64
1822 10:52:27.948080
1823 10:52:27.948180 Set Vref, RX VrefLevel [Byte0]: 65
1824 10:52:27.951261 [Byte1]: 65
1825 10:52:27.955828
1826 10:52:27.955908 Set Vref, RX VrefLevel [Byte0]: 66
1827 10:52:27.959127 [Byte1]: 66
1828 10:52:27.963198
1829 10:52:27.963278 Set Vref, RX VrefLevel [Byte0]: 67
1830 10:52:27.966624 [Byte1]: 67
1831 10:52:27.970938
1832 10:52:27.971025 Set Vref, RX VrefLevel [Byte0]: 68
1833 10:52:27.974501 [Byte1]: 68
1834 10:52:27.979139
1835 10:52:27.979219 Set Vref, RX VrefLevel [Byte0]: 69
1836 10:52:27.981688 [Byte1]: 69
1837 10:52:27.986068
1838 10:52:27.986149 Set Vref, RX VrefLevel [Byte0]: 70
1839 10:52:27.989201 [Byte1]: 70
1840 10:52:27.993624
1841 10:52:27.993704 Set Vref, RX VrefLevel [Byte0]: 71
1842 10:52:27.997198 [Byte1]: 71
1843 10:52:28.001087
1844 10:52:28.001167 Set Vref, RX VrefLevel [Byte0]: 72
1845 10:52:28.005221 [Byte1]: 72
1846 10:52:28.009009
1847 10:52:28.009089 Set Vref, RX VrefLevel [Byte0]: 73
1848 10:52:28.012127 [Byte1]: 73
1849 10:52:28.016803
1850 10:52:28.016883 Set Vref, RX VrefLevel [Byte0]: 74
1851 10:52:28.019565 [Byte1]: 74
1852 10:52:28.024009
1853 10:52:28.024089 Set Vref, RX VrefLevel [Byte0]: 75
1854 10:52:28.027320 [Byte1]: 75
1855 10:52:28.031729
1856 10:52:28.031810 Final RX Vref Byte 0 = 56 to rank0
1857 10:52:28.034896 Final RX Vref Byte 1 = 62 to rank0
1858 10:52:28.037947 Final RX Vref Byte 0 = 56 to rank1
1859 10:52:28.041689 Final RX Vref Byte 1 = 62 to rank1==
1860 10:52:28.044767 Dram Type= 6, Freq= 0, CH_1, rank 0
1861 10:52:28.051809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 10:52:28.051925 ==
1863 10:52:28.052012 DQS Delay:
1864 10:52:28.052092 DQS0 = 0, DQS1 = 0
1865 10:52:28.055614 DQM Delay:
1866 10:52:28.055717 DQM0 = 87, DQM1 = 78
1867 10:52:28.058415 DQ Delay:
1868 10:52:28.061420 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1869 10:52:28.064837 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1870 10:52:28.068333 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1871 10:52:28.071469 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =84
1872 10:52:28.071555
1873 10:52:28.071639
1874 10:52:28.078256 [DQSOSCAuto] RK0, (LSB)MR18= 0x311e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1875 10:52:28.081497 CH1 RK0: MR19=606, MR18=311E
1876 10:52:28.088161 CH1_RK0: MR19=0x606, MR18=0x311E, DQSOSC=397, MR23=63, INC=93, DEC=62
1877 10:52:28.088248
1878 10:52:28.091505 ----->DramcWriteLeveling(PI) begin...
1879 10:52:28.091627 ==
1880 10:52:28.094505 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 10:52:28.098083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 10:52:28.098170 ==
1883 10:52:28.101867 Write leveling (Byte 0): 26 => 26
1884 10:52:28.104867 Write leveling (Byte 1): 31 => 31
1885 10:52:28.107770 DramcWriteLeveling(PI) end<-----
1886 10:52:28.107855
1887 10:52:28.107940 ==
1888 10:52:28.111348 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 10:52:28.114361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 10:52:28.114447 ==
1891 10:52:28.117681 [Gating] SW mode calibration
1892 10:52:28.124248 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1893 10:52:28.131437 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1894 10:52:28.134396 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1895 10:52:28.140826 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1896 10:52:28.145046 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1897 10:52:28.147364 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1898 10:52:28.154225 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 10:52:28.157526 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 10:52:28.160660 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 10:52:28.168016 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:52:28.171218 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:52:28.173914 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:52:28.177336 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:52:28.184373 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:52:28.187352 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:52:28.190706 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:52:28.197764 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 10:52:28.201067 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:52:28.203913 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 10:52:28.210705 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1912 10:52:28.214118 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 10:52:28.217190 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 10:52:28.223988 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 10:52:28.227409 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 10:52:28.230556 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 10:52:28.236978 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 10:52:28.240595 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 10:52:28.243654 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 10:52:28.250708 0 9 8 | B1->B0 | 3030 2727 | 1 0 | (1 1) (0 0)
1921 10:52:28.254047 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 10:52:28.257308 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 10:52:28.263460 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 10:52:28.267105 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 10:52:28.270734 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 10:52:28.277257 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 10:52:28.280869 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1928 10:52:28.283498 0 10 8 | B1->B0 | 2626 2c2c | 0 1 | (0 0) (1 0)
1929 10:52:28.290400 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 10:52:28.294265 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 10:52:28.297236 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 10:52:28.303816 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 10:52:28.307416 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 10:52:28.310534 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 10:52:28.316772 0 11 4 | B1->B0 | 2f2f 2828 | 0 1 | (0 0) (0 0)
1936 10:52:28.320156 0 11 8 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
1937 10:52:28.323404 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1938 10:52:28.326926 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 10:52:28.333454 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 10:52:28.336846 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 10:52:28.339788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 10:52:28.347008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 10:52:28.349966 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1944 10:52:28.352903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1945 10:52:28.359700 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 10:52:28.363100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 10:52:28.366223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 10:52:28.373165 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 10:52:28.376177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 10:52:28.379758 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 10:52:28.386627 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 10:52:28.389567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 10:52:28.392675 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 10:52:28.399551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 10:52:28.402806 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 10:52:28.406104 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 10:52:28.412711 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 10:52:28.416349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1959 10:52:28.419417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1960 10:52:28.426728 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1961 10:52:28.429286 Total UI for P1: 0, mck2ui 16
1962 10:52:28.432912 best dqsien dly found for B0: ( 0, 14, 2)
1963 10:52:28.433011 Total UI for P1: 0, mck2ui 16
1964 10:52:28.439187 best dqsien dly found for B1: ( 0, 14, 2)
1965 10:52:28.442570 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1966 10:52:28.446057 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1967 10:52:28.446140
1968 10:52:28.449276 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1969 10:52:28.452555 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1970 10:52:28.455807 [Gating] SW calibration Done
1971 10:52:28.455891 ==
1972 10:52:28.459368 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 10:52:28.462168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 10:52:28.462253 ==
1975 10:52:28.465943 RX Vref Scan: 0
1976 10:52:28.466035
1977 10:52:28.466131 RX Vref 0 -> 0, step: 1
1978 10:52:28.466197
1979 10:52:28.469215 RX Delay -130 -> 252, step: 16
1980 10:52:28.472781 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1981 10:52:28.479240 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1982 10:52:28.482387 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1983 10:52:28.485770 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1984 10:52:28.489080 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1985 10:52:28.495423 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1986 10:52:28.498719 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1987 10:52:28.502182 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1988 10:52:28.505355 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1989 10:52:28.508551 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1990 10:52:28.515476 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1991 10:52:28.519374 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1992 10:52:28.521903 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1993 10:52:28.525338 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1994 10:52:28.528420 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1995 10:52:28.535581 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1996 10:52:28.535681 ==
1997 10:52:28.539073 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 10:52:28.542264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 10:52:28.542347 ==
2000 10:52:28.542439 DQS Delay:
2001 10:52:28.545725 DQS0 = 0, DQS1 = 0
2002 10:52:28.545807 DQM Delay:
2003 10:52:28.548381 DQM0 = 87, DQM1 = 78
2004 10:52:28.548463 DQ Delay:
2005 10:52:28.552016 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
2006 10:52:28.555126 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2007 10:52:28.558567 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2008 10:52:28.562243 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2009 10:52:28.562326
2010 10:52:28.562391
2011 10:52:28.562450 ==
2012 10:52:28.565161 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 10:52:28.568753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 10:52:28.571861 ==
2015 10:52:28.571945
2016 10:52:28.572011
2017 10:52:28.572071 TX Vref Scan disable
2018 10:52:28.575112 == TX Byte 0 ==
2019 10:52:28.578353 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2020 10:52:28.582143 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2021 10:52:28.585204 == TX Byte 1 ==
2022 10:52:28.588414 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2023 10:52:28.591869 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2024 10:52:28.595613 ==
2025 10:52:28.598655 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 10:52:28.601556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 10:52:28.601640 ==
2028 10:52:28.614325 TX Vref=22, minBit 1, minWin=27, winSum=446
2029 10:52:28.618010 TX Vref=24, minBit 1, minWin=27, winSum=444
2030 10:52:28.620965 TX Vref=26, minBit 13, minWin=27, winSum=450
2031 10:52:28.624327 TX Vref=28, minBit 13, minWin=27, winSum=451
2032 10:52:28.628201 TX Vref=30, minBit 8, minWin=27, winSum=451
2033 10:52:28.634412 TX Vref=32, minBit 8, minWin=27, winSum=448
2034 10:52:28.637509 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 28
2035 10:52:28.637592
2036 10:52:28.640839 Final TX Range 1 Vref 28
2037 10:52:28.640923
2038 10:52:28.640989 ==
2039 10:52:28.643843 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 10:52:28.647189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 10:52:28.650666 ==
2042 10:52:28.650748
2043 10:52:28.650814
2044 10:52:28.650874 TX Vref Scan disable
2045 10:52:28.654758 == TX Byte 0 ==
2046 10:52:28.657992 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2047 10:52:28.665050 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2048 10:52:28.665156 == TX Byte 1 ==
2049 10:52:28.667833 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2050 10:52:28.674675 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2051 10:52:28.674801
2052 10:52:28.674898 [DATLAT]
2053 10:52:28.674988 Freq=800, CH1 RK1
2054 10:52:28.675076
2055 10:52:28.677353 DATLAT Default: 0xa
2056 10:52:28.680698 0, 0xFFFF, sum = 0
2057 10:52:28.680890 1, 0xFFFF, sum = 0
2058 10:52:28.684229 2, 0xFFFF, sum = 0
2059 10:52:28.684367 3, 0xFFFF, sum = 0
2060 10:52:28.687435 4, 0xFFFF, sum = 0
2061 10:52:28.687573 5, 0xFFFF, sum = 0
2062 10:52:28.690686 6, 0xFFFF, sum = 0
2063 10:52:28.690842 7, 0xFFFF, sum = 0
2064 10:52:28.694406 8, 0xFFFF, sum = 0
2065 10:52:28.694490 9, 0x0, sum = 1
2066 10:52:28.697155 10, 0x0, sum = 2
2067 10:52:28.697238 11, 0x0, sum = 3
2068 10:52:28.700505 12, 0x0, sum = 4
2069 10:52:28.700610 best_step = 10
2070 10:52:28.700676
2071 10:52:28.700751 ==
2072 10:52:28.703893 Dram Type= 6, Freq= 0, CH_1, rank 1
2073 10:52:28.706794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2074 10:52:28.706878 ==
2075 10:52:28.710348 RX Vref Scan: 0
2076 10:52:28.710447
2077 10:52:28.713578 RX Vref 0 -> 0, step: 1
2078 10:52:28.713704
2079 10:52:28.713828 RX Delay -95 -> 252, step: 8
2080 10:52:28.720935 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2081 10:52:28.724593 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2082 10:52:28.727887 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2083 10:52:28.731217 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2084 10:52:28.734531 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2085 10:52:28.740798 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2086 10:52:28.744765 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2087 10:52:28.747544 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2088 10:52:28.750737 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2089 10:52:28.757111 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2090 10:52:28.760708 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2091 10:52:28.764149 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2092 10:52:28.767318 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2093 10:52:28.770913 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2094 10:52:28.777281 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2095 10:52:28.780696 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2096 10:52:28.780803 ==
2097 10:52:28.783908 Dram Type= 6, Freq= 0, CH_1, rank 1
2098 10:52:28.786938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2099 10:52:28.787024 ==
2100 10:52:28.790257 DQS Delay:
2101 10:52:28.790339 DQS0 = 0, DQS1 = 0
2102 10:52:28.790405 DQM Delay:
2103 10:52:28.793693 DQM0 = 87, DQM1 = 79
2104 10:52:28.793776 DQ Delay:
2105 10:52:28.797331 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2106 10:52:28.800741 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2107 10:52:28.804058 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2108 10:52:28.806869 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2109 10:52:28.806952
2110 10:52:28.807018
2111 10:52:28.817164 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
2112 10:52:28.820234 CH1 RK1: MR19=606, MR18=1B14
2113 10:52:28.823844 CH1_RK1: MR19=0x606, MR18=0x1B14, DQSOSC=403, MR23=63, INC=90, DEC=60
2114 10:52:28.827416 [RxdqsGatingPostProcess] freq 800
2115 10:52:28.833475 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2116 10:52:28.836802 Pre-setting of DQS Precalculation
2117 10:52:28.840133 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2118 10:52:28.850278 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2119 10:52:28.856965 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2120 10:52:28.857050
2121 10:52:28.857116
2122 10:52:28.860456 [Calibration Summary] 1600 Mbps
2123 10:52:28.860575 CH 0, Rank 0
2124 10:52:28.863300 SW Impedance : PASS
2125 10:52:28.863399 DUTY Scan : NO K
2126 10:52:28.866743 ZQ Calibration : PASS
2127 10:52:28.869993 Jitter Meter : NO K
2128 10:52:28.870076 CBT Training : PASS
2129 10:52:28.873080 Write leveling : PASS
2130 10:52:28.876705 RX DQS gating : PASS
2131 10:52:28.876788 RX DQ/DQS(RDDQC) : PASS
2132 10:52:28.880118 TX DQ/DQS : PASS
2133 10:52:28.883260 RX DATLAT : PASS
2134 10:52:28.883343 RX DQ/DQS(Engine): PASS
2135 10:52:28.886680 TX OE : NO K
2136 10:52:28.886763 All Pass.
2137 10:52:28.886828
2138 10:52:28.890041 CH 0, Rank 1
2139 10:52:28.890124 SW Impedance : PASS
2140 10:52:28.893633 DUTY Scan : NO K
2141 10:52:28.893717 ZQ Calibration : PASS
2142 10:52:28.896965 Jitter Meter : NO K
2143 10:52:28.900359 CBT Training : PASS
2144 10:52:28.900441 Write leveling : PASS
2145 10:52:28.903157 RX DQS gating : PASS
2146 10:52:28.906289 RX DQ/DQS(RDDQC) : PASS
2147 10:52:28.906372 TX DQ/DQS : PASS
2148 10:52:28.909814 RX DATLAT : PASS
2149 10:52:28.913415 RX DQ/DQS(Engine): PASS
2150 10:52:28.913498 TX OE : NO K
2151 10:52:28.916814 All Pass.
2152 10:52:28.916896
2153 10:52:28.916961 CH 1, Rank 0
2154 10:52:28.919810 SW Impedance : PASS
2155 10:52:28.919933 DUTY Scan : NO K
2156 10:52:28.923480 ZQ Calibration : PASS
2157 10:52:28.926710 Jitter Meter : NO K
2158 10:52:28.926797 CBT Training : PASS
2159 10:52:28.930423 Write leveling : PASS
2160 10:52:28.932992 RX DQS gating : PASS
2161 10:52:28.933075 RX DQ/DQS(RDDQC) : PASS
2162 10:52:28.936455 TX DQ/DQS : PASS
2163 10:52:28.940018 RX DATLAT : PASS
2164 10:52:28.940161 RX DQ/DQS(Engine): PASS
2165 10:52:28.943318 TX OE : NO K
2166 10:52:28.943402 All Pass.
2167 10:52:28.943467
2168 10:52:28.946489 CH 1, Rank 1
2169 10:52:28.946572 SW Impedance : PASS
2170 10:52:28.950147 DUTY Scan : NO K
2171 10:52:28.950230 ZQ Calibration : PASS
2172 10:52:28.953116 Jitter Meter : NO K
2173 10:52:28.956223 CBT Training : PASS
2174 10:52:28.956307 Write leveling : PASS
2175 10:52:28.959649 RX DQS gating : PASS
2176 10:52:28.963026 RX DQ/DQS(RDDQC) : PASS
2177 10:52:28.963113 TX DQ/DQS : PASS
2178 10:52:28.966182 RX DATLAT : PASS
2179 10:52:28.969535 RX DQ/DQS(Engine): PASS
2180 10:52:28.969617 TX OE : NO K
2181 10:52:28.972731 All Pass.
2182 10:52:28.972813
2183 10:52:28.972878 DramC Write-DBI off
2184 10:52:28.976045 PER_BANK_REFRESH: Hybrid Mode
2185 10:52:28.979397 TX_TRACKING: ON
2186 10:52:28.982773 [GetDramInforAfterCalByMRR] Vendor 6.
2187 10:52:28.987242 [GetDramInforAfterCalByMRR] Revision 606.
2188 10:52:28.989413 [GetDramInforAfterCalByMRR] Revision 2 0.
2189 10:52:28.989496 MR0 0x3b3b
2190 10:52:28.989561 MR8 0x5151
2191 10:52:28.996020 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2192 10:52:28.996103
2193 10:52:28.996167 MR0 0x3b3b
2194 10:52:28.996228 MR8 0x5151
2195 10:52:28.999527 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2196 10:52:28.999610
2197 10:52:29.009321 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2198 10:52:29.012500 [FAST_K] Save calibration result to emmc
2199 10:52:29.015599 [FAST_K] Save calibration result to emmc
2200 10:52:29.019354 dram_init: config_dvfs: 1
2201 10:52:29.022448 dramc_set_vcore_voltage set vcore to 662500
2202 10:52:29.026620 Read voltage for 1200, 2
2203 10:52:29.026697 Vio18 = 0
2204 10:52:29.026762 Vcore = 662500
2205 10:52:29.029098 Vdram = 0
2206 10:52:29.029172 Vddq = 0
2207 10:52:29.029234 Vmddr = 0
2208 10:52:29.035547 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2209 10:52:29.039086 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2210 10:52:29.042317 MEM_TYPE=3, freq_sel=15
2211 10:52:29.045317 sv_algorithm_assistance_LP4_1600
2212 10:52:29.049148 ============ PULL DRAM RESETB DOWN ============
2213 10:52:29.055590 ========== PULL DRAM RESETB DOWN end =========
2214 10:52:29.058486 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2215 10:52:29.062126 ===================================
2216 10:52:29.065497 LPDDR4 DRAM CONFIGURATION
2217 10:52:29.068825 ===================================
2218 10:52:29.068898 EX_ROW_EN[0] = 0x0
2219 10:52:29.072031 EX_ROW_EN[1] = 0x0
2220 10:52:29.072130 LP4Y_EN = 0x0
2221 10:52:29.075143 WORK_FSP = 0x0
2222 10:52:29.075242 WL = 0x4
2223 10:52:29.079014 RL = 0x4
2224 10:52:29.079113 BL = 0x2
2225 10:52:29.081933 RPST = 0x0
2226 10:52:29.082004 RD_PRE = 0x0
2227 10:52:29.085195 WR_PRE = 0x1
2228 10:52:29.085264 WR_PST = 0x0
2229 10:52:29.088669 DBI_WR = 0x0
2230 10:52:29.091838 DBI_RD = 0x0
2231 10:52:29.091911 OTF = 0x1
2232 10:52:29.095224 ===================================
2233 10:52:29.098658 ===================================
2234 10:52:29.098742 ANA top config
2235 10:52:29.101877 ===================================
2236 10:52:29.105257 DLL_ASYNC_EN = 0
2237 10:52:29.108997 ALL_SLAVE_EN = 0
2238 10:52:29.112307 NEW_RANK_MODE = 1
2239 10:52:29.115434 DLL_IDLE_MODE = 1
2240 10:52:29.115505 LP45_APHY_COMB_EN = 1
2241 10:52:29.118690 TX_ODT_DIS = 1
2242 10:52:29.122118 NEW_8X_MODE = 1
2243 10:52:29.125390 ===================================
2244 10:52:29.128854 ===================================
2245 10:52:29.131736 data_rate = 2400
2246 10:52:29.134975 CKR = 1
2247 10:52:29.135061 DQ_P2S_RATIO = 8
2248 10:52:29.139037 ===================================
2249 10:52:29.141789 CA_P2S_RATIO = 8
2250 10:52:29.145172 DQ_CA_OPEN = 0
2251 10:52:29.148268 DQ_SEMI_OPEN = 0
2252 10:52:29.152195 CA_SEMI_OPEN = 0
2253 10:52:29.155112 CA_FULL_RATE = 0
2254 10:52:29.155186 DQ_CKDIV4_EN = 0
2255 10:52:29.158253 CA_CKDIV4_EN = 0
2256 10:52:29.161865 CA_PREDIV_EN = 0
2257 10:52:29.164925 PH8_DLY = 17
2258 10:52:29.168163 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2259 10:52:29.171662 DQ_AAMCK_DIV = 4
2260 10:52:29.171737 CA_AAMCK_DIV = 4
2261 10:52:29.174778 CA_ADMCK_DIV = 4
2262 10:52:29.178632 DQ_TRACK_CA_EN = 0
2263 10:52:29.181568 CA_PICK = 1200
2264 10:52:29.185097 CA_MCKIO = 1200
2265 10:52:29.188407 MCKIO_SEMI = 0
2266 10:52:29.191287 PLL_FREQ = 2366
2267 10:52:29.191361 DQ_UI_PI_RATIO = 32
2268 10:52:29.194614 CA_UI_PI_RATIO = 0
2269 10:52:29.198522 ===================================
2270 10:52:29.201188 ===================================
2271 10:52:29.204539 memory_type:LPDDR4
2272 10:52:29.208089 GP_NUM : 10
2273 10:52:29.208164 SRAM_EN : 1
2274 10:52:29.211620 MD32_EN : 0
2275 10:52:29.215131 ===================================
2276 10:52:29.218239 [ANA_INIT] >>>>>>>>>>>>>>
2277 10:52:29.218341 <<<<<< [CONFIGURE PHASE]: ANA_TX
2278 10:52:29.224504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2279 10:52:29.227729 ===================================
2280 10:52:29.227823 data_rate = 2400,PCW = 0X5b00
2281 10:52:29.231032 ===================================
2282 10:52:29.234465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2283 10:52:29.241140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2284 10:52:29.248073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2285 10:52:29.251081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2286 10:52:29.254045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2287 10:52:29.257619 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2288 10:52:29.261347 [ANA_INIT] flow start
2289 10:52:29.261434 [ANA_INIT] PLL >>>>>>>>
2290 10:52:29.264775 [ANA_INIT] PLL <<<<<<<<
2291 10:52:29.267606 [ANA_INIT] MIDPI >>>>>>>>
2292 10:52:29.270841 [ANA_INIT] MIDPI <<<<<<<<
2293 10:52:29.270939 [ANA_INIT] DLL >>>>>>>>
2294 10:52:29.274117 [ANA_INIT] DLL <<<<<<<<
2295 10:52:29.277451 [ANA_INIT] flow end
2296 10:52:29.280968 ============ LP4 DIFF to SE enter ============
2297 10:52:29.283986 ============ LP4 DIFF to SE exit ============
2298 10:52:29.287373 [ANA_INIT] <<<<<<<<<<<<<
2299 10:52:29.290513 [Flow] Enable top DCM control >>>>>
2300 10:52:29.294112 [Flow] Enable top DCM control <<<<<
2301 10:52:29.297152 Enable DLL master slave shuffle
2302 10:52:29.300565 ==============================================================
2303 10:52:29.303722 Gating Mode config
2304 10:52:29.310580 ==============================================================
2305 10:52:29.310660 Config description:
2306 10:52:29.320812 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2307 10:52:29.327036 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2308 10:52:29.330640 SELPH_MODE 0: By rank 1: By Phase
2309 10:52:29.337249 ==============================================================
2310 10:52:29.340316 GAT_TRACK_EN = 1
2311 10:52:29.343883 RX_GATING_MODE = 2
2312 10:52:29.346980 RX_GATING_TRACK_MODE = 2
2313 10:52:29.350419 SELPH_MODE = 1
2314 10:52:29.353266 PICG_EARLY_EN = 1
2315 10:52:29.357154 VALID_LAT_VALUE = 1
2316 10:52:29.360360 ==============================================================
2317 10:52:29.364020 Enter into Gating configuration >>>>
2318 10:52:29.366784 Exit from Gating configuration <<<<
2319 10:52:29.369984 Enter into DVFS_PRE_config >>>>>
2320 10:52:29.380133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2321 10:52:29.383283 Exit from DVFS_PRE_config <<<<<
2322 10:52:29.386927 Enter into PICG configuration >>>>
2323 10:52:29.390011 Exit from PICG configuration <<<<
2324 10:52:29.393803 [RX_INPUT] configuration >>>>>
2325 10:52:29.397053 [RX_INPUT] configuration <<<<<
2326 10:52:29.403603 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2327 10:52:29.406747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2328 10:52:29.413962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2329 10:52:29.420305 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2330 10:52:29.426783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2331 10:52:29.433509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2332 10:52:29.436450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2333 10:52:29.440376 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2334 10:52:29.443625 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2335 10:52:29.449854 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2336 10:52:29.453698 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2337 10:52:29.456472 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2338 10:52:29.460117 ===================================
2339 10:52:29.463213 LPDDR4 DRAM CONFIGURATION
2340 10:52:29.466844 ===================================
2341 10:52:29.466928 EX_ROW_EN[0] = 0x0
2342 10:52:29.470088 EX_ROW_EN[1] = 0x0
2343 10:52:29.470177 LP4Y_EN = 0x0
2344 10:52:29.473199 WORK_FSP = 0x0
2345 10:52:29.473282 WL = 0x4
2346 10:52:29.477182 RL = 0x4
2347 10:52:29.480020 BL = 0x2
2348 10:52:29.480128 RPST = 0x0
2349 10:52:29.483261 RD_PRE = 0x0
2350 10:52:29.483371 WR_PRE = 0x1
2351 10:52:29.487027 WR_PST = 0x0
2352 10:52:29.487135 DBI_WR = 0x0
2353 10:52:29.490221 DBI_RD = 0x0
2354 10:52:29.490295 OTF = 0x1
2355 10:52:29.493138 ===================================
2356 10:52:29.497030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2357 10:52:29.503126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2358 10:52:29.506700 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2359 10:52:29.510018 ===================================
2360 10:52:29.513072 LPDDR4 DRAM CONFIGURATION
2361 10:52:29.516347 ===================================
2362 10:52:29.516471 EX_ROW_EN[0] = 0x10
2363 10:52:29.520023 EX_ROW_EN[1] = 0x0
2364 10:52:29.520132 LP4Y_EN = 0x0
2365 10:52:29.523231 WORK_FSP = 0x0
2366 10:52:29.523305 WL = 0x4
2367 10:52:29.526283 RL = 0x4
2368 10:52:29.526358 BL = 0x2
2369 10:52:29.529828 RPST = 0x0
2370 10:52:29.529916 RD_PRE = 0x0
2371 10:52:29.533293 WR_PRE = 0x1
2372 10:52:29.536118 WR_PST = 0x0
2373 10:52:29.536215 DBI_WR = 0x0
2374 10:52:29.539751 DBI_RD = 0x0
2375 10:52:29.539822 OTF = 0x1
2376 10:52:29.543067 ===================================
2377 10:52:29.549910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2378 10:52:29.550018 ==
2379 10:52:29.552524 Dram Type= 6, Freq= 0, CH_0, rank 0
2380 10:52:29.556255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 10:52:29.556352 ==
2382 10:52:29.559337 [Duty_Offset_Calibration]
2383 10:52:29.562697 B0:1 B1:-1 CA:0
2384 10:52:29.562767
2385 10:52:29.565799 [DutyScan_Calibration_Flow] k_type=0
2386 10:52:29.574560
2387 10:52:29.574644 ==CLK 0==
2388 10:52:29.577613 Final CLK duty delay cell = 0
2389 10:52:29.580490 [0] MAX Duty = 5125%(X100), DQS PI = 24
2390 10:52:29.584156 [0] MIN Duty = 4875%(X100), DQS PI = 10
2391 10:52:29.587112 [0] AVG Duty = 5000%(X100)
2392 10:52:29.587193
2393 10:52:29.590572 CH0 CLK Duty spec in!! Max-Min= 250%
2394 10:52:29.593878 [DutyScan_Calibration_Flow] ====Done====
2395 10:52:29.593988
2396 10:52:29.597501 [DutyScan_Calibration_Flow] k_type=1
2397 10:52:29.611913
2398 10:52:29.612010 ==DQS 0 ==
2399 10:52:29.615592 Final DQS duty delay cell = -4
2400 10:52:29.618811 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2401 10:52:29.621818 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2402 10:52:29.625364 [-4] AVG Duty = 4968%(X100)
2403 10:52:29.625447
2404 10:52:29.625511 ==DQS 1 ==
2405 10:52:29.628334 Final DQS duty delay cell = -4
2406 10:52:29.631729 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2407 10:52:29.635104 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2408 10:52:29.638405 [-4] AVG Duty = 4938%(X100)
2409 10:52:29.638501
2410 10:52:29.641501 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2411 10:52:29.641668
2412 10:52:29.645764 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2413 10:52:29.648104 [DutyScan_Calibration_Flow] ====Done====
2414 10:52:29.648215
2415 10:52:29.651362 [DutyScan_Calibration_Flow] k_type=3
2416 10:52:29.670045
2417 10:52:29.670173 ==DQM 0 ==
2418 10:52:29.673116 Final DQM duty delay cell = 0
2419 10:52:29.676391 [0] MAX Duty = 5031%(X100), DQS PI = 16
2420 10:52:29.679505 [0] MIN Duty = 4875%(X100), DQS PI = 6
2421 10:52:29.682862 [0] AVG Duty = 4953%(X100)
2422 10:52:29.682945
2423 10:52:29.683011 ==DQM 1 ==
2424 10:52:29.686189 Final DQM duty delay cell = 4
2425 10:52:29.689739 [4] MAX Duty = 5187%(X100), DQS PI = 16
2426 10:52:29.692773 [4] MIN Duty = 5000%(X100), DQS PI = 24
2427 10:52:29.696372 [4] AVG Duty = 5093%(X100)
2428 10:52:29.696457
2429 10:52:29.699831 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2430 10:52:29.699930
2431 10:52:29.702777 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2432 10:52:29.706333 [DutyScan_Calibration_Flow] ====Done====
2433 10:52:29.706430
2434 10:52:29.710012 [DutyScan_Calibration_Flow] k_type=2
2435 10:52:29.725601
2436 10:52:29.725700 ==DQ 0 ==
2437 10:52:29.729054 Final DQ duty delay cell = -4
2438 10:52:29.732164 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2439 10:52:29.736120 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2440 10:52:29.738932 [-4] AVG Duty = 4969%(X100)
2441 10:52:29.739031
2442 10:52:29.739125 ==DQ 1 ==
2443 10:52:29.742179 Final DQ duty delay cell = 0
2444 10:52:29.745383 [0] MAX Duty = 5093%(X100), DQS PI = 2
2445 10:52:29.749121 [0] MIN Duty = 4969%(X100), DQS PI = 40
2446 10:52:29.752217 [0] AVG Duty = 5031%(X100)
2447 10:52:29.752300
2448 10:52:29.755352 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2449 10:52:29.755451
2450 10:52:29.758801 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2451 10:52:29.762136 [DutyScan_Calibration_Flow] ====Done====
2452 10:52:29.762220 ==
2453 10:52:29.765967 Dram Type= 6, Freq= 0, CH_1, rank 0
2454 10:52:29.768502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 10:52:29.768615 ==
2456 10:52:29.772159 [Duty_Offset_Calibration]
2457 10:52:29.772246 B0:-1 B1:1 CA:1
2458 10:52:29.772314
2459 10:52:29.775384 [DutyScan_Calibration_Flow] k_type=0
2460 10:52:29.785576
2461 10:52:29.785664 ==CLK 0==
2462 10:52:29.789030 Final CLK duty delay cell = 0
2463 10:52:29.792501 [0] MAX Duty = 5156%(X100), DQS PI = 4
2464 10:52:29.795664 [0] MIN Duty = 5000%(X100), DQS PI = 28
2465 10:52:29.795741 [0] AVG Duty = 5078%(X100)
2466 10:52:29.799587
2467 10:52:29.802263 CH1 CLK Duty spec in!! Max-Min= 156%
2468 10:52:29.805735 [DutyScan_Calibration_Flow] ====Done====
2469 10:52:29.805809
2470 10:52:29.808854 [DutyScan_Calibration_Flow] k_type=1
2471 10:52:29.824973
2472 10:52:29.825051 ==DQS 0 ==
2473 10:52:29.828407 Final DQS duty delay cell = 0
2474 10:52:29.831621 [0] MAX Duty = 5156%(X100), DQS PI = 18
2475 10:52:29.835357 [0] MIN Duty = 4938%(X100), DQS PI = 6
2476 10:52:29.838117 [0] AVG Duty = 5047%(X100)
2477 10:52:29.838192
2478 10:52:29.838255 ==DQS 1 ==
2479 10:52:29.841879 Final DQS duty delay cell = 0
2480 10:52:29.844761 [0] MAX Duty = 5062%(X100), DQS PI = 0
2481 10:52:29.847949 [0] MIN Duty = 4969%(X100), DQS PI = 26
2482 10:52:29.851665 [0] AVG Duty = 5015%(X100)
2483 10:52:29.851738
2484 10:52:29.854569 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2485 10:52:29.854645
2486 10:52:29.858459 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2487 10:52:29.861189 [DutyScan_Calibration_Flow] ====Done====
2488 10:52:29.861275
2489 10:52:29.864489 [DutyScan_Calibration_Flow] k_type=3
2490 10:52:29.880813
2491 10:52:29.880896 ==DQM 0 ==
2492 10:52:29.884033 Final DQM duty delay cell = -4
2493 10:52:29.887184 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2494 10:52:29.890552 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2495 10:52:29.893904 [-4] AVG Duty = 4953%(X100)
2496 10:52:29.894032
2497 10:52:29.894105 ==DQM 1 ==
2498 10:52:29.897128 Final DQM duty delay cell = 0
2499 10:52:29.900457 [0] MAX Duty = 5187%(X100), DQS PI = 36
2500 10:52:29.903740 [0] MIN Duty = 4969%(X100), DQS PI = 6
2501 10:52:29.906841 [0] AVG Duty = 5078%(X100)
2502 10:52:29.906919
2503 10:52:29.910813 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2504 10:52:29.910931
2505 10:52:29.914077 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2506 10:52:29.916871 [DutyScan_Calibration_Flow] ====Done====
2507 10:52:29.916979
2508 10:52:29.920130 [DutyScan_Calibration_Flow] k_type=2
2509 10:52:29.937117
2510 10:52:29.937198 ==DQ 0 ==
2511 10:52:29.940465 Final DQ duty delay cell = 0
2512 10:52:29.943895 [0] MAX Duty = 5156%(X100), DQS PI = 0
2513 10:52:29.947045 [0] MIN Duty = 4907%(X100), DQS PI = 38
2514 10:52:29.947127 [0] AVG Duty = 5031%(X100)
2515 10:52:29.947192
2516 10:52:29.950567 ==DQ 1 ==
2517 10:52:29.953755 Final DQ duty delay cell = 0
2518 10:52:29.957922 [0] MAX Duty = 5124%(X100), DQS PI = 42
2519 10:52:29.960700 [0] MIN Duty = 4969%(X100), DQS PI = 2
2520 10:52:29.960783 [0] AVG Duty = 5046%(X100)
2521 10:52:29.960851
2522 10:52:29.964217 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2523 10:52:29.964296
2524 10:52:29.970484 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2525 10:52:29.974322 [DutyScan_Calibration_Flow] ====Done====
2526 10:52:29.977237 nWR fixed to 30
2527 10:52:29.977341 [ModeRegInit_LP4] CH0 RK0
2528 10:52:29.980239 [ModeRegInit_LP4] CH0 RK1
2529 10:52:29.983959 [ModeRegInit_LP4] CH1 RK0
2530 10:52:29.984040 [ModeRegInit_LP4] CH1 RK1
2531 10:52:29.987435 match AC timing 7
2532 10:52:29.990504 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2533 10:52:29.993535 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2534 10:52:30.000399 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2535 10:52:30.003965 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2536 10:52:30.010643 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2537 10:52:30.010730 ==
2538 10:52:30.013743 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 10:52:30.016911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 10:52:30.016996 ==
2541 10:52:30.023694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 10:52:30.030297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2543 10:52:30.037336 [CA 0] Center 39 (9~70) winsize 62
2544 10:52:30.040433 [CA 1] Center 39 (9~69) winsize 61
2545 10:52:30.043872 [CA 2] Center 35 (5~66) winsize 62
2546 10:52:30.047230 [CA 3] Center 35 (4~66) winsize 63
2547 10:52:30.050435 [CA 4] Center 33 (4~63) winsize 60
2548 10:52:30.053741 [CA 5] Center 33 (3~63) winsize 61
2549 10:52:30.053840
2550 10:52:30.056763 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2551 10:52:30.056847
2552 10:52:30.060364 [CATrainingPosCal] consider 1 rank data
2553 10:52:30.063826 u2DelayCellTimex100 = 270/100 ps
2554 10:52:30.067085 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2555 10:52:30.073865 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2556 10:52:30.076678 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2557 10:52:30.080276 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2558 10:52:30.083673 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2559 10:52:30.087049 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2560 10:52:30.087132
2561 10:52:30.090075 CA PerBit enable=1, Macro0, CA PI delay=33
2562 10:52:30.090156
2563 10:52:30.093263 [CBTSetCACLKResult] CA Dly = 33
2564 10:52:30.096691 CS Dly: 8 (0~39)
2565 10:52:30.096774 ==
2566 10:52:30.099729 Dram Type= 6, Freq= 0, CH_0, rank 1
2567 10:52:30.103344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 10:52:30.103422 ==
2569 10:52:30.109629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2570 10:52:30.113426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2571 10:52:30.122710 [CA 0] Center 39 (9~70) winsize 62
2572 10:52:30.125884 [CA 1] Center 39 (9~70) winsize 62
2573 10:52:30.129449 [CA 2] Center 35 (5~66) winsize 62
2574 10:52:30.132837 [CA 3] Center 34 (4~65) winsize 62
2575 10:52:30.135873 [CA 4] Center 33 (3~64) winsize 62
2576 10:52:30.139891 [CA 5] Center 33 (3~63) winsize 61
2577 10:52:30.139971
2578 10:52:30.142555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2579 10:52:30.142627
2580 10:52:30.146296 [CATrainingPosCal] consider 2 rank data
2581 10:52:30.149905 u2DelayCellTimex100 = 270/100 ps
2582 10:52:30.153045 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2583 10:52:30.156537 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2584 10:52:30.162540 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2585 10:52:30.166024 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2586 10:52:30.169210 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2587 10:52:30.172666 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2588 10:52:30.172746
2589 10:52:30.176172 CA PerBit enable=1, Macro0, CA PI delay=33
2590 10:52:30.176265
2591 10:52:30.179235 [CBTSetCACLKResult] CA Dly = 33
2592 10:52:30.179327 CS Dly: 9 (0~41)
2593 10:52:30.179392
2594 10:52:30.182985 ----->DramcWriteLeveling(PI) begin...
2595 10:52:30.186149 ==
2596 10:52:30.189617 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 10:52:30.193193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 10:52:30.193279 ==
2599 10:52:30.196233 Write leveling (Byte 0): 33 => 33
2600 10:52:30.199430 Write leveling (Byte 1): 30 => 30
2601 10:52:30.202514 DramcWriteLeveling(PI) end<-----
2602 10:52:30.202597
2603 10:52:30.202687 ==
2604 10:52:30.206027 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 10:52:30.209680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 10:52:30.209844 ==
2607 10:52:30.212710 [Gating] SW mode calibration
2608 10:52:30.219213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2609 10:52:30.225915 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2610 10:52:30.228726 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2611 10:52:30.232151 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2612 10:52:30.239313 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2613 10:52:30.242073 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 10:52:30.245724 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 10:52:30.252383 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2616 10:52:30.255235 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2617 10:52:30.258599 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
2618 10:52:30.265339 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2619 10:52:30.268667 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 10:52:30.272181 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 10:52:30.276006 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 10:52:30.282581 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 10:52:30.285524 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 10:52:30.289011 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 10:52:30.295684 1 0 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
2626 10:52:30.298513 1 1 0 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2627 10:52:30.302083 1 1 4 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2628 10:52:30.308774 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 10:52:30.312983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 10:52:30.315608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 10:52:30.321616 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 10:52:30.325544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 10:52:30.328279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2634 10:52:30.335420 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2635 10:52:30.338062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2636 10:52:30.342114 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 10:52:30.348321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 10:52:30.351571 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 10:52:30.354898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 10:52:30.361702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 10:52:30.364647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 10:52:30.367742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 10:52:30.374830 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 10:52:30.378156 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 10:52:30.381810 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 10:52:30.388316 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 10:52:30.391230 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 10:52:30.394858 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 10:52:30.401131 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2650 10:52:30.404487 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2651 10:52:30.407710 Total UI for P1: 0, mck2ui 16
2652 10:52:30.411423 best dqsien dly found for B0: ( 1, 3, 28)
2653 10:52:30.414294 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2654 10:52:30.421596 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2655 10:52:30.421681 Total UI for P1: 0, mck2ui 16
2656 10:52:30.427831 best dqsien dly found for B1: ( 1, 4, 2)
2657 10:52:30.431040 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2658 10:52:30.434284 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2659 10:52:30.434363
2660 10:52:30.437838 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2661 10:52:30.440803 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2662 10:52:30.444108 [Gating] SW calibration Done
2663 10:52:30.444186 ==
2664 10:52:30.447650 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 10:52:30.450725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 10:52:30.450807 ==
2667 10:52:30.454340 RX Vref Scan: 0
2668 10:52:30.454419
2669 10:52:30.454483 RX Vref 0 -> 0, step: 1
2670 10:52:30.454548
2671 10:52:30.457735 RX Delay -40 -> 252, step: 8
2672 10:52:30.460871 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2673 10:52:30.467239 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2674 10:52:30.470902 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2675 10:52:30.474348 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2676 10:52:30.477428 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2677 10:52:30.481048 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2678 10:52:30.487624 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2679 10:52:30.490805 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2680 10:52:30.494349 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2681 10:52:30.497780 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2682 10:52:30.500448 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2683 10:52:30.507332 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2684 10:52:30.510590 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2685 10:52:30.513798 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2686 10:52:30.517204 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2687 10:52:30.521045 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2688 10:52:30.523962 ==
2689 10:52:30.527576 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 10:52:30.530054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 10:52:30.530140 ==
2692 10:52:30.530206 DQS Delay:
2693 10:52:30.534096 DQS0 = 0, DQS1 = 0
2694 10:52:30.534206 DQM Delay:
2695 10:52:30.537023 DQM0 = 119, DQM1 = 106
2696 10:52:30.537108 DQ Delay:
2697 10:52:30.540562 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2698 10:52:30.543529 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2699 10:52:30.546727 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2700 10:52:30.550010 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2701 10:52:30.550090
2702 10:52:30.550187
2703 10:52:30.550268 ==
2704 10:52:30.553300 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 10:52:30.560145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 10:52:30.560228 ==
2707 10:52:30.560298
2708 10:52:30.560373
2709 10:52:30.560432 TX Vref Scan disable
2710 10:52:30.563412 == TX Byte 0 ==
2711 10:52:30.567430 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2712 10:52:30.573266 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2713 10:52:30.573363 == TX Byte 1 ==
2714 10:52:30.576729 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2715 10:52:30.583761 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2716 10:52:30.583856 ==
2717 10:52:30.586752 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 10:52:30.590420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 10:52:30.590514 ==
2720 10:52:30.601646 TX Vref=22, minBit 7, minWin=25, winSum=418
2721 10:52:30.604841 TX Vref=24, minBit 1, minWin=26, winSum=426
2722 10:52:30.608069 TX Vref=26, minBit 14, minWin=26, winSum=432
2723 10:52:30.611509 TX Vref=28, minBit 4, minWin=26, winSum=435
2724 10:52:30.615205 TX Vref=30, minBit 5, minWin=26, winSum=432
2725 10:52:30.622210 TX Vref=32, minBit 4, minWin=26, winSum=428
2726 10:52:30.625388 [TxChooseVref] Worse bit 4, Min win 26, Win sum 435, Final Vref 28
2727 10:52:30.625469
2728 10:52:30.628189 Final TX Range 1 Vref 28
2729 10:52:30.628335
2730 10:52:30.628433 ==
2731 10:52:30.631809 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 10:52:30.634958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 10:52:30.635082 ==
2734 10:52:30.638467
2735 10:52:30.638622
2736 10:52:30.638719 TX Vref Scan disable
2737 10:52:30.641626 == TX Byte 0 ==
2738 10:52:30.644627 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2739 10:52:30.651488 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2740 10:52:30.651571 == TX Byte 1 ==
2741 10:52:30.654462 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2742 10:52:30.660990 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2743 10:52:30.661080
2744 10:52:30.661149 [DATLAT]
2745 10:52:30.661212 Freq=1200, CH0 RK0
2746 10:52:30.661273
2747 10:52:30.664429 DATLAT Default: 0xd
2748 10:52:30.668176 0, 0xFFFF, sum = 0
2749 10:52:30.668263 1, 0xFFFF, sum = 0
2750 10:52:30.670915 2, 0xFFFF, sum = 0
2751 10:52:30.670990 3, 0xFFFF, sum = 0
2752 10:52:30.674185 4, 0xFFFF, sum = 0
2753 10:52:30.674258 5, 0xFFFF, sum = 0
2754 10:52:30.677427 6, 0xFFFF, sum = 0
2755 10:52:30.677512 7, 0xFFFF, sum = 0
2756 10:52:30.681336 8, 0xFFFF, sum = 0
2757 10:52:30.681423 9, 0xFFFF, sum = 0
2758 10:52:30.684760 10, 0xFFFF, sum = 0
2759 10:52:30.684846 11, 0xFFFF, sum = 0
2760 10:52:30.687613 12, 0x0, sum = 1
2761 10:52:30.687699 13, 0x0, sum = 2
2762 10:52:30.691057 14, 0x0, sum = 3
2763 10:52:30.691142 15, 0x0, sum = 4
2764 10:52:30.694274 best_step = 13
2765 10:52:30.694357
2766 10:52:30.694424 ==
2767 10:52:30.697533 Dram Type= 6, Freq= 0, CH_0, rank 0
2768 10:52:30.700757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2769 10:52:30.700842 ==
2770 10:52:30.703978 RX Vref Scan: 1
2771 10:52:30.704088
2772 10:52:30.704183 Set Vref Range= 32 -> 127
2773 10:52:30.704273
2774 10:52:30.707568 RX Vref 32 -> 127, step: 1
2775 10:52:30.707652
2776 10:52:30.710771 RX Delay -21 -> 252, step: 4
2777 10:52:30.710855
2778 10:52:30.714763 Set Vref, RX VrefLevel [Byte0]: 32
2779 10:52:30.717406 [Byte1]: 32
2780 10:52:30.717490
2781 10:52:30.720660 Set Vref, RX VrefLevel [Byte0]: 33
2782 10:52:30.724112 [Byte1]: 33
2783 10:52:30.727842
2784 10:52:30.727927 Set Vref, RX VrefLevel [Byte0]: 34
2785 10:52:30.731218 [Byte1]: 34
2786 10:52:30.736001
2787 10:52:30.736084 Set Vref, RX VrefLevel [Byte0]: 35
2788 10:52:30.739393 [Byte1]: 35
2789 10:52:30.743666
2790 10:52:30.743750 Set Vref, RX VrefLevel [Byte0]: 36
2791 10:52:30.747033 [Byte1]: 36
2792 10:52:30.751821
2793 10:52:30.751905 Set Vref, RX VrefLevel [Byte0]: 37
2794 10:52:30.755322 [Byte1]: 37
2795 10:52:30.759425
2796 10:52:30.759509 Set Vref, RX VrefLevel [Byte0]: 38
2797 10:52:30.763151 [Byte1]: 38
2798 10:52:30.767792
2799 10:52:30.767876 Set Vref, RX VrefLevel [Byte0]: 39
2800 10:52:30.770945 [Byte1]: 39
2801 10:52:30.775981
2802 10:52:30.776065 Set Vref, RX VrefLevel [Byte0]: 40
2803 10:52:30.779311 [Byte1]: 40
2804 10:52:30.783887
2805 10:52:30.783971 Set Vref, RX VrefLevel [Byte0]: 41
2806 10:52:30.787260 [Byte1]: 41
2807 10:52:30.791287
2808 10:52:30.791391 Set Vref, RX VrefLevel [Byte0]: 42
2809 10:52:30.794603 [Byte1]: 42
2810 10:52:30.799121
2811 10:52:30.799236 Set Vref, RX VrefLevel [Byte0]: 43
2812 10:52:30.802445 [Byte1]: 43
2813 10:52:30.807453
2814 10:52:30.807537 Set Vref, RX VrefLevel [Byte0]: 44
2815 10:52:30.810692 [Byte1]: 44
2816 10:52:30.815279
2817 10:52:30.815391 Set Vref, RX VrefLevel [Byte0]: 45
2818 10:52:30.818118 [Byte1]: 45
2819 10:52:30.823230
2820 10:52:30.823314 Set Vref, RX VrefLevel [Byte0]: 46
2821 10:52:30.826333 [Byte1]: 46
2822 10:52:30.830914
2823 10:52:30.830999 Set Vref, RX VrefLevel [Byte0]: 47
2824 10:52:30.834007 [Byte1]: 47
2825 10:52:30.838989
2826 10:52:30.839077 Set Vref, RX VrefLevel [Byte0]: 48
2827 10:52:30.842361 [Byte1]: 48
2828 10:52:30.846672
2829 10:52:30.846756 Set Vref, RX VrefLevel [Byte0]: 49
2830 10:52:30.849951 [Byte1]: 49
2831 10:52:30.854461
2832 10:52:30.854544 Set Vref, RX VrefLevel [Byte0]: 50
2833 10:52:30.858254 [Byte1]: 50
2834 10:52:30.862659
2835 10:52:30.862742 Set Vref, RX VrefLevel [Byte0]: 51
2836 10:52:30.865849 [Byte1]: 51
2837 10:52:30.870875
2838 10:52:30.870959 Set Vref, RX VrefLevel [Byte0]: 52
2839 10:52:30.873739 [Byte1]: 52
2840 10:52:30.878475
2841 10:52:30.878599 Set Vref, RX VrefLevel [Byte0]: 53
2842 10:52:30.882071 [Byte1]: 53
2843 10:52:30.886365
2844 10:52:30.886448 Set Vref, RX VrefLevel [Byte0]: 54
2845 10:52:30.890147 [Byte1]: 54
2846 10:52:30.894396
2847 10:52:30.894509 Set Vref, RX VrefLevel [Byte0]: 55
2848 10:52:30.897942 [Byte1]: 55
2849 10:52:30.902432
2850 10:52:30.902515 Set Vref, RX VrefLevel [Byte0]: 56
2851 10:52:30.905916 [Byte1]: 56
2852 10:52:30.910256
2853 10:52:30.910339 Set Vref, RX VrefLevel [Byte0]: 57
2854 10:52:30.913300 [Byte1]: 57
2855 10:52:30.918159
2856 10:52:30.918242 Set Vref, RX VrefLevel [Byte0]: 58
2857 10:52:30.921195 [Byte1]: 58
2858 10:52:30.926078
2859 10:52:30.926197 Set Vref, RX VrefLevel [Byte0]: 59
2860 10:52:30.929512 [Byte1]: 59
2861 10:52:30.934011
2862 10:52:30.934118 Set Vref, RX VrefLevel [Byte0]: 60
2863 10:52:30.937865 [Byte1]: 60
2864 10:52:30.942139
2865 10:52:30.942319 Set Vref, RX VrefLevel [Byte0]: 61
2866 10:52:30.945245 [Byte1]: 61
2867 10:52:30.949733
2868 10:52:30.949885 Set Vref, RX VrefLevel [Byte0]: 62
2869 10:52:30.953450 [Byte1]: 62
2870 10:52:30.957496
2871 10:52:30.957630 Set Vref, RX VrefLevel [Byte0]: 63
2872 10:52:30.961689 [Byte1]: 63
2873 10:52:30.965568
2874 10:52:30.965691 Set Vref, RX VrefLevel [Byte0]: 64
2875 10:52:30.969094 [Byte1]: 64
2876 10:52:30.973499
2877 10:52:30.973630 Set Vref, RX VrefLevel [Byte0]: 65
2878 10:52:30.976778 [Byte1]: 65
2879 10:52:30.981634
2880 10:52:30.981758 Set Vref, RX VrefLevel [Byte0]: 66
2881 10:52:30.985074 [Byte1]: 66
2882 10:52:30.989201
2883 10:52:30.989320 Set Vref, RX VrefLevel [Byte0]: 67
2884 10:52:30.992523 [Byte1]: 67
2885 10:52:30.997303
2886 10:52:30.997392 Set Vref, RX VrefLevel [Byte0]: 68
2887 10:52:31.000879 [Byte1]: 68
2888 10:52:31.005277
2889 10:52:31.005370 Set Vref, RX VrefLevel [Byte0]: 69
2890 10:52:31.009208 [Byte1]: 69
2891 10:52:31.013453
2892 10:52:31.013541 Set Vref, RX VrefLevel [Byte0]: 70
2893 10:52:31.016676 [Byte1]: 70
2894 10:52:31.021131
2895 10:52:31.021217 Set Vref, RX VrefLevel [Byte0]: 71
2896 10:52:31.024254 [Byte1]: 71
2897 10:52:31.029075
2898 10:52:31.029162 Set Vref, RX VrefLevel [Byte0]: 72
2899 10:52:31.032279 [Byte1]: 72
2900 10:52:31.037289
2901 10:52:31.037376 Set Vref, RX VrefLevel [Byte0]: 73
2902 10:52:31.041054 [Byte1]: 73
2903 10:52:31.044749
2904 10:52:31.044866 Set Vref, RX VrefLevel [Byte0]: 74
2905 10:52:31.048029 [Byte1]: 74
2906 10:52:31.052469
2907 10:52:31.056422 Set Vref, RX VrefLevel [Byte0]: 75
2908 10:52:31.059237 [Byte1]: 75
2909 10:52:31.059326
2910 10:52:31.062347 Set Vref, RX VrefLevel [Byte0]: 76
2911 10:52:31.066136 [Byte1]: 76
2912 10:52:31.066222
2913 10:52:31.069356 Set Vref, RX VrefLevel [Byte0]: 77
2914 10:52:31.072649 [Byte1]: 77
2915 10:52:31.076474
2916 10:52:31.076612 Set Vref, RX VrefLevel [Byte0]: 78
2917 10:52:31.079854 [Byte1]: 78
2918 10:52:31.084661
2919 10:52:31.084750 Set Vref, RX VrefLevel [Byte0]: 79
2920 10:52:31.087646 [Byte1]: 79
2921 10:52:31.092220
2922 10:52:31.092332 Final RX Vref Byte 0 = 55 to rank0
2923 10:52:31.095763 Final RX Vref Byte 1 = 49 to rank0
2924 10:52:31.099016 Final RX Vref Byte 0 = 55 to rank1
2925 10:52:31.102377 Final RX Vref Byte 1 = 49 to rank1==
2926 10:52:31.105920 Dram Type= 6, Freq= 0, CH_0, rank 0
2927 10:52:31.112488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 10:52:31.112625 ==
2929 10:52:31.112692 DQS Delay:
2930 10:52:31.112754 DQS0 = 0, DQS1 = 0
2931 10:52:31.115662 DQM Delay:
2932 10:52:31.115746 DQM0 = 118, DQM1 = 106
2933 10:52:31.119360 DQ Delay:
2934 10:52:31.122801 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2935 10:52:31.125828 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2936 10:52:31.129112 DQ8 =98, DQ9 =92, DQ10 =108, DQ11 =100
2937 10:52:31.132570 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2938 10:52:31.132661
2939 10:52:31.132724
2940 10:52:31.138853 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2941 10:52:31.142085 CH0 RK0: MR19=403, MR18=EFA
2942 10:52:31.148769 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2943 10:52:31.148852
2944 10:52:31.152034 ----->DramcWriteLeveling(PI) begin...
2945 10:52:31.152135 ==
2946 10:52:31.155757 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 10:52:31.158987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 10:52:31.162504 ==
2949 10:52:31.162586 Write leveling (Byte 0): 34 => 34
2950 10:52:31.165671 Write leveling (Byte 1): 31 => 31
2951 10:52:31.168833 DramcWriteLeveling(PI) end<-----
2952 10:52:31.168916
2953 10:52:31.169006 ==
2954 10:52:31.172228 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 10:52:31.179031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 10:52:31.179133 ==
2957 10:52:31.181918 [Gating] SW mode calibration
2958 10:52:31.188703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2959 10:52:31.191923 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2960 10:52:31.198432 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2961 10:52:31.202228 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2962 10:52:31.205220 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 10:52:31.211863 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 10:52:31.214925 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 10:52:31.218305 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 10:52:31.224865 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 10:52:31.228059 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2968 10:52:31.231681 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2969 10:52:31.235032 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2970 10:52:31.241582 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 10:52:31.244972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 10:52:31.248113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 10:52:31.255140 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 10:52:31.257896 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 10:52:31.261669 1 0 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
2976 10:52:31.268181 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2977 10:52:31.271428 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 10:52:31.274510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 10:52:31.281467 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 10:52:31.284805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 10:52:31.288368 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 10:52:31.294354 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 10:52:31.297633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2984 10:52:31.301230 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2985 10:52:31.308009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 10:52:31.311525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 10:52:31.314226 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 10:52:31.321056 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 10:52:31.324133 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 10:52:31.327748 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 10:52:31.334597 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 10:52:31.337382 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 10:52:31.341360 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 10:52:31.347584 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 10:52:31.350866 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 10:52:31.354173 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 10:52:31.360649 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 10:52:31.363942 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2999 10:52:31.367524 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3000 10:52:31.374132 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3001 10:52:31.374238 Total UI for P1: 0, mck2ui 16
3002 10:52:31.380744 best dqsien dly found for B0: ( 1, 3, 26)
3003 10:52:31.383575 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3004 10:52:31.387440 Total UI for P1: 0, mck2ui 16
3005 10:52:31.390517 best dqsien dly found for B1: ( 1, 4, 0)
3006 10:52:31.393756 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3007 10:52:31.396943 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3008 10:52:31.397048
3009 10:52:31.400111 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3010 10:52:31.403652 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3011 10:52:31.407097 [Gating] SW calibration Done
3012 10:52:31.407195 ==
3013 10:52:31.410401 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 10:52:31.414024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 10:52:31.416743 ==
3016 10:52:31.416839 RX Vref Scan: 0
3017 10:52:31.416926
3018 10:52:31.420143 RX Vref 0 -> 0, step: 1
3019 10:52:31.420228
3020 10:52:31.420295 RX Delay -40 -> 252, step: 8
3021 10:52:31.427029 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3022 10:52:31.430917 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3023 10:52:31.434114 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3024 10:52:31.437453 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3025 10:52:31.440246 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3026 10:52:31.447697 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
3027 10:52:31.450966 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3028 10:52:31.453572 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3029 10:52:31.456986 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3030 10:52:31.460881 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3031 10:52:31.466942 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3032 10:52:31.470602 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3033 10:52:31.473665 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3034 10:52:31.477039 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3035 10:52:31.480670 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3036 10:52:31.486919 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3037 10:52:31.486997 ==
3038 10:52:31.490855 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 10:52:31.493268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 10:52:31.493351 ==
3041 10:52:31.493418 DQS Delay:
3042 10:52:31.496746 DQS0 = 0, DQS1 = 0
3043 10:52:31.496823 DQM Delay:
3044 10:52:31.500315 DQM0 = 117, DQM1 = 108
3045 10:52:31.500429 DQ Delay:
3046 10:52:31.503930 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3047 10:52:31.506617 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =127
3048 10:52:31.509808 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3049 10:52:31.513597 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3050 10:52:31.513682
3051 10:52:31.516653
3052 10:52:31.516737 ==
3053 10:52:31.519918 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 10:52:31.523375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 10:52:31.523460 ==
3056 10:52:31.523526
3057 10:52:31.523586
3058 10:52:31.526521 TX Vref Scan disable
3059 10:52:31.526630 == TX Byte 0 ==
3060 10:52:31.533142 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3061 10:52:31.536431 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3062 10:52:31.536576 == TX Byte 1 ==
3063 10:52:31.543367 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3064 10:52:31.546557 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3065 10:52:31.546641 ==
3066 10:52:31.549689 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 10:52:31.553828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 10:52:31.553929 ==
3069 10:52:31.565705 TX Vref=22, minBit 5, minWin=25, winSum=418
3070 10:52:31.569084 TX Vref=24, minBit 0, minWin=26, winSum=421
3071 10:52:31.572091 TX Vref=26, minBit 0, minWin=26, winSum=423
3072 10:52:31.575618 TX Vref=28, minBit 1, minWin=26, winSum=428
3073 10:52:31.578822 TX Vref=30, minBit 14, minWin=25, winSum=429
3074 10:52:31.585970 TX Vref=32, minBit 10, minWin=25, winSum=423
3075 10:52:31.589039 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3076 10:52:31.589123
3077 10:52:31.592215 Final TX Range 1 Vref 28
3078 10:52:31.592326
3079 10:52:31.592425 ==
3080 10:52:31.595313 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 10:52:31.599038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 10:52:31.602068 ==
3083 10:52:31.602152
3084 10:52:31.602218
3085 10:52:31.602277 TX Vref Scan disable
3086 10:52:31.605411 == TX Byte 0 ==
3087 10:52:31.609051 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3088 10:52:31.612406 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3089 10:52:31.616008 == TX Byte 1 ==
3090 10:52:31.619124 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3091 10:52:31.625696 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3092 10:52:31.625780
3093 10:52:31.625862 [DATLAT]
3094 10:52:31.625940 Freq=1200, CH0 RK1
3095 10:52:31.625999
3096 10:52:31.628851 DATLAT Default: 0xd
3097 10:52:31.628935 0, 0xFFFF, sum = 0
3098 10:52:31.632008 1, 0xFFFF, sum = 0
3099 10:52:31.632122 2, 0xFFFF, sum = 0
3100 10:52:31.635529 3, 0xFFFF, sum = 0
3101 10:52:31.638795 4, 0xFFFF, sum = 0
3102 10:52:31.638881 5, 0xFFFF, sum = 0
3103 10:52:31.642400 6, 0xFFFF, sum = 0
3104 10:52:31.642485 7, 0xFFFF, sum = 0
3105 10:52:31.645588 8, 0xFFFF, sum = 0
3106 10:52:31.645674 9, 0xFFFF, sum = 0
3107 10:52:31.649339 10, 0xFFFF, sum = 0
3108 10:52:31.649424 11, 0xFFFF, sum = 0
3109 10:52:31.652030 12, 0x0, sum = 1
3110 10:52:31.652147 13, 0x0, sum = 2
3111 10:52:31.655699 14, 0x0, sum = 3
3112 10:52:31.655785 15, 0x0, sum = 4
3113 10:52:31.658725 best_step = 13
3114 10:52:31.658808
3115 10:52:31.658875 ==
3116 10:52:31.661836 Dram Type= 6, Freq= 0, CH_0, rank 1
3117 10:52:31.665425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 10:52:31.665510 ==
3119 10:52:31.665576 RX Vref Scan: 0
3120 10:52:31.665639
3121 10:52:31.668877 RX Vref 0 -> 0, step: 1
3122 10:52:31.668961
3123 10:52:31.672651 RX Delay -21 -> 252, step: 4
3124 10:52:31.675349 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3125 10:52:31.681917 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3126 10:52:31.685409 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3127 10:52:31.688693 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3128 10:52:31.692020 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3129 10:52:31.695195 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3130 10:52:31.702120 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3131 10:52:31.705247 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3132 10:52:31.708645 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3133 10:52:31.711929 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3134 10:52:31.715068 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3135 10:52:31.721813 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3136 10:52:31.725066 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3137 10:52:31.728393 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3138 10:52:31.731653 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3139 10:52:31.734941 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3140 10:52:31.738447 ==
3141 10:52:31.741722 Dram Type= 6, Freq= 0, CH_0, rank 1
3142 10:52:31.745020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 10:52:31.745105 ==
3144 10:52:31.745172 DQS Delay:
3145 10:52:31.748657 DQS0 = 0, DQS1 = 0
3146 10:52:31.748768 DQM Delay:
3147 10:52:31.751510 DQM0 = 116, DQM1 = 107
3148 10:52:31.751595 DQ Delay:
3149 10:52:31.755222 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3150 10:52:31.758283 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3151 10:52:31.761948 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3152 10:52:31.765295 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3153 10:52:31.765379
3154 10:52:31.765466
3155 10:52:31.774902 [DQSOSCAuto] RK1, (LSB)MR18= 0xee9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3156 10:52:31.774989 CH0 RK1: MR19=403, MR18=EE9
3157 10:52:31.782081 CH0_RK1: MR19=0x403, MR18=0xEE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3158 10:52:31.784643 [RxdqsGatingPostProcess] freq 1200
3159 10:52:31.791591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3160 10:52:31.794902 best DQS0 dly(2T, 0.5T) = (0, 11)
3161 10:52:31.798235 best DQS1 dly(2T, 0.5T) = (0, 12)
3162 10:52:31.801327 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3163 10:52:31.804903 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3164 10:52:31.808188 best DQS0 dly(2T, 0.5T) = (0, 11)
3165 10:52:31.811156 best DQS1 dly(2T, 0.5T) = (0, 12)
3166 10:52:31.811241 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3167 10:52:31.814655 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3168 10:52:31.817929 Pre-setting of DQS Precalculation
3169 10:52:31.824709 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3170 10:52:31.824794 ==
3171 10:52:31.827981 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 10:52:31.831264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 10:52:31.831348 ==
3174 10:52:31.837803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3175 10:52:31.844358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3176 10:52:31.851665 [CA 0] Center 37 (7~67) winsize 61
3177 10:52:31.855674 [CA 1] Center 38 (8~68) winsize 61
3178 10:52:31.858560 [CA 2] Center 34 (4~64) winsize 61
3179 10:52:31.862109 [CA 3] Center 33 (3~64) winsize 62
3180 10:52:31.864909 [CA 4] Center 34 (4~64) winsize 61
3181 10:52:31.868372 [CA 5] Center 33 (3~64) winsize 62
3182 10:52:31.868483
3183 10:52:31.871683 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3184 10:52:31.871768
3185 10:52:31.874700 [CATrainingPosCal] consider 1 rank data
3186 10:52:31.878244 u2DelayCellTimex100 = 270/100 ps
3187 10:52:31.881214 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3188 10:52:31.887715 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3189 10:52:31.891685 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3190 10:52:31.894581 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3191 10:52:31.897868 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3192 10:52:31.901495 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3193 10:52:31.901596
3194 10:52:31.904940 CA PerBit enable=1, Macro0, CA PI delay=33
3195 10:52:31.905024
3196 10:52:31.907592 [CBTSetCACLKResult] CA Dly = 33
3197 10:52:31.910906 CS Dly: 5 (0~36)
3198 10:52:31.910989 ==
3199 10:52:31.914971 Dram Type= 6, Freq= 0, CH_1, rank 1
3200 10:52:31.917752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 10:52:31.917852 ==
3202 10:52:31.924154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3203 10:52:31.927475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3204 10:52:31.937335 [CA 0] Center 37 (7~67) winsize 61
3205 10:52:31.940399 [CA 1] Center 38 (8~68) winsize 61
3206 10:52:31.943752 [CA 2] Center 34 (3~65) winsize 63
3207 10:52:31.947189 [CA 3] Center 33 (3~64) winsize 62
3208 10:52:31.950637 [CA 4] Center 34 (3~65) winsize 63
3209 10:52:31.953931 [CA 5] Center 33 (3~64) winsize 62
3210 10:52:31.954015
3211 10:52:31.957000 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3212 10:52:31.957085
3213 10:52:31.960480 [CATrainingPosCal] consider 2 rank data
3214 10:52:31.963719 u2DelayCellTimex100 = 270/100 ps
3215 10:52:31.967330 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3216 10:52:31.973875 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3217 10:52:31.977068 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3218 10:52:31.980338 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3219 10:52:31.983508 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3220 10:52:31.986781 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3221 10:52:31.986896
3222 10:52:31.990270 CA PerBit enable=1, Macro0, CA PI delay=33
3223 10:52:31.990354
3224 10:52:31.993630 [CBTSetCACLKResult] CA Dly = 33
3225 10:52:31.996703 CS Dly: 7 (0~40)
3226 10:52:31.996788
3227 10:52:32.000377 ----->DramcWriteLeveling(PI) begin...
3228 10:52:32.000488 ==
3229 10:52:32.003560 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 10:52:32.006646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 10:52:32.006731 ==
3232 10:52:32.010593 Write leveling (Byte 0): 26 => 26
3233 10:52:32.013730 Write leveling (Byte 1): 28 => 28
3234 10:52:32.016667 DramcWriteLeveling(PI) end<-----
3235 10:52:32.016751
3236 10:52:32.016817 ==
3237 10:52:32.020148 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 10:52:32.023421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 10:52:32.023506 ==
3240 10:52:32.027067 [Gating] SW mode calibration
3241 10:52:32.033167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3242 10:52:32.040237 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3243 10:52:32.043381 0 15 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
3244 10:52:32.046374 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 10:52:32.052900 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3246 10:52:32.056540 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3247 10:52:32.059859 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 10:52:32.066307 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3249 10:52:32.069454 0 15 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
3250 10:52:32.072865 0 15 28 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
3251 10:52:32.079526 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 10:52:32.083249 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 10:52:32.086398 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 10:52:32.092950 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 10:52:32.096176 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 10:52:32.099939 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3257 10:52:32.106388 1 0 24 | B1->B0 | 2828 4040 | 0 1 | (0 0) (0 0)
3258 10:52:32.109550 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3259 10:52:32.112780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 10:52:32.119113 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 10:52:32.122666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 10:52:32.126203 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 10:52:32.132676 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 10:52:32.135845 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3265 10:52:32.139386 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3266 10:52:32.145657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3267 10:52:32.149442 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3268 10:52:32.152348 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 10:52:32.159525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 10:52:32.162371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 10:52:32.165650 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 10:52:32.169673 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 10:52:32.175660 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 10:52:32.178796 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 10:52:32.182024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 10:52:32.189056 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 10:52:32.192145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 10:52:32.195606 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 10:52:32.202026 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 10:52:32.205523 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 10:52:32.209099 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3282 10:52:32.215700 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3283 10:52:32.218911 Total UI for P1: 0, mck2ui 16
3284 10:52:32.221938 best dqsien dly found for B0: ( 1, 3, 24)
3285 10:52:32.225078 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 10:52:32.228367 Total UI for P1: 0, mck2ui 16
3287 10:52:32.232174 best dqsien dly found for B1: ( 1, 3, 26)
3288 10:52:32.235381 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3289 10:52:32.238803 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3290 10:52:32.238887
3291 10:52:32.241723 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3292 10:52:32.245663 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3293 10:52:32.248491 [Gating] SW calibration Done
3294 10:52:32.248613 ==
3295 10:52:32.251686 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 10:52:32.258550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 10:52:32.258634 ==
3298 10:52:32.258701 RX Vref Scan: 0
3299 10:52:32.258762
3300 10:52:32.261657 RX Vref 0 -> 0, step: 1
3301 10:52:32.261768
3302 10:52:32.265100 RX Delay -40 -> 252, step: 8
3303 10:52:32.268661 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3304 10:52:32.271731 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3305 10:52:32.275276 iDelay=208, Bit 2, Center 115 (48 ~ 183) 136
3306 10:52:32.281723 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3307 10:52:32.284801 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3308 10:52:32.288497 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3309 10:52:32.291476 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3310 10:52:32.295767 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3311 10:52:32.298284 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3312 10:52:32.304796 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3313 10:52:32.308482 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3314 10:52:32.311741 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3315 10:52:32.315117 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3316 10:52:32.318489 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3317 10:52:32.324768 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3318 10:52:32.327930 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3319 10:52:32.328033 ==
3320 10:52:32.331323 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 10:52:32.335100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 10:52:32.335183 ==
3323 10:52:32.337995 DQS Delay:
3324 10:52:32.338078 DQS0 = 0, DQS1 = 0
3325 10:52:32.338144 DQM Delay:
3326 10:52:32.341183 DQM0 = 120, DQM1 = 110
3327 10:52:32.341266 DQ Delay:
3328 10:52:32.344454 DQ0 =123, DQ1 =115, DQ2 =115, DQ3 =119
3329 10:52:32.347653 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3330 10:52:32.351293 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3331 10:52:32.357855 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3332 10:52:32.357939
3333 10:52:32.358036
3334 10:52:32.358147 ==
3335 10:52:32.361179 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 10:52:32.364387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 10:52:32.364471 ==
3338 10:52:32.364593
3339 10:52:32.364669
3340 10:52:32.367767 TX Vref Scan disable
3341 10:52:32.367850 == TX Byte 0 ==
3342 10:52:32.375291 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3343 10:52:32.377543 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3344 10:52:32.377627 == TX Byte 1 ==
3345 10:52:32.384341 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3346 10:52:32.387648 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3347 10:52:32.387732 ==
3348 10:52:32.390830 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 10:52:32.394343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 10:52:32.394427 ==
3351 10:52:32.407073 TX Vref=22, minBit 11, minWin=25, winSum=418
3352 10:52:32.410415 TX Vref=24, minBit 1, minWin=25, winSum=422
3353 10:52:32.415047 TX Vref=26, minBit 0, minWin=26, winSum=428
3354 10:52:32.417259 TX Vref=28, minBit 1, minWin=26, winSum=433
3355 10:52:32.420238 TX Vref=30, minBit 3, minWin=26, winSum=430
3356 10:52:32.426837 TX Vref=32, minBit 1, minWin=26, winSum=426
3357 10:52:32.430367 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3358 10:52:32.430451
3359 10:52:32.433858 Final TX Range 1 Vref 28
3360 10:52:32.433941
3361 10:52:32.434005 ==
3362 10:52:32.437037 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 10:52:32.440235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 10:52:32.443284 ==
3365 10:52:32.443365
3366 10:52:32.443429
3367 10:52:32.443488 TX Vref Scan disable
3368 10:52:32.447102 == TX Byte 0 ==
3369 10:52:32.450851 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3370 10:52:32.453810 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3371 10:52:32.456735 == TX Byte 1 ==
3372 10:52:32.460380 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3373 10:52:32.467083 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3374 10:52:32.467167
3375 10:52:32.467230 [DATLAT]
3376 10:52:32.467289 Freq=1200, CH1 RK0
3377 10:52:32.467347
3378 10:52:32.470089 DATLAT Default: 0xd
3379 10:52:32.470169 0, 0xFFFF, sum = 0
3380 10:52:32.473856 1, 0xFFFF, sum = 0
3381 10:52:32.476639 2, 0xFFFF, sum = 0
3382 10:52:32.476722 3, 0xFFFF, sum = 0
3383 10:52:32.480321 4, 0xFFFF, sum = 0
3384 10:52:32.480403 5, 0xFFFF, sum = 0
3385 10:52:32.483318 6, 0xFFFF, sum = 0
3386 10:52:32.483400 7, 0xFFFF, sum = 0
3387 10:52:32.486743 8, 0xFFFF, sum = 0
3388 10:52:32.486826 9, 0xFFFF, sum = 0
3389 10:52:32.489697 10, 0xFFFF, sum = 0
3390 10:52:32.489779 11, 0xFFFF, sum = 0
3391 10:52:32.493410 12, 0x0, sum = 1
3392 10:52:32.493492 13, 0x0, sum = 2
3393 10:52:32.496361 14, 0x0, sum = 3
3394 10:52:32.496443 15, 0x0, sum = 4
3395 10:52:32.499983 best_step = 13
3396 10:52:32.500064
3397 10:52:32.500126 ==
3398 10:52:32.503483 Dram Type= 6, Freq= 0, CH_1, rank 0
3399 10:52:32.506588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3400 10:52:32.506669 ==
3401 10:52:32.506734 RX Vref Scan: 1
3402 10:52:32.506792
3403 10:52:32.509936 Set Vref Range= 32 -> 127
3404 10:52:32.510018
3405 10:52:32.513414 RX Vref 32 -> 127, step: 1
3406 10:52:32.513496
3407 10:52:32.516621 RX Delay -21 -> 252, step: 4
3408 10:52:32.516702
3409 10:52:32.520077 Set Vref, RX VrefLevel [Byte0]: 32
3410 10:52:32.523089 [Byte1]: 32
3411 10:52:32.523171
3412 10:52:32.526736 Set Vref, RX VrefLevel [Byte0]: 33
3413 10:52:32.529701 [Byte1]: 33
3414 10:52:32.534776
3415 10:52:32.534858 Set Vref, RX VrefLevel [Byte0]: 34
3416 10:52:32.536761 [Byte1]: 34
3417 10:52:32.541129
3418 10:52:32.541210 Set Vref, RX VrefLevel [Byte0]: 35
3419 10:52:32.544477 [Byte1]: 35
3420 10:52:32.549322
3421 10:52:32.549403 Set Vref, RX VrefLevel [Byte0]: 36
3422 10:52:32.552659 [Byte1]: 36
3423 10:52:32.557105
3424 10:52:32.557187 Set Vref, RX VrefLevel [Byte0]: 37
3425 10:52:32.560485 [Byte1]: 37
3426 10:52:32.565178
3427 10:52:32.565260 Set Vref, RX VrefLevel [Byte0]: 38
3428 10:52:32.568282 [Byte1]: 38
3429 10:52:32.572829
3430 10:52:32.572910 Set Vref, RX VrefLevel [Byte0]: 39
3431 10:52:32.576629 [Byte1]: 39
3432 10:52:32.580807
3433 10:52:32.580888 Set Vref, RX VrefLevel [Byte0]: 40
3434 10:52:32.584310 [Byte1]: 40
3435 10:52:32.588671
3436 10:52:32.588755 Set Vref, RX VrefLevel [Byte0]: 41
3437 10:52:32.591951 [Byte1]: 41
3438 10:52:32.596536
3439 10:52:32.596619 Set Vref, RX VrefLevel [Byte0]: 42
3440 10:52:32.600319 [Byte1]: 42
3441 10:52:32.604410
3442 10:52:32.604495 Set Vref, RX VrefLevel [Byte0]: 43
3443 10:52:32.607879 [Byte1]: 43
3444 10:52:32.612444
3445 10:52:32.612551 Set Vref, RX VrefLevel [Byte0]: 44
3446 10:52:32.616057 [Byte1]: 44
3447 10:52:32.620458
3448 10:52:32.620577 Set Vref, RX VrefLevel [Byte0]: 45
3449 10:52:32.623972 [Byte1]: 45
3450 10:52:32.628547
3451 10:52:32.628630 Set Vref, RX VrefLevel [Byte0]: 46
3452 10:52:32.632140 [Byte1]: 46
3453 10:52:32.636152
3454 10:52:32.636235 Set Vref, RX VrefLevel [Byte0]: 47
3455 10:52:32.639548 [Byte1]: 47
3456 10:52:32.644280
3457 10:52:32.644363 Set Vref, RX VrefLevel [Byte0]: 48
3458 10:52:32.647807 [Byte1]: 48
3459 10:52:32.652429
3460 10:52:32.652516 Set Vref, RX VrefLevel [Byte0]: 49
3461 10:52:32.655682 [Byte1]: 49
3462 10:52:32.659955
3463 10:52:32.660038 Set Vref, RX VrefLevel [Byte0]: 50
3464 10:52:32.663251 [Byte1]: 50
3465 10:52:32.668270
3466 10:52:32.668354 Set Vref, RX VrefLevel [Byte0]: 51
3467 10:52:32.671176 [Byte1]: 51
3468 10:52:32.675788
3469 10:52:32.675872 Set Vref, RX VrefLevel [Byte0]: 52
3470 10:52:32.679402 [Byte1]: 52
3471 10:52:32.684037
3472 10:52:32.684120 Set Vref, RX VrefLevel [Byte0]: 53
3473 10:52:32.687018 [Byte1]: 53
3474 10:52:32.691830
3475 10:52:32.691914 Set Vref, RX VrefLevel [Byte0]: 54
3476 10:52:32.695174 [Byte1]: 54
3477 10:52:32.699586
3478 10:52:32.699669 Set Vref, RX VrefLevel [Byte0]: 55
3479 10:52:32.703068 [Byte1]: 55
3480 10:52:32.707462
3481 10:52:32.707546 Set Vref, RX VrefLevel [Byte0]: 56
3482 10:52:32.711328 [Byte1]: 56
3483 10:52:32.715289
3484 10:52:32.715373 Set Vref, RX VrefLevel [Byte0]: 57
3485 10:52:32.718749 [Byte1]: 57
3486 10:52:32.723396
3487 10:52:32.723481 Set Vref, RX VrefLevel [Byte0]: 58
3488 10:52:32.727259 [Byte1]: 58
3489 10:52:32.731843
3490 10:52:32.731926 Set Vref, RX VrefLevel [Byte0]: 59
3491 10:52:32.734599 [Byte1]: 59
3492 10:52:32.739285
3493 10:52:32.739368 Set Vref, RX VrefLevel [Byte0]: 60
3494 10:52:32.742932 [Byte1]: 60
3495 10:52:32.747681
3496 10:52:32.747764 Set Vref, RX VrefLevel [Byte0]: 61
3497 10:52:32.750589 [Byte1]: 61
3498 10:52:32.755100
3499 10:52:32.755183 Set Vref, RX VrefLevel [Byte0]: 62
3500 10:52:32.758582 [Byte1]: 62
3501 10:52:32.763247
3502 10:52:32.763332 Set Vref, RX VrefLevel [Byte0]: 63
3503 10:52:32.766631 [Byte1]: 63
3504 10:52:32.771130
3505 10:52:32.771214 Set Vref, RX VrefLevel [Byte0]: 64
3506 10:52:32.774556 [Byte1]: 64
3507 10:52:32.779037
3508 10:52:32.779121 Set Vref, RX VrefLevel [Byte0]: 65
3509 10:52:32.782099 [Byte1]: 65
3510 10:52:32.786626
3511 10:52:32.786710 Set Vref, RX VrefLevel [Byte0]: 66
3512 10:52:32.790288 [Byte1]: 66
3513 10:52:32.794896
3514 10:52:32.794979 Set Vref, RX VrefLevel [Byte0]: 67
3515 10:52:32.798200 [Byte1]: 67
3516 10:52:32.802589
3517 10:52:32.802673 Set Vref, RX VrefLevel [Byte0]: 68
3518 10:52:32.806259 [Byte1]: 68
3519 10:52:32.810663
3520 10:52:32.810747 Final RX Vref Byte 0 = 47 to rank0
3521 10:52:32.813970 Final RX Vref Byte 1 = 54 to rank0
3522 10:52:32.817366 Final RX Vref Byte 0 = 47 to rank1
3523 10:52:32.820420 Final RX Vref Byte 1 = 54 to rank1==
3524 10:52:32.824025 Dram Type= 6, Freq= 0, CH_1, rank 0
3525 10:52:32.830828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 10:52:32.830913 ==
3527 10:52:32.830979 DQS Delay:
3528 10:52:32.831040 DQS0 = 0, DQS1 = 0
3529 10:52:32.834028 DQM Delay:
3530 10:52:32.834111 DQM0 = 117, DQM1 = 112
3531 10:52:32.836861 DQ Delay:
3532 10:52:32.840447 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3533 10:52:32.843573 DQ4 =116, DQ5 =128, DQ6 =128, DQ7 =116
3534 10:52:32.847512 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =100
3535 10:52:32.850348 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3536 10:52:32.850430
3537 10:52:32.850500
3538 10:52:32.860392 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3539 10:52:32.860492 CH1 RK0: MR19=403, MR18=2F5
3540 10:52:32.866747 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3541 10:52:32.866831
3542 10:52:32.869960 ----->DramcWriteLeveling(PI) begin...
3543 10:52:32.870044 ==
3544 10:52:32.873611 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 10:52:32.879957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 10:52:32.880041 ==
3547 10:52:32.883454 Write leveling (Byte 0): 23 => 23
3548 10:52:32.883563 Write leveling (Byte 1): 28 => 28
3549 10:52:32.886920 DramcWriteLeveling(PI) end<-----
3550 10:52:32.887003
3551 10:52:32.890383 ==
3552 10:52:32.890465 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 10:52:32.896315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 10:52:32.896398 ==
3555 10:52:32.899902 [Gating] SW mode calibration
3556 10:52:32.906358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3557 10:52:32.909744 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3558 10:52:32.916180 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3559 10:52:32.919678 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 10:52:32.923670 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 10:52:32.929385 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3562 10:52:32.932674 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3563 10:52:32.936075 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3564 10:52:32.942206 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3565 10:52:32.945578 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
3566 10:52:32.948709 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3567 10:52:32.955651 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 10:52:32.958718 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 10:52:32.962290 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3570 10:52:32.968959 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3571 10:52:32.971896 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3572 10:52:32.976123 1 0 24 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
3573 10:52:32.981921 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
3574 10:52:32.985139 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 10:52:32.989184 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 10:52:32.994898 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 10:52:32.998171 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 10:52:33.001654 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 10:52:33.008318 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 10:52:33.011677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 10:52:33.014607 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3582 10:52:33.021317 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 10:52:33.024510 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 10:52:33.027888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 10:52:33.034914 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 10:52:33.038256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 10:52:33.041790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 10:52:33.047552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 10:52:33.051354 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 10:52:33.054498 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 10:52:33.060926 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 10:52:33.064331 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 10:52:33.067258 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 10:52:33.074258 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 10:52:33.077696 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 10:52:33.080541 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3597 10:52:33.087806 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3598 10:52:33.090814 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3599 10:52:33.094354 Total UI for P1: 0, mck2ui 16
3600 10:52:33.097046 best dqsien dly found for B0: ( 1, 3, 26)
3601 10:52:33.100450 Total UI for P1: 0, mck2ui 16
3602 10:52:33.103487 best dqsien dly found for B1: ( 1, 3, 26)
3603 10:52:33.107143 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3604 10:52:33.110376 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3605 10:52:33.110460
3606 10:52:33.113498 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3607 10:52:33.120180 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3608 10:52:33.120264 [Gating] SW calibration Done
3609 10:52:33.120331 ==
3610 10:52:33.123303 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 10:52:33.130708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 10:52:33.130793 ==
3613 10:52:33.130860 RX Vref Scan: 0
3614 10:52:33.130922
3615 10:52:33.133354 RX Vref 0 -> 0, step: 1
3616 10:52:33.133438
3617 10:52:33.136637 RX Delay -40 -> 252, step: 8
3618 10:52:33.139929 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3619 10:52:33.143154 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3620 10:52:33.146870 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3621 10:52:33.153787 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3622 10:52:33.156475 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3623 10:52:33.160461 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3624 10:52:33.163447 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3625 10:52:33.166661 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3626 10:52:33.173201 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3627 10:52:33.176730 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3628 10:52:33.180455 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3629 10:52:33.183331 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3630 10:52:33.186529 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3631 10:52:33.192790 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3632 10:52:33.196213 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3633 10:52:33.199424 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3634 10:52:33.199532 ==
3635 10:52:33.203155 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 10:52:33.206223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 10:52:33.209396 ==
3638 10:52:33.209478 DQS Delay:
3639 10:52:33.209543 DQS0 = 0, DQS1 = 0
3640 10:52:33.212834 DQM Delay:
3641 10:52:33.212916 DQM0 = 117, DQM1 = 110
3642 10:52:33.216413 DQ Delay:
3643 10:52:33.219417 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3644 10:52:33.222602 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3645 10:52:33.226081 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3646 10:52:33.229921 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3647 10:52:33.230003
3648 10:52:33.230068
3649 10:52:33.230154 ==
3650 10:52:33.232727 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 10:52:33.235586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 10:52:33.235670 ==
3653 10:52:33.235735
3654 10:52:33.238878
3655 10:52:33.238961 TX Vref Scan disable
3656 10:52:33.242310 == TX Byte 0 ==
3657 10:52:33.245590 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3658 10:52:33.249363 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3659 10:52:33.251919 == TX Byte 1 ==
3660 10:52:33.255713 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3661 10:52:33.258618 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3662 10:52:33.258703 ==
3663 10:52:33.262080 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 10:52:33.268323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 10:52:33.268409 ==
3666 10:52:33.279664 TX Vref=22, minBit 9, minWin=25, winSum=424
3667 10:52:33.282832 TX Vref=24, minBit 1, minWin=26, winSum=431
3668 10:52:33.286497 TX Vref=26, minBit 13, minWin=26, winSum=431
3669 10:52:33.290141 TX Vref=28, minBit 9, minWin=26, winSum=432
3670 10:52:33.292878 TX Vref=30, minBit 9, minWin=26, winSum=431
3671 10:52:33.299236 TX Vref=32, minBit 6, minWin=26, winSum=431
3672 10:52:33.302480 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3673 10:52:33.302564
3674 10:52:33.305674 Final TX Range 1 Vref 28
3675 10:52:33.305758
3676 10:52:33.305825 ==
3677 10:52:33.309196 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 10:52:33.312522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 10:52:33.315547 ==
3680 10:52:33.315630
3681 10:52:33.315695
3682 10:52:33.315755 TX Vref Scan disable
3683 10:52:33.319748 == TX Byte 0 ==
3684 10:52:33.322767 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3685 10:52:33.329567 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3686 10:52:33.329650 == TX Byte 1 ==
3687 10:52:33.333123 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3688 10:52:33.339456 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3689 10:52:33.339539
3690 10:52:33.339605 [DATLAT]
3691 10:52:33.339665 Freq=1200, CH1 RK1
3692 10:52:33.339724
3693 10:52:33.342334 DATLAT Default: 0xd
3694 10:52:33.345663 0, 0xFFFF, sum = 0
3695 10:52:33.345748 1, 0xFFFF, sum = 0
3696 10:52:33.349733 2, 0xFFFF, sum = 0
3697 10:52:33.349815 3, 0xFFFF, sum = 0
3698 10:52:33.352116 4, 0xFFFF, sum = 0
3699 10:52:33.352198 5, 0xFFFF, sum = 0
3700 10:52:33.355923 6, 0xFFFF, sum = 0
3701 10:52:33.356006 7, 0xFFFF, sum = 0
3702 10:52:33.358809 8, 0xFFFF, sum = 0
3703 10:52:33.358892 9, 0xFFFF, sum = 0
3704 10:52:33.362657 10, 0xFFFF, sum = 0
3705 10:52:33.362740 11, 0xFFFF, sum = 0
3706 10:52:33.365716 12, 0x0, sum = 1
3707 10:52:33.365812 13, 0x0, sum = 2
3708 10:52:33.369229 14, 0x0, sum = 3
3709 10:52:33.369312 15, 0x0, sum = 4
3710 10:52:33.372047 best_step = 13
3711 10:52:33.372128
3712 10:52:33.372192 ==
3713 10:52:33.375493 Dram Type= 6, Freq= 0, CH_1, rank 1
3714 10:52:33.378550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3715 10:52:33.378647 ==
3716 10:52:33.381858 RX Vref Scan: 0
3717 10:52:33.381939
3718 10:52:33.382003 RX Vref 0 -> 0, step: 1
3719 10:52:33.382063
3720 10:52:33.385083 RX Delay -21 -> 252, step: 4
3721 10:52:33.391862 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3722 10:52:33.395525 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3723 10:52:33.398330 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3724 10:52:33.401437 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3725 10:52:33.407921 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3726 10:52:33.411687 iDelay=199, Bit 5, Center 128 (67 ~ 190) 124
3727 10:52:33.414631 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3728 10:52:33.418279 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3729 10:52:33.421233 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3730 10:52:33.427998 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3731 10:52:33.431148 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3732 10:52:33.434666 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3733 10:52:33.437440 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3734 10:52:33.440979 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3735 10:52:33.447545 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3736 10:52:33.451131 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3737 10:52:33.451214 ==
3738 10:52:33.454469 Dram Type= 6, Freq= 0, CH_1, rank 1
3739 10:52:33.457769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3740 10:52:33.457853 ==
3741 10:52:33.461137 DQS Delay:
3742 10:52:33.461220 DQS0 = 0, DQS1 = 0
3743 10:52:33.461286 DQM Delay:
3744 10:52:33.464410 DQM0 = 117, DQM1 = 111
3745 10:52:33.464550 DQ Delay:
3746 10:52:33.467502 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3747 10:52:33.470950 DQ4 =116, DQ5 =128, DQ6 =132, DQ7 =114
3748 10:52:33.477518 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3749 10:52:33.480925 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3750 10:52:33.481008
3751 10:52:33.481073
3752 10:52:33.487035 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3753 10:52:33.490838 CH1 RK1: MR19=303, MR18=F7F2
3754 10:52:33.497487 CH1_RK1: MR19=0x303, MR18=0xF7F2, DQSOSC=413, MR23=63, INC=38, DEC=25
3755 10:52:33.500442 [RxdqsGatingPostProcess] freq 1200
3756 10:52:33.504047 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3757 10:52:33.507088 best DQS0 dly(2T, 0.5T) = (0, 11)
3758 10:52:33.510128 best DQS1 dly(2T, 0.5T) = (0, 11)
3759 10:52:33.513962 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3760 10:52:33.516915 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3761 10:52:33.520170 best DQS0 dly(2T, 0.5T) = (0, 11)
3762 10:52:33.523444 best DQS1 dly(2T, 0.5T) = (0, 11)
3763 10:52:33.526705 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3764 10:52:33.530082 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3765 10:52:33.533337 Pre-setting of DQS Precalculation
3766 10:52:33.540158 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3767 10:52:33.546677 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3768 10:52:33.553346 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3769 10:52:33.553429
3770 10:52:33.553494
3771 10:52:33.556886 [Calibration Summary] 2400 Mbps
3772 10:52:33.556968 CH 0, Rank 0
3773 10:52:33.559801 SW Impedance : PASS
3774 10:52:33.563032 DUTY Scan : NO K
3775 10:52:33.563115 ZQ Calibration : PASS
3776 10:52:33.566596 Jitter Meter : NO K
3777 10:52:33.569707 CBT Training : PASS
3778 10:52:33.569790 Write leveling : PASS
3779 10:52:33.573247 RX DQS gating : PASS
3780 10:52:33.573330 RX DQ/DQS(RDDQC) : PASS
3781 10:52:33.576538 TX DQ/DQS : PASS
3782 10:52:33.579679 RX DATLAT : PASS
3783 10:52:33.579762 RX DQ/DQS(Engine): PASS
3784 10:52:33.583517 TX OE : NO K
3785 10:52:33.583600 All Pass.
3786 10:52:33.583666
3787 10:52:33.586554 CH 0, Rank 1
3788 10:52:33.586658 SW Impedance : PASS
3789 10:52:33.589826 DUTY Scan : NO K
3790 10:52:33.592979 ZQ Calibration : PASS
3791 10:52:33.593062 Jitter Meter : NO K
3792 10:52:33.597609 CBT Training : PASS
3793 10:52:33.600016 Write leveling : PASS
3794 10:52:33.600098 RX DQS gating : PASS
3795 10:52:33.603105 RX DQ/DQS(RDDQC) : PASS
3796 10:52:33.606548 TX DQ/DQS : PASS
3797 10:52:33.606631 RX DATLAT : PASS
3798 10:52:33.609482 RX DQ/DQS(Engine): PASS
3799 10:52:33.613273 TX OE : NO K
3800 10:52:33.613356 All Pass.
3801 10:52:33.613422
3802 10:52:33.613481 CH 1, Rank 0
3803 10:52:33.616787 SW Impedance : PASS
3804 10:52:33.619281 DUTY Scan : NO K
3805 10:52:33.619363 ZQ Calibration : PASS
3806 10:52:33.622775 Jitter Meter : NO K
3807 10:52:33.626079 CBT Training : PASS
3808 10:52:33.626161 Write leveling : PASS
3809 10:52:33.629661 RX DQS gating : PASS
3810 10:52:33.632447 RX DQ/DQS(RDDQC) : PASS
3811 10:52:33.632537 TX DQ/DQS : PASS
3812 10:52:33.636010 RX DATLAT : PASS
3813 10:52:33.636092 RX DQ/DQS(Engine): PASS
3814 10:52:33.639360 TX OE : NO K
3815 10:52:33.639443 All Pass.
3816 10:52:33.639508
3817 10:52:33.642704 CH 1, Rank 1
3818 10:52:33.642787 SW Impedance : PASS
3819 10:52:33.645644 DUTY Scan : NO K
3820 10:52:33.649061 ZQ Calibration : PASS
3821 10:52:33.649144 Jitter Meter : NO K
3822 10:52:33.652315 CBT Training : PASS
3823 10:52:33.655820 Write leveling : PASS
3824 10:52:33.655903 RX DQS gating : PASS
3825 10:52:33.659982 RX DQ/DQS(RDDQC) : PASS
3826 10:52:33.662548 TX DQ/DQS : PASS
3827 10:52:33.662632 RX DATLAT : PASS
3828 10:52:33.665554 RX DQ/DQS(Engine): PASS
3829 10:52:33.669164 TX OE : NO K
3830 10:52:33.669247 All Pass.
3831 10:52:33.669313
3832 10:52:33.672257 DramC Write-DBI off
3833 10:52:33.672340 PER_BANK_REFRESH: Hybrid Mode
3834 10:52:33.676262 TX_TRACKING: ON
3835 10:52:33.682370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3836 10:52:33.689052 [FAST_K] Save calibration result to emmc
3837 10:52:33.692380 dramc_set_vcore_voltage set vcore to 650000
3838 10:52:33.692463 Read voltage for 600, 5
3839 10:52:33.695469 Vio18 = 0
3840 10:52:33.695553 Vcore = 650000
3841 10:52:33.695619 Vdram = 0
3842 10:52:33.698559 Vddq = 0
3843 10:52:33.698642 Vmddr = 0
3844 10:52:33.701865 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3845 10:52:33.708644 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3846 10:52:33.712361 MEM_TYPE=3, freq_sel=19
3847 10:52:33.715281 sv_algorithm_assistance_LP4_1600
3848 10:52:33.718432 ============ PULL DRAM RESETB DOWN ============
3849 10:52:33.721917 ========== PULL DRAM RESETB DOWN end =========
3850 10:52:33.728843 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 10:52:33.732136 ===================================
3852 10:52:33.732221 LPDDR4 DRAM CONFIGURATION
3853 10:52:33.735232 ===================================
3854 10:52:33.738200 EX_ROW_EN[0] = 0x0
3855 10:52:33.738283 EX_ROW_EN[1] = 0x0
3856 10:52:33.741842 LP4Y_EN = 0x0
3857 10:52:33.745513 WORK_FSP = 0x0
3858 10:52:33.745597 WL = 0x2
3859 10:52:33.749505 RL = 0x2
3860 10:52:33.749589 BL = 0x2
3861 10:52:33.751926 RPST = 0x0
3862 10:52:33.752009 RD_PRE = 0x0
3863 10:52:33.755326 WR_PRE = 0x1
3864 10:52:33.755409 WR_PST = 0x0
3865 10:52:33.758071 DBI_WR = 0x0
3866 10:52:33.758154 DBI_RD = 0x0
3867 10:52:33.761525 OTF = 0x1
3868 10:52:33.764644 ===================================
3869 10:52:33.767948 ===================================
3870 10:52:33.768036 ANA top config
3871 10:52:33.771639 ===================================
3872 10:52:33.774816 DLL_ASYNC_EN = 0
3873 10:52:33.778599 ALL_SLAVE_EN = 1
3874 10:52:33.778686 NEW_RANK_MODE = 1
3875 10:52:33.781923 DLL_IDLE_MODE = 1
3876 10:52:33.784655 LP45_APHY_COMB_EN = 1
3877 10:52:33.787944 TX_ODT_DIS = 1
3878 10:52:33.791433 NEW_8X_MODE = 1
3879 10:52:33.794478 ===================================
3880 10:52:33.798599 ===================================
3881 10:52:33.801206 data_rate = 1200
3882 10:52:33.801290 CKR = 1
3883 10:52:33.804547 DQ_P2S_RATIO = 8
3884 10:52:33.807888 ===================================
3885 10:52:33.811274 CA_P2S_RATIO = 8
3886 10:52:33.814195 DQ_CA_OPEN = 0
3887 10:52:33.818062 DQ_SEMI_OPEN = 0
3888 10:52:33.821477 CA_SEMI_OPEN = 0
3889 10:52:33.821562 CA_FULL_RATE = 0
3890 10:52:33.824359 DQ_CKDIV4_EN = 1
3891 10:52:33.827353 CA_CKDIV4_EN = 1
3892 10:52:33.831109 CA_PREDIV_EN = 0
3893 10:52:33.834531 PH8_DLY = 0
3894 10:52:33.837360 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3895 10:52:33.837444 DQ_AAMCK_DIV = 4
3896 10:52:33.840657 CA_AAMCK_DIV = 4
3897 10:52:33.844504 CA_ADMCK_DIV = 4
3898 10:52:33.847338 DQ_TRACK_CA_EN = 0
3899 10:52:33.850934 CA_PICK = 600
3900 10:52:33.853654 CA_MCKIO = 600
3901 10:52:33.853740 MCKIO_SEMI = 0
3902 10:52:33.857067 PLL_FREQ = 2288
3903 10:52:33.860685 DQ_UI_PI_RATIO = 32
3904 10:52:33.863844 CA_UI_PI_RATIO = 0
3905 10:52:33.867790 ===================================
3906 10:52:33.870217 ===================================
3907 10:52:33.873488 memory_type:LPDDR4
3908 10:52:33.873572 GP_NUM : 10
3909 10:52:33.877165 SRAM_EN : 1
3910 10:52:33.880100 MD32_EN : 0
3911 10:52:33.883783 ===================================
3912 10:52:33.883868 [ANA_INIT] >>>>>>>>>>>>>>
3913 10:52:33.886901 <<<<<< [CONFIGURE PHASE]: ANA_TX
3914 10:52:33.890289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3915 10:52:33.893849 ===================================
3916 10:52:33.897116 data_rate = 1200,PCW = 0X5800
3917 10:52:33.899956 ===================================
3918 10:52:33.903699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3919 10:52:33.909935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3920 10:52:33.916406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3921 10:52:33.919887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3922 10:52:33.923036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3923 10:52:33.926208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3924 10:52:33.929467 [ANA_INIT] flow start
3925 10:52:33.929551 [ANA_INIT] PLL >>>>>>>>
3926 10:52:33.933183 [ANA_INIT] PLL <<<<<<<<
3927 10:52:33.936364 [ANA_INIT] MIDPI >>>>>>>>
3928 10:52:33.936448 [ANA_INIT] MIDPI <<<<<<<<
3929 10:52:33.939910 [ANA_INIT] DLL >>>>>>>>
3930 10:52:33.943035 [ANA_INIT] flow end
3931 10:52:33.946106 ============ LP4 DIFF to SE enter ============
3932 10:52:33.949432 ============ LP4 DIFF to SE exit ============
3933 10:52:33.952852 [ANA_INIT] <<<<<<<<<<<<<
3934 10:52:33.956241 [Flow] Enable top DCM control >>>>>
3935 10:52:33.959632 [Flow] Enable top DCM control <<<<<
3936 10:52:33.962829 Enable DLL master slave shuffle
3937 10:52:33.965868 ==============================================================
3938 10:52:33.969874 Gating Mode config
3939 10:52:33.975825 ==============================================================
3940 10:52:33.975908 Config description:
3941 10:52:33.985943 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3942 10:52:33.993211 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3943 10:52:33.998817 SELPH_MODE 0: By rank 1: By Phase
3944 10:52:34.002611 ==============================================================
3945 10:52:34.005799 GAT_TRACK_EN = 1
3946 10:52:34.009333 RX_GATING_MODE = 2
3947 10:52:34.012334 RX_GATING_TRACK_MODE = 2
3948 10:52:34.015468 SELPH_MODE = 1
3949 10:52:34.018966 PICG_EARLY_EN = 1
3950 10:52:34.022213 VALID_LAT_VALUE = 1
3951 10:52:34.025685 ==============================================================
3952 10:52:34.032335 Enter into Gating configuration >>>>
3953 10:52:34.032418 Exit from Gating configuration <<<<
3954 10:52:34.035449 Enter into DVFS_PRE_config >>>>>
3955 10:52:34.048443 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3956 10:52:34.051889 Exit from DVFS_PRE_config <<<<<
3957 10:52:34.055592 Enter into PICG configuration >>>>
3958 10:52:34.058910 Exit from PICG configuration <<<<
3959 10:52:34.058992 [RX_INPUT] configuration >>>>>
3960 10:52:34.061683 [RX_INPUT] configuration <<<<<
3961 10:52:34.068332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3962 10:52:34.074982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3963 10:52:34.078439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3964 10:52:34.084824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3965 10:52:34.091410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3966 10:52:34.098381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3967 10:52:34.101144 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3968 10:52:34.104189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3969 10:52:34.110755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3970 10:52:34.114475 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3971 10:52:34.117449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3972 10:52:34.124016 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3973 10:52:34.127354 ===================================
3974 10:52:34.127450 LPDDR4 DRAM CONFIGURATION
3975 10:52:34.130752 ===================================
3976 10:52:34.133958 EX_ROW_EN[0] = 0x0
3977 10:52:34.137876 EX_ROW_EN[1] = 0x0
3978 10:52:34.137958 LP4Y_EN = 0x0
3979 10:52:34.140259 WORK_FSP = 0x0
3980 10:52:34.140354 WL = 0x2
3981 10:52:34.143903 RL = 0x2
3982 10:52:34.143986 BL = 0x2
3983 10:52:34.147148 RPST = 0x0
3984 10:52:34.147230 RD_PRE = 0x0
3985 10:52:34.150478 WR_PRE = 0x1
3986 10:52:34.150561 WR_PST = 0x0
3987 10:52:34.153719 DBI_WR = 0x0
3988 10:52:34.153801 DBI_RD = 0x0
3989 10:52:34.157001 OTF = 0x1
3990 10:52:34.160486 ===================================
3991 10:52:34.163434 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3992 10:52:34.167164 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3993 10:52:34.173713 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3994 10:52:34.176998 ===================================
3995 10:52:34.177082 LPDDR4 DRAM CONFIGURATION
3996 10:52:34.180290 ===================================
3997 10:52:34.183625 EX_ROW_EN[0] = 0x10
3998 10:52:34.186699 EX_ROW_EN[1] = 0x0
3999 10:52:34.186782 LP4Y_EN = 0x0
4000 10:52:34.190037 WORK_FSP = 0x0
4001 10:52:34.190120 WL = 0x2
4002 10:52:34.193579 RL = 0x2
4003 10:52:34.193662 BL = 0x2
4004 10:52:34.196852 RPST = 0x0
4005 10:52:34.196935 RD_PRE = 0x0
4006 10:52:34.199830 WR_PRE = 0x1
4007 10:52:34.199912 WR_PST = 0x0
4008 10:52:34.203178 DBI_WR = 0x0
4009 10:52:34.203261 DBI_RD = 0x0
4010 10:52:34.206965 OTF = 0x1
4011 10:52:34.209609 ===================================
4012 10:52:34.216216 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4013 10:52:34.219488 nWR fixed to 30
4014 10:52:34.223125 [ModeRegInit_LP4] CH0 RK0
4015 10:52:34.223208 [ModeRegInit_LP4] CH0 RK1
4016 10:52:34.226307 [ModeRegInit_LP4] CH1 RK0
4017 10:52:34.230566 [ModeRegInit_LP4] CH1 RK1
4018 10:52:34.230649 match AC timing 17
4019 10:52:34.236243 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4020 10:52:34.240058 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4021 10:52:34.243124 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4022 10:52:34.249933 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4023 10:52:34.252467 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4024 10:52:34.252589 ==
4025 10:52:34.256070 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 10:52:34.259476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 10:52:34.259560 ==
4028 10:52:34.265827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4029 10:52:34.272854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4030 10:52:34.275595 [CA 0] Center 36 (6~66) winsize 61
4031 10:52:34.278837 [CA 1] Center 36 (6~66) winsize 61
4032 10:52:34.282175 [CA 2] Center 34 (4~65) winsize 62
4033 10:52:34.285867 [CA 3] Center 34 (4~65) winsize 62
4034 10:52:34.289167 [CA 4] Center 33 (3~64) winsize 62
4035 10:52:34.292332 [CA 5] Center 33 (3~64) winsize 62
4036 10:52:34.292415
4037 10:52:34.295797 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4038 10:52:34.295881
4039 10:52:34.298800 [CATrainingPosCal] consider 1 rank data
4040 10:52:34.302699 u2DelayCellTimex100 = 270/100 ps
4041 10:52:34.305379 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4042 10:52:34.308965 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4043 10:52:34.311669 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4044 10:52:34.315205 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4045 10:52:34.321765 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4046 10:52:34.325151 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4047 10:52:34.325236
4048 10:52:34.328194 CA PerBit enable=1, Macro0, CA PI delay=33
4049 10:52:34.328277
4050 10:52:34.332174 [CBTSetCACLKResult] CA Dly = 33
4051 10:52:34.332275 CS Dly: 4 (0~35)
4052 10:52:34.332342 ==
4053 10:52:34.334986 Dram Type= 6, Freq= 0, CH_0, rank 1
4054 10:52:34.342368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 10:52:34.342452 ==
4056 10:52:34.344725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4057 10:52:34.352286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4058 10:52:34.354679 [CA 0] Center 35 (5~66) winsize 62
4059 10:52:34.358238 [CA 1] Center 36 (6~66) winsize 61
4060 10:52:34.361586 [CA 2] Center 33 (3~64) winsize 62
4061 10:52:34.364960 [CA 3] Center 33 (3~64) winsize 62
4062 10:52:34.368168 [CA 4] Center 33 (2~64) winsize 63
4063 10:52:34.371347 [CA 5] Center 33 (2~64) winsize 63
4064 10:52:34.371429
4065 10:52:34.374460 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4066 10:52:34.374543
4067 10:52:34.377865 [CATrainingPosCal] consider 2 rank data
4068 10:52:34.381380 u2DelayCellTimex100 = 270/100 ps
4069 10:52:34.384478 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4070 10:52:34.387945 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4071 10:52:34.394643 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4072 10:52:34.397774 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4073 10:52:34.401048 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4074 10:52:34.404630 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4075 10:52:34.404714
4076 10:52:34.407581 CA PerBit enable=1, Macro0, CA PI delay=33
4077 10:52:34.407666
4078 10:52:34.411185 [CBTSetCACLKResult] CA Dly = 33
4079 10:52:34.411268 CS Dly: 5 (0~37)
4080 10:52:34.414329
4081 10:52:34.417755 ----->DramcWriteLeveling(PI) begin...
4082 10:52:34.417840 ==
4083 10:52:34.421394 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 10:52:34.424245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 10:52:34.424328 ==
4086 10:52:34.427632 Write leveling (Byte 0): 33 => 33
4087 10:52:34.430822 Write leveling (Byte 1): 31 => 31
4088 10:52:34.434824 DramcWriteLeveling(PI) end<-----
4089 10:52:34.434906
4090 10:52:34.434972 ==
4091 10:52:34.437388 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 10:52:34.440807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 10:52:34.440890 ==
4094 10:52:34.444328 [Gating] SW mode calibration
4095 10:52:34.450908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4096 10:52:34.457299 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4097 10:52:34.460785 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4098 10:52:34.463836 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4099 10:52:34.470724 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4100 10:52:34.473543 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
4101 10:52:34.477207 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
4102 10:52:34.483740 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 10:52:34.487595 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 10:52:34.491045 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 10:52:34.497255 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 10:52:34.500237 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4107 10:52:34.503542 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4108 10:52:34.510252 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4109 10:52:34.513323 0 10 16 | B1->B0 | 3232 4444 | 0 0 | (0 0) (0 0)
4110 10:52:34.516936 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 10:52:34.523352 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 10:52:34.526769 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 10:52:34.530210 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 10:52:34.536537 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 10:52:34.539977 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 10:52:34.543612 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 10:52:34.549723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4118 10:52:34.553007 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 10:52:34.556121 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 10:52:34.562989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 10:52:34.566073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 10:52:34.570127 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 10:52:34.576462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 10:52:34.579823 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 10:52:34.583623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 10:52:34.589786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 10:52:34.592703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 10:52:34.595966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 10:52:34.602516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 10:52:34.606242 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 10:52:34.609918 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 10:52:34.612443 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4133 10:52:34.619607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4134 10:52:34.623154 Total UI for P1: 0, mck2ui 16
4135 10:52:34.626271 best dqsien dly found for B0: ( 0, 13, 12)
4136 10:52:34.629343 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4137 10:52:34.632459 Total UI for P1: 0, mck2ui 16
4138 10:52:34.636115 best dqsien dly found for B1: ( 0, 13, 14)
4139 10:52:34.639625 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4140 10:52:34.642805 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4141 10:52:34.642888
4142 10:52:34.646241 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4143 10:52:34.652362 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4144 10:52:34.652446 [Gating] SW calibration Done
4145 10:52:34.652512 ==
4146 10:52:34.655927 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 10:52:34.662167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 10:52:34.662250 ==
4149 10:52:34.662315 RX Vref Scan: 0
4150 10:52:34.662375
4151 10:52:34.665369 RX Vref 0 -> 0, step: 1
4152 10:52:34.665452
4153 10:52:34.668659 RX Delay -230 -> 252, step: 16
4154 10:52:34.672000 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4155 10:52:34.675461 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4156 10:52:34.682370 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4157 10:52:34.685582 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4158 10:52:34.688697 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4159 10:52:34.691866 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4160 10:52:34.695602 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4161 10:52:34.701914 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4162 10:52:34.705575 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4163 10:52:34.708393 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4164 10:52:34.712102 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4165 10:52:34.718584 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4166 10:52:34.721866 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4167 10:52:34.725295 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4168 10:52:34.728433 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4169 10:52:34.735375 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4170 10:52:34.735460 ==
4171 10:52:34.738454 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 10:52:34.741567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 10:52:34.741652 ==
4174 10:52:34.741721 DQS Delay:
4175 10:52:34.744610 DQS0 = 0, DQS1 = 0
4176 10:52:34.744725 DQM Delay:
4177 10:52:34.748534 DQM0 = 41, DQM1 = 32
4178 10:52:34.748632 DQ Delay:
4179 10:52:34.751685 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4180 10:52:34.754854 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4181 10:52:34.758095 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4182 10:52:34.761457 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4183 10:52:34.761549
4184 10:52:34.761615
4185 10:52:34.761674 ==
4186 10:52:34.765102 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 10:52:34.767841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 10:52:34.771745 ==
4189 10:52:34.771838
4190 10:52:34.771907
4191 10:52:34.771968 TX Vref Scan disable
4192 10:52:34.774559 == TX Byte 0 ==
4193 10:52:34.777895 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4194 10:52:34.781883 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4195 10:52:34.784387 == TX Byte 1 ==
4196 10:52:34.788400 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4197 10:52:34.791070 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4198 10:52:34.794699 ==
4199 10:52:34.798022 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 10:52:34.800939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 10:52:34.801023 ==
4202 10:52:34.801088
4203 10:52:34.801146
4204 10:52:34.804155 TX Vref Scan disable
4205 10:52:34.807553 == TX Byte 0 ==
4206 10:52:34.810747 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4207 10:52:34.813878 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4208 10:52:34.817437 == TX Byte 1 ==
4209 10:52:34.820745 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4210 10:52:34.824421 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4211 10:52:34.824505
4212 10:52:34.824605 [DATLAT]
4213 10:52:34.828202 Freq=600, CH0 RK0
4214 10:52:34.828289
4215 10:52:34.830884 DATLAT Default: 0x9
4216 10:52:34.830976 0, 0xFFFF, sum = 0
4217 10:52:34.834076 1, 0xFFFF, sum = 0
4218 10:52:34.834164 2, 0xFFFF, sum = 0
4219 10:52:34.837440 3, 0xFFFF, sum = 0
4220 10:52:34.837528 4, 0xFFFF, sum = 0
4221 10:52:34.840417 5, 0xFFFF, sum = 0
4222 10:52:34.840504 6, 0xFFFF, sum = 0
4223 10:52:34.843721 7, 0xFFFF, sum = 0
4224 10:52:34.843809 8, 0x0, sum = 1
4225 10:52:34.846950 9, 0x0, sum = 2
4226 10:52:34.847038 10, 0x0, sum = 3
4227 10:52:34.850852 11, 0x0, sum = 4
4228 10:52:34.850940 best_step = 9
4229 10:52:34.851025
4230 10:52:34.851105 ==
4231 10:52:34.853727 Dram Type= 6, Freq= 0, CH_0, rank 0
4232 10:52:34.857140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 10:52:34.857227 ==
4234 10:52:34.860481 RX Vref Scan: 1
4235 10:52:34.860605
4236 10:52:34.863724 RX Vref 0 -> 0, step: 1
4237 10:52:34.863810
4238 10:52:34.863895 RX Delay -179 -> 252, step: 8
4239 10:52:34.863976
4240 10:52:34.866738 Set Vref, RX VrefLevel [Byte0]: 55
4241 10:52:34.870341 [Byte1]: 49
4242 10:52:34.874966
4243 10:52:34.875052 Final RX Vref Byte 0 = 55 to rank0
4244 10:52:34.878119 Final RX Vref Byte 1 = 49 to rank0
4245 10:52:34.881107 Final RX Vref Byte 0 = 55 to rank1
4246 10:52:34.884638 Final RX Vref Byte 1 = 49 to rank1==
4247 10:52:34.888227 Dram Type= 6, Freq= 0, CH_0, rank 0
4248 10:52:34.894357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 10:52:34.894444 ==
4250 10:52:34.894530 DQS Delay:
4251 10:52:34.897972 DQS0 = 0, DQS1 = 0
4252 10:52:34.898059 DQM Delay:
4253 10:52:34.898145 DQM0 = 44, DQM1 = 32
4254 10:52:34.900933 DQ Delay:
4255 10:52:34.904838 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4256 10:52:34.907891 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4257 10:52:34.910980 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4258 10:52:34.914038 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4259 10:52:34.914124
4260 10:52:34.914210
4261 10:52:34.921188 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4262 10:52:34.923920 CH0 RK0: MR19=808, MR18=5F37
4263 10:52:34.930620 CH0_RK0: MR19=0x808, MR18=0x5F37, DQSOSC=391, MR23=63, INC=171, DEC=114
4264 10:52:34.930707
4265 10:52:34.934534 ----->DramcWriteLeveling(PI) begin...
4266 10:52:34.934622 ==
4267 10:52:34.937548 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 10:52:34.941324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 10:52:34.941410 ==
4270 10:52:34.944414 Write leveling (Byte 0): 33 => 33
4271 10:52:34.947240 Write leveling (Byte 1): 33 => 33
4272 10:52:34.950888 DramcWriteLeveling(PI) end<-----
4273 10:52:34.950974
4274 10:52:34.951059 ==
4275 10:52:34.954072 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 10:52:34.957378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 10:52:34.960524 ==
4278 10:52:34.960628 [Gating] SW mode calibration
4279 10:52:34.970711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4280 10:52:34.973760 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4281 10:52:34.977024 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4282 10:52:34.983986 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4283 10:52:34.986868 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4284 10:52:34.990247 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4285 10:52:34.996877 0 9 16 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
4286 10:52:35.000863 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 10:52:35.003322 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 10:52:35.010841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 10:52:35.013445 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 10:52:35.016695 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 10:52:35.023185 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 10:52:35.027207 0 10 12 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
4293 10:52:35.030041 0 10 16 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (0 0)
4294 10:52:35.036704 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 10:52:35.039977 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 10:52:35.043078 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 10:52:35.050089 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 10:52:35.053320 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 10:52:35.056446 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 10:52:35.063194 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 10:52:35.066255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 10:52:35.069905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 10:52:35.076699 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 10:52:35.079469 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 10:52:35.082902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 10:52:35.089689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 10:52:35.093052 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 10:52:35.096439 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 10:52:35.102832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 10:52:35.105935 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 10:52:35.109242 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 10:52:35.115838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 10:52:35.119375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 10:52:35.122853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 10:52:35.129476 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 10:52:35.132769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4317 10:52:35.135880 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4318 10:52:35.142714 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 10:52:35.142798 Total UI for P1: 0, mck2ui 16
4320 10:52:35.148858 best dqsien dly found for B0: ( 0, 13, 14)
4321 10:52:35.148941 Total UI for P1: 0, mck2ui 16
4322 10:52:35.152305 best dqsien dly found for B1: ( 0, 13, 14)
4323 10:52:35.159219 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4324 10:52:35.162821 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4325 10:52:35.162904
4326 10:52:35.165836 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4327 10:52:35.168846 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4328 10:52:35.172300 [Gating] SW calibration Done
4329 10:52:35.172382 ==
4330 10:52:35.175706 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 10:52:35.178835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 10:52:35.178918 ==
4333 10:52:35.182161 RX Vref Scan: 0
4334 10:52:35.182244
4335 10:52:35.182315 RX Vref 0 -> 0, step: 1
4336 10:52:35.182375
4337 10:52:35.185495 RX Delay -230 -> 252, step: 16
4338 10:52:35.192357 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4339 10:52:35.195525 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4340 10:52:35.198908 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4341 10:52:35.202458 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4342 10:52:35.205396 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4343 10:52:35.211935 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4344 10:52:35.215017 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4345 10:52:35.218371 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4346 10:52:35.222081 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4347 10:52:35.228715 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4348 10:52:35.231364 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4349 10:52:35.235062 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4350 10:52:35.238290 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4351 10:52:35.244866 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4352 10:52:35.248085 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4353 10:52:35.251443 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4354 10:52:35.251527 ==
4355 10:52:35.254338 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 10:52:35.257584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 10:52:35.261046 ==
4358 10:52:35.261130 DQS Delay:
4359 10:52:35.261196 DQS0 = 0, DQS1 = 0
4360 10:52:35.264752 DQM Delay:
4361 10:52:35.264834 DQM0 = 43, DQM1 = 40
4362 10:52:35.267908 DQ Delay:
4363 10:52:35.270860 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4364 10:52:35.270943 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4365 10:52:35.274137 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4366 10:52:35.280676 DQ12 =49, DQ13 =57, DQ14 =57, DQ15 =49
4367 10:52:35.280758
4368 10:52:35.280826
4369 10:52:35.280891 ==
4370 10:52:35.284146 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 10:52:35.287571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 10:52:35.287654 ==
4373 10:52:35.287719
4374 10:52:35.287778
4375 10:52:35.290750 TX Vref Scan disable
4376 10:52:35.290833 == TX Byte 0 ==
4377 10:52:35.297655 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4378 10:52:35.300546 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4379 10:52:35.300628 == TX Byte 1 ==
4380 10:52:35.307108 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4381 10:52:35.310352 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4382 10:52:35.310434 ==
4383 10:52:35.313755 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 10:52:35.316951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 10:52:35.317033 ==
4386 10:52:35.317098
4387 10:52:35.320133
4388 10:52:35.320214 TX Vref Scan disable
4389 10:52:35.324000 == TX Byte 0 ==
4390 10:52:35.327629 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4391 10:52:35.330631 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4392 10:52:35.333569 == TX Byte 1 ==
4393 10:52:35.337122 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4394 10:52:35.344210 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4395 10:52:35.344293
4396 10:52:35.344358 [DATLAT]
4397 10:52:35.344417 Freq=600, CH0 RK1
4398 10:52:35.344475
4399 10:52:35.346942 DATLAT Default: 0x9
4400 10:52:35.347024 0, 0xFFFF, sum = 0
4401 10:52:35.350407 1, 0xFFFF, sum = 0
4402 10:52:35.353384 2, 0xFFFF, sum = 0
4403 10:52:35.353474 3, 0xFFFF, sum = 0
4404 10:52:35.357044 4, 0xFFFF, sum = 0
4405 10:52:35.357127 5, 0xFFFF, sum = 0
4406 10:52:35.360282 6, 0xFFFF, sum = 0
4407 10:52:35.360366 7, 0xFFFF, sum = 0
4408 10:52:35.363832 8, 0x0, sum = 1
4409 10:52:35.363915 9, 0x0, sum = 2
4410 10:52:35.363982 10, 0x0, sum = 3
4411 10:52:35.367295 11, 0x0, sum = 4
4412 10:52:35.367378 best_step = 9
4413 10:52:35.367442
4414 10:52:35.367501 ==
4415 10:52:35.370172 Dram Type= 6, Freq= 0, CH_0, rank 1
4416 10:52:35.376703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 10:52:35.376790 ==
4418 10:52:35.376854 RX Vref Scan: 0
4419 10:52:35.376913
4420 10:52:35.380246 RX Vref 0 -> 0, step: 1
4421 10:52:35.380327
4422 10:52:35.383326 RX Delay -179 -> 252, step: 8
4423 10:52:35.386714 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4424 10:52:35.393986 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4425 10:52:35.396631 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4426 10:52:35.400047 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4427 10:52:35.403512 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4428 10:52:35.409807 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4429 10:52:35.412997 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4430 10:52:35.416802 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4431 10:52:35.419866 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4432 10:52:35.426498 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4433 10:52:35.429694 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4434 10:52:35.433356 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4435 10:52:35.436499 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4436 10:52:35.439480 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4437 10:52:35.446275 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4438 10:52:35.449890 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4439 10:52:35.449974 ==
4440 10:52:35.452623 Dram Type= 6, Freq= 0, CH_0, rank 1
4441 10:52:35.456104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 10:52:35.456189 ==
4443 10:52:35.459690 DQS Delay:
4444 10:52:35.459774 DQS0 = 0, DQS1 = 0
4445 10:52:35.463348 DQM Delay:
4446 10:52:35.463431 DQM0 = 41, DQM1 = 36
4447 10:52:35.463498 DQ Delay:
4448 10:52:35.466088 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4449 10:52:35.469312 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4450 10:52:35.472852 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4451 10:52:35.475973 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4452 10:52:35.476057
4453 10:52:35.476123
4454 10:52:35.485962 [DQSOSCAuto] RK1, (LSB)MR18= 0x6317, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4455 10:52:35.488727 CH0 RK1: MR19=808, MR18=6317
4456 10:52:35.495483 CH0_RK1: MR19=0x808, MR18=0x6317, DQSOSC=391, MR23=63, INC=171, DEC=114
4457 10:52:35.498969 [RxdqsGatingPostProcess] freq 600
4458 10:52:35.502369 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4459 10:52:35.505400 Pre-setting of DQS Precalculation
4460 10:52:35.511872 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4461 10:52:35.511956 ==
4462 10:52:35.515144 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 10:52:35.518453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 10:52:35.518536 ==
4465 10:52:35.525845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4466 10:52:35.528448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4467 10:52:35.532474 [CA 0] Center 35 (5~66) winsize 62
4468 10:52:35.535908 [CA 1] Center 35 (5~66) winsize 62
4469 10:52:35.539573 [CA 2] Center 34 (4~65) winsize 62
4470 10:52:35.542910 [CA 3] Center 33 (3~64) winsize 62
4471 10:52:35.545999 [CA 4] Center 34 (4~64) winsize 61
4472 10:52:35.549633 [CA 5] Center 33 (3~64) winsize 62
4473 10:52:35.549717
4474 10:52:35.552472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4475 10:52:35.552605
4476 10:52:35.555619 [CATrainingPosCal] consider 1 rank data
4477 10:52:35.559222 u2DelayCellTimex100 = 270/100 ps
4478 10:52:35.562575 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4479 10:52:35.569393 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4480 10:52:35.572556 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4481 10:52:35.575876 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 10:52:35.578916 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4483 10:52:35.582632 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 10:52:35.582718
4485 10:52:35.585644 CA PerBit enable=1, Macro0, CA PI delay=33
4486 10:52:35.585731
4487 10:52:35.589322 [CBTSetCACLKResult] CA Dly = 33
4488 10:52:35.592080 CS Dly: 5 (0~36)
4489 10:52:35.592166 ==
4490 10:52:35.595685 Dram Type= 6, Freq= 0, CH_1, rank 1
4491 10:52:35.598826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 10:52:35.598911 ==
4493 10:52:35.605253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4494 10:52:35.608627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4495 10:52:35.612707 [CA 0] Center 35 (5~66) winsize 62
4496 10:52:35.615985 [CA 1] Center 36 (6~66) winsize 61
4497 10:52:35.619235 [CA 2] Center 34 (4~65) winsize 62
4498 10:52:35.622629 [CA 3] Center 33 (3~64) winsize 62
4499 10:52:35.626240 [CA 4] Center 34 (3~65) winsize 63
4500 10:52:35.629168 [CA 5] Center 34 (3~65) winsize 63
4501 10:52:35.629253
4502 10:52:35.632893 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4503 10:52:35.632977
4504 10:52:35.635746 [CATrainingPosCal] consider 2 rank data
4505 10:52:35.639239 u2DelayCellTimex100 = 270/100 ps
4506 10:52:35.642699 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4507 10:52:35.649401 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4508 10:52:35.652378 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4509 10:52:35.656507 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4510 10:52:35.659138 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4511 10:52:35.662196 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4512 10:52:35.662280
4513 10:52:35.665663 CA PerBit enable=1, Macro0, CA PI delay=33
4514 10:52:35.665751
4515 10:52:35.669613 [CBTSetCACLKResult] CA Dly = 33
4516 10:52:35.669697 CS Dly: 5 (0~36)
4517 10:52:35.672211
4518 10:52:35.676226 ----->DramcWriteLeveling(PI) begin...
4519 10:52:35.676311 ==
4520 10:52:35.678949 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 10:52:35.682197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 10:52:35.682282 ==
4523 10:52:35.685628 Write leveling (Byte 0): 30 => 30
4524 10:52:35.688558 Write leveling (Byte 1): 29 => 29
4525 10:52:35.692818 DramcWriteLeveling(PI) end<-----
4526 10:52:35.692902
4527 10:52:35.692968 ==
4528 10:52:35.696322 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 10:52:35.698648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 10:52:35.698733 ==
4531 10:52:35.702178 [Gating] SW mode calibration
4532 10:52:35.708858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4533 10:52:35.715425 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4534 10:52:35.718795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4535 10:52:35.721997 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4536 10:52:35.728323 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4537 10:52:35.731542 0 9 12 | B1->B0 | 3131 2b2b | 1 1 | (1 1) (1 0)
4538 10:52:35.735698 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4539 10:52:35.741975 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4540 10:52:35.745079 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4541 10:52:35.748298 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4542 10:52:35.755301 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4543 10:52:35.758304 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4544 10:52:35.761467 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4545 10:52:35.768174 0 10 12 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
4546 10:52:35.771397 0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4547 10:52:35.774902 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 10:52:35.781180 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 10:52:35.784844 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 10:52:35.787580 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 10:52:35.794570 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 10:52:35.797842 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 10:52:35.800942 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4554 10:52:35.807643 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 10:52:35.811019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 10:52:35.814426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 10:52:35.821204 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 10:52:35.824454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 10:52:35.827526 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 10:52:35.833829 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 10:52:35.837241 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 10:52:35.840738 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 10:52:35.847364 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 10:52:35.850340 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 10:52:35.853749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 10:52:35.860132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 10:52:35.863652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 10:52:35.866751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 10:52:35.873425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4570 10:52:35.876869 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4571 10:52:35.880407 Total UI for P1: 0, mck2ui 16
4572 10:52:35.883583 best dqsien dly found for B0: ( 0, 13, 12)
4573 10:52:35.888069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4574 10:52:35.890027 Total UI for P1: 0, mck2ui 16
4575 10:52:35.893499 best dqsien dly found for B1: ( 0, 13, 16)
4576 10:52:35.896707 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4577 10:52:35.899915 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4578 10:52:35.900023
4579 10:52:35.906457 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4580 10:52:35.910535 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4581 10:52:35.910618 [Gating] SW calibration Done
4582 10:52:35.913569 ==
4583 10:52:35.916713 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 10:52:35.920219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 10:52:35.920302 ==
4586 10:52:35.920367 RX Vref Scan: 0
4587 10:52:35.920426
4588 10:52:35.923386 RX Vref 0 -> 0, step: 1
4589 10:52:35.923472
4590 10:52:35.926685 RX Delay -230 -> 252, step: 16
4591 10:52:35.929725 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4592 10:52:35.933726 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4593 10:52:35.939779 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4594 10:52:35.942719 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4595 10:52:35.946021 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4596 10:52:35.949726 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4597 10:52:35.955865 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4598 10:52:35.959534 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4599 10:52:35.962515 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4600 10:52:35.966439 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4601 10:52:35.972828 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4602 10:52:35.975738 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4603 10:52:35.979442 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4604 10:52:35.982494 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4605 10:52:35.989441 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4606 10:52:35.992116 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4607 10:52:35.992224 ==
4608 10:52:35.995383 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 10:52:35.998807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 10:52:35.998890 ==
4611 10:52:36.002162 DQS Delay:
4612 10:52:36.002244 DQS0 = 0, DQS1 = 0
4613 10:52:36.002308 DQM Delay:
4614 10:52:36.005583 DQM0 = 43, DQM1 = 33
4615 10:52:36.005665 DQ Delay:
4616 10:52:36.009189 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4617 10:52:36.011860 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =41
4618 10:52:36.015263 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4619 10:52:36.018459 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4620 10:52:36.018543
4621 10:52:36.018608
4622 10:52:36.018667 ==
4623 10:52:36.022032 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 10:52:36.028219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 10:52:36.028301 ==
4626 10:52:36.028366
4627 10:52:36.028424
4628 10:52:36.028481 TX Vref Scan disable
4629 10:52:36.032361 == TX Byte 0 ==
4630 10:52:36.035555 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4631 10:52:36.042342 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4632 10:52:36.042425 == TX Byte 1 ==
4633 10:52:36.045719 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4634 10:52:36.052034 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4635 10:52:36.052117 ==
4636 10:52:36.055968 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 10:52:36.058678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 10:52:36.058760 ==
4639 10:52:36.058825
4640 10:52:36.058883
4641 10:52:36.062135 TX Vref Scan disable
4642 10:52:36.065387 == TX Byte 0 ==
4643 10:52:36.068601 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4644 10:52:36.071816 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4645 10:52:36.075759 == TX Byte 1 ==
4646 10:52:36.078836 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4647 10:52:36.081866 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4648 10:52:36.081949
4649 10:52:36.082013 [DATLAT]
4650 10:52:36.085163 Freq=600, CH1 RK0
4651 10:52:36.085246
4652 10:52:36.088313 DATLAT Default: 0x9
4653 10:52:36.088395 0, 0xFFFF, sum = 0
4654 10:52:36.091971 1, 0xFFFF, sum = 0
4655 10:52:36.092056 2, 0xFFFF, sum = 0
4656 10:52:36.095267 3, 0xFFFF, sum = 0
4657 10:52:36.095351 4, 0xFFFF, sum = 0
4658 10:52:36.098442 5, 0xFFFF, sum = 0
4659 10:52:36.098525 6, 0xFFFF, sum = 0
4660 10:52:36.101984 7, 0xFFFF, sum = 0
4661 10:52:36.102068 8, 0x0, sum = 1
4662 10:52:36.104729 9, 0x0, sum = 2
4663 10:52:36.104812 10, 0x0, sum = 3
4664 10:52:36.107986 11, 0x0, sum = 4
4665 10:52:36.108070 best_step = 9
4666 10:52:36.108135
4667 10:52:36.108193 ==
4668 10:52:36.111607 Dram Type= 6, Freq= 0, CH_1, rank 0
4669 10:52:36.114780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 10:52:36.114863 ==
4671 10:52:36.118068 RX Vref Scan: 1
4672 10:52:36.118150
4673 10:52:36.121438 RX Vref 0 -> 0, step: 1
4674 10:52:36.121519
4675 10:52:36.124471 RX Delay -195 -> 252, step: 8
4676 10:52:36.124571
4677 10:52:36.128020 Set Vref, RX VrefLevel [Byte0]: 47
4678 10:52:36.131473 [Byte1]: 54
4679 10:52:36.131555
4680 10:52:36.134878 Final RX Vref Byte 0 = 47 to rank0
4681 10:52:36.137817 Final RX Vref Byte 1 = 54 to rank0
4682 10:52:36.141289 Final RX Vref Byte 0 = 47 to rank1
4683 10:52:36.144548 Final RX Vref Byte 1 = 54 to rank1==
4684 10:52:36.147991 Dram Type= 6, Freq= 0, CH_1, rank 0
4685 10:52:36.151094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 10:52:36.151177 ==
4687 10:52:36.154651 DQS Delay:
4688 10:52:36.154733 DQS0 = 0, DQS1 = 0
4689 10:52:36.154796 DQM Delay:
4690 10:52:36.157765 DQM0 = 44, DQM1 = 35
4691 10:52:36.157846 DQ Delay:
4692 10:52:36.161206 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4693 10:52:36.164236 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =36
4694 10:52:36.167626 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4695 10:52:36.170364 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4696 10:52:36.170447
4697 10:52:36.170513
4698 10:52:36.181025 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4699 10:52:36.183775 CH1 RK0: MR19=808, MR18=4A2F
4700 10:52:36.187669 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4701 10:52:36.187752
4702 10:52:36.190454 ----->DramcWriteLeveling(PI) begin...
4703 10:52:36.193745 ==
4704 10:52:36.196828 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 10:52:36.200137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 10:52:36.200220 ==
4707 10:52:36.203523 Write leveling (Byte 0): 28 => 28
4708 10:52:36.207122 Write leveling (Byte 1): 32 => 32
4709 10:52:36.210000 DramcWriteLeveling(PI) end<-----
4710 10:52:36.210083
4711 10:52:36.210156 ==
4712 10:52:36.213663 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 10:52:36.216894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 10:52:36.216977 ==
4715 10:52:36.220653 [Gating] SW mode calibration
4716 10:52:36.226459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4717 10:52:36.233146 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4718 10:52:36.236782 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4719 10:52:36.239876 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4720 10:52:36.246947 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4721 10:52:36.250144 0 9 12 | B1->B0 | 3030 3030 | 0 1 | (1 0) (1 1)
4722 10:52:36.253275 0 9 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
4723 10:52:36.259928 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4724 10:52:36.263014 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4725 10:52:36.267072 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4726 10:52:36.273255 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4727 10:52:36.276338 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4728 10:52:36.279416 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4729 10:52:36.285836 0 10 12 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
4730 10:52:36.289499 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4731 10:52:36.292466 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 10:52:36.299314 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 10:52:36.302252 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 10:52:36.305605 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 10:52:36.312180 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 10:52:36.315537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 10:52:36.318643 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4738 10:52:36.325695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 10:52:36.329049 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 10:52:36.332506 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 10:52:36.338588 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 10:52:36.342303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 10:52:36.345210 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 10:52:36.352269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 10:52:36.355681 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 10:52:36.358658 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 10:52:36.365304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 10:52:36.368453 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 10:52:36.372224 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 10:52:36.378325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 10:52:36.381641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4752 10:52:36.385034 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4753 10:52:36.391471 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4754 10:52:36.395101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4755 10:52:36.398155 Total UI for P1: 0, mck2ui 16
4756 10:52:36.401384 best dqsien dly found for B0: ( 0, 13, 12)
4757 10:52:36.404940 Total UI for P1: 0, mck2ui 16
4758 10:52:36.408437 best dqsien dly found for B1: ( 0, 13, 12)
4759 10:52:36.411244 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4760 10:52:36.414558 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4761 10:52:36.414640
4762 10:52:36.418223 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4763 10:52:36.421754 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4764 10:52:36.424463 [Gating] SW calibration Done
4765 10:52:36.424566 ==
4766 10:52:36.427819 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 10:52:36.430934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 10:52:36.434611 ==
4769 10:52:36.434694 RX Vref Scan: 0
4770 10:52:36.434760
4771 10:52:36.438467 RX Vref 0 -> 0, step: 1
4772 10:52:36.438550
4773 10:52:36.441821 RX Delay -230 -> 252, step: 16
4774 10:52:36.444726 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4775 10:52:36.447476 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4776 10:52:36.450751 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4777 10:52:36.457830 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4778 10:52:36.461203 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4779 10:52:36.464005 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4780 10:52:36.467817 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4781 10:52:36.470667 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4782 10:52:36.477938 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4783 10:52:36.480636 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4784 10:52:36.483978 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4785 10:52:36.487340 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4786 10:52:36.493849 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4787 10:52:36.497407 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4788 10:52:36.500534 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4789 10:52:36.504267 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4790 10:52:36.507476 ==
4791 10:52:36.510141 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 10:52:36.513559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 10:52:36.513644 ==
4794 10:52:36.513709 DQS Delay:
4795 10:52:36.517264 DQS0 = 0, DQS1 = 0
4796 10:52:36.517348 DQM Delay:
4797 10:52:36.520555 DQM0 = 40, DQM1 = 34
4798 10:52:36.520664 DQ Delay:
4799 10:52:36.523727 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4800 10:52:36.527184 DQ4 =33, DQ5 =49, DQ6 =57, DQ7 =33
4801 10:52:36.531034 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =17
4802 10:52:36.533621 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4803 10:52:36.533704
4804 10:52:36.533769
4805 10:52:36.533830 ==
4806 10:52:36.537213 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 10:52:36.540075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 10:52:36.540159 ==
4809 10:52:36.540225
4810 10:52:36.540285
4811 10:52:36.543822 TX Vref Scan disable
4812 10:52:36.547005 == TX Byte 0 ==
4813 10:52:36.550515 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4814 10:52:36.554239 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4815 10:52:36.557102 == TX Byte 1 ==
4816 10:52:36.560248 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4817 10:52:36.563094 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4818 10:52:36.563177 ==
4819 10:52:36.567250 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 10:52:36.573026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 10:52:36.573110 ==
4822 10:52:36.573176
4823 10:52:36.573235
4824 10:52:36.573293 TX Vref Scan disable
4825 10:52:36.577598 == TX Byte 0 ==
4826 10:52:36.581008 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4827 10:52:36.587702 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4828 10:52:36.587786 == TX Byte 1 ==
4829 10:52:36.590669 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4830 10:52:36.597639 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4831 10:52:36.597723
4832 10:52:36.597789 [DATLAT]
4833 10:52:36.597849 Freq=600, CH1 RK1
4834 10:52:36.597908
4835 10:52:36.600964 DATLAT Default: 0x9
4836 10:52:36.601047 0, 0xFFFF, sum = 0
4837 10:52:36.603880 1, 0xFFFF, sum = 0
4838 10:52:36.607418 2, 0xFFFF, sum = 0
4839 10:52:36.607503 3, 0xFFFF, sum = 0
4840 10:52:36.610699 4, 0xFFFF, sum = 0
4841 10:52:36.610784 5, 0xFFFF, sum = 0
4842 10:52:36.613774 6, 0xFFFF, sum = 0
4843 10:52:36.613859 7, 0xFFFF, sum = 0
4844 10:52:36.618065 8, 0x0, sum = 1
4845 10:52:36.618150 9, 0x0, sum = 2
4846 10:52:36.618217 10, 0x0, sum = 3
4847 10:52:36.621029 11, 0x0, sum = 4
4848 10:52:36.621114 best_step = 9
4849 10:52:36.621180
4850 10:52:36.623614 ==
4851 10:52:36.623697 Dram Type= 6, Freq= 0, CH_1, rank 1
4852 10:52:36.630811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4853 10:52:36.630896 ==
4854 10:52:36.630962 RX Vref Scan: 0
4855 10:52:36.631022
4856 10:52:36.633494 RX Vref 0 -> 0, step: 1
4857 10:52:36.633577
4858 10:52:36.636865 RX Delay -195 -> 252, step: 8
4859 10:52:36.643378 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4860 10:52:36.646658 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4861 10:52:36.650398 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4862 10:52:36.653560 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4863 10:52:36.660013 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4864 10:52:36.662957 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4865 10:52:36.666461 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4866 10:52:36.669547 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4867 10:52:36.672707 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4868 10:52:36.679606 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4869 10:52:36.683570 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4870 10:52:36.686106 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4871 10:52:36.689428 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4872 10:52:36.696393 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4873 10:52:36.699162 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4874 10:52:36.702750 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4875 10:52:36.702834 ==
4876 10:52:36.705917 Dram Type= 6, Freq= 0, CH_1, rank 1
4877 10:52:36.712414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4878 10:52:36.712498 ==
4879 10:52:36.712573 DQS Delay:
4880 10:52:36.712635 DQS0 = 0, DQS1 = 0
4881 10:52:36.715580 DQM Delay:
4882 10:52:36.715665 DQM0 = 42, DQM1 = 33
4883 10:52:36.718963 DQ Delay:
4884 10:52:36.722226 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4885 10:52:36.725725 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4886 10:52:36.729098 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4887 10:52:36.732221 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4888 10:52:36.732304
4889 10:52:36.732369
4890 10:52:36.738369 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4891 10:52:36.741805 CH1 RK1: MR19=808, MR18=2B21
4892 10:52:36.748947 CH1_RK1: MR19=0x808, MR18=0x2B21, DQSOSC=401, MR23=63, INC=163, DEC=108
4893 10:52:36.751671 [RxdqsGatingPostProcess] freq 600
4894 10:52:36.754848 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4895 10:52:36.758456 Pre-setting of DQS Precalculation
4896 10:52:36.764797 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4897 10:52:36.771637 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4898 10:52:36.777978 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4899 10:52:36.778062
4900 10:52:36.778127
4901 10:52:36.781860 [Calibration Summary] 1200 Mbps
4902 10:52:36.784709 CH 0, Rank 0
4903 10:52:36.784791 SW Impedance : PASS
4904 10:52:36.788198 DUTY Scan : NO K
4905 10:52:36.788282 ZQ Calibration : PASS
4906 10:52:36.791755 Jitter Meter : NO K
4907 10:52:36.794679 CBT Training : PASS
4908 10:52:36.794761 Write leveling : PASS
4909 10:52:36.797776 RX DQS gating : PASS
4910 10:52:36.801095 RX DQ/DQS(RDDQC) : PASS
4911 10:52:36.801178 TX DQ/DQS : PASS
4912 10:52:36.804757 RX DATLAT : PASS
4913 10:52:36.807904 RX DQ/DQS(Engine): PASS
4914 10:52:36.807987 TX OE : NO K
4915 10:52:36.811664 All Pass.
4916 10:52:36.811747
4917 10:52:36.811813 CH 0, Rank 1
4918 10:52:36.814080 SW Impedance : PASS
4919 10:52:36.814191 DUTY Scan : NO K
4920 10:52:36.817595 ZQ Calibration : PASS
4921 10:52:36.820960 Jitter Meter : NO K
4922 10:52:36.821043 CBT Training : PASS
4923 10:52:36.824179 Write leveling : PASS
4924 10:52:36.827468 RX DQS gating : PASS
4925 10:52:36.827551 RX DQ/DQS(RDDQC) : PASS
4926 10:52:36.830762 TX DQ/DQS : PASS
4927 10:52:36.834127 RX DATLAT : PASS
4928 10:52:36.834211 RX DQ/DQS(Engine): PASS
4929 10:52:36.837856 TX OE : NO K
4930 10:52:36.837940 All Pass.
4931 10:52:36.838006
4932 10:52:36.841228 CH 1, Rank 0
4933 10:52:36.841311 SW Impedance : PASS
4934 10:52:36.843989 DUTY Scan : NO K
4935 10:52:36.847171 ZQ Calibration : PASS
4936 10:52:36.847255 Jitter Meter : NO K
4937 10:52:36.850570 CBT Training : PASS
4938 10:52:36.854099 Write leveling : PASS
4939 10:52:36.854182 RX DQS gating : PASS
4940 10:52:36.857266 RX DQ/DQS(RDDQC) : PASS
4941 10:52:36.860930 TX DQ/DQS : PASS
4942 10:52:36.861014 RX DATLAT : PASS
4943 10:52:36.864442 RX DQ/DQS(Engine): PASS
4944 10:52:36.864552 TX OE : NO K
4945 10:52:36.867494 All Pass.
4946 10:52:36.867577
4947 10:52:36.867642 CH 1, Rank 1
4948 10:52:36.870581 SW Impedance : PASS
4949 10:52:36.870664 DUTY Scan : NO K
4950 10:52:36.874075 ZQ Calibration : PASS
4951 10:52:36.876952 Jitter Meter : NO K
4952 10:52:36.877036 CBT Training : PASS
4953 10:52:36.880963 Write leveling : PASS
4954 10:52:36.883542 RX DQS gating : PASS
4955 10:52:36.883651 RX DQ/DQS(RDDQC) : PASS
4956 10:52:36.886945 TX DQ/DQS : PASS
4957 10:52:36.890382 RX DATLAT : PASS
4958 10:52:36.890466 RX DQ/DQS(Engine): PASS
4959 10:52:36.893744 TX OE : NO K
4960 10:52:36.893828 All Pass.
4961 10:52:36.893894
4962 10:52:36.897163 DramC Write-DBI off
4963 10:52:36.899999 PER_BANK_REFRESH: Hybrid Mode
4964 10:52:36.900083 TX_TRACKING: ON
4965 10:52:36.910178 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4966 10:52:36.913562 [FAST_K] Save calibration result to emmc
4967 10:52:36.916471 dramc_set_vcore_voltage set vcore to 662500
4968 10:52:36.919689 Read voltage for 933, 3
4969 10:52:36.919772 Vio18 = 0
4970 10:52:36.919839 Vcore = 662500
4971 10:52:36.923372 Vdram = 0
4972 10:52:36.923455 Vddq = 0
4973 10:52:36.923521 Vmddr = 0
4974 10:52:36.929630 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4975 10:52:36.933340 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4976 10:52:36.936549 MEM_TYPE=3, freq_sel=17
4977 10:52:36.940696 sv_algorithm_assistance_LP4_1600
4978 10:52:36.943013 ============ PULL DRAM RESETB DOWN ============
4979 10:52:36.949819 ========== PULL DRAM RESETB DOWN end =========
4980 10:52:36.952766 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 10:52:36.955982 ===================================
4982 10:52:36.959794 LPDDR4 DRAM CONFIGURATION
4983 10:52:36.962864 ===================================
4984 10:52:36.962949 EX_ROW_EN[0] = 0x0
4985 10:52:36.966179 EX_ROW_EN[1] = 0x0
4986 10:52:36.966263 LP4Y_EN = 0x0
4987 10:52:36.969350 WORK_FSP = 0x0
4988 10:52:36.969433 WL = 0x3
4989 10:52:36.972799 RL = 0x3
4990 10:52:36.972884 BL = 0x2
4991 10:52:36.975794 RPST = 0x0
4992 10:52:36.975878 RD_PRE = 0x0
4993 10:52:36.979408 WR_PRE = 0x1
4994 10:52:36.983015 WR_PST = 0x0
4995 10:52:36.983099 DBI_WR = 0x0
4996 10:52:36.986126 DBI_RD = 0x0
4997 10:52:36.986209 OTF = 0x1
4998 10:52:36.989840 ===================================
4999 10:52:36.993063 ===================================
5000 10:52:36.993147 ANA top config
5001 10:52:36.995995 ===================================
5002 10:52:36.999178 DLL_ASYNC_EN = 0
5003 10:52:37.003146 ALL_SLAVE_EN = 1
5004 10:52:37.005540 NEW_RANK_MODE = 1
5005 10:52:37.009230 DLL_IDLE_MODE = 1
5006 10:52:37.009313 LP45_APHY_COMB_EN = 1
5007 10:52:37.012877 TX_ODT_DIS = 1
5008 10:52:37.015746 NEW_8X_MODE = 1
5009 10:52:37.019210 ===================================
5010 10:52:37.022300 ===================================
5011 10:52:37.025717 data_rate = 1866
5012 10:52:37.028690 CKR = 1
5013 10:52:37.032408 DQ_P2S_RATIO = 8
5014 10:52:37.035420 ===================================
5015 10:52:37.035504 CA_P2S_RATIO = 8
5016 10:52:37.038663 DQ_CA_OPEN = 0
5017 10:52:37.042113 DQ_SEMI_OPEN = 0
5018 10:52:37.045641 CA_SEMI_OPEN = 0
5019 10:52:37.048791 CA_FULL_RATE = 0
5020 10:52:37.051694 DQ_CKDIV4_EN = 1
5021 10:52:37.051778 CA_CKDIV4_EN = 1
5022 10:52:37.055377 CA_PREDIV_EN = 0
5023 10:52:37.058528 PH8_DLY = 0
5024 10:52:37.061964 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5025 10:52:37.065308 DQ_AAMCK_DIV = 4
5026 10:52:37.068389 CA_AAMCK_DIV = 4
5027 10:52:37.068487 CA_ADMCK_DIV = 4
5028 10:52:37.071676 DQ_TRACK_CA_EN = 0
5029 10:52:37.074624 CA_PICK = 933
5030 10:52:37.078044 CA_MCKIO = 933
5031 10:52:37.081475 MCKIO_SEMI = 0
5032 10:52:37.084671 PLL_FREQ = 3732
5033 10:52:37.088084 DQ_UI_PI_RATIO = 32
5034 10:52:37.091258 CA_UI_PI_RATIO = 0
5035 10:52:37.095000 ===================================
5036 10:52:37.097808 ===================================
5037 10:52:37.097892 memory_type:LPDDR4
5038 10:52:37.100947 GP_NUM : 10
5039 10:52:37.105235 SRAM_EN : 1
5040 10:52:37.105322 MD32_EN : 0
5041 10:52:37.108398 ===================================
5042 10:52:37.110859 [ANA_INIT] >>>>>>>>>>>>>>
5043 10:52:37.114345 <<<<<< [CONFIGURE PHASE]: ANA_TX
5044 10:52:37.117682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5045 10:52:37.120759 ===================================
5046 10:52:37.124053 data_rate = 1866,PCW = 0X8f00
5047 10:52:37.128226 ===================================
5048 10:52:37.130656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5049 10:52:37.134119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5050 10:52:37.140753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5051 10:52:37.143757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5052 10:52:37.147742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5053 10:52:37.150433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5054 10:52:37.153921 [ANA_INIT] flow start
5055 10:52:37.157374 [ANA_INIT] PLL >>>>>>>>
5056 10:52:37.157457 [ANA_INIT] PLL <<<<<<<<
5057 10:52:37.160404 [ANA_INIT] MIDPI >>>>>>>>
5058 10:52:37.163808 [ANA_INIT] MIDPI <<<<<<<<
5059 10:52:37.167671 [ANA_INIT] DLL >>>>>>>>
5060 10:52:37.167753 [ANA_INIT] flow end
5061 10:52:37.170505 ============ LP4 DIFF to SE enter ============
5062 10:52:37.177072 ============ LP4 DIFF to SE exit ============
5063 10:52:37.177155 [ANA_INIT] <<<<<<<<<<<<<
5064 10:52:37.180193 [Flow] Enable top DCM control >>>>>
5065 10:52:37.183741 [Flow] Enable top DCM control <<<<<
5066 10:52:37.186823 Enable DLL master slave shuffle
5067 10:52:37.193860 ==============================================================
5068 10:52:37.193943 Gating Mode config
5069 10:52:37.200367 ==============================================================
5070 10:52:37.203667 Config description:
5071 10:52:37.213285 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5072 10:52:37.220296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5073 10:52:37.223010 SELPH_MODE 0: By rank 1: By Phase
5074 10:52:37.230002 ==============================================================
5075 10:52:37.233321 GAT_TRACK_EN = 1
5076 10:52:37.236425 RX_GATING_MODE = 2
5077 10:52:37.236570 RX_GATING_TRACK_MODE = 2
5078 10:52:37.239782 SELPH_MODE = 1
5079 10:52:37.243218 PICG_EARLY_EN = 1
5080 10:52:37.246188 VALID_LAT_VALUE = 1
5081 10:52:37.252942 ==============================================================
5082 10:52:37.256260 Enter into Gating configuration >>>>
5083 10:52:37.259304 Exit from Gating configuration <<<<
5084 10:52:37.262683 Enter into DVFS_PRE_config >>>>>
5085 10:52:37.272868 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5086 10:52:37.275744 Exit from DVFS_PRE_config <<<<<
5087 10:52:37.278888 Enter into PICG configuration >>>>
5088 10:52:37.282666 Exit from PICG configuration <<<<
5089 10:52:37.285906 [RX_INPUT] configuration >>>>>
5090 10:52:37.289559 [RX_INPUT] configuration <<<<<
5091 10:52:37.292510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5092 10:52:37.298958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5093 10:52:37.305432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5094 10:52:37.311946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5095 10:52:37.318643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5096 10:52:37.325337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5097 10:52:37.328708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5098 10:52:37.331740 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5099 10:52:37.334842 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5100 10:52:37.341984 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5101 10:52:37.344615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5102 10:52:37.348351 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5103 10:52:37.351959 ===================================
5104 10:52:37.354637 LPDDR4 DRAM CONFIGURATION
5105 10:52:37.358530 ===================================
5106 10:52:37.358613 EX_ROW_EN[0] = 0x0
5107 10:52:37.361666 EX_ROW_EN[1] = 0x0
5108 10:52:37.364489 LP4Y_EN = 0x0
5109 10:52:37.364579 WORK_FSP = 0x0
5110 10:52:37.368315 WL = 0x3
5111 10:52:37.368429 RL = 0x3
5112 10:52:37.371234 BL = 0x2
5113 10:52:37.371315 RPST = 0x0
5114 10:52:37.374361 RD_PRE = 0x0
5115 10:52:37.374443 WR_PRE = 0x1
5116 10:52:37.377665 WR_PST = 0x0
5117 10:52:37.377748 DBI_WR = 0x0
5118 10:52:37.381175 DBI_RD = 0x0
5119 10:52:37.381257 OTF = 0x1
5120 10:52:37.384243 ===================================
5121 10:52:37.387714 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5122 10:52:37.394337 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5123 10:52:37.397354 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5124 10:52:37.401277 ===================================
5125 10:52:37.404538 LPDDR4 DRAM CONFIGURATION
5126 10:52:37.408055 ===================================
5127 10:52:37.408138 EX_ROW_EN[0] = 0x10
5128 10:52:37.410675 EX_ROW_EN[1] = 0x0
5129 10:52:37.414201 LP4Y_EN = 0x0
5130 10:52:37.414283 WORK_FSP = 0x0
5131 10:52:37.417139 WL = 0x3
5132 10:52:37.417221 RL = 0x3
5133 10:52:37.420512 BL = 0x2
5134 10:52:37.420632 RPST = 0x0
5135 10:52:37.424221 RD_PRE = 0x0
5136 10:52:37.424304 WR_PRE = 0x1
5137 10:52:37.427723 WR_PST = 0x0
5138 10:52:37.427810 DBI_WR = 0x0
5139 10:52:37.430802 DBI_RD = 0x0
5140 10:52:37.430885 OTF = 0x1
5141 10:52:37.434119 ===================================
5142 10:52:37.440866 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5143 10:52:37.444857 nWR fixed to 30
5144 10:52:37.448745 [ModeRegInit_LP4] CH0 RK0
5145 10:52:37.448828 [ModeRegInit_LP4] CH0 RK1
5146 10:52:37.451790 [ModeRegInit_LP4] CH1 RK0
5147 10:52:37.454868 [ModeRegInit_LP4] CH1 RK1
5148 10:52:37.454950 match AC timing 9
5149 10:52:37.461366 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5150 10:52:37.464864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5151 10:52:37.467869 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5152 10:52:37.474542 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5153 10:52:37.478133 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5154 10:52:37.478216 ==
5155 10:52:37.481083 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 10:52:37.484235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 10:52:37.484318 ==
5158 10:52:37.491463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5159 10:52:37.498140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5160 10:52:37.500929 [CA 0] Center 37 (7~68) winsize 62
5161 10:52:37.504866 [CA 1] Center 37 (7~68) winsize 62
5162 10:52:37.507872 [CA 2] Center 34 (4~65) winsize 62
5163 10:52:37.510969 [CA 3] Center 34 (4~65) winsize 62
5164 10:52:37.514375 [CA 4] Center 33 (3~64) winsize 62
5165 10:52:37.518239 [CA 5] Center 33 (3~64) winsize 62
5166 10:52:37.518322
5167 10:52:37.521174 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5168 10:52:37.521257
5169 10:52:37.523934 [CATrainingPosCal] consider 1 rank data
5170 10:52:37.527416 u2DelayCellTimex100 = 270/100 ps
5171 10:52:37.530773 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5172 10:52:37.533971 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5173 10:52:37.537297 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5174 10:52:37.540810 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5175 10:52:37.546984 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5176 10:52:37.550644 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5177 10:52:37.550727
5178 10:52:37.553693 CA PerBit enable=1, Macro0, CA PI delay=33
5179 10:52:37.553775
5180 10:52:37.557750 [CBTSetCACLKResult] CA Dly = 33
5181 10:52:37.557832 CS Dly: 7 (0~38)
5182 10:52:37.557898 ==
5183 10:52:37.560182 Dram Type= 6, Freq= 0, CH_0, rank 1
5184 10:52:37.566556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 10:52:37.566639 ==
5186 10:52:37.570221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5187 10:52:37.576588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5188 10:52:37.579937 [CA 0] Center 37 (7~68) winsize 62
5189 10:52:37.583188 [CA 1] Center 37 (7~68) winsize 62
5190 10:52:37.587102 [CA 2] Center 34 (4~65) winsize 62
5191 10:52:37.589618 [CA 3] Center 34 (4~65) winsize 62
5192 10:52:37.593327 [CA 4] Center 33 (3~64) winsize 62
5193 10:52:37.596456 [CA 5] Center 33 (3~63) winsize 61
5194 10:52:37.596594
5195 10:52:37.599695 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5196 10:52:37.599778
5197 10:52:37.603069 [CATrainingPosCal] consider 2 rank data
5198 10:52:37.606114 u2DelayCellTimex100 = 270/100 ps
5199 10:52:37.609733 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5200 10:52:37.616326 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5201 10:52:37.619361 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5202 10:52:37.623517 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5203 10:52:37.625965 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5204 10:52:37.629190 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5205 10:52:37.629272
5206 10:52:37.632778 CA PerBit enable=1, Macro0, CA PI delay=33
5207 10:52:37.632861
5208 10:52:37.636333 [CBTSetCACLKResult] CA Dly = 33
5209 10:52:37.639696 CS Dly: 7 (0~39)
5210 10:52:37.639804
5211 10:52:37.642635 ----->DramcWriteLeveling(PI) begin...
5212 10:52:37.642719 ==
5213 10:52:37.646518 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 10:52:37.649271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 10:52:37.649355 ==
5216 10:52:37.652821 Write leveling (Byte 0): 34 => 34
5217 10:52:37.655749 Write leveling (Byte 1): 30 => 30
5218 10:52:37.659350 DramcWriteLeveling(PI) end<-----
5219 10:52:37.659432
5220 10:52:37.659497 ==
5221 10:52:37.662449 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 10:52:37.665529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 10:52:37.665612 ==
5224 10:52:37.669113 [Gating] SW mode calibration
5225 10:52:37.675879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5226 10:52:37.681969 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5227 10:52:37.685281 0 14 0 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
5228 10:52:37.688784 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5229 10:52:37.695339 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5230 10:52:37.698397 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5231 10:52:37.702346 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5232 10:52:37.708998 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5233 10:52:37.711591 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5234 10:52:37.715495 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
5235 10:52:37.721853 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5236 10:52:37.724975 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5237 10:52:37.728067 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5238 10:52:37.734872 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5239 10:52:37.738367 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5240 10:52:37.741635 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5241 10:52:37.748121 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5242 10:52:37.751492 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5243 10:52:37.754833 1 0 0 | B1->B0 | 3131 4545 | 1 0 | (0 0) (0 0)
5244 10:52:37.761272 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 10:52:37.764269 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 10:52:37.767828 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5247 10:52:37.774263 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5248 10:52:37.777951 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 10:52:37.780933 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 10:52:37.788022 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5251 10:52:37.791019 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5252 10:52:37.794294 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 10:52:37.800911 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 10:52:37.805149 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 10:52:37.807607 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 10:52:37.813890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 10:52:37.817697 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 10:52:37.820672 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 10:52:37.827219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 10:52:37.830822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 10:52:37.833671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 10:52:37.840457 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 10:52:37.844207 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 10:52:37.846778 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 10:52:37.853647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5266 10:52:37.856903 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5267 10:52:37.860652 Total UI for P1: 0, mck2ui 16
5268 10:52:37.863242 best dqsien dly found for B0: ( 1, 2, 26)
5269 10:52:37.866969 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5270 10:52:37.873539 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5271 10:52:37.877010 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5272 10:52:37.879909 Total UI for P1: 0, mck2ui 16
5273 10:52:37.883659 best dqsien dly found for B1: ( 1, 3, 2)
5274 10:52:37.886350 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5275 10:52:37.889821 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5276 10:52:37.889906
5277 10:52:37.892822 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5278 10:52:37.896141 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5279 10:52:37.899385 [Gating] SW calibration Done
5280 10:52:37.899470 ==
5281 10:52:37.903007 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 10:52:37.909388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 10:52:37.909473 ==
5284 10:52:37.909559 RX Vref Scan: 0
5285 10:52:37.909638
5286 10:52:37.912700 RX Vref 0 -> 0, step: 1
5287 10:52:37.912785
5288 10:52:37.916280 RX Delay -80 -> 252, step: 8
5289 10:52:37.919230 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5290 10:52:37.922767 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5291 10:52:37.926247 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5292 10:52:37.929212 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5293 10:52:37.935717 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5294 10:52:37.939082 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5295 10:52:37.942618 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5296 10:52:37.945576 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5297 10:52:37.948693 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5298 10:52:37.956065 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5299 10:52:37.959122 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5300 10:52:37.962076 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5301 10:52:37.965571 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5302 10:52:37.968672 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5303 10:52:37.975155 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5304 10:52:37.978364 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5305 10:52:37.978451 ==
5306 10:52:37.981750 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 10:52:37.985071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 10:52:37.985158 ==
5309 10:52:37.988072 DQS Delay:
5310 10:52:37.988158 DQS0 = 0, DQS1 = 0
5311 10:52:37.988244 DQM Delay:
5312 10:52:37.991599 DQM0 = 97, DQM1 = 86
5313 10:52:37.991685 DQ Delay:
5314 10:52:37.994828 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5315 10:52:37.998712 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5316 10:52:38.001518 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5317 10:52:38.005137 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5318 10:52:38.005223
5319 10:52:38.005308
5320 10:52:38.005388 ==
5321 10:52:38.008467 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 10:52:38.015056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 10:52:38.015143 ==
5324 10:52:38.015228
5325 10:52:38.015308
5326 10:52:38.018039 TX Vref Scan disable
5327 10:52:38.018125 == TX Byte 0 ==
5328 10:52:38.021505 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5329 10:52:38.028092 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5330 10:52:38.028179 == TX Byte 1 ==
5331 10:52:38.031309 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5332 10:52:38.037932 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5333 10:52:38.038022 ==
5334 10:52:38.041312 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 10:52:38.044960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 10:52:38.045047 ==
5337 10:52:38.045133
5338 10:52:38.045212
5339 10:52:38.047668 TX Vref Scan disable
5340 10:52:38.051011 == TX Byte 0 ==
5341 10:52:38.054410 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5342 10:52:38.057762 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5343 10:52:38.060989 == TX Byte 1 ==
5344 10:52:38.064691 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5345 10:52:38.067432 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5346 10:52:38.067519
5347 10:52:38.071159 [DATLAT]
5348 10:52:38.071246 Freq=933, CH0 RK0
5349 10:52:38.071332
5350 10:52:38.074274 DATLAT Default: 0xd
5351 10:52:38.074360 0, 0xFFFF, sum = 0
5352 10:52:38.077736 1, 0xFFFF, sum = 0
5353 10:52:38.077823 2, 0xFFFF, sum = 0
5354 10:52:38.080900 3, 0xFFFF, sum = 0
5355 10:52:38.080987 4, 0xFFFF, sum = 0
5356 10:52:38.084020 5, 0xFFFF, sum = 0
5357 10:52:38.084107 6, 0xFFFF, sum = 0
5358 10:52:38.087443 7, 0xFFFF, sum = 0
5359 10:52:38.087531 8, 0xFFFF, sum = 0
5360 10:52:38.090462 9, 0xFFFF, sum = 0
5361 10:52:38.090571 10, 0x0, sum = 1
5362 10:52:38.094496 11, 0x0, sum = 2
5363 10:52:38.094579 12, 0x0, sum = 3
5364 10:52:38.097545 13, 0x0, sum = 4
5365 10:52:38.097628 best_step = 11
5366 10:52:38.097692
5367 10:52:38.097752 ==
5368 10:52:38.101201 Dram Type= 6, Freq= 0, CH_0, rank 0
5369 10:52:38.107282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 10:52:38.107364 ==
5371 10:52:38.107428 RX Vref Scan: 1
5372 10:52:38.107488
5373 10:52:38.110620 RX Vref 0 -> 0, step: 1
5374 10:52:38.110702
5375 10:52:38.113839 RX Delay -61 -> 252, step: 4
5376 10:52:38.113920
5377 10:52:38.117282 Set Vref, RX VrefLevel [Byte0]: 55
5378 10:52:38.120464 [Byte1]: 49
5379 10:52:38.120553
5380 10:52:38.123908 Final RX Vref Byte 0 = 55 to rank0
5381 10:52:38.127236 Final RX Vref Byte 1 = 49 to rank0
5382 10:52:38.130568 Final RX Vref Byte 0 = 55 to rank1
5383 10:52:38.133519 Final RX Vref Byte 1 = 49 to rank1==
5384 10:52:38.137072 Dram Type= 6, Freq= 0, CH_0, rank 0
5385 10:52:38.140694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 10:52:38.140776 ==
5387 10:52:38.143377 DQS Delay:
5388 10:52:38.143458 DQS0 = 0, DQS1 = 0
5389 10:52:38.146553 DQM Delay:
5390 10:52:38.146634 DQM0 = 96, DQM1 = 85
5391 10:52:38.146699 DQ Delay:
5392 10:52:38.150304 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5393 10:52:38.153706 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5394 10:52:38.156988 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5395 10:52:38.159844 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =94
5396 10:52:38.159926
5397 10:52:38.159989
5398 10:52:38.170268 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5399 10:52:38.173726 CH0 RK0: MR19=505, MR18=2D13
5400 10:52:38.179835 CH0_RK0: MR19=0x505, MR18=0x2D13, DQSOSC=407, MR23=63, INC=65, DEC=43
5401 10:52:38.179917
5402 10:52:38.183541 ----->DramcWriteLeveling(PI) begin...
5403 10:52:38.183625 ==
5404 10:52:38.186224 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 10:52:38.190479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 10:52:38.190562 ==
5407 10:52:38.192937 Write leveling (Byte 0): 33 => 33
5408 10:52:38.196230 Write leveling (Byte 1): 33 => 33
5409 10:52:38.199796 DramcWriteLeveling(PI) end<-----
5410 10:52:38.199897
5411 10:52:38.199987 ==
5412 10:52:38.202844 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 10:52:38.206126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 10:52:38.206209 ==
5415 10:52:38.209286 [Gating] SW mode calibration
5416 10:52:38.216283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5417 10:52:38.222995 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5418 10:52:38.225705 0 14 0 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
5419 10:52:38.229298 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 10:52:38.235575 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5421 10:52:38.239549 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 10:52:38.242318 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 10:52:38.248860 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 10:52:38.252370 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 10:52:38.255476 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5426 10:52:38.262106 0 15 0 | B1->B0 | 2e2e 2929 | 1 0 | (0 0) (0 0)
5427 10:52:38.265397 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 10:52:38.269169 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5429 10:52:38.275629 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 10:52:38.278845 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 10:52:38.282024 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 10:52:38.289077 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 10:52:38.291764 0 15 28 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5434 10:52:38.295040 1 0 0 | B1->B0 | 4343 4444 | 0 0 | (1 1) (0 0)
5435 10:52:38.302223 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 10:52:38.305573 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 10:52:38.309238 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 10:52:38.315256 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 10:52:38.318176 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 10:52:38.321763 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 10:52:38.328275 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5442 10:52:38.331567 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5443 10:52:38.334440 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 10:52:38.341071 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 10:52:38.344966 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 10:52:38.347698 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 10:52:38.354460 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 10:52:38.358033 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 10:52:38.360963 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 10:52:38.367502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 10:52:38.371248 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 10:52:38.374648 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 10:52:38.381027 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 10:52:38.384310 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 10:52:38.387269 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 10:52:38.393876 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 10:52:38.397121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5458 10:52:38.400493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5459 10:52:38.404504 Total UI for P1: 0, mck2ui 16
5460 10:52:38.407319 best dqsien dly found for B0: ( 1, 2, 28)
5461 10:52:38.413985 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5462 10:52:38.417165 Total UI for P1: 0, mck2ui 16
5463 10:52:38.420407 best dqsien dly found for B1: ( 1, 3, 0)
5464 10:52:38.423634 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5465 10:52:38.426889 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5466 10:52:38.426973
5467 10:52:38.430226 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5468 10:52:38.433416 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5469 10:52:38.436807 [Gating] SW calibration Done
5470 10:52:38.436890 ==
5471 10:52:38.439931 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 10:52:38.443964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 10:52:38.444048 ==
5474 10:52:38.446418 RX Vref Scan: 0
5475 10:52:38.446502
5476 10:52:38.449733 RX Vref 0 -> 0, step: 1
5477 10:52:38.449817
5478 10:52:38.449883 RX Delay -80 -> 252, step: 8
5479 10:52:38.456366 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5480 10:52:38.460425 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5481 10:52:38.463003 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5482 10:52:38.466430 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5483 10:52:38.469759 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5484 10:52:38.473102 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5485 10:52:38.479818 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5486 10:52:38.483362 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5487 10:52:38.486027 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5488 10:52:38.489728 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5489 10:52:38.493103 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5490 10:52:38.499676 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5491 10:52:38.502892 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5492 10:52:38.505763 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5493 10:52:38.509367 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5494 10:52:38.512349 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5495 10:52:38.512432 ==
5496 10:52:38.516128 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 10:52:38.522582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 10:52:38.522666 ==
5499 10:52:38.522731 DQS Delay:
5500 10:52:38.525733 DQS0 = 0, DQS1 = 0
5501 10:52:38.525816 DQM Delay:
5502 10:52:38.529197 DQM0 = 96, DQM1 = 87
5503 10:52:38.529280 DQ Delay:
5504 10:52:38.532488 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5505 10:52:38.535877 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5506 10:52:38.539149 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5507 10:52:38.542426 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5508 10:52:38.542508
5509 10:52:38.542573
5510 10:52:38.542632 ==
5511 10:52:38.545514 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 10:52:38.548908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 10:52:38.549003 ==
5514 10:52:38.549097
5515 10:52:38.549160
5516 10:52:38.552012 TX Vref Scan disable
5517 10:52:38.555922 == TX Byte 0 ==
5518 10:52:38.558632 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5519 10:52:38.562189 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5520 10:52:38.565433 == TX Byte 1 ==
5521 10:52:38.568856 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5522 10:52:38.571883 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5523 10:52:38.571967 ==
5524 10:52:38.575425 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 10:52:38.581972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 10:52:38.582056 ==
5527 10:52:38.582121
5528 10:52:38.582180
5529 10:52:38.582237 TX Vref Scan disable
5530 10:52:38.585902 == TX Byte 0 ==
5531 10:52:38.588808 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5532 10:52:38.596047 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5533 10:52:38.596131 == TX Byte 1 ==
5534 10:52:38.599313 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5535 10:52:38.606006 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5536 10:52:38.606089
5537 10:52:38.606155 [DATLAT]
5538 10:52:38.606213 Freq=933, CH0 RK1
5539 10:52:38.606271
5540 10:52:38.608922 DATLAT Default: 0xb
5541 10:52:38.609004 0, 0xFFFF, sum = 0
5542 10:52:38.612075 1, 0xFFFF, sum = 0
5543 10:52:38.615570 2, 0xFFFF, sum = 0
5544 10:52:38.615654 3, 0xFFFF, sum = 0
5545 10:52:38.618571 4, 0xFFFF, sum = 0
5546 10:52:38.618656 5, 0xFFFF, sum = 0
5547 10:52:38.622215 6, 0xFFFF, sum = 0
5548 10:52:38.622299 7, 0xFFFF, sum = 0
5549 10:52:38.625079 8, 0xFFFF, sum = 0
5550 10:52:38.625164 9, 0xFFFF, sum = 0
5551 10:52:38.628575 10, 0x0, sum = 1
5552 10:52:38.628660 11, 0x0, sum = 2
5553 10:52:38.632064 12, 0x0, sum = 3
5554 10:52:38.632148 13, 0x0, sum = 4
5555 10:52:38.632215 best_step = 11
5556 10:52:38.635392
5557 10:52:38.635476 ==
5558 10:52:38.638916 Dram Type= 6, Freq= 0, CH_0, rank 1
5559 10:52:38.641989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 10:52:38.642072 ==
5561 10:52:38.642138 RX Vref Scan: 0
5562 10:52:38.642198
5563 10:52:38.645108 RX Vref 0 -> 0, step: 1
5564 10:52:38.645191
5565 10:52:38.648247 RX Delay -69 -> 252, step: 4
5566 10:52:38.655405 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5567 10:52:38.658096 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5568 10:52:38.662084 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5569 10:52:38.665041 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5570 10:52:38.667931 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5571 10:52:38.671789 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5572 10:52:38.678497 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5573 10:52:38.681466 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5574 10:52:38.684827 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5575 10:52:38.687755 iDelay=199, Bit 9, Center 74 (-17 ~ 166) 184
5576 10:52:38.691197 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5577 10:52:38.697913 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5578 10:52:38.701130 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5579 10:52:38.704699 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5580 10:52:38.707640 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5581 10:52:38.711074 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5582 10:52:38.714385 ==
5583 10:52:38.714466 Dram Type= 6, Freq= 0, CH_0, rank 1
5584 10:52:38.721172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 10:52:38.721254 ==
5586 10:52:38.721318 DQS Delay:
5587 10:52:38.724344 DQS0 = 0, DQS1 = 0
5588 10:52:38.724424 DQM Delay:
5589 10:52:38.727399 DQM0 = 95, DQM1 = 86
5590 10:52:38.727492 DQ Delay:
5591 10:52:38.730625 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =92
5592 10:52:38.733892 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5593 10:52:38.737490 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5594 10:52:38.740882 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =92
5595 10:52:38.740964
5596 10:52:38.741028
5597 10:52:38.747210 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5598 10:52:38.750929 CH0 RK1: MR19=504, MR18=29FA
5599 10:52:38.757595 CH0_RK1: MR19=0x504, MR18=0x29FA, DQSOSC=408, MR23=63, INC=65, DEC=43
5600 10:52:38.760405 [RxdqsGatingPostProcess] freq 933
5601 10:52:38.767130 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5602 10:52:38.770658 best DQS0 dly(2T, 0.5T) = (0, 10)
5603 10:52:38.770741 best DQS1 dly(2T, 0.5T) = (0, 11)
5604 10:52:38.773796 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5605 10:52:38.777003 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5606 10:52:38.779994 best DQS0 dly(2T, 0.5T) = (0, 10)
5607 10:52:38.783915 best DQS1 dly(2T, 0.5T) = (0, 11)
5608 10:52:38.787337 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5609 10:52:38.790145 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5610 10:52:38.793545 Pre-setting of DQS Precalculation
5611 10:52:38.799952 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5612 10:52:38.800036 ==
5613 10:52:38.803393 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 10:52:38.806719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 10:52:38.806802 ==
5616 10:52:38.813123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5617 10:52:38.819616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5618 10:52:38.822795 [CA 0] Center 36 (6~67) winsize 62
5619 10:52:38.826544 [CA 1] Center 36 (6~67) winsize 62
5620 10:52:38.829593 [CA 2] Center 34 (4~65) winsize 62
5621 10:52:38.833083 [CA 3] Center 33 (3~64) winsize 62
5622 10:52:38.836121 [CA 4] Center 34 (4~64) winsize 61
5623 10:52:38.839602 [CA 5] Center 33 (3~64) winsize 62
5624 10:52:38.839688
5625 10:52:38.843052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5626 10:52:38.843135
5627 10:52:38.845994 [CATrainingPosCal] consider 1 rank data
5628 10:52:38.849623 u2DelayCellTimex100 = 270/100 ps
5629 10:52:38.852471 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5630 10:52:38.855870 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5631 10:52:38.860048 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5632 10:52:38.862985 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5633 10:52:38.865935 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5634 10:52:38.869163 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5635 10:52:38.869245
5636 10:52:38.875901 CA PerBit enable=1, Macro0, CA PI delay=33
5637 10:52:38.875985
5638 10:52:38.876050 [CBTSetCACLKResult] CA Dly = 33
5639 10:52:38.879098 CS Dly: 6 (0~37)
5640 10:52:38.879181 ==
5641 10:52:38.882263 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 10:52:38.886043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 10:52:38.886129 ==
5644 10:52:38.892482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5645 10:52:38.898826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5646 10:52:38.902443 [CA 0] Center 36 (6~67) winsize 62
5647 10:52:38.905322 [CA 1] Center 37 (7~67) winsize 61
5648 10:52:38.909021 [CA 2] Center 34 (3~65) winsize 63
5649 10:52:38.912422 [CA 3] Center 33 (3~64) winsize 62
5650 10:52:38.915228 [CA 4] Center 34 (3~65) winsize 63
5651 10:52:38.919002 [CA 5] Center 33 (3~64) winsize 62
5652 10:52:38.919085
5653 10:52:38.922309 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5654 10:52:38.922392
5655 10:52:38.925345 [CATrainingPosCal] consider 2 rank data
5656 10:52:38.928457 u2DelayCellTimex100 = 270/100 ps
5657 10:52:38.931943 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5658 10:52:38.935422 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5659 10:52:38.939348 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5660 10:52:38.942080 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5661 10:52:38.945246 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5662 10:52:38.951897 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5663 10:52:38.951982
5664 10:52:38.954978 CA PerBit enable=1, Macro0, CA PI delay=33
5665 10:52:38.955061
5666 10:52:38.958069 [CBTSetCACLKResult] CA Dly = 33
5667 10:52:38.958152 CS Dly: 7 (0~39)
5668 10:52:38.958218
5669 10:52:38.961638 ----->DramcWriteLeveling(PI) begin...
5670 10:52:38.961722 ==
5671 10:52:38.964778 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 10:52:38.971669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 10:52:38.971753 ==
5674 10:52:38.974737 Write leveling (Byte 0): 24 => 24
5675 10:52:38.977751 Write leveling (Byte 1): 29 => 29
5676 10:52:38.977834 DramcWriteLeveling(PI) end<-----
5677 10:52:38.977899
5678 10:52:38.981068 ==
5679 10:52:38.984352 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 10:52:38.987560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 10:52:38.987644 ==
5682 10:52:38.990979 [Gating] SW mode calibration
5683 10:52:38.997831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5684 10:52:39.001232 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5685 10:52:39.007666 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5686 10:52:39.011263 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5687 10:52:39.014553 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5688 10:52:39.021519 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5689 10:52:39.024166 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5690 10:52:39.027369 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5691 10:52:39.033884 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5692 10:52:39.037472 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (1 0) (1 0)
5693 10:52:39.040310 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5694 10:52:39.047085 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5695 10:52:39.050935 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5696 10:52:39.053881 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5697 10:52:39.060820 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5698 10:52:39.064089 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5699 10:52:39.066761 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5700 10:52:39.074160 0 15 28 | B1->B0 | 3333 3b3b | 0 1 | (1 1) (0 0)
5701 10:52:39.077683 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 10:52:39.080616 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5703 10:52:39.086756 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 10:52:39.090454 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 10:52:39.093388 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 10:52:39.100167 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 10:52:39.103966 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5708 10:52:39.106894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5709 10:52:39.113386 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 10:52:39.116468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 10:52:39.120030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 10:52:39.126722 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 10:52:39.130000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 10:52:39.132989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 10:52:39.139455 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 10:52:39.143353 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 10:52:39.146437 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 10:52:39.153194 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 10:52:39.156087 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 10:52:39.159346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 10:52:39.165622 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5722 10:52:39.169511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5723 10:52:39.172618 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5724 10:52:39.179060 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5725 10:52:39.182855 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5726 10:52:39.185874 Total UI for P1: 0, mck2ui 16
5727 10:52:39.189009 best dqsien dly found for B0: ( 1, 2, 24)
5728 10:52:39.192186 Total UI for P1: 0, mck2ui 16
5729 10:52:39.195587 best dqsien dly found for B1: ( 1, 2, 28)
5730 10:52:39.199062 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5731 10:52:39.202368 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5732 10:52:39.202451
5733 10:52:39.205935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5734 10:52:39.208938 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5735 10:52:39.211914 [Gating] SW calibration Done
5736 10:52:39.211997 ==
5737 10:52:39.215291 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 10:52:39.222085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 10:52:39.222169 ==
5740 10:52:39.222235 RX Vref Scan: 0
5741 10:52:39.222294
5742 10:52:39.225426 RX Vref 0 -> 0, step: 1
5743 10:52:39.225509
5744 10:52:39.228500 RX Delay -80 -> 252, step: 8
5745 10:52:39.232109 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5746 10:52:39.235367 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5747 10:52:39.238626 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5748 10:52:39.241648 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5749 10:52:39.248435 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5750 10:52:39.251802 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5751 10:52:39.255035 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5752 10:52:39.258244 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5753 10:52:39.261854 iDelay=208, Bit 8, Center 83 (-16 ~ 183) 200
5754 10:52:39.264562 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5755 10:52:39.271501 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5756 10:52:39.274418 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5757 10:52:39.277866 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5758 10:52:39.281267 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5759 10:52:39.284270 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5760 10:52:39.290997 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5761 10:52:39.291097 ==
5762 10:52:39.294089 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 10:52:39.297839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 10:52:39.297928 ==
5765 10:52:39.298009 DQS Delay:
5766 10:52:39.300985 DQS0 = 0, DQS1 = 0
5767 10:52:39.301070 DQM Delay:
5768 10:52:39.304273 DQM0 = 100, DQM1 = 92
5769 10:52:39.304357 DQ Delay:
5770 10:52:39.307387 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5771 10:52:39.310861 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =99
5772 10:52:39.314115 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =83
5773 10:52:39.317802 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5774 10:52:39.317887
5775 10:52:39.317952
5776 10:52:39.318013 ==
5777 10:52:39.320784 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 10:52:39.327289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 10:52:39.327385 ==
5780 10:52:39.327452
5781 10:52:39.327512
5782 10:52:39.327570 TX Vref Scan disable
5783 10:52:39.330717 == TX Byte 0 ==
5784 10:52:39.333859 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5785 10:52:39.340487 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5786 10:52:39.340580 == TX Byte 1 ==
5787 10:52:39.343831 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5788 10:52:39.350525 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5789 10:52:39.350612 ==
5790 10:52:39.353693 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 10:52:39.356786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 10:52:39.356871 ==
5793 10:52:39.356939
5794 10:52:39.357000
5795 10:52:39.360097 TX Vref Scan disable
5796 10:52:39.360181 == TX Byte 0 ==
5797 10:52:39.366918 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5798 10:52:39.370730 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5799 10:52:39.373842 == TX Byte 1 ==
5800 10:52:39.376581 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5801 10:52:39.379802 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5802 10:52:39.379893
5803 10:52:39.379958 [DATLAT]
5804 10:52:39.383696 Freq=933, CH1 RK0
5805 10:52:39.383781
5806 10:52:39.387094 DATLAT Default: 0xd
5807 10:52:39.387178 0, 0xFFFF, sum = 0
5808 10:52:39.390197 1, 0xFFFF, sum = 0
5809 10:52:39.390286 2, 0xFFFF, sum = 0
5810 10:52:39.393554 3, 0xFFFF, sum = 0
5811 10:52:39.393641 4, 0xFFFF, sum = 0
5812 10:52:39.396507 5, 0xFFFF, sum = 0
5813 10:52:39.396633 6, 0xFFFF, sum = 0
5814 10:52:39.400049 7, 0xFFFF, sum = 0
5815 10:52:39.400133 8, 0xFFFF, sum = 0
5816 10:52:39.403360 9, 0xFFFF, sum = 0
5817 10:52:39.403444 10, 0x0, sum = 1
5818 10:52:39.406395 11, 0x0, sum = 2
5819 10:52:39.406478 12, 0x0, sum = 3
5820 10:52:39.409641 13, 0x0, sum = 4
5821 10:52:39.409724 best_step = 11
5822 10:52:39.409789
5823 10:52:39.409883 ==
5824 10:52:39.412612 Dram Type= 6, Freq= 0, CH_1, rank 0
5825 10:52:39.416880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 10:52:39.419401 ==
5827 10:52:39.419483 RX Vref Scan: 1
5828 10:52:39.419548
5829 10:52:39.422918 RX Vref 0 -> 0, step: 1
5830 10:52:39.423029
5831 10:52:39.425835 RX Delay -61 -> 252, step: 4
5832 10:52:39.425944
5833 10:52:39.429537 Set Vref, RX VrefLevel [Byte0]: 47
5834 10:52:39.432605 [Byte1]: 54
5835 10:52:39.432722
5836 10:52:39.435687 Final RX Vref Byte 0 = 47 to rank0
5837 10:52:39.439419 Final RX Vref Byte 1 = 54 to rank0
5838 10:52:39.443020 Final RX Vref Byte 0 = 47 to rank1
5839 10:52:39.445583 Final RX Vref Byte 1 = 54 to rank1==
5840 10:52:39.449353 Dram Type= 6, Freq= 0, CH_1, rank 0
5841 10:52:39.452624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 10:52:39.452741 ==
5843 10:52:39.455919 DQS Delay:
5844 10:52:39.456035 DQS0 = 0, DQS1 = 0
5845 10:52:39.456138 DQM Delay:
5846 10:52:39.458914 DQM0 = 100, DQM1 = 94
5847 10:52:39.459022 DQ Delay:
5848 10:52:39.462323 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5849 10:52:39.465494 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5850 10:52:39.469267 DQ8 =80, DQ9 =86, DQ10 =94, DQ11 =84
5851 10:52:39.472014 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5852 10:52:39.475662
5853 10:52:39.475744
5854 10:52:39.481926 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5855 10:52:39.485204 CH1 RK0: MR19=505, MR18=1E0E
5856 10:52:39.491771 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5857 10:52:39.491855
5858 10:52:39.495460 ----->DramcWriteLeveling(PI) begin...
5859 10:52:39.495544 ==
5860 10:52:39.498145 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 10:52:39.501637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 10:52:39.501722 ==
5863 10:52:39.504513 Write leveling (Byte 0): 24 => 24
5864 10:52:39.507916 Write leveling (Byte 1): 31 => 31
5865 10:52:39.511609 DramcWriteLeveling(PI) end<-----
5866 10:52:39.511692
5867 10:52:39.511757 ==
5868 10:52:39.514727 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 10:52:39.518294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 10:52:39.518378 ==
5871 10:52:39.521336 [Gating] SW mode calibration
5872 10:52:39.528018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5873 10:52:39.534724 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5874 10:52:39.538056 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5875 10:52:39.544354 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5876 10:52:39.547688 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5877 10:52:39.551292 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5878 10:52:39.557568 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5879 10:52:39.561164 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5880 10:52:39.564203 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
5881 10:52:39.570738 0 14 28 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
5882 10:52:39.573962 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5883 10:52:39.577407 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5884 10:52:39.584234 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5885 10:52:39.587240 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5886 10:52:39.590580 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5887 10:52:39.597313 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5888 10:52:39.600859 0 15 24 | B1->B0 | 2c2b 2525 | 1 0 | (1 1) (0 0)
5889 10:52:39.603890 0 15 28 | B1->B0 | 3d3d 3737 | 0 0 | (0 0) (0 0)
5890 10:52:39.610234 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5891 10:52:39.613702 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5892 10:52:39.616880 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 10:52:39.623568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5894 10:52:39.626630 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 10:52:39.630236 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5896 10:52:39.636794 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5897 10:52:39.640151 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5898 10:52:39.643190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 10:52:39.649708 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 10:52:39.653152 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 10:52:39.656398 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 10:52:39.663328 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 10:52:39.666298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 10:52:39.669939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 10:52:39.676416 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 10:52:39.679629 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 10:52:39.682754 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 10:52:39.689837 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 10:52:39.692947 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5910 10:52:39.696261 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5911 10:52:39.702892 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5912 10:52:39.706588 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5913 10:52:39.709982 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5914 10:52:39.716034 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5915 10:52:39.716118 Total UI for P1: 0, mck2ui 16
5916 10:52:39.722513 best dqsien dly found for B0: ( 1, 2, 26)
5917 10:52:39.722599 Total UI for P1: 0, mck2ui 16
5918 10:52:39.726598 best dqsien dly found for B1: ( 1, 2, 26)
5919 10:52:39.732372 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5920 10:52:39.736061 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5921 10:52:39.736146
5922 10:52:39.739447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5923 10:52:39.742148 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5924 10:52:39.745648 [Gating] SW calibration Done
5925 10:52:39.745733 ==
5926 10:52:39.748810 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 10:52:39.752104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 10:52:39.752190 ==
5929 10:52:39.755359 RX Vref Scan: 0
5930 10:52:39.755444
5931 10:52:39.755528 RX Vref 0 -> 0, step: 1
5932 10:52:39.755608
5933 10:52:39.758960 RX Delay -80 -> 252, step: 8
5934 10:52:39.762059 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5935 10:52:39.769257 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5936 10:52:39.772073 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5937 10:52:39.775454 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5938 10:52:39.778430 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5939 10:52:39.781910 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5940 10:52:39.785319 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5941 10:52:39.791935 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5942 10:52:39.794909 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5943 10:52:39.798182 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5944 10:52:39.802065 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5945 10:52:39.804924 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5946 10:52:39.811359 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5947 10:52:39.815141 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5948 10:52:39.818052 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5949 10:52:39.821289 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5950 10:52:39.821372 ==
5951 10:52:39.824474 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 10:52:39.831180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 10:52:39.831265 ==
5954 10:52:39.831331 DQS Delay:
5955 10:52:39.831390 DQS0 = 0, DQS1 = 0
5956 10:52:39.835369 DQM Delay:
5957 10:52:39.835453 DQM0 = 99, DQM1 = 91
5958 10:52:39.838190 DQ Delay:
5959 10:52:39.841771 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5960 10:52:39.844414 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5961 10:52:39.848231 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5962 10:52:39.851055 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5963 10:52:39.851137
5964 10:52:39.851201
5965 10:52:39.851260 ==
5966 10:52:39.854440 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 10:52:39.857704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 10:52:39.857787 ==
5969 10:52:39.857851
5970 10:52:39.857909
5971 10:52:39.860931 TX Vref Scan disable
5972 10:52:39.861029 == TX Byte 0 ==
5973 10:52:39.867879 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5974 10:52:39.870868 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5975 10:52:39.870950 == TX Byte 1 ==
5976 10:52:39.877701 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5977 10:52:39.881156 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5978 10:52:39.881241 ==
5979 10:52:39.884465 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 10:52:39.888188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 10:52:39.888272 ==
5982 10:52:39.891065
5983 10:52:39.891147
5984 10:52:39.891212 TX Vref Scan disable
5985 10:52:39.894041 == TX Byte 0 ==
5986 10:52:39.897299 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5987 10:52:39.904247 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5988 10:52:39.904334 == TX Byte 1 ==
5989 10:52:39.907239 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5990 10:52:39.914551 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5991 10:52:39.914661
5992 10:52:39.914748 [DATLAT]
5993 10:52:39.914811 Freq=933, CH1 RK1
5994 10:52:39.914871
5995 10:52:39.917071 DATLAT Default: 0xb
5996 10:52:39.920412 0, 0xFFFF, sum = 0
5997 10:52:39.920512 1, 0xFFFF, sum = 0
5998 10:52:39.924622 2, 0xFFFF, sum = 0
5999 10:52:39.924706 3, 0xFFFF, sum = 0
6000 10:52:39.927811 4, 0xFFFF, sum = 0
6001 10:52:39.927896 5, 0xFFFF, sum = 0
6002 10:52:39.930488 6, 0xFFFF, sum = 0
6003 10:52:39.930597 7, 0xFFFF, sum = 0
6004 10:52:39.933724 8, 0xFFFF, sum = 0
6005 10:52:39.933808 9, 0xFFFF, sum = 0
6006 10:52:39.937178 10, 0x0, sum = 1
6007 10:52:39.937262 11, 0x0, sum = 2
6008 10:52:39.940502 12, 0x0, sum = 3
6009 10:52:39.940621 13, 0x0, sum = 4
6010 10:52:39.943989 best_step = 11
6011 10:52:39.944086
6012 10:52:39.944180 ==
6013 10:52:39.946830 Dram Type= 6, Freq= 0, CH_1, rank 1
6014 10:52:39.950190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6015 10:52:39.950275 ==
6016 10:52:39.950341 RX Vref Scan: 0
6017 10:52:39.950405
6018 10:52:39.953468 RX Vref 0 -> 0, step: 1
6019 10:52:39.953552
6020 10:52:39.956900 RX Delay -61 -> 252, step: 4
6021 10:52:39.963537 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6022 10:52:39.966780 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6023 10:52:39.970381 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6024 10:52:39.973273 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6025 10:52:39.976442 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6026 10:52:39.983204 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
6027 10:52:39.986734 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6028 10:52:39.990189 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6029 10:52:39.993024 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6030 10:52:39.996655 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6031 10:52:39.999607 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6032 10:52:40.006519 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6033 10:52:40.009717 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6034 10:52:40.012893 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6035 10:52:40.016650 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6036 10:52:40.023385 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6037 10:52:40.023470 ==
6038 10:52:40.026233 Dram Type= 6, Freq= 0, CH_1, rank 1
6039 10:52:40.029838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6040 10:52:40.029923 ==
6041 10:52:40.029990 DQS Delay:
6042 10:52:40.032817 DQS0 = 0, DQS1 = 0
6043 10:52:40.032901 DQM Delay:
6044 10:52:40.036947 DQM0 = 102, DQM1 = 94
6045 10:52:40.037031 DQ Delay:
6046 10:52:40.039297 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
6047 10:52:40.042629 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
6048 10:52:40.045827 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =82
6049 10:52:40.049162 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =104
6050 10:52:40.049247
6051 10:52:40.049313
6052 10:52:40.058894 [DQSOSCAuto] RK1, (LSB)MR18= 0x903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6053 10:52:40.058981 CH1 RK1: MR19=505, MR18=903
6054 10:52:40.065773 CH1_RK1: MR19=0x505, MR18=0x903, DQSOSC=419, MR23=63, INC=61, DEC=41
6055 10:52:40.068832 [RxdqsGatingPostProcess] freq 933
6056 10:52:40.075636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6057 10:52:40.078886 best DQS0 dly(2T, 0.5T) = (0, 10)
6058 10:52:40.081967 best DQS1 dly(2T, 0.5T) = (0, 10)
6059 10:52:40.085353 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6060 10:52:40.088960 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6061 10:52:40.091746 best DQS0 dly(2T, 0.5T) = (0, 10)
6062 10:52:40.095489 best DQS1 dly(2T, 0.5T) = (0, 10)
6063 10:52:40.098224 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6064 10:52:40.101679 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6065 10:52:40.101764 Pre-setting of DQS Precalculation
6066 10:52:40.108291 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6067 10:52:40.115340 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6068 10:52:40.121604 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6069 10:52:40.121690
6070 10:52:40.121756
6071 10:52:40.124700 [Calibration Summary] 1866 Mbps
6072 10:52:40.128012 CH 0, Rank 0
6073 10:52:40.128096 SW Impedance : PASS
6074 10:52:40.132033 DUTY Scan : NO K
6075 10:52:40.134611 ZQ Calibration : PASS
6076 10:52:40.134696 Jitter Meter : NO K
6077 10:52:40.138173 CBT Training : PASS
6078 10:52:40.141863 Write leveling : PASS
6079 10:52:40.141947 RX DQS gating : PASS
6080 10:52:40.144860 RX DQ/DQS(RDDQC) : PASS
6081 10:52:40.148708 TX DQ/DQS : PASS
6082 10:52:40.148791 RX DATLAT : PASS
6083 10:52:40.151243 RX DQ/DQS(Engine): PASS
6084 10:52:40.154798 TX OE : NO K
6085 10:52:40.154881 All Pass.
6086 10:52:40.154962
6087 10:52:40.155024 CH 0, Rank 1
6088 10:52:40.157823 SW Impedance : PASS
6089 10:52:40.161434 DUTY Scan : NO K
6090 10:52:40.161546 ZQ Calibration : PASS
6091 10:52:40.164405 Jitter Meter : NO K
6092 10:52:40.164489 CBT Training : PASS
6093 10:52:40.167525 Write leveling : PASS
6094 10:52:40.170902 RX DQS gating : PASS
6095 10:52:40.170984 RX DQ/DQS(RDDQC) : PASS
6096 10:52:40.174427 TX DQ/DQS : PASS
6097 10:52:40.177391 RX DATLAT : PASS
6098 10:52:40.177474 RX DQ/DQS(Engine): PASS
6099 10:52:40.180872 TX OE : NO K
6100 10:52:40.180954 All Pass.
6101 10:52:40.181019
6102 10:52:40.184206 CH 1, Rank 0
6103 10:52:40.184288 SW Impedance : PASS
6104 10:52:40.188039 DUTY Scan : NO K
6105 10:52:40.190780 ZQ Calibration : PASS
6106 10:52:40.190864 Jitter Meter : NO K
6107 10:52:40.194357 CBT Training : PASS
6108 10:52:40.197497 Write leveling : PASS
6109 10:52:40.197579 RX DQS gating : PASS
6110 10:52:40.200934 RX DQ/DQS(RDDQC) : PASS
6111 10:52:40.204156 TX DQ/DQS : PASS
6112 10:52:40.204240 RX DATLAT : PASS
6113 10:52:40.207673 RX DQ/DQS(Engine): PASS
6114 10:52:40.210567 TX OE : NO K
6115 10:52:40.210650 All Pass.
6116 10:52:40.210715
6117 10:52:40.210775 CH 1, Rank 1
6118 10:52:40.213997 SW Impedance : PASS
6119 10:52:40.217417 DUTY Scan : NO K
6120 10:52:40.217500 ZQ Calibration : PASS
6121 10:52:40.220736 Jitter Meter : NO K
6122 10:52:40.223895 CBT Training : PASS
6123 10:52:40.223977 Write leveling : PASS
6124 10:52:40.227118 RX DQS gating : PASS
6125 10:52:40.227204 RX DQ/DQS(RDDQC) : PASS
6126 10:52:40.230432 TX DQ/DQS : PASS
6127 10:52:40.233948 RX DATLAT : PASS
6128 10:52:40.234030 RX DQ/DQS(Engine): PASS
6129 10:52:40.237475 TX OE : NO K
6130 10:52:40.237558 All Pass.
6131 10:52:40.237623
6132 10:52:40.240604 DramC Write-DBI off
6133 10:52:40.243701 PER_BANK_REFRESH: Hybrid Mode
6134 10:52:40.243783 TX_TRACKING: ON
6135 10:52:40.253559 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6136 10:52:40.256864 [FAST_K] Save calibration result to emmc
6137 10:52:40.260339 dramc_set_vcore_voltage set vcore to 650000
6138 10:52:40.264057 Read voltage for 400, 6
6139 10:52:40.264138 Vio18 = 0
6140 10:52:40.267489 Vcore = 650000
6141 10:52:40.267589 Vdram = 0
6142 10:52:40.267683 Vddq = 0
6143 10:52:40.267758 Vmddr = 0
6144 10:52:40.274108 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6145 10:52:40.280415 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6146 10:52:40.280549 MEM_TYPE=3, freq_sel=20
6147 10:52:40.283587 sv_algorithm_assistance_LP4_800
6148 10:52:40.286841 ============ PULL DRAM RESETB DOWN ============
6149 10:52:40.293656 ========== PULL DRAM RESETB DOWN end =========
6150 10:52:40.297679 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 10:52:40.299759 ===================================
6152 10:52:40.303263 LPDDR4 DRAM CONFIGURATION
6153 10:52:40.306491 ===================================
6154 10:52:40.306590 EX_ROW_EN[0] = 0x0
6155 10:52:40.309839 EX_ROW_EN[1] = 0x0
6156 10:52:40.309922 LP4Y_EN = 0x0
6157 10:52:40.313112 WORK_FSP = 0x0
6158 10:52:40.313195 WL = 0x2
6159 10:52:40.316685 RL = 0x2
6160 10:52:40.319780 BL = 0x2
6161 10:52:40.319863 RPST = 0x0
6162 10:52:40.323206 RD_PRE = 0x0
6163 10:52:40.323287 WR_PRE = 0x1
6164 10:52:40.326225 WR_PST = 0x0
6165 10:52:40.326307 DBI_WR = 0x0
6166 10:52:40.329924 DBI_RD = 0x0
6167 10:52:40.330007 OTF = 0x1
6168 10:52:40.333544 ===================================
6169 10:52:40.336409 ===================================
6170 10:52:40.339476 ANA top config
6171 10:52:40.342755 ===================================
6172 10:52:40.342837 DLL_ASYNC_EN = 0
6173 10:52:40.345912 ALL_SLAVE_EN = 1
6174 10:52:40.349221 NEW_RANK_MODE = 1
6175 10:52:40.352717 DLL_IDLE_MODE = 1
6176 10:52:40.355915 LP45_APHY_COMB_EN = 1
6177 10:52:40.355998 TX_ODT_DIS = 1
6178 10:52:40.359256 NEW_8X_MODE = 1
6179 10:52:40.362610 ===================================
6180 10:52:40.365832 ===================================
6181 10:52:40.369393 data_rate = 800
6182 10:52:40.372440 CKR = 1
6183 10:52:40.375990 DQ_P2S_RATIO = 4
6184 10:52:40.379037 ===================================
6185 10:52:40.379137 CA_P2S_RATIO = 4
6186 10:52:40.382541 DQ_CA_OPEN = 0
6187 10:52:40.385514 DQ_SEMI_OPEN = 1
6188 10:52:40.388956 CA_SEMI_OPEN = 1
6189 10:52:40.392723 CA_FULL_RATE = 0
6190 10:52:40.395525 DQ_CKDIV4_EN = 0
6191 10:52:40.395608 CA_CKDIV4_EN = 1
6192 10:52:40.399203 CA_PREDIV_EN = 0
6193 10:52:40.402459 PH8_DLY = 0
6194 10:52:40.405928 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6195 10:52:40.408834 DQ_AAMCK_DIV = 0
6196 10:52:40.412430 CA_AAMCK_DIV = 0
6197 10:52:40.412520 CA_ADMCK_DIV = 4
6198 10:52:40.415630 DQ_TRACK_CA_EN = 0
6199 10:52:40.418681 CA_PICK = 800
6200 10:52:40.422062 CA_MCKIO = 400
6201 10:52:40.426013 MCKIO_SEMI = 400
6202 10:52:40.428813 PLL_FREQ = 3016
6203 10:52:40.432320 DQ_UI_PI_RATIO = 32
6204 10:52:40.435448 CA_UI_PI_RATIO = 32
6205 10:52:40.438619 ===================================
6206 10:52:40.441905 ===================================
6207 10:52:40.441989 memory_type:LPDDR4
6208 10:52:40.445136 GP_NUM : 10
6209 10:52:40.448477 SRAM_EN : 1
6210 10:52:40.448567 MD32_EN : 0
6211 10:52:40.452319 ===================================
6212 10:52:40.455678 [ANA_INIT] >>>>>>>>>>>>>>
6213 10:52:40.458253 <<<<<< [CONFIGURE PHASE]: ANA_TX
6214 10:52:40.461586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6215 10:52:40.465029 ===================================
6216 10:52:40.468467 data_rate = 800,PCW = 0X7400
6217 10:52:40.471690 ===================================
6218 10:52:40.475175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6219 10:52:40.478188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6220 10:52:40.491431 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6221 10:52:40.494879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6222 10:52:40.498174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6223 10:52:40.502018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6224 10:52:40.504776 [ANA_INIT] flow start
6225 10:52:40.508161 [ANA_INIT] PLL >>>>>>>>
6226 10:52:40.508245 [ANA_INIT] PLL <<<<<<<<
6227 10:52:40.511522 [ANA_INIT] MIDPI >>>>>>>>
6228 10:52:40.514585 [ANA_INIT] MIDPI <<<<<<<<
6229 10:52:40.514669 [ANA_INIT] DLL >>>>>>>>
6230 10:52:40.518404 [ANA_INIT] flow end
6231 10:52:40.521239 ============ LP4 DIFF to SE enter ============
6232 10:52:40.524818 ============ LP4 DIFF to SE exit ============
6233 10:52:40.528021 [ANA_INIT] <<<<<<<<<<<<<
6234 10:52:40.530876 [Flow] Enable top DCM control >>>>>
6235 10:52:40.534265 [Flow] Enable top DCM control <<<<<
6236 10:52:40.537696 Enable DLL master slave shuffle
6237 10:52:40.543892 ==============================================================
6238 10:52:40.543977 Gating Mode config
6239 10:52:40.550714 ==============================================================
6240 10:52:40.554082 Config description:
6241 10:52:40.560748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6242 10:52:40.567739 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6243 10:52:40.574175 SELPH_MODE 0: By rank 1: By Phase
6244 10:52:40.581020 ==============================================================
6245 10:52:40.581356 GAT_TRACK_EN = 0
6246 10:52:40.583818 RX_GATING_MODE = 2
6247 10:52:40.588130 RX_GATING_TRACK_MODE = 2
6248 10:52:40.590789 SELPH_MODE = 1
6249 10:52:40.593674 PICG_EARLY_EN = 1
6250 10:52:40.597338 VALID_LAT_VALUE = 1
6251 10:52:40.603982 ==============================================================
6252 10:52:40.607293 Enter into Gating configuration >>>>
6253 10:52:40.610274 Exit from Gating configuration <<<<
6254 10:52:40.614126 Enter into DVFS_PRE_config >>>>>
6255 10:52:40.623922 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6256 10:52:40.626753 Exit from DVFS_PRE_config <<<<<
6257 10:52:40.630057 Enter into PICG configuration >>>>
6258 10:52:40.633568 Exit from PICG configuration <<<<
6259 10:52:40.637100 [RX_INPUT] configuration >>>>>
6260 10:52:40.637183 [RX_INPUT] configuration <<<<<
6261 10:52:40.643276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6262 10:52:40.649957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6263 10:52:40.657086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6264 10:52:40.660158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6265 10:52:40.666331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6266 10:52:40.673456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6267 10:52:40.676047 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6268 10:52:40.682692 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6269 10:52:40.686570 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6270 10:52:40.689805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6271 10:52:40.692592 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6272 10:52:40.699207 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6273 10:52:40.702395 ===================================
6274 10:52:40.705925 LPDDR4 DRAM CONFIGURATION
6275 10:52:40.706010 ===================================
6276 10:52:40.708987 EX_ROW_EN[0] = 0x0
6277 10:52:40.712715 EX_ROW_EN[1] = 0x0
6278 10:52:40.712800 LP4Y_EN = 0x0
6279 10:52:40.715788 WORK_FSP = 0x0
6280 10:52:40.715874 WL = 0x2
6281 10:52:40.719074 RL = 0x2
6282 10:52:40.719159 BL = 0x2
6283 10:52:40.722627 RPST = 0x0
6284 10:52:40.722712 RD_PRE = 0x0
6285 10:52:40.725439 WR_PRE = 0x1
6286 10:52:40.725525 WR_PST = 0x0
6287 10:52:40.729535 DBI_WR = 0x0
6288 10:52:40.729619 DBI_RD = 0x0
6289 10:52:40.732343 OTF = 0x1
6290 10:52:40.735657 ===================================
6291 10:52:40.738724 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6292 10:52:40.742013 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6293 10:52:40.748902 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6294 10:52:40.751962 ===================================
6295 10:52:40.755170 LPDDR4 DRAM CONFIGURATION
6296 10:52:40.758489 ===================================
6297 10:52:40.758573 EX_ROW_EN[0] = 0x10
6298 10:52:40.761994 EX_ROW_EN[1] = 0x0
6299 10:52:40.762078 LP4Y_EN = 0x0
6300 10:52:40.765552 WORK_FSP = 0x0
6301 10:52:40.765636 WL = 0x2
6302 10:52:40.768566 RL = 0x2
6303 10:52:40.768649 BL = 0x2
6304 10:52:40.772256 RPST = 0x0
6305 10:52:40.772339 RD_PRE = 0x0
6306 10:52:40.775469 WR_PRE = 0x1
6307 10:52:40.775553 WR_PST = 0x0
6308 10:52:40.778308 DBI_WR = 0x0
6309 10:52:40.778391 DBI_RD = 0x0
6310 10:52:40.782272 OTF = 0x1
6311 10:52:40.785060 ===================================
6312 10:52:40.791797 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6313 10:52:40.795582 nWR fixed to 30
6314 10:52:40.798100 [ModeRegInit_LP4] CH0 RK0
6315 10:52:40.798243 [ModeRegInit_LP4] CH0 RK1
6316 10:52:40.802202 [ModeRegInit_LP4] CH1 RK0
6317 10:52:40.804868 [ModeRegInit_LP4] CH1 RK1
6318 10:52:40.804952 match AC timing 19
6319 10:52:40.811587 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6320 10:52:40.814681 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6321 10:52:40.818461 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6322 10:52:40.824881 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6323 10:52:40.828308 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6324 10:52:40.828392 ==
6325 10:52:40.831421 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 10:52:40.835044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 10:52:40.835129 ==
6328 10:52:40.841304 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6329 10:52:40.847632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6330 10:52:40.850871 [CA 0] Center 36 (8~64) winsize 57
6331 10:52:40.854700 [CA 1] Center 36 (8~64) winsize 57
6332 10:52:40.857557 [CA 2] Center 36 (8~64) winsize 57
6333 10:52:40.860980 [CA 3] Center 36 (8~64) winsize 57
6334 10:52:40.864825 [CA 4] Center 36 (8~64) winsize 57
6335 10:52:40.867615 [CA 5] Center 36 (8~64) winsize 57
6336 10:52:40.867698
6337 10:52:40.871227 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6338 10:52:40.871311
6339 10:52:40.874414 [CATrainingPosCal] consider 1 rank data
6340 10:52:40.878029 u2DelayCellTimex100 = 270/100 ps
6341 10:52:40.880915 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 10:52:40.884438 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 10:52:40.887636 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 10:52:40.890767 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 10:52:40.894396 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 10:52:40.897389 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 10:52:40.897472
6348 10:52:40.901389 CA PerBit enable=1, Macro0, CA PI delay=36
6349 10:52:40.901472
6350 10:52:40.904669 [CBTSetCACLKResult] CA Dly = 36
6351 10:52:40.907637 CS Dly: 1 (0~32)
6352 10:52:40.907720 ==
6353 10:52:40.911027 Dram Type= 6, Freq= 0, CH_0, rank 1
6354 10:52:40.914303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 10:52:40.914400 ==
6356 10:52:40.920443 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6357 10:52:40.927001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6358 10:52:40.930431 [CA 0] Center 36 (8~64) winsize 57
6359 10:52:40.933738 [CA 1] Center 36 (8~64) winsize 57
6360 10:52:40.937133 [CA 2] Center 36 (8~64) winsize 57
6361 10:52:40.937214 [CA 3] Center 36 (8~64) winsize 57
6362 10:52:40.940256 [CA 4] Center 36 (8~64) winsize 57
6363 10:52:40.943513 [CA 5] Center 36 (8~64) winsize 57
6364 10:52:40.943593
6365 10:52:40.950123 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6366 10:52:40.950204
6367 10:52:40.953378 [CATrainingPosCal] consider 2 rank data
6368 10:52:40.957351 u2DelayCellTimex100 = 270/100 ps
6369 10:52:40.960402 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 10:52:40.963391 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 10:52:40.966452 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 10:52:40.970222 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 10:52:40.973803 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 10:52:40.976642 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 10:52:40.976728
6376 10:52:40.980306 CA PerBit enable=1, Macro0, CA PI delay=36
6377 10:52:40.980386
6378 10:52:40.983401 [CBTSetCACLKResult] CA Dly = 36
6379 10:52:40.986505 CS Dly: 1 (0~32)
6380 10:52:40.986585
6381 10:52:40.990382 ----->DramcWriteLeveling(PI) begin...
6382 10:52:40.990465 ==
6383 10:52:40.993236 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 10:52:40.996473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 10:52:40.996596 ==
6386 10:52:40.999690 Write leveling (Byte 0): 40 => 8
6387 10:52:41.002895 Write leveling (Byte 1): 32 => 0
6388 10:52:41.006593 DramcWriteLeveling(PI) end<-----
6389 10:52:41.006673
6390 10:52:41.006736 ==
6391 10:52:41.009817 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 10:52:41.012858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 10:52:41.012939 ==
6394 10:52:41.016343 [Gating] SW mode calibration
6395 10:52:41.022895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6396 10:52:41.029853 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6397 10:52:41.032750 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6398 10:52:41.036145 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6399 10:52:41.042828 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6400 10:52:41.045874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6401 10:52:41.049504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6402 10:52:41.055719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6403 10:52:41.059472 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6404 10:52:41.062396 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 10:52:41.069149 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6406 10:52:41.072470 Total UI for P1: 0, mck2ui 16
6407 10:52:41.075715 best dqsien dly found for B0: ( 0, 14, 24)
6408 10:52:41.079202 Total UI for P1: 0, mck2ui 16
6409 10:52:41.082809 best dqsien dly found for B1: ( 0, 14, 24)
6410 10:52:41.085875 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6411 10:52:41.088861 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6412 10:52:41.088942
6413 10:52:41.092584 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6414 10:52:41.095736 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6415 10:52:41.098559 [Gating] SW calibration Done
6416 10:52:41.098644 ==
6417 10:52:41.102090 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 10:52:41.105366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 10:52:41.105450 ==
6420 10:52:41.108836 RX Vref Scan: 0
6421 10:52:41.108919
6422 10:52:41.112168 RX Vref 0 -> 0, step: 1
6423 10:52:41.112252
6424 10:52:41.115240 RX Delay -410 -> 252, step: 16
6425 10:52:41.118483 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6426 10:52:41.121762 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6427 10:52:41.125289 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6428 10:52:41.131734 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6429 10:52:41.135167 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6430 10:52:41.139044 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6431 10:52:41.141627 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6432 10:52:41.148518 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6433 10:52:41.152105 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6434 10:52:41.154850 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6435 10:52:41.158872 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6436 10:52:41.165334 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6437 10:52:41.167947 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6438 10:52:41.171181 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6439 10:52:41.178411 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6440 10:52:41.181533 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6441 10:52:41.181620 ==
6442 10:52:41.184359 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 10:52:41.187617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 10:52:41.187701 ==
6445 10:52:41.191252 DQS Delay:
6446 10:52:41.191336 DQS0 = 43, DQS1 = 59
6447 10:52:41.191401 DQM Delay:
6448 10:52:41.194596 DQM0 = 9, DQM1 = 12
6449 10:52:41.194680 DQ Delay:
6450 10:52:41.198137 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6451 10:52:41.201002 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6452 10:52:41.204376 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6453 10:52:41.207599 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6454 10:52:41.207683
6455 10:52:41.207748
6456 10:52:41.207809 ==
6457 10:52:41.210766 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 10:52:41.214684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 10:52:41.217751 ==
6460 10:52:41.217835
6461 10:52:41.217900
6462 10:52:41.217959 TX Vref Scan disable
6463 10:52:41.220768 == TX Byte 0 ==
6464 10:52:41.223858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6465 10:52:41.227881 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6466 10:52:41.230777 == TX Byte 1 ==
6467 10:52:41.233785 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6468 10:52:41.237160 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6469 10:52:41.237244 ==
6470 10:52:41.240346 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 10:52:41.247314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 10:52:41.247397 ==
6473 10:52:41.247462
6474 10:52:41.247522
6475 10:52:41.247579 TX Vref Scan disable
6476 10:52:41.251129 == TX Byte 0 ==
6477 10:52:41.253726 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6478 10:52:41.257070 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6479 10:52:41.260653 == TX Byte 1 ==
6480 10:52:41.263386 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6481 10:52:41.267033 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6482 10:52:41.270416
6483 10:52:41.270497 [DATLAT]
6484 10:52:41.270561 Freq=400, CH0 RK0
6485 10:52:41.270619
6486 10:52:41.273282 DATLAT Default: 0xf
6487 10:52:41.273362 0, 0xFFFF, sum = 0
6488 10:52:41.276642 1, 0xFFFF, sum = 0
6489 10:52:41.276725 2, 0xFFFF, sum = 0
6490 10:52:41.280374 3, 0xFFFF, sum = 0
6491 10:52:41.280471 4, 0xFFFF, sum = 0
6492 10:52:41.283497 5, 0xFFFF, sum = 0
6493 10:52:41.286854 6, 0xFFFF, sum = 0
6494 10:52:41.286937 7, 0xFFFF, sum = 0
6495 10:52:41.290152 8, 0xFFFF, sum = 0
6496 10:52:41.290236 9, 0xFFFF, sum = 0
6497 10:52:41.293280 10, 0xFFFF, sum = 0
6498 10:52:41.293362 11, 0xFFFF, sum = 0
6499 10:52:41.296393 12, 0xFFFF, sum = 0
6500 10:52:41.296475 13, 0x0, sum = 1
6501 10:52:41.299732 14, 0x0, sum = 2
6502 10:52:41.299814 15, 0x0, sum = 3
6503 10:52:41.303046 16, 0x0, sum = 4
6504 10:52:41.303129 best_step = 14
6505 10:52:41.303193
6506 10:52:41.303251 ==
6507 10:52:41.306352 Dram Type= 6, Freq= 0, CH_0, rank 0
6508 10:52:41.309765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 10:52:41.313378 ==
6510 10:52:41.313460 RX Vref Scan: 1
6511 10:52:41.313524
6512 10:52:41.316769 RX Vref 0 -> 0, step: 1
6513 10:52:41.316850
6514 10:52:41.320045 RX Delay -359 -> 252, step: 8
6515 10:52:41.320126
6516 10:52:41.322824 Set Vref, RX VrefLevel [Byte0]: 55
6517 10:52:41.326130 [Byte1]: 49
6518 10:52:41.326211
6519 10:52:41.329758 Final RX Vref Byte 0 = 55 to rank0
6520 10:52:41.332976 Final RX Vref Byte 1 = 49 to rank0
6521 10:52:41.336388 Final RX Vref Byte 0 = 55 to rank1
6522 10:52:41.339577 Final RX Vref Byte 1 = 49 to rank1==
6523 10:52:41.342842 Dram Type= 6, Freq= 0, CH_0, rank 0
6524 10:52:41.345895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 10:52:41.345976 ==
6526 10:52:41.349197 DQS Delay:
6527 10:52:41.349280 DQS0 = 44, DQS1 = 60
6528 10:52:41.352388 DQM Delay:
6529 10:52:41.352470 DQM0 = 9, DQM1 = 12
6530 10:52:41.356400 DQ Delay:
6531 10:52:41.356483 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6532 10:52:41.359327 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6533 10:52:41.362534 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6534 10:52:41.365988 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6535 10:52:41.366070
6536 10:52:41.366143
6537 10:52:41.375751 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6538 10:52:41.379188 CH0 RK0: MR19=C0C, MR18=BE81
6539 10:52:41.382442 CH0_RK0: MR19=0xC0C, MR18=0xBE81, DQSOSC=386, MR23=63, INC=396, DEC=264
6540 10:52:41.385592 ==
6541 10:52:41.388826 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 10:52:41.392388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 10:52:41.392471 ==
6544 10:52:41.395658 [Gating] SW mode calibration
6545 10:52:41.402505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6546 10:52:41.405793 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6547 10:52:41.411853 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6548 10:52:41.415682 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6549 10:52:41.418482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6550 10:52:41.425430 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6551 10:52:41.428893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6552 10:52:41.431895 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6553 10:52:41.438759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6554 10:52:41.441903 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6555 10:52:41.445319 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6556 10:52:41.448252 Total UI for P1: 0, mck2ui 16
6557 10:52:41.451825 best dqsien dly found for B0: ( 0, 14, 24)
6558 10:52:41.454939 Total UI for P1: 0, mck2ui 16
6559 10:52:41.458165 best dqsien dly found for B1: ( 0, 14, 24)
6560 10:52:41.461427 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6561 10:52:41.467922 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6562 10:52:41.468004
6563 10:52:41.471648 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6564 10:52:41.474436 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6565 10:52:41.477714 [Gating] SW calibration Done
6566 10:52:41.477797 ==
6567 10:52:41.481598 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 10:52:41.484852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 10:52:41.484952 ==
6570 10:52:41.488370 RX Vref Scan: 0
6571 10:52:41.488452
6572 10:52:41.488573 RX Vref 0 -> 0, step: 1
6573 10:52:41.488648
6574 10:52:41.491414 RX Delay -410 -> 252, step: 16
6575 10:52:41.494675 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6576 10:52:41.500995 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6577 10:52:41.504328 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6578 10:52:41.508019 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6579 10:52:41.511025 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6580 10:52:41.517557 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6581 10:52:41.521328 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6582 10:52:41.524366 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6583 10:52:41.527237 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6584 10:52:41.534221 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6585 10:52:41.537660 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6586 10:52:41.540928 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6587 10:52:41.547229 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6588 10:52:41.550282 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6589 10:52:41.553602 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6590 10:52:41.557172 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6591 10:52:41.560407 ==
6592 10:52:41.563592 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 10:52:41.567231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 10:52:41.567315 ==
6595 10:52:41.567381 DQS Delay:
6596 10:52:41.569990 DQS0 = 43, DQS1 = 59
6597 10:52:41.570073 DQM Delay:
6598 10:52:41.573306 DQM0 = 9, DQM1 = 16
6599 10:52:41.573389 DQ Delay:
6600 10:52:41.577620 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6601 10:52:41.580066 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6602 10:52:41.583376 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6603 10:52:41.586954 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6604 10:52:41.587038
6605 10:52:41.587103
6606 10:52:41.587164 ==
6607 10:52:41.589859 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 10:52:41.594138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 10:52:41.594222 ==
6610 10:52:41.594288
6611 10:52:41.594347
6612 10:52:41.596365 TX Vref Scan disable
6613 10:52:41.596449 == TX Byte 0 ==
6614 10:52:41.602976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6615 10:52:41.606537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6616 10:52:41.606621 == TX Byte 1 ==
6617 10:52:41.613111 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6618 10:52:41.616227 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6619 10:52:41.616311 ==
6620 10:52:41.620090 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 10:52:41.623248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 10:52:41.623332 ==
6623 10:52:41.623398
6624 10:52:41.623458
6625 10:52:41.626203 TX Vref Scan disable
6626 10:52:41.626288 == TX Byte 0 ==
6627 10:52:41.633093 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6628 10:52:41.636024 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6629 10:52:41.636107 == TX Byte 1 ==
6630 10:52:41.642805 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6631 10:52:41.645909 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6632 10:52:41.645993
6633 10:52:41.646058 [DATLAT]
6634 10:52:41.649498 Freq=400, CH0 RK1
6635 10:52:41.649582
6636 10:52:41.649648 DATLAT Default: 0xe
6637 10:52:41.652555 0, 0xFFFF, sum = 0
6638 10:52:41.652641 1, 0xFFFF, sum = 0
6639 10:52:41.655843 2, 0xFFFF, sum = 0
6640 10:52:41.655927 3, 0xFFFF, sum = 0
6641 10:52:41.660181 4, 0xFFFF, sum = 0
6642 10:52:41.660267 5, 0xFFFF, sum = 0
6643 10:52:41.662499 6, 0xFFFF, sum = 0
6644 10:52:41.665726 7, 0xFFFF, sum = 0
6645 10:52:41.665811 8, 0xFFFF, sum = 0
6646 10:52:41.669217 9, 0xFFFF, sum = 0
6647 10:52:41.669302 10, 0xFFFF, sum = 0
6648 10:52:41.672495 11, 0xFFFF, sum = 0
6649 10:52:41.672620 12, 0xFFFF, sum = 0
6650 10:52:41.675781 13, 0x0, sum = 1
6651 10:52:41.675866 14, 0x0, sum = 2
6652 10:52:41.679211 15, 0x0, sum = 3
6653 10:52:41.679296 16, 0x0, sum = 4
6654 10:52:41.682168 best_step = 14
6655 10:52:41.682251
6656 10:52:41.682317 ==
6657 10:52:41.685418 Dram Type= 6, Freq= 0, CH_0, rank 1
6658 10:52:41.688773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 10:52:41.688857 ==
6660 10:52:41.688923 RX Vref Scan: 0
6661 10:52:41.692379
6662 10:52:41.692462 RX Vref 0 -> 0, step: 1
6663 10:52:41.692570
6664 10:52:41.695217 RX Delay -359 -> 252, step: 8
6665 10:52:41.702994 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6666 10:52:41.705968 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6667 10:52:41.709548 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6668 10:52:41.715925 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6669 10:52:41.719751 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6670 10:52:41.722795 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6671 10:52:41.726258 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6672 10:52:41.729215 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6673 10:52:41.735785 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6674 10:52:41.739066 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6675 10:52:41.742390 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6676 10:52:41.748932 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6677 10:52:41.752163 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6678 10:52:41.755401 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6679 10:52:41.758686 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6680 10:52:41.765724 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6681 10:52:41.765808 ==
6682 10:52:41.768799 Dram Type= 6, Freq= 0, CH_0, rank 1
6683 10:52:41.771757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 10:52:41.771841 ==
6685 10:52:41.771906 DQS Delay:
6686 10:52:41.775812 DQS0 = 44, DQS1 = 60
6687 10:52:41.775894 DQM Delay:
6688 10:52:41.778657 DQM0 = 9, DQM1 = 14
6689 10:52:41.778740 DQ Delay:
6690 10:52:41.781920 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6691 10:52:41.785619 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6692 10:52:41.788805 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6693 10:52:41.791683 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6694 10:52:41.791766
6695 10:52:41.791831
6696 10:52:41.801712 [DQSOSCAuto] RK1, (LSB)MR18= 0xb03c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6697 10:52:41.801796 CH0 RK1: MR19=C0C, MR18=B03C
6698 10:52:41.808148 CH0_RK1: MR19=0xC0C, MR18=0xB03C, DQSOSC=387, MR23=63, INC=394, DEC=262
6699 10:52:41.811853 [RxdqsGatingPostProcess] freq 400
6700 10:52:41.818057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6701 10:52:41.821999 best DQS0 dly(2T, 0.5T) = (0, 10)
6702 10:52:41.824725 best DQS1 dly(2T, 0.5T) = (0, 10)
6703 10:52:41.827964 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6704 10:52:41.831140 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6705 10:52:41.834508 best DQS0 dly(2T, 0.5T) = (0, 10)
6706 10:52:41.834591 best DQS1 dly(2T, 0.5T) = (0, 10)
6707 10:52:41.837598 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6708 10:52:41.841498 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6709 10:52:41.844135 Pre-setting of DQS Precalculation
6710 10:52:41.851043 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6711 10:52:41.851125 ==
6712 10:52:41.854386 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 10:52:41.857315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 10:52:41.857398 ==
6715 10:52:41.864369 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6716 10:52:41.870831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6717 10:52:41.874276 [CA 0] Center 36 (8~64) winsize 57
6718 10:52:41.878228 [CA 1] Center 36 (8~64) winsize 57
6719 10:52:41.880680 [CA 2] Center 36 (8~64) winsize 57
6720 10:52:41.884036 [CA 3] Center 36 (8~64) winsize 57
6721 10:52:41.884118 [CA 4] Center 36 (8~64) winsize 57
6722 10:52:41.887109 [CA 5] Center 36 (8~64) winsize 57
6723 10:52:41.887190
6724 10:52:41.893892 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6725 10:52:41.893973
6726 10:52:41.897291 [CATrainingPosCal] consider 1 rank data
6727 10:52:41.900406 u2DelayCellTimex100 = 270/100 ps
6728 10:52:41.903974 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 10:52:41.907011 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 10:52:41.910437 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 10:52:41.913655 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 10:52:41.916961 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 10:52:41.920052 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 10:52:41.920134
6735 10:52:41.923723 CA PerBit enable=1, Macro0, CA PI delay=36
6736 10:52:41.923804
6737 10:52:41.927059 [CBTSetCACLKResult] CA Dly = 36
6738 10:52:41.930163 CS Dly: 1 (0~32)
6739 10:52:41.930244 ==
6740 10:52:41.933194 Dram Type= 6, Freq= 0, CH_1, rank 1
6741 10:52:41.936989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 10:52:41.937071 ==
6743 10:52:41.943186 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6744 10:52:41.949606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6745 10:52:41.953479 [CA 0] Center 36 (8~64) winsize 57
6746 10:52:41.956473 [CA 1] Center 36 (8~64) winsize 57
6747 10:52:41.956592 [CA 2] Center 36 (8~64) winsize 57
6748 10:52:41.959457 [CA 3] Center 36 (8~64) winsize 57
6749 10:52:41.963372 [CA 4] Center 36 (8~64) winsize 57
6750 10:52:41.966613 [CA 5] Center 36 (8~64) winsize 57
6751 10:52:41.966696
6752 10:52:41.969600 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6753 10:52:41.973091
6754 10:52:41.976126 [CATrainingPosCal] consider 2 rank data
6755 10:52:41.976209 u2DelayCellTimex100 = 270/100 ps
6756 10:52:41.982823 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6757 10:52:41.985971 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6758 10:52:41.989167 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6759 10:52:41.993075 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6760 10:52:41.996011 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6761 10:52:41.999618 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6762 10:52:41.999702
6763 10:52:42.002664 CA PerBit enable=1, Macro0, CA PI delay=36
6764 10:52:42.002746
6765 10:52:42.006108 [CBTSetCACLKResult] CA Dly = 36
6766 10:52:42.009188 CS Dly: 1 (0~32)
6767 10:52:42.009269
6768 10:52:42.012139 ----->DramcWriteLeveling(PI) begin...
6769 10:52:42.012222 ==
6770 10:52:42.015614 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 10:52:42.018864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 10:52:42.018947 ==
6773 10:52:42.022051 Write leveling (Byte 0): 40 => 8
6774 10:52:42.025365 Write leveling (Byte 1): 32 => 0
6775 10:52:42.028842 DramcWriteLeveling(PI) end<-----
6776 10:52:42.028924
6777 10:52:42.028988 ==
6778 10:52:42.032176 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 10:52:42.035482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 10:52:42.035565 ==
6781 10:52:42.038962 [Gating] SW mode calibration
6782 10:52:42.045340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6783 10:52:42.052120 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6784 10:52:42.055176 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6785 10:52:42.061838 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6786 10:52:42.064963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6787 10:52:42.068500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6788 10:52:42.074793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6789 10:52:42.078723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6790 10:52:42.081488 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6791 10:52:42.088478 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 10:52:42.091410 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6793 10:52:42.094617 Total UI for P1: 0, mck2ui 16
6794 10:52:42.098307 best dqsien dly found for B0: ( 0, 14, 24)
6795 10:52:42.101346 Total UI for P1: 0, mck2ui 16
6796 10:52:42.104791 best dqsien dly found for B1: ( 0, 14, 24)
6797 10:52:42.108075 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6798 10:52:42.111681 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6799 10:52:42.111764
6800 10:52:42.115015 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6801 10:52:42.117739 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6802 10:52:42.120965 [Gating] SW calibration Done
6803 10:52:42.121048 ==
6804 10:52:42.124463 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 10:52:42.127847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 10:52:42.130902 ==
6807 10:52:42.130984 RX Vref Scan: 0
6808 10:52:42.131049
6809 10:52:42.134579 RX Vref 0 -> 0, step: 1
6810 10:52:42.134661
6811 10:52:42.137827 RX Delay -410 -> 252, step: 16
6812 10:52:42.141075 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6813 10:52:42.144087 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6814 10:52:42.147834 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6815 10:52:42.154244 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6816 10:52:42.157699 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6817 10:52:42.160814 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6818 10:52:42.163877 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6819 10:52:42.170567 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6820 10:52:42.173869 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6821 10:52:42.177393 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6822 10:52:42.183376 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6823 10:52:42.186927 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6824 10:52:42.189960 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6825 10:52:42.193369 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6826 10:52:42.200504 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6827 10:52:42.203643 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6828 10:52:42.203727 ==
6829 10:52:42.206809 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 10:52:42.210377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 10:52:42.210461 ==
6832 10:52:42.213055 DQS Delay:
6833 10:52:42.213138 DQS0 = 43, DQS1 = 51
6834 10:52:42.216331 DQM Delay:
6835 10:52:42.216413 DQM0 = 12, DQM1 = 14
6836 10:52:42.216479 DQ Delay:
6837 10:52:42.219759 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6838 10:52:42.222885 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6839 10:52:42.226407 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6840 10:52:42.229302 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6841 10:52:42.229386
6842 10:52:42.229451
6843 10:52:42.229510 ==
6844 10:52:42.232661 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 10:52:42.239469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 10:52:42.239553 ==
6847 10:52:42.239620
6848 10:52:42.239679
6849 10:52:42.239737 TX Vref Scan disable
6850 10:52:42.242858 == TX Byte 0 ==
6851 10:52:42.245865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6852 10:52:42.249586 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6853 10:52:42.253196 == TX Byte 1 ==
6854 10:52:42.256118 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6855 10:52:42.262627 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6856 10:52:42.262712 ==
6857 10:52:42.266028 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 10:52:42.268971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 10:52:42.269055 ==
6860 10:52:42.269121
6861 10:52:42.269182
6862 10:52:42.272328 TX Vref Scan disable
6863 10:52:42.272411 == TX Byte 0 ==
6864 10:52:42.275585 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6865 10:52:42.281902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6866 10:52:42.281987 == TX Byte 1 ==
6867 10:52:42.286492 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6868 10:52:42.292023 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6869 10:52:42.292107
6870 10:52:42.292172 [DATLAT]
6871 10:52:42.292232 Freq=400, CH1 RK0
6872 10:52:42.295469
6873 10:52:42.295552 DATLAT Default: 0xf
6874 10:52:42.299107 0, 0xFFFF, sum = 0
6875 10:52:42.299193 1, 0xFFFF, sum = 0
6876 10:52:42.301743 2, 0xFFFF, sum = 0
6877 10:52:42.301829 3, 0xFFFF, sum = 0
6878 10:52:42.305416 4, 0xFFFF, sum = 0
6879 10:52:42.305501 5, 0xFFFF, sum = 0
6880 10:52:42.309040 6, 0xFFFF, sum = 0
6881 10:52:42.309125 7, 0xFFFF, sum = 0
6882 10:52:42.311710 8, 0xFFFF, sum = 0
6883 10:52:42.311794 9, 0xFFFF, sum = 0
6884 10:52:42.315792 10, 0xFFFF, sum = 0
6885 10:52:42.315877 11, 0xFFFF, sum = 0
6886 10:52:42.318506 12, 0xFFFF, sum = 0
6887 10:52:42.318591 13, 0x0, sum = 1
6888 10:52:42.321358 14, 0x0, sum = 2
6889 10:52:42.321443 15, 0x0, sum = 3
6890 10:52:42.324744 16, 0x0, sum = 4
6891 10:52:42.324828 best_step = 14
6892 10:52:42.324894
6893 10:52:42.324955 ==
6894 10:52:42.328077 Dram Type= 6, Freq= 0, CH_1, rank 0
6895 10:52:42.334840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 10:52:42.334924 ==
6897 10:52:42.334989 RX Vref Scan: 1
6898 10:52:42.335051
6899 10:52:42.338441 RX Vref 0 -> 0, step: 1
6900 10:52:42.338524
6901 10:52:42.341255 RX Delay -343 -> 252, step: 8
6902 10:52:42.341338
6903 10:52:42.344895 Set Vref, RX VrefLevel [Byte0]: 47
6904 10:52:42.348193 [Byte1]: 54
6905 10:52:42.351248
6906 10:52:42.351335 Final RX Vref Byte 0 = 47 to rank0
6907 10:52:42.354667 Final RX Vref Byte 1 = 54 to rank0
6908 10:52:42.357801 Final RX Vref Byte 0 = 47 to rank1
6909 10:52:42.361578 Final RX Vref Byte 1 = 54 to rank1==
6910 10:52:42.364781 Dram Type= 6, Freq= 0, CH_1, rank 0
6911 10:52:42.371209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 10:52:42.371293 ==
6913 10:52:42.371359 DQS Delay:
6914 10:52:42.374304 DQS0 = 44, DQS1 = 52
6915 10:52:42.374388 DQM Delay:
6916 10:52:42.374454 DQM0 = 8, DQM1 = 9
6917 10:52:42.377582 DQ Delay:
6918 10:52:42.381180 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6919 10:52:42.381264 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6920 10:52:42.384449 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6921 10:52:42.387355 DQ12 =20, DQ13 =12, DQ14 =12, DQ15 =20
6922 10:52:42.387438
6923 10:52:42.390708
6924 10:52:42.398099 [DQSOSCAuto] RK0, (LSB)MR18= 0x936a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6925 10:52:42.400722 CH1 RK0: MR19=C0C, MR18=936A
6926 10:52:42.407512 CH1_RK0: MR19=0xC0C, MR18=0x936A, DQSOSC=391, MR23=63, INC=386, DEC=257
6927 10:52:42.407596 ==
6928 10:52:42.411135 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 10:52:42.413888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 10:52:42.413978 ==
6931 10:52:42.417148 [Gating] SW mode calibration
6932 10:52:42.424049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6933 10:52:42.430578 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6934 10:52:42.433627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6935 10:52:42.437102 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6936 10:52:42.443890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6937 10:52:42.446737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6938 10:52:42.450292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6939 10:52:42.457032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6940 10:52:42.460164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6941 10:52:42.464085 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6942 10:52:42.470592 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6943 10:52:42.470675 Total UI for P1: 0, mck2ui 16
6944 10:52:42.476684 best dqsien dly found for B0: ( 0, 14, 24)
6945 10:52:42.476766 Total UI for P1: 0, mck2ui 16
6946 10:52:42.483119 best dqsien dly found for B1: ( 0, 14, 24)
6947 10:52:42.486552 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6948 10:52:42.490518 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6949 10:52:42.490600
6950 10:52:42.493121 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6951 10:52:42.496275 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6952 10:52:42.500434 [Gating] SW calibration Done
6953 10:52:42.500575 ==
6954 10:52:42.502963 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 10:52:42.506390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 10:52:42.506473 ==
6957 10:52:42.509415 RX Vref Scan: 0
6958 10:52:42.509498
6959 10:52:42.509562 RX Vref 0 -> 0, step: 1
6960 10:52:42.512813
6961 10:52:42.512896 RX Delay -410 -> 252, step: 16
6962 10:52:42.519623 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6963 10:52:42.523161 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6964 10:52:42.526035 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6965 10:52:42.529501 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6966 10:52:42.536234 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6967 10:52:42.539270 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6968 10:52:42.542713 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6969 10:52:42.545957 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6970 10:52:42.552439 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6971 10:52:42.555585 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6972 10:52:42.559039 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6973 10:52:42.565482 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6974 10:52:42.569383 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6975 10:52:42.572480 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6976 10:52:42.575501 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6977 10:52:42.582000 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6978 10:52:42.582147 ==
6979 10:52:42.585449 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 10:52:42.588735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 10:52:42.588860 ==
6982 10:52:42.588935 DQS Delay:
6983 10:52:42.591799 DQS0 = 51, DQS1 = 59
6984 10:52:42.591882 DQM Delay:
6985 10:52:42.594971 DQM0 = 19, DQM1 = 22
6986 10:52:42.595055 DQ Delay:
6987 10:52:42.599345 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6988 10:52:42.601950 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6989 10:52:42.605117 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6990 10:52:42.608426 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6991 10:52:42.608571
6992 10:52:42.608652
6993 10:52:42.608711 ==
6994 10:52:42.611646 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 10:52:42.615348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 10:52:42.618115 ==
6997 10:52:42.618213
6998 10:52:42.618313
6999 10:52:42.618387 TX Vref Scan disable
7000 10:52:42.621785 == TX Byte 0 ==
7001 10:52:42.625221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7002 10:52:42.628506 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7003 10:52:42.631780 == TX Byte 1 ==
7004 10:52:42.634548 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
7005 10:52:42.638380 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
7006 10:52:42.638464 ==
7007 10:52:42.641584 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 10:52:42.648045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 10:52:42.648133 ==
7010 10:52:42.648199
7011 10:52:42.648260
7012 10:52:42.648319 TX Vref Scan disable
7013 10:52:42.651287 == TX Byte 0 ==
7014 10:52:42.654800 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7015 10:52:42.658100 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7016 10:52:42.661265 == TX Byte 1 ==
7017 10:52:42.664300 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
7018 10:52:42.668028 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
7019 10:52:42.668112
7020 10:52:42.671404 [DATLAT]
7021 10:52:42.671487 Freq=400, CH1 RK1
7022 10:52:42.671555
7023 10:52:42.674403 DATLAT Default: 0xe
7024 10:52:42.674489 0, 0xFFFF, sum = 0
7025 10:52:42.677981 1, 0xFFFF, sum = 0
7026 10:52:42.678105 2, 0xFFFF, sum = 0
7027 10:52:42.681470 3, 0xFFFF, sum = 0
7028 10:52:42.681556 4, 0xFFFF, sum = 0
7029 10:52:42.684403 5, 0xFFFF, sum = 0
7030 10:52:42.684539 6, 0xFFFF, sum = 0
7031 10:52:42.687581 7, 0xFFFF, sum = 0
7032 10:52:42.687666 8, 0xFFFF, sum = 0
7033 10:52:42.691246 9, 0xFFFF, sum = 0
7034 10:52:42.691333 10, 0xFFFF, sum = 0
7035 10:52:42.694053 11, 0xFFFF, sum = 0
7036 10:52:42.697553 12, 0xFFFF, sum = 0
7037 10:52:42.697639 13, 0x0, sum = 1
7038 10:52:42.700848 14, 0x0, sum = 2
7039 10:52:42.700935 15, 0x0, sum = 3
7040 10:52:42.701003 16, 0x0, sum = 4
7041 10:52:42.704400 best_step = 14
7042 10:52:42.704484
7043 10:52:42.704596 ==
7044 10:52:42.707432 Dram Type= 6, Freq= 0, CH_1, rank 1
7045 10:52:42.710779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7046 10:52:42.710866 ==
7047 10:52:42.714109 RX Vref Scan: 0
7048 10:52:42.714225
7049 10:52:42.717493 RX Vref 0 -> 0, step: 1
7050 10:52:42.717577
7051 10:52:42.717644 RX Delay -359 -> 252, step: 8
7052 10:52:42.725808 iDelay=217, Bit 0, Center -28 (-263 ~ 208) 472
7053 10:52:42.728996 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
7054 10:52:42.732871 iDelay=217, Bit 2, Center -44 (-279 ~ 192) 472
7055 10:52:42.735904 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
7056 10:52:42.742281 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7057 10:52:42.745593 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
7058 10:52:42.749033 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
7059 10:52:42.755754 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
7060 10:52:42.759294 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7061 10:52:42.762352 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7062 10:52:42.765614 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
7063 10:52:42.772170 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7064 10:52:42.775263 iDelay=217, Bit 12, Center -32 (-279 ~ 216) 496
7065 10:52:42.779149 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7066 10:52:42.782033 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7067 10:52:42.789068 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
7068 10:52:42.789189 ==
7069 10:52:42.791853 Dram Type= 6, Freq= 0, CH_1, rank 1
7070 10:52:42.795367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7071 10:52:42.795468 ==
7072 10:52:42.795536 DQS Delay:
7073 10:52:42.799304 DQS0 = 44, DQS1 = 56
7074 10:52:42.799392 DQM Delay:
7075 10:52:42.801696 DQM0 = 10, DQM1 = 12
7076 10:52:42.801781 DQ Delay:
7077 10:52:42.804981 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7078 10:52:42.808484 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7079 10:52:42.811946 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7080 10:52:42.815067 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
7081 10:52:42.815155
7082 10:52:42.815222
7083 10:52:42.824699 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7084 10:52:42.824798 CH1 RK1: MR19=C0C, MR18=6C5C
7085 10:52:42.832105 CH1_RK1: MR19=0xC0C, MR18=0x6C5C, DQSOSC=396, MR23=63, INC=376, DEC=251
7086 10:52:42.835036 [RxdqsGatingPostProcess] freq 400
7087 10:52:42.841489 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7088 10:52:42.844480 best DQS0 dly(2T, 0.5T) = (0, 10)
7089 10:52:42.847998 best DQS1 dly(2T, 0.5T) = (0, 10)
7090 10:52:42.851255 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7091 10:52:42.854892 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7092 10:52:42.854981 best DQS0 dly(2T, 0.5T) = (0, 10)
7093 10:52:42.857888 best DQS1 dly(2T, 0.5T) = (0, 10)
7094 10:52:42.861153 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7095 10:52:42.864511 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7096 10:52:42.867902 Pre-setting of DQS Precalculation
7097 10:52:42.874235 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7098 10:52:42.881242 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7099 10:52:42.887636 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7100 10:52:42.887741
7101 10:52:42.887807
7102 10:52:42.891240 [Calibration Summary] 800 Mbps
7103 10:52:42.891325 CH 0, Rank 0
7104 10:52:42.894036 SW Impedance : PASS
7105 10:52:42.897799 DUTY Scan : NO K
7106 10:52:42.897886 ZQ Calibration : PASS
7107 10:52:42.901032 Jitter Meter : NO K
7108 10:52:42.904135 CBT Training : PASS
7109 10:52:42.904220 Write leveling : PASS
7110 10:52:42.907303 RX DQS gating : PASS
7111 10:52:42.910594 RX DQ/DQS(RDDQC) : PASS
7112 10:52:42.910681 TX DQ/DQS : PASS
7113 10:52:42.913964 RX DATLAT : PASS
7114 10:52:42.917038 RX DQ/DQS(Engine): PASS
7115 10:52:42.917121 TX OE : NO K
7116 10:52:42.920905 All Pass.
7117 10:52:42.920990
7118 10:52:42.921054 CH 0, Rank 1
7119 10:52:42.923704 SW Impedance : PASS
7120 10:52:42.923817 DUTY Scan : NO K
7121 10:52:42.927028 ZQ Calibration : PASS
7122 10:52:42.930977 Jitter Meter : NO K
7123 10:52:42.931062 CBT Training : PASS
7124 10:52:42.934113 Write leveling : NO K
7125 10:52:42.937298 RX DQS gating : PASS
7126 10:52:42.937384 RX DQ/DQS(RDDQC) : PASS
7127 10:52:42.940030 TX DQ/DQS : PASS
7128 10:52:42.943884 RX DATLAT : PASS
7129 10:52:42.943968 RX DQ/DQS(Engine): PASS
7130 10:52:42.946836 TX OE : NO K
7131 10:52:42.946921 All Pass.
7132 10:52:42.946988
7133 10:52:42.950387 CH 1, Rank 0
7134 10:52:42.950472 SW Impedance : PASS
7135 10:52:42.953745 DUTY Scan : NO K
7136 10:52:42.957211 ZQ Calibration : PASS
7137 10:52:42.957297 Jitter Meter : NO K
7138 10:52:42.960234 CBT Training : PASS
7139 10:52:42.963701 Write leveling : PASS
7140 10:52:42.963788 RX DQS gating : PASS
7141 10:52:42.966540 RX DQ/DQS(RDDQC) : PASS
7142 10:52:42.966625 TX DQ/DQS : PASS
7143 10:52:42.970088 RX DATLAT : PASS
7144 10:52:42.973273 RX DQ/DQS(Engine): PASS
7145 10:52:42.973359 TX OE : NO K
7146 10:52:42.976461 All Pass.
7147 10:52:42.976608
7148 10:52:42.976675 CH 1, Rank 1
7149 10:52:42.979719 SW Impedance : PASS
7150 10:52:42.979834 DUTY Scan : NO K
7151 10:52:42.982964 ZQ Calibration : PASS
7152 10:52:42.986670 Jitter Meter : NO K
7153 10:52:42.986760 CBT Training : PASS
7154 10:52:42.989757 Write leveling : NO K
7155 10:52:42.992865 RX DQS gating : PASS
7156 10:52:42.992951 RX DQ/DQS(RDDQC) : PASS
7157 10:52:42.996706 TX DQ/DQS : PASS
7158 10:52:42.999813 RX DATLAT : PASS
7159 10:52:42.999899 RX DQ/DQS(Engine): PASS
7160 10:52:43.003019 TX OE : NO K
7161 10:52:43.003114 All Pass.
7162 10:52:43.003181
7163 10:52:43.006447 DramC Write-DBI off
7164 10:52:43.009648 PER_BANK_REFRESH: Hybrid Mode
7165 10:52:43.009737 TX_TRACKING: ON
7166 10:52:43.019292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7167 10:52:43.022893 [FAST_K] Save calibration result to emmc
7168 10:52:43.026316 dramc_set_vcore_voltage set vcore to 725000
7169 10:52:43.029848 Read voltage for 1600, 0
7170 10:52:43.029937 Vio18 = 0
7171 10:52:43.030004 Vcore = 725000
7172 10:52:43.032908 Vdram = 0
7173 10:52:43.032993 Vddq = 0
7174 10:52:43.033059 Vmddr = 0
7175 10:52:43.039395 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7176 10:52:43.042696 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7177 10:52:43.045899 MEM_TYPE=3, freq_sel=13
7178 10:52:43.049368 sv_algorithm_assistance_LP4_3733
7179 10:52:43.052482 ============ PULL DRAM RESETB DOWN ============
7180 10:52:43.059176 ========== PULL DRAM RESETB DOWN end =========
7181 10:52:43.062348 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 10:52:43.065681 ===================================
7183 10:52:43.068999 LPDDR4 DRAM CONFIGURATION
7184 10:52:43.072745 ===================================
7185 10:52:43.072842 EX_ROW_EN[0] = 0x0
7186 10:52:43.075522 EX_ROW_EN[1] = 0x0
7187 10:52:43.075608 LP4Y_EN = 0x0
7188 10:52:43.079324 WORK_FSP = 0x1
7189 10:52:43.079425 WL = 0x5
7190 10:52:43.082161 RL = 0x5
7191 10:52:43.082248 BL = 0x2
7192 10:52:43.085311 RPST = 0x0
7193 10:52:43.085399 RD_PRE = 0x0
7194 10:52:43.088867 WR_PRE = 0x1
7195 10:52:43.091842 WR_PST = 0x1
7196 10:52:43.091930 DBI_WR = 0x0
7197 10:52:43.095843 DBI_RD = 0x0
7198 10:52:43.095930 OTF = 0x1
7199 10:52:43.098937 ===================================
7200 10:52:43.101860 ===================================
7201 10:52:43.105186 ANA top config
7202 10:52:43.108628 ===================================
7203 10:52:43.108717 DLL_ASYNC_EN = 0
7204 10:52:43.112303 ALL_SLAVE_EN = 0
7205 10:52:43.115060 NEW_RANK_MODE = 1
7206 10:52:43.118599 DLL_IDLE_MODE = 1
7207 10:52:43.118687 LP45_APHY_COMB_EN = 1
7208 10:52:43.122093 TX_ODT_DIS = 0
7209 10:52:43.125727 NEW_8X_MODE = 1
7210 10:52:43.128480 ===================================
7211 10:52:43.131435 ===================================
7212 10:52:43.135044 data_rate = 3200
7213 10:52:43.138314 CKR = 1
7214 10:52:43.141884 DQ_P2S_RATIO = 8
7215 10:52:43.145329 ===================================
7216 10:52:43.145418 CA_P2S_RATIO = 8
7217 10:52:43.148482 DQ_CA_OPEN = 0
7218 10:52:43.151605 DQ_SEMI_OPEN = 0
7219 10:52:43.154945 CA_SEMI_OPEN = 0
7220 10:52:43.158378 CA_FULL_RATE = 0
7221 10:52:43.161446 DQ_CKDIV4_EN = 0
7222 10:52:43.161533 CA_CKDIV4_EN = 0
7223 10:52:43.164459 CA_PREDIV_EN = 0
7224 10:52:43.168040 PH8_DLY = 12
7225 10:52:43.171131 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7226 10:52:43.174647 DQ_AAMCK_DIV = 4
7227 10:52:43.177689 CA_AAMCK_DIV = 4
7228 10:52:43.177780 CA_ADMCK_DIV = 4
7229 10:52:43.180920 DQ_TRACK_CA_EN = 0
7230 10:52:43.184409 CA_PICK = 1600
7231 10:52:43.187883 CA_MCKIO = 1600
7232 10:52:43.191231 MCKIO_SEMI = 0
7233 10:52:43.194216 PLL_FREQ = 3068
7234 10:52:43.197508 DQ_UI_PI_RATIO = 32
7235 10:52:43.200937 CA_UI_PI_RATIO = 0
7236 10:52:43.204330 ===================================
7237 10:52:43.207655 ===================================
7238 10:52:43.207746 memory_type:LPDDR4
7239 10:52:43.210879 GP_NUM : 10
7240 10:52:43.210969 SRAM_EN : 1
7241 10:52:43.214002 MD32_EN : 0
7242 10:52:43.218336 ===================================
7243 10:52:43.220705 [ANA_INIT] >>>>>>>>>>>>>>
7244 10:52:43.224147 <<<<<< [CONFIGURE PHASE]: ANA_TX
7245 10:52:43.227796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7246 10:52:43.230997 ===================================
7247 10:52:43.234163 data_rate = 3200,PCW = 0X7600
7248 10:52:43.234259 ===================================
7249 10:52:43.240962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7250 10:52:43.244182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7251 10:52:43.250966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7252 10:52:43.253958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7253 10:52:43.257298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7254 10:52:43.260703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7255 10:52:43.263700 [ANA_INIT] flow start
7256 10:52:43.266930 [ANA_INIT] PLL >>>>>>>>
7257 10:52:43.267019 [ANA_INIT] PLL <<<<<<<<
7258 10:52:43.271087 [ANA_INIT] MIDPI >>>>>>>>
7259 10:52:43.273740 [ANA_INIT] MIDPI <<<<<<<<
7260 10:52:43.276949 [ANA_INIT] DLL >>>>>>>>
7261 10:52:43.277039 [ANA_INIT] DLL <<<<<<<<
7262 10:52:43.280061 [ANA_INIT] flow end
7263 10:52:43.283752 ============ LP4 DIFF to SE enter ============
7264 10:52:43.286927 ============ LP4 DIFF to SE exit ============
7265 10:52:43.290245 [ANA_INIT] <<<<<<<<<<<<<
7266 10:52:43.293355 [Flow] Enable top DCM control >>>>>
7267 10:52:43.296630 [Flow] Enable top DCM control <<<<<
7268 10:52:43.299958 Enable DLL master slave shuffle
7269 10:52:43.306710 ==============================================================
7270 10:52:43.306815 Gating Mode config
7271 10:52:43.313781 ==============================================================
7272 10:52:43.313895 Config description:
7273 10:52:43.323182 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7274 10:52:43.329469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7275 10:52:43.336449 SELPH_MODE 0: By rank 1: By Phase
7276 10:52:43.339445 ==============================================================
7277 10:52:43.343116 GAT_TRACK_EN = 1
7278 10:52:43.346137 RX_GATING_MODE = 2
7279 10:52:43.349130 RX_GATING_TRACK_MODE = 2
7280 10:52:43.352953 SELPH_MODE = 1
7281 10:52:43.355981 PICG_EARLY_EN = 1
7282 10:52:43.359653 VALID_LAT_VALUE = 1
7283 10:52:43.365980 ==============================================================
7284 10:52:43.369120 Enter into Gating configuration >>>>
7285 10:52:43.372707 Exit from Gating configuration <<<<
7286 10:52:43.375884 Enter into DVFS_PRE_config >>>>>
7287 10:52:43.385526 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7288 10:52:43.388788 Exit from DVFS_PRE_config <<<<<
7289 10:52:43.392128 Enter into PICG configuration >>>>
7290 10:52:43.395415 Exit from PICG configuration <<<<
7291 10:52:43.398529 [RX_INPUT] configuration >>>>>
7292 10:52:43.398622 [RX_INPUT] configuration <<<<<
7293 10:52:43.405077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7294 10:52:43.412174 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7295 10:52:43.418755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7296 10:52:43.422402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7297 10:52:43.428251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7298 10:52:43.435122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7299 10:52:43.438124 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7300 10:52:43.445392 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7301 10:52:43.448178 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7302 10:52:43.451982 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7303 10:52:43.454799 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7304 10:52:43.461684 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7305 10:52:43.465636 ===================================
7306 10:52:43.465730 LPDDR4 DRAM CONFIGURATION
7307 10:52:43.468415 ===================================
7308 10:52:43.471666 EX_ROW_EN[0] = 0x0
7309 10:52:43.474675 EX_ROW_EN[1] = 0x0
7310 10:52:43.474764 LP4Y_EN = 0x0
7311 10:52:43.478035 WORK_FSP = 0x1
7312 10:52:43.478148 WL = 0x5
7313 10:52:43.481095 RL = 0x5
7314 10:52:43.481192 BL = 0x2
7315 10:52:43.484502 RPST = 0x0
7316 10:52:43.484621 RD_PRE = 0x0
7317 10:52:43.487997 WR_PRE = 0x1
7318 10:52:43.488092 WR_PST = 0x1
7319 10:52:43.491358 DBI_WR = 0x0
7320 10:52:43.491444 DBI_RD = 0x0
7321 10:52:43.494516 OTF = 0x1
7322 10:52:43.497478 ===================================
7323 10:52:43.501655 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7324 10:52:43.504359 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7325 10:52:43.510634 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7326 10:52:43.514071 ===================================
7327 10:52:43.514168 LPDDR4 DRAM CONFIGURATION
7328 10:52:43.517173 ===================================
7329 10:52:43.520733 EX_ROW_EN[0] = 0x10
7330 10:52:43.524161 EX_ROW_EN[1] = 0x0
7331 10:52:43.524255 LP4Y_EN = 0x0
7332 10:52:43.527504 WORK_FSP = 0x1
7333 10:52:43.527592 WL = 0x5
7334 10:52:43.530354 RL = 0x5
7335 10:52:43.530440 BL = 0x2
7336 10:52:43.534297 RPST = 0x0
7337 10:52:43.534386 RD_PRE = 0x0
7338 10:52:43.537306 WR_PRE = 0x1
7339 10:52:43.537393 WR_PST = 0x1
7340 10:52:43.540342 DBI_WR = 0x0
7341 10:52:43.540427 DBI_RD = 0x0
7342 10:52:43.543611 OTF = 0x1
7343 10:52:43.547325 ===================================
7344 10:52:43.553609 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7345 10:52:43.553711 ==
7346 10:52:43.556759 Dram Type= 6, Freq= 0, CH_0, rank 0
7347 10:52:43.560061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7348 10:52:43.560150 ==
7349 10:52:43.563707 [Duty_Offset_Calibration]
7350 10:52:43.563793 B0:1 B1:-1 CA:0
7351 10:52:43.563860
7352 10:52:43.566699 [DutyScan_Calibration_Flow] k_type=0
7353 10:52:43.577995
7354 10:52:43.578119 ==CLK 0==
7355 10:52:43.581404 Final CLK duty delay cell = 0
7356 10:52:43.584467 [0] MAX Duty = 5124%(X100), DQS PI = 22
7357 10:52:43.588174 [0] MIN Duty = 4907%(X100), DQS PI = 6
7358 10:52:43.588269 [0] AVG Duty = 5015%(X100)
7359 10:52:43.591451
7360 10:52:43.594972 CH0 CLK Duty spec in!! Max-Min= 217%
7361 10:52:43.597759 [DutyScan_Calibration_Flow] ====Done====
7362 10:52:43.597849
7363 10:52:43.600957 [DutyScan_Calibration_Flow] k_type=1
7364 10:52:43.617045
7365 10:52:43.617175 ==DQS 0 ==
7366 10:52:43.621076 Final DQS duty delay cell = -4
7367 10:52:43.623517 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7368 10:52:43.627027 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7369 10:52:43.630563 [-4] AVG Duty = 4922%(X100)
7370 10:52:43.630654
7371 10:52:43.630720 ==DQS 1 ==
7372 10:52:43.633670 Final DQS duty delay cell = 0
7373 10:52:43.636767 [0] MAX Duty = 5156%(X100), DQS PI = 2
7374 10:52:43.640436 [0] MIN Duty = 5031%(X100), DQS PI = 20
7375 10:52:43.643685 [0] AVG Duty = 5093%(X100)
7376 10:52:43.643774
7377 10:52:43.647126 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7378 10:52:43.647212
7379 10:52:43.650130 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7380 10:52:43.654350 [DutyScan_Calibration_Flow] ====Done====
7381 10:52:43.654442
7382 10:52:43.656698 [DutyScan_Calibration_Flow] k_type=3
7383 10:52:43.674638
7384 10:52:43.674786 ==DQM 0 ==
7385 10:52:43.677971 Final DQM duty delay cell = 0
7386 10:52:43.681527 [0] MAX Duty = 5125%(X100), DQS PI = 22
7387 10:52:43.684766 [0] MIN Duty = 4876%(X100), DQS PI = 10
7388 10:52:43.687783 [0] AVG Duty = 5000%(X100)
7389 10:52:43.687871
7390 10:52:43.687935 ==DQM 1 ==
7391 10:52:43.690922 Final DQM duty delay cell = 0
7392 10:52:43.694322 [0] MAX Duty = 5000%(X100), DQS PI = 4
7393 10:52:43.697768 [0] MIN Duty = 4813%(X100), DQS PI = 20
7394 10:52:43.701021 [0] AVG Duty = 4906%(X100)
7395 10:52:43.701109
7396 10:52:43.704469 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7397 10:52:43.704592
7398 10:52:43.707447 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7399 10:52:43.711109 [DutyScan_Calibration_Flow] ====Done====
7400 10:52:43.711199
7401 10:52:43.714312 [DutyScan_Calibration_Flow] k_type=2
7402 10:52:43.731053
7403 10:52:43.731189 ==DQ 0 ==
7404 10:52:43.734022 Final DQ duty delay cell = -4
7405 10:52:43.737366 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7406 10:52:43.741005 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7407 10:52:43.744022 [-4] AVG Duty = 4953%(X100)
7408 10:52:43.744112
7409 10:52:43.744178 ==DQ 1 ==
7410 10:52:43.747936 Final DQ duty delay cell = 0
7411 10:52:43.750667 [0] MAX Duty = 5125%(X100), DQS PI = 4
7412 10:52:43.754114 [0] MIN Duty = 4969%(X100), DQS PI = 36
7413 10:52:43.757514 [0] AVG Duty = 5047%(X100)
7414 10:52:43.757611
7415 10:52:43.760714 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7416 10:52:43.760801
7417 10:52:43.763845 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7418 10:52:43.767218 [DutyScan_Calibration_Flow] ====Done====
7419 10:52:43.767304 ==
7420 10:52:43.770953 Dram Type= 6, Freq= 0, CH_1, rank 0
7421 10:52:43.773772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7422 10:52:43.773859 ==
7423 10:52:43.777193 [Duty_Offset_Calibration]
7424 10:52:43.777277 B0:-1 B1:1 CA:2
7425 10:52:43.777342
7426 10:52:43.780300 [DutyScan_Calibration_Flow] k_type=0
7427 10:52:43.791587
7428 10:52:43.791732 ==CLK 0==
7429 10:52:43.795216 Final CLK duty delay cell = 0
7430 10:52:43.798519 [0] MAX Duty = 5156%(X100), DQS PI = 20
7431 10:52:43.801440 [0] MIN Duty = 5031%(X100), DQS PI = 14
7432 10:52:43.804769 [0] AVG Duty = 5093%(X100)
7433 10:52:43.804855
7434 10:52:43.808088 CH1 CLK Duty spec in!! Max-Min= 125%
7435 10:52:43.811286 [DutyScan_Calibration_Flow] ====Done====
7436 10:52:43.811372
7437 10:52:43.815113 [DutyScan_Calibration_Flow] k_type=1
7438 10:52:43.831383
7439 10:52:43.831521 ==DQS 0 ==
7440 10:52:43.834532 Final DQS duty delay cell = 0
7441 10:52:43.838153 [0] MAX Duty = 5156%(X100), DQS PI = 20
7442 10:52:43.842055 [0] MIN Duty = 4938%(X100), DQS PI = 40
7443 10:52:43.844861 [0] AVG Duty = 5047%(X100)
7444 10:52:43.844963
7445 10:52:43.845030 ==DQS 1 ==
7446 10:52:43.848260 Final DQS duty delay cell = 0
7447 10:52:43.851352 [0] MAX Duty = 5093%(X100), DQS PI = 6
7448 10:52:43.854536 [0] MIN Duty = 5000%(X100), DQS PI = 24
7449 10:52:43.857844 [0] AVG Duty = 5046%(X100)
7450 10:52:43.857979
7451 10:52:43.860798 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7452 10:52:43.860883
7453 10:52:43.864502 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7454 10:52:43.867576 [DutyScan_Calibration_Flow] ====Done====
7455 10:52:43.867663
7456 10:52:43.870632 [DutyScan_Calibration_Flow] k_type=3
7457 10:52:43.887977
7458 10:52:43.888122 ==DQM 0 ==
7459 10:52:43.891210 Final DQM duty delay cell = 0
7460 10:52:43.894509 [0] MAX Duty = 5187%(X100), DQS PI = 4
7461 10:52:43.898006 [0] MIN Duty = 5031%(X100), DQS PI = 40
7462 10:52:43.901828 [0] AVG Duty = 5109%(X100)
7463 10:52:43.901920
7464 10:52:43.901987 ==DQM 1 ==
7465 10:52:43.904701 Final DQM duty delay cell = 0
7466 10:52:43.907817 [0] MAX Duty = 5187%(X100), DQS PI = 34
7467 10:52:43.911653 [0] MIN Duty = 4969%(X100), DQS PI = 58
7468 10:52:43.914574 [0] AVG Duty = 5078%(X100)
7469 10:52:43.914660
7470 10:52:43.918250 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7471 10:52:43.918336
7472 10:52:43.921606 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7473 10:52:43.924412 [DutyScan_Calibration_Flow] ====Done====
7474 10:52:43.924498
7475 10:52:43.927862 [DutyScan_Calibration_Flow] k_type=2
7476 10:52:43.945077
7477 10:52:43.945230 ==DQ 0 ==
7478 10:52:43.948502 Final DQ duty delay cell = 0
7479 10:52:43.951549 [0] MAX Duty = 5156%(X100), DQS PI = 0
7480 10:52:43.954661 [0] MIN Duty = 4906%(X100), DQS PI = 40
7481 10:52:43.954751 [0] AVG Duty = 5031%(X100)
7482 10:52:43.958203
7483 10:52:43.958291 ==DQ 1 ==
7484 10:52:43.961321 Final DQ duty delay cell = 0
7485 10:52:43.965126 [0] MAX Duty = 5156%(X100), DQS PI = 42
7486 10:52:43.967879 [0] MIN Duty = 4969%(X100), DQS PI = 28
7487 10:52:43.971192 [0] AVG Duty = 5062%(X100)
7488 10:52:43.971280
7489 10:52:43.974453 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7490 10:52:43.974540
7491 10:52:43.978247 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7492 10:52:43.981478 [DutyScan_Calibration_Flow] ====Done====
7493 10:52:43.984556 nWR fixed to 30
7494 10:52:43.987925 [ModeRegInit_LP4] CH0 RK0
7495 10:52:43.988015 [ModeRegInit_LP4] CH0 RK1
7496 10:52:43.991386 [ModeRegInit_LP4] CH1 RK0
7497 10:52:43.994328 [ModeRegInit_LP4] CH1 RK1
7498 10:52:43.994415 match AC timing 5
7499 10:52:44.000801 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7500 10:52:44.004211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7501 10:52:44.007427 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7502 10:52:44.014196 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7503 10:52:44.017492 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7504 10:52:44.017592 [MiockJmeterHQA]
7505 10:52:44.017663
7506 10:52:44.020666 [DramcMiockJmeter] u1RxGatingPI = 0
7507 10:52:44.024231 0 : 4257, 4029
7508 10:52:44.024320 4 : 4363, 4138
7509 10:52:44.027346 8 : 4368, 4139
7510 10:52:44.027434 12 : 4365, 4140
7511 10:52:44.030437 16 : 4362, 4137
7512 10:52:44.030531 20 : 4252, 4027
7513 10:52:44.030599 24 : 4254, 4029
7514 10:52:44.033973 28 : 4253, 4027
7515 10:52:44.034060 32 : 4363, 4138
7516 10:52:44.037382 36 : 4252, 4027
7517 10:52:44.037470 40 : 4363, 4137
7518 10:52:44.040579 44 : 4252, 4027
7519 10:52:44.040665 48 : 4253, 4026
7520 10:52:44.044196 52 : 4253, 4026
7521 10:52:44.044284 56 : 4255, 4029
7522 10:52:44.044352 60 : 4250, 4026
7523 10:52:44.047182 64 : 4252, 4030
7524 10:52:44.047269 68 : 4363, 4139
7525 10:52:44.050490 72 : 4250, 4027
7526 10:52:44.050576 76 : 4252, 4029
7527 10:52:44.054023 80 : 4250, 4027
7528 10:52:44.054110 84 : 4360, 4138
7529 10:52:44.057812 88 : 4250, 4027
7530 10:52:44.057899 92 : 4360, 386
7531 10:52:44.057967 96 : 4249, 0
7532 10:52:44.060327 100 : 4250, 0
7533 10:52:44.060413 104 : 4250, 0
7534 10:52:44.063955 108 : 4250, 0
7535 10:52:44.064044 112 : 4252, 0
7536 10:52:44.064112 116 : 4250, 0
7537 10:52:44.067027 120 : 4250, 0
7538 10:52:44.067112 124 : 4252, 0
7539 10:52:44.067179 128 : 4360, 0
7540 10:52:44.070181 132 : 4250, 0
7541 10:52:44.070268 136 : 4249, 0
7542 10:52:44.073441 140 : 4249, 0
7543 10:52:44.073528 144 : 4361, 0
7544 10:52:44.073596 148 : 4360, 0
7545 10:52:44.076478 152 : 4249, 0
7546 10:52:44.076603 156 : 4250, 0
7547 10:52:44.079913 160 : 4250, 0
7548 10:52:44.080001 164 : 4252, 0
7549 10:52:44.080069 168 : 4250, 0
7550 10:52:44.083449 172 : 4250, 0
7551 10:52:44.083540 176 : 4252, 0
7552 10:52:44.087046 180 : 4360, 0
7553 10:52:44.087134 184 : 4250, 0
7554 10:52:44.087201 188 : 4249, 0
7555 10:52:44.090415 192 : 4249, 0
7556 10:52:44.090503 196 : 4361, 0
7557 10:52:44.093062 200 : 4361, 0
7558 10:52:44.093147 204 : 4250, 0
7559 10:52:44.093215 208 : 4250, 0
7560 10:52:44.096370 212 : 4363, 0
7561 10:52:44.096457 216 : 4250, 0
7562 10:52:44.099586 220 : 4250, 0
7563 10:52:44.099672 224 : 4250, 490
7564 10:52:44.099740 228 : 4360, 3748
7565 10:52:44.103300 232 : 4249, 4027
7566 10:52:44.103386 236 : 4363, 4140
7567 10:52:44.106392 240 : 4252, 4029
7568 10:52:44.106479 244 : 4250, 4027
7569 10:52:44.109726 248 : 4249, 4027
7570 10:52:44.109813 252 : 4253, 4029
7571 10:52:44.113062 256 : 4250, 4027
7572 10:52:44.113150 260 : 4250, 4027
7573 10:52:44.116173 264 : 4249, 4027
7574 10:52:44.116259 268 : 4253, 4029
7575 10:52:44.119666 272 : 4250, 4027
7576 10:52:44.119753 276 : 4360, 4138
7577 10:52:44.123207 280 : 4360, 4138
7578 10:52:44.123294 284 : 4250, 4026
7579 10:52:44.123361 288 : 4363, 4139
7580 10:52:44.126276 292 : 4360, 4138
7581 10:52:44.126366 296 : 4250, 4027
7582 10:52:44.129440 300 : 4249, 4027
7583 10:52:44.129528 304 : 4252, 4029
7584 10:52:44.132645 308 : 4250, 4027
7585 10:52:44.132732 312 : 4250, 4027
7586 10:52:44.136334 316 : 4250, 4027
7587 10:52:44.136422 320 : 4252, 4029
7588 10:52:44.139117 324 : 4250, 4027
7589 10:52:44.139205 328 : 4360, 4138
7590 10:52:44.142643 332 : 4360, 4138
7591 10:52:44.142731 336 : 4249, 3383
7592 10:52:44.145699 340 : 4363, 1428
7593 10:52:44.145786
7594 10:52:44.145853 MIOCK jitter meter ch=0
7595 10:52:44.145915
7596 10:52:44.149765 1T = (340-92) = 248 dly cells
7597 10:52:44.156365 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7598 10:52:44.156464 ==
7599 10:52:44.159240 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 10:52:44.162068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 10:52:44.162162 ==
7602 10:52:44.169230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7603 10:52:44.172297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7604 10:52:44.179977 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7605 10:52:44.181996 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7606 10:52:44.192173 [CA 0] Center 43 (13~74) winsize 62
7607 10:52:44.195805 [CA 1] Center 43 (13~74) winsize 62
7608 10:52:44.198774 [CA 2] Center 39 (10~69) winsize 60
7609 10:52:44.202056 [CA 3] Center 39 (10~69) winsize 60
7610 10:52:44.205462 [CA 4] Center 37 (8~66) winsize 59
7611 10:52:44.208678 [CA 5] Center 36 (7~66) winsize 60
7612 10:52:44.208772
7613 10:52:44.211851 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7614 10:52:44.211937
7615 10:52:44.218392 [CATrainingPosCal] consider 1 rank data
7616 10:52:44.218509 u2DelayCellTimex100 = 262/100 ps
7617 10:52:44.225559 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7618 10:52:44.228405 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7619 10:52:44.232129 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7620 10:52:44.235243 CA3 delay=39 (10~69),Diff = 3 PI (11 cell)
7621 10:52:44.238411 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7622 10:52:44.241620 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7623 10:52:44.241711
7624 10:52:44.244670 CA PerBit enable=1, Macro0, CA PI delay=36
7625 10:52:44.244782
7626 10:52:44.248152 [CBTSetCACLKResult] CA Dly = 36
7627 10:52:44.251303 CS Dly: 12 (0~43)
7628 10:52:44.254864 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7629 10:52:44.257644 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7630 10:52:44.261243 ==
7631 10:52:44.264630 Dram Type= 6, Freq= 0, CH_0, rank 1
7632 10:52:44.267510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 10:52:44.267599 ==
7634 10:52:44.271370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7635 10:52:44.277653 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7636 10:52:44.280945 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7637 10:52:44.287112 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7638 10:52:44.296051 [CA 0] Center 42 (12~73) winsize 62
7639 10:52:44.299282 [CA 1] Center 43 (13~73) winsize 61
7640 10:52:44.302506 [CA 2] Center 37 (8~67) winsize 60
7641 10:52:44.306106 [CA 3] Center 37 (7~67) winsize 61
7642 10:52:44.308834 [CA 4] Center 35 (6~65) winsize 60
7643 10:52:44.312487 [CA 5] Center 35 (5~65) winsize 61
7644 10:52:44.312621
7645 10:52:44.315465 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7646 10:52:44.315551
7647 10:52:44.322469 [CATrainingPosCal] consider 2 rank data
7648 10:52:44.322562 u2DelayCellTimex100 = 262/100 ps
7649 10:52:44.328661 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7650 10:52:44.331858 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7651 10:52:44.335146 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7652 10:52:44.338571 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7653 10:52:44.342481 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7654 10:52:44.345472 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7655 10:52:44.345563
7656 10:52:44.348622 CA PerBit enable=1, Macro0, CA PI delay=36
7657 10:52:44.348711
7658 10:52:44.351966 [CBTSetCACLKResult] CA Dly = 36
7659 10:52:44.355055 CS Dly: 12 (0~44)
7660 10:52:44.358460 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7661 10:52:44.362005 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7662 10:52:44.362095
7663 10:52:44.365353 ----->DramcWriteLeveling(PI) begin...
7664 10:52:44.368413 ==
7665 10:52:44.368498 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 10:52:44.375416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 10:52:44.375514 ==
7668 10:52:44.378629 Write leveling (Byte 0): 36 => 36
7669 10:52:44.381760 Write leveling (Byte 1): 28 => 28
7670 10:52:44.385080 DramcWriteLeveling(PI) end<-----
7671 10:52:44.385171
7672 10:52:44.385239 ==
7673 10:52:44.388455 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 10:52:44.391435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 10:52:44.391521 ==
7676 10:52:44.394807 [Gating] SW mode calibration
7677 10:52:44.401088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7678 10:52:44.407895 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7679 10:52:44.411029 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 10:52:44.414583 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 10:52:44.421027 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 10:52:44.424125 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7683 10:52:44.427683 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7684 10:52:44.434390 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7685 10:52:44.437702 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7686 10:52:44.441039 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7687 10:52:44.448036 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7688 10:52:44.450709 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7689 10:52:44.454250 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7690 10:52:44.457889 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7691 10:52:44.464441 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7692 10:52:44.467648 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7693 10:52:44.470754 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7694 10:52:44.477339 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7695 10:52:44.480964 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7696 10:52:44.484029 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7697 10:52:44.490667 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7698 10:52:44.493762 1 6 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7699 10:52:44.497085 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7700 10:52:44.503820 1 6 20 | B1->B0 | 2827 4646 | 1 0 | (0 0) (0 0)
7701 10:52:44.507188 1 6 24 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
7702 10:52:44.510570 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7703 10:52:44.517119 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7704 10:52:44.520501 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 10:52:44.523556 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7706 10:52:44.529901 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7707 10:52:44.533653 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7708 10:52:44.536918 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7709 10:52:44.543690 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7710 10:52:44.546954 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 10:52:44.550448 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 10:52:44.556847 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 10:52:44.560287 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 10:52:44.563444 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 10:52:44.569915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 10:52:44.573184 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 10:52:44.576394 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 10:52:44.582915 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 10:52:44.586413 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7720 10:52:44.589458 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7721 10:52:44.595947 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7722 10:52:44.599440 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7723 10:52:44.602713 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7724 10:52:44.605955 Total UI for P1: 0, mck2ui 16
7725 10:52:44.609270 best dqsien dly found for B0: ( 1, 9, 10)
7726 10:52:44.615779 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7727 10:52:44.619294 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7728 10:52:44.622330 Total UI for P1: 0, mck2ui 16
7729 10:52:44.626050 best dqsien dly found for B1: ( 1, 9, 20)
7730 10:52:44.629448 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7731 10:52:44.632126 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7732 10:52:44.632214
7733 10:52:44.635379 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7734 10:52:44.642423 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7735 10:52:44.642527 [Gating] SW calibration Done
7736 10:52:44.642594 ==
7737 10:52:44.645415 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 10:52:44.652201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 10:52:44.652301 ==
7740 10:52:44.652370 RX Vref Scan: 0
7741 10:52:44.652431
7742 10:52:44.655426 RX Vref 0 -> 0, step: 1
7743 10:52:44.655511
7744 10:52:44.658688 RX Delay 0 -> 252, step: 8
7745 10:52:44.662130 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7746 10:52:44.665248 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7747 10:52:44.668846 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7748 10:52:44.674978 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7749 10:52:44.678189 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7750 10:52:44.681425 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7751 10:52:44.684997 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7752 10:52:44.688050 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7753 10:52:44.694650 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7754 10:52:44.698062 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7755 10:52:44.701829 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7756 10:52:44.704760 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7757 10:52:44.708205 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7758 10:52:44.714619 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7759 10:52:44.717706 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7760 10:52:44.721452 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7761 10:52:44.721545 ==
7762 10:52:44.724511 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 10:52:44.731480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 10:52:44.731583 ==
7765 10:52:44.731651 DQS Delay:
7766 10:52:44.731712 DQS0 = 0, DQS1 = 0
7767 10:52:44.734363 DQM Delay:
7768 10:52:44.734449 DQM0 = 136, DQM1 = 126
7769 10:52:44.737732 DQ Delay:
7770 10:52:44.740876 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7771 10:52:44.744179 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7772 10:52:44.747592 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7773 10:52:44.750723 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7774 10:52:44.750809
7775 10:52:44.750874
7776 10:52:44.750932 ==
7777 10:52:44.754033 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 10:52:44.760835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 10:52:44.760934 ==
7780 10:52:44.761001
7781 10:52:44.761060
7782 10:52:44.761118 TX Vref Scan disable
7783 10:52:44.763680 == TX Byte 0 ==
7784 10:52:44.767058 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7785 10:52:44.773605 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7786 10:52:44.773709 == TX Byte 1 ==
7787 10:52:44.776834 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7788 10:52:44.783513 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7789 10:52:44.783623 ==
7790 10:52:44.786803 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 10:52:44.790091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 10:52:44.790182 ==
7793 10:52:44.803127
7794 10:52:44.806830 TX Vref early break, caculate TX vref
7795 10:52:44.809675 TX Vref=16, minBit 5, minWin=22, winSum=372
7796 10:52:44.813244 TX Vref=18, minBit 4, minWin=22, winSum=384
7797 10:52:44.816493 TX Vref=20, minBit 1, minWin=23, winSum=396
7798 10:52:44.819920 TX Vref=22, minBit 3, minWin=24, winSum=403
7799 10:52:44.823020 TX Vref=24, minBit 0, minWin=25, winSum=408
7800 10:52:44.829523 TX Vref=26, minBit 3, minWin=24, winSum=413
7801 10:52:44.833163 TX Vref=28, minBit 4, minWin=25, winSum=418
7802 10:52:44.836250 TX Vref=30, minBit 0, minWin=24, winSum=412
7803 10:52:44.839296 TX Vref=32, minBit 5, minWin=23, winSum=404
7804 10:52:44.842697 TX Vref=34, minBit 4, minWin=23, winSum=390
7805 10:52:44.849184 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7806 10:52:44.849286
7807 10:52:44.852271 Final TX Range 0 Vref 28
7808 10:52:44.852353
7809 10:52:44.852417 ==
7810 10:52:44.855567 Dram Type= 6, Freq= 0, CH_0, rank 0
7811 10:52:44.858738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7812 10:52:44.858821 ==
7813 10:52:44.858886
7814 10:52:44.862124
7815 10:52:44.862232 TX Vref Scan disable
7816 10:52:44.868704 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7817 10:52:44.868835 == TX Byte 0 ==
7818 10:52:44.872081 u2DelayCellOfst[0]=18 cells (5 PI)
7819 10:52:44.875716 u2DelayCellOfst[1]=18 cells (5 PI)
7820 10:52:44.878782 u2DelayCellOfst[2]=14 cells (4 PI)
7821 10:52:44.882152 u2DelayCellOfst[3]=14 cells (4 PI)
7822 10:52:44.885476 u2DelayCellOfst[4]=11 cells (3 PI)
7823 10:52:44.888859 u2DelayCellOfst[5]=0 cells (0 PI)
7824 10:52:44.892082 u2DelayCellOfst[6]=18 cells (5 PI)
7825 10:52:44.895449 u2DelayCellOfst[7]=22 cells (6 PI)
7826 10:52:44.898411 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7827 10:52:44.901854 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7828 10:52:44.905154 == TX Byte 1 ==
7829 10:52:44.908410 u2DelayCellOfst[8]=0 cells (0 PI)
7830 10:52:44.911513 u2DelayCellOfst[9]=3 cells (1 PI)
7831 10:52:44.914948 u2DelayCellOfst[10]=7 cells (2 PI)
7832 10:52:44.918620 u2DelayCellOfst[11]=3 cells (1 PI)
7833 10:52:44.921842 u2DelayCellOfst[12]=11 cells (3 PI)
7834 10:52:44.924825 u2DelayCellOfst[13]=11 cells (3 PI)
7835 10:52:44.928120 u2DelayCellOfst[14]=14 cells (4 PI)
7836 10:52:44.928237 u2DelayCellOfst[15]=11 cells (3 PI)
7837 10:52:44.934769 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7838 10:52:44.937988 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7839 10:52:44.941120 DramC Write-DBI on
7840 10:52:44.941207 ==
7841 10:52:44.944320 Dram Type= 6, Freq= 0, CH_0, rank 0
7842 10:52:44.948179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7843 10:52:44.948270 ==
7844 10:52:44.948336
7845 10:52:44.948395
7846 10:52:44.950983 TX Vref Scan disable
7847 10:52:44.951066 == TX Byte 0 ==
7848 10:52:44.958052 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7849 10:52:44.958146 == TX Byte 1 ==
7850 10:52:44.964309 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7851 10:52:44.964404 DramC Write-DBI off
7852 10:52:44.964470
7853 10:52:44.964558 [DATLAT]
7854 10:52:44.967524 Freq=1600, CH0 RK0
7855 10:52:44.967607
7856 10:52:44.970946 DATLAT Default: 0xf
7857 10:52:44.971030 0, 0xFFFF, sum = 0
7858 10:52:44.974455 1, 0xFFFF, sum = 0
7859 10:52:44.974541 2, 0xFFFF, sum = 0
7860 10:52:44.977431 3, 0xFFFF, sum = 0
7861 10:52:44.977515 4, 0xFFFF, sum = 0
7862 10:52:44.981242 5, 0xFFFF, sum = 0
7863 10:52:44.981384 6, 0xFFFF, sum = 0
7864 10:52:44.983874 7, 0xFFFF, sum = 0
7865 10:52:44.983961 8, 0xFFFF, sum = 0
7866 10:52:44.987350 9, 0xFFFF, sum = 0
7867 10:52:44.987443 10, 0xFFFF, sum = 0
7868 10:52:44.990988 11, 0xFFFF, sum = 0
7869 10:52:44.991075 12, 0xFFFF, sum = 0
7870 10:52:44.993905 13, 0xFFFF, sum = 0
7871 10:52:44.993990 14, 0x0, sum = 1
7872 10:52:44.997142 15, 0x0, sum = 2
7873 10:52:44.997227 16, 0x0, sum = 3
7874 10:52:45.000923 17, 0x0, sum = 4
7875 10:52:45.001010 best_step = 15
7876 10:52:45.001076
7877 10:52:45.001136 ==
7878 10:52:45.004140 Dram Type= 6, Freq= 0, CH_0, rank 0
7879 10:52:45.010606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7880 10:52:45.010701 ==
7881 10:52:45.010768 RX Vref Scan: 1
7882 10:52:45.010827
7883 10:52:45.013620 Set Vref Range= 24 -> 127
7884 10:52:45.013704
7885 10:52:45.016956 RX Vref 24 -> 127, step: 1
7886 10:52:45.017041
7887 10:52:45.020198 RX Delay 11 -> 252, step: 4
7888 10:52:45.020285
7889 10:52:45.023662 Set Vref, RX VrefLevel [Byte0]: 24
7890 10:52:45.023746 [Byte1]: 24
7891 10:52:45.028032
7892 10:52:45.028134 Set Vref, RX VrefLevel [Byte0]: 25
7893 10:52:45.031380 [Byte1]: 25
7894 10:52:45.035617
7895 10:52:45.035720 Set Vref, RX VrefLevel [Byte0]: 26
7896 10:52:45.039001 [Byte1]: 26
7897 10:52:45.043258
7898 10:52:45.043347 Set Vref, RX VrefLevel [Byte0]: 27
7899 10:52:45.046463 [Byte1]: 27
7900 10:52:45.050975
7901 10:52:45.051065 Set Vref, RX VrefLevel [Byte0]: 28
7902 10:52:45.054578 [Byte1]: 28
7903 10:52:45.058783
7904 10:52:45.058869 Set Vref, RX VrefLevel [Byte0]: 29
7905 10:52:45.062343 [Byte1]: 29
7906 10:52:45.066295
7907 10:52:45.066381 Set Vref, RX VrefLevel [Byte0]: 30
7908 10:52:45.069256 [Byte1]: 30
7909 10:52:45.073712
7910 10:52:45.073801 Set Vref, RX VrefLevel [Byte0]: 31
7911 10:52:45.077288 [Byte1]: 31
7912 10:52:45.081218
7913 10:52:45.081304 Set Vref, RX VrefLevel [Byte0]: 32
7914 10:52:45.084319 [Byte1]: 32
7915 10:52:45.089670
7916 10:52:45.089792 Set Vref, RX VrefLevel [Byte0]: 33
7917 10:52:45.092457 [Byte1]: 33
7918 10:52:45.096761
7919 10:52:45.096850 Set Vref, RX VrefLevel [Byte0]: 34
7920 10:52:45.099934 [Byte1]: 34
7921 10:52:45.104415
7922 10:52:45.104511 Set Vref, RX VrefLevel [Byte0]: 35
7923 10:52:45.107135 [Byte1]: 35
7924 10:52:45.112062
7925 10:52:45.112154 Set Vref, RX VrefLevel [Byte0]: 36
7926 10:52:45.115420 [Byte1]: 36
7927 10:52:45.119379
7928 10:52:45.119467 Set Vref, RX VrefLevel [Byte0]: 37
7929 10:52:45.122474 [Byte1]: 37
7930 10:52:45.127255
7931 10:52:45.127347 Set Vref, RX VrefLevel [Byte0]: 38
7932 10:52:45.130313 [Byte1]: 38
7933 10:52:45.134741
7934 10:52:45.134833 Set Vref, RX VrefLevel [Byte0]: 39
7935 10:52:45.137923 [Byte1]: 39
7936 10:52:45.142275
7937 10:52:45.142367 Set Vref, RX VrefLevel [Byte0]: 40
7938 10:52:45.145643 [Byte1]: 40
7939 10:52:45.149498
7940 10:52:45.153191 Set Vref, RX VrefLevel [Byte0]: 41
7941 10:52:45.153285 [Byte1]: 41
7942 10:52:45.157262
7943 10:52:45.157352 Set Vref, RX VrefLevel [Byte0]: 42
7944 10:52:45.160496 [Byte1]: 42
7945 10:52:45.165266
7946 10:52:45.165361 Set Vref, RX VrefLevel [Byte0]: 43
7947 10:52:45.168230 [Byte1]: 43
7948 10:52:45.172921
7949 10:52:45.173015 Set Vref, RX VrefLevel [Byte0]: 44
7950 10:52:45.176117 [Byte1]: 44
7951 10:52:45.180348
7952 10:52:45.180455 Set Vref, RX VrefLevel [Byte0]: 45
7953 10:52:45.183779 [Byte1]: 45
7954 10:52:45.187936
7955 10:52:45.188037 Set Vref, RX VrefLevel [Byte0]: 46
7956 10:52:45.192018 [Byte1]: 46
7957 10:52:45.195467
7958 10:52:45.195558 Set Vref, RX VrefLevel [Byte0]: 47
7959 10:52:45.198834 [Byte1]: 47
7960 10:52:45.203591
7961 10:52:45.203685 Set Vref, RX VrefLevel [Byte0]: 48
7962 10:52:45.206548 [Byte1]: 48
7963 10:52:45.210614
7964 10:52:45.210704 Set Vref, RX VrefLevel [Byte0]: 49
7965 10:52:45.213934 [Byte1]: 49
7966 10:52:45.218576
7967 10:52:45.218666 Set Vref, RX VrefLevel [Byte0]: 50
7968 10:52:45.221994 [Byte1]: 50
7969 10:52:45.225937
7970 10:52:45.226026 Set Vref, RX VrefLevel [Byte0]: 51
7971 10:52:45.229139 [Byte1]: 51
7972 10:52:45.233619
7973 10:52:45.233709 Set Vref, RX VrefLevel [Byte0]: 52
7974 10:52:45.236675 [Byte1]: 52
7975 10:52:45.241186
7976 10:52:45.241277 Set Vref, RX VrefLevel [Byte0]: 53
7977 10:52:45.245046 [Byte1]: 53
7978 10:52:45.248869
7979 10:52:45.248964 Set Vref, RX VrefLevel [Byte0]: 54
7980 10:52:45.252271 [Byte1]: 54
7981 10:52:45.256189
7982 10:52:45.256282 Set Vref, RX VrefLevel [Byte0]: 55
7983 10:52:45.260085 [Byte1]: 55
7984 10:52:45.263787
7985 10:52:45.263879 Set Vref, RX VrefLevel [Byte0]: 56
7986 10:52:45.267488 [Byte1]: 56
7987 10:52:45.271616
7988 10:52:45.271707 Set Vref, RX VrefLevel [Byte0]: 57
7989 10:52:45.274705 [Byte1]: 57
7990 10:52:45.279448
7991 10:52:45.279541 Set Vref, RX VrefLevel [Byte0]: 58
7992 10:52:45.282666 [Byte1]: 58
7993 10:52:45.286921
7994 10:52:45.287015 Set Vref, RX VrefLevel [Byte0]: 59
7995 10:52:45.290101 [Byte1]: 59
7996 10:52:45.294281
7997 10:52:45.294374 Set Vref, RX VrefLevel [Byte0]: 60
7998 10:52:45.297919 [Byte1]: 60
7999 10:52:45.302325
8000 10:52:45.302419 Set Vref, RX VrefLevel [Byte0]: 61
8001 10:52:45.305329 [Byte1]: 61
8002 10:52:45.309670
8003 10:52:45.309762 Set Vref, RX VrefLevel [Byte0]: 62
8004 10:52:45.312897 [Byte1]: 62
8005 10:52:45.317203
8006 10:52:45.317295 Set Vref, RX VrefLevel [Byte0]: 63
8007 10:52:45.320399 [Byte1]: 63
8008 10:52:45.325021
8009 10:52:45.325111 Set Vref, RX VrefLevel [Byte0]: 64
8010 10:52:45.328035 [Byte1]: 64
8011 10:52:45.332563
8012 10:52:45.332654 Set Vref, RX VrefLevel [Byte0]: 65
8013 10:52:45.335790 [Byte1]: 65
8014 10:52:45.340778
8015 10:52:45.340870 Set Vref, RX VrefLevel [Byte0]: 66
8016 10:52:45.343316 [Byte1]: 66
8017 10:52:45.348002
8018 10:52:45.348095 Set Vref, RX VrefLevel [Byte0]: 67
8019 10:52:45.350866 [Byte1]: 67
8020 10:52:45.355064
8021 10:52:45.355164 Set Vref, RX VrefLevel [Byte0]: 68
8022 10:52:45.358933 [Byte1]: 68
8023 10:52:45.363167
8024 10:52:45.363262 Set Vref, RX VrefLevel [Byte0]: 69
8025 10:52:45.366201 [Byte1]: 69
8026 10:52:45.370381
8027 10:52:45.370472 Set Vref, RX VrefLevel [Byte0]: 70
8028 10:52:45.373726 [Byte1]: 70
8029 10:52:45.378457
8030 10:52:45.378546 Set Vref, RX VrefLevel [Byte0]: 71
8031 10:52:45.381563 [Byte1]: 71
8032 10:52:45.385566
8033 10:52:45.385665 Set Vref, RX VrefLevel [Byte0]: 72
8034 10:52:45.389299 [Byte1]: 72
8035 10:52:45.393710
8036 10:52:45.393802 Set Vref, RX VrefLevel [Byte0]: 73
8037 10:52:45.396649 [Byte1]: 73
8038 10:52:45.400876
8039 10:52:45.400967 Set Vref, RX VrefLevel [Byte0]: 74
8040 10:52:45.404030 [Byte1]: 74
8041 10:52:45.408504
8042 10:52:45.408604 Set Vref, RX VrefLevel [Byte0]: 75
8043 10:52:45.411706 [Byte1]: 75
8044 10:52:45.416177
8045 10:52:45.416269 Set Vref, RX VrefLevel [Byte0]: 76
8046 10:52:45.419849 [Byte1]: 76
8047 10:52:45.424369
8048 10:52:45.424461 Set Vref, RX VrefLevel [Byte0]: 77
8049 10:52:45.426816 [Byte1]: 77
8050 10:52:45.431509
8051 10:52:45.431599 Set Vref, RX VrefLevel [Byte0]: 78
8052 10:52:45.434816 [Byte1]: 78
8053 10:52:45.438943
8054 10:52:45.439036 Set Vref, RX VrefLevel [Byte0]: 79
8055 10:52:45.442645 [Byte1]: 79
8056 10:52:45.446716
8057 10:52:45.446808 Final RX Vref Byte 0 = 68 to rank0
8058 10:52:45.450342 Final RX Vref Byte 1 = 58 to rank0
8059 10:52:45.453673 Final RX Vref Byte 0 = 68 to rank1
8060 10:52:45.456488 Final RX Vref Byte 1 = 58 to rank1==
8061 10:52:45.459753 Dram Type= 6, Freq= 0, CH_0, rank 0
8062 10:52:45.466568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 10:52:45.466678 ==
8064 10:52:45.466749 DQS Delay:
8065 10:52:45.469596 DQS0 = 0, DQS1 = 0
8066 10:52:45.469683 DQM Delay:
8067 10:52:45.469750 DQM0 = 134, DQM1 = 123
8068 10:52:45.472984 DQ Delay:
8069 10:52:45.476440 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =134
8070 10:52:45.479445 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =144
8071 10:52:45.483184 DQ8 =116, DQ9 =112, DQ10 =122, DQ11 =118
8072 10:52:45.486329 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8073 10:52:45.486425
8074 10:52:45.486493
8075 10:52:45.486554
8076 10:52:45.489656 [DramC_TX_OE_Calibration] TA2
8077 10:52:45.492633 Original DQ_B0 (3 6) =30, OEN = 27
8078 10:52:45.496280 Original DQ_B1 (3 6) =30, OEN = 27
8079 10:52:45.499167 24, 0x0, End_B0=24 End_B1=24
8080 10:52:45.503372 25, 0x0, End_B0=25 End_B1=25
8081 10:52:45.503484 26, 0x0, End_B0=26 End_B1=26
8082 10:52:45.506153 27, 0x0, End_B0=27 End_B1=27
8083 10:52:45.509666 28, 0x0, End_B0=28 End_B1=28
8084 10:52:45.512041 29, 0x0, End_B0=29 End_B1=29
8085 10:52:45.515821 30, 0x0, End_B0=30 End_B1=30
8086 10:52:45.515917 31, 0x4141, End_B0=30 End_B1=30
8087 10:52:45.518833 Byte0 end_step=30 best_step=27
8088 10:52:45.522556 Byte1 end_step=30 best_step=27
8089 10:52:45.525724 Byte0 TX OE(2T, 0.5T) = (3, 3)
8090 10:52:45.528673 Byte1 TX OE(2T, 0.5T) = (3, 3)
8091 10:52:45.528762
8092 10:52:45.528828
8093 10:52:45.535418 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8094 10:52:45.538494 CH0 RK0: MR19=303, MR18=1F10
8095 10:52:45.545363 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8096 10:52:45.545473
8097 10:52:45.548801 ----->DramcWriteLeveling(PI) begin...
8098 10:52:45.548889 ==
8099 10:52:45.551905 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 10:52:45.555764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 10:52:45.555854 ==
8102 10:52:45.558576 Write leveling (Byte 0): 34 => 34
8103 10:52:45.561801 Write leveling (Byte 1): 29 => 29
8104 10:52:45.565145 DramcWriteLeveling(PI) end<-----
8105 10:52:45.565235
8106 10:52:45.565302 ==
8107 10:52:45.568457 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 10:52:45.574752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 10:52:45.574855 ==
8110 10:52:45.574925 [Gating] SW mode calibration
8111 10:52:45.584784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8112 10:52:45.588361 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8113 10:52:45.594590 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 10:52:45.598319 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 10:52:45.601654 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 10:52:45.604666 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 10:52:45.611739 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8118 10:52:45.614437 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8119 10:52:45.617875 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 10:52:45.624948 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 10:52:45.627773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 10:52:45.631152 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 10:52:45.638107 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8124 10:52:45.641087 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8125 10:52:45.647615 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
8126 10:52:45.650518 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8127 10:52:45.654286 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 10:52:45.660804 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 10:52:45.664426 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 10:52:45.666975 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 10:52:45.674065 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 10:52:45.677466 1 6 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8133 10:52:45.680741 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8134 10:52:45.686920 1 6 20 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8135 10:52:45.690585 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8136 10:52:45.693444 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 10:52:45.700429 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 10:52:45.703302 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 10:52:45.706960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 10:52:45.710514 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8141 10:52:45.716862 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8142 10:52:45.720015 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8143 10:52:45.723528 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8144 10:52:45.730494 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 10:52:45.733595 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 10:52:45.736719 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 10:52:45.743219 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 10:52:45.746915 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 10:52:45.750470 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 10:52:45.756359 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 10:52:45.760158 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 10:52:45.763044 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 10:52:45.769731 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 10:52:45.773239 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 10:52:45.776346 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8156 10:52:45.783475 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8157 10:52:45.786402 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8158 10:52:45.789607 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8159 10:52:45.793261 Total UI for P1: 0, mck2ui 16
8160 10:52:45.796429 best dqsien dly found for B0: ( 1, 9, 12)
8161 10:52:45.802934 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8162 10:52:45.803044 Total UI for P1: 0, mck2ui 16
8163 10:52:45.809275 best dqsien dly found for B1: ( 1, 9, 20)
8164 10:52:45.812664 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8165 10:52:45.816373 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8166 10:52:45.816493
8167 10:52:45.819372 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8168 10:52:45.822703 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8169 10:52:45.826183 [Gating] SW calibration Done
8170 10:52:45.826274 ==
8171 10:52:45.829007 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 10:52:45.832666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 10:52:45.832755 ==
8174 10:52:45.835994 RX Vref Scan: 0
8175 10:52:45.836081
8176 10:52:45.838914 RX Vref 0 -> 0, step: 1
8177 10:52:45.839027
8178 10:52:45.839104 RX Delay 0 -> 252, step: 8
8179 10:52:45.845709 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8180 10:52:45.849330 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8181 10:52:45.852328 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8182 10:52:45.855278 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8183 10:52:45.859026 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8184 10:52:45.865434 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8185 10:52:45.868648 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8186 10:52:45.872236 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8187 10:52:45.875140 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8188 10:52:45.878327 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8189 10:52:45.885036 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8190 10:52:45.888169 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8191 10:52:45.891929 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8192 10:52:45.895048 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8193 10:52:45.901567 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8194 10:52:45.905378 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8195 10:52:45.905478 ==
8196 10:52:45.908235 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 10:52:45.911526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 10:52:45.911615 ==
8199 10:52:45.914694 DQS Delay:
8200 10:52:45.914785 DQS0 = 0, DQS1 = 0
8201 10:52:45.914853 DQM Delay:
8202 10:52:45.918201 DQM0 = 133, DQM1 = 128
8203 10:52:45.918289 DQ Delay:
8204 10:52:45.921294 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8205 10:52:45.925161 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8206 10:52:45.927921 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8207 10:52:45.935110 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8208 10:52:45.935217
8209 10:52:45.935286
8210 10:52:45.935347 ==
8211 10:52:45.937783 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 10:52:45.941046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 10:52:45.941134 ==
8214 10:52:45.941200
8215 10:52:45.941261
8216 10:52:45.944301 TX Vref Scan disable
8217 10:52:45.944386 == TX Byte 0 ==
8218 10:52:45.951475 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8219 10:52:45.954717 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8220 10:52:45.954810 == TX Byte 1 ==
8221 10:52:45.961211 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8222 10:52:45.964328 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8223 10:52:45.964419 ==
8224 10:52:45.967479 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 10:52:45.970719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 10:52:45.970808 ==
8227 10:52:45.984258
8228 10:52:45.987532 TX Vref early break, caculate TX vref
8229 10:52:45.990921 TX Vref=16, minBit 3, minWin=22, winSum=379
8230 10:52:45.994507 TX Vref=18, minBit 0, minWin=23, winSum=390
8231 10:52:45.997831 TX Vref=20, minBit 0, minWin=24, winSum=398
8232 10:52:46.001051 TX Vref=22, minBit 1, minWin=23, winSum=405
8233 10:52:46.003849 TX Vref=24, minBit 1, minWin=24, winSum=415
8234 10:52:46.010864 TX Vref=26, minBit 1, minWin=24, winSum=420
8235 10:52:46.013972 TX Vref=28, minBit 1, minWin=24, winSum=413
8236 10:52:46.017022 TX Vref=30, minBit 0, minWin=24, winSum=401
8237 10:52:46.020433 TX Vref=32, minBit 0, minWin=23, winSum=398
8238 10:52:46.027067 [TxChooseVref] Worse bit 1, Min win 24, Win sum 420, Final Vref 26
8239 10:52:46.027181
8240 10:52:46.030254 Final TX Range 0 Vref 26
8241 10:52:46.030344
8242 10:52:46.030411 ==
8243 10:52:46.033816 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 10:52:46.037006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 10:52:46.037097 ==
8246 10:52:46.037164
8247 10:52:46.037224
8248 10:52:46.040191 TX Vref Scan disable
8249 10:52:46.046916 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8250 10:52:46.047020 == TX Byte 0 ==
8251 10:52:46.050087 u2DelayCellOfst[0]=11 cells (3 PI)
8252 10:52:46.053815 u2DelayCellOfst[1]=14 cells (4 PI)
8253 10:52:46.056885 u2DelayCellOfst[2]=11 cells (3 PI)
8254 10:52:46.060453 u2DelayCellOfst[3]=11 cells (3 PI)
8255 10:52:46.063369 u2DelayCellOfst[4]=7 cells (2 PI)
8256 10:52:46.066746 u2DelayCellOfst[5]=0 cells (0 PI)
8257 10:52:46.070216 u2DelayCellOfst[6]=18 cells (5 PI)
8258 10:52:46.070307 u2DelayCellOfst[7]=14 cells (4 PI)
8259 10:52:46.076901 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8260 10:52:46.079751 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8261 10:52:46.083736 == TX Byte 1 ==
8262 10:52:46.083883 u2DelayCellOfst[8]=0 cells (0 PI)
8263 10:52:46.086710 u2DelayCellOfst[9]=3 cells (1 PI)
8264 10:52:46.089679 u2DelayCellOfst[10]=11 cells (3 PI)
8265 10:52:46.093029 u2DelayCellOfst[11]=3 cells (1 PI)
8266 10:52:46.096365 u2DelayCellOfst[12]=14 cells (4 PI)
8267 10:52:46.099958 u2DelayCellOfst[13]=14 cells (4 PI)
8268 10:52:46.103394 u2DelayCellOfst[14]=18 cells (5 PI)
8269 10:52:46.107066 u2DelayCellOfst[15]=14 cells (4 PI)
8270 10:52:46.110600 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8271 10:52:46.116332 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8272 10:52:46.116444 DramC Write-DBI on
8273 10:52:46.116536 ==
8274 10:52:46.119246 Dram Type= 6, Freq= 0, CH_0, rank 1
8275 10:52:46.127068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 10:52:46.127185 ==
8277 10:52:46.127255
8278 10:52:46.127316
8279 10:52:46.127374 TX Vref Scan disable
8280 10:52:46.129741 == TX Byte 0 ==
8281 10:52:46.133114 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8282 10:52:46.136502 == TX Byte 1 ==
8283 10:52:46.139824 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8284 10:52:46.142799 DramC Write-DBI off
8285 10:52:46.142890
8286 10:52:46.142956 [DATLAT]
8287 10:52:46.143016 Freq=1600, CH0 RK1
8288 10:52:46.143075
8289 10:52:46.146455 DATLAT Default: 0xf
8290 10:52:46.149537 0, 0xFFFF, sum = 0
8291 10:52:46.149626 1, 0xFFFF, sum = 0
8292 10:52:46.152674 2, 0xFFFF, sum = 0
8293 10:52:46.152762 3, 0xFFFF, sum = 0
8294 10:52:46.156278 4, 0xFFFF, sum = 0
8295 10:52:46.156393 5, 0xFFFF, sum = 0
8296 10:52:46.159466 6, 0xFFFF, sum = 0
8297 10:52:46.159553 7, 0xFFFF, sum = 0
8298 10:52:46.163546 8, 0xFFFF, sum = 0
8299 10:52:46.163633 9, 0xFFFF, sum = 0
8300 10:52:46.166006 10, 0xFFFF, sum = 0
8301 10:52:46.166093 11, 0xFFFF, sum = 0
8302 10:52:46.169295 12, 0xFFFF, sum = 0
8303 10:52:46.169381 13, 0xFFFF, sum = 0
8304 10:52:46.172502 14, 0x0, sum = 1
8305 10:52:46.172624 15, 0x0, sum = 2
8306 10:52:46.175940 16, 0x0, sum = 3
8307 10:52:46.176027 17, 0x0, sum = 4
8308 10:52:46.179491 best_step = 15
8309 10:52:46.179578
8310 10:52:46.179645 ==
8311 10:52:46.182627 Dram Type= 6, Freq= 0, CH_0, rank 1
8312 10:52:46.185747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 10:52:46.185861 ==
8314 10:52:46.189270 RX Vref Scan: 0
8315 10:52:46.189357
8316 10:52:46.189423 RX Vref 0 -> 0, step: 1
8317 10:52:46.189484
8318 10:52:46.192502 RX Delay 11 -> 252, step: 4
8319 10:52:46.199635 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8320 10:52:46.202270 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8321 10:52:46.205414 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8322 10:52:46.208952 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8323 10:52:46.212687 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8324 10:52:46.219039 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8325 10:52:46.222524 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8326 10:52:46.225521 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8327 10:52:46.228775 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8328 10:52:46.232845 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8329 10:52:46.238430 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8330 10:52:46.241782 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8331 10:52:46.244915 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8332 10:52:46.248293 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8333 10:52:46.255661 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8334 10:52:46.258368 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8335 10:52:46.258462 ==
8336 10:52:46.261546 Dram Type= 6, Freq= 0, CH_0, rank 1
8337 10:52:46.265260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 10:52:46.265352 ==
8339 10:52:46.268396 DQS Delay:
8340 10:52:46.268481 DQS0 = 0, DQS1 = 0
8341 10:52:46.268554 DQM Delay:
8342 10:52:46.271901 DQM0 = 130, DQM1 = 125
8343 10:52:46.271986 DQ Delay:
8344 10:52:46.274741 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126
8345 10:52:46.278603 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8346 10:52:46.281270 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8347 10:52:46.288255 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8348 10:52:46.288394
8349 10:52:46.288492
8350 10:52:46.288605
8351 10:52:46.291328 [DramC_TX_OE_Calibration] TA2
8352 10:52:46.294480 Original DQ_B0 (3 6) =30, OEN = 27
8353 10:52:46.294570 Original DQ_B1 (3 6) =30, OEN = 27
8354 10:52:46.298029 24, 0x0, End_B0=24 End_B1=24
8355 10:52:46.301580 25, 0x0, End_B0=25 End_B1=25
8356 10:52:46.304611 26, 0x0, End_B0=26 End_B1=26
8357 10:52:46.307522 27, 0x0, End_B0=27 End_B1=27
8358 10:52:46.307612 28, 0x0, End_B0=28 End_B1=28
8359 10:52:46.311208 29, 0x0, End_B0=29 End_B1=29
8360 10:52:46.314354 30, 0x0, End_B0=30 End_B1=30
8361 10:52:46.318232 31, 0x4141, End_B0=30 End_B1=30
8362 10:52:46.320974 Byte0 end_step=30 best_step=27
8363 10:52:46.324457 Byte1 end_step=30 best_step=27
8364 10:52:46.324570 Byte0 TX OE(2T, 0.5T) = (3, 3)
8365 10:52:46.327502 Byte1 TX OE(2T, 0.5T) = (3, 3)
8366 10:52:46.327586
8367 10:52:46.327650
8368 10:52:46.337260 [DQSOSCAuto] RK1, (LSB)MR18= 0x1cff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8369 10:52:46.340774 CH0 RK1: MR19=302, MR18=1CFF
8370 10:52:46.344417 CH0_RK1: MR19=0x302, MR18=0x1CFF, DQSOSC=395, MR23=63, INC=23, DEC=15
8371 10:52:46.347531 [RxdqsGatingPostProcess] freq 1600
8372 10:52:46.353958 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8373 10:52:46.357389 best DQS0 dly(2T, 0.5T) = (1, 1)
8374 10:52:46.360738 best DQS1 dly(2T, 0.5T) = (1, 1)
8375 10:52:46.363861 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8376 10:52:46.367159 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8377 10:52:46.370458 best DQS0 dly(2T, 0.5T) = (1, 1)
8378 10:52:46.374099 best DQS1 dly(2T, 0.5T) = (1, 1)
8379 10:52:46.376866 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8380 10:52:46.376954 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8381 10:52:46.380147 Pre-setting of DQS Precalculation
8382 10:52:46.387103 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8383 10:52:46.387212 ==
8384 10:52:46.390090 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 10:52:46.393821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 10:52:46.393912 ==
8387 10:52:46.400167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8388 10:52:46.403482 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8389 10:52:46.407060 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8390 10:52:46.413389 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8391 10:52:46.423775 [CA 0] Center 41 (12~71) winsize 60
8392 10:52:46.426416 [CA 1] Center 42 (13~72) winsize 60
8393 10:52:46.429550 [CA 2] Center 36 (7~66) winsize 60
8394 10:52:46.433037 [CA 3] Center 35 (6~65) winsize 60
8395 10:52:46.436123 [CA 4] Center 37 (8~66) winsize 59
8396 10:52:46.439639 [CA 5] Center 36 (7~66) winsize 60
8397 10:52:46.439734
8398 10:52:46.443195 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8399 10:52:46.443283
8400 10:52:46.446264 [CATrainingPosCal] consider 1 rank data
8401 10:52:46.449479 u2DelayCellTimex100 = 262/100 ps
8402 10:52:46.456446 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8403 10:52:46.459086 CA1 delay=42 (13~72),Diff = 7 PI (26 cell)
8404 10:52:46.463199 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8405 10:52:46.466171 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8406 10:52:46.469780 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
8407 10:52:46.472272 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8408 10:52:46.472366
8409 10:52:46.475530 CA PerBit enable=1, Macro0, CA PI delay=35
8410 10:52:46.475614
8411 10:52:46.479375 [CBTSetCACLKResult] CA Dly = 35
8412 10:52:46.482558 CS Dly: 9 (0~40)
8413 10:52:46.485617 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8414 10:52:46.488743 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8415 10:52:46.488838 ==
8416 10:52:46.492201 Dram Type= 6, Freq= 0, CH_1, rank 1
8417 10:52:46.499107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 10:52:46.499214 ==
8419 10:52:46.502377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8420 10:52:46.509043 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8421 10:52:46.512463 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8422 10:52:46.519024 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8423 10:52:46.526044 [CA 0] Center 42 (13~72) winsize 60
8424 10:52:46.529589 [CA 1] Center 42 (13~72) winsize 60
8425 10:52:46.533253 [CA 2] Center 37 (8~67) winsize 60
8426 10:52:46.535857 [CA 3] Center 37 (7~67) winsize 61
8427 10:52:46.539104 [CA 4] Center 38 (9~67) winsize 59
8428 10:52:46.542599 [CA 5] Center 37 (8~67) winsize 60
8429 10:52:46.542690
8430 10:52:46.546161 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8431 10:52:46.546252
8432 10:52:46.549121 [CATrainingPosCal] consider 2 rank data
8433 10:52:46.552898 u2DelayCellTimex100 = 262/100 ps
8434 10:52:46.559354 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8435 10:52:46.562414 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8436 10:52:46.565583 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8437 10:52:46.569193 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8438 10:52:46.572464 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8439 10:52:46.575577 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8440 10:52:46.575665
8441 10:52:46.579038 CA PerBit enable=1, Macro0, CA PI delay=36
8442 10:52:46.579123
8443 10:52:46.582528 [CBTSetCACLKResult] CA Dly = 36
8444 10:52:46.585732 CS Dly: 10 (0~43)
8445 10:52:46.589150 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8446 10:52:46.592166 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8447 10:52:46.592259
8448 10:52:46.595623 ----->DramcWriteLeveling(PI) begin...
8449 10:52:46.595713 ==
8450 10:52:46.598649 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 10:52:46.605240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 10:52:46.605345 ==
8453 10:52:46.608740 Write leveling (Byte 0): 26 => 26
8454 10:52:46.611984 Write leveling (Byte 1): 27 => 27
8455 10:52:46.612073 DramcWriteLeveling(PI) end<-----
8456 10:52:46.615508
8457 10:52:46.615597 ==
8458 10:52:46.618357 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 10:52:46.621725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 10:52:46.621817 ==
8461 10:52:46.625569 [Gating] SW mode calibration
8462 10:52:46.631705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8463 10:52:46.638064 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8464 10:52:46.641405 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 10:52:46.644653 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 10:52:46.651541 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 10:52:46.654481 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8468 10:52:46.658066 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 10:52:46.664529 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 10:52:46.667671 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 10:52:46.671187 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 10:52:46.677355 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 10:52:46.681094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 10:52:46.684541 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8475 10:52:46.690782 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8476 10:52:46.695040 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 10:52:46.697195 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 10:52:46.704337 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 10:52:46.707056 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 10:52:46.710498 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 10:52:46.717068 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 10:52:46.720368 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
8483 10:52:46.724454 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8484 10:52:46.730793 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 10:52:46.733712 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 10:52:46.736925 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 10:52:46.743535 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 10:52:46.747088 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 10:52:46.750575 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 10:52:46.756863 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 10:52:46.759916 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8492 10:52:46.763565 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 10:52:46.769753 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 10:52:46.773209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 10:52:46.776758 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 10:52:46.779913 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 10:52:46.786492 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 10:52:46.789872 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 10:52:46.793491 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 10:52:46.799862 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 10:52:46.803216 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 10:52:46.806821 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 10:52:46.813188 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 10:52:46.816627 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 10:52:46.819353 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 10:52:46.826298 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8507 10:52:46.829461 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8508 10:52:46.833143 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8509 10:52:46.836165 Total UI for P1: 0, mck2ui 16
8510 10:52:46.839182 best dqsien dly found for B0: ( 1, 9, 10)
8511 10:52:46.845979 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 10:52:46.849125 Total UI for P1: 0, mck2ui 16
8513 10:52:46.852770 best dqsien dly found for B1: ( 1, 9, 12)
8514 10:52:46.855835 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8515 10:52:46.859095 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8516 10:52:46.859188
8517 10:52:46.862795 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8518 10:52:46.865895 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8519 10:52:46.869051 [Gating] SW calibration Done
8520 10:52:46.869138 ==
8521 10:52:46.872486 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 10:52:46.875527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 10:52:46.875615 ==
8524 10:52:46.878796 RX Vref Scan: 0
8525 10:52:46.878883
8526 10:52:46.882191 RX Vref 0 -> 0, step: 1
8527 10:52:46.882278
8528 10:52:46.882344 RX Delay 0 -> 252, step: 8
8529 10:52:46.889033 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8530 10:52:46.892226 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8531 10:52:46.895455 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8532 10:52:46.898496 iDelay=208, Bit 3, Center 135 (88 ~ 183) 96
8533 10:52:46.902175 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8534 10:52:46.908464 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8535 10:52:46.912156 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8536 10:52:46.915324 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8537 10:52:46.918925 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8538 10:52:46.921655 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8539 10:52:46.929368 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8540 10:52:46.931653 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8541 10:52:46.934733 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8542 10:52:46.938327 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8543 10:52:46.945052 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8544 10:52:46.948654 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8545 10:52:46.948751 ==
8546 10:52:46.951246 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 10:52:46.954653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 10:52:46.954743 ==
8549 10:52:46.958540 DQS Delay:
8550 10:52:46.958628 DQS0 = 0, DQS1 = 0
8551 10:52:46.958695 DQM Delay:
8552 10:52:46.961288 DQM0 = 137, DQM1 = 130
8553 10:52:46.961373 DQ Delay:
8554 10:52:46.964624 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8555 10:52:46.968013 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8556 10:52:46.971803 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8557 10:52:46.977894 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8558 10:52:46.977997
8559 10:52:46.978067
8560 10:52:46.978127 ==
8561 10:52:46.981445 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 10:52:46.984414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 10:52:46.984506 ==
8564 10:52:46.984620
8565 10:52:46.984682
8566 10:52:46.987852 TX Vref Scan disable
8567 10:52:46.987958 == TX Byte 0 ==
8568 10:52:46.994741 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8569 10:52:46.998085 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8570 10:52:46.998181 == TX Byte 1 ==
8571 10:52:47.004384 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8572 10:52:47.007591 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8573 10:52:47.007685 ==
8574 10:52:47.011217 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 10:52:47.014330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 10:52:47.014420 ==
8577 10:52:47.028210
8578 10:52:47.031116 TX Vref early break, caculate TX vref
8579 10:52:47.034555 TX Vref=16, minBit 0, minWin=23, winSum=380
8580 10:52:47.038362 TX Vref=18, minBit 0, minWin=23, winSum=393
8581 10:52:47.041314 TX Vref=20, minBit 5, minWin=24, winSum=400
8582 10:52:47.044849 TX Vref=22, minBit 0, minWin=25, winSum=410
8583 10:52:47.047539 TX Vref=24, minBit 0, minWin=24, winSum=415
8584 10:52:47.055053 TX Vref=26, minBit 0, minWin=25, winSum=421
8585 10:52:47.057678 TX Vref=28, minBit 5, minWin=25, winSum=422
8586 10:52:47.061357 TX Vref=30, minBit 1, minWin=25, winSum=418
8587 10:52:47.064505 TX Vref=32, minBit 0, minWin=24, winSum=406
8588 10:52:47.067970 TX Vref=34, minBit 5, minWin=23, winSum=394
8589 10:52:47.074387 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 28
8590 10:52:47.074495
8591 10:52:47.077505 Final TX Range 0 Vref 28
8592 10:52:47.077593
8593 10:52:47.077659 ==
8594 10:52:47.080711 Dram Type= 6, Freq= 0, CH_1, rank 0
8595 10:52:47.084230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8596 10:52:47.084321 ==
8597 10:52:47.084387
8598 10:52:47.084447
8599 10:52:47.087831 TX Vref Scan disable
8600 10:52:47.094479 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8601 10:52:47.094592 == TX Byte 0 ==
8602 10:52:47.097523 u2DelayCellOfst[0]=18 cells (5 PI)
8603 10:52:47.101071 u2DelayCellOfst[1]=14 cells (4 PI)
8604 10:52:47.104246 u2DelayCellOfst[2]=0 cells (0 PI)
8605 10:52:47.107569 u2DelayCellOfst[3]=7 cells (2 PI)
8606 10:52:47.110600 u2DelayCellOfst[4]=7 cells (2 PI)
8607 10:52:47.113907 u2DelayCellOfst[5]=22 cells (6 PI)
8608 10:52:47.117403 u2DelayCellOfst[6]=22 cells (6 PI)
8609 10:52:47.120659 u2DelayCellOfst[7]=7 cells (2 PI)
8610 10:52:47.123806 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8611 10:52:47.127017 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8612 10:52:47.130336 == TX Byte 1 ==
8613 10:52:47.134247 u2DelayCellOfst[8]=0 cells (0 PI)
8614 10:52:47.134344 u2DelayCellOfst[9]=3 cells (1 PI)
8615 10:52:47.136994 u2DelayCellOfst[10]=11 cells (3 PI)
8616 10:52:47.140024 u2DelayCellOfst[11]=7 cells (2 PI)
8617 10:52:47.143439 u2DelayCellOfst[12]=14 cells (4 PI)
8618 10:52:47.147255 u2DelayCellOfst[13]=18 cells (5 PI)
8619 10:52:47.150115 u2DelayCellOfst[14]=18 cells (5 PI)
8620 10:52:47.153450 u2DelayCellOfst[15]=18 cells (5 PI)
8621 10:52:47.160384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8622 10:52:47.163271 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8623 10:52:47.163369 DramC Write-DBI on
8624 10:52:47.163436 ==
8625 10:52:47.166674 Dram Type= 6, Freq= 0, CH_1, rank 0
8626 10:52:47.173074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8627 10:52:47.173180 ==
8628 10:52:47.173248
8629 10:52:47.173309
8630 10:52:47.173367 TX Vref Scan disable
8631 10:52:47.177329 == TX Byte 0 ==
8632 10:52:47.181122 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8633 10:52:47.184130 == TX Byte 1 ==
8634 10:52:47.187368 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8635 10:52:47.190459 DramC Write-DBI off
8636 10:52:47.190551
8637 10:52:47.190618 [DATLAT]
8638 10:52:47.190679 Freq=1600, CH1 RK0
8639 10:52:47.190739
8640 10:52:47.193969 DATLAT Default: 0xf
8641 10:52:47.197454 0, 0xFFFF, sum = 0
8642 10:52:47.197546 1, 0xFFFF, sum = 0
8643 10:52:47.200436 2, 0xFFFF, sum = 0
8644 10:52:47.200581 3, 0xFFFF, sum = 0
8645 10:52:47.203575 4, 0xFFFF, sum = 0
8646 10:52:47.203663 5, 0xFFFF, sum = 0
8647 10:52:47.207372 6, 0xFFFF, sum = 0
8648 10:52:47.207489 7, 0xFFFF, sum = 0
8649 10:52:47.210135 8, 0xFFFF, sum = 0
8650 10:52:47.210222 9, 0xFFFF, sum = 0
8651 10:52:47.213810 10, 0xFFFF, sum = 0
8652 10:52:47.213897 11, 0xFFFF, sum = 0
8653 10:52:47.216582 12, 0xFFFF, sum = 0
8654 10:52:47.216670 13, 0xFFFF, sum = 0
8655 10:52:47.220080 14, 0x0, sum = 1
8656 10:52:47.220168 15, 0x0, sum = 2
8657 10:52:47.223210 16, 0x0, sum = 3
8658 10:52:47.223297 17, 0x0, sum = 4
8659 10:52:47.226524 best_step = 15
8660 10:52:47.226610
8661 10:52:47.226676 ==
8662 10:52:47.229629 Dram Type= 6, Freq= 0, CH_1, rank 0
8663 10:52:47.233089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8664 10:52:47.233179 ==
8665 10:52:47.236868 RX Vref Scan: 1
8666 10:52:47.236956
8667 10:52:47.237022 Set Vref Range= 24 -> 127
8668 10:52:47.239906
8669 10:52:47.239990 RX Vref 24 -> 127, step: 1
8670 10:52:47.240056
8671 10:52:47.242978 RX Delay 11 -> 252, step: 4
8672 10:52:47.243064
8673 10:52:47.246522 Set Vref, RX VrefLevel [Byte0]: 24
8674 10:52:47.249487 [Byte1]: 24
8675 10:52:47.249575
8676 10:52:47.252821 Set Vref, RX VrefLevel [Byte0]: 25
8677 10:52:47.256194 [Byte1]: 25
8678 10:52:47.260047
8679 10:52:47.260136 Set Vref, RX VrefLevel [Byte0]: 26
8680 10:52:47.266516 [Byte1]: 26
8681 10:52:47.266608
8682 10:52:47.269962 Set Vref, RX VrefLevel [Byte0]: 27
8683 10:52:47.273351 [Byte1]: 27
8684 10:52:47.273440
8685 10:52:47.276554 Set Vref, RX VrefLevel [Byte0]: 28
8686 10:52:47.279943 [Byte1]: 28
8687 10:52:47.280029
8688 10:52:47.283174 Set Vref, RX VrefLevel [Byte0]: 29
8689 10:52:47.286581 [Byte1]: 29
8690 10:52:47.291041
8691 10:52:47.291138 Set Vref, RX VrefLevel [Byte0]: 30
8692 10:52:47.294370 [Byte1]: 30
8693 10:52:47.298118
8694 10:52:47.298209 Set Vref, RX VrefLevel [Byte0]: 31
8695 10:52:47.301532 [Byte1]: 31
8696 10:52:47.305736
8697 10:52:47.305823 Set Vref, RX VrefLevel [Byte0]: 32
8698 10:52:47.309844 [Byte1]: 32
8699 10:52:47.313649
8700 10:52:47.313740 Set Vref, RX VrefLevel [Byte0]: 33
8701 10:52:47.316679 [Byte1]: 33
8702 10:52:47.320839
8703 10:52:47.320930 Set Vref, RX VrefLevel [Byte0]: 34
8704 10:52:47.324023 [Byte1]: 34
8705 10:52:47.328463
8706 10:52:47.328575 Set Vref, RX VrefLevel [Byte0]: 35
8707 10:52:47.332120 [Byte1]: 35
8708 10:52:47.336265
8709 10:52:47.336355 Set Vref, RX VrefLevel [Byte0]: 36
8710 10:52:47.339485 [Byte1]: 36
8711 10:52:47.344128
8712 10:52:47.344219 Set Vref, RX VrefLevel [Byte0]: 37
8713 10:52:47.347689 [Byte1]: 37
8714 10:52:47.351716
8715 10:52:47.351804 Set Vref, RX VrefLevel [Byte0]: 38
8716 10:52:47.354759 [Byte1]: 38
8717 10:52:47.359373
8718 10:52:47.359462 Set Vref, RX VrefLevel [Byte0]: 39
8719 10:52:47.362300 [Byte1]: 39
8720 10:52:47.366688
8721 10:52:47.366779 Set Vref, RX VrefLevel [Byte0]: 40
8722 10:52:47.369774 [Byte1]: 40
8723 10:52:47.374247
8724 10:52:47.374342 Set Vref, RX VrefLevel [Byte0]: 41
8725 10:52:47.377439 [Byte1]: 41
8726 10:52:47.381839
8727 10:52:47.381928 Set Vref, RX VrefLevel [Byte0]: 42
8728 10:52:47.385252 [Byte1]: 42
8729 10:52:47.389364
8730 10:52:47.389460 Set Vref, RX VrefLevel [Byte0]: 43
8731 10:52:47.392842 [Byte1]: 43
8732 10:52:47.397111
8733 10:52:47.397202 Set Vref, RX VrefLevel [Byte0]: 44
8734 10:52:47.400489 [Byte1]: 44
8735 10:52:47.404492
8736 10:52:47.404623 Set Vref, RX VrefLevel [Byte0]: 45
8737 10:52:47.408455 [Byte1]: 45
8738 10:52:47.412686
8739 10:52:47.412777 Set Vref, RX VrefLevel [Byte0]: 46
8740 10:52:47.416026 [Byte1]: 46
8741 10:52:47.420379
8742 10:52:47.420498 Set Vref, RX VrefLevel [Byte0]: 47
8743 10:52:47.423636 [Byte1]: 47
8744 10:52:47.427782
8745 10:52:47.427875 Set Vref, RX VrefLevel [Byte0]: 48
8746 10:52:47.431148 [Byte1]: 48
8747 10:52:47.435648
8748 10:52:47.435741 Set Vref, RX VrefLevel [Byte0]: 49
8749 10:52:47.438589 [Byte1]: 49
8750 10:52:47.442678
8751 10:52:47.442771 Set Vref, RX VrefLevel [Byte0]: 50
8752 10:52:47.446355 [Byte1]: 50
8753 10:52:47.450536
8754 10:52:47.450629 Set Vref, RX VrefLevel [Byte0]: 51
8755 10:52:47.453704 [Byte1]: 51
8756 10:52:47.458050
8757 10:52:47.458143 Set Vref, RX VrefLevel [Byte0]: 52
8758 10:52:47.461434 [Byte1]: 52
8759 10:52:47.465527
8760 10:52:47.465617 Set Vref, RX VrefLevel [Byte0]: 53
8761 10:52:47.469465 [Byte1]: 53
8762 10:52:47.473505
8763 10:52:47.473598 Set Vref, RX VrefLevel [Byte0]: 54
8764 10:52:47.476996 [Byte1]: 54
8765 10:52:47.480688
8766 10:52:47.480779 Set Vref, RX VrefLevel [Byte0]: 55
8767 10:52:47.484212 [Byte1]: 55
8768 10:52:47.488628
8769 10:52:47.488724 Set Vref, RX VrefLevel [Byte0]: 56
8770 10:52:47.491812 [Byte1]: 56
8771 10:52:47.496234
8772 10:52:47.496329 Set Vref, RX VrefLevel [Byte0]: 57
8773 10:52:47.499273 [Byte1]: 57
8774 10:52:47.503774
8775 10:52:47.503866 Set Vref, RX VrefLevel [Byte0]: 58
8776 10:52:47.506900 [Byte1]: 58
8777 10:52:47.511466
8778 10:52:47.511559 Set Vref, RX VrefLevel [Byte0]: 59
8779 10:52:47.514453 [Byte1]: 59
8780 10:52:47.518981
8781 10:52:47.519074 Set Vref, RX VrefLevel [Byte0]: 60
8782 10:52:47.522318 [Byte1]: 60
8783 10:52:47.526623
8784 10:52:47.526718 Set Vref, RX VrefLevel [Byte0]: 61
8785 10:52:47.530213 [Byte1]: 61
8786 10:52:47.534461
8787 10:52:47.534559 Set Vref, RX VrefLevel [Byte0]: 62
8788 10:52:47.537183 [Byte1]: 62
8789 10:52:47.542904
8790 10:52:47.543006 Set Vref, RX VrefLevel [Byte0]: 63
8791 10:52:47.545277 [Byte1]: 63
8792 10:52:47.549213
8793 10:52:47.549305 Set Vref, RX VrefLevel [Byte0]: 64
8794 10:52:47.552482 [Byte1]: 64
8795 10:52:47.557040
8796 10:52:47.557136 Set Vref, RX VrefLevel [Byte0]: 65
8797 10:52:47.563229 [Byte1]: 65
8798 10:52:47.563327
8799 10:52:47.566681 Set Vref, RX VrefLevel [Byte0]: 66
8800 10:52:47.570284 [Byte1]: 66
8801 10:52:47.570378
8802 10:52:47.573434 Set Vref, RX VrefLevel [Byte0]: 67
8803 10:52:47.577580 [Byte1]: 67
8804 10:52:47.579705
8805 10:52:47.579795 Set Vref, RX VrefLevel [Byte0]: 68
8806 10:52:47.583336 [Byte1]: 68
8807 10:52:47.587662
8808 10:52:47.587761 Set Vref, RX VrefLevel [Byte0]: 69
8809 10:52:47.590748 [Byte1]: 69
8810 10:52:47.595320
8811 10:52:47.595415 Set Vref, RX VrefLevel [Byte0]: 70
8812 10:52:47.598201 [Byte1]: 70
8813 10:52:47.602904
8814 10:52:47.602997 Set Vref, RX VrefLevel [Byte0]: 71
8815 10:52:47.606384 [Byte1]: 71
8816 10:52:47.610227
8817 10:52:47.610319 Set Vref, RX VrefLevel [Byte0]: 72
8818 10:52:47.613966 [Byte1]: 72
8819 10:52:47.617792
8820 10:52:47.617883 Set Vref, RX VrefLevel [Byte0]: 73
8821 10:52:47.621329 [Byte1]: 73
8822 10:52:47.625752
8823 10:52:47.625845 Final RX Vref Byte 0 = 53 to rank0
8824 10:52:47.628922 Final RX Vref Byte 1 = 58 to rank0
8825 10:52:47.632746 Final RX Vref Byte 0 = 53 to rank1
8826 10:52:47.635508 Final RX Vref Byte 1 = 58 to rank1==
8827 10:52:47.638603 Dram Type= 6, Freq= 0, CH_1, rank 0
8828 10:52:47.645187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 10:52:47.645294 ==
8830 10:52:47.645364 DQS Delay:
8831 10:52:47.648453 DQS0 = 0, DQS1 = 0
8832 10:52:47.648579 DQM Delay:
8833 10:52:47.648647 DQM0 = 134, DQM1 = 129
8834 10:52:47.651941 DQ Delay:
8835 10:52:47.656264 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8836 10:52:47.658521 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8837 10:52:47.661885 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8838 10:52:47.665124 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8839 10:52:47.665217
8840 10:52:47.665284
8841 10:52:47.665343
8842 10:52:47.668480 [DramC_TX_OE_Calibration] TA2
8843 10:52:47.672414 Original DQ_B0 (3 6) =30, OEN = 27
8844 10:52:47.675043 Original DQ_B1 (3 6) =30, OEN = 27
8845 10:52:47.678246 24, 0x0, End_B0=24 End_B1=24
8846 10:52:47.678339 25, 0x0, End_B0=25 End_B1=25
8847 10:52:47.681858 26, 0x0, End_B0=26 End_B1=26
8848 10:52:47.685076 27, 0x0, End_B0=27 End_B1=27
8849 10:52:47.688179 28, 0x0, End_B0=28 End_B1=28
8850 10:52:47.691592 29, 0x0, End_B0=29 End_B1=29
8851 10:52:47.691687 30, 0x0, End_B0=30 End_B1=30
8852 10:52:47.694869 31, 0x4141, End_B0=30 End_B1=30
8853 10:52:47.698117 Byte0 end_step=30 best_step=27
8854 10:52:47.701662 Byte1 end_step=30 best_step=27
8855 10:52:47.704878 Byte0 TX OE(2T, 0.5T) = (3, 3)
8856 10:52:47.707957 Byte1 TX OE(2T, 0.5T) = (3, 3)
8857 10:52:47.708046
8858 10:52:47.708113
8859 10:52:47.714809 [DQSOSCAuto] RK0, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8860 10:52:47.718127 CH1 RK0: MR19=303, MR18=160C
8861 10:52:47.724743 CH1_RK0: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8862 10:52:47.724851
8863 10:52:47.728032 ----->DramcWriteLeveling(PI) begin...
8864 10:52:47.728120 ==
8865 10:52:47.730951 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 10:52:47.734488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 10:52:47.734578 ==
8868 10:52:47.738009 Write leveling (Byte 0): 23 => 23
8869 10:52:47.741115 Write leveling (Byte 1): 27 => 27
8870 10:52:47.744509 DramcWriteLeveling(PI) end<-----
8871 10:52:47.744633
8872 10:52:47.744700 ==
8873 10:52:47.747984 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 10:52:47.750706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 10:52:47.754518 ==
8876 10:52:47.754609 [Gating] SW mode calibration
8877 10:52:47.764132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8878 10:52:47.767251 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8879 10:52:47.771158 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 10:52:47.776911 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 10:52:47.780993 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8882 10:52:47.783833 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8883 10:52:47.790527 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 10:52:47.793554 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8885 10:52:47.797229 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8886 10:52:47.804022 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8887 10:52:47.806896 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8888 10:52:47.809926 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8889 10:52:47.816675 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8890 10:52:47.820296 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8891 10:52:47.823099 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 10:52:47.829857 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8893 10:52:47.833213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8894 10:52:47.836227 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8895 10:52:47.843496 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8896 10:52:47.846018 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8897 10:52:47.849429 1 6 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8898 10:52:47.856786 1 6 12 | B1->B0 | 4646 3333 | 0 1 | (0 0) (0 0)
8899 10:52:47.859420 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 10:52:47.862529 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 10:52:47.869980 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8902 10:52:47.872520 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8903 10:52:47.875940 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8904 10:52:47.883015 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8905 10:52:47.886084 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8906 10:52:47.889412 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8907 10:52:47.896088 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8908 10:52:47.899154 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 10:52:47.902707 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 10:52:47.909145 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 10:52:47.912415 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 10:52:47.915766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 10:52:47.922387 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 10:52:47.925539 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 10:52:47.929227 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 10:52:47.935439 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 10:52:47.938958 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 10:52:47.942611 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8919 10:52:47.948730 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8920 10:52:47.952180 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8921 10:52:47.955636 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8922 10:52:47.961934 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8923 10:52:47.965437 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8924 10:52:47.968466 Total UI for P1: 0, mck2ui 16
8925 10:52:47.971906 best dqsien dly found for B0: ( 1, 9, 10)
8926 10:52:47.975604 Total UI for P1: 0, mck2ui 16
8927 10:52:47.978464 best dqsien dly found for B1: ( 1, 9, 10)
8928 10:52:47.982259 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8929 10:52:47.985201 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8930 10:52:47.985293
8931 10:52:47.988912 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8932 10:52:47.991526 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8933 10:52:47.995065 [Gating] SW calibration Done
8934 10:52:47.995163 ==
8935 10:52:47.998726 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 10:52:48.004868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 10:52:48.004973 ==
8938 10:52:48.005041 RX Vref Scan: 0
8939 10:52:48.005102
8940 10:52:48.008291 RX Vref 0 -> 0, step: 1
8941 10:52:48.008403
8942 10:52:48.011493 RX Delay 0 -> 252, step: 8
8943 10:52:48.014759 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8944 10:52:48.018732 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8945 10:52:48.021252 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8946 10:52:48.024652 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8947 10:52:48.031831 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8948 10:52:48.034451 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8949 10:52:48.038381 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8950 10:52:48.041146 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8951 10:52:48.044394 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8952 10:52:48.050949 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8953 10:52:48.054043 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8954 10:52:48.058226 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8955 10:52:48.061049 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8956 10:52:48.067283 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8957 10:52:48.070942 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8958 10:52:48.074244 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8959 10:52:48.074338 ==
8960 10:52:48.077458 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 10:52:48.080410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 10:52:48.083787 ==
8963 10:52:48.083881 DQS Delay:
8964 10:52:48.083948 DQS0 = 0, DQS1 = 0
8965 10:52:48.087348 DQM Delay:
8966 10:52:48.087460 DQM0 = 136, DQM1 = 128
8967 10:52:48.090408 DQ Delay:
8968 10:52:48.093781 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8969 10:52:48.097452 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8970 10:52:48.100635 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8971 10:52:48.103757 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8972 10:52:48.103850
8973 10:52:48.103918
8974 10:52:48.103980 ==
8975 10:52:48.106966 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 10:52:48.110451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 10:52:48.110544 ==
8978 10:52:48.113321
8979 10:52:48.113407
8980 10:52:48.113473 TX Vref Scan disable
8981 10:52:48.116921 == TX Byte 0 ==
8982 10:52:48.120188 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8983 10:52:48.123203 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8984 10:52:48.126882 == TX Byte 1 ==
8985 10:52:48.130033 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8986 10:52:48.133614 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8987 10:52:48.136444 ==
8988 10:52:48.136563 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 10:52:48.143028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 10:52:48.143129 ==
8991 10:52:48.156252
8992 10:52:48.159604 TX Vref early break, caculate TX vref
8993 10:52:48.163143 TX Vref=16, minBit 1, minWin=22, winSum=379
8994 10:52:48.166457 TX Vref=18, minBit 0, minWin=22, winSum=389
8995 10:52:48.169748 TX Vref=20, minBit 1, minWin=23, winSum=398
8996 10:52:48.173006 TX Vref=22, minBit 0, minWin=23, winSum=402
8997 10:52:48.176351 TX Vref=24, minBit 0, minWin=25, winSum=414
8998 10:52:48.183188 TX Vref=26, minBit 0, minWin=25, winSum=416
8999 10:52:48.185841 TX Vref=28, minBit 0, minWin=24, winSum=416
9000 10:52:48.189263 TX Vref=30, minBit 0, minWin=23, winSum=409
9001 10:52:48.192991 TX Vref=32, minBit 0, minWin=23, winSum=402
9002 10:52:48.196415 TX Vref=34, minBit 0, minWin=23, winSum=396
9003 10:52:48.199485 TX Vref=36, minBit 0, minWin=22, winSum=385
9004 10:52:48.206018 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
9005 10:52:48.206126
9006 10:52:48.209021 Final TX Range 0 Vref 26
9007 10:52:48.209138
9008 10:52:48.209219 ==
9009 10:52:48.212771 Dram Type= 6, Freq= 0, CH_1, rank 1
9010 10:52:48.215753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9011 10:52:48.215843 ==
9012 10:52:48.215910
9013 10:52:48.219082
9014 10:52:48.219170 TX Vref Scan disable
9015 10:52:48.226380 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9016 10:52:48.226483 == TX Byte 0 ==
9017 10:52:48.228912 u2DelayCellOfst[0]=18 cells (5 PI)
9018 10:52:48.232277 u2DelayCellOfst[1]=11 cells (3 PI)
9019 10:52:48.235527 u2DelayCellOfst[2]=0 cells (0 PI)
9020 10:52:48.238688 u2DelayCellOfst[3]=3 cells (1 PI)
9021 10:52:48.242695 u2DelayCellOfst[4]=7 cells (2 PI)
9022 10:52:48.245588 u2DelayCellOfst[5]=18 cells (5 PI)
9023 10:52:48.248852 u2DelayCellOfst[6]=18 cells (5 PI)
9024 10:52:48.252209 u2DelayCellOfst[7]=3 cells (1 PI)
9025 10:52:48.255260 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9026 10:52:48.259224 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9027 10:52:48.261806 == TX Byte 1 ==
9028 10:52:48.265328 u2DelayCellOfst[8]=0 cells (0 PI)
9029 10:52:48.268432 u2DelayCellOfst[9]=3 cells (1 PI)
9030 10:52:48.272152 u2DelayCellOfst[10]=14 cells (4 PI)
9031 10:52:48.275005 u2DelayCellOfst[11]=7 cells (2 PI)
9032 10:52:48.278453 u2DelayCellOfst[12]=14 cells (4 PI)
9033 10:52:48.278541 u2DelayCellOfst[13]=14 cells (4 PI)
9034 10:52:48.281754 u2DelayCellOfst[14]=18 cells (5 PI)
9035 10:52:48.286007 u2DelayCellOfst[15]=18 cells (5 PI)
9036 10:52:48.292158 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9037 10:52:48.295672 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9038 10:52:48.295774 DramC Write-DBI on
9039 10:52:48.298883 ==
9040 10:52:48.301956 Dram Type= 6, Freq= 0, CH_1, rank 1
9041 10:52:48.304866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9042 10:52:48.304955 ==
9043 10:52:48.305020
9044 10:52:48.305078
9045 10:52:48.308490 TX Vref Scan disable
9046 10:52:48.308627 == TX Byte 0 ==
9047 10:52:48.315104 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9048 10:52:48.315204 == TX Byte 1 ==
9049 10:52:48.317995 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9050 10:52:48.321177 DramC Write-DBI off
9051 10:52:48.321266
9052 10:52:48.321331 [DATLAT]
9053 10:52:48.325036 Freq=1600, CH1 RK1
9054 10:52:48.325148
9055 10:52:48.325227 DATLAT Default: 0xf
9056 10:52:48.327905 0, 0xFFFF, sum = 0
9057 10:52:48.327990 1, 0xFFFF, sum = 0
9058 10:52:48.331696 2, 0xFFFF, sum = 0
9059 10:52:48.331782 3, 0xFFFF, sum = 0
9060 10:52:48.334399 4, 0xFFFF, sum = 0
9061 10:52:48.338118 5, 0xFFFF, sum = 0
9062 10:52:48.338206 6, 0xFFFF, sum = 0
9063 10:52:48.341206 7, 0xFFFF, sum = 0
9064 10:52:48.341292 8, 0xFFFF, sum = 0
9065 10:52:48.344635 9, 0xFFFF, sum = 0
9066 10:52:48.344724 10, 0xFFFF, sum = 0
9067 10:52:48.347626 11, 0xFFFF, sum = 0
9068 10:52:48.347714 12, 0xFFFF, sum = 0
9069 10:52:48.350956 13, 0xFFFF, sum = 0
9070 10:52:48.351044 14, 0x0, sum = 1
9071 10:52:48.354340 15, 0x0, sum = 2
9072 10:52:48.354429 16, 0x0, sum = 3
9073 10:52:48.357641 17, 0x0, sum = 4
9074 10:52:48.357728 best_step = 15
9075 10:52:48.357793
9076 10:52:48.357876 ==
9077 10:52:48.361183 Dram Type= 6, Freq= 0, CH_1, rank 1
9078 10:52:48.367645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9079 10:52:48.367748 ==
9080 10:52:48.367817 RX Vref Scan: 0
9081 10:52:48.367879
9082 10:52:48.370895 RX Vref 0 -> 0, step: 1
9083 10:52:48.370980
9084 10:52:48.374205 RX Delay 11 -> 252, step: 4
9085 10:52:48.377112 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9086 10:52:48.380713 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9087 10:52:48.383755 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9088 10:52:48.390507 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9089 10:52:48.393655 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9090 10:52:48.396953 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9091 10:52:48.400422 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9092 10:52:48.404202 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9093 10:52:48.410126 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9094 10:52:48.413642 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9095 10:52:48.416645 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9096 10:52:48.420488 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9097 10:52:48.427042 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9098 10:52:48.430049 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9099 10:52:48.433228 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9100 10:52:48.436889 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9101 10:52:48.436979 ==
9102 10:52:48.440085 Dram Type= 6, Freq= 0, CH_1, rank 1
9103 10:52:48.446639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9104 10:52:48.446742 ==
9105 10:52:48.446811 DQS Delay:
9106 10:52:48.446874 DQS0 = 0, DQS1 = 0
9107 10:52:48.450024 DQM Delay:
9108 10:52:48.450109 DQM0 = 133, DQM1 = 126
9109 10:52:48.453293 DQ Delay:
9110 10:52:48.456853 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9111 10:52:48.459936 DQ4 =134, DQ5 =142, DQ6 =146, DQ7 =130
9112 10:52:48.463472 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9113 10:52:48.466653 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9114 10:52:48.466742
9115 10:52:48.466808
9116 10:52:48.466868
9117 10:52:48.469632 [DramC_TX_OE_Calibration] TA2
9118 10:52:48.473140 Original DQ_B0 (3 6) =30, OEN = 27
9119 10:52:48.476169 Original DQ_B1 (3 6) =30, OEN = 27
9120 10:52:48.479562 24, 0x0, End_B0=24 End_B1=24
9121 10:52:48.479654 25, 0x0, End_B0=25 End_B1=25
9122 10:52:48.483101 26, 0x0, End_B0=26 End_B1=26
9123 10:52:48.486213 27, 0x0, End_B0=27 End_B1=27
9124 10:52:48.490151 28, 0x0, End_B0=28 End_B1=28
9125 10:52:48.492772 29, 0x0, End_B0=29 End_B1=29
9126 10:52:48.492869 30, 0x0, End_B0=30 End_B1=30
9127 10:52:48.496120 31, 0x4141, End_B0=30 End_B1=30
9128 10:52:48.499646 Byte0 end_step=30 best_step=27
9129 10:52:48.502724 Byte1 end_step=30 best_step=27
9130 10:52:48.506328 Byte0 TX OE(2T, 0.5T) = (3, 3)
9131 10:52:48.509641 Byte1 TX OE(2T, 0.5T) = (3, 3)
9132 10:52:48.509737
9133 10:52:48.509805
9134 10:52:48.515771 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9135 10:52:48.519357 CH1 RK1: MR19=303, MR18=D0A
9136 10:52:48.526107 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9137 10:52:48.529260 [RxdqsGatingPostProcess] freq 1600
9138 10:52:48.532439 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9139 10:52:48.535921 best DQS0 dly(2T, 0.5T) = (1, 1)
9140 10:52:48.539316 best DQS1 dly(2T, 0.5T) = (1, 1)
9141 10:52:48.542204 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9142 10:52:48.545466 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9143 10:52:48.548793 best DQS0 dly(2T, 0.5T) = (1, 1)
9144 10:52:48.552206 best DQS1 dly(2T, 0.5T) = (1, 1)
9145 10:52:48.555245 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9146 10:52:48.558786 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9147 10:52:48.562426 Pre-setting of DQS Precalculation
9148 10:52:48.565573 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9149 10:52:48.571919 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9150 10:52:48.581763 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 10:52:48.581889
9152 10:52:48.581964
9153 10:52:48.585295 [Calibration Summary] 3200 Mbps
9154 10:52:48.585381 CH 0, Rank 0
9155 10:52:48.588375 SW Impedance : PASS
9156 10:52:48.588480 DUTY Scan : NO K
9157 10:52:48.591857 ZQ Calibration : PASS
9158 10:52:48.595013 Jitter Meter : NO K
9159 10:52:48.595107 CBT Training : PASS
9160 10:52:48.598355 Write leveling : PASS
9161 10:52:48.602186 RX DQS gating : PASS
9162 10:52:48.602280 RX DQ/DQS(RDDQC) : PASS
9163 10:52:48.605120 TX DQ/DQS : PASS
9164 10:52:48.605209 RX DATLAT : PASS
9165 10:52:48.608277 RX DQ/DQS(Engine): PASS
9166 10:52:48.612053 TX OE : PASS
9167 10:52:48.612142 All Pass.
9168 10:52:48.612209
9169 10:52:48.612269 CH 0, Rank 1
9170 10:52:48.615070 SW Impedance : PASS
9171 10:52:48.618039 DUTY Scan : NO K
9172 10:52:48.618126 ZQ Calibration : PASS
9173 10:52:48.621591 Jitter Meter : NO K
9174 10:52:48.624761 CBT Training : PASS
9175 10:52:48.624851 Write leveling : PASS
9176 10:52:48.627856 RX DQS gating : PASS
9177 10:52:48.631040 RX DQ/DQS(RDDQC) : PASS
9178 10:52:48.631128 TX DQ/DQS : PASS
9179 10:52:48.634961 RX DATLAT : PASS
9180 10:52:48.638176 RX DQ/DQS(Engine): PASS
9181 10:52:48.638266 TX OE : PASS
9182 10:52:48.641082 All Pass.
9183 10:52:48.641167
9184 10:52:48.641234 CH 1, Rank 0
9185 10:52:48.644343 SW Impedance : PASS
9186 10:52:48.644429 DUTY Scan : NO K
9187 10:52:48.648150 ZQ Calibration : PASS
9188 10:52:48.651059 Jitter Meter : NO K
9189 10:52:48.651146 CBT Training : PASS
9190 10:52:48.654093 Write leveling : PASS
9191 10:52:48.658061 RX DQS gating : PASS
9192 10:52:48.658152 RX DQ/DQS(RDDQC) : PASS
9193 10:52:48.660974 TX DQ/DQS : PASS
9194 10:52:48.664368 RX DATLAT : PASS
9195 10:52:48.664457 RX DQ/DQS(Engine): PASS
9196 10:52:48.667507 TX OE : PASS
9197 10:52:48.667592 All Pass.
9198 10:52:48.667658
9199 10:52:48.670561 CH 1, Rank 1
9200 10:52:48.670646 SW Impedance : PASS
9201 10:52:48.674142 DUTY Scan : NO K
9202 10:52:48.677367 ZQ Calibration : PASS
9203 10:52:48.677455 Jitter Meter : NO K
9204 10:52:48.680688 CBT Training : PASS
9205 10:52:48.683784 Write leveling : PASS
9206 10:52:48.683870 RX DQS gating : PASS
9207 10:52:48.687507 RX DQ/DQS(RDDQC) : PASS
9208 10:52:48.687593 TX DQ/DQS : PASS
9209 10:52:48.690829 RX DATLAT : PASS
9210 10:52:48.693908 RX DQ/DQS(Engine): PASS
9211 10:52:48.694000 TX OE : PASS
9212 10:52:48.697130 All Pass.
9213 10:52:48.697218
9214 10:52:48.697284 DramC Write-DBI on
9215 10:52:48.700929 PER_BANK_REFRESH: Hybrid Mode
9216 10:52:48.703492 TX_TRACKING: ON
9217 10:52:48.710698 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9218 10:52:48.720293 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9219 10:52:48.726719 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9220 10:52:48.729853 [FAST_K] Save calibration result to emmc
9221 10:52:48.733195 sync common calibartion params.
9222 10:52:48.736769 sync cbt_mode0:1, 1:1
9223 10:52:48.736859 dram_init: ddr_geometry: 2
9224 10:52:48.740317 dram_init: ddr_geometry: 2
9225 10:52:48.743286 dram_init: ddr_geometry: 2
9226 10:52:48.743376 0:dram_rank_size:100000000
9227 10:52:48.746652 1:dram_rank_size:100000000
9228 10:52:48.753250 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9229 10:52:48.756703 DFS_SHUFFLE_HW_MODE: ON
9230 10:52:48.759392 dramc_set_vcore_voltage set vcore to 725000
9231 10:52:48.759482 Read voltage for 1600, 0
9232 10:52:48.763024 Vio18 = 0
9233 10:52:48.763113 Vcore = 725000
9234 10:52:48.763180 Vdram = 0
9235 10:52:48.766388 Vddq = 0
9236 10:52:48.766473 Vmddr = 0
9237 10:52:48.769287 switch to 3200 Mbps bootup
9238 10:52:48.769371 [DramcRunTimeConfig]
9239 10:52:48.769436 PHYPLL
9240 10:52:48.772853 DPM_CONTROL_AFTERK: ON
9241 10:52:48.776068 PER_BANK_REFRESH: ON
9242 10:52:48.779140 REFRESH_OVERHEAD_REDUCTION: ON
9243 10:52:48.779231 CMD_PICG_NEW_MODE: OFF
9244 10:52:48.782422 XRTWTW_NEW_MODE: ON
9245 10:52:48.782509 XRTRTR_NEW_MODE: ON
9246 10:52:48.786072 TX_TRACKING: ON
9247 10:52:48.786160 RDSEL_TRACKING: OFF
9248 10:52:48.789470 DQS Precalculation for DVFS: ON
9249 10:52:48.792829 RX_TRACKING: OFF
9250 10:52:48.792922 HW_GATING DBG: ON
9251 10:52:48.796188 ZQCS_ENABLE_LP4: ON
9252 10:52:48.796278 RX_PICG_NEW_MODE: ON
9253 10:52:48.799776 TX_PICG_NEW_MODE: ON
9254 10:52:48.799865 ENABLE_RX_DCM_DPHY: ON
9255 10:52:48.802532 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9256 10:52:48.805742 DUMMY_READ_FOR_TRACKING: OFF
9257 10:52:48.809360 !!! SPM_CONTROL_AFTERK: OFF
9258 10:52:48.812455 !!! SPM could not control APHY
9259 10:52:48.812589 IMPEDANCE_TRACKING: ON
9260 10:52:48.815802 TEMP_SENSOR: ON
9261 10:52:48.815891 HW_SAVE_FOR_SR: OFF
9262 10:52:48.819370 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9263 10:52:48.822368 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9264 10:52:48.825833 Read ODT Tracking: ON
9265 10:52:48.829219 Refresh Rate DeBounce: ON
9266 10:52:48.829310 DFS_NO_QUEUE_FLUSH: ON
9267 10:52:48.832840 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9268 10:52:48.835843 ENABLE_DFS_RUNTIME_MRW: OFF
9269 10:52:48.839058 DDR_RESERVE_NEW_MODE: ON
9270 10:52:48.839147 MR_CBT_SWITCH_FREQ: ON
9271 10:52:48.842214 =========================
9272 10:52:48.860548 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9273 10:52:48.863955 dram_init: ddr_geometry: 2
9274 10:52:48.882218 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9275 10:52:48.886452 dram_init: dram init end (result: 0)
9276 10:52:48.892464 DRAM-K: Full calibration passed in 24661 msecs
9277 10:52:48.895383 MRC: failed to locate region type 0.
9278 10:52:48.895481 DRAM rank0 size:0x100000000,
9279 10:52:48.899191 DRAM rank1 size=0x100000000
9280 10:52:48.908860 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9281 10:52:48.915337 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9282 10:52:48.922167 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9283 10:52:48.931615 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9284 10:52:48.931747 DRAM rank0 size:0x100000000,
9285 10:52:48.935182 DRAM rank1 size=0x100000000
9286 10:52:48.935272 CBMEM:
9287 10:52:48.938483 IMD: root @ 0xfffff000 254 entries.
9288 10:52:48.941779 IMD: root @ 0xffffec00 62 entries.
9289 10:52:48.944691 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9290 10:52:48.951536 WARNING: RO_VPD is uninitialized or empty.
9291 10:52:48.954682 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9292 10:52:48.962777 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9293 10:52:48.975143 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9294 10:52:48.986515 BS: romstage times (exec / console): total (unknown) / 24150 ms
9295 10:52:48.986654
9296 10:52:48.986723
9297 10:52:48.996502 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9298 10:52:48.999659 ARM64: Exception handlers installed.
9299 10:52:49.003021 ARM64: Testing exception
9300 10:52:49.006690 ARM64: Done test exception
9301 10:52:49.006788 Enumerating buses...
9302 10:52:49.010063 Show all devs... Before device enumeration.
9303 10:52:49.012962 Root Device: enabled 1
9304 10:52:49.016568 CPU_CLUSTER: 0: enabled 1
9305 10:52:49.016660 CPU: 00: enabled 1
9306 10:52:49.019688 Compare with tree...
9307 10:52:49.019777 Root Device: enabled 1
9308 10:52:49.023030 CPU_CLUSTER: 0: enabled 1
9309 10:52:49.026271 CPU: 00: enabled 1
9310 10:52:49.026363 Root Device scanning...
9311 10:52:49.029476 scan_static_bus for Root Device
9312 10:52:49.032880 CPU_CLUSTER: 0 enabled
9313 10:52:49.036314 scan_static_bus for Root Device done
9314 10:52:49.039713 scan_bus: bus Root Device finished in 8 msecs
9315 10:52:49.039803 done
9316 10:52:49.046047 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9317 10:52:49.049040 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9318 10:52:49.055679 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9319 10:52:49.058998 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9320 10:52:49.062399 Allocating resources...
9321 10:52:49.065758 Reading resources...
9322 10:52:49.069103 Root Device read_resources bus 0 link: 0
9323 10:52:49.072224 DRAM rank0 size:0x100000000,
9324 10:52:49.072318 DRAM rank1 size=0x100000000
9325 10:52:49.078790 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9326 10:52:49.078894 CPU: 00 missing read_resources
9327 10:52:49.085554 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9328 10:52:49.088609 Root Device read_resources bus 0 link: 0 done
9329 10:52:49.091980 Done reading resources.
9330 10:52:49.095345 Show resources in subtree (Root Device)...After reading.
9331 10:52:49.098908 Root Device child on link 0 CPU_CLUSTER: 0
9332 10:52:49.101956 CPU_CLUSTER: 0 child on link 0 CPU: 00
9333 10:52:49.112033 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9334 10:52:49.112156 CPU: 00
9335 10:52:49.115145 Root Device assign_resources, bus 0 link: 0
9336 10:52:49.118605 CPU_CLUSTER: 0 missing set_resources
9337 10:52:49.125478 Root Device assign_resources, bus 0 link: 0 done
9338 10:52:49.125594 Done setting resources.
9339 10:52:49.131746 Show resources in subtree (Root Device)...After assigning values.
9340 10:52:49.135200 Root Device child on link 0 CPU_CLUSTER: 0
9341 10:52:49.138203 CPU_CLUSTER: 0 child on link 0 CPU: 00
9342 10:52:49.148421 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9343 10:52:49.148551 CPU: 00
9344 10:52:49.151498 Done allocating resources.
9345 10:52:49.158279 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9346 10:52:49.158384 Enabling resources...
9347 10:52:49.158453 done.
9348 10:52:49.165112 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9349 10:52:49.168064 Initializing devices...
9350 10:52:49.168157 Root Device init
9351 10:52:49.171187 init hardware done!
9352 10:52:49.171274 0x00000018: ctrlr->caps
9353 10:52:49.174807 52.000 MHz: ctrlr->f_max
9354 10:52:49.177910 0.400 MHz: ctrlr->f_min
9355 10:52:49.178003 0x40ff8080: ctrlr->voltages
9356 10:52:49.181034 sclk: 390625
9357 10:52:49.181126 Bus Width = 1
9358 10:52:49.184738 sclk: 390625
9359 10:52:49.184827 Bus Width = 1
9360 10:52:49.188125 Early init status = 3
9361 10:52:49.191169 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9362 10:52:49.194842 in-header: 03 fc 00 00 01 00 00 00
9363 10:52:49.197909 in-data: 00
9364 10:52:49.201088 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9365 10:52:49.207069 in-header: 03 fd 00 00 00 00 00 00
9366 10:52:49.209794 in-data:
9367 10:52:49.213066 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9368 10:52:49.220169 in-header: 03 fc 00 00 01 00 00 00
9369 10:52:49.223338 in-data: 00
9370 10:52:49.227147 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9371 10:52:49.231905 in-header: 03 fd 00 00 00 00 00 00
9372 10:52:49.235508 in-data:
9373 10:52:49.238590 [SSUSB] Setting up USB HOST controller...
9374 10:52:49.241838 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9375 10:52:49.244909 [SSUSB] phy power-on done.
9376 10:52:49.248438 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9377 10:52:49.254826 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9378 10:52:49.258538 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9379 10:52:49.264713 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9380 10:52:49.271421 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9381 10:52:49.278141 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9382 10:52:49.284743 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9383 10:52:49.291609 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9384 10:52:49.294547 SPM: binary array size = 0x9dc
9385 10:52:49.298015 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9386 10:52:49.304380 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9387 10:52:49.311414 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9388 10:52:49.317708 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9389 10:52:49.321011 configure_display: Starting display init
9390 10:52:49.355438 anx7625_power_on_init: Init interface.
9391 10:52:49.358424 anx7625_disable_pd_protocol: Disabled PD feature.
9392 10:52:49.361822 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9393 10:52:49.389507 anx7625_start_dp_work: Secure OCM version=00
9394 10:52:49.392885 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9395 10:52:49.408110 sp_tx_get_edid_block: EDID Block = 1
9396 10:52:49.510632 Extracted contents:
9397 10:52:49.513846 header: 00 ff ff ff ff ff ff 00
9398 10:52:49.516723 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9399 10:52:49.520183 version: 01 04
9400 10:52:49.523363 basic params: 95 1f 11 78 0a
9401 10:52:49.526760 chroma info: 76 90 94 55 54 90 27 21 50 54
9402 10:52:49.530502 established: 00 00 00
9403 10:52:49.536628 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9404 10:52:49.539993 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9405 10:52:49.546801 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9406 10:52:49.553147 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9407 10:52:49.560384 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9408 10:52:49.563115 extensions: 00
9409 10:52:49.563197 checksum: fb
9410 10:52:49.563262
9411 10:52:49.566544 Manufacturer: IVO Model 57d Serial Number 0
9412 10:52:49.570216 Made week 0 of 2020
9413 10:52:49.570299 EDID version: 1.4
9414 10:52:49.573448 Digital display
9415 10:52:49.576297 6 bits per primary color channel
9416 10:52:49.576410 DisplayPort interface
9417 10:52:49.579826 Maximum image size: 31 cm x 17 cm
9418 10:52:49.582926 Gamma: 220%
9419 10:52:49.583009 Check DPMS levels
9420 10:52:49.586579 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9421 10:52:49.593030 First detailed timing is preferred timing
9422 10:52:49.593118 Established timings supported:
9423 10:52:49.596246 Standard timings supported:
9424 10:52:49.600284 Detailed timings
9425 10:52:49.602978 Hex of detail: 383680a07038204018303c0035ae10000019
9426 10:52:49.606808 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9427 10:52:49.612788 0780 0798 07c8 0820 hborder 0
9428 10:52:49.617173 0438 043b 0447 0458 vborder 0
9429 10:52:49.619738 -hsync -vsync
9430 10:52:49.619847 Did detailed timing
9431 10:52:49.626048 Hex of detail: 000000000000000000000000000000000000
9432 10:52:49.629393 Manufacturer-specified data, tag 0
9433 10:52:49.633135 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9434 10:52:49.635901 ASCII string: InfoVision
9435 10:52:49.639596 Hex of detail: 000000fe00523134304e574635205248200a
9436 10:52:49.642620 ASCII string: R140NWF5 RH
9437 10:52:49.642703 Checksum
9438 10:52:49.645955 Checksum: 0xfb (valid)
9439 10:52:49.649280 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9440 10:52:49.652454 DSI data_rate: 832800000 bps
9441 10:52:49.658978 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9442 10:52:49.663036 anx7625_parse_edid: pixelclock(138800).
9443 10:52:49.665862 hactive(1920), hsync(48), hfp(24), hbp(88)
9444 10:52:49.668914 vactive(1080), vsync(12), vfp(3), vbp(17)
9445 10:52:49.672242 anx7625_dsi_config: config dsi.
9446 10:52:49.678682 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9447 10:52:49.692379 anx7625_dsi_config: success to config DSI
9448 10:52:49.695345 anx7625_dp_start: MIPI phy setup OK.
9449 10:52:49.698576 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9450 10:52:49.702066 mtk_ddp_mode_set invalid vrefresh 60
9451 10:52:49.705317 main_disp_path_setup
9452 10:52:49.705400 ovl_layer_smi_id_en
9453 10:52:49.708343 ovl_layer_smi_id_en
9454 10:52:49.708461 ccorr_config
9455 10:52:49.708585 aal_config
9456 10:52:49.712082 gamma_config
9457 10:52:49.712164 postmask_config
9458 10:52:49.715177 dither_config
9459 10:52:49.718400 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9460 10:52:49.725235 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9461 10:52:49.728921 Root Device init finished in 556 msecs
9462 10:52:49.731810 CPU_CLUSTER: 0 init
9463 10:52:49.738455 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9464 10:52:49.745249 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9465 10:52:49.745339 APU_MBOX 0x190000b0 = 0x10001
9466 10:52:49.748194 APU_MBOX 0x190001b0 = 0x10001
9467 10:52:49.751399 APU_MBOX 0x190005b0 = 0x10001
9468 10:52:49.754849 APU_MBOX 0x190006b0 = 0x10001
9469 10:52:49.761124 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9470 10:52:49.770997 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9471 10:52:49.783509 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9472 10:52:49.790088 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9473 10:52:49.801865 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9474 10:52:49.811003 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9475 10:52:49.814291 CPU_CLUSTER: 0 init finished in 81 msecs
9476 10:52:49.818239 Devices initialized
9477 10:52:49.820853 Show all devs... After init.
9478 10:52:49.820961 Root Device: enabled 1
9479 10:52:49.824640 CPU_CLUSTER: 0: enabled 1
9480 10:52:49.827870 CPU: 00: enabled 1
9481 10:52:49.830928 BS: BS_DEV_INIT run times (exec / console): 215 / 447 ms
9482 10:52:49.834331 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9483 10:52:49.837334 ELOG: NV offset 0x57f000 size 0x1000
9484 10:52:49.844266 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9485 10:52:49.850674 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9486 10:52:49.854488 ELOG: Event(17) added with size 13 at 2023-06-05 10:52:50 UTC
9487 10:52:49.860814 out: cmd=0x121: 03 db 21 01 00 00 00 00
9488 10:52:49.864224 in-header: 03 93 00 00 2c 00 00 00
9489 10:52:49.877298 in-data: cc 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9490 10:52:49.880196 ELOG: Event(A1) added with size 10 at 2023-06-05 10:52:50 UTC
9491 10:52:49.890382 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9492 10:52:49.893431 ELOG: Event(A0) added with size 9 at 2023-06-05 10:52:50 UTC
9493 10:52:49.897135 elog_add_boot_reason: Logged dev mode boot
9494 10:52:49.903580 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9495 10:52:49.903669 Finalize devices...
9496 10:52:49.906595 Devices finalized
9497 10:52:49.909913 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9498 10:52:49.913406 Writing coreboot table at 0xffe64000
9499 10:52:49.920131 0. 000000000010a000-0000000000113fff: RAMSTAGE
9500 10:52:49.923328 1. 0000000040000000-00000000400fffff: RAM
9501 10:52:49.926230 2. 0000000040100000-000000004032afff: RAMSTAGE
9502 10:52:49.929990 3. 000000004032b000-00000000545fffff: RAM
9503 10:52:49.933496 4. 0000000054600000-000000005465ffff: BL31
9504 10:52:49.939568 5. 0000000054660000-00000000ffe63fff: RAM
9505 10:52:49.943256 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9506 10:52:49.947123 7. 0000000100000000-000000023fffffff: RAM
9507 10:52:49.949497 Passing 5 GPIOs to payload:
9508 10:52:49.956257 NAME | PORT | POLARITY | VALUE
9509 10:52:49.959588 EC in RW | 0x000000aa | low | undefined
9510 10:52:49.962777 EC interrupt | 0x00000005 | low | undefined
9511 10:52:49.970294 TPM interrupt | 0x000000ab | high | undefined
9512 10:52:49.973115 SD card detect | 0x00000011 | high | undefined
9513 10:52:49.979572 speaker enable | 0x00000093 | high | undefined
9514 10:52:49.982877 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9515 10:52:49.985696 in-header: 03 f9 00 00 02 00 00 00
9516 10:52:49.985779 in-data: 02 00
9517 10:52:49.989316 ADC[4]: Raw value=900443 ID=7
9518 10:52:49.992739 ADC[3]: Raw value=214021 ID=1
9519 10:52:49.992823 RAM Code: 0x71
9520 10:52:49.996255 ADC[6]: Raw value=75036 ID=0
9521 10:52:49.999202 ADC[5]: Raw value=213652 ID=1
9522 10:52:49.999285 SKU Code: 0x1
9523 10:52:50.005961 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9524 10:52:50.009483 coreboot table: 964 bytes.
9525 10:52:50.012242 IMD ROOT 0. 0xfffff000 0x00001000
9526 10:52:50.016066 IMD SMALL 1. 0xffffe000 0x00001000
9527 10:52:50.019161 RO MCACHE 2. 0xffffc000 0x00001104
9528 10:52:50.022704 CONSOLE 3. 0xfff7c000 0x00080000
9529 10:52:50.025403 FMAP 4. 0xfff7b000 0x00000452
9530 10:52:50.028930 TIME STAMP 5. 0xfff7a000 0x00000910
9531 10:52:50.032194 VBOOT WORK 6. 0xfff66000 0x00014000
9532 10:52:50.035451 RAMOOPS 7. 0xffe66000 0x00100000
9533 10:52:50.038625 COREBOOT 8. 0xffe64000 0x00002000
9534 10:52:50.038709 IMD small region:
9535 10:52:50.041993 IMD ROOT 0. 0xffffec00 0x00000400
9536 10:52:50.045528 VPD 1. 0xffffeba0 0x0000004c
9537 10:52:50.048721 MMC STATUS 2. 0xffffeb80 0x00000004
9538 10:52:50.055437 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9539 10:52:50.058470 Probing TPM: done!
9540 10:52:50.061760 Connected to device vid:did:rid of 1ae0:0028:00
9541 10:52:50.071634 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9542 10:52:50.074954 Initialized TPM device CR50 revision 0
9543 10:52:50.079037 Checking cr50 for pending updates
9544 10:52:50.082223 Reading cr50 TPM mode
9545 10:52:50.091045 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9546 10:52:50.097644 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9547 10:52:50.137597 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9548 10:52:50.140941 Checking segment from ROM address 0x40100000
9549 10:52:50.144188 Checking segment from ROM address 0x4010001c
9550 10:52:50.150919 Loading segment from ROM address 0x40100000
9551 10:52:50.151008 code (compression=0)
9552 10:52:50.160813 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9553 10:52:50.167584 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9554 10:52:50.167671 it's not compressed!
9555 10:52:50.174168 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9556 10:52:50.180568 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9557 10:52:50.198072 Loading segment from ROM address 0x4010001c
9558 10:52:50.198168 Entry Point 0x80000000
9559 10:52:50.201399 Loaded segments
9560 10:52:50.204797 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9561 10:52:50.211297 Jumping to boot code at 0x80000000(0xffe64000)
9562 10:52:50.218145 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9563 10:52:50.224696 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9564 10:52:50.232336 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9565 10:52:50.235930 Checking segment from ROM address 0x40100000
9566 10:52:50.239107 Checking segment from ROM address 0x4010001c
9567 10:52:50.245509 Loading segment from ROM address 0x40100000
9568 10:52:50.245596 code (compression=1)
9569 10:52:50.252277 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9570 10:52:50.262288 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9571 10:52:50.262380 using LZMA
9572 10:52:50.270633 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9573 10:52:50.277615 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9574 10:52:50.280929 Loading segment from ROM address 0x4010001c
9575 10:52:50.281015 Entry Point 0x54601000
9576 10:52:50.284038 Loaded segments
9577 10:52:50.287489 NOTICE: MT8192 bl31_setup
9578 10:52:50.295347 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9579 10:52:50.297931 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9580 10:52:50.300907 WARNING: region 0:
9581 10:52:50.304388 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9582 10:52:50.304485 WARNING: region 1:
9583 10:52:50.310966 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9584 10:52:50.314562 WARNING: region 2:
9585 10:52:50.317713 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9586 10:52:50.320856 WARNING: region 3:
9587 10:52:50.324179 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9588 10:52:50.327436 WARNING: region 4:
9589 10:52:50.334303 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9590 10:52:50.334392 WARNING: region 5:
9591 10:52:50.337341 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9592 10:52:50.341250 WARNING: region 6:
9593 10:52:50.344874 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9594 10:52:50.347355 WARNING: region 7:
9595 10:52:50.350795 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9596 10:52:50.357351 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9597 10:52:50.360796 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9598 10:52:50.364554 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9599 10:52:50.370506 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9600 10:52:50.374084 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9601 10:52:50.377745 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9602 10:52:50.383970 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9603 10:52:50.387262 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9604 10:52:50.393965 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9605 10:52:50.397635 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9606 10:52:50.400447 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9607 10:52:50.407519 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9608 10:52:50.410710 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9609 10:52:50.416845 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9610 10:52:50.420189 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9611 10:52:50.423747 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9612 10:52:50.430719 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9613 10:52:50.434088 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9614 10:52:50.437251 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9615 10:52:50.443818 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9616 10:52:50.447163 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9617 10:52:50.453392 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9618 10:52:50.457297 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9619 10:52:50.460066 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9620 10:52:50.466833 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9621 10:52:50.469949 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9622 10:52:50.477564 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9623 10:52:50.480476 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9624 10:52:50.483369 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9625 10:52:50.490532 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9626 10:52:50.493433 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9627 10:52:50.499880 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9628 10:52:50.503082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9629 10:52:50.506928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9630 10:52:50.509830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9631 10:52:50.516860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9632 10:52:50.519944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9633 10:52:50.523596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9634 10:52:50.526720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9635 10:52:50.532975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9636 10:52:50.536382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9637 10:52:50.539619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9638 10:52:50.542916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9639 10:52:50.549759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9640 10:52:50.552841 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9641 10:52:50.556390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9642 10:52:50.562748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9643 10:52:50.566284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9644 10:52:50.569962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9645 10:52:50.575941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9646 10:52:50.579591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9647 10:52:50.586514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9648 10:52:50.589171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9649 10:52:50.592559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9650 10:52:50.599288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9651 10:52:50.602406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9652 10:52:50.609385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9653 10:52:50.612673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9654 10:52:50.619282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9655 10:52:50.622331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9656 10:52:50.629036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9657 10:52:50.632150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9658 10:52:50.635299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9659 10:52:50.642323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9660 10:52:50.645599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9661 10:52:50.652783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9662 10:52:50.655395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9663 10:52:50.662272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9664 10:52:50.665498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9665 10:52:50.669907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9666 10:52:50.675685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9667 10:52:50.678798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9668 10:52:50.685761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9669 10:52:50.689090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9670 10:52:50.695164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9671 10:52:50.698585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9672 10:52:50.705041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9673 10:52:50.708319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9674 10:52:50.711801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9675 10:52:50.718641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9676 10:52:50.721743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9677 10:52:50.728458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9678 10:52:50.732077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9679 10:52:50.738559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9680 10:52:50.742113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9681 10:52:50.744945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9682 10:52:50.751963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9683 10:52:50.755279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9684 10:52:50.761461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9685 10:52:50.765132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9686 10:52:50.771414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9687 10:52:50.775039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9688 10:52:50.781322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9689 10:52:50.784794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9690 10:52:50.788125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9691 10:52:50.795064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9692 10:52:50.797974 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9693 10:52:50.801362 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9694 10:52:50.807747 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9695 10:52:50.811009 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9696 10:52:50.814366 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9697 10:52:50.821195 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9698 10:52:50.824330 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9699 10:52:50.830923 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9700 10:52:50.834462 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9701 10:52:50.837934 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9702 10:52:50.844833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9703 10:52:50.847719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9704 10:52:50.854657 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9705 10:52:50.858041 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9706 10:52:50.861234 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9707 10:52:50.867657 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9708 10:52:50.871172 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9709 10:52:50.877365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9710 10:52:50.880636 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9711 10:52:50.884249 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9712 10:52:50.888116 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9713 10:52:50.893934 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9714 10:52:50.897648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9715 10:52:50.900781 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9716 10:52:50.907570 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9717 10:52:50.910847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9718 10:52:50.913471 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9719 10:52:50.920837 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9720 10:52:50.923553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9721 10:52:50.927042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9722 10:52:50.933780 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9723 10:52:50.937101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9724 10:52:50.943373 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9725 10:52:50.946714 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9726 10:52:50.950224 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9727 10:52:50.956501 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9728 10:52:50.960119 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9729 10:52:50.963272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9730 10:52:50.969802 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9731 10:52:50.973195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9732 10:52:50.979828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9733 10:52:50.983399 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9734 10:52:50.986630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9735 10:52:50.993101 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9736 10:52:50.996241 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9737 10:52:51.002920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9738 10:52:51.006259 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9739 10:52:51.009960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9740 10:52:51.016501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9741 10:52:51.020126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9742 10:52:51.026560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9743 10:52:51.030035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9744 10:52:51.033267 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9745 10:52:51.039962 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9746 10:52:51.043028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9747 10:52:51.046370 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9748 10:52:51.053031 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9749 10:52:51.056562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9750 10:52:51.063069 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9751 10:52:51.066112 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9752 10:52:51.072757 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9753 10:52:51.076068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9754 10:52:51.079424 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9755 10:52:51.086027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9756 10:52:51.089122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9757 10:52:51.092325 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9758 10:52:51.098976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9759 10:52:51.102805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9760 10:52:51.109217 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9761 10:52:51.112000 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9762 10:52:51.116449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9763 10:52:51.122445 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9764 10:52:51.125506 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9765 10:52:51.132332 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9766 10:52:51.135501 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9767 10:52:51.142315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9768 10:52:51.145563 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9769 10:52:51.149161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9770 10:52:51.155241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9771 10:52:51.158613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9772 10:52:51.165233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9773 10:52:51.168309 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9774 10:52:51.171540 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9775 10:52:51.178702 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9776 10:52:51.181533 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9777 10:52:51.187987 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9778 10:52:51.191432 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9779 10:52:51.194717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9780 10:52:51.201594 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9781 10:52:51.204631 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9782 10:52:51.207852 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9783 10:52:51.215502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9784 10:52:51.217961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9785 10:52:51.224205 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9786 10:52:51.227769 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9787 10:52:51.233983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9788 10:52:51.237375 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9789 10:52:51.241089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9790 10:52:51.247867 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9791 10:52:51.250959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9792 10:52:51.257095 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9793 10:52:51.260827 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9794 10:52:51.267016 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9795 10:52:51.270546 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9796 10:52:51.274126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9797 10:52:51.280429 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9798 10:52:51.283589 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9799 10:52:51.290174 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9800 10:52:51.293810 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9801 10:52:51.300247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9802 10:52:51.303530 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9803 10:52:51.306981 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9804 10:52:51.313489 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9805 10:52:51.316664 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9806 10:52:51.323098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9807 10:52:51.326747 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9808 10:52:51.333304 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9809 10:52:51.337169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9810 10:52:51.339701 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9811 10:52:51.346567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9812 10:52:51.350345 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9813 10:52:51.356638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9814 10:52:51.359678 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9815 10:52:51.366230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9816 10:52:51.369968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9817 10:52:51.373087 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9818 10:52:51.379544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9819 10:52:51.382904 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9820 10:52:51.389547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9821 10:52:51.392964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9822 10:52:51.396820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9823 10:52:51.403338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9824 10:52:51.406109 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9825 10:52:51.409845 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9826 10:52:51.416364 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9827 10:52:51.419427 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9828 10:52:51.422448 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9829 10:52:51.426122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9830 10:52:51.432708 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9831 10:52:51.436362 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9832 10:52:51.442109 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9833 10:52:51.445490 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9834 10:52:51.448938 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9835 10:52:51.455572 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9836 10:52:51.458883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9837 10:52:51.462394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9838 10:52:51.468820 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9839 10:52:51.472156 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9840 10:52:51.478447 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9841 10:52:51.481992 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9842 10:52:51.485434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9843 10:52:51.492264 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9844 10:52:51.494782 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9845 10:52:51.498709 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9846 10:52:51.505012 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9847 10:52:51.508027 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9848 10:52:51.515076 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9849 10:52:51.518289 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9850 10:52:51.521431 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9851 10:52:51.528453 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9852 10:52:51.531320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9853 10:52:51.538204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9854 10:52:51.541551 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9855 10:52:51.544039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9856 10:52:51.550749 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9857 10:52:51.554506 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9858 10:52:51.560724 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9859 10:52:51.563915 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9860 10:52:51.567556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9861 10:52:51.573881 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9862 10:52:51.577273 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9863 10:52:51.580372 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9864 10:52:51.587370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9865 10:52:51.590159 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9866 10:52:51.593638 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9867 10:52:51.596775 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9868 10:52:51.603397 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9869 10:52:51.606735 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9870 10:52:51.610246 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9871 10:52:51.613853 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9872 10:52:51.620073 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9873 10:52:51.623878 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9874 10:52:51.626675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9875 10:52:51.629711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9876 10:52:51.636741 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9877 10:52:51.639532 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9878 10:52:51.643264 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9879 10:52:51.649583 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9880 10:52:51.653082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9881 10:52:51.659810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9882 10:52:51.663312 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9883 10:52:51.669833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9884 10:52:51.672787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9885 10:52:51.676126 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9886 10:52:51.683031 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9887 10:52:51.686294 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9888 10:52:51.692723 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9889 10:52:51.695893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9890 10:52:51.699451 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9891 10:52:51.706242 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9892 10:52:51.709583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9893 10:52:51.716001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9894 10:52:51.719616 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9895 10:52:51.722857 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9896 10:52:51.729018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9897 10:52:51.732650 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9898 10:52:51.738862 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9899 10:52:51.742735 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9900 10:52:51.749016 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9901 10:52:51.752208 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9902 10:52:51.755334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9903 10:52:51.762223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9904 10:52:51.765916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9905 10:52:51.771897 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9906 10:52:51.775524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9907 10:52:51.778522 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9908 10:52:51.785163 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9909 10:52:51.788795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9910 10:52:51.795874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9911 10:52:51.798430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9912 10:52:51.805104 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9913 10:52:51.808458 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9914 10:52:51.811780 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9915 10:52:51.818455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9916 10:52:51.821319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9917 10:52:51.828741 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9918 10:52:51.831278 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9919 10:52:51.835014 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9920 10:52:51.841395 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9921 10:52:51.844878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9922 10:52:51.851286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9923 10:52:51.854406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9924 10:52:51.861829 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9925 10:52:51.864433 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9926 10:52:51.868059 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9927 10:52:51.874482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9928 10:52:51.878100 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9929 10:52:51.884037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9930 10:52:51.887406 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9931 10:52:51.890745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9932 10:52:51.897148 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9933 10:52:51.900418 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9934 10:52:51.907526 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9935 10:52:51.910697 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9936 10:52:51.916963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9937 10:52:51.920977 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9938 10:52:51.923674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9939 10:52:51.930538 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9940 10:52:51.933710 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9941 10:52:51.940333 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9942 10:52:51.943361 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9943 10:52:51.946991 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9944 10:52:51.953580 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9945 10:52:51.956790 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9946 10:52:51.963358 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9947 10:52:51.966457 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9948 10:52:51.973212 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9949 10:52:51.976500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9950 10:52:51.979490 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9951 10:52:51.986163 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9952 10:52:51.989332 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9953 10:52:51.996162 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9954 10:52:51.999423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9955 10:52:52.006269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9956 10:52:52.009276 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9957 10:52:52.016371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9958 10:52:52.019725 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9959 10:52:52.022750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9960 10:52:52.028868 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9961 10:52:52.032467 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9962 10:52:52.038716 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9963 10:52:52.042641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9964 10:52:52.048671 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9965 10:52:52.051702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9966 10:52:52.058844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9967 10:52:52.062365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9968 10:52:52.068200 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9969 10:52:52.071770 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9970 10:52:52.074962 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9971 10:52:52.081378 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9972 10:52:52.084992 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9973 10:52:52.091574 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9974 10:52:52.094553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9975 10:52:52.101209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9976 10:52:52.104430 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9977 10:52:52.111703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9978 10:52:52.114768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9979 10:52:52.118129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9980 10:52:52.125499 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9981 10:52:52.127726 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9982 10:52:52.134719 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9983 10:52:52.137612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9984 10:52:52.144309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9985 10:52:52.147762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9986 10:52:52.154411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9987 10:52:52.157359 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9988 10:52:52.160651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9989 10:52:52.167555 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9990 10:52:52.170650 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9991 10:52:52.177845 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9992 10:52:52.180536 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9993 10:52:52.187256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9994 10:52:52.190910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9995 10:52:52.197166 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9996 10:52:52.200786 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9997 10:52:52.203643 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9998 10:52:52.210236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9999 10:52:52.213423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10000 10:52:52.220408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10001 10:52:52.223577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10002 10:52:52.230309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10003 10:52:52.233629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10004 10:52:52.240558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10005 10:52:52.243639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10006 10:52:52.249978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10007 10:52:52.253231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10008 10:52:52.256695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10009 10:52:52.263351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10010 10:52:52.266401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10011 10:52:52.273030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10012 10:52:52.277047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10013 10:52:52.282840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10014 10:52:52.286225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10015 10:52:52.292775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10016 10:52:52.296012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10017 10:52:52.302735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10018 10:52:52.305995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10019 10:52:52.312282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10020 10:52:52.315934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10021 10:52:52.322289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10022 10:52:52.325603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10023 10:52:52.332375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10024 10:52:52.335800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10025 10:52:52.342696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10026 10:52:52.348807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10027 10:52:52.352203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10028 10:52:52.358714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10029 10:52:52.362299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10030 10:52:52.365216 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10031 10:52:52.368905 INFO: [APUAPC] vio 0
10032 10:52:52.371952 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10033 10:52:52.379223 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10034 10:52:52.382143 INFO: [APUAPC] D0_APC_0: 0x400510
10035 10:52:52.385709 INFO: [APUAPC] D0_APC_1: 0x0
10036 10:52:52.388678 INFO: [APUAPC] D0_APC_2: 0x1540
10037 10:52:52.388762 INFO: [APUAPC] D0_APC_3: 0x0
10038 10:52:52.391902 INFO: [APUAPC] D1_APC_0: 0xffffffff
10039 10:52:52.398549 INFO: [APUAPC] D1_APC_1: 0xffffffff
10040 10:52:52.401643 INFO: [APUAPC] D1_APC_2: 0x3fffff
10041 10:52:52.401729 INFO: [APUAPC] D1_APC_3: 0x0
10042 10:52:52.405080 INFO: [APUAPC] D2_APC_0: 0xffffffff
10043 10:52:52.408368 INFO: [APUAPC] D2_APC_1: 0xffffffff
10044 10:52:52.411601 INFO: [APUAPC] D2_APC_2: 0x3fffff
10045 10:52:52.414807 INFO: [APUAPC] D2_APC_3: 0x0
10046 10:52:52.418715 INFO: [APUAPC] D3_APC_0: 0xffffffff
10047 10:52:52.421703 INFO: [APUAPC] D3_APC_1: 0xffffffff
10048 10:52:52.424884 INFO: [APUAPC] D3_APC_2: 0x3fffff
10049 10:52:52.428469 INFO: [APUAPC] D3_APC_3: 0x0
10050 10:52:52.431663 INFO: [APUAPC] D4_APC_0: 0xffffffff
10051 10:52:52.434913 INFO: [APUAPC] D4_APC_1: 0xffffffff
10052 10:52:52.438530 INFO: [APUAPC] D4_APC_2: 0x3fffff
10053 10:52:52.441687 INFO: [APUAPC] D4_APC_3: 0x0
10054 10:52:52.444594 INFO: [APUAPC] D5_APC_0: 0xffffffff
10055 10:52:52.448618 INFO: [APUAPC] D5_APC_1: 0xffffffff
10056 10:52:52.451147 INFO: [APUAPC] D5_APC_2: 0x3fffff
10057 10:52:52.454651 INFO: [APUAPC] D5_APC_3: 0x0
10058 10:52:52.458250 INFO: [APUAPC] D6_APC_0: 0xffffffff
10059 10:52:52.461259 INFO: [APUAPC] D6_APC_1: 0xffffffff
10060 10:52:52.464622 INFO: [APUAPC] D6_APC_2: 0x3fffff
10061 10:52:52.467783 INFO: [APUAPC] D6_APC_3: 0x0
10062 10:52:52.471184 INFO: [APUAPC] D7_APC_0: 0xffffffff
10063 10:52:52.474704 INFO: [APUAPC] D7_APC_1: 0xffffffff
10064 10:52:52.477860 INFO: [APUAPC] D7_APC_2: 0x3fffff
10065 10:52:52.481508 INFO: [APUAPC] D7_APC_3: 0x0
10066 10:52:52.484807 INFO: [APUAPC] D8_APC_0: 0xffffffff
10067 10:52:52.487462 INFO: [APUAPC] D8_APC_1: 0xffffffff
10068 10:52:52.491331 INFO: [APUAPC] D8_APC_2: 0x3fffff
10069 10:52:52.494649 INFO: [APUAPC] D8_APC_3: 0x0
10070 10:52:52.497446 INFO: [APUAPC] D9_APC_0: 0xffffffff
10071 10:52:52.501388 INFO: [APUAPC] D9_APC_1: 0xffffffff
10072 10:52:52.504004 INFO: [APUAPC] D9_APC_2: 0x3fffff
10073 10:52:52.507439 INFO: [APUAPC] D9_APC_3: 0x0
10074 10:52:52.510983 INFO: [APUAPC] D10_APC_0: 0xffffffff
10075 10:52:52.513997 INFO: [APUAPC] D10_APC_1: 0xffffffff
10076 10:52:52.517698 INFO: [APUAPC] D10_APC_2: 0x3fffff
10077 10:52:52.520714 INFO: [APUAPC] D10_APC_3: 0x0
10078 10:52:52.523873 INFO: [APUAPC] D11_APC_0: 0xffffffff
10079 10:52:52.527479 INFO: [APUAPC] D11_APC_1: 0xffffffff
10080 10:52:52.530659 INFO: [APUAPC] D11_APC_2: 0x3fffff
10081 10:52:52.534154 INFO: [APUAPC] D11_APC_3: 0x0
10082 10:52:52.537040 INFO: [APUAPC] D12_APC_0: 0xffffffff
10083 10:52:52.540374 INFO: [APUAPC] D12_APC_1: 0xffffffff
10084 10:52:52.543735 INFO: [APUAPC] D12_APC_2: 0x3fffff
10085 10:52:52.547180 INFO: [APUAPC] D12_APC_3: 0x0
10086 10:52:52.550304 INFO: [APUAPC] D13_APC_0: 0xffffffff
10087 10:52:52.554279 INFO: [APUAPC] D13_APC_1: 0xffffffff
10088 10:52:52.557455 INFO: [APUAPC] D13_APC_2: 0x3fffff
10089 10:52:52.560717 INFO: [APUAPC] D13_APC_3: 0x0
10090 10:52:52.564197 INFO: [APUAPC] D14_APC_0: 0xffffffff
10091 10:52:52.566903 INFO: [APUAPC] D14_APC_1: 0xffffffff
10092 10:52:52.570412 INFO: [APUAPC] D14_APC_2: 0x3fffff
10093 10:52:52.573720 INFO: [APUAPC] D14_APC_3: 0x0
10094 10:52:52.577045 INFO: [APUAPC] D15_APC_0: 0xffffffff
10095 10:52:52.580259 INFO: [APUAPC] D15_APC_1: 0xffffffff
10096 10:52:52.583573 INFO: [APUAPC] D15_APC_2: 0x3fffff
10097 10:52:52.586697 INFO: [APUAPC] D15_APC_3: 0x0
10098 10:52:52.590155 INFO: [APUAPC] APC_CON: 0x4
10099 10:52:52.593541 INFO: [NOCDAPC] D0_APC_0: 0x0
10100 10:52:52.597137 INFO: [NOCDAPC] D0_APC_1: 0x0
10101 10:52:52.599945 INFO: [NOCDAPC] D1_APC_0: 0x0
10102 10:52:52.603081 INFO: [NOCDAPC] D1_APC_1: 0xfff
10103 10:52:52.606788 INFO: [NOCDAPC] D2_APC_0: 0x0
10104 10:52:52.606871 INFO: [NOCDAPC] D2_APC_1: 0xfff
10105 10:52:52.610110 INFO: [NOCDAPC] D3_APC_0: 0x0
10106 10:52:52.612991 INFO: [NOCDAPC] D3_APC_1: 0xfff
10107 10:52:52.616245 INFO: [NOCDAPC] D4_APC_0: 0x0
10108 10:52:52.619945 INFO: [NOCDAPC] D4_APC_1: 0xfff
10109 10:52:52.622915 INFO: [NOCDAPC] D5_APC_0: 0x0
10110 10:52:52.626438 INFO: [NOCDAPC] D5_APC_1: 0xfff
10111 10:52:52.629580 INFO: [NOCDAPC] D6_APC_0: 0x0
10112 10:52:52.633275 INFO: [NOCDAPC] D6_APC_1: 0xfff
10113 10:52:52.636331 INFO: [NOCDAPC] D7_APC_0: 0x0
10114 10:52:52.639895 INFO: [NOCDAPC] D7_APC_1: 0xfff
10115 10:52:52.639980 INFO: [NOCDAPC] D8_APC_0: 0x0
10116 10:52:52.643350 INFO: [NOCDAPC] D8_APC_1: 0xfff
10117 10:52:52.646167 INFO: [NOCDAPC] D9_APC_0: 0x0
10118 10:52:52.649793 INFO: [NOCDAPC] D9_APC_1: 0xfff
10119 10:52:52.652922 INFO: [NOCDAPC] D10_APC_0: 0x0
10120 10:52:52.656252 INFO: [NOCDAPC] D10_APC_1: 0xfff
10121 10:52:52.659325 INFO: [NOCDAPC] D11_APC_0: 0x0
10122 10:52:52.662860 INFO: [NOCDAPC] D11_APC_1: 0xfff
10123 10:52:52.666267 INFO: [NOCDAPC] D12_APC_0: 0x0
10124 10:52:52.669707 INFO: [NOCDAPC] D12_APC_1: 0xfff
10125 10:52:52.672935 INFO: [NOCDAPC] D13_APC_0: 0x0
10126 10:52:52.676022 INFO: [NOCDAPC] D13_APC_1: 0xfff
10127 10:52:52.679341 INFO: [NOCDAPC] D14_APC_0: 0x0
10128 10:52:52.682636 INFO: [NOCDAPC] D14_APC_1: 0xfff
10129 10:52:52.682722 INFO: [NOCDAPC] D15_APC_0: 0x0
10130 10:52:52.686098 INFO: [NOCDAPC] D15_APC_1: 0xfff
10131 10:52:52.689289 INFO: [NOCDAPC] APC_CON: 0x4
10132 10:52:52.693113 INFO: [APUAPC] set_apusys_apc done
10133 10:52:52.696145 INFO: [DEVAPC] devapc_init done
10134 10:52:52.702961 INFO: GICv3 without legacy support detected.
10135 10:52:52.705944 INFO: ARM GICv3 driver initialized in EL3
10136 10:52:52.709571 INFO: Maximum SPI INTID supported: 639
10137 10:52:52.712318 INFO: BL31: Initializing runtime services
10138 10:52:52.719429 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10139 10:52:52.722531 INFO: SPM: enable CPC mode
10140 10:52:52.725894 INFO: mcdi ready for mcusys-off-idle and system suspend
10141 10:52:52.732460 INFO: BL31: Preparing for EL3 exit to normal world
10142 10:52:52.735656 INFO: Entry point address = 0x80000000
10143 10:52:52.735743 INFO: SPSR = 0x8
10144 10:52:52.742474
10145 10:52:52.742559
10146 10:52:52.742626
10147 10:52:52.745953 Starting depthcharge on Spherion...
10148 10:52:52.746038
10149 10:52:52.746104 Wipe memory regions:
10150 10:52:52.746165
10151 10:52:52.746789 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10152 10:52:52.746892 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10153 10:52:52.746980 Setting prompt string to ['asurada:']
10154 10:52:52.747065 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10155 10:52:52.748786 [0x00000040000000, 0x00000054600000)
10156 10:52:52.871631
10157 10:52:52.871788 [0x00000054660000, 0x00000080000000)
10158 10:52:53.132592
10159 10:52:53.132737 [0x000000821a7280, 0x000000ffe64000)
10160 10:52:53.876306
10161 10:52:53.876495 [0x00000100000000, 0x00000240000000)
10162 10:52:55.766094
10163 10:52:55.768963 Initializing XHCI USB controller at 0x11200000.
10164 10:52:56.751509
10165 10:52:56.752021 R8152: Initializing
10166 10:52:56.752368
10167 10:52:56.754585 Version 9 (ocp_data = 6010)
10168 10:52:56.755063
10169 10:52:56.758082 R8152: Done initializing
10170 10:52:56.758562
10171 10:52:56.758915 Adding net device
10172 10:52:57.278937
10173 10:52:57.282161 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10174 10:52:57.282606
10175 10:52:57.283047
10176 10:52:57.283376
10177 10:52:57.284116 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10179 10:52:57.385337 asurada: tftpboot 192.168.201.1 10590974/tftp-deploy-5p_k0bha/kernel/image.itb 10590974/tftp-deploy-5p_k0bha/kernel/cmdline
10180 10:52:57.385949 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10181 10:52:57.386423 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10182 10:52:57.391122 tftpboot 192.168.201.1 10590974/tftp-deploy-5p_k0bha/kernel/image.itp-deploy-5p_k0bha/kernel/cmdline
10183 10:52:57.391559
10184 10:52:57.391896 Waiting for link
10185 10:52:57.593264
10186 10:52:57.593810 done.
10187 10:52:57.594197
10188 10:52:57.594549 MAC: f4:f5:e8:50:de:0a
10189 10:52:57.594855
10190 10:52:57.596294 Sending DHCP discover... done.
10191 10:52:57.596779
10192 10:52:57.600543 Waiting for reply... done.
10193 10:52:57.601106
10194 10:52:57.602777 Sending DHCP request... done.
10195 10:52:57.603205
10196 10:52:57.606523 Waiting for reply... done.
10197 10:52:57.606950
10198 10:52:57.607283 My ip is 192.168.201.14
10199 10:52:57.607598
10200 10:52:57.609708 The DHCP server ip is 192.168.201.1
10201 10:52:57.610144
10202 10:52:57.616266 TFTP server IP predefined by user: 192.168.201.1
10203 10:52:57.616822
10204 10:52:57.623098 Bootfile predefined by user: 10590974/tftp-deploy-5p_k0bha/kernel/image.itb
10205 10:52:57.623525
10206 10:52:57.626292 Sending tftp read request... done.
10207 10:52:57.626720
10208 10:52:57.631954 Waiting for the transfer...
10209 10:52:57.632465
10210 10:52:57.937895 00000000 ################################################################
10211 10:52:57.938031
10212 10:52:58.172328 00080000 ################################################################
10213 10:52:58.172458
10214 10:52:58.397264 00100000 ################################################################
10215 10:52:58.397395
10216 10:52:58.635736 00180000 ################################################################
10217 10:52:58.635900
10218 10:52:58.866535 00200000 ################################################################
10219 10:52:58.866702
10220 10:52:59.092003 00280000 ################################################################
10221 10:52:59.092137
10222 10:52:59.315357 00300000 ################################################################
10223 10:52:59.315516
10224 10:52:59.536868 00380000 ################################################################
10225 10:52:59.537056
10226 10:52:59.763125 00400000 ################################################################
10227 10:52:59.763305
10228 10:52:59.981706 00480000 ################################################################
10229 10:52:59.981886
10230 10:53:00.202756 00500000 ################################################################
10231 10:53:00.202937
10232 10:53:00.424764 00580000 ################################################################
10233 10:53:00.424948
10234 10:53:00.647074 00600000 ################################################################
10235 10:53:00.647253
10236 10:53:00.880188 00680000 ################################################################
10237 10:53:00.880351
10238 10:53:01.126009 00700000 ################################################################
10239 10:53:01.126188
10240 10:53:01.371267 00780000 ################################################################
10241 10:53:01.371437
10242 10:53:01.596633 00800000 ################################################################
10243 10:53:01.596809
10244 10:53:01.820459 00880000 ################################################################
10245 10:53:01.820620
10246 10:53:02.055251 00900000 ################################################################
10247 10:53:02.055389
10248 10:53:02.289537 00980000 ################################################################
10249 10:53:02.289693
10250 10:53:02.515900 00a00000 ################################################################
10251 10:53:02.516073
10252 10:53:02.742462 00a80000 ################################################################
10253 10:53:02.742601
10254 10:53:02.966560 00b00000 ################################################################
10255 10:53:02.966696
10256 10:53:03.190006 00b80000 ################################################################
10257 10:53:03.190140
10258 10:53:03.415219 00c00000 ################################################################
10259 10:53:03.415357
10260 10:53:03.652080 00c80000 ################################################################
10261 10:53:03.652220
10262 10:53:03.905600 00d00000 ################################################################
10263 10:53:03.905760
10264 10:53:04.130104 00d80000 ################################################################
10265 10:53:04.130242
10266 10:53:04.354935 00e00000 ################################################################
10267 10:53:04.355077
10268 10:53:04.587573 00e80000 ################################################################
10269 10:53:04.587715
10270 10:53:04.810400 00f00000 ################################################################
10271 10:53:04.810540
10272 10:53:05.035635 00f80000 ################################################################
10273 10:53:05.035772
10274 10:53:05.259417 01000000 ################################################################
10275 10:53:05.259548
10276 10:53:05.481243 01080000 ################################################################
10277 10:53:05.481423
10278 10:53:05.713648 01100000 ################################################################
10279 10:53:05.713794
10280 10:53:05.951914 01180000 ################################################################
10281 10:53:05.952065
10282 10:53:06.183555 01200000 ################################################################
10283 10:53:06.183704
10284 10:53:06.423766 01280000 ################################################################
10285 10:53:06.423909
10286 10:53:06.667133 01300000 ################################################################
10287 10:53:06.667276
10288 10:53:06.901688 01380000 ################################################################
10289 10:53:06.901840
10290 10:53:07.155257 01400000 ################################################################
10291 10:53:07.155411
10292 10:53:07.394198 01480000 ################################################################
10293 10:53:07.394366
10294 10:53:07.630294 01500000 ################################################################
10295 10:53:07.630461
10296 10:53:07.870702 01580000 ################################################################
10297 10:53:07.870839
10298 10:53:08.109894 01600000 ################################################################
10299 10:53:08.110025
10300 10:53:08.348010 01680000 ################################################################
10301 10:53:08.348155
10302 10:53:08.587975 01700000 ################################################################
10303 10:53:08.588110
10304 10:53:08.814902 01780000 ################################################################
10305 10:53:08.815046
10306 10:53:09.047644 01800000 ################################################################
10307 10:53:09.047790
10308 10:53:09.295135 01880000 ################################################################
10309 10:53:09.295311
10310 10:53:09.519433 01900000 ################################################################
10311 10:53:09.519595
10312 10:53:09.754335 01980000 ################################################################
10313 10:53:09.754501
10314 10:53:09.998050 01a00000 ################################################################
10315 10:53:09.998210
10316 10:53:10.246258 01a80000 ################################################################
10317 10:53:10.246398
10318 10:53:10.444050 01b00000 #################################################### done.
10319 10:53:10.447410
10320 10:53:10.450433 The bootfile was 28734998 bytes long.
10321 10:53:10.450539
10322 10:53:10.450633 Sending tftp read request... done.
10323 10:53:10.450722
10324 10:53:10.454070 Waiting for the transfer...
10325 10:53:10.454147
10326 10:53:10.456910 00000000 # done.
10327 10:53:10.456983
10328 10:53:10.463689 Command line loaded dynamically from TFTP file: 10590974/tftp-deploy-5p_k0bha/kernel/cmdline
10329 10:53:10.463769
10330 10:53:10.483791 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10331 10:53:10.483886
10332 10:53:10.483953 Loading FIT.
10333 10:53:10.486637
10334 10:53:10.486735 Image ramdisk-1 has 18604104 bytes.
10335 10:53:10.486825
10336 10:53:10.490609 Image fdt-1 has 46924 bytes.
10337 10:53:10.490682
10338 10:53:10.493609 Image kernel-1 has 10081937 bytes.
10339 10:53:10.493682
10340 10:53:10.502975 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10341 10:53:10.503079
10342 10:53:10.519780 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10343 10:53:10.519888
10344 10:53:10.526145 Choosing best match conf-1 for compat google,spherion-rev2.
10345 10:53:10.529773
10346 10:53:10.534367 Connected to device vid:did:rid of 1ae0:0028:00
10347 10:53:10.541240
10348 10:53:10.544710 tpm_get_response: command 0x17b, return code 0x0
10349 10:53:10.544785
10350 10:53:10.548175 ec_init: CrosEC protocol v3 supported (256, 248)
10351 10:53:10.552287
10352 10:53:10.555894 tpm_cleanup: add release locality here.
10353 10:53:10.555993
10354 10:53:10.556083 Shutting down all USB controllers.
10355 10:53:10.559085
10356 10:53:10.559185 Removing current net device
10357 10:53:10.559274
10358 10:53:10.565692 Exiting depthcharge with code 4 at timestamp: 47285343
10359 10:53:10.565767
10360 10:53:10.569419 LZMA decompressing kernel-1 to 0x821a6718
10361 10:53:10.569492
10362 10:53:10.572563 LZMA decompressing kernel-1 to 0x40000000
10363 10:53:11.838898
10364 10:53:11.839070 jumping to kernel
10365 10:53:11.839736 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10366 10:53:11.839836 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10367 10:53:11.839914 Setting prompt string to ['Linux version [0-9]']
10368 10:53:11.839984 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10369 10:53:11.840054 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10370 10:53:11.921882
10371 10:53:11.925319 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10372 10:53:11.928314 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10373 10:53:11.928423 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10374 10:53:11.928560 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10375 10:53:11.928655 Using line separator: #'\n'#
10376 10:53:11.928719 No login prompt set.
10377 10:53:11.928782 Parsing kernel messages
10378 10:53:11.928838 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10379 10:53:11.928938 [login-action] Waiting for messages, (timeout 00:04:06)
10380 10:53:11.948393 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10381 10:53:11.951471 [ 0.000000] random: crng init done
10382 10:53:11.955260 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10383 10:53:11.958336 [ 0.000000] efi: UEFI not found.
10384 10:53:11.967955 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10385 10:53:11.974473 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10386 10:53:11.985044 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10387 10:53:11.994428 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10388 10:53:12.000775 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10389 10:53:12.007408 [ 0.000000] printk: bootconsole [mtk8250] enabled
10390 10:53:12.014317 [ 0.000000] NUMA: No NUMA configuration found
10391 10:53:12.020750 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10392 10:53:12.024092 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10393 10:53:12.027242 [ 0.000000] Zone ranges:
10394 10:53:12.034197 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10395 10:53:12.037095 [ 0.000000] DMA32 empty
10396 10:53:12.043741 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10397 10:53:12.046879 [ 0.000000] Movable zone start for each node
10398 10:53:12.050222 [ 0.000000] Early memory node ranges
10399 10:53:12.057382 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10400 10:53:12.063888 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10401 10:53:12.070420 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10402 10:53:12.077036 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10403 10:53:12.083139 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10404 10:53:12.089692 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10405 10:53:12.145421 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10406 10:53:12.152261 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10407 10:53:12.158495 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10408 10:53:12.161878 [ 0.000000] psci: probing for conduit method from DT.
10409 10:53:12.168942 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10410 10:53:12.171731 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10411 10:53:12.178279 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10412 10:53:12.181768 [ 0.000000] psci: SMC Calling Convention v1.2
10413 10:53:12.188163 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10414 10:53:12.191632 [ 0.000000] Detected VIPT I-cache on CPU0
10415 10:53:12.198445 [ 0.000000] CPU features: detected: GIC system register CPU interface
10416 10:53:12.205577 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10417 10:53:12.211177 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10418 10:53:12.218467 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10419 10:53:12.227481 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10420 10:53:12.234374 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10421 10:53:12.237740 [ 0.000000] alternatives: applying boot alternatives
10422 10:53:12.244002 [ 0.000000] Fallback order for Node 0: 0
10423 10:53:12.251030 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10424 10:53:12.254411 [ 0.000000] Policy zone: Normal
10425 10:53:12.273902 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10426 10:53:12.283641 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10427 10:53:12.296121 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10428 10:53:12.305837 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10429 10:53:12.312326 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10430 10:53:12.316247 <6>[ 0.000000] software IO TLB: area num 8.
10431 10:53:12.372609 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10432 10:53:12.521451 <6>[ 0.000000] Memory: 7954776K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397992K reserved, 32768K cma-reserved)
10433 10:53:12.527881 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10434 10:53:12.534794 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10435 10:53:12.537653 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10436 10:53:12.544305 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10437 10:53:12.551171 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10438 10:53:12.554494 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10439 10:53:12.564367 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10440 10:53:12.570879 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10441 10:53:12.577236 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10442 10:53:12.584288 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10443 10:53:12.587293 <6>[ 0.000000] GICv3: 608 SPIs implemented
10444 10:53:12.590707 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10445 10:53:12.596995 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10446 10:53:12.600328 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10447 10:53:12.607425 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10448 10:53:12.620646 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10449 10:53:12.633391 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10450 10:53:12.640150 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10451 10:53:12.647868 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10452 10:53:12.661133 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10453 10:53:12.667562 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10454 10:53:12.674471 <6>[ 0.009229] Console: colour dummy device 80x25
10455 10:53:12.684178 <6>[ 0.013984] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10456 10:53:12.691471 <6>[ 0.024491] pid_max: default: 32768 minimum: 301
10457 10:53:12.694465 <6>[ 0.029365] LSM: Security Framework initializing
10458 10:53:12.701188 <6>[ 0.034305] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 10:53:12.711164 <6>[ 0.042119] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 10:53:12.720350 <6>[ 0.051549] cblist_init_generic: Setting adjustable number of callback queues.
10461 10:53:12.727450 <6>[ 0.059001] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 10:53:12.730233 <6>[ 0.065338] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 10:53:12.736900 <6>[ 0.071745] rcu: Hierarchical SRCU implementation.
10464 10:53:12.743276 <6>[ 0.076758] rcu: Max phase no-delay instances is 1000.
10465 10:53:12.749943 <6>[ 0.083779] EFI services will not be available.
10466 10:53:12.753187 <6>[ 0.088752] smp: Bringing up secondary CPUs ...
10467 10:53:12.761896 <6>[ 0.093832] Detected VIPT I-cache on CPU1
10468 10:53:12.768158 <6>[ 0.093904] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10469 10:53:12.774700 <6>[ 0.093936] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10470 10:53:12.778065 <6>[ 0.094273] Detected VIPT I-cache on CPU2
10471 10:53:12.787932 <6>[ 0.094325] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10472 10:53:12.795094 <6>[ 0.094341] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10473 10:53:12.797963 <6>[ 0.094599] Detected VIPT I-cache on CPU3
10474 10:53:12.804236 <6>[ 0.094645] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10475 10:53:12.810963 <6>[ 0.094659] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10476 10:53:12.814371 <6>[ 0.094967] CPU features: detected: Spectre-v4
10477 10:53:12.821079 <6>[ 0.094973] CPU features: detected: Spectre-BHB
10478 10:53:12.824109 <6>[ 0.094979] Detected PIPT I-cache on CPU4
10479 10:53:12.830428 <6>[ 0.095037] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10480 10:53:12.837475 <6>[ 0.095054] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10481 10:53:12.843878 <6>[ 0.095348] Detected PIPT I-cache on CPU5
10482 10:53:12.850679 <6>[ 0.095412] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10483 10:53:12.857016 <6>[ 0.095429] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10484 10:53:12.860435 <6>[ 0.095711] Detected PIPT I-cache on CPU6
10485 10:53:12.869816 <6>[ 0.095776] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10486 10:53:12.876944 <6>[ 0.095793] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10487 10:53:12.879811 <6>[ 0.096097] Detected PIPT I-cache on CPU7
10488 10:53:12.886348 <6>[ 0.096163] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10489 10:53:12.892940 <6>[ 0.096179] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10490 10:53:12.896576 <6>[ 0.096227] smp: Brought up 1 node, 8 CPUs
10491 10:53:12.902911 <6>[ 0.237487] SMP: Total of 8 processors activated.
10492 10:53:12.909536 <6>[ 0.242408] CPU features: detected: 32-bit EL0 Support
10493 10:53:12.916171 <6>[ 0.247804] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10494 10:53:12.923097 <6>[ 0.256603] CPU features: detected: Common not Private translations
10495 10:53:12.929439 <6>[ 0.263119] CPU features: detected: CRC32 instructions
10496 10:53:12.936241 <6>[ 0.268503] CPU features: detected: RCpc load-acquire (LDAPR)
10497 10:53:12.939702 <6>[ 0.274462] CPU features: detected: LSE atomic instructions
10498 10:53:12.945983 <6>[ 0.280243] CPU features: detected: Privileged Access Never
10499 10:53:12.953058 <6>[ 0.286023] CPU features: detected: RAS Extension Support
10500 10:53:12.959354 <6>[ 0.291631] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10501 10:53:12.962502 <6>[ 0.298852] CPU: All CPU(s) started at EL2
10502 10:53:12.969058 <6>[ 0.303194] alternatives: applying system-wide alternatives
10503 10:53:12.979146 <6>[ 0.313926] devtmpfs: initialized
10504 10:53:12.994341 <6>[ 0.322696] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10505 10:53:13.001108 <6>[ 0.332653] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10506 10:53:13.008010 <6>[ 0.340896] pinctrl core: initialized pinctrl subsystem
10507 10:53:13.011212 <6>[ 0.347559] DMI not present or invalid.
10508 10:53:13.017729 <6>[ 0.351875] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10509 10:53:13.027366 <6>[ 0.358760] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10510 10:53:13.034017 <6>[ 0.366334] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10511 10:53:13.043922 <6>[ 0.374562] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10512 10:53:13.047616 <6>[ 0.382802] audit: initializing netlink subsys (disabled)
10513 10:53:13.057083 <5>[ 0.388496] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10514 10:53:13.063663 <6>[ 0.389206] thermal_sys: Registered thermal governor 'step_wise'
10515 10:53:13.069950 <6>[ 0.396461] thermal_sys: Registered thermal governor 'power_allocator'
10516 10:53:13.073246 <6>[ 0.402714] cpuidle: using governor menu
10517 10:53:13.080252 <6>[ 0.413672] NET: Registered PF_QIPCRTR protocol family
10518 10:53:13.086440 <6>[ 0.419158] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10519 10:53:13.093751 <6>[ 0.426261] ASID allocator initialised with 32768 entries
10520 10:53:13.096841 <6>[ 0.432826] Serial: AMBA PL011 UART driver
10521 10:53:13.107149 <4>[ 0.441531] Trying to register duplicate clock ID: 134
10522 10:53:13.160436 <6>[ 0.498737] KASLR enabled
10523 10:53:13.175038 <6>[ 0.506414] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10524 10:53:13.181505 <6>[ 0.513424] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10525 10:53:13.187956 <6>[ 0.519914] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10526 10:53:13.194695 <6>[ 0.526920] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10527 10:53:13.201615 <6>[ 0.533407] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10528 10:53:13.207972 <6>[ 0.540413] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10529 10:53:13.214593 <6>[ 0.546900] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10530 10:53:13.221151 <6>[ 0.553903] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10531 10:53:13.224459 <6>[ 0.561369] ACPI: Interpreter disabled.
10532 10:53:13.233221 <6>[ 0.567788] iommu: Default domain type: Translated
10533 10:53:13.239402 <6>[ 0.572900] iommu: DMA domain TLB invalidation policy: strict mode
10534 10:53:13.243107 <5>[ 0.579557] SCSI subsystem initialized
10535 10:53:13.249484 <6>[ 0.583793] usbcore: registered new interface driver usbfs
10536 10:53:13.256111 <6>[ 0.589524] usbcore: registered new interface driver hub
10537 10:53:13.259507 <6>[ 0.595077] usbcore: registered new device driver usb
10538 10:53:13.266410 <6>[ 0.601171] pps_core: LinuxPPS API ver. 1 registered
10539 10:53:13.276033 <6>[ 0.606367] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10540 10:53:13.279689 <6>[ 0.615710] PTP clock support registered
10541 10:53:13.282642 <6>[ 0.619943] EDAC MC: Ver: 3.0.0
10542 10:53:13.290482 <6>[ 0.625136] FPGA manager framework
10543 10:53:13.296991 <6>[ 0.628812] Advanced Linux Sound Architecture Driver Initialized.
10544 10:53:13.300438 <6>[ 0.635576] vgaarb: loaded
10545 10:53:13.306529 <6>[ 0.638739] clocksource: Switched to clocksource arch_sys_counter
10546 10:53:13.309899 <5>[ 0.645186] VFS: Disk quotas dquot_6.6.0
10547 10:53:13.316610 <6>[ 0.649371] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10548 10:53:13.320407 <6>[ 0.656561] pnp: PnP ACPI: disabled
10549 10:53:13.328498 <6>[ 0.663296] NET: Registered PF_INET protocol family
10550 10:53:13.338798 <6>[ 0.668892] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10551 10:53:13.349919 <6>[ 0.681194] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10552 10:53:13.359504 <6>[ 0.690012] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10553 10:53:13.366479 <6>[ 0.697986] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10554 10:53:13.375990 <6>[ 0.706683] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10555 10:53:13.382787 <6>[ 0.716421] TCP: Hash tables configured (established 65536 bind 65536)
10556 10:53:13.388790 <6>[ 0.723274] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 10:53:13.398811 <6>[ 0.730468] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10558 10:53:13.405592 <6>[ 0.738168] NET: Registered PF_UNIX/PF_LOCAL protocol family
10559 10:53:13.412284 <6>[ 0.744330] RPC: Registered named UNIX socket transport module.
10560 10:53:13.415332 <6>[ 0.750485] RPC: Registered udp transport module.
10561 10:53:13.421842 <6>[ 0.755417] RPC: Registered tcp transport module.
10562 10:53:13.428440 <6>[ 0.760349] RPC: Registered tcp NFSv4.1 backchannel transport module.
10563 10:53:13.431895 <6>[ 0.767018] PCI: CLS 0 bytes, default 64
10564 10:53:13.435022 <6>[ 0.771396] Unpacking initramfs...
10565 10:53:13.451642 <6>[ 0.783267] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10566 10:53:13.461797 <6>[ 0.791940] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10567 10:53:13.465334 <6>[ 0.800784] kvm [1]: IPA Size Limit: 40 bits
10568 10:53:13.472102 <6>[ 0.805313] kvm [1]: GICv3: no GICV resource entry
10569 10:53:13.475159 <6>[ 0.810333] kvm [1]: disabling GICv2 emulation
10570 10:53:13.481803 <6>[ 0.815017] kvm [1]: GIC system register CPU interface enabled
10571 10:53:13.485029 <6>[ 0.821174] kvm [1]: vgic interrupt IRQ18
10572 10:53:13.491333 <6>[ 0.825541] kvm [1]: VHE mode initialized successfully
10573 10:53:13.498419 <5>[ 0.831969] Initialise system trusted keyrings
10574 10:53:13.504421 <6>[ 0.836772] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10575 10:53:13.511946 <6>[ 0.846738] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10576 10:53:13.518375 <5>[ 0.853116] NFS: Registering the id_resolver key type
10577 10:53:13.521828 <5>[ 0.858418] Key type id_resolver registered
10578 10:53:13.528306 <5>[ 0.862831] Key type id_legacy registered
10579 10:53:13.534793 <6>[ 0.867123] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10580 10:53:13.541656 <6>[ 0.874043] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10581 10:53:13.548194 <6>[ 0.881770] 9p: Installing v9fs 9p2000 file system support
10582 10:53:13.584426 <5>[ 0.919210] Key type asymmetric registered
10583 10:53:13.587947 <5>[ 0.923544] Asymmetric key parser 'x509' registered
10584 10:53:13.597703 <6>[ 0.928687] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10585 10:53:13.601262 <6>[ 0.936302] io scheduler mq-deadline registered
10586 10:53:13.603928 <6>[ 0.941076] io scheduler kyber registered
10587 10:53:13.622753 <6>[ 0.957850] EINJ: ACPI disabled.
10588 10:53:13.655806 <4>[ 0.983676] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 10:53:13.665431 <4>[ 0.994304] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 10:53:13.680346 <6>[ 1.015077] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10591 10:53:13.688159 <6>[ 1.023001] printk: console [ttyS0] disabled
10592 10:53:13.716169 <6>[ 1.047670] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10593 10:53:13.722558 <6>[ 1.057146] printk: console [ttyS0] enabled
10594 10:53:13.726230 <6>[ 1.057146] printk: console [ttyS0] enabled
10595 10:53:13.732749 <6>[ 1.066047] printk: bootconsole [mtk8250] disabled
10596 10:53:13.735751 <6>[ 1.066047] printk: bootconsole [mtk8250] disabled
10597 10:53:13.742782 <6>[ 1.077315] SuperH (H)SCI(F) driver initialized
10598 10:53:13.745685 <6>[ 1.082588] msm_serial: driver initialized
10599 10:53:13.760458 <6>[ 1.091528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10600 10:53:13.769943 <6>[ 1.100077] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10601 10:53:13.776811 <6>[ 1.108620] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10602 10:53:13.786431 <6>[ 1.117249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10603 10:53:13.796272 <6>[ 1.125955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10604 10:53:13.803560 <6>[ 1.134670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10605 10:53:13.812781 <6>[ 1.143209] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10606 10:53:13.819450 <6>[ 1.152014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10607 10:53:13.829559 <6>[ 1.160561] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10608 10:53:13.841686 <6>[ 1.176174] loop: module loaded
10609 10:53:13.848800 <6>[ 1.182177] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10610 10:53:13.871290 <4>[ 1.205655] mtk-pmic-keys: Failed to locate of_node [id: -1]
10611 10:53:13.877863 <6>[ 1.212669] megasas: 07.719.03.00-rc1
10612 10:53:13.887434 <6>[ 1.222228] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10613 10:53:13.899144 <6>[ 1.234137] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10614 10:53:13.916058 <6>[ 1.250802] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10615 10:53:13.976118 <6>[ 1.304459] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10616 10:53:14.217107 <6>[ 1.551702] Freeing initrd memory: 18164K
10617 10:53:14.228398 <6>[ 1.563143] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10618 10:53:14.239121 <6>[ 1.573941] tun: Universal TUN/TAP device driver, 1.6
10619 10:53:14.242216 <6>[ 1.579986] thunder_xcv, ver 1.0
10620 10:53:14.245900 <6>[ 1.583490] thunder_bgx, ver 1.0
10621 10:53:14.248975 <6>[ 1.586983] nicpf, ver 1.0
10622 10:53:14.259303 <6>[ 1.590990] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10623 10:53:14.262802 <6>[ 1.598465] hns3: Copyright (c) 2017 Huawei Corporation.
10624 10:53:14.269913 <6>[ 1.604051] hclge is initializing
10625 10:53:14.273031 <6>[ 1.607626] e1000: Intel(R) PRO/1000 Network Driver
10626 10:53:14.279646 <6>[ 1.612755] e1000: Copyright (c) 1999-2006 Intel Corporation.
10627 10:53:14.282859 <6>[ 1.618767] e1000e: Intel(R) PRO/1000 Network Driver
10628 10:53:14.289409 <6>[ 1.623983] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10629 10:53:14.295601 <6>[ 1.630171] igb: Intel(R) Gigabit Ethernet Network Driver
10630 10:53:14.302252 <6>[ 1.635821] igb: Copyright (c) 2007-2014 Intel Corporation.
10631 10:53:14.309077 <6>[ 1.641657] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10632 10:53:14.315634 <6>[ 1.648175] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10633 10:53:14.318955 <6>[ 1.654633] sky2: driver version 1.30
10634 10:53:14.325700 <6>[ 1.659624] VFIO - User Level meta-driver version: 0.3
10635 10:53:14.333107 <6>[ 1.667777] usbcore: registered new interface driver usb-storage
10636 10:53:14.339593 <6>[ 1.674219] usbcore: registered new device driver onboard-usb-hub
10637 10:53:14.348461 <6>[ 1.683251] mt6397-rtc mt6359-rtc: registered as rtc0
10638 10:53:14.358832 <6>[ 1.688718] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:53:14 UTC (1685962394)
10639 10:53:14.361429 <6>[ 1.698271] i2c_dev: i2c /dev entries driver
10640 10:53:14.378637 <6>[ 1.709856] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10641 10:53:14.385479 <6>[ 1.720051] sdhci: Secure Digital Host Controller Interface driver
10642 10:53:14.391869 <6>[ 1.726490] sdhci: Copyright(c) Pierre Ossman
10643 10:53:14.398815 <6>[ 1.731878] Synopsys Designware Multimedia Card Interface Driver
10644 10:53:14.401608 <6>[ 1.738450] mmc0: CQHCI version 5.10
10645 10:53:14.408354 <6>[ 1.739033] sdhci-pltfm: SDHCI platform and OF driver helper
10646 10:53:14.415863 <6>[ 1.750300] ledtrig-cpu: registered to indicate activity on CPUs
10647 10:53:14.426258 <6>[ 1.757618] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10648 10:53:14.432329 <6>[ 1.765003] usbcore: registered new interface driver usbhid
10649 10:53:14.436009 <6>[ 1.770831] usbhid: USB HID core driver
10650 10:53:14.442521 <6>[ 1.775079] spi_master spi0: will run message pump with realtime priority
10651 10:53:14.490483 <6>[ 1.818609] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10652 10:53:14.512762 <6>[ 1.836972] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10653 10:53:14.515737 <6>[ 1.850534] mmc0: Command Queue Engine enabled
10654 10:53:14.522560 <6>[ 1.852454] cros-ec-spi spi0.0: Chrome EC device registered
10655 10:53:14.529329 <6>[ 1.855269] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10656 10:53:14.532874 <6>[ 1.868366] mmcblk0: mmc0:0001 DA4128 116 GiB
10657 10:53:14.545695 <6>[ 1.877038] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10658 10:53:14.552056 <6>[ 1.879125] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10659 10:53:14.559003 <6>[ 1.888576] NET: Registered PF_PACKET protocol family
10660 10:53:14.562307 <6>[ 1.893623] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10661 10:53:14.568472 <6>[ 1.897697] 9pnet: Installing 9P2000 support
10662 10:53:14.571571 <6>[ 1.903489] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10663 10:53:14.578528 <5>[ 1.907378] Key type dns_resolver registered
10664 10:53:14.585007 <6>[ 1.913190] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10665 10:53:14.588945 <6>[ 1.917683] registered taskstats version 1
10666 10:53:14.591440 <5>[ 1.928021] Loading compiled-in X.509 certificates
10667 10:53:14.627161 <4>[ 1.955177] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 10:53:14.636640 <4>[ 1.965868] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 10:53:14.646908 <3>[ 1.978608] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10670 10:53:14.659016 <6>[ 1.993959] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10671 10:53:14.666050 <6>[ 2.000705] xhci-mtk 11200000.usb: xHCI Host Controller
10672 10:53:14.672268 <6>[ 2.006204] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10673 10:53:14.683419 <6>[ 2.014059] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10674 10:53:14.689752 <6>[ 2.023509] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10675 10:53:14.695888 <6>[ 2.029688] xhci-mtk 11200000.usb: xHCI Host Controller
10676 10:53:14.702623 <6>[ 2.035187] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10677 10:53:14.709173 <6>[ 2.042845] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10678 10:53:14.716298 <6>[ 2.050753] hub 1-0:1.0: USB hub found
10679 10:53:14.719052 <6>[ 2.054783] hub 1-0:1.0: 1 port detected
10680 10:53:14.729039 <6>[ 2.059135] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10681 10:53:14.732185 <6>[ 2.067930] hub 2-0:1.0: USB hub found
10682 10:53:14.735997 <6>[ 2.071967] hub 2-0:1.0: 1 port detected
10683 10:53:14.744353 <6>[ 2.079153] mtk-msdc 11f70000.mmc: Got CD GPIO
10684 10:53:14.766263 <6>[ 2.097299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10685 10:53:14.772824 <6>[ 2.105369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10686 10:53:14.782284 <4>[ 2.113344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10687 10:53:14.792849 <6>[ 2.123007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10688 10:53:14.799063 <6>[ 2.131096] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10689 10:53:14.805404 <6>[ 2.139125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10690 10:53:14.815791 <6>[ 2.147041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10691 10:53:14.822012 <6>[ 2.154862] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10692 10:53:14.831861 <6>[ 2.162684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10693 10:53:14.841657 <6>[ 2.173319] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10694 10:53:14.848683 <6>[ 2.181697] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10695 10:53:14.858712 <6>[ 2.190049] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10696 10:53:14.868309 <6>[ 2.198392] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10697 10:53:14.875629 <6>[ 2.206737] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10698 10:53:14.885128 <6>[ 2.215081] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10699 10:53:14.891489 <6>[ 2.223424] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10700 10:53:14.901525 <6>[ 2.231766] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10701 10:53:14.907956 <6>[ 2.240109] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10702 10:53:14.918308 <6>[ 2.248460] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10703 10:53:14.924883 <6>[ 2.256804] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10704 10:53:14.934623 <6>[ 2.265149] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10705 10:53:14.941461 <6>[ 2.273492] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10706 10:53:14.950841 <6>[ 2.281836] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10707 10:53:14.957643 <6>[ 2.290179] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10708 10:53:14.963985 <6>[ 2.299119] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10709 10:53:14.971802 <6>[ 2.306603] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10710 10:53:14.978778 <6>[ 2.313693] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10711 10:53:14.988987 <6>[ 2.320836] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10712 10:53:14.995859 <6>[ 2.328149] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10713 10:53:15.005694 <6>[ 2.335092] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10714 10:53:15.012512 <6>[ 2.344234] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10715 10:53:15.022242 <6>[ 2.353362] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10716 10:53:15.032376 <6>[ 2.362665] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10717 10:53:15.042304 <6>[ 2.372141] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10718 10:53:15.052366 <6>[ 2.381616] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10719 10:53:15.061991 <6>[ 2.390743] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10720 10:53:15.068420 <6>[ 2.400216] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10721 10:53:15.078388 <6>[ 2.409343] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10722 10:53:15.088325 <6>[ 2.418646] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10723 10:53:15.098603 <6>[ 2.428812] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10724 10:53:15.108846 <6>[ 2.440697] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10725 10:53:15.115881 <6>[ 2.450887] Trying to probe devices needed for running init ...
10726 10:53:15.147061 <6>[ 2.479021] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10727 10:53:15.301656 <6>[ 2.636255] hub 1-1:1.0: USB hub found
10728 10:53:15.304466 <6>[ 2.640677] hub 1-1:1.0: 4 ports detected
10729 10:53:15.427271 <6>[ 2.759042] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10730 10:53:15.452309 <6>[ 2.787285] hub 2-1:1.0: USB hub found
10731 10:53:15.455729 <6>[ 2.791658] hub 2-1:1.0: 3 ports detected
10732 10:53:15.627268 <6>[ 2.959011] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10733 10:53:15.757918 <6>[ 3.092722] hub 1-1.1:1.0: USB hub found
10734 10:53:15.761071 <6>[ 3.097003] hub 1-1.1:1.0: 4 ports detected
10735 10:53:15.874726 <6>[ 3.206787] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10736 10:53:16.008270 <6>[ 3.343268] hub 1-1.4:1.0: USB hub found
10737 10:53:16.011483 <6>[ 3.347917] hub 1-1.4:1.0: 2 ports detected
10738 10:53:16.087315 <6>[ 3.419013] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10739 10:53:16.275596 <6>[ 3.607011] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10740 10:53:16.359929 <3>[ 3.695222] usb 1-1.1.4: device descriptor read/64, error -32
10741 10:53:16.552037 <3>[ 3.887249] usb 1-1.1.4: device descriptor read/64, error -32
10742 10:53:16.747072 <6>[ 4.079013] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10743 10:53:16.935486 <6>[ 4.267012] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10744 10:53:17.020629 <3>[ 4.355220] usb 1-1.1.4: device descriptor read/64, error -32
10745 10:53:17.212175 <3>[ 4.547220] usb 1-1.1.4: device descriptor read/64, error -32
10746 10:53:17.324328 <6>[ 4.659475] usb 1-1.1-port4: attempt power cycle
10747 10:53:17.411480 <6>[ 4.743011] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10748 10:53:17.935438 <6>[ 5.267011] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10749 10:53:17.941431 <4>[ 5.274465] usb 1-1.1.4: Device not responding to setup address.
10750 10:53:18.152694 <4>[ 5.487274] usb 1-1.1.4: Device not responding to setup address.
10751 10:53:18.363699 <3>[ 5.699001] usb 1-1.1.4: device not accepting address 10, error -71
10752 10:53:18.450734 <6>[ 5.783021] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10753 10:53:18.457526 <4>[ 5.790470] usb 1-1.1.4: Device not responding to setup address.
10754 10:53:18.667770 <4>[ 6.003297] usb 1-1.1.4: Device not responding to setup address.
10755 10:53:18.879533 <3>[ 6.215004] usb 1-1.1.4: device not accepting address 11, error -71
10756 10:53:18.886731 <3>[ 6.221954] usb 1-1.1-port4: unable to enumerate USB device
10757 10:53:27.392666 <6>[ 14.731486] ALSA device list:
10758 10:53:27.398937 <6>[ 14.734721] No soundcards found.
10759 10:53:27.411336 <6>[ 14.747150] Freeing unused kernel memory: 8384K
10760 10:53:27.414327 <6>[ 14.752084] Run /init as init process
10761 10:53:27.426619 Loading, please wait...
10762 10:53:27.454429 Starting systemd-udevd version 252.6-1
10763 10:53:27.873853 <6>[ 15.206340] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10764 10:53:27.880647 <6>[ 15.214170] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10765 10:53:27.891142 <6>[ 15.223941] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10766 10:53:27.901161 <3>[ 15.226060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 10:53:27.908124 <3>[ 15.240878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 10:53:27.917498 <3>[ 15.249036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 10:53:27.924507 <6>[ 15.252350] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10770 10:53:27.931281 <3>[ 15.257319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 10:53:27.937555 <6>[ 15.257832] mc: Linux media interface: v0.10
10772 10:53:27.941175 <6>[ 15.259663] usbcore: registered new interface driver r8152
10773 10:53:27.948210 <6>[ 15.267807] remoteproc remoteproc0: scp is available
10774 10:53:27.954309 <3>[ 15.272620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 10:53:27.960869 <6>[ 15.273662] videodev: Linux video capture interface: v2.00
10776 10:53:27.967507 <4>[ 15.274550] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10777 10:53:27.977794 <4>[ 15.274653] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10778 10:53:27.986886 <4>[ 15.277314] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10779 10:53:27.993399 <6>[ 15.283375] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10780 10:53:28.000327 <6>[ 15.283468] usbcore: registered new interface driver cdc_ether
10781 10:53:28.007344 <3>[ 15.283503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 10:53:28.014155 <3>[ 15.283517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 10:53:28.024260 <3>[ 15.283525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 10:53:28.031007 <3>[ 15.283568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 10:53:28.041257 <3>[ 15.283606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 10:53:28.047732 <3>[ 15.283613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 10:53:28.054662 <3>[ 15.283619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 10:53:28.064996 <3>[ 15.283661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 10:53:28.071239 <3>[ 15.283668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 10:53:28.080575 <3>[ 15.283674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 10:53:28.087103 <3>[ 15.283680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 10:53:28.097017 <3>[ 15.283686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 10:53:28.103847 <3>[ 15.283719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 10:53:28.110532 <6>[ 15.288155] remoteproc remoteproc0: powering up scp
10795 10:53:28.117201 <4>[ 15.315242] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10796 10:53:28.123743 <4>[ 15.315242] Fallback method does not support PEC.
10797 10:53:28.133489 <4>[ 15.316594] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10798 10:53:28.140165 <6>[ 15.343286] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10799 10:53:28.146728 <3>[ 15.348179] remoteproc remoteproc0: request_firmware failed: -2
10800 10:53:28.156791 <3>[ 15.352024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 10:53:28.163607 <6>[ 15.356209] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10802 10:53:28.169779 <6>[ 15.356216] pci_bus 0000:00: root bus resource [bus 00-ff]
10803 10:53:28.176451 <6>[ 15.356224] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10804 10:53:28.186092 <6>[ 15.356229] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10805 10:53:28.193026 <6>[ 15.356263] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10806 10:53:28.199493 <3>[ 15.379248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10807 10:53:28.209187 <6>[ 15.380537] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10808 10:53:28.215809 <6>[ 15.384482] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10809 10:53:28.226128 <6>[ 15.395177] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10810 10:53:28.232284 <6>[ 15.396743] pci 0000:00:00.0: supports D1 D2
10811 10:53:28.242561 <6>[ 15.405156] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10812 10:53:28.249480 <6>[ 15.412977] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10813 10:53:28.253098 <6>[ 15.437746] usbcore: registered new interface driver r8153_ecm
10814 10:53:28.259010 <6>[ 15.446862] Bluetooth: Core ver 2.22
10815 10:53:28.265615 <6>[ 15.447702] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10816 10:53:28.271986 <6>[ 15.447861] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10817 10:53:28.278937 <6>[ 15.447895] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10818 10:53:28.288183 <6>[ 15.447917] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10819 10:53:28.295037 <6>[ 15.447935] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10820 10:53:28.298557 <6>[ 15.448058] pci 0000:01:00.0: supports D1 D2
10821 10:53:28.305316 <6>[ 15.448063] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10822 10:53:28.311763 <6>[ 15.459044] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10823 10:53:28.318234 <6>[ 15.464303] NET: Registered PF_BLUETOOTH protocol family
10824 10:53:28.325423 <6>[ 15.465673] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10825 10:53:28.338360 <6>[ 15.467520] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10826 10:53:28.345124 <6>[ 15.467789] usbcore: registered new interface driver uvcvideo
10827 10:53:28.351353 <4>[ 15.469753] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10828 10:53:28.361524 <4>[ 15.469764] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10829 10:53:28.367850 <6>[ 15.474097] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10830 10:53:28.374896 <6>[ 15.481481] Bluetooth: HCI device and connection manager initialized
10831 10:53:28.384137 <6>[ 15.487621] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10832 10:53:28.387667 <6>[ 15.496352] Bluetooth: HCI socket layer initialized
10833 10:53:28.394197 <6>[ 15.497124] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10834 10:53:28.403952 <6>[ 15.503231] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10835 10:53:28.410936 <6>[ 15.503248] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10836 10:53:28.420473 <6>[ 15.503264] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10837 10:53:28.423858 <6>[ 15.503281] pci 0000:00:00.0: PCI bridge to [bus 01]
10838 10:53:28.430797 <6>[ 15.509028] Bluetooth: L2CAP socket layer initialized
10839 10:53:28.437270 <6>[ 15.516136] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10840 10:53:28.443791 <6>[ 15.526053] Bluetooth: SCO socket layer initialized
10841 10:53:28.450460 <6>[ 15.532608] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10842 10:53:28.453567 <6>[ 15.539058] r8152 1-1.1.1:1.0 eth0: v1.12.13
10843 10:53:28.460288 <6>[ 15.548901] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10844 10:53:28.467082 <6>[ 15.558913] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10845 10:53:28.473326 <6>[ 15.588977] usbcore: registered new interface driver btusb
10846 10:53:28.483332 <4>[ 15.589799] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10847 10:53:28.490040 <3>[ 15.589808] Bluetooth: hci0: Failed to load firmware file (-2)
10848 10:53:28.493271 <3>[ 15.589810] Bluetooth: hci0: Failed to set up firmware (-2)
10849 10:53:28.503313 <4>[ 15.589814] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10850 10:53:28.509591 <6>[ 15.595222] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10851 10:53:28.527998 <5>[ 15.860855] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10852 10:53:28.550904 <5>[ 15.882515] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10853 10:53:28.556510 <4>[ 15.889423] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10854 10:53:28.563216 <6>[ 15.898308] cfg80211: failed to load regulatory.db
10855 10:53:28.605856 <6>[ 15.938406] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10856 10:53:28.612479 <6>[ 15.945937] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10857 10:53:28.637692 <6>[ 15.972660] mt7921e 0000:01:00.0: ASIC revision: 79610010
10858 10:53:28.741798 <4>[ 16.070980] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 10:53:28.758926 Begin: Loading essential drivers ... done.
10860 10:53:28.761650 Begin: Running /scripts/init-premount ... done.
10861 10:53:28.768402 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10862 10:53:28.777977 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10863 10:53:28.781479 Device /sys/class/net/enxf4f5e850de0a found
10864 10:53:28.782049 done.
10865 10:53:28.807073 Begin: Waiting up to 180 secs for any network device to become available ... done.
10866 10:53:28.838426 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10867 10:53:28.860100 <4>[ 16.189535] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10868 10:53:28.979620 <4>[ 16.308650] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 10:53:29.095170 <4>[ 16.424430] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10870 10:53:29.211059 <4>[ 16.540504] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10871 10:53:29.327202 <4>[ 16.656384] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 10:53:29.442812 <4>[ 16.772358] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10873 10:53:29.559051 <4>[ 16.888283] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10874 10:53:29.675146 <4>[ 17.004288] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10875 10:53:29.790582 <4>[ 17.120221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10876 10:53:29.856557 IP-Config: no response after 2 s<6>[ 17.191429] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10877 10:53:29.857143 ecs - giving up
10878 10:53:29.890275 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10879 10:53:29.899146 <3>[ 17.235193] mt7921e 0000:01:00.0: hardware init failed
10880 10:53:30.993571 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10881 10:53:30.999986 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10882 10:53:31.006631 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10883 10:53:31.013155 host : mt8192-asurada-spherion-r0-cbg-9
10884 10:53:31.019470 domain : lava-rack
10885 10:53:31.025898 rootserver: 192.168.201.1 rootpath:
10886 10:53:31.026071 filename :
10887 10:53:31.043077 done.
10888 10:53:31.051010 Begin: Running /scripts/nfs-bottom ... done.
10889 10:53:31.070672 Begin: Running /scripts/init-bottom ... done.
10890 10:53:32.328413 <6>[ 19.665039] NET: Registered PF_INET6 protocol family
10891 10:53:32.335493 <6>[ 19.672219] Segment Routing with IPv6
10892 10:53:32.338662 <6>[ 19.676223] In-situ OAM (IOAM) with IPv6
10893 10:53:32.507967 <30>[ 19.817754] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10894 10:53:32.514244 <30>[ 19.850114] systemd[1]: Detected architecture arm64.
10895 10:53:32.521706
10896 10:53:32.524214 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10897 10:53:32.524683
10898 10:53:32.548156 <30>[ 19.884706] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10899 10:53:33.294113 <30>[ 20.627677] systemd[1]: Queued start job for default target graphical.target.
10900 10:53:33.320147 <30>[ 20.653253] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10901 10:53:33.326623 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10902 10:53:33.347025 <30>[ 20.679850] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10903 10:53:33.356485 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10904 10:53:33.374807 <30>[ 20.707738] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10905 10:53:33.384815 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10906 10:53:33.403332 <30>[ 20.736185] systemd[1]: Created slice user.slice - User and Session Slice.
10907 10:53:33.409187 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10908 10:53:33.429341 <30>[ 20.759273] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10909 10:53:33.439670 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10910 10:53:33.457312 <30>[ 20.787162] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10911 10:53:33.464129 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10912 10:53:33.492444 <30>[ 20.815462] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10913 10:53:33.502537 <30>[ 20.835319] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10914 10:53:33.508440 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10915 10:53:33.525954 <30>[ 20.859352] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10916 10:53:33.536245 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10917 10:53:33.550572 <30>[ 20.887251] systemd[1]: Reached target paths.target - Path Units.
10918 10:53:33.560617 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10919 10:53:33.578284 <30>[ 20.911343] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10920 10:53:33.584882 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10921 10:53:33.598706 <30>[ 20.935033] systemd[1]: Reached target slices.target - Slice Units.
10922 10:53:33.608982 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10923 10:53:33.622726 <30>[ 20.959359] systemd[1]: Reached target swap.target - Swaps.
10924 10:53:33.629777 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10925 10:53:33.650043 <30>[ 20.983118] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10926 10:53:33.659650 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10927 10:53:33.678408 <30>[ 21.011317] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10928 10:53:33.688387 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10929 10:53:33.707995 <30>[ 21.040959] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10930 10:53:33.717806 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10931 10:53:33.735294 <30>[ 21.068320] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10932 10:53:33.745148 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10933 10:53:33.762472 <30>[ 21.095366] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10934 10:53:33.768672 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10935 10:53:33.787735 <30>[ 21.120429] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10936 10:53:33.797376 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10937 10:53:33.816903 <30>[ 21.149707] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10938 10:53:33.826328 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10939 10:53:33.842426 <30>[ 21.175764] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10940 10:53:33.852921 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10941 10:53:33.894020 <30>[ 21.227273] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10942 10:53:33.900587 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10943 10:53:33.924653 <30>[ 21.257991] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10944 10:53:33.930898 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10945 10:53:33.981849 <30>[ 21.315057] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10946 10:53:33.988638 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10947 10:53:34.016697 <30>[ 21.343223] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10948 10:53:34.028728 <30>[ 21.362108] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10949 10:53:34.038795 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10950 10:53:34.061034 <30>[ 21.394020] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10951 10:53:34.067493 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10952 10:53:34.088666 <30>[ 21.422006] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10953 10:53:34.095505 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10954 10:53:34.116663 <30>[ 21.450304] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10955 10:53:34.123399 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10956 10:53:34.132934 <6>[ 21.464415] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10957 10:53:34.133080
10958 10:53:34.145001 <30>[ 21.478596] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10959 10:53:34.151510 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10960 10:53:34.177401 <30>[ 21.510127] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10961 10:53:34.182964 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10962 10:53:34.205018 <30>[ 21.538680] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10963 10:53:34.212013 Starting [0;1;39mmodpr<6>[ 21.549247] fuse: init (API version 7.37)
10964 10:53:34.214968 obe@loop.ser…e[0m - Load Kernel Module loop...
10965 10:53:34.238812 <30>[ 21.572144] systemd[1]: Starting systemd-journald.service - Journal Service...
10966 10:53:34.245070 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10967 10:53:34.268381 <30>[ 21.602002] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10968 10:53:34.275174 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10969 10:53:34.299912 <30>[ 21.630324] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10970 10:53:34.306349 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10971 10:53:34.353869 <30>[ 21.687681] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10972 10:53:34.364182 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10973 10:53:34.386183 <30>[ 21.718956] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10974 10:53:34.398965 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug Al<3>[ 21.732301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 10:53:34.402148 l udev Devices...
10976 10:53:34.425491 <30>[ 21.758580] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10977 10:53:34.436102 [[0;32m OK [0m] Mounted [0;<3>[ 21.767673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 10:53:34.442215 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10979 10:53:34.457650 <30>[ 21.791504] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10980 10:53:34.464627 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10981 10:53:34.482037 <30>[ 21.815421] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10982 10:53:34.488650 <3>[ 21.818323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 10:53:34.499153 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10984 10:53:34.518500 <30>[ 21.852003] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10985 10:53:34.528252 <3>[ 21.858034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 10:53:34.535104 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10987 10:53:34.555306 <30>[ 21.888131] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10988 10:53:34.561940 <3>[ 21.895581] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 10:53:34.572553 <30>[ 21.895994] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10990 10:53:34.579085 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10991 10:53:34.593160 <3>[ 21.926784] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 10:53:34.603572 <30>[ 21.936729] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10993 10:53:34.610307 <30>[ 21.944474] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10994 10:53:34.623494 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 21.956745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 10:53:34.626881 m_mod.s…e[0m - Load Kernel Module dm_mod.
10996 10:53:34.644632 <30>[ 21.980064] systemd[1]: modprobe@drm.service: Deactivated successfully.
10997 10:53:34.654119 <3>[ 21.986843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 10:53:34.660923 <30>[ 21.987465] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10999 10:53:34.671074 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11000 10:53:34.687371 <30>[ 22.020267] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11001 10:53:34.693873 <3>[ 22.022309] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 10:53:34.703757 <30>[ 22.028423] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11003 10:53:34.713742 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11004 10:53:34.728143 <3>[ 22.061209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 10:53:34.738133 <30>[ 22.071405] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11006 10:53:34.744911 <30>[ 22.078988] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11007 10:53:34.754638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11008 10:53:34.771138 <30>[ 22.104104] systemd[1]: modprobe@loop.service: Deactivated successfully.
11009 10:53:34.777332 <30>[ 22.111617] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11010 10:53:34.784594 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11011 10:53:34.802147 <30>[ 22.135518] systemd[1]: Started systemd-journald.service - Journal Service.
11012 10:53:34.808898 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11013 10:53:34.827921 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11014 10:53:34.846953 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11015 10:53:34.871881 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11016 10:53:34.891560 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11017 10:53:34.934348 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11018 10:53:34.956820 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11019 10:53:34.978078 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11020 10:53:35.004214 <4>[ 22.331333] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11021 10:53:35.014009 <3>[ 22.347032] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11022 10:53:35.020668 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11023 10:53:35.048741 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11024 10:53:35.063889 <46>[ 22.397837] systemd-journald[298]: Received client request to flush runtime journal.
11025 10:53:35.076871 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11026 10:53:35.372420 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11027 10:53:35.389742 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11028 10:53:35.405065 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11029 10:53:35.421950 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11030 10:53:35.823833 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11031 10:53:36.283069 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11032 10:53:36.321567 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11033 10:53:36.442527 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11034 10:53:36.511174 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11035 10:53:36.529768 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11036 10:53:36.545493 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11037 10:53:36.598492 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11038 10:53:36.620174 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11039 10:53:36.641993 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11040 10:53:36.665502 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11041 10:53:36.677634 See 'systemctl status systemd-binfmt.service' for details.
11042 10:53:36.868712 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11043 10:53:36.950687 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11044 10:53:36.973625 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11045 10:53:37.027020 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11046 10:53:37.119291 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11047 10:53:37.147284 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11048 10:53:37.339842 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11049 10:53:37.433368 <6>[ 24.770301] remoteproc remoteproc0: powering up scp
11050 10:53:37.443088 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11051 10:53:37.454387 <4>[ 24.788130] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11052 10:53:37.461593 <3>[ 24.798123] remoteproc remoteproc0: request_firmware failed: -2
11053 10:53:37.472642 <3>[ 24.805735] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11054 10:53:37.478913 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11055 10:53:37.529872 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11056 10:53:37.549469 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11057 10:53:37.569903 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11058 10:53:37.595161 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11059 10:53:37.627960 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11060 10:53:37.645572 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11061 10:53:37.661267 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11062 10:53:37.677579 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11063 10:53:37.698971 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11064 10:53:37.719303 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11065 10:53:37.737381 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11066 10:53:37.780820 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11067 10:53:37.799778 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11068 10:53:37.817311 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11069 10:53:37.834972 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11070 10:53:37.853396 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11071 10:53:37.869898 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11072 10:53:37.885849 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11073 10:53:37.936229 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11074 10:53:37.967648 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11075 10:53:38.008818 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11076 10:53:38.028588 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11077 10:53:38.050191 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11078 10:53:38.238160 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11079 10:53:38.298504 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11080 10:53:38.319554 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11081 10:53:38.343168 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11082 10:53:38.363376 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11083 10:53:38.383838 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11084 10:53:38.406384 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11085 10:53:38.430864 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11086 10:53:38.455609 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11087 10:53:38.473542 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11088 10:53:38.519047 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11089 10:53:38.539357 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11090 10:53:38.580154 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11091 10:53:38.660902 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11092 10:53:38.733338
11093 10:53:38.733463
11094 10:53:38.736590 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11095 10:53:38.736676
11096 10:53:38.739595 debian-bookworm-arm64 login: root (automatic login)
11097 10:53:38.739682
11098 10:53:38.739748
11099 10:53:38.992056 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11100 10:53:38.992189
11101 10:53:38.998488 The programs included with the Debian GNU/Linux system are free software;
11102 10:53:39.004868 the exact distribution terms for each program are described in the
11103 10:53:39.008847 individual files in /usr/share/doc/*/copyright.
11104 10:53:39.008930
11105 10:53:39.015143 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11106 10:53:39.017959 permitted by applicable law.
11107 10:53:39.871853 Matched prompt #10: / #
11109 10:53:39.873077 Setting prompt string to ['/ #']
11110 10:53:39.873527 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11112 10:53:39.874523 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11113 10:53:39.874961 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11114 10:53:39.875330 Setting prompt string to ['/ #']
11115 10:53:39.875651 Forcing a shell prompt, looking for ['/ #']
11117 10:53:39.926487 / #
11118 10:53:39.927144 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11119 10:53:39.927650 Waiting using forced prompt support (timeout 00:02:30)
11120 10:53:39.932806
11121 10:53:39.933770 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11122 10:53:39.934298 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11124 10:53:40.035473 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby'
11125 10:53:40.040861 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590974/extract-nfsrootfs-bpnc2kby'
11127 10:53:40.141996 / # export NFS_SERVER_IP='192.168.201.1'
11128 10:53:40.148492 export NFS_SERVER_IP='192.168.201.1'
11129 10:53:40.149465 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11130 10:53:40.150044 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11131 10:53:40.150561 end: 2 depthcharge-action (duration 00:01:22) [common]
11132 10:53:40.151049 start: 3 lava-test-retry (timeout 00:07:44) [common]
11133 10:53:40.151546 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
11134 10:53:40.151969 Using namespace: common
11136 10:53:40.253298 / # #
11137 10:53:40.253971 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11138 10:53:40.259806 #
11139 10:53:40.260684 Using /lava-10590974
11141 10:53:40.362052 / # export SHELL=/bin/bash
11142 10:53:40.368933 export SHELL=/bin/bash
11144 10:53:40.470843 / # . /lava-10590974/environment
11145 10:53:40.477700 . /lava-10590974/environment
11147 10:53:40.583083 / # /lava-10590974/bin/lava-test-runner /lava-10590974/0
11148 10:53:40.583733 Test shell timeout: 10s (minimum of the action and connection timeout)
11149 10:53:40.589643 /lava-10590974/bin/lava-test-runner /lava-10590974/0
11150 10:53:40.825753 + export TESTRUN_ID=0_timesync-off
11151 10:53:40.829069 + TESTRUN_ID=0_timesync-off
11152 10:53:40.832493 + cd /lava-10590974/0/tests/0_timesync-off
11153 10:53:40.835625 ++ cat uuid
11154 10:53:40.835743 + UUID=10590974_1.6.2.3.1
11155 10:53:40.838687 + set +x
11156 10:53:40.842175 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10590974_1.6.2.3.1>
11157 10:53:40.842451 Received signal: <STARTRUN> 0_timesync-off 10590974_1.6.2.3.1
11158 10:53:40.842530 Starting test lava.0_timesync-off (10590974_1.6.2.3.1)
11159 10:53:40.842671 Skipping test definition patterns.
11160 10:53:40.845328 + systemctl stop systemd-timesyncd
11161 10:53:40.885441 + set +x
11162 10:53:40.888672 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10590974_1.6.2.3.1>
11163 10:53:40.889038 Received signal: <ENDRUN> 0_timesync-off 10590974_1.6.2.3.1
11164 10:53:40.889214 Ending use of test pattern.
11165 10:53:40.889347 Ending test lava.0_timesync-off (10590974_1.6.2.3.1), duration 0.05
11167 10:53:40.942516 + export TESTRUN_ID=1_kselftest-alsa
11168 10:53:40.945866 + TESTRUN_ID=1_kselftest-alsa
11169 10:53:40.952097 + cd /lava-10590974/0/tests/1_kselftest-alsa
11170 10:53:40.952196 ++ cat uuid
11171 10:53:40.955260 + UUID=10590974_1.6.2.3.5
11172 10:53:40.955399 + set +x
11173 10:53:40.959381 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10590974_1.6.2.3.5>
11174 10:53:40.959672 Received signal: <STARTRUN> 1_kselftest-alsa 10590974_1.6.2.3.5
11175 10:53:40.959767 Starting test lava.1_kselftest-alsa (10590974_1.6.2.3.5)
11176 10:53:40.959916 Skipping test definition patterns.
11177 10:53:40.962439 + cd ./automated/linux/kselftest/
11178 10:53:40.991722 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11179 10:53:41.013904 INFO: install_deps skipped
11180 10:53:41.478691 --2023-06-05 10:53:41-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11181 10:53:41.485437 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11182 10:53:41.630443 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11183 10:53:41.777194 HTTP request sent, awaiting response... 200 OK
11184 10:53:41.780215 Length: 2712696 (2.6M) [application/octet-stream]
11185 10:53:41.783437 Saving to: 'kselftest.tar.xz'
11186 10:53:41.783925
11187 10:53:41.784323
11188 10:53:42.078688 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11189 10:53:42.383788 kselftest.tar.xz 1%[ ] 49.22K 166KB/s
11190 10:53:42.672757 kselftest.tar.xz 5%[> ] 145.38K 243KB/s
11191 10:53:42.969256 kselftest.tar.xz 15%[==> ] 415.46K 470KB/s
11192 10:53:43.261961 kselftest.tar.xz 24%[===> ] 653.03K 555KB/s
11193 10:53:43.584168 kselftest.tar.xz 34%[=====> ] 906.14K 618KB/s
11194 10:53:43.857790 kselftest.tar.xz 43%[=======> ] 1.13M 646KB/s
11195 10:53:44.143879 kselftest.tar.xz 50%[=========> ] 1.30M 646KB/s
11196 10:53:44.438052 kselftest.tar.xz 57%[==========> ] 1.48M 647KB/s
11197 10:53:44.652612 kselftest.tar.xz 62%[===========> ] 1.61M 628KB/s
11198 10:53:44.883130 kselftest.tar.xz 67%[============> ] 1.75M 630KB/s
11199 10:53:45.092933 kselftest.tar.xz 70%[=============> ] 1.83M 609KB/s eta 1s
11200 10:53:45.322552 kselftest.tar.xz 76%[==============> ] 1.97M 614KB/s eta 1s
11201 10:53:45.535209 kselftest.tar.xz 79%[==============> ] 2.05M 599KB/s eta 1s
11202 10:53:45.762701 kselftest.tar.xz 84%[===============> ] 2.19M 603KB/s eta 1s
11203 10:53:45.974090 kselftest.tar.xz 88%[================> ] 2.28M 592KB/s eta 1s
11204 10:53:46.205419 kselftest.tar.xz 93%[=================> ] 2.42M 620KB/s eta 0s
11205 10:53:46.351633 kselftest.tar.xz 97%[==================> ] 2.51M 641KB/s eta 0s
11206 10:53:46.358095 kselftest.tar.xz 100%[===================>] 2.59M 612KB/s in 4.5s
11207 10:53:46.358632
11208 10:53:46.592196 2023-06-05 10:53:46 (585 KB/s) - 'kselftest.tar.xz' saved [2712696/2712696]
11209 10:53:46.592351
11210 10:53:51.330242 skiplist:
11211 10:53:51.333285 ========================================
11212 10:53:51.336810 ========================================
11213 10:53:51.370279 alsa:mixer-test
11214 10:53:51.386353 ============== Tests to run ===============
11215 10:53:51.386484 alsa:mixer-test
11216 10:53:51.389740 ===========End Tests to run ===============
11217 10:53:51.476459 <12>[ 38.815606] kselftest: Running tests in alsa
11218 10:53:51.484314 TAP version 13
11219 10:53:51.497590 1..1
11220 10:53:51.509595 # selftests: alsa: mixer-test
11221 10:53:51.938363 # TAP version 13
11222 10:53:51.938942 # 1..0
11223 10:53:51.945214 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11224 10:53:51.948378 ok 1 selftests: alsa: mixer-test
11225 10:53:52.590085 alsa_mixer-test pass
11226 10:53:52.622131 + ../../utils/send-to-lava.sh ./output/result.txt
11227 10:53:52.685651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11228 10:53:52.686126 + set +x
11229 10:53:52.686748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11231 10:53:52.691655 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10590974_1.6.2.3.5>
11232 10:53:52.692369 Received signal: <ENDRUN> 1_kselftest-alsa 10590974_1.6.2.3.5
11233 10:53:52.692818 Ending use of test pattern.
11234 10:53:52.693187 Ending test lava.1_kselftest-alsa (10590974_1.6.2.3.5), duration 11.73
11236 10:53:52.695287 <LAVA_TEST_RUNNER EXIT>
11237 10:53:52.695966 ok: lava_test_shell seems to have completed
11238 10:53:52.696466 alsa_mixer-test: pass
11239 10:53:52.696951 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11240 10:53:52.697402 end: 3 lava-test-retry (duration 00:00:13) [common]
11241 10:53:52.697841 start: 4 finalize (timeout 00:07:31) [common]
11242 10:53:52.698295 start: 4.1 power-off (timeout 00:00:30) [common]
11243 10:53:52.699055 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11244 10:53:52.818348 >> Command sent successfully.
11245 10:53:52.823042 Returned 0 in 0 seconds
11246 10:53:52.923978 end: 4.1 power-off (duration 00:00:00) [common]
11248 10:53:52.925828 start: 4.2 read-feedback (timeout 00:07:31) [common]
11249 10:53:52.927102 Listened to connection for namespace 'common' for up to 1s
11250 10:53:53.927123 Finalising connection for namespace 'common'
11251 10:53:53.927907 Disconnecting from shell: Finalise
11252 10:53:53.928470 / #
11253 10:53:54.029468 end: 4.2 read-feedback (duration 00:00:01) [common]
11254 10:53:54.029740 end: 4 finalize (duration 00:00:01) [common]
11255 10:53:54.029951 Cleaning after the job
11256 10:53:54.030123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/ramdisk
11257 10:53:54.033914 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/kernel
11258 10:53:54.049738 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/dtb
11259 10:53:54.050061 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/nfsrootfs
11260 10:53:54.130799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590974/tftp-deploy-5p_k0bha/modules
11261 10:53:54.135804 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10590974
11262 10:53:54.656255 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10590974
11263 10:53:54.656439 Job finished correctly