Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 10:54:51.528636 lava-dispatcher, installed at version: 2023.05.1
2 10:54:51.528836 start: 0 validate
3 10:54:51.528968 Start time: 2023-06-05 10:54:51.528960+00:00 (UTC)
4 10:54:51.529100 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:54:51.529231 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:54:51.816528 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:54:51.816711 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:54:52.097962 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:54:52.098190 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:54:52.390690 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:54:52.390885 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:54:52.674384 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:54:52.674556 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:54:52.969029 validate duration: 1.44
16 10:54:52.969355 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:54:52.969455 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:54:52.969577 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:54:52.969706 Not decompressing ramdisk as can be used compressed.
20 10:54:52.969825 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:54:52.969892 saving as /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/ramdisk/initrd.cpio.gz
22 10:54:52.969986 total size: 4665601 (4MB)
23 10:54:52.971205 progress 0% (0MB)
24 10:54:52.972554 progress 5% (0MB)
25 10:54:52.973855 progress 10% (0MB)
26 10:54:52.975161 progress 15% (0MB)
27 10:54:52.976471 progress 20% (0MB)
28 10:54:52.977838 progress 25% (1MB)
29 10:54:52.979129 progress 30% (1MB)
30 10:54:52.980432 progress 35% (1MB)
31 10:54:52.981712 progress 40% (1MB)
32 10:54:52.983147 progress 45% (2MB)
33 10:54:52.984484 progress 50% (2MB)
34 10:54:52.985813 progress 55% (2MB)
35 10:54:52.987096 progress 60% (2MB)
36 10:54:52.988375 progress 65% (2MB)
37 10:54:52.989645 progress 70% (3MB)
38 10:54:52.990952 progress 75% (3MB)
39 10:54:52.992211 progress 80% (3MB)
40 10:54:52.993634 progress 85% (3MB)
41 10:54:52.994941 progress 90% (4MB)
42 10:54:52.996180 progress 95% (4MB)
43 10:54:52.997463 progress 100% (4MB)
44 10:54:52.997656 4MB downloaded in 0.03s (160.83MB/s)
45 10:54:52.997843 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:54:52.998136 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:54:52.998253 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:54:52.998370 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:54:52.998511 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:54:52.998586 saving as /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/kernel/Image
52 10:54:52.998650 total size: 45746688 (43MB)
53 10:54:52.998712 No compression specified
54 10:54:52.999878 progress 0% (0MB)
55 10:54:53.011636 progress 5% (2MB)
56 10:54:53.023418 progress 10% (4MB)
57 10:54:53.035612 progress 15% (6MB)
58 10:54:53.047766 progress 20% (8MB)
59 10:54:53.059732 progress 25% (10MB)
60 10:54:53.071505 progress 30% (13MB)
61 10:54:53.083299 progress 35% (15MB)
62 10:54:53.095226 progress 40% (17MB)
63 10:54:53.107115 progress 45% (19MB)
64 10:54:53.118941 progress 50% (21MB)
65 10:54:53.130578 progress 55% (24MB)
66 10:54:53.142419 progress 60% (26MB)
67 10:54:53.154350 progress 65% (28MB)
68 10:54:53.166059 progress 70% (30MB)
69 10:54:53.177952 progress 75% (32MB)
70 10:54:53.189618 progress 80% (34MB)
71 10:54:53.201431 progress 85% (37MB)
72 10:54:53.213403 progress 90% (39MB)
73 10:54:53.225015 progress 95% (41MB)
74 10:54:53.236520 progress 100% (43MB)
75 10:54:53.236722 43MB downloaded in 0.24s (183.26MB/s)
76 10:54:53.236922 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:54:53.237201 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:54:53.237324 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:54:53.237444 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:54:53.237614 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:54:53.237686 saving as /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/dtb/mt8192-asurada-spherion-r0.dtb
83 10:54:53.237752 total size: 46924 (0MB)
84 10:54:53.237813 No compression specified
85 10:54:53.238996 progress 69% (0MB)
86 10:54:53.239287 progress 100% (0MB)
87 10:54:53.239474 0MB downloaded in 0.00s (26.02MB/s)
88 10:54:53.239632 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:54:53.239900 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:54:53.240018 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:54:53.240132 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:54:53.240282 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:54:53.240352 saving as /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/nfsrootfs/full.rootfs.tar
95 10:54:53.240415 total size: 200770336 (191MB)
96 10:54:53.240477 Using unxz to decompress xz
97 10:54:53.244216 progress 0% (0MB)
98 10:54:53.792057 progress 5% (9MB)
99 10:54:54.369648 progress 10% (19MB)
100 10:54:54.975704 progress 15% (28MB)
101 10:54:55.354072 progress 20% (38MB)
102 10:54:55.691276 progress 25% (47MB)
103 10:54:56.295167 progress 30% (57MB)
104 10:54:56.865616 progress 35% (67MB)
105 10:54:57.456138 progress 40% (76MB)
106 10:54:58.015866 progress 45% (86MB)
107 10:54:58.590029 progress 50% (95MB)
108 10:54:59.210070 progress 55% (105MB)
109 10:54:59.872997 progress 60% (114MB)
110 10:54:59.991240 progress 65% (124MB)
111 10:55:00.132070 progress 70% (134MB)
112 10:55:00.226722 progress 75% (143MB)
113 10:55:00.301062 progress 80% (153MB)
114 10:55:00.370097 progress 85% (162MB)
115 10:55:00.467985 progress 90% (172MB)
116 10:55:00.746070 progress 95% (181MB)
117 10:55:01.322926 progress 100% (191MB)
118 10:55:01.327727 191MB downloaded in 8.09s (23.68MB/s)
119 10:55:01.328037 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:55:01.328362 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:55:01.328481 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:55:01.328570 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:55:01.328706 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:55:01.328780 saving as /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/modules/modules.tar
126 10:55:01.328842 total size: 8542412 (8MB)
127 10:55:01.328904 Using unxz to decompress xz
128 10:55:01.332499 progress 0% (0MB)
129 10:55:01.354157 progress 5% (0MB)
130 10:55:01.379321 progress 10% (0MB)
131 10:55:01.405095 progress 15% (1MB)
132 10:55:01.429949 progress 20% (1MB)
133 10:55:01.455765 progress 25% (2MB)
134 10:55:01.480822 progress 30% (2MB)
135 10:55:01.505941 progress 35% (2MB)
136 10:55:01.531201 progress 40% (3MB)
137 10:55:01.556484 progress 45% (3MB)
138 10:55:01.613728 progress 50% (4MB)
139 10:55:01.637279 progress 55% (4MB)
140 10:55:01.662317 progress 60% (4MB)
141 10:55:01.687472 progress 65% (5MB)
142 10:55:01.712522 progress 70% (5MB)
143 10:55:01.738726 progress 75% (6MB)
144 10:55:01.767986 progress 80% (6MB)
145 10:55:01.790298 progress 85% (6MB)
146 10:55:01.815304 progress 90% (7MB)
147 10:55:01.838641 progress 95% (7MB)
148 10:55:01.862326 progress 100% (8MB)
149 10:55:01.868081 8MB downloaded in 0.54s (15.11MB/s)
150 10:55:01.868366 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:55:01.868629 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:55:01.868722 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:55:01.868811 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:55:05.167903 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r
156 10:55:05.168119 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:55:05.168221 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:55:05.168398 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch
159 10:55:05.168530 makedir: /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin
160 10:55:05.168629 makedir: /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/tests
161 10:55:05.168725 makedir: /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/results
162 10:55:05.168829 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-add-keys
163 10:55:05.168971 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-add-sources
164 10:55:05.169095 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-background-process-start
165 10:55:05.169221 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-background-process-stop
166 10:55:05.169343 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-common-functions
167 10:55:05.169463 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-echo-ipv4
168 10:55:05.169583 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-install-packages
169 10:55:05.169701 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-installed-packages
170 10:55:05.169817 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-os-build
171 10:55:05.169938 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-probe-channel
172 10:55:05.170057 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-probe-ip
173 10:55:05.170174 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-target-ip
174 10:55:05.170295 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-target-mac
175 10:55:05.170412 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-target-storage
176 10:55:05.170531 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-case
177 10:55:05.170650 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-event
178 10:55:05.170767 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-feedback
179 10:55:05.171003 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-raise
180 10:55:05.171124 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-reference
181 10:55:05.171247 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-runner
182 10:55:05.171366 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-set
183 10:55:05.171485 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-test-shell
184 10:55:05.171605 Updating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-add-keys (debian)
185 10:55:05.171764 Updating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-add-sources (debian)
186 10:55:05.171938 Updating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-install-packages (debian)
187 10:55:05.172106 Updating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-installed-packages (debian)
188 10:55:05.172241 Updating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/bin/lava-os-build (debian)
189 10:55:05.172360 Creating /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/environment
190 10:55:05.172457 LAVA metadata
191 10:55:05.172527 - LAVA_JOB_ID=10591009
192 10:55:05.172590 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:55:05.172695 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:55:05.172760 skipped lava-vland-overlay
195 10:55:05.172834 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:55:05.172912 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:55:05.172972 skipped lava-multinode-overlay
198 10:55:05.173042 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:55:05.173119 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:55:05.173191 Loading test definitions
201 10:55:05.173279 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:55:05.173350 Using /lava-10591009 at stage 0
203 10:55:05.173627 uuid=10591009_1.6.2.3.1 testdef=None
204 10:55:05.173714 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:55:05.173798 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:55:05.174234 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:55:05.174457 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:55:05.174995 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:55:05.175222 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:55:05.175743 runner path: /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/0/tests/0_timesync-off test_uuid 10591009_1.6.2.3.1
213 10:55:05.175899 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:55:05.176120 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:55:05.176192 Using /lava-10591009 at stage 0
217 10:55:05.176286 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:55:05.176362 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/0/tests/1_kselftest-arm64'
219 10:55:12.947268 Running '/usr/bin/git checkout kernelci.org
220 10:55:13.092205 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 10:55:13.092940 uuid=10591009_1.6.2.3.5 testdef=None
222 10:55:13.093114 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 10:55:13.093409 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 10:55:13.094207 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:55:13.094453 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 10:55:13.095465 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:55:13.095711 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 10:55:13.096643 runner path: /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/0/tests/1_kselftest-arm64 test_uuid 10591009_1.6.2.3.5
232 10:55:13.096739 BOARD='mt8192-asurada-spherion-r0'
233 10:55:13.096805 BRANCH='cip-gitlab'
234 10:55:13.096865 SKIPFILE='/dev/null'
235 10:55:13.096924 SKIP_INSTALL='True'
236 10:55:13.096980 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:55:13.097037 TST_CASENAME=''
238 10:55:13.097101 TST_CMDFILES='arm64'
239 10:55:13.097247 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:55:13.097494 Creating lava-test-runner.conf files
242 10:55:13.097563 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591009/lava-overlay-z847wzch/lava-10591009/0 for stage 0
243 10:55:13.097657 - 0_timesync-off
244 10:55:13.097726 - 1_kselftest-arm64
245 10:55:13.097821 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 10:55:13.097911 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 10:55:20.558675 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 10:55:20.558826 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 10:55:20.558994 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:55:20.559095 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 10:55:20.559197 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 10:55:20.671996 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:55:20.672353 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 10:55:20.672463 extracting modules file /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r
255 10:55:20.871629 extracting modules file /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591009/extract-overlay-ramdisk-0ugwdzp_/ramdisk
256 10:55:21.073096 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:55:21.073268 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 10:55:21.073359 [common] Applying overlay to NFS
259 10:55:21.073426 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591009/compress-overlay-00wk6lop/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r
260 10:55:22.040660 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:55:22.040831 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 10:55:22.040930 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:55:22.041025 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 10:55:22.041116 Building ramdisk /var/lib/lava/dispatcher/tmp/10591009/extract-overlay-ramdisk-0ugwdzp_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591009/extract-overlay-ramdisk-0ugwdzp_/ramdisk
265 10:55:22.315559 >> 117801 blocks
266 10:55:24.277646 rename /var/lib/lava/dispatcher/tmp/10591009/extract-overlay-ramdisk-0ugwdzp_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/ramdisk/ramdisk.cpio.gz
267 10:55:24.278090 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:55:24.278207 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 10:55:24.278303 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 10:55:24.278405 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/kernel/Image'
271 10:55:35.889722 Returned 0 in 11 seconds
272 10:55:35.990323 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/kernel/image.itb
273 10:55:36.303506 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:55:36.303866 output: Created: Mon Jun 5 11:55:36 2023
275 10:55:36.303943 output: Image 0 (kernel-1)
276 10:55:36.304007 output: Description:
277 10:55:36.304070 output: Created: Mon Jun 5 11:55:36 2023
278 10:55:36.304131 output: Type: Kernel Image
279 10:55:36.304192 output: Compression: lzma compressed
280 10:55:36.304249 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
281 10:55:36.304306 output: Architecture: AArch64
282 10:55:36.304363 output: OS: Linux
283 10:55:36.304419 output: Load Address: 0x00000000
284 10:55:36.304473 output: Entry Point: 0x00000000
285 10:55:36.304527 output: Hash algo: crc32
286 10:55:36.304581 output: Hash value: 8ce42972
287 10:55:36.304633 output: Image 1 (fdt-1)
288 10:55:36.304685 output: Description: mt8192-asurada-spherion-r0
289 10:55:36.304738 output: Created: Mon Jun 5 11:55:36 2023
290 10:55:36.304790 output: Type: Flat Device Tree
291 10:55:36.304848 output: Compression: uncompressed
292 10:55:36.304918 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:55:36.304972 output: Architecture: AArch64
294 10:55:36.305025 output: Hash algo: crc32
295 10:55:36.305077 output: Hash value: 1df858fa
296 10:55:36.305130 output: Image 2 (ramdisk-1)
297 10:55:36.305182 output: Description: unavailable
298 10:55:36.305234 output: Created: Mon Jun 5 11:55:36 2023
299 10:55:36.305287 output: Type: RAMDisk Image
300 10:55:36.305339 output: Compression: Unknown Compression
301 10:55:36.305392 output: Data Size: 17641973 Bytes = 17228.49 KiB = 16.82 MiB
302 10:55:36.305444 output: Architecture: AArch64
303 10:55:36.305496 output: OS: Linux
304 10:55:36.305548 output: Load Address: unavailable
305 10:55:36.305600 output: Entry Point: unavailable
306 10:55:36.305652 output: Hash algo: crc32
307 10:55:36.305704 output: Hash value: 9d79f6f1
308 10:55:36.305756 output: Default Configuration: 'conf-1'
309 10:55:36.305808 output: Configuration 0 (conf-1)
310 10:55:36.305859 output: Description: mt8192-asurada-spherion-r0
311 10:55:36.305911 output: Kernel: kernel-1
312 10:55:36.305963 output: Init Ramdisk: ramdisk-1
313 10:55:36.306015 output: FDT: fdt-1
314 10:55:36.306067 output: Loadables: kernel-1
315 10:55:36.306119 output:
316 10:55:36.306313 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:55:36.306407 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:55:36.306506 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 10:55:36.306602 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 10:55:36.306679 No LXC device requested
321 10:55:36.306755 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:55:36.306842 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 10:55:36.306951 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:55:36.307021 Checking files for TFTP limit of 4294967296 bytes.
325 10:55:36.307507 end: 1 tftp-deploy (duration 00:00:43) [common]
326 10:55:36.307610 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:55:36.307700 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:55:36.307827 substitutions:
329 10:55:36.307897 - {DTB}: 10591009/tftp-deploy-3jx6k2xn/dtb/mt8192-asurada-spherion-r0.dtb
330 10:55:36.307962 - {INITRD}: 10591009/tftp-deploy-3jx6k2xn/ramdisk/ramdisk.cpio.gz
331 10:55:36.308021 - {KERNEL}: 10591009/tftp-deploy-3jx6k2xn/kernel/Image
332 10:55:36.308078 - {LAVA_MAC}: None
333 10:55:36.308134 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r
334 10:55:36.308189 - {NFS_SERVER_IP}: 192.168.201.1
335 10:55:36.308243 - {PRESEED_CONFIG}: None
336 10:55:36.308296 - {PRESEED_LOCAL}: None
337 10:55:36.308350 - {RAMDISK}: 10591009/tftp-deploy-3jx6k2xn/ramdisk/ramdisk.cpio.gz
338 10:55:36.308404 - {ROOT_PART}: None
339 10:55:36.308459 - {ROOT}: None
340 10:55:36.308514 - {SERVER_IP}: 192.168.201.1
341 10:55:36.308568 - {TEE}: None
342 10:55:36.308622 Parsed boot commands:
343 10:55:36.308675 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:55:36.308843 Parsed boot commands: tftpboot 192.168.201.1 10591009/tftp-deploy-3jx6k2xn/kernel/image.itb 10591009/tftp-deploy-3jx6k2xn/kernel/cmdline
345 10:55:36.308934 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:55:36.309014 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:55:36.309103 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:55:36.309191 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:55:36.309261 Not connected, no need to disconnect.
350 10:55:36.309332 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:55:36.309412 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:55:36.309478 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
353 10:55:36.312879 Setting prompt string to ['lava-test: # ']
354 10:55:36.313228 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:55:36.313332 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:55:36.313429 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:55:36.313517 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:55:36.313725 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 10:55:41.449219 >> Command sent successfully.
360 10:55:41.451593 Returned 0 in 5 seconds
361 10:55:41.551980 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:55:41.552299 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:55:41.552400 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:55:41.552488 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:55:41.552559 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:55:41.552642 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:55:41.552940 [Enter `^Ec?' for help]
369 10:55:41.723548
370 10:55:41.724065
371 10:55:41.724419 F0: 102B 0000
372 10:55:41.724745
373 10:55:41.725056 F3: 1001 0000 [0200]
374 10:55:41.726490
375 10:55:41.726952 F3: 1001 0000
376 10:55:41.727306
377 10:55:41.727629 F7: 102D 0000
378 10:55:41.727943
379 10:55:41.729910 F1: 0000 0000
380 10:55:41.730341
381 10:55:41.730682 V0: 0000 0000 [0001]
382 10:55:41.731050
383 10:55:41.733494 00: 0007 8000
384 10:55:41.733946
385 10:55:41.734287 01: 0000 0000
386 10:55:41.734690
387 10:55:41.736308 BP: 0C00 0209 [0000]
388 10:55:41.736857
389 10:55:41.737210 G0: 1182 0000
390 10:55:41.737530
391 10:55:41.740372 EC: 0000 0021 [4000]
392 10:55:41.740809
393 10:55:41.741154 S7: 0000 0000 [0000]
394 10:55:41.741472
395 10:55:41.743347 CC: 0000 0000 [0001]
396 10:55:41.743819
397 10:55:41.744204 T0: 0000 0040 [010F]
398 10:55:41.744563
399 10:55:41.746852 Jump to BL
400 10:55:41.747306
401 10:55:41.769911
402 10:55:41.770412
403 10:55:41.770790
404 10:55:41.780543 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:55:41.784143 ARM64: Exception handlers installed.
406 10:55:41.784809 ARM64: Testing exception
407 10:55:41.787310 ARM64: Done test exception
408 10:55:41.793814 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:55:41.803375 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:55:41.810905 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:55:41.820658 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:55:41.827578 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:55:41.837919 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:55:41.848267 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:55:41.854605 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:55:41.873182 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:55:41.876426 WDT: Last reset was cold boot
418 10:55:41.879507 SPI1(PAD0) initialized at 2873684 Hz
419 10:55:41.882814 SPI5(PAD0) initialized at 992727 Hz
420 10:55:41.886392 VBOOT: Loading verstage.
421 10:55:41.892605 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:55:41.896337 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:55:41.899644 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:55:41.903326 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:55:41.910658 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:55:41.916908 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:55:41.928074 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 10:55:41.928544
429 10:55:41.928927
430 10:55:41.937877 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:55:41.941525 ARM64: Exception handlers installed.
432 10:55:41.944754 ARM64: Testing exception
433 10:55:41.945233 ARM64: Done test exception
434 10:55:41.951283 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:55:41.954800 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:55:41.968873 Probing TPM: . done!
437 10:55:41.969311 TPM ready after 0 ms
438 10:55:41.976106 Connected to device vid:did:rid of 1ae0:0028:00
439 10:55:42.024660 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:55:42.024763 Initialized TPM device CR50 revision 0
441 10:55:42.036518 tlcl_send_startup: Startup return code is 0
442 10:55:42.036610 TPM: setup succeeded
443 10:55:42.047611 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:55:42.056967 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:55:42.068903 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:55:42.077608 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:55:42.081198 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:55:42.085054 in-header: 03 07 00 00 08 00 00 00
449 10:55:42.087986 in-data: aa e4 47 04 13 02 00 00
450 10:55:42.091690 Chrome EC: UHEPI supported
451 10:55:42.098601 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:55:42.102322 in-header: 03 9d 00 00 08 00 00 00
453 10:55:42.105991 in-data: 10 20 20 08 00 00 00 00
454 10:55:42.109515 Phase 1
455 10:55:42.113286 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:55:42.116434 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:55:42.124053 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:55:42.128092 Recovery requested (1009000e)
459 10:55:42.133548 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:55:42.139108 tlcl_extend: response is 0
461 10:55:42.147601 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:55:42.152605 tlcl_extend: response is 0
463 10:55:42.158730 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:55:42.179949 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 10:55:42.187567 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:55:42.187655
467 10:55:42.187734
468 10:55:42.198147 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:55:42.198248 ARM64: Exception handlers installed.
470 10:55:42.201945 ARM64: Testing exception
471 10:55:42.205143 ARM64: Done test exception
472 10:55:42.225485 pmic_efuse_setting: Set efuses in 11 msecs
473 10:55:42.229117 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:55:42.232775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:55:42.240415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:55:42.244204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:55:42.247327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:55:42.255301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:55:42.258386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:55:42.262107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:55:42.269027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:55:42.272156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:55:42.275882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:55:42.282068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:55:42.285663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:55:42.291905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:55:42.298987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:55:42.301991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:55:42.308612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:55:42.315179 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:55:42.318982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:55:42.325778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:55:42.333280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:55:42.337056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:55:42.343629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:55:42.347201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:55:42.354067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:55:42.357771 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:55:42.364453 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:55:42.368237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:55:42.375535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:55:42.378749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:55:42.385109 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:55:42.388824 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:55:42.392354 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:55:42.399803 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:55:42.403602 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:55:42.407339 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:55:42.414990 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:55:42.418141 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:55:42.424389 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:55:42.428198 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:55:42.431401 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:55:42.437678 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:55:42.441361 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:55:42.444576 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:55:42.451148 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:55:42.454232 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:55:42.457881 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:55:42.464205 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:55:42.467675 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:55:42.470863 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:55:42.477586 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:55:42.480559 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:55:42.487459 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:55:42.497427 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:55:42.500272 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:55:42.510417 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:55:42.517161 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:55:42.523607 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:55:42.526984 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:55:42.530081 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:55:42.537623 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 10:55:42.544476 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:55:42.547660 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 10:55:42.554170 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:55:42.562499 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 10:55:42.565587 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 10:55:42.572287 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 10:55:42.575410 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 10:55:42.579159 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 10:55:42.582068 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 10:55:42.585865 ADC[4]: Raw value=899630 ID=7
544 10:55:42.589044 ADC[3]: Raw value=212700 ID=1
545 10:55:42.592239 RAM Code: 0x71
546 10:55:42.595202 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 10:55:42.598775 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 10:55:42.609004 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 10:55:42.615793 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 10:55:42.619387 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 10:55:42.622607 in-header: 03 07 00 00 08 00 00 00
552 10:55:42.625837 in-data: aa e4 47 04 13 02 00 00
553 10:55:42.629190 Chrome EC: UHEPI supported
554 10:55:42.635887 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 10:55:42.639628 in-header: 03 95 00 00 08 00 00 00
556 10:55:42.643525 in-data: 18 20 20 08 00 00 00 00
557 10:55:42.646727 MRC: failed to locate region type 0.
558 10:55:42.650728 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 10:55:42.653935 DRAM-K: Running full calibration
560 10:55:42.660886 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 10:55:42.664202 header.status = 0x0
562 10:55:42.667507 header.version = 0x6 (expected: 0x6)
563 10:55:42.670599 header.size = 0xd00 (expected: 0xd00)
564 10:55:42.670686 header.flags = 0x0
565 10:55:42.677539 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 10:55:42.695075 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
567 10:55:42.701492 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 10:55:42.704660 dram_init: ddr_geometry: 2
569 10:55:42.707926 [EMI] MDL number = 2
570 10:55:42.708013 [EMI] Get MDL freq = 0
571 10:55:42.711482 dram_init: ddr_type: 0
572 10:55:42.711566 is_discrete_lpddr4: 1
573 10:55:42.714957 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 10:55:42.715043
575 10:55:42.715110
576 10:55:42.718068 [Bian_co] ETT version 0.0.0.1
577 10:55:42.725209 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 10:55:42.725389
579 10:55:42.728207 dramc_set_vcore_voltage set vcore to 650000
580 10:55:42.731489 Read voltage for 800, 4
581 10:55:42.731597 Vio18 = 0
582 10:55:42.731682 Vcore = 650000
583 10:55:42.731761 Vdram = 0
584 10:55:42.734719 Vddq = 0
585 10:55:42.734843 Vmddr = 0
586 10:55:42.738429 dram_init: config_dvfs: 1
587 10:55:42.741449 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 10:55:42.748233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 10:55:42.752198 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 10:55:42.755078 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 10:55:42.758248 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 10:55:42.761711 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 10:55:42.764865 MEM_TYPE=3, freq_sel=18
594 10:55:42.768081 sv_algorithm_assistance_LP4_1600
595 10:55:42.772025 ============ PULL DRAM RESETB DOWN ============
596 10:55:42.778513 ========== PULL DRAM RESETB DOWN end =========
597 10:55:42.781663 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 10:55:42.785177 ===================================
599 10:55:42.788149 LPDDR4 DRAM CONFIGURATION
600 10:55:42.791643 ===================================
601 10:55:42.792131 EX_ROW_EN[0] = 0x0
602 10:55:42.794769 EX_ROW_EN[1] = 0x0
603 10:55:42.795163 LP4Y_EN = 0x0
604 10:55:42.798036 WORK_FSP = 0x0
605 10:55:42.798122 WL = 0x2
606 10:55:42.801189 RL = 0x2
607 10:55:42.801275 BL = 0x2
608 10:55:42.804306 RPST = 0x0
609 10:55:42.804391 RD_PRE = 0x0
610 10:55:42.807984 WR_PRE = 0x1
611 10:55:42.808069 WR_PST = 0x0
612 10:55:42.810992 DBI_WR = 0x0
613 10:55:42.814098 DBI_RD = 0x0
614 10:55:42.814182 OTF = 0x1
615 10:55:42.817664 ===================================
616 10:55:42.821099 ===================================
617 10:55:42.821185 ANA top config
618 10:55:42.824577 ===================================
619 10:55:42.827501 DLL_ASYNC_EN = 0
620 10:55:42.830875 ALL_SLAVE_EN = 1
621 10:55:42.834421 NEW_RANK_MODE = 1
622 10:55:42.837526 DLL_IDLE_MODE = 1
623 10:55:42.837611 LP45_APHY_COMB_EN = 1
624 10:55:42.841631 TX_ODT_DIS = 1
625 10:55:42.844960 NEW_8X_MODE = 1
626 10:55:42.848695 ===================================
627 10:55:42.852188 ===================================
628 10:55:42.852273 data_rate = 1600
629 10:55:42.855830 CKR = 1
630 10:55:42.858919 DQ_P2S_RATIO = 8
631 10:55:42.862547 ===================================
632 10:55:42.866308 CA_P2S_RATIO = 8
633 10:55:42.866393 DQ_CA_OPEN = 0
634 10:55:42.870083 DQ_SEMI_OPEN = 0
635 10:55:42.873844 CA_SEMI_OPEN = 0
636 10:55:42.877537 CA_FULL_RATE = 0
637 10:55:42.877622 DQ_CKDIV4_EN = 1
638 10:55:42.881059 CA_CKDIV4_EN = 1
639 10:55:42.884117 CA_PREDIV_EN = 0
640 10:55:42.888139 PH8_DLY = 0
641 10:55:42.891586 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 10:55:42.891674 DQ_AAMCK_DIV = 4
643 10:55:42.894616 CA_AAMCK_DIV = 4
644 10:55:42.898395 CA_ADMCK_DIV = 4
645 10:55:42.902093 DQ_TRACK_CA_EN = 0
646 10:55:42.902178 CA_PICK = 800
647 10:55:42.905910 CA_MCKIO = 800
648 10:55:42.909563 MCKIO_SEMI = 0
649 10:55:42.913308 PLL_FREQ = 3068
650 10:55:42.917002 DQ_UI_PI_RATIO = 32
651 10:55:42.917115 CA_UI_PI_RATIO = 0
652 10:55:42.920867 ===================================
653 10:55:42.924021 ===================================
654 10:55:42.927919 memory_type:LPDDR4
655 10:55:42.928024 GP_NUM : 10
656 10:55:42.931428 SRAM_EN : 1
657 10:55:42.934337 MD32_EN : 0
658 10:55:42.937713 ===================================
659 10:55:42.937799 [ANA_INIT] >>>>>>>>>>>>>>
660 10:55:42.941382 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 10:55:42.944357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 10:55:42.948010 ===================================
663 10:55:42.951121 data_rate = 1600,PCW = 0X7600
664 10:55:42.954647 ===================================
665 10:55:42.957472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 10:55:42.964306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 10:55:42.967832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 10:55:42.974185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 10:55:42.978035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 10:55:42.981796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 10:55:42.981882 [ANA_INIT] flow start
672 10:55:42.985329 [ANA_INIT] PLL >>>>>>>>
673 10:55:42.985415 [ANA_INIT] PLL <<<<<<<<
674 10:55:42.989077 [ANA_INIT] MIDPI >>>>>>>>
675 10:55:42.992056 [ANA_INIT] MIDPI <<<<<<<<
676 10:55:42.995624 [ANA_INIT] DLL >>>>>>>>
677 10:55:42.995709 [ANA_INIT] flow end
678 10:55:42.999610 ============ LP4 DIFF to SE enter ============
679 10:55:43.003397 ============ LP4 DIFF to SE exit ============
680 10:55:43.006975 [ANA_INIT] <<<<<<<<<<<<<
681 10:55:43.010123 [Flow] Enable top DCM control >>>>>
682 10:55:43.013871 [Flow] Enable top DCM control <<<<<
683 10:55:43.017578 Enable DLL master slave shuffle
684 10:55:43.021393 ==============================================================
685 10:55:43.024429 Gating Mode config
686 10:55:43.028179 ==============================================================
687 10:55:43.031153 Config description:
688 10:55:43.041377 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 10:55:43.047842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 10:55:43.051386 SELPH_MODE 0: By rank 1: By Phase
691 10:55:43.057879 ==============================================================
692 10:55:43.061437 GAT_TRACK_EN = 1
693 10:55:43.064466 RX_GATING_MODE = 2
694 10:55:43.064552 RX_GATING_TRACK_MODE = 2
695 10:55:43.067938 SELPH_MODE = 1
696 10:55:43.071528 PICG_EARLY_EN = 1
697 10:55:43.074634 VALID_LAT_VALUE = 1
698 10:55:43.081488 ==============================================================
699 10:55:43.084562 Enter into Gating configuration >>>>
700 10:55:43.087612 Exit from Gating configuration <<<<
701 10:55:43.091336 Enter into DVFS_PRE_config >>>>>
702 10:55:43.101019 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 10:55:43.104488 Exit from DVFS_PRE_config <<<<<
704 10:55:43.108501 Enter into PICG configuration >>>>
705 10:55:43.112036 Exit from PICG configuration <<<<
706 10:55:43.115821 [RX_INPUT] configuration >>>>>
707 10:55:43.115925 [RX_INPUT] configuration <<<<<
708 10:55:43.122685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 10:55:43.126427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 10:55:43.133797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 10:55:43.140691 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 10:55:43.144337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 10:55:43.151611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 10:55:43.155151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 10:55:43.158796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 10:55:43.162375 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 10:55:43.169583 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 10:55:43.173497 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 10:55:43.177064 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 10:55:43.180845 ===================================
721 10:55:43.180930 LPDDR4 DRAM CONFIGURATION
722 10:55:43.184652 ===================================
723 10:55:43.187751 EX_ROW_EN[0] = 0x0
724 10:55:43.191371 EX_ROW_EN[1] = 0x0
725 10:55:43.191455 LP4Y_EN = 0x0
726 10:55:43.191521 WORK_FSP = 0x0
727 10:55:43.195675 WL = 0x2
728 10:55:43.195760 RL = 0x2
729 10:55:43.198751 BL = 0x2
730 10:55:43.198904 RPST = 0x0
731 10:55:43.203076 RD_PRE = 0x0
732 10:55:43.203161 WR_PRE = 0x1
733 10:55:43.206236 WR_PST = 0x0
734 10:55:43.206320 DBI_WR = 0x0
735 10:55:43.210039 DBI_RD = 0x0
736 10:55:43.210123 OTF = 0x1
737 10:55:43.213543 ===================================
738 10:55:43.216963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 10:55:43.220832 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 10:55:43.228373 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 10:55:43.228458 ===================================
742 10:55:43.232073 LPDDR4 DRAM CONFIGURATION
743 10:55:43.235895 ===================================
744 10:55:43.235980 EX_ROW_EN[0] = 0x10
745 10:55:43.239509 EX_ROW_EN[1] = 0x0
746 10:55:43.243279 LP4Y_EN = 0x0
747 10:55:43.243391 WORK_FSP = 0x0
748 10:55:43.243489 WL = 0x2
749 10:55:43.246475 RL = 0x2
750 10:55:43.246585 BL = 0x2
751 10:55:43.250014 RPST = 0x0
752 10:55:43.250124 RD_PRE = 0x0
753 10:55:43.253742 WR_PRE = 0x1
754 10:55:43.253826 WR_PST = 0x0
755 10:55:43.257887 DBI_WR = 0x0
756 10:55:43.257992 DBI_RD = 0x0
757 10:55:43.261428 OTF = 0x1
758 10:55:43.265138 ===================================
759 10:55:43.268650 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 10:55:43.273685 nWR fixed to 40
761 10:55:43.277217 [ModeRegInit_LP4] CH0 RK0
762 10:55:43.277301 [ModeRegInit_LP4] CH0 RK1
763 10:55:43.280671 [ModeRegInit_LP4] CH1 RK0
764 10:55:43.280755 [ModeRegInit_LP4] CH1 RK1
765 10:55:43.284944 match AC timing 13
766 10:55:43.287830 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 10:55:43.291582 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 10:55:43.298420 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 10:55:43.302060 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 10:55:43.305797 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 10:55:43.309438 [EMI DOE] emi_dcm 0
772 10:55:43.313303 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 10:55:43.313391 ==
774 10:55:43.316924 Dram Type= 6, Freq= 0, CH_0, rank 0
775 10:55:43.320755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 10:55:43.320839 ==
777 10:55:43.324184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 10:55:43.331536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 10:55:43.341428 [CA 0] Center 38 (7~69) winsize 63
780 10:55:43.345085 [CA 1] Center 37 (7~68) winsize 62
781 10:55:43.348904 [CA 2] Center 35 (5~66) winsize 62
782 10:55:43.352537 [CA 3] Center 35 (5~66) winsize 62
783 10:55:43.355570 [CA 4] Center 34 (4~65) winsize 62
784 10:55:43.359357 [CA 5] Center 34 (3~65) winsize 63
785 10:55:43.359440
786 10:55:43.363144 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 10:55:43.363227
788 10:55:43.367157 [CATrainingPosCal] consider 1 rank data
789 10:55:43.367240 u2DelayCellTimex100 = 270/100 ps
790 10:55:43.371165 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 10:55:43.374924 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 10:55:43.378269 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 10:55:43.382016 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 10:55:43.385626 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 10:55:43.389373 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 10:55:43.389475
797 10:55:43.392807 CA PerBit enable=1, Macro0, CA PI delay=34
798 10:55:43.392890
799 10:55:43.396511 [CBTSetCACLKResult] CA Dly = 34
800 10:55:43.400666 CS Dly: 6 (0~37)
801 10:55:43.400750 ==
802 10:55:43.404320 Dram Type= 6, Freq= 0, CH_0, rank 1
803 10:55:43.407400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 10:55:43.407486 ==
805 10:55:43.411135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 10:55:43.417375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 10:55:43.426993 [CA 0] Center 38 (7~69) winsize 63
808 10:55:43.430669 [CA 1] Center 38 (7~69) winsize 63
809 10:55:43.433633 [CA 2] Center 35 (5~66) winsize 62
810 10:55:43.437023 [CA 3] Center 35 (5~66) winsize 62
811 10:55:43.439922 [CA 4] Center 34 (4~65) winsize 62
812 10:55:43.443638 [CA 5] Center 34 (4~65) winsize 62
813 10:55:43.443722
814 10:55:43.446648 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 10:55:43.446732
816 10:55:43.450443 [CATrainingPosCal] consider 2 rank data
817 10:55:43.453577 u2DelayCellTimex100 = 270/100 ps
818 10:55:43.457322 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 10:55:43.463557 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 10:55:43.466777 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 10:55:43.470473 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 10:55:43.473424 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 10:55:43.477122 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 10:55:43.477230
825 10:55:43.479993 CA PerBit enable=1, Macro0, CA PI delay=34
826 10:55:43.480097
827 10:55:43.483562 [CBTSetCACLKResult] CA Dly = 34
828 10:55:43.483639 CS Dly: 6 (0~37)
829 10:55:43.483713
830 10:55:43.486803 ----->DramcWriteLeveling(PI) begin...
831 10:55:43.489947 ==
832 10:55:43.493672 Dram Type= 6, Freq= 0, CH_0, rank 0
833 10:55:43.496632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 10:55:43.496736 ==
835 10:55:43.500146 Write leveling (Byte 0): 31 => 31
836 10:55:43.503036 Write leveling (Byte 1): 30 => 30
837 10:55:43.506603 DramcWriteLeveling(PI) end<-----
838 10:55:43.506704
839 10:55:43.506795 ==
840 10:55:43.510403 Dram Type= 6, Freq= 0, CH_0, rank 0
841 10:55:43.513332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 10:55:43.513435 ==
843 10:55:43.517104 [Gating] SW mode calibration
844 10:55:43.523267 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 10:55:43.529734 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 10:55:43.533439 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 10:55:43.536567 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 10:55:43.543368 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 10:55:43.546508 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 10:55:43.549606 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 10:55:43.556383 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 10:55:43.559452 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 10:55:43.563601 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:55:43.566680 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:55:43.574169 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:55:43.577473 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:55:43.581057 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:55:43.587096 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:55:43.591165 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:55:43.594533 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:55:43.597876 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:55:43.604468 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:55:43.608019 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:55:43.611111 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
865 10:55:43.617910 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
866 10:55:43.621200 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:55:43.624565 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:55:43.630725 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:55:43.634639 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:55:43.637851 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 10:55:43.644375 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 10:55:43.647928 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:55:43.651136 0 9 12 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
874 10:55:43.657870 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 10:55:43.661018 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 10:55:43.664613 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 10:55:43.671122 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 10:55:43.674599 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 10:55:43.677584 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 10:55:43.684155 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
881 10:55:43.687434 0 10 12 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
882 10:55:43.691053 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 10:55:43.697632 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 10:55:43.700996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 10:55:43.704090 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 10:55:43.710613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 10:55:43.714258 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 10:55:43.717124 0 11 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
889 10:55:43.723528 0 11 12 | B1->B0 | 3333 4545 | 1 0 | (0 0) (1 1)
890 10:55:43.727676 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 10:55:43.730358 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 10:55:43.737375 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 10:55:43.740386 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 10:55:43.743839 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 10:55:43.750240 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 10:55:43.753508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 10:55:43.756520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 10:55:43.763697 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 10:55:43.766863 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 10:55:43.769924 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 10:55:43.776721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:55:43.779769 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:55:43.783596 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:55:43.789841 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:55:43.792683 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:55:43.796611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:55:43.803180 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:55:43.806401 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:55:43.809263 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:55:43.816355 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:55:43.819369 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:55:43.822489 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 10:55:43.829224 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 10:55:43.829807 Total UI for P1: 0, mck2ui 16
915 10:55:43.832662 best dqsien dly found for B0: ( 0, 14, 8)
916 10:55:43.839584 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 10:55:43.842877 Total UI for P1: 0, mck2ui 16
918 10:55:43.846028 best dqsien dly found for B1: ( 0, 14, 12)
919 10:55:43.849527 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 10:55:43.852374 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 10:55:43.852864
922 10:55:43.856035 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 10:55:43.858979 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 10:55:43.862522 [Gating] SW calibration Done
925 10:55:43.863040 ==
926 10:55:43.865467 Dram Type= 6, Freq= 0, CH_0, rank 0
927 10:55:43.869468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 10:55:43.870048 ==
929 10:55:43.872419 RX Vref Scan: 0
930 10:55:43.872998
931 10:55:43.876010 RX Vref 0 -> 0, step: 1
932 10:55:43.876593
933 10:55:43.876976 RX Delay -130 -> 252, step: 16
934 10:55:43.882195 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
935 10:55:43.885999 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
936 10:55:43.889073 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
937 10:55:43.892347 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
938 10:55:43.898984 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
939 10:55:43.902131 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
940 10:55:43.905278 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
941 10:55:43.908722 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
942 10:55:43.912507 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
943 10:55:43.915554 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
944 10:55:43.921947 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
945 10:55:43.925139 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
946 10:55:43.928813 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
947 10:55:43.931710 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
948 10:55:43.938598 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
949 10:55:43.942033 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
950 10:55:43.942619 ==
951 10:55:43.944817 Dram Type= 6, Freq= 0, CH_0, rank 0
952 10:55:43.948456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 10:55:43.948936 ==
954 10:55:43.951974 DQS Delay:
955 10:55:43.952497 DQS0 = 0, DQS1 = 0
956 10:55:43.952875 DQM Delay:
957 10:55:43.955237 DQM0 = 81, DQM1 = 70
958 10:55:43.955711 DQ Delay:
959 10:55:43.958334 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
960 10:55:43.961664 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
961 10:55:43.965162 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
962 10:55:43.968980 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
963 10:55:43.969561
964 10:55:43.969937
965 10:55:43.970285 ==
966 10:55:43.971956 Dram Type= 6, Freq= 0, CH_0, rank 0
967 10:55:43.974928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 10:55:43.978966 ==
969 10:55:43.979521
970 10:55:43.979895
971 10:55:43.980244 TX Vref Scan disable
972 10:55:43.981860 == TX Byte 0 ==
973 10:55:43.985186 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 10:55:43.989027 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 10:55:43.992159 == TX Byte 1 ==
976 10:55:43.995063 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 10:55:43.998976 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 10:55:44.002063 ==
979 10:55:44.002540 Dram Type= 6, Freq= 0, CH_0, rank 0
980 10:55:44.008248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 10:55:44.008908 ==
982 10:55:44.020519 TX Vref=22, minBit 1, minWin=26, winSum=436
983 10:55:44.023631 TX Vref=24, minBit 5, minWin=26, winSum=436
984 10:55:44.027171 TX Vref=26, minBit 14, minWin=26, winSum=439
985 10:55:44.030924 TX Vref=28, minBit 11, minWin=27, winSum=443
986 10:55:44.033821 TX Vref=30, minBit 2, minWin=27, winSum=443
987 10:55:44.040843 TX Vref=32, minBit 10, minWin=27, winSum=443
988 10:55:44.044236 [TxChooseVref] Worse bit 11, Min win 27, Win sum 443, Final Vref 28
989 10:55:44.044723
990 10:55:44.047088 Final TX Range 1 Vref 28
991 10:55:44.047728
992 10:55:44.048123 ==
993 10:55:44.050754 Dram Type= 6, Freq= 0, CH_0, rank 0
994 10:55:44.053744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 10:55:44.057133 ==
996 10:55:44.057611
997 10:55:44.057990
998 10:55:44.058338 TX Vref Scan disable
999 10:55:44.061145 == TX Byte 0 ==
1000 10:55:44.064332 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1001 10:55:44.071015 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1002 10:55:44.071612 == TX Byte 1 ==
1003 10:55:44.073887 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 10:55:44.080759 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 10:55:44.081423
1006 10:55:44.081817 [DATLAT]
1007 10:55:44.082174 Freq=800, CH0 RK0
1008 10:55:44.082518
1009 10:55:44.083827 DATLAT Default: 0xa
1010 10:55:44.084309 0, 0xFFFF, sum = 0
1011 10:55:44.087381 1, 0xFFFF, sum = 0
1012 10:55:44.087871 2, 0xFFFF, sum = 0
1013 10:55:44.090491 3, 0xFFFF, sum = 0
1014 10:55:44.094282 4, 0xFFFF, sum = 0
1015 10:55:44.094792 5, 0xFFFF, sum = 0
1016 10:55:44.097359 6, 0xFFFF, sum = 0
1017 10:55:44.097843 7, 0xFFFF, sum = 0
1018 10:55:44.100694 8, 0xFFFF, sum = 0
1019 10:55:44.101307 9, 0x0, sum = 1
1020 10:55:44.104048 10, 0x0, sum = 2
1021 10:55:44.104537 11, 0x0, sum = 3
1022 10:55:44.104919 12, 0x0, sum = 4
1023 10:55:44.107330 best_step = 10
1024 10:55:44.107809
1025 10:55:44.108221 ==
1026 10:55:44.110527 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 10:55:44.113789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 10:55:44.114360 ==
1029 10:55:44.117391 RX Vref Scan: 1
1030 10:55:44.117963
1031 10:55:44.120828 Set Vref Range= 32 -> 127
1032 10:55:44.121398
1033 10:55:44.121776 RX Vref 32 -> 127, step: 1
1034 10:55:44.122122
1035 10:55:44.123577 RX Delay -111 -> 252, step: 8
1036 10:55:44.124052
1037 10:55:44.127367 Set Vref, RX VrefLevel [Byte0]: 32
1038 10:55:44.130369 [Byte1]: 32
1039 10:55:44.134068
1040 10:55:44.134635 Set Vref, RX VrefLevel [Byte0]: 33
1041 10:55:44.136887 [Byte1]: 33
1042 10:55:44.141557
1043 10:55:44.142028 Set Vref, RX VrefLevel [Byte0]: 34
1044 10:55:44.144612 [Byte1]: 34
1045 10:55:44.148948
1046 10:55:44.149412 Set Vref, RX VrefLevel [Byte0]: 35
1047 10:55:44.152040 [Byte1]: 35
1048 10:55:44.156704
1049 10:55:44.157198 Set Vref, RX VrefLevel [Byte0]: 36
1050 10:55:44.160393 [Byte1]: 36
1051 10:55:44.164115
1052 10:55:44.164576 Set Vref, RX VrefLevel [Byte0]: 37
1053 10:55:44.167580 [Byte1]: 37
1054 10:55:44.172233
1055 10:55:44.172795 Set Vref, RX VrefLevel [Byte0]: 38
1056 10:55:44.175272 [Byte1]: 38
1057 10:55:44.179498
1058 10:55:44.179982 Set Vref, RX VrefLevel [Byte0]: 39
1059 10:55:44.185952 [Byte1]: 39
1060 10:55:44.186739
1061 10:55:44.189695 Set Vref, RX VrefLevel [Byte0]: 40
1062 10:55:44.192544 [Byte1]: 40
1063 10:55:44.193085
1064 10:55:44.196177 Set Vref, RX VrefLevel [Byte0]: 41
1065 10:55:44.199724 [Byte1]: 41
1066 10:55:44.200296
1067 10:55:44.202748 Set Vref, RX VrefLevel [Byte0]: 42
1068 10:55:44.206007 [Byte1]: 42
1069 10:55:44.210331
1070 10:55:44.210794 Set Vref, RX VrefLevel [Byte0]: 43
1071 10:55:44.213487 [Byte1]: 43
1072 10:55:44.218106
1073 10:55:44.218676 Set Vref, RX VrefLevel [Byte0]: 44
1074 10:55:44.221192 [Byte1]: 44
1075 10:55:44.226372
1076 10:55:44.226982 Set Vref, RX VrefLevel [Byte0]: 45
1077 10:55:44.229407 [Byte1]: 45
1078 10:55:44.233477
1079 10:55:44.234085 Set Vref, RX VrefLevel [Byte0]: 46
1080 10:55:44.236730 [Byte1]: 46
1081 10:55:44.240996
1082 10:55:44.241563 Set Vref, RX VrefLevel [Byte0]: 47
1083 10:55:44.244265 [Byte1]: 47
1084 10:55:44.248863
1085 10:55:44.249394 Set Vref, RX VrefLevel [Byte0]: 48
1086 10:55:44.252644 [Byte1]: 48
1087 10:55:44.256263
1088 10:55:44.256725 Set Vref, RX VrefLevel [Byte0]: 49
1089 10:55:44.260125 [Byte1]: 49
1090 10:55:44.263771
1091 10:55:44.264241 Set Vref, RX VrefLevel [Byte0]: 50
1092 10:55:44.267257 [Byte1]: 50
1093 10:55:44.271466
1094 10:55:44.272032 Set Vref, RX VrefLevel [Byte0]: 51
1095 10:55:44.275020 [Byte1]: 51
1096 10:55:44.279531
1097 10:55:44.280118 Set Vref, RX VrefLevel [Byte0]: 52
1098 10:55:44.282428 [Byte1]: 52
1099 10:55:44.286993
1100 10:55:44.287558 Set Vref, RX VrefLevel [Byte0]: 53
1101 10:55:44.289731 [Byte1]: 53
1102 10:55:44.294268
1103 10:55:44.294734 Set Vref, RX VrefLevel [Byte0]: 54
1104 10:55:44.297662 [Byte1]: 54
1105 10:55:44.301652
1106 10:55:44.302115 Set Vref, RX VrefLevel [Byte0]: 55
1107 10:55:44.305356 [Byte1]: 55
1108 10:55:44.309600
1109 10:55:44.310155 Set Vref, RX VrefLevel [Byte0]: 56
1110 10:55:44.313314 [Byte1]: 56
1111 10:55:44.317151
1112 10:55:44.317718 Set Vref, RX VrefLevel [Byte0]: 57
1113 10:55:44.320675 [Byte1]: 57
1114 10:55:44.325353
1115 10:55:44.325916 Set Vref, RX VrefLevel [Byte0]: 58
1116 10:55:44.328436 [Byte1]: 58
1117 10:55:44.332469
1118 10:55:44.332992 Set Vref, RX VrefLevel [Byte0]: 59
1119 10:55:44.335394 [Byte1]: 59
1120 10:55:44.340232
1121 10:55:44.340693 Set Vref, RX VrefLevel [Byte0]: 60
1122 10:55:44.343115 [Byte1]: 60
1123 10:55:44.347680
1124 10:55:44.348191 Set Vref, RX VrefLevel [Byte0]: 61
1125 10:55:44.351026 [Byte1]: 61
1126 10:55:44.355489
1127 10:55:44.355958 Set Vref, RX VrefLevel [Byte0]: 62
1128 10:55:44.359007 [Byte1]: 62
1129 10:55:44.363169
1130 10:55:44.363640 Set Vref, RX VrefLevel [Byte0]: 63
1131 10:55:44.366281 [Byte1]: 63
1132 10:55:44.370730
1133 10:55:44.371346 Set Vref, RX VrefLevel [Byte0]: 64
1134 10:55:44.374126 [Byte1]: 64
1135 10:55:44.378420
1136 10:55:44.379037 Set Vref, RX VrefLevel [Byte0]: 65
1137 10:55:44.381986 [Byte1]: 65
1138 10:55:44.386080
1139 10:55:44.386552 Set Vref, RX VrefLevel [Byte0]: 66
1140 10:55:44.389440 [Byte1]: 66
1141 10:55:44.393947
1142 10:55:44.394526 Set Vref, RX VrefLevel [Byte0]: 67
1143 10:55:44.396653 [Byte1]: 67
1144 10:55:44.401411
1145 10:55:44.401879 Set Vref, RX VrefLevel [Byte0]: 68
1146 10:55:44.404520 [Byte1]: 68
1147 10:55:44.409243
1148 10:55:44.409828 Set Vref, RX VrefLevel [Byte0]: 69
1149 10:55:44.412406 [Byte1]: 69
1150 10:55:44.416588
1151 10:55:44.417162 Set Vref, RX VrefLevel [Byte0]: 70
1152 10:55:44.419717 [Byte1]: 70
1153 10:55:44.424031
1154 10:55:44.424614 Set Vref, RX VrefLevel [Byte0]: 71
1155 10:55:44.427730 [Byte1]: 71
1156 10:55:44.431902
1157 10:55:44.432376 Set Vref, RX VrefLevel [Byte0]: 72
1158 10:55:44.435260 [Byte1]: 72
1159 10:55:44.439547
1160 10:55:44.440142 Set Vref, RX VrefLevel [Byte0]: 73
1161 10:55:44.443145 [Byte1]: 73
1162 10:55:44.447472
1163 10:55:44.448057 Set Vref, RX VrefLevel [Byte0]: 74
1164 10:55:44.450535 [Byte1]: 74
1165 10:55:44.454571
1166 10:55:44.455198 Set Vref, RX VrefLevel [Byte0]: 75
1167 10:55:44.458089 [Byte1]: 75
1168 10:55:44.462697
1169 10:55:44.463337 Set Vref, RX VrefLevel [Byte0]: 76
1170 10:55:44.465912 [Byte1]: 76
1171 10:55:44.470087
1172 10:55:44.470673 Set Vref, RX VrefLevel [Byte0]: 77
1173 10:55:44.473265 [Byte1]: 77
1174 10:55:44.477722
1175 10:55:44.478302 Set Vref, RX VrefLevel [Byte0]: 78
1176 10:55:44.484159 [Byte1]: 78
1177 10:55:44.484632
1178 10:55:44.487304 Set Vref, RX VrefLevel [Byte0]: 79
1179 10:55:44.490672 [Byte1]: 79
1180 10:55:44.491169
1181 10:55:44.493772 Final RX Vref Byte 0 = 63 to rank0
1182 10:55:44.497485 Final RX Vref Byte 1 = 59 to rank0
1183 10:55:44.500520 Final RX Vref Byte 0 = 63 to rank1
1184 10:55:44.504125 Final RX Vref Byte 1 = 59 to rank1==
1185 10:55:44.506983 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 10:55:44.510889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 10:55:44.511649 ==
1188 10:55:44.513619 DQS Delay:
1189 10:55:44.514160 DQS0 = 0, DQS1 = 0
1190 10:55:44.514545 DQM Delay:
1191 10:55:44.517115 DQM0 = 81, DQM1 = 68
1192 10:55:44.517589 DQ Delay:
1193 10:55:44.520613 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 10:55:44.523898 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1195 10:55:44.527308 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1196 10:55:44.530111 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1197 10:55:44.530603
1198 10:55:44.531024
1199 10:55:44.540227 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1200 10:55:44.543924 CH0 RK0: MR19=606, MR18=2323
1201 10:55:44.546945 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1202 10:55:44.547431
1203 10:55:44.554008 ----->DramcWriteLeveling(PI) begin...
1204 10:55:44.554597 ==
1205 10:55:44.556817 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 10:55:44.560292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 10:55:44.561035 ==
1208 10:55:44.563749 Write leveling (Byte 0): 30 => 30
1209 10:55:44.567130 Write leveling (Byte 1): 31 => 31
1210 10:55:44.570172 DramcWriteLeveling(PI) end<-----
1211 10:55:44.570760
1212 10:55:44.571175 ==
1213 10:55:44.573439 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 10:55:44.576914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 10:55:44.577394 ==
1216 10:55:44.580530 [Gating] SW mode calibration
1217 10:55:44.586891 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 10:55:44.593670 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 10:55:44.596552 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 10:55:44.600269 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 10:55:44.606621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1222 10:55:44.609907 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1223 10:55:44.613095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:55:44.620071 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:55:44.622938 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:55:44.626813 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:55:44.632837 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:55:44.636684 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:55:44.639599 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:55:44.646871 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:55:44.690424 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:55:44.691058 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:55:44.691446 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:55:44.692148 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 10:55:44.692521 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:55:44.692864 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:55:44.693194 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1238 10:55:44.693515 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1239 10:55:44.693831 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 10:55:44.694144 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 10:55:44.734652 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:55:44.735313 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:55:44.736065 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:55:44.736455 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:55:44.736808 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1246 10:55:44.737152 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 10:55:44.737504 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 10:55:44.737829 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 10:55:44.738147 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 10:55:44.738460 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 10:55:44.739254 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 10:55:44.742139 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1253 10:55:44.746210 0 10 8 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (1 0)
1254 10:55:44.749164 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1255 10:55:44.755669 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 10:55:44.759009 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 10:55:44.763208 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 10:55:44.769242 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 10:55:44.772117 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 10:55:44.776157 0 11 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1261 10:55:44.782522 0 11 8 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
1262 10:55:44.785416 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1263 10:55:44.788874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 10:55:44.795276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 10:55:44.798712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 10:55:44.802699 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 10:55:44.805817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 10:55:44.813206 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 10:55:44.816680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 10:55:44.820504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:55:44.823472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:55:44.830007 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:55:44.833460 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:55:44.837196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:55:44.843926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:55:44.846819 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:55:44.849893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:55:44.857217 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 10:55:44.860268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 10:55:44.863720 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 10:55:44.870193 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 10:55:44.873525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 10:55:44.876318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 10:55:44.882951 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 10:55:44.887119 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 10:55:44.889887 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 10:55:44.892945 Total UI for P1: 0, mck2ui 16
1288 10:55:44.896406 best dqsien dly found for B0: ( 0, 14, 8)
1289 10:55:44.899984 Total UI for P1: 0, mck2ui 16
1290 10:55:44.903311 best dqsien dly found for B1: ( 0, 14, 8)
1291 10:55:44.905991 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1292 10:55:44.909705 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 10:55:44.910176
1294 10:55:44.916501 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1295 10:55:44.919806 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 10:55:44.920286 [Gating] SW calibration Done
1297 10:55:44.922740 ==
1298 10:55:44.923259 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 10:55:44.929950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 10:55:44.930528 ==
1301 10:55:44.930943 RX Vref Scan: 0
1302 10:55:44.931297
1303 10:55:44.932764 RX Vref 0 -> 0, step: 1
1304 10:55:44.933237
1305 10:55:44.936192 RX Delay -130 -> 252, step: 16
1306 10:55:44.939358 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1307 10:55:44.942919 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1308 10:55:44.945797 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1309 10:55:44.952517 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1310 10:55:44.955925 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1311 10:55:44.959960 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1312 10:55:44.962713 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1313 10:55:44.966472 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1314 10:55:44.972681 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1315 10:55:44.975687 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1316 10:55:44.978961 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1317 10:55:44.982376 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1318 10:55:44.988933 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1319 10:55:44.992797 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1320 10:55:44.995677 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1321 10:55:44.999316 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1322 10:55:44.999898 ==
1323 10:55:45.002685 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 10:55:45.008759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 10:55:45.009250 ==
1326 10:55:45.009731 DQS Delay:
1327 10:55:45.010182 DQS0 = 0, DQS1 = 0
1328 10:55:45.012046 DQM Delay:
1329 10:55:45.012524 DQM0 = 81, DQM1 = 69
1330 10:55:45.015365 DQ Delay:
1331 10:55:45.019093 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =77
1332 10:55:45.019696 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1333 10:55:45.022533 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1334 10:55:45.029068 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1335 10:55:45.029643
1336 10:55:45.030124
1337 10:55:45.030572 ==
1338 10:55:45.032336 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 10:55:45.035493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 10:55:45.036003 ==
1341 10:55:45.036473
1342 10:55:45.036919
1343 10:55:45.038515 TX Vref Scan disable
1344 10:55:45.039021 == TX Byte 0 ==
1345 10:55:45.045683 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 10:55:45.049602 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 10:55:45.050190 == TX Byte 1 ==
1348 10:55:45.055136 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1349 10:55:45.058941 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1350 10:55:45.059517 ==
1351 10:55:45.062174 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 10:55:45.064861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 10:55:45.065355 ==
1354 10:55:45.079148 TX Vref=22, minBit 13, minWin=26, winSum=436
1355 10:55:45.082363 TX Vref=24, minBit 3, minWin=27, winSum=438
1356 10:55:45.085394 TX Vref=26, minBit 0, minWin=27, winSum=440
1357 10:55:45.088606 TX Vref=28, minBit 5, minWin=27, winSum=442
1358 10:55:45.091851 TX Vref=30, minBit 4, minWin=27, winSum=439
1359 10:55:45.098796 TX Vref=32, minBit 2, minWin=27, winSum=441
1360 10:55:45.102020 [TxChooseVref] Worse bit 5, Min win 27, Win sum 442, Final Vref 28
1361 10:55:45.102443
1362 10:55:45.105267 Final TX Range 1 Vref 28
1363 10:55:45.105729
1364 10:55:45.106065 ==
1365 10:55:45.108535 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 10:55:45.112118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 10:55:45.112420 ==
1368 10:55:45.115101
1369 10:55:45.115375
1370 10:55:45.115553 TX Vref Scan disable
1371 10:55:45.118557 == TX Byte 0 ==
1372 10:55:45.121532 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1373 10:55:45.128744 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1374 10:55:45.128928 == TX Byte 1 ==
1375 10:55:45.132039 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1376 10:55:45.138538 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1377 10:55:45.138777
1378 10:55:45.138976 [DATLAT]
1379 10:55:45.139110 Freq=800, CH0 RK1
1380 10:55:45.139237
1381 10:55:45.141684 DATLAT Default: 0xa
1382 10:55:45.141881 0, 0xFFFF, sum = 0
1383 10:55:45.144871 1, 0xFFFF, sum = 0
1384 10:55:45.145051 2, 0xFFFF, sum = 0
1385 10:55:45.148554 3, 0xFFFF, sum = 0
1386 10:55:45.151591 4, 0xFFFF, sum = 0
1387 10:55:45.151770 5, 0xFFFF, sum = 0
1388 10:55:45.154652 6, 0xFFFF, sum = 0
1389 10:55:45.154920 7, 0xFFFF, sum = 0
1390 10:55:45.158489 8, 0xFFFF, sum = 0
1391 10:55:45.158755 9, 0x0, sum = 1
1392 10:55:45.161582 10, 0x0, sum = 2
1393 10:55:45.161765 11, 0x0, sum = 3
1394 10:55:45.162011 12, 0x0, sum = 4
1395 10:55:45.164953 best_step = 10
1396 10:55:45.165131
1397 10:55:45.165270 ==
1398 10:55:45.167942 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 10:55:45.171695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 10:55:45.171885 ==
1401 10:55:45.174741 RX Vref Scan: 0
1402 10:55:45.174975
1403 10:55:45.178133 RX Vref 0 -> 0, step: 1
1404 10:55:45.178314
1405 10:55:45.178452 RX Delay -111 -> 252, step: 8
1406 10:55:45.185404 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1407 10:55:45.188709 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1408 10:55:45.191891 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1409 10:55:45.194961 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1410 10:55:45.198460 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1411 10:55:45.205641 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1412 10:55:45.208938 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1413 10:55:45.212065 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1414 10:55:45.215370 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1415 10:55:45.218499 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1416 10:55:45.225214 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1417 10:55:45.228730 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1418 10:55:45.231854 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1419 10:55:45.235309 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1420 10:55:45.241802 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1421 10:55:45.244902 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1422 10:55:45.245356 ==
1423 10:55:45.248502 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 10:55:45.251485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 10:55:45.251962 ==
1426 10:55:45.255177 DQS Delay:
1427 10:55:45.255627 DQS0 = 0, DQS1 = 0
1428 10:55:45.255982 DQM Delay:
1429 10:55:45.258119 DQM0 = 78, DQM1 = 71
1430 10:55:45.258627 DQ Delay:
1431 10:55:45.261870 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1432 10:55:45.265326 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1433 10:55:45.268346 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1434 10:55:45.271642 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1435 10:55:45.272062
1436 10:55:45.272383
1437 10:55:45.281778 [DQSOSCAuto] RK1, (LSB)MR18= 0x4925, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1438 10:55:45.282256 CH0 RK1: MR19=606, MR18=4925
1439 10:55:45.288291 CH0_RK1: MR19=0x606, MR18=0x4925, DQSOSC=391, MR23=63, INC=96, DEC=64
1440 10:55:45.291429 [RxdqsGatingPostProcess] freq 800
1441 10:55:45.298352 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 10:55:45.301491 Pre-setting of DQS Precalculation
1443 10:55:45.304870 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 10:55:45.305303 ==
1445 10:55:45.308046 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 10:55:45.314566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 10:55:45.315034 ==
1448 10:55:45.317918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 10:55:45.324895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 10:55:45.333736 [CA 0] Center 36 (6~66) winsize 61
1451 10:55:45.337253 [CA 1] Center 36 (6~67) winsize 62
1452 10:55:45.340268 [CA 2] Center 34 (4~64) winsize 61
1453 10:55:45.343811 [CA 3] Center 34 (4~64) winsize 61
1454 10:55:45.346932 [CA 4] Center 34 (4~65) winsize 62
1455 10:55:45.350056 [CA 5] Center 33 (3~64) winsize 62
1456 10:55:45.350609
1457 10:55:45.353670 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 10:55:45.354232
1459 10:55:45.356599 [CATrainingPosCal] consider 1 rank data
1460 10:55:45.360402 u2DelayCellTimex100 = 270/100 ps
1461 10:55:45.363643 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 10:55:45.370273 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1463 10:55:45.373574 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1464 10:55:45.376645 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1465 10:55:45.379788 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1466 10:55:45.383263 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 10:55:45.383345
1468 10:55:45.386346 CA PerBit enable=1, Macro0, CA PI delay=33
1469 10:55:45.386453
1470 10:55:45.389970 [CBTSetCACLKResult] CA Dly = 33
1471 10:55:45.393215 CS Dly: 5 (0~36)
1472 10:55:45.393297 ==
1473 10:55:45.396415 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 10:55:45.399664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 10:55:45.399747 ==
1476 10:55:45.403320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 10:55:45.409920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 10:55:45.419665 [CA 0] Center 37 (7~67) winsize 61
1479 10:55:45.422816 [CA 1] Center 36 (6~67) winsize 62
1480 10:55:45.426080 [CA 2] Center 34 (4~65) winsize 62
1481 10:55:45.429553 [CA 3] Center 33 (3~64) winsize 62
1482 10:55:45.432695 [CA 4] Center 34 (4~65) winsize 62
1483 10:55:45.436466 [CA 5] Center 33 (3~64) winsize 62
1484 10:55:45.436574
1485 10:55:45.439308 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 10:55:45.439405
1487 10:55:45.442803 [CATrainingPosCal] consider 2 rank data
1488 10:55:45.445971 u2DelayCellTimex100 = 270/100 ps
1489 10:55:45.449308 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1490 10:55:45.456323 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1491 10:55:45.459250 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1492 10:55:45.463002 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1493 10:55:45.466156 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1494 10:55:45.469956 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1495 10:55:45.470040
1496 10:55:45.473485 CA PerBit enable=1, Macro0, CA PI delay=33
1497 10:55:45.473568
1498 10:55:45.476990 [CBTSetCACLKResult] CA Dly = 33
1499 10:55:45.477073 CS Dly: 6 (0~38)
1500 10:55:45.477138
1501 10:55:45.481089 ----->DramcWriteLeveling(PI) begin...
1502 10:55:45.481173 ==
1503 10:55:45.484238 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 10:55:45.488065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 10:55:45.488176 ==
1506 10:55:45.491577 Write leveling (Byte 0): 26 => 26
1507 10:55:45.495225 Write leveling (Byte 1): 31 => 31
1508 10:55:45.498895 DramcWriteLeveling(PI) end<-----
1509 10:55:45.498977
1510 10:55:45.499042 ==
1511 10:55:45.502111 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 10:55:45.505786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 10:55:45.505870 ==
1514 10:55:45.509061 [Gating] SW mode calibration
1515 10:55:45.515650 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 10:55:45.522267 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 10:55:45.525537 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 10:55:45.528732 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 10:55:45.535115 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 10:55:45.538380 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:55:45.542168 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:55:45.548421 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:55:45.552098 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:55:45.555180 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:55:45.562287 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:55:45.565070 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:55:45.568922 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:55:45.575384 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:55:45.578609 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:55:45.581929 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 10:55:45.588449 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:55:45.591803 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:55:45.594897 0 8 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1534 10:55:45.601648 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1535 10:55:45.605328 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1536 10:55:45.608293 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 10:55:45.611549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 10:55:45.618062 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 10:55:45.622056 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:55:45.625260 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:55:45.631886 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:55:45.635030 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:55:45.638294 0 9 8 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
1544 10:55:45.644900 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 10:55:45.648089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 10:55:45.651229 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 10:55:45.657973 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 10:55:45.661394 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 10:55:45.665060 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 10:55:45.671571 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1551 10:55:45.675000 0 10 8 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
1552 10:55:45.678094 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 10:55:45.684630 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 10:55:45.688048 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 10:55:45.691400 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 10:55:45.698322 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 10:55:45.701641 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 10:55:45.704644 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 10:55:45.710939 0 11 8 | B1->B0 | 3838 3636 | 1 0 | (1 1) (0 0)
1560 10:55:45.714493 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 10:55:45.717727 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 10:55:45.724315 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 10:55:45.727535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 10:55:45.730737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 10:55:45.737919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 10:55:45.741146 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 10:55:45.744328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 10:55:45.750840 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:55:45.754031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:55:45.757257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:55:45.764316 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:55:45.767355 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:55:45.770719 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:55:45.777481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:55:45.780405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 10:55:45.784015 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 10:55:45.790528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 10:55:45.794465 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 10:55:45.797484 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 10:55:45.800361 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 10:55:45.807283 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 10:55:45.810459 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 10:55:45.813781 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 10:55:45.820603 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 10:55:45.824086 Total UI for P1: 0, mck2ui 16
1586 10:55:45.827351 best dqsien dly found for B0: ( 0, 14, 8)
1587 10:55:45.830651 Total UI for P1: 0, mck2ui 16
1588 10:55:45.833825 best dqsien dly found for B1: ( 0, 14, 8)
1589 10:55:45.837005 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1590 10:55:45.840345 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1591 10:55:45.840419
1592 10:55:45.843601 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1593 10:55:45.847362 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1594 10:55:45.850469 [Gating] SW calibration Done
1595 10:55:45.850548 ==
1596 10:55:45.853735 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 10:55:45.856915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 10:55:45.857011 ==
1599 10:55:45.860727 RX Vref Scan: 0
1600 10:55:45.860829
1601 10:55:45.860910 RX Vref 0 -> 0, step: 1
1602 10:55:45.860984
1603 10:55:45.863737 RX Delay -130 -> 252, step: 16
1604 10:55:45.870320 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1605 10:55:45.873512 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1606 10:55:45.877099 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1607 10:55:45.880140 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1608 10:55:45.883987 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1609 10:55:45.890594 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1610 10:55:45.893463 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1611 10:55:45.897154 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1612 10:55:45.899868 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1613 10:55:45.903575 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1614 10:55:45.909949 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1615 10:55:45.913458 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1616 10:55:45.916567 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1617 10:55:45.919826 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1618 10:55:45.923023 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1619 10:55:45.929846 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1620 10:55:45.929931 ==
1621 10:55:45.932935 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 10:55:45.936317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 10:55:45.936403 ==
1624 10:55:45.936487 DQS Delay:
1625 10:55:45.939506 DQS0 = 0, DQS1 = 0
1626 10:55:45.939590 DQM Delay:
1627 10:55:45.943381 DQM0 = 81, DQM1 = 71
1628 10:55:45.943466 DQ Delay:
1629 10:55:45.946509 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1630 10:55:45.949757 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1631 10:55:45.953087 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1632 10:55:45.956247 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1633 10:55:45.956332
1634 10:55:45.956415
1635 10:55:45.956493 ==
1636 10:55:45.959909 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 10:55:45.963084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 10:55:45.966229 ==
1639 10:55:45.966314
1640 10:55:45.966397
1641 10:55:45.966475 TX Vref Scan disable
1642 10:55:45.969329 == TX Byte 0 ==
1643 10:55:45.972783 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 10:55:45.975908 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 10:55:45.979617 == TX Byte 1 ==
1646 10:55:45.982630 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1647 10:55:45.986258 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1648 10:55:45.989384 ==
1649 10:55:45.989467 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 10:55:45.995986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 10:55:45.996076 ==
1652 10:55:46.008606 TX Vref=22, minBit 1, minWin=26, winSum=442
1653 10:55:46.012608 TX Vref=24, minBit 5, minWin=27, winSum=445
1654 10:55:46.015373 TX Vref=26, minBit 5, minWin=27, winSum=446
1655 10:55:46.018657 TX Vref=28, minBit 5, minWin=27, winSum=449
1656 10:55:46.022017 TX Vref=30, minBit 9, minWin=27, winSum=451
1657 10:55:46.028735 TX Vref=32, minBit 9, minWin=27, winSum=451
1658 10:55:46.031813 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 30
1659 10:55:46.031896
1660 10:55:46.035138 Final TX Range 1 Vref 30
1661 10:55:46.035222
1662 10:55:46.035286 ==
1663 10:55:46.038699 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 10:55:46.042070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 10:55:46.044796 ==
1666 10:55:46.044879
1667 10:55:46.044944
1668 10:55:46.045004 TX Vref Scan disable
1669 10:55:46.048555 == TX Byte 0 ==
1670 10:55:46.052028 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 10:55:46.055213 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 10:55:46.058512 == TX Byte 1 ==
1673 10:55:46.061636 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1674 10:55:46.068720 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1675 10:55:46.068803
1676 10:55:46.068869 [DATLAT]
1677 10:55:46.068928 Freq=800, CH1 RK0
1678 10:55:46.068987
1679 10:55:46.071901 DATLAT Default: 0xa
1680 10:55:46.071983 0, 0xFFFF, sum = 0
1681 10:55:46.075021 1, 0xFFFF, sum = 0
1682 10:55:46.078327 2, 0xFFFF, sum = 0
1683 10:55:46.078417 3, 0xFFFF, sum = 0
1684 10:55:46.082077 4, 0xFFFF, sum = 0
1685 10:55:46.082176 5, 0xFFFF, sum = 0
1686 10:55:46.085135 6, 0xFFFF, sum = 0
1687 10:55:46.085233 7, 0xFFFF, sum = 0
1688 10:55:46.088401 8, 0xFFFF, sum = 0
1689 10:55:46.088506 9, 0x0, sum = 1
1690 10:55:46.091665 10, 0x0, sum = 2
1691 10:55:46.091771 11, 0x0, sum = 3
1692 10:55:46.091853 12, 0x0, sum = 4
1693 10:55:46.095156 best_step = 10
1694 10:55:46.095259
1695 10:55:46.095341 ==
1696 10:55:46.098188 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 10:55:46.101857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 10:55:46.101983 ==
1699 10:55:46.105146 RX Vref Scan: 1
1700 10:55:46.105274
1701 10:55:46.108642 Set Vref Range= 32 -> 127
1702 10:55:46.108768
1703 10:55:46.108865 RX Vref 32 -> 127, step: 1
1704 10:55:46.108957
1705 10:55:46.111972 RX Delay -111 -> 252, step: 8
1706 10:55:46.112134
1707 10:55:46.114847 Set Vref, RX VrefLevel [Byte0]: 32
1708 10:55:46.118647 [Byte1]: 32
1709 10:55:46.121973
1710 10:55:46.122152 Set Vref, RX VrefLevel [Byte0]: 33
1711 10:55:46.125167 [Byte1]: 33
1712 10:55:46.129440
1713 10:55:46.129615 Set Vref, RX VrefLevel [Byte0]: 34
1714 10:55:46.132639 [Byte1]: 34
1715 10:55:46.136627
1716 10:55:46.136803 Set Vref, RX VrefLevel [Byte0]: 35
1717 10:55:46.140320 [Byte1]: 35
1718 10:55:46.144651
1719 10:55:46.144827 Set Vref, RX VrefLevel [Byte0]: 36
1720 10:55:46.148016 [Byte1]: 36
1721 10:55:46.151877
1722 10:55:46.152052 Set Vref, RX VrefLevel [Byte0]: 37
1723 10:55:46.155772 [Byte1]: 37
1724 10:55:46.159647
1725 10:55:46.159858 Set Vref, RX VrefLevel [Byte0]: 38
1726 10:55:46.163554 [Byte1]: 38
1727 10:55:46.167425
1728 10:55:46.167737 Set Vref, RX VrefLevel [Byte0]: 39
1729 10:55:46.170713 [Byte1]: 39
1730 10:55:46.175123
1731 10:55:46.175577 Set Vref, RX VrefLevel [Byte0]: 40
1732 10:55:46.178367 [Byte1]: 40
1733 10:55:46.182746
1734 10:55:46.183234 Set Vref, RX VrefLevel [Byte0]: 41
1735 10:55:46.186436 [Byte1]: 41
1736 10:55:46.190642
1737 10:55:46.191179 Set Vref, RX VrefLevel [Byte0]: 42
1738 10:55:46.193908 [Byte1]: 42
1739 10:55:46.197863
1740 10:55:46.197945 Set Vref, RX VrefLevel [Byte0]: 43
1741 10:55:46.201591 [Byte1]: 43
1742 10:55:46.206143
1743 10:55:46.206225 Set Vref, RX VrefLevel [Byte0]: 44
1744 10:55:46.208815 [Byte1]: 44
1745 10:55:46.213058
1746 10:55:46.213133 Set Vref, RX VrefLevel [Byte0]: 45
1747 10:55:46.216792 [Byte1]: 45
1748 10:55:46.221391
1749 10:55:46.221474 Set Vref, RX VrefLevel [Byte0]: 46
1750 10:55:46.227325 [Byte1]: 46
1751 10:55:46.227415
1752 10:55:46.230444 Set Vref, RX VrefLevel [Byte0]: 47
1753 10:55:46.234402 [Byte1]: 47
1754 10:55:46.234512
1755 10:55:46.237295 Set Vref, RX VrefLevel [Byte0]: 48
1756 10:55:46.241011 [Byte1]: 48
1757 10:55:46.244082
1758 10:55:46.244165 Set Vref, RX VrefLevel [Byte0]: 49
1759 10:55:46.247642 [Byte1]: 49
1760 10:55:46.251375
1761 10:55:46.251471 Set Vref, RX VrefLevel [Byte0]: 50
1762 10:55:46.254992 [Byte1]: 50
1763 10:55:46.259055
1764 10:55:46.259157 Set Vref, RX VrefLevel [Byte0]: 51
1765 10:55:46.262269 [Byte1]: 51
1766 10:55:46.266767
1767 10:55:46.266885 Set Vref, RX VrefLevel [Byte0]: 52
1768 10:55:46.270016 [Byte1]: 52
1769 10:55:46.274414
1770 10:55:46.274495 Set Vref, RX VrefLevel [Byte0]: 53
1771 10:55:46.277776 [Byte1]: 53
1772 10:55:46.282181
1773 10:55:46.282276 Set Vref, RX VrefLevel [Byte0]: 54
1774 10:55:46.285224 [Byte1]: 54
1775 10:55:46.289878
1776 10:55:46.289980 Set Vref, RX VrefLevel [Byte0]: 55
1777 10:55:46.293069 [Byte1]: 55
1778 10:55:46.297708
1779 10:55:46.297803 Set Vref, RX VrefLevel [Byte0]: 56
1780 10:55:46.300982 [Byte1]: 56
1781 10:55:46.304800
1782 10:55:46.304882 Set Vref, RX VrefLevel [Byte0]: 57
1783 10:55:46.308369 [Byte1]: 57
1784 10:55:46.312770
1785 10:55:46.312868 Set Vref, RX VrefLevel [Byte0]: 58
1786 10:55:46.315741 [Byte1]: 58
1787 10:55:46.320157
1788 10:55:46.320268 Set Vref, RX VrefLevel [Byte0]: 59
1789 10:55:46.326775 [Byte1]: 59
1790 10:55:46.326899
1791 10:55:46.330381 Set Vref, RX VrefLevel [Byte0]: 60
1792 10:55:46.333478 [Byte1]: 60
1793 10:55:46.333579
1794 10:55:46.336625 Set Vref, RX VrefLevel [Byte0]: 61
1795 10:55:46.339870 [Byte1]: 61
1796 10:55:46.343170
1797 10:55:46.343245 Set Vref, RX VrefLevel [Byte0]: 62
1798 10:55:46.346838 [Byte1]: 62
1799 10:55:46.351063
1800 10:55:46.351137 Set Vref, RX VrefLevel [Byte0]: 63
1801 10:55:46.354299 [Byte1]: 63
1802 10:55:46.358730
1803 10:55:46.358841 Set Vref, RX VrefLevel [Byte0]: 64
1804 10:55:46.361854 [Byte1]: 64
1805 10:55:46.366204
1806 10:55:46.366279 Set Vref, RX VrefLevel [Byte0]: 65
1807 10:55:46.369356 [Byte1]: 65
1808 10:55:46.373898
1809 10:55:46.373971 Set Vref, RX VrefLevel [Byte0]: 66
1810 10:55:46.377075 [Byte1]: 66
1811 10:55:46.381468
1812 10:55:46.381550 Set Vref, RX VrefLevel [Byte0]: 67
1813 10:55:46.384625 [Byte1]: 67
1814 10:55:46.389106
1815 10:55:46.392357 Set Vref, RX VrefLevel [Byte0]: 68
1816 10:55:46.395494 [Byte1]: 68
1817 10:55:46.395576
1818 10:55:46.398585 Set Vref, RX VrefLevel [Byte0]: 69
1819 10:55:46.402503 [Byte1]: 69
1820 10:55:46.402600
1821 10:55:46.405822 Set Vref, RX VrefLevel [Byte0]: 70
1822 10:55:46.408788 [Byte1]: 70
1823 10:55:46.411960
1824 10:55:46.412061 Set Vref, RX VrefLevel [Byte0]: 71
1825 10:55:46.415144 [Byte1]: 71
1826 10:55:46.419789
1827 10:55:46.419923 Set Vref, RX VrefLevel [Byte0]: 72
1828 10:55:46.426205 [Byte1]: 72
1829 10:55:46.426288
1830 10:55:46.429048 Final RX Vref Byte 0 = 58 to rank0
1831 10:55:46.432675 Final RX Vref Byte 1 = 56 to rank0
1832 10:55:46.436175 Final RX Vref Byte 0 = 58 to rank1
1833 10:55:46.439693 Final RX Vref Byte 1 = 56 to rank1==
1834 10:55:46.442528 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 10:55:46.446148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 10:55:46.446228 ==
1837 10:55:46.446294 DQS Delay:
1838 10:55:46.449467 DQS0 = 0, DQS1 = 0
1839 10:55:46.449537 DQM Delay:
1840 10:55:46.452572 DQM0 = 81, DQM1 = 71
1841 10:55:46.452655 DQ Delay:
1842 10:55:46.455736 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1843 10:55:46.458973 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1844 10:55:46.462430 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1845 10:55:46.465389 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1846 10:55:46.465473
1847 10:55:46.465538
1848 10:55:46.475790 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1849 10:55:46.475875 CH1 RK0: MR19=606, MR18=131D
1850 10:55:46.482410 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1851 10:55:46.482494
1852 10:55:46.485400 ----->DramcWriteLeveling(PI) begin...
1853 10:55:46.485485 ==
1854 10:55:46.488415 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 10:55:46.495030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 10:55:46.495114 ==
1857 10:55:46.498810 Write leveling (Byte 0): 26 => 26
1858 10:55:46.501966 Write leveling (Byte 1): 31 => 31
1859 10:55:46.502079 DramcWriteLeveling(PI) end<-----
1860 10:55:46.502174
1861 10:55:46.505315 ==
1862 10:55:46.508375 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 10:55:46.512243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 10:55:46.512383 ==
1865 10:55:46.515180 [Gating] SW mode calibration
1866 10:55:46.521530 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 10:55:46.524784 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 10:55:46.531522 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 10:55:46.534796 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1870 10:55:46.538137 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:55:46.544690 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:55:46.548259 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:55:46.551080 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:55:46.557989 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:55:46.561110 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:55:46.564333 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:55:46.571046 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:55:46.574577 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:55:46.577528 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:55:46.584443 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:55:46.587826 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:55:46.590904 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:55:46.597843 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:55:46.600948 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1885 10:55:46.604691 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1886 10:55:46.610944 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1887 10:55:46.613968 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:55:46.617756 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:55:46.624013 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:55:46.627843 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:55:46.630900 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 10:55:46.637750 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 10:55:46.640832 0 9 4 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
1894 10:55:46.643957 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1895 10:55:46.651064 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 10:55:46.653886 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 10:55:46.657365 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 10:55:46.663874 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 10:55:46.667519 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 10:55:46.670756 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1901 10:55:46.677220 0 10 4 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 1)
1902 10:55:46.680837 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
1903 10:55:46.683864 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:55:46.691034 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:55:46.694175 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:55:46.697317 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:55:46.703832 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:55:46.707672 0 11 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1909 10:55:46.710647 0 11 4 | B1->B0 | 2d2d 3535 | 0 1 | (0 0) (0 0)
1910 10:55:46.713795 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1911 10:55:46.720602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 10:55:46.723553 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 10:55:46.729952 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 10:55:46.733234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 10:55:46.736679 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 10:55:46.743695 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 10:55:46.746872 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1918 10:55:46.749887 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1919 10:55:46.756673 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1920 10:55:46.759705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:55:46.763331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:55:46.769839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:55:46.773066 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:55:46.776577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:55:46.782809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:55:46.786081 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:55:46.789608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:55:46.795784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:55:46.799407 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:55:46.802528 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:55:46.809600 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 10:55:46.812789 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 10:55:46.816198 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1934 10:55:46.822648 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 10:55:46.823279 Total UI for P1: 0, mck2ui 16
1936 10:55:46.825798 best dqsien dly found for B0: ( 0, 14, 4)
1937 10:55:46.829549 Total UI for P1: 0, mck2ui 16
1938 10:55:46.832829 best dqsien dly found for B1: ( 0, 14, 6)
1939 10:55:46.836150 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 10:55:46.842291 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1941 10:55:46.842730
1942 10:55:46.845928 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 10:55:46.849297 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1944 10:55:46.852545 [Gating] SW calibration Done
1945 10:55:46.853095 ==
1946 10:55:46.855778 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 10:55:46.858653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 10:55:46.859230 ==
1949 10:55:46.862429 RX Vref Scan: 0
1950 10:55:46.863025
1951 10:55:46.863378 RX Vref 0 -> 0, step: 1
1952 10:55:46.863745
1953 10:55:46.865413 RX Delay -130 -> 252, step: 16
1954 10:55:46.869275 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1955 10:55:46.875182 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1956 10:55:46.878655 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1957 10:55:46.881731 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1958 10:55:46.884945 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1959 10:55:46.888746 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1960 10:55:46.895024 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1961 10:55:46.898643 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1962 10:55:46.901463 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1963 10:55:46.905141 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1964 10:55:46.908240 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1965 10:55:46.915199 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1966 10:55:46.918184 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1967 10:55:46.921316 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1968 10:55:46.925121 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1969 10:55:46.928437 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1970 10:55:46.931566 ==
1971 10:55:46.934797 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 10:55:46.938017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 10:55:46.938221 ==
1974 10:55:46.938394 DQS Delay:
1975 10:55:46.941369 DQS0 = 0, DQS1 = 0
1976 10:55:46.941546 DQM Delay:
1977 10:55:46.944546 DQM0 = 79, DQM1 = 74
1978 10:55:46.944628 DQ Delay:
1979 10:55:46.948098 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1980 10:55:46.951360 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1981 10:55:46.954547 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1982 10:55:46.957931 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1983 10:55:46.958015
1984 10:55:46.958081
1985 10:55:46.958142 ==
1986 10:55:46.961041 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 10:55:46.964781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 10:55:46.964867 ==
1989 10:55:46.964932
1990 10:55:46.964993
1991 10:55:46.967737 TX Vref Scan disable
1992 10:55:46.971358 == TX Byte 0 ==
1993 10:55:46.974389 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1994 10:55:46.977808 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1995 10:55:46.980907 == TX Byte 1 ==
1996 10:55:46.984407 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1997 10:55:46.987455 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1998 10:55:46.987542 ==
1999 10:55:46.991348 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 10:55:46.997597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 10:55:46.997710 ==
2002 10:55:47.009801 TX Vref=22, minBit 6, minWin=27, winSum=453
2003 10:55:47.012996 TX Vref=24, minBit 1, minWin=28, winSum=457
2004 10:55:47.016322 TX Vref=26, minBit 1, minWin=28, winSum=457
2005 10:55:47.019408 TX Vref=28, minBit 1, minWin=28, winSum=462
2006 10:55:47.023138 TX Vref=30, minBit 1, minWin=28, winSum=464
2007 10:55:47.029498 TX Vref=32, minBit 1, minWin=28, winSum=460
2008 10:55:47.032675 [TxChooseVref] Worse bit 1, Min win 28, Win sum 464, Final Vref 30
2009 10:55:47.032773
2010 10:55:47.036415 Final TX Range 1 Vref 30
2011 10:55:47.036524
2012 10:55:47.036622 ==
2013 10:55:47.039659 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 10:55:47.042903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 10:55:47.042992 ==
2016 10:55:47.045957
2017 10:55:47.046049
2018 10:55:47.046146 TX Vref Scan disable
2019 10:55:47.049618 == TX Byte 0 ==
2020 10:55:47.052710 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2021 10:55:47.059511 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2022 10:55:47.059620 == TX Byte 1 ==
2023 10:55:47.062730 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2024 10:55:47.069559 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2025 10:55:47.069668
2026 10:55:47.069763 [DATLAT]
2027 10:55:47.069851 Freq=800, CH1 RK1
2028 10:55:47.069941
2029 10:55:47.072492 DATLAT Default: 0xa
2030 10:55:47.072573 0, 0xFFFF, sum = 0
2031 10:55:47.076295 1, 0xFFFF, sum = 0
2032 10:55:47.079487 2, 0xFFFF, sum = 0
2033 10:55:47.079589 3, 0xFFFF, sum = 0
2034 10:55:47.082798 4, 0xFFFF, sum = 0
2035 10:55:47.082928 5, 0xFFFF, sum = 0
2036 10:55:47.085792 6, 0xFFFF, sum = 0
2037 10:55:47.085863 7, 0xFFFF, sum = 0
2038 10:55:47.089014 8, 0xFFFF, sum = 0
2039 10:55:47.089096 9, 0x0, sum = 1
2040 10:55:47.092650 10, 0x0, sum = 2
2041 10:55:47.092760 11, 0x0, sum = 3
2042 10:55:47.095639 12, 0x0, sum = 4
2043 10:55:47.095756 best_step = 10
2044 10:55:47.095821
2045 10:55:47.095917 ==
2046 10:55:47.098905 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 10:55:47.102052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 10:55:47.102158 ==
2049 10:55:47.105797 RX Vref Scan: 0
2050 10:55:47.105916
2051 10:55:47.108895 RX Vref 0 -> 0, step: 1
2052 10:55:47.109005
2053 10:55:47.109107 RX Delay -95 -> 252, step: 8
2054 10:55:47.116394 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2055 10:55:47.119823 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2056 10:55:47.122982 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2057 10:55:47.126110 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2058 10:55:47.129811 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2059 10:55:47.136170 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2060 10:55:47.139292 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2061 10:55:47.142507 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2062 10:55:47.146427 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2063 10:55:47.149577 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2064 10:55:47.156015 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2065 10:55:47.159377 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2066 10:55:47.162563 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2067 10:55:47.165712 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2068 10:55:47.172708 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2069 10:55:47.175914 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2070 10:55:47.175998 ==
2071 10:55:47.179585 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 10:55:47.182675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 10:55:47.182786 ==
2074 10:55:47.182877 DQS Delay:
2075 10:55:47.185947 DQS0 = 0, DQS1 = 0
2076 10:55:47.186057 DQM Delay:
2077 10:55:47.189321 DQM0 = 77, DQM1 = 74
2078 10:55:47.189405 DQ Delay:
2079 10:55:47.192355 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2080 10:55:47.196076 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2081 10:55:47.199119 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2082 10:55:47.202210 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2083 10:55:47.202326
2084 10:55:47.202420
2085 10:55:47.212313 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2086 10:55:47.212400 CH1 RK1: MR19=606, MR18=1D36
2087 10:55:47.218990 CH1_RK1: MR19=0x606, MR18=0x1D36, DQSOSC=396, MR23=63, INC=94, DEC=62
2088 10:55:47.222462 [RxdqsGatingPostProcess] freq 800
2089 10:55:47.229143 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 10:55:47.232089 Pre-setting of DQS Precalculation
2091 10:55:47.235292 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 10:55:47.242402 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 10:55:47.251962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 10:55:47.252049
2095 10:55:47.252115
2096 10:55:47.255796 [Calibration Summary] 1600 Mbps
2097 10:55:47.255913 CH 0, Rank 0
2098 10:55:47.258800 SW Impedance : PASS
2099 10:55:47.258968 DUTY Scan : NO K
2100 10:55:47.261994 ZQ Calibration : PASS
2101 10:55:47.265182 Jitter Meter : NO K
2102 10:55:47.265265 CBT Training : PASS
2103 10:55:47.269055 Write leveling : PASS
2104 10:55:47.269137 RX DQS gating : PASS
2105 10:55:47.272312 RX DQ/DQS(RDDQC) : PASS
2106 10:55:47.275407 TX DQ/DQS : PASS
2107 10:55:47.275490 RX DATLAT : PASS
2108 10:55:47.279008 RX DQ/DQS(Engine): PASS
2109 10:55:47.281908 TX OE : NO K
2110 10:55:47.282015 All Pass.
2111 10:55:47.282106
2112 10:55:47.282194 CH 0, Rank 1
2113 10:55:47.285153 SW Impedance : PASS
2114 10:55:47.288354 DUTY Scan : NO K
2115 10:55:47.288436 ZQ Calibration : PASS
2116 10:55:47.291890 Jitter Meter : NO K
2117 10:55:47.294988 CBT Training : PASS
2118 10:55:47.295069 Write leveling : PASS
2119 10:55:47.298446 RX DQS gating : PASS
2120 10:55:47.302068 RX DQ/DQS(RDDQC) : PASS
2121 10:55:47.302149 TX DQ/DQS : PASS
2122 10:55:47.305000 RX DATLAT : PASS
2123 10:55:47.308538 RX DQ/DQS(Engine): PASS
2124 10:55:47.308624 TX OE : NO K
2125 10:55:47.311690 All Pass.
2126 10:55:47.311837
2127 10:55:47.311960 CH 1, Rank 0
2128 10:55:47.314778 SW Impedance : PASS
2129 10:55:47.314897 DUTY Scan : NO K
2130 10:55:47.318707 ZQ Calibration : PASS
2131 10:55:47.321806 Jitter Meter : NO K
2132 10:55:47.321914 CBT Training : PASS
2133 10:55:47.325177 Write leveling : PASS
2134 10:55:47.328132 RX DQS gating : PASS
2135 10:55:47.328253 RX DQ/DQS(RDDQC) : PASS
2136 10:55:47.331789 TX DQ/DQS : PASS
2137 10:55:47.331871 RX DATLAT : PASS
2138 10:55:47.334755 RX DQ/DQS(Engine): PASS
2139 10:55:47.337843 TX OE : NO K
2140 10:55:47.337934 All Pass.
2141 10:55:47.338000
2142 10:55:47.338061 CH 1, Rank 1
2143 10:55:47.341760 SW Impedance : PASS
2144 10:55:47.344935 DUTY Scan : NO K
2145 10:55:47.345019 ZQ Calibration : PASS
2146 10:55:47.347957 Jitter Meter : NO K
2147 10:55:47.351152 CBT Training : PASS
2148 10:55:47.351226 Write leveling : PASS
2149 10:55:47.354988 RX DQS gating : PASS
2150 10:55:47.358145 RX DQ/DQS(RDDQC) : PASS
2151 10:55:47.358221 TX DQ/DQS : PASS
2152 10:55:47.361294 RX DATLAT : PASS
2153 10:55:47.364444 RX DQ/DQS(Engine): PASS
2154 10:55:47.364526 TX OE : NO K
2155 10:55:47.367817 All Pass.
2156 10:55:47.367891
2157 10:55:47.367952 DramC Write-DBI off
2158 10:55:47.370949 PER_BANK_REFRESH: Hybrid Mode
2159 10:55:47.371031 TX_TRACKING: ON
2160 10:55:47.377891 [GetDramInforAfterCalByMRR] Vendor 6.
2161 10:55:47.381126 [GetDramInforAfterCalByMRR] Revision 606.
2162 10:55:47.384024 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 10:55:47.384100 MR0 0x3b3b
2164 10:55:47.384164 MR8 0x5151
2165 10:55:47.391053 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 10:55:47.391138
2167 10:55:47.391204 MR0 0x3b3b
2168 10:55:47.391265 MR8 0x5151
2169 10:55:47.394107 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 10:55:47.394191
2171 10:55:47.404388 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 10:55:47.407346 [FAST_K] Save calibration result to emmc
2173 10:55:47.411038 [FAST_K] Save calibration result to emmc
2174 10:55:47.414043 dram_init: config_dvfs: 1
2175 10:55:47.417174 dramc_set_vcore_voltage set vcore to 662500
2176 10:55:47.420931 Read voltage for 1200, 2
2177 10:55:47.421015 Vio18 = 0
2178 10:55:47.421081 Vcore = 662500
2179 10:55:47.424075 Vdram = 0
2180 10:55:47.424158 Vddq = 0
2181 10:55:47.424231 Vmddr = 0
2182 10:55:47.430446 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 10:55:47.434446 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 10:55:47.437122 MEM_TYPE=3, freq_sel=15
2185 10:55:47.440727 sv_algorithm_assistance_LP4_1600
2186 10:55:47.444105 ============ PULL DRAM RESETB DOWN ============
2187 10:55:47.450504 ========== PULL DRAM RESETB DOWN end =========
2188 10:55:47.453553 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 10:55:47.457383 ===================================
2190 10:55:47.460531 LPDDR4 DRAM CONFIGURATION
2191 10:55:47.463774 ===================================
2192 10:55:47.463851 EX_ROW_EN[0] = 0x0
2193 10:55:47.466961 EX_ROW_EN[1] = 0x0
2194 10:55:47.467035 LP4Y_EN = 0x0
2195 10:55:47.470662 WORK_FSP = 0x0
2196 10:55:47.470769 WL = 0x4
2197 10:55:47.473750 RL = 0x4
2198 10:55:47.473851 BL = 0x2
2199 10:55:47.477034 RPST = 0x0
2200 10:55:47.477135 RD_PRE = 0x0
2201 10:55:47.480146 WR_PRE = 0x1
2202 10:55:47.480247 WR_PST = 0x0
2203 10:55:47.483347 DBI_WR = 0x0
2204 10:55:47.486884 DBI_RD = 0x0
2205 10:55:47.486974 OTF = 0x1
2206 10:55:47.490208 ===================================
2207 10:55:47.493393 ===================================
2208 10:55:47.493500 ANA top config
2209 10:55:47.497187 ===================================
2210 10:55:47.500382 DLL_ASYNC_EN = 0
2211 10:55:47.503316 ALL_SLAVE_EN = 0
2212 10:55:47.506950 NEW_RANK_MODE = 1
2213 10:55:47.507031 DLL_IDLE_MODE = 1
2214 10:55:47.509993 LP45_APHY_COMB_EN = 1
2215 10:55:47.513585 TX_ODT_DIS = 1
2216 10:55:47.516669 NEW_8X_MODE = 1
2217 10:55:47.520112 ===================================
2218 10:55:47.523211 ===================================
2219 10:55:47.526969 data_rate = 2400
2220 10:55:47.530148 CKR = 1
2221 10:55:47.530245 DQ_P2S_RATIO = 8
2222 10:55:47.533351 ===================================
2223 10:55:47.536455 CA_P2S_RATIO = 8
2224 10:55:47.540164 DQ_CA_OPEN = 0
2225 10:55:47.543217 DQ_SEMI_OPEN = 0
2226 10:55:47.546315 CA_SEMI_OPEN = 0
2227 10:55:47.549873 CA_FULL_RATE = 0
2228 10:55:47.550020 DQ_CKDIV4_EN = 0
2229 10:55:47.553458 CA_CKDIV4_EN = 0
2230 10:55:47.556640 CA_PREDIV_EN = 0
2231 10:55:47.559778 PH8_DLY = 17
2232 10:55:47.562870 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 10:55:47.566159 DQ_AAMCK_DIV = 4
2234 10:55:47.566244 CA_AAMCK_DIV = 4
2235 10:55:47.569912 CA_ADMCK_DIV = 4
2236 10:55:47.573057 DQ_TRACK_CA_EN = 0
2237 10:55:47.576070 CA_PICK = 1200
2238 10:55:47.579665 CA_MCKIO = 1200
2239 10:55:47.582744 MCKIO_SEMI = 0
2240 10:55:47.586505 PLL_FREQ = 2366
2241 10:55:47.590178 DQ_UI_PI_RATIO = 32
2242 10:55:47.590263 CA_UI_PI_RATIO = 0
2243 10:55:47.593096 ===================================
2244 10:55:47.596145 ===================================
2245 10:55:47.599312 memory_type:LPDDR4
2246 10:55:47.603071 GP_NUM : 10
2247 10:55:47.603156 SRAM_EN : 1
2248 10:55:47.606160 MD32_EN : 0
2249 10:55:47.609574 ===================================
2250 10:55:47.613015 [ANA_INIT] >>>>>>>>>>>>>>
2251 10:55:47.615924 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 10:55:47.619291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 10:55:47.622778 ===================================
2254 10:55:47.622885 data_rate = 2400,PCW = 0X5b00
2255 10:55:47.626227 ===================================
2256 10:55:47.629194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 10:55:47.635824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 10:55:47.642462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 10:55:47.646367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 10:55:47.649238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 10:55:47.652423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 10:55:47.655872 [ANA_INIT] flow start
2263 10:55:47.655956 [ANA_INIT] PLL >>>>>>>>
2264 10:55:47.659260 [ANA_INIT] PLL <<<<<<<<
2265 10:55:47.662589 [ANA_INIT] MIDPI >>>>>>>>
2266 10:55:47.665651 [ANA_INIT] MIDPI <<<<<<<<
2267 10:55:47.665759 [ANA_INIT] DLL >>>>>>>>
2268 10:55:47.669277 [ANA_INIT] DLL <<<<<<<<
2269 10:55:47.672465 [ANA_INIT] flow end
2270 10:55:47.675509 ============ LP4 DIFF to SE enter ============
2271 10:55:47.679054 ============ LP4 DIFF to SE exit ============
2272 10:55:47.682136 [ANA_INIT] <<<<<<<<<<<<<
2273 10:55:47.685924 [Flow] Enable top DCM control >>>>>
2274 10:55:47.689324 [Flow] Enable top DCM control <<<<<
2275 10:55:47.691943 Enable DLL master slave shuffle
2276 10:55:47.695442 ==============================================================
2277 10:55:47.698655 Gating Mode config
2278 10:55:47.705553 ==============================================================
2279 10:55:47.705636 Config description:
2280 10:55:47.715607 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 10:55:47.721994 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 10:55:47.725634 SELPH_MODE 0: By rank 1: By Phase
2283 10:55:47.732327 ==============================================================
2284 10:55:47.735568 GAT_TRACK_EN = 1
2285 10:55:47.738849 RX_GATING_MODE = 2
2286 10:55:47.741709 RX_GATING_TRACK_MODE = 2
2287 10:55:47.745212 SELPH_MODE = 1
2288 10:55:47.748897 PICG_EARLY_EN = 1
2289 10:55:47.751687 VALID_LAT_VALUE = 1
2290 10:55:47.755270 ==============================================================
2291 10:55:47.758237 Enter into Gating configuration >>>>
2292 10:55:47.761711 Exit from Gating configuration <<<<
2293 10:55:47.764975 Enter into DVFS_PRE_config >>>>>
2294 10:55:47.778712 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 10:55:47.778896 Exit from DVFS_PRE_config <<<<<
2296 10:55:47.781531 Enter into PICG configuration >>>>
2297 10:55:47.785149 Exit from PICG configuration <<<<
2298 10:55:47.788191 [RX_INPUT] configuration >>>>>
2299 10:55:47.791274 [RX_INPUT] configuration <<<<<
2300 10:55:47.798393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 10:55:47.801372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 10:55:47.808716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 10:55:47.814825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 10:55:47.821734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 10:55:47.827990 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 10:55:47.831254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 10:55:47.835328 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 10:55:47.838328 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 10:55:47.844966 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 10:55:47.848322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 10:55:47.851959 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 10:55:47.854663 ===================================
2313 10:55:47.858283 LPDDR4 DRAM CONFIGURATION
2314 10:55:47.861425 ===================================
2315 10:55:47.864394 EX_ROW_EN[0] = 0x0
2316 10:55:47.864855 EX_ROW_EN[1] = 0x0
2317 10:55:47.868036 LP4Y_EN = 0x0
2318 10:55:47.868500 WORK_FSP = 0x0
2319 10:55:47.871044 WL = 0x4
2320 10:55:47.871518 RL = 0x4
2321 10:55:47.874765 BL = 0x2
2322 10:55:47.875261 RPST = 0x0
2323 10:55:47.877789 RD_PRE = 0x0
2324 10:55:47.878364 WR_PRE = 0x1
2325 10:55:47.881102 WR_PST = 0x0
2326 10:55:47.881802 DBI_WR = 0x0
2327 10:55:47.884750 DBI_RD = 0x0
2328 10:55:47.885360 OTF = 0x1
2329 10:55:47.887735 ===================================
2330 10:55:47.894615 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 10:55:47.897613 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 10:55:47.900729 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 10:55:47.904157 ===================================
2334 10:55:47.907837 LPDDR4 DRAM CONFIGURATION
2335 10:55:47.911133 ===================================
2336 10:55:47.914353 EX_ROW_EN[0] = 0x10
2337 10:55:47.914980 EX_ROW_EN[1] = 0x0
2338 10:55:47.917475 LP4Y_EN = 0x0
2339 10:55:47.918048 WORK_FSP = 0x0
2340 10:55:47.920801 WL = 0x4
2341 10:55:47.921265 RL = 0x4
2342 10:55:47.924010 BL = 0x2
2343 10:55:47.924476 RPST = 0x0
2344 10:55:47.926966 RD_PRE = 0x0
2345 10:55:47.927433 WR_PRE = 0x1
2346 10:55:47.930685 WR_PST = 0x0
2347 10:55:47.931191 DBI_WR = 0x0
2348 10:55:47.934186 DBI_RD = 0x0
2349 10:55:47.934757 OTF = 0x1
2350 10:55:47.937280 ===================================
2351 10:55:47.944049 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 10:55:47.944665 ==
2353 10:55:47.947137 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 10:55:47.954280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 10:55:47.954902 ==
2356 10:55:47.955283 [Duty_Offset_Calibration]
2357 10:55:47.957293 B0:2 B1:0 CA:3
2358 10:55:47.957863
2359 10:55:47.960298 [DutyScan_Calibration_Flow] k_type=0
2360 10:55:47.969158
2361 10:55:47.969636 ==CLK 0==
2362 10:55:47.972794 Final CLK duty delay cell = 0
2363 10:55:47.975894 [0] MAX Duty = 5031%(X100), DQS PI = 12
2364 10:55:47.979583 [0] MIN Duty = 4875%(X100), DQS PI = 56
2365 10:55:47.982740 [0] AVG Duty = 4953%(X100)
2366 10:55:47.983240
2367 10:55:47.985606 CH0 CLK Duty spec in!! Max-Min= 156%
2368 10:55:47.989241 [DutyScan_Calibration_Flow] ====Done====
2369 10:55:47.989560
2370 10:55:47.992631 [DutyScan_Calibration_Flow] k_type=1
2371 10:55:48.007701
2372 10:55:48.008139 ==DQS 0 ==
2373 10:55:48.011361 Final DQS duty delay cell = 0
2374 10:55:48.014380 [0] MAX Duty = 5062%(X100), DQS PI = 12
2375 10:55:48.017584 [0] MIN Duty = 4907%(X100), DQS PI = 2
2376 10:55:48.020865 [0] AVG Duty = 4984%(X100)
2377 10:55:48.021433
2378 10:55:48.021769 ==DQS 1 ==
2379 10:55:48.024051 Final DQS duty delay cell = -4
2380 10:55:48.027251 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2381 10:55:48.030669 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2382 10:55:48.034145 [-4] AVG Duty = 4937%(X100)
2383 10:55:48.034556
2384 10:55:48.037506 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2385 10:55:48.037923
2386 10:55:48.040698 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2387 10:55:48.043776 [DutyScan_Calibration_Flow] ====Done====
2388 10:55:48.044386
2389 10:55:48.047013 [DutyScan_Calibration_Flow] k_type=3
2390 10:55:48.065074
2391 10:55:48.065488 ==DQM 0 ==
2392 10:55:48.068667 Final DQM duty delay cell = 0
2393 10:55:48.072471 [0] MAX Duty = 5093%(X100), DQS PI = 20
2394 10:55:48.075080 [0] MIN Duty = 4876%(X100), DQS PI = 0
2395 10:55:48.075578 [0] AVG Duty = 4984%(X100)
2396 10:55:48.078795
2397 10:55:48.079457 ==DQM 1 ==
2398 10:55:48.082165 Final DQM duty delay cell = 4
2399 10:55:48.085383 [4] MAX Duty = 5124%(X100), DQS PI = 50
2400 10:55:48.088727 [4] MIN Duty = 5031%(X100), DQS PI = 10
2401 10:55:48.091861 [4] AVG Duty = 5077%(X100)
2402 10:55:48.092418
2403 10:55:48.095507 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2404 10:55:48.096030
2405 10:55:48.098592 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2406 10:55:48.101761 [DutyScan_Calibration_Flow] ====Done====
2407 10:55:48.102289
2408 10:55:48.104933 [DutyScan_Calibration_Flow] k_type=2
2409 10:55:48.120604
2410 10:55:48.121390 ==DQ 0 ==
2411 10:55:48.123542 Final DQ duty delay cell = -4
2412 10:55:48.126726 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2413 10:55:48.129837 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2414 10:55:48.133665 [-4] AVG Duty = 4969%(X100)
2415 10:55:48.134227
2416 10:55:48.134587 ==DQ 1 ==
2417 10:55:48.136743 Final DQ duty delay cell = -4
2418 10:55:48.140152 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2419 10:55:48.143743 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2420 10:55:48.146906 [-4] AVG Duty = 4938%(X100)
2421 10:55:48.147476
2422 10:55:48.149745 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2423 10:55:48.150206
2424 10:55:48.153659 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 10:55:48.156505 [DutyScan_Calibration_Flow] ====Done====
2426 10:55:48.156967 ==
2427 10:55:48.160173 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 10:55:48.163542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 10:55:48.164008 ==
2430 10:55:48.166550 [Duty_Offset_Calibration]
2431 10:55:48.167199 B0:1 B1:-2 CA:0
2432 10:55:48.167572
2433 10:55:48.170127 [DutyScan_Calibration_Flow] k_type=0
2434 10:55:48.180662
2435 10:55:48.181186 ==CLK 0==
2436 10:55:48.184002 Final CLK duty delay cell = 0
2437 10:55:48.187316 [0] MAX Duty = 5031%(X100), DQS PI = 0
2438 10:55:48.190909 [0] MIN Duty = 4844%(X100), DQS PI = 26
2439 10:55:48.191381 [0] AVG Duty = 4937%(X100)
2440 10:55:48.191735
2441 10:55:48.194004 CH1 CLK Duty spec in!! Max-Min= 187%
2442 10:55:48.201051 [DutyScan_Calibration_Flow] ====Done====
2443 10:55:48.201607
2444 10:55:48.204040 [DutyScan_Calibration_Flow] k_type=1
2445 10:55:48.219256
2446 10:55:48.219827 ==DQS 0 ==
2447 10:55:48.222271 Final DQS duty delay cell = -4
2448 10:55:48.226299 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2449 10:55:48.229474 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2450 10:55:48.232557 [-4] AVG Duty = 4953%(X100)
2451 10:55:48.233114
2452 10:55:48.233475 ==DQS 1 ==
2453 10:55:48.235507 Final DQS duty delay cell = 0
2454 10:55:48.239406 [0] MAX Duty = 5093%(X100), DQS PI = 32
2455 10:55:48.242242 [0] MIN Duty = 4875%(X100), DQS PI = 10
2456 10:55:48.246152 [0] AVG Duty = 4984%(X100)
2457 10:55:48.246707
2458 10:55:48.248988 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2459 10:55:48.249539
2460 10:55:48.252105 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 10:55:48.255389 [DutyScan_Calibration_Flow] ====Done====
2462 10:55:48.255937
2463 10:55:48.259379 [DutyScan_Calibration_Flow] k_type=3
2464 10:55:48.275855
2465 10:55:48.276391 ==DQM 0 ==
2466 10:55:48.279152 Final DQM duty delay cell = 0
2467 10:55:48.282441 [0] MAX Duty = 5000%(X100), DQS PI = 54
2468 10:55:48.285966 [0] MIN Duty = 4876%(X100), DQS PI = 20
2469 10:55:48.288911 [0] AVG Duty = 4938%(X100)
2470 10:55:48.289387
2471 10:55:48.289759 ==DQM 1 ==
2472 10:55:48.292388 Final DQM duty delay cell = 0
2473 10:55:48.295908 [0] MAX Duty = 5031%(X100), DQS PI = 4
2474 10:55:48.299319 [0] MIN Duty = 4907%(X100), DQS PI = 10
2475 10:55:48.302757 [0] AVG Duty = 4969%(X100)
2476 10:55:48.303429
2477 10:55:48.305308 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2478 10:55:48.305812
2479 10:55:48.309305 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 10:55:48.312189 [DutyScan_Calibration_Flow] ====Done====
2481 10:55:48.312672
2482 10:55:48.315357 [DutyScan_Calibration_Flow] k_type=2
2483 10:55:48.332181
2484 10:55:48.332762 ==DQ 0 ==
2485 10:55:48.335866 Final DQ duty delay cell = 0
2486 10:55:48.339075 [0] MAX Duty = 5062%(X100), DQS PI = 0
2487 10:55:48.342244 [0] MIN Duty = 4969%(X100), DQS PI = 20
2488 10:55:48.342851 [0] AVG Duty = 5015%(X100)
2489 10:55:48.343348
2490 10:55:48.345798 ==DQ 1 ==
2491 10:55:48.348943 Final DQ duty delay cell = 0
2492 10:55:48.352052 [0] MAX Duty = 5093%(X100), DQS PI = 2
2493 10:55:48.356095 [0] MIN Duty = 4969%(X100), DQS PI = 58
2494 10:55:48.356705 [0] AVG Duty = 5031%(X100)
2495 10:55:48.357189
2496 10:55:48.358944 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2497 10:55:48.359425
2498 10:55:48.362031 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2499 10:55:48.369187 [DutyScan_Calibration_Flow] ====Done====
2500 10:55:48.371987 nWR fixed to 30
2501 10:55:48.372565 [ModeRegInit_LP4] CH0 RK0
2502 10:55:48.375624 [ModeRegInit_LP4] CH0 RK1
2503 10:55:48.378818 [ModeRegInit_LP4] CH1 RK0
2504 10:55:48.379440 [ModeRegInit_LP4] CH1 RK1
2505 10:55:48.381958 match AC timing 7
2506 10:55:48.385328 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 10:55:48.388424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 10:55:48.395230 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 10:55:48.398820 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 10:55:48.405193 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 10:55:48.405659 ==
2512 10:55:48.408895 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 10:55:48.411538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 10:55:48.412013 ==
2515 10:55:48.418360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 10:55:48.425181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 10:55:48.432555 [CA 0] Center 40 (10~71) winsize 62
2518 10:55:48.435738 [CA 1] Center 39 (9~70) winsize 62
2519 10:55:48.438616 [CA 2] Center 36 (6~66) winsize 61
2520 10:55:48.442308 [CA 3] Center 35 (5~66) winsize 62
2521 10:55:48.445222 [CA 4] Center 34 (4~65) winsize 62
2522 10:55:48.448671 [CA 5] Center 33 (3~63) winsize 61
2523 10:55:48.449251
2524 10:55:48.451907 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2525 10:55:48.452375
2526 10:55:48.455333 [CATrainingPosCal] consider 1 rank data
2527 10:55:48.459165 u2DelayCellTimex100 = 270/100 ps
2528 10:55:48.461990 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2529 10:55:48.468181 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 10:55:48.472071 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2531 10:55:48.475475 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 10:55:48.478649 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 10:55:48.482456 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2534 10:55:48.483097
2535 10:55:48.485377 CA PerBit enable=1, Macro0, CA PI delay=33
2536 10:55:48.485950
2537 10:55:48.488453 [CBTSetCACLKResult] CA Dly = 33
2538 10:55:48.491558 CS Dly: 7 (0~38)
2539 10:55:48.492023 ==
2540 10:55:48.495102 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 10:55:48.498631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 10:55:48.499264 ==
2543 10:55:48.505270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 10:55:48.507988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 10:55:48.518001 [CA 0] Center 40 (10~71) winsize 62
2546 10:55:48.521309 [CA 1] Center 40 (10~70) winsize 61
2547 10:55:48.524878 [CA 2] Center 35 (5~66) winsize 62
2548 10:55:48.527941 [CA 3] Center 35 (5~66) winsize 62
2549 10:55:48.531463 [CA 4] Center 34 (4~65) winsize 62
2550 10:55:48.534788 [CA 5] Center 33 (3~63) winsize 61
2551 10:55:48.535393
2552 10:55:48.538206 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2553 10:55:48.538635
2554 10:55:48.541114 [CATrainingPosCal] consider 2 rank data
2555 10:55:48.544534 u2DelayCellTimex100 = 270/100 ps
2556 10:55:48.547967 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2557 10:55:48.554728 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2558 10:55:48.557989 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2559 10:55:48.560959 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 10:55:48.564993 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2561 10:55:48.568029 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2562 10:55:48.568594
2563 10:55:48.571172 CA PerBit enable=1, Macro0, CA PI delay=33
2564 10:55:48.571748
2565 10:55:48.574995 [CBTSetCACLKResult] CA Dly = 33
2566 10:55:48.577843 CS Dly: 8 (0~40)
2567 10:55:48.578405
2568 10:55:48.581366 ----->DramcWriteLeveling(PI) begin...
2569 10:55:48.581841 ==
2570 10:55:48.584529 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 10:55:48.587770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 10:55:48.588345 ==
2573 10:55:48.590720 Write leveling (Byte 0): 34 => 34
2574 10:55:48.594237 Write leveling (Byte 1): 30 => 30
2575 10:55:48.597974 DramcWriteLeveling(PI) end<-----
2576 10:55:48.598542
2577 10:55:48.598943 ==
2578 10:55:48.600770 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 10:55:48.604435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 10:55:48.605010 ==
2581 10:55:48.607833 [Gating] SW mode calibration
2582 10:55:48.614450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 10:55:48.621847 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 10:55:48.624324 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 10:55:48.627233 0 15 4 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2586 10:55:48.633744 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 10:55:48.637275 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 10:55:48.640436 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 10:55:48.647342 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 10:55:48.650888 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 10:55:48.653877 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2592 10:55:48.660450 1 0 0 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (0 0)
2593 10:55:48.663447 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 10:55:48.667380 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 10:55:48.673478 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 10:55:48.677385 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 10:55:48.680339 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 10:55:48.687110 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 10:55:48.690224 1 0 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2600 10:55:48.693330 1 1 0 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
2601 10:55:48.700030 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2602 10:55:48.703646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 10:55:48.706668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 10:55:48.713577 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 10:55:48.716507 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 10:55:48.720122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 10:55:48.726613 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 10:55:48.729981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2609 10:55:48.733428 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 10:55:48.739768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:55:48.743192 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:55:48.746306 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:55:48.752875 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:55:48.756626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:55:48.760451 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:55:48.766635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:55:48.769733 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:55:48.772857 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:55:48.779639 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:55:48.782793 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:55:48.786090 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 10:55:48.792800 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 10:55:48.795952 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 10:55:48.799744 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2625 10:55:48.802775 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 10:55:48.806510 Total UI for P1: 0, mck2ui 16
2627 10:55:48.809634 best dqsien dly found for B0: ( 1, 4, 0)
2628 10:55:48.816065 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 10:55:48.819590 Total UI for P1: 0, mck2ui 16
2630 10:55:48.823003 best dqsien dly found for B1: ( 1, 4, 4)
2631 10:55:48.825984 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2632 10:55:48.829585 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2633 10:55:48.830011
2634 10:55:48.832737 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 10:55:48.835801 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2636 10:55:48.839147 [Gating] SW calibration Done
2637 10:55:48.839571 ==
2638 10:55:48.842512 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 10:55:48.846097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 10:55:48.846526 ==
2641 10:55:48.849011 RX Vref Scan: 0
2642 10:55:48.849437
2643 10:55:48.849775 RX Vref 0 -> 0, step: 1
2644 10:55:48.852707
2645 10:55:48.853128 RX Delay -40 -> 252, step: 8
2646 10:55:48.859258 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2647 10:55:48.862330 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2648 10:55:48.866026 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2649 10:55:48.868887 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2650 10:55:48.872585 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2651 10:55:48.878865 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2652 10:55:48.882387 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2653 10:55:48.885708 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2654 10:55:48.889074 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2655 10:55:48.892150 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2656 10:55:48.895236 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2657 10:55:48.901993 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2658 10:55:48.905101 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2659 10:55:48.908720 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2660 10:55:48.912128 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2661 10:55:48.918817 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2662 10:55:48.919302 ==
2663 10:55:48.921806 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 10:55:48.925123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 10:55:48.925579 ==
2666 10:55:48.925918 DQS Delay:
2667 10:55:48.928479 DQS0 = 0, DQS1 = 0
2668 10:55:48.928908 DQM Delay:
2669 10:55:48.932336 DQM0 = 112, DQM1 = 102
2670 10:55:48.933008 DQ Delay:
2671 10:55:48.934923 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2672 10:55:48.938684 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2673 10:55:48.941677 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2674 10:55:48.944976 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2675 10:55:48.945487
2676 10:55:48.946035
2677 10:55:48.946469 ==
2678 10:55:48.948311 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 10:55:48.954962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 10:55:48.955405 ==
2681 10:55:48.955839
2682 10:55:48.956246
2683 10:55:48.956643 TX Vref Scan disable
2684 10:55:48.958609 == TX Byte 0 ==
2685 10:55:48.961915 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2686 10:55:48.968642 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2687 10:55:48.969078 == TX Byte 1 ==
2688 10:55:48.972227 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2689 10:55:48.978426 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2690 10:55:48.978900 ==
2691 10:55:48.981509 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 10:55:48.985221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 10:55:48.985661 ==
2694 10:55:48.997019 TX Vref=22, minBit 1, minWin=25, winSum=409
2695 10:55:49.000100 TX Vref=24, minBit 7, minWin=25, winSum=418
2696 10:55:49.003427 TX Vref=26, minBit 7, minWin=25, winSum=425
2697 10:55:49.006948 TX Vref=28, minBit 4, minWin=26, winSum=431
2698 10:55:49.010153 TX Vref=30, minBit 2, minWin=26, winSum=428
2699 10:55:49.016631 TX Vref=32, minBit 2, minWin=26, winSum=425
2700 10:55:49.019696 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 28
2701 10:55:49.020328
2702 10:55:49.023500 Final TX Range 1 Vref 28
2703 10:55:49.023928
2704 10:55:49.024261 ==
2705 10:55:49.026709 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 10:55:49.029945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 10:55:49.030382 ==
2708 10:55:49.033293
2709 10:55:49.033770
2710 10:55:49.034121 TX Vref Scan disable
2711 10:55:49.036813 == TX Byte 0 ==
2712 10:55:49.039876 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2713 10:55:49.046478 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2714 10:55:49.047071 == TX Byte 1 ==
2715 10:55:49.050080 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2716 10:55:49.056742 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2717 10:55:49.057183
2718 10:55:49.057522 [DATLAT]
2719 10:55:49.057834 Freq=1200, CH0 RK0
2720 10:55:49.058160
2721 10:55:49.060384 DATLAT Default: 0xd
2722 10:55:49.060837 0, 0xFFFF, sum = 0
2723 10:55:49.062922 1, 0xFFFF, sum = 0
2724 10:55:49.063356 2, 0xFFFF, sum = 0
2725 10:55:49.066420 3, 0xFFFF, sum = 0
2726 10:55:49.069916 4, 0xFFFF, sum = 0
2727 10:55:49.070348 5, 0xFFFF, sum = 0
2728 10:55:49.073261 6, 0xFFFF, sum = 0
2729 10:55:49.073691 7, 0xFFFF, sum = 0
2730 10:55:49.076330 8, 0xFFFF, sum = 0
2731 10:55:49.076762 9, 0xFFFF, sum = 0
2732 10:55:49.079941 10, 0xFFFF, sum = 0
2733 10:55:49.080410 11, 0xFFFF, sum = 0
2734 10:55:49.083354 12, 0x0, sum = 1
2735 10:55:49.083785 13, 0x0, sum = 2
2736 10:55:49.086154 14, 0x0, sum = 3
2737 10:55:49.086657 15, 0x0, sum = 4
2738 10:55:49.087055 best_step = 13
2739 10:55:49.089716
2740 10:55:49.090136 ==
2741 10:55:49.092957 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 10:55:49.096706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 10:55:49.097388 ==
2744 10:55:49.098055 RX Vref Scan: 1
2745 10:55:49.098666
2746 10:55:49.099698 Set Vref Range= 32 -> 127
2747 10:55:49.100251
2748 10:55:49.102880 RX Vref 32 -> 127, step: 1
2749 10:55:49.103293
2750 10:55:49.106606 RX Delay -37 -> 252, step: 4
2751 10:55:49.107191
2752 10:55:49.109759 Set Vref, RX VrefLevel [Byte0]: 32
2753 10:55:49.112949 [Byte1]: 32
2754 10:55:49.113508
2755 10:55:49.116372 Set Vref, RX VrefLevel [Byte0]: 33
2756 10:55:49.120137 [Byte1]: 33
2757 10:55:49.123593
2758 10:55:49.124237 Set Vref, RX VrefLevel [Byte0]: 34
2759 10:55:49.126633 [Byte1]: 34
2760 10:55:49.131514
2761 10:55:49.132047 Set Vref, RX VrefLevel [Byte0]: 35
2762 10:55:49.137429 [Byte1]: 35
2763 10:55:49.138031
2764 10:55:49.140846 Set Vref, RX VrefLevel [Byte0]: 36
2765 10:55:49.144246 [Byte1]: 36
2766 10:55:49.144886
2767 10:55:49.147574 Set Vref, RX VrefLevel [Byte0]: 37
2768 10:55:49.150575 [Byte1]: 37
2769 10:55:49.155357
2770 10:55:49.155959 Set Vref, RX VrefLevel [Byte0]: 38
2771 10:55:49.158475 [Byte1]: 38
2772 10:55:49.163220
2773 10:55:49.163844 Set Vref, RX VrefLevel [Byte0]: 39
2774 10:55:49.166264 [Byte1]: 39
2775 10:55:49.170873
2776 10:55:49.171475 Set Vref, RX VrefLevel [Byte0]: 40
2777 10:55:49.174483 [Byte1]: 40
2778 10:55:49.179125
2779 10:55:49.179701 Set Vref, RX VrefLevel [Byte0]: 41
2780 10:55:49.182594 [Byte1]: 41
2781 10:55:49.187401
2782 10:55:49.187869 Set Vref, RX VrefLevel [Byte0]: 42
2783 10:55:49.190369 [Byte1]: 42
2784 10:55:49.194942
2785 10:55:49.195441 Set Vref, RX VrefLevel [Byte0]: 43
2786 10:55:49.198655 [Byte1]: 43
2787 10:55:49.203655
2788 10:55:49.204085 Set Vref, RX VrefLevel [Byte0]: 44
2789 10:55:49.206912 [Byte1]: 44
2790 10:55:49.211137
2791 10:55:49.211577 Set Vref, RX VrefLevel [Byte0]: 45
2792 10:55:49.214784 [Byte1]: 45
2793 10:55:49.219240
2794 10:55:49.219681 Set Vref, RX VrefLevel [Byte0]: 46
2795 10:55:49.222775 [Byte1]: 46
2796 10:55:49.227170
2797 10:55:49.227610 Set Vref, RX VrefLevel [Byte0]: 47
2798 10:55:49.230877 [Byte1]: 47
2799 10:55:49.235309
2800 10:55:49.235751 Set Vref, RX VrefLevel [Byte0]: 48
2801 10:55:49.238895 [Byte1]: 48
2802 10:55:49.243525
2803 10:55:49.244092 Set Vref, RX VrefLevel [Byte0]: 49
2804 10:55:49.246431 [Byte1]: 49
2805 10:55:49.251284
2806 10:55:49.251835 Set Vref, RX VrefLevel [Byte0]: 50
2807 10:55:49.254528 [Byte1]: 50
2808 10:55:49.259399
2809 10:55:49.259953 Set Vref, RX VrefLevel [Byte0]: 51
2810 10:55:49.262442 [Byte1]: 51
2811 10:55:49.267591
2812 10:55:49.268017 Set Vref, RX VrefLevel [Byte0]: 52
2813 10:55:49.270671 [Byte1]: 52
2814 10:55:49.275499
2815 10:55:49.276200 Set Vref, RX VrefLevel [Byte0]: 53
2816 10:55:49.278194 [Byte1]: 53
2817 10:55:49.283443
2818 10:55:49.283893 Set Vref, RX VrefLevel [Byte0]: 54
2819 10:55:49.286770 [Byte1]: 54
2820 10:55:49.290932
2821 10:55:49.291421 Set Vref, RX VrefLevel [Byte0]: 55
2822 10:55:49.294820 [Byte1]: 55
2823 10:55:49.299165
2824 10:55:49.302639 Set Vref, RX VrefLevel [Byte0]: 56
2825 10:55:49.303133 [Byte1]: 56
2826 10:55:49.307560
2827 10:55:49.308002 Set Vref, RX VrefLevel [Byte0]: 57
2828 10:55:49.310734 [Byte1]: 57
2829 10:55:49.315611
2830 10:55:49.316051 Set Vref, RX VrefLevel [Byte0]: 58
2831 10:55:49.318757 [Byte1]: 58
2832 10:55:49.323245
2833 10:55:49.323682 Set Vref, RX VrefLevel [Byte0]: 59
2834 10:55:49.326773 [Byte1]: 59
2835 10:55:49.331715
2836 10:55:49.332141 Set Vref, RX VrefLevel [Byte0]: 60
2837 10:55:49.334878 [Byte1]: 60
2838 10:55:49.339129
2839 10:55:49.339556 Set Vref, RX VrefLevel [Byte0]: 61
2840 10:55:49.342749 [Byte1]: 61
2841 10:55:49.347456
2842 10:55:49.347887 Set Vref, RX VrefLevel [Byte0]: 62
2843 10:55:49.350898 [Byte1]: 62
2844 10:55:49.355119
2845 10:55:49.355547 Set Vref, RX VrefLevel [Byte0]: 63
2846 10:55:49.358634 [Byte1]: 63
2847 10:55:49.363179
2848 10:55:49.363589 Set Vref, RX VrefLevel [Byte0]: 64
2849 10:55:49.366741 [Byte1]: 64
2850 10:55:49.371100
2851 10:55:49.371521 Set Vref, RX VrefLevel [Byte0]: 65
2852 10:55:49.374959 [Byte1]: 65
2853 10:55:49.379288
2854 10:55:49.379710 Set Vref, RX VrefLevel [Byte0]: 66
2855 10:55:49.382964 [Byte1]: 66
2856 10:55:49.387032
2857 10:55:49.387453 Set Vref, RX VrefLevel [Byte0]: 67
2858 10:55:49.390581 [Byte1]: 67
2859 10:55:49.395140
2860 10:55:49.395563 Set Vref, RX VrefLevel [Byte0]: 68
2861 10:55:49.398762 [Byte1]: 68
2862 10:55:49.403564
2863 10:55:49.403990 Set Vref, RX VrefLevel [Byte0]: 69
2864 10:55:49.406705 [Byte1]: 69
2865 10:55:49.411487
2866 10:55:49.411908 Set Vref, RX VrefLevel [Byte0]: 70
2867 10:55:49.414609 [Byte1]: 70
2868 10:55:49.419625
2869 10:55:49.420059 Set Vref, RX VrefLevel [Byte0]: 71
2870 10:55:49.422693 [Byte1]: 71
2871 10:55:49.427172
2872 10:55:49.427616 Set Vref, RX VrefLevel [Byte0]: 72
2873 10:55:49.430645 [Byte1]: 72
2874 10:55:49.435560
2875 10:55:49.435983 Set Vref, RX VrefLevel [Byte0]: 73
2876 10:55:49.438585 [Byte1]: 73
2877 10:55:49.443586
2878 10:55:49.444045 Set Vref, RX VrefLevel [Byte0]: 74
2879 10:55:49.446633 [Byte1]: 74
2880 10:55:49.451416
2881 10:55:49.451846 Final RX Vref Byte 0 = 62 to rank0
2882 10:55:49.454734 Final RX Vref Byte 1 = 47 to rank0
2883 10:55:49.457931 Final RX Vref Byte 0 = 62 to rank1
2884 10:55:49.461416 Final RX Vref Byte 1 = 47 to rank1==
2885 10:55:49.464335 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 10:55:49.471146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 10:55:49.471742 ==
2888 10:55:49.472214 DQS Delay:
2889 10:55:49.474534 DQS0 = 0, DQS1 = 0
2890 10:55:49.475073 DQM Delay:
2891 10:55:49.475414 DQM0 = 112, DQM1 = 98
2892 10:55:49.477977 DQ Delay:
2893 10:55:49.481351 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2894 10:55:49.484429 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =120
2895 10:55:49.487422 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2896 10:55:49.491063 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2897 10:55:49.491490
2898 10:55:49.491824
2899 10:55:49.500806 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2900 10:55:49.501432 CH0 RK0: MR19=303, MR18=FDFD
2901 10:55:49.507638 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2902 10:55:49.508065
2903 10:55:49.510669 ----->DramcWriteLeveling(PI) begin...
2904 10:55:49.511177 ==
2905 10:55:49.514249 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 10:55:49.520887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 10:55:49.521315 ==
2908 10:55:49.524015 Write leveling (Byte 0): 31 => 31
2909 10:55:49.524440 Write leveling (Byte 1): 29 => 29
2910 10:55:49.527087 DramcWriteLeveling(PI) end<-----
2911 10:55:49.527512
2912 10:55:49.530884 ==
2913 10:55:49.531311 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 10:55:49.537615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 10:55:49.538040 ==
2916 10:55:49.540744 [Gating] SW mode calibration
2917 10:55:49.547019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 10:55:49.551066 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 10:55:49.556980 0 15 0 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
2920 10:55:49.560577 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 10:55:49.563488 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 10:55:49.570441 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 10:55:49.573481 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 10:55:49.576907 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 10:55:49.583786 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2926 10:55:49.586948 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2927 10:55:49.590083 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2928 10:55:49.596714 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 10:55:49.600378 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 10:55:49.603658 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 10:55:49.610403 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 10:55:49.613767 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 10:55:49.616556 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2934 10:55:49.623355 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2935 10:55:49.626912 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2936 10:55:49.630002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 10:55:49.636878 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 10:55:49.639835 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 10:55:49.643414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 10:55:49.646603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 10:55:49.653703 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 10:55:49.656464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 10:55:49.659645 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2944 10:55:49.666569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 10:55:49.669641 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 10:55:49.673392 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 10:55:49.679911 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 10:55:49.683455 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 10:55:49.686233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 10:55:49.693268 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 10:55:49.696435 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 10:55:49.699358 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 10:55:49.706009 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 10:55:49.709537 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 10:55:49.712838 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 10:55:49.718864 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 10:55:49.722057 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2958 10:55:49.725517 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 10:55:49.731871 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2960 10:55:49.735635 Total UI for P1: 0, mck2ui 16
2961 10:55:49.738768 best dqsien dly found for B0: ( 1, 3, 26)
2962 10:55:49.741774 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 10:55:49.745321 Total UI for P1: 0, mck2ui 16
2964 10:55:49.749046 best dqsien dly found for B1: ( 1, 4, 0)
2965 10:55:49.752079 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2966 10:55:49.755421 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2967 10:55:49.755503
2968 10:55:49.758980 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2969 10:55:49.762102 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2970 10:55:49.765237 [Gating] SW calibration Done
2971 10:55:49.765319 ==
2972 10:55:49.768487 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 10:55:49.775291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 10:55:49.775374 ==
2975 10:55:49.775440 RX Vref Scan: 0
2976 10:55:49.775501
2977 10:55:49.778337 RX Vref 0 -> 0, step: 1
2978 10:55:49.778420
2979 10:55:49.782108 RX Delay -40 -> 252, step: 8
2980 10:55:49.785011 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2981 10:55:49.788507 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2982 10:55:49.792016 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2983 10:55:49.794985 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2984 10:55:49.801575 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2985 10:55:49.804656 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2986 10:55:49.808427 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2987 10:55:49.811404 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2988 10:55:49.814430 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2989 10:55:49.821576 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2990 10:55:49.824510 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2991 10:55:49.827558 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2992 10:55:49.830975 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2993 10:55:49.834505 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2994 10:55:49.841112 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2995 10:55:49.844123 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2996 10:55:49.844207 ==
2997 10:55:49.847778 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 10:55:49.850743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 10:55:49.850851 ==
3000 10:55:49.854641 DQS Delay:
3001 10:55:49.854725 DQS0 = 0, DQS1 = 0
3002 10:55:49.854825 DQM Delay:
3003 10:55:49.857734 DQM0 = 112, DQM1 = 99
3004 10:55:49.857818 DQ Delay:
3005 10:55:49.860851 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3006 10:55:49.863984 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3007 10:55:49.867655 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
3008 10:55:49.873938 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
3009 10:55:49.874021
3010 10:55:49.874104
3011 10:55:49.874182 ==
3012 10:55:49.877656 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 10:55:49.880681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 10:55:49.880765 ==
3015 10:55:49.880849
3016 10:55:49.880927
3017 10:55:49.883839 TX Vref Scan disable
3018 10:55:49.883923 == TX Byte 0 ==
3019 10:55:49.891067 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3020 10:55:49.894042 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3021 10:55:49.897059 == TX Byte 1 ==
3022 10:55:49.900716 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3023 10:55:49.903903 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3024 10:55:49.903987 ==
3025 10:55:49.906807 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 10:55:49.910549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 10:55:49.910632 ==
3028 10:55:49.923759 TX Vref=22, minBit 0, minWin=26, winSum=424
3029 10:55:49.926717 TX Vref=24, minBit 1, minWin=26, winSum=431
3030 10:55:49.930366 TX Vref=26, minBit 1, minWin=27, winSum=436
3031 10:55:49.933852 TX Vref=28, minBit 1, minWin=27, winSum=442
3032 10:55:49.937106 TX Vref=30, minBit 10, minWin=26, winSum=439
3033 10:55:49.943357 TX Vref=32, minBit 10, minWin=26, winSum=439
3034 10:55:49.946805 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
3035 10:55:49.946936
3036 10:55:49.950143 Final TX Range 1 Vref 28
3037 10:55:49.950229
3038 10:55:49.950296 ==
3039 10:55:49.953672 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 10:55:49.956840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 10:55:49.956923 ==
3042 10:55:49.959900
3043 10:55:49.959981
3044 10:55:49.960045 TX Vref Scan disable
3045 10:55:49.963679 == TX Byte 0 ==
3046 10:55:49.966776 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3047 10:55:49.973631 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3048 10:55:49.973713 == TX Byte 1 ==
3049 10:55:49.976773 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3050 10:55:49.983480 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3051 10:55:49.983563
3052 10:55:49.983627 [DATLAT]
3053 10:55:49.983687 Freq=1200, CH0 RK1
3054 10:55:49.983745
3055 10:55:49.986468 DATLAT Default: 0xd
3056 10:55:49.989738 0, 0xFFFF, sum = 0
3057 10:55:49.989822 1, 0xFFFF, sum = 0
3058 10:55:49.992876 2, 0xFFFF, sum = 0
3059 10:55:49.992960 3, 0xFFFF, sum = 0
3060 10:55:49.996379 4, 0xFFFF, sum = 0
3061 10:55:49.996470 5, 0xFFFF, sum = 0
3062 10:55:49.999432 6, 0xFFFF, sum = 0
3063 10:55:49.999515 7, 0xFFFF, sum = 0
3064 10:55:50.003090 8, 0xFFFF, sum = 0
3065 10:55:50.003173 9, 0xFFFF, sum = 0
3066 10:55:50.006121 10, 0xFFFF, sum = 0
3067 10:55:50.006204 11, 0xFFFF, sum = 0
3068 10:55:50.009436 12, 0x0, sum = 1
3069 10:55:50.009520 13, 0x0, sum = 2
3070 10:55:50.012755 14, 0x0, sum = 3
3071 10:55:50.012838 15, 0x0, sum = 4
3072 10:55:50.016384 best_step = 13
3073 10:55:50.016466
3074 10:55:50.016530 ==
3075 10:55:50.019220 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 10:55:50.022822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 10:55:50.022947 ==
3078 10:55:50.026143 RX Vref Scan: 0
3079 10:55:50.026225
3080 10:55:50.026289 RX Vref 0 -> 0, step: 1
3081 10:55:50.026348
3082 10:55:50.029425 RX Delay -37 -> 252, step: 4
3083 10:55:50.036051 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3084 10:55:50.039536 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3085 10:55:50.042354 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3086 10:55:50.046120 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3087 10:55:50.049127 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3088 10:55:50.055820 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3089 10:55:50.058996 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3090 10:55:50.062697 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3091 10:55:50.065746 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3092 10:55:50.068941 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3093 10:55:50.075850 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3094 10:55:50.079086 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3095 10:55:50.082150 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3096 10:55:50.085850 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3097 10:55:50.088860 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3098 10:55:50.095641 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3099 10:55:50.095723 ==
3100 10:55:50.098691 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 10:55:50.102237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 10:55:50.102321 ==
3103 10:55:50.102408 DQS Delay:
3104 10:55:50.105398 DQS0 = 0, DQS1 = 0
3105 10:55:50.105480 DQM Delay:
3106 10:55:50.108476 DQM0 = 111, DQM1 = 99
3107 10:55:50.108558 DQ Delay:
3108 10:55:50.112061 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3109 10:55:50.115087 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3110 10:55:50.118669 DQ8 =88, DQ9 =82, DQ10 =100, DQ11 =90
3111 10:55:50.121920 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3112 10:55:50.122002
3113 10:55:50.125186
3114 10:55:50.131791 [DQSOSCAuto] RK1, (LSB)MR18= 0xef6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3115 10:55:50.135090 CH0 RK1: MR19=403, MR18=EF6
3116 10:55:50.141897 CH0_RK1: MR19=0x403, MR18=0xEF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3117 10:55:50.141980 [RxdqsGatingPostProcess] freq 1200
3118 10:55:50.148279 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 10:55:50.151636 best DQS0 dly(2T, 0.5T) = (0, 12)
3120 10:55:50.155190 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 10:55:50.158182 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3122 10:55:50.161773 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 10:55:50.164765 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 10:55:50.167958 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 10:55:50.171624 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 10:55:50.174721 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 10:55:50.177907 Pre-setting of DQS Precalculation
3128 10:55:50.181093 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 10:55:50.181175 ==
3130 10:55:50.185055 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 10:55:50.187958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 10:55:50.190973 ==
3133 10:55:50.194662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 10:55:50.200905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 10:55:50.209473 [CA 0] Center 37 (7~67) winsize 61
3136 10:55:50.212527 [CA 1] Center 37 (7~68) winsize 62
3137 10:55:50.216099 [CA 2] Center 34 (5~64) winsize 60
3138 10:55:50.219130 [CA 3] Center 34 (4~64) winsize 61
3139 10:55:50.222353 [CA 4] Center 34 (5~64) winsize 60
3140 10:55:50.225902 [CA 5] Center 33 (3~63) winsize 61
3141 10:55:50.225986
3142 10:55:50.228948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3143 10:55:50.229033
3144 10:55:50.232388 [CATrainingPosCal] consider 1 rank data
3145 10:55:50.235653 u2DelayCellTimex100 = 270/100 ps
3146 10:55:50.239355 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3147 10:55:50.245960 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 10:55:50.248806 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3149 10:55:50.252288 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 10:55:50.255614 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3151 10:55:50.259056 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 10:55:50.259141
3153 10:55:50.262053 CA PerBit enable=1, Macro0, CA PI delay=33
3154 10:55:50.262139
3155 10:55:50.265425 [CBTSetCACLKResult] CA Dly = 33
3156 10:55:50.269225 CS Dly: 6 (0~37)
3157 10:55:50.269310 ==
3158 10:55:50.272037 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 10:55:50.275796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 10:55:50.275882 ==
3161 10:55:50.281948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 10:55:50.285590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3163 10:55:50.294794 [CA 0] Center 37 (7~67) winsize 61
3164 10:55:50.298463 [CA 1] Center 37 (7~68) winsize 62
3165 10:55:50.301533 [CA 2] Center 34 (4~65) winsize 62
3166 10:55:50.304655 [CA 3] Center 33 (3~64) winsize 62
3167 10:55:50.308300 [CA 4] Center 34 (4~65) winsize 62
3168 10:55:50.311352 [CA 5] Center 33 (3~63) winsize 61
3169 10:55:50.311436
3170 10:55:50.315087 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3171 10:55:50.315173
3172 10:55:50.318099 [CATrainingPosCal] consider 2 rank data
3173 10:55:50.321767 u2DelayCellTimex100 = 270/100 ps
3174 10:55:50.324967 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3175 10:55:50.331297 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3176 10:55:50.334596 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3177 10:55:50.338011 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 10:55:50.341430 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3179 10:55:50.344704 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3180 10:55:50.344812
3181 10:55:50.347920 CA PerBit enable=1, Macro0, CA PI delay=33
3182 10:55:50.348027
3183 10:55:50.351363 [CBTSetCACLKResult] CA Dly = 33
3184 10:55:50.351477 CS Dly: 7 (0~40)
3185 10:55:50.354708
3186 10:55:50.358420 ----->DramcWriteLeveling(PI) begin...
3187 10:55:50.358536 ==
3188 10:55:50.361469 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 10:55:50.364380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 10:55:50.364481 ==
3191 10:55:50.368051 Write leveling (Byte 0): 24 => 24
3192 10:55:50.371220 Write leveling (Byte 1): 30 => 30
3193 10:55:50.374377 DramcWriteLeveling(PI) end<-----
3194 10:55:50.374451
3195 10:55:50.374514 ==
3196 10:55:50.377837 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 10:55:50.380965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 10:55:50.381054 ==
3199 10:55:50.384723 [Gating] SW mode calibration
3200 10:55:50.390842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 10:55:50.397950 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 10:55:50.400919 0 15 0 | B1->B0 | 2828 2727 | 1 1 | (1 1) (1 1)
3203 10:55:50.404562 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 10:55:50.410765 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 10:55:50.414203 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 10:55:50.417439 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 10:55:50.424147 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 10:55:50.427755 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3209 10:55:50.430902 0 15 28 | B1->B0 | 3232 3232 | 0 0 | (0 1) (0 1)
3210 10:55:50.437749 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3211 10:55:50.440937 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 10:55:50.444655 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 10:55:50.450735 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 10:55:50.454352 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 10:55:50.457350 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 10:55:50.464352 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 10:55:50.467582 1 0 28 | B1->B0 | 3f3f 3737 | 0 1 | (0 0) (0 0)
3218 10:55:50.471046 1 1 0 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
3219 10:55:50.477451 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 10:55:50.480969 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 10:55:50.484613 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 10:55:50.487518 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 10:55:50.494161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 10:55:50.497780 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 10:55:50.500618 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 10:55:50.507672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 10:55:50.510680 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 10:55:50.513733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 10:55:50.520433 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 10:55:50.524491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 10:55:50.527312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 10:55:50.533892 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 10:55:50.536985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 10:55:50.540322 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 10:55:50.547116 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 10:55:50.550119 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 10:55:50.553647 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 10:55:50.560508 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 10:55:50.563302 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 10:55:50.567145 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 10:55:50.573539 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3242 10:55:50.576865 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 10:55:50.580269 Total UI for P1: 0, mck2ui 16
3244 10:55:50.583476 best dqsien dly found for B0: ( 1, 3, 28)
3245 10:55:50.586433 Total UI for P1: 0, mck2ui 16
3246 10:55:50.590242 best dqsien dly found for B1: ( 1, 3, 28)
3247 10:55:50.593428 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3248 10:55:50.596368 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3249 10:55:50.596793
3250 10:55:50.600179 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3251 10:55:50.603313 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3252 10:55:50.606568 [Gating] SW calibration Done
3253 10:55:50.607029 ==
3254 10:55:50.610076 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 10:55:50.616742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 10:55:50.617173 ==
3257 10:55:50.617506 RX Vref Scan: 0
3258 10:55:50.617817
3259 10:55:50.620021 RX Vref 0 -> 0, step: 1
3260 10:55:50.620445
3261 10:55:50.623052 RX Delay -40 -> 252, step: 8
3262 10:55:50.626748 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3263 10:55:50.629874 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3264 10:55:50.633446 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3265 10:55:50.636313 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3266 10:55:50.643108 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3267 10:55:50.646684 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3268 10:55:50.649792 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3269 10:55:50.652970 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3270 10:55:50.656470 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3271 10:55:50.663295 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3272 10:55:50.666608 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3273 10:55:50.669354 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3274 10:55:50.672966 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3275 10:55:50.676543 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3276 10:55:50.682933 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3277 10:55:50.686551 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3278 10:55:50.687082 ==
3279 10:55:50.689358 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 10:55:50.692655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 10:55:50.693089 ==
3282 10:55:50.696215 DQS Delay:
3283 10:55:50.696750 DQS0 = 0, DQS1 = 0
3284 10:55:50.697126 DQM Delay:
3285 10:55:50.699579 DQM0 = 115, DQM1 = 106
3286 10:55:50.700052 DQ Delay:
3287 10:55:50.702572 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3288 10:55:50.706082 DQ4 =111, DQ5 =123, DQ6 =127, DQ7 =111
3289 10:55:50.709220 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3290 10:55:50.715931 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3291 10:55:50.716400
3292 10:55:50.716782
3293 10:55:50.717128 ==
3294 10:55:50.719664 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 10:55:50.722752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 10:55:50.723213 ==
3297 10:55:50.723548
3298 10:55:50.723860
3299 10:55:50.725760 TX Vref Scan disable
3300 10:55:50.726184 == TX Byte 0 ==
3301 10:55:50.732563 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3302 10:55:50.735588 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3303 10:55:50.736060 == TX Byte 1 ==
3304 10:55:50.742799 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3305 10:55:50.745911 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3306 10:55:50.746479 ==
3307 10:55:50.749580 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 10:55:50.752337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 10:55:50.752814 ==
3310 10:55:50.765893 TX Vref=22, minBit 1, minWin=24, winSum=403
3311 10:55:50.769048 TX Vref=24, minBit 1, minWin=24, winSum=409
3312 10:55:50.772791 TX Vref=26, minBit 1, minWin=24, winSum=417
3313 10:55:50.775625 TX Vref=28, minBit 1, minWin=25, winSum=421
3314 10:55:50.778774 TX Vref=30, minBit 1, minWin=25, winSum=421
3315 10:55:50.785485 TX Vref=32, minBit 3, minWin=24, winSum=416
3316 10:55:50.788797 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
3317 10:55:50.789273
3318 10:55:50.792108 Final TX Range 1 Vref 28
3319 10:55:50.792582
3320 10:55:50.793013 ==
3321 10:55:50.795430 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 10:55:50.798907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 10:55:50.799464 ==
3324 10:55:50.802387
3325 10:55:50.802910
3326 10:55:50.803449 TX Vref Scan disable
3327 10:55:50.805259 == TX Byte 0 ==
3328 10:55:50.808816 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3329 10:55:50.815530 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3330 10:55:50.816004 == TX Byte 1 ==
3331 10:55:50.818896 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3332 10:55:50.825477 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3333 10:55:50.825950
3334 10:55:50.826320 [DATLAT]
3335 10:55:50.826666 Freq=1200, CH1 RK0
3336 10:55:50.827048
3337 10:55:50.828413 DATLAT Default: 0xd
3338 10:55:50.828743 0, 0xFFFF, sum = 0
3339 10:55:50.831967 1, 0xFFFF, sum = 0
3340 10:55:50.835005 2, 0xFFFF, sum = 0
3341 10:55:50.835253 3, 0xFFFF, sum = 0
3342 10:55:50.838156 4, 0xFFFF, sum = 0
3343 10:55:50.838352 5, 0xFFFF, sum = 0
3344 10:55:50.841705 6, 0xFFFF, sum = 0
3345 10:55:50.841901 7, 0xFFFF, sum = 0
3346 10:55:50.844669 8, 0xFFFF, sum = 0
3347 10:55:50.844834 9, 0xFFFF, sum = 0
3348 10:55:50.848301 10, 0xFFFF, sum = 0
3349 10:55:50.848456 11, 0xFFFF, sum = 0
3350 10:55:50.851323 12, 0x0, sum = 1
3351 10:55:50.851468 13, 0x0, sum = 2
3352 10:55:50.854783 14, 0x0, sum = 3
3353 10:55:50.854949 15, 0x0, sum = 4
3354 10:55:50.857932 best_step = 13
3355 10:55:50.858077
3356 10:55:50.858186 ==
3357 10:55:50.861496 Dram Type= 6, Freq= 0, CH_1, rank 0
3358 10:55:50.864677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3359 10:55:50.864822 ==
3360 10:55:50.864929 RX Vref Scan: 1
3361 10:55:50.867789
3362 10:55:50.867961 Set Vref Range= 32 -> 127
3363 10:55:50.868070
3364 10:55:50.871458 RX Vref 32 -> 127, step: 1
3365 10:55:50.871677
3366 10:55:50.874540 RX Delay -21 -> 252, step: 4
3367 10:55:50.874715
3368 10:55:50.877711 Set Vref, RX VrefLevel [Byte0]: 32
3369 10:55:50.881249 [Byte1]: 32
3370 10:55:50.881383
3371 10:55:50.884611 Set Vref, RX VrefLevel [Byte0]: 33
3372 10:55:50.887863 [Byte1]: 33
3373 10:55:50.891980
3374 10:55:50.892112 Set Vref, RX VrefLevel [Byte0]: 34
3375 10:55:50.895155 [Byte1]: 34
3376 10:55:50.899435
3377 10:55:50.899584 Set Vref, RX VrefLevel [Byte0]: 35
3378 10:55:50.902685 [Byte1]: 35
3379 10:55:50.907536
3380 10:55:50.907707 Set Vref, RX VrefLevel [Byte0]: 36
3381 10:55:50.910993 [Byte1]: 36
3382 10:55:50.915860
3383 10:55:50.916272 Set Vref, RX VrefLevel [Byte0]: 37
3384 10:55:50.919034 [Byte1]: 37
3385 10:55:50.923676
3386 10:55:50.924088 Set Vref, RX VrefLevel [Byte0]: 38
3387 10:55:50.927232 [Byte1]: 38
3388 10:55:50.931443
3389 10:55:50.931853 Set Vref, RX VrefLevel [Byte0]: 39
3390 10:55:50.934683 [Byte1]: 39
3391 10:55:50.939415
3392 10:55:50.940027 Set Vref, RX VrefLevel [Byte0]: 40
3393 10:55:50.942589 [Byte1]: 40
3394 10:55:50.947497
3395 10:55:50.947908 Set Vref, RX VrefLevel [Byte0]: 41
3396 10:55:50.950482 [Byte1]: 41
3397 10:55:50.955394
3398 10:55:50.955809 Set Vref, RX VrefLevel [Byte0]: 42
3399 10:55:50.958192 [Byte1]: 42
3400 10:55:50.963351
3401 10:55:50.963762 Set Vref, RX VrefLevel [Byte0]: 43
3402 10:55:50.966505 [Byte1]: 43
3403 10:55:50.971287
3404 10:55:50.971701 Set Vref, RX VrefLevel [Byte0]: 44
3405 10:55:50.974418 [Byte1]: 44
3406 10:55:50.979248
3407 10:55:50.979807 Set Vref, RX VrefLevel [Byte0]: 45
3408 10:55:50.982337 [Byte1]: 45
3409 10:55:50.987388
3410 10:55:50.987949 Set Vref, RX VrefLevel [Byte0]: 46
3411 10:55:50.990127 [Byte1]: 46
3412 10:55:50.995113
3413 10:55:50.995571 Set Vref, RX VrefLevel [Byte0]: 47
3414 10:55:50.998119 [Byte1]: 47
3415 10:55:51.003332
3416 10:55:51.003891 Set Vref, RX VrefLevel [Byte0]: 48
3417 10:55:51.006408 [Byte1]: 48
3418 10:55:51.011032
3419 10:55:51.011610 Set Vref, RX VrefLevel [Byte0]: 49
3420 10:55:51.013975 [Byte1]: 49
3421 10:55:51.018550
3422 10:55:51.019149 Set Vref, RX VrefLevel [Byte0]: 50
3423 10:55:51.022143 [Byte1]: 50
3424 10:55:51.026653
3425 10:55:51.027271 Set Vref, RX VrefLevel [Byte0]: 51
3426 10:55:51.030256 [Byte1]: 51
3427 10:55:51.034521
3428 10:55:51.035173 Set Vref, RX VrefLevel [Byte0]: 52
3429 10:55:51.037407 [Byte1]: 52
3430 10:55:51.042486
3431 10:55:51.043103 Set Vref, RX VrefLevel [Byte0]: 53
3432 10:55:51.046340 [Byte1]: 53
3433 10:55:51.050483
3434 10:55:51.051099 Set Vref, RX VrefLevel [Byte0]: 54
3435 10:55:51.053385 [Byte1]: 54
3436 10:55:51.058301
3437 10:55:51.058760 Set Vref, RX VrefLevel [Byte0]: 55
3438 10:55:51.061338 [Byte1]: 55
3439 10:55:51.066400
3440 10:55:51.067001 Set Vref, RX VrefLevel [Byte0]: 56
3441 10:55:51.069372 [Byte1]: 56
3442 10:55:51.074430
3443 10:55:51.075050 Set Vref, RX VrefLevel [Byte0]: 57
3444 10:55:51.077197 [Byte1]: 57
3445 10:55:51.082467
3446 10:55:51.083061 Set Vref, RX VrefLevel [Byte0]: 58
3447 10:55:51.085665 [Byte1]: 58
3448 10:55:51.089981
3449 10:55:51.090543 Set Vref, RX VrefLevel [Byte0]: 59
3450 10:55:51.093553 [Byte1]: 59
3451 10:55:51.097657
3452 10:55:51.098124 Set Vref, RX VrefLevel [Byte0]: 60
3453 10:55:51.100895 [Byte1]: 60
3454 10:55:51.105815
3455 10:55:51.106386 Set Vref, RX VrefLevel [Byte0]: 61
3456 10:55:51.109314 [Byte1]: 61
3457 10:55:51.113629
3458 10:55:51.114182 Set Vref, RX VrefLevel [Byte0]: 62
3459 10:55:51.117011 [Byte1]: 62
3460 10:55:51.121645
3461 10:55:51.122195 Set Vref, RX VrefLevel [Byte0]: 63
3462 10:55:51.125167 [Byte1]: 63
3463 10:55:51.129739
3464 10:55:51.130289 Set Vref, RX VrefLevel [Byte0]: 64
3465 10:55:51.133068 [Byte1]: 64
3466 10:55:51.137194
3467 10:55:51.137654 Set Vref, RX VrefLevel [Byte0]: 65
3468 10:55:51.140760 [Byte1]: 65
3469 10:55:51.145296
3470 10:55:51.145752 Set Vref, RX VrefLevel [Byte0]: 66
3471 10:55:51.148918 [Byte1]: 66
3472 10:55:51.153432
3473 10:55:51.153988 Final RX Vref Byte 0 = 58 to rank0
3474 10:55:51.157118 Final RX Vref Byte 1 = 48 to rank0
3475 10:55:51.159743 Final RX Vref Byte 0 = 58 to rank1
3476 10:55:51.163466 Final RX Vref Byte 1 = 48 to rank1==
3477 10:55:51.166896 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 10:55:51.173481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 10:55:51.174035 ==
3480 10:55:51.174393 DQS Delay:
3481 10:55:51.176829 DQS0 = 0, DQS1 = 0
3482 10:55:51.177389 DQM Delay:
3483 10:55:51.177754 DQM0 = 115, DQM1 = 105
3484 10:55:51.180130 DQ Delay:
3485 10:55:51.183100 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3486 10:55:51.186253 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3487 10:55:51.190107 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =100
3488 10:55:51.193189 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3489 10:55:51.193828
3490 10:55:51.194399
3491 10:55:51.203182 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3492 10:55:51.203741 CH1 RK0: MR19=303, MR18=F0F7
3493 10:55:51.209695 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3494 10:55:51.210268
3495 10:55:51.213377 ----->DramcWriteLeveling(PI) begin...
3496 10:55:51.213957 ==
3497 10:55:51.216195 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 10:55:51.222794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 10:55:51.223396 ==
3500 10:55:51.225719 Write leveling (Byte 0): 23 => 23
3501 10:55:51.229550 Write leveling (Byte 1): 26 => 26
3502 10:55:51.230018 DramcWriteLeveling(PI) end<-----
3503 10:55:51.230456
3504 10:55:51.232513 ==
3505 10:55:51.235895 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 10:55:51.239292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 10:55:51.239759 ==
3508 10:55:51.242669 [Gating] SW mode calibration
3509 10:55:51.249134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 10:55:51.252562 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 10:55:51.259151 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3512 10:55:51.262282 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 10:55:51.265863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 10:55:51.272136 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 10:55:51.275534 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 10:55:51.278612 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 10:55:51.285196 0 15 24 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
3518 10:55:51.288900 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
3519 10:55:51.292027 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 10:55:51.298347 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 10:55:51.301345 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 10:55:51.305189 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 10:55:51.311865 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 10:55:51.315044 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3525 10:55:51.318017 1 0 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
3526 10:55:51.325054 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3527 10:55:51.328193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 10:55:51.331358 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 10:55:51.342042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 10:55:51.342342 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 10:55:51.345087 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 10:55:51.351268 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 10:55:51.355074 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3534 10:55:51.357985 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:55:51.415037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 10:55:51.415748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 10:55:51.416428 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 10:55:51.416955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 10:55:51.417377 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 10:55:51.418032 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 10:55:51.418651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 10:55:51.419285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 10:55:51.419942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 10:55:51.420597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 10:55:51.421245 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 10:55:51.421884 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 10:55:51.422929 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 10:55:51.423619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 10:55:51.424374 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 10:55:51.430707 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3551 10:55:51.431514 Total UI for P1: 0, mck2ui 16
3552 10:55:51.437698 best dqsien dly found for B0: ( 1, 3, 24)
3553 10:55:51.445523 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 10:55:51.445990 Total UI for P1: 0, mck2ui 16
3555 10:55:51.447389 best dqsien dly found for B1: ( 1, 3, 26)
3556 10:55:51.450226 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3557 10:55:51.453599 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3558 10:55:51.453917
3559 10:55:51.457082 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 10:55:51.460359 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 10:55:51.463587 [Gating] SW calibration Done
3562 10:55:51.463916 ==
3563 10:55:51.466906 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 10:55:51.469910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 10:55:51.473440 ==
3566 10:55:51.473951 RX Vref Scan: 0
3567 10:55:51.474306
3568 10:55:51.476877 RX Vref 0 -> 0, step: 1
3569 10:55:51.477137
3570 10:55:51.480611 RX Delay -40 -> 252, step: 8
3571 10:55:51.483440 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3572 10:55:51.486469 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3573 10:55:51.489668 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3574 10:55:51.493074 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3575 10:55:51.499925 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3576 10:55:51.502991 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3577 10:55:51.506265 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3578 10:55:51.509363 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3579 10:55:51.513174 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3580 10:55:51.519673 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3581 10:55:51.523389 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3582 10:55:51.526111 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3583 10:55:51.529619 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3584 10:55:51.532990 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3585 10:55:51.539334 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3586 10:55:51.543128 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3587 10:55:51.543540 ==
3588 10:55:51.546497 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 10:55:51.549736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 10:55:51.550249 ==
3591 10:55:51.552538 DQS Delay:
3592 10:55:51.552949 DQS0 = 0, DQS1 = 0
3593 10:55:51.556037 DQM Delay:
3594 10:55:51.556447 DQM0 = 112, DQM1 = 108
3595 10:55:51.556774 DQ Delay:
3596 10:55:51.559540 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =107
3597 10:55:51.565674 DQ4 =107, DQ5 =123, DQ6 =123, DQ7 =111
3598 10:55:51.569275 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3599 10:55:51.572451 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3600 10:55:51.572902
3601 10:55:51.573231
3602 10:55:51.573569 ==
3603 10:55:51.575361 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 10:55:51.578931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 10:55:51.579365 ==
3606 10:55:51.579688
3607 10:55:51.580036
3608 10:55:51.581657 TX Vref Scan disable
3609 10:55:51.585408 == TX Byte 0 ==
3610 10:55:51.588754 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3611 10:55:51.592065 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3612 10:55:51.594797 == TX Byte 1 ==
3613 10:55:51.598390 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3614 10:55:51.601740 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3615 10:55:51.602159 ==
3616 10:55:51.605280 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 10:55:51.611427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 10:55:51.611856 ==
3619 10:55:51.622050 TX Vref=22, minBit 0, minWin=24, winSum=409
3620 10:55:51.625460 TX Vref=24, minBit 0, minWin=25, winSum=416
3621 10:55:51.628551 TX Vref=26, minBit 0, minWin=25, winSum=424
3622 10:55:51.631564 TX Vref=28, minBit 1, minWin=25, winSum=422
3623 10:55:51.635166 TX Vref=30, minBit 1, minWin=25, winSum=424
3624 10:55:51.641693 TX Vref=32, minBit 1, minWin=25, winSum=420
3625 10:55:51.644681 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
3626 10:55:51.644865
3627 10:55:51.647742 Final TX Range 1 Vref 26
3628 10:55:51.647876
3629 10:55:51.647977 ==
3630 10:55:51.650978 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 10:55:51.654536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 10:55:51.657779 ==
3633 10:55:51.657893
3634 10:55:51.657973
3635 10:55:51.658045 TX Vref Scan disable
3636 10:55:51.661402 == TX Byte 0 ==
3637 10:55:51.664658 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3638 10:55:51.671146 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3639 10:55:51.671298 == TX Byte 1 ==
3640 10:55:51.674324 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3641 10:55:51.680549 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3642 10:55:51.680694
3643 10:55:51.680762 [DATLAT]
3644 10:55:51.680822 Freq=1200, CH1 RK1
3645 10:55:51.684072
3646 10:55:51.684188 DATLAT Default: 0xd
3647 10:55:51.687408 0, 0xFFFF, sum = 0
3648 10:55:51.687541 1, 0xFFFF, sum = 0
3649 10:55:51.690782 2, 0xFFFF, sum = 0
3650 10:55:51.690899 3, 0xFFFF, sum = 0
3651 10:55:51.693800 4, 0xFFFF, sum = 0
3652 10:55:51.693885 5, 0xFFFF, sum = 0
3653 10:55:51.697374 6, 0xFFFF, sum = 0
3654 10:55:51.697457 7, 0xFFFF, sum = 0
3655 10:55:51.700708 8, 0xFFFF, sum = 0
3656 10:55:51.700792 9, 0xFFFF, sum = 0
3657 10:55:51.704534 10, 0xFFFF, sum = 0
3658 10:55:51.704708 11, 0xFFFF, sum = 0
3659 10:55:51.706882 12, 0x0, sum = 1
3660 10:55:51.707018 13, 0x0, sum = 2
3661 10:55:51.710251 14, 0x0, sum = 3
3662 10:55:51.710416 15, 0x0, sum = 4
3663 10:55:51.713909 best_step = 13
3664 10:55:51.714072
3665 10:55:51.714144 ==
3666 10:55:51.716992 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 10:55:51.720747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 10:55:51.720921 ==
3669 10:55:51.723806 RX Vref Scan: 0
3670 10:55:51.723980
3671 10:55:51.724061 RX Vref 0 -> 0, step: 1
3672 10:55:51.724131
3673 10:55:51.726650 RX Delay -21 -> 252, step: 4
3674 10:55:51.733520 iDelay=195, Bit 0, Center 116 (43 ~ 190) 148
3675 10:55:51.737325 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3676 10:55:51.740282 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3677 10:55:51.743306 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3678 10:55:51.750043 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3679 10:55:51.753559 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3680 10:55:51.756702 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3681 10:55:51.760277 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3682 10:55:51.763458 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3683 10:55:51.770608 iDelay=195, Bit 9, Center 106 (43 ~ 170) 128
3684 10:55:51.773221 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3685 10:55:51.776841 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3686 10:55:51.779676 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3687 10:55:51.783264 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3688 10:55:51.789514 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3689 10:55:51.793043 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3690 10:55:51.793724 ==
3691 10:55:51.796456 Dram Type= 6, Freq= 0, CH_1, rank 1
3692 10:55:51.799783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3693 10:55:51.800343 ==
3694 10:55:51.802672 DQS Delay:
3695 10:55:51.803227 DQS0 = 0, DQS1 = 0
3696 10:55:51.806049 DQM Delay:
3697 10:55:51.806458 DQM0 = 112, DQM1 = 112
3698 10:55:51.806777 DQ Delay:
3699 10:55:51.812686 DQ0 =116, DQ1 =108, DQ2 =102, DQ3 =110
3700 10:55:51.815987 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3701 10:55:51.819052 DQ8 =98, DQ9 =106, DQ10 =114, DQ11 =106
3702 10:55:51.822311 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3703 10:55:51.822723
3704 10:55:51.823100
3705 10:55:51.829171 [DQSOSCAuto] RK1, (LSB)MR18= 0xf606, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3706 10:55:51.832078 CH1 RK1: MR19=304, MR18=F606
3707 10:55:51.838684 CH1_RK1: MR19=0x304, MR18=0xF606, DQSOSC=407, MR23=63, INC=39, DEC=26
3708 10:55:51.842334 [RxdqsGatingPostProcess] freq 1200
3709 10:55:51.848957 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3710 10:55:51.849198 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 10:55:51.851860 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 10:55:51.855407 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 10:55:51.859101 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 10:55:51.862320 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 10:55:51.865327 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 10:55:51.868457 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 10:55:51.872138 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 10:55:51.875391 Pre-setting of DQS Precalculation
3719 10:55:51.881958 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3720 10:55:51.888691 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3721 10:55:51.895140 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3722 10:55:51.895393
3723 10:55:51.895585
3724 10:55:51.897967 [Calibration Summary] 2400 Mbps
3725 10:55:51.898125 CH 0, Rank 0
3726 10:55:51.901705 SW Impedance : PASS
3727 10:55:51.905049 DUTY Scan : NO K
3728 10:55:51.905222 ZQ Calibration : PASS
3729 10:55:51.907935 Jitter Meter : NO K
3730 10:55:51.911339 CBT Training : PASS
3731 10:55:51.911556 Write leveling : PASS
3732 10:55:51.914734 RX DQS gating : PASS
3733 10:55:51.918264 RX DQ/DQS(RDDQC) : PASS
3734 10:55:51.918433 TX DQ/DQS : PASS
3735 10:55:51.921339 RX DATLAT : PASS
3736 10:55:51.924855 RX DQ/DQS(Engine): PASS
3737 10:55:51.925052 TX OE : NO K
3738 10:55:51.925187 All Pass.
3739 10:55:51.927944
3740 10:55:51.928159 CH 0, Rank 1
3741 10:55:51.931294 SW Impedance : PASS
3742 10:55:51.931519 DUTY Scan : NO K
3743 10:55:51.934646 ZQ Calibration : PASS
3744 10:55:51.937537 Jitter Meter : NO K
3745 10:55:51.937775 CBT Training : PASS
3746 10:55:51.941266 Write leveling : PASS
3747 10:55:51.941429 RX DQS gating : PASS
3748 10:55:51.944505 RX DQ/DQS(RDDQC) : PASS
3749 10:55:51.947668 TX DQ/DQS : PASS
3750 10:55:51.947833 RX DATLAT : PASS
3751 10:55:51.951003 RX DQ/DQS(Engine): PASS
3752 10:55:51.954548 TX OE : NO K
3753 10:55:51.955156 All Pass.
3754 10:55:51.955632
3755 10:55:51.956082 CH 1, Rank 0
3756 10:55:51.957921 SW Impedance : PASS
3757 10:55:51.961212 DUTY Scan : NO K
3758 10:55:51.961712 ZQ Calibration : PASS
3759 10:55:51.964444 Jitter Meter : NO K
3760 10:55:51.967663 CBT Training : PASS
3761 10:55:51.968072 Write leveling : PASS
3762 10:55:51.970774 RX DQS gating : PASS
3763 10:55:51.974535 RX DQ/DQS(RDDQC) : PASS
3764 10:55:51.975059 TX DQ/DQS : PASS
3765 10:55:51.977502 RX DATLAT : PASS
3766 10:55:51.980641 RX DQ/DQS(Engine): PASS
3767 10:55:51.981179 TX OE : NO K
3768 10:55:51.984512 All Pass.
3769 10:55:51.984934
3770 10:55:51.985260 CH 1, Rank 1
3771 10:55:51.987478 SW Impedance : PASS
3772 10:55:51.987898 DUTY Scan : NO K
3773 10:55:51.990429 ZQ Calibration : PASS
3774 10:55:51.994360 Jitter Meter : NO K
3775 10:55:51.994778 CBT Training : PASS
3776 10:55:51.997540 Write leveling : PASS
3777 10:55:52.000405 RX DQS gating : PASS
3778 10:55:52.000709 RX DQ/DQS(RDDQC) : PASS
3779 10:55:52.004127 TX DQ/DQS : PASS
3780 10:55:52.007414 RX DATLAT : PASS
3781 10:55:52.007715 RX DQ/DQS(Engine): PASS
3782 10:55:52.010750 TX OE : NO K
3783 10:55:52.011097 All Pass.
3784 10:55:52.011337
3785 10:55:52.013878 DramC Write-DBI off
3786 10:55:52.017445 PER_BANK_REFRESH: Hybrid Mode
3787 10:55:52.017750 TX_TRACKING: ON
3788 10:55:52.027355 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3789 10:55:52.030873 [FAST_K] Save calibration result to emmc
3790 10:55:52.034160 dramc_set_vcore_voltage set vcore to 650000
3791 10:55:52.037012 Read voltage for 600, 5
3792 10:55:52.037508 Vio18 = 0
3793 10:55:52.037872 Vcore = 650000
3794 10:55:52.040970 Vdram = 0
3795 10:55:52.041531 Vddq = 0
3796 10:55:52.041898 Vmddr = 0
3797 10:55:52.046870 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3798 10:55:52.050143 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3799 10:55:52.053516 MEM_TYPE=3, freq_sel=19
3800 10:55:52.056645 sv_algorithm_assistance_LP4_1600
3801 10:55:52.059937 ============ PULL DRAM RESETB DOWN ============
3802 10:55:52.063668 ========== PULL DRAM RESETB DOWN end =========
3803 10:55:52.070383 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3804 10:55:52.073017 ===================================
3805 10:55:52.076152 LPDDR4 DRAM CONFIGURATION
3806 10:55:52.080258 ===================================
3807 10:55:52.080826 EX_ROW_EN[0] = 0x0
3808 10:55:52.083088 EX_ROW_EN[1] = 0x0
3809 10:55:52.083571 LP4Y_EN = 0x0
3810 10:55:52.086696 WORK_FSP = 0x0
3811 10:55:52.087340 WL = 0x2
3812 10:55:52.089655 RL = 0x2
3813 10:55:52.090224 BL = 0x2
3814 10:55:52.093006 RPST = 0x0
3815 10:55:52.093491 RD_PRE = 0x0
3816 10:55:52.096226 WR_PRE = 0x1
3817 10:55:52.099488 WR_PST = 0x0
3818 10:55:52.100051 DBI_WR = 0x0
3819 10:55:52.102533 DBI_RD = 0x0
3820 10:55:52.103170 OTF = 0x1
3821 10:55:52.106511 ===================================
3822 10:55:52.109104 ===================================
3823 10:55:52.112873 ANA top config
3824 10:55:52.115819 ===================================
3825 10:55:52.116441 DLL_ASYNC_EN = 0
3826 10:55:52.119009 ALL_SLAVE_EN = 1
3827 10:55:52.122391 NEW_RANK_MODE = 1
3828 10:55:52.125856 DLL_IDLE_MODE = 1
3829 10:55:52.126330 LP45_APHY_COMB_EN = 1
3830 10:55:52.128810 TX_ODT_DIS = 1
3831 10:55:52.132711 NEW_8X_MODE = 1
3832 10:55:52.135797 ===================================
3833 10:55:52.138542 ===================================
3834 10:55:52.142321 data_rate = 1200
3835 10:55:52.145663 CKR = 1
3836 10:55:52.148774 DQ_P2S_RATIO = 8
3837 10:55:52.151786 ===================================
3838 10:55:52.152247 CA_P2S_RATIO = 8
3839 10:55:52.155612 DQ_CA_OPEN = 0
3840 10:55:52.159024 DQ_SEMI_OPEN = 0
3841 10:55:52.162021 CA_SEMI_OPEN = 0
3842 10:55:52.164933 CA_FULL_RATE = 0
3843 10:55:52.168387 DQ_CKDIV4_EN = 1
3844 10:55:52.169005 CA_CKDIV4_EN = 1
3845 10:55:52.171939 CA_PREDIV_EN = 0
3846 10:55:52.174758 PH8_DLY = 0
3847 10:55:52.178303 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3848 10:55:52.182015 DQ_AAMCK_DIV = 4
3849 10:55:52.185134 CA_AAMCK_DIV = 4
3850 10:55:52.185701 CA_ADMCK_DIV = 4
3851 10:55:52.188679 DQ_TRACK_CA_EN = 0
3852 10:55:52.191575 CA_PICK = 600
3853 10:55:52.194482 CA_MCKIO = 600
3854 10:55:52.198355 MCKIO_SEMI = 0
3855 10:55:52.201374 PLL_FREQ = 2288
3856 10:55:52.205074 DQ_UI_PI_RATIO = 32
3857 10:55:52.207984 CA_UI_PI_RATIO = 0
3858 10:55:52.211454 ===================================
3859 10:55:52.214978 ===================================
3860 10:55:52.215543 memory_type:LPDDR4
3861 10:55:52.218032 GP_NUM : 10
3862 10:55:52.221005 SRAM_EN : 1
3863 10:55:52.221562 MD32_EN : 0
3864 10:55:52.224342 ===================================
3865 10:55:52.227794 [ANA_INIT] >>>>>>>>>>>>>>
3866 10:55:52.231189 <<<<<< [CONFIGURE PHASE]: ANA_TX
3867 10:55:52.233898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3868 10:55:52.237254 ===================================
3869 10:55:52.241054 data_rate = 1200,PCW = 0X5800
3870 10:55:52.244181 ===================================
3871 10:55:52.247515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3872 10:55:52.250446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 10:55:52.257377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 10:55:52.260390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3875 10:55:52.264169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3876 10:55:52.267541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3877 10:55:52.270628 [ANA_INIT] flow start
3878 10:55:52.273758 [ANA_INIT] PLL >>>>>>>>
3879 10:55:52.274316 [ANA_INIT] PLL <<<<<<<<
3880 10:55:52.276996 [ANA_INIT] MIDPI >>>>>>>>
3881 10:55:52.280484 [ANA_INIT] MIDPI <<<<<<<<
3882 10:55:52.283474 [ANA_INIT] DLL >>>>>>>>
3883 10:55:52.284051 [ANA_INIT] flow end
3884 10:55:52.287065 ============ LP4 DIFF to SE enter ============
3885 10:55:52.293605 ============ LP4 DIFF to SE exit ============
3886 10:55:52.294208 [ANA_INIT] <<<<<<<<<<<<<
3887 10:55:52.296675 [Flow] Enable top DCM control >>>>>
3888 10:55:52.300259 [Flow] Enable top DCM control <<<<<
3889 10:55:52.303522 Enable DLL master slave shuffle
3890 10:55:52.309842 ==============================================================
3891 10:55:52.313477 Gating Mode config
3892 10:55:52.316357 ==============================================================
3893 10:55:52.319785 Config description:
3894 10:55:52.329770 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3895 10:55:52.336435 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3896 10:55:52.340514 SELPH_MODE 0: By rank 1: By Phase
3897 10:55:52.346020 ==============================================================
3898 10:55:52.349545 GAT_TRACK_EN = 1
3899 10:55:52.352890 RX_GATING_MODE = 2
3900 10:55:52.356387 RX_GATING_TRACK_MODE = 2
3901 10:55:52.359432 SELPH_MODE = 1
3902 10:55:52.359914 PICG_EARLY_EN = 1
3903 10:55:52.362950 VALID_LAT_VALUE = 1
3904 10:55:52.369126 ==============================================================
3905 10:55:52.372858 Enter into Gating configuration >>>>
3906 10:55:52.376025 Exit from Gating configuration <<<<
3907 10:55:52.378938 Enter into DVFS_PRE_config >>>>>
3908 10:55:52.388724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3909 10:55:52.392356 Exit from DVFS_PRE_config <<<<<
3910 10:55:52.395324 Enter into PICG configuration >>>>
3911 10:55:52.398814 Exit from PICG configuration <<<<
3912 10:55:52.401917 [RX_INPUT] configuration >>>>>
3913 10:55:52.404777 [RX_INPUT] configuration <<<<<
3914 10:55:52.408638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3915 10:55:52.414864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3916 10:55:52.421890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 10:55:52.427976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 10:55:52.434684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 10:55:52.441868 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 10:55:52.444656 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3921 10:55:52.448228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3922 10:55:52.451419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3923 10:55:52.457856 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3924 10:55:52.461281 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3925 10:55:52.464357 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 10:55:52.467907 ===================================
3927 10:55:52.471436 LPDDR4 DRAM CONFIGURATION
3928 10:55:52.474565 ===================================
3929 10:55:52.475122 EX_ROW_EN[0] = 0x0
3930 10:55:52.477993 EX_ROW_EN[1] = 0x0
3931 10:55:52.481256 LP4Y_EN = 0x0
3932 10:55:52.481807 WORK_FSP = 0x0
3933 10:55:52.484465 WL = 0x2
3934 10:55:52.485015 RL = 0x2
3935 10:55:52.488144 BL = 0x2
3936 10:55:52.488693 RPST = 0x0
3937 10:55:52.491168 RD_PRE = 0x0
3938 10:55:52.491740 WR_PRE = 0x1
3939 10:55:52.494534 WR_PST = 0x0
3940 10:55:52.495146 DBI_WR = 0x0
3941 10:55:52.497821 DBI_RD = 0x0
3942 10:55:52.498373 OTF = 0x1
3943 10:55:52.500607 ===================================
3944 10:55:52.507690 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3945 10:55:52.510457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3946 10:55:52.514258 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 10:55:52.517677 ===================================
3948 10:55:52.520586 LPDDR4 DRAM CONFIGURATION
3949 10:55:52.524534 ===================================
3950 10:55:52.527375 EX_ROW_EN[0] = 0x10
3951 10:55:52.527839 EX_ROW_EN[1] = 0x0
3952 10:55:52.530584 LP4Y_EN = 0x0
3953 10:55:52.531169 WORK_FSP = 0x0
3954 10:55:52.534281 WL = 0x2
3955 10:55:52.534873 RL = 0x2
3956 10:55:52.537325 BL = 0x2
3957 10:55:52.538039 RPST = 0x0
3958 10:55:52.540049 RD_PRE = 0x0
3959 10:55:52.540511 WR_PRE = 0x1
3960 10:55:52.543949 WR_PST = 0x0
3961 10:55:52.544503 DBI_WR = 0x0
3962 10:55:52.546870 DBI_RD = 0x0
3963 10:55:52.547338 OTF = 0x1
3964 10:55:52.550150 ===================================
3965 10:55:52.557082 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3966 10:55:52.561467 nWR fixed to 30
3967 10:55:52.565027 [ModeRegInit_LP4] CH0 RK0
3968 10:55:52.565513 [ModeRegInit_LP4] CH0 RK1
3969 10:55:52.568391 [ModeRegInit_LP4] CH1 RK0
3970 10:55:52.571864 [ModeRegInit_LP4] CH1 RK1
3971 10:55:52.572329 match AC timing 17
3972 10:55:52.578399 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3973 10:55:52.582027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 10:55:52.584804 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3975 10:55:52.591685 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3976 10:55:52.594701 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3977 10:55:52.595214 ==
3978 10:55:52.598404 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 10:55:52.601111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 10:55:52.601569 ==
3981 10:55:52.608104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 10:55:52.614417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 10:55:52.617902 [CA 0] Center 37 (7~67) winsize 61
3984 10:55:52.621182 [CA 1] Center 37 (7~67) winsize 61
3985 10:55:52.624147 [CA 2] Center 35 (5~65) winsize 61
3986 10:55:52.627369 [CA 3] Center 35 (5~65) winsize 61
3987 10:55:52.631555 [CA 4] Center 34 (4~65) winsize 62
3988 10:55:52.634391 [CA 5] Center 34 (4~64) winsize 61
3989 10:55:52.634988
3990 10:55:52.637359 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 10:55:52.637838
3992 10:55:52.641060 [CATrainingPosCal] consider 1 rank data
3993 10:55:52.644078 u2DelayCellTimex100 = 270/100 ps
3994 10:55:52.647255 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3995 10:55:52.650872 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 10:56:04.360975 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 10:56:04.361203 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 10:56:04.361272 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3999 10:56:04.361331 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4000 10:56:04.361388
4001 10:56:04.361443 CA PerBit enable=1, Macro0, CA PI delay=34
4002 10:56:04.361497
4003 10:56:04.361550 [CBTSetCACLKResult] CA Dly = 34
4004 10:56:04.361603 CS Dly: 6 (0~37)
4005 10:56:04.361655 ==
4006 10:56:04.361708 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 10:56:04.361759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 10:56:04.361812 ==
4009 10:56:04.361864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 10:56:04.361916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4011 10:56:04.361968 [CA 0] Center 37 (7~67) winsize 61
4012 10:56:04.362019 [CA 1] Center 37 (7~67) winsize 61
4013 10:56:04.362070 [CA 2] Center 35 (5~65) winsize 61
4014 10:56:04.362121 [CA 3] Center 35 (5~65) winsize 61
4015 10:56:04.362172 [CA 4] Center 34 (4~65) winsize 62
4016 10:56:04.362223 [CA 5] Center 33 (3~64) winsize 62
4017 10:56:04.362273
4018 10:56:04.362324 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4019 10:56:04.362375
4020 10:56:04.362425 [CATrainingPosCal] consider 2 rank data
4021 10:56:04.362477 u2DelayCellTimex100 = 270/100 ps
4022 10:56:04.362528 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4023 10:56:04.362579 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4024 10:56:04.362630 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 10:56:04.362698 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 10:56:04.362778 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4027 10:56:04.362892 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4028 10:56:04.362946
4029 10:56:04.362997 CA PerBit enable=1, Macro0, CA PI delay=34
4030 10:56:04.363049
4031 10:56:04.363100 [CBTSetCACLKResult] CA Dly = 34
4032 10:56:04.363198 CS Dly: 5 (0~36)
4033 10:56:04.363252
4034 10:56:04.363303 ----->DramcWriteLeveling(PI) begin...
4035 10:56:04.363356 ==
4036 10:56:04.363407 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 10:56:04.363459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 10:56:04.363510 ==
4039 10:56:04.363562 Write leveling (Byte 0): 34 => 34
4040 10:56:04.363613 Write leveling (Byte 1): 31 => 31
4041 10:56:04.363663 DramcWriteLeveling(PI) end<-----
4042 10:56:04.363714
4043 10:56:04.363765 ==
4044 10:56:04.363816 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 10:56:04.363867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 10:56:04.363935 ==
4047 10:56:04.364000 [Gating] SW mode calibration
4048 10:56:04.364051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4049 10:56:04.364103 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4050 10:56:04.364155 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 10:56:04.364206 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 10:56:04.364258 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 10:56:04.364309 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
4054 10:56:04.364360 0 9 16 | B1->B0 | 3333 2828 | 1 0 | (0 1) (0 1)
4055 10:56:04.364411 0 9 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4056 10:56:04.364462 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 10:56:04.364512 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 10:56:04.364563 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 10:56:04.364614 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 10:56:04.364665 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 10:56:04.364716 0 10 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4062 10:56:04.364767 0 10 16 | B1->B0 | 3131 4040 | 1 0 | (0 0) (1 1)
4063 10:56:04.364818 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 10:56:04.364869 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 10:56:04.364920 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 10:56:04.364971 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 10:56:04.365021 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 10:56:04.365072 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 10:56:04.365179 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4070 10:56:04.365260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4071 10:56:04.365314 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:56:04.365366 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 10:56:04.365418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 10:56:04.365469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 10:56:04.365520 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 10:56:04.365571 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 10:56:04.365622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 10:56:04.365673 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 10:56:04.365723 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 10:56:04.365774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 10:56:04.365825 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 10:56:04.365875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 10:56:04.365926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 10:56:04.365981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 10:56:04.366032 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4086 10:56:04.366083 Total UI for P1: 0, mck2ui 16
4087 10:56:04.366135 best dqsien dly found for B0: ( 0, 13, 10)
4088 10:56:04.366187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4089 10:56:04.366237 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 10:56:04.366288 Total UI for P1: 0, mck2ui 16
4091 10:56:04.366339 best dqsien dly found for B1: ( 0, 13, 18)
4092 10:56:04.366390 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4093 10:56:04.366441 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4094 10:56:04.366492
4095 10:56:04.366543 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4096 10:56:04.366594 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4097 10:56:04.366644 [Gating] SW calibration Done
4098 10:56:04.366695 ==
4099 10:56:04.366746 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 10:56:04.366797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 10:56:04.366876 ==
4102 10:56:04.366942 RX Vref Scan: 0
4103 10:56:04.366993
4104 10:56:04.367248 RX Vref 0 -> 0, step: 1
4105 10:56:04.367361
4106 10:56:04.367479 RX Delay -230 -> 252, step: 16
4107 10:56:04.367581 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4108 10:56:04.367683 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4109 10:56:04.367805 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4110 10:56:04.367887 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4111 10:56:04.367968 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4112 10:56:04.368051 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4113 10:56:04.368106 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4114 10:56:04.368158 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4115 10:56:04.368210 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4116 10:56:04.368261 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4117 10:56:04.368312 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4118 10:56:04.368364 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4119 10:56:04.368415 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4120 10:56:04.368473 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4121 10:56:04.368525 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4122 10:56:04.368576 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4123 10:56:04.368628 ==
4124 10:56:04.368679 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 10:56:04.368731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 10:56:04.368782 ==
4127 10:56:04.368835 DQS Delay:
4128 10:56:04.368887 DQS0 = 0, DQS1 = 0
4129 10:56:04.368940 DQM Delay:
4130 10:56:04.368992 DQM0 = 37, DQM1 = 28
4131 10:56:04.369045 DQ Delay:
4132 10:56:04.369100 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4133 10:56:04.369187 DQ4 =33, DQ5 =25, DQ6 =57, DQ7 =49
4134 10:56:04.369264 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4135 10:56:04.369347 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4136 10:56:04.369403
4137 10:56:04.369456
4138 10:56:04.369516 ==
4139 10:56:04.369569 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 10:56:04.369623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 10:56:04.369676 ==
4142 10:56:04.369729
4143 10:56:04.369781
4144 10:56:04.369833 TX Vref Scan disable
4145 10:56:04.369892 == TX Byte 0 ==
4146 10:56:04.369946 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4147 10:56:04.370000 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4148 10:56:04.370053 == TX Byte 1 ==
4149 10:56:04.370106 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4150 10:56:04.370159 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4151 10:56:04.370212 ==
4152 10:56:04.370265 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 10:56:04.370318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 10:56:04.370371 ==
4155 10:56:04.370423
4156 10:56:04.370475
4157 10:56:04.370527 TX Vref Scan disable
4158 10:56:04.370580 == TX Byte 0 ==
4159 10:56:04.370633 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4160 10:56:04.370686 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4161 10:56:04.370739 == TX Byte 1 ==
4162 10:56:04.370791 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4163 10:56:04.370884 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4164 10:56:04.370939
4165 10:56:04.370991 [DATLAT]
4166 10:56:04.371043 Freq=600, CH0 RK0
4167 10:56:04.371096
4168 10:56:04.371148 DATLAT Default: 0x9
4169 10:56:04.371230 0, 0xFFFF, sum = 0
4170 10:56:04.371284 1, 0xFFFF, sum = 0
4171 10:56:04.371338 2, 0xFFFF, sum = 0
4172 10:56:04.371391 3, 0xFFFF, sum = 0
4173 10:56:04.371444 4, 0xFFFF, sum = 0
4174 10:56:04.371497 5, 0xFFFF, sum = 0
4175 10:56:04.371550 6, 0xFFFF, sum = 0
4176 10:56:04.371602 7, 0xFFFF, sum = 0
4177 10:56:04.371655 8, 0x0, sum = 1
4178 10:56:04.371709 9, 0x0, sum = 2
4179 10:56:04.371762 10, 0x0, sum = 3
4180 10:56:04.371814 11, 0x0, sum = 4
4181 10:56:04.371867 best_step = 9
4182 10:56:04.371919
4183 10:56:04.371971 ==
4184 10:56:04.372024 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 10:56:04.372103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 10:56:04.372185 ==
4187 10:56:04.372238 RX Vref Scan: 1
4188 10:56:04.372291
4189 10:56:04.372343 RX Vref 0 -> 0, step: 1
4190 10:56:04.372395
4191 10:56:04.372447 RX Delay -195 -> 252, step: 8
4192 10:56:04.372499
4193 10:56:04.372551 Set Vref, RX VrefLevel [Byte0]: 62
4194 10:56:04.372604 [Byte1]: 47
4195 10:56:04.372656
4196 10:56:04.372708 Final RX Vref Byte 0 = 62 to rank0
4197 10:56:04.372761 Final RX Vref Byte 1 = 47 to rank0
4198 10:56:04.372814 Final RX Vref Byte 0 = 62 to rank1
4199 10:56:04.372866 Final RX Vref Byte 1 = 47 to rank1==
4200 10:56:04.372918 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 10:56:04.372971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 10:56:04.373023 ==
4203 10:56:04.373076 DQS Delay:
4204 10:56:04.373128 DQS0 = 0, DQS1 = 0
4205 10:56:04.373192 DQM Delay:
4206 10:56:04.373245 DQM0 = 34, DQM1 = 29
4207 10:56:04.373297 DQ Delay:
4208 10:56:04.373350 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4209 10:56:04.373402 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4210 10:56:04.373454 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4211 10:56:04.373506 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4212 10:56:04.373558
4213 10:56:04.373610
4214 10:56:04.373662 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4215 10:56:04.373715 CH0 RK0: MR19=808, MR18=3E3D
4216 10:56:04.373767 CH0_RK0: MR19=0x808, MR18=0x3E3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4217 10:56:04.373820
4218 10:56:04.373873 ----->DramcWriteLeveling(PI) begin...
4219 10:56:04.373925 ==
4220 10:56:04.373981 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 10:56:04.374065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 10:56:04.374117 ==
4223 10:56:04.374169 Write leveling (Byte 0): 34 => 34
4224 10:56:04.374222 Write leveling (Byte 1): 31 => 31
4225 10:56:04.374278 DramcWriteLeveling(PI) end<-----
4226 10:56:04.374332
4227 10:56:04.374384 ==
4228 10:56:04.374436 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 10:56:04.374488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 10:56:04.374548 ==
4231 10:56:04.374602 [Gating] SW mode calibration
4232 10:56:04.374655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 10:56:04.374708 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4234 10:56:04.374760 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 10:56:04.374813 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 10:56:04.374909 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 10:56:04.374966 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4238 10:56:04.375019 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4239 10:56:04.375071 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 10:56:04.375123 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 10:56:04.375209 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 10:56:04.375266 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 10:56:04.375321 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 10:56:04.375559 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 10:56:04.375643 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4246 10:56:04.375745 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4247 10:56:04.375855 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 10:56:04.375940 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 10:56:04.376017 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 10:56:04.376073 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 10:56:04.376140 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 10:56:04.376193 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 10:56:04.376246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4254 10:56:04.376298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4255 10:56:04.376351 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:56:04.376403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 10:56:04.376456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 10:56:04.376508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 10:56:04.376560 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 10:56:04.376612 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 10:56:04.376665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 10:56:04.376717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 10:56:04.376770 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 10:56:04.376822 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 10:56:04.376874 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 10:56:04.376927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 10:56:04.376979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 10:56:04.377031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 10:56:04.377084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 10:56:04.377160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 10:56:04.377258 Total UI for P1: 0, mck2ui 16
4272 10:56:04.377358 best dqsien dly found for B0: ( 0, 13, 14)
4273 10:56:04.377456 Total UI for P1: 0, mck2ui 16
4274 10:56:04.377508 best dqsien dly found for B1: ( 0, 13, 14)
4275 10:56:04.377561 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4276 10:56:04.377613 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 10:56:04.377665
4278 10:56:04.377717 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 10:56:04.377770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 10:56:04.377822 [Gating] SW calibration Done
4281 10:56:04.377873 ==
4282 10:56:04.377926 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 10:56:04.377978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 10:56:04.378031 ==
4285 10:56:04.378083 RX Vref Scan: 0
4286 10:56:04.378135
4287 10:56:04.378186 RX Vref 0 -> 0, step: 1
4288 10:56:04.378238
4289 10:56:04.378290 RX Delay -230 -> 252, step: 16
4290 10:56:04.378345 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 10:56:04.378400 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4292 10:56:04.378452 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4293 10:56:04.378505 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 10:56:04.378557 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4295 10:56:04.378609 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4296 10:56:04.378660 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 10:56:04.378713 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 10:56:04.378764 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 10:56:04.378817 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4300 10:56:04.378917 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 10:56:04.378972 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4302 10:56:04.379025 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4303 10:56:04.379078 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 10:56:04.379129 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4305 10:56:04.379228 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4306 10:56:04.379282 ==
4307 10:56:04.379334 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 10:56:04.379386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 10:56:04.379439 ==
4310 10:56:04.379491 DQS Delay:
4311 10:56:04.379543 DQS0 = 0, DQS1 = 0
4312 10:56:04.379595 DQM Delay:
4313 10:56:04.379647 DQM0 = 39, DQM1 = 31
4314 10:56:04.379699 DQ Delay:
4315 10:56:04.379752 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4316 10:56:04.379804 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4317 10:56:04.379856 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4318 10:56:04.379908 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4319 10:56:04.379961
4320 10:56:04.380012
4321 10:56:04.380064 ==
4322 10:56:04.380116 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 10:56:04.380168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 10:56:04.380221 ==
4325 10:56:04.380272
4326 10:56:04.380340
4327 10:56:04.380406 TX Vref Scan disable
4328 10:56:04.380458 == TX Byte 0 ==
4329 10:56:04.380510 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4330 10:56:04.380562 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4331 10:56:04.380614 == TX Byte 1 ==
4332 10:56:04.380666 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 10:56:04.380719 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 10:56:04.380808 ==
4335 10:56:04.380890 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 10:56:04.380942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 10:56:04.380994 ==
4338 10:56:04.381046
4339 10:56:04.381098
4340 10:56:04.381166 TX Vref Scan disable
4341 10:56:04.381232 == TX Byte 0 ==
4342 10:56:04.381285 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4343 10:56:04.381337 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4344 10:56:04.381389 == TX Byte 1 ==
4345 10:56:04.381441 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4346 10:56:04.381494 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4347 10:56:04.381546
4348 10:56:04.381598 [DATLAT]
4349 10:56:04.381650 Freq=600, CH0 RK1
4350 10:56:04.381702
4351 10:56:04.381753 DATLAT Default: 0x9
4352 10:56:04.381805 0, 0xFFFF, sum = 0
4353 10:56:04.381858 1, 0xFFFF, sum = 0
4354 10:56:04.381911 2, 0xFFFF, sum = 0
4355 10:56:04.381964 3, 0xFFFF, sum = 0
4356 10:56:04.382016 4, 0xFFFF, sum = 0
4357 10:56:04.382069 5, 0xFFFF, sum = 0
4358 10:56:04.382121 6, 0xFFFF, sum = 0
4359 10:56:04.382173 7, 0xFFFF, sum = 0
4360 10:56:04.382225 8, 0x0, sum = 1
4361 10:56:04.382277 9, 0x0, sum = 2
4362 10:56:04.382328 10, 0x0, sum = 3
4363 10:56:04.382379 11, 0x0, sum = 4
4364 10:56:04.382430 best_step = 9
4365 10:56:04.382480
4366 10:56:04.382530 ==
4367 10:56:04.382580 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 10:56:04.382631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 10:56:04.382682 ==
4370 10:56:04.382732 RX Vref Scan: 0
4371 10:56:04.382782
4372 10:56:04.383036 RX Vref 0 -> 0, step: 1
4373 10:56:04.383093
4374 10:56:04.383206 RX Delay -195 -> 252, step: 8
4375 10:56:04.383285 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4376 10:56:04.383379 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4377 10:56:04.383434 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4378 10:56:04.383486 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4379 10:56:04.383567 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4380 10:56:04.383618 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4381 10:56:04.383669 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4382 10:56:04.383720 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4383 10:56:04.383771 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4384 10:56:04.383822 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4385 10:56:04.383872 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4386 10:56:04.383923 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4387 10:56:04.383973 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4388 10:56:04.384024 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 10:56:04.384075 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4390 10:56:04.384125 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4391 10:56:04.384176 ==
4392 10:56:04.384226 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 10:56:04.384277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 10:56:04.384328 ==
4395 10:56:04.384379 DQS Delay:
4396 10:56:04.384429 DQS0 = 0, DQS1 = 0
4397 10:56:04.384480 DQM Delay:
4398 10:56:04.384530 DQM0 = 33, DQM1 = 28
4399 10:56:04.384580 DQ Delay:
4400 10:56:04.384630 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4401 10:56:04.384682 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4402 10:56:04.384733 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =16
4403 10:56:04.384783 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4404 10:56:04.384833
4405 10:56:04.384883
4406 10:56:04.384933 [DQSOSCAuto] RK1, (LSB)MR18= 0x6533, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4407 10:56:04.384984 CH0 RK1: MR19=808, MR18=6533
4408 10:56:04.385035 CH0_RK1: MR19=0x808, MR18=0x6533, DQSOSC=390, MR23=63, INC=172, DEC=114
4409 10:56:04.385085 [RxdqsGatingPostProcess] freq 600
4410 10:56:04.385136 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 10:56:04.385193 Pre-setting of DQS Precalculation
4412 10:56:04.385244 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 10:56:04.385295 ==
4414 10:56:04.385346 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 10:56:04.385396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 10:56:04.385447 ==
4417 10:56:04.385497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 10:56:04.385548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4419 10:56:04.385599 [CA 0] Center 35 (5~66) winsize 62
4420 10:56:04.385649 [CA 1] Center 35 (5~66) winsize 62
4421 10:56:04.385700 [CA 2] Center 34 (4~65) winsize 62
4422 10:56:04.385750 [CA 3] Center 34 (4~65) winsize 62
4423 10:56:04.385801 [CA 4] Center 34 (4~65) winsize 62
4424 10:56:04.385851 [CA 5] Center 33 (3~64) winsize 62
4425 10:56:04.385901
4426 10:56:04.385951 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4427 10:56:04.386002
4428 10:56:04.386051 [CATrainingPosCal] consider 1 rank data
4429 10:56:04.386101 u2DelayCellTimex100 = 270/100 ps
4430 10:56:04.386152 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 10:56:04.386202 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 10:56:04.386253 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 10:56:04.386303 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 10:56:04.386354 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 10:56:04.386404 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 10:56:04.386455
4437 10:56:04.386505 CA PerBit enable=1, Macro0, CA PI delay=33
4438 10:56:04.386555
4439 10:56:04.386606 [CBTSetCACLKResult] CA Dly = 33
4440 10:56:04.386657 CS Dly: 4 (0~35)
4441 10:56:04.386707 ==
4442 10:56:04.386757 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 10:56:04.386808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 10:56:04.386897 ==
4445 10:56:04.386949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 10:56:04.387000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 10:56:04.387052 [CA 0] Center 35 (5~66) winsize 62
4448 10:56:04.387102 [CA 1] Center 35 (5~66) winsize 62
4449 10:56:04.387153 [CA 2] Center 34 (4~65) winsize 62
4450 10:56:04.387203 [CA 3] Center 34 (4~65) winsize 62
4451 10:56:04.387253 [CA 4] Center 34 (4~65) winsize 62
4452 10:56:04.387303 [CA 5] Center 34 (3~65) winsize 63
4453 10:56:04.387354
4454 10:56:04.387404 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 10:56:04.387455
4456 10:56:04.387505 [CATrainingPosCal] consider 2 rank data
4457 10:56:04.387556 u2DelayCellTimex100 = 270/100 ps
4458 10:56:04.387606 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 10:56:04.387657 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 10:56:04.387708 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 10:56:04.387758 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 10:56:04.387809 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 10:56:04.387859 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 10:56:04.387909
4465 10:56:04.387960 CA PerBit enable=1, Macro0, CA PI delay=33
4466 10:56:04.388010
4467 10:56:04.388060 [CBTSetCACLKResult] CA Dly = 33
4468 10:56:04.388110 CS Dly: 4 (0~36)
4469 10:56:04.388160
4470 10:56:04.388210 ----->DramcWriteLeveling(PI) begin...
4471 10:56:04.388262 ==
4472 10:56:04.388313 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 10:56:04.388364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 10:56:04.388415 ==
4475 10:56:04.388466 Write leveling (Byte 0): 29 => 29
4476 10:56:04.388516 Write leveling (Byte 1): 31 => 31
4477 10:56:04.388567 DramcWriteLeveling(PI) end<-----
4478 10:56:04.388617
4479 10:56:04.388667 ==
4480 10:56:04.388718 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 10:56:04.388769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 10:56:04.388820 ==
4483 10:56:04.388871 [Gating] SW mode calibration
4484 10:56:04.388922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 10:56:04.388973 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 10:56:04.389024 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 10:56:04.389075 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 10:56:04.389126 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 10:56:04.389190 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (0 0) (1 0)
4490 10:56:04.389432 0 9 16 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
4491 10:56:04.389528 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 10:56:04.389580 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 10:56:04.389631 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 10:56:04.389682 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 10:56:04.389733 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 10:56:04.389783 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 10:56:04.389834 0 10 12 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
4498 10:56:04.389888 0 10 16 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
4499 10:56:04.389941 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 10:56:04.389991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 10:56:04.390042 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 10:56:04.390093 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 10:56:04.390143 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 10:56:04.390194 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 10:56:04.390245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4506 10:56:04.390310 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 10:56:04.390393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 10:56:04.390476 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 10:56:04.390557 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 10:56:04.390654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 10:56:04.390737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 10:56:04.390818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 10:56:04.390935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 10:56:04.391014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 10:56:04.391067 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 10:56:04.391118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 10:56:04.391169 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 10:56:04.391221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 10:56:04.391272 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 10:56:04.391323 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 10:56:04.391374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 10:56:04.391425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 10:56:04.391476 Total UI for P1: 0, mck2ui 16
4524 10:56:04.391527 best dqsien dly found for B0: ( 0, 13, 14)
4525 10:56:04.391578 Total UI for P1: 0, mck2ui 16
4526 10:56:04.391648 best dqsien dly found for B1: ( 0, 13, 14)
4527 10:56:04.391702 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4528 10:56:04.391754 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4529 10:56:04.391805
4530 10:56:04.391856 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4531 10:56:04.391907 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 10:56:04.391958 [Gating] SW calibration Done
4533 10:56:04.392009 ==
4534 10:56:04.392060 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 10:56:04.392129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 10:56:04.392182 ==
4537 10:56:04.392233 RX Vref Scan: 0
4538 10:56:04.392284
4539 10:56:04.392333 RX Vref 0 -> 0, step: 1
4540 10:56:04.392384
4541 10:56:04.392434 RX Delay -230 -> 252, step: 16
4542 10:56:04.392485 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4543 10:56:04.392536 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4544 10:56:04.392587 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4545 10:56:04.392637 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4546 10:56:04.392688 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4547 10:56:04.392739 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4548 10:56:04.392789 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4549 10:56:04.392840 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4550 10:56:04.392891 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 10:56:04.392942 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4552 10:56:04.392993 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 10:56:04.393044 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4554 10:56:04.393095 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4555 10:56:04.393146 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4556 10:56:04.393196 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4557 10:56:04.393247 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4558 10:56:04.393297 ==
4559 10:56:04.393348 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 10:56:04.393399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 10:56:04.393449 ==
4562 10:56:04.393500 DQS Delay:
4563 10:56:04.393550 DQS0 = 0, DQS1 = 0
4564 10:56:04.393601 DQM Delay:
4565 10:56:04.393681 DQM0 = 39, DQM1 = 30
4566 10:56:04.393732 DQ Delay:
4567 10:56:04.393782 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4568 10:56:04.393833 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4569 10:56:04.393883 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4570 10:56:04.393933 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4571 10:56:04.393983
4572 10:56:04.394033
4573 10:56:04.394083 ==
4574 10:56:04.394133 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 10:56:04.394184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 10:56:04.394235 ==
4577 10:56:04.394304
4578 10:56:04.394357
4579 10:56:04.394408 TX Vref Scan disable
4580 10:56:04.394459 == TX Byte 0 ==
4581 10:56:04.394510 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 10:56:04.394561 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 10:56:04.394640 == TX Byte 1 ==
4584 10:56:04.394691 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4585 10:56:04.394742 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4586 10:56:04.394793 ==
4587 10:56:04.394881 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 10:56:04.394933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:56:04.395017 ==
4590 10:56:04.395067
4591 10:56:04.395117
4592 10:56:04.395167 TX Vref Scan disable
4593 10:56:04.395218 == TX Byte 0 ==
4594 10:56:04.395269 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 10:56:04.395321 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 10:56:04.395371 == TX Byte 1 ==
4597 10:56:04.395422 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4598 10:56:04.395473 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4599 10:56:04.395523
4600 10:56:04.395573 [DATLAT]
4601 10:56:04.395623 Freq=600, CH1 RK0
4602 10:56:04.395673
4603 10:56:04.395724 DATLAT Default: 0x9
4604 10:56:04.395774 0, 0xFFFF, sum = 0
4605 10:56:04.395826 1, 0xFFFF, sum = 0
4606 10:56:04.395878 2, 0xFFFF, sum = 0
4607 10:56:04.395929 3, 0xFFFF, sum = 0
4608 10:56:04.396163 4, 0xFFFF, sum = 0
4609 10:56:04.396220 5, 0xFFFF, sum = 0
4610 10:56:04.396272 6, 0xFFFF, sum = 0
4611 10:56:04.396324 7, 0xFFFF, sum = 0
4612 10:56:04.396375 8, 0x0, sum = 1
4613 10:56:04.396427 9, 0x0, sum = 2
4614 10:56:04.396478 10, 0x0, sum = 3
4615 10:56:04.396529 11, 0x0, sum = 4
4616 10:56:04.396581 best_step = 9
4617 10:56:04.396687
4618 10:56:04.396737 ==
4619 10:56:04.396823 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 10:56:04.396902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 10:56:04.396967 ==
4622 10:56:04.397046 RX Vref Scan: 1
4623 10:56:04.397098
4624 10:56:04.397149 RX Vref 0 -> 0, step: 1
4625 10:56:04.397201
4626 10:56:04.397266 RX Delay -195 -> 252, step: 8
4627 10:56:04.397316
4628 10:56:04.397367 Set Vref, RX VrefLevel [Byte0]: 58
4629 10:56:04.397454 [Byte1]: 48
4630 10:56:04.397504
4631 10:56:04.397555 Final RX Vref Byte 0 = 58 to rank0
4632 10:56:04.397606 Final RX Vref Byte 1 = 48 to rank0
4633 10:56:04.397656 Final RX Vref Byte 0 = 58 to rank1
4634 10:56:04.397707 Final RX Vref Byte 1 = 48 to rank1==
4635 10:56:04.397758 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 10:56:04.397852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 10:56:04.397904 ==
4638 10:56:04.397954 DQS Delay:
4639 10:56:04.398005 DQS0 = 0, DQS1 = 0
4640 10:56:04.398055 DQM Delay:
4641 10:56:04.398105 DQM0 = 38, DQM1 = 28
4642 10:56:04.398155 DQ Delay:
4643 10:56:04.398206 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4644 10:56:04.398256 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4645 10:56:04.398307 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =24
4646 10:56:04.398357 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4647 10:56:04.398407
4648 10:56:04.398457
4649 10:56:04.398507 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4650 10:56:04.398559 CH1 RK0: MR19=808, MR18=202D
4651 10:56:04.398610 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4652 10:56:04.398678
4653 10:56:04.398729 ----->DramcWriteLeveling(PI) begin...
4654 10:56:04.398782 ==
4655 10:56:04.398842 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 10:56:04.398907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 10:56:04.398958 ==
4658 10:56:04.399009 Write leveling (Byte 0): 29 => 29
4659 10:56:04.399060 Write leveling (Byte 1): 29 => 29
4660 10:56:04.399110 DramcWriteLeveling(PI) end<-----
4661 10:56:04.399161
4662 10:56:04.399211 ==
4663 10:56:04.399261 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 10:56:04.399311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 10:56:04.399362 ==
4666 10:56:04.399413 [Gating] SW mode calibration
4667 10:56:04.399463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 10:56:04.399515 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 10:56:04.399566 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 10:56:04.399617 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 10:56:04.399668 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 10:56:04.399719 0 9 12 | B1->B0 | 3030 2e2e | 1 0 | (1 1) (0 0)
4673 10:56:04.399770 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4674 10:56:04.399820 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 10:56:04.399871 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 10:56:04.399921 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 10:56:04.399972 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 10:56:04.400023 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 10:56:04.400074 0 10 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4680 10:56:04.400125 0 10 12 | B1->B0 | 2f2f 3f3f | 0 0 | (0 0) (0 0)
4681 10:56:04.400176 0 10 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
4682 10:56:04.400226 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 10:56:04.400277 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 10:56:04.400328 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 10:56:04.400378 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 10:56:04.400429 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 10:56:04.400480 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 10:56:04.400530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4689 10:56:04.400581 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:56:04.400631 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 10:56:04.400682 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 10:56:04.400732 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 10:56:04.400783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 10:56:04.400834 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 10:56:04.400885 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 10:56:04.400935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 10:56:04.400986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 10:56:04.401037 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 10:56:04.401087 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 10:56:04.401138 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 10:56:04.401189 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 10:56:04.401240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 10:56:04.401291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 10:56:04.401341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4705 10:56:04.401392 Total UI for P1: 0, mck2ui 16
4706 10:56:04.401443 best dqsien dly found for B0: ( 0, 13, 10)
4707 10:56:04.401504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 10:56:04.401557 Total UI for P1: 0, mck2ui 16
4709 10:56:04.401608 best dqsien dly found for B1: ( 0, 13, 12)
4710 10:56:04.401660 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4711 10:56:04.401712 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4712 10:56:04.401763
4713 10:56:04.401813 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4714 10:56:04.401867 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 10:56:04.401919 [Gating] SW calibration Done
4716 10:56:04.401970 ==
4717 10:56:04.402020 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 10:56:04.402071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 10:56:04.402122 ==
4720 10:56:04.402172 RX Vref Scan: 0
4721 10:56:04.402222
4722 10:56:04.402272 RX Vref 0 -> 0, step: 1
4723 10:56:04.402323
4724 10:56:04.402373 RX Delay -230 -> 252, step: 16
4725 10:56:04.402424 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4726 10:56:04.402475 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4727 10:56:04.402732 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4728 10:56:04.402819 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4729 10:56:04.402884 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4730 10:56:04.402938 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4731 10:56:04.402990 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 10:56:04.403051 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4733 10:56:04.403103 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 10:56:04.403156 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4735 10:56:04.403208 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 10:56:04.403273 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4737 10:56:04.403324 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4738 10:56:04.403374 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4739 10:56:04.403425 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4740 10:56:04.403475 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4741 10:56:04.403526 ==
4742 10:56:04.403576 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 10:56:04.403627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 10:56:04.403678 ==
4745 10:56:04.403729 DQS Delay:
4746 10:56:04.403805 DQS0 = 0, DQS1 = 0
4747 10:56:04.403877 DQM Delay:
4748 10:56:04.403935 DQM0 = 35, DQM1 = 29
4749 10:56:04.404021 DQ Delay:
4750 10:56:04.404078 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4751 10:56:04.404130 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4752 10:56:04.404181 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4753 10:56:04.404232 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4754 10:56:04.404283
4755 10:56:04.404333
4756 10:56:04.404383 ==
4757 10:56:04.404434 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 10:56:04.404485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 10:56:04.404536 ==
4760 10:56:04.404586
4761 10:56:04.404636
4762 10:56:04.404686 TX Vref Scan disable
4763 10:56:04.404736 == TX Byte 0 ==
4764 10:56:04.404787 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4765 10:56:04.404838 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4766 10:56:04.404889 == TX Byte 1 ==
4767 10:56:04.404939 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4768 10:56:04.404990 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4769 10:56:04.405041 ==
4770 10:56:04.405091 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 10:56:04.405142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 10:56:04.405193 ==
4773 10:56:04.405243
4774 10:56:04.405293
4775 10:56:04.405342 TX Vref Scan disable
4776 10:56:04.405393 == TX Byte 0 ==
4777 10:56:04.405443 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4778 10:56:04.405494 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4779 10:56:04.405544 == TX Byte 1 ==
4780 10:56:04.405594 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4781 10:56:04.405645 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4782 10:56:04.405695
4783 10:56:04.405745 [DATLAT]
4784 10:56:04.405796 Freq=600, CH1 RK1
4785 10:56:04.405846
4786 10:56:04.405897 DATLAT Default: 0x9
4787 10:56:04.405947 0, 0xFFFF, sum = 0
4788 10:56:04.405999 1, 0xFFFF, sum = 0
4789 10:56:04.406050 2, 0xFFFF, sum = 0
4790 10:56:04.406101 3, 0xFFFF, sum = 0
4791 10:56:04.406153 4, 0xFFFF, sum = 0
4792 10:56:04.406204 5, 0xFFFF, sum = 0
4793 10:56:04.406256 6, 0xFFFF, sum = 0
4794 10:56:04.406307 7, 0xFFFF, sum = 0
4795 10:56:04.406358 8, 0x0, sum = 1
4796 10:56:04.406409 9, 0x0, sum = 2
4797 10:56:04.406460 10, 0x0, sum = 3
4798 10:56:04.406511 11, 0x0, sum = 4
4799 10:56:04.406562 best_step = 9
4800 10:56:04.406613
4801 10:56:04.406663 ==
4802 10:56:04.406714 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 10:56:04.406764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 10:56:04.406815 ==
4805 10:56:04.406902 RX Vref Scan: 0
4806 10:56:04.406953
4807 10:56:04.407004 RX Vref 0 -> 0, step: 1
4808 10:56:04.407054
4809 10:56:04.407104 RX Delay -195 -> 252, step: 8
4810 10:56:04.407155 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 10:56:04.407205 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 10:56:04.407256 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4813 10:56:04.407306 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4814 10:56:04.407357 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4815 10:56:04.407407 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4816 10:56:04.407462 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 10:56:04.407513 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4818 10:56:04.407563 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4819 10:56:04.407614 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 10:56:04.407664 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4821 10:56:04.407715 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4822 10:56:04.407766 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4823 10:56:04.407816 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4824 10:56:04.407867 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4825 10:56:04.407917 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4826 10:56:04.407968 ==
4827 10:56:04.408018 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 10:56:04.408069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 10:56:04.408119 ==
4830 10:56:04.408169 DQS Delay:
4831 10:56:04.408220 DQS0 = 0, DQS1 = 0
4832 10:56:04.408269 DQM Delay:
4833 10:56:04.408320 DQM0 = 36, DQM1 = 30
4834 10:56:04.408371 DQ Delay:
4835 10:56:04.408421 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4836 10:56:04.408472 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4837 10:56:04.408522 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4838 10:56:04.408572 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4839 10:56:04.408623
4840 10:56:04.408673
4841 10:56:04.408723 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4842 10:56:04.408774 CH1 RK1: MR19=808, MR18=3959
4843 10:56:04.408825 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4844 10:56:04.408876 [RxdqsGatingPostProcess] freq 600
4845 10:56:04.408927 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 10:56:04.408978 Pre-setting of DQS Precalculation
4847 10:56:04.409029 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 10:56:04.409080 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 10:56:04.409131 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 10:56:04.409182
4851 10:56:04.409232
4852 10:56:04.409282 [Calibration Summary] 1200 Mbps
4853 10:56:04.409333 CH 0, Rank 0
4854 10:56:04.409383 SW Impedance : PASS
4855 10:56:04.409433 DUTY Scan : NO K
4856 10:56:04.409483 ZQ Calibration : PASS
4857 10:56:04.409534 Jitter Meter : NO K
4858 10:56:04.409584 CBT Training : PASS
4859 10:56:04.409635 Write leveling : PASS
4860 10:56:04.409701 RX DQS gating : PASS
4861 10:56:04.409756 RX DQ/DQS(RDDQC) : PASS
4862 10:56:04.409807 TX DQ/DQS : PASS
4863 10:56:04.409858 RX DATLAT : PASS
4864 10:56:04.410093 RX DQ/DQS(Engine): PASS
4865 10:56:04.410153 TX OE : NO K
4866 10:56:04.410206 All Pass.
4867 10:56:04.410256
4868 10:56:04.410307 CH 0, Rank 1
4869 10:56:04.410357 SW Impedance : PASS
4870 10:56:04.410408 DUTY Scan : NO K
4871 10:56:04.410459 ZQ Calibration : PASS
4872 10:56:04.410509 Jitter Meter : NO K
4873 10:56:04.410561 CBT Training : PASS
4874 10:56:04.410611 Write leveling : PASS
4875 10:56:04.410666 RX DQS gating : PASS
4876 10:56:04.410743 RX DQ/DQS(RDDQC) : PASS
4877 10:56:04.410826 TX DQ/DQS : PASS
4878 10:56:04.410903 RX DATLAT : PASS
4879 10:56:04.410955 RX DQ/DQS(Engine): PASS
4880 10:56:04.411006 TX OE : NO K
4881 10:56:04.411058 All Pass.
4882 10:56:04.411108
4883 10:56:04.411159 CH 1, Rank 0
4884 10:56:04.411209 SW Impedance : PASS
4885 10:56:04.411260 DUTY Scan : NO K
4886 10:56:04.411310 ZQ Calibration : PASS
4887 10:56:04.411360 Jitter Meter : NO K
4888 10:56:04.411411 CBT Training : PASS
4889 10:56:04.411461 Write leveling : PASS
4890 10:56:04.411511 RX DQS gating : PASS
4891 10:56:04.411562 RX DQ/DQS(RDDQC) : PASS
4892 10:56:04.411612 TX DQ/DQS : PASS
4893 10:56:04.411662 RX DATLAT : PASS
4894 10:56:04.411712 RX DQ/DQS(Engine): PASS
4895 10:56:04.411763 TX OE : NO K
4896 10:56:04.411814 All Pass.
4897 10:56:04.411864
4898 10:56:04.411914 CH 1, Rank 1
4899 10:56:04.411964 SW Impedance : PASS
4900 10:56:04.412014 DUTY Scan : NO K
4901 10:56:04.412064 ZQ Calibration : PASS
4902 10:56:04.412114 Jitter Meter : NO K
4903 10:56:04.412165 CBT Training : PASS
4904 10:56:04.412215 Write leveling : PASS
4905 10:56:04.412265 RX DQS gating : PASS
4906 10:56:04.412315 RX DQ/DQS(RDDQC) : PASS
4907 10:56:04.412365 TX DQ/DQS : PASS
4908 10:56:04.412416 RX DATLAT : PASS
4909 10:56:04.412466 RX DQ/DQS(Engine): PASS
4910 10:56:04.412516 TX OE : NO K
4911 10:56:04.412567 All Pass.
4912 10:56:04.412617
4913 10:56:04.412667 DramC Write-DBI off
4914 10:56:04.412717 PER_BANK_REFRESH: Hybrid Mode
4915 10:56:04.412768 TX_TRACKING: ON
4916 10:56:04.412818 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 10:56:04.412871 [FAST_K] Save calibration result to emmc
4918 10:56:04.412922 dramc_set_vcore_voltage set vcore to 662500
4919 10:56:04.412972 Read voltage for 933, 3
4920 10:56:04.413022 Vio18 = 0
4921 10:56:04.413073 Vcore = 662500
4922 10:56:04.413123 Vdram = 0
4923 10:56:04.413174 Vddq = 0
4924 10:56:04.413224 Vmddr = 0
4925 10:56:04.413275 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 10:56:04.413325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 10:56:04.413376 MEM_TYPE=3, freq_sel=17
4928 10:56:04.413427 sv_algorithm_assistance_LP4_1600
4929 10:56:04.413477 ============ PULL DRAM RESETB DOWN ============
4930 10:56:04.413528 ========== PULL DRAM RESETB DOWN end =========
4931 10:56:04.413579 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 10:56:04.413637 ===================================
4933 10:56:04.413718 LPDDR4 DRAM CONFIGURATION
4934 10:56:04.413798 ===================================
4935 10:56:04.413880 EX_ROW_EN[0] = 0x0
4936 10:56:04.413960 EX_ROW_EN[1] = 0x0
4937 10:56:04.414048 LP4Y_EN = 0x0
4938 10:56:04.414102 WORK_FSP = 0x0
4939 10:56:04.414153 WL = 0x3
4940 10:56:04.414203 RL = 0x3
4941 10:56:04.414254 BL = 0x2
4942 10:56:04.414304 RPST = 0x0
4943 10:56:04.414355 RD_PRE = 0x0
4944 10:56:04.414444 WR_PRE = 0x1
4945 10:56:04.414494 WR_PST = 0x0
4946 10:56:04.414544 DBI_WR = 0x0
4947 10:56:04.414630 DBI_RD = 0x0
4948 10:56:04.414681 OTF = 0x1
4949 10:56:04.414731 ===================================
4950 10:56:04.414782 ===================================
4951 10:56:04.414854 ANA top config
4952 10:56:04.414920 ===================================
4953 10:56:04.414971 DLL_ASYNC_EN = 0
4954 10:56:04.415022 ALL_SLAVE_EN = 1
4955 10:56:04.415072 NEW_RANK_MODE = 1
4956 10:56:04.415124 DLL_IDLE_MODE = 1
4957 10:56:04.415175 LP45_APHY_COMB_EN = 1
4958 10:56:04.415226 TX_ODT_DIS = 1
4959 10:56:04.415276 NEW_8X_MODE = 1
4960 10:56:04.415327 ===================================
4961 10:56:04.415406 ===================================
4962 10:56:04.415472 data_rate = 1866
4963 10:56:04.415523 CKR = 1
4964 10:56:04.415573 DQ_P2S_RATIO = 8
4965 10:56:04.415624 ===================================
4966 10:56:04.415674 CA_P2S_RATIO = 8
4967 10:56:04.415725 DQ_CA_OPEN = 0
4968 10:56:04.415775 DQ_SEMI_OPEN = 0
4969 10:56:04.415826 CA_SEMI_OPEN = 0
4970 10:56:04.415876 CA_FULL_RATE = 0
4971 10:56:04.415926 DQ_CKDIV4_EN = 1
4972 10:56:04.415976 CA_CKDIV4_EN = 1
4973 10:56:04.416042 CA_PREDIV_EN = 0
4974 10:56:04.416095 PH8_DLY = 0
4975 10:56:04.416146 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 10:56:04.416197 DQ_AAMCK_DIV = 4
4977 10:56:04.416247 CA_AAMCK_DIV = 4
4978 10:56:04.416297 CA_ADMCK_DIV = 4
4979 10:56:04.416348 DQ_TRACK_CA_EN = 0
4980 10:56:04.416398 CA_PICK = 933
4981 10:56:04.416448 CA_MCKIO = 933
4982 10:56:04.416498 MCKIO_SEMI = 0
4983 10:56:04.416548 PLL_FREQ = 3732
4984 10:56:04.416598 DQ_UI_PI_RATIO = 32
4985 10:56:04.416666 CA_UI_PI_RATIO = 0
4986 10:56:04.416730 ===================================
4987 10:56:04.416780 ===================================
4988 10:56:04.416831 memory_type:LPDDR4
4989 10:56:04.416881 GP_NUM : 10
4990 10:56:04.416931 SRAM_EN : 1
4991 10:56:04.416982 MD32_EN : 0
4992 10:56:04.417032 ===================================
4993 10:56:04.417083 [ANA_INIT] >>>>>>>>>>>>>>
4994 10:56:04.417134 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 10:56:04.417184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 10:56:04.417235 ===================================
4997 10:56:04.743919 data_rate = 1866,PCW = 0X8f00
4998 10:56:04.744061 ===================================
4999 10:56:04.744128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 10:56:04.744188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 10:56:04.744246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 10:56:04.744302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 10:56:04.744357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 10:56:04.744432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 10:56:04.744501 [ANA_INIT] flow start
5006 10:56:04.744554 [ANA_INIT] PLL >>>>>>>>
5007 10:56:04.744808 [ANA_INIT] PLL <<<<<<<<
5008 10:56:04.744900 [ANA_INIT] MIDPI >>>>>>>>
5009 10:56:04.744957 [ANA_INIT] MIDPI <<<<<<<<
5010 10:56:04.745039 [ANA_INIT] DLL >>>>>>>>
5011 10:56:04.745119 [ANA_INIT] flow end
5012 10:56:04.745203 ============ LP4 DIFF to SE enter ============
5013 10:56:04.745286 ============ LP4 DIFF to SE exit ============
5014 10:56:04.745367 [ANA_INIT] <<<<<<<<<<<<<
5015 10:56:04.745447 [Flow] Enable top DCM control >>>>>
5016 10:56:04.745527 [Flow] Enable top DCM control <<<<<
5017 10:56:04.745610 Enable DLL master slave shuffle
5018 10:56:04.745692 ==============================================================
5019 10:56:04.745772 Gating Mode config
5020 10:56:04.745853 ==============================================================
5021 10:56:04.745933 Config description:
5022 10:56:04.746011 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 10:56:04.746066 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 10:56:04.746119 SELPH_MODE 0: By rank 1: By Phase
5025 10:56:04.746171 ==============================================================
5026 10:56:04.746223 GAT_TRACK_EN = 1
5027 10:56:04.746274 RX_GATING_MODE = 2
5028 10:56:04.746325 RX_GATING_TRACK_MODE = 2
5029 10:56:04.746376 SELPH_MODE = 1
5030 10:56:04.746434 PICG_EARLY_EN = 1
5031 10:56:04.746513 VALID_LAT_VALUE = 1
5032 10:56:04.746565 ==============================================================
5033 10:56:04.746617 Enter into Gating configuration >>>>
5034 10:56:04.746698 Exit from Gating configuration <<<<
5035 10:56:04.746779 Enter into DVFS_PRE_config >>>>>
5036 10:56:04.746887 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 10:56:04.746942 Exit from DVFS_PRE_config <<<<<
5038 10:56:04.746994 Enter into PICG configuration >>>>
5039 10:56:04.747045 Exit from PICG configuration <<<<
5040 10:56:04.747096 [RX_INPUT] configuration >>>>>
5041 10:56:04.747153 [RX_INPUT] configuration <<<<<
5042 10:56:04.747205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 10:56:04.747256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 10:56:04.747308 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 10:56:04.747359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 10:56:04.747410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 10:56:04.747461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 10:56:04.747517 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 10:56:04.747569 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 10:56:04.747621 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 10:56:04.747671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 10:56:04.747722 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 10:56:04.747773 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 10:56:04.747825 ===================================
5055 10:56:04.747876 LPDDR4 DRAM CONFIGURATION
5056 10:56:04.747933 ===================================
5057 10:56:04.747984 EX_ROW_EN[0] = 0x0
5058 10:56:04.748035 EX_ROW_EN[1] = 0x0
5059 10:56:04.748086 LP4Y_EN = 0x0
5060 10:56:04.748140 WORK_FSP = 0x0
5061 10:56:04.748192 WL = 0x3
5062 10:56:04.748242 RL = 0x3
5063 10:56:04.748293 BL = 0x2
5064 10:56:04.748343 RPST = 0x0
5065 10:56:04.748393 RD_PRE = 0x0
5066 10:56:04.748444 WR_PRE = 0x1
5067 10:56:04.748494 WR_PST = 0x0
5068 10:56:04.748552 DBI_WR = 0x0
5069 10:56:04.748603 DBI_RD = 0x0
5070 10:56:04.748654 OTF = 0x1
5071 10:56:04.748709 ===================================
5072 10:56:04.748761 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 10:56:04.748812 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 10:56:04.748864 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 10:56:04.748915 ===================================
5076 10:56:04.748966 LPDDR4 DRAM CONFIGURATION
5077 10:56:04.749017 ===================================
5078 10:56:04.749068 EX_ROW_EN[0] = 0x10
5079 10:56:04.749142 EX_ROW_EN[1] = 0x0
5080 10:56:04.749222 LP4Y_EN = 0x0
5081 10:56:04.749306 WORK_FSP = 0x0
5082 10:56:04.749386 WL = 0x3
5083 10:56:04.749465 RL = 0x3
5084 10:56:04.749548 BL = 0x2
5085 10:56:04.749628 RPST = 0x0
5086 10:56:04.749709 RD_PRE = 0x0
5087 10:56:04.749790 WR_PRE = 0x1
5088 10:56:04.749871 WR_PST = 0x0
5089 10:56:04.749945 DBI_WR = 0x0
5090 10:56:04.749997 DBI_RD = 0x0
5091 10:56:04.750050 OTF = 0x1
5092 10:56:04.750102 ===================================
5093 10:56:04.750155 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 10:56:04.750207 nWR fixed to 30
5095 10:56:04.750259 [ModeRegInit_LP4] CH0 RK0
5096 10:56:04.750311 [ModeRegInit_LP4] CH0 RK1
5097 10:56:04.750369 [ModeRegInit_LP4] CH1 RK0
5098 10:56:04.750422 [ModeRegInit_LP4] CH1 RK1
5099 10:56:04.750474 match AC timing 9
5100 10:56:04.750526 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 10:56:04.750578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 10:56:04.750631 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 10:56:04.750689 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 10:56:04.750772 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 10:56:04.750883 ==
5106 10:56:04.750939 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 10:56:04.750997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 10:56:04.751052 ==
5109 10:56:04.751104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 10:56:04.751157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 10:56:04.751211 [CA 0] Center 38 (8~69) winsize 62
5112 10:56:04.751264 [CA 1] Center 38 (8~69) winsize 62
5113 10:56:04.751316 [CA 2] Center 35 (5~66) winsize 62
5114 10:56:04.751368 [CA 3] Center 35 (4~66) winsize 63
5115 10:56:04.751608 [CA 4] Center 34 (4~65) winsize 62
5116 10:56:04.751698 [CA 5] Center 34 (4~64) winsize 61
5117 10:56:04.751751
5118 10:56:04.751823 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 10:56:04.751890
5120 10:56:04.751943 [CATrainingPosCal] consider 1 rank data
5121 10:56:04.751995 u2DelayCellTimex100 = 270/100 ps
5122 10:56:04.752052 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5123 10:56:04.752121 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5124 10:56:04.752189 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5125 10:56:04.752241 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5126 10:56:04.752293 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5127 10:56:04.752345 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 10:56:04.752396
5129 10:56:04.752455 CA PerBit enable=1, Macro0, CA PI delay=34
5130 10:56:04.752524
5131 10:56:04.752578 [CBTSetCACLKResult] CA Dly = 34
5132 10:56:04.752631 CS Dly: 7 (0~38)
5133 10:56:04.752684 ==
5134 10:56:04.752737 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 10:56:04.752790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 10:56:04.752844 ==
5137 10:56:04.752898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 10:56:04.752951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5139 10:56:04.753007 [CA 0] Center 38 (8~69) winsize 62
5140 10:56:04.753078 [CA 1] Center 38 (8~69) winsize 62
5141 10:56:04.753131 [CA 2] Center 35 (5~66) winsize 62
5142 10:56:04.753183 [CA 3] Center 35 (5~66) winsize 62
5143 10:56:04.753241 [CA 4] Center 34 (4~65) winsize 62
5144 10:56:04.753323 [CA 5] Center 34 (4~64) winsize 61
5145 10:56:04.753375
5146 10:56:04.753449 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5147 10:56:04.753515
5148 10:56:04.753567 [CATrainingPosCal] consider 2 rank data
5149 10:56:04.753619 u2DelayCellTimex100 = 270/100 ps
5150 10:56:04.753671 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5151 10:56:04.753723 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 10:56:04.753776 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5153 10:56:04.753828 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5154 10:56:04.753916 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5155 10:56:04.754000 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5156 10:56:04.754052
5157 10:56:04.754104 CA PerBit enable=1, Macro0, CA PI delay=34
5158 10:56:04.754156
5159 10:56:04.754207 [CBTSetCACLKResult] CA Dly = 34
5160 10:56:04.754266 CS Dly: 7 (0~38)
5161 10:56:04.754350
5162 10:56:04.754402 ----->DramcWriteLeveling(PI) begin...
5163 10:56:04.754456 ==
5164 10:56:04.754508 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 10:56:04.754561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 10:56:04.754614 ==
5167 10:56:04.754687 Write leveling (Byte 0): 31 => 31
5168 10:56:04.754741 Write leveling (Byte 1): 30 => 30
5169 10:56:04.754794 DramcWriteLeveling(PI) end<-----
5170 10:56:04.754870
5171 10:56:04.754929 ==
5172 10:56:04.754981 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 10:56:04.755034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 10:56:04.755087 ==
5175 10:56:04.755139 [Gating] SW mode calibration
5176 10:56:04.755191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 10:56:04.755245 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 10:56:04.755303 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5179 10:56:04.755356 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5180 10:56:04.755409 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 10:56:04.755462 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 10:56:04.755515 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 10:56:04.755567 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 10:56:04.755620 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 10:56:04.755678 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5186 10:56:04.755732 0 15 0 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5187 10:56:04.755785 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5188 10:56:04.755838 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 10:56:04.755890 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 10:56:04.755943 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 10:56:04.755996 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 10:56:04.756053 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 10:56:04.756123 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5194 10:56:04.756189 1 0 0 | B1->B0 | 2929 4141 | 0 0 | (0 0) (0 0)
5195 10:56:04.756242 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5196 10:56:04.756295 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 10:56:04.756347 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 10:56:04.756400 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 10:56:04.756452 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 10:56:04.756511 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 10:56:04.756565 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 10:56:04.756617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5203 10:56:04.756670 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 10:56:04.756722 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 10:56:04.756774 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 10:56:04.756826 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 10:56:04.756885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 10:56:04.756938 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 10:56:04.756991 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 10:56:04.757043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 10:56:04.757096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 10:56:04.757148 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 10:56:04.757201 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 10:56:04.757261 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 10:56:04.757344 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 10:56:04.757425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 10:56:04.757507 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 10:56:04.757589 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5219 10:56:04.757706 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 10:56:04.757968 Total UI for P1: 0, mck2ui 16
5221 10:56:04.758029 best dqsien dly found for B0: ( 1, 2, 30)
5222 10:56:04.758084 Total UI for P1: 0, mck2ui 16
5223 10:56:04.758137 best dqsien dly found for B1: ( 1, 3, 2)
5224 10:56:04.758190 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5225 10:56:04.758242 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5226 10:56:04.758295
5227 10:56:04.758367 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5228 10:56:04.758449 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5229 10:56:04.758530 [Gating] SW calibration Done
5230 10:56:04.758611 ==
5231 10:56:04.758696 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 10:56:04.758779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 10:56:04.758891 ==
5234 10:56:04.758976 RX Vref Scan: 0
5235 10:56:04.759032
5236 10:56:04.759085 RX Vref 0 -> 0, step: 1
5237 10:56:04.759137
5238 10:56:04.759190 RX Delay -80 -> 252, step: 8
5239 10:56:04.759242 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5240 10:56:04.759294 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5241 10:56:04.759347 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5242 10:56:04.759400 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5243 10:56:04.759456 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5244 10:56:04.759510 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5245 10:56:04.759563 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5246 10:56:04.759615 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5247 10:56:04.759667 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5248 10:56:04.759726 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5249 10:56:04.759779 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5250 10:56:04.759832 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5251 10:56:04.759884 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5252 10:56:04.759936 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5253 10:56:04.759989 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5254 10:56:04.760047 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5255 10:56:04.760101 ==
5256 10:56:04.760153 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 10:56:04.760205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 10:56:04.760258 ==
5259 10:56:04.760311 DQS Delay:
5260 10:56:04.760368 DQS0 = 0, DQS1 = 0
5261 10:56:04.760421 DQM Delay:
5262 10:56:04.760473 DQM0 = 95, DQM1 = 83
5263 10:56:04.760525 DQ Delay:
5264 10:56:04.760577 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5265 10:56:04.760629 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5266 10:56:04.760682 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5267 10:56:04.760733 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =91
5268 10:56:04.760791
5269 10:56:04.760844
5270 10:56:04.760895 ==
5271 10:56:04.760948 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 10:56:04.761000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 10:56:04.761053 ==
5274 10:56:04.761105
5275 10:56:04.761161
5276 10:56:04.761214 TX Vref Scan disable
5277 10:56:04.761266 == TX Byte 0 ==
5278 10:56:04.761319 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5279 10:56:04.761372 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5280 10:56:04.761425 == TX Byte 1 ==
5281 10:56:04.761477 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5282 10:56:04.761536 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5283 10:56:04.761618 ==
5284 10:56:04.761700 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 10:56:04.761782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 10:56:04.761864 ==
5287 10:56:04.761945
5288 10:56:04.762026
5289 10:56:04.762081 TX Vref Scan disable
5290 10:56:04.762134 == TX Byte 0 ==
5291 10:56:04.762187 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5292 10:56:04.762244 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5293 10:56:04.762297 == TX Byte 1 ==
5294 10:56:04.762350 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5295 10:56:04.762402 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5296 10:56:04.762454
5297 10:56:04.762506 [DATLAT]
5298 10:56:04.762558 Freq=933, CH0 RK0
5299 10:56:04.762637
5300 10:56:04.762718 DATLAT Default: 0xd
5301 10:56:04.762799 0, 0xFFFF, sum = 0
5302 10:56:04.762902 1, 0xFFFF, sum = 0
5303 10:56:04.762958 2, 0xFFFF, sum = 0
5304 10:56:04.763016 3, 0xFFFF, sum = 0
5305 10:56:04.763071 4, 0xFFFF, sum = 0
5306 10:56:04.763123 5, 0xFFFF, sum = 0
5307 10:56:04.763177 6, 0xFFFF, sum = 0
5308 10:56:04.763230 7, 0xFFFF, sum = 0
5309 10:56:04.763283 8, 0xFFFF, sum = 0
5310 10:56:04.763336 9, 0xFFFF, sum = 0
5311 10:56:04.763389 10, 0x0, sum = 1
5312 10:56:04.763448 11, 0x0, sum = 2
5313 10:56:04.763501 12, 0x0, sum = 3
5314 10:56:04.763554 13, 0x0, sum = 4
5315 10:56:04.763606 best_step = 11
5316 10:56:04.763658
5317 10:56:04.763710 ==
5318 10:56:04.763762 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 10:56:04.763815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 10:56:04.763872 ==
5321 10:56:04.763925 RX Vref Scan: 1
5322 10:56:04.763977
5323 10:56:04.764030 RX Vref 0 -> 0, step: 1
5324 10:56:04.764088
5325 10:56:04.764140 RX Delay -69 -> 252, step: 4
5326 10:56:04.764192
5327 10:56:04.764244 Set Vref, RX VrefLevel [Byte0]: 62
5328 10:56:04.764296 [Byte1]: 47
5329 10:56:04.764348
5330 10:56:04.764400 Final RX Vref Byte 0 = 62 to rank0
5331 10:56:04.764453 Final RX Vref Byte 1 = 47 to rank0
5332 10:56:04.764523 Final RX Vref Byte 0 = 62 to rank1
5333 10:56:04.764605 Final RX Vref Byte 1 = 47 to rank1==
5334 10:56:04.764689 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 10:56:04.764772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 10:56:04.764854 ==
5337 10:56:04.764935 DQS Delay:
5338 10:56:04.765015 DQS0 = 0, DQS1 = 0
5339 10:56:04.765090 DQM Delay:
5340 10:56:04.765144 DQM0 = 95, DQM1 = 82
5341 10:56:04.765197 DQ Delay:
5342 10:56:04.765249 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5343 10:56:04.765302 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =106
5344 10:56:04.765355 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =78
5345 10:56:04.765407 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =90
5346 10:56:04.765464
5347 10:56:04.765545
5348 10:56:04.765628 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5349 10:56:04.765710 CH0 RK0: MR19=505, MR18=1211
5350 10:56:04.765797 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5351 10:56:04.765872
5352 10:56:04.765926 ----->DramcWriteLeveling(PI) begin...
5353 10:56:04.765979 ==
5354 10:56:04.766032 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 10:56:04.766085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 10:56:04.766138 ==
5357 10:56:04.766191 Write leveling (Byte 0): 33 => 33
5358 10:56:04.766243 Write leveling (Byte 1): 28 => 28
5359 10:56:04.766296 DramcWriteLeveling(PI) end<-----
5360 10:56:04.766352
5361 10:56:04.766403 ==
5362 10:56:04.766454 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 10:56:04.766505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 10:56:04.766556 ==
5365 10:56:04.766606 [Gating] SW mode calibration
5366 10:56:04.766657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 10:56:04.766718 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 10:56:04.766799 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5369 10:56:04.767087 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 10:56:04.767146 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 10:56:04.767230 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 10:56:04.767282 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 10:56:04.767334 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 10:56:04.767407 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 10:56:04.767460 0 14 28 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (0 0)
5376 10:56:04.767525 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5377 10:56:04.767576 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 10:56:04.767627 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 10:56:04.767678 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 10:56:04.767729 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 10:56:04.767786 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 10:56:04.767837 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 10:56:04.767888 0 15 28 | B1->B0 | 2525 3535 | 1 0 | (0 0) (1 1)
5384 10:56:04.767939 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5385 10:56:04.767990 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 10:56:04.768041 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 10:56:04.768092 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 10:56:04.768148 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 10:56:04.768200 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 10:56:04.768250 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 10:56:04.768302 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 10:56:04.768353 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 10:56:04.768404 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5394 10:56:04.768455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 10:56:04.768510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 10:56:04.768564 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 10:56:04.768615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 10:56:04.768665 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 10:56:04.768716 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 10:56:04.768772 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 10:56:04.768824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 10:56:04.768875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 10:56:04.768926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 10:56:04.768976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 10:56:04.769027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 10:56:04.769078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 10:56:04.769128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5408 10:56:04.769208 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5409 10:56:04.769288 Total UI for P1: 0, mck2ui 16
5410 10:56:04.769369 best dqsien dly found for B0: ( 1, 2, 28)
5411 10:56:04.769450 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 10:56:04.769531 Total UI for P1: 0, mck2ui 16
5413 10:56:04.769614 best dqsien dly found for B1: ( 1, 3, 0)
5414 10:56:04.769694 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5415 10:56:04.769775 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5416 10:56:04.769854
5417 10:56:04.769935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5418 10:56:04.769989 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5419 10:56:04.770040 [Gating] SW calibration Done
5420 10:56:04.770091 ==
5421 10:56:04.770142 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 10:56:04.770194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 10:56:04.770250 ==
5424 10:56:04.770301 RX Vref Scan: 0
5425 10:56:04.770352
5426 10:56:04.770402 RX Vref 0 -> 0, step: 1
5427 10:56:04.770453
5428 10:56:04.770503 RX Delay -80 -> 252, step: 8
5429 10:56:04.770554 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5430 10:56:04.770622 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5431 10:56:04.770703 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5432 10:56:04.770784 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5433 10:56:04.770917 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5434 10:56:04.771001 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5435 10:56:04.771082 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5436 10:56:04.771170 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5437 10:56:04.771226 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5438 10:56:04.771278 iDelay=208, Bit 9, Center 67 (-24 ~ 159) 184
5439 10:56:04.771329 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5440 10:56:04.771399 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5441 10:56:04.771480 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5442 10:56:04.771560 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5443 10:56:04.771640 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5444 10:56:04.771720 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5445 10:56:04.771799 ==
5446 10:56:04.771863 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 10:56:04.771915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 10:56:04.771967 ==
5449 10:56:04.772022 DQS Delay:
5450 10:56:04.772074 DQS0 = 0, DQS1 = 0
5451 10:56:04.772125 DQM Delay:
5452 10:56:04.772176 DQM0 = 92, DQM1 = 82
5453 10:56:04.772226 DQ Delay:
5454 10:56:04.772277 DQ0 =95, DQ1 =95, DQ2 =87, DQ3 =87
5455 10:56:04.772328 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5456 10:56:04.772379 DQ8 =71, DQ9 =67, DQ10 =87, DQ11 =71
5457 10:56:04.772459 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =87
5458 10:56:04.772538
5459 10:56:04.772617
5460 10:56:04.772702 ==
5461 10:56:04.772757 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 10:56:04.772814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 10:56:04.772867 ==
5464 10:56:04.772918
5465 10:56:04.772968
5466 10:56:04.773018 TX Vref Scan disable
5467 10:56:04.773068 == TX Byte 0 ==
5468 10:56:04.773119 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5469 10:56:04.773174 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5470 10:56:04.773226 == TX Byte 1 ==
5471 10:56:04.773277 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5472 10:56:04.773329 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5473 10:56:04.773380 ==
5474 10:56:04.773431 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 10:56:04.773481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 10:56:04.773532 ==
5477 10:56:04.773610
5478 10:56:04.773689
5479 10:56:04.773956 TX Vref Scan disable
5480 10:56:04.774046 == TX Byte 0 ==
5481 10:56:04.774099 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5482 10:56:04.774151 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5483 10:56:04.774202 == TX Byte 1 ==
5484 10:56:04.774253 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5485 10:56:04.774308 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5486 10:56:04.774391
5487 10:56:04.774485 [DATLAT]
5488 10:56:04.774564 Freq=933, CH0 RK1
5489 10:56:04.774644
5490 10:56:04.774724 DATLAT Default: 0xb
5491 10:56:04.774803 0, 0xFFFF, sum = 0
5492 10:56:04.774903 1, 0xFFFF, sum = 0
5493 10:56:04.774960 2, 0xFFFF, sum = 0
5494 10:56:04.775012 3, 0xFFFF, sum = 0
5495 10:56:04.775064 4, 0xFFFF, sum = 0
5496 10:56:04.775115 5, 0xFFFF, sum = 0
5497 10:56:04.775166 6, 0xFFFF, sum = 0
5498 10:56:04.775222 7, 0xFFFF, sum = 0
5499 10:56:04.775273 8, 0xFFFF, sum = 0
5500 10:56:04.775324 9, 0xFFFF, sum = 0
5501 10:56:04.775376 10, 0x0, sum = 1
5502 10:56:04.775427 11, 0x0, sum = 2
5503 10:56:04.775479 12, 0x0, sum = 3
5504 10:56:04.775530 13, 0x0, sum = 4
5505 10:56:04.775588 best_step = 11
5506 10:56:04.775639
5507 10:56:04.775689 ==
5508 10:56:04.775740 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 10:56:04.775792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 10:56:04.775842 ==
5511 10:56:04.775893 RX Vref Scan: 0
5512 10:56:04.775943
5513 10:56:04.775994 RX Vref 0 -> 0, step: 1
5514 10:56:04.776044
5515 10:56:04.776094 RX Delay -69 -> 252, step: 4
5516 10:56:04.776150 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5517 10:56:04.776202 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5518 10:56:04.776252 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5519 10:56:04.776303 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5520 10:56:04.776360 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5521 10:56:04.776412 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5522 10:56:04.776462 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5523 10:56:04.776514 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5524 10:56:04.776565 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5525 10:56:04.776615 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5526 10:56:04.776666 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5527 10:56:04.776721 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5528 10:56:04.776774 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5529 10:56:04.776824 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5530 10:56:04.776875 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5531 10:56:04.776926 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5532 10:56:04.776976 ==
5533 10:56:04.777027 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 10:56:04.777078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 10:56:04.777158 ==
5536 10:56:04.777238 DQS Delay:
5537 10:56:04.777317 DQS0 = 0, DQS1 = 0
5538 10:56:04.777397 DQM Delay:
5539 10:56:04.777479 DQM0 = 92, DQM1 = 83
5540 10:56:04.777559 DQ Delay:
5541 10:56:04.777639 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5542 10:56:04.777719 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5543 10:56:04.777799 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5544 10:56:04.777877 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =92
5545 10:56:04.777931
5546 10:56:04.777982
5547 10:56:04.778032 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5548 10:56:04.778085 CH0 RK1: MR19=505, MR18=2F10
5549 10:56:04.778135 CH0_RK1: MR19=0x505, MR18=0x2F10, DQSOSC=407, MR23=63, INC=65, DEC=43
5550 10:56:04.778186 [RxdqsGatingPostProcess] freq 933
5551 10:56:04.778237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 10:56:04.778288 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 10:56:04.778345 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 10:56:04.778397 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 10:56:04.778447 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 10:56:04.778498 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 10:56:04.778548 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 10:56:04.778599 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 10:56:04.778650 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 10:56:04.778706 Pre-setting of DQS Precalculation
5561 10:56:04.778788 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 10:56:04.778894 ==
5563 10:56:04.778947 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 10:56:04.778999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 10:56:04.779050 ==
5566 10:56:04.779117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 10:56:04.779199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5568 10:56:04.779267 [CA 0] Center 37 (7~67) winsize 61
5569 10:56:04.779321 [CA 1] Center 37 (7~67) winsize 61
5570 10:56:04.779372 [CA 2] Center 34 (5~64) winsize 60
5571 10:56:04.779423 [CA 3] Center 34 (4~64) winsize 61
5572 10:56:04.779474 [CA 4] Center 34 (5~64) winsize 60
5573 10:56:04.779525 [CA 5] Center 33 (4~63) winsize 60
5574 10:56:04.779575
5575 10:56:04.779625 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5576 10:56:04.779676
5577 10:56:04.779732 [CATrainingPosCal] consider 1 rank data
5578 10:56:04.779784 u2DelayCellTimex100 = 270/100 ps
5579 10:56:04.779835 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5580 10:56:04.779885 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5581 10:56:04.779936 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5582 10:56:04.779992 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 10:56:04.780043 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5584 10:56:04.780094 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5585 10:56:04.780144
5586 10:56:04.780194 CA PerBit enable=1, Macro0, CA PI delay=33
5587 10:56:04.780244
5588 10:56:04.780295 [CBTSetCACLKResult] CA Dly = 33
5589 10:56:04.780350 CS Dly: 5 (0~36)
5590 10:56:04.780402 ==
5591 10:56:04.780453 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 10:56:04.780504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 10:56:04.780556 ==
5594 10:56:04.780607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 10:56:04.780658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5596 10:56:04.780710 [CA 0] Center 38 (8~68) winsize 61
5597 10:56:04.780761 [CA 1] Center 37 (7~68) winsize 62
5598 10:56:04.780812 [CA 2] Center 35 (5~65) winsize 61
5599 10:56:04.780869 [CA 3] Center 34 (4~64) winsize 61
5600 10:56:04.780920 [CA 4] Center 34 (5~64) winsize 60
5601 10:56:04.780971 [CA 5] Center 34 (4~64) winsize 61
5602 10:56:04.781025
5603 10:56:04.781077 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5604 10:56:04.781128
5605 10:56:04.781178 [CATrainingPosCal] consider 2 rank data
5606 10:56:04.781229 u2DelayCellTimex100 = 270/100 ps
5607 10:56:04.781279 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5608 10:56:04.781330 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5609 10:56:04.781565 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5610 10:56:04.781622 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 10:56:04.781707 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5612 10:56:04.781758 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5613 10:56:04.781809
5614 10:56:04.781867 CA PerBit enable=1, Macro0, CA PI delay=33
5615 10:56:04.781918
5616 10:56:04.781969 [CBTSetCACLKResult] CA Dly = 33
5617 10:56:04.782020 CS Dly: 6 (0~39)
5618 10:56:04.782070
5619 10:56:04.782120 ----->DramcWriteLeveling(PI) begin...
5620 10:56:04.782172 ==
5621 10:56:04.782223 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 10:56:04.782278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 10:56:04.782330 ==
5624 10:56:04.782380 Write leveling (Byte 0): 23 => 23
5625 10:56:04.782431 Write leveling (Byte 1): 27 => 27
5626 10:56:04.782481 DramcWriteLeveling(PI) end<-----
5627 10:56:04.782532
5628 10:56:04.782582 ==
5629 10:56:04.782637 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 10:56:04.782718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 10:56:04.782798 ==
5632 10:56:04.782870 [Gating] SW mode calibration
5633 10:56:04.782923 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 10:56:04.782975 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 10:56:04.783030 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5636 10:56:04.783083 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 10:56:04.783135 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 10:56:04.783186 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 10:56:04.783237 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 10:56:04.783287 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 10:56:04.783338 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 10:56:04.783389 0 14 28 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 1)
5643 10:56:04.783447 0 15 0 | B1->B0 | 2525 2828 | 0 0 | (1 1) (1 1)
5644 10:56:04.783499 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 10:56:04.783550 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 10:56:04.783601 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 10:56:04.783652 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 10:56:04.783708 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 10:56:04.783760 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 10:56:04.783811 0 15 28 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5651 10:56:04.783861 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 10:56:04.783912 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 10:56:04.783963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 10:56:04.784014 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 10:56:04.784065 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 10:56:04.784120 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 10:56:04.784172 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 10:56:04.784223 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5659 10:56:04.784274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 10:56:04.784325 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 10:56:04.784375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 10:56:04.784426 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 10:56:04.784476 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 10:56:04.784533 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 10:56:04.784584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 10:56:04.784635 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 10:56:04.784686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 10:56:04.784741 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 10:56:04.784793 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 10:56:04.784844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 10:56:04.784895 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 10:56:04.784946 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 10:56:04.784997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 10:56:04.785047 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 10:56:04.785098 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5676 10:56:04.785154 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 10:56:04.785206 Total UI for P1: 0, mck2ui 16
5678 10:56:04.785258 best dqsien dly found for B0: ( 1, 2, 30)
5679 10:56:04.785309 Total UI for P1: 0, mck2ui 16
5680 10:56:04.785360 best dqsien dly found for B1: ( 1, 2, 30)
5681 10:56:04.785411 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5682 10:56:04.785461 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5683 10:56:04.785516
5684 10:56:04.785568 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5685 10:56:04.785619 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5686 10:56:04.785669 [Gating] SW calibration Done
5687 10:56:04.785720 ==
5688 10:56:04.785771 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 10:56:04.785822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 10:56:04.785872 ==
5691 10:56:04.785930 RX Vref Scan: 0
5692 10:56:04.785982
5693 10:56:04.786032 RX Vref 0 -> 0, step: 1
5694 10:56:04.786083
5695 10:56:04.786133 RX Delay -80 -> 252, step: 8
5696 10:56:04.786183 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5697 10:56:04.786234 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5698 10:56:04.786289 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5699 10:56:04.786341 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5700 10:56:04.786393 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5701 10:56:04.786443 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5702 10:56:04.786493 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5703 10:56:04.786545 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5704 10:56:04.786625 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5705 10:56:04.786706 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5706 10:56:04.786786 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5707 10:56:04.786902 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5708 10:56:04.786973 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5709 10:56:04.787025 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5710 10:56:04.787077 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5711 10:56:04.787332 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5712 10:56:04.787428 ==
5713 10:56:04.787495 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 10:56:04.787547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 10:56:04.787598 ==
5716 10:56:04.787649 DQS Delay:
5717 10:56:04.787708 DQS0 = 0, DQS1 = 0
5718 10:56:04.787760 DQM Delay:
5719 10:56:04.787817 DQM0 = 94, DQM1 = 86
5720 10:56:04.787868 DQ Delay:
5721 10:56:04.787919 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5722 10:56:04.787975 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5723 10:56:04.788027 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5724 10:56:04.788078 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5725 10:56:04.788129
5726 10:56:04.788179
5727 10:56:04.788229 ==
5728 10:56:04.788280 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 10:56:04.788330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 10:56:04.788381 ==
5731 10:56:04.788439
5732 10:56:04.788490
5733 10:56:04.788541 TX Vref Scan disable
5734 10:56:04.788591 == TX Byte 0 ==
5735 10:56:04.788642 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5736 10:56:04.788693 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5737 10:56:04.788748 == TX Byte 1 ==
5738 10:56:04.788800 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 10:56:04.788851 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 10:56:04.788902 ==
5741 10:56:04.788953 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 10:56:04.789003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 10:56:04.789056 ==
5744 10:56:04.789106
5745 10:56:04.789161
5746 10:56:04.789212 TX Vref Scan disable
5747 10:56:04.789263 == TX Byte 0 ==
5748 10:56:04.789314 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5749 10:56:04.789364 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5750 10:56:04.789415 == TX Byte 1 ==
5751 10:56:04.789465 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5752 10:56:04.789520 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5753 10:56:04.789572
5754 10:56:04.789622 [DATLAT]
5755 10:56:04.789673 Freq=933, CH1 RK0
5756 10:56:04.789723
5757 10:56:04.789774 DATLAT Default: 0xd
5758 10:56:04.789824 0, 0xFFFF, sum = 0
5759 10:56:04.789876 1, 0xFFFF, sum = 0
5760 10:56:04.789931 2, 0xFFFF, sum = 0
5761 10:56:04.789986 3, 0xFFFF, sum = 0
5762 10:56:04.790037 4, 0xFFFF, sum = 0
5763 10:56:04.790089 5, 0xFFFF, sum = 0
5764 10:56:04.790141 6, 0xFFFF, sum = 0
5765 10:56:04.790192 7, 0xFFFF, sum = 0
5766 10:56:04.790242 8, 0xFFFF, sum = 0
5767 10:56:04.790294 9, 0xFFFF, sum = 0
5768 10:56:04.790345 10, 0x0, sum = 1
5769 10:56:04.790402 11, 0x0, sum = 2
5770 10:56:04.790470 12, 0x0, sum = 3
5771 10:56:04.790539 13, 0x0, sum = 4
5772 10:56:04.790592 best_step = 11
5773 10:56:04.790642
5774 10:56:04.790692 ==
5775 10:56:04.790742 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 10:56:04.790793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 10:56:04.790869 ==
5778 10:56:04.790935 RX Vref Scan: 1
5779 10:56:04.790989
5780 10:56:04.791066 RX Vref 0 -> 0, step: 1
5781 10:56:04.791131
5782 10:56:04.791181 RX Delay -69 -> 252, step: 4
5783 10:56:04.791232
5784 10:56:04.791282 Set Vref, RX VrefLevel [Byte0]: 58
5785 10:56:04.791333 [Byte1]: 48
5786 10:56:04.791388
5787 10:56:04.791439 Final RX Vref Byte 0 = 58 to rank0
5788 10:56:04.791491 Final RX Vref Byte 1 = 48 to rank0
5789 10:56:04.791542 Final RX Vref Byte 0 = 58 to rank1
5790 10:56:04.791592 Final RX Vref Byte 1 = 48 to rank1==
5791 10:56:04.791684 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 10:56:04.791765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 10:56:04.791861 ==
5794 10:56:04.791929 DQS Delay:
5795 10:56:04.791980 DQS0 = 0, DQS1 = 0
5796 10:56:04.792064 DQM Delay:
5797 10:56:04.792115 DQM0 = 96, DQM1 = 86
5798 10:56:04.792166 DQ Delay:
5799 10:56:04.792217 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5800 10:56:04.792267 DQ4 =94, DQ5 =104, DQ6 =108, DQ7 =94
5801 10:56:04.792318 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5802 10:56:04.792368 DQ12 =94, DQ13 =94, DQ14 =92, DQ15 =94
5803 10:56:04.792423
5804 10:56:04.792504
5805 10:56:04.792554 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd06, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5806 10:56:04.792609 CH1 RK0: MR19=405, MR18=FD06
5807 10:56:04.792660 CH1_RK0: MR19=0x405, MR18=0xFD06, DQSOSC=420, MR23=63, INC=61, DEC=40
5808 10:56:04.792711
5809 10:56:04.792762 ----->DramcWriteLeveling(PI) begin...
5810 10:56:04.792832 ==
5811 10:56:04.792897 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 10:56:04.792948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 10:56:04.792999 ==
5814 10:56:04.793050 Write leveling (Byte 0): 24 => 24
5815 10:56:04.793100 Write leveling (Byte 1): 26 => 26
5816 10:56:04.793151 DramcWriteLeveling(PI) end<-----
5817 10:56:04.793201
5818 10:56:04.793257 ==
5819 10:56:04.793350 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 10:56:04.793415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 10:56:04.793466 ==
5822 10:56:04.793517 [Gating] SW mode calibration
5823 10:56:04.793567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5824 10:56:04.793636 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5825 10:56:04.793703 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5826 10:56:04.793754 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 10:56:04.793804 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 10:56:04.793856 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 10:56:04.793907 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 10:56:04.793958 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 10:56:04.794015 0 14 24 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
5832 10:56:04.794067 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5833 10:56:04.794118 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5834 10:56:04.794168 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 10:56:04.794219 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 10:56:04.794270 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 10:56:04.794321 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 10:56:04.794371 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 10:56:04.794428 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5840 10:56:04.794479 0 15 28 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5841 10:56:04.794530 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 10:56:04.794585 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 10:56:04.794638 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 10:56:04.794688 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 10:56:04.794739 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 10:56:04.794790 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 10:56:04.794879 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5848 10:56:04.794930 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5849 10:56:04.795168 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 10:56:04.795226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 10:56:04.795306 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 10:56:04.795357 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 10:56:04.795409 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 10:56:04.795495 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 10:56:04.795548 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 10:56:04.795615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 10:56:04.795688 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 10:56:04.795740 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 10:56:04.795806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 10:56:04.795871 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 10:56:04.795927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 10:56:04.795979 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 10:56:04.796047 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5864 10:56:04.796112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5865 10:56:04.796163 Total UI for P1: 0, mck2ui 16
5866 10:56:04.796231 best dqsien dly found for B0: ( 1, 2, 24)
5867 10:56:04.796299 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 10:56:04.796353 Total UI for P1: 0, mck2ui 16
5869 10:56:04.796404 best dqsien dly found for B1: ( 1, 2, 28)
5870 10:56:04.796455 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5871 10:56:04.796506 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5872 10:56:04.796556
5873 10:56:04.796606 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 10:56:04.796657 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5875 10:56:04.796714 [Gating] SW calibration Done
5876 10:56:04.796765 ==
5877 10:56:04.796816 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 10:56:04.796867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 10:56:04.796918 ==
5880 10:56:04.796969 RX Vref Scan: 0
5881 10:56:04.797019
5882 10:56:04.797072 RX Vref 0 -> 0, step: 1
5883 10:56:04.797125
5884 10:56:04.797175 RX Delay -80 -> 252, step: 8
5885 10:56:04.797225 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5886 10:56:04.797275 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5887 10:56:04.797326 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5888 10:56:04.797377 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5889 10:56:04.797427 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5890 10:56:04.797477 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5891 10:56:04.797532 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5892 10:56:04.797584 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5893 10:56:04.797634 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5894 10:56:04.797685 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5895 10:56:04.797735 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5896 10:56:04.797786 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5897 10:56:04.797837 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5898 10:56:04.797887 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5899 10:56:04.797938 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5900 10:56:04.797993 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5901 10:56:04.798046 ==
5902 10:56:04.798096 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 10:56:04.798147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 10:56:04.798199 ==
5905 10:56:04.798249 DQS Delay:
5906 10:56:04.798299 DQS0 = 0, DQS1 = 0
5907 10:56:04.798350 DQM Delay:
5908 10:56:04.798407 DQM0 = 93, DQM1 = 87
5909 10:56:04.798458 DQ Delay:
5910 10:56:04.798509 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5911 10:56:04.798560 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5912 10:56:04.798616 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5913 10:56:04.798673 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5914 10:56:04.798725
5915 10:56:04.798775
5916 10:56:04.798825 ==
5917 10:56:04.798946 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 10:56:04.799029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 10:56:04.799110 ==
5920 10:56:04.799189
5921 10:56:04.799268
5922 10:56:04.799347 TX Vref Scan disable
5923 10:56:04.799429 == TX Byte 0 ==
5924 10:56:04.799511 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5925 10:56:04.799591 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5926 10:56:04.799671 == TX Byte 1 ==
5927 10:56:04.799751 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5928 10:56:04.799835 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5929 10:56:04.799915 ==
5930 10:56:04.799995 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 10:56:04.800077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 10:56:04.800158 ==
5933 10:56:04.800237
5934 10:56:04.800316
5935 10:56:04.800395 TX Vref Scan disable
5936 10:56:04.800474 == TX Byte 0 ==
5937 10:56:04.800557 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5938 10:56:04.800638 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5939 10:56:04.800710 == TX Byte 1 ==
5940 10:56:04.800762 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5941 10:56:04.800814 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5942 10:56:04.800866
5943 10:56:04.800917 [DATLAT]
5944 10:56:04.800967 Freq=933, CH1 RK1
5945 10:56:04.801018
5946 10:56:04.801072 DATLAT Default: 0xb
5947 10:56:04.801124 0, 0xFFFF, sum = 0
5948 10:56:04.801176 1, 0xFFFF, sum = 0
5949 10:56:04.801227 2, 0xFFFF, sum = 0
5950 10:56:04.801279 3, 0xFFFF, sum = 0
5951 10:56:04.801330 4, 0xFFFF, sum = 0
5952 10:56:04.801381 5, 0xFFFF, sum = 0
5953 10:56:04.801432 6, 0xFFFF, sum = 0
5954 10:56:04.801483 7, 0xFFFF, sum = 0
5955 10:56:04.801565 8, 0xFFFF, sum = 0
5956 10:56:04.801653 9, 0xFFFF, sum = 0
5957 10:56:04.801707 10, 0x0, sum = 1
5958 10:56:04.801759 11, 0x0, sum = 2
5959 10:56:04.801810 12, 0x0, sum = 3
5960 10:56:04.801862 13, 0x0, sum = 4
5961 10:56:04.801919 best_step = 11
5962 10:56:04.801971
5963 10:56:04.802022 ==
5964 10:56:04.802072 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 10:56:04.802123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 10:56:04.802174 ==
5967 10:56:04.802224 RX Vref Scan: 0
5968 10:56:04.802275
5969 10:56:04.802331 RX Vref 0 -> 0, step: 1
5970 10:56:04.802382
5971 10:56:04.802433 RX Delay -69 -> 252, step: 4
5972 10:56:04.802484 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5973 10:56:04.802539 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5974 10:56:04.802591 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5975 10:56:04.802642 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5976 10:56:04.802692 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5977 10:56:04.802742 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5978 10:56:04.802792 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5979 10:56:04.802899 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5980 10:56:04.802953 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5981 10:56:04.803005 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5982 10:56:04.803246 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5983 10:56:06.848247 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5984 10:56:06.848393 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5985 10:56:06.848458 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5986 10:56:06.848516 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5987 10:56:06.848572 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5988 10:56:06.848626 ==
5989 10:56:06.848681 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 10:56:06.848734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 10:56:06.848787 ==
5992 10:56:06.848840 DQS Delay:
5993 10:56:06.848892 DQS0 = 0, DQS1 = 0
5994 10:56:06.848944 DQM Delay:
5995 10:56:06.848994 DQM0 = 91, DQM1 = 91
5996 10:56:06.849045 DQ Delay:
5997 10:56:06.849096 DQ0 =94, DQ1 =86, DQ2 =80, DQ3 =88
5998 10:56:06.849147 DQ4 =88, DQ5 =102, DQ6 =106, DQ7 =88
5999 10:56:06.849198 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
6000 10:56:06.849249 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =98
6001 10:56:06.849300
6002 10:56:06.849350
6003 10:56:06.849401 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
6004 10:56:06.849452 CH1 RK1: MR19=505, MR18=B1E
6005 10:56:06.849503 CH1_RK1: MR19=0x505, MR18=0xB1E, DQSOSC=412, MR23=63, INC=63, DEC=42
6006 10:56:06.849555 [RxdqsGatingPostProcess] freq 933
6007 10:56:06.849606 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 10:56:06.849657 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 10:56:06.849708 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 10:56:06.849758 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 10:56:06.849809 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 10:56:06.849859 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 10:56:06.849909 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 10:56:06.849960 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 10:56:06.850027 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 10:56:06.850092 Pre-setting of DQS Precalculation
6017 10:56:06.850142 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 10:56:06.850193 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 10:56:06.850245 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 10:56:06.850296
6021 10:56:06.850346
6022 10:56:06.850395 [Calibration Summary] 1866 Mbps
6023 10:56:06.850445 CH 0, Rank 0
6024 10:56:06.850496 SW Impedance : PASS
6025 10:56:06.850547 DUTY Scan : NO K
6026 10:56:06.850597 ZQ Calibration : PASS
6027 10:56:06.850648 Jitter Meter : NO K
6028 10:56:06.850698 CBT Training : PASS
6029 10:56:06.850748 Write leveling : PASS
6030 10:56:06.850799 RX DQS gating : PASS
6031 10:56:06.850891 RX DQ/DQS(RDDQC) : PASS
6032 10:56:06.850944 TX DQ/DQS : PASS
6033 10:56:06.850995 RX DATLAT : PASS
6034 10:56:06.851046 RX DQ/DQS(Engine): PASS
6035 10:56:06.851096 TX OE : NO K
6036 10:56:06.851147 All Pass.
6037 10:56:06.851197
6038 10:56:06.851247 CH 0, Rank 1
6039 10:56:06.851298 SW Impedance : PASS
6040 10:56:06.851348 DUTY Scan : NO K
6041 10:56:06.851398 ZQ Calibration : PASS
6042 10:56:06.851449 Jitter Meter : NO K
6043 10:56:06.851500 CBT Training : PASS
6044 10:56:06.851550 Write leveling : PASS
6045 10:56:06.851600 RX DQS gating : PASS
6046 10:56:06.851651 RX DQ/DQS(RDDQC) : PASS
6047 10:56:06.851702 TX DQ/DQS : PASS
6048 10:56:06.851752 RX DATLAT : PASS
6049 10:56:06.851803 RX DQ/DQS(Engine): PASS
6050 10:56:06.851853 TX OE : NO K
6051 10:56:06.851922 All Pass.
6052 10:56:06.852004
6053 10:56:06.852068 CH 1, Rank 0
6054 10:56:06.852119 SW Impedance : PASS
6055 10:56:06.852169 DUTY Scan : NO K
6056 10:56:06.852220 ZQ Calibration : PASS
6057 10:56:06.852270 Jitter Meter : NO K
6058 10:56:06.852321 CBT Training : PASS
6059 10:56:06.852371 Write leveling : PASS
6060 10:56:06.852422 RX DQS gating : PASS
6061 10:56:06.852472 RX DQ/DQS(RDDQC) : PASS
6062 10:56:06.852523 TX DQ/DQS : PASS
6063 10:56:06.852573 RX DATLAT : PASS
6064 10:56:06.852623 RX DQ/DQS(Engine): PASS
6065 10:56:06.852674 TX OE : NO K
6066 10:56:06.852723 All Pass.
6067 10:56:06.852774
6068 10:56:06.852823 CH 1, Rank 1
6069 10:56:06.852874 SW Impedance : PASS
6070 10:56:06.852924 DUTY Scan : NO K
6071 10:56:06.852974 ZQ Calibration : PASS
6072 10:56:06.853025 Jitter Meter : NO K
6073 10:56:06.853076 CBT Training : PASS
6074 10:56:06.853127 Write leveling : PASS
6075 10:56:06.853177 RX DQS gating : PASS
6076 10:56:06.853227 RX DQ/DQS(RDDQC) : PASS
6077 10:56:06.853277 TX DQ/DQS : PASS
6078 10:56:06.853328 RX DATLAT : PASS
6079 10:56:06.853378 RX DQ/DQS(Engine): PASS
6080 10:56:06.853428 TX OE : NO K
6081 10:56:06.853478 All Pass.
6082 10:56:06.853529
6083 10:56:06.853578 DramC Write-DBI off
6084 10:56:06.853629 PER_BANK_REFRESH: Hybrid Mode
6085 10:56:06.853680 TX_TRACKING: ON
6086 10:56:06.853731 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 10:56:06.853783 [FAST_K] Save calibration result to emmc
6088 10:56:06.853833 dramc_set_vcore_voltage set vcore to 650000
6089 10:56:06.853884 Read voltage for 400, 6
6090 10:56:06.853934 Vio18 = 0
6091 10:56:06.854022 Vcore = 650000
6092 10:56:06.854089 Vdram = 0
6093 10:56:06.854141 Vddq = 0
6094 10:56:06.854192 Vmddr = 0
6095 10:56:06.854243 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 10:56:06.854296 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 10:56:06.854349 MEM_TYPE=3, freq_sel=20
6098 10:56:06.854400 sv_algorithm_assistance_LP4_800
6099 10:56:06.854452 ============ PULL DRAM RESETB DOWN ============
6100 10:56:06.854504 ========== PULL DRAM RESETB DOWN end =========
6101 10:56:06.854557 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 10:56:06.854609 ===================================
6103 10:56:06.854662 LPDDR4 DRAM CONFIGURATION
6104 10:56:06.854714 ===================================
6105 10:56:06.854766 EX_ROW_EN[0] = 0x0
6106 10:56:06.854817 EX_ROW_EN[1] = 0x0
6107 10:56:06.854908 LP4Y_EN = 0x0
6108 10:56:06.854961 WORK_FSP = 0x0
6109 10:56:06.855013 WL = 0x2
6110 10:56:06.855065 RL = 0x2
6111 10:56:06.855117 BL = 0x2
6112 10:56:06.855168 RPST = 0x0
6113 10:56:06.855220 RD_PRE = 0x0
6114 10:56:06.855272 WR_PRE = 0x1
6115 10:56:06.855324 WR_PST = 0x0
6116 10:56:06.855375 DBI_WR = 0x0
6117 10:56:06.855427 DBI_RD = 0x0
6118 10:56:06.855479 OTF = 0x1
6119 10:56:06.855532 ===================================
6120 10:56:06.855584 ===================================
6121 10:56:06.855637 ANA top config
6122 10:56:06.855688 ===================================
6123 10:56:06.855740 DLL_ASYNC_EN = 0
6124 10:56:06.855793 ALL_SLAVE_EN = 1
6125 10:56:06.855845 NEW_RANK_MODE = 1
6126 10:56:06.856102 DLL_IDLE_MODE = 1
6127 10:56:06.856181 LP45_APHY_COMB_EN = 1
6128 10:56:06.856236 TX_ODT_DIS = 1
6129 10:56:06.856321 NEW_8X_MODE = 1
6130 10:56:06.856406 ===================================
6131 10:56:06.856475 ===================================
6132 10:56:06.856544 data_rate = 800
6133 10:56:06.856628 CKR = 1
6134 10:56:06.856681 DQ_P2S_RATIO = 4
6135 10:56:06.856735 ===================================
6136 10:56:06.856789 CA_P2S_RATIO = 4
6137 10:56:06.856842 DQ_CA_OPEN = 0
6138 10:56:06.856895 DQ_SEMI_OPEN = 1
6139 10:56:06.856948 CA_SEMI_OPEN = 1
6140 10:56:06.857001 CA_FULL_RATE = 0
6141 10:56:06.857054 DQ_CKDIV4_EN = 0
6142 10:56:06.857107 CA_CKDIV4_EN = 1
6143 10:56:06.857160 CA_PREDIV_EN = 0
6144 10:56:06.857213 PH8_DLY = 0
6145 10:56:06.857266 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 10:56:06.857319 DQ_AAMCK_DIV = 0
6147 10:56:06.857371 CA_AAMCK_DIV = 0
6148 10:56:06.857424 CA_ADMCK_DIV = 4
6149 10:56:06.857477 DQ_TRACK_CA_EN = 0
6150 10:56:06.857530 CA_PICK = 800
6151 10:56:06.857583 CA_MCKIO = 400
6152 10:56:06.857636 MCKIO_SEMI = 400
6153 10:56:06.857689 PLL_FREQ = 3016
6154 10:56:06.857742 DQ_UI_PI_RATIO = 32
6155 10:56:06.857794 CA_UI_PI_RATIO = 32
6156 10:56:06.857847 ===================================
6157 10:56:06.857900 ===================================
6158 10:56:06.857953 memory_type:LPDDR4
6159 10:56:06.858010 GP_NUM : 10
6160 10:56:06.858065 SRAM_EN : 1
6161 10:56:06.858118 MD32_EN : 0
6162 10:56:06.858171 ===================================
6163 10:56:06.858224 [ANA_INIT] >>>>>>>>>>>>>>
6164 10:56:06.858278 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 10:56:06.858332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 10:56:06.858385 ===================================
6167 10:56:06.858439 data_rate = 800,PCW = 0X7400
6168 10:56:06.858492 ===================================
6169 10:56:06.858545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 10:56:06.858599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 10:56:06.858653 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 10:56:06.858708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 10:56:06.858762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 10:56:06.858816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 10:56:06.858879 [ANA_INIT] flow start
6176 10:56:06.858933 [ANA_INIT] PLL >>>>>>>>
6177 10:56:06.858986 [ANA_INIT] PLL <<<<<<<<
6178 10:56:06.859039 [ANA_INIT] MIDPI >>>>>>>>
6179 10:56:06.859093 [ANA_INIT] MIDPI <<<<<<<<
6180 10:56:06.859146 [ANA_INIT] DLL >>>>>>>>
6181 10:56:06.859199 [ANA_INIT] flow end
6182 10:56:06.859252 ============ LP4 DIFF to SE enter ============
6183 10:56:06.859307 ============ LP4 DIFF to SE exit ============
6184 10:56:06.859361 [ANA_INIT] <<<<<<<<<<<<<
6185 10:56:06.859414 [Flow] Enable top DCM control >>>>>
6186 10:56:06.859467 [Flow] Enable top DCM control <<<<<
6187 10:56:06.859520 Enable DLL master slave shuffle
6188 10:56:06.859573 ==============================================================
6189 10:56:06.859627 Gating Mode config
6190 10:56:06.859680 ==============================================================
6191 10:56:06.859734 Config description:
6192 10:56:06.859788 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 10:56:06.859842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 10:56:06.859896 SELPH_MODE 0: By rank 1: By Phase
6195 10:56:06.859950 ==============================================================
6196 10:56:06.860027 GAT_TRACK_EN = 0
6197 10:56:06.860083 RX_GATING_MODE = 2
6198 10:56:06.860137 RX_GATING_TRACK_MODE = 2
6199 10:56:06.860190 SELPH_MODE = 1
6200 10:56:06.860243 PICG_EARLY_EN = 1
6201 10:56:06.860296 VALID_LAT_VALUE = 1
6202 10:56:06.860350 ==============================================================
6203 10:56:06.860404 Enter into Gating configuration >>>>
6204 10:56:06.860457 Exit from Gating configuration <<<<
6205 10:56:06.860511 Enter into DVFS_PRE_config >>>>>
6206 10:56:06.860564 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 10:56:06.860619 Exit from DVFS_PRE_config <<<<<
6208 10:56:06.860673 Enter into PICG configuration >>>>
6209 10:56:06.860726 Exit from PICG configuration <<<<
6210 10:56:06.860778 [RX_INPUT] configuration >>>>>
6211 10:56:06.860832 [RX_INPUT] configuration <<<<<
6212 10:56:06.860885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 10:56:06.860938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 10:56:06.860991 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 10:56:06.861045 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 10:56:06.861099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 10:56:06.861152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 10:56:06.861205 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 10:56:06.861272 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 10:56:06.861340 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 10:56:06.861393 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 10:56:06.861463 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 10:56:06.861529 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 10:56:06.861582 ===================================
6225 10:56:06.861836 LPDDR4 DRAM CONFIGURATION
6226 10:56:06.861896 ===================================
6227 10:56:06.861968 EX_ROW_EN[0] = 0x0
6228 10:56:06.862039 EX_ROW_EN[1] = 0x0
6229 10:56:06.862123 LP4Y_EN = 0x0
6230 10:56:06.862191 WORK_FSP = 0x0
6231 10:56:06.862261 WL = 0x2
6232 10:56:06.862347 RL = 0x2
6233 10:56:06.862400 BL = 0x2
6234 10:56:06.862453 RPST = 0x0
6235 10:56:06.862506 RD_PRE = 0x0
6236 10:56:06.862559 WR_PRE = 0x1
6237 10:56:06.862612 WR_PST = 0x0
6238 10:56:06.862678 DBI_WR = 0x0
6239 10:56:06.862729 DBI_RD = 0x0
6240 10:56:06.862781 OTF = 0x1
6241 10:56:06.862857 ===================================
6242 10:56:06.862925 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 10:56:06.862994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 10:56:06.863062 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 10:56:06.863114 ===================================
6246 10:56:06.863166 LPDDR4 DRAM CONFIGURATION
6247 10:56:06.863248 ===================================
6248 10:56:06.863301 EX_ROW_EN[0] = 0x10
6249 10:56:06.863353 EX_ROW_EN[1] = 0x0
6250 10:56:06.863405 LP4Y_EN = 0x0
6251 10:56:06.863456 WORK_FSP = 0x0
6252 10:56:06.863509 WL = 0x2
6253 10:56:06.863561 RL = 0x2
6254 10:56:06.863613 BL = 0x2
6255 10:56:06.863665 RPST = 0x0
6256 10:56:06.863717 RD_PRE = 0x0
6257 10:56:06.863769 WR_PRE = 0x1
6258 10:56:06.863822 WR_PST = 0x0
6259 10:56:06.863873 DBI_WR = 0x0
6260 10:56:06.863925 DBI_RD = 0x0
6261 10:56:06.864004 OTF = 0x1
6262 10:56:06.864083 ===================================
6263 10:56:06.864137 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 10:56:06.864190 nWR fixed to 30
6265 10:56:06.864243 [ModeRegInit_LP4] CH0 RK0
6266 10:56:06.864295 [ModeRegInit_LP4] CH0 RK1
6267 10:56:06.864347 [ModeRegInit_LP4] CH1 RK0
6268 10:56:06.864399 [ModeRegInit_LP4] CH1 RK1
6269 10:56:06.864451 match AC timing 19
6270 10:56:06.864503 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 10:56:06.864556 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 10:56:06.864609 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 10:56:06.864662 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 10:56:06.864714 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 10:56:06.864767 ==
6276 10:56:06.864819 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 10:56:06.864871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 10:56:06.864925 ==
6279 10:56:06.865007 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 10:56:06.865060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6281 10:56:06.865113 [CA 0] Center 36 (8~64) winsize 57
6282 10:56:06.865165 [CA 1] Center 36 (8~64) winsize 57
6283 10:56:06.865217 [CA 2] Center 36 (8~64) winsize 57
6284 10:56:06.865269 [CA 3] Center 36 (8~64) winsize 57
6285 10:56:06.865321 [CA 4] Center 36 (8~64) winsize 57
6286 10:56:06.865372 [CA 5] Center 36 (8~64) winsize 57
6287 10:56:06.865424
6288 10:56:06.865476 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6289 10:56:06.865527
6290 10:56:06.865579 [CATrainingPosCal] consider 1 rank data
6291 10:56:06.865632 u2DelayCellTimex100 = 270/100 ps
6292 10:56:06.865684 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:56:06.865736 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 10:56:06.865789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 10:56:06.865841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 10:56:06.865893 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 10:56:06.865945 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 10:56:06.866000
6299 10:56:06.866053 CA PerBit enable=1, Macro0, CA PI delay=36
6300 10:56:06.866105
6301 10:56:06.866158 [CBTSetCACLKResult] CA Dly = 36
6302 10:56:06.866210 CS Dly: 1 (0~32)
6303 10:56:06.866262 ==
6304 10:56:06.866314 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 10:56:06.866367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 10:56:06.866420 ==
6307 10:56:06.866472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 10:56:06.866525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6309 10:56:06.866577 [CA 0] Center 36 (8~64) winsize 57
6310 10:56:06.866630 [CA 1] Center 36 (8~64) winsize 57
6311 10:56:06.866682 [CA 2] Center 36 (8~64) winsize 57
6312 10:56:06.866734 [CA 3] Center 36 (8~64) winsize 57
6313 10:56:06.866787 [CA 4] Center 36 (8~64) winsize 57
6314 10:56:06.866863 [CA 5] Center 36 (8~64) winsize 57
6315 10:56:06.866931
6316 10:56:06.866982 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6317 10:56:06.867034
6318 10:56:06.867086 [CATrainingPosCal] consider 2 rank data
6319 10:56:06.867138 u2DelayCellTimex100 = 270/100 ps
6320 10:56:06.867190 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 10:56:06.867242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 10:56:06.867294 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 10:56:06.867347 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 10:56:06.867399 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 10:56:06.867451 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 10:56:06.867503
6327 10:56:06.867555 CA PerBit enable=1, Macro0, CA PI delay=36
6328 10:56:06.867607
6329 10:56:06.867659 [CBTSetCACLKResult] CA Dly = 36
6330 10:56:06.867711 CS Dly: 1 (0~32)
6331 10:56:06.867763
6332 10:56:06.867844 ----->DramcWriteLeveling(PI) begin...
6333 10:56:06.867898 ==
6334 10:56:06.867981 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 10:56:06.868065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 10:56:06.868156 ==
6337 10:56:06.868240 Write leveling (Byte 0): 40 => 8
6338 10:56:06.868322 Write leveling (Byte 1): 40 => 8
6339 10:56:06.868394 DramcWriteLeveling(PI) end<-----
6340 10:56:06.868449
6341 10:56:06.868502 ==
6342 10:56:06.868555 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 10:56:06.868608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 10:56:06.868661 ==
6345 10:56:06.868714 [Gating] SW mode calibration
6346 10:56:06.868767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 10:56:06.868820 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 10:56:06.868873 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 10:56:06.868927 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 10:56:06.868980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 10:56:06.869033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 10:56:06.869085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 10:56:06.869138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 10:56:06.869374 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 10:56:06.869487 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 10:56:06.869568 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 10:56:06.869623 Total UI for P1: 0, mck2ui 16
6358 10:56:06.869677 best dqsien dly found for B0: ( 0, 14, 24)
6359 10:56:06.869731 Total UI for P1: 0, mck2ui 16
6360 10:56:06.869784 best dqsien dly found for B1: ( 0, 14, 24)
6361 10:56:06.869836 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 10:56:06.869888 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 10:56:06.869940
6364 10:56:06.870005 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 10:56:06.870056 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 10:56:06.870106 [Gating] SW calibration Done
6367 10:56:06.870157 ==
6368 10:56:06.870208 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 10:56:06.870258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 10:56:06.870310 ==
6371 10:56:06.870360 RX Vref Scan: 0
6372 10:56:06.870410
6373 10:56:06.870460 RX Vref 0 -> 0, step: 1
6374 10:56:06.870511
6375 10:56:06.870561 RX Delay -410 -> 252, step: 16
6376 10:56:06.870611 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6377 10:56:06.870682 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6378 10:56:06.870734 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6379 10:56:06.870786 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6380 10:56:06.870846 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6381 10:56:06.870913 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6382 10:56:06.870964 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6383 10:56:06.871014 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6384 10:56:06.871065 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6385 10:56:06.871116 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6386 10:56:06.871166 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6387 10:56:06.871217 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6388 10:56:06.871268 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6389 10:56:06.871318 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6390 10:56:06.871369 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6391 10:56:06.871419 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6392 10:56:06.871486 ==
6393 10:56:06.871550 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:56:06.871601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:56:06.871652 ==
6396 10:56:06.871703 DQS Delay:
6397 10:56:06.871753 DQS0 = 59, DQS1 = 59
6398 10:56:06.871803 DQM Delay:
6399 10:56:06.871855 DQM0 = 18, DQM1 = 10
6400 10:56:06.871905 DQ Delay:
6401 10:56:06.871955 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6402 10:56:06.872006 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6403 10:56:06.872057 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6404 10:56:06.872107 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6405 10:56:06.872158
6406 10:56:06.872208
6407 10:56:06.872258 ==
6408 10:56:06.872308 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 10:56:06.872359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 10:56:06.872409 ==
6411 10:56:06.872460
6412 10:56:06.872510
6413 10:56:06.872561 TX Vref Scan disable
6414 10:56:06.872612 == TX Byte 0 ==
6415 10:56:06.872662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 10:56:06.872713 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 10:56:06.872764 == TX Byte 1 ==
6418 10:56:06.872815 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 10:56:06.872866 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 10:56:06.872917 ==
6421 10:56:06.872967 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 10:56:06.873018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:56:06.873069 ==
6424 10:56:06.873119
6425 10:56:06.873169
6426 10:56:06.873219 TX Vref Scan disable
6427 10:56:06.873270 == TX Byte 0 ==
6428 10:56:06.873320 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 10:56:06.873371 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 10:56:06.873421 == TX Byte 1 ==
6431 10:56:06.873472 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 10:56:06.873523 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 10:56:06.873573
6434 10:56:06.873623 [DATLAT]
6435 10:56:06.873673 Freq=400, CH0 RK0
6436 10:56:06.873723
6437 10:56:06.873773 DATLAT Default: 0xf
6438 10:56:06.873824 0, 0xFFFF, sum = 0
6439 10:56:06.873876 1, 0xFFFF, sum = 0
6440 10:56:06.873927 2, 0xFFFF, sum = 0
6441 10:56:06.873979 3, 0xFFFF, sum = 0
6442 10:56:06.874031 4, 0xFFFF, sum = 0
6443 10:56:06.874082 5, 0xFFFF, sum = 0
6444 10:56:06.874134 6, 0xFFFF, sum = 0
6445 10:56:06.874200 7, 0xFFFF, sum = 0
6446 10:56:06.874257 8, 0xFFFF, sum = 0
6447 10:56:06.874309 9, 0xFFFF, sum = 0
6448 10:56:06.874361 10, 0xFFFF, sum = 0
6449 10:56:06.874412 11, 0xFFFF, sum = 0
6450 10:56:06.874493 12, 0xFFFF, sum = 0
6451 10:56:06.874545 13, 0x0, sum = 1
6452 10:56:06.874613 14, 0x0, sum = 2
6453 10:56:06.874679 15, 0x0, sum = 3
6454 10:56:06.874730 16, 0x0, sum = 4
6455 10:56:06.874782 best_step = 14
6456 10:56:06.874856
6457 10:56:06.874922 ==
6458 10:56:06.874972 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 10:56:06.875023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 10:56:06.875073 ==
6461 10:56:06.875124 RX Vref Scan: 1
6462 10:56:06.875174
6463 10:56:06.875224 RX Vref 0 -> 0, step: 1
6464 10:56:06.875274
6465 10:56:06.875324 RX Delay -359 -> 252, step: 8
6466 10:56:06.875375
6467 10:56:06.875425 Set Vref, RX VrefLevel [Byte0]: 62
6468 10:56:06.875476 [Byte1]: 47
6469 10:56:06.875527
6470 10:56:06.875578 Final RX Vref Byte 0 = 62 to rank0
6471 10:56:06.875629 Final RX Vref Byte 1 = 47 to rank0
6472 10:56:06.875680 Final RX Vref Byte 0 = 62 to rank1
6473 10:56:06.875730 Final RX Vref Byte 1 = 47 to rank1==
6474 10:56:06.875781 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 10:56:06.875831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 10:56:06.875882 ==
6477 10:56:06.875932 DQS Delay:
6478 10:56:06.875982 DQS0 = 60, DQS1 = 68
6479 10:56:06.876033 DQM Delay:
6480 10:56:06.876083 DQM0 = 15, DQM1 = 13
6481 10:56:06.876133 DQ Delay:
6482 10:56:06.876183 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =16
6483 10:56:06.876234 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6484 10:56:06.876284 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6485 10:56:06.876334 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6486 10:56:06.876385
6487 10:56:06.876436
6488 10:56:06.876486 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6489 10:56:06.876537 CH0 RK0: MR19=C0C, MR18=8281
6490 10:56:06.876603 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6491 10:56:06.876673 ==
6492 10:56:06.876723 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 10:56:06.876774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 10:56:06.876824 ==
6495 10:56:06.876874 [Gating] SW mode calibration
6496 10:56:06.876925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 10:56:06.876976 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 10:56:06.877028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 10:56:06.877263 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 10:56:06.877360 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 10:56:06.877412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 10:56:06.877463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 10:56:06.877514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 10:56:06.877565 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 10:56:06.877615 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 10:56:06.877665 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 10:56:06.877716 Total UI for P1: 0, mck2ui 16
6508 10:56:06.877767 best dqsien dly found for B0: ( 0, 14, 24)
6509 10:56:06.877818 Total UI for P1: 0, mck2ui 16
6510 10:56:06.877868 best dqsien dly found for B1: ( 0, 14, 24)
6511 10:56:06.877918 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 10:56:06.877969 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 10:56:06.878049
6514 10:56:06.878099 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 10:56:06.878150 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 10:56:06.878200 [Gating] SW calibration Done
6517 10:56:06.878250 ==
6518 10:56:06.878301 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 10:56:06.878351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 10:56:06.878401 ==
6521 10:56:06.878452 RX Vref Scan: 0
6522 10:56:06.878502
6523 10:56:06.878552 RX Vref 0 -> 0, step: 1
6524 10:56:06.878604
6525 10:56:06.878654 RX Delay -410 -> 252, step: 16
6526 10:56:06.878704 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6527 10:56:06.878755 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6528 10:56:06.878805 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6529 10:56:06.878896 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6530 10:56:06.878948 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6531 10:56:06.878999 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6532 10:56:06.879050 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6533 10:56:06.879100 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6534 10:56:06.879151 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6535 10:56:06.879201 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6536 10:56:06.879252 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6537 10:56:06.879302 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6538 10:56:06.879352 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6539 10:56:06.879402 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6540 10:56:06.879453 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6541 10:56:06.879503 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6542 10:56:06.879553 ==
6543 10:56:06.879604 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 10:56:06.879654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 10:56:06.879705 ==
6546 10:56:06.879756 DQS Delay:
6547 10:56:06.879806 DQS0 = 59, DQS1 = 59
6548 10:56:06.879857 DQM Delay:
6549 10:56:06.879907 DQM0 = 17, DQM1 = 10
6550 10:56:06.879957 DQ Delay:
6551 10:56:06.880008 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6552 10:56:06.880058 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6553 10:56:06.880109 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6554 10:56:06.880159 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6555 10:56:06.880209
6556 10:56:06.880259
6557 10:56:06.880309 ==
6558 10:56:06.880359 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 10:56:06.880409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 10:56:06.880461 ==
6561 10:56:06.880511
6562 10:56:06.880561
6563 10:56:06.880611 TX Vref Scan disable
6564 10:56:06.880663 == TX Byte 0 ==
6565 10:56:06.880714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6566 10:56:06.880765 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6567 10:56:06.880816 == TX Byte 1 ==
6568 10:56:06.880866 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6569 10:56:06.880916 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6570 10:56:06.880997 ==
6571 10:56:06.881047 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 10:56:06.881098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 10:56:06.881149 ==
6574 10:56:06.881205
6575 10:56:06.881260
6576 10:56:06.881310 TX Vref Scan disable
6577 10:56:06.881361 == TX Byte 0 ==
6578 10:56:06.881411 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6579 10:56:06.881462 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6580 10:56:06.881513 == TX Byte 1 ==
6581 10:56:06.881563 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6582 10:56:06.881614 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6583 10:56:06.881665
6584 10:56:06.881715 [DATLAT]
6585 10:56:06.881765 Freq=400, CH0 RK1
6586 10:56:06.881816
6587 10:56:06.881865 DATLAT Default: 0xe
6588 10:56:06.881916 0, 0xFFFF, sum = 0
6589 10:56:06.881968 1, 0xFFFF, sum = 0
6590 10:56:06.882019 2, 0xFFFF, sum = 0
6591 10:56:06.882073 3, 0xFFFF, sum = 0
6592 10:56:06.882132 4, 0xFFFF, sum = 0
6593 10:56:06.882184 5, 0xFFFF, sum = 0
6594 10:56:06.882236 6, 0xFFFF, sum = 0
6595 10:56:06.882287 7, 0xFFFF, sum = 0
6596 10:56:06.882339 8, 0xFFFF, sum = 0
6597 10:56:06.882389 9, 0xFFFF, sum = 0
6598 10:56:06.882441 10, 0xFFFF, sum = 0
6599 10:56:06.882493 11, 0xFFFF, sum = 0
6600 10:56:06.882544 12, 0xFFFF, sum = 0
6601 10:56:06.882595 13, 0x0, sum = 1
6602 10:56:06.882647 14, 0x0, sum = 2
6603 10:56:06.882698 15, 0x0, sum = 3
6604 10:56:06.882749 16, 0x0, sum = 4
6605 10:56:06.882799 best_step = 14
6606 10:56:06.882891
6607 10:56:06.882941 ==
6608 10:56:06.882993 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 10:56:06.883043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 10:56:06.883095 ==
6611 10:56:06.883145 RX Vref Scan: 0
6612 10:56:06.883196
6613 10:56:06.883246 RX Vref 0 -> 0, step: 1
6614 10:56:06.883297
6615 10:56:06.883347 RX Delay -359 -> 252, step: 8
6616 10:56:06.883398 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6617 10:56:06.883448 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6618 10:56:06.883499 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6619 10:56:06.883549 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6620 10:56:06.883600 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6621 10:56:06.883651 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6622 10:56:06.883701 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6623 10:56:06.883752 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6624 10:56:06.883802 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6625 10:56:06.883852 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6626 10:56:06.883903 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6627 10:56:06.883953 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6628 10:56:06.884004 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6629 10:56:06.884054 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6630 10:56:06.884105 iDelay=217, Bit 14, Center -44 (-287 ~ 200) 488
6631 10:56:06.884155 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6632 10:56:06.884206 ==
6633 10:56:06.884257 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 10:56:06.884491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 10:56:06.884548 ==
6636 10:56:06.884600 DQS Delay:
6637 10:56:06.884689 DQS0 = 60, DQS1 = 68
6638 10:56:06.884740 DQM Delay:
6639 10:56:06.884832 DQM0 = 12, DQM1 = 13
6640 10:56:06.884923 DQ Delay:
6641 10:56:06.884975 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6642 10:56:06.885025 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6643 10:56:06.885076 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6644 10:56:06.885127 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6645 10:56:06.885177
6646 10:56:06.885227
6647 10:56:06.885277 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6648 10:56:06.885330 CH0 RK1: MR19=C0C, MR18=C67C
6649 10:56:06.885381 CH0_RK1: MR19=0xC0C, MR18=0xC67C, DQSOSC=385, MR23=63, INC=398, DEC=265
6650 10:56:06.885432 [RxdqsGatingPostProcess] freq 400
6651 10:56:06.885482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 10:56:06.885533 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 10:56:06.885584 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 10:56:06.885634 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 10:56:06.885684 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 10:56:06.885735 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 10:56:06.885785 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 10:56:06.885836 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 10:56:06.885886 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 10:56:06.885936 Pre-setting of DQS Precalculation
6661 10:56:06.885987 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 10:56:06.886038 ==
6663 10:56:06.886089 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 10:56:06.886139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 10:56:06.886191 ==
6666 10:56:06.886242 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 10:56:06.886293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6668 10:56:06.886344 [CA 0] Center 36 (8~64) winsize 57
6669 10:56:06.886394 [CA 1] Center 36 (8~64) winsize 57
6670 10:56:06.886444 [CA 2] Center 36 (8~64) winsize 57
6671 10:56:06.886494 [CA 3] Center 36 (8~64) winsize 57
6672 10:56:06.886545 [CA 4] Center 36 (8~64) winsize 57
6673 10:56:06.886595 [CA 5] Center 36 (8~64) winsize 57
6674 10:56:06.886646
6675 10:56:06.886696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6676 10:56:06.886746
6677 10:56:06.886796 [CATrainingPosCal] consider 1 rank data
6678 10:56:06.886896 u2DelayCellTimex100 = 270/100 ps
6679 10:56:06.886962 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:56:06.887013 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 10:56:06.887063 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 10:56:06.887114 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 10:56:06.887164 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 10:56:06.887215 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 10:56:06.887265
6686 10:56:06.887316 CA PerBit enable=1, Macro0, CA PI delay=36
6687 10:56:06.887366
6688 10:56:06.887416 [CBTSetCACLKResult] CA Dly = 36
6689 10:56:06.887467 CS Dly: 1 (0~32)
6690 10:56:06.887517 ==
6691 10:56:06.887567 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 10:56:06.887618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 10:56:06.887669 ==
6694 10:56:06.887720 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 10:56:06.887771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6696 10:56:06.887822 [CA 0] Center 36 (8~64) winsize 57
6697 10:56:06.887873 [CA 1] Center 36 (8~64) winsize 57
6698 10:56:06.887923 [CA 2] Center 36 (8~64) winsize 57
6699 10:56:06.887974 [CA 3] Center 36 (8~64) winsize 57
6700 10:56:06.888024 [CA 4] Center 36 (8~64) winsize 57
6701 10:56:06.888075 [CA 5] Center 36 (8~64) winsize 57
6702 10:56:06.888125
6703 10:56:06.888175 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6704 10:56:06.888226
6705 10:56:06.888277 [CATrainingPosCal] consider 2 rank data
6706 10:56:06.888327 u2DelayCellTimex100 = 270/100 ps
6707 10:56:06.888378 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 10:56:06.888428 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 10:56:06.888479 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 10:56:06.888529 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 10:56:06.888579 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 10:56:06.888630 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 10:56:06.888680
6714 10:56:06.888730 CA PerBit enable=1, Macro0, CA PI delay=36
6715 10:56:06.888780
6716 10:56:06.888830 [CBTSetCACLKResult] CA Dly = 36
6717 10:56:06.888899 CS Dly: 1 (0~32)
6718 10:56:06.888963
6719 10:56:06.889013 ----->DramcWriteLeveling(PI) begin...
6720 10:56:06.889065 ==
6721 10:56:06.889116 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 10:56:06.889167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 10:56:06.889218 ==
6724 10:56:06.889269 Write leveling (Byte 0): 40 => 8
6725 10:56:06.889319 Write leveling (Byte 1): 40 => 8
6726 10:56:06.889370 DramcWriteLeveling(PI) end<-----
6727 10:56:06.889421
6728 10:56:06.889471 ==
6729 10:56:06.889521 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 10:56:06.889572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 10:56:06.889623 ==
6732 10:56:06.889674 [Gating] SW mode calibration
6733 10:56:06.889724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 10:56:06.889775 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 10:56:06.889827 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 10:56:06.889878 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 10:56:06.889929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 10:56:06.889980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 10:56:06.890031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 10:56:06.890081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 10:56:06.890132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 10:56:06.890183 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 10:56:06.890234 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 10:56:06.890285 Total UI for P1: 0, mck2ui 16
6745 10:56:06.890336 best dqsien dly found for B0: ( 0, 14, 24)
6746 10:56:06.890387 Total UI for P1: 0, mck2ui 16
6747 10:56:06.890438 best dqsien dly found for B1: ( 0, 14, 24)
6748 10:56:06.890489 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 10:56:06.890539 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 10:56:06.890589
6751 10:56:06.890640 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 10:56:06.890691 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 10:56:06.890930 [Gating] SW calibration Done
6754 10:56:06.891039 ==
6755 10:56:06.891167 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 10:56:06.891235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 10:56:06.891287 ==
6758 10:56:06.891338 RX Vref Scan: 0
6759 10:56:06.891389
6760 10:56:06.891440 RX Vref 0 -> 0, step: 1
6761 10:56:06.891491
6762 10:56:06.891541 RX Delay -410 -> 252, step: 16
6763 10:56:06.891592 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6764 10:56:06.891644 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6765 10:56:06.891695 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6766 10:56:06.891746 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6767 10:56:06.891797 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6768 10:56:06.891848 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6769 10:56:06.891898 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6770 10:56:06.891949 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6771 10:56:06.892000 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6772 10:56:06.892051 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6773 10:56:06.892101 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6774 10:56:06.892152 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6775 10:56:06.892202 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6776 10:56:06.892253 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6777 10:56:06.892303 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6778 10:56:06.892354 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6779 10:56:06.892404 ==
6780 10:56:06.892454 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:56:06.892505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:56:06.892556 ==
6783 10:56:06.892606 DQS Delay:
6784 10:56:06.892657 DQS0 = 51, DQS1 = 67
6785 10:56:06.892707 DQM Delay:
6786 10:56:06.892758 DQM0 = 12, DQM1 = 17
6787 10:56:06.892808 DQ Delay:
6788 10:56:06.892859 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6789 10:56:06.892910 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6790 10:56:06.892960 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6791 10:56:06.893011 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6792 10:56:06.893061
6793 10:56:06.893112
6794 10:56:06.893162 ==
6795 10:56:06.893212 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 10:56:06.893262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 10:56:06.893313 ==
6798 10:56:06.893363
6799 10:56:06.893413
6800 10:56:06.893463 TX Vref Scan disable
6801 10:56:06.893514 == TX Byte 0 ==
6802 10:56:06.893564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 10:56:06.893616 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 10:56:06.893667 == TX Byte 1 ==
6805 10:56:06.893718 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 10:56:06.893769 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 10:56:06.893820 ==
6808 10:56:06.893871 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 10:56:06.893921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:56:06.893972 ==
6811 10:56:06.894023
6812 10:56:06.894073
6813 10:56:06.894123 TX Vref Scan disable
6814 10:56:06.894173 == TX Byte 0 ==
6815 10:56:06.894224 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 10:56:06.894274 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 10:56:06.894325 == TX Byte 1 ==
6818 10:56:06.894375 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 10:56:06.894425 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 10:56:06.894477
6821 10:56:06.894527 [DATLAT]
6822 10:56:06.894594 Freq=400, CH1 RK0
6823 10:56:06.894658
6824 10:56:06.894708 DATLAT Default: 0xf
6825 10:56:06.894758 0, 0xFFFF, sum = 0
6826 10:56:06.894810 1, 0xFFFF, sum = 0
6827 10:56:06.894916 2, 0xFFFF, sum = 0
6828 10:56:06.894999 3, 0xFFFF, sum = 0
6829 10:56:06.895064 4, 0xFFFF, sum = 0
6830 10:56:06.895115 5, 0xFFFF, sum = 0
6831 10:56:06.895167 6, 0xFFFF, sum = 0
6832 10:56:06.895217 7, 0xFFFF, sum = 0
6833 10:56:06.895268 8, 0xFFFF, sum = 0
6834 10:56:06.895319 9, 0xFFFF, sum = 0
6835 10:56:06.895370 10, 0xFFFF, sum = 0
6836 10:56:06.895422 11, 0xFFFF, sum = 0
6837 10:56:06.895473 12, 0xFFFF, sum = 0
6838 10:56:06.895524 13, 0x0, sum = 1
6839 10:56:06.895575 14, 0x0, sum = 2
6840 10:56:06.895626 15, 0x0, sum = 3
6841 10:56:06.895678 16, 0x0, sum = 4
6842 10:56:06.895729 best_step = 14
6843 10:56:06.895779
6844 10:56:06.895830 ==
6845 10:56:06.895880 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 10:56:06.895931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 10:56:06.895982 ==
6848 10:56:06.896033 RX Vref Scan: 1
6849 10:56:06.896084
6850 10:56:06.896134 RX Vref 0 -> 0, step: 1
6851 10:56:06.896184
6852 10:56:06.896234 RX Delay -375 -> 252, step: 8
6853 10:56:06.896284
6854 10:56:06.896335 Set Vref, RX VrefLevel [Byte0]: 58
6855 10:56:06.896421 [Byte1]: 48
6856 10:56:06.896472
6857 10:56:06.896522 Final RX Vref Byte 0 = 58 to rank0
6858 10:56:06.896572 Final RX Vref Byte 1 = 48 to rank0
6859 10:56:06.896623 Final RX Vref Byte 0 = 58 to rank1
6860 10:56:06.896674 Final RX Vref Byte 1 = 48 to rank1==
6861 10:56:06.896725 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 10:56:06.896775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 10:56:06.896826 ==
6864 10:56:06.896876 DQS Delay:
6865 10:56:06.896926 DQS0 = 56, DQS1 = 68
6866 10:56:06.896976 DQM Delay:
6867 10:56:06.897025 DQM0 = 12, DQM1 = 14
6868 10:56:06.897076 DQ Delay:
6869 10:56:06.897126 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6870 10:56:06.897177 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6871 10:56:06.897227 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6872 10:56:06.897277 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6873 10:56:06.897328
6874 10:56:06.897378
6875 10:56:06.897428 [DQSOSCAuto] RK0, (LSB)MR18= 0x586b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6876 10:56:06.897479 CH1 RK0: MR19=C0C, MR18=586B
6877 10:56:06.897531 CH1_RK0: MR19=0xC0C, MR18=0x586B, DQSOSC=396, MR23=63, INC=376, DEC=251
6878 10:56:06.897582 ==
6879 10:56:06.897632 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 10:56:06.897683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 10:56:06.897766 ==
6882 10:56:06.897817 [Gating] SW mode calibration
6883 10:56:06.897867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 10:56:06.897919 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 10:56:06.897970 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 10:56:06.898021 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 10:56:06.898072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 10:56:06.898123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 10:56:06.898174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 10:56:06.898225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 10:56:06.898276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 10:56:06.898327 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 10:56:06.898378 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 10:56:06.898428 Total UI for P1: 0, mck2ui 16
6895 10:56:06.898479 best dqsien dly found for B0: ( 0, 14, 24)
6896 10:56:06.898717 Total UI for P1: 0, mck2ui 16
6897 10:56:06.898793 best dqsien dly found for B1: ( 0, 14, 24)
6898 10:56:06.898868 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 10:56:06.898921 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 10:56:06.898972
6901 10:56:06.899023 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 10:56:06.899074 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 10:56:06.899125 [Gating] SW calibration Done
6904 10:56:06.899206 ==
6905 10:56:06.899257 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 10:56:06.899308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 10:56:06.899360 ==
6908 10:56:06.899410 RX Vref Scan: 0
6909 10:56:06.899461
6910 10:56:06.899511 RX Vref 0 -> 0, step: 1
6911 10:56:06.899561
6912 10:56:06.899611 RX Delay -410 -> 252, step: 16
6913 10:56:06.899662 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6914 10:56:06.899712 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6915 10:56:06.899763 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6916 10:56:06.899814 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6917 10:56:06.899864 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6918 10:56:06.899914 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6919 10:56:06.899965 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6920 10:56:06.900016 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6921 10:56:06.900066 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6922 10:56:06.900116 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6923 10:56:06.900167 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6924 10:56:06.900218 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6925 10:56:06.900270 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6926 10:56:06.900320 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6927 10:56:06.900370 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6928 10:56:06.900421 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6929 10:56:06.900471 ==
6930 10:56:06.900521 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 10:56:06.900572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 10:56:06.900622 ==
6933 10:56:06.900673 DQS Delay:
6934 10:56:06.900723 DQS0 = 59, DQS1 = 59
6935 10:56:06.900773 DQM Delay:
6936 10:56:06.900823 DQM0 = 19, DQM1 = 12
6937 10:56:06.900873 DQ Delay:
6938 10:56:06.900923 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6939 10:56:06.900973 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6940 10:56:06.901024 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6941 10:56:06.901075 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6942 10:56:06.901125
6943 10:56:06.901175
6944 10:56:06.901225 ==
6945 10:56:06.901275 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 10:56:06.901325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 10:56:06.901376 ==
6948 10:56:06.901426
6949 10:56:06.901476
6950 10:56:06.901526 TX Vref Scan disable
6951 10:56:06.901576 == TX Byte 0 ==
6952 10:56:06.901626 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6953 10:56:06.901677 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6954 10:56:06.901728 == TX Byte 1 ==
6955 10:56:06.901778 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6956 10:56:06.901828 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6957 10:56:06.901879 ==
6958 10:56:06.901929 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 10:56:06.901980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 10:56:06.902030 ==
6961 10:56:06.902080
6962 10:56:06.902130
6963 10:56:06.902179 TX Vref Scan disable
6964 10:56:06.902230 == TX Byte 0 ==
6965 10:56:06.902280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6966 10:56:06.902330 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6967 10:56:06.902381 == TX Byte 1 ==
6968 10:56:06.902432 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6969 10:56:06.902482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6970 10:56:06.902533
6971 10:56:06.902584 [DATLAT]
6972 10:56:06.902634 Freq=400, CH1 RK1
6973 10:56:06.902684
6974 10:56:06.902734 DATLAT Default: 0xe
6975 10:56:06.902784 0, 0xFFFF, sum = 0
6976 10:56:06.902840 1, 0xFFFF, sum = 0
6977 10:56:06.902924 2, 0xFFFF, sum = 0
6978 10:56:06.902975 3, 0xFFFF, sum = 0
6979 10:56:06.903026 4, 0xFFFF, sum = 0
6980 10:56:06.903077 5, 0xFFFF, sum = 0
6981 10:56:06.903128 6, 0xFFFF, sum = 0
6982 10:56:06.903179 7, 0xFFFF, sum = 0
6983 10:56:06.903230 8, 0xFFFF, sum = 0
6984 10:56:06.903281 9, 0xFFFF, sum = 0
6985 10:56:06.903332 10, 0xFFFF, sum = 0
6986 10:56:06.903384 11, 0xFFFF, sum = 0
6987 10:56:06.903435 12, 0xFFFF, sum = 0
6988 10:56:06.903486 13, 0x0, sum = 1
6989 10:56:06.903537 14, 0x0, sum = 2
6990 10:56:06.903588 15, 0x0, sum = 3
6991 10:56:06.903640 16, 0x0, sum = 4
6992 10:56:06.903690 best_step = 14
6993 10:56:06.903740
6994 10:56:06.903790 ==
6995 10:56:06.903841 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 10:56:06.903891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 10:56:06.903943 ==
6998 10:56:06.903993 RX Vref Scan: 0
6999 10:56:06.904044
7000 10:56:06.904094 RX Vref 0 -> 0, step: 1
7001 10:56:06.904144
7002 10:56:06.904194 RX Delay -359 -> 252, step: 8
7003 10:56:06.904244 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7004 10:56:06.904295 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7005 10:56:06.904346 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7006 10:56:06.904421 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7007 10:56:06.904485 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7008 10:56:06.904536 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7009 10:56:06.904586 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7010 10:56:07.250423 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
7011 10:56:07.250565 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7012 10:56:07.250630 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
7013 10:56:07.250689 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7014 10:56:07.250746 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7015 10:56:07.250802 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7016 10:56:07.250879 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7017 10:56:07.250947 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7018 10:56:07.251001 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7019 10:56:07.251053 ==
7020 10:56:07.251106 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 10:56:07.251159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 10:56:07.251212 ==
7023 10:56:07.251264 DQS Delay:
7024 10:56:07.251316 DQS0 = 60, DQS1 = 64
7025 10:56:07.251367 DQM Delay:
7026 10:56:07.251418 DQM0 = 13, DQM1 = 11
7027 10:56:07.251469 DQ Delay:
7028 10:56:07.251520 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7029 10:56:07.251572 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7030 10:56:07.251623 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7031 10:56:07.251674 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7032 10:56:07.251726
7033 10:56:07.251776
7034 10:56:07.251828 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7035 10:56:07.251880 CH1 RK1: MR19=C0C, MR18=76A6
7036 10:56:07.251931 CH1_RK1: MR19=0xC0C, MR18=0x76A6, DQSOSC=389, MR23=63, INC=390, DEC=260
7037 10:56:07.252180 [RxdqsGatingPostProcess] freq 400
7038 10:56:07.252239 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 10:56:07.252308 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 10:56:07.252362 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 10:56:07.252414 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 10:56:07.252467 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 10:56:07.252519 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 10:56:07.252571 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 10:56:07.252623 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 10:56:07.252674 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 10:56:07.252738 Pre-setting of DQS Precalculation
7048 10:56:07.252789 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 10:56:07.252840 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 10:56:07.252892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 10:56:07.252944
7052 10:56:07.252995
7053 10:56:07.253045 [Calibration Summary] 800 Mbps
7054 10:56:07.253096 CH 0, Rank 0
7055 10:56:07.253147 SW Impedance : PASS
7056 10:56:07.253197 DUTY Scan : NO K
7057 10:56:07.253248 ZQ Calibration : PASS
7058 10:56:07.253299 Jitter Meter : NO K
7059 10:56:07.253350 CBT Training : PASS
7060 10:56:07.253400 Write leveling : PASS
7061 10:56:07.253451 RX DQS gating : PASS
7062 10:56:07.253502 RX DQ/DQS(RDDQC) : PASS
7063 10:56:07.253553 TX DQ/DQS : PASS
7064 10:56:07.253603 RX DATLAT : PASS
7065 10:56:07.253653 RX DQ/DQS(Engine): PASS
7066 10:56:07.253704 TX OE : NO K
7067 10:56:07.253755 All Pass.
7068 10:56:07.253805
7069 10:56:07.253855 CH 0, Rank 1
7070 10:56:07.253906 SW Impedance : PASS
7071 10:56:07.253957 DUTY Scan : NO K
7072 10:56:07.254008 ZQ Calibration : PASS
7073 10:56:07.254059 Jitter Meter : NO K
7074 10:56:07.254110 CBT Training : PASS
7075 10:56:07.254161 Write leveling : NO K
7076 10:56:07.254212 RX DQS gating : PASS
7077 10:56:07.254263 RX DQ/DQS(RDDQC) : PASS
7078 10:56:07.254313 TX DQ/DQS : PASS
7079 10:56:07.254411 RX DATLAT : PASS
7080 10:56:07.254475 RX DQ/DQS(Engine): PASS
7081 10:56:07.254526 TX OE : NO K
7082 10:56:07.254577 All Pass.
7083 10:56:07.254627
7084 10:56:07.254678 CH 1, Rank 0
7085 10:56:07.254728 SW Impedance : PASS
7086 10:56:07.254778 DUTY Scan : NO K
7087 10:56:07.254852 ZQ Calibration : PASS
7088 10:56:07.254920 Jitter Meter : NO K
7089 10:56:07.254971 CBT Training : PASS
7090 10:56:07.255022 Write leveling : PASS
7091 10:56:07.255072 RX DQS gating : PASS
7092 10:56:07.255123 RX DQ/DQS(RDDQC) : PASS
7093 10:56:07.255174 TX DQ/DQS : PASS
7094 10:56:07.255225 RX DATLAT : PASS
7095 10:56:07.255275 RX DQ/DQS(Engine): PASS
7096 10:56:07.255326 TX OE : NO K
7097 10:56:07.255378 All Pass.
7098 10:56:07.255428
7099 10:56:07.255478 CH 1, Rank 1
7100 10:56:07.255528 SW Impedance : PASS
7101 10:56:07.255579 DUTY Scan : NO K
7102 10:56:07.255629 ZQ Calibration : PASS
7103 10:56:07.255679 Jitter Meter : NO K
7104 10:56:07.255730 CBT Training : PASS
7105 10:56:07.255781 Write leveling : NO K
7106 10:56:07.255831 RX DQS gating : PASS
7107 10:56:07.255882 RX DQ/DQS(RDDQC) : PASS
7108 10:56:07.255932 TX DQ/DQS : PASS
7109 10:56:07.255983 RX DATLAT : PASS
7110 10:56:07.256034 RX DQ/DQS(Engine): PASS
7111 10:56:07.256085 TX OE : NO K
7112 10:56:07.256136 All Pass.
7113 10:56:07.256186
7114 10:56:07.256237 DramC Write-DBI off
7115 10:56:07.256288 PER_BANK_REFRESH: Hybrid Mode
7116 10:56:07.256339 TX_TRACKING: ON
7117 10:56:07.256392 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 10:56:07.256445 [FAST_K] Save calibration result to emmc
7119 10:56:07.256497 dramc_set_vcore_voltage set vcore to 725000
7120 10:56:07.256548 Read voltage for 1600, 0
7121 10:56:07.256600 Vio18 = 0
7122 10:56:07.256651 Vcore = 725000
7123 10:56:07.256703 Vdram = 0
7124 10:56:07.256754 Vddq = 0
7125 10:56:07.256806 Vmddr = 0
7126 10:56:07.256857 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 10:56:07.256909 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 10:56:07.256961 MEM_TYPE=3, freq_sel=13
7129 10:56:07.257013 sv_algorithm_assistance_LP4_3733
7130 10:56:07.257065 ============ PULL DRAM RESETB DOWN ============
7131 10:56:07.257118 ========== PULL DRAM RESETB DOWN end =========
7132 10:56:07.257171 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 10:56:07.257223 ===================================
7134 10:56:07.257276 LPDDR4 DRAM CONFIGURATION
7135 10:56:07.257328 ===================================
7136 10:56:07.257381 EX_ROW_EN[0] = 0x0
7137 10:56:07.257432 EX_ROW_EN[1] = 0x0
7138 10:56:07.257485 LP4Y_EN = 0x0
7139 10:56:07.257537 WORK_FSP = 0x1
7140 10:56:07.257589 WL = 0x5
7141 10:56:07.257641 RL = 0x5
7142 10:56:07.257693 BL = 0x2
7143 10:56:07.257745 RPST = 0x0
7144 10:56:07.257797 RD_PRE = 0x0
7145 10:56:07.257850 WR_PRE = 0x1
7146 10:56:07.257901 WR_PST = 0x1
7147 10:56:07.257953 DBI_WR = 0x0
7148 10:56:07.258005 DBI_RD = 0x0
7149 10:56:07.258057 OTF = 0x1
7150 10:56:07.258173 ===================================
7151 10:56:07.258225 ===================================
7152 10:56:07.258278 ANA top config
7153 10:56:07.258330 ===================================
7154 10:56:07.258383 DLL_ASYNC_EN = 0
7155 10:56:07.258436 ALL_SLAVE_EN = 0
7156 10:56:07.258488 NEW_RANK_MODE = 1
7157 10:56:07.258540 DLL_IDLE_MODE = 1
7158 10:56:07.258592 LP45_APHY_COMB_EN = 1
7159 10:56:07.258644 TX_ODT_DIS = 0
7160 10:56:07.258697 NEW_8X_MODE = 1
7161 10:56:07.258749 ===================================
7162 10:56:07.258801 ===================================
7163 10:56:07.258893 data_rate = 3200
7164 10:56:07.258947 CKR = 1
7165 10:56:07.259000 DQ_P2S_RATIO = 8
7166 10:56:07.259052 ===================================
7167 10:56:07.259104 CA_P2S_RATIO = 8
7168 10:56:07.259157 DQ_CA_OPEN = 0
7169 10:56:07.259209 DQ_SEMI_OPEN = 0
7170 10:56:07.259261 CA_SEMI_OPEN = 0
7171 10:56:07.259313 CA_FULL_RATE = 0
7172 10:56:07.259365 DQ_CKDIV4_EN = 0
7173 10:56:07.259418 CA_CKDIV4_EN = 0
7174 10:56:07.259470 CA_PREDIV_EN = 0
7175 10:56:07.259522 PH8_DLY = 12
7176 10:56:07.259574 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 10:56:07.259626 DQ_AAMCK_DIV = 4
7178 10:56:07.259679 CA_AAMCK_DIV = 4
7179 10:56:07.259731 CA_ADMCK_DIV = 4
7180 10:56:07.259783 DQ_TRACK_CA_EN = 0
7181 10:56:07.260019 CA_PICK = 1600
7182 10:56:07.260132 CA_MCKIO = 1600
7183 10:56:07.260216 MCKIO_SEMI = 0
7184 10:56:07.260270 PLL_FREQ = 3068
7185 10:56:07.260324 DQ_UI_PI_RATIO = 32
7186 10:56:07.260378 CA_UI_PI_RATIO = 0
7187 10:56:07.260431 ===================================
7188 10:56:07.260485 ===================================
7189 10:56:07.260539 memory_type:LPDDR4
7190 10:56:07.260607 GP_NUM : 10
7191 10:56:07.260659 SRAM_EN : 1
7192 10:56:07.260712 MD32_EN : 0
7193 10:56:07.260765 ===================================
7194 10:56:07.260817 [ANA_INIT] >>>>>>>>>>>>>>
7195 10:56:07.260870 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 10:56:07.260922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 10:56:07.260975 ===================================
7198 10:56:07.261027 data_rate = 3200,PCW = 0X7600
7199 10:56:07.261080 ===================================
7200 10:56:07.261132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 10:56:07.261201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 10:56:07.261255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 10:56:07.261322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 10:56:07.261374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 10:56:07.261427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 10:56:07.261479 [ANA_INIT] flow start
7207 10:56:07.261531 [ANA_INIT] PLL >>>>>>>>
7208 10:56:07.261583 [ANA_INIT] PLL <<<<<<<<
7209 10:56:07.261635 [ANA_INIT] MIDPI >>>>>>>>
7210 10:56:07.261687 [ANA_INIT] MIDPI <<<<<<<<
7211 10:56:07.261751 [ANA_INIT] DLL >>>>>>>>
7212 10:56:07.261804 [ANA_INIT] DLL <<<<<<<<
7213 10:56:07.261856 [ANA_INIT] flow end
7214 10:56:07.261909 ============ LP4 DIFF to SE enter ============
7215 10:56:07.261962 ============ LP4 DIFF to SE exit ============
7216 10:56:07.262015 [ANA_INIT] <<<<<<<<<<<<<
7217 10:56:07.262067 [Flow] Enable top DCM control >>>>>
7218 10:56:07.262119 [Flow] Enable top DCM control <<<<<
7219 10:56:07.262172 Enable DLL master slave shuffle
7220 10:56:07.262224 ==============================================================
7221 10:56:07.262277 Gating Mode config
7222 10:56:07.262329 ==============================================================
7223 10:56:07.262381 Config description:
7224 10:56:07.262433 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 10:56:07.262487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 10:56:07.262540 SELPH_MODE 0: By rank 1: By Phase
7227 10:56:07.262593 ==============================================================
7228 10:56:07.262646 GAT_TRACK_EN = 1
7229 10:56:07.262698 RX_GATING_MODE = 2
7230 10:56:07.262751 RX_GATING_TRACK_MODE = 2
7231 10:56:07.262803 SELPH_MODE = 1
7232 10:56:07.262897 PICG_EARLY_EN = 1
7233 10:56:07.262951 VALID_LAT_VALUE = 1
7234 10:56:07.263003 ==============================================================
7235 10:56:07.263056 Enter into Gating configuration >>>>
7236 10:56:07.263109 Exit from Gating configuration <<<<
7237 10:56:07.263161 Enter into DVFS_PRE_config >>>>>
7238 10:56:07.263214 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 10:56:07.263268 Exit from DVFS_PRE_config <<<<<
7240 10:56:07.263320 Enter into PICG configuration >>>>
7241 10:56:07.263373 Exit from PICG configuration <<<<
7242 10:56:07.263425 [RX_INPUT] configuration >>>>>
7243 10:56:07.263477 [RX_INPUT] configuration <<<<<
7244 10:56:07.263530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 10:56:07.263582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 10:56:07.263635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 10:56:07.263688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 10:56:07.263740 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 10:56:07.263793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 10:56:07.263845 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 10:56:07.263897 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 10:56:07.263950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 10:56:07.264003 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 10:56:07.264055 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 10:56:07.264107 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 10:56:07.264159 ===================================
7257 10:56:07.264211 LPDDR4 DRAM CONFIGURATION
7258 10:56:07.264263 ===================================
7259 10:56:07.264333 EX_ROW_EN[0] = 0x0
7260 10:56:07.264399 EX_ROW_EN[1] = 0x0
7261 10:56:07.264450 LP4Y_EN = 0x0
7262 10:56:07.264502 WORK_FSP = 0x1
7263 10:56:07.264554 WL = 0x5
7264 10:56:07.264606 RL = 0x5
7265 10:56:07.264658 BL = 0x2
7266 10:56:07.264710 RPST = 0x0
7267 10:56:07.264761 RD_PRE = 0x0
7268 10:56:07.264813 WR_PRE = 0x1
7269 10:56:07.264865 WR_PST = 0x1
7270 10:56:07.264916 DBI_WR = 0x0
7271 10:56:07.264968 DBI_RD = 0x0
7272 10:56:07.265019 OTF = 0x1
7273 10:56:07.265072 ===================================
7274 10:56:07.265124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 10:56:07.265177 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 10:56:07.265228 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 10:56:07.265281 ===================================
7278 10:56:07.265334 LPDDR4 DRAM CONFIGURATION
7279 10:56:07.265386 ===================================
7280 10:56:07.265438 EX_ROW_EN[0] = 0x10
7281 10:56:07.265490 EX_ROW_EN[1] = 0x0
7282 10:56:07.265542 LP4Y_EN = 0x0
7283 10:56:07.265594 WORK_FSP = 0x1
7284 10:56:07.265646 WL = 0x5
7285 10:56:07.265698 RL = 0x5
7286 10:56:07.265750 BL = 0x2
7287 10:56:07.265801 RPST = 0x0
7288 10:56:07.265853 RD_PRE = 0x0
7289 10:56:07.265904 WR_PRE = 0x1
7290 10:56:07.266152 WR_PST = 0x1
7291 10:56:07.266212 DBI_WR = 0x0
7292 10:56:07.266266 DBI_RD = 0x0
7293 10:56:07.266319 OTF = 0x1
7294 10:56:07.266373 ===================================
7295 10:56:07.266427 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 10:56:07.266482 ==
7297 10:56:07.266535 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 10:56:07.266589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 10:56:07.266658 ==
7300 10:56:07.266710 [Duty_Offset_Calibration]
7301 10:56:07.266762 B0:2 B1:0 CA:3
7302 10:56:07.266814
7303 10:56:07.266910 [DutyScan_Calibration_Flow] k_type=0
7304 10:56:07.266963
7305 10:56:07.267015 ==CLK 0==
7306 10:56:07.267068 Final CLK duty delay cell = 0
7307 10:56:07.267121 [0] MAX Duty = 5031%(X100), DQS PI = 12
7308 10:56:07.267173 [0] MIN Duty = 4907%(X100), DQS PI = 6
7309 10:56:07.267225 [0] AVG Duty = 4969%(X100)
7310 10:56:07.267277
7311 10:56:07.267346 CH0 CLK Duty spec in!! Max-Min= 124%
7312 10:56:07.267412 [DutyScan_Calibration_Flow] ====Done====
7313 10:56:07.267465
7314 10:56:07.267517 [DutyScan_Calibration_Flow] k_type=1
7315 10:56:07.267569
7316 10:56:07.267620 ==DQS 0 ==
7317 10:56:07.267673 Final DQS duty delay cell = 0
7318 10:56:07.267725 [0] MAX Duty = 5094%(X100), DQS PI = 28
7319 10:56:07.267778 [0] MIN Duty = 4906%(X100), DQS PI = 48
7320 10:56:07.267830 [0] AVG Duty = 5000%(X100)
7321 10:56:07.267882
7322 10:56:07.267934 ==DQS 1 ==
7323 10:56:07.267987 Final DQS duty delay cell = 0
7324 10:56:07.268039 [0] MAX Duty = 5156%(X100), DQS PI = 30
7325 10:56:07.268091 [0] MIN Duty = 5031%(X100), DQS PI = 12
7326 10:56:07.268143 [0] AVG Duty = 5093%(X100)
7327 10:56:07.268195
7328 10:56:07.268246 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7329 10:56:07.268299
7330 10:56:07.268350 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7331 10:56:07.268402 [DutyScan_Calibration_Flow] ====Done====
7332 10:56:07.268483
7333 10:56:07.268583 [DutyScan_Calibration_Flow] k_type=3
7334 10:56:07.268667
7335 10:56:07.268733 ==DQM 0 ==
7336 10:56:07.268785 Final DQM duty delay cell = 0
7337 10:56:07.268839 [0] MAX Duty = 5156%(X100), DQS PI = 30
7338 10:56:07.268903 [0] MIN Duty = 4875%(X100), DQS PI = 0
7339 10:56:07.268957 [0] AVG Duty = 5015%(X100)
7340 10:56:07.269009
7341 10:56:07.269061 ==DQM 1 ==
7342 10:56:07.269114 Final DQM duty delay cell = 4
7343 10:56:07.269167 [4] MAX Duty = 5187%(X100), DQS PI = 62
7344 10:56:07.269219 [4] MIN Duty = 5000%(X100), DQS PI = 40
7345 10:56:07.269271 [4] AVG Duty = 5093%(X100)
7346 10:56:07.269323
7347 10:56:07.269375 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7348 10:56:07.269427
7349 10:56:07.269479 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7350 10:56:07.269532 [DutyScan_Calibration_Flow] ====Done====
7351 10:56:07.269584
7352 10:56:07.269636 [DutyScan_Calibration_Flow] k_type=2
7353 10:56:07.269688
7354 10:56:07.269739 ==DQ 0 ==
7355 10:56:07.269792 Final DQ duty delay cell = -4
7356 10:56:07.269845 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7357 10:56:07.269897 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7358 10:56:07.269949 [-4] AVG Duty = 4938%(X100)
7359 10:56:07.270002
7360 10:56:07.270053 ==DQ 1 ==
7361 10:56:07.270104 Final DQ duty delay cell = 0
7362 10:56:07.270156 [0] MAX Duty = 5156%(X100), DQS PI = 60
7363 10:56:07.270207 [0] MIN Duty = 5000%(X100), DQS PI = 14
7364 10:56:07.270258 [0] AVG Duty = 5078%(X100)
7365 10:56:07.270309
7366 10:56:07.270359 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7367 10:56:07.270410
7368 10:56:07.270461 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7369 10:56:07.270512 [DutyScan_Calibration_Flow] ====Done====
7370 10:56:07.270562 ==
7371 10:56:07.270613 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 10:56:07.270664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 10:56:07.270716 ==
7374 10:56:07.270767 [Duty_Offset_Calibration]
7375 10:56:07.270817 B0:1 B1:-2 CA:0
7376 10:56:07.270918
7377 10:56:07.270970 [DutyScan_Calibration_Flow] k_type=0
7378 10:56:07.271038
7379 10:56:07.271133 ==CLK 0==
7380 10:56:07.271183 Final CLK duty delay cell = 0
7381 10:56:07.271235 [0] MAX Duty = 5093%(X100), DQS PI = 22
7382 10:56:07.271286 [0] MIN Duty = 4844%(X100), DQS PI = 4
7383 10:56:07.271337 [0] AVG Duty = 4968%(X100)
7384 10:56:07.271388
7385 10:56:07.271439 CH1 CLK Duty spec in!! Max-Min= 249%
7386 10:56:07.271490 [DutyScan_Calibration_Flow] ====Done====
7387 10:56:07.271540
7388 10:56:07.271590 [DutyScan_Calibration_Flow] k_type=1
7389 10:56:07.271641
7390 10:56:07.271691 ==DQS 0 ==
7391 10:56:07.271742 Final DQS duty delay cell = -4
7392 10:56:07.271793 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7393 10:56:07.271844 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7394 10:56:07.271895 [-4] AVG Duty = 4922%(X100)
7395 10:56:07.271946
7396 10:56:07.271996 ==DQS 1 ==
7397 10:56:07.272047 Final DQS duty delay cell = 0
7398 10:56:07.272098 [0] MAX Duty = 5093%(X100), DQS PI = 0
7399 10:56:07.272149 [0] MIN Duty = 4844%(X100), DQS PI = 24
7400 10:56:07.272199 [0] AVG Duty = 4968%(X100)
7401 10:56:07.272250
7402 10:56:07.272300 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7403 10:56:07.272352
7404 10:56:07.272402 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7405 10:56:07.272453 [DutyScan_Calibration_Flow] ====Done====
7406 10:56:07.272504
7407 10:56:07.272554 [DutyScan_Calibration_Flow] k_type=3
7408 10:56:07.272604
7409 10:56:07.272655 ==DQM 0 ==
7410 10:56:07.272705 Final DQM duty delay cell = 0
7411 10:56:07.272756 [0] MAX Duty = 5031%(X100), DQS PI = 26
7412 10:56:07.272807 [0] MIN Duty = 4813%(X100), DQS PI = 56
7413 10:56:07.272858 [0] AVG Duty = 4922%(X100)
7414 10:56:07.272908
7415 10:56:07.272971 ==DQM 1 ==
7416 10:56:07.273024 Final DQM duty delay cell = 0
7417 10:56:07.273075 [0] MAX Duty = 5062%(X100), DQS PI = 34
7418 10:56:07.273126 [0] MIN Duty = 4875%(X100), DQS PI = 26
7419 10:56:07.273177 [0] AVG Duty = 4968%(X100)
7420 10:56:07.273227
7421 10:56:07.273278 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7422 10:56:07.273329
7423 10:56:07.273379 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7424 10:56:07.273430 [DutyScan_Calibration_Flow] ====Done====
7425 10:56:07.273481
7426 10:56:07.273532 [DutyScan_Calibration_Flow] k_type=2
7427 10:56:07.273582
7428 10:56:07.273632 ==DQ 0 ==
7429 10:56:07.273684 Final DQ duty delay cell = 0
7430 10:56:07.273735 [0] MAX Duty = 5093%(X100), DQS PI = 20
7431 10:56:07.273785 [0] MIN Duty = 4907%(X100), DQS PI = 46
7432 10:56:07.273836 [0] AVG Duty = 5000%(X100)
7433 10:56:07.273886
7434 10:56:07.273936 ==DQ 1 ==
7435 10:56:07.273987 Final DQ duty delay cell = 0
7436 10:56:07.274038 [0] MAX Duty = 5156%(X100), DQS PI = 36
7437 10:56:07.274118 [0] MIN Duty = 4969%(X100), DQS PI = 24
7438 10:56:07.274170 [0] AVG Duty = 5062%(X100)
7439 10:56:07.274221
7440 10:56:07.274271 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7441 10:56:07.274323
7442 10:56:07.274373 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7443 10:56:07.274424 [DutyScan_Calibration_Flow] ====Done====
7444 10:56:07.274474 nWR fixed to 30
7445 10:56:07.274525 [ModeRegInit_LP4] CH0 RK0
7446 10:56:07.274576 [ModeRegInit_LP4] CH0 RK1
7447 10:56:07.274627 [ModeRegInit_LP4] CH1 RK0
7448 10:56:07.274677 [ModeRegInit_LP4] CH1 RK1
7449 10:56:07.274757 match AC timing 5
7450 10:56:07.274869 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 10:56:07.275124 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 10:56:07.275182 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 10:56:07.275236 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 10:56:07.275289 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 10:56:07.275340 [MiockJmeterHQA]
7456 10:56:07.275391
7457 10:56:07.275442 [DramcMiockJmeter] u1RxGatingPI = 0
7458 10:56:07.275493 0 : 4363, 4137
7459 10:56:07.275545 4 : 4363, 4137
7460 10:56:07.275597 8 : 4252, 4027
7461 10:56:07.275649 12 : 4257, 4029
7462 10:56:07.275701 16 : 4257, 4030
7463 10:56:07.275753 20 : 4252, 4027
7464 10:56:07.275805 24 : 4252, 4027
7465 10:56:07.275856 28 : 4252, 4027
7466 10:56:07.275908 32 : 4366, 4140
7467 10:56:07.275959 36 : 4253, 4026
7468 10:56:07.276010 40 : 4255, 4030
7469 10:56:07.276061 44 : 4252, 4027
7470 10:56:07.276112 48 : 4363, 4137
7471 10:56:07.276164 52 : 4252, 4026
7472 10:56:07.276215 56 : 4363, 4137
7473 10:56:07.276267 60 : 4252, 4027
7474 10:56:07.276318 64 : 4250, 4026
7475 10:56:07.276370 68 : 4250, 4026
7476 10:56:07.276422 72 : 4252, 4029
7477 10:56:07.276474 76 : 4361, 4137
7478 10:56:07.276526 80 : 4250, 4027
7479 10:56:07.276577 84 : 4360, 4137
7480 10:56:07.276628 88 : 4250, 4026
7481 10:56:07.276680 92 : 4249, 4027
7482 10:56:07.276731 96 : 4250, 4026
7483 10:56:07.276783 100 : 4361, 4137
7484 10:56:07.276834 104 : 4249, 3996
7485 10:56:07.276886 108 : 4360, 74
7486 10:56:07.276937 112 : 4361, 0
7487 10:56:07.276989 116 : 4252, 0
7488 10:56:07.277041 120 : 4253, 0
7489 10:56:07.277097 124 : 4360, 0
7490 10:56:07.277149 128 : 4360, 0
7491 10:56:07.277200 132 : 4363, 0
7492 10:56:07.277252 136 : 4250, 0
7493 10:56:07.277303 140 : 4250, 0
7494 10:56:07.277355 144 : 4363, 0
7495 10:56:07.277406 148 : 4250, 0
7496 10:56:07.277457 152 : 4250, 0
7497 10:56:07.277508 156 : 4250, 0
7498 10:56:07.277559 160 : 4252, 0
7499 10:56:07.277610 164 : 4363, 0
7500 10:56:07.277662 168 : 4250, 0
7501 10:56:07.277713 172 : 4250, 0
7502 10:56:07.277765 176 : 4252, 0
7503 10:56:07.277816 180 : 4361, 0
7504 10:56:07.277867 184 : 4361, 0
7505 10:56:07.277918 188 : 4250, 0
7506 10:56:07.277970 192 : 4250, 0
7507 10:56:07.278021 196 : 4250, 0
7508 10:56:07.278072 200 : 4252, 0
7509 10:56:07.278123 204 : 4250, 0
7510 10:56:07.278174 208 : 4250, 0
7511 10:56:07.278225 212 : 4252, 0
7512 10:56:07.278276 216 : 4361, 0
7513 10:56:07.278327 220 : 4250, 0
7514 10:56:07.278378 224 : 4250, 0
7515 10:56:07.278430 228 : 4250, 0
7516 10:56:07.278481 232 : 4361, 0
7517 10:56:07.278533 236 : 4361, 813
7518 10:56:07.278585 240 : 4250, 4023
7519 10:56:07.278637 244 : 4361, 4137
7520 10:56:07.278687 248 : 4250, 4027
7521 10:56:07.278739 252 : 4250, 4027
7522 10:56:07.278790 256 : 4361, 4137
7523 10:56:07.278865 260 : 4361, 4137
7524 10:56:07.278932 264 : 4250, 4026
7525 10:56:07.278984 268 : 4363, 4140
7526 10:56:07.279035 272 : 4361, 4137
7527 10:56:07.279086 276 : 4250, 4027
7528 10:56:07.279137 280 : 4250, 4027
7529 10:56:07.279188 284 : 4252, 4030
7530 10:56:07.279239 288 : 4250, 4026
7531 10:56:07.279291 292 : 4250, 4026
7532 10:56:07.279342 296 : 4250, 4027
7533 10:56:07.279394 300 : 4252, 4030
7534 10:56:07.279445 304 : 4250, 4027
7535 10:56:07.279496 308 : 4361, 4137
7536 10:56:07.279549 312 : 4361, 4137
7537 10:56:07.279600 316 : 4250, 4027
7538 10:56:07.279651 320 : 4363, 4139
7539 10:56:07.279703 324 : 4361, 4137
7540 10:56:07.279755 328 : 4250, 4027
7541 10:56:07.279806 332 : 4252, 4027
7542 10:56:07.279857 336 : 4252, 4029
7543 10:56:07.279909 340 : 4250, 4027
7544 10:56:07.279960 344 : 4250, 4026
7545 10:56:07.280012 348 : 4250, 4027
7546 10:56:07.280062 352 : 4252, 4027
7547 10:56:07.280114 356 : 4250, 2829
7548 10:56:07.280165 360 : 4361, 1
7549 10:56:07.280217
7550 10:56:07.280267 MIOCK jitter meter ch=0
7551 10:56:07.280318
7552 10:56:07.280369 1T = (360-108) = 252 dly cells
7553 10:56:07.280420 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7554 10:56:07.280472 ==
7555 10:56:07.280523 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 10:56:07.280573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 10:56:07.280625 ==
7558 10:56:07.280675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 10:56:07.280726 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 10:56:07.280777 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 10:56:07.280828 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 10:56:07.280879 [CA 0] Center 44 (14~74) winsize 61
7563 10:56:07.280930 [CA 1] Center 43 (13~74) winsize 62
7564 10:56:07.280981 [CA 2] Center 39 (10~68) winsize 59
7565 10:56:07.281031 [CA 3] Center 38 (9~68) winsize 60
7566 10:56:07.281081 [CA 4] Center 36 (7~66) winsize 60
7567 10:56:07.281132 [CA 5] Center 36 (7~66) winsize 60
7568 10:56:07.281182
7569 10:56:07.281232 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7570 10:56:07.281283
7571 10:56:07.281333 [CATrainingPosCal] consider 1 rank data
7572 10:56:07.281383 u2DelayCellTimex100 = 258/100 ps
7573 10:56:07.281434 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7574 10:56:07.281485 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7575 10:56:07.281535 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7576 10:56:07.281585 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7577 10:56:07.281637 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 10:56:07.281698 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7579 10:56:07.281751
7580 10:56:07.281802 CA PerBit enable=1, Macro0, CA PI delay=36
7581 10:56:07.281853
7582 10:56:07.281903 [CBTSetCACLKResult] CA Dly = 36
7583 10:56:07.281954 CS Dly: 11 (0~42)
7584 10:56:07.282004 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 10:56:07.282055 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 10:56:07.282107 ==
7587 10:56:07.282157 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 10:56:07.282208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 10:56:07.282259 ==
7590 10:56:07.282310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 10:56:07.282362 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 10:56:07.282413 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 10:56:07.282463 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 10:56:07.282515 [CA 0] Center 44 (14~74) winsize 61
7595 10:56:07.282570 [CA 1] Center 43 (13~74) winsize 62
7596 10:56:07.282628 [CA 2] Center 39 (10~68) winsize 59
7597 10:56:07.282679 [CA 3] Center 39 (10~68) winsize 59
7598 10:56:07.282730 [CA 4] Center 36 (7~66) winsize 60
7599 10:56:07.282781 [CA 5] Center 36 (7~66) winsize 60
7600 10:56:07.282841
7601 10:56:07.282928 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7602 10:56:07.282979
7603 10:56:07.283029 [CATrainingPosCal] consider 2 rank data
7604 10:56:07.283080 u2DelayCellTimex100 = 258/100 ps
7605 10:56:07.283131 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7606 10:56:07.283182 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7607 10:56:07.283233 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7608 10:56:07.283284 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7609 10:56:07.283335 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7610 10:56:07.283386 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7611 10:56:07.283437
7612 10:56:07.283487 CA PerBit enable=1, Macro0, CA PI delay=36
7613 10:56:07.283538
7614 10:56:07.283588 [CBTSetCACLKResult] CA Dly = 36
7615 10:56:07.283639 CS Dly: 11 (0~43)
7616 10:56:07.283690 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 10:56:07.283928 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 10:56:07.283988
7619 10:56:07.284040 ----->DramcWriteLeveling(PI) begin...
7620 10:56:07.284092 ==
7621 10:56:07.284144 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 10:56:07.284194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 10:56:07.284246 ==
7624 10:56:07.284297 Write leveling (Byte 0): 38 => 38
7625 10:56:07.284348 Write leveling (Byte 1): 27 => 27
7626 10:56:07.284399 DramcWriteLeveling(PI) end<-----
7627 10:56:07.284449
7628 10:56:07.284499 ==
7629 10:56:07.284580 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 10:56:07.284630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 10:56:07.284681 ==
7632 10:56:07.284732 [Gating] SW mode calibration
7633 10:56:07.284783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 10:56:07.284835 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 10:56:07.284887 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 10:56:07.284938 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 10:56:07.284989 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 10:56:07.285040 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 10:56:07.285091 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7640 10:56:07.285142 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7641 10:56:07.285193 1 4 24 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
7642 10:56:07.285244 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 10:56:07.285295 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 10:56:07.285345 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 10:56:07.285396 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 10:56:07.285447 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7647 10:56:07.285497 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7648 10:56:07.285548 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7649 10:56:07.285598 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7650 10:56:07.285649 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 10:56:07.285699 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 10:56:07.285750 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 10:56:07.285802 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 10:56:07.285853 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 10:56:07.285904 1 6 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7656 10:56:07.285955 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7657 10:56:07.286006 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7658 10:56:07.286056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 10:56:07.286106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 10:56:07.286157 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 10:56:07.286208 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 10:56:07.286258 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7663 10:56:07.286309 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7664 10:56:07.286359 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7665 10:56:07.286410 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7666 10:56:07.286461 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7667 10:56:07.286512 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 10:56:07.286562 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 10:56:07.286613 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 10:56:07.286664 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 10:56:07.286714 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 10:56:07.286765 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 10:56:07.286816 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 10:56:07.286908 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 10:56:07.286959 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 10:56:07.287010 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 10:56:07.287060 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 10:56:07.287112 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 10:56:07.287162 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 10:56:07.287213 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7681 10:56:07.287263 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7682 10:56:07.287314 Total UI for P1: 0, mck2ui 16
7683 10:56:07.287366 best dqsien dly found for B0: ( 1, 9, 18)
7684 10:56:07.287417 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 10:56:07.287468 Total UI for P1: 0, mck2ui 16
7686 10:56:07.287519 best dqsien dly found for B1: ( 1, 9, 24)
7687 10:56:07.287570 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7688 10:56:07.287621 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7689 10:56:07.287671
7690 10:56:07.287722 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7691 10:56:07.287773 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7692 10:56:07.287824 [Gating] SW calibration Done
7693 10:56:07.287875 ==
7694 10:56:07.287925 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 10:56:07.287976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 10:56:07.288027 ==
7697 10:56:07.288078 RX Vref Scan: 0
7698 10:56:07.288128
7699 10:56:07.288178 RX Vref 0 -> 0, step: 1
7700 10:56:07.288229
7701 10:56:07.288280 RX Delay 0 -> 252, step: 8
7702 10:56:07.288330 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7703 10:56:07.288381 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7704 10:56:07.288432 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7705 10:56:07.288482 iDelay=192, Bit 3, Center 123 (64 ~ 183) 120
7706 10:56:07.288564 iDelay=192, Bit 4, Center 131 (80 ~ 183) 104
7707 10:56:07.288614 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7708 10:56:07.288665 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7709 10:56:07.288715 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7710 10:56:07.288766 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7711 10:56:07.288816 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7712 10:56:07.288866 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7713 10:56:07.288917 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7714 10:56:07.288967 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7715 10:56:07.289200 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7716 10:56:07.289257 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7717 10:56:07.289309 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7718 10:56:07.289360 ==
7719 10:56:07.289411 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 10:56:07.289462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 10:56:07.289513 ==
7722 10:56:07.289564 DQS Delay:
7723 10:56:07.289615 DQS0 = 0, DQS1 = 0
7724 10:56:07.289666 DQM Delay:
7725 10:56:07.289716 DQM0 = 128, DQM1 = 124
7726 10:56:07.289768 DQ Delay:
7727 10:56:07.289819 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7728 10:56:07.289870 DQ4 =131, DQ5 =111, DQ6 =139, DQ7 =139
7729 10:56:07.289921 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7730 10:56:07.289971 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
7731 10:56:07.290023
7732 10:56:07.290073
7733 10:56:07.290123 ==
7734 10:56:07.290174 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 10:56:07.290224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 10:56:07.290275 ==
7737 10:56:07.290326
7738 10:56:07.290376
7739 10:56:07.290427 TX Vref Scan disable
7740 10:56:07.290477 == TX Byte 0 ==
7741 10:56:07.290559 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
7742 10:56:07.290611 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
7743 10:56:07.290662 == TX Byte 1 ==
7744 10:56:07.290712 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7745 10:56:07.290763 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7746 10:56:07.290814 ==
7747 10:56:07.290886 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 10:56:07.290953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 10:56:07.291004 ==
7750 10:56:07.291055
7751 10:56:07.291106 TX Vref early break, caculate TX vref
7752 10:56:07.291157 TX Vref=16, minBit 8, minWin=21, winSum=366
7753 10:56:07.291209 TX Vref=18, minBit 8, minWin=21, winSum=373
7754 10:56:07.291260 TX Vref=20, minBit 8, minWin=21, winSum=384
7755 10:56:07.291312 TX Vref=22, minBit 8, minWin=23, winSum=395
7756 10:56:07.291363 TX Vref=24, minBit 8, minWin=23, winSum=402
7757 10:56:07.291413 TX Vref=26, minBit 12, minWin=24, winSum=409
7758 10:56:07.291464 TX Vref=28, minBit 8, minWin=24, winSum=408
7759 10:56:07.291515 TX Vref=30, minBit 8, minWin=23, winSum=400
7760 10:56:07.291566 TX Vref=32, minBit 8, minWin=22, winSum=395
7761 10:56:07.291617 TX Vref=34, minBit 8, minWin=22, winSum=386
7762 10:56:07.291668 [TxChooseVref] Worse bit 12, Min win 24, Win sum 409, Final Vref 26
7763 10:56:07.291719
7764 10:56:07.291770 Final TX Range 0 Vref 26
7765 10:56:07.291821
7766 10:56:07.291872 ==
7767 10:56:07.291923 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 10:56:07.291974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 10:56:07.292025 ==
7770 10:56:07.292075
7771 10:56:07.292126
7772 10:56:07.292176 TX Vref Scan disable
7773 10:56:07.292227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7774 10:56:07.292278 == TX Byte 0 ==
7775 10:56:07.292329 u2DelayCellOfst[0]=7 cells (2 PI)
7776 10:56:07.292379 u2DelayCellOfst[1]=11 cells (3 PI)
7777 10:56:07.292430 u2DelayCellOfst[2]=7 cells (2 PI)
7778 10:56:07.292480 u2DelayCellOfst[3]=7 cells (2 PI)
7779 10:56:07.292541 u2DelayCellOfst[4]=7 cells (2 PI)
7780 10:56:07.292592 u2DelayCellOfst[5]=0 cells (0 PI)
7781 10:56:07.292643 u2DelayCellOfst[6]=11 cells (3 PI)
7782 10:56:07.292694 u2DelayCellOfst[7]=11 cells (3 PI)
7783 10:56:07.292745 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7784 10:56:07.292796 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7785 10:56:07.292848 == TX Byte 1 ==
7786 10:56:07.292899 u2DelayCellOfst[8]=0 cells (0 PI)
7787 10:56:07.292949 u2DelayCellOfst[9]=3 cells (1 PI)
7788 10:56:07.292999 u2DelayCellOfst[10]=11 cells (3 PI)
7789 10:56:07.293050 u2DelayCellOfst[11]=7 cells (2 PI)
7790 10:56:07.293100 u2DelayCellOfst[12]=15 cells (4 PI)
7791 10:56:07.293151 u2DelayCellOfst[13]=15 cells (4 PI)
7792 10:56:07.293201 u2DelayCellOfst[14]=18 cells (5 PI)
7793 10:56:07.293252 u2DelayCellOfst[15]=15 cells (4 PI)
7794 10:56:07.293303 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7795 10:56:07.293354 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7796 10:56:07.293404 DramC Write-DBI on
7797 10:56:07.293455 ==
7798 10:56:07.293505 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 10:56:07.293556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 10:56:07.293607 ==
7801 10:56:07.293657
7802 10:56:07.293708
7803 10:56:07.293757 TX Vref Scan disable
7804 10:56:07.293808 == TX Byte 0 ==
7805 10:56:07.293858 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
7806 10:56:07.293908 == TX Byte 1 ==
7807 10:56:07.293960 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7808 10:56:07.294011 DramC Write-DBI off
7809 10:56:07.294061
7810 10:56:07.294111 [DATLAT]
7811 10:56:07.294162 Freq=1600, CH0 RK0
7812 10:56:07.294213
7813 10:56:07.294263 DATLAT Default: 0xf
7814 10:56:07.294314 0, 0xFFFF, sum = 0
7815 10:56:07.294366 1, 0xFFFF, sum = 0
7816 10:56:07.294417 2, 0xFFFF, sum = 0
7817 10:56:07.294469 3, 0xFFFF, sum = 0
7818 10:56:07.294551 4, 0xFFFF, sum = 0
7819 10:56:07.294602 5, 0xFFFF, sum = 0
7820 10:56:07.294654 6, 0xFFFF, sum = 0
7821 10:56:07.294705 7, 0xFFFF, sum = 0
7822 10:56:07.294756 8, 0xFFFF, sum = 0
7823 10:56:07.294807 9, 0xFFFF, sum = 0
7824 10:56:07.294863 10, 0xFFFF, sum = 0
7825 10:56:07.294916 11, 0xFFFF, sum = 0
7826 10:56:07.294967 12, 0xFFFF, sum = 0
7827 10:56:07.295018 13, 0xCFFF, sum = 0
7828 10:56:07.295070 14, 0x0, sum = 1
7829 10:56:07.295121 15, 0x0, sum = 2
7830 10:56:07.295172 16, 0x0, sum = 3
7831 10:56:07.295224 17, 0x0, sum = 4
7832 10:56:07.295275 best_step = 15
7833 10:56:07.295326
7834 10:56:07.295376 ==
7835 10:56:07.295427 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 10:56:07.295477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 10:56:07.295529 ==
7838 10:56:07.295579 RX Vref Scan: 1
7839 10:56:07.295629
7840 10:56:07.295680 Set Vref Range= 24 -> 127
7841 10:56:07.295730
7842 10:56:07.295780 RX Vref 24 -> 127, step: 1
7843 10:56:07.295831
7844 10:56:07.295881 RX Delay 11 -> 252, step: 4
7845 10:56:07.295932
7846 10:56:07.295982 Set Vref, RX VrefLevel [Byte0]: 24
7847 10:56:07.296033 [Byte1]: 24
7848 10:56:07.296084
7849 10:56:07.296134 Set Vref, RX VrefLevel [Byte0]: 25
7850 10:56:07.296184 [Byte1]: 25
7851 10:56:07.296234
7852 10:56:07.296285 Set Vref, RX VrefLevel [Byte0]: 26
7853 10:56:07.296336 [Byte1]: 26
7854 10:56:07.296387
7855 10:56:07.296437 Set Vref, RX VrefLevel [Byte0]: 27
7856 10:56:07.296488 [Byte1]: 27
7857 10:56:07.296554
7858 10:56:07.296622 Set Vref, RX VrefLevel [Byte0]: 28
7859 10:56:07.296696 [Byte1]: 28
7860 10:56:07.296750
7861 10:56:07.296801 Set Vref, RX VrefLevel [Byte0]: 29
7862 10:56:07.296852 [Byte1]: 29
7863 10:56:07.296903
7864 10:56:07.296953 Set Vref, RX VrefLevel [Byte0]: 30
7865 10:56:07.297004 [Byte1]: 30
7866 10:56:07.297055
7867 10:56:07.297105 Set Vref, RX VrefLevel [Byte0]: 31
7868 10:56:07.297156 [Byte1]: 31
7869 10:56:07.297207
7870 10:56:07.297257 Set Vref, RX VrefLevel [Byte0]: 32
7871 10:56:07.297490 [Byte1]: 32
7872 10:56:07.297546
7873 10:56:07.297597 Set Vref, RX VrefLevel [Byte0]: 33
7874 10:56:07.297649 [Byte1]: 33
7875 10:56:07.297715
7876 10:56:07.297767 Set Vref, RX VrefLevel [Byte0]: 34
7877 10:56:07.297820 [Byte1]: 34
7878 10:56:07.297872
7879 10:56:07.297923 Set Vref, RX VrefLevel [Byte0]: 35
7880 10:56:07.297975 [Byte1]: 35
7881 10:56:07.298040
7882 10:56:07.298090 Set Vref, RX VrefLevel [Byte0]: 36
7883 10:56:07.298141 [Byte1]: 36
7884 10:56:07.298192
7885 10:56:07.298242 Set Vref, RX VrefLevel [Byte0]: 37
7886 10:56:07.298292 [Byte1]: 37
7887 10:56:07.298342
7888 10:56:07.298392 Set Vref, RX VrefLevel [Byte0]: 38
7889 10:56:07.298442 [Byte1]: 38
7890 10:56:07.298509
7891 10:56:07.298573 Set Vref, RX VrefLevel [Byte0]: 39
7892 10:56:07.298624 [Byte1]: 39
7893 10:56:07.298674
7894 10:56:07.298725 Set Vref, RX VrefLevel [Byte0]: 40
7895 10:56:07.298776 [Byte1]: 40
7896 10:56:07.298835
7897 10:56:07.298915 Set Vref, RX VrefLevel [Byte0]: 41
7898 10:56:07.298966 [Byte1]: 41
7899 10:56:07.299017
7900 10:56:07.299067 Set Vref, RX VrefLevel [Byte0]: 42
7901 10:56:07.299118 [Byte1]: 42
7902 10:56:07.299168
7903 10:56:07.299219 Set Vref, RX VrefLevel [Byte0]: 43
7904 10:56:07.299269 [Byte1]: 43
7905 10:56:07.299319
7906 10:56:07.299369 Set Vref, RX VrefLevel [Byte0]: 44
7907 10:56:07.299420 [Byte1]: 44
7908 10:56:07.299470
7909 10:56:07.299520 Set Vref, RX VrefLevel [Byte0]: 45
7910 10:56:07.299571 [Byte1]: 45
7911 10:56:07.299622
7912 10:56:07.299672 Set Vref, RX VrefLevel [Byte0]: 46
7913 10:56:07.299722 [Byte1]: 46
7914 10:56:07.299773
7915 10:56:07.299823 Set Vref, RX VrefLevel [Byte0]: 47
7916 10:56:07.299874 [Byte1]: 47
7917 10:56:07.299924
7918 10:56:07.299975 Set Vref, RX VrefLevel [Byte0]: 48
7919 10:56:07.300025 [Byte1]: 48
7920 10:56:07.300076
7921 10:56:07.300126 Set Vref, RX VrefLevel [Byte0]: 49
7922 10:56:07.300176 [Byte1]: 49
7923 10:56:07.300227
7924 10:56:07.300277 Set Vref, RX VrefLevel [Byte0]: 50
7925 10:56:07.300328 [Byte1]: 50
7926 10:56:07.300378
7927 10:56:07.300428 Set Vref, RX VrefLevel [Byte0]: 51
7928 10:56:07.300479 [Byte1]: 51
7929 10:56:07.300529
7930 10:56:07.300579 Set Vref, RX VrefLevel [Byte0]: 52
7931 10:56:07.300630 [Byte1]: 52
7932 10:56:07.300680
7933 10:56:07.300730 Set Vref, RX VrefLevel [Byte0]: 53
7934 10:56:07.300780 [Byte1]: 53
7935 10:56:07.300831
7936 10:56:07.300881 Set Vref, RX VrefLevel [Byte0]: 54
7937 10:56:07.300932 [Byte1]: 54
7938 10:56:07.300983
7939 10:56:07.301033 Set Vref, RX VrefLevel [Byte0]: 55
7940 10:56:07.301083 [Byte1]: 55
7941 10:56:07.301134
7942 10:56:07.301185 Set Vref, RX VrefLevel [Byte0]: 56
7943 10:56:07.301235 [Byte1]: 56
7944 10:56:07.301286
7945 10:56:07.301336 Set Vref, RX VrefLevel [Byte0]: 57
7946 10:56:07.301386 [Byte1]: 57
7947 10:56:07.301437
7948 10:56:07.301488 Set Vref, RX VrefLevel [Byte0]: 58
7949 10:56:07.301538 [Byte1]: 58
7950 10:56:07.301588
7951 10:56:07.301639 Set Vref, RX VrefLevel [Byte0]: 59
7952 10:56:07.301689 [Byte1]: 59
7953 10:56:07.301740
7954 10:56:07.301790 Set Vref, RX VrefLevel [Byte0]: 60
7955 10:56:07.301840 [Byte1]: 60
7956 10:56:07.301891
7957 10:56:07.301941 Set Vref, RX VrefLevel [Byte0]: 61
7958 10:56:07.301991 [Byte1]: 61
7959 10:56:07.302042
7960 10:56:07.302092 Set Vref, RX VrefLevel [Byte0]: 62
7961 10:56:07.302143 [Byte1]: 62
7962 10:56:07.302194
7963 10:56:07.302244 Set Vref, RX VrefLevel [Byte0]: 63
7964 10:56:07.302295 [Byte1]: 63
7965 10:56:07.302345
7966 10:56:07.302395 Set Vref, RX VrefLevel [Byte0]: 64
7967 10:56:07.302446 [Byte1]: 64
7968 10:56:07.302496
7969 10:56:07.302546 Set Vref, RX VrefLevel [Byte0]: 65
7970 10:56:07.302630 [Byte1]: 65
7971 10:56:07.302681
7972 10:56:07.302731 Set Vref, RX VrefLevel [Byte0]: 66
7973 10:56:07.302782 [Byte1]: 66
7974 10:56:07.302836
7975 10:56:07.302917 Set Vref, RX VrefLevel [Byte0]: 67
7976 10:56:07.302968 [Byte1]: 67
7977 10:56:07.303018
7978 10:56:07.303068 Set Vref, RX VrefLevel [Byte0]: 68
7979 10:56:07.303119 [Byte1]: 68
7980 10:56:07.303170
7981 10:56:07.303221 Set Vref, RX VrefLevel [Byte0]: 69
7982 10:56:07.303271 [Byte1]: 69
7983 10:56:07.303322
7984 10:56:07.303373 Set Vref, RX VrefLevel [Byte0]: 70
7985 10:56:07.303423 [Byte1]: 70
7986 10:56:07.303474
7987 10:56:07.303524 Set Vref, RX VrefLevel [Byte0]: 71
7988 10:56:07.303575 [Byte1]: 71
7989 10:56:07.303626
7990 10:56:07.303676 Set Vref, RX VrefLevel [Byte0]: 72
7991 10:56:07.303726 [Byte1]: 72
7992 10:56:07.303777
7993 10:56:07.303828 Set Vref, RX VrefLevel [Byte0]: 73
7994 10:56:07.303878 [Byte1]: 73
7995 10:56:07.303929
7996 10:56:07.303979 Set Vref, RX VrefLevel [Byte0]: 74
7997 10:56:07.304029 [Byte1]: 74
7998 10:56:07.304080
7999 10:56:07.304130 Set Vref, RX VrefLevel [Byte0]: 75
8000 10:56:07.304180 [Byte1]: 75
8001 10:56:07.304231
8002 10:56:07.304281 Set Vref, RX VrefLevel [Byte0]: 76
8003 10:56:07.304332 [Byte1]: 76
8004 10:56:07.304382
8005 10:56:07.304433 Final RX Vref Byte 0 = 63 to rank0
8006 10:56:07.304484 Final RX Vref Byte 1 = 59 to rank0
8007 10:56:07.304535 Final RX Vref Byte 0 = 63 to rank1
8008 10:56:07.304586 Final RX Vref Byte 1 = 59 to rank1==
8009 10:56:07.304637 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 10:56:07.304687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 10:56:07.304739 ==
8012 10:56:07.304790 DQS Delay:
8013 10:56:07.304841 DQS0 = 0, DQS1 = 0
8014 10:56:07.304891 DQM Delay:
8015 10:56:07.304941 DQM0 = 126, DQM1 = 119
8016 10:56:07.304992 DQ Delay:
8017 10:56:07.305042 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8018 10:56:07.305093 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8019 10:56:07.305143 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8020 10:56:07.305193 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8021 10:56:07.747332
8022 10:56:07.747506
8023 10:56:07.747607
8024 10:56:07.747704 [DramC_TX_OE_Calibration] TA2
8025 10:56:07.747798 Original DQ_B0 (3 6) =30, OEN = 27
8026 10:56:07.747911 Original DQ_B1 (3 6) =30, OEN = 27
8027 10:56:07.748002 24, 0x0, End_B0=24 End_B1=24
8028 10:56:07.748064 25, 0x0, End_B0=25 End_B1=25
8029 10:56:07.748120 26, 0x0, End_B0=26 End_B1=26
8030 10:56:07.748176 27, 0x0, End_B0=27 End_B1=27
8031 10:56:07.748429 28, 0x0, End_B0=28 End_B1=28
8032 10:56:07.748490 29, 0x0, End_B0=29 End_B1=29
8033 10:56:07.748573 30, 0x0, End_B0=30 End_B1=30
8034 10:56:07.748628 31, 0x4101, End_B0=30 End_B1=30
8035 10:56:07.748682 Byte0 end_step=30 best_step=27
8036 10:56:07.748735 Byte1 end_step=30 best_step=27
8037 10:56:07.748788 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 10:56:07.748840 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 10:56:07.748893
8040 10:56:07.748989
8041 10:56:07.749087 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8042 10:56:07.749170 CH0 RK0: MR19=303, MR18=1413
8043 10:56:07.749252 CH0_RK0: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
8044 10:56:07.749334
8045 10:56:07.749430 ----->DramcWriteLeveling(PI) begin...
8046 10:56:07.749514 ==
8047 10:56:07.749607 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 10:56:07.749690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 10:56:07.749784 ==
8050 10:56:07.749876 Write leveling (Byte 0): 33 => 33
8051 10:56:07.749935 Write leveling (Byte 1): 28 => 28
8052 10:56:07.749988 DramcWriteLeveling(PI) end<-----
8053 10:56:07.750041
8054 10:56:07.750093 ==
8055 10:56:07.750145 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 10:56:07.750197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 10:56:07.750251 ==
8058 10:56:07.750303 [Gating] SW mode calibration
8059 10:56:07.750355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 10:56:07.750409 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 10:56:07.750462 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 10:56:07.750516 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 10:56:07.750568 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 10:56:07.750620 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8065 10:56:07.750688 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8066 10:56:07.750774 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8067 10:56:07.750900 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 10:56:07.750970 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 10:56:07.751024 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 10:56:07.751100 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 10:56:07.751157 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8072 10:56:07.751211 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8073 10:56:07.751282 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8074 10:56:07.751337 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8075 10:56:07.751390 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 10:56:07.751445 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 10:56:07.751498 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 10:56:07.751551 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 10:56:07.751603 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8080 10:56:07.751657 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8081 10:56:07.751709 1 6 16 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8082 10:56:07.751762 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8083 10:56:07.751814 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 10:56:07.751900 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 10:56:07.751953 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 10:56:07.752006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 10:56:07.752058 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 10:56:07.752111 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 10:56:07.752163 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 10:56:07.752215 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 10:56:07.752268 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 10:56:07.752320 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 10:56:07.752373 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 10:56:07.752430 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 10:56:07.752483 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 10:56:07.752535 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 10:56:07.752587 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 10:56:07.752639 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 10:56:07.752691 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 10:56:07.752743 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 10:56:07.752795 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 10:56:07.752848 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 10:56:07.752900 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 10:56:07.752952 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 10:56:07.753004 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 10:56:07.753056 Total UI for P1: 0, mck2ui 16
8107 10:56:07.753109 best dqsien dly found for B0: ( 1, 9, 10)
8108 10:56:07.753163 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 10:56:07.753217 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 10:56:07.753270 Total UI for P1: 0, mck2ui 16
8111 10:56:07.753324 best dqsien dly found for B1: ( 1, 9, 18)
8112 10:56:07.753378 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8113 10:56:07.753432 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8114 10:56:07.753485
8115 10:56:07.753539 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8116 10:56:07.753592 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8117 10:56:07.753646 [Gating] SW calibration Done
8118 10:56:07.753699 ==
8119 10:56:07.753752 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 10:56:07.753806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 10:56:07.753865 ==
8122 10:56:07.753953 RX Vref Scan: 0
8123 10:56:07.754023
8124 10:56:07.754079 RX Vref 0 -> 0, step: 1
8125 10:56:07.754133
8126 10:56:07.754187 RX Delay 0 -> 252, step: 8
8127 10:56:07.754241 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8128 10:56:07.754295 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8129 10:56:07.754350 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8130 10:56:07.754404 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8131 10:56:07.754458 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8132 10:56:07.754721 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8133 10:56:07.754811 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 10:56:07.754924 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8135 10:56:07.754995 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8136 10:56:07.755050 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8137 10:56:07.755104 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8138 10:56:07.755158 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8139 10:56:07.755212 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8140 10:56:07.755265 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8141 10:56:07.755319 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8142 10:56:07.755373 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8143 10:56:07.755427 ==
8144 10:56:07.755481 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 10:56:07.755535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 10:56:07.755600 ==
8147 10:56:07.755658 DQS Delay:
8148 10:56:07.755712 DQS0 = 0, DQS1 = 0
8149 10:56:07.755769 DQM Delay:
8150 10:56:07.755846 DQM0 = 127, DQM1 = 122
8151 10:56:07.755930 DQ Delay:
8152 10:56:07.756003 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8153 10:56:07.756060 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8154 10:56:07.756114 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8155 10:56:07.756188 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8156 10:56:07.756251
8157 10:56:07.756305
8158 10:56:07.756369 ==
8159 10:56:07.756435 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 10:56:07.756490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 10:56:07.756555 ==
8162 10:56:07.756641
8163 10:56:07.756723
8164 10:56:07.756809 TX Vref Scan disable
8165 10:56:07.756865 == TX Byte 0 ==
8166 10:56:07.756920 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8167 10:56:07.757003 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8168 10:56:07.757086 == TX Byte 1 ==
8169 10:56:07.757169 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8170 10:56:07.757253 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8171 10:56:07.757335 ==
8172 10:56:07.757418 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 10:56:07.757501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 10:56:07.757584 ==
8175 10:56:07.757666
8176 10:56:07.757748 TX Vref early break, caculate TX vref
8177 10:56:07.757832 TX Vref=16, minBit 8, minWin=22, winSum=367
8178 10:56:07.757922 TX Vref=18, minBit 1, minWin=22, winSum=368
8179 10:56:07.758008 TX Vref=20, minBit 8, minWin=22, winSum=379
8180 10:56:07.758094 TX Vref=22, minBit 8, minWin=23, winSum=391
8181 10:56:07.758184 TX Vref=24, minBit 0, minWin=24, winSum=396
8182 10:56:07.758268 TX Vref=26, minBit 8, minWin=24, winSum=405
8183 10:56:07.758351 TX Vref=28, minBit 8, minWin=24, winSum=408
8184 10:56:07.758434 TX Vref=30, minBit 8, minWin=24, winSum=403
8185 10:56:07.758517 TX Vref=32, minBit 8, minWin=23, winSum=395
8186 10:56:07.758600 TX Vref=34, minBit 8, minWin=23, winSum=385
8187 10:56:07.758684 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 28
8188 10:56:07.758779
8189 10:56:07.758897 Final TX Range 0 Vref 28
8190 10:56:07.758959
8191 10:56:07.759014 ==
8192 10:56:07.759068 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 10:56:07.759157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 10:56:07.759242 ==
8195 10:56:07.759332
8196 10:56:07.759415
8197 10:56:07.759499 TX Vref Scan disable
8198 10:56:07.759573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8199 10:56:07.759629 == TX Byte 0 ==
8200 10:56:07.759684 u2DelayCellOfst[0]=15 cells (4 PI)
8201 10:56:07.759737 u2DelayCellOfst[1]=22 cells (6 PI)
8202 10:56:07.759791 u2DelayCellOfst[2]=15 cells (4 PI)
8203 10:56:07.759845 u2DelayCellOfst[3]=15 cells (4 PI)
8204 10:56:07.759902 u2DelayCellOfst[4]=11 cells (3 PI)
8205 10:56:07.759955 u2DelayCellOfst[5]=0 cells (0 PI)
8206 10:56:07.760009 u2DelayCellOfst[6]=22 cells (6 PI)
8207 10:56:07.760063 u2DelayCellOfst[7]=18 cells (5 PI)
8208 10:56:07.760116 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8209 10:56:07.760170 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8210 10:56:07.760224 == TX Byte 1 ==
8211 10:56:07.760277 u2DelayCellOfst[8]=0 cells (0 PI)
8212 10:56:07.760330 u2DelayCellOfst[9]=3 cells (1 PI)
8213 10:56:07.760384 u2DelayCellOfst[10]=11 cells (3 PI)
8214 10:56:07.760438 u2DelayCellOfst[11]=7 cells (2 PI)
8215 10:56:07.760491 u2DelayCellOfst[12]=15 cells (4 PI)
8216 10:56:07.760545 u2DelayCellOfst[13]=11 cells (3 PI)
8217 10:56:07.760598 u2DelayCellOfst[14]=15 cells (4 PI)
8218 10:56:07.760651 u2DelayCellOfst[15]=11 cells (3 PI)
8219 10:56:07.760705 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8220 10:56:07.760759 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8221 10:56:07.760812 DramC Write-DBI on
8222 10:56:07.760865 ==
8223 10:56:07.760919 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 10:56:07.760972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 10:56:07.761027 ==
8226 10:56:07.761080
8227 10:56:07.761133
8228 10:56:07.761185 TX Vref Scan disable
8229 10:56:07.761238 == TX Byte 0 ==
8230 10:56:07.761292 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8231 10:56:07.761345 == TX Byte 1 ==
8232 10:56:07.761398 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8233 10:56:07.761452 DramC Write-DBI off
8234 10:56:07.761505
8235 10:56:07.761558 [DATLAT]
8236 10:56:07.761611 Freq=1600, CH0 RK1
8237 10:56:07.761664
8238 10:56:07.761718 DATLAT Default: 0xf
8239 10:56:07.761771 0, 0xFFFF, sum = 0
8240 10:56:07.761826 1, 0xFFFF, sum = 0
8241 10:56:07.761880 2, 0xFFFF, sum = 0
8242 10:56:07.761934 3, 0xFFFF, sum = 0
8243 10:56:07.761988 4, 0xFFFF, sum = 0
8244 10:56:07.762042 5, 0xFFFF, sum = 0
8245 10:56:07.762096 6, 0xFFFF, sum = 0
8246 10:56:07.762150 7, 0xFFFF, sum = 0
8247 10:56:07.762203 8, 0xFFFF, sum = 0
8248 10:56:07.762257 9, 0xFFFF, sum = 0
8249 10:56:07.762311 10, 0xFFFF, sum = 0
8250 10:56:07.762365 11, 0xFFFF, sum = 0
8251 10:56:07.762419 12, 0xFFFF, sum = 0
8252 10:56:07.762474 13, 0xCFFF, sum = 0
8253 10:56:07.762528 14, 0x0, sum = 1
8254 10:56:07.762582 15, 0x0, sum = 2
8255 10:56:07.762636 16, 0x0, sum = 3
8256 10:56:07.762689 17, 0x0, sum = 4
8257 10:56:07.762743 best_step = 15
8258 10:56:07.762796
8259 10:56:07.762888 ==
8260 10:56:07.762942 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 10:56:07.762996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 10:56:07.763053 ==
8263 10:56:07.763107 RX Vref Scan: 0
8264 10:56:07.763161
8265 10:56:07.763214 RX Vref 0 -> 0, step: 1
8266 10:56:07.763267
8267 10:56:07.763320 RX Delay 3 -> 252, step: 4
8268 10:56:07.763374 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8269 10:56:07.763427 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8270 10:56:07.763481 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8271 10:56:07.763535 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8272 10:56:07.763588 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8273 10:56:07.763641 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8274 10:56:07.763694 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8275 10:56:07.763938 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8276 10:56:07.763997 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8277 10:56:07.764052 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8278 10:56:07.764106 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8279 10:56:07.764160 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8280 10:56:07.764213 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8281 10:56:07.764282 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8282 10:56:07.764349 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8283 10:56:07.764403 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8284 10:56:07.764457 ==
8285 10:56:07.764510 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 10:56:07.764564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 10:56:07.764618 ==
8288 10:56:07.764672 DQS Delay:
8289 10:56:07.764725 DQS0 = 0, DQS1 = 0
8290 10:56:07.764778 DQM Delay:
8291 10:56:07.764831 DQM0 = 124, DQM1 = 117
8292 10:56:07.764884 DQ Delay:
8293 10:56:07.764938 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8294 10:56:07.764991 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8295 10:56:07.765045 DQ8 =108, DQ9 =104, DQ10 =118, DQ11 =112
8296 10:56:07.765098 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8297 10:56:07.765152
8298 10:56:07.765205
8299 10:56:07.765258
8300 10:56:07.765310 [DramC_TX_OE_Calibration] TA2
8301 10:56:07.765364 Original DQ_B0 (3 6) =30, OEN = 27
8302 10:56:07.765417 Original DQ_B1 (3 6) =30, OEN = 27
8303 10:56:07.765471 24, 0x0, End_B0=24 End_B1=24
8304 10:56:07.765524 25, 0x0, End_B0=25 End_B1=25
8305 10:56:07.765578 26, 0x0, End_B0=26 End_B1=26
8306 10:56:07.765632 27, 0x0, End_B0=27 End_B1=27
8307 10:56:07.765687 28, 0x0, End_B0=28 End_B1=28
8308 10:56:07.765741 29, 0x0, End_B0=29 End_B1=29
8309 10:56:07.765795 30, 0x0, End_B0=30 End_B1=30
8310 10:56:07.765849 31, 0x4141, End_B0=30 End_B1=30
8311 10:56:07.765931 Byte0 end_step=30 best_step=27
8312 10:56:07.765985 Byte1 end_step=30 best_step=27
8313 10:56:07.766038 Byte0 TX OE(2T, 0.5T) = (3, 3)
8314 10:56:07.766092 Byte1 TX OE(2T, 0.5T) = (3, 3)
8315 10:56:07.766145
8316 10:56:07.766198
8317 10:56:07.766251 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8318 10:56:07.766305 CH0 RK1: MR19=303, MR18=2412
8319 10:56:07.766358 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8320 10:56:07.766411 [RxdqsGatingPostProcess] freq 1600
8321 10:56:07.766465 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8322 10:56:07.766519 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 10:56:07.766573 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 10:56:07.766626 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 10:56:07.766679 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 10:56:07.766732 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 10:56:07.766786 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 10:56:07.766864 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 10:56:07.766932 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 10:56:07.766985 Pre-setting of DQS Precalculation
8331 10:56:07.767039 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8332 10:56:07.767093 ==
8333 10:56:07.767147 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 10:56:07.767201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 10:56:07.767255 ==
8336 10:56:07.767309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 10:56:07.767363 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 10:56:07.767418 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 10:56:07.767471 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 10:56:07.767525 [CA 0] Center 41 (12~71) winsize 60
8341 10:56:07.767580 [CA 1] Center 42 (13~72) winsize 60
8342 10:56:07.767633 [CA 2] Center 37 (9~66) winsize 58
8343 10:56:07.767686 [CA 3] Center 37 (8~66) winsize 59
8344 10:56:07.767739 [CA 4] Center 37 (8~66) winsize 59
8345 10:56:07.767793 [CA 5] Center 36 (7~66) winsize 60
8346 10:56:07.767846
8347 10:56:07.767927 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8348 10:56:07.767980
8349 10:56:07.768033 [CATrainingPosCal] consider 1 rank data
8350 10:56:07.768086 u2DelayCellTimex100 = 258/100 ps
8351 10:56:07.768139 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8352 10:56:07.768193 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8353 10:56:07.768247 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8354 10:56:07.768300 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8355 10:56:07.768353 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8356 10:56:07.768406 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8357 10:56:07.768459
8358 10:56:07.768512 CA PerBit enable=1, Macro0, CA PI delay=36
8359 10:56:07.768565
8360 10:56:07.768617 [CBTSetCACLKResult] CA Dly = 36
8361 10:56:07.768669 CS Dly: 10 (0~41)
8362 10:56:07.768720 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 10:56:07.768772 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 10:56:07.768824 ==
8365 10:56:07.768876 Dram Type= 6, Freq= 0, CH_1, rank 1
8366 10:56:07.768928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 10:56:07.768980 ==
8368 10:56:07.769032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 10:56:07.769085 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 10:56:07.769137 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 10:56:07.769189 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 10:56:07.769241 [CA 0] Center 42 (12~72) winsize 61
8373 10:56:07.769293 [CA 1] Center 42 (12~72) winsize 61
8374 10:56:07.769345 [CA 2] Center 37 (8~67) winsize 60
8375 10:56:07.769397 [CA 3] Center 36 (7~66) winsize 60
8376 10:56:07.769448 [CA 4] Center 38 (8~68) winsize 61
8377 10:56:07.769500 [CA 5] Center 36 (6~66) winsize 61
8378 10:56:07.769551
8379 10:56:07.769602 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 10:56:07.769654
8381 10:56:07.769705 [CATrainingPosCal] consider 2 rank data
8382 10:56:07.769757 u2DelayCellTimex100 = 258/100 ps
8383 10:56:07.769809 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8384 10:56:07.769860 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8385 10:56:07.769912 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8386 10:56:07.769964 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8387 10:56:07.770015 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8388 10:56:07.770067 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 10:56:07.770118
8390 10:56:07.770169 CA PerBit enable=1, Macro0, CA PI delay=36
8391 10:56:07.770221
8392 10:56:07.770272 [CBTSetCACLKResult] CA Dly = 36
8393 10:56:07.770324 CS Dly: 11 (0~44)
8394 10:56:07.770375 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 10:56:07.770609 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 10:56:07.770666
8397 10:56:07.770733 ----->DramcWriteLeveling(PI) begin...
8398 10:56:07.770788 ==
8399 10:56:07.770868 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 10:56:07.770923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 10:56:07.770976 ==
8402 10:56:07.771029 Write leveling (Byte 0): 26 => 26
8403 10:56:07.771081 Write leveling (Byte 1): 27 => 27
8404 10:56:07.771133 DramcWriteLeveling(PI) end<-----
8405 10:56:07.771185
8406 10:56:07.771236 ==
8407 10:56:07.771289 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 10:56:07.771375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 10:56:07.771428 ==
8410 10:56:07.771479 [Gating] SW mode calibration
8411 10:56:07.771531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8412 10:56:07.771584 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8413 10:56:07.771636 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 10:56:07.771689 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 10:56:07.771741 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 10:56:07.771794 1 4 12 | B1->B0 | 2525 2323 | 1 0 | (1 1) (1 1)
8417 10:56:07.771846 1 4 16 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
8418 10:56:07.771898 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 10:56:07.771949 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 10:56:07.772001 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 10:56:07.772053 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 10:56:07.772104 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 10:56:07.772156 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 10:56:07.772207 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8425 10:56:07.772259 1 5 16 | B1->B0 | 2727 2828 | 0 0 | (1 0) (0 1)
8426 10:56:07.772311 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 10:56:07.772363 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 10:56:07.772415 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 10:56:07.772466 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 10:56:07.772518 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 10:56:07.772570 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 10:56:07.772621 1 6 12 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
8433 10:56:07.772673 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 10:56:07.772725 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 10:56:07.772778 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 10:56:07.772830 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 10:56:07.772881 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 10:56:07.772933 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 10:56:07.772985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 10:56:07.773037 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 10:56:07.773089 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 10:56:07.773141 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8443 10:56:07.773193 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 10:56:07.773245 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 10:56:07.773297 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 10:56:07.773349 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 10:56:07.773400 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 10:56:07.773453 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 10:56:07.773505 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 10:56:07.773557 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 10:56:07.773609 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 10:56:07.773660 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 10:56:07.773712 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 10:56:07.773764 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 10:56:07.773815 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 10:56:07.773867 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8457 10:56:07.773918 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8458 10:56:07.773970 Total UI for P1: 0, mck2ui 16
8459 10:56:07.774022 best dqsien dly found for B0: ( 1, 9, 12)
8460 10:56:07.774074 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8461 10:56:07.774126 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 10:56:07.774177 Total UI for P1: 0, mck2ui 16
8463 10:56:07.774229 best dqsien dly found for B1: ( 1, 9, 18)
8464 10:56:07.774281 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8465 10:56:07.774334 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8466 10:56:07.774385
8467 10:56:07.774437 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8468 10:56:07.774489 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8469 10:56:07.774541 [Gating] SW calibration Done
8470 10:56:07.774593 ==
8471 10:56:07.774646 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 10:56:07.774697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 10:56:07.774750 ==
8474 10:56:07.774802 RX Vref Scan: 0
8475 10:56:07.774901
8476 10:56:07.774953 RX Vref 0 -> 0, step: 1
8477 10:56:07.775005
8478 10:56:07.775057 RX Delay 0 -> 252, step: 8
8479 10:56:07.775109 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8480 10:56:07.775161 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8481 10:56:07.775213 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8482 10:56:07.775265 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8483 10:56:07.775317 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8484 10:56:07.775369 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8485 10:56:07.775420 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8486 10:56:07.775472 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8487 10:56:07.775523 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8488 10:56:07.775575 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8489 10:56:07.775626 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8490 10:56:07.775677 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8491 10:56:07.775729 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8492 10:56:07.775966 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8493 10:56:07.776027 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8494 10:56:07.776081 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8495 10:56:07.776133 ==
8496 10:56:07.776185 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 10:56:07.776252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 10:56:07.776318 ==
8499 10:56:07.776370 DQS Delay:
8500 10:56:07.776422 DQS0 = 0, DQS1 = 0
8501 10:56:07.776473 DQM Delay:
8502 10:56:07.776526 DQM0 = 132, DQM1 = 125
8503 10:56:07.776578 DQ Delay:
8504 10:56:07.776629 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8505 10:56:07.776681 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8506 10:56:07.776733 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8507 10:56:07.776785 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8508 10:56:07.776838
8509 10:56:07.776890
8510 10:56:07.776942 ==
8511 10:56:07.776994 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 10:56:07.777045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 10:56:07.777098 ==
8514 10:56:07.777149
8515 10:56:07.777201
8516 10:56:07.777252 TX Vref Scan disable
8517 10:56:07.777304 == TX Byte 0 ==
8518 10:56:07.777355 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8519 10:56:07.777407 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8520 10:56:07.777459 == TX Byte 1 ==
8521 10:56:07.777511 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8522 10:56:07.777563 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8523 10:56:07.777615 ==
8524 10:56:07.777697 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 10:56:07.777752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 10:56:07.777805 ==
8527 10:56:07.777874
8528 10:56:07.777928 TX Vref early break, caculate TX vref
8529 10:56:07.777981 TX Vref=16, minBit 1, minWin=22, winSum=363
8530 10:56:07.778034 TX Vref=18, minBit 11, minWin=22, winSum=372
8531 10:56:07.778087 TX Vref=20, minBit 10, minWin=22, winSum=383
8532 10:56:07.778139 TX Vref=22, minBit 1, minWin=24, winSum=395
8533 10:56:07.778192 TX Vref=24, minBit 5, minWin=24, winSum=405
8534 10:56:07.778244 TX Vref=26, minBit 1, minWin=24, winSum=412
8535 10:56:07.778296 TX Vref=28, minBit 0, minWin=25, winSum=416
8536 10:56:07.778348 TX Vref=30, minBit 0, minWin=24, winSum=412
8537 10:56:07.778400 TX Vref=32, minBit 0, minWin=24, winSum=404
8538 10:56:07.778452 TX Vref=34, minBit 0, minWin=23, winSum=396
8539 10:56:07.778505 TX Vref=36, minBit 0, minWin=23, winSum=383
8540 10:56:07.778572 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
8541 10:56:07.778630
8542 10:56:07.778682 Final TX Range 0 Vref 28
8543 10:56:07.778734
8544 10:56:07.778785 ==
8545 10:56:07.778859 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 10:56:07.778925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 10:56:07.778977 ==
8548 10:56:07.779029
8549 10:56:07.779081
8550 10:56:07.779133 TX Vref Scan disable
8551 10:56:07.779185 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8552 10:56:07.779237 == TX Byte 0 ==
8553 10:56:07.779289 u2DelayCellOfst[0]=18 cells (5 PI)
8554 10:56:07.779340 u2DelayCellOfst[1]=11 cells (3 PI)
8555 10:56:07.779392 u2DelayCellOfst[2]=0 cells (0 PI)
8556 10:56:07.779444 u2DelayCellOfst[3]=3 cells (1 PI)
8557 10:56:07.779496 u2DelayCellOfst[4]=7 cells (2 PI)
8558 10:56:07.779547 u2DelayCellOfst[5]=18 cells (5 PI)
8559 10:56:07.779599 u2DelayCellOfst[6]=18 cells (5 PI)
8560 10:56:07.779650 u2DelayCellOfst[7]=3 cells (1 PI)
8561 10:56:07.779702 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8562 10:56:07.779755 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8563 10:56:07.779807 == TX Byte 1 ==
8564 10:56:07.779858 u2DelayCellOfst[8]=0 cells (0 PI)
8565 10:56:07.779910 u2DelayCellOfst[9]=7 cells (2 PI)
8566 10:56:07.779961 u2DelayCellOfst[10]=15 cells (4 PI)
8567 10:56:07.780013 u2DelayCellOfst[11]=11 cells (3 PI)
8568 10:56:07.780064 u2DelayCellOfst[12]=18 cells (5 PI)
8569 10:56:07.780116 u2DelayCellOfst[13]=22 cells (6 PI)
8570 10:56:07.780167 u2DelayCellOfst[14]=22 cells (6 PI)
8571 10:56:07.780218 u2DelayCellOfst[15]=22 cells (6 PI)
8572 10:56:07.780270 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8573 10:56:07.780322 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8574 10:56:07.780374 DramC Write-DBI on
8575 10:56:07.780426 ==
8576 10:56:07.780477 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 10:56:07.780529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 10:56:07.780581 ==
8579 10:56:07.780632
8580 10:56:07.780684
8581 10:56:07.780735 TX Vref Scan disable
8582 10:56:07.780786 == TX Byte 0 ==
8583 10:56:07.780838 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8584 10:56:07.780890 == TX Byte 1 ==
8585 10:56:07.780942 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8586 10:56:07.780994 DramC Write-DBI off
8587 10:56:07.781046
8588 10:56:07.781097 [DATLAT]
8589 10:56:07.781149 Freq=1600, CH1 RK0
8590 10:56:07.781202
8591 10:56:07.781254 DATLAT Default: 0xf
8592 10:56:07.781305 0, 0xFFFF, sum = 0
8593 10:56:07.781359 1, 0xFFFF, sum = 0
8594 10:56:07.781411 2, 0xFFFF, sum = 0
8595 10:56:07.781463 3, 0xFFFF, sum = 0
8596 10:56:07.781516 4, 0xFFFF, sum = 0
8597 10:56:07.781568 5, 0xFFFF, sum = 0
8598 10:56:07.781620 6, 0xFFFF, sum = 0
8599 10:56:07.781673 7, 0xFFFF, sum = 0
8600 10:56:07.781725 8, 0xFFFF, sum = 0
8601 10:56:07.781777 9, 0xFFFF, sum = 0
8602 10:56:07.781830 10, 0xFFFF, sum = 0
8603 10:56:07.781883 11, 0xFFFF, sum = 0
8604 10:56:07.781935 12, 0xFFFF, sum = 0
8605 10:56:07.781986 13, 0x8FFF, sum = 0
8606 10:56:07.782038 14, 0x0, sum = 1
8607 10:56:07.782090 15, 0x0, sum = 2
8608 10:56:07.782143 16, 0x0, sum = 3
8609 10:56:07.782195 17, 0x0, sum = 4
8610 10:56:07.782247 best_step = 15
8611 10:56:07.782298
8612 10:56:07.782349 ==
8613 10:56:07.782401 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 10:56:07.782453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 10:56:07.782505 ==
8616 10:56:07.782557 RX Vref Scan: 1
8617 10:56:07.782608
8618 10:56:07.782659 Set Vref Range= 24 -> 127
8619 10:56:07.782710
8620 10:56:07.782762 RX Vref 24 -> 127, step: 1
8621 10:56:07.782813
8622 10:56:07.782899 RX Delay 11 -> 252, step: 4
8623 10:56:07.782951
8624 10:56:07.783003 Set Vref, RX VrefLevel [Byte0]: 24
8625 10:56:07.783055 [Byte1]: 24
8626 10:56:07.783128
8627 10:56:07.783182 Set Vref, RX VrefLevel [Byte0]: 25
8628 10:56:07.783234 [Byte1]: 25
8629 10:56:07.783300
8630 10:56:07.783361 Set Vref, RX VrefLevel [Byte0]: 26
8631 10:56:07.783413 [Byte1]: 26
8632 10:56:07.783465
8633 10:56:07.783517 Set Vref, RX VrefLevel [Byte0]: 27
8634 10:56:07.783569 [Byte1]: 27
8635 10:56:07.783622
8636 10:56:07.783674 Set Vref, RX VrefLevel [Byte0]: 28
8637 10:56:07.783725 [Byte1]: 28
8638 10:56:07.783777
8639 10:56:07.783829 Set Vref, RX VrefLevel [Byte0]: 29
8640 10:56:07.783881 [Byte1]: 29
8641 10:56:07.783933
8642 10:56:07.783984 Set Vref, RX VrefLevel [Byte0]: 30
8643 10:56:07.784036 [Byte1]: 30
8644 10:56:07.784087
8645 10:56:07.784139 Set Vref, RX VrefLevel [Byte0]: 31
8646 10:56:07.784191 [Byte1]: 31
8647 10:56:07.784242
8648 10:56:07.784294 Set Vref, RX VrefLevel [Byte0]: 32
8649 10:56:07.784531 [Byte1]: 32
8650 10:56:07.784589
8651 10:56:07.784642 Set Vref, RX VrefLevel [Byte0]: 33
8652 10:56:07.784694 [Byte1]: 33
8653 10:56:07.784747
8654 10:56:07.784798 Set Vref, RX VrefLevel [Byte0]: 34
8655 10:56:07.784849 [Byte1]: 34
8656 10:56:07.784901
8657 10:56:07.784952 Set Vref, RX VrefLevel [Byte0]: 35
8658 10:56:07.785004 [Byte1]: 35
8659 10:56:07.785056
8660 10:56:07.785108 Set Vref, RX VrefLevel [Byte0]: 36
8661 10:56:07.785160 [Byte1]: 36
8662 10:56:07.785211
8663 10:56:07.785262 Set Vref, RX VrefLevel [Byte0]: 37
8664 10:56:07.785314 [Byte1]: 37
8665 10:56:07.785365
8666 10:56:07.785416 Set Vref, RX VrefLevel [Byte0]: 38
8667 10:56:07.785468 [Byte1]: 38
8668 10:56:07.785520
8669 10:56:07.785582 Set Vref, RX VrefLevel [Byte0]: 39
8670 10:56:07.785641 [Byte1]: 39
8671 10:56:07.785693
8672 10:56:07.785745 Set Vref, RX VrefLevel [Byte0]: 40
8673 10:56:07.785823 [Byte1]: 40
8674 10:56:07.785878
8675 10:56:07.785929 Set Vref, RX VrefLevel [Byte0]: 41
8676 10:56:07.785982 [Byte1]: 41
8677 10:56:07.786035
8678 10:56:07.786088 Set Vref, RX VrefLevel [Byte0]: 42
8679 10:56:07.786140 [Byte1]: 42
8680 10:56:07.786191
8681 10:56:07.786243 Set Vref, RX VrefLevel [Byte0]: 43
8682 10:56:07.786295 [Byte1]: 43
8683 10:56:07.786360
8684 10:56:07.786416 Set Vref, RX VrefLevel [Byte0]: 44
8685 10:56:07.786468 [Byte1]: 44
8686 10:56:07.786523
8687 10:56:07.786587 Set Vref, RX VrefLevel [Byte0]: 45
8688 10:56:07.786640 [Byte1]: 45
8689 10:56:07.786692
8690 10:56:07.786770 Set Vref, RX VrefLevel [Byte0]: 46
8691 10:56:07.786832 [Byte1]: 46
8692 10:56:07.786920
8693 10:56:07.786985 Set Vref, RX VrefLevel [Byte0]: 47
8694 10:56:07.787037 [Byte1]: 47
8695 10:56:07.787090
8696 10:56:07.787185 Set Vref, RX VrefLevel [Byte0]: 48
8697 10:56:07.787268 [Byte1]: 48
8698 10:56:07.787351
8699 10:56:07.787432 Set Vref, RX VrefLevel [Byte0]: 49
8700 10:56:07.787514 [Byte1]: 49
8701 10:56:07.787601
8702 10:56:07.787683 Set Vref, RX VrefLevel [Byte0]: 50
8703 10:56:07.787774 [Byte1]: 50
8704 10:56:07.787831
8705 10:56:07.787883 Set Vref, RX VrefLevel [Byte0]: 51
8706 10:56:07.787952 [Byte1]: 51
8707 10:56:07.788039
8708 10:56:07.788125 Set Vref, RX VrefLevel [Byte0]: 52
8709 10:56:07.788188 [Byte1]: 52
8710 10:56:07.788241
8711 10:56:07.788294 Set Vref, RX VrefLevel [Byte0]: 53
8712 10:56:07.788379 [Byte1]: 53
8713 10:56:07.788434
8714 10:56:07.788487 Set Vref, RX VrefLevel [Byte0]: 54
8715 10:56:07.788543 [Byte1]: 54
8716 10:56:07.788595
8717 10:56:07.788648 Set Vref, RX VrefLevel [Byte0]: 55
8718 10:56:07.788700 [Byte1]: 55
8719 10:56:07.788753
8720 10:56:07.788805 Set Vref, RX VrefLevel [Byte0]: 56
8721 10:56:07.788857 [Byte1]: 56
8722 10:56:07.788909
8723 10:56:07.788961 Set Vref, RX VrefLevel [Byte0]: 57
8724 10:56:07.789013 [Byte1]: 57
8725 10:56:07.789065
8726 10:56:07.789117 Set Vref, RX VrefLevel [Byte0]: 58
8727 10:56:07.789169 [Byte1]: 58
8728 10:56:07.789220
8729 10:56:07.789271 Set Vref, RX VrefLevel [Byte0]: 59
8730 10:56:07.789323 [Byte1]: 59
8731 10:56:07.789374
8732 10:56:07.789426 Set Vref, RX VrefLevel [Byte0]: 60
8733 10:56:07.789477 [Byte1]: 60
8734 10:56:07.789529
8735 10:56:07.789580 Set Vref, RX VrefLevel [Byte0]: 61
8736 10:56:07.789631 [Byte1]: 61
8737 10:56:07.789683
8738 10:56:07.789734 Set Vref, RX VrefLevel [Byte0]: 62
8739 10:56:07.789786 [Byte1]: 62
8740 10:56:07.789837
8741 10:56:07.789889 Set Vref, RX VrefLevel [Byte0]: 63
8742 10:56:07.789940 [Byte1]: 63
8743 10:56:07.789992
8744 10:56:07.790043 Set Vref, RX VrefLevel [Byte0]: 64
8745 10:56:07.790094 [Byte1]: 64
8746 10:56:07.790145
8747 10:56:07.790197 Set Vref, RX VrefLevel [Byte0]: 65
8748 10:56:07.790248 [Byte1]: 65
8749 10:56:07.790304
8750 10:56:07.790357 Set Vref, RX VrefLevel [Byte0]: 66
8751 10:56:07.790408 [Byte1]: 66
8752 10:56:07.790460
8753 10:56:07.790512 Set Vref, RX VrefLevel [Byte0]: 67
8754 10:56:07.790564 [Byte1]: 67
8755 10:56:07.790615
8756 10:56:07.790666 Set Vref, RX VrefLevel [Byte0]: 68
8757 10:56:07.790718 [Byte1]: 68
8758 10:56:07.790769
8759 10:56:07.790820 Set Vref, RX VrefLevel [Byte0]: 69
8760 10:56:07.790918 [Byte1]: 69
8761 10:56:07.790972
8762 10:56:07.791023 Set Vref, RX VrefLevel [Byte0]: 70
8763 10:56:07.791076 [Byte1]: 70
8764 10:56:07.791128
8765 10:56:07.791179 Set Vref, RX VrefLevel [Byte0]: 71
8766 10:56:07.791231 [Byte1]: 71
8767 10:56:07.791283
8768 10:56:07.791334 Set Vref, RX VrefLevel [Byte0]: 72
8769 10:56:07.791386 [Byte1]: 72
8770 10:56:07.791438
8771 10:56:07.791489 Set Vref, RX VrefLevel [Byte0]: 73
8772 10:56:07.791541 [Byte1]: 73
8773 10:56:07.791593
8774 10:56:07.791644 Final RX Vref Byte 0 = 55 to rank0
8775 10:56:07.791696 Final RX Vref Byte 1 = 54 to rank0
8776 10:56:07.791749 Final RX Vref Byte 0 = 55 to rank1
8777 10:56:07.791800 Final RX Vref Byte 1 = 54 to rank1==
8778 10:56:07.791852 Dram Type= 6, Freq= 0, CH_1, rank 0
8779 10:56:07.791904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 10:56:07.791957 ==
8781 10:56:07.792009 DQS Delay:
8782 10:56:07.792061 DQS0 = 0, DQS1 = 0
8783 10:56:07.792113 DQM Delay:
8784 10:56:07.792165 DQM0 = 130, DQM1 = 123
8785 10:56:07.792216 DQ Delay:
8786 10:56:07.792268 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =126
8787 10:56:07.792319 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8788 10:56:07.792371 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8789 10:56:07.792423 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8790 10:56:07.792475
8791 10:56:07.792527
8792 10:56:07.792578
8793 10:56:07.792630 [DramC_TX_OE_Calibration] TA2
8794 10:56:07.792681 Original DQ_B0 (3 6) =30, OEN = 27
8795 10:56:07.792734 Original DQ_B1 (3 6) =30, OEN = 27
8796 10:56:07.792786 24, 0x0, End_B0=24 End_B1=24
8797 10:56:07.792839 25, 0x0, End_B0=25 End_B1=25
8798 10:56:07.792892 26, 0x0, End_B0=26 End_B1=26
8799 10:56:07.792944 27, 0x0, End_B0=27 End_B1=27
8800 10:56:07.792996 28, 0x0, End_B0=28 End_B1=28
8801 10:56:07.793049 29, 0x0, End_B0=29 End_B1=29
8802 10:56:07.793101 30, 0x0, End_B0=30 End_B1=30
8803 10:56:07.793155 31, 0x4141, End_B0=30 End_B1=30
8804 10:56:07.793208 Byte0 end_step=30 best_step=27
8805 10:56:07.793260 Byte1 end_step=30 best_step=27
8806 10:56:07.793312 Byte0 TX OE(2T, 0.5T) = (3, 3)
8807 10:56:07.793548 Byte1 TX OE(2T, 0.5T) = (3, 3)
8808 10:56:07.793605
8809 10:56:07.793657
8810 10:56:07.793709 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8811 10:56:07.793763 CH1 RK0: MR19=303, MR18=80D
8812 10:56:07.793815 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8813 10:56:07.793867
8814 10:56:07.793919 ----->DramcWriteLeveling(PI) begin...
8815 10:56:07.793972 ==
8816 10:56:07.794024 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 10:56:07.794075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 10:56:07.794127 ==
8819 10:56:07.794179 Write leveling (Byte 0): 24 => 24
8820 10:56:07.794230 Write leveling (Byte 1): 29 => 29
8821 10:56:07.794282 DramcWriteLeveling(PI) end<-----
8822 10:56:07.794333
8823 10:56:07.794385 ==
8824 10:56:07.794437 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 10:56:07.794488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 10:56:07.794540 ==
8827 10:56:07.794592 [Gating] SW mode calibration
8828 10:56:07.794644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8829 10:56:07.794696 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8830 10:56:07.794748 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 10:56:07.794801 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8832 10:56:07.794882 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8833 10:56:07.794980 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 10:56:07.795032 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 10:56:07.795085 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 10:56:07.795137 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 10:56:07.795189 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 10:56:07.795241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 10:56:07.795292 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 10:56:07.795344 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8841 10:56:07.795397 1 5 12 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (1 0)
8842 10:56:07.795449 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 10:56:07.795501 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 10:56:07.795553 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 10:56:07.795606 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 10:56:07.795658 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 10:56:07.795710 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8848 10:56:07.795762 1 6 8 | B1->B0 | 2727 4141 | 0 0 | (0 0) (0 0)
8849 10:56:07.795815 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8850 10:56:07.795867 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 10:56:07.795919 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 10:56:07.795971 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 10:56:07.796024 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 10:56:07.796076 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 10:56:07.796128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 10:56:07.796180 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8857 10:56:07.796232 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8858 10:56:07.796285 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 10:56:07.796336 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 10:56:07.796388 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 10:56:07.796440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 10:56:07.796492 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 10:56:07.796545 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 10:56:07.796597 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 10:56:07.796649 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 10:56:07.796701 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 10:56:07.796753 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 10:56:07.796805 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 10:56:07.796857 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 10:56:07.796909 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 10:56:07.796961 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 10:56:07.797013 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8873 10:56:07.797065 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8874 10:56:07.797118 Total UI for P1: 0, mck2ui 16
8875 10:56:07.797170 best dqsien dly found for B0: ( 1, 9, 8)
8876 10:56:07.797222 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 10:56:07.797274 Total UI for P1: 0, mck2ui 16
8878 10:56:07.797326 best dqsien dly found for B1: ( 1, 9, 12)
8879 10:56:07.797378 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8880 10:56:07.797429 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8881 10:56:07.797481
8882 10:56:07.797533 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8883 10:56:07.797586 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8884 10:56:07.797638 [Gating] SW calibration Done
8885 10:56:07.797690 ==
8886 10:56:07.797742 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 10:56:07.797794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 10:56:07.797847 ==
8889 10:56:07.797899 RX Vref Scan: 0
8890 10:56:07.797951
8891 10:56:07.798002 RX Vref 0 -> 0, step: 1
8892 10:56:07.798054
8893 10:56:07.798106 RX Delay 0 -> 252, step: 8
8894 10:56:07.798158 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8895 10:56:07.798210 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8896 10:56:07.798261 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8897 10:56:07.798314 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8898 10:56:07.798366 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8899 10:56:07.798418 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8900 10:56:07.798469 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8901 10:56:07.798521 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8902 10:56:07.798572 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8903 10:56:07.798624 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8904 10:56:07.798676 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8905 10:56:07.798909 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8906 10:56:07.798968 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8907 10:56:07.799021 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8908 10:56:07.799074 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8909 10:56:07.799125 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8910 10:56:07.799177 ==
8911 10:56:07.799229 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 10:56:07.799283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 10:56:07.799336 ==
8914 10:56:07.799388 DQS Delay:
8915 10:56:07.799440 DQS0 = 0, DQS1 = 0
8916 10:56:07.799491 DQM Delay:
8917 10:56:07.799543 DQM0 = 128, DQM1 = 127
8918 10:56:07.799595 DQ Delay:
8919 10:56:07.799647 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8920 10:56:07.799699 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8921 10:56:07.799751 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8922 10:56:07.799803 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8923 10:56:07.799855
8924 10:56:07.799907
8925 10:56:07.799958 ==
8926 10:56:07.800010 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 10:56:07.800062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 10:56:07.800115 ==
8929 10:56:07.800167
8930 10:56:07.800218
8931 10:56:07.800270 TX Vref Scan disable
8932 10:56:07.800322 == TX Byte 0 ==
8933 10:56:07.800374 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8934 10:56:07.800427 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8935 10:56:07.800479 == TX Byte 1 ==
8936 10:56:07.800531 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8937 10:56:07.800583 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8938 10:56:07.800635 ==
8939 10:56:07.800687 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 10:56:07.800739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 10:56:07.800792 ==
8942 10:56:07.800843
8943 10:56:07.800895 TX Vref early break, caculate TX vref
8944 10:56:07.800947 TX Vref=16, minBit 8, minWin=22, winSum=380
8945 10:56:07.801000 TX Vref=18, minBit 0, minWin=23, winSum=387
8946 10:56:07.801052 TX Vref=20, minBit 0, minWin=22, winSum=393
8947 10:56:07.801104 TX Vref=22, minBit 0, minWin=24, winSum=404
8948 10:56:07.801156 TX Vref=24, minBit 0, minWin=25, winSum=413
8949 10:56:07.801208 TX Vref=26, minBit 0, minWin=24, winSum=414
8950 10:56:07.801260 TX Vref=28, minBit 5, minWin=25, winSum=422
8951 10:56:07.801312 TX Vref=30, minBit 8, minWin=24, winSum=416
8952 10:56:07.801364 TX Vref=32, minBit 8, minWin=23, winSum=409
8953 10:56:07.801417 TX Vref=34, minBit 5, minWin=23, winSum=398
8954 10:56:07.801470 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 28
8955 10:56:07.801523
8956 10:56:07.801574 Final TX Range 0 Vref 28
8957 10:56:07.801626
8958 10:56:07.801678 ==
8959 10:56:07.801730 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 10:56:07.801782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 10:56:07.801834 ==
8962 10:56:07.801886
8963 10:56:07.801937
8964 10:56:07.801988 TX Vref Scan disable
8965 10:56:07.802040 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8966 10:56:07.802092 == TX Byte 0 ==
8967 10:56:07.802144 u2DelayCellOfst[0]=18 cells (5 PI)
8968 10:56:07.802196 u2DelayCellOfst[1]=18 cells (5 PI)
8969 10:56:07.802247 u2DelayCellOfst[2]=0 cells (0 PI)
8970 10:56:07.802299 u2DelayCellOfst[3]=7 cells (2 PI)
8971 10:56:07.802351 u2DelayCellOfst[4]=11 cells (3 PI)
8972 10:56:07.802403 u2DelayCellOfst[5]=26 cells (7 PI)
8973 10:56:07.802455 u2DelayCellOfst[6]=22 cells (6 PI)
8974 10:56:07.802507 u2DelayCellOfst[7]=7 cells (2 PI)
8975 10:56:07.802559 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8976 10:56:07.802611 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8977 10:56:07.802663 == TX Byte 1 ==
8978 10:56:07.802715 u2DelayCellOfst[8]=0 cells (0 PI)
8979 10:56:07.802767 u2DelayCellOfst[9]=11 cells (3 PI)
8980 10:56:07.802819 u2DelayCellOfst[10]=15 cells (4 PI)
8981 10:56:07.802913 u2DelayCellOfst[11]=7 cells (2 PI)
8982 10:56:07.802965 u2DelayCellOfst[12]=18 cells (5 PI)
8983 10:56:07.803017 u2DelayCellOfst[13]=18 cells (5 PI)
8984 10:56:07.803069 u2DelayCellOfst[14]=22 cells (6 PI)
8985 10:56:07.803121 u2DelayCellOfst[15]=18 cells (5 PI)
8986 10:56:07.803172 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8987 10:56:07.803224 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8988 10:56:07.803276 DramC Write-DBI on
8989 10:56:07.803327 ==
8990 10:56:07.803380 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 10:56:07.803432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 10:56:07.803485 ==
8993 10:56:08.163925
8994 10:56:08.164066
8995 10:56:08.164161 TX Vref Scan disable
8996 10:56:08.164222 == TX Byte 0 ==
8997 10:56:08.164281 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8998 10:56:08.164338 == TX Byte 1 ==
8999 10:56:08.164393 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9000 10:56:08.164448 DramC Write-DBI off
9001 10:56:08.164502
9002 10:56:08.164555 [DATLAT]
9003 10:56:08.164607 Freq=1600, CH1 RK1
9004 10:56:08.164661
9005 10:56:08.164713 DATLAT Default: 0xf
9006 10:56:08.164765 0, 0xFFFF, sum = 0
9007 10:56:08.164818 1, 0xFFFF, sum = 0
9008 10:56:08.164872 2, 0xFFFF, sum = 0
9009 10:56:08.164925 3, 0xFFFF, sum = 0
9010 10:56:08.164979 4, 0xFFFF, sum = 0
9011 10:56:08.165032 5, 0xFFFF, sum = 0
9012 10:56:08.165085 6, 0xFFFF, sum = 0
9013 10:56:08.165138 7, 0xFFFF, sum = 0
9014 10:56:08.165190 8, 0xFFFF, sum = 0
9015 10:56:08.165265 9, 0xFFFF, sum = 0
9016 10:56:08.165320 10, 0xFFFF, sum = 0
9017 10:56:08.165374 11, 0xFFFF, sum = 0
9018 10:56:08.165428 12, 0xFFFF, sum = 0
9019 10:56:08.165480 13, 0x8FFF, sum = 0
9020 10:56:08.165533 14, 0x0, sum = 1
9021 10:56:08.165586 15, 0x0, sum = 2
9022 10:56:08.165639 16, 0x0, sum = 3
9023 10:56:08.165692 17, 0x0, sum = 4
9024 10:56:08.165745 best_step = 15
9025 10:56:08.165797
9026 10:56:08.165849 ==
9027 10:56:08.165901 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 10:56:08.165953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 10:56:08.166006 ==
9030 10:56:08.166058 RX Vref Scan: 0
9031 10:56:08.166110
9032 10:56:08.166161 RX Vref 0 -> 0, step: 1
9033 10:56:08.166213
9034 10:56:08.166264 RX Delay 3 -> 252, step: 4
9035 10:56:08.166316 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9036 10:56:08.166368 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9037 10:56:08.166419 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9038 10:56:08.166471 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9039 10:56:08.166523 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9040 10:56:08.166575 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9041 10:56:08.166627 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9042 10:56:08.166679 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
9043 10:56:08.166731 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9044 10:56:08.166782 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9045 10:56:08.166842 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9046 10:56:08.166926 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9047 10:56:08.166978 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9048 10:56:08.167029 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9049 10:56:08.167278 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9050 10:56:08.167336 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9051 10:56:08.167389 ==
9052 10:56:08.167442 Dram Type= 6, Freq= 0, CH_1, rank 1
9053 10:56:08.167495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9054 10:56:08.167547 ==
9055 10:56:08.167599 DQS Delay:
9056 10:56:08.167651 DQS0 = 0, DQS1 = 0
9057 10:56:08.167702 DQM Delay:
9058 10:56:08.167754 DQM0 = 127, DQM1 = 124
9059 10:56:08.167805 DQ Delay:
9060 10:56:08.167856 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =124
9061 10:56:08.167908 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9062 10:56:08.167959 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
9063 10:56:08.168012 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
9064 10:56:08.168064
9065 10:56:08.168115
9066 10:56:08.168166
9067 10:56:08.168217 [DramC_TX_OE_Calibration] TA2
9068 10:56:08.168269 Original DQ_B0 (3 6) =30, OEN = 27
9069 10:56:08.168321 Original DQ_B1 (3 6) =30, OEN = 27
9070 10:56:08.168373 24, 0x0, End_B0=24 End_B1=24
9071 10:56:08.168425 25, 0x0, End_B0=25 End_B1=25
9072 10:56:08.168477 26, 0x0, End_B0=26 End_B1=26
9073 10:56:08.168529 27, 0x0, End_B0=27 End_B1=27
9074 10:56:08.168602 28, 0x0, End_B0=28 End_B1=28
9075 10:56:08.168657 29, 0x0, End_B0=29 End_B1=29
9076 10:56:08.168710 30, 0x0, End_B0=30 End_B1=30
9077 10:56:08.168764 31, 0x4141, End_B0=30 End_B1=30
9078 10:56:08.168818 Byte0 end_step=30 best_step=27
9079 10:56:08.168870 Byte1 end_step=30 best_step=27
9080 10:56:08.168921 Byte0 TX OE(2T, 0.5T) = (3, 3)
9081 10:56:08.168973 Byte1 TX OE(2T, 0.5T) = (3, 3)
9082 10:56:08.169025
9083 10:56:08.169077
9084 10:56:08.169129 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9085 10:56:08.169182 CH1 RK1: MR19=303, MR18=E1B
9086 10:56:08.169233 CH1_RK1: MR19=0x303, MR18=0xE1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9087 10:56:08.169285 [RxdqsGatingPostProcess] freq 1600
9088 10:56:08.169338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9089 10:56:08.169390 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 10:56:08.169442 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 10:56:08.169494 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 10:56:08.169546 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 10:56:08.169598 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 10:56:08.169650 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 10:56:08.169701 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 10:56:08.169753 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 10:56:08.169807 Pre-setting of DQS Precalculation
9098 10:56:08.169860 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9099 10:56:08.169913 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9100 10:56:08.169966 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 10:56:08.170020
9102 10:56:08.170072
9103 10:56:08.170125 [Calibration Summary] 3200 Mbps
9104 10:56:08.170177 CH 0, Rank 0
9105 10:56:08.170231 SW Impedance : PASS
9106 10:56:08.170284 DUTY Scan : NO K
9107 10:56:08.170337 ZQ Calibration : PASS
9108 10:56:08.170390 Jitter Meter : NO K
9109 10:56:08.170443 CBT Training : PASS
9110 10:56:08.170497 Write leveling : PASS
9111 10:56:08.170551 RX DQS gating : PASS
9112 10:56:08.170604 RX DQ/DQS(RDDQC) : PASS
9113 10:56:08.170658 TX DQ/DQS : PASS
9114 10:56:08.170712 RX DATLAT : PASS
9115 10:56:08.170765 RX DQ/DQS(Engine): PASS
9116 10:56:08.170818 TX OE : PASS
9117 10:56:08.170915 All Pass.
9118 10:56:08.170970
9119 10:56:08.171024 CH 0, Rank 1
9120 10:56:08.171077 SW Impedance : PASS
9121 10:56:08.171131 DUTY Scan : NO K
9122 10:56:08.171185 ZQ Calibration : PASS
9123 10:56:08.171239 Jitter Meter : NO K
9124 10:56:08.171292 CBT Training : PASS
9125 10:56:08.171345 Write leveling : PASS
9126 10:56:08.171399 RX DQS gating : PASS
9127 10:56:08.171452 RX DQ/DQS(RDDQC) : PASS
9128 10:56:08.171505 TX DQ/DQS : PASS
9129 10:56:08.171558 RX DATLAT : PASS
9130 10:56:08.171611 RX DQ/DQS(Engine): PASS
9131 10:56:08.171684 TX OE : PASS
9132 10:56:08.171741 All Pass.
9133 10:56:08.171794
9134 10:56:08.171848 CH 1, Rank 0
9135 10:56:08.171901 SW Impedance : PASS
9136 10:56:08.171954 DUTY Scan : NO K
9137 10:56:08.172008 ZQ Calibration : PASS
9138 10:56:08.172061 Jitter Meter : NO K
9139 10:56:08.172114 CBT Training : PASS
9140 10:56:08.172167 Write leveling : PASS
9141 10:56:08.172220 RX DQS gating : PASS
9142 10:56:08.172272 RX DQ/DQS(RDDQC) : PASS
9143 10:56:08.172326 TX DQ/DQS : PASS
9144 10:56:08.172379 RX DATLAT : PASS
9145 10:56:08.172432 RX DQ/DQS(Engine): PASS
9146 10:56:08.172485 TX OE : PASS
9147 10:56:08.172538 All Pass.
9148 10:56:08.172591
9149 10:56:08.172643 CH 1, Rank 1
9150 10:56:08.172697 SW Impedance : PASS
9151 10:56:08.172751 DUTY Scan : NO K
9152 10:56:08.172804 ZQ Calibration : PASS
9153 10:56:08.172857 Jitter Meter : NO K
9154 10:56:08.172910 CBT Training : PASS
9155 10:56:08.172979 Write leveling : PASS
9156 10:56:08.173037 RX DQS gating : PASS
9157 10:56:08.173092 RX DQ/DQS(RDDQC) : PASS
9158 10:56:08.173147 TX DQ/DQS : PASS
9159 10:56:08.173226 RX DATLAT : PASS
9160 10:56:08.173282 RX DQ/DQS(Engine): PASS
9161 10:56:08.173336 TX OE : PASS
9162 10:56:08.173390 All Pass.
9163 10:56:08.173443
9164 10:56:08.173496 DramC Write-DBI on
9165 10:56:08.173550 PER_BANK_REFRESH: Hybrid Mode
9166 10:56:08.173603 TX_TRACKING: ON
9167 10:56:08.173657 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9168 10:56:08.173712 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9169 10:56:08.173788 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9170 10:56:08.173845 [FAST_K] Save calibration result to emmc
9171 10:56:08.173899 sync common calibartion params.
9172 10:56:08.173968 sync cbt_mode0:1, 1:1
9173 10:56:08.174024 dram_init: ddr_geometry: 2
9174 10:56:08.174078 dram_init: ddr_geometry: 2
9175 10:56:08.174131 dram_init: ddr_geometry: 2
9176 10:56:08.174185 0:dram_rank_size:100000000
9177 10:56:08.174240 1:dram_rank_size:100000000
9178 10:56:08.174295 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9179 10:56:08.174375 DFS_SHUFFLE_HW_MODE: ON
9180 10:56:08.174432 dramc_set_vcore_voltage set vcore to 725000
9181 10:56:08.174487 Read voltage for 1600, 0
9182 10:56:08.174556 Vio18 = 0
9183 10:56:08.174612 Vcore = 725000
9184 10:56:08.174667 Vdram = 0
9185 10:56:08.174720 Vddq = 0
9186 10:56:08.174774 Vmddr = 0
9187 10:56:08.174891 switch to 3200 Mbps bootup
9188 10:56:08.174948 [DramcRunTimeConfig]
9189 10:56:08.175001 PHYPLL
9190 10:56:08.175055 DPM_CONTROL_AFTERK: ON
9191 10:56:08.175109 PER_BANK_REFRESH: ON
9192 10:56:08.175162 REFRESH_OVERHEAD_REDUCTION: ON
9193 10:56:08.175216 CMD_PICG_NEW_MODE: OFF
9194 10:56:08.175269 XRTWTW_NEW_MODE: ON
9195 10:56:08.175509 XRTRTR_NEW_MODE: ON
9196 10:56:08.175572 TX_TRACKING: ON
9197 10:56:08.175644 RDSEL_TRACKING: OFF
9198 10:56:08.175701 DQS Precalculation for DVFS: ON
9199 10:56:08.175755 RX_TRACKING: OFF
9200 10:56:08.175809 HW_GATING DBG: ON
9201 10:56:08.175863 ZQCS_ENABLE_LP4: ON
9202 10:56:08.175917 RX_PICG_NEW_MODE: ON
9203 10:56:08.175970 TX_PICG_NEW_MODE: ON
9204 10:56:08.176024 ENABLE_RX_DCM_DPHY: ON
9205 10:56:08.176077 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9206 10:56:08.176131 DUMMY_READ_FOR_TRACKING: OFF
9207 10:56:08.176184 !!! SPM_CONTROL_AFTERK: OFF
9208 10:56:08.176245 !!! SPM could not control APHY
9209 10:56:08.176299 IMPEDANCE_TRACKING: ON
9210 10:56:08.176353 TEMP_SENSOR: ON
9211 10:56:08.176427 HW_SAVE_FOR_SR: OFF
9212 10:56:08.176482 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9213 10:56:08.176536 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9214 10:56:08.176612 Read ODT Tracking: ON
9215 10:56:08.176669 Refresh Rate DeBounce: ON
9216 10:56:08.176724 DFS_NO_QUEUE_FLUSH: ON
9217 10:56:08.176795 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9218 10:56:08.176852 ENABLE_DFS_RUNTIME_MRW: OFF
9219 10:56:08.176906 DDR_RESERVE_NEW_MODE: ON
9220 10:56:08.176973 MR_CBT_SWITCH_FREQ: ON
9221 10:56:08.177039 =========================
9222 10:56:08.177093 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9223 10:56:08.177157 dram_init: ddr_geometry: 2
9224 10:56:08.177234 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9225 10:56:08.177290 dram_init: dram init end (result: 0)
9226 10:56:08.177353 DRAM-K: Full calibration passed in 24561 msecs
9227 10:56:08.177446 MRC: failed to locate region type 0.
9228 10:56:08.177533 DRAM rank0 size:0x100000000,
9229 10:56:08.177620 DRAM rank1 size=0x100000000
9230 10:56:08.177705 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9231 10:56:08.177805 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9232 10:56:08.177891 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9233 10:56:08.177986 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9234 10:56:08.178070 DRAM rank0 size:0x100000000,
9235 10:56:08.178156 DRAM rank1 size=0x100000000
9236 10:56:08.178213 CBMEM:
9237 10:56:08.178268 IMD: root @ 0xfffff000 254 entries.
9238 10:56:08.178326 IMD: root @ 0xffffec00 62 entries.
9239 10:56:08.178380 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9240 10:56:08.178435 WARNING: RO_VPD is uninitialized or empty.
9241 10:56:08.178494 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9242 10:56:08.178570 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9243 10:56:08.178626 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9244 10:56:08.178705 BS: romstage times (exec / console): total (unknown) / 24027 ms
9245 10:56:08.178790
9246 10:56:08.178921
9247 10:56:08.179008 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9248 10:56:08.179095 ARM64: Exception handlers installed.
9249 10:56:08.179164 ARM64: Testing exception
9250 10:56:08.179219 ARM64: Done test exception
9251 10:56:08.179273 Enumerating buses...
9252 10:56:08.179327 Show all devs... Before device enumeration.
9253 10:56:08.179381 Root Device: enabled 1
9254 10:56:08.179435 CPU_CLUSTER: 0: enabled 1
9255 10:56:08.179489 CPU: 00: enabled 1
9256 10:56:08.179542 Compare with tree...
9257 10:56:08.179595 Root Device: enabled 1
9258 10:56:08.179649 CPU_CLUSTER: 0: enabled 1
9259 10:56:08.179702 CPU: 00: enabled 1
9260 10:56:08.179756 Root Device scanning...
9261 10:56:08.179830 scan_static_bus for Root Device
9262 10:56:08.179889 CPU_CLUSTER: 0 enabled
9263 10:56:08.179943 scan_static_bus for Root Device done
9264 10:56:08.180011 scan_bus: bus Root Device finished in 8 msecs
9265 10:56:08.180069 done
9266 10:56:08.180123 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9267 10:56:08.180178 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9268 10:56:08.180236 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9269 10:56:08.180291 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9270 10:56:08.180345 Allocating resources...
9271 10:56:08.180399 Reading resources...
9272 10:56:08.180452 Root Device read_resources bus 0 link: 0
9273 10:56:08.180507 DRAM rank0 size:0x100000000,
9274 10:56:08.180584 DRAM rank1 size=0x100000000
9275 10:56:08.180640 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9276 10:56:08.180693 CPU: 00 missing read_resources
9277 10:56:08.180764 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9278 10:56:08.180820 Root Device read_resources bus 0 link: 0 done
9279 10:56:08.180874 Done reading resources.
9280 10:56:08.180952 Show resources in subtree (Root Device)...After reading.
9281 10:56:08.181010 Root Device child on link 0 CPU_CLUSTER: 0
9282 10:56:08.181064 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 10:56:08.181122 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 10:56:08.181178 CPU: 00
9285 10:56:08.181232 Root Device assign_resources, bus 0 link: 0
9286 10:56:08.181286 CPU_CLUSTER: 0 missing set_resources
9287 10:56:08.181339 Root Device assign_resources, bus 0 link: 0 done
9288 10:56:08.181393 Done setting resources.
9289 10:56:08.181447 Show resources in subtree (Root Device)...After assigning values.
9290 10:56:08.181501 Root Device child on link 0 CPU_CLUSTER: 0
9291 10:56:08.181555 CPU_CLUSTER: 0 child on link 0 CPU: 00
9292 10:56:08.181609 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9293 10:56:08.181663 CPU: 00
9294 10:56:08.181717 Done allocating resources.
9295 10:56:08.181770 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9296 10:56:08.181824 Enabling resources...
9297 10:56:08.181900 done.
9298 10:56:08.181956 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9299 10:56:08.182011 Initializing devices...
9300 10:56:08.182066 Root Device init
9301 10:56:08.182154 init hardware done!
9302 10:56:08.182237 0x00000018: ctrlr->caps
9303 10:56:08.182326 52.000 MHz: ctrlr->f_max
9304 10:56:08.182412 0.400 MHz: ctrlr->f_min
9305 10:56:08.182691 0x40ff8080: ctrlr->voltages
9306 10:56:08.182782 sclk: 390625
9307 10:56:08.182878 Bus Width = 1
9308 10:56:08.182962 sclk: 390625
9309 10:56:08.183047 Bus Width = 1
9310 10:56:08.183131 Early init status = 3
9311 10:56:08.183215 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9312 10:56:08.183302 in-header: 03 fc 00 00 01 00 00 00
9313 10:56:08.183385 in-data: 00
9314 10:56:08.183460 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9315 10:56:08.183517 in-header: 03 fd 00 00 00 00 00 00
9316 10:56:08.183571 in-data:
9317 10:56:08.183636 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9318 10:56:08.183693 in-header: 03 fc 00 00 01 00 00 00
9319 10:56:08.183747 in-data: 00
9320 10:56:08.183805 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9321 10:56:08.183892 in-header: 03 fd 00 00 00 00 00 00
9322 10:56:08.183975 in-data:
9323 10:56:08.184065 [SSUSB] Setting up USB HOST controller...
9324 10:56:08.184148 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9325 10:56:08.184236 [SSUSB] phy power-on done.
9326 10:56:08.184324 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9327 10:56:08.184391 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9328 10:56:08.184449 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9329 10:56:08.184503 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9330 10:56:08.184558 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9331 10:56:08.184625 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9332 10:56:08.184681 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9333 10:56:08.184736 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9334 10:56:08.184793 SPM: binary array size = 0x9dc
9335 10:56:08.184848 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9336 10:56:08.184902 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9337 10:56:08.184980 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9338 10:56:08.185038 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9339 10:56:08.185092 configure_display: Starting display init
9340 10:56:08.185147 anx7625_power_on_init: Init interface.
9341 10:56:08.185210 anx7625_disable_pd_protocol: Disabled PD feature.
9342 10:56:08.185265 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9343 10:56:08.185319 anx7625_start_dp_work: Secure OCM version=00
9344 10:56:08.185381 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9345 10:56:08.185436 sp_tx_get_edid_block: EDID Block = 1
9346 10:56:08.185491 Extracted contents:
9347 10:56:08.185554 header: 00 ff ff ff ff ff ff 00
9348 10:56:08.185610 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9349 10:56:08.185664 version: 01 04
9350 10:56:08.185727 basic params: 95 1f 11 78 0a
9351 10:56:08.185785 chroma info: 76 90 94 55 54 90 27 21 50 54
9352 10:56:08.185839 established: 00 00 00
9353 10:56:08.185892 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9354 10:56:08.185958 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9355 10:56:08.186014 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 10:56:08.186068 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9357 10:56:08.186122 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9358 10:56:08.186177 extensions: 00
9359 10:56:08.186231 checksum: fb
9360 10:56:08.186283
9361 10:56:08.186335 Manufacturer: IVO Model 57d Serial Number 0
9362 10:56:08.186408 Made week 0 of 2020
9363 10:56:08.186462 EDID version: 1.4
9364 10:56:08.186515 Digital display
9365 10:56:08.186566 6 bits per primary color channel
9366 10:56:08.186619 DisplayPort interface
9367 10:56:08.186671 Maximum image size: 31 cm x 17 cm
9368 10:56:08.186723 Gamma: 220%
9369 10:56:08.186791 Check DPMS levels
9370 10:56:08.186902 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9371 10:56:08.186963 First detailed timing is preferred timing
9372 10:56:08.187019 Established timings supported:
9373 10:56:08.187072 Standard timings supported:
9374 10:56:08.187124 Detailed timings
9375 10:56:08.187185 Hex of detail: 383680a07038204018303c0035ae10000019
9376 10:56:08.187239 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9377 10:56:08.187291 0780 0798 07c8 0820 hborder 0
9378 10:56:08.187349 0438 043b 0447 0458 vborder 0
9379 10:56:08.187403 -hsync -vsync
9380 10:56:08.187455 Did detailed timing
9381 10:56:08.187507 Hex of detail: 000000000000000000000000000000000000
9382 10:56:08.187563 Manufacturer-specified data, tag 0
9383 10:56:08.187615 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9384 10:56:08.187667 ASCII string: InfoVision
9385 10:56:08.187724 Hex of detail: 000000fe00523134304e574635205248200a
9386 10:56:08.187778 ASCII string: R140NWF5 RH
9387 10:56:08.187830 Checksum
9388 10:56:08.187882 Checksum: 0xfb (valid)
9389 10:56:08.187943 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9390 10:56:08.188026 DSI data_rate: 832800000 bps
9391 10:56:08.188112 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9392 10:56:08.188195 anx7625_parse_edid: pixelclock(138800).
9393 10:56:08.188277 hactive(1920), hsync(48), hfp(24), hbp(88)
9394 10:56:08.188404 vactive(1080), vsync(12), vfp(3), vbp(17)
9395 10:56:08.188468 anx7625_dsi_config: config dsi.
9396 10:56:08.188531 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9397 10:56:08.188586 anx7625_dsi_config: success to config DSI
9398 10:56:08.188639 anx7625_dp_start: MIPI phy setup OK.
9399 10:56:08.188695 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9400 10:56:08.188748 mtk_ddp_mode_set invalid vrefresh 60
9401 10:56:08.188800 main_disp_path_setup
9402 10:56:08.188853 ovl_layer_smi_id_en
9403 10:56:08.188912 ovl_layer_smi_id_en
9404 10:56:08.188965 ccorr_config
9405 10:56:08.189017 aal_config
9406 10:56:08.189076 gamma_config
9407 10:56:08.189131 postmask_config
9408 10:56:08.189183 dither_config
9409 10:56:08.189234 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9410 10:56:08.189466 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9411 10:56:08.189526 Root Device init finished in 551 msecs
9412 10:56:08.189579 CPU_CLUSTER: 0 init
9413 10:56:08.189632 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9414 10:56:08.189686 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9415 10:56:08.189739 APU_MBOX 0x190000b0 = 0x10001
9416 10:56:08.189791 APU_MBOX 0x190001b0 = 0x10001
9417 10:56:08.189843 APU_MBOX 0x190005b0 = 0x10001
9418 10:56:08.189895 APU_MBOX 0x190006b0 = 0x10001
9419 10:56:08.189946 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9420 10:56:08.189999 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9421 10:56:08.190052 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9422 10:56:08.190105 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9423 10:56:08.190158 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9424 10:56:08.190211 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9425 10:56:08.190263 CPU_CLUSTER: 0 init finished in 81 msecs
9426 10:56:08.190315 Devices initialized
9427 10:56:08.190375 Show all devs... After init.
9428 10:56:08.190457 Root Device: enabled 1
9429 10:56:08.190561 CPU_CLUSTER: 0: enabled 1
9430 10:56:08.190615 CPU: 00: enabled 1
9431 10:56:08.190668 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9432 10:56:08.190721 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9433 10:56:08.190775 ELOG: NV offset 0x57f000 size 0x1000
9434 10:56:08.190842 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9435 10:56:08.190928 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9436 10:56:08.190981 ELOG: Event(17) added with size 13 at 2023-06-05 10:56:08 UTC
9437 10:56:08.191834 out: cmd=0x121: 03 db 21 01 00 00 00 00
9438 10:56:08.194543 in-header: 03 60 00 00 2c 00 00 00
9439 10:56:08.204556 in-data: ff 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9440 10:56:08.211294 ELOG: Event(A1) added with size 10 at 2023-06-05 10:56:08 UTC
9441 10:56:08.217927 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9442 10:56:08.224724 ELOG: Event(A0) added with size 9 at 2023-06-05 10:56:08 UTC
9443 10:56:08.227826 elog_add_boot_reason: Logged dev mode boot
9444 10:56:08.234631 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9445 10:56:08.234738 Finalize devices...
9446 10:56:08.237798 Devices finalized
9447 10:56:08.240898 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9448 10:56:08.244479 Writing coreboot table at 0xffe64000
9449 10:56:08.247437 0. 000000000010a000-0000000000113fff: RAMSTAGE
9450 10:56:08.254000 1. 0000000040000000-00000000400fffff: RAM
9451 10:56:08.256995 2. 0000000040100000-000000004032afff: RAMSTAGE
9452 10:56:08.260380 3. 000000004032b000-00000000545fffff: RAM
9453 10:56:08.264025 4. 0000000054600000-000000005465ffff: BL31
9454 10:56:08.266984 5. 0000000054660000-00000000ffe63fff: RAM
9455 10:56:08.273894 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9456 10:56:08.276911 7. 0000000100000000-000000023fffffff: RAM
9457 10:56:08.280064 Passing 5 GPIOs to payload:
9458 10:56:08.283835 NAME | PORT | POLARITY | VALUE
9459 10:56:08.289880 EC in RW | 0x000000aa | low | undefined
9460 10:56:08.293524 EC interrupt | 0x00000005 | low | undefined
9461 10:56:08.299846 TPM interrupt | 0x000000ab | high | undefined
9462 10:56:08.303386 SD card detect | 0x00000011 | high | undefined
9463 10:56:08.306748 speaker enable | 0x00000093 | high | undefined
9464 10:56:08.309615 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9465 10:56:08.313199 in-header: 03 f9 00 00 02 00 00 00
9466 10:56:08.316978 in-data: 02 00
9467 10:56:08.319963 ADC[4]: Raw value=894821 ID=7
9468 10:56:08.323703 ADC[3]: Raw value=212700 ID=1
9469 10:56:08.323787 RAM Code: 0x71
9470 10:56:08.326792 ADC[6]: Raw value=74722 ID=0
9471 10:56:08.329832 ADC[5]: Raw value=211590 ID=1
9472 10:56:08.329939 SKU Code: 0x1
9473 10:56:08.336733 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9474 10:56:08.336851 coreboot table: 964 bytes.
9475 10:56:08.339870 IMD ROOT 0. 0xfffff000 0x00001000
9476 10:56:08.343104 IMD SMALL 1. 0xffffe000 0x00001000
9477 10:56:08.346292 RO MCACHE 2. 0xffffc000 0x00001104
9478 10:56:08.349864 CONSOLE 3. 0xfff7c000 0x00080000
9479 10:56:08.352881 FMAP 4. 0xfff7b000 0x00000452
9480 10:56:08.356297 TIME STAMP 5. 0xfff7a000 0x00000910
9481 10:56:08.359754 VBOOT WORK 6. 0xfff66000 0x00014000
9482 10:56:08.362697 RAMOOPS 7. 0xffe66000 0x00100000
9483 10:56:08.365944 COREBOOT 8. 0xffe64000 0x00002000
9484 10:56:08.369175 IMD small region:
9485 10:56:08.372851 IMD ROOT 0. 0xffffec00 0x00000400
9486 10:56:08.375975 VPD 1. 0xffffeba0 0x0000004c
9487 10:56:08.379548 MMC STATUS 2. 0xffffeb80 0x00000004
9488 10:56:08.385913 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9489 10:56:08.385995 Probing TPM: done!
9490 10:56:08.392756 Connected to device vid:did:rid of 1ae0:0028:00
9491 10:56:08.399443 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9492 10:56:08.402444 Initialized TPM device CR50 revision 0
9493 10:56:08.406087 Checking cr50 for pending updates
9494 10:56:08.411660 Reading cr50 TPM mode
9495 10:56:08.420322 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9496 10:56:08.426787 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9497 10:56:08.466745 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9498 10:56:08.470275 Checking segment from ROM address 0x40100000
9499 10:56:08.473749 Checking segment from ROM address 0x4010001c
9500 10:56:08.479816 Loading segment from ROM address 0x40100000
9501 10:56:08.479925 code (compression=0)
9502 10:56:08.489808 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9503 10:56:08.496817 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9504 10:56:08.496940 it's not compressed!
9505 10:56:08.502989 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9506 10:56:08.509929 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9507 10:56:08.527346 Loading segment from ROM address 0x4010001c
9508 10:56:08.527466 Entry Point 0x80000000
9509 10:56:08.530355 Loaded segments
9510 10:56:08.534093 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9511 10:56:08.540237 Jumping to boot code at 0x80000000(0xffe64000)
9512 10:56:08.547063 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9513 10:56:08.553861 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9514 10:56:08.561933 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9515 10:56:08.564983 Checking segment from ROM address 0x40100000
9516 10:56:08.568479 Checking segment from ROM address 0x4010001c
9517 10:56:08.574994 Loading segment from ROM address 0x40100000
9518 10:56:08.575091 code (compression=1)
9519 10:56:08.581523 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9520 10:56:08.591294 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9521 10:56:08.591403 using LZMA
9522 10:56:08.600231 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9523 10:56:08.606742 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9524 10:56:08.610450 Loading segment from ROM address 0x4010001c
9525 10:56:08.610557 Entry Point 0x54601000
9526 10:56:08.613574 Loaded segments
9527 10:56:08.616667 NOTICE: MT8192 bl31_setup
9528 10:56:08.623689 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9529 10:56:08.626623 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9530 10:56:08.630190 WARNING: region 0:
9531 10:56:08.633494 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 10:56:08.633604 WARNING: region 1:
9533 10:56:08.639986 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9534 10:56:08.643723 WARNING: region 2:
9535 10:56:08.647089 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9536 10:56:08.649965 WARNING: region 3:
9537 10:56:08.656290 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 10:56:08.656376 WARNING: region 4:
9539 10:56:08.663079 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 10:56:08.663167 WARNING: region 5:
9541 10:56:08.666208 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 10:56:08.669946 WARNING: region 6:
9543 10:56:08.672951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 10:56:08.676690 WARNING: region 7:
9545 10:56:08.679685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 10:56:08.686074 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9547 10:56:08.689514 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9548 10:56:08.696009 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9549 10:56:08.699724 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9550 10:56:08.702648 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9551 10:56:08.709224 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9552 10:56:08.712850 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9553 10:56:08.715967 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9554 10:56:08.722769 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9555 10:56:08.725842 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9556 10:56:08.732287 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9557 10:56:08.735771 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9558 10:56:08.739254 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9559 10:56:08.745418 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9560 10:56:08.749082 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9561 10:56:08.755835 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9562 10:56:08.759104 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9563 10:56:08.761930 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9564 10:56:08.768831 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9565 10:56:08.771979 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9566 10:56:08.778539 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9567 10:56:08.781685 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9568 10:56:08.785404 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9569 10:56:08.792022 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9570 10:56:08.794727 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9571 10:56:08.801730 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9572 10:56:08.805077 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9573 10:56:08.808128 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9574 10:56:08.814820 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9575 10:56:08.818426 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9576 10:56:08.824784 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9577 10:56:08.827839 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9578 10:56:08.831552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9579 10:56:08.834497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9580 10:56:08.841720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9581 10:56:08.844605 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9582 10:56:08.848049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9583 10:56:08.851515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9584 10:56:08.858106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9585 10:56:08.861129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9586 10:56:08.864907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9587 10:56:08.868034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9588 10:56:08.874272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9589 10:56:08.877899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9590 10:56:08.881419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9591 10:56:08.887663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9592 10:56:08.891334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9593 10:56:08.894336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9594 10:56:08.900919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9595 10:56:08.904316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9596 10:56:08.907812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9597 10:56:08.914061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9598 10:56:08.917623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9599 10:56:08.923894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9600 10:56:08.927503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9601 10:56:08.934308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9602 10:56:08.937391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9603 10:56:08.940429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9604 10:56:08.947344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9605 10:56:08.950338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9606 10:56:08.957391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9607 10:56:08.960386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9608 10:56:08.967121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9609 10:56:08.970746 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9610 10:56:08.977084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9611 10:56:08.980117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9612 10:56:08.983717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9613 10:56:08.990520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9614 10:56:08.993634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9615 10:56:09.000242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9616 10:56:09.003920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9617 10:56:09.010063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9618 10:56:09.013428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9619 10:56:09.016868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9620 10:56:09.023694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9621 10:56:09.026585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9622 10:56:09.033423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9623 10:56:09.036669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9624 10:56:09.043454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9625 10:56:09.046487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9626 10:56:09.053210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9627 10:56:09.056674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9628 10:56:09.060340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9629 10:56:09.066737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9630 10:56:09.070291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9631 10:56:09.076572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9632 10:56:09.079686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9633 10:56:09.086471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9634 10:56:09.089985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9635 10:56:09.096759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9636 10:56:09.099894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9637 10:56:09.103014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9638 10:56:09.109781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9639 10:56:09.112916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9640 10:56:09.119674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9641 10:56:09.122781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9642 10:56:09.129133 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9643 10:56:09.132503 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9644 10:56:09.135962 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9645 10:56:09.139526 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9646 10:56:09.146208 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9647 10:56:09.149243 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9648 10:56:09.152558 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9649 10:56:09.159009 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9650 10:56:09.162497 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9651 10:56:09.168890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9652 10:56:09.172365 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9653 10:56:09.175950 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9654 10:56:09.182208 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9655 10:56:09.185358 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9656 10:56:09.192085 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9657 10:56:09.195999 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9658 10:56:09.198831 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9659 10:56:09.205688 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9660 10:56:09.208823 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9661 10:56:09.215090 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9662 10:56:09.218866 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9663 10:56:09.221988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9664 10:56:09.228444 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9665 10:56:09.231828 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9666 10:56:09.235507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9667 10:56:09.238656 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9668 10:56:09.241543 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9669 10:56:09.248219 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9670 10:56:09.251742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9671 10:56:09.258356 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9672 10:56:09.261461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9673 10:56:09.265063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9674 10:56:09.271460 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9675 10:56:09.274893 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9676 10:56:09.281358 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9677 10:56:09.284838 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9678 10:56:09.287927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9679 10:56:09.294632 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9680 10:56:09.298182 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9681 10:56:09.304930 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9682 10:56:09.307888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9683 10:56:09.311108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9684 10:56:09.318257 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9685 10:56:09.321294 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9686 10:56:09.327732 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9687 10:56:09.331297 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9688 10:56:09.334769 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9689 10:56:09.341092 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9690 10:56:09.344521 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9691 10:56:09.348033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9692 10:56:09.354259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9693 10:56:09.357823 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9694 10:56:09.364237 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9695 10:56:09.367997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9696 10:56:09.374756 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9697 10:56:09.377770 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9698 10:56:09.380702 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9699 10:56:09.387519 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9700 10:56:09.391099 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9701 10:56:09.394262 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9702 10:56:09.400879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9703 10:56:09.404435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9704 10:56:09.410608 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9705 10:56:09.414393 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9706 10:56:09.417566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9707 10:56:09.423796 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9708 10:56:09.427439 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9709 10:56:09.433771 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9710 10:56:09.437474 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9711 10:56:09.440576 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9712 10:56:09.447130 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9713 10:56:09.450544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9714 10:56:09.456985 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9715 10:56:09.460264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9716 10:56:09.463643 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9717 10:56:09.470250 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9718 10:56:09.473274 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9719 10:56:09.480266 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9720 10:56:09.483505 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9721 10:56:09.486467 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9722 10:56:09.492977 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9723 10:56:09.496490 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9724 10:56:09.503392 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9725 10:56:09.506239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9726 10:56:09.510181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9727 10:56:09.516529 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9728 10:56:09.519598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9729 10:56:09.526641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9730 10:56:09.529653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9731 10:56:09.536543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9732 10:56:09.539598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9733 10:56:09.543132 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9734 10:56:09.549338 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9735 10:56:09.552362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9736 10:56:09.559257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9737 10:56:09.562971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9738 10:56:09.565667 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9739 10:56:09.572582 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9740 10:56:09.575569 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9741 10:56:09.582659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9742 10:56:09.585435 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9743 10:56:09.591910 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9744 10:56:09.595384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9745 10:56:09.598936 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9746 10:56:09.605864 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9747 10:56:09.608572 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9748 10:56:09.615299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9749 10:56:09.618354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9750 10:56:09.625502 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9751 10:56:09.628379 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9752 10:56:09.635179 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9753 10:56:09.638223 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9754 10:56:09.641278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9755 10:56:09.647981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9756 10:56:09.651146 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9757 10:56:09.658085 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9758 10:56:09.661765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9759 10:56:09.664563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9760 10:56:09.671489 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9761 10:56:09.674296 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9762 10:56:09.681264 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9763 10:56:09.684740 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9764 10:56:09.691059 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9765 10:56:09.694141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9766 10:56:09.697607 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9767 10:56:09.704316 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9768 10:56:09.707813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9769 10:56:09.714196 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9770 10:56:09.717761 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9771 10:56:09.723905 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9772 10:56:09.727830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9773 10:56:09.731018 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9774 10:56:09.737164 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9775 10:56:09.740326 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9776 10:56:09.744194 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9777 10:56:09.747184 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9778 10:56:09.753683 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9779 10:56:09.757384 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9780 10:56:09.760574 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9781 10:56:09.766685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9782 10:56:09.770206 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9783 10:56:09.776566 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9784 10:56:09.780174 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9785 10:56:09.783042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9786 10:56:09.789968 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9787 10:56:09.793289 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9788 10:56:09.796555 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9789 10:56:09.802712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9790 10:56:09.806147 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9791 10:56:09.813060 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9792 10:56:09.816127 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9793 10:56:09.819567 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9794 10:56:09.826010 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9795 10:56:09.829200 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9796 10:56:09.832681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9797 10:56:09.839253 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9798 10:56:09.842294 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9799 10:56:09.845948 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9800 10:56:09.851993 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9801 10:56:09.855519 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9802 10:56:09.861821 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9803 10:56:09.865507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9804 10:56:09.868706 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9805 10:56:09.874959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9806 10:56:09.878652 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9807 10:56:09.885254 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9808 10:56:09.888154 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9809 10:56:09.891592 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9810 10:56:09.898072 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9811 10:56:09.901686 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9812 10:56:09.904705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9813 10:56:09.911491 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9814 10:56:09.914620 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9815 10:56:09.917679 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9816 10:56:09.924652 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9817 10:56:09.927528 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9818 10:56:09.930839 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9819 10:56:09.934447 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9820 10:56:09.940731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9821 10:56:09.944498 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9822 10:56:09.947634 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9823 10:56:09.950693 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9824 10:56:09.957487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9825 10:56:09.960386 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9826 10:56:09.964154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9827 10:56:09.967287 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9828 10:56:09.973501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9829 10:56:09.977103 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9830 10:56:09.983333 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9831 10:56:09.987039 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9832 10:56:09.993578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9833 10:56:09.996981 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9834 10:56:10.003436 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9835 10:56:10.006398 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9836 10:56:10.010019 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9837 10:56:10.016205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9838 10:56:10.019912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9839 10:56:10.026476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9840 10:56:10.029311 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9841 10:56:10.036176 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9842 10:56:10.039655 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9843 10:56:10.042412 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9844 10:56:10.049287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9845 10:56:10.052499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9846 10:56:10.059305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9847 10:56:10.062271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9848 10:56:10.069101 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9849 10:56:10.072202 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9850 10:56:10.075303 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9851 10:56:10.082059 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9852 10:56:10.085086 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9853 10:56:10.091928 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9854 10:56:10.095423 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9855 10:56:10.098437 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9856 10:56:10.104963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9857 10:56:10.108515 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9858 10:56:10.114925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9859 10:56:10.118508 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9860 10:56:10.121598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9861 10:56:10.127739 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9862 10:56:10.131444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9863 10:56:10.137935 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9864 10:56:10.141408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9865 10:56:10.147917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9866 10:56:10.151550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9867 10:56:10.154726 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9868 10:56:10.160945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9869 10:56:10.164041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9870 10:56:10.170659 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9871 10:56:10.174462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9872 10:56:10.180645 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9873 10:56:10.184282 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9874 10:56:10.187255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9875 10:56:10.194142 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9876 10:56:10.197168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9877 10:56:10.203627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9878 10:56:10.207230 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9879 10:56:10.213688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9880 10:56:10.216662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9881 10:56:10.220302 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9882 10:56:10.226630 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9883 10:56:10.229806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9884 10:56:10.236474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9885 10:56:10.239919 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9886 10:56:10.246335 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9887 10:56:10.249552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9888 10:56:10.252974 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9889 10:56:10.259531 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9890 10:56:10.262605 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9891 10:56:10.269297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9892 10:56:10.272834 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9893 10:56:10.276026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9894 10:56:10.282453 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9895 10:56:10.286283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9896 10:56:10.292748 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9897 10:56:10.295879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9898 10:56:10.302909 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9899 10:56:10.305826 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9900 10:56:10.309328 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9901 10:56:10.315595 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9902 10:56:10.319082 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9903 10:56:10.325474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9904 10:56:10.329057 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9905 10:56:10.335053 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9906 10:56:10.338727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9907 10:56:10.341733 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9908 10:56:10.348516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9909 10:56:10.351575 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9910 10:56:10.358608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9911 10:56:10.361821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9912 10:56:10.367918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9913 10:56:10.371667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9914 10:56:10.378595 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9915 10:56:10.381390 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9916 10:56:10.384625 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9917 10:56:10.391463 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9918 10:56:10.394419 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9919 10:56:10.401023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9920 10:56:10.404744 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9921 10:56:10.410986 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9922 10:56:10.414676 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9923 10:56:10.421112 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9924 10:56:10.424442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9925 10:56:10.427691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9926 10:56:10.434192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9927 10:56:10.437237 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9928 10:56:10.444189 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9929 10:56:10.447424 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9930 10:56:10.453789 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9931 10:56:10.457359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9932 10:56:10.463835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9933 10:56:10.466746 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9934 10:56:10.473399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9935 10:56:10.477166 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9936 10:56:10.483209 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9937 10:56:10.486472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9938 10:56:10.490158 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9939 10:56:10.496286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9940 10:56:10.499879 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9941 10:56:10.506682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9942 10:56:10.509776 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9943 10:56:10.515994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9944 10:56:10.519198 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9945 10:56:10.525802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9946 10:56:10.529655 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9947 10:56:10.532888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9948 10:56:10.539272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9949 10:56:10.542737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9950 10:56:10.549431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9951 10:56:10.552373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9952 10:56:10.558761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9953 10:56:10.562513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9954 10:56:10.568910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9955 10:56:10.572294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9956 10:56:10.579059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9957 10:56:10.582067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9958 10:56:10.588729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9959 10:56:10.591906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9960 10:56:10.598738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9961 10:56:10.601891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9962 10:56:10.608493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9963 10:56:10.611633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9964 10:56:10.618535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9965 10:56:10.621898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9966 10:56:10.624732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9967 10:56:10.631441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9968 10:56:10.638152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9969 10:56:10.641591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9970 10:56:10.647799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9971 10:56:10.651306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9972 10:56:10.657891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9973 10:56:10.661619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9974 10:56:10.667792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9975 10:56:10.670806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9976 10:56:10.677404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9977 10:56:10.680815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9978 10:56:10.687118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9979 10:56:10.690804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9980 10:56:10.693947 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9981 10:56:10.697074 INFO: [APUAPC] vio 0
9982 10:56:10.703934 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9983 10:56:10.707020 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9984 10:56:10.710723 INFO: [APUAPC] D0_APC_0: 0x400510
9985 10:56:10.713857 INFO: [APUAPC] D0_APC_1: 0x0
9986 10:56:10.716958 INFO: [APUAPC] D0_APC_2: 0x1540
9987 10:56:10.720723 INFO: [APUAPC] D0_APC_3: 0x0
9988 10:56:10.723818 INFO: [APUAPC] D1_APC_0: 0xffffffff
9989 10:56:10.726963 INFO: [APUAPC] D1_APC_1: 0xffffffff
9990 10:56:10.730042 INFO: [APUAPC] D1_APC_2: 0x3fffff
9991 10:56:10.733643 INFO: [APUAPC] D1_APC_3: 0x0
9992 10:56:10.736786 INFO: [APUAPC] D2_APC_0: 0xffffffff
9993 10:56:10.740544 INFO: [APUAPC] D2_APC_1: 0xffffffff
9994 10:56:10.743643 INFO: [APUAPC] D2_APC_2: 0x3fffff
9995 10:56:10.746647 INFO: [APUAPC] D2_APC_3: 0x0
9996 10:56:10.750007 INFO: [APUAPC] D3_APC_0: 0xffffffff
9997 10:56:10.753455 INFO: [APUAPC] D3_APC_1: 0xffffffff
9998 10:56:10.756860 INFO: [APUAPC] D3_APC_2: 0x3fffff
9999 10:56:10.756942 INFO: [APUAPC] D3_APC_3: 0x0
10000 10:56:10.763768 INFO: [APUAPC] D4_APC_0: 0xffffffff
10001 10:56:10.766734 INFO: [APUAPC] D4_APC_1: 0xffffffff
10002 10:56:10.769779 INFO: [APUAPC] D4_APC_2: 0x3fffff
10003 10:56:10.769861 INFO: [APUAPC] D4_APC_3: 0x0
10004 10:56:10.773139 INFO: [APUAPC] D5_APC_0: 0xffffffff
10005 10:56:10.779836 INFO: [APUAPC] D5_APC_1: 0xffffffff
10006 10:56:10.783553 INFO: [APUAPC] D5_APC_2: 0x3fffff
10007 10:56:10.783638 INFO: [APUAPC] D5_APC_3: 0x0
10008 10:56:10.786263 INFO: [APUAPC] D6_APC_0: 0xffffffff
10009 10:56:10.789653 INFO: [APUAPC] D6_APC_1: 0xffffffff
10010 10:56:10.793224 INFO: [APUAPC] D6_APC_2: 0x3fffff
10011 10:56:10.796196 INFO: [APUAPC] D6_APC_3: 0x0
10012 10:56:10.799873 INFO: [APUAPC] D7_APC_0: 0xffffffff
10013 10:56:10.802978 INFO: [APUAPC] D7_APC_1: 0xffffffff
10014 10:56:10.806085 INFO: [APUAPC] D7_APC_2: 0x3fffff
10015 10:56:10.809748 INFO: [APUAPC] D7_APC_3: 0x0
10016 10:56:10.812826 INFO: [APUAPC] D8_APC_0: 0xffffffff
10017 10:56:10.816002 INFO: [APUAPC] D8_APC_1: 0xffffffff
10018 10:56:10.819773 INFO: [APUAPC] D8_APC_2: 0x3fffff
10019 10:56:10.822775 INFO: [APUAPC] D8_APC_3: 0x0
10020 10:56:10.826039 INFO: [APUAPC] D9_APC_0: 0xffffffff
10021 10:56:10.829141 INFO: [APUAPC] D9_APC_1: 0xffffffff
10022 10:56:10.832852 INFO: [APUAPC] D9_APC_2: 0x3fffff
10023 10:56:10.835947 INFO: [APUAPC] D9_APC_3: 0x0
10024 10:56:10.839045 INFO: [APUAPC] D10_APC_0: 0xffffffff
10025 10:56:10.842700 INFO: [APUAPC] D10_APC_1: 0xffffffff
10026 10:56:10.845845 INFO: [APUAPC] D10_APC_2: 0x3fffff
10027 10:56:10.848911 INFO: [APUAPC] D10_APC_3: 0x0
10028 10:56:10.852546 INFO: [APUAPC] D11_APC_0: 0xffffffff
10029 10:56:10.855483 INFO: [APUAPC] D11_APC_1: 0xffffffff
10030 10:56:10.858968 INFO: [APUAPC] D11_APC_2: 0x3fffff
10031 10:56:10.862325 INFO: [APUAPC] D11_APC_3: 0x0
10032 10:56:10.865603 INFO: [APUAPC] D12_APC_0: 0xffffffff
10033 10:56:10.868824 INFO: [APUAPC] D12_APC_1: 0xffffffff
10034 10:56:10.872409 INFO: [APUAPC] D12_APC_2: 0x3fffff
10035 10:56:10.875603 INFO: [APUAPC] D12_APC_3: 0x0
10036 10:56:10.878530 INFO: [APUAPC] D13_APC_0: 0xffffffff
10037 10:56:10.882039 INFO: [APUAPC] D13_APC_1: 0xffffffff
10038 10:56:10.885119 INFO: [APUAPC] D13_APC_2: 0x3fffff
10039 10:56:10.889053 INFO: [APUAPC] D13_APC_3: 0x0
10040 10:56:10.892208 INFO: [APUAPC] D14_APC_0: 0xffffffff
10041 10:56:10.895114 INFO: [APUAPC] D14_APC_1: 0xffffffff
10042 10:56:10.901713 INFO: [APUAPC] D14_APC_2: 0x3fffff
10043 10:56:10.901798 INFO: [APUAPC] D14_APC_3: 0x0
10044 10:56:10.905230 INFO: [APUAPC] D15_APC_0: 0xffffffff
10045 10:56:10.912100 INFO: [APUAPC] D15_APC_1: 0xffffffff
10046 10:56:10.915136 INFO: [APUAPC] D15_APC_2: 0x3fffff
10047 10:56:10.915218 INFO: [APUAPC] D15_APC_3: 0x0
10048 10:56:10.918106 INFO: [APUAPC] APC_CON: 0x4
10049 10:56:10.921878 INFO: [NOCDAPC] D0_APC_0: 0x0
10050 10:56:10.925021 INFO: [NOCDAPC] D0_APC_1: 0x0
10051 10:56:10.928179 INFO: [NOCDAPC] D1_APC_0: 0x0
10052 10:56:10.931906 INFO: [NOCDAPC] D1_APC_1: 0xfff
10053 10:56:10.934904 INFO: [NOCDAPC] D2_APC_0: 0x0
10054 10:56:10.938607 INFO: [NOCDAPC] D2_APC_1: 0xfff
10055 10:56:10.941496 INFO: [NOCDAPC] D3_APC_0: 0x0
10056 10:56:10.941578 INFO: [NOCDAPC] D3_APC_1: 0xfff
10057 10:56:10.944626 INFO: [NOCDAPC] D4_APC_0: 0x0
10058 10:56:10.948432 INFO: [NOCDAPC] D4_APC_1: 0xfff
10059 10:56:10.951810 INFO: [NOCDAPC] D5_APC_0: 0x0
10060 10:56:10.954624 INFO: [NOCDAPC] D5_APC_1: 0xfff
10061 10:56:10.958391 INFO: [NOCDAPC] D6_APC_0: 0x0
10062 10:56:10.961661 INFO: [NOCDAPC] D6_APC_1: 0xfff
10063 10:56:10.964399 INFO: [NOCDAPC] D7_APC_0: 0x0
10064 10:56:10.967836 INFO: [NOCDAPC] D7_APC_1: 0xfff
10065 10:56:10.971125 INFO: [NOCDAPC] D8_APC_0: 0x0
10066 10:56:10.974606 INFO: [NOCDAPC] D8_APC_1: 0xfff
10067 10:56:10.977548 INFO: [NOCDAPC] D9_APC_0: 0x0
10068 10:56:10.977647 INFO: [NOCDAPC] D9_APC_1: 0xfff
10069 10:56:10.981060 INFO: [NOCDAPC] D10_APC_0: 0x0
10070 10:56:10.984468 INFO: [NOCDAPC] D10_APC_1: 0xfff
10071 10:56:10.987940 INFO: [NOCDAPC] D11_APC_0: 0x0
10072 10:56:10.990912 INFO: [NOCDAPC] D11_APC_1: 0xfff
10073 10:56:10.994465 INFO: [NOCDAPC] D12_APC_0: 0x0
10074 10:56:10.997596 INFO: [NOCDAPC] D12_APC_1: 0xfff
10075 10:56:11.001196 INFO: [NOCDAPC] D13_APC_0: 0x0
10076 10:56:11.004088 INFO: [NOCDAPC] D13_APC_1: 0xfff
10077 10:56:11.007608 INFO: [NOCDAPC] D14_APC_0: 0x0
10078 10:56:11.011022 INFO: [NOCDAPC] D14_APC_1: 0xfff
10079 10:56:11.013952 INFO: [NOCDAPC] D15_APC_0: 0x0
10080 10:56:11.017407 INFO: [NOCDAPC] D15_APC_1: 0xfff
10081 10:56:11.020734 INFO: [NOCDAPC] APC_CON: 0x4
10082 10:56:11.023852 INFO: [APUAPC] set_apusys_apc done
10083 10:56:11.027590 INFO: [DEVAPC] devapc_init done
10084 10:56:11.030648 INFO: GICv3 without legacy support detected.
10085 10:56:11.033717 INFO: ARM GICv3 driver initialized in EL3
10086 10:56:11.037394 INFO: Maximum SPI INTID supported: 639
10087 10:56:11.040748 INFO: BL31: Initializing runtime services
10088 10:56:11.047232 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10089 10:56:11.050359 INFO: SPM: enable CPC mode
10090 10:56:11.057093 INFO: mcdi ready for mcusys-off-idle and system suspend
10091 10:56:11.060139 INFO: BL31: Preparing for EL3 exit to normal world
10092 10:56:11.063280 INFO: Entry point address = 0x80000000
10093 10:56:11.066994 INFO: SPSR = 0x8
10094 10:56:11.071748
10095 10:56:11.071850
10096 10:56:11.071941
10097 10:56:11.074734 Starting depthcharge on Spherion...
10098 10:56:11.074860
10099 10:56:11.074940 Wipe memory regions:
10100 10:56:11.075000
10101 10:56:11.075566 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10102 10:56:11.075666 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10103 10:56:11.075766 Setting prompt string to ['asurada:']
10104 10:56:11.075876 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10105 10:56:11.078251 [0x00000040000000, 0x00000054600000)
10106 10:56:11.200381
10107 10:56:11.200538 [0x00000054660000, 0x00000080000000)
10108 10:56:11.460987
10109 10:56:11.461132 [0x000000821a7280, 0x000000ffe64000)
10110 10:56:12.206191
10111 10:56:12.206379 [0x00000100000000, 0x00000240000000)
10112 10:56:14.096609
10113 10:56:14.099891 Initializing XHCI USB controller at 0x11200000.
10114 10:56:15.137842
10115 10:56:15.140899 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10116 10:56:15.141017
10117 10:56:15.141116
10118 10:56:15.141210
10119 10:56:15.141527 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 10:56:15.241924 asurada: tftpboot 192.168.201.1 10591009/tftp-deploy-3jx6k2xn/kernel/image.itb 10591009/tftp-deploy-3jx6k2xn/kernel/cmdline
10122 10:56:15.242148 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 10:56:15.242267 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10124 10:56:15.246670 tftpboot 192.168.201.1 10591009/tftp-deploy-3jx6k2xn/kernel/image.itp-deploy-3jx6k2xn/kernel/cmdline
10125 10:56:15.246791
10126 10:56:15.246923 Waiting for link
10127 10:56:15.407528
10128 10:56:15.407689 R8152: Initializing
10129 10:56:15.407763
10130 10:56:15.410979 Version 6 (ocp_data = 5c30)
10131 10:56:15.411095
10132 10:56:15.413720 R8152: Done initializing
10133 10:56:15.413820
10134 10:56:15.413914 Adding net device
10135 10:56:17.316909
10136 10:56:17.317092 done.
10137 10:56:17.317188
10138 10:56:17.317281 MAC: 00:24:32:30:78:ff
10139 10:56:17.317408
10140 10:56:17.320863 Sending DHCP discover... done.
10141 10:56:17.320967
10142 10:56:17.323872 Waiting for reply... done.
10143 10:56:17.323949
10144 10:56:17.326733 Sending DHCP request... done.
10145 10:56:17.326837
10146 10:56:17.333739 Waiting for reply... done.
10147 10:56:17.333843
10148 10:56:17.333933 My ip is 192.168.201.21
10149 10:56:17.334019
10150 10:56:17.336962 The DHCP server ip is 192.168.201.1
10151 10:56:17.337062
10152 10:56:17.343614 TFTP server IP predefined by user: 192.168.201.1
10153 10:56:17.343698
10154 10:56:17.350145 Bootfile predefined by user: 10591009/tftp-deploy-3jx6k2xn/kernel/image.itb
10155 10:56:17.350229
10156 10:56:17.352917 Sending tftp read request... done.
10157 10:56:17.353005
10158 10:56:17.357096 Waiting for the transfer...
10159 10:56:17.357176
10160 10:56:17.948547 00000000 ################################################################
10161 10:56:17.948714
10162 10:56:18.594782 00080000 ################################################################
10163 10:56:18.595003
10164 10:56:19.263597 00100000 ################################################################
10165 10:56:19.263754
10166 10:56:19.932841 00180000 ################################################################
10167 10:56:19.932997
10168 10:56:20.561412 00200000 ################################################################
10169 10:56:20.561607
10170 10:56:21.205308 00280000 ################################################################
10171 10:56:21.205502
10172 10:56:21.883936 00300000 ################################################################
10173 10:56:21.884090
10174 10:56:22.518570 00380000 ################################################################
10175 10:56:22.518729
10176 10:56:23.180260 00400000 ################################################################
10177 10:56:23.180418
10178 10:56:23.818909 00480000 ################################################################
10179 10:56:23.819060
10180 10:56:24.452906 00500000 ################################################################
10181 10:56:24.453062
10182 10:56:25.025048 00580000 ################################################################
10183 10:56:25.025202
10184 10:56:25.628960 00600000 ################################################################
10185 10:56:25.629108
10186 10:56:26.204184 00680000 ################################################################
10187 10:56:26.204333
10188 10:56:26.778145 00700000 ################################################################
10189 10:56:26.778300
10190 10:56:27.326674 00780000 ################################################################
10191 10:56:27.326838
10192 10:56:27.897910 00800000 ################################################################
10193 10:56:27.898065
10194 10:56:28.468630 00880000 ################################################################
10195 10:56:28.468804
10196 10:56:29.036616 00900000 ################################################################
10197 10:56:29.036762
10198 10:56:29.597096 00980000 ################################################################
10199 10:56:29.597250
10200 10:56:30.157100 00a00000 ################################################################
10201 10:56:30.157257
10202 10:56:30.718728 00a80000 ################################################################
10203 10:56:30.718936
10204 10:56:31.283187 00b00000 ################################################################
10205 10:56:31.283334
10206 10:56:31.851262 00b80000 ################################################################
10207 10:56:31.851419
10208 10:56:32.413858 00c00000 ################################################################
10209 10:56:32.414012
10210 10:56:32.971168 00c80000 ################################################################
10211 10:56:32.971325
10212 10:56:33.542811 00d00000 ################################################################
10213 10:56:33.542997
10214 10:56:34.106457 00d80000 ################################################################
10215 10:56:34.106610
10216 10:56:34.680012 00e00000 ################################################################
10217 10:56:34.680159
10218 10:56:35.243919 00e80000 ################################################################
10219 10:56:35.244074
10220 10:56:35.815143 00f00000 ################################################################
10221 10:56:35.815298
10222 10:56:36.381370 00f80000 ################################################################
10223 10:56:36.381562
10224 10:56:36.940885 01000000 ################################################################
10225 10:56:36.941042
10226 10:56:37.501721 01080000 ################################################################
10227 10:56:37.501879
10228 10:56:38.072441 01100000 ################################################################
10229 10:56:38.072590
10230 10:56:38.639223 01180000 ################################################################
10231 10:56:38.639440
10232 10:56:39.200551 01200000 ################################################################
10233 10:56:39.200703
10234 10:56:39.754090 01280000 ################################################################
10235 10:56:39.754241
10236 10:56:40.322938 01300000 ################################################################
10237 10:56:40.323124
10238 10:56:40.899013 01380000 ################################################################
10239 10:56:40.899174
10240 10:56:41.472485 01400000 ################################################################
10241 10:56:41.472633
10242 10:56:42.040218 01480000 ################################################################
10243 10:56:42.040370
10244 10:56:42.589588 01500000 ################################################################
10245 10:56:42.589745
10246 10:56:43.127910 01580000 ################################################################
10247 10:56:43.128071
10248 10:56:43.695933 01600000 ################################################################
10249 10:56:43.696116
10250 10:56:44.289009 01680000 ################################################################
10251 10:56:44.289192
10252 10:56:44.900436 01700000 ################################################################
10253 10:56:44.900951
10254 10:56:45.549108 01780000 ################################################################
10255 10:56:45.549407
10256 10:56:46.193800 01800000 ################################################################
10257 10:56:46.193954
10258 10:56:46.785092 01880000 ################################################################
10259 10:56:46.785245
10260 10:56:47.411287 01900000 ################################################################
10261 10:56:47.411443
10262 10:56:48.083997 01980000 ################################################################
10263 10:56:48.084528
10264 10:56:48.724771 01a00000 ############################################################### done.
10265 10:56:48.725315
10266 10:56:48.727725 The bootfile was 27772870 bytes long.
10267 10:56:48.731259
10268 10:56:48.731818 Sending tftp read request... done.
10269 10:56:48.732299
10270 10:56:48.734455 Waiting for the transfer...
10271 10:56:48.737346
10272 10:56:48.738000 00000000 # done.
10273 10:56:48.738516
10274 10:56:48.744092 Command line loaded dynamically from TFTP file: 10591009/tftp-deploy-3jx6k2xn/kernel/cmdline
10275 10:56:48.744725
10276 10:56:48.764098 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10277 10:56:48.764708
10278 10:56:48.767114 Loading FIT.
10279 10:56:48.767530
10280 10:56:48.770931 Image ramdisk-1 has 17641973 bytes.
10281 10:56:48.771352
10282 10:56:48.773930 Image fdt-1 has 46924 bytes.
10283 10:56:48.774362
10284 10:56:48.774692 Image kernel-1 has 10081937 bytes.
10285 10:56:48.776903
10286 10:56:48.784101 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10287 10:56:48.784523
10288 10:56:48.803435 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10289 10:56:48.803896
10290 10:56:48.806808 Choosing best match conf-1 for compat google,spherion-rev2.
10291 10:56:48.811286
10292 10:56:48.815239 Connected to device vid:did:rid of 1ae0:0028:00
10293 10:56:48.822812
10294 10:56:48.825808 tpm_get_response: command 0x17b, return code 0x0
10295 10:56:48.826384
10296 10:56:48.829002 ec_init: CrosEC protocol v3 supported (256, 248)
10297 10:56:48.833194
10298 10:56:48.836822 tpm_cleanup: add release locality here.
10299 10:56:48.837376
10300 10:56:48.837868 Shutting down all USB controllers.
10301 10:56:48.839992
10302 10:56:48.840410 Removing current net device
10303 10:56:48.840744
10304 10:56:48.846611 Exiting depthcharge with code 4 at timestamp: 67072522
10305 10:56:48.847117
10306 10:56:48.850256 LZMA decompressing kernel-1 to 0x821a6718
10307 10:56:48.850811
10308 10:56:48.853315 LZMA decompressing kernel-1 to 0x40000000
10309 10:56:50.119345
10310 10:56:50.119920 jumping to kernel
10311 10:56:50.121362 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10312 10:56:50.121882 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10313 10:56:50.122293 Setting prompt string to ['Linux version [0-9]']
10314 10:56:50.122663 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10315 10:56:50.123089 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10316 10:56:50.201035
10317 10:56:50.203992 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10318 10:56:50.207952 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10319 10:56:50.208491 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10320 10:56:50.208954 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10321 10:56:50.209364 Using line separator: #'\n'#
10322 10:56:50.209705 No login prompt set.
10323 10:56:50.210045 Parsing kernel messages
10324 10:56:50.210379 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10325 10:56:50.210983 [login-action] Waiting for messages, (timeout 00:03:46)
10326 10:56:50.227142 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10327 10:56:50.230736 [ 0.000000] random: crng init done
10328 10:56:50.237127 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10329 10:56:50.240320 [ 0.000000] efi: UEFI not found.
10330 10:56:50.246760 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10331 10:56:50.253378 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10332 10:56:50.263196 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10333 10:56:50.273433 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10334 10:56:50.279916 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10335 10:56:50.286931 [ 0.000000] printk: bootconsole [mtk8250] enabled
10336 10:56:50.293231 [ 0.000000] NUMA: No NUMA configuration found
10337 10:56:50.299732 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10338 10:56:50.302729 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10339 10:56:50.306020 [ 0.000000] Zone ranges:
10340 10:56:50.312773 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10341 10:56:50.316053 [ 0.000000] DMA32 empty
10342 10:56:50.322675 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10343 10:56:50.325867 [ 0.000000] Movable zone start for each node
10344 10:56:50.329278 [ 0.000000] Early memory node ranges
10345 10:56:50.335906 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10346 10:56:50.342227 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10347 10:56:50.348758 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10348 10:56:50.355708 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10349 10:56:50.362007 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10350 10:56:50.368594 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10351 10:56:50.425351 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10352 10:56:50.431297 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10353 10:56:50.438120 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10354 10:56:50.441637 [ 0.000000] psci: probing for conduit method from DT.
10355 10:56:50.448146 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10356 10:56:50.450925 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10357 10:56:50.457914 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10358 10:56:50.461385 [ 0.000000] psci: SMC Calling Convention v1.2
10359 10:56:50.468133 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10360 10:56:50.471300 [ 0.000000] Detected VIPT I-cache on CPU0
10361 10:56:50.477793 [ 0.000000] CPU features: detected: GIC system register CPU interface
10362 10:56:50.484200 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10363 10:56:50.490810 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10364 10:56:50.497426 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10365 10:56:50.507663 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10366 10:56:50.514113 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10367 10:56:50.517670 [ 0.000000] alternatives: applying boot alternatives
10368 10:56:50.524172 [ 0.000000] Fallback order for Node 0: 0
10369 10:56:50.531171 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10370 10:56:50.534065 [ 0.000000] Policy zone: Normal
10371 10:56:50.553863 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10372 10:56:50.563373 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10373 10:56:50.575334 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10374 10:56:50.585391 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10375 10:56:50.591668 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10376 10:56:50.594951 <6>[ 0.000000] software IO TLB: area num 8.
10377 10:56:50.652114 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10378 10:56:50.800848 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10379 10:56:50.807964 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10380 10:56:50.814199 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10381 10:56:50.817556 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10382 10:56:50.824091 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10383 10:56:50.830620 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10384 10:56:50.833975 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10385 10:56:50.843939 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10386 10:56:50.850522 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10387 10:56:50.857160 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10388 10:56:50.863538 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10389 10:56:50.867176 <6>[ 0.000000] GICv3: 608 SPIs implemented
10390 10:56:50.870132 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10391 10:56:50.876904 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10392 10:56:50.880489 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10393 10:56:50.886625 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10394 10:56:50.899727 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10395 10:56:50.913022 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10396 10:56:50.919244 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10397 10:56:50.927212 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10398 10:56:50.940305 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10399 10:56:50.947086 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10400 10:56:50.953791 <6>[ 0.009216] Console: colour dummy device 80x25
10401 10:56:50.963340 <6>[ 0.013973] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10402 10:56:50.970020 <6>[ 0.024480] pid_max: default: 32768 minimum: 301
10403 10:56:50.973613 <6>[ 0.029355] LSM: Security Framework initializing
10404 10:56:50.980262 <6>[ 0.034295] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10405 10:56:50.989961 <6>[ 0.042109] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 10:56:50.999655 <6>[ 0.051536] cblist_init_generic: Setting adjustable number of callback queues.
10407 10:56:51.006728 <6>[ 0.058985] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 10:56:51.009920 <6>[ 0.065323] cblist_init_generic: Setting shift to 3 and lim to 1.
10409 10:56:51.016279 <6>[ 0.071730] rcu: Hierarchical SRCU implementation.
10410 10:56:51.023258 <6>[ 0.076744] rcu: Max phase no-delay instances is 1000.
10411 10:56:51.029420 <6>[ 0.083793] EFI services will not be available.
10412 10:56:51.032838 <6>[ 0.088764] smp: Bringing up secondary CPUs ...
10413 10:56:51.040767 <6>[ 0.093818] Detected VIPT I-cache on CPU1
10414 10:56:51.047446 <6>[ 0.093890] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10415 10:56:51.054304 <6>[ 0.093920] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10416 10:56:51.057313 <6>[ 0.094256] Detected VIPT I-cache on CPU2
10417 10:56:51.067126 <6>[ 0.094310] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10418 10:56:51.073491 <6>[ 0.094327] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10419 10:56:51.077232 <6>[ 0.094586] Detected VIPT I-cache on CPU3
10420 10:56:51.083274 <6>[ 0.094633] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10421 10:56:51.089929 <6>[ 0.094647] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10422 10:56:51.096551 <6>[ 0.094950] CPU features: detected: Spectre-v4
10423 10:56:51.099993 <6>[ 0.094956] CPU features: detected: Spectre-BHB
10424 10:56:51.103440 <6>[ 0.094962] Detected PIPT I-cache on CPU4
10425 10:56:51.110053 <6>[ 0.095021] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10426 10:56:51.119741 <6>[ 0.095037] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10427 10:56:51.122755 <6>[ 0.095331] Detected PIPT I-cache on CPU5
10428 10:56:51.129369 <6>[ 0.095396] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10429 10:56:51.135769 <6>[ 0.095413] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10430 10:56:51.139287 <6>[ 0.095696] Detected PIPT I-cache on CPU6
10431 10:56:51.148948 <6>[ 0.095763] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10432 10:56:51.155677 <6>[ 0.095779] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10433 10:56:51.158701 <6>[ 0.096075] Detected PIPT I-cache on CPU7
10434 10:56:51.165463 <6>[ 0.096140] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10435 10:56:51.172224 <6>[ 0.096157] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10436 10:56:51.178644 <6>[ 0.096203] smp: Brought up 1 node, 8 CPUs
10437 10:56:51.181508 <6>[ 0.237569] SMP: Total of 8 processors activated.
10438 10:56:51.188166 <6>[ 0.242490] CPU features: detected: 32-bit EL0 Support
10439 10:56:51.195030 <6>[ 0.247853] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10440 10:56:51.201639 <6>[ 0.256708] CPU features: detected: Common not Private translations
10441 10:56:51.208094 <6>[ 0.263183] CPU features: detected: CRC32 instructions
10442 10:56:51.214329 <6>[ 0.268534] CPU features: detected: RCpc load-acquire (LDAPR)
10443 10:56:51.221257 <6>[ 0.274530] CPU features: detected: LSE atomic instructions
10444 10:56:51.224171 <6>[ 0.280312] CPU features: detected: Privileged Access Never
10445 10:56:51.231032 <6>[ 0.286127] CPU features: detected: RAS Extension Support
10446 10:56:51.237896 <6>[ 0.291736] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10447 10:56:51.244118 <6>[ 0.298955] CPU: All CPU(s) started at EL2
10448 10:56:51.247168 <6>[ 0.303271] alternatives: applying system-wide alternatives
10449 10:56:51.258665 <6>[ 0.313927] devtmpfs: initialized
10450 10:56:51.274543 <6>[ 0.323026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10451 10:56:51.280851 <6>[ 0.332987] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10452 10:56:51.287445 <6>[ 0.341235] pinctrl core: initialized pinctrl subsystem
10453 10:56:51.291102 <6>[ 0.347913] DMI not present or invalid.
10454 10:56:51.297139 <6>[ 0.352318] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10455 10:56:51.306920 <6>[ 0.359216] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10456 10:56:51.313635 <6>[ 0.366795] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10457 10:56:51.323306 <6>[ 0.375031] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10458 10:56:51.330119 <6>[ 0.383272] audit: initializing netlink subsys (disabled)
10459 10:56:51.336923 <5>[ 0.388967] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10460 10:56:51.343383 <6>[ 0.389672] thermal_sys: Registered thermal governor 'step_wise'
10461 10:56:51.349675 <6>[ 0.396938] thermal_sys: Registered thermal governor 'power_allocator'
10462 10:56:51.353250 <6>[ 0.403190] cpuidle: using governor menu
10463 10:56:51.359961 <6>[ 0.414148] NET: Registered PF_QIPCRTR protocol family
10464 10:56:51.366419 <6>[ 0.419638] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10465 10:56:51.373149 <6>[ 0.426736] ASID allocator initialised with 32768 entries
10466 10:56:51.376191 <6>[ 0.433303] Serial: AMBA PL011 UART driver
10467 10:56:51.386588 <4>[ 0.441991] Trying to register duplicate clock ID: 134
10468 10:56:51.440481 <6>[ 0.499254] KASLR enabled
10469 10:56:51.454871 <6>[ 0.507026] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10470 10:56:51.461335 <6>[ 0.514041] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10471 10:56:51.468106 <6>[ 0.520532] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10472 10:56:51.474986 <6>[ 0.527537] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10473 10:56:51.480955 <6>[ 0.534026] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10474 10:56:51.487544 <6>[ 0.541030] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10475 10:56:51.494651 <6>[ 0.547516] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10476 10:56:51.500640 <6>[ 0.554518] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10477 10:56:51.504177 <6>[ 0.561977] ACPI: Interpreter disabled.
10478 10:56:51.512795 <6>[ 0.568359] iommu: Default domain type: Translated
10479 10:56:51.519627 <6>[ 0.573470] iommu: DMA domain TLB invalidation policy: strict mode
10480 10:56:51.522689 <5>[ 0.580123] SCSI subsystem initialized
10481 10:56:51.529263 <6>[ 0.584292] usbcore: registered new interface driver usbfs
10482 10:56:51.536179 <6>[ 0.590026] usbcore: registered new interface driver hub
10483 10:56:51.539041 <6>[ 0.595577] usbcore: registered new device driver usb
10484 10:56:51.546447 <6>[ 0.601657] pps_core: LinuxPPS API ver. 1 registered
10485 10:56:51.556108 <6>[ 0.606849] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10486 10:56:51.559608 <6>[ 0.616195] PTP clock support registered
10487 10:56:51.562340 <6>[ 0.620435] EDAC MC: Ver: 3.0.0
10488 10:56:51.569948 <6>[ 0.625579] FPGA manager framework
10489 10:56:51.576640 <6>[ 0.629257] Advanced Linux Sound Architecture Driver Initialized.
10490 10:56:51.579918 <6>[ 0.636026] vgaarb: loaded
10491 10:56:51.586500 <6>[ 0.639205] clocksource: Switched to clocksource arch_sys_counter
10492 10:56:51.590047 <5>[ 0.645624] VFS: Disk quotas dquot_6.6.0
10493 10:56:51.596605 <6>[ 0.649808] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10494 10:56:51.599686 <6>[ 0.656993] pnp: PnP ACPI: disabled
10495 10:56:51.608081 <6>[ 0.663684] NET: Registered PF_INET protocol family
10496 10:56:51.617707 <6>[ 0.669269] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10497 10:56:51.629408 <6>[ 0.681564] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10498 10:56:51.639582 <6>[ 0.690379] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10499 10:56:51.645987 <6>[ 0.698349] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10500 10:56:51.655410 <6>[ 0.707048] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10501 10:56:51.662447 <6>[ 0.716802] TCP: Hash tables configured (established 65536 bind 65536)
10502 10:56:51.668651 <6>[ 0.723658] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10503 10:56:51.678538 <6>[ 0.730856] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10504 10:56:51.685417 <6>[ 0.738553] NET: Registered PF_UNIX/PF_LOCAL protocol family
10505 10:56:51.691713 <6>[ 0.744722] RPC: Registered named UNIX socket transport module.
10506 10:56:51.695398 <6>[ 0.750877] RPC: Registered udp transport module.
10507 10:56:51.701910 <6>[ 0.755810] RPC: Registered tcp transport module.
10508 10:56:51.708003 <6>[ 0.760744] RPC: Registered tcp NFSv4.1 backchannel transport module.
10509 10:56:51.711740 <6>[ 0.767414] PCI: CLS 0 bytes, default 64
10510 10:56:51.714651 <6>[ 0.771761] Unpacking initramfs...
10511 10:56:51.731432 <6>[ 0.783843] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10512 10:56:51.741730 <6>[ 0.792490] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10513 10:56:51.744728 <6>[ 0.801337] kvm [1]: IPA Size Limit: 40 bits
10514 10:56:51.751734 <6>[ 0.805862] kvm [1]: GICv3: no GICV resource entry
10515 10:56:51.754712 <6>[ 0.810883] kvm [1]: disabling GICv2 emulation
10516 10:56:51.761623 <6>[ 0.815571] kvm [1]: GIC system register CPU interface enabled
10517 10:56:51.764465 <6>[ 0.821733] kvm [1]: vgic interrupt IRQ18
10518 10:56:51.771529 <6>[ 0.827252] kvm [1]: VHE mode initialized successfully
10519 10:56:51.778606 <5>[ 0.833647] Initialise system trusted keyrings
10520 10:56:51.784673 <6>[ 0.838473] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10521 10:56:51.793037 <6>[ 0.848591] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10522 10:56:51.800072 <5>[ 0.854983] NFS: Registering the id_resolver key type
10523 10:56:51.802870 <5>[ 0.860289] Key type id_resolver registered
10524 10:56:51.809662 <5>[ 0.864704] Key type id_legacy registered
10525 10:56:51.816483 <6>[ 0.868991] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10526 10:56:51.823144 <6>[ 0.875917] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10527 10:56:51.829270 <6>[ 0.883673] 9p: Installing v9fs 9p2000 file system support
10528 10:56:51.867642 <5>[ 0.922809] Key type asymmetric registered
10529 10:56:51.870495 <5>[ 0.927142] Asymmetric key parser 'x509' registered
10530 10:56:51.880510 <6>[ 0.932315] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10531 10:56:51.883971 <6>[ 0.939929] io scheduler mq-deadline registered
10532 10:56:51.887038 <6>[ 0.944688] io scheduler kyber registered
10533 10:56:51.906285 <6>[ 0.961691] EINJ: ACPI disabled.
10534 10:56:51.938438 <4>[ 0.987157] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 10:56:51.947901 <4>[ 0.997760] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 10:56:51.962769 <6>[ 1.018434] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10537 10:56:51.970683 <6>[ 1.026437] printk: console [ttyS0] disabled
10538 10:56:51.998812 <6>[ 1.051079] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10539 10:56:52.005303 <6>[ 1.060575] printk: console [ttyS0] enabled
10540 10:56:52.008779 <6>[ 1.060575] printk: console [ttyS0] enabled
10541 10:56:52.015720 <6>[ 1.069469] printk: bootconsole [mtk8250] disabled
10542 10:56:52.018698 <6>[ 1.069469] printk: bootconsole [mtk8250] disabled
10543 10:56:52.025575 <6>[ 1.080698] SuperH (H)SCI(F) driver initialized
10544 10:56:52.028641 <6>[ 1.085958] msm_serial: driver initialized
10545 10:56:52.043096 <6>[ 1.094926] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10546 10:56:52.052564 <6>[ 1.103473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10547 10:56:52.059206 <6>[ 1.112014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10548 10:56:52.069241 <6>[ 1.120642] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10549 10:56:52.079071 <6>[ 1.129348] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10550 10:56:52.085657 <6>[ 1.138062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10551 10:56:52.095681 <6>[ 1.146603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10552 10:56:52.102726 <6>[ 1.155407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10553 10:56:52.112181 <6>[ 1.163958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10554 10:56:52.123857 <6>[ 1.179514] loop: module loaded
10555 10:56:52.130673 <6>[ 1.185655] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10556 10:56:52.153986 <4>[ 1.209239] mtk-pmic-keys: Failed to locate of_node [id: -1]
10557 10:56:52.160373 <6>[ 1.215903] megasas: 07.719.03.00-rc1
10558 10:56:52.170161 <6>[ 1.225473] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10559 10:56:52.179436 <6>[ 1.234590] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10560 10:56:52.195771 <6>[ 1.251249] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10561 10:56:52.256072 <6>[ 1.305296] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10562 10:56:52.442110 <6>[ 1.497923] Freeing initrd memory: 17224K
10563 10:56:52.452438 <6>[ 1.508106] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10564 10:56:52.463554 <6>[ 1.518982] tun: Universal TUN/TAP device driver, 1.6
10565 10:56:52.466626 <6>[ 1.525040] thunder_xcv, ver 1.0
10566 10:56:52.469984 <6>[ 1.528544] thunder_bgx, ver 1.0
10567 10:56:52.473781 <6>[ 1.532038] nicpf, ver 1.0
10568 10:56:52.483797 <6>[ 1.536046] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10569 10:56:52.487554 <6>[ 1.543523] hns3: Copyright (c) 2017 Huawei Corporation.
10570 10:56:52.493628 <6>[ 1.549108] hclge is initializing
10571 10:56:52.497342 <6>[ 1.552689] e1000: Intel(R) PRO/1000 Network Driver
10572 10:56:52.503677 <6>[ 1.557818] e1000: Copyright (c) 1999-2006 Intel Corporation.
10573 10:56:52.507100 <6>[ 1.563831] e1000e: Intel(R) PRO/1000 Network Driver
10574 10:56:52.514171 <6>[ 1.569046] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10575 10:56:52.520207 <6>[ 1.575233] igb: Intel(R) Gigabit Ethernet Network Driver
10576 10:56:52.526557 <6>[ 1.580883] igb: Copyright (c) 2007-2014 Intel Corporation.
10577 10:56:52.533624 <6>[ 1.586719] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10578 10:56:52.540272 <6>[ 1.593237] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10579 10:56:52.543539 <6>[ 1.599694] sky2: driver version 1.30
10580 10:56:52.549933 <6>[ 1.604685] VFIO - User Level meta-driver version: 0.3
10581 10:56:52.557605 <6>[ 1.612820] usbcore: registered new interface driver usb-storage
10582 10:56:52.563695 <6>[ 1.619273] usbcore: registered new device driver onboard-usb-hub
10583 10:56:52.572752 <6>[ 1.628304] mt6397-rtc mt6359-rtc: registered as rtc0
10584 10:56:52.583113 <6>[ 1.633769] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:56:52 UTC (1685962612)
10585 10:56:52.586179 <6>[ 1.643358] i2c_dev: i2c /dev entries driver
10586 10:56:52.603013 <6>[ 1.654948] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10587 10:56:52.609504 <6>[ 1.665162] sdhci: Secure Digital Host Controller Interface driver
10588 10:56:52.616145 <6>[ 1.671599] sdhci: Copyright(c) Pierre Ossman
10589 10:56:52.623121 <6>[ 1.677001] Synopsys Designware Multimedia Card Interface Driver
10590 10:56:52.626415 <6>[ 1.683573] mmc0: CQHCI version 5.10
10591 10:56:52.632909 <6>[ 1.684147] sdhci-pltfm: SDHCI platform and OF driver helper
10592 10:56:52.640040 <6>[ 1.695723] ledtrig-cpu: registered to indicate activity on CPUs
10593 10:56:52.650813 <6>[ 1.703109] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10594 10:56:52.654226 <6>[ 1.710509] usbcore: registered new interface driver usbhid
10595 10:56:52.661089 <6>[ 1.716339] usbhid: USB HID core driver
10596 10:56:52.667196 <6>[ 1.720588] spi_master spi0: will run message pump with realtime priority
10597 10:56:52.713685 <6>[ 1.762373] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10598 10:56:52.732634 <6>[ 1.778122] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10599 10:56:52.736397 <6>[ 1.791699] mmc0: Command Queue Engine enabled
10600 10:56:52.742866 <6>[ 1.792966] cros-ec-spi spi0.0: Chrome EC device registered
10601 10:56:52.749736 <6>[ 1.796437] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10602 10:56:52.753297 <6>[ 1.809643] mmcblk0: mmc0:0001 DA4128 116 GiB
10603 10:56:52.763975 <6>[ 1.819370] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10604 10:56:52.773916 <6>[ 1.819707] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10605 10:56:52.780622 <6>[ 1.826576] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10606 10:56:52.783526 <6>[ 1.836809] NET: Registered PF_PACKET protocol family
10607 10:56:52.790017 <6>[ 1.840472] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10608 10:56:52.793761 <6>[ 1.845253] 9pnet: Installing 9P2000 support
10609 10:56:52.800472 <6>[ 1.851001] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10610 10:56:52.807132 <5>[ 1.854924] Key type dns_resolver registered
10611 10:56:52.810097 <6>[ 1.866515] registered taskstats version 1
10612 10:56:52.816629 <5>[ 1.870898] Loading compiled-in X.509 certificates
10613 10:56:52.850763 <4>[ 1.899665] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 10:56:52.860433 <4>[ 1.910352] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 10:56:52.870959 <3>[ 1.923107] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10616 10:56:52.882705 <6>[ 1.938488] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10617 10:56:52.889757 <6>[ 1.945366] xhci-mtk 11200000.usb: xHCI Host Controller
10618 10:56:52.896187 <6>[ 1.950876] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10619 10:56:52.906505 <6>[ 1.958731] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10620 10:56:52.913275 <6>[ 1.968156] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10621 10:56:52.919561 <6>[ 1.974242] xhci-mtk 11200000.usb: xHCI Host Controller
10622 10:56:52.926757 <6>[ 1.979724] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 10:56:52.933360 <6>[ 1.987377] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10624 10:56:52.939891 <6>[ 1.995093] hub 1-0:1.0: USB hub found
10625 10:56:52.943202 <6>[ 1.999119] hub 1-0:1.0: 1 port detected
10626 10:56:52.949568 <6>[ 2.003448] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10627 10:56:52.956853 <6>[ 2.012076] hub 2-0:1.0: USB hub found
10628 10:56:52.959921 <6>[ 2.016098] hub 2-0:1.0: 1 port detected
10629 10:56:52.967601 <6>[ 2.023109] mtk-msdc 11f70000.mmc: Got CD GPIO
10630 10:56:52.984849 <6>[ 2.037134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10631 10:56:52.991326 <6>[ 2.045201] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10632 10:56:53.001763 <4>[ 2.053177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10633 10:56:53.011600 <6>[ 2.062835] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10634 10:56:53.018189 <6>[ 2.070916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10635 10:56:53.024737 <6>[ 2.078946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10636 10:56:53.034487 <6>[ 2.086860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10637 10:56:53.041504 <6>[ 2.094681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10638 10:56:53.051163 <6>[ 2.102503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10639 10:56:53.061276 <6>[ 2.113265] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10640 10:56:53.070821 <6>[ 2.121633] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 10:56:53.077408 <6>[ 2.129987] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 10:56:53.087683 <6>[ 2.138330] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 10:56:53.094326 <6>[ 2.146674] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 10:56:53.104085 <6>[ 2.155016] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 10:56:53.110820 <6>[ 2.163360] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 10:56:53.120623 <6>[ 2.171703] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 10:56:53.127635 <6>[ 2.180047] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 10:56:53.137290 <6>[ 2.188389] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 10:56:53.143861 <6>[ 2.196732] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 10:56:53.153768 <6>[ 2.205076] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 10:56:53.160612 <6>[ 2.213419] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 10:56:53.170745 <6>[ 2.221761] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 10:56:53.177620 <6>[ 2.230109] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 10:56:53.183822 <6>[ 2.239019] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 10:56:53.190652 <6>[ 2.246451] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 10:56:53.197787 <6>[ 2.253519] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 10:56:53.208610 <6>[ 2.260641] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 10:56:53.214771 <6>[ 2.267905] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 10:56:53.225179 <6>[ 2.274810] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 10:56:53.231562 <6>[ 2.283952] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 10:56:53.241409 <6>[ 2.293083] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 10:56:53.251014 <6>[ 2.302391] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 10:56:53.261278 <6>[ 2.311866] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 10:56:53.271081 <6>[ 2.321341] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 10:56:53.280890 <6>[ 2.330468] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 10:56:53.287601 <6>[ 2.339942] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 10:56:53.297429 <6>[ 2.349068] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 10:56:53.307014 <6>[ 2.358370] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 10:56:53.317184 <6>[ 2.368535] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 10:56:53.327992 <6>[ 2.379953] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10671 10:56:53.333994 <6>[ 2.389663] Trying to probe devices needed for running init ...
10672 10:56:53.374617 <6>[ 2.427264] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 10:56:53.527863 <6>[ 2.583366] hub 1-1:1.0: USB hub found
10674 10:56:53.530771 <6>[ 2.587718] hub 1-1:1.0: 4 ports detected
10675 10:56:53.655362 <6>[ 2.707829] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10676 10:56:53.682440 <6>[ 2.737865] hub 2-1:1.0: USB hub found
10677 10:56:53.685538 <6>[ 2.742343] hub 2-1:1.0: 3 ports detected
10678 10:56:53.851201 <6>[ 2.903505] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10679 10:56:53.984121 <6>[ 3.039489] hub 1-1.4:1.0: USB hub found
10680 10:56:53.987017 <6>[ 3.044162] hub 1-1.4:1.0: 2 ports detected
10681 10:56:54.063384 <6>[ 3.115727] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10682 10:56:54.283064 <6>[ 3.335480] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10683 10:56:54.474783 <6>[ 3.527479] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10684 10:57:05.607957 <6>[ 14.668060] ALSA device list:
10685 10:57:05.614299 <6>[ 14.671323] No soundcards found.
10686 10:57:05.621612 <6>[ 14.678610] Freeing unused kernel memory: 8384K
10687 10:57:05.625300 <6>[ 14.683531] Run /init as init process
10688 10:57:05.633415 Loading, please wait...
10689 10:57:05.651291 Starting version 247.3-7+deb11u2
10690 10:57:05.986428 <6>[ 15.040409] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10691 10:57:05.997594 <6>[ 15.054834] remoteproc remoteproc0: scp is available
10692 10:57:06.007989 <4>[ 15.060343] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10693 10:57:06.017927 <3>[ 15.062912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 10:57:06.021311 <6>[ 15.070183] remoteproc remoteproc0: powering up scp
10695 10:57:06.027664 <6>[ 15.075856] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10696 10:57:06.037167 <3>[ 15.078279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 10:57:06.047270 <4>[ 15.083432] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10698 10:57:06.054721 <3>[ 15.091084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 10:57:06.060881 <3>[ 15.099178] remoteproc remoteproc0: request_firmware failed: -2
10700 10:57:06.067818 <6>[ 15.100733] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10701 10:57:06.077328 <6>[ 15.100783] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10702 10:57:06.087573 <6>[ 15.100795] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10703 10:57:06.094593 <4>[ 15.101958] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10704 10:57:06.101293 <4>[ 15.101958] Fallback method does not support PEC.
10705 10:57:06.107485 <3>[ 15.118601] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 10:57:06.117950 <3>[ 15.127931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 10:57:06.121349 <6>[ 15.157623] mc: Linux media interface: v0.10
10708 10:57:06.127900 <4>[ 15.159446] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10709 10:57:06.138083 <3>[ 15.161970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 10:57:06.144149 <4>[ 15.166308] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 10:57:06.154404 <3>[ 15.175390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 10:57:06.160637 <3>[ 15.178776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 10:57:06.167279 <6>[ 15.200588] videodev: Linux video capture interface: v2.00
10714 10:57:06.173813 <3>[ 15.206138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 10:57:06.180739 <6>[ 15.208375] usbcore: registered new interface driver r8152
10716 10:57:06.187156 <6>[ 15.220677] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10717 10:57:06.197023 <3>[ 15.222983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 10:57:06.203872 <3>[ 15.223037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 10:57:06.210118 <6>[ 15.228799] pci_bus 0000:00: root bus resource [bus 00-ff]
10720 10:57:06.216973 <3>[ 15.236843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 10:57:06.223650 <6>[ 15.242592] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10722 10:57:06.233537 <3>[ 15.249420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 10:57:06.240136 <3>[ 15.249427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 10:57:06.250019 <6>[ 15.257518] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10725 10:57:06.259878 <3>[ 15.265660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 10:57:06.266166 <6>[ 15.271429] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10727 10:57:06.272884 <3>[ 15.279417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 10:57:06.282696 <3>[ 15.279424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 10:57:06.289801 <6>[ 15.286214] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10730 10:57:06.299767 <6>[ 15.286679] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10731 10:57:06.309202 <6>[ 15.291613] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10732 10:57:06.316077 <6>[ 15.291835] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10733 10:57:06.325877 <3>[ 15.294634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 10:57:06.332568 <3>[ 15.294640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 10:57:06.342485 <3>[ 15.294702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 10:57:06.345494 <6>[ 15.302820] pci 0000:00:00.0: supports D1 D2
10737 10:57:06.352504 <6>[ 15.321053] usbcore: registered new interface driver cdc_ether
10738 10:57:06.359028 <6>[ 15.327795] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10739 10:57:06.365225 <6>[ 15.335780] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10740 10:57:06.368841 <6>[ 15.344815] Bluetooth: Core ver 2.22
10741 10:57:06.378702 <6>[ 15.345509] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10742 10:57:06.385291 <6>[ 15.346083] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10743 10:57:06.392032 <6>[ 15.346241] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10744 10:57:06.398617 <6>[ 15.346272] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10745 10:57:06.404931 <6>[ 15.346292] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10746 10:57:06.414817 <6>[ 15.346310] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10747 10:57:06.418628 <6>[ 15.346428] pci 0000:01:00.0: supports D1 D2
10748 10:57:06.425157 <6>[ 15.346431] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 10:57:06.437998 <6>[ 15.347103] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10750 10:57:06.444832 <6>[ 15.347275] usbcore: registered new interface driver uvcvideo
10751 10:57:06.451553 <6>[ 15.353404] usbcore: registered new interface driver r8153_ecm
10752 10:57:06.457994 <6>[ 15.355362] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10753 10:57:06.464436 <6>[ 15.355397] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10754 10:57:06.474901 <6>[ 15.355405] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10755 10:57:06.480927 <6>[ 15.355420] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10756 10:57:06.487871 <6>[ 15.355435] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10757 10:57:06.497906 <6>[ 15.355452] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10758 10:57:06.501049 <6>[ 15.355467] pci 0000:00:00.0: PCI bridge to [bus 01]
10759 10:57:06.510942 <6>[ 15.355475] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10760 10:57:06.517609 <6>[ 15.355702] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10761 10:57:06.524155 <6>[ 15.357105] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10762 10:57:06.527529 <6>[ 15.357360] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10763 10:57:06.534197 <6>[ 15.360625] NET: Registered PF_BLUETOOTH protocol family
10764 10:57:06.544127 <4>[ 15.374814] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10765 10:57:06.550372 <6>[ 15.379585] Bluetooth: HCI device and connection manager initialized
10766 10:57:06.554108 <6>[ 15.379614] Bluetooth: HCI socket layer initialized
10767 10:57:06.563667 <5>[ 15.382292] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10768 10:57:06.570184 <4>[ 15.387751] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10769 10:57:06.576908 <5>[ 15.391671] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10770 10:57:06.586803 <4>[ 15.391741] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10771 10:57:06.589948 <6>[ 15.391747] cfg80211: failed to load regulatory.db
10772 10:57:06.596745 <6>[ 15.395778] Bluetooth: L2CAP socket layer initialized
10773 10:57:06.603191 <6>[ 15.396535] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10774 10:57:06.606733 <6>[ 15.455383] r8152 2-1.3:1.0 eth0: v1.12.13
10775 10:57:06.613533 <6>[ 15.461368] Bluetooth: SCO socket layer initialized
10776 10:57:06.620130 <6>[ 15.482898] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10777 10:57:06.626587 <6>[ 15.497043] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10778 10:57:06.632896 <6>[ 15.535935] usbcore: registered new interface driver btusb
10779 10:57:06.642758 <4>[ 15.536817] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10780 10:57:06.649606 <3>[ 15.536826] Bluetooth: hci0: Failed to load firmware file (-2)
10781 10:57:06.656005 <3>[ 15.536829] Bluetooth: hci0: Failed to set up firmware (-2)
10782 10:57:06.665950 <4>[ 15.536834] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10783 10:57:06.672488 <6>[ 15.543406] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10784 10:57:06.696736 <6>[ 15.753973] mt7921e 0000:01:00.0: ASIC revision: 79610010
10785 10:57:06.805033 <4>[ 15.855553] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 10:57:06.817995 Begin: Loading essential drivers ... done.
10787 10:57:06.821036 Begin: Running /scripts/init-premount ... done.
10788 10:57:06.827823 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10789 10:57:06.837630 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10790 10:57:06.840757 Device /sys/class/net/enx0024323078ff found
10791 10:57:06.840840 done.
10792 10:57:06.913761 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10793 10:57:06.927413 <4>[ 15.978073] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 10:57:07.046440 <4>[ 16.097086] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 10:57:07.162554 <4>[ 16.212983] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 10:57:07.278339 <4>[ 16.328940] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 10:57:07.394169 <4>[ 16.444814] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 10:57:07.509996 <4>[ 16.560854] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 10:57:07.626288 <4>[ 16.676891] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 10:57:07.741927 <4>[ 16.792860] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 10:57:07.858127 <4>[ 16.908757] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 10:57:07.965153 <3>[ 17.022731] mt7921e 0000:01:00.0: hardware init failed
10803 10:57:08.028553 <6>[ 17.085823] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10804 10:57:08.076241 IP-Config: no response after 2 secs - giving up
10805 10:57:08.121511 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10806 10:57:08.124373 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10807 10:57:08.131488 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10808 10:57:08.140807 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10809 10:57:08.147813 host : mt8192-asurada-spherion-r0-cbg-8
10810 10:57:08.154075 domain : lava-rack
10811 10:57:08.157735 rootserver: 192.168.201.1 rootpath:
10812 10:57:08.157850 filename :
10813 10:57:08.178942 done.
10814 10:57:08.185661 Begin: Running /scripts/nfs-bottom ... done.
10815 10:57:08.203644 Begin: Running /scripts/init-bottom ... done.
10816 10:57:09.329593 <6>[ 18.386966] NET: Registered PF_INET6 protocol family
10817 10:57:09.336325 <6>[ 18.393744] Segment Routing with IPv6
10818 10:57:09.339284 <6>[ 18.397723] In-situ OAM (IOAM) with IPv6
10819 10:57:09.455733 <30>[ 18.493154] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10820 10:57:09.458882 <30>[ 18.516940] systemd[1]: Detected architecture arm64.
10821 10:57:09.479396
10822 10:57:09.482138 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10823 10:57:09.482245
10824 10:57:09.500245 <30>[ 18.557809] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10825 10:57:10.076971 <30>[ 19.131177] systemd[1]: Queued start job for default target Graphical Interface.
10826 10:57:10.115117 <30>[ 19.172455] systemd[1]: Created slice system-getty.slice.
10827 10:57:10.121480 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10828 10:57:10.138597 <30>[ 19.196049] systemd[1]: Created slice system-modprobe.slice.
10829 10:57:10.145270 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10830 10:57:10.163023 <30>[ 19.220650] systemd[1]: Created slice system-serial\x2dgetty.slice.
10831 10:57:10.173181 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10832 10:57:10.186664 <30>[ 19.243980] systemd[1]: Created slice User and Session Slice.
10833 10:57:10.193021 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10834 10:57:10.213831 <30>[ 19.268044] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10835 10:57:10.223318 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10836 10:57:10.241144 <30>[ 19.295608] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10837 10:57:10.248154 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10838 10:57:10.268416 <30>[ 19.319541] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10839 10:57:10.275071 <30>[ 19.331569] systemd[1]: Reached target Local Encrypted Volumes.
10840 10:57:10.281487 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10841 10:57:10.298387 <30>[ 19.355596] systemd[1]: Reached target Paths.
10842 10:57:10.301464 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10843 10:57:10.318444 <30>[ 19.375520] systemd[1]: Reached target Remote File Systems.
10844 10:57:10.324467 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10845 10:57:10.337922 <30>[ 19.395493] systemd[1]: Reached target Slices.
10846 10:57:10.341218 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10847 10:57:10.357581 <30>[ 19.415513] systemd[1]: Reached target Swap.
10848 10:57:10.361208 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10849 10:57:10.381587 <30>[ 19.435768] systemd[1]: Listening on initctl Compatibility Named Pipe.
10850 10:57:10.388312 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10851 10:57:10.394624 <30>[ 19.451273] systemd[1]: Listening on Journal Audit Socket.
10852 10:57:10.401453 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10853 10:57:10.415286 <30>[ 19.472582] systemd[1]: Listening on Journal Socket (/dev/log).
10854 10:57:10.421409 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10855 10:57:10.439101 <30>[ 19.496295] systemd[1]: Listening on Journal Socket.
10856 10:57:10.445486 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10857 10:57:10.462902 <30>[ 19.517064] systemd[1]: Listening on Network Service Netlink Socket.
10858 10:57:10.469281 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10859 10:57:10.484952 <30>[ 19.542528] systemd[1]: Listening on udev Control Socket.
10860 10:57:10.491390 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10861 10:57:10.506420 <30>[ 19.563774] systemd[1]: Listening on udev Kernel Socket.
10862 10:57:10.512689 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10863 10:57:10.562234 <30>[ 19.619700] systemd[1]: Mounting Huge Pages File System...
10864 10:57:10.568436 Mounting [0;1;39mHuge Pages File System[0m...
10865 10:57:10.587389 <30>[ 19.641732] systemd[1]: Mounting POSIX Message Queue File System...
10866 10:57:10.590643 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10867 10:57:10.622157 <30>[ 19.679662] systemd[1]: Mounting Kernel Debug File System...
10868 10:57:10.628863 Mounting [0;1;39mKernel Debug File System[0m...
10869 10:57:10.645626 <30>[ 19.699875] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10870 10:57:10.663546 <30>[ 19.717797] systemd[1]: Starting Create list of static device nodes for the current kernel...
10871 10:57:10.670135 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10872 10:57:10.688617 <30>[ 19.746096] systemd[1]: Starting Load Kernel Module configfs...
10873 10:57:10.694826 Starting [0;1;39mLoad Kernel Module configfs[0m...
10874 10:57:10.712240 <30>[ 19.769965] systemd[1]: Starting Load Kernel Module drm...
10875 10:57:10.718488 Starting [0;1;39mLoad Kernel Module drm[0m...
10876 10:57:10.736667 <30>[ 19.794005] systemd[1]: Starting Load Kernel Module fuse...
10877 10:57:10.743045 Starting [0;1;39mLoad Kernel Module fuse[0m...
10878 10:57:10.776447 <6>[ 19.834206] fuse: init (API version 7.37)
10879 10:57:10.786458 <30>[ 19.839813] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10880 10:57:10.795822 <30>[ 19.853654] systemd[1]: Starting Journal Service...
10881 10:57:10.799342 Starting [0;1;39mJournal Service[0m...
10882 10:57:10.825972 <30>[ 19.883804] systemd[1]: Starting Load Kernel Modules...
10883 10:57:10.832761 Starting [0;1;39mLoad Kernel Modules[0m...
10884 10:57:10.851747 <30>[ 19.906284] systemd[1]: Starting Remount Root and Kernel File Systems...
10885 10:57:10.858729 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10886 10:57:10.873091 <30>[ 19.930575] systemd[1]: Starting Coldplug All udev Devices...
10887 10:57:10.879545 Starting [0;1;39mColdplug All udev Devices[0m...
10888 10:57:10.897156 <30>[ 19.954599] systemd[1]: Mounted Huge Pages File System.
10889 10:57:10.903271 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10890 10:57:10.918369 <30>[ 19.975900] systemd[1]: Mounted POSIX Message Queue File System.
10891 10:57:10.924975 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10892 10:57:10.942400 <30>[ 19.999740] systemd[1]: Mounted Kernel Debug File System.
10893 10:57:10.952129 <3>[ 20.003455] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 10:57:10.958924 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10895 10:57:10.978594 <30>[ 20.032379] systemd[1]: Finished Create list of static device nodes for the current kernel.
10896 10:57:10.988656 <3>[ 20.035680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 10:57:10.994563 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10898 10:57:11.010500 <30>[ 20.068452] systemd[1]: modprobe@configfs.service: Succeeded.
10899 10:57:11.017942 <30>[ 20.075606] systemd[1]: Finished Load Kernel Module configfs.
10900 10:57:11.024743 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10901 10:57:11.034613 <3>[ 20.088013] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 10:57:11.043275 <30>[ 20.100623] systemd[1]: modprobe@drm.service: Succeeded.
10903 10:57:11.050112 <30>[ 20.106868] systemd[1]: Finished Load Kernel Module drm.
10904 10:57:11.063165 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 20.117555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 10:57:11.063259 .
10906 10:57:11.078476 <30>[ 20.136332] systemd[1]: modprobe@fuse.service: Succeeded.
10907 10:57:11.085824 <30>[ 20.142658] systemd[1]: Finished Load Kernel Module fuse.
10908 10:57:11.095708 <3>[ 20.147489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 10:57:11.102348 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10910 10:57:11.119848 <30>[ 20.176812] systemd[1]: Finished Load Kernel Modules.
10911 10:57:11.129700 <3>[ 20.180057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 10:57:11.132790 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10913 10:57:11.156948 <3>[ 20.211440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 10:57:11.163769 <30>[ 20.212590] systemd[1]: Finished Remount Root and Kernel File Systems.
10915 10:57:11.170076 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10916 10:57:11.192505 <3>[ 20.247030] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 10:57:11.221680 <3>[ 20.276430] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 10:57:11.228363 <30>[ 20.279747] systemd[1]: Mounting FUSE Control File System...
10919 10:57:11.235157 Mounting [0;1;39mFUSE Control File System[0m...
10920 10:57:11.253168 <30>[ 20.310064] systemd[1]: Mounting Kernel Configuration File System...
10921 10:57:11.262820 <3>[ 20.313755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 10:57:11.269467 Mounting [0;1;39mKernel Configuration File System[0m...
10923 10:57:11.291231 <3>[ 20.345624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 10:57:11.301200 <30>[ 20.349209] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10925 10:57:11.310844 <30>[ 20.363428] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10926 10:57:11.325344 <3>[ 20.379520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 10:57:11.338261 <30>[ 20.395967] systemd[1]: Starting Load/Save Random Seed...
10928 10:57:11.345390 Starting [0;1;39mLoad/Save Random Seed[0m...
10929 10:57:11.355604 <3>[ 20.409731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 10:57:11.364224 <30>[ 20.421944] systemd[1]: Starting Apply Kernel Variables...
10931 10:57:11.370815 Starting [0;1;39mApply Kernel Variables[0m...
10932 10:57:11.389574 <30>[ 20.447073] systemd[1]: Starting Create System Users...
10933 10:57:11.399760 <3>[ 20.451234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:57:11.403063 Starting [0;1;39mCreate System Users[0m...
10935 10:57:11.419543 <30>[ 20.477193] systemd[1]: Mounted FUSE Control File System.
10936 10:57:11.426118 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10937 10:57:11.442407 <30>[ 20.499908] systemd[1]: Mounted Kernel Configuration File System.
10938 10:57:11.449139 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10939 10:57:11.472680 <4>[ 20.520433] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10940 10:57:11.482645 <3>[ 20.536100] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10941 10:57:11.485805 <30>[ 20.536478] systemd[1]: Started Journal Service.
10942 10:57:11.492591 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10943 10:57:11.512021 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10944 10:57:11.529986 See 'systemctl status systemd-udev-trigger.service' for details.
10945 10:57:11.550697 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10946 10:57:11.566564 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10947 10:57:11.582572 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10948 10:57:11.626820 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10949 10:57:11.644368 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10950 10:57:11.691447 <46>[ 20.745779] systemd-journald[295]: Received client request to flush runtime journal.
10951 10:57:11.815103 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10952 10:57:11.826324 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10953 10:57:11.841652 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10954 10:57:11.897763 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10955 10:57:13.065988 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10956 10:57:13.102297 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10957 10:57:13.157065 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10958 10:57:13.215383 Starting [0;1;39mNetwork Service[0m...
10959 10:57:13.511891 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10960 10:57:13.554226 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10961 10:57:13.572759 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10962 10:57:13.756634 <6>[ 22.814579] remoteproc remoteproc0: powering up scp
10963 10:57:13.795460 <4>[ 22.850303] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10964 10:57:13.802420 <3>[ 22.860197] remoteproc remoteproc0: request_firmware failed: -2
10965 10:57:13.812251 <3>[ 22.867271] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10966 10:57:13.925210 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10967 10:57:13.942530 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10968 10:57:13.962108 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10969 10:57:13.995964 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10970 10:57:14.012974 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10971 10:57:14.054243 Starting [0;1;39mNetwork Name Resolution[0m...
10972 10:57:14.089029 Starting [0;1;39mNetwork Time Synchronization[0m...
10973 10:57:14.108036 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10974 10:57:14.129010 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10975 10:57:14.159928 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10976 10:57:14.184551 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10977 10:57:14.522803 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10978 10:57:14.542204 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10979 10:57:14.560875 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10980 10:57:14.578080 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10981 10:57:14.593317 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10982 10:57:14.652479 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10983 10:57:14.675962 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10984 10:57:14.696143 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10985 10:57:14.716051 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10986 10:57:14.729747 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10987 10:57:14.750681 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10988 10:57:14.765671 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10989 10:57:14.781710 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10990 10:57:14.821912 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10991 10:57:14.863527 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10992 10:57:14.902943 Starting [0;1;39mUser Login Management[0m...
10993 10:57:14.918207 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10994 10:57:14.933893 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10995 10:57:14.952853 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10996 10:57:14.997828 Starting [0;1;39mPermit User Sessions[0m...
10997 10:57:15.118095 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10998 10:57:15.173228 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10999 10:57:15.192091 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11000 10:57:15.208587 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11001 10:57:15.229750 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11002 10:57:15.246016 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11003 10:57:15.265541 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11004 10:57:15.280318 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11005 10:57:15.323913 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11006 10:57:15.362969 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11007 10:57:15.474714
11008 10:57:15.474922
11009 10:57:15.478025 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11010 10:57:15.478137
11011 10:57:15.481059 debian-bullseye-arm64 login: root (automatic login)
11012 10:57:15.481170
11013 10:57:15.481256
11014 10:57:15.804340 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11015 10:57:15.804516
11016 10:57:15.810389 The programs included with the Debian GNU/Linux system are free software;
11017 10:57:15.817392 the exact distribution terms for each program are described in the
11018 10:57:15.820334 individual files in /usr/share/doc/*/copyright.
11019 10:57:15.820417
11020 10:57:15.827215 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11021 10:57:15.830474 permitted by applicable law.
11022 10:57:16.872644 Matched prompt #10: / #
11024 10:57:16.872922 Setting prompt string to ['/ #']
11025 10:57:16.873020 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11027 10:57:16.873219 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11028 10:57:16.873308 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
11029 10:57:16.873379 Setting prompt string to ['/ #']
11030 10:57:16.873442 Forcing a shell prompt, looking for ['/ #']
11032 10:57:16.923667 / #
11033 10:57:16.923792 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11034 10:57:16.923877 Waiting using forced prompt support (timeout 00:02:30)
11035 10:57:16.928797
11036 10:57:16.929074 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11037 10:57:16.929168 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
11039 10:57:17.029526 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r'
11040 10:57:17.034804 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591009/extract-nfsrootfs-neotsm7r'
11042 10:57:17.135370 / # export NFS_SERVER_IP='192.168.201.1'
11043 10:57:17.140211 export NFS_SERVER_IP='192.168.201.1'
11044 10:57:17.140497 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11045 10:57:17.140600 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
11046 10:57:17.140694 end: 2 depthcharge-action (duration 00:01:41) [common]
11047 10:57:17.140784 start: 3 lava-test-retry (timeout 00:07:36) [common]
11048 10:57:17.140872 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
11049 10:57:17.140952 Using namespace: common
11051 10:57:17.241284 / # #
11052 10:57:17.241428 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11053 10:57:17.246257 #
11054 10:57:17.246527 Using /lava-10591009
11056 10:57:17.346864 / # export SHELL=/bin/bash
11057 10:57:17.352063 export SHELL=/bin/bash
11059 10:57:17.452607 / # . /lava-10591009/environment
11060 10:57:17.457812 . /lava-10591009/environment
11062 10:57:17.562807 / # /lava-10591009/bin/lava-test-runner /lava-10591009/0
11063 10:57:17.562956 Test shell timeout: 10s (minimum of the action and connection timeout)
11064 10:57:17.567551 /lava-10591009/bin/lava-test-runner /lava-10591009/0
11065 10:57:17.841519 + export TESTRUN_ID=0_timesync-off
11066 10:57:17.844618 + TESTRUN_ID=0_timesync-off
11067 10:57:17.847850 + cd /lava-10591009/0/tests/0_timesync-off
11068 10:57:17.851140 ++ cat uuid
11069 10:57:17.857171 + UUID=10591009_1.6.2.3.1
11070 10:57:17.860874 + set +x
11071 10:57:17.863821 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10591009_1.6.2.3.1>
11072 10:57:17.864085 Received signal: <STARTRUN> 0_timesync-off 10591009_1.6.2.3.1
11073 10:57:17.864160 Starting test lava.0_timesync-off (10591009_1.6.2.3.1)
11074 10:57:17.864249 Skipping test definition patterns.
11075 10:57:17.867424 + systemctl stop systemd-timesyncd
11076 10:57:17.905072 + set +x
11077 10:57:17.908224 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10591009_1.6.2.3.1>
11078 10:57:17.908485 Received signal: <ENDRUN> 0_timesync-off 10591009_1.6.2.3.1
11079 10:57:17.908594 Ending use of test pattern.
11080 10:57:17.908688 Ending test lava.0_timesync-off (10591009_1.6.2.3.1), duration 0.04
11082 10:57:17.987826 + export TESTRUN_ID=1_kselftest-arm64
11083 10:57:17.988071 + TESTRUN_ID=1_kselftest-arm64
11084 10:57:17.994775 + cd /lava-10591009/0/tests/1_kselftest-arm64
11085 10:57:17.994910 ++ cat uuid
11086 10:57:18.000779 + UUID=10591009_1.6.2.3.5
11087 10:57:18.000864 + set +x
11088 10:57:18.007011 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10591009_1.6.2.3.5>
11089 10:57:18.007309 Received signal: <STARTRUN> 1_kselftest-arm64 10591009_1.6.2.3.5
11090 10:57:18.007385 Starting test lava.1_kselftest-arm64 (10591009_1.6.2.3.5)
11091 10:57:18.007468 Skipping test definition patterns.
11092 10:57:18.010676 + cd ./automated/linux/kselftest/
11093 10:57:18.037022 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11094 10:57:18.074126 INFO: install_deps skipped
11095 10:57:18.197052 --2023-06-05 10:57:18-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11096 10:57:18.203587 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11097 10:57:18.348447 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11098 10:57:18.494597 HTTP request sent, awaiting response... 200 OK
11099 10:57:18.498302 Length: 2712696 (2.6M) [application/octet-stream]
11100 10:57:18.501360 Saving to: 'kselftest.tar.xz'
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11111 10:57:19.964423
11112 10:57:25.388991 skiplist:
11113 10:57:25.391920 ========================================
11114 10:57:25.395578 ========================================
11115 10:57:25.443117 arm64:tags_test
11116 10:57:25.446316 arm64:run_tags_test.sh
11117 10:57:25.446397 arm64:fake_sigreturn_bad_magic
11118 10:57:25.449568 arm64:fake_sigreturn_bad_size
11119 10:57:25.452786 arm64:fake_sigreturn_bad_size_for_magic0
11120 10:57:25.456042 arm64:fake_sigreturn_duplicated_fpsimd
11121 10:57:25.459828 arm64:fake_sigreturn_misaligned_sp
11122 10:57:25.462968 arm64:fake_sigreturn_missing_fpsimd
11123 10:57:25.466140 arm64:fake_sigreturn_sme_change_vl
11124 10:57:25.469319 arm64:fake_sigreturn_sve_change_vl
11125 10:57:25.472943 arm64:mangle_pstate_invalid_compat_toggle
11126 10:57:25.475898 arm64:mangle_pstate_invalid_daif_bits
11127 10:57:25.479570 arm64:mangle_pstate_invalid_mode_el1h
11128 10:57:25.482460 arm64:mangle_pstate_invalid_mode_el1t
11129 10:57:25.486091 arm64:mangle_pstate_invalid_mode_el2h
11130 10:57:25.488986 arm64:mangle_pstate_invalid_mode_el2t
11131 10:57:25.492489 arm64:mangle_pstate_invalid_mode_el3h
11132 10:57:25.499421 arm64:mangle_pstate_invalid_mode_el3t
11133 10:57:25.499503 arm64:sme_trap_no_sm
11134 10:57:25.502459 arm64:sme_trap_non_streaming
11135 10:57:25.502532 arm64:sme_trap_za
11136 10:57:25.505689 arm64:sme_vl
11137 10:57:25.505763 arm64:ssve_regs
11138 10:57:25.509043 arm64:sve_regs
11139 10:57:25.509116 arm64:sve_vl
11140 10:57:25.509176 arm64:za_no_regs
11141 10:57:25.512230 arm64:za_regs
11142 10:57:25.512299 arm64:pac
11143 10:57:25.515389 arm64:fp-stress
11144 10:57:25.515485 arm64:sve-ptrace
11145 10:57:25.519669 arm64:sve-probe-vls
11146 10:57:25.519757 arm64:vec-syscfg
11147 10:57:25.519835 arm64:za-fork
11148 10:57:25.522235 arm64:za-ptrace
11149 10:57:25.525725 arm64:check_buffer_fill
11150 10:57:25.525844 arm64:check_child_memory
11151 10:57:25.528754 arm64:check_gcr_el1_cswitch
11152 10:57:25.532295 arm64:check_ksm_options
11153 10:57:25.532393 arm64:check_mmap_options
11154 10:57:25.535592 arm64:check_prctl
11155 10:57:25.538669 arm64:check_tags_inclusion
11156 10:57:25.538768 arm64:check_user_mem
11157 10:57:25.542153 arm64:btitest
11158 10:57:25.542253 arm64:nobtitest
11159 10:57:25.542341 arm64:hwcap
11160 10:57:25.545034 arm64:ptrace
11161 10:57:25.545130 arm64:syscall-abi
11162 10:57:25.548905 arm64:tpidr2
11163 10:57:25.552087 ============== Tests to run ===============
11164 10:57:25.552163 arm64:tags_test
11165 10:57:25.555189 arm64:run_tags_test.sh
11166 10:57:25.558371 arm64:fake_sigreturn_bad_magic
11167 10:57:25.561567 arm64:fake_sigreturn_bad_size
11168 10:57:25.564785 arm64:fake_sigreturn_bad_size_for_magic0
11169 10:57:25.568551 arm64:fake_sigreturn_duplicated_fpsimd
11170 10:57:25.571731 arm64:fake_sigreturn_misaligned_sp
11171 10:57:25.575149 arm64:fake_sigreturn_missing_fpsimd
11172 10:57:25.578120 arm64:fake_sigreturn_sme_change_vl
11173 10:57:25.581665 arm64:fake_sigreturn_sve_change_vl
11174 10:57:25.584580 arm64:mangle_pstate_invalid_compat_toggle
11175 10:57:25.588166 arm64:mangle_pstate_invalid_daif_bits
11176 10:57:25.591627 arm64:mangle_pstate_invalid_mode_el1h
11177 10:57:25.594954 arm64:mangle_pstate_invalid_mode_el1t
11178 10:57:25.598018 arm64:mangle_pstate_invalid_mode_el2h
11179 10:57:25.601571 arm64:mangle_pstate_invalid_mode_el2t
11180 10:57:25.604453 arm64:mangle_pstate_invalid_mode_el3h
11181 10:57:25.607934 arm64:mangle_pstate_invalid_mode_el3t
11182 10:57:25.608058 arm64:sme_trap_no_sm
11183 10:57:25.610969 arm64:sme_trap_non_streaming
11184 10:57:25.614811 arm64:sme_trap_za
11185 10:57:25.614930 arm64:sme_vl
11186 10:57:25.618127 arm64:ssve_regs
11187 10:57:25.618208 arm64:sve_regs
11188 10:57:25.618272 arm64:sve_vl
11189 10:57:25.621341 arm64:za_no_regs
11190 10:57:25.621423 arm64:za_regs
11191 10:57:25.621487 arm64:pac
11192 10:57:25.624456 arm64:fp-stress
11193 10:57:25.624537 arm64:sve-ptrace
11194 10:57:25.628067 arm64:sve-probe-vls
11195 10:57:25.628149 arm64:vec-syscfg
11196 10:57:25.630981 arm64:za-fork
11197 10:57:25.631062 arm64:za-ptrace
11198 10:57:25.634467 arm64:check_buffer_fill
11199 10:57:25.637392 arm64:check_child_memory
11200 10:57:25.637474 arm64:check_gcr_el1_cswitch
11201 10:57:25.640954 arm64:check_ksm_options
11202 10:57:25.644226 arm64:check_mmap_options
11203 10:57:25.644308 arm64:check_prctl
11204 10:57:25.647449 arm64:check_tags_inclusion
11205 10:57:25.650590 arm64:check_user_mem
11206 10:57:25.650672 arm64:btitest
11207 10:57:25.650736 arm64:nobtitest
11208 10:57:25.654360 arm64:hwcap
11209 10:57:25.654441 arm64:ptrace
11210 10:57:25.657277 arm64:syscall-abi
11211 10:57:25.657362 arm64:tpidr2
11212 10:57:25.660472 ===========End Tests to run ===============
11213 10:57:25.899777 <12>[ 34.959046] kselftest: Running tests in arm64
11214 10:57:25.908948 TAP version 13
11215 10:57:25.922221 1..48
11216 10:57:25.938617 # selftests: arm64: tags_test
11217 10:57:26.333887 ok 1 selftests: arm64: tags_test
11218 10:57:26.348767 # selftests: arm64: run_tags_test.sh
11219 10:57:26.403776 # --------------------
11220 10:57:26.407066 # running tags test
11221 10:57:26.407155 # --------------------
11222 10:57:26.410295 # [PASS]
11223 10:57:26.413489 ok 2 selftests: arm64: run_tags_test.sh
11224 10:57:26.424106 # selftests: arm64: fake_sigreturn_bad_magic
11225 10:57:26.472959 # Registered handlers for all signals.
11226 10:57:26.473086 # Detected MINSTKSIGSZ:4720
11227 10:57:26.476539 # Testcase initialized.
11228 10:57:26.479571 # uc context validated.
11229 10:57:26.483337 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11230 10:57:26.486262 # Handled SIG_COPYCTX
11231 10:57:26.486339 # Available space:3568
11232 10:57:26.493174 # Using badly built context - ERR: BAD MAGIC !
11233 10:57:26.499315 # SIG_OK -- SP:0xFFFFCFDFE8B0 si_addr@:0xffffcfdfe8b0 si_code:2 token@:0xffffcfdfd650 offset:-4704
11234 10:57:26.503027 # ==>> completed. PASS(1)
11235 10:57:26.509654 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11236 10:57:26.515968 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCFDFD650
11237 10:57:26.522794 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11238 10:57:26.526005 # selftests: arm64: fake_sigreturn_bad_size
11239 10:57:26.542232 # Registered handlers for all signals.
11240 10:57:26.542385 # Detected MINSTKSIGSZ:4720
11241 10:57:26.545388 # Testcase initialized.
11242 10:57:26.548534 # uc context validated.
11243 10:57:26.552315 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11244 10:57:26.555493 # Handled SIG_COPYCTX
11245 10:57:26.555602 # Available space:3568
11246 10:57:26.558513 # uc context validated.
11247 10:57:26.565477 # Using badly built context - ERR: Bad size for esr_context
11248 10:57:26.572120 # SIG_OK -- SP:0xFFFFF6EA0440 si_addr@:0xfffff6ea0440 si_code:2 token@:0xfffff6e9f1e0 offset:-4704
11249 10:57:26.575203 # ==>> completed. PASS(1)
11250 10:57:26.581981 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11251 10:57:26.588728 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF6E9F1E0
11252 10:57:26.591811 ok 4 selftests: arm64: fake_sigreturn_bad_size
11253 10:57:26.598634 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11254 10:57:26.609296 # Registered handlers for all signals.
11255 10:57:26.609384 # Detected MINSTKSIGSZ:4720
11256 10:57:26.613057 # Testcase initialized.
11257 10:57:26.616044 # uc context validated.
11258 10:57:26.619874 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11259 10:57:26.622726 # Handled SIG_COPYCTX
11260 10:57:26.622810 # Available space:3568
11261 10:57:26.629200 # Using badly built context - ERR: Bad size for terminator
11262 10:57:26.639251 # SIG_OK -- SP:0xFFFFF3102880 si_addr@:0xfffff3102880 si_code:2 token@:0xfffff3101620 offset:-4704
11263 10:57:26.639336 # ==>> completed. PASS(1)
11264 10:57:26.649074 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11265 10:57:26.655408 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF3101620
11266 10:57:26.659202 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11267 10:57:26.665475 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11268 10:57:26.675100 # Registered handlers for all signals.
11269 10:57:26.675216 # Detected MINSTKSIGSZ:4720
11270 10:57:26.678834 # Testcase initialized.
11271 10:57:26.682118 # uc context validated.
11272 10:57:26.685333 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11273 10:57:26.688452 # Handled SIG_COPYCTX
11274 10:57:26.688558 # Available space:3568
11275 10:57:26.695034 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11276 10:57:26.705261 # SIG_OK -- SP:0xFFFFF1F841E0 si_addr@:0xfffff1f841e0 si_code:2 token@:0xfffff1f82f80 offset:-4704
11277 10:57:26.705370 # ==>> completed. PASS(1)
11278 10:57:26.714836 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11279 10:57:26.721816 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF1F82F80
11280 10:57:26.724673 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11281 10:57:26.728393 # selftests: arm64: fake_sigreturn_misaligned_sp
11282 10:57:26.744324 # Registered handlers for all signals.
11283 10:57:26.744484 # Detected MINSTKSIGSZ:4720
11284 10:57:26.747494 # Testcase initialized.
11285 10:57:26.751145 # uc context validated.
11286 10:57:26.754293 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11287 10:57:26.757537 # Handled SIG_COPYCTX
11288 10:57:26.764433 # SIG_OK -- SP:0xFFFFC82E6D63 si_addr@:0xffffc82e6d63 si_code:2 token@:0xffffc82e6d63 offset:0
11289 10:57:26.767558 # ==>> completed. PASS(1)
11290 10:57:26.773794 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11291 10:57:26.780441 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC82E6D63
11292 10:57:26.787537 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11293 10:57:26.790695 # selftests: arm64: fake_sigreturn_missing_fpsimd
11294 10:57:26.812939 # Registered handlers for all signals.
11295 10:57:26.813052 # Detected MINSTKSIGSZ:4720
11296 10:57:26.816473 # Testcase initialized.
11297 10:57:26.819738 # uc context validated.
11298 10:57:26.822977 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11299 10:57:26.826092 # Handled SIG_COPYCTX
11300 10:57:26.829197 # Mangling template header. Spare space:4096
11301 10:57:26.833272 # Using badly built context - ERR: Missing FPSIMD
11302 10:57:26.842737 # SIG_OK -- SP:0xFFFFC70DE910 si_addr@:0xffffc70de910 si_code:2 token@:0xffffc70dd6b0 offset:-4704
11303 10:57:26.845841 # ==>> completed. PASS(1)
11304 10:57:26.852704 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11305 10:57:26.858869 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC70DD6B0
11306 10:57:26.862100 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11307 10:57:26.869062 # selftests: arm64: fake_sigreturn_sme_change_vl
11308 10:57:26.883257 # Registered handlers for all signals.
11309 10:57:26.883341 # Detected MINSTKSIGSZ:4720
11310 10:57:26.886327 # ==>> completed. SKIP.
11311 10:57:26.892800 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11312 10:57:26.896582 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11313 10:57:26.902681 # selftests: arm64: fake_sigreturn_sve_change_vl
11314 10:57:26.950862 # Registered handlers for all signals.
11315 10:57:26.950976 # Detected MINSTKSIGSZ:4720
11316 10:57:26.953965 # ==>> completed. SKIP.
11317 10:57:26.960831 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11318 10:57:26.964119 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11319 10:57:26.970255 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11320 10:57:27.019376 # Registered handlers for all signals.
11321 10:57:27.019476 # Detected MINSTKSIGSZ:4720
11322 10:57:27.022395 # Testcase initialized.
11323 10:57:27.025939 # uc context validated.
11324 10:57:27.026047 # Handled SIG_TRIG
11325 10:57:27.035680 # SIG_OK -- SP:0xFFFFE8300660 si_addr@:0xffffe8300660 si_code:2 token@:(nil) offset:-281474577204832
11326 10:57:27.038799 # ==>> completed. PASS(1)
11327 10:57:27.045907 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11328 10:57:27.051932 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11329 10:57:27.055513 # selftests: arm64: mangle_pstate_invalid_daif_bits
11330 10:57:27.088664 # Registered handlers for all signals.
11331 10:57:27.088759 # Detected MINSTKSIGSZ:4720
11332 10:57:27.091761 # Testcase initialized.
11333 10:57:27.095449 # uc context validated.
11334 10:57:27.095520 # Handled SIG_TRIG
11335 10:57:27.104805 # SIG_OK -- SP:0xFFFFCDE26A70 si_addr@:0xffffcde26a70 si_code:2 token@:(nil) offset:-281474135911024
11336 10:57:27.108302 # ==>> completed. PASS(1)
11337 10:57:27.114909 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11338 10:57:27.118088 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11339 10:57:27.124373 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11340 10:57:27.159283 # Registered handlers for all signals.
11341 10:57:27.159368 # Detected MINSTKSIGSZ:4720
11342 10:57:27.162265 # Testcase initialized.
11343 10:57:27.165429 # uc context validated.
11344 10:57:27.165500 # Handled SIG_TRIG
11345 10:57:27.175503 # SIG_OK -- SP:0xFFFFC6C0AD10 si_addr@:0xffffc6c0ad10 si_code:2 token@:(nil) offset:-281474016259344
11346 10:57:27.178592 # ==>> completed. PASS(1)
11347 10:57:27.185590 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11348 10:57:27.188840 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11349 10:57:27.195261 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11350 10:57:27.229700 # Registered handlers for all signals.
11351 10:57:27.229788 # Detected MINSTKSIGSZ:4720
11352 10:57:27.233460 # Testcase initialized.
11353 10:57:27.236707 # uc context validated.
11354 10:57:27.236792 # Handled SIG_TRIG
11355 10:57:27.246625 # SIG_OK -- SP:0xFFFFE2095A90 si_addr@:0xffffe2095a90 si_code:2 token@:(nil) offset:-281474474007184
11356 10:57:27.249700 # ==>> completed. PASS(1)
11357 10:57:27.256472 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11358 10:57:27.259691 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11359 10:57:27.265913 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11360 10:57:27.299639 # Registered handlers for all signals.
11361 10:57:27.299734 # Detected MINSTKSIGSZ:4720
11362 10:57:27.302808 # Testcase initialized.
11363 10:57:27.306049 # uc context validated.
11364 10:57:27.306145 # Handled SIG_TRIG
11365 10:57:27.315790 # SIG_OK -- SP:0xFFFFF3372630 si_addr@:0xfffff3372630 si_code:2 token@:(nil) offset:-281474762221104
11366 10:57:27.319432 # ==>> completed. PASS(1)
11367 10:57:27.326003 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11368 10:57:27.328956 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11369 10:57:27.335658 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11370 10:57:27.367548 # Registered handlers for all signals.
11371 10:57:27.367647 # Detected MINSTKSIGSZ:4720
11372 10:57:27.370663 # Testcase initialized.
11373 10:57:27.373772 # uc context validated.
11374 10:57:27.373858 # Handled SIG_TRIG
11375 10:57:27.383815 # SIG_OK -- SP:0xFFFFEB985A60 si_addr@:0xffffeb985a60 si_code:2 token@:(nil) offset:-281474634373728
11376 10:57:27.387445 # ==>> completed. PASS(1)
11377 10:57:27.393655 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11378 10:57:27.397417 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11379 10:57:27.403812 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11380 10:57:27.436147 # Registered handlers for all signals.
11381 10:57:27.436273 # Detected MINSTKSIGSZ:4720
11382 10:57:27.439908 # Testcase initialized.
11383 10:57:27.442953 # uc context validated.
11384 10:57:27.443054 # Handled SIG_TRIG
11385 10:57:27.453048 # SIG_OK -- SP:0xFFFFFBFC82B0 si_addr@:0xfffffbfc82b0 si_code:2 token@:(nil) offset:-281474909373104
11386 10:57:27.456293 # ==>> completed. PASS(1)
11387 10:57:27.462618 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11388 10:57:27.466110 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11389 10:57:27.472418 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11390 10:57:27.505371 # Registered handlers for all signals.
11391 10:57:27.505484 # Detected MINSTKSIGSZ:4720
11392 10:57:27.508674 # Testcase initialized.
11393 10:57:27.511714 # uc context validated.
11394 10:57:27.511789 # Handled SIG_TRIG
11395 10:57:27.521875 # SIG_OK -- SP:0xFFFFFB841550 si_addr@:0xfffffb841550 si_code:2 token@:(nil) offset:-281474901480784
11396 10:57:27.524832 # ==>> completed. PASS(1)
11397 10:57:27.531349 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11398 10:57:27.534986 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11399 10:57:27.538004 # selftests: arm64: sme_trap_no_sm
11400 10:57:27.572429 # Registered handlers for all signals.
11401 10:57:27.572522 # Detected MINSTKSIGSZ:4720
11402 10:57:27.575578 # ==>> completed. SKIP.
11403 10:57:27.584915 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11404 10:57:27.588640 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11405 10:57:27.591860 # selftests: arm64: sme_trap_non_streaming
11406 10:57:27.641308 # Registered handlers for all signals.
11407 10:57:27.641401 # Detected MINSTKSIGSZ:4720
11408 10:57:27.644719 # ==>> completed. SKIP.
11409 10:57:27.654244 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11410 10:57:27.661220 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11411 10:57:27.664375 # selftests: arm64: sme_trap_za
11412 10:57:27.709637 # Registered handlers for all signals.
11413 10:57:27.709732 # Detected MINSTKSIGSZ:4720
11414 10:57:27.713455 # Testcase initialized.
11415 10:57:27.723046 # SIG_OK -- SP:0xFFFFE61AF330 si_addr@:0xaaaad7a82510 si_code:1 token@:(nil) offset:-187650739283216
11416 10:57:27.723142 # ==>> completed. PASS(1)
11417 10:57:27.733040 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11418 10:57:27.736112 ok 21 selftests: arm64: sme_trap_za
11419 10:57:27.736196 # selftests: arm64: sme_vl
11420 10:57:27.778525 # Registered handlers for all signals.
11421 10:57:27.778638 # Detected MINSTKSIGSZ:4720
11422 10:57:27.782219 # ==>> completed. SKIP.
11423 10:57:27.788429 # # SME VL :: Check that we get the right SME VL reported
11424 10:57:27.791935 ok 22 selftests: arm64: sme_vl # SKIP
11425 10:57:27.794984 # selftests: arm64: ssve_regs
11426 10:57:27.848334 # Registered handlers for all signals.
11427 10:57:27.848436 # Detected MINSTKSIGSZ:4720
11428 10:57:27.851516 # ==>> completed. SKIP.
11429 10:57:27.858124 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11430 10:57:27.864353 ok 23 selftests: arm64: ssve_regs # SKIP
11431 10:57:27.864436 # selftests: arm64: sve_regs
11432 10:57:27.916755 # Registered handlers for all signals.
11433 10:57:27.916889 # Detected MINSTKSIGSZ:4720
11434 10:57:27.920454 # ==>> completed. SKIP.
11435 10:57:27.926774 # # SVE registers :: Check that we get the right SVE registers reported
11436 10:57:27.929986 ok 24 selftests: arm64: sve_regs # SKIP
11437 10:57:27.933022 # selftests: arm64: sve_vl
11438 10:57:27.986717 # Registered handlers for all signals.
11439 10:57:27.986865 # Detected MINSTKSIGSZ:4720
11440 10:57:27.990454 # ==>> completed. SKIP.
11441 10:57:27.996610 # # SVE VL :: Check that we get the right SVE VL reported
11442 10:57:28.000306 ok 25 selftests: arm64: sve_vl # SKIP
11443 10:57:28.003491 # selftests: arm64: za_no_regs
11444 10:57:28.057135 # Registered handlers for all signals.
11445 10:57:28.057236 # Detected MINSTKSIGSZ:4720
11446 10:57:28.060525 # ==>> completed. SKIP.
11447 10:57:28.067308 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11448 10:57:28.070399 ok 26 selftests: arm64: za_no_regs # SKIP
11449 10:57:28.074031 # selftests: arm64: za_regs
11450 10:57:28.127974 # Registered handlers for all signals.
11451 10:57:28.128082 # Detected MINSTKSIGSZ:4720
11452 10:57:28.131387 # ==>> completed. SKIP.
11453 10:57:28.137692 # # ZA register :: Check that we get the right ZA registers reported
11454 10:57:28.140764 ok 27 selftests: arm64: za_regs # SKIP
11455 10:57:28.143992 # selftests: arm64: pac
11456 10:57:28.193597 # TAP version 13
11457 10:57:28.193704 # 1..7
11458 10:57:28.197256 # # Starting 7 tests from 1 test cases.
11459 10:57:28.200498 # # RUN global.corrupt_pac ...
11460 10:57:28.203354 # # SKIP PAUTH not enabled
11461 10:57:28.206955 # # OK global.corrupt_pac
11462 10:57:28.210119 # ok 1 # SKIP PAUTH not enabled
11463 10:57:28.216426 # # RUN global.pac_instructions_not_nop ...
11464 10:57:28.219987 # # SKIP PAUTH not enabled
11465 10:57:28.223188 # # OK global.pac_instructions_not_nop
11466 10:57:28.226329 # ok 2 # SKIP PAUTH not enabled
11467 10:57:28.233520 # # RUN global.pac_instructions_not_nop_generic ...
11468 10:57:28.236487 # # SKIP Generic PAUTH not enabled
11469 10:57:28.240121 # # OK global.pac_instructions_not_nop_generic
11470 10:57:28.246483 # ok 3 # SKIP Generic PAUTH not enabled
11471 10:57:28.250019 # # RUN global.single_thread_different_keys ...
11472 10:57:28.253201 # # SKIP PAUTH not enabled
11473 10:57:28.259477 # # OK global.single_thread_different_keys
11474 10:57:28.259562 # ok 4 # SKIP PAUTH not enabled
11475 10:57:28.266343 # # RUN global.exec_changed_keys ...
11476 10:57:28.269442 # # SKIP PAUTH not enabled
11477 10:57:28.272496 # # OK global.exec_changed_keys
11478 10:57:28.276189 # ok 5 # SKIP PAUTH not enabled
11479 10:57:28.279375 # # RUN global.context_switch_keep_keys ...
11480 10:57:28.282620 # # SKIP PAUTH not enabled
11481 10:57:28.289306 # # OK global.context_switch_keep_keys
11482 10:57:28.292444 # ok 6 # SKIP PAUTH not enabled
11483 10:57:28.295897 # # RUN global.context_switch_keep_keys_generic ...
11484 10:57:28.299374 # # SKIP Generic PAUTH not enabled
11485 10:57:28.305736 # # OK global.context_switch_keep_keys_generic
11486 10:57:28.309112 # ok 7 # SKIP Generic PAUTH not enabled
11487 10:57:28.312635 # # PASSED: 7 / 7 tests passed.
11488 10:57:28.315827 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11489 10:57:28.318783 ok 28 selftests: arm64: pac
11490 10:57:28.321841 # selftests: arm64: fp-stress
11491 10:57:37.030510 <6>[ 46.094249] vpu: disabling
11492 10:57:37.033516 <6>[ 46.097301] vproc2: disabling
11493 10:57:37.037135 <6>[ 46.100817] vproc1: disabling
11494 10:57:37.040404 <6>[ 46.104503] vaud18: disabling
11495 10:57:37.047743 <6>[ 46.108015] vsram_others: disabling
11496 10:57:37.050358 <6>[ 46.112010] va09: disabling
11497 10:57:37.054314 <6>[ 46.115208] vsram_md: disabling
11498 10:57:37.057422 <6>[ 46.118796] Vgpu: disabling
11499 10:57:38.257088 # TAP version 13
11500 10:57:38.257233 # 1..16
11501 10:57:38.260179 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11502 10:57:38.263310 # # Will run for 10s
11503 10:57:38.263426 # # Started FPSIMD-0-0
11504 10:57:38.266410 # # Started FPSIMD-0-1
11505 10:57:38.269658 # # Started FPSIMD-1-0
11506 10:57:38.269756 # # Started FPSIMD-1-1
11507 10:57:38.273356 # # Started FPSIMD-2-0
11508 10:57:38.276295 # # Started FPSIMD-2-1
11509 10:57:38.276376 # # Started FPSIMD-3-0
11510 10:57:38.279867 # # Started FPSIMD-3-1
11511 10:57:38.279952 # # Started FPSIMD-4-0
11512 10:57:38.282804 # # Started FPSIMD-4-1
11513 10:57:38.286668 # # Started FPSIMD-5-0
11514 10:57:38.286777 # # Started FPSIMD-5-1
11515 10:57:38.289720 # # Started FPSIMD-6-0
11516 10:57:38.292783 # # Started FPSIMD-6-1
11517 10:57:38.292941 # # Started FPSIMD-7-0
11518 10:57:38.296011 # # Started FPSIMD-7-1
11519 10:57:38.299619 # # FPSIMD-0-1: Vector length: 128 bits
11520 10:57:38.302779 # # FPSIMD-0-1: PID: 1123
11521 10:57:38.306160 # # FPSIMD-1-0: Vector length: 128 bits
11522 10:57:38.306247 # # FPSIMD-1-0: PID: 1124
11523 10:57:38.312739 # # FPSIMD-1-1: Vector length: 128 bits
11524 10:57:38.312846 # # FPSIMD-1-1: PID: 1125
11525 10:57:38.315929 # # FPSIMD-4-1: Vector length: 128 bits
11526 10:57:38.319094 # # FPSIMD-4-1: PID: 1131
11527 10:57:38.322715 # # FPSIMD-4-0: Vector length: 128 bits
11528 10:57:38.325931 # # FPSIMD-4-0: PID: 1130
11529 10:57:38.329007 # # FPSIMD-5-0: Vector length: 128 bits
11530 10:57:38.332313 # # FPSIMD-5-0: PID: 1132
11531 10:57:38.335906 # # FPSIMD-2-0: Vector length: 128 bits
11532 10:57:38.336020 # # FPSIMD-2-0: PID: 1126
11533 10:57:38.342508 # # FPSIMD-2-1: Vector length: 128 bits
11534 10:57:38.342615 # # FPSIMD-2-1: PID: 1127
11535 10:57:38.345438 # # FPSIMD-3-1: Vector length: 128 bits
11536 10:57:38.348968 # # FPSIMD-3-1: PID: 1129
11537 10:57:38.351831 # # FPSIMD-3-0: Vector length: 128 bits
11538 10:57:38.355557 # # FPSIMD-3-0: PID: 1128
11539 10:57:38.358661 # # FPSIMD-0-0: Vector length: 128 bits
11540 10:57:38.361608 # # FPSIMD-0-0: PID: 1122
11541 10:57:38.365294 # # FPSIMD-6-1: Vector length: 128 bits
11542 10:57:38.365428 # # FPSIMD-6-1: PID: 1135
11543 10:57:38.371928 # # FPSIMD-7-1: Vector length: 128 bits
11544 10:57:38.372060 # # FPSIMD-7-1: PID: 1137
11545 10:57:38.375156 # # FPSIMD-6-0: Vector length: 128 bits
11546 10:57:38.378357 # # FPSIMD-6-0: PID: 1134
11547 10:57:38.381448 # # FPSIMD-7-0: Vector length: 128 bits
11548 10:57:38.384982 # # FPSIMD-7-0: PID: 1136
11549 10:57:38.388009 # # FPSIMD-5-1: Vector length: 128 bits
11550 10:57:38.391805 # # FPSIMD-5-1: PID: 1133
11551 10:57:38.391915 # # Finishing up...
11552 10:57:38.398438 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=569743, signals=10
11553 10:57:38.408342 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1339589, signals=10
11554 10:57:38.414606 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1128379, signals=10
11555 10:57:38.420902 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=354773, signals=10
11556 10:57:38.427896 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1116661, signals=10
11557 10:57:38.434234 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=403981, signals=10
11558 10:57:38.441011 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=339240, signals=10
11559 10:57:38.443955 # ok 1 FPSIMD-0-0
11560 10:57:38.444046 # ok 2 FPSIMD-0-1
11561 10:57:38.447598 # ok 3 FPSIMD-1-0
11562 10:57:38.447682 # ok 4 FPSIMD-1-1
11563 10:57:38.450647 # ok 5 FPSIMD-2-0
11564 10:57:38.450757 # ok 6 FPSIMD-2-1
11565 10:57:38.453731 # ok 7 FPSIMD-3-0
11566 10:57:38.453854 # ok 8 FPSIMD-3-1
11567 10:57:38.457324 # ok 9 FPSIMD-4-0
11568 10:57:38.457430 # ok 10 FPSIMD-4-1
11569 10:57:38.460775 # ok 11 FPSIMD-5-0
11570 10:57:38.463849 # ok 12 FPSIMD-5-1
11571 10:57:38.463959 # ok 13 FPSIMD-6-0
11572 10:57:38.466994 # ok 14 FPSIMD-6-1
11573 10:57:38.467108 # ok 15 FPSIMD-7-0
11574 10:57:38.470171 # ok 16 FPSIMD-7-1
11575 10:57:38.477037 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1306884, signals=9
11576 10:57:38.483363 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=986579, signals=10
11577 10:57:38.490239 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1298895, signals=10
11578 10:57:38.497026 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=721508, signals=10
11579 10:57:38.503229 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=342512, signals=10
11580 10:57:38.513238 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=339643, signals=10
11581 10:57:38.519623 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=598987, signals=9
11582 10:57:38.526642 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1448990, signals=10
11583 10:57:38.532941 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=495737, signals=10
11584 10:57:38.539866 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11585 10:57:38.542963 ok 29 selftests: arm64: fp-stress
11586 10:57:38.543050 # selftests: arm64: sve-ptrace
11587 10:57:38.546440 # TAP version 13
11588 10:57:38.546525 # 1..4104
11589 10:57:38.549829 # ok 2 # SKIP SVE not available
11590 10:57:38.552966 # # Planned tests != run tests (4104 != 1)
11591 10:57:38.559365 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11592 10:57:38.562949 ok 30 selftests: arm64: sve-ptrace # SKIP
11593 10:57:38.565957 # selftests: arm64: sve-probe-vls
11594 10:57:38.566047 # TAP version 13
11595 10:57:38.566117 # 1..2
11596 10:57:38.569243 # ok 2 # SKIP SVE not available
11597 10:57:38.572787 # # Planned tests != run tests (2 != 1)
11598 10:57:38.579229 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11599 10:57:38.582746 ok 31 selftests: arm64: sve-probe-vls # SKIP
11600 10:57:38.585966 # selftests: arm64: vec-syscfg
11601 10:57:38.586050 # TAP version 13
11602 10:57:38.589011 # 1..20
11603 10:57:38.592680 # ok 1 # SKIP SVE not supported
11604 10:57:38.592761 # ok 2 # SKIP SVE not supported
11605 10:57:38.595844 # ok 3 # SKIP SVE not supported
11606 10:57:38.598916 # ok 4 # SKIP SVE not supported
11607 10:57:38.602018 # ok 5 # SKIP SVE not supported
11608 10:57:38.605439 # ok 6 # SKIP SVE not supported
11609 10:57:38.609206 # ok 7 # SKIP SVE not supported
11610 10:57:38.612373 # ok 8 # SKIP SVE not supported
11611 10:57:38.612465 # ok 9 # SKIP SVE not supported
11612 10:57:38.615418 # ok 10 # SKIP SVE not supported
11613 10:57:38.619002 # ok 11 # SKIP SME not supported
11614 10:57:38.622282 # ok 12 # SKIP SME not supported
11615 10:57:38.625430 # ok 13 # SKIP SME not supported
11616 10:57:38.628717 # ok 14 # SKIP SME not supported
11617 10:57:38.632006 # ok 15 # SKIP SME not supported
11618 10:57:38.635121 # ok 16 # SKIP SME not supported
11619 10:57:38.638443 # ok 17 # SKIP SME not supported
11620 10:57:38.641706 # ok 18 # SKIP SME not supported
11621 10:57:38.641790 # ok 19 # SKIP SME not supported
11622 10:57:38.645574 # ok 20 # SKIP SME not supported
11623 10:57:38.651949 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11624 10:57:38.654988 ok 32 selftests: arm64: vec-syscfg
11625 10:57:38.658177 # selftests: arm64: za-fork
11626 10:57:38.658289 # TAP version 13
11627 10:57:38.658385 # 1..1
11628 10:57:38.661965 # # PID: 1208
11629 10:57:38.662085 # # SME support not present
11630 10:57:38.664859 # ok 0 skipped
11631 10:57:38.668392 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11632 10:57:38.671357 ok 33 selftests: arm64: za-fork
11633 10:57:38.674769 # selftests: arm64: za-ptrace
11634 10:57:38.678257 # TAP version 13
11635 10:57:38.678368 # 1..1
11636 10:57:38.681557 # ok 2 # SKIP SME not available
11637 10:57:38.684630 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11638 10:57:38.688201 ok 34 selftests: arm64: za-ptrace # SKIP
11639 10:57:38.691506 # selftests: arm64: check_buffer_fill
11640 10:57:38.725242 # # SKIP: MTE features unavailable
11641 10:57:38.732232 ok 35 selftests: arm64: check_buffer_fill # SKIP
11642 10:57:38.748801 # selftests: arm64: check_child_memory
11643 10:57:38.801293 # # SKIP: MTE features unavailable
11644 10:57:38.807236 ok 36 selftests: arm64: check_child_memory # SKIP
11645 10:57:38.824132 # selftests: arm64: check_gcr_el1_cswitch
11646 10:57:38.876368 # # SKIP: MTE features unavailable
11647 10:57:38.883231 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11648 10:57:38.900820 # selftests: arm64: check_ksm_options
11649 10:57:38.951874 # # SKIP: MTE features unavailable
11650 10:57:38.958900 ok 38 selftests: arm64: check_ksm_options # SKIP
11651 10:57:38.974489 # selftests: arm64: check_mmap_options
11652 10:57:39.021079 # # SKIP: MTE features unavailable
11653 10:57:39.028134 ok 39 selftests: arm64: check_mmap_options # SKIP
11654 10:57:39.037622 # selftests: arm64: check_prctl
11655 10:57:39.088402 # TAP version 13
11656 10:57:39.088510 # 1..5
11657 10:57:39.091556 # ok 1 check_basic_read
11658 10:57:39.091631 # ok 2 NONE
11659 10:57:39.094707 # ok 3 # SKIP SYNC
11660 10:57:39.094807 # ok 4 # SKIP ASYNC
11661 10:57:39.098000 # ok 5 # SKIP SYNC+ASYNC
11662 10:57:39.101029 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11663 10:57:39.104594 ok 40 selftests: arm64: check_prctl
11664 10:57:39.111047 # selftests: arm64: check_tags_inclusion
11665 10:57:39.156450 # # SKIP: MTE features unavailable
11666 10:57:39.163566 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11667 10:57:39.174536 # selftests: arm64: check_user_mem
11668 10:57:39.226383 # # SKIP: MTE features unavailable
11669 10:57:39.232891 ok 42 selftests: arm64: check_user_mem # SKIP
11670 10:57:39.244805 # selftests: arm64: btitest
11671 10:57:39.295696 # TAP version 13
11672 10:57:39.295805 # 1..18
11673 10:57:39.298744 # # HWCAP_PACA not present
11674 10:57:39.301956 # # HWCAP2_BTI not present
11675 10:57:39.302033 # # Test binary built for BTI
11676 10:57:39.308908 # ok 1 nohint_func/call_using_br_x0 # SKIP
11677 10:57:39.312067 # ok 1 nohint_func/call_using_br_x16 # SKIP
11678 10:57:39.315383 # ok 1 nohint_func/call_using_blr # SKIP
11679 10:57:39.318479 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11680 10:57:39.322116 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11681 10:57:39.328652 # ok 1 bti_none_func/call_using_blr # SKIP
11682 10:57:39.331693 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11683 10:57:39.335318 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11684 10:57:39.338229 # ok 1 bti_c_func/call_using_blr # SKIP
11685 10:57:39.342073 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11686 10:57:39.344836 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11687 10:57:39.348189 # ok 1 bti_j_func/call_using_blr # SKIP
11688 10:57:39.351358 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11689 10:57:39.358220 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11690 10:57:39.361627 # ok 1 bti_jc_func/call_using_blr # SKIP
11691 10:57:39.364573 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11692 10:57:39.368290 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11693 10:57:39.371337 # ok 1 paciasp_func/call_using_blr # SKIP
11694 10:57:39.378208 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11695 10:57:39.381314 # # WARNING - EXPECTED TEST COUNT WRONG
11696 10:57:39.384400 ok 43 selftests: arm64: btitest
11697 10:57:39.387563 # selftests: arm64: nobtitest
11698 10:57:39.387646 # TAP version 13
11699 10:57:39.387711 # 1..18
11700 10:57:39.391340 # # HWCAP_PACA not present
11701 10:57:39.394435 # # HWCAP2_BTI not present
11702 10:57:39.397532 # # Test binary not built for BTI
11703 10:57:39.400958 # ok 1 nohint_func/call_using_br_x0 # SKIP
11704 10:57:39.404282 # ok 1 nohint_func/call_using_br_x16 # SKIP
11705 10:57:39.407458 # ok 1 nohint_func/call_using_blr # SKIP
11706 10:57:39.410698 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11707 10:57:39.417807 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11708 10:57:39.420969 # ok 1 bti_none_func/call_using_blr # SKIP
11709 10:57:39.424191 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11710 10:57:39.427364 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11711 10:57:39.430885 # ok 1 bti_c_func/call_using_blr # SKIP
11712 10:57:39.433813 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11713 10:57:39.437163 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11714 10:57:39.440792 # ok 1 bti_j_func/call_using_blr # SKIP
11715 10:57:39.447297 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11716 10:57:39.450315 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11717 10:57:39.453909 # ok 1 bti_jc_func/call_using_blr # SKIP
11718 10:57:39.457061 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11719 10:57:39.460260 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11720 10:57:39.463910 # ok 1 paciasp_func/call_using_blr # SKIP
11721 10:57:39.470336 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11722 10:57:39.473887 # # WARNING - EXPECTED TEST COUNT WRONG
11723 10:57:39.476927 ok 44 selftests: arm64: nobtitest
11724 10:57:39.479967 # selftests: arm64: hwcap
11725 10:57:39.480050 # TAP version 13
11726 10:57:39.480115 # 1..28
11727 10:57:39.483619 # ok 1 cpuinfo_match_RNG
11728 10:57:39.486846 # # SIGILL reported for RNG
11729 10:57:39.489864 # ok 2 # SKIP sigill_RNG
11730 10:57:39.489947 # ok 3 cpuinfo_match_SME
11731 10:57:39.493614 # ok 4 sigill_SME
11732 10:57:39.493697 # ok 5 cpuinfo_match_SVE
11733 10:57:39.496902 # ok 6 sigill_SVE
11734 10:57:39.500011 # ok 7 cpuinfo_match_SVE 2
11735 10:57:39.500094 # # SIGILL reported for SVE 2
11736 10:57:39.503149 # ok 8 # SKIP sigill_SVE 2
11737 10:57:39.506249 # ok 9 cpuinfo_match_SVE AES
11738 10:57:39.510036 # # SIGILL reported for SVE AES
11739 10:57:39.513328 # ok 10 # SKIP sigill_SVE AES
11740 10:57:39.516573 # ok 11 cpuinfo_match_SVE2 PMULL
11741 10:57:39.519782 # # SIGILL reported for SVE2 PMULL
11742 10:57:39.519866 # ok 12 # SKIP sigill_SVE2 PMULL
11743 10:57:39.523208 # ok 13 cpuinfo_match_SVE2 BITPERM
11744 10:57:39.526109 # # SIGILL reported for SVE2 BITPERM
11745 10:57:39.529328 # ok 14 # SKIP sigill_SVE2 BITPERM
11746 10:57:39.533018 # ok 15 cpuinfo_match_SVE2 SHA3
11747 10:57:39.536063 # # SIGILL reported for SVE2 SHA3
11748 10:57:39.539195 # ok 16 # SKIP sigill_SVE2 SHA3
11749 10:57:39.542925 # ok 17 cpuinfo_match_SVE2 SM4
11750 10:57:39.545867 # # SIGILL reported for SVE2 SM4
11751 10:57:39.549423 # ok 18 # SKIP sigill_SVE2 SM4
11752 10:57:39.549497 # ok 19 cpuinfo_match_SVE2 I8MM
11753 10:57:39.552887 # # SIGILL reported for SVE2 I8MM
11754 10:57:39.556218 # ok 20 # SKIP sigill_SVE2 I8MM
11755 10:57:39.559062 # ok 21 cpuinfo_match_SVE2 F32MM
11756 10:57:39.562729 # # SIGILL reported for SVE2 F32MM
11757 10:57:39.565898 # ok 22 # SKIP sigill_SVE2 F32MM
11758 10:57:39.569033 # ok 23 cpuinfo_match_SVE2 F64MM
11759 10:57:39.572709 # # SIGILL reported for SVE2 F64MM
11760 10:57:39.575602 # ok 24 # SKIP sigill_SVE2 F64MM
11761 10:57:39.579276 # ok 25 cpuinfo_match_SVE2 BF16
11762 10:57:39.579383 # # SIGILL reported for SVE2 BF16
11763 10:57:39.582238 # ok 26 # SKIP sigill_SVE2 BF16
11764 10:57:39.585833 # ok 27 cpuinfo_match_SVE2 EBF16
11765 10:57:39.588923 # ok 28 # SKIP sigill_SVE2 EBF16
11766 10:57:39.595680 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11767 10:57:39.598909 ok 45 selftests: arm64: hwcap
11768 10:57:39.598994 # selftests: arm64: ptrace
11769 10:57:39.602158 # TAP version 13
11770 10:57:39.602233 # 1..7
11771 10:57:39.605258 # # Parent is 1437, child is 1438
11772 10:57:39.605341 # ok 1 read_tpidr_one
11773 10:57:39.609011 # ok 2 write_tpidr_one
11774 10:57:39.612476 # ok 3 verify_tpidr_one
11775 10:57:39.612562 # ok 4 count_tpidrs
11776 10:57:39.615396 # ok 5 tpidr2_write
11777 10:57:39.615468 # ok 6 tpidr2_read
11778 10:57:39.618534 # ok 7 write_tpidr_only
11779 10:57:39.625557 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11780 10:57:39.625641 ok 46 selftests: arm64: ptrace
11781 10:57:39.628673 # selftests: arm64: syscall-abi
11782 10:57:39.631889 # TAP version 13
11783 10:57:39.631974 # 1..2
11784 10:57:39.635065 # ok 1 getpid() FPSIMD
11785 10:57:39.635148 # ok 2 sched_yield() FPSIMD
11786 10:57:39.641959 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11787 10:57:39.645136 ok 47 selftests: arm64: syscall-abi
11788 10:57:39.648172 # selftests: arm64: tpidr2
11789 10:57:39.656349 # TAP version 13
11790 10:57:39.656432 # 1..5
11791 10:57:39.659912 # # PID: 1472
11792 10:57:39.660000 # # SME support not present
11793 10:57:39.662772 # ok 0 skipped, TPIDR2 not supported
11794 10:57:39.666487 # ok 1 skipped, TPIDR2 not supported
11795 10:57:39.669393 # ok 2 skipped, TPIDR2 not supported
11796 10:57:39.672650 # ok 3 skipped, TPIDR2 not supported
11797 10:57:39.676377 # ok 4 skipped, TPIDR2 not supported
11798 10:57:39.682482 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11799 10:57:39.686022 ok 48 selftests: arm64: tpidr2
11800 10:57:40.188643 arm64_tags_test pass
11801 10:57:40.191610 arm64_run_tags_test_sh pass
11802 10:57:40.195075 arm64_fake_sigreturn_bad_magic pass
11803 10:57:40.198500 arm64_fake_sigreturn_bad_size pass
11804 10:57:40.201881 arm64_fake_sigreturn_bad_size_for_magic0 pass
11805 10:57:40.204840 arm64_fake_sigreturn_duplicated_fpsimd pass
11806 10:57:40.208612 arm64_fake_sigreturn_misaligned_sp pass
11807 10:57:40.211504 arm64_fake_sigreturn_missing_fpsimd pass
11808 10:57:40.215126 arm64_fake_sigreturn_sme_change_vl skip
11809 10:57:40.221450 arm64_fake_sigreturn_sve_change_vl skip
11810 10:57:40.225124 arm64_mangle_pstate_invalid_compat_toggle pass
11811 10:57:40.228115 arm64_mangle_pstate_invalid_daif_bits pass
11812 10:57:40.231706 arm64_mangle_pstate_invalid_mode_el1h pass
11813 10:57:40.234581 arm64_mangle_pstate_invalid_mode_el1t pass
11814 10:57:40.238461 arm64_mangle_pstate_invalid_mode_el2h pass
11815 10:57:40.244618 arm64_mangle_pstate_invalid_mode_el2t pass
11816 10:57:40.248318 arm64_mangle_pstate_invalid_mode_el3h pass
11817 10:57:40.251441 arm64_mangle_pstate_invalid_mode_el3t pass
11818 10:57:40.254508 arm64_sme_trap_no_sm skip
11819 10:57:40.257647 arm64_sme_trap_non_streaming skip
11820 10:57:40.257750 arm64_sme_trap_za pass
11821 10:57:40.261378 arm64_sme_vl skip
11822 10:57:40.261487 arm64_ssve_regs skip
11823 10:57:40.264476 arm64_sve_regs skip
11824 10:57:40.264580 arm64_sve_vl skip
11825 10:57:40.267532 arm64_za_no_regs skip
11826 10:57:40.267642 arm64_za_regs skip
11827 10:57:40.270744 arm64_pac_PAUTH_not_enabled skip
11828 10:57:40.274668 arm64_pac_PAUTH_not_enabled skip
11829 10:57:40.277950 arm64_pac_Generic_PAUTH_not_enabled skip
11830 10:57:40.281073 arm64_pac_PAUTH_not_enabled skip
11831 10:57:40.284328 arm64_pac_PAUTH_not_enabled skip
11832 10:57:40.287520 arm64_pac_PAUTH_not_enabled skip
11833 10:57:40.290596 arm64_pac_Generic_PAUTH_not_enabled skip
11834 10:57:40.294502 arm64_pac pass
11835 10:57:40.294611 arm64_fp-stress_FPSIMD-0-0 pass
11836 10:57:40.297703 arm64_fp-stress_FPSIMD-0-1 pass
11837 10:57:40.300648 arm64_fp-stress_FPSIMD-1-0 pass
11838 10:57:40.303766 arm64_fp-stress_FPSIMD-1-1 pass
11839 10:57:40.307390 arm64_fp-stress_FPSIMD-2-0 pass
11840 10:57:40.310749 arm64_fp-stress_FPSIMD-2-1 pass
11841 10:57:40.313699 arm64_fp-stress_FPSIMD-3-0 pass
11842 10:57:40.313806 arm64_fp-stress_FPSIMD-3-1 pass
11843 10:57:40.317501 arm64_fp-stress_FPSIMD-4-0 pass
11844 10:57:40.320371 arm64_fp-stress_FPSIMD-4-1 pass
11845 10:57:40.323988 arm64_fp-stress_FPSIMD-5-0 pass
11846 10:57:40.327055 arm64_fp-stress_FPSIMD-5-1 pass
11847 10:57:40.330639 arm64_fp-stress_FPSIMD-6-0 pass
11848 10:57:40.333814 arm64_fp-stress_FPSIMD-6-1 pass
11849 10:57:40.336961 arm64_fp-stress_FPSIMD-7-0 pass
11850 10:57:40.337065 arm64_fp-stress_FPSIMD-7-1 pass
11851 10:57:40.340051 arm64_fp-stress pass
11852 10:57:40.343650 arm64_sve-ptrace_SVE_not_available skip
11853 10:57:40.346773 arm64_sve-ptrace skip
11854 10:57:40.350459 arm64_sve-probe-vls_SVE_not_available skip
11855 10:57:40.353425 arm64_sve-probe-vls skip
11856 10:57:40.357085 arm64_vec-syscfg_SVE_not_supported skip
11857 10:57:40.360372 arm64_vec-syscfg_SVE_not_supported skip
11858 10:57:40.363519 arm64_vec-syscfg_SVE_not_supported skip
11859 10:57:40.366660 arm64_vec-syscfg_SVE_not_supported skip
11860 10:57:40.369710 arm64_vec-syscfg_SVE_not_supported skip
11861 10:57:40.373448 arm64_vec-syscfg_SVE_not_supported skip
11862 10:57:40.376627 arm64_vec-syscfg_SVE_not_supported skip
11863 10:57:40.379899 arm64_vec-syscfg_SVE_not_supported skip
11864 10:57:40.383086 arm64_vec-syscfg_SVE_not_supported skip
11865 10:57:40.386304 arm64_vec-syscfg_SVE_not_supported skip
11866 10:57:40.389529 arm64_vec-syscfg_SME_not_supported skip
11867 10:57:40.393375 arm64_vec-syscfg_SME_not_supported skip
11868 10:57:40.399701 arm64_vec-syscfg_SME_not_supported skip
11869 10:57:40.402813 arm64_vec-syscfg_SME_not_supported skip
11870 10:57:40.406577 arm64_vec-syscfg_SME_not_supported skip
11871 10:57:40.409731 arm64_vec-syscfg_SME_not_supported skip
11872 10:57:40.412849 arm64_vec-syscfg_SME_not_supported skip
11873 10:57:40.416431 arm64_vec-syscfg_SME_not_supported skip
11874 10:57:40.419408 arm64_vec-syscfg_SME_not_supported skip
11875 10:57:40.422816 arm64_vec-syscfg_SME_not_supported skip
11876 10:57:40.425879 arm64_vec-syscfg pass
11877 10:57:40.425961 arm64_za-fork_skipped pass
11878 10:57:40.429584 arm64_za-fork pass
11879 10:57:40.432639 arm64_za-ptrace_SME_not_available skip
11880 10:57:40.436186 arm64_za-ptrace skip
11881 10:57:40.436268 arm64_check_buffer_fill skip
11882 10:57:40.439175 arm64_check_child_memory skip
11883 10:57:40.442369 arm64_check_gcr_el1_cswitch skip
11884 10:57:40.446103 arm64_check_ksm_options skip
11885 10:57:40.449190 arm64_check_mmap_options skip
11886 10:57:40.453060 arm64_check_prctl_check_basic_read pass
11887 10:57:40.455989 arm64_check_prctl_NONE pass
11888 10:57:40.456072 arm64_check_prctl_SYNC skip
11889 10:57:40.459191 arm64_check_prctl_ASYNC skip
11890 10:57:40.462376 arm64_check_prctl_SYNC_ASYNC skip
11891 10:57:40.465620 arm64_check_prctl pass
11892 10:57:40.468740 arm64_check_tags_inclusion skip
11893 10:57:40.468823 arm64_check_user_mem skip
11894 10:57:40.475534 arm64_btitest_nohint_func_call_using_br_x0 skip
11895 10:57:40.478708 arm64_btitest_nohint_func_call_using_br_x16 skip
11896 10:57:40.481888 arm64_btitest_nohint_func_call_using_blr skip
11897 10:57:40.485603 arm64_btitest_bti_none_func_call_using_br_x0 skip
11898 10:57:40.492028 arm64_btitest_bti_none_func_call_using_br_x16 skip
11899 10:57:40.495219 arm64_btitest_bti_none_func_call_using_blr skip
11900 10:57:40.498423 arm64_btitest_bti_c_func_call_using_br_x0 skip
11901 10:57:40.505404 arm64_btitest_bti_c_func_call_using_br_x16 skip
11902 10:57:40.508467 arm64_btitest_bti_c_func_call_using_blr skip
11903 10:57:40.511613 arm64_btitest_bti_j_func_call_using_br_x0 skip
11904 10:57:40.515336 arm64_btitest_bti_j_func_call_using_br_x16 skip
11905 10:57:40.521507 arm64_btitest_bti_j_func_call_using_blr skip
11906 10:57:40.525112 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11907 10:57:40.528109 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11908 10:57:40.531691 arm64_btitest_bti_jc_func_call_using_blr skip
11909 10:57:40.538318 arm64_btitest_paciasp_func_call_using_br_x0 skip
11910 10:57:40.541346 arm64_btitest_paciasp_func_call_using_br_x16 skip
11911 10:57:40.544847 arm64_btitest_paciasp_func_call_using_blr skip
11912 10:57:40.547919 arm64_btitest pass
11913 10:57:40.551043 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11914 10:57:40.558186 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11915 10:57:40.561353 arm64_nobtitest_nohint_func_call_using_blr skip
11916 10:57:40.564816 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11917 10:57:40.570983 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11918 10:57:40.574199 arm64_nobtitest_bti_none_func_call_using_blr skip
11919 10:57:40.577974 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11920 10:57:40.584481 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11921 10:57:40.587638 arm64_nobtitest_bti_c_func_call_using_blr skip
11922 10:57:40.590873 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11923 10:57:40.597195 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11924 10:57:40.601027 arm64_nobtitest_bti_j_func_call_using_blr skip
11925 10:57:40.604205 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11926 10:57:40.610521 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11927 10:57:40.614196 arm64_nobtitest_bti_jc_func_call_using_blr skip
11928 10:57:40.617319 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11929 10:57:40.623629 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11930 10:57:40.627338 arm64_nobtitest_paciasp_func_call_using_blr skip
11931 10:57:40.630199 arm64_nobtitest pass
11932 10:57:40.630302 arm64_hwcap_cpuinfo_match_RNG pass
11933 10:57:40.633846 arm64_hwcap_sigill_RNG skip
11934 10:57:40.636894 arm64_hwcap_cpuinfo_match_SME pass
11935 10:57:40.640408 arm64_hwcap_sigill_SME pass
11936 10:57:40.643428 arm64_hwcap_cpuinfo_match_SVE pass
11937 10:57:40.647263 arm64_hwcap_sigill_SVE pass
11938 10:57:40.650271 arm64_hwcap_cpuinfo_match_SVE_2 pass
11939 10:57:40.650360 arm64_hwcap_sigill_SVE_2 skip
11940 10:57:40.656852 arm64_hwcap_cpuinfo_match_SVE_AES pass
11941 10:57:40.656936 arm64_hwcap_sigill_SVE_AES skip
11942 10:57:40.663352 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11943 10:57:40.663436 arm64_hwcap_sigill_SVE2_PMULL skip
11944 10:57:40.670052 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11945 10:57:40.673002 arm64_hwcap_sigill_SVE2_BITPERM skip
11946 10:57:40.676619 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11947 10:57:40.680060 arm64_hwcap_sigill_SVE2_SHA3 skip
11948 10:57:40.683070 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11949 10:57:40.686252 arm64_hwcap_sigill_SVE2_SM4 skip
11950 10:57:40.690006 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11951 10:57:40.693168 arm64_hwcap_sigill_SVE2_I8MM skip
11952 10:57:40.696384 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11953 10:57:40.699504 arm64_hwcap_sigill_SVE2_F32MM skip
11954 10:57:40.702699 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11955 10:57:40.706535 arm64_hwcap_sigill_SVE2_F64MM skip
11956 10:57:40.709626 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11957 10:57:40.712807 arm64_hwcap_sigill_SVE2_BF16 skip
11958 10:57:40.716387 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11959 10:57:40.719516 arm64_hwcap_sigill_SVE2_EBF16 skip
11960 10:57:40.719607 arm64_hwcap pass
11961 10:57:40.722622 arm64_ptrace_read_tpidr_one pass
11962 10:57:40.725869 arm64_ptrace_write_tpidr_one pass
11963 10:57:40.729109 arm64_ptrace_verify_tpidr_one pass
11964 10:57:40.732883 arm64_ptrace_count_tpidrs pass
11965 10:57:40.735888 arm64_ptrace_tpidr2_write pass
11966 10:57:40.739534 arm64_ptrace_tpidr2_read pass
11967 10:57:40.742509 arm64_ptrace_write_tpidr_only pass
11968 10:57:40.742594 arm64_ptrace pass
11969 10:57:40.746038 arm64_syscall-abi_getpid_FPSIMD pass
11970 10:57:40.749031 arm64_syscall-abi_sched_yield_FPSIMD pass
11971 10:57:40.752255 arm64_syscall-abi pass
11972 10:57:40.755922 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11973 10:57:40.758947 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11974 10:57:40.765652 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11975 10:57:40.768800 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11976 10:57:40.772497 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11977 10:57:40.775516 arm64_tpidr2 pass
11978 10:57:40.778520 + ../../utils/send-to-lava.sh ./output/result.txt
11979 10:57:40.785079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11980 10:57:40.785366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11982 10:57:40.792264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11983 10:57:40.792513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11985 10:57:40.798458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11986 10:57:40.798713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11988 10:57:40.805407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11989 10:57:40.805665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11991 10:57:40.811951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11992 10:57:40.812222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11994 10:57:40.843506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11995 10:57:40.843767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11997 10:57:40.899255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11998 10:57:40.899557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12000 10:57:40.949462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12001 10:57:40.949726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12003 10:57:41.002526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12004 10:57:41.002865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12006 10:57:41.060616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12007 10:57:41.060978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12009 10:57:41.114620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12010 10:57:41.114956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12012 10:57:41.168768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12013 10:57:41.169115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12015 10:57:41.219795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12016 10:57:41.220075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12018 10:57:41.270706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12019 10:57:41.271030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12021 10:57:41.322987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12022 10:57:41.323271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12024 10:57:41.374970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12025 10:57:41.375247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12027 10:57:41.428417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12028 10:57:41.428696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12030 10:57:41.490519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12031 10:57:41.490790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12033 10:57:41.548663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12034 10:57:41.548939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12036 10:57:41.599844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12038 10:57:41.603234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12039 10:57:41.649102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12040 10:57:41.649372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12042 10:57:41.698676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12043 10:57:41.698945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12045 10:57:41.758248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12046 10:57:41.758526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12048 10:57:41.812255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12049 10:57:41.812532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12051 10:57:41.867121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12052 10:57:41.867389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12054 10:57:41.917416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12055 10:57:41.917740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12057 10:57:41.970220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12058 10:57:41.970529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12060 10:57:42.019819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12062 10:57:42.022685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12063 10:57:42.067167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12065 10:57:42.070100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12066 10:57:42.122033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12067 10:57:42.122309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12069 10:57:42.172028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12071 10:57:42.174945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12072 10:57:42.219770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12074 10:57:42.222735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12075 10:57:42.267857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12077 10:57:42.270623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12078 10:57:42.324459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12079 10:57:42.324732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12081 10:57:42.373582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12082 10:57:42.373886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12084 10:57:42.429647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12085 10:57:42.429951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12087 10:57:42.482467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12088 10:57:42.482769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12090 10:57:42.536840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12091 10:57:42.537112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12093 10:57:42.590321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12094 10:57:42.590616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12096 10:57:42.647234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12097 10:57:42.647506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12099 10:57:42.704164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12100 10:57:42.704468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12102 10:57:42.754477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12103 10:57:42.754777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12105 10:57:42.803245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12106 10:57:42.803519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12108 10:57:42.855460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12109 10:57:42.855726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12111 10:57:42.907276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12112 10:57:42.907573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12114 10:57:42.963925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12115 10:57:42.964193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12117 10:57:43.017536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12118 10:57:43.017811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12120 10:57:43.070787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12121 10:57:43.071106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12123 10:57:43.126972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12125 10:57:43.130102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12126 10:57:43.180374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12127 10:57:43.180660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12129 10:57:43.237481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12130 10:57:43.237780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12132 10:57:43.290292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12133 10:57:43.290585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12135 10:57:43.342169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12136 10:57:43.342494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12138 10:57:43.394565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12139 10:57:43.394906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12141 10:57:43.448761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12142 10:57:43.449068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12144 10:57:43.494656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12145 10:57:43.494980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12147 10:57:43.549457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12148 10:57:43.549744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12150 10:57:43.606616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12151 10:57:43.606924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12153 10:57:43.659646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12154 10:57:43.659937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12156 10:57:43.707553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12157 10:57:43.707861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12159 10:57:43.760493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12160 10:57:43.760788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12162 10:57:43.809634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12163 10:57:43.809956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12165 10:57:43.866940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12166 10:57:43.867216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12168 10:57:43.917580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12169 10:57:43.917904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12171 10:57:43.969881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12172 10:57:43.970176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12174 10:57:44.025890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12175 10:57:44.026165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12177 10:57:44.085429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12178 10:57:44.085700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12180 10:57:44.140376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12181 10:57:44.140647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12183 10:57:44.193213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12184 10:57:44.193519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12186 10:57:44.242451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12187 10:57:44.242770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12189 10:57:44.294580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12190 10:57:44.294869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12192 10:57:44.342148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12193 10:57:44.342487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12195 10:57:44.391906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12196 10:57:44.392181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12198 10:57:44.442799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12199 10:57:44.443107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12201 10:57:44.489629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12202 10:57:44.489948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12204 10:57:44.544513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12205 10:57:44.545207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12207 10:57:44.600162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12208 10:57:44.600910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12210 10:57:44.661856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12211 10:57:44.662126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12213 10:57:44.710905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12214 10:57:44.711218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12216 10:57:44.769168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12217 10:57:44.769444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12219 10:57:44.816478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12220 10:57:44.816781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12222 10:57:44.869801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12223 10:57:44.870075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12225 10:57:44.919509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12226 10:57:44.919807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12228 10:57:44.965730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12230 10:57:44.968410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12231 10:57:45.016646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12232 10:57:45.017007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12234 10:57:45.064878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12235 10:57:45.065181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12237 10:57:45.119736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12238 10:57:45.120059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12240 10:57:45.164371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12241 10:57:45.164642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12243 10:57:45.217734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12244 10:57:45.218041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12246 10:57:45.270674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12247 10:57:45.270998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12249 10:57:45.320098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12251 10:57:45.323436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12252 10:57:45.373049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12253 10:57:45.373335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12255 10:57:45.423938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12256 10:57:45.424210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12258 10:57:45.477317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12259 10:57:45.477597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12261 10:57:45.530129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12262 10:57:45.530422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12264 10:57:45.579069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12265 10:57:45.579335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12267 10:57:45.636495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12268 10:57:45.636790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12270 10:57:45.693236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12271 10:57:45.693545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12273 10:57:45.746352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12274 10:57:45.746652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12276 10:57:45.799359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12277 10:57:45.799681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12279 10:57:45.853672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12280 10:57:45.853994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12282 10:57:45.901783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12283 10:57:45.902077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12285 10:57:45.952862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12286 10:57:45.953153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12288 10:57:46.006593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12289 10:57:46.006915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12291 10:57:46.053744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12292 10:57:46.054028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12294 10:57:46.107065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12295 10:57:46.107348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12297 10:57:46.155394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12298 10:57:46.155672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12300 10:57:46.205876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12301 10:57:46.206148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12303 10:57:46.257044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12304 10:57:46.257340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12306 10:57:46.313366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12307 10:57:46.313652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12309 10:57:46.369587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12310 10:57:46.369858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12312 10:57:46.423727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12313 10:57:46.424010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12315 10:57:46.473019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12316 10:57:46.473316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12318 10:57:46.531946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12319 10:57:46.532243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12321 10:57:46.589206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12322 10:57:46.589514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12324 10:57:46.645028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12325 10:57:46.645320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12327 10:57:46.695116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12328 10:57:46.695391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12330 10:57:46.747080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12331 10:57:46.747358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12333 10:57:46.804413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12334 10:57:46.804685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12336 10:57:46.862316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12337 10:57:46.862629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12339 10:57:46.915846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12340 10:57:46.916126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12342 10:57:46.965752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12343 10:57:46.966047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12345 10:57:47.017066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12346 10:57:47.017347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12348 10:57:47.069039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12349 10:57:47.069345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12351 10:57:47.118502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12352 10:57:47.118792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12354 10:57:47.171004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12355 10:57:47.171270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12357 10:57:47.219950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12358 10:57:47.220253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12360 10:57:47.270818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12361 10:57:47.271212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12363 10:57:47.330394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12364 10:57:47.330705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12366 10:57:47.388581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12367 10:57:47.388867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12369 10:57:47.444890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12370 10:57:47.445209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12372 10:57:47.500418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12373 10:57:47.500724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12375 10:57:47.555525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12376 10:57:47.555827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12378 10:57:47.612995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12379 10:57:47.613284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12381 10:57:47.672402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12382 10:57:47.672677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12384 10:57:47.721116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12385 10:57:47.721390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12387 10:57:47.774678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12388 10:57:47.774966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12390 10:57:47.830198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12391 10:57:47.830502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12393 10:57:47.888700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12394 10:57:47.888976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12396 10:57:47.940381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12397 10:57:47.940654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12399 10:57:48.007012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12400 10:57:48.007763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12402 10:57:48.073146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12404 10:57:48.075775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12405 10:57:48.142637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12406 10:57:48.143442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12408 10:57:48.209111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12409 10:57:48.210063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12411 10:57:48.275061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12412 10:57:48.275939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12414 10:57:48.336010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12415 10:57:48.336915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12417 10:57:48.398616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12418 10:57:48.399554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12420 10:57:48.459370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12422 10:57:48.462749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12423 10:57:48.530807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12424 10:57:48.531684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12426 10:57:48.592366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12428 10:57:48.595157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12429 10:57:48.656366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12430 10:57:48.656698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12432 10:57:48.709507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12434 10:57:48.713021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12435 10:57:48.770239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12436 10:57:48.770510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12438 10:57:48.818668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12439 10:57:48.818931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12441 10:57:48.872950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12442 10:57:48.873225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12444 10:57:48.925115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12445 10:57:48.925443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12447 10:57:48.981174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12448 10:57:48.981962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12450 10:57:49.043355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12452 10:57:49.046662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12453 10:57:49.111208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12454 10:57:49.112057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12456 10:57:49.169656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12457 10:57:49.170581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12459 10:57:49.222904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12460 10:57:49.223184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12462 10:57:49.279379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12464 10:57:49.282114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12465 10:57:49.329071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12467 10:57:49.332419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12468 10:57:49.393537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12469 10:57:49.393819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12471 10:57:49.448430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12472 10:57:49.448778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12474 10:57:49.507647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12475 10:57:49.508413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12477 10:57:49.574478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12478 10:57:49.575232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12480 10:57:49.640557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12481 10:57:49.641377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12483 10:57:49.695091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12484 10:57:49.695800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12486 10:57:49.769070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12487 10:57:49.769972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12489 10:57:49.832662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12490 10:57:49.832954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12492 10:57:49.880912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12493 10:57:49.881193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12495 10:57:49.937108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12496 10:57:49.937422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12498 10:57:49.995856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12499 10:57:49.996141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12501 10:57:50.049920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12502 10:57:50.050340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12504 10:57:50.106148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12505 10:57:50.106946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12507 10:57:50.168230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12508 10:57:50.168984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12510 10:57:50.230770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12511 10:57:50.231276 + set +x
12512 10:57:50.231870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12514 10:57:50.237678 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10591009_1.6.2.3.5>
12515 10:57:50.238415 Received signal: <ENDRUN> 1_kselftest-arm64 10591009_1.6.2.3.5
12516 10:57:50.238788 Ending use of test pattern.
12517 10:57:50.239157 Ending test lava.1_kselftest-arm64 (10591009_1.6.2.3.5), duration 32.23
12519 10:57:50.240627 <LAVA_TEST_RUNNER EXIT>
12520 10:57:50.241358 ok: lava_test_shell seems to have completed
12521 10:57:50.246336 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12522 10:57:50.247095 end: 3.1 lava-test-shell (duration 00:00:33) [common]
12523 10:57:50.247531 end: 3 lava-test-retry (duration 00:00:33) [common]
12524 10:57:50.248099 start: 4 finalize (timeout 00:07:03) [common]
12525 10:57:50.248591 start: 4.1 power-off (timeout 00:00:30) [common]
12526 10:57:50.249454 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12527 10:57:50.367487 >> Command sent successfully.
12528 10:57:50.371293 Returned 0 in 0 seconds
12529 10:57:50.472127 end: 4.1 power-off (duration 00:00:00) [common]
12531 10:57:50.473705 start: 4.2 read-feedback (timeout 00:07:02) [common]
12532 10:57:50.475107 Listened to connection for namespace 'common' for up to 1s
12533 10:57:51.474921 Finalising connection for namespace 'common'
12534 10:57:51.475090 Disconnecting from shell: Finalise
12535 10:57:51.475175 / #
12536 10:57:51.575474 end: 4.2 read-feedback (duration 00:00:01) [common]
12537 10:57:51.575643 end: 4 finalize (duration 00:00:01) [common]
12538 10:57:51.575764 Cleaning after the job
12539 10:57:51.575861 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/ramdisk
12540 10:57:51.577759 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/kernel
12541 10:57:51.586006 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/dtb
12542 10:57:51.586174 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/nfsrootfs
12543 10:57:51.646315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591009/tftp-deploy-3jx6k2xn/modules
12544 10:57:51.651390 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591009
12545 10:57:52.191039 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591009
12546 10:57:52.191207 Job finished correctly