Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 10:50:40.430119 lava-dispatcher, installed at version: 2023.05.1
2 10:50:40.430309 start: 0 validate
3 10:50:40.430433 Start time: 2023-06-05 10:50:40.430425+00:00 (UTC)
4 10:50:40.430546 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:50:40.430671 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 10:50:40.729321 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:50:40.730146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:50:41.024042 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:50:41.024800 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:51:00.987794 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:51:00.987985 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:51:01.559380 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:51:01.559547 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:51:01.846458 validate duration: 21.42
16 10:51:01.846729 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:51:01.846827 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:51:01.846917 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:51:01.847050 Not decompressing ramdisk as can be used compressed.
20 10:51:01.847137 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 10:51:01.847203 saving as /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/ramdisk/initrd.cpio.gz
22 10:51:01.847267 total size: 4665601 (4MB)
23 10:51:06.829203 progress 0% (0MB)
24 10:51:06.833710 progress 5% (0MB)
25 10:51:06.834899 progress 10% (0MB)
26 10:51:06.836075 progress 15% (0MB)
27 10:51:06.837392 progress 20% (0MB)
28 10:51:06.838555 progress 25% (1MB)
29 10:51:06.839713 progress 30% (1MB)
30 10:51:06.840922 progress 35% (1MB)
31 10:51:06.842100 progress 40% (1MB)
32 10:51:06.843412 progress 45% (2MB)
33 10:51:06.844570 progress 50% (2MB)
34 10:51:06.845775 progress 55% (2MB)
35 10:51:06.846938 progress 60% (2MB)
36 10:51:06.848100 progress 65% (2MB)
37 10:51:06.849305 progress 70% (3MB)
38 10:51:06.850463 progress 75% (3MB)
39 10:51:06.851620 progress 80% (3MB)
40 10:51:06.852977 progress 85% (3MB)
41 10:51:06.854135 progress 90% (4MB)
42 10:51:06.855290 progress 95% (4MB)
43 10:51:06.856463 progress 100% (4MB)
44 10:51:06.856608 4MB downloaded in 5.01s (0.89MB/s)
45 10:51:06.856751 end: 1.1.1 http-download (duration 00:00:05) [common]
47 10:51:06.856993 end: 1.1 download-retry (duration 00:00:05) [common]
48 10:51:06.857077 start: 1.2 download-retry (timeout 00:09:55) [common]
49 10:51:06.857159 start: 1.2.1 http-download (timeout 00:09:55) [common]
50 10:51:06.857303 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:51:06.857373 saving as /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/kernel/Image
52 10:51:06.857431 total size: 45746688 (43MB)
53 10:51:06.857489 No compression specified
54 10:51:07.152365 progress 0% (0MB)
55 10:51:07.197081 progress 5% (2MB)
56 10:51:07.214909 progress 10% (4MB)
57 10:51:07.227508 progress 15% (6MB)
58 10:51:07.238846 progress 20% (8MB)
59 10:51:07.250124 progress 25% (10MB)
60 10:51:07.261192 progress 30% (13MB)
61 10:51:07.272298 progress 35% (15MB)
62 10:51:07.283353 progress 40% (17MB)
63 10:51:07.294449 progress 45% (19MB)
64 10:51:07.305569 progress 50% (21MB)
65 10:51:07.316518 progress 55% (24MB)
66 10:51:07.327922 progress 60% (26MB)
67 10:51:07.339169 progress 65% (28MB)
68 10:51:07.350440 progress 70% (30MB)
69 10:51:07.361683 progress 75% (32MB)
70 10:51:07.372668 progress 80% (34MB)
71 10:51:07.383684 progress 85% (37MB)
72 10:51:07.394777 progress 90% (39MB)
73 10:51:07.405716 progress 95% (41MB)
74 10:51:07.416575 progress 100% (43MB)
75 10:51:07.416689 43MB downloaded in 0.56s (78.01MB/s)
76 10:51:07.416873 end: 1.2.1 http-download (duration 00:00:01) [common]
78 10:51:07.417134 end: 1.2 download-retry (duration 00:00:01) [common]
79 10:51:07.417224 start: 1.3 download-retry (timeout 00:09:54) [common]
80 10:51:07.417312 start: 1.3.1 http-download (timeout 00:09:54) [common]
81 10:51:07.417466 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:51:07.417536 saving as /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/dtb/mt8192-asurada-spherion-r0.dtb
83 10:51:07.417615 total size: 46924 (0MB)
84 10:51:07.417677 No compression specified
85 10:51:07.418872 progress 69% (0MB)
86 10:51:07.419136 progress 100% (0MB)
87 10:51:07.419285 0MB downloaded in 0.00s (26.60MB/s)
88 10:51:07.419404 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:51:07.419622 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:51:07.419705 start: 1.4 download-retry (timeout 00:09:54) [common]
92 10:51:07.419786 start: 1.4.1 http-download (timeout 00:09:54) [common]
93 10:51:07.419908 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 10:51:07.419976 saving as /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/nfsrootfs/full.rootfs.tar
95 10:51:07.420036 total size: 200770336 (191MB)
96 10:51:07.420095 Using unxz to decompress xz
97 10:51:07.423310 progress 0% (0MB)
98 10:51:07.935477 progress 5% (9MB)
99 10:51:08.433039 progress 10% (19MB)
100 10:51:08.998327 progress 15% (28MB)
101 10:51:09.354100 progress 20% (38MB)
102 10:51:09.673230 progress 25% (47MB)
103 10:51:10.256349 progress 30% (57MB)
104 10:51:10.793587 progress 35% (67MB)
105 10:51:11.370881 progress 40% (76MB)
106 10:51:11.921109 progress 45% (86MB)
107 10:51:12.492858 progress 50% (95MB)
108 10:51:13.109558 progress 55% (105MB)
109 10:51:13.753111 progress 60% (114MB)
110 10:51:13.869386 progress 65% (124MB)
111 10:51:14.007004 progress 70% (134MB)
112 10:51:14.101109 progress 75% (143MB)
113 10:51:14.173609 progress 80% (153MB)
114 10:51:14.241257 progress 85% (162MB)
115 10:51:14.338842 progress 90% (172MB)
116 10:51:14.610727 progress 95% (181MB)
117 10:51:15.182077 progress 100% (191MB)
118 10:51:15.186652 191MB downloaded in 7.77s (24.65MB/s)
119 10:51:15.186936 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:51:15.187202 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:51:15.187293 start: 1.5 download-retry (timeout 00:09:47) [common]
123 10:51:15.187384 start: 1.5.1 http-download (timeout 00:09:47) [common]
124 10:51:15.187601 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:51:15.187712 saving as /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/modules/modules.tar
126 10:51:15.187812 total size: 8542412 (8MB)
127 10:51:15.187890 Using unxz to decompress xz
128 10:51:15.482065 progress 0% (0MB)
129 10:51:15.535474 progress 5% (0MB)
130 10:51:15.561170 progress 10% (0MB)
131 10:51:15.586566 progress 15% (1MB)
132 10:51:15.610923 progress 20% (1MB)
133 10:51:15.636043 progress 25% (2MB)
134 10:51:15.660615 progress 30% (2MB)
135 10:51:15.685330 progress 35% (2MB)
136 10:51:15.709709 progress 40% (3MB)
137 10:51:15.734380 progress 45% (3MB)
138 10:51:15.757814 progress 50% (4MB)
139 10:51:15.780167 progress 55% (4MB)
140 10:51:15.804636 progress 60% (4MB)
141 10:51:15.829383 progress 65% (5MB)
142 10:51:15.854314 progress 70% (5MB)
143 10:51:15.880439 progress 75% (6MB)
144 10:51:15.908962 progress 80% (6MB)
145 10:51:15.930988 progress 85% (6MB)
146 10:51:15.955687 progress 90% (7MB)
147 10:51:15.978452 progress 95% (7MB)
148 10:51:16.001494 progress 100% (8MB)
149 10:51:16.007078 8MB downloaded in 0.82s (9.94MB/s)
150 10:51:16.007329 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:51:16.007584 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:51:16.007679 start: 1.6 prepare-tftp-overlay (timeout 00:09:46) [common]
154 10:51:16.007774 start: 1.6.1 extract-nfsrootfs (timeout 00:09:46) [common]
155 10:51:19.421237 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8
156 10:51:19.421437 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:51:19.421541 start: 1.6.2 lava-overlay (timeout 00:09:42) [common]
158 10:51:19.421728 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt
159 10:51:19.421942 makedir: /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin
160 10:51:19.422055 makedir: /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/tests
161 10:51:19.422164 makedir: /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/results
162 10:51:19.422265 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-add-keys
163 10:51:19.422405 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-add-sources
164 10:51:19.422529 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-background-process-start
165 10:51:19.422656 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-background-process-stop
166 10:51:19.422779 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-common-functions
167 10:51:19.422898 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-echo-ipv4
168 10:51:19.423017 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-install-packages
169 10:51:19.423135 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-installed-packages
170 10:51:19.423256 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-os-build
171 10:51:19.423373 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-probe-channel
172 10:51:19.423491 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-probe-ip
173 10:51:19.423608 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-target-ip
174 10:51:19.423727 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-target-mac
175 10:51:19.423849 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-target-storage
176 10:51:19.423971 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-case
177 10:51:19.424090 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-event
178 10:51:19.424209 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-feedback
179 10:51:19.424328 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-raise
180 10:51:19.424446 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-reference
181 10:51:19.424564 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-runner
182 10:51:19.424684 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-set
183 10:51:19.424868 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-test-shell
184 10:51:19.425039 Updating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-add-keys (debian)
185 10:51:19.425192 Updating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-add-sources (debian)
186 10:51:19.425336 Updating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-install-packages (debian)
187 10:51:19.425471 Updating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-installed-packages (debian)
188 10:51:19.425608 Updating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/bin/lava-os-build (debian)
189 10:51:19.425729 Creating /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/environment
190 10:51:19.425827 LAVA metadata
191 10:51:19.425895 - LAVA_JOB_ID=10590964
192 10:51:19.425958 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:51:19.426056 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:42) [common]
194 10:51:19.426122 skipped lava-vland-overlay
195 10:51:19.426196 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:51:19.426274 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:42) [common]
197 10:51:19.426334 skipped lava-multinode-overlay
198 10:51:19.426406 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:51:19.426484 start: 1.6.2.3 test-definition (timeout 00:09:42) [common]
200 10:51:19.426556 Loading test definitions
201 10:51:19.426647 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:42) [common]
202 10:51:19.426719 Using /lava-10590964 at stage 0
203 10:51:19.427037 uuid=10590964_1.6.2.3.1 testdef=None
204 10:51:19.427124 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:51:19.427210 start: 1.6.2.3.2 test-overlay (timeout 00:09:42) [common]
206 10:51:19.427644 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:51:19.427865 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:42) [common]
209 10:51:19.428410 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:51:19.428640 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:42) [common]
212 10:51:19.429207 runner path: /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/0/tests/0_timesync-off test_uuid 10590964_1.6.2.3.1
213 10:51:19.429357 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:51:19.429579 start: 1.6.2.3.5 git-repo-action (timeout 00:09:42) [common]
216 10:51:19.429653 Using /lava-10590964 at stage 0
217 10:51:19.429749 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:51:19.429826 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/0/tests/1_kselftest-tpm2'
219 10:51:23.925655 Running '/usr/bin/git checkout kernelci.org
220 10:51:24.071490 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 10:51:24.072189 uuid=10590964_1.6.2.3.5 testdef=None
222 10:51:24.072377 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 10:51:24.072640 start: 1.6.2.3.6 test-overlay (timeout 00:09:38) [common]
225 10:51:24.073457 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:51:24.073701 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:38) [common]
228 10:51:24.074737 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:51:24.074987 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:38) [common]
231 10:51:24.075953 runner path: /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/0/tests/1_kselftest-tpm2 test_uuid 10590964_1.6.2.3.5
232 10:51:24.076048 BOARD='mt8192-asurada-spherion-r0'
233 10:51:24.076120 BRANCH='cip-gitlab'
234 10:51:24.076183 SKIPFILE='/dev/null'
235 10:51:24.076242 SKIP_INSTALL='True'
236 10:51:24.076300 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:51:24.076365 TST_CASENAME=''
238 10:51:24.076426 TST_CMDFILES='tpm2'
239 10:51:24.076569 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:51:24.076822 Creating lava-test-runner.conf files
242 10:51:24.076908 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10590964/lava-overlay-366yl5gt/lava-10590964/0 for stage 0
243 10:51:24.077003 - 0_timesync-off
244 10:51:24.077075 - 1_kselftest-tpm2
245 10:51:24.077177 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 10:51:24.077268 start: 1.6.2.4 compress-overlay (timeout 00:09:38) [common]
247 10:51:31.701584 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:51:31.701771 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:30) [common]
249 10:51:31.701896 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:51:31.701995 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 10:51:31.702086 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
252 10:51:31.812426 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:51:31.812756 start: 1.6.4 extract-modules (timeout 00:09:30) [common]
254 10:51:31.812905 extracting modules file /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8
255 10:51:32.013414 extracting modules file /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590964/extract-overlay-ramdisk-s_ggkn9o/ramdisk
256 10:51:32.218308 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:51:32.218479 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
258 10:51:32.218580 [common] Applying overlay to NFS
259 10:51:32.218649 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590964/compress-overlay-gqb4ogse/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8
260 10:51:33.106095 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:51:33.106258 start: 1.6.6 configure-preseed-file (timeout 00:09:29) [common]
262 10:51:33.106354 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:51:33.106448 start: 1.6.7 compress-ramdisk (timeout 00:09:29) [common]
264 10:51:33.106535 Building ramdisk /var/lib/lava/dispatcher/tmp/10590964/extract-overlay-ramdisk-s_ggkn9o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10590964/extract-overlay-ramdisk-s_ggkn9o/ramdisk
265 10:51:33.363222 >> 117801 blocks
266 10:51:35.196451 rename /var/lib/lava/dispatcher/tmp/10590964/extract-overlay-ramdisk-s_ggkn9o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/ramdisk/ramdisk.cpio.gz
267 10:51:35.196912 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:51:35.197042 start: 1.6.8 prepare-kernel (timeout 00:09:27) [common]
269 10:51:35.197149 start: 1.6.8.1 prepare-fit (timeout 00:09:27) [common]
270 10:51:35.197252 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/kernel/Image'
271 10:51:46.538432 Returned 0 in 11 seconds
272 10:51:46.639145 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/kernel/image.itb
273 10:51:46.937069 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:51:46.937401 output: Created: Mon Jun 5 11:51:46 2023
275 10:51:46.937477 output: Image 0 (kernel-1)
276 10:51:46.937545 output: Description:
277 10:51:46.937608 output: Created: Mon Jun 5 11:51:46 2023
278 10:51:46.937670 output: Type: Kernel Image
279 10:51:46.937730 output: Compression: lzma compressed
280 10:51:46.937792 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
281 10:51:46.937850 output: Architecture: AArch64
282 10:51:46.937908 output: OS: Linux
283 10:51:46.937967 output: Load Address: 0x00000000
284 10:51:46.938027 output: Entry Point: 0x00000000
285 10:51:46.938083 output: Hash algo: crc32
286 10:51:46.938137 output: Hash value: 8ce42972
287 10:51:46.938191 output: Image 1 (fdt-1)
288 10:51:46.938245 output: Description: mt8192-asurada-spherion-r0
289 10:51:46.938299 output: Created: Mon Jun 5 11:51:46 2023
290 10:51:46.938353 output: Type: Flat Device Tree
291 10:51:46.938435 output: Compression: uncompressed
292 10:51:46.938489 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 10:51:46.938543 output: Architecture: AArch64
294 10:51:46.938596 output: Hash algo: crc32
295 10:51:46.938650 output: Hash value: 1df858fa
296 10:51:46.938703 output: Image 2 (ramdisk-1)
297 10:51:46.938756 output: Description: unavailable
298 10:51:46.938809 output: Created: Mon Jun 5 11:51:46 2023
299 10:51:46.938863 output: Type: RAMDisk Image
300 10:51:46.938916 output: Compression: Unknown Compression
301 10:51:46.938969 output: Data Size: 17643313 Bytes = 17229.80 KiB = 16.83 MiB
302 10:51:46.939022 output: Architecture: AArch64
303 10:51:46.939075 output: OS: Linux
304 10:51:46.939128 output: Load Address: unavailable
305 10:51:46.939225 output: Entry Point: unavailable
306 10:51:46.939335 output: Hash algo: crc32
307 10:51:46.939401 output: Hash value: 0777c0e5
308 10:51:46.939469 output: Default Configuration: 'conf-1'
309 10:51:46.939536 output: Configuration 0 (conf-1)
310 10:51:46.939588 output: Description: mt8192-asurada-spherion-r0
311 10:51:46.939641 output: Kernel: kernel-1
312 10:51:46.939694 output: Init Ramdisk: ramdisk-1
313 10:51:46.939747 output: FDT: fdt-1
314 10:51:46.939800 output: Loadables: kernel-1
315 10:51:46.939853 output:
316 10:51:46.940041 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 10:51:46.940138 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 10:51:46.940246 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 10:51:46.940342 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 10:51:46.940450 No LXC device requested
321 10:51:46.940528 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:51:46.940612 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 10:51:46.940688 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:51:46.940752 Checking files for TFTP limit of 4294967296 bytes.
325 10:51:46.941276 end: 1 tftp-deploy (duration 00:00:45) [common]
326 10:51:46.941385 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:51:46.941481 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:51:46.941603 substitutions:
329 10:51:46.941672 - {DTB}: 10590964/tftp-deploy-yzu6itfl/dtb/mt8192-asurada-spherion-r0.dtb
330 10:51:46.941738 - {INITRD}: 10590964/tftp-deploy-yzu6itfl/ramdisk/ramdisk.cpio.gz
331 10:51:46.941798 - {KERNEL}: 10590964/tftp-deploy-yzu6itfl/kernel/Image
332 10:51:46.941856 - {LAVA_MAC}: None
333 10:51:46.941912 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8
334 10:51:46.941968 - {NFS_SERVER_IP}: 192.168.201.1
335 10:51:46.942024 - {PRESEED_CONFIG}: None
336 10:51:46.942079 - {PRESEED_LOCAL}: None
337 10:51:46.942134 - {RAMDISK}: 10590964/tftp-deploy-yzu6itfl/ramdisk/ramdisk.cpio.gz
338 10:51:46.942189 - {ROOT_PART}: None
339 10:51:46.942244 - {ROOT}: None
340 10:51:46.942298 - {SERVER_IP}: 192.168.201.1
341 10:51:46.942352 - {TEE}: None
342 10:51:46.942422 Parsed boot commands:
343 10:51:46.942477 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:51:46.942680 Parsed boot commands: tftpboot 192.168.201.1 10590964/tftp-deploy-yzu6itfl/kernel/image.itb 10590964/tftp-deploy-yzu6itfl/kernel/cmdline
345 10:51:46.942858 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:51:46.942970 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:51:46.943104 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:51:46.943190 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:51:46.943261 Not connected, no need to disconnect.
350 10:51:46.943338 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:51:46.943422 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:51:46.943489 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 10:51:46.946721 Setting prompt string to ['lava-test: # ']
354 10:51:46.947067 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:51:46.947192 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:51:46.947321 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:51:46.947438 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:51:46.947676 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 10:51:52.098167 >> Command sent successfully.
360 10:51:52.103713 Returned 0 in 5 seconds
361 10:51:52.204535 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:51:52.206109 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:51:52.206679 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:51:52.207302 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:51:52.207945 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:51:52.208393 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:51:52.209737 [Enter `^Ec?' for help]
369 10:51:52.378091 057d)
370 10:51:52.378697 <3>[ 39.149129] anx7625
371 10:51:52.379096 F0: 102B 0000
372 10:51:52.379452
373 10:51:52.381434 F3: 1001 0000 [0200]
374 10:51:52.381915
375 10:51:52.382288 F3: 1001 0000
376 10:51:52.382646
377 10:51:52.382987 F7: 102D 0000
378 10:51:52.383321
379 10:51:52.384837 F1: 0000 0000
380 10:51:52.385317
381 10:51:52.385694 V0: 0000 0000 [0001]
382 10:51:52.386046
383 10:51:52.388478 00: 0007 8000
384 10:51:52.389109
385 10:51:52.389512 01: 0000 0000
386 10:51:52.389885
387 10:51:52.391508 BP: 0C00 0209 [0000]
388 10:51:52.392031
389 10:51:52.392410 G0: 1182 0000
390 10:51:52.392763
391 10:51:52.394737 EC: 0000 0021 [4000]
392 10:51:52.395216
393 10:51:52.395594 S7: 0000 0000 [0000]
394 10:51:52.395947
395 10:51:52.398188 CC: 0000 0000 [0001]
396 10:51:52.398668
397 10:51:52.399045 T0: 0000 0040 [010F]
398 10:51:52.399673
399 10:51:52.400050 Jump to BL
400 10:51:52.401603
401 10:51:52.425163
402 10:51:52.425786
403 10:51:52.426167
404 10:51:52.431973 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:51:52.435462 ARM64: Exception handlers installed.
406 10:51:52.439074 ARM64: Testing exception
407 10:51:52.442261 ARM64: Done test exception
408 10:51:52.449689 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:51:52.459530 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:51:52.466213 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:51:52.475937 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:51:52.482777 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:51:52.493129 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:51:52.503355 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:51:52.510177 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:51:52.527700 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:51:52.531272 WDT: Last reset was cold boot
418 10:51:52.534610 SPI1(PAD0) initialized at 2873684 Hz
419 10:51:52.538047 SPI5(PAD0) initialized at 992727 Hz
420 10:51:52.541432 VBOOT: Loading verstage.
421 10:51:52.548019 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:51:52.551466 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:51:52.554586 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:51:52.558134 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:51:52.565605 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:51:52.572064 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:51:52.583130 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 10:51:52.583723
429 10:51:52.584099
430 10:51:52.593004 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:51:52.596573 ARM64: Exception handlers installed.
432 10:51:52.599793 ARM64: Testing exception
433 10:51:52.600397 ARM64: Done test exception
434 10:51:52.606073 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:51:52.609796 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:51:52.624092 Probing TPM: . done!
437 10:51:52.624673 TPM ready after 0 ms
438 10:51:52.631189 Connected to device vid:did:rid of 1ae0:0028:00
439 10:51:52.637464 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:51:52.641419 Initialized TPM device CR50 revision 0
441 10:51:52.706857 tlcl_send_startup: Startup return code is 0
442 10:51:52.707421 TPM: setup succeeded
443 10:51:52.718367 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:51:52.727508 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:51:52.737402 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:51:52.746542 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:51:52.750173 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:51:52.756658 in-header: 03 07 00 00 08 00 00 00
449 10:51:52.760558 in-data: aa e4 47 04 13 02 00 00
450 10:51:52.764006 Chrome EC: UHEPI supported
451 10:51:52.770586 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:51:52.774915 in-header: 03 ad 00 00 08 00 00 00
453 10:51:52.778134 in-data: 00 20 20 08 00 00 00 00
454 10:51:52.778576 Phase 1
455 10:51:52.781943 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:51:52.788914 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:51:52.793005 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:51:52.796884 Recovery requested (1009000e)
459 10:51:52.807224 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:51:52.813059 tlcl_extend: response is 0
461 10:51:52.822874 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:51:52.828876 tlcl_extend: response is 0
463 10:51:52.835622 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:51:52.856848 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:51:52.863516 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:51:52.864069
467 10:51:52.864412
468 10:51:52.873271 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:51:52.877372 ARM64: Exception handlers installed.
470 10:51:52.877934 ARM64: Testing exception
471 10:51:52.879915 ARM64: Done test exception
472 10:51:52.901538 pmic_efuse_setting: Set efuses in 11 msecs
473 10:51:52.905665 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:51:52.912027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:51:52.915573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:51:52.918745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:51:52.925645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:51:52.928981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:51:52.936338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:51:52.940047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:51:52.943915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:51:52.947243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:51:52.954839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:51:52.958730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:51:52.961962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:51:52.968279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:51:52.975311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:51:52.978484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:51:52.985898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:51:52.989531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:51:52.995950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:51:53.003077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:51:53.006171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:51:53.013700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:51:53.016914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:51:53.023556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:51:53.030324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:51:53.033712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:51:53.040273 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:51:53.046902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:51:53.050089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:51:53.053430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:51:53.060354 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:51:53.063490 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:51:53.070003 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:51:53.073159 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:51:53.079806 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:51:53.083434 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:51:53.090152 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:51:53.096561 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:51:53.099704 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:51:53.103056 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:51:53.110310 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:51:53.113745 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:51:53.117114 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:51:53.120742 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:51:53.126949 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:51:53.130440 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:51:53.133497 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:51:53.140406 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:51:53.143551 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:51:53.147152 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:51:53.150099 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:51:53.156655 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:51:53.163475 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:51:53.173761 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:51:53.176741 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:51:53.183486 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:51:53.193706 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:51:53.196723 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:51:53.203567 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:51:53.206821 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:51:53.214285 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
534 10:51:53.220505 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:51:53.224059 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 10:51:53.227456 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:51:53.238644 [RTC]rtc_get_frequency_meter,154: input=15, output=771
538 10:51:53.247982 [RTC]rtc_get_frequency_meter,154: input=23, output=955
539 10:51:53.257435 [RTC]rtc_get_frequency_meter,154: input=19, output=865
540 10:51:53.266837 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 10:51:53.276265 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 10:51:53.279523 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 10:51:53.286121 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 10:51:53.289686 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 10:51:53.292986 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 10:51:53.296199 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 10:51:53.299360 ADC[4]: Raw value=902876 ID=7
548 10:51:53.302795 ADC[3]: Raw value=213179 ID=1
549 10:51:53.306147 RAM Code: 0x71
550 10:51:53.309560 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 10:51:53.313545 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 10:51:53.323119 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 10:51:53.330101 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 10:51:53.333289 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 10:51:53.336804 in-header: 03 07 00 00 08 00 00 00
556 10:51:53.339874 in-data: aa e4 47 04 13 02 00 00
557 10:51:53.344026 Chrome EC: UHEPI supported
558 10:51:53.350043 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 10:51:53.353428 in-header: 03 ed 00 00 08 00 00 00
560 10:51:53.356694 in-data: 80 20 60 08 00 00 00 00
561 10:51:53.359798 MRC: failed to locate region type 0.
562 10:51:53.367338 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 10:51:53.370907 DRAM-K: Running full calibration
564 10:51:53.374675 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 10:51:53.378265 header.status = 0x0
566 10:51:53.382239 header.version = 0x6 (expected: 0x6)
567 10:51:53.382689 header.size = 0xd00 (expected: 0xd00)
568 10:51:53.386005 header.flags = 0x0
569 10:51:53.393166 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 10:51:53.409651 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
571 10:51:53.416854 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 10:51:53.420466 dram_init: ddr_geometry: 2
573 10:51:53.420654 [EMI] MDL number = 2
574 10:51:53.423878 [EMI] Get MDL freq = 0
575 10:51:53.424036 dram_init: ddr_type: 0
576 10:51:53.427417 is_discrete_lpddr4: 1
577 10:51:53.430979 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 10:51:53.431115
579 10:51:53.431221
580 10:51:53.433961 [Bian_co] ETT version 0.0.0.1
581 10:51:53.437386 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 10:51:53.437523
583 10:51:53.440953 dramc_set_vcore_voltage set vcore to 650000
584 10:51:53.443877 Read voltage for 800, 4
585 10:51:53.444002 Vio18 = 0
586 10:51:53.447452 Vcore = 650000
587 10:51:53.447539 Vdram = 0
588 10:51:53.447607 Vddq = 0
589 10:51:53.447669 Vmddr = 0
590 10:51:53.450599 dram_init: config_dvfs: 1
591 10:51:53.457218 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 10:51:53.460730 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 10:51:53.464215 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 10:51:53.470487 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 10:51:53.474044 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 10:51:53.477623 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 10:51:53.477718 MEM_TYPE=3, freq_sel=18
598 10:51:53.481032 sv_algorithm_assistance_LP4_1600
599 10:51:53.488365 ============ PULL DRAM RESETB DOWN ============
600 10:51:53.491657 ========== PULL DRAM RESETB DOWN end =========
601 10:51:53.495286 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 10:51:53.498995 ===================================
603 10:51:53.502736 LPDDR4 DRAM CONFIGURATION
604 10:51:53.502896 ===================================
605 10:51:53.506364 EX_ROW_EN[0] = 0x0
606 10:51:53.509338 EX_ROW_EN[1] = 0x0
607 10:51:53.509530 LP4Y_EN = 0x0
608 10:51:53.512884 WORK_FSP = 0x0
609 10:51:53.513166 WL = 0x2
610 10:51:53.516054 RL = 0x2
611 10:51:53.516226 BL = 0x2
612 10:51:53.519474 RPST = 0x0
613 10:51:53.519850 RD_PRE = 0x0
614 10:51:53.523453 WR_PRE = 0x1
615 10:51:53.523990 WR_PST = 0x0
616 10:51:53.526620 DBI_WR = 0x0
617 10:51:53.527051 DBI_RD = 0x0
618 10:51:53.529546 OTF = 0x1
619 10:51:53.532962 ===================================
620 10:51:53.536348 ===================================
621 10:51:53.536882 ANA top config
622 10:51:53.539435 ===================================
623 10:51:53.542786 DLL_ASYNC_EN = 0
624 10:51:53.546385 ALL_SLAVE_EN = 1
625 10:51:53.549874 NEW_RANK_MODE = 1
626 10:51:53.550425 DLL_IDLE_MODE = 1
627 10:51:53.553013 LP45_APHY_COMB_EN = 1
628 10:51:53.556480 TX_ODT_DIS = 1
629 10:51:53.559582 NEW_8X_MODE = 1
630 10:51:53.563028 ===================================
631 10:51:53.566439 ===================================
632 10:51:53.569690 data_rate = 1600
633 10:51:53.570223 CKR = 1
634 10:51:53.572633 DQ_P2S_RATIO = 8
635 10:51:53.576425 ===================================
636 10:51:53.579502 CA_P2S_RATIO = 8
637 10:51:53.582899 DQ_CA_OPEN = 0
638 10:51:53.586590 DQ_SEMI_OPEN = 0
639 10:51:53.589666 CA_SEMI_OPEN = 0
640 10:51:53.590202 CA_FULL_RATE = 0
641 10:51:53.593184 DQ_CKDIV4_EN = 1
642 10:51:53.596391 CA_CKDIV4_EN = 1
643 10:51:53.599648 CA_PREDIV_EN = 0
644 10:51:53.603177 PH8_DLY = 0
645 10:51:53.603610 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 10:51:53.605947 DQ_AAMCK_DIV = 4
647 10:51:53.609427 CA_AAMCK_DIV = 4
648 10:51:53.613028 CA_ADMCK_DIV = 4
649 10:51:53.616199 DQ_TRACK_CA_EN = 0
650 10:51:53.619405 CA_PICK = 800
651 10:51:53.622923 CA_MCKIO = 800
652 10:51:53.623467 MCKIO_SEMI = 0
653 10:51:53.626129 PLL_FREQ = 3068
654 10:51:53.629085 DQ_UI_PI_RATIO = 32
655 10:51:53.632901 CA_UI_PI_RATIO = 0
656 10:51:53.636072 ===================================
657 10:51:53.639762 ===================================
658 10:51:53.642935 memory_type:LPDDR4
659 10:51:53.643366 GP_NUM : 10
660 10:51:53.645766 SRAM_EN : 1
661 10:51:53.649789 MD32_EN : 0
662 10:51:53.650221 ===================================
663 10:51:53.653139 [ANA_INIT] >>>>>>>>>>>>>>
664 10:51:53.656696 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 10:51:53.660033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 10:51:53.663989 ===================================
667 10:51:53.667475 data_rate = 1600,PCW = 0X7600
668 10:51:53.667912 ===================================
669 10:51:53.671151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 10:51:53.678197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 10:51:53.682243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 10:51:53.688979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 10:51:53.692274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 10:51:53.696037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 10:51:53.696608 [ANA_INIT] flow start
676 10:51:53.699237 [ANA_INIT] PLL >>>>>>>>
677 10:51:53.702660 [ANA_INIT] PLL <<<<<<<<
678 10:51:53.703216 [ANA_INIT] MIDPI >>>>>>>>
679 10:51:53.705512 [ANA_INIT] MIDPI <<<<<<<<
680 10:51:53.708558 [ANA_INIT] DLL >>>>>>>>
681 10:51:53.709037 [ANA_INIT] flow end
682 10:51:53.715404 ============ LP4 DIFF to SE enter ============
683 10:51:53.718848 ============ LP4 DIFF to SE exit ============
684 10:51:53.721980 [ANA_INIT] <<<<<<<<<<<<<
685 10:51:53.725776 [Flow] Enable top DCM control >>>>>
686 10:51:53.728744 [Flow] Enable top DCM control <<<<<
687 10:51:53.729211 Enable DLL master slave shuffle
688 10:51:53.736184 ==============================================================
689 10:51:53.738922 Gating Mode config
690 10:51:53.742839 ==============================================================
691 10:51:53.745486 Config description:
692 10:51:53.755696 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 10:51:53.762245 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 10:51:53.765964 SELPH_MODE 0: By rank 1: By Phase
695 10:51:53.771837 ==============================================================
696 10:51:53.775690 GAT_TRACK_EN = 1
697 10:51:53.778762 RX_GATING_MODE = 2
698 10:51:53.782169 RX_GATING_TRACK_MODE = 2
699 10:51:53.785367 SELPH_MODE = 1
700 10:51:53.785901 PICG_EARLY_EN = 1
701 10:51:53.788725 VALID_LAT_VALUE = 1
702 10:51:53.795132 ==============================================================
703 10:51:53.798852 Enter into Gating configuration >>>>
704 10:51:53.801988 Exit from Gating configuration <<<<
705 10:51:53.805165 Enter into DVFS_PRE_config >>>>>
706 10:51:53.815369 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 10:51:53.818759 Exit from DVFS_PRE_config <<<<<
708 10:51:53.821875 Enter into PICG configuration >>>>
709 10:51:53.825180 Exit from PICG configuration <<<<
710 10:51:53.828478 [RX_INPUT] configuration >>>>>
711 10:51:53.832708 [RX_INPUT] configuration <<<<<
712 10:51:53.835622 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 10:51:53.842534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 10:51:53.849235 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 10:51:53.853120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 10:51:53.860375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 10:51:53.867274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 10:51:53.870743 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 10:51:53.874420 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 10:51:53.878427 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 10:51:53.882414 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 10:51:53.885522 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 10:51:53.892613 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 10:51:53.896895 ===================================
725 10:51:53.897601 LPDDR4 DRAM CONFIGURATION
726 10:51:53.899931 ===================================
727 10:51:53.903532 EX_ROW_EN[0] = 0x0
728 10:51:53.904027 EX_ROW_EN[1] = 0x0
729 10:51:53.907231 LP4Y_EN = 0x0
730 10:51:53.907661 WORK_FSP = 0x0
731 10:51:53.911647 WL = 0x2
732 10:51:53.912235 RL = 0x2
733 10:51:53.915061 BL = 0x2
734 10:51:53.915657 RPST = 0x0
735 10:51:53.916037 RD_PRE = 0x0
736 10:51:53.918512 WR_PRE = 0x1
737 10:51:53.918985 WR_PST = 0x0
738 10:51:53.922602 DBI_WR = 0x0
739 10:51:53.923154 DBI_RD = 0x0
740 10:51:53.926082 OTF = 0x1
741 10:51:53.929341 ===================================
742 10:51:53.933253 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 10:51:53.936873 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 10:51:53.941262 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 10:51:53.944278 ===================================
746 10:51:53.948008 LPDDR4 DRAM CONFIGURATION
747 10:51:53.951791 ===================================
748 10:51:53.952224 EX_ROW_EN[0] = 0x10
749 10:51:53.955397 EX_ROW_EN[1] = 0x0
750 10:51:53.955829 LP4Y_EN = 0x0
751 10:51:53.959708 WORK_FSP = 0x0
752 10:51:53.960259 WL = 0x2
753 10:51:53.960610 RL = 0x2
754 10:51:53.963127 BL = 0x2
755 10:51:53.963683 RPST = 0x0
756 10:51:53.966715 RD_PRE = 0x0
757 10:51:53.967268 WR_PRE = 0x1
758 10:51:53.970514 WR_PST = 0x0
759 10:51:53.971069 DBI_WR = 0x0
760 10:51:53.974194 DBI_RD = 0x0
761 10:51:53.974659 OTF = 0x1
762 10:51:53.978017 ===================================
763 10:51:53.985105 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 10:51:53.988282 nWR fixed to 40
765 10:51:53.988722 [ModeRegInit_LP4] CH0 RK0
766 10:51:53.992372 [ModeRegInit_LP4] CH0 RK1
767 10:51:53.995688 [ModeRegInit_LP4] CH1 RK0
768 10:51:53.996125 [ModeRegInit_LP4] CH1 RK1
769 10:51:53.999878 match AC timing 13
770 10:51:54.003656 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 10:51:54.006849 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 10:51:54.010320 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 10:51:54.018426 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 10:51:54.021742 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 10:51:54.022338 [EMI DOE] emi_dcm 0
776 10:51:54.028626 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 10:51:54.029149 ==
778 10:51:54.032300 Dram Type= 6, Freq= 0, CH_0, rank 0
779 10:51:54.036104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 10:51:54.036665 ==
781 10:51:54.040111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 10:51:54.046507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 10:51:54.055892 [CA 0] Center 38 (7~69) winsize 63
784 10:51:54.059284 [CA 1] Center 38 (7~69) winsize 63
785 10:51:54.063137 [CA 2] Center 35 (5~66) winsize 62
786 10:51:54.066355 [CA 3] Center 35 (4~66) winsize 63
787 10:51:54.070391 [CA 4] Center 34 (4~65) winsize 62
788 10:51:54.074452 [CA 5] Center 33 (3~64) winsize 62
789 10:51:54.074999
790 10:51:54.077647 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 10:51:54.078083
792 10:51:54.081504 [CATrainingPosCal] consider 1 rank data
793 10:51:54.081936 u2DelayCellTimex100 = 270/100 ps
794 10:51:54.085194 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 10:51:54.088608 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 10:51:54.092832 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 10:51:54.100083 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
798 10:51:54.100661 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 10:51:54.103512 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 10:51:54.107081
801 10:51:54.107633 CA PerBit enable=1, Macro0, CA PI delay=33
802 10:51:54.110729
803 10:51:54.111284 [CBTSetCACLKResult] CA Dly = 33
804 10:51:54.114779 CS Dly: 6 (0~37)
805 10:51:54.115209 ==
806 10:51:54.118641 Dram Type= 6, Freq= 0, CH_0, rank 1
807 10:51:54.122226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 10:51:54.122938 ==
809 10:51:54.125638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 10:51:54.132554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 10:51:54.142472 [CA 0] Center 38 (7~69) winsize 63
812 10:51:54.145702 [CA 1] Center 38 (7~69) winsize 63
813 10:51:54.149099 [CA 2] Center 36 (6~67) winsize 62
814 10:51:54.152874 [CA 3] Center 35 (5~66) winsize 62
815 10:51:54.155692 [CA 4] Center 35 (4~66) winsize 63
816 10:51:54.159450 [CA 5] Center 34 (4~65) winsize 62
817 10:51:54.159563
818 10:51:54.162512 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 10:51:54.162602
820 10:51:54.165633 [CATrainingPosCal] consider 2 rank data
821 10:51:54.168949 u2DelayCellTimex100 = 270/100 ps
822 10:51:54.172496 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 10:51:54.175673 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 10:51:54.178996 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 10:51:54.182464 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 10:51:54.185565 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 10:51:54.192268 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 10:51:54.192384
829 10:51:54.195561 CA PerBit enable=1, Macro0, CA PI delay=34
830 10:51:54.195667
831 10:51:54.199167 [CBTSetCACLKResult] CA Dly = 34
832 10:51:54.199256 CS Dly: 6 (0~38)
833 10:51:54.199326
834 10:51:54.202542 ----->DramcWriteLeveling(PI) begin...
835 10:51:54.202644 ==
836 10:51:54.205421 Dram Type= 6, Freq= 0, CH_0, rank 0
837 10:51:54.212060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 10:51:54.212184 ==
839 10:51:54.215573 Write leveling (Byte 0): 30 => 30
840 10:51:54.215686 Write leveling (Byte 1): 29 => 29
841 10:51:54.218690 DramcWriteLeveling(PI) end<-----
842 10:51:54.218791
843 10:51:54.222095 ==
844 10:51:54.222203 Dram Type= 6, Freq= 0, CH_0, rank 0
845 10:51:54.229056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 10:51:54.229135 ==
847 10:51:54.232507 [Gating] SW mode calibration
848 10:51:54.239517 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 10:51:54.242373 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 10:51:54.246312 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 10:51:54.253115 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
852 10:51:54.256667 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 10:51:54.259966 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:51:54.263592 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:51:54.270314 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:51:54.273768 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:51:54.277315 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:51:54.283509 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:51:54.286793 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:51:54.290079 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:51:54.296867 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:51:54.300471 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:51:54.303547 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:51:54.310239 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:51:54.313640 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:51:54.316735 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 10:51:54.323649 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 10:51:54.327001 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:51:54.330016 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:51:54.336694 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 10:51:54.340180 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 10:51:54.343606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:51:54.346680 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:51:54.353571 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:51:54.357046 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
876 10:51:54.360160 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 10:51:54.366733 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
878 10:51:54.370228 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 10:51:54.373547 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 10:51:54.380402 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 10:51:54.383580 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:51:54.386802 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 10:51:54.393296 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
884 10:51:54.396756 0 10 8 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
885 10:51:54.400363 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
886 10:51:54.406543 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 10:51:54.409971 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 10:51:54.413666 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 10:51:54.420075 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:51:54.423754 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:51:54.426861 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
892 10:51:54.433397 0 11 8 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
893 10:51:54.436660 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 10:51:54.440149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 10:51:54.446799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 10:51:54.449819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 10:51:54.453448 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:51:54.456926 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 10:51:54.463281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 10:51:54.466897 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 10:51:54.469928 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:51:54.476683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:51:54.479939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:51:54.483469 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:51:54.490284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:51:54.493458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:51:54.496593 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:51:54.503129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:51:54.506427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:51:54.509783 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:51:54.516681 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:51:54.520103 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:51:54.523164 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:51:54.529962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:51:54.533453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:51:54.536551 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 10:51:54.539884 Total UI for P1: 0, mck2ui 16
918 10:51:54.543308 best dqsien dly found for B0: ( 0, 14, 6)
919 10:51:54.546367 Total UI for P1: 0, mck2ui 16
920 10:51:54.549821 best dqsien dly found for B1: ( 0, 14, 6)
921 10:51:54.553147 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
922 10:51:54.556274 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
923 10:51:54.556357
924 10:51:54.559787 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
925 10:51:54.566320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 10:51:54.566404 [Gating] SW calibration Done
927 10:51:54.566470 ==
928 10:51:54.569962 Dram Type= 6, Freq= 0, CH_0, rank 0
929 10:51:54.576519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 10:51:54.576604 ==
931 10:51:54.576670 RX Vref Scan: 0
932 10:51:54.576732
933 10:51:54.579788 RX Vref 0 -> 0, step: 1
934 10:51:54.579872
935 10:51:54.583124 RX Delay -130 -> 252, step: 16
936 10:51:54.586330 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
937 10:51:54.589808 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 10:51:54.593237 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
939 10:51:54.599735 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
940 10:51:54.603015 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 10:51:54.606290 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 10:51:54.609565 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 10:51:54.613023 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 10:51:54.619753 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 10:51:54.623112 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
946 10:51:54.626173 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
947 10:51:54.629792 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 10:51:54.633092 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
949 10:51:54.639659 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 10:51:54.643161 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 10:51:54.646113 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
952 10:51:54.646215 ==
953 10:51:54.649603 Dram Type= 6, Freq= 0, CH_0, rank 0
954 10:51:54.652970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 10:51:54.653050 ==
956 10:51:54.655929 DQS Delay:
957 10:51:54.656042 DQS0 = 0, DQS1 = 0
958 10:51:54.659698 DQM Delay:
959 10:51:54.659802 DQM0 = 90, DQM1 = 80
960 10:51:54.659911 DQ Delay:
961 10:51:54.662858 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
962 10:51:54.666104 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
963 10:51:54.669489 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
964 10:51:54.672666 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
965 10:51:54.672774
966 10:51:54.676162
967 10:51:54.676233 ==
968 10:51:54.679288 Dram Type= 6, Freq= 0, CH_0, rank 0
969 10:51:54.682537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 10:51:54.682636 ==
971 10:51:54.682734
972 10:51:54.682822
973 10:51:54.686155 TX Vref Scan disable
974 10:51:54.686228 == TX Byte 0 ==
975 10:51:54.692413 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
976 10:51:54.695809 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
977 10:51:54.695908 == TX Byte 1 ==
978 10:51:54.702651 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
979 10:51:54.705882 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
980 10:51:54.705991 ==
981 10:51:54.708973 Dram Type= 6, Freq= 0, CH_0, rank 0
982 10:51:54.712063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 10:51:54.712169 ==
984 10:51:54.725705 TX Vref=22, minBit 1, minWin=27, winSum=440
985 10:51:54.729204 TX Vref=24, minBit 10, minWin=27, winSum=444
986 10:51:54.732439 TX Vref=26, minBit 8, minWin=27, winSum=450
987 10:51:54.735963 TX Vref=28, minBit 9, minWin=27, winSum=452
988 10:51:54.739186 TX Vref=30, minBit 3, minWin=28, winSum=454
989 10:51:54.745892 TX Vref=32, minBit 6, minWin=28, winSum=456
990 10:51:54.749229 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 32
991 10:51:54.749314
992 10:51:54.752374 Final TX Range 1 Vref 32
993 10:51:54.752458
994 10:51:54.752525 ==
995 10:51:54.755796 Dram Type= 6, Freq= 0, CH_0, rank 0
996 10:51:54.759034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 10:51:54.762220 ==
998 10:51:54.762304
999 10:51:54.762371
1000 10:51:54.762431 TX Vref Scan disable
1001 10:51:54.766123 == TX Byte 0 ==
1002 10:51:54.769507 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1003 10:51:54.776046 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1004 10:51:54.776131 == TX Byte 1 ==
1005 10:51:54.779305 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1006 10:51:54.782500 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1007 10:51:54.785800
1008 10:51:54.785884 [DATLAT]
1009 10:51:54.785951 Freq=800, CH0 RK0
1010 10:51:54.786013
1011 10:51:54.788909 DATLAT Default: 0xa
1012 10:51:54.788994 0, 0xFFFF, sum = 0
1013 10:51:54.792398 1, 0xFFFF, sum = 0
1014 10:51:54.795707 2, 0xFFFF, sum = 0
1015 10:51:54.795792 3, 0xFFFF, sum = 0
1016 10:51:54.798945 4, 0xFFFF, sum = 0
1017 10:51:54.799030 5, 0xFFFF, sum = 0
1018 10:51:54.802363 6, 0xFFFF, sum = 0
1019 10:51:54.802449 7, 0xFFFF, sum = 0
1020 10:51:54.805538 8, 0xFFFF, sum = 0
1021 10:51:54.805623 9, 0x0, sum = 1
1022 10:51:54.809212 10, 0x0, sum = 2
1023 10:51:54.809297 11, 0x0, sum = 3
1024 10:51:54.809365 12, 0x0, sum = 4
1025 10:51:54.812466 best_step = 10
1026 10:51:54.812548
1027 10:51:54.812613 ==
1028 10:51:54.815830 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 10:51:54.819045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 10:51:54.819129 ==
1031 10:51:54.822092 RX Vref Scan: 1
1032 10:51:54.822174
1033 10:51:54.825537 Set Vref Range= 32 -> 127
1034 10:51:54.825619
1035 10:51:54.825684 RX Vref 32 -> 127, step: 1
1036 10:51:54.825743
1037 10:51:54.828895 RX Delay -79 -> 252, step: 8
1038 10:51:54.828977
1039 10:51:54.832327 Set Vref, RX VrefLevel [Byte0]: 32
1040 10:51:54.835642 [Byte1]: 32
1041 10:51:54.835725
1042 10:51:54.839053 Set Vref, RX VrefLevel [Byte0]: 33
1043 10:51:54.842094 [Byte1]: 33
1044 10:51:54.846251
1045 10:51:54.846334 Set Vref, RX VrefLevel [Byte0]: 34
1046 10:51:54.849381 [Byte1]: 34
1047 10:51:54.853760
1048 10:51:54.853843 Set Vref, RX VrefLevel [Byte0]: 35
1049 10:51:54.857050 [Byte1]: 35
1050 10:51:54.861367
1051 10:51:54.861449 Set Vref, RX VrefLevel [Byte0]: 36
1052 10:51:54.864883 [Byte1]: 36
1053 10:51:54.869372
1054 10:51:54.869454 Set Vref, RX VrefLevel [Byte0]: 37
1055 10:51:54.872418 [Byte1]: 37
1056 10:51:54.876443
1057 10:51:54.876525 Set Vref, RX VrefLevel [Byte0]: 38
1058 10:51:54.879627 [Byte1]: 38
1059 10:51:54.884155
1060 10:51:54.884239 Set Vref, RX VrefLevel [Byte0]: 39
1061 10:51:54.887234 [Byte1]: 39
1062 10:51:54.891645
1063 10:51:54.891727 Set Vref, RX VrefLevel [Byte0]: 40
1064 10:51:54.894962 [Byte1]: 40
1065 10:51:54.898846
1066 10:51:54.902624 Set Vref, RX VrefLevel [Byte0]: 41
1067 10:51:54.902709 [Byte1]: 41
1068 10:51:54.907063
1069 10:51:54.907147 Set Vref, RX VrefLevel [Byte0]: 42
1070 10:51:54.910457 [Byte1]: 42
1071 10:51:54.914614
1072 10:51:54.914697 Set Vref, RX VrefLevel [Byte0]: 43
1073 10:51:54.917664 [Byte1]: 43
1074 10:51:54.922124
1075 10:51:54.922207 Set Vref, RX VrefLevel [Byte0]: 44
1076 10:51:54.924943 [Byte1]: 44
1077 10:51:54.929091
1078 10:51:54.929176 Set Vref, RX VrefLevel [Byte0]: 45
1079 10:51:54.932608 [Byte1]: 45
1080 10:51:54.936458
1081 10:51:54.939968 Set Vref, RX VrefLevel [Byte0]: 46
1082 10:51:54.940053 [Byte1]: 46
1083 10:51:54.944513
1084 10:51:54.944596 Set Vref, RX VrefLevel [Byte0]: 47
1085 10:51:54.947553 [Byte1]: 47
1086 10:51:54.951809
1087 10:51:54.951892 Set Vref, RX VrefLevel [Byte0]: 48
1088 10:51:54.955282 [Byte1]: 48
1089 10:51:54.959317
1090 10:51:54.959400 Set Vref, RX VrefLevel [Byte0]: 49
1091 10:51:54.962738 [Byte1]: 49
1092 10:51:54.967286
1093 10:51:54.967369 Set Vref, RX VrefLevel [Byte0]: 50
1094 10:51:54.970296 [Byte1]: 50
1095 10:51:54.974454
1096 10:51:54.974538 Set Vref, RX VrefLevel [Byte0]: 51
1097 10:51:54.977735 [Byte1]: 51
1098 10:51:54.982146
1099 10:51:54.982229 Set Vref, RX VrefLevel [Byte0]: 52
1100 10:51:54.985441 [Byte1]: 52
1101 10:51:54.989750
1102 10:51:54.989832 Set Vref, RX VrefLevel [Byte0]: 53
1103 10:51:54.992731 [Byte1]: 53
1104 10:51:54.997185
1105 10:51:54.997268 Set Vref, RX VrefLevel [Byte0]: 54
1106 10:51:55.000411 [Byte1]: 54
1107 10:51:55.004646
1108 10:51:55.004729 Set Vref, RX VrefLevel [Byte0]: 55
1109 10:51:55.008070 [Byte1]: 55
1110 10:51:55.012427
1111 10:51:55.012511 Set Vref, RX VrefLevel [Byte0]: 56
1112 10:51:55.015591 [Byte1]: 56
1113 10:51:55.020006
1114 10:51:55.020092 Set Vref, RX VrefLevel [Byte0]: 57
1115 10:51:55.023000 [Byte1]: 57
1116 10:51:55.027249
1117 10:51:55.027332 Set Vref, RX VrefLevel [Byte0]: 58
1118 10:51:55.030505 [Byte1]: 58
1119 10:51:55.034980
1120 10:51:55.035063 Set Vref, RX VrefLevel [Byte0]: 59
1121 10:51:55.038100 [Byte1]: 59
1122 10:51:55.042587
1123 10:51:55.042670 Set Vref, RX VrefLevel [Byte0]: 60
1124 10:51:55.045790 [Byte1]: 60
1125 10:51:55.049837
1126 10:51:55.049920 Set Vref, RX VrefLevel [Byte0]: 61
1127 10:51:55.053222 [Byte1]: 61
1128 10:51:55.057429
1129 10:51:55.057513 Set Vref, RX VrefLevel [Byte0]: 62
1130 10:51:55.061149 [Byte1]: 62
1131 10:51:55.064868
1132 10:51:55.064951 Set Vref, RX VrefLevel [Byte0]: 63
1133 10:51:55.068474 [Byte1]: 63
1134 10:51:55.072757
1135 10:51:55.072877 Set Vref, RX VrefLevel [Byte0]: 64
1136 10:51:55.075718 [Byte1]: 64
1137 10:51:55.080117
1138 10:51:55.080200 Set Vref, RX VrefLevel [Byte0]: 65
1139 10:51:55.083509 [Byte1]: 65
1140 10:51:55.087855
1141 10:51:55.087941 Set Vref, RX VrefLevel [Byte0]: 66
1142 10:51:55.091087 [Byte1]: 66
1143 10:51:55.095453
1144 10:51:55.095536 Set Vref, RX VrefLevel [Byte0]: 67
1145 10:51:55.098373 [Byte1]: 67
1146 10:51:55.102962
1147 10:51:55.103046 Set Vref, RX VrefLevel [Byte0]: 68
1148 10:51:55.106002 [Byte1]: 68
1149 10:51:55.110300
1150 10:51:55.110384 Set Vref, RX VrefLevel [Byte0]: 69
1151 10:51:55.113893 [Byte1]: 69
1152 10:51:55.117842
1153 10:51:55.117925 Set Vref, RX VrefLevel [Byte0]: 70
1154 10:51:55.121162 [Byte1]: 70
1155 10:51:55.125564
1156 10:51:55.125647 Set Vref, RX VrefLevel [Byte0]: 71
1157 10:51:55.128733 [Byte1]: 71
1158 10:51:55.132933
1159 10:51:55.133016 Set Vref, RX VrefLevel [Byte0]: 72
1160 10:51:55.136198 [Byte1]: 72
1161 10:51:55.140623
1162 10:51:55.140706 Set Vref, RX VrefLevel [Byte0]: 73
1163 10:51:55.143947 [Byte1]: 73
1164 10:51:55.148212
1165 10:51:55.148295 Set Vref, RX VrefLevel [Byte0]: 74
1166 10:51:55.151587 [Byte1]: 74
1167 10:51:55.155503
1168 10:51:55.155586 Set Vref, RX VrefLevel [Byte0]: 75
1169 10:51:55.158981 [Byte1]: 75
1170 10:51:55.163185
1171 10:51:55.163269 Set Vref, RX VrefLevel [Byte0]: 76
1172 10:51:55.166346 [Byte1]: 76
1173 10:51:55.170710
1174 10:51:55.170793 Set Vref, RX VrefLevel [Byte0]: 77
1175 10:51:55.174127 [Byte1]: 77
1176 10:51:55.178228
1177 10:51:55.178311 Final RX Vref Byte 0 = 61 to rank0
1178 10:51:55.181363 Final RX Vref Byte 1 = 63 to rank0
1179 10:51:55.184777 Final RX Vref Byte 0 = 61 to rank1
1180 10:51:55.188197 Final RX Vref Byte 1 = 63 to rank1==
1181 10:51:55.191508 Dram Type= 6, Freq= 0, CH_0, rank 0
1182 10:51:55.198627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 10:51:55.198711 ==
1184 10:51:55.198778 DQS Delay:
1185 10:51:55.198838 DQS0 = 0, DQS1 = 0
1186 10:51:55.201559 DQM Delay:
1187 10:51:55.201643 DQM0 = 93, DQM1 = 82
1188 10:51:55.204708 DQ Delay:
1189 10:51:55.208564 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1190 10:51:55.211896 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1191 10:51:55.211983 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1192 10:51:55.218537 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1193 10:51:55.218621
1194 10:51:55.218686
1195 10:51:55.224881 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1196 10:51:55.228353 CH0 RK0: MR19=606, MR18=3C37
1197 10:51:55.235060 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1198 10:51:55.235144
1199 10:51:55.238039 ----->DramcWriteLeveling(PI) begin...
1200 10:51:55.238124 ==
1201 10:51:55.241362 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 10:51:55.244797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 10:51:55.244895 ==
1204 10:51:55.248517 Write leveling (Byte 0): 33 => 33
1205 10:51:55.251601 Write leveling (Byte 1): 29 => 29
1206 10:51:55.254874 DramcWriteLeveling(PI) end<-----
1207 10:51:55.254958
1208 10:51:55.255023 ==
1209 10:51:55.258435 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 10:51:55.261630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 10:51:55.261714 ==
1212 10:51:55.264811 [Gating] SW mode calibration
1213 10:51:55.271812 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1214 10:51:55.278060 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1215 10:51:55.281686 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 10:51:55.284874 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1217 10:51:55.291489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1218 10:51:55.294989 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:51:55.298160 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:51:55.345577 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:51:55.345671 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:51:55.346123 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:51:55.346206 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:51:55.346457 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:51:55.346762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:51:55.346845 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:51:55.347356 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:51:55.348176 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:51:55.348509 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:51:55.388967 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:51:55.389069 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1232 10:51:55.389350 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1233 10:51:55.389432 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:51:55.389507 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 10:51:55.389579 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:51:55.389640 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:51:55.389880 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 10:51:55.389946 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 10:51:55.390014 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 10:51:55.393213 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1241 10:51:55.396827 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1242 10:51:55.399907 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 10:51:55.403167 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 10:51:55.409680 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 10:51:55.413409 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 10:51:55.416325 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 10:51:55.423432 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 10:51:55.426368 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1249 10:51:55.429833 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1250 10:51:55.436682 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:51:55.439800 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:51:55.443164 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:51:55.449704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:51:55.453151 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 10:51:55.456067 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 10:51:55.462880 0 11 4 | B1->B0 | 2525 3131 | 0 1 | (0 0) (0 0)
1257 10:51:55.466497 0 11 8 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
1258 10:51:55.469527 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 10:51:55.476018 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 10:51:55.479772 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 10:51:55.483210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 10:51:55.487351 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 10:51:55.491120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 10:51:55.498244 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1265 10:51:55.501575 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 10:51:55.505123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:51:55.511945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:51:55.514992 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:51:55.518483 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:51:55.525196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:51:55.528179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:51:55.531778 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:51:55.535349 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:51:55.541761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:51:55.545077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:51:55.548287 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:51:55.554937 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:51:55.558046 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 10:51:55.561787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 10:51:55.568377 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1281 10:51:55.571805 Total UI for P1: 0, mck2ui 16
1282 10:51:55.574769 best dqsien dly found for B0: ( 0, 14, 2)
1283 10:51:55.578153 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1284 10:51:55.581464 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 10:51:55.584902 Total UI for P1: 0, mck2ui 16
1286 10:51:55.588048 best dqsien dly found for B1: ( 0, 14, 6)
1287 10:51:55.591579 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1288 10:51:55.594809 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1289 10:51:55.594893
1290 10:51:55.601399 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1291 10:51:55.604968 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 10:51:55.605052 [Gating] SW calibration Done
1293 10:51:55.608050 ==
1294 10:51:55.611238 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 10:51:55.614550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 10:51:55.614635 ==
1297 10:51:55.614702 RX Vref Scan: 0
1298 10:51:55.614765
1299 10:51:55.618140 RX Vref 0 -> 0, step: 1
1300 10:51:55.618223
1301 10:51:55.621320 RX Delay -130 -> 252, step: 16
1302 10:51:55.624688 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1303 10:51:55.627727 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1304 10:51:55.634699 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1305 10:51:55.637745 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1306 10:51:55.640964 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1307 10:51:55.644455 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1308 10:51:55.648248 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1309 10:51:55.654535 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1310 10:51:55.657664 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1311 10:51:55.661044 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1312 10:51:55.664309 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1313 10:51:55.667771 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1314 10:51:55.674382 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1315 10:51:55.677637 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1316 10:51:55.680861 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1317 10:51:55.684143 iDelay=206, Bit 15, Center 77 (-34 ~ 189) 224
1318 10:51:55.684227 ==
1319 10:51:55.687745 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 10:51:55.694120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 10:51:55.694205 ==
1322 10:51:55.694272 DQS Delay:
1323 10:51:55.694366 DQS0 = 0, DQS1 = 0
1324 10:51:55.697561 DQM Delay:
1325 10:51:55.697645 DQM0 = 87, DQM1 = 78
1326 10:51:55.700793 DQ Delay:
1327 10:51:55.704083 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1328 10:51:55.704167 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1329 10:51:55.707457 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1330 10:51:55.714391 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
1331 10:51:55.714477
1332 10:51:55.714543
1333 10:51:55.714603 ==
1334 10:51:55.717518 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 10:51:55.721023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 10:51:55.721114 ==
1337 10:51:55.721181
1338 10:51:55.721243
1339 10:51:55.724281 TX Vref Scan disable
1340 10:51:55.724365 == TX Byte 0 ==
1341 10:51:55.730745 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1342 10:51:55.734002 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1343 10:51:55.734086 == TX Byte 1 ==
1344 10:51:55.740754 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1345 10:51:55.744165 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1346 10:51:55.744252 ==
1347 10:51:55.747650 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 10:51:55.750593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 10:51:55.750677 ==
1350 10:51:55.765020 TX Vref=22, minBit 3, minWin=27, winSum=445
1351 10:51:55.768598 TX Vref=24, minBit 8, minWin=27, winSum=449
1352 10:51:55.771688 TX Vref=26, minBit 8, minWin=27, winSum=450
1353 10:51:55.775282 TX Vref=28, minBit 8, minWin=27, winSum=454
1354 10:51:55.778172 TX Vref=30, minBit 8, minWin=27, winSum=457
1355 10:51:55.784774 TX Vref=32, minBit 8, minWin=27, winSum=457
1356 10:51:55.788079 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1357 10:51:55.788163
1358 10:51:55.791801 Final TX Range 1 Vref 30
1359 10:51:55.791885
1360 10:51:55.791949 ==
1361 10:51:55.794794 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 10:51:55.798135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 10:51:55.798223 ==
1364 10:51:55.801287
1365 10:51:55.801368
1366 10:51:55.801432 TX Vref Scan disable
1367 10:51:55.805038 == TX Byte 0 ==
1368 10:51:55.808197 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1369 10:51:55.815080 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1370 10:51:55.815165 == TX Byte 1 ==
1371 10:51:55.818294 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1372 10:51:55.825057 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1373 10:51:55.825139
1374 10:51:55.825203 [DATLAT]
1375 10:51:55.825263 Freq=800, CH0 RK1
1376 10:51:55.825320
1377 10:51:55.828427 DATLAT Default: 0xa
1378 10:51:55.828509 0, 0xFFFF, sum = 0
1379 10:51:55.831352 1, 0xFFFF, sum = 0
1380 10:51:55.834826 2, 0xFFFF, sum = 0
1381 10:51:55.834909 3, 0xFFFF, sum = 0
1382 10:51:55.837937 4, 0xFFFF, sum = 0
1383 10:51:55.838020 5, 0xFFFF, sum = 0
1384 10:51:55.841311 6, 0xFFFF, sum = 0
1385 10:51:55.841394 7, 0xFFFF, sum = 0
1386 10:51:55.844919 8, 0xFFFF, sum = 0
1387 10:51:55.845002 9, 0x0, sum = 1
1388 10:51:55.847944 10, 0x0, sum = 2
1389 10:51:55.848027 11, 0x0, sum = 3
1390 10:51:55.848092 12, 0x0, sum = 4
1391 10:51:55.851201 best_step = 10
1392 10:51:55.851283
1393 10:51:55.851347 ==
1394 10:51:55.854959 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 10:51:55.858104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 10:51:55.858186 ==
1397 10:51:55.861261 RX Vref Scan: 0
1398 10:51:55.861343
1399 10:51:55.861406 RX Vref 0 -> 0, step: 1
1400 10:51:55.864856
1401 10:51:55.864937 RX Delay -79 -> 252, step: 8
1402 10:51:55.871540 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1403 10:51:55.874750 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1404 10:51:55.878188 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 10:51:55.881720 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1406 10:51:55.884746 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 10:51:55.891778 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1408 10:51:55.895015 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 10:51:55.898264 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 10:51:55.902204 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1411 10:51:55.904774 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1412 10:51:55.911480 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1413 10:51:55.914566 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1414 10:51:55.918158 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1415 10:51:55.921226 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 10:51:55.927739 iDelay=209, Bit 14, Center 88 (-15 ~ 192) 208
1417 10:51:55.931077 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1418 10:51:55.931159 ==
1419 10:51:55.934872 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 10:51:55.937638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 10:51:55.937720 ==
1422 10:51:55.941002 DQS Delay:
1423 10:51:55.941083 DQS0 = 0, DQS1 = 0
1424 10:51:55.941146 DQM Delay:
1425 10:51:55.944465 DQM0 = 91, DQM1 = 80
1426 10:51:55.944547 DQ Delay:
1427 10:51:55.947687 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1428 10:51:55.951268 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1429 10:51:55.954387 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1430 10:51:55.957930 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1431 10:51:55.958012
1432 10:51:55.958075
1433 10:51:55.967490 [DQSOSCAuto] RK1, (LSB)MR18= 0x431e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1434 10:51:55.971159 CH0 RK1: MR19=606, MR18=431E
1435 10:51:55.974119 CH0_RK1: MR19=0x606, MR18=0x431E, DQSOSC=393, MR23=63, INC=95, DEC=63
1436 10:51:55.977477 [RxdqsGatingPostProcess] freq 800
1437 10:51:55.983906 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 10:51:55.987332 Pre-setting of DQS Precalculation
1439 10:51:55.990932 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 10:51:55.991019 ==
1441 10:51:55.993863 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 10:51:56.000580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 10:51:56.000665 ==
1444 10:51:56.004022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 10:51:56.010790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 10:51:56.020046 [CA 0] Center 36 (6~67) winsize 62
1447 10:51:56.023293 [CA 1] Center 37 (6~68) winsize 63
1448 10:51:56.026607 [CA 2] Center 35 (5~65) winsize 61
1449 10:51:56.030200 [CA 3] Center 34 (4~65) winsize 62
1450 10:51:56.033440 [CA 4] Center 34 (4~65) winsize 62
1451 10:51:56.036745 [CA 5] Center 33 (3~64) winsize 62
1452 10:51:56.036868
1453 10:51:56.040171 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1454 10:51:56.040254
1455 10:51:56.043365 [CATrainingPosCal] consider 1 rank data
1456 10:51:56.046642 u2DelayCellTimex100 = 270/100 ps
1457 10:51:56.050118 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1458 10:51:56.056717 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1459 10:51:56.059953 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1460 10:51:56.063356 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 10:51:56.066953 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 10:51:56.070005 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 10:51:56.070089
1464 10:51:56.073406 CA PerBit enable=1, Macro0, CA PI delay=33
1465 10:51:56.073490
1466 10:51:56.076482 [CBTSetCACLKResult] CA Dly = 33
1467 10:51:56.079681 CS Dly: 5 (0~36)
1468 10:51:56.079765 ==
1469 10:51:56.083220 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 10:51:56.086662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 10:51:56.086747 ==
1472 10:51:56.093088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 10:51:56.096344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 10:51:56.106440 [CA 0] Center 37 (7~68) winsize 62
1475 10:51:56.109904 [CA 1] Center 37 (6~68) winsize 63
1476 10:51:56.112914 [CA 2] Center 35 (5~66) winsize 62
1477 10:51:56.116410 [CA 3] Center 34 (4~65) winsize 62
1478 10:51:56.119951 [CA 4] Center 35 (5~65) winsize 61
1479 10:51:56.122938 [CA 5] Center 34 (4~65) winsize 62
1480 10:51:56.123022
1481 10:51:56.126276 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1482 10:51:56.126360
1483 10:51:56.129873 [CATrainingPosCal] consider 2 rank data
1484 10:51:56.132900 u2DelayCellTimex100 = 270/100 ps
1485 10:51:56.136797 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1486 10:51:56.143062 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1487 10:51:56.146487 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 10:51:56.150035 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 10:51:56.153575 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1490 10:51:56.157321 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 10:51:56.157404
1492 10:51:56.161115 CA PerBit enable=1, Macro0, CA PI delay=34
1493 10:51:56.161198
1494 10:51:56.164706 [CBTSetCACLKResult] CA Dly = 34
1495 10:51:56.164793 CS Dly: 6 (0~38)
1496 10:51:56.164860
1497 10:51:56.168537 ----->DramcWriteLeveling(PI) begin...
1498 10:51:56.168621 ==
1499 10:51:56.172074 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 10:51:56.175724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 10:51:56.175808 ==
1502 10:51:56.179275 Write leveling (Byte 0): 29 => 29
1503 10:51:56.182648 Write leveling (Byte 1): 29 => 29
1504 10:51:56.186456 DramcWriteLeveling(PI) end<-----
1505 10:51:56.186539
1506 10:51:56.186604 ==
1507 10:51:56.189312 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 10:51:56.192773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 10:51:56.192859 ==
1510 10:51:56.196156 [Gating] SW mode calibration
1511 10:51:56.202572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 10:51:56.209378 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 10:51:56.212871 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 10:51:56.215880 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1515 10:51:56.222466 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:51:56.226210 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:51:56.229501 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:51:56.232509 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:51:56.239073 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:51:56.242433 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:51:56.245709 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:51:56.252226 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:51:56.255935 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:51:56.259224 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:51:56.265744 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:51:56.269017 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:51:56.272380 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:51:56.278871 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:51:56.282226 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:51:56.285642 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1531 10:51:56.292265 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:51:56.295587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:51:56.299053 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 10:51:56.305507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 10:51:56.308667 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 10:51:56.312501 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 10:51:56.318697 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 10:51:56.322487 0 9 4 | B1->B0 | 2323 2727 | 1 0 | (1 1) (0 0)
1539 10:51:56.325482 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1540 10:51:56.332149 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 10:51:56.335505 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 10:51:56.338697 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 10:51:56.345538 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 10:51:56.348692 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 10:51:56.352251 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1546 10:51:56.358936 0 10 4 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 0)
1547 10:51:56.362150 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:51:56.365022 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:51:56.371740 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:51:56.374860 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:51:56.378234 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:51:56.385032 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 10:51:56.388401 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 10:51:56.391636 0 11 4 | B1->B0 | 3030 3333 | 0 0 | (1 1) (0 0)
1555 10:51:56.398286 0 11 8 | B1->B0 | 4545 4444 | 0 0 | (0 0) (1 1)
1556 10:51:56.401992 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 10:51:56.405078 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 10:51:56.411530 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 10:51:56.414828 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 10:51:56.418260 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 10:51:56.421333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1562 10:51:56.428231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1563 10:51:56.431527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1564 10:51:56.434982 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:51:56.441230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:51:56.444773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:51:56.448269 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:51:56.454512 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:51:56.457819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:51:56.461322 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:51:56.468697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:51:56.471597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:51:56.474895 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:51:56.481501 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 10:51:56.485054 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 10:51:56.488230 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 10:51:56.494882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 10:51:56.498026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1579 10:51:56.501234 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 10:51:56.504731 Total UI for P1: 0, mck2ui 16
1581 10:51:56.508077 best dqsien dly found for B0: ( 0, 14, 2)
1582 10:51:56.511501 Total UI for P1: 0, mck2ui 16
1583 10:51:56.514648 best dqsien dly found for B1: ( 0, 14, 6)
1584 10:51:56.517942 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1585 10:51:56.521502 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1586 10:51:56.521584
1587 10:51:56.524694 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1588 10:51:56.531149 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1589 10:51:56.531222 [Gating] SW calibration Done
1590 10:51:56.531284 ==
1591 10:51:56.534931 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:51:56.541433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:51:56.541506 ==
1594 10:51:56.541576 RX Vref Scan: 0
1595 10:51:56.541634
1596 10:51:56.544540 RX Vref 0 -> 0, step: 1
1597 10:51:56.544642
1598 10:51:56.548056 RX Delay -130 -> 252, step: 16
1599 10:51:56.550982 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 10:51:56.554401 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 10:51:56.557571 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1602 10:51:56.564421 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 10:51:56.567789 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1604 10:51:56.570919 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1605 10:51:56.574656 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 10:51:56.577758 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 10:51:56.584228 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1608 10:51:56.587601 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 10:51:56.591201 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1610 10:51:56.594522 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 10:51:56.597916 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 10:51:56.604520 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 10:51:56.607515 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1614 10:51:56.611153 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1615 10:51:56.611234 ==
1616 10:51:56.614448 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 10:51:56.617596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 10:51:56.617667 ==
1619 10:51:56.621023 DQS Delay:
1620 10:51:56.621092 DQS0 = 0, DQS1 = 0
1621 10:51:56.624858 DQM Delay:
1622 10:51:56.624933 DQM0 = 93, DQM1 = 87
1623 10:51:56.624995 DQ Delay:
1624 10:51:56.627649 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1625 10:51:56.630859 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1626 10:51:56.634386 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1627 10:51:56.637701 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1628 10:51:56.637777
1629 10:51:56.637838
1630 10:51:56.641138 ==
1631 10:51:56.644266 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 10:51:56.647636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 10:51:56.647713 ==
1634 10:51:56.647774
1635 10:51:56.647832
1636 10:51:56.650706 TX Vref Scan disable
1637 10:51:56.650780 == TX Byte 0 ==
1638 10:51:56.657409 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1639 10:51:56.660768 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1640 10:51:56.660903 == TX Byte 1 ==
1641 10:51:56.667637 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1642 10:51:56.671006 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1643 10:51:56.671078 ==
1644 10:51:56.674076 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 10:51:56.677327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 10:51:56.677398 ==
1647 10:51:56.690632 TX Vref=22, minBit 11, minWin=26, winSum=446
1648 10:51:56.694115 TX Vref=24, minBit 8, minWin=27, winSum=450
1649 10:51:56.697310 TX Vref=26, minBit 8, minWin=27, winSum=453
1650 10:51:56.700647 TX Vref=28, minBit 15, minWin=27, winSum=457
1651 10:51:56.703972 TX Vref=30, minBit 8, minWin=28, winSum=460
1652 10:51:56.710848 TX Vref=32, minBit 8, minWin=27, winSum=458
1653 10:51:56.713876 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1654 10:51:56.713957
1655 10:51:56.717631 Final TX Range 1 Vref 30
1656 10:51:56.717702
1657 10:51:56.717770 ==
1658 10:51:56.720528 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 10:51:56.724386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 10:51:56.724456 ==
1661 10:51:56.727498
1662 10:51:56.727597
1663 10:51:56.727688 TX Vref Scan disable
1664 10:51:56.731102 == TX Byte 0 ==
1665 10:51:56.734648 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1666 10:51:56.737950 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1667 10:51:56.741180 == TX Byte 1 ==
1668 10:51:56.744509 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1669 10:51:56.747748 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1670 10:51:56.747817
1671 10:51:56.751084 [DATLAT]
1672 10:51:56.751153 Freq=800, CH1 RK0
1673 10:51:56.751220
1674 10:51:56.754396 DATLAT Default: 0xa
1675 10:51:56.754471 0, 0xFFFF, sum = 0
1676 10:51:56.758076 1, 0xFFFF, sum = 0
1677 10:51:56.758152 2, 0xFFFF, sum = 0
1678 10:51:56.761234 3, 0xFFFF, sum = 0
1679 10:51:56.761305 4, 0xFFFF, sum = 0
1680 10:51:56.764998 5, 0xFFFF, sum = 0
1681 10:51:56.765073 6, 0xFFFF, sum = 0
1682 10:51:56.768151 7, 0xFFFF, sum = 0
1683 10:51:56.768221 8, 0xFFFF, sum = 0
1684 10:51:56.771352 9, 0x0, sum = 1
1685 10:51:56.771422 10, 0x0, sum = 2
1686 10:51:56.774670 11, 0x0, sum = 3
1687 10:51:56.774745 12, 0x0, sum = 4
1688 10:51:56.777881 best_step = 10
1689 10:51:56.777951
1690 10:51:56.778011 ==
1691 10:51:56.781878 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 10:51:56.784331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 10:51:56.784408 ==
1694 10:51:56.788087 RX Vref Scan: 1
1695 10:51:56.788156
1696 10:51:56.788214 Set Vref Range= 32 -> 127
1697 10:51:56.788280
1698 10:51:56.791102 RX Vref 32 -> 127, step: 1
1699 10:51:56.791175
1700 10:51:56.794424 RX Delay -79 -> 252, step: 8
1701 10:51:56.794492
1702 10:51:56.797833 Set Vref, RX VrefLevel [Byte0]: 32
1703 10:51:56.801680 [Byte1]: 32
1704 10:51:56.801749
1705 10:51:56.804670 Set Vref, RX VrefLevel [Byte0]: 33
1706 10:51:56.807683 [Byte1]: 33
1707 10:51:56.810968
1708 10:51:56.811040 Set Vref, RX VrefLevel [Byte0]: 34
1709 10:51:56.814354 [Byte1]: 34
1710 10:51:56.818372
1711 10:51:56.818447 Set Vref, RX VrefLevel [Byte0]: 35
1712 10:51:56.821746 [Byte1]: 35
1713 10:51:56.825927
1714 10:51:56.825995 Set Vref, RX VrefLevel [Byte0]: 36
1715 10:51:56.829422 [Byte1]: 36
1716 10:51:56.833925
1717 10:51:56.834006 Set Vref, RX VrefLevel [Byte0]: 37
1718 10:51:56.837224 [Byte1]: 37
1719 10:51:56.841368
1720 10:51:56.841444 Set Vref, RX VrefLevel [Byte0]: 38
1721 10:51:56.844523 [Byte1]: 38
1722 10:51:56.849061
1723 10:51:56.849140 Set Vref, RX VrefLevel [Byte0]: 39
1724 10:51:56.851897 [Byte1]: 39
1725 10:51:56.856423
1726 10:51:56.856491 Set Vref, RX VrefLevel [Byte0]: 40
1727 10:51:56.859638 [Byte1]: 40
1728 10:51:56.863865
1729 10:51:56.863941 Set Vref, RX VrefLevel [Byte0]: 41
1730 10:51:56.867123 [Byte1]: 41
1731 10:51:56.871714
1732 10:51:56.871795 Set Vref, RX VrefLevel [Byte0]: 42
1733 10:51:56.874837 [Byte1]: 42
1734 10:51:56.878818
1735 10:51:56.878899 Set Vref, RX VrefLevel [Byte0]: 43
1736 10:51:56.882242 [Byte1]: 43
1737 10:51:56.886487
1738 10:51:56.886568 Set Vref, RX VrefLevel [Byte0]: 44
1739 10:51:56.889913 [Byte1]: 44
1740 10:51:56.894015
1741 10:51:56.894091 Set Vref, RX VrefLevel [Byte0]: 45
1742 10:51:56.897458 [Byte1]: 45
1743 10:51:56.901827
1744 10:51:56.901896 Set Vref, RX VrefLevel [Byte0]: 46
1745 10:51:56.905081 [Byte1]: 46
1746 10:51:56.909293
1747 10:51:56.909367 Set Vref, RX VrefLevel [Byte0]: 47
1748 10:51:56.912685 [Byte1]: 47
1749 10:51:56.916752
1750 10:51:56.916864 Set Vref, RX VrefLevel [Byte0]: 48
1751 10:51:56.919836 [Byte1]: 48
1752 10:51:56.924245
1753 10:51:56.924316 Set Vref, RX VrefLevel [Byte0]: 49
1754 10:51:56.927320 [Byte1]: 49
1755 10:51:56.931928
1756 10:51:56.931997 Set Vref, RX VrefLevel [Byte0]: 50
1757 10:51:56.934990 [Byte1]: 50
1758 10:51:56.939540
1759 10:51:56.939613 Set Vref, RX VrefLevel [Byte0]: 51
1760 10:51:56.942556 [Byte1]: 51
1761 10:51:56.946793
1762 10:51:56.946870 Set Vref, RX VrefLevel [Byte0]: 52
1763 10:51:56.950098 [Byte1]: 52
1764 10:51:56.954458
1765 10:51:56.954533 Set Vref, RX VrefLevel [Byte0]: 53
1766 10:51:56.957790 [Byte1]: 53
1767 10:51:56.961795
1768 10:51:56.961873 Set Vref, RX VrefLevel [Byte0]: 54
1769 10:51:56.965149 [Byte1]: 54
1770 10:51:56.969405
1771 10:51:56.969475 Set Vref, RX VrefLevel [Byte0]: 55
1772 10:51:56.972963 [Byte1]: 55
1773 10:51:56.977136
1774 10:51:56.977213 Set Vref, RX VrefLevel [Byte0]: 56
1775 10:51:56.980325 [Byte1]: 56
1776 10:51:56.984744
1777 10:51:56.984831 Set Vref, RX VrefLevel [Byte0]: 57
1778 10:51:56.987827 [Byte1]: 57
1779 10:51:56.992024
1780 10:51:56.992099 Set Vref, RX VrefLevel [Byte0]: 58
1781 10:51:56.995681 [Byte1]: 58
1782 10:51:56.999565
1783 10:51:56.999643 Set Vref, RX VrefLevel [Byte0]: 59
1784 10:51:57.003034 [Byte1]: 59
1785 10:51:57.007461
1786 10:51:57.007537 Set Vref, RX VrefLevel [Byte0]: 60
1787 10:51:57.010386 [Byte1]: 60
1788 10:51:57.015058
1789 10:51:57.015129 Set Vref, RX VrefLevel [Byte0]: 61
1790 10:51:57.017951 [Byte1]: 61
1791 10:51:57.022215
1792 10:51:57.022296 Set Vref, RX VrefLevel [Byte0]: 62
1793 10:51:57.025694 [Byte1]: 62
1794 10:51:57.029857
1795 10:51:57.029926 Set Vref, RX VrefLevel [Byte0]: 63
1796 10:51:57.033337 [Byte1]: 63
1797 10:51:57.037327
1798 10:51:57.037396 Set Vref, RX VrefLevel [Byte0]: 64
1799 10:51:57.040595 [Byte1]: 64
1800 10:51:57.044903
1801 10:51:57.048450 Set Vref, RX VrefLevel [Byte0]: 65
1802 10:51:57.051383 [Byte1]: 65
1803 10:51:57.051453
1804 10:51:57.054828 Set Vref, RX VrefLevel [Byte0]: 66
1805 10:51:57.057884 [Byte1]: 66
1806 10:51:57.057953
1807 10:51:57.061439 Set Vref, RX VrefLevel [Byte0]: 67
1808 10:51:57.064593 [Byte1]: 67
1809 10:51:57.064661
1810 10:51:57.068126 Set Vref, RX VrefLevel [Byte0]: 68
1811 10:51:57.071112 [Byte1]: 68
1812 10:51:57.075209
1813 10:51:57.075286 Set Vref, RX VrefLevel [Byte0]: 69
1814 10:51:57.081397 [Byte1]: 69
1815 10:51:57.081475
1816 10:51:57.084934 Set Vref, RX VrefLevel [Byte0]: 70
1817 10:51:57.088074 [Byte1]: 70
1818 10:51:57.088151
1819 10:51:57.091478 Set Vref, RX VrefLevel [Byte0]: 71
1820 10:51:57.094818 [Byte1]: 71
1821 10:51:57.094898
1822 10:51:57.098074 Set Vref, RX VrefLevel [Byte0]: 72
1823 10:51:57.101439 [Byte1]: 72
1824 10:51:57.105197
1825 10:51:57.105276 Set Vref, RX VrefLevel [Byte0]: 73
1826 10:51:57.108623 [Byte1]: 73
1827 10:51:57.113092
1828 10:51:57.113165 Final RX Vref Byte 0 = 53 to rank0
1829 10:51:57.116235 Final RX Vref Byte 1 = 62 to rank0
1830 10:51:57.119443 Final RX Vref Byte 0 = 53 to rank1
1831 10:51:57.122841 Final RX Vref Byte 1 = 62 to rank1==
1832 10:51:57.126279 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 10:51:57.132927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 10:51:57.133001 ==
1835 10:51:57.133063 DQS Delay:
1836 10:51:57.133135 DQS0 = 0, DQS1 = 0
1837 10:51:57.136112 DQM Delay:
1838 10:51:57.136186 DQM0 = 92, DQM1 = 83
1839 10:51:57.139507 DQ Delay:
1840 10:51:57.142988 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1841 10:51:57.146012 DQ4 =88, DQ5 =108, DQ6 =100, DQ7 =88
1842 10:51:57.149701 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1843 10:51:57.153009 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1844 10:51:57.153087
1845 10:51:57.153148
1846 10:51:57.159559 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1847 10:51:57.162463 CH1 RK0: MR19=606, MR18=2D4A
1848 10:51:57.169196 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1849 10:51:57.169271
1850 10:51:57.172703 ----->DramcWriteLeveling(PI) begin...
1851 10:51:57.172802 ==
1852 10:51:57.175947 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 10:51:57.179154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 10:51:57.179225 ==
1855 10:51:57.182397 Write leveling (Byte 0): 25 => 25
1856 10:51:57.185863 Write leveling (Byte 1): 28 => 28
1857 10:51:57.189202 DramcWriteLeveling(PI) end<-----
1858 10:51:57.189276
1859 10:51:57.189351 ==
1860 10:51:57.192547 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 10:51:57.195961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 10:51:57.196067 ==
1863 10:51:57.199030 [Gating] SW mode calibration
1864 10:51:57.205804 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 10:51:57.212653 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 10:51:57.215735 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 10:51:57.222340 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1868 10:51:57.225796 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:51:57.229258 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:51:57.232603 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:51:57.238910 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:51:57.242458 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:51:57.245515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:51:57.252412 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:51:57.255460 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:51:57.259100 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:51:57.265606 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:51:57.268995 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:51:57.272601 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:51:57.279121 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:51:57.282158 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:51:57.285607 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1883 10:51:57.292374 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1884 10:51:57.295711 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:51:57.298767 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:51:57.305445 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:51:57.308736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:51:57.312427 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:51:57.318829 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:51:57.322142 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:51:57.325377 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1892 10:51:57.332055 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1893 10:51:57.335667 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 10:51:57.339077 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 10:51:57.342010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 10:51:57.348797 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 10:51:57.352158 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 10:51:57.355605 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 10:51:57.362282 0 10 4 | B1->B0 | 2e2e 3131 | 0 1 | (1 1) (1 0)
1900 10:51:57.365366 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1901 10:51:57.368685 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:51:57.375284 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:51:57.378641 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:51:57.382220 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:51:57.388699 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:51:57.392150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:51:57.395446 0 11 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1908 10:51:57.402191 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1909 10:51:57.405373 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 10:51:57.408670 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 10:51:57.415292 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 10:51:57.418551 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 10:51:57.422180 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 10:51:57.428623 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 10:51:57.432297 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 10:51:57.435140 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1917 10:51:57.441944 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:51:57.445347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:51:57.448746 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:51:57.455338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:51:57.459074 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:51:57.462027 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:51:57.465078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:51:57.471812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:51:57.475226 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:51:57.478594 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:51:57.485249 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:51:57.488511 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:51:57.491982 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:51:57.498287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:51:57.501594 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 10:51:57.505083 Total UI for P1: 0, mck2ui 16
1933 10:51:57.508654 best dqsien dly found for B0: ( 0, 14, 2)
1934 10:51:57.511739 Total UI for P1: 0, mck2ui 16
1935 10:51:57.515137 best dqsien dly found for B1: ( 0, 14, 2)
1936 10:51:57.518250 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1937 10:51:57.521681 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1938 10:51:57.521754
1939 10:51:57.524988 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1940 10:51:57.528393 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1941 10:51:57.531838 [Gating] SW calibration Done
1942 10:51:57.531914 ==
1943 10:51:57.534947 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 10:51:57.538092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 10:51:57.541684 ==
1946 10:51:57.541758 RX Vref Scan: 0
1947 10:51:57.541819
1948 10:51:57.545157 RX Vref 0 -> 0, step: 1
1949 10:51:57.545225
1950 10:51:57.548169 RX Delay -130 -> 252, step: 16
1951 10:51:57.551489 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1952 10:51:57.554821 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1953 10:51:57.558087 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1954 10:51:57.561193 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1955 10:51:57.568032 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1956 10:51:57.571416 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1957 10:51:57.574569 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1958 10:51:57.578047 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1959 10:51:57.581104 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1960 10:51:57.587942 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1961 10:51:57.591597 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1962 10:51:57.594394 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1963 10:51:57.597966 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1964 10:51:57.601269 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1965 10:51:57.607900 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1966 10:51:57.611361 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1967 10:51:57.611436 ==
1968 10:51:57.614277 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 10:51:57.617925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 10:51:57.618009 ==
1971 10:51:57.620926 DQS Delay:
1972 10:51:57.621013 DQS0 = 0, DQS1 = 0
1973 10:51:57.624198 DQM Delay:
1974 10:51:57.624286 DQM0 = 90, DQM1 = 85
1975 10:51:57.624355 DQ Delay:
1976 10:51:57.627754 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1977 10:51:57.631398 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1978 10:51:57.634158 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1979 10:51:57.637856 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1980 10:51:57.637984
1981 10:51:57.638072
1982 10:51:57.641475 ==
1983 10:51:57.641674 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 10:51:57.647913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 10:51:57.648130 ==
1986 10:51:57.648251
1987 10:51:57.648358
1988 10:51:57.651122 TX Vref Scan disable
1989 10:51:57.651291 == TX Byte 0 ==
1990 10:51:57.654915 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1991 10:51:57.661186 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1992 10:51:57.661476 == TX Byte 1 ==
1993 10:51:57.664734 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 10:51:57.671565 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 10:51:57.671967 ==
1996 10:51:57.674807 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 10:51:57.677754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 10:51:57.678258 ==
1999 10:51:57.691457 TX Vref=22, minBit 13, minWin=27, winSum=452
2000 10:51:57.694349 TX Vref=24, minBit 13, minWin=27, winSum=453
2001 10:51:57.697707 TX Vref=26, minBit 8, minWin=28, winSum=458
2002 10:51:57.701610 TX Vref=28, minBit 8, minWin=28, winSum=462
2003 10:51:57.705268 TX Vref=30, minBit 8, minWin=28, winSum=461
2004 10:51:57.711021 TX Vref=32, minBit 9, minWin=27, winSum=458
2005 10:51:57.714205 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 28
2006 10:51:57.714673
2007 10:51:57.717392 Final TX Range 1 Vref 28
2008 10:51:57.717863
2009 10:51:57.718227 ==
2010 10:51:57.721014 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 10:51:57.724354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 10:51:57.727416 ==
2013 10:51:57.727880
2014 10:51:57.728243
2015 10:51:57.728578 TX Vref Scan disable
2016 10:51:57.731034 == TX Byte 0 ==
2017 10:51:57.734422 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2018 10:51:57.740934 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2019 10:51:57.741398 == TX Byte 1 ==
2020 10:51:57.744622 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2021 10:51:57.751275 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2022 10:51:57.751849
2023 10:51:57.752218 [DATLAT]
2024 10:51:57.752566 Freq=800, CH1 RK1
2025 10:51:57.752934
2026 10:51:57.754447 DATLAT Default: 0xa
2027 10:51:57.755016 0, 0xFFFF, sum = 0
2028 10:51:57.757602 1, 0xFFFF, sum = 0
2029 10:51:57.761270 2, 0xFFFF, sum = 0
2030 10:51:57.761845 3, 0xFFFF, sum = 0
2031 10:51:57.764723 4, 0xFFFF, sum = 0
2032 10:51:57.765324 5, 0xFFFF, sum = 0
2033 10:51:57.767485 6, 0xFFFF, sum = 0
2034 10:51:57.767961 7, 0xFFFF, sum = 0
2035 10:51:57.771204 8, 0xFFFF, sum = 0
2036 10:51:57.771816 9, 0x0, sum = 1
2037 10:51:57.774224 10, 0x0, sum = 2
2038 10:51:57.774803 11, 0x0, sum = 3
2039 10:51:57.777576 12, 0x0, sum = 4
2040 10:51:57.778052 best_step = 10
2041 10:51:57.778424
2042 10:51:57.778768 ==
2043 10:51:57.781243 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 10:51:57.784323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 10:51:57.784924 ==
2046 10:51:57.787742 RX Vref Scan: 0
2047 10:51:57.788314
2048 10:51:57.790765 RX Vref 0 -> 0, step: 1
2049 10:51:57.791337
2050 10:51:57.791707 RX Delay -79 -> 252, step: 8
2051 10:51:57.798109 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2052 10:51:57.801393 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2053 10:51:57.805017 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2054 10:51:57.808129 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2055 10:51:57.811685 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2056 10:51:57.817805 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2057 10:51:57.821192 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2058 10:51:57.824421 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2059 10:51:57.827541 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2060 10:51:57.831081 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2061 10:51:57.837692 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2062 10:51:57.841120 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2063 10:51:57.844025 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2064 10:51:57.847820 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2065 10:51:57.850831 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2066 10:51:57.857659 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2067 10:51:57.858237 ==
2068 10:51:57.860964 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 10:51:57.864367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 10:51:57.864980 ==
2071 10:51:57.865361 DQS Delay:
2072 10:51:57.867839 DQS0 = 0, DQS1 = 0
2073 10:51:57.868410 DQM Delay:
2074 10:51:57.871277 DQM0 = 92, DQM1 = 85
2075 10:51:57.871853 DQ Delay:
2076 10:51:57.874168 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2077 10:51:57.877487 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2078 10:51:57.880929 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =84
2079 10:51:57.884250 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2080 10:51:57.884843
2081 10:51:57.885221
2082 10:51:57.893961 [DQSOSCAuto] RK1, (LSB)MR18= 0x370b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps
2083 10:51:57.894533 CH1 RK1: MR19=606, MR18=370B
2084 10:51:57.900571 CH1_RK1: MR19=0x606, MR18=0x370B, DQSOSC=395, MR23=63, INC=94, DEC=63
2085 10:51:57.904349 [RxdqsGatingPostProcess] freq 800
2086 10:51:57.910298 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2087 10:51:57.913606 Pre-setting of DQS Precalculation
2088 10:51:57.917194 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2089 10:51:57.923362 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2090 10:51:57.933392 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2091 10:51:57.934049
2092 10:51:57.934434
2093 10:51:57.936685 [Calibration Summary] 1600 Mbps
2094 10:51:57.937208 CH 0, Rank 0
2095 10:51:57.939838 SW Impedance : PASS
2096 10:51:57.940401 DUTY Scan : NO K
2097 10:51:57.943712 ZQ Calibration : PASS
2098 10:51:57.946964 Jitter Meter : NO K
2099 10:51:57.947534 CBT Training : PASS
2100 10:51:57.949833 Write leveling : PASS
2101 10:51:57.950307 RX DQS gating : PASS
2102 10:51:57.953506 RX DQ/DQS(RDDQC) : PASS
2103 10:51:57.957240 TX DQ/DQS : PASS
2104 10:51:57.957805 RX DATLAT : PASS
2105 10:51:57.960206 RX DQ/DQS(Engine): PASS
2106 10:51:57.963433 TX OE : NO K
2107 10:51:57.963903 All Pass.
2108 10:51:57.964272
2109 10:51:57.964613 CH 0, Rank 1
2110 10:51:57.966771 SW Impedance : PASS
2111 10:51:57.970104 DUTY Scan : NO K
2112 10:51:57.970665 ZQ Calibration : PASS
2113 10:51:57.973379 Jitter Meter : NO K
2114 10:51:57.976496 CBT Training : PASS
2115 10:51:57.976998 Write leveling : PASS
2116 10:51:57.979467 RX DQS gating : PASS
2117 10:51:57.983521 RX DQ/DQS(RDDQC) : PASS
2118 10:51:57.984084 TX DQ/DQS : PASS
2119 10:51:57.986363 RX DATLAT : PASS
2120 10:51:57.989670 RX DQ/DQS(Engine): PASS
2121 10:51:57.990139 TX OE : NO K
2122 10:51:57.993306 All Pass.
2123 10:51:57.993919
2124 10:51:57.994304 CH 1, Rank 0
2125 10:51:57.996810 SW Impedance : PASS
2126 10:51:57.997375 DUTY Scan : NO K
2127 10:51:57.999801 ZQ Calibration : PASS
2128 10:51:58.003419 Jitter Meter : NO K
2129 10:51:58.003983 CBT Training : PASS
2130 10:51:58.006606 Write leveling : PASS
2131 10:51:58.009834 RX DQS gating : PASS
2132 10:51:58.010399 RX DQ/DQS(RDDQC) : PASS
2133 10:51:58.012689 TX DQ/DQS : PASS
2134 10:51:58.013178 RX DATLAT : PASS
2135 10:51:58.016219 RX DQ/DQS(Engine): PASS
2136 10:51:58.020004 TX OE : NO K
2137 10:51:58.020571 All Pass.
2138 10:51:58.021002
2139 10:51:58.021351 CH 1, Rank 1
2140 10:51:58.022885 SW Impedance : PASS
2141 10:51:58.026077 DUTY Scan : NO K
2142 10:51:58.026549 ZQ Calibration : PASS
2143 10:51:58.029438 Jitter Meter : NO K
2144 10:51:58.032970 CBT Training : PASS
2145 10:51:58.033436 Write leveling : PASS
2146 10:51:58.036487 RX DQS gating : PASS
2147 10:51:58.039391 RX DQ/DQS(RDDQC) : PASS
2148 10:51:58.039975 TX DQ/DQS : PASS
2149 10:51:58.042676 RX DATLAT : PASS
2150 10:51:58.045818 RX DQ/DQS(Engine): PASS
2151 10:51:58.046320 TX OE : NO K
2152 10:51:58.049457 All Pass.
2153 10:51:58.049926
2154 10:51:58.050297 DramC Write-DBI off
2155 10:51:58.052525 PER_BANK_REFRESH: Hybrid Mode
2156 10:51:58.053043 TX_TRACKING: ON
2157 10:51:58.056011 [GetDramInforAfterCalByMRR] Vendor 6.
2158 10:51:58.062384 [GetDramInforAfterCalByMRR] Revision 606.
2159 10:51:58.066070 [GetDramInforAfterCalByMRR] Revision 2 0.
2160 10:51:58.066767 MR0 0x3b3b
2161 10:51:58.067150 MR8 0x5151
2162 10:51:58.069228 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 10:51:58.072802
2164 10:51:58.073377 MR0 0x3b3b
2165 10:51:58.073748 MR8 0x5151
2166 10:51:58.075767 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 10:51:58.076328
2168 10:51:58.085699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2169 10:51:58.089315 [FAST_K] Save calibration result to emmc
2170 10:51:58.092169 [FAST_K] Save calibration result to emmc
2171 10:51:58.095370 dram_init: config_dvfs: 1
2172 10:51:58.099215 dramc_set_vcore_voltage set vcore to 662500
2173 10:51:58.102079 Read voltage for 1200, 2
2174 10:51:58.102528 Vio18 = 0
2175 10:51:58.102974 Vcore = 662500
2176 10:51:58.105170 Vdram = 0
2177 10:51:58.105640 Vddq = 0
2178 10:51:58.106044 Vmddr = 0
2179 10:51:58.112174 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2180 10:51:58.115285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2181 10:51:58.118315 MEM_TYPE=3, freq_sel=15
2182 10:51:58.121958 sv_algorithm_assistance_LP4_1600
2183 10:51:58.125256 ============ PULL DRAM RESETB DOWN ============
2184 10:51:58.128448 ========== PULL DRAM RESETB DOWN end =========
2185 10:51:58.135219 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2186 10:51:58.138136 ===================================
2187 10:51:58.141520 LPDDR4 DRAM CONFIGURATION
2188 10:51:58.145001 ===================================
2189 10:51:58.145433 EX_ROW_EN[0] = 0x0
2190 10:51:58.148155 EX_ROW_EN[1] = 0x0
2191 10:51:58.148576 LP4Y_EN = 0x0
2192 10:51:58.151333 WORK_FSP = 0x0
2193 10:51:58.151757 WL = 0x4
2194 10:51:58.154605 RL = 0x4
2195 10:51:58.154908 BL = 0x2
2196 10:51:58.157757 RPST = 0x0
2197 10:51:58.158050 RD_PRE = 0x0
2198 10:51:58.161419 WR_PRE = 0x1
2199 10:51:58.161647 WR_PST = 0x0
2200 10:51:58.164400 DBI_WR = 0x0
2201 10:51:58.167913 DBI_RD = 0x0
2202 10:51:58.168104 OTF = 0x1
2203 10:51:58.171127 ===================================
2204 10:51:58.174468 ===================================
2205 10:51:58.174651 ANA top config
2206 10:51:58.178028 ===================================
2207 10:51:58.180791 DLL_ASYNC_EN = 0
2208 10:51:58.184322 ALL_SLAVE_EN = 0
2209 10:51:58.187445 NEW_RANK_MODE = 1
2210 10:51:58.191417 DLL_IDLE_MODE = 1
2211 10:51:58.191603 LP45_APHY_COMB_EN = 1
2212 10:51:58.194198 TX_ODT_DIS = 1
2213 10:51:58.198106 NEW_8X_MODE = 1
2214 10:51:58.200736 ===================================
2215 10:51:58.203970 ===================================
2216 10:51:58.207191 data_rate = 2400
2217 10:51:58.211016 CKR = 1
2218 10:51:58.213911 DQ_P2S_RATIO = 8
2219 10:51:58.214095 ===================================
2220 10:51:58.217224 CA_P2S_RATIO = 8
2221 10:51:58.220453 DQ_CA_OPEN = 0
2222 10:51:58.224102 DQ_SEMI_OPEN = 0
2223 10:51:58.226843 CA_SEMI_OPEN = 0
2224 10:51:58.230131 CA_FULL_RATE = 0
2225 10:51:58.233862 DQ_CKDIV4_EN = 0
2226 10:51:58.233945 CA_CKDIV4_EN = 0
2227 10:51:58.236816 CA_PREDIV_EN = 0
2228 10:51:58.240208 PH8_DLY = 17
2229 10:51:58.243662 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2230 10:51:58.247078 DQ_AAMCK_DIV = 4
2231 10:51:58.250277 CA_AAMCK_DIV = 4
2232 10:51:58.250361 CA_ADMCK_DIV = 4
2233 10:51:58.253648 DQ_TRACK_CA_EN = 0
2234 10:51:58.256770 CA_PICK = 1200
2235 10:51:58.260025 CA_MCKIO = 1200
2236 10:51:58.263439 MCKIO_SEMI = 0
2237 10:51:58.266717 PLL_FREQ = 2366
2238 10:51:58.270005 DQ_UI_PI_RATIO = 32
2239 10:51:58.270080 CA_UI_PI_RATIO = 0
2240 10:51:58.273217 ===================================
2241 10:51:58.276650 ===================================
2242 10:51:58.279944 memory_type:LPDDR4
2243 10:51:58.283327 GP_NUM : 10
2244 10:51:58.283398 SRAM_EN : 1
2245 10:51:58.286663 MD32_EN : 0
2246 10:51:58.290259 ===================================
2247 10:51:58.293247 [ANA_INIT] >>>>>>>>>>>>>>
2248 10:51:58.296661 <<<<<< [CONFIGURE PHASE]: ANA_TX
2249 10:51:58.300131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2250 10:51:58.303361 ===================================
2251 10:51:58.303434 data_rate = 2400,PCW = 0X5b00
2252 10:51:58.306378 ===================================
2253 10:51:58.309624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2254 10:51:58.316660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 10:51:58.323025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 10:51:58.326339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2257 10:51:58.330033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2258 10:51:58.333308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2259 10:51:58.336036 [ANA_INIT] flow start
2260 10:51:58.339441 [ANA_INIT] PLL >>>>>>>>
2261 10:51:58.339512 [ANA_INIT] PLL <<<<<<<<
2262 10:51:58.343025 [ANA_INIT] MIDPI >>>>>>>>
2263 10:51:58.346297 [ANA_INIT] MIDPI <<<<<<<<
2264 10:51:58.346366 [ANA_INIT] DLL >>>>>>>>
2265 10:51:58.349484 [ANA_INIT] DLL <<<<<<<<
2266 10:51:58.352761 [ANA_INIT] flow end
2267 10:51:58.356168 ============ LP4 DIFF to SE enter ============
2268 10:51:58.359323 ============ LP4 DIFF to SE exit ============
2269 10:51:58.363087 [ANA_INIT] <<<<<<<<<<<<<
2270 10:51:58.366413 [Flow] Enable top DCM control >>>>>
2271 10:51:58.369407 [Flow] Enable top DCM control <<<<<
2272 10:51:58.372679 Enable DLL master slave shuffle
2273 10:51:58.375911 ==============================================================
2274 10:51:58.379469 Gating Mode config
2275 10:51:58.385983 ==============================================================
2276 10:51:58.386055 Config description:
2277 10:51:58.396073 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2278 10:51:58.402629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2279 10:51:58.409028 SELPH_MODE 0: By rank 1: By Phase
2280 10:51:58.412208 ==============================================================
2281 10:51:58.415676 GAT_TRACK_EN = 1
2282 10:51:58.419158 RX_GATING_MODE = 2
2283 10:51:58.422283 RX_GATING_TRACK_MODE = 2
2284 10:51:58.425531 SELPH_MODE = 1
2285 10:51:58.428962 PICG_EARLY_EN = 1
2286 10:51:58.432213 VALID_LAT_VALUE = 1
2287 10:51:58.435474 ==============================================================
2288 10:51:58.438628 Enter into Gating configuration >>>>
2289 10:51:58.442073 Exit from Gating configuration <<<<
2290 10:51:58.445574 Enter into DVFS_PRE_config >>>>>
2291 10:51:58.458812 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2292 10:51:58.462197 Exit from DVFS_PRE_config <<<<<
2293 10:51:58.462282 Enter into PICG configuration >>>>
2294 10:51:58.465593 Exit from PICG configuration <<<<
2295 10:51:58.468843 [RX_INPUT] configuration >>>>>
2296 10:51:58.472279 [RX_INPUT] configuration <<<<<
2297 10:51:58.478811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2298 10:51:58.482024 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2299 10:51:58.488568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 10:51:58.494875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 10:51:58.501597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 10:51:58.508331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 10:51:58.511592 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2304 10:51:58.514995 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2305 10:51:58.521641 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2306 10:51:58.524952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2307 10:51:58.528060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2308 10:51:58.531541 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 10:51:58.534783 ===================================
2310 10:51:58.538401 LPDDR4 DRAM CONFIGURATION
2311 10:51:58.541472 ===================================
2312 10:51:58.544686 EX_ROW_EN[0] = 0x0
2313 10:51:58.544793 EX_ROW_EN[1] = 0x0
2314 10:51:58.548041 LP4Y_EN = 0x0
2315 10:51:58.548137 WORK_FSP = 0x0
2316 10:51:58.551535 WL = 0x4
2317 10:51:58.551632 RL = 0x4
2318 10:51:58.554820 BL = 0x2
2319 10:51:58.554916 RPST = 0x0
2320 10:51:58.557968 RD_PRE = 0x0
2321 10:51:58.558113 WR_PRE = 0x1
2322 10:51:58.561479 WR_PST = 0x0
2323 10:51:58.561576 DBI_WR = 0x0
2324 10:51:58.564602 DBI_RD = 0x0
2325 10:51:58.564700 OTF = 0x1
2326 10:51:58.571418 ===================================
2327 10:51:58.574632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2328 10:51:58.577655 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2329 10:51:58.581188 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 10:51:58.584593 ===================================
2331 10:51:58.588182 LPDDR4 DRAM CONFIGURATION
2332 10:51:58.591222 ===================================
2333 10:51:58.594335 EX_ROW_EN[0] = 0x10
2334 10:51:58.594433 EX_ROW_EN[1] = 0x0
2335 10:51:58.597809 LP4Y_EN = 0x0
2336 10:51:58.597907 WORK_FSP = 0x0
2337 10:51:58.601051 WL = 0x4
2338 10:51:58.601148 RL = 0x4
2339 10:51:58.604644 BL = 0x2
2340 10:51:58.604739 RPST = 0x0
2341 10:51:58.607822 RD_PRE = 0x0
2342 10:51:58.607919 WR_PRE = 0x1
2343 10:51:58.611141 WR_PST = 0x0
2344 10:51:58.611225 DBI_WR = 0x0
2345 10:51:58.614237 DBI_RD = 0x0
2346 10:51:58.614322 OTF = 0x1
2347 10:51:58.617804 ===================================
2348 10:51:58.624242 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2349 10:51:58.624328 ==
2350 10:51:58.627763 Dram Type= 6, Freq= 0, CH_0, rank 0
2351 10:51:58.634071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2352 10:51:58.634157 ==
2353 10:51:58.634223 [Duty_Offset_Calibration]
2354 10:51:58.637510 B0:2 B1:0 CA:1
2355 10:51:58.637594
2356 10:51:58.640976 [DutyScan_Calibration_Flow] k_type=0
2357 10:51:58.648911
2358 10:51:58.648995 ==CLK 0==
2359 10:51:58.652398 Final CLK duty delay cell = -4
2360 10:51:58.656362 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2361 10:51:58.658877 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2362 10:51:58.662325 [-4] AVG Duty = 4953%(X100)
2363 10:51:58.662407
2364 10:51:58.665574 CH0 CLK Duty spec in!! Max-Min= 156%
2365 10:51:58.669395 [DutyScan_Calibration_Flow] ====Done====
2366 10:51:58.669476
2367 10:51:58.672042 [DutyScan_Calibration_Flow] k_type=1
2368 10:51:58.687842
2369 10:51:58.687923 ==DQS 0 ==
2370 10:51:58.691224 Final DQS duty delay cell = 0
2371 10:51:58.694841 [0] MAX Duty = 5187%(X100), DQS PI = 30
2372 10:51:58.697759 [0] MIN Duty = 4938%(X100), DQS PI = 0
2373 10:51:58.697870 [0] AVG Duty = 5062%(X100)
2374 10:51:58.701167
2375 10:51:58.701268 ==DQS 1 ==
2376 10:51:58.704708 Final DQS duty delay cell = -4
2377 10:51:58.707845 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2378 10:51:58.710978 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2379 10:51:58.714478 [-4] AVG Duty = 5031%(X100)
2380 10:51:58.714588
2381 10:51:58.717825 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2382 10:51:58.717926
2383 10:51:58.720949 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2384 10:51:58.724552 [DutyScan_Calibration_Flow] ====Done====
2385 10:51:58.724651
2386 10:51:58.727596 [DutyScan_Calibration_Flow] k_type=3
2387 10:51:58.744066
2388 10:51:58.744175 ==DQM 0 ==
2389 10:51:58.747190 Final DQM duty delay cell = 0
2390 10:51:58.750693 [0] MAX Duty = 5062%(X100), DQS PI = 24
2391 10:51:58.753918 [0] MIN Duty = 4844%(X100), DQS PI = 2
2392 10:51:58.754018 [0] AVG Duty = 4953%(X100)
2393 10:51:58.756878
2394 10:51:58.756956 ==DQM 1 ==
2395 10:51:58.760480 Final DQM duty delay cell = -4
2396 10:51:58.763515 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2397 10:51:58.766896 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2398 10:51:58.770054 [-4] AVG Duty = 4906%(X100)
2399 10:51:58.770153
2400 10:51:58.773804 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2401 10:51:58.773917
2402 10:51:58.776930 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2403 10:51:58.780341 [DutyScan_Calibration_Flow] ====Done====
2404 10:51:58.780459
2405 10:51:58.783404 [DutyScan_Calibration_Flow] k_type=2
2406 10:51:58.799941
2407 10:51:58.800053 ==DQ 0 ==
2408 10:51:58.803165 Final DQ duty delay cell = -4
2409 10:51:58.806358 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2410 10:51:58.809766 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2411 10:51:58.812929 [-4] AVG Duty = 4969%(X100)
2412 10:51:58.813006
2413 10:51:58.813083 ==DQ 1 ==
2414 10:51:58.816300 Final DQ duty delay cell = 0
2415 10:51:58.819992 [0] MAX Duty = 4938%(X100), DQS PI = 4
2416 10:51:58.822911 [0] MIN Duty = 4907%(X100), DQS PI = 0
2417 10:51:58.823032 [0] AVG Duty = 4922%(X100)
2418 10:51:58.826219
2419 10:51:58.829540 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2420 10:51:58.829643
2421 10:51:58.832797 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2422 10:51:58.836168 [DutyScan_Calibration_Flow] ====Done====
2423 10:51:58.836275 ==
2424 10:51:58.839495 Dram Type= 6, Freq= 0, CH_1, rank 0
2425 10:51:58.843135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2426 10:51:58.843235 ==
2427 10:51:58.846555 [Duty_Offset_Calibration]
2428 10:51:58.846639 B0:0 B1:-1 CA:2
2429 10:51:58.846704
2430 10:51:58.849639 [DutyScan_Calibration_Flow] k_type=0
2431 10:51:58.860071
2432 10:51:58.860178 ==CLK 0==
2433 10:51:58.863598 Final CLK duty delay cell = 0
2434 10:51:58.866538 [0] MAX Duty = 5156%(X100), DQS PI = 10
2435 10:51:58.869821 [0] MIN Duty = 4969%(X100), DQS PI = 44
2436 10:51:58.869938 [0] AVG Duty = 5062%(X100)
2437 10:51:58.873154
2438 10:51:58.876547 CH1 CLK Duty spec in!! Max-Min= 187%
2439 10:51:58.880045 [DutyScan_Calibration_Flow] ====Done====
2440 10:51:58.880140
2441 10:51:58.883209 [DutyScan_Calibration_Flow] k_type=1
2442 10:51:58.899379
2443 10:51:58.899500 ==DQS 0 ==
2444 10:51:58.902430 Final DQS duty delay cell = 0
2445 10:51:58.905928 [0] MAX Duty = 5093%(X100), DQS PI = 26
2446 10:51:58.909017 [0] MIN Duty = 4969%(X100), DQS PI = 0
2447 10:51:58.912318 [0] AVG Duty = 5031%(X100)
2448 10:51:58.912417
2449 10:51:58.912518 ==DQS 1 ==
2450 10:51:58.915826 Final DQS duty delay cell = 0
2451 10:51:58.919267 [0] MAX Duty = 5156%(X100), DQS PI = 0
2452 10:51:58.922477 [0] MIN Duty = 4844%(X100), DQS PI = 36
2453 10:51:58.922552 [0] AVG Duty = 5000%(X100)
2454 10:51:58.926137
2455 10:51:58.929485 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2456 10:51:58.929564
2457 10:51:58.932703 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2458 10:51:58.935781 [DutyScan_Calibration_Flow] ====Done====
2459 10:51:58.935855
2460 10:51:58.938953 [DutyScan_Calibration_Flow] k_type=3
2461 10:51:58.955790
2462 10:51:58.955903 ==DQM 0 ==
2463 10:51:58.959265 Final DQM duty delay cell = 4
2464 10:51:58.962227 [4] MAX Duty = 5093%(X100), DQS PI = 6
2465 10:51:58.965573 [4] MIN Duty = 4938%(X100), DQS PI = 48
2466 10:51:58.969372 [4] AVG Duty = 5015%(X100)
2467 10:51:58.969446
2468 10:51:58.969531 ==DQM 1 ==
2469 10:51:58.972442 Final DQM duty delay cell = -4
2470 10:51:58.975590 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2471 10:51:58.978995 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2472 10:51:58.982467 [-4] AVG Duty = 4860%(X100)
2473 10:51:58.982577
2474 10:51:58.985476 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2475 10:51:58.985550
2476 10:51:58.989044 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2477 10:51:58.992011 [DutyScan_Calibration_Flow] ====Done====
2478 10:51:58.992083
2479 10:51:58.995569 [DutyScan_Calibration_Flow] k_type=2
2480 10:51:59.012636
2481 10:51:59.012724 ==DQ 0 ==
2482 10:51:59.015893 Final DQ duty delay cell = 0
2483 10:51:59.019298 [0] MAX Duty = 5062%(X100), DQS PI = 20
2484 10:51:59.022324 [0] MIN Duty = 4938%(X100), DQS PI = 44
2485 10:51:59.022423 [0] AVG Duty = 5000%(X100)
2486 10:51:59.025753
2487 10:51:59.025843 ==DQ 1 ==
2488 10:51:59.029272 Final DQ duty delay cell = 0
2489 10:51:59.032728 [0] MAX Duty = 5031%(X100), DQS PI = 2
2490 10:51:59.035984 [0] MIN Duty = 4813%(X100), DQS PI = 36
2491 10:51:59.036055 [0] AVG Duty = 4922%(X100)
2492 10:51:59.036116
2493 10:51:59.039664 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2494 10:51:59.042588
2495 10:51:59.045841 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2496 10:51:59.049274 [DutyScan_Calibration_Flow] ====Done====
2497 10:51:59.052615 nWR fixed to 30
2498 10:51:59.052701 [ModeRegInit_LP4] CH0 RK0
2499 10:51:59.055684 [ModeRegInit_LP4] CH0 RK1
2500 10:51:59.059030 [ModeRegInit_LP4] CH1 RK0
2501 10:51:59.059099 [ModeRegInit_LP4] CH1 RK1
2502 10:51:59.062509 match AC timing 7
2503 10:51:59.065613 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2504 10:51:59.072392 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2505 10:51:59.075820 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2506 10:51:59.079009 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2507 10:51:59.085864 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2508 10:51:59.085942 ==
2509 10:51:59.089289 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 10:51:59.092443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 10:51:59.092514 ==
2512 10:51:59.099188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2513 10:51:59.105787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2514 10:51:59.112528 [CA 0] Center 38 (7~69) winsize 63
2515 10:51:59.115967 [CA 1] Center 38 (8~69) winsize 62
2516 10:51:59.119392 [CA 2] Center 35 (5~66) winsize 62
2517 10:51:59.122703 [CA 3] Center 35 (4~66) winsize 63
2518 10:51:59.125869 [CA 4] Center 34 (4~65) winsize 62
2519 10:51:59.129124 [CA 5] Center 33 (3~64) winsize 62
2520 10:51:59.129190
2521 10:51:59.132555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2522 10:51:59.132619
2523 10:51:59.136509 [CATrainingPosCal] consider 1 rank data
2524 10:51:59.139239 u2DelayCellTimex100 = 270/100 ps
2525 10:51:59.142811 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2526 10:51:59.146052 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2527 10:51:59.152376 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 10:51:59.155791 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2529 10:51:59.159314 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2530 10:51:59.162438 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2531 10:51:59.162511
2532 10:51:59.165812 CA PerBit enable=1, Macro0, CA PI delay=33
2533 10:51:59.165882
2534 10:51:59.168990 [CBTSetCACLKResult] CA Dly = 33
2535 10:51:59.169063 CS Dly: 6 (0~37)
2536 10:51:59.172334 ==
2537 10:51:59.175635 Dram Type= 6, Freq= 0, CH_0, rank 1
2538 10:51:59.178826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 10:51:59.178908 ==
2540 10:51:59.182361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2541 10:51:59.188758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2542 10:51:59.198334 [CA 0] Center 39 (8~70) winsize 63
2543 10:51:59.201594 [CA 1] Center 38 (8~69) winsize 62
2544 10:51:59.204915 [CA 2] Center 35 (5~66) winsize 62
2545 10:51:59.208485 [CA 3] Center 35 (5~66) winsize 62
2546 10:51:59.211514 [CA 4] Center 34 (4~65) winsize 62
2547 10:51:59.214838 [CA 5] Center 34 (4~64) winsize 61
2548 10:51:59.214913
2549 10:51:59.218390 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2550 10:51:59.218465
2551 10:51:59.221480 [CATrainingPosCal] consider 2 rank data
2552 10:51:59.224841 u2DelayCellTimex100 = 270/100 ps
2553 10:51:59.228409 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2554 10:51:59.231495 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2555 10:51:59.237980 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2556 10:51:59.241356 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2557 10:51:59.244868 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2558 10:51:59.248086 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2559 10:51:59.248158
2560 10:51:59.251510 CA PerBit enable=1, Macro0, CA PI delay=34
2561 10:51:59.251584
2562 10:51:59.255372 [CBTSetCACLKResult] CA Dly = 34
2563 10:51:59.255443 CS Dly: 7 (0~39)
2564 10:51:59.255504
2565 10:51:59.258324 ----->DramcWriteLeveling(PI) begin...
2566 10:51:59.261335 ==
2567 10:51:59.264926 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 10:51:59.268104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 10:51:59.268177 ==
2570 10:51:59.271477 Write leveling (Byte 0): 35 => 35
2571 10:51:59.274698 Write leveling (Byte 1): 30 => 30
2572 10:51:59.278041 DramcWriteLeveling(PI) end<-----
2573 10:51:59.278110
2574 10:51:59.278171 ==
2575 10:51:59.281631 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 10:51:59.284845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 10:51:59.284917 ==
2578 10:51:59.288180 [Gating] SW mode calibration
2579 10:51:59.294557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2580 10:51:59.301592 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2581 10:51:59.304493 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2582 10:51:59.308017 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2583 10:51:59.314254 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 10:51:59.317977 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 10:51:59.321060 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 10:51:59.324549 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 10:51:59.331291 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2588 10:51:59.334285 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2589 10:51:59.340756 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
2590 10:51:59.344293 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 10:51:59.347297 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 10:51:59.353794 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 10:51:59.357148 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 10:51:59.360606 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 10:51:59.367154 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2596 10:51:59.370438 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2597 10:51:59.374025 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
2598 10:51:59.377159 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 10:51:59.383812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 10:51:59.386978 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 10:51:59.390479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 10:51:59.396998 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 10:51:59.400310 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 10:51:59.403936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2605 10:51:59.410203 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2606 10:51:59.413639 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 10:51:59.416937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 10:51:59.423762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 10:51:59.427004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:51:59.430449 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:51:59.436928 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:51:59.440462 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:51:59.443722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:51:59.450186 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:51:59.453453 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:51:59.456696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:51:59.463759 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:51:59.466738 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:51:59.470019 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 10:51:59.476707 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 10:51:59.480033 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 10:51:59.483595 Total UI for P1: 0, mck2ui 16
2623 10:51:59.486807 best dqsien dly found for B0: ( 1, 3, 26)
2624 10:51:59.489758 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 10:51:59.493324 Total UI for P1: 0, mck2ui 16
2626 10:51:59.496466 best dqsien dly found for B1: ( 1, 4, 0)
2627 10:51:59.500002 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2628 10:51:59.503202 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2629 10:51:59.503278
2630 10:51:59.506425 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2631 10:51:59.513381 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2632 10:51:59.513455 [Gating] SW calibration Done
2633 10:51:59.513521 ==
2634 10:51:59.516291 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 10:51:59.523090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 10:51:59.523168 ==
2637 10:51:59.523236 RX Vref Scan: 0
2638 10:51:59.523295
2639 10:51:59.526603 RX Vref 0 -> 0, step: 1
2640 10:51:59.526674
2641 10:51:59.529987 RX Delay -40 -> 252, step: 8
2642 10:51:59.533063 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2643 10:51:59.536530 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2644 10:51:59.539942 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2645 10:51:59.546326 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2646 10:51:59.549744 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2647 10:51:59.553170 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2648 10:51:59.556425 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2649 10:51:59.559718 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2650 10:51:59.566434 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2651 10:51:59.569526 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2652 10:51:59.572839 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2653 10:51:59.576543 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2654 10:51:59.579644 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2655 10:51:59.586254 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2656 10:51:59.589327 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2657 10:51:59.592464 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2658 10:51:59.592547 ==
2659 10:51:59.595969 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 10:51:59.599489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 10:51:59.602606 ==
2662 10:51:59.602689 DQS Delay:
2663 10:51:59.602754 DQS0 = 0, DQS1 = 0
2664 10:51:59.605840 DQM Delay:
2665 10:51:59.605923 DQM0 = 123, DQM1 = 110
2666 10:51:59.609195 DQ Delay:
2667 10:51:59.612646 DQ0 =119, DQ1 =127, DQ2 =119, DQ3 =119
2668 10:51:59.615877 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2669 10:51:59.619283 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2670 10:51:59.622991 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2671 10:51:59.623074
2672 10:51:59.623139
2673 10:51:59.623198 ==
2674 10:51:59.625963 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 10:51:59.629336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 10:51:59.629420 ==
2677 10:51:59.629485
2678 10:51:59.629545
2679 10:51:59.632749 TX Vref Scan disable
2680 10:51:59.635796 == TX Byte 0 ==
2681 10:51:59.639355 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2682 10:51:59.642478 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2683 10:51:59.646028 == TX Byte 1 ==
2684 10:51:59.649047 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2685 10:51:59.652637 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2686 10:51:59.652720 ==
2687 10:51:59.655915 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 10:51:59.662451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 10:51:59.662534 ==
2690 10:51:59.672806 TX Vref=22, minBit 7, minWin=22, winSum=400
2691 10:51:59.676121 TX Vref=24, minBit 0, minWin=24, winSum=408
2692 10:51:59.679354 TX Vref=26, minBit 0, minWin=25, winSum=413
2693 10:51:59.682880 TX Vref=28, minBit 0, minWin=25, winSum=418
2694 10:51:59.686015 TX Vref=30, minBit 1, minWin=25, winSum=416
2695 10:51:59.692932 TX Vref=32, minBit 1, minWin=25, winSum=415
2696 10:51:59.696030 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
2697 10:51:59.696114
2698 10:51:59.699627 Final TX Range 1 Vref 28
2699 10:51:59.699710
2700 10:51:59.699776 ==
2701 10:51:59.702633 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 10:51:59.706097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 10:51:59.709105 ==
2704 10:51:59.709187
2705 10:51:59.709252
2706 10:51:59.709311 TX Vref Scan disable
2707 10:51:59.712756 == TX Byte 0 ==
2708 10:51:59.715904 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2709 10:51:59.722473 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2710 10:51:59.722557 == TX Byte 1 ==
2711 10:51:59.725868 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2712 10:51:59.732551 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2713 10:51:59.732635
2714 10:51:59.732700 [DATLAT]
2715 10:51:59.732761 Freq=1200, CH0 RK0
2716 10:51:59.732887
2717 10:51:59.735699 DATLAT Default: 0xd
2718 10:51:59.739129 0, 0xFFFF, sum = 0
2719 10:51:59.739213 1, 0xFFFF, sum = 0
2720 10:51:59.742358 2, 0xFFFF, sum = 0
2721 10:51:59.742442 3, 0xFFFF, sum = 0
2722 10:51:59.745905 4, 0xFFFF, sum = 0
2723 10:51:59.745989 5, 0xFFFF, sum = 0
2724 10:51:59.748893 6, 0xFFFF, sum = 0
2725 10:51:59.748978 7, 0xFFFF, sum = 0
2726 10:51:59.752338 8, 0xFFFF, sum = 0
2727 10:51:59.752422 9, 0xFFFF, sum = 0
2728 10:51:59.755699 10, 0xFFFF, sum = 0
2729 10:51:59.755783 11, 0xFFFF, sum = 0
2730 10:51:59.758657 12, 0x0, sum = 1
2731 10:51:59.758741 13, 0x0, sum = 2
2732 10:51:59.762201 14, 0x0, sum = 3
2733 10:51:59.762285 15, 0x0, sum = 4
2734 10:51:59.765474 best_step = 13
2735 10:51:59.765557
2736 10:51:59.765622 ==
2737 10:51:59.768723 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 10:51:59.772194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 10:51:59.772278 ==
2740 10:51:59.775599 RX Vref Scan: 1
2741 10:51:59.775681
2742 10:51:59.775746 Set Vref Range= 32 -> 127
2743 10:51:59.775806
2744 10:51:59.778597 RX Vref 32 -> 127, step: 1
2745 10:51:59.778680
2746 10:51:59.782095 RX Delay -13 -> 252, step: 4
2747 10:51:59.782178
2748 10:51:59.785246 Set Vref, RX VrefLevel [Byte0]: 32
2749 10:51:59.788680 [Byte1]: 32
2750 10:51:59.788786
2751 10:51:59.791883 Set Vref, RX VrefLevel [Byte0]: 33
2752 10:51:59.795231 [Byte1]: 33
2753 10:51:59.799092
2754 10:51:59.799174 Set Vref, RX VrefLevel [Byte0]: 34
2755 10:51:59.802642 [Byte1]: 34
2756 10:51:59.807082
2757 10:51:59.807164 Set Vref, RX VrefLevel [Byte0]: 35
2758 10:51:59.810447 [Byte1]: 35
2759 10:51:59.814931
2760 10:51:59.815015 Set Vref, RX VrefLevel [Byte0]: 36
2761 10:51:59.818299 [Byte1]: 36
2762 10:51:59.822895
2763 10:51:59.822978 Set Vref, RX VrefLevel [Byte0]: 37
2764 10:51:59.825967 [Byte1]: 37
2765 10:51:59.830905
2766 10:51:59.830987 Set Vref, RX VrefLevel [Byte0]: 38
2767 10:51:59.833847 [Byte1]: 38
2768 10:51:59.838696
2769 10:51:59.838778 Set Vref, RX VrefLevel [Byte0]: 39
2770 10:51:59.841812 [Byte1]: 39
2771 10:51:59.846485
2772 10:51:59.846567 Set Vref, RX VrefLevel [Byte0]: 40
2773 10:51:59.849748 [Byte1]: 40
2774 10:51:59.854381
2775 10:51:59.854463 Set Vref, RX VrefLevel [Byte0]: 41
2776 10:51:59.857886 [Byte1]: 41
2777 10:51:59.862078
2778 10:51:59.862161 Set Vref, RX VrefLevel [Byte0]: 42
2779 10:51:59.865708 [Byte1]: 42
2780 10:51:59.870299
2781 10:51:59.870382 Set Vref, RX VrefLevel [Byte0]: 43
2782 10:51:59.873300 [Byte1]: 43
2783 10:51:59.878305
2784 10:51:59.878388 Set Vref, RX VrefLevel [Byte0]: 44
2785 10:51:59.881546 [Byte1]: 44
2786 10:51:59.885794
2787 10:51:59.885877 Set Vref, RX VrefLevel [Byte0]: 45
2788 10:51:59.889368 [Byte1]: 45
2789 10:51:59.893930
2790 10:51:59.894012 Set Vref, RX VrefLevel [Byte0]: 46
2791 10:51:59.897439 [Byte1]: 46
2792 10:51:59.901600
2793 10:51:59.901683 Set Vref, RX VrefLevel [Byte0]: 47
2794 10:51:59.905023 [Byte1]: 47
2795 10:51:59.909518
2796 10:51:59.909600 Set Vref, RX VrefLevel [Byte0]: 48
2797 10:51:59.913039 [Byte1]: 48
2798 10:51:59.917348
2799 10:51:59.917432 Set Vref, RX VrefLevel [Byte0]: 49
2800 10:51:59.920723 [Byte1]: 49
2801 10:51:59.925223
2802 10:51:59.925306 Set Vref, RX VrefLevel [Byte0]: 50
2803 10:51:59.928644 [Byte1]: 50
2804 10:51:59.933048
2805 10:51:59.933134 Set Vref, RX VrefLevel [Byte0]: 51
2806 10:51:59.936654 [Byte1]: 51
2807 10:51:59.941443
2808 10:51:59.941526 Set Vref, RX VrefLevel [Byte0]: 52
2809 10:51:59.944447 [Byte1]: 52
2810 10:51:59.948927
2811 10:51:59.949009 Set Vref, RX VrefLevel [Byte0]: 53
2812 10:51:59.952395 [Byte1]: 53
2813 10:51:59.957102
2814 10:51:59.957184 Set Vref, RX VrefLevel [Byte0]: 54
2815 10:51:59.960377 [Byte1]: 54
2816 10:51:59.964675
2817 10:51:59.964757 Set Vref, RX VrefLevel [Byte0]: 55
2818 10:51:59.968082 [Byte1]: 55
2819 10:51:59.972730
2820 10:51:59.972821 Set Vref, RX VrefLevel [Byte0]: 56
2821 10:51:59.976336 [Byte1]: 56
2822 10:51:59.980470
2823 10:51:59.980553 Set Vref, RX VrefLevel [Byte0]: 57
2824 10:51:59.983740 [Byte1]: 57
2825 10:51:59.988407
2826 10:51:59.988489 Set Vref, RX VrefLevel [Byte0]: 58
2827 10:51:59.991778 [Byte1]: 58
2828 10:51:59.996229
2829 10:51:59.996312 Set Vref, RX VrefLevel [Byte0]: 59
2830 10:51:59.999673 [Byte1]: 59
2831 10:52:00.004468
2832 10:52:00.004551 Set Vref, RX VrefLevel [Byte0]: 60
2833 10:52:00.007747 [Byte1]: 60
2834 10:52:00.012921
2835 10:52:00.013024 Set Vref, RX VrefLevel [Byte0]: 61
2836 10:52:00.015403 [Byte1]: 61
2837 10:52:00.019896
2838 10:52:00.019980 Set Vref, RX VrefLevel [Byte0]: 62
2839 10:52:00.026621 [Byte1]: 62
2840 10:52:00.026709
2841 10:52:00.029577 Set Vref, RX VrefLevel [Byte0]: 63
2842 10:52:00.033039 [Byte1]: 63
2843 10:52:00.033126
2844 10:52:00.036565 Set Vref, RX VrefLevel [Byte0]: 64
2845 10:52:00.039469 [Byte1]: 64
2846 10:52:00.044076
2847 10:52:00.044158 Set Vref, RX VrefLevel [Byte0]: 65
2848 10:52:00.047204 [Byte1]: 65
2849 10:52:00.051724
2850 10:52:00.051807 Set Vref, RX VrefLevel [Byte0]: 66
2851 10:52:00.055231 [Byte1]: 66
2852 10:52:00.059427
2853 10:52:00.059509 Set Vref, RX VrefLevel [Byte0]: 67
2854 10:52:00.062972 [Byte1]: 67
2855 10:52:00.067383
2856 10:52:00.067466 Set Vref, RX VrefLevel [Byte0]: 68
2857 10:52:00.070484 [Byte1]: 68
2858 10:52:00.075465
2859 10:52:00.075548 Set Vref, RX VrefLevel [Byte0]: 69
2860 10:52:00.078731 [Byte1]: 69
2861 10:52:00.083176
2862 10:52:00.083259 Set Vref, RX VrefLevel [Byte0]: 70
2863 10:52:00.086667 [Byte1]: 70
2864 10:52:00.091047
2865 10:52:00.091130 Set Vref, RX VrefLevel [Byte0]: 71
2866 10:52:00.094370 [Byte1]: 71
2867 10:52:00.098794
2868 10:52:00.098877 Set Vref, RX VrefLevel [Byte0]: 72
2869 10:52:00.102100 [Byte1]: 72
2870 10:52:00.107070
2871 10:52:00.107153 Final RX Vref Byte 0 = 59 to rank0
2872 10:52:00.110361 Final RX Vref Byte 1 = 49 to rank0
2873 10:52:00.113570 Final RX Vref Byte 0 = 59 to rank1
2874 10:52:00.117216 Final RX Vref Byte 1 = 49 to rank1==
2875 10:52:00.120278 Dram Type= 6, Freq= 0, CH_0, rank 0
2876 10:52:00.127032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 10:52:00.127119 ==
2878 10:52:00.127185 DQS Delay:
2879 10:52:00.127251 DQS0 = 0, DQS1 = 0
2880 10:52:00.130203 DQM Delay:
2881 10:52:00.130275 DQM0 = 122, DQM1 = 109
2882 10:52:00.133341 DQ Delay:
2883 10:52:00.136762 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2884 10:52:00.140553 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2885 10:52:00.143470 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2886 10:52:00.146531 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2887 10:52:00.146620
2888 10:52:00.146687
2889 10:52:00.153396 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2890 10:52:00.156923 CH0 RK0: MR19=404, MR18=906
2891 10:52:00.163369 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2892 10:52:00.163458
2893 10:52:00.166822 ----->DramcWriteLeveling(PI) begin...
2894 10:52:00.166909 ==
2895 10:52:00.169860 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 10:52:00.173211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 10:52:00.176517 ==
2898 10:52:00.176603 Write leveling (Byte 0): 33 => 33
2899 10:52:00.179738 Write leveling (Byte 1): 31 => 31
2900 10:52:00.183339 DramcWriteLeveling(PI) end<-----
2901 10:52:00.183433
2902 10:52:00.183502 ==
2903 10:52:00.187056 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 10:52:00.192949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 10:52:00.193037 ==
2906 10:52:00.196603 [Gating] SW mode calibration
2907 10:52:00.202944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2908 10:52:00.206033 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2909 10:52:00.212897 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2910 10:52:00.216334 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 10:52:00.219421 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 10:52:00.226051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 10:52:00.229747 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 10:52:00.233034 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 10:52:00.236334 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 10:52:00.242629 0 15 28 | B1->B0 | 2f2f 2d2d | 1 0 | (1 1) (0 1)
2917 10:52:00.246396 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2918 10:52:00.249768 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 10:52:00.256095 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 10:52:00.259442 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 10:52:00.262689 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 10:52:00.269347 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 10:52:00.272723 1 0 24 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2924 10:52:00.276204 1 0 28 | B1->B0 | 3131 3d3d | 0 1 | (0 0) (0 0)
2925 10:52:00.282703 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2926 10:52:00.285927 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 10:52:00.288996 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 10:52:00.295905 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 10:52:00.299408 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 10:52:00.302633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 10:52:00.309190 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 10:52:00.312182 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2933 10:52:00.315702 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2934 10:52:00.322402 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:52:00.325591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:52:00.329024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 10:52:00.335889 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 10:52:00.339226 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 10:52:00.342302 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 10:52:00.348879 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 10:52:00.352258 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 10:52:00.355733 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 10:52:00.362167 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 10:52:00.365265 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 10:52:00.368641 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 10:52:00.375557 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 10:52:00.378769 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2948 10:52:00.382202 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2949 10:52:00.388899 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 10:52:00.388971 Total UI for P1: 0, mck2ui 16
2951 10:52:00.395331 best dqsien dly found for B0: ( 1, 3, 26)
2952 10:52:00.395403 Total UI for P1: 0, mck2ui 16
2953 10:52:00.398798 best dqsien dly found for B1: ( 1, 3, 28)
2954 10:52:00.405140 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2955 10:52:00.408628 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2956 10:52:00.408725
2957 10:52:00.411635 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2958 10:52:00.415154 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2959 10:52:00.418526 [Gating] SW calibration Done
2960 10:52:00.418602 ==
2961 10:52:00.421612 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 10:52:00.425251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 10:52:00.425327 ==
2964 10:52:00.428267 RX Vref Scan: 0
2965 10:52:00.428337
2966 10:52:00.428398 RX Vref 0 -> 0, step: 1
2967 10:52:00.428456
2968 10:52:00.431557 RX Delay -40 -> 252, step: 8
2969 10:52:00.435079 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2970 10:52:00.442018 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2971 10:52:00.444945 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2972 10:52:00.448168 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2973 10:52:00.451906 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2974 10:52:00.455451 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2975 10:52:00.461796 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2976 10:52:00.464944 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2977 10:52:00.468401 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2978 10:52:00.471450 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2979 10:52:00.475007 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2980 10:52:00.478198 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2981 10:52:00.485037 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2982 10:52:00.488169 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2983 10:52:00.491487 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2984 10:52:00.494673 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2985 10:52:00.494763 ==
2986 10:52:00.498267 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 10:52:00.505009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 10:52:00.505093 ==
2989 10:52:00.505158 DQS Delay:
2990 10:52:00.507967 DQS0 = 0, DQS1 = 0
2991 10:52:00.508049 DQM Delay:
2992 10:52:00.511668 DQM0 = 120, DQM1 = 108
2993 10:52:00.511750 DQ Delay:
2994 10:52:00.515136 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2995 10:52:00.517807 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2996 10:52:00.521071 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2997 10:52:00.524705 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2998 10:52:00.524817
2999 10:52:00.524895
3000 10:52:00.524956 ==
3001 10:52:00.528014 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 10:52:00.534499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 10:52:00.534582 ==
3004 10:52:00.534647
3005 10:52:00.534707
3006 10:52:00.534765 TX Vref Scan disable
3007 10:52:00.537744 == TX Byte 0 ==
3008 10:52:00.541301 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3009 10:52:00.544782 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3010 10:52:00.547703 == TX Byte 1 ==
3011 10:52:00.551243 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3012 10:52:00.554239 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3013 10:52:00.557800 ==
3014 10:52:00.561090 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 10:52:00.564586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 10:52:00.564671 ==
3017 10:52:00.575812 TX Vref=22, minBit 4, minWin=24, winSum=407
3018 10:52:00.578987 TX Vref=24, minBit 0, minWin=25, winSum=417
3019 10:52:00.582569 TX Vref=26, minBit 0, minWin=25, winSum=412
3020 10:52:00.585505 TX Vref=28, minBit 1, minWin=24, winSum=419
3021 10:52:00.588776 TX Vref=30, minBit 1, minWin=25, winSum=422
3022 10:52:00.595734 TX Vref=32, minBit 5, minWin=25, winSum=420
3023 10:52:00.599000 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 30
3024 10:52:00.599085
3025 10:52:00.602144 Final TX Range 1 Vref 30
3026 10:52:00.602228
3027 10:52:00.602294 ==
3028 10:52:00.605675 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 10:52:00.609194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 10:52:00.609279 ==
3031 10:52:00.612006
3032 10:52:00.612090
3033 10:52:00.612156 TX Vref Scan disable
3034 10:52:00.615566 == TX Byte 0 ==
3035 10:52:00.618555 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3036 10:52:00.625201 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3037 10:52:00.625286 == TX Byte 1 ==
3038 10:52:00.628574 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3039 10:52:00.635511 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3040 10:52:00.635595
3041 10:52:00.635676 [DATLAT]
3042 10:52:00.635750 Freq=1200, CH0 RK1
3043 10:52:00.635809
3044 10:52:00.638586 DATLAT Default: 0xd
3045 10:52:00.638668 0, 0xFFFF, sum = 0
3046 10:52:00.642158 1, 0xFFFF, sum = 0
3047 10:52:00.645234 2, 0xFFFF, sum = 0
3048 10:52:00.645332 3, 0xFFFF, sum = 0
3049 10:52:00.648738 4, 0xFFFF, sum = 0
3050 10:52:00.648883 5, 0xFFFF, sum = 0
3051 10:52:00.652028 6, 0xFFFF, sum = 0
3052 10:52:00.652113 7, 0xFFFF, sum = 0
3053 10:52:00.655243 8, 0xFFFF, sum = 0
3054 10:52:00.655328 9, 0xFFFF, sum = 0
3055 10:52:00.658523 10, 0xFFFF, sum = 0
3056 10:52:00.658608 11, 0xFFFF, sum = 0
3057 10:52:00.661920 12, 0x0, sum = 1
3058 10:52:00.662003 13, 0x0, sum = 2
3059 10:52:00.664920 14, 0x0, sum = 3
3060 10:52:00.665017 15, 0x0, sum = 4
3061 10:52:00.668566 best_step = 13
3062 10:52:00.668650
3063 10:52:00.668716 ==
3064 10:52:00.671675 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 10:52:00.675165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 10:52:00.675250 ==
3067 10:52:00.675317 RX Vref Scan: 0
3068 10:52:00.678556
3069 10:52:00.678651 RX Vref 0 -> 0, step: 1
3070 10:52:00.678716
3071 10:52:00.681592 RX Delay -21 -> 252, step: 4
3072 10:52:00.688230 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3073 10:52:00.691732 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3074 10:52:00.694926 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3075 10:52:00.698452 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3076 10:52:00.701489 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3077 10:52:00.704774 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3078 10:52:00.711346 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3079 10:52:00.714956 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3080 10:52:00.718012 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3081 10:52:00.721493 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3082 10:52:00.724598 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3083 10:52:00.731263 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3084 10:52:00.734682 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3085 10:52:00.737917 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3086 10:52:00.741376 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3087 10:52:00.747902 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3088 10:52:00.747986 ==
3089 10:52:00.751210 Dram Type= 6, Freq= 0, CH_0, rank 1
3090 10:52:00.754767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 10:52:00.754851 ==
3092 10:52:00.754918 DQS Delay:
3093 10:52:00.758687 DQS0 = 0, DQS1 = 0
3094 10:52:00.758772 DQM Delay:
3095 10:52:00.761353 DQM0 = 119, DQM1 = 108
3096 10:52:00.761437 DQ Delay:
3097 10:52:00.764502 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3098 10:52:00.768227 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3099 10:52:00.770919 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3100 10:52:00.774274 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
3101 10:52:00.774357
3102 10:52:00.774423
3103 10:52:00.784198 [DQSOSCAuto] RK1, (LSB)MR18= 0xef6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3104 10:52:00.787452 CH0 RK1: MR19=403, MR18=EF6
3105 10:52:00.791087 CH0_RK1: MR19=0x403, MR18=0xEF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3106 10:52:00.794088 [RxdqsGatingPostProcess] freq 1200
3107 10:52:00.801145 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3108 10:52:00.804261 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 10:52:00.807755 best DQS1 dly(2T, 0.5T) = (0, 12)
3110 10:52:00.810787 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 10:52:00.814008 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3112 10:52:00.817634 best DQS0 dly(2T, 0.5T) = (0, 11)
3113 10:52:00.820805 best DQS1 dly(2T, 0.5T) = (0, 11)
3114 10:52:00.824040 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3115 10:52:00.827593 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3116 10:52:00.830669 Pre-setting of DQS Precalculation
3117 10:52:00.834087 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3118 10:52:00.834171 ==
3119 10:52:00.837212 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 10:52:00.840674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 10:52:00.840786 ==
3122 10:52:00.847353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 10:52:00.853675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3124 10:52:00.861585 [CA 0] Center 37 (7~68) winsize 62
3125 10:52:00.865211 [CA 1] Center 37 (7~68) winsize 62
3126 10:52:00.868207 [CA 2] Center 35 (5~65) winsize 61
3127 10:52:00.871786 [CA 3] Center 34 (4~65) winsize 62
3128 10:52:00.875028 [CA 4] Center 34 (4~65) winsize 62
3129 10:52:00.878121 [CA 5] Center 33 (3~64) winsize 62
3130 10:52:00.878205
3131 10:52:00.881620 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3132 10:52:00.881705
3133 10:52:00.885026 [CATrainingPosCal] consider 1 rank data
3134 10:52:00.888180 u2DelayCellTimex100 = 270/100 ps
3135 10:52:00.891639 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 10:52:00.898251 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 10:52:00.901353 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 10:52:00.904744 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3139 10:52:00.908006 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3140 10:52:00.911479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 10:52:00.911563
3142 10:52:00.914628 CA PerBit enable=1, Macro0, CA PI delay=33
3143 10:52:00.914711
3144 10:52:00.917938 [CBTSetCACLKResult] CA Dly = 33
3145 10:52:00.918023 CS Dly: 5 (0~36)
3146 10:52:00.921205 ==
3147 10:52:00.924375 Dram Type= 6, Freq= 0, CH_1, rank 1
3148 10:52:00.927769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 10:52:00.927853 ==
3150 10:52:00.931247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3151 10:52:00.937916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3152 10:52:00.947360 [CA 0] Center 38 (8~68) winsize 61
3153 10:52:00.950599 [CA 1] Center 38 (8~68) winsize 61
3154 10:52:00.953885 [CA 2] Center 35 (5~66) winsize 62
3155 10:52:00.957288 [CA 3] Center 34 (4~65) winsize 62
3156 10:52:00.960583 [CA 4] Center 35 (5~65) winsize 61
3157 10:52:00.963761 [CA 5] Center 34 (4~65) winsize 62
3158 10:52:00.963846
3159 10:52:00.967424 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3160 10:52:00.967512
3161 10:52:00.970379 [CATrainingPosCal] consider 2 rank data
3162 10:52:00.974032 u2DelayCellTimex100 = 270/100 ps
3163 10:52:00.977138 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3164 10:52:00.980371 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3165 10:52:00.987161 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3166 10:52:00.990726 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3167 10:52:00.993699 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3168 10:52:00.996906 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3169 10:52:00.996990
3170 10:52:01.000343 CA PerBit enable=1, Macro0, CA PI delay=34
3171 10:52:01.000427
3172 10:52:01.003763 [CBTSetCACLKResult] CA Dly = 34
3173 10:52:01.003846 CS Dly: 6 (0~39)
3174 10:52:01.003913
3175 10:52:01.006953 ----->DramcWriteLeveling(PI) begin...
3176 10:52:01.010298 ==
3177 10:52:01.013733 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 10:52:01.016965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 10:52:01.017049 ==
3180 10:52:01.020379 Write leveling (Byte 0): 23 => 23
3181 10:52:01.023683 Write leveling (Byte 1): 26 => 26
3182 10:52:01.027016 DramcWriteLeveling(PI) end<-----
3183 10:52:01.027100
3184 10:52:01.027166 ==
3185 10:52:01.030514 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 10:52:01.034002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 10:52:01.034087 ==
3188 10:52:01.036817 [Gating] SW mode calibration
3189 10:52:01.043902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3190 10:52:01.050238 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3191 10:52:01.053438 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 10:52:01.057161 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 10:52:01.063508 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 10:52:01.066589 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 10:52:01.070025 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 10:52:01.076900 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3197 10:52:01.080358 0 15 24 | B1->B0 | 2f2f 2929 | 1 1 | (1 0) (1 0)
3198 10:52:01.083406 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3199 10:52:01.086677 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 10:52:01.093667 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 10:52:01.096791 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 10:52:01.099856 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 10:52:01.106468 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 10:52:01.110010 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 10:52:01.113546 1 0 24 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
3206 10:52:01.119877 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 10:52:01.123287 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 10:52:01.126650 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 10:52:01.132974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 10:52:01.136505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 10:52:01.139862 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 10:52:01.146315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 10:52:01.149652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3214 10:52:01.153408 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3215 10:52:01.159537 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:52:01.163054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:52:01.166301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:52:01.173393 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 10:52:01.176492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 10:52:01.179697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 10:52:01.186417 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 10:52:01.189787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 10:52:01.193024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 10:52:01.199433 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 10:52:01.202762 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 10:52:01.206333 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 10:52:01.212945 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 10:52:01.216153 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3229 10:52:01.219536 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3230 10:52:01.226108 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 10:52:01.226200 Total UI for P1: 0, mck2ui 16
3232 10:52:01.229842 best dqsien dly found for B0: ( 1, 3, 22)
3233 10:52:01.232934 Total UI for P1: 0, mck2ui 16
3234 10:52:01.236392 best dqsien dly found for B1: ( 1, 3, 24)
3235 10:52:01.239511 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3236 10:52:01.242861 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3237 10:52:01.246266
3238 10:52:01.249364 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3239 10:52:01.252752 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3240 10:52:01.256167 [Gating] SW calibration Done
3241 10:52:01.256234 ==
3242 10:52:01.259464 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 10:52:01.262707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 10:52:01.262776 ==
3245 10:52:01.262836 RX Vref Scan: 0
3246 10:52:01.266075
3247 10:52:01.266143 RX Vref 0 -> 0, step: 1
3248 10:52:01.266203
3249 10:52:01.269169 RX Delay -40 -> 252, step: 8
3250 10:52:01.272724 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3251 10:52:01.276336 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3252 10:52:01.282969 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3253 10:52:01.285938 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3254 10:52:01.289852 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3255 10:52:01.293141 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3256 10:52:01.296451 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3257 10:52:01.302754 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3258 10:52:01.306061 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3259 10:52:01.309135 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3260 10:52:01.312322 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3261 10:52:01.315866 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3262 10:52:01.322417 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3263 10:52:01.325861 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3264 10:52:01.328978 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3265 10:52:01.332666 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3266 10:52:01.332738 ==
3267 10:52:01.335882 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 10:52:01.342544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 10:52:01.342614 ==
3270 10:52:01.342679 DQS Delay:
3271 10:52:01.345657 DQS0 = 0, DQS1 = 0
3272 10:52:01.345726 DQM Delay:
3273 10:52:01.345787 DQM0 = 120, DQM1 = 112
3274 10:52:01.349226 DQ Delay:
3275 10:52:01.352541 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3276 10:52:01.355912 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3277 10:52:01.359145 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3278 10:52:01.362662 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3279 10:52:01.362728
3280 10:52:01.362788
3281 10:52:01.362849 ==
3282 10:52:01.366050 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 10:52:01.369049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 10:52:01.369116 ==
3285 10:52:01.372407
3286 10:52:01.372471
3287 10:52:01.372529 TX Vref Scan disable
3288 10:52:01.375959 == TX Byte 0 ==
3289 10:52:01.379066 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3290 10:52:01.382321 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3291 10:52:01.385583 == TX Byte 1 ==
3292 10:52:01.388738 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3293 10:52:01.392151 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3294 10:52:01.392222 ==
3295 10:52:01.395553 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 10:52:01.402160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 10:52:01.402232 ==
3298 10:52:01.412825 TX Vref=22, minBit 11, minWin=23, winSum=407
3299 10:52:01.416288 TX Vref=24, minBit 11, minWin=24, winSum=410
3300 10:52:01.419422 TX Vref=26, minBit 8, minWin=25, winSum=416
3301 10:52:01.422992 TX Vref=28, minBit 10, minWin=25, winSum=420
3302 10:52:01.426067 TX Vref=30, minBit 10, minWin=25, winSum=421
3303 10:52:01.432498 TX Vref=32, minBit 1, minWin=26, winSum=422
3304 10:52:01.436111 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 32
3305 10:52:01.436184
3306 10:52:01.439314 Final TX Range 1 Vref 32
3307 10:52:01.439381
3308 10:52:01.439444 ==
3309 10:52:01.442731 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 10:52:01.449083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 10:52:01.449152 ==
3312 10:52:01.449213
3313 10:52:01.449272
3314 10:52:01.449328 TX Vref Scan disable
3315 10:52:01.452951 == TX Byte 0 ==
3316 10:52:01.456362 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3317 10:52:01.459731 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3318 10:52:01.462667 == TX Byte 1 ==
3319 10:52:01.466314 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3320 10:52:01.472843 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3321 10:52:01.472913
3322 10:52:01.472974 [DATLAT]
3323 10:52:01.473036 Freq=1200, CH1 RK0
3324 10:52:01.473095
3325 10:52:01.476100 DATLAT Default: 0xd
3326 10:52:01.476176 0, 0xFFFF, sum = 0
3327 10:52:01.479313 1, 0xFFFF, sum = 0
3328 10:52:01.482498 2, 0xFFFF, sum = 0
3329 10:52:01.482569 3, 0xFFFF, sum = 0
3330 10:52:01.486277 4, 0xFFFF, sum = 0
3331 10:52:01.486346 5, 0xFFFF, sum = 0
3332 10:52:01.489041 6, 0xFFFF, sum = 0
3333 10:52:01.489110 7, 0xFFFF, sum = 0
3334 10:52:01.492527 8, 0xFFFF, sum = 0
3335 10:52:01.492603 9, 0xFFFF, sum = 0
3336 10:52:01.495874 10, 0xFFFF, sum = 0
3337 10:52:01.495941 11, 0xFFFF, sum = 0
3338 10:52:01.499381 12, 0x0, sum = 1
3339 10:52:01.499447 13, 0x0, sum = 2
3340 10:52:01.502618 14, 0x0, sum = 3
3341 10:52:01.502687 15, 0x0, sum = 4
3342 10:52:01.505962 best_step = 13
3343 10:52:01.506029
3344 10:52:01.506091 ==
3345 10:52:01.509894 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 10:52:01.512523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 10:52:01.512589 ==
3348 10:52:01.512649 RX Vref Scan: 1
3349 10:52:01.512707
3350 10:52:01.515850 Set Vref Range= 32 -> 127
3351 10:52:01.515913
3352 10:52:01.519572 RX Vref 32 -> 127, step: 1
3353 10:52:01.519644
3354 10:52:01.522455 RX Delay -13 -> 252, step: 4
3355 10:52:01.522520
3356 10:52:01.526000 Set Vref, RX VrefLevel [Byte0]: 32
3357 10:52:01.529294 [Byte1]: 32
3358 10:52:01.529363
3359 10:52:01.532672 Set Vref, RX VrefLevel [Byte0]: 33
3360 10:52:01.535664 [Byte1]: 33
3361 10:52:01.539138
3362 10:52:01.539219 Set Vref, RX VrefLevel [Byte0]: 34
3363 10:52:01.542538 [Byte1]: 34
3364 10:52:01.547147
3365 10:52:01.547228 Set Vref, RX VrefLevel [Byte0]: 35
3366 10:52:01.550776 [Byte1]: 35
3367 10:52:01.555232
3368 10:52:01.555313 Set Vref, RX VrefLevel [Byte0]: 36
3369 10:52:01.558172 [Byte1]: 36
3370 10:52:01.563003
3371 10:52:01.563084 Set Vref, RX VrefLevel [Byte0]: 37
3372 10:52:01.566175 [Byte1]: 37
3373 10:52:01.570692
3374 10:52:01.570772 Set Vref, RX VrefLevel [Byte0]: 38
3375 10:52:01.573960 [Byte1]: 38
3376 10:52:01.578995
3377 10:52:01.579158 Set Vref, RX VrefLevel [Byte0]: 39
3378 10:52:01.582382 [Byte1]: 39
3379 10:52:01.587189
3380 10:52:01.587358 Set Vref, RX VrefLevel [Byte0]: 40
3381 10:52:01.590287 [Byte1]: 40
3382 10:52:01.594902
3383 10:52:01.595088 Set Vref, RX VrefLevel [Byte0]: 41
3384 10:52:01.598133 [Byte1]: 41
3385 10:52:01.602613
3386 10:52:01.602735 Set Vref, RX VrefLevel [Byte0]: 42
3387 10:52:01.606207 [Byte1]: 42
3388 10:52:01.610743
3389 10:52:01.610894 Set Vref, RX VrefLevel [Byte0]: 43
3390 10:52:01.614156 [Byte1]: 43
3391 10:52:01.618526
3392 10:52:01.618778 Set Vref, RX VrefLevel [Byte0]: 44
3393 10:52:01.621779 [Byte1]: 44
3394 10:52:01.626415
3395 10:52:01.626769 Set Vref, RX VrefLevel [Byte0]: 45
3396 10:52:01.629781 [Byte1]: 45
3397 10:52:01.635018
3398 10:52:01.635430 Set Vref, RX VrefLevel [Byte0]: 46
3399 10:52:01.637518 [Byte1]: 46
3400 10:52:01.642547
3401 10:52:01.643096 Set Vref, RX VrefLevel [Byte0]: 47
3402 10:52:01.646155 [Byte1]: 47
3403 10:52:01.650810
3404 10:52:01.651452 Set Vref, RX VrefLevel [Byte0]: 48
3405 10:52:01.653573 [Byte1]: 48
3406 10:52:01.658324
3407 10:52:01.658874 Set Vref, RX VrefLevel [Byte0]: 49
3408 10:52:01.661358 [Byte1]: 49
3409 10:52:01.666010
3410 10:52:01.666608 Set Vref, RX VrefLevel [Byte0]: 50
3411 10:52:01.669500 [Byte1]: 50
3412 10:52:01.674192
3413 10:52:01.674735 Set Vref, RX VrefLevel [Byte0]: 51
3414 10:52:01.677357 [Byte1]: 51
3415 10:52:01.681871
3416 10:52:01.682328 Set Vref, RX VrefLevel [Byte0]: 52
3417 10:52:01.685152 [Byte1]: 52
3418 10:52:01.689682
3419 10:52:01.690245 Set Vref, RX VrefLevel [Byte0]: 53
3420 10:52:01.693145 [Byte1]: 53
3421 10:52:01.697706
3422 10:52:01.698257 Set Vref, RX VrefLevel [Byte0]: 54
3423 10:52:01.701402 [Byte1]: 54
3424 10:52:01.705547
3425 10:52:01.706002 Set Vref, RX VrefLevel [Byte0]: 55
3426 10:52:01.708761 [Byte1]: 55
3427 10:52:01.713498
3428 10:52:01.714070 Set Vref, RX VrefLevel [Byte0]: 56
3429 10:52:01.716630 [Byte1]: 56
3430 10:52:01.721209
3431 10:52:01.721871 Set Vref, RX VrefLevel [Byte0]: 57
3432 10:52:01.724759 [Byte1]: 57
3433 10:52:01.729236
3434 10:52:01.729691 Set Vref, RX VrefLevel [Byte0]: 58
3435 10:52:01.732410 [Byte1]: 58
3436 10:52:01.737146
3437 10:52:01.737695 Set Vref, RX VrefLevel [Byte0]: 59
3438 10:52:01.740531 [Byte1]: 59
3439 10:52:01.744978
3440 10:52:01.745523 Set Vref, RX VrefLevel [Byte0]: 60
3441 10:52:01.748554 [Byte1]: 60
3442 10:52:01.753376
3443 10:52:01.753930 Set Vref, RX VrefLevel [Byte0]: 61
3444 10:52:01.756334 [Byte1]: 61
3445 10:52:01.760750
3446 10:52:01.761330 Set Vref, RX VrefLevel [Byte0]: 62
3447 10:52:01.764538 [Byte1]: 62
3448 10:52:01.768488
3449 10:52:01.768987 Set Vref, RX VrefLevel [Byte0]: 63
3450 10:52:01.771659 [Byte1]: 63
3451 10:52:01.776245
3452 10:52:01.779521 Set Vref, RX VrefLevel [Byte0]: 64
3453 10:52:01.782704 [Byte1]: 64
3454 10:52:01.783360
3455 10:52:01.786216 Set Vref, RX VrefLevel [Byte0]: 65
3456 10:52:01.789324 [Byte1]: 65
3457 10:52:01.789905
3458 10:52:01.792912 Set Vref, RX VrefLevel [Byte0]: 66
3459 10:52:01.795910 [Byte1]: 66
3460 10:52:01.799893
3461 10:52:01.800190 Set Vref, RX VrefLevel [Byte0]: 67
3462 10:52:01.803304 [Byte1]: 67
3463 10:52:01.807861
3464 10:52:01.808099 Final RX Vref Byte 0 = 51 to rank0
3465 10:52:01.810725 Final RX Vref Byte 1 = 57 to rank0
3466 10:52:01.814114 Final RX Vref Byte 0 = 51 to rank1
3467 10:52:01.817412 Final RX Vref Byte 1 = 57 to rank1==
3468 10:52:01.820803 Dram Type= 6, Freq= 0, CH_1, rank 0
3469 10:52:01.827551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 10:52:01.827661 ==
3471 10:52:01.827745 DQS Delay:
3472 10:52:01.827821 DQS0 = 0, DQS1 = 0
3473 10:52:01.830711 DQM Delay:
3474 10:52:01.830807 DQM0 = 119, DQM1 = 113
3475 10:52:01.834278 DQ Delay:
3476 10:52:01.837397 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3477 10:52:01.840610 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3478 10:52:01.844267 DQ8 =102, DQ9 =100, DQ10 =118, DQ11 =106
3479 10:52:01.847150 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =122
3480 10:52:01.847233
3481 10:52:01.847298
3482 10:52:01.857097 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3483 10:52:01.857184 CH1 RK0: MR19=404, MR18=417
3484 10:52:01.863885 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3485 10:52:01.863969
3486 10:52:01.867088 ----->DramcWriteLeveling(PI) begin...
3487 10:52:01.867172 ==
3488 10:52:01.870343 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 10:52:01.876968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 10:52:01.877052 ==
3491 10:52:01.880446 Write leveling (Byte 0): 26 => 26
3492 10:52:01.880529 Write leveling (Byte 1): 28 => 28
3493 10:52:01.883968 DramcWriteLeveling(PI) end<-----
3494 10:52:01.884051
3495 10:52:01.884116 ==
3496 10:52:01.886986 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 10:52:01.893990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 10:52:01.894075 ==
3499 10:52:01.897285 [Gating] SW mode calibration
3500 10:52:01.903895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3501 10:52:01.907123 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3502 10:52:01.913925 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 10:52:01.916877 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 10:52:01.920357 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 10:52:01.927090 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 10:52:01.930362 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 10:52:01.934082 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 10:52:01.937516 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
3509 10:52:01.944428 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3510 10:52:01.947182 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 10:52:01.950533 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 10:52:01.956658 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 10:52:01.960290 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 10:52:01.963562 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 10:52:01.970597 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3516 10:52:01.973492 1 0 24 | B1->B0 | 3c3c 2929 | 1 0 | (0 0) (1 1)
3517 10:52:01.976871 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
3518 10:52:01.983312 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 10:52:01.987044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 10:52:01.990304 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 10:52:01.996708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 10:52:02.000009 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 10:52:02.003355 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 10:52:02.009952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3525 10:52:02.013580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 10:52:02.016903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 10:52:02.023609 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 10:52:02.026619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 10:52:02.029849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 10:52:02.036745 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 10:52:02.039532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 10:52:02.042885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 10:52:02.049735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 10:52:02.053062 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:52:02.056220 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 10:52:02.062969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 10:52:02.065982 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 10:52:02.069125 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 10:52:02.076281 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 10:52:02.078922 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3541 10:52:02.082327 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3542 10:52:02.085923 Total UI for P1: 0, mck2ui 16
3543 10:52:02.088915 best dqsien dly found for B0: ( 1, 3, 24)
3544 10:52:02.095854 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 10:52:02.095955 Total UI for P1: 0, mck2ui 16
3546 10:52:02.102155 best dqsien dly found for B1: ( 1, 3, 26)
3547 10:52:02.105539 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3548 10:52:02.109105 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3549 10:52:02.109203
3550 10:52:02.112081 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3551 10:52:02.115339 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3552 10:52:02.118594 [Gating] SW calibration Done
3553 10:52:02.118680 ==
3554 10:52:02.122384 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 10:52:02.125321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 10:52:02.125416 ==
3557 10:52:02.128580 RX Vref Scan: 0
3558 10:52:02.128686
3559 10:52:02.128824 RX Vref 0 -> 0, step: 1
3560 10:52:02.128917
3561 10:52:02.131958 RX Delay -40 -> 252, step: 8
3562 10:52:02.135305 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3563 10:52:02.142161 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3564 10:52:02.145463 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3565 10:52:02.148905 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3566 10:52:02.151987 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3567 10:52:02.158494 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3568 10:52:02.161642 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3569 10:52:02.164970 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3570 10:52:02.168300 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3571 10:52:02.171326 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3572 10:52:02.174984 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3573 10:52:02.181491 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3574 10:52:02.184613 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3575 10:52:02.188281 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3576 10:52:02.191728 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3577 10:52:02.197933 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3578 10:52:02.198027 ==
3579 10:52:02.201119 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 10:52:02.204248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 10:52:02.204360 ==
3582 10:52:02.204450 DQS Delay:
3583 10:52:02.207634 DQS0 = 0, DQS1 = 0
3584 10:52:02.207730 DQM Delay:
3585 10:52:02.210952 DQM0 = 119, DQM1 = 113
3586 10:52:02.211064 DQ Delay:
3587 10:52:02.214235 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3588 10:52:02.217499 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3589 10:52:02.220756 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3590 10:52:02.224219 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3591 10:52:02.224338
3592 10:52:02.227658
3593 10:52:02.227749 ==
3594 10:52:02.230700 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 10:52:02.234060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 10:52:02.234165 ==
3597 10:52:02.234258
3598 10:52:02.234346
3599 10:52:02.237436 TX Vref Scan disable
3600 10:52:02.237514 == TX Byte 0 ==
3601 10:52:02.244217 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3602 10:52:02.247282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3603 10:52:02.247391 == TX Byte 1 ==
3604 10:52:02.254048 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3605 10:52:02.257423 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3606 10:52:02.257520 ==
3607 10:52:02.260651 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 10:52:02.264155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 10:52:02.264265 ==
3610 10:52:02.276455 TX Vref=22, minBit 9, minWin=24, winSum=414
3611 10:52:02.279355 TX Vref=24, minBit 1, minWin=25, winSum=423
3612 10:52:02.282681 TX Vref=26, minBit 3, minWin=25, winSum=425
3613 10:52:02.286283 TX Vref=28, minBit 1, minWin=26, winSum=428
3614 10:52:02.289373 TX Vref=30, minBit 1, minWin=26, winSum=427
3615 10:52:02.296002 TX Vref=32, minBit 1, minWin=26, winSum=427
3616 10:52:02.299659 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3617 10:52:02.299747
3618 10:52:02.302575 Final TX Range 1 Vref 28
3619 10:52:02.302677
3620 10:52:02.302759 ==
3621 10:52:02.306216 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 10:52:02.309217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 10:52:02.312385 ==
3624 10:52:02.312469
3625 10:52:02.312535
3626 10:52:02.312611 TX Vref Scan disable
3627 10:52:02.315970 == TX Byte 0 ==
3628 10:52:02.319395 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3629 10:52:02.325764 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3630 10:52:02.325892 == TX Byte 1 ==
3631 10:52:02.329292 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3632 10:52:02.336089 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3633 10:52:02.336175
3634 10:52:02.336275 [DATLAT]
3635 10:52:02.336337 Freq=1200, CH1 RK1
3636 10:52:02.336397
3637 10:52:02.339394 DATLAT Default: 0xd
3638 10:52:02.342496 0, 0xFFFF, sum = 0
3639 10:52:02.342582 1, 0xFFFF, sum = 0
3640 10:52:02.345908 2, 0xFFFF, sum = 0
3641 10:52:02.345993 3, 0xFFFF, sum = 0
3642 10:52:02.348986 4, 0xFFFF, sum = 0
3643 10:52:02.349071 5, 0xFFFF, sum = 0
3644 10:52:02.352587 6, 0xFFFF, sum = 0
3645 10:52:02.352672 7, 0xFFFF, sum = 0
3646 10:52:02.355802 8, 0xFFFF, sum = 0
3647 10:52:02.355887 9, 0xFFFF, sum = 0
3648 10:52:02.359137 10, 0xFFFF, sum = 0
3649 10:52:02.359223 11, 0xFFFF, sum = 0
3650 10:52:02.362252 12, 0x0, sum = 1
3651 10:52:02.362337 13, 0x0, sum = 2
3652 10:52:02.365172 14, 0x0, sum = 3
3653 10:52:02.365257 15, 0x0, sum = 4
3654 10:52:02.368582 best_step = 13
3655 10:52:02.368665
3656 10:52:02.368730 ==
3657 10:52:02.372210 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 10:52:02.375083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 10:52:02.375167 ==
3660 10:52:02.378291 RX Vref Scan: 0
3661 10:52:02.378375
3662 10:52:02.378441 RX Vref 0 -> 0, step: 1
3663 10:52:02.378503
3664 10:52:02.381912 RX Delay -13 -> 252, step: 4
3665 10:52:02.388331 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3666 10:52:02.391448 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3667 10:52:02.395074 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3668 10:52:02.398122 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3669 10:52:02.401411 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3670 10:52:02.408250 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3671 10:52:02.411244 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3672 10:52:02.414619 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3673 10:52:02.418014 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3674 10:52:02.421396 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3675 10:52:02.427861 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3676 10:52:02.431313 iDelay=195, Bit 11, Center 110 (47 ~ 174) 128
3677 10:52:02.434519 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3678 10:52:02.437902 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3679 10:52:02.444451 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3680 10:52:02.447829 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3681 10:52:02.447913 ==
3682 10:52:02.451448 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 10:52:02.454391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 10:52:02.454475 ==
3685 10:52:02.457665 DQS Delay:
3686 10:52:02.457748 DQS0 = 0, DQS1 = 0
3687 10:52:02.457815 DQM Delay:
3688 10:52:02.460707 DQM0 = 119, DQM1 = 114
3689 10:52:02.460815 DQ Delay:
3690 10:52:02.464292 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3691 10:52:02.467519 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3692 10:52:02.470775 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =110
3693 10:52:02.477395 DQ12 =122, DQ13 =120, DQ14 =122, DQ15 =124
3694 10:52:02.477479
3695 10:52:02.477545
3696 10:52:02.483791 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3697 10:52:02.487282 CH1 RK1: MR19=403, MR18=6EA
3698 10:52:02.493999 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3699 10:52:02.496920 [RxdqsGatingPostProcess] freq 1200
3700 10:52:02.500645 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3701 10:52:02.503785 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 10:52:02.507146 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 10:52:02.510591 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 10:52:02.513566 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 10:52:02.517016 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 10:52:02.520110 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 10:52:02.523409 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 10:52:02.526706 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 10:52:02.530240 Pre-setting of DQS Precalculation
3710 10:52:02.533354 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3711 10:52:02.543233 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3712 10:52:02.550016 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3713 10:52:02.550101
3714 10:52:02.550167
3715 10:52:02.553160 [Calibration Summary] 2400 Mbps
3716 10:52:02.553245 CH 0, Rank 0
3717 10:52:02.556337 SW Impedance : PASS
3718 10:52:02.556420 DUTY Scan : NO K
3719 10:52:02.559698 ZQ Calibration : PASS
3720 10:52:02.563173 Jitter Meter : NO K
3721 10:52:02.563257 CBT Training : PASS
3722 10:52:02.566351 Write leveling : PASS
3723 10:52:02.569414 RX DQS gating : PASS
3724 10:52:02.569498 RX DQ/DQS(RDDQC) : PASS
3725 10:52:02.573001 TX DQ/DQS : PASS
3726 10:52:02.576069 RX DATLAT : PASS
3727 10:52:02.576152 RX DQ/DQS(Engine): PASS
3728 10:52:02.579528 TX OE : NO K
3729 10:52:02.579612 All Pass.
3730 10:52:02.579679
3731 10:52:02.582865 CH 0, Rank 1
3732 10:52:02.582949 SW Impedance : PASS
3733 10:52:02.586175 DUTY Scan : NO K
3734 10:52:02.589673 ZQ Calibration : PASS
3735 10:52:02.589759 Jitter Meter : NO K
3736 10:52:02.592787 CBT Training : PASS
3737 10:52:02.595824 Write leveling : PASS
3738 10:52:02.595908 RX DQS gating : PASS
3739 10:52:02.599167 RX DQ/DQS(RDDQC) : PASS
3740 10:52:02.602620 TX DQ/DQS : PASS
3741 10:52:02.602704 RX DATLAT : PASS
3742 10:52:02.605777 RX DQ/DQS(Engine): PASS
3743 10:52:02.609306 TX OE : NO K
3744 10:52:02.609390 All Pass.
3745 10:52:02.609457
3746 10:52:02.609519 CH 1, Rank 0
3747 10:52:02.612740 SW Impedance : PASS
3748 10:52:02.616246 DUTY Scan : NO K
3749 10:52:02.616330 ZQ Calibration : PASS
3750 10:52:02.619354 Jitter Meter : NO K
3751 10:52:02.622498 CBT Training : PASS
3752 10:52:02.622581 Write leveling : PASS
3753 10:52:02.625890 RX DQS gating : PASS
3754 10:52:02.625974 RX DQ/DQS(RDDQC) : PASS
3755 10:52:02.629021 TX DQ/DQS : PASS
3756 10:52:02.632378 RX DATLAT : PASS
3757 10:52:02.632461 RX DQ/DQS(Engine): PASS
3758 10:52:02.635606 TX OE : NO K
3759 10:52:02.635690 All Pass.
3760 10:52:02.635757
3761 10:52:02.639286 CH 1, Rank 1
3762 10:52:02.639370 SW Impedance : PASS
3763 10:52:02.642103 DUTY Scan : NO K
3764 10:52:02.645594 ZQ Calibration : PASS
3765 10:52:02.645677 Jitter Meter : NO K
3766 10:52:02.649234 CBT Training : PASS
3767 10:52:02.652175 Write leveling : PASS
3768 10:52:02.652258 RX DQS gating : PASS
3769 10:52:02.655810 RX DQ/DQS(RDDQC) : PASS
3770 10:52:02.658977 TX DQ/DQS : PASS
3771 10:52:02.659060 RX DATLAT : PASS
3772 10:52:02.661976 RX DQ/DQS(Engine): PASS
3773 10:52:02.665231 TX OE : NO K
3774 10:52:02.665314 All Pass.
3775 10:52:02.665380
3776 10:52:02.668332 DramC Write-DBI off
3777 10:52:02.668416 PER_BANK_REFRESH: Hybrid Mode
3778 10:52:02.671646 TX_TRACKING: ON
3779 10:52:02.681649 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3780 10:52:02.685036 [FAST_K] Save calibration result to emmc
3781 10:52:02.688078 dramc_set_vcore_voltage set vcore to 650000
3782 10:52:02.688162 Read voltage for 600, 5
3783 10:52:02.691694 Vio18 = 0
3784 10:52:02.691778 Vcore = 650000
3785 10:52:02.691845 Vdram = 0
3786 10:52:02.694891 Vddq = 0
3787 10:52:02.694974 Vmddr = 0
3788 10:52:02.701408 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3789 10:52:02.704593 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3790 10:52:02.708190 MEM_TYPE=3, freq_sel=19
3791 10:52:02.711100 sv_algorithm_assistance_LP4_1600
3792 10:52:02.714351 ============ PULL DRAM RESETB DOWN ============
3793 10:52:02.717925 ========== PULL DRAM RESETB DOWN end =========
3794 10:52:02.724258 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3795 10:52:02.728412 ===================================
3796 10:52:02.728521 LPDDR4 DRAM CONFIGURATION
3797 10:52:02.731205 ===================================
3798 10:52:02.734192 EX_ROW_EN[0] = 0x0
3799 10:52:02.737638 EX_ROW_EN[1] = 0x0
3800 10:52:02.737722 LP4Y_EN = 0x0
3801 10:52:02.740712 WORK_FSP = 0x0
3802 10:52:02.740837 WL = 0x2
3803 10:52:02.744252 RL = 0x2
3804 10:52:02.744335 BL = 0x2
3805 10:52:02.747487 RPST = 0x0
3806 10:52:02.747571 RD_PRE = 0x0
3807 10:52:02.750661 WR_PRE = 0x1
3808 10:52:02.750774 WR_PST = 0x0
3809 10:52:02.754127 DBI_WR = 0x0
3810 10:52:02.754211 DBI_RD = 0x0
3811 10:52:02.757426 OTF = 0x1
3812 10:52:02.760708 ===================================
3813 10:52:02.763922 ===================================
3814 10:52:02.764007 ANA top config
3815 10:52:02.767307 ===================================
3816 10:52:02.770397 DLL_ASYNC_EN = 0
3817 10:52:02.773813 ALL_SLAVE_EN = 1
3818 10:52:02.777315 NEW_RANK_MODE = 1
3819 10:52:02.777430 DLL_IDLE_MODE = 1
3820 10:52:02.780608 LP45_APHY_COMB_EN = 1
3821 10:52:02.783631 TX_ODT_DIS = 1
3822 10:52:02.787138 NEW_8X_MODE = 1
3823 10:52:02.790440 ===================================
3824 10:52:02.793617 ===================================
3825 10:52:02.797060 data_rate = 1200
3826 10:52:02.797144 CKR = 1
3827 10:52:02.800328 DQ_P2S_RATIO = 8
3828 10:52:02.803552 ===================================
3829 10:52:02.806801 CA_P2S_RATIO = 8
3830 10:52:02.810171 DQ_CA_OPEN = 0
3831 10:52:02.813686 DQ_SEMI_OPEN = 0
3832 10:52:02.816733 CA_SEMI_OPEN = 0
3833 10:52:02.816844 CA_FULL_RATE = 0
3834 10:52:02.819930 DQ_CKDIV4_EN = 1
3835 10:52:02.823424 CA_CKDIV4_EN = 1
3836 10:52:02.826601 CA_PREDIV_EN = 0
3837 10:52:02.830273 PH8_DLY = 0
3838 10:52:02.833172 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3839 10:52:02.833250 DQ_AAMCK_DIV = 4
3840 10:52:02.836492 CA_AAMCK_DIV = 4
3841 10:52:02.839842 CA_ADMCK_DIV = 4
3842 10:52:02.843404 DQ_TRACK_CA_EN = 0
3843 10:52:02.846541 CA_PICK = 600
3844 10:52:02.849837 CA_MCKIO = 600
3845 10:52:02.853055 MCKIO_SEMI = 0
3846 10:52:02.856753 PLL_FREQ = 2288
3847 10:52:02.856837 DQ_UI_PI_RATIO = 32
3848 10:52:02.859815 CA_UI_PI_RATIO = 0
3849 10:52:02.863282 ===================================
3850 10:52:02.866186 ===================================
3851 10:52:02.869740 memory_type:LPDDR4
3852 10:52:02.873116 GP_NUM : 10
3853 10:52:02.873187 SRAM_EN : 1
3854 10:52:02.876559 MD32_EN : 0
3855 10:52:02.879518 ===================================
3856 10:52:02.879591 [ANA_INIT] >>>>>>>>>>>>>>
3857 10:52:02.882875 <<<<<< [CONFIGURE PHASE]: ANA_TX
3858 10:52:02.886139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3859 10:52:02.889411 ===================================
3860 10:52:02.892898 data_rate = 1200,PCW = 0X5800
3861 10:52:02.896117 ===================================
3862 10:52:02.899181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3863 10:52:02.906131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 10:52:02.912378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 10:52:02.915510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3866 10:52:02.918661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3867 10:52:02.922263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3868 10:52:02.925461 [ANA_INIT] flow start
3869 10:52:02.925555 [ANA_INIT] PLL >>>>>>>>
3870 10:52:02.928638 [ANA_INIT] PLL <<<<<<<<
3871 10:52:02.931997 [ANA_INIT] MIDPI >>>>>>>>
3872 10:52:02.935168 [ANA_INIT] MIDPI <<<<<<<<
3873 10:52:02.935245 [ANA_INIT] DLL >>>>>>>>
3874 10:52:02.938685 [ANA_INIT] flow end
3875 10:52:02.941804 ============ LP4 DIFF to SE enter ============
3876 10:52:02.945037 ============ LP4 DIFF to SE exit ============
3877 10:52:02.948674 [ANA_INIT] <<<<<<<<<<<<<
3878 10:52:02.951571 [Flow] Enable top DCM control >>>>>
3879 10:52:02.954953 [Flow] Enable top DCM control <<<<<
3880 10:52:02.958333 Enable DLL master slave shuffle
3881 10:52:02.965136 ==============================================================
3882 10:52:02.965222 Gating Mode config
3883 10:52:02.972094 ==============================================================
3884 10:52:02.972176 Config description:
3885 10:52:02.981673 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 10:52:02.987910 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 10:52:02.994843 SELPH_MODE 0: By rank 1: By Phase
3888 10:52:02.998040 ==============================================================
3889 10:52:03.001026 GAT_TRACK_EN = 1
3890 10:52:03.004329 RX_GATING_MODE = 2
3891 10:52:03.007818 RX_GATING_TRACK_MODE = 2
3892 10:52:03.011083 SELPH_MODE = 1
3893 10:52:03.014329 PICG_EARLY_EN = 1
3894 10:52:03.017592 VALID_LAT_VALUE = 1
3895 10:52:03.024264 ==============================================================
3896 10:52:03.027663 Enter into Gating configuration >>>>
3897 10:52:03.030696 Exit from Gating configuration <<<<
3898 10:52:03.034353 Enter into DVFS_PRE_config >>>>>
3899 10:52:03.043863 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 10:52:03.047306 Exit from DVFS_PRE_config <<<<<
3901 10:52:03.050227 Enter into PICG configuration >>>>
3902 10:52:03.053852 Exit from PICG configuration <<<<
3903 10:52:03.056831 [RX_INPUT] configuration >>>>>
3904 10:52:03.060316 [RX_INPUT] configuration <<<<<
3905 10:52:03.063747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 10:52:03.069914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 10:52:03.076594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 10:52:03.083219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 10:52:03.086345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 10:52:03.093326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 10:52:03.096524 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 10:52:03.103091 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 10:52:03.106545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 10:52:03.109602 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 10:52:03.113067 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 10:52:03.119326 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 10:52:03.122784 ===================================
3918 10:52:03.126152 LPDDR4 DRAM CONFIGURATION
3919 10:52:03.129619 ===================================
3920 10:52:03.129700 EX_ROW_EN[0] = 0x0
3921 10:52:03.132572 EX_ROW_EN[1] = 0x0
3922 10:52:03.132683 LP4Y_EN = 0x0
3923 10:52:03.136593 WORK_FSP = 0x0
3924 10:52:03.136701 WL = 0x2
3925 10:52:03.139656 RL = 0x2
3926 10:52:03.139726 BL = 0x2
3927 10:52:03.142873 RPST = 0x0
3928 10:52:03.142943 RD_PRE = 0x0
3929 10:52:03.145995 WR_PRE = 0x1
3930 10:52:03.146070 WR_PST = 0x0
3931 10:52:03.149288 DBI_WR = 0x0
3932 10:52:03.149392 DBI_RD = 0x0
3933 10:52:03.152656 OTF = 0x1
3934 10:52:03.156023 ===================================
3935 10:52:03.159164 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 10:52:03.162683 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 10:52:03.169138 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 10:52:03.172717 ===================================
3939 10:52:03.175865 LPDDR4 DRAM CONFIGURATION
3940 10:52:03.179209 ===================================
3941 10:52:03.179281 EX_ROW_EN[0] = 0x10
3942 10:52:03.182215 EX_ROW_EN[1] = 0x0
3943 10:52:03.182284 LP4Y_EN = 0x0
3944 10:52:03.185635 WORK_FSP = 0x0
3945 10:52:03.185734 WL = 0x2
3946 10:52:03.189219 RL = 0x2
3947 10:52:03.189321 BL = 0x2
3948 10:52:03.192374 RPST = 0x0
3949 10:52:03.192444 RD_PRE = 0x0
3950 10:52:03.195428 WR_PRE = 0x1
3951 10:52:03.195497 WR_PST = 0x0
3952 10:52:03.198702 DBI_WR = 0x0
3953 10:52:03.202151 DBI_RD = 0x0
3954 10:52:03.202222 OTF = 0x1
3955 10:52:03.205364 ===================================
3956 10:52:03.212096 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 10:52:03.215575 nWR fixed to 30
3958 10:52:03.219060 [ModeRegInit_LP4] CH0 RK0
3959 10:52:03.219134 [ModeRegInit_LP4] CH0 RK1
3960 10:52:03.222098 [ModeRegInit_LP4] CH1 RK0
3961 10:52:03.225599 [ModeRegInit_LP4] CH1 RK1
3962 10:52:03.225673 match AC timing 17
3963 10:52:03.232242 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 10:52:03.235333 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 10:52:03.238701 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 10:52:03.245289 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 10:52:03.248653 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 10:52:03.248751 ==
3969 10:52:03.252214 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 10:52:03.255432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 10:52:03.255504 ==
3972 10:52:03.261947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 10:52:03.268580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 10:52:03.271903 [CA 0] Center 36 (6~67) winsize 62
3975 10:52:03.275265 [CA 1] Center 36 (6~67) winsize 62
3976 10:52:03.278642 [CA 2] Center 34 (4~65) winsize 62
3977 10:52:03.281875 [CA 3] Center 34 (3~65) winsize 63
3978 10:52:03.285395 [CA 4] Center 33 (3~64) winsize 62
3979 10:52:03.288499 [CA 5] Center 33 (3~64) winsize 62
3980 10:52:03.288577
3981 10:52:03.292011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 10:52:03.292082
3983 10:52:03.295102 [CATrainingPosCal] consider 1 rank data
3984 10:52:03.298502 u2DelayCellTimex100 = 270/100 ps
3985 10:52:03.301433 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 10:52:03.304973 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3987 10:52:03.308436 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 10:52:03.311460 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3989 10:52:03.318172 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 10:52:03.321548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 10:52:03.321629
3992 10:52:03.324653 CA PerBit enable=1, Macro0, CA PI delay=33
3993 10:52:03.324757
3994 10:52:03.328182 [CBTSetCACLKResult] CA Dly = 33
3995 10:52:03.328254 CS Dly: 5 (0~36)
3996 10:52:03.328326 ==
3997 10:52:03.331176 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 10:52:03.337666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 10:52:03.337752 ==
4000 10:52:03.341197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 10:52:03.347735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4002 10:52:03.351323 [CA 0] Center 36 (6~67) winsize 62
4003 10:52:03.354209 [CA 1] Center 36 (6~67) winsize 62
4004 10:52:03.357548 [CA 2] Center 35 (4~66) winsize 63
4005 10:52:03.360888 [CA 3] Center 35 (4~66) winsize 63
4006 10:52:03.364056 [CA 4] Center 34 (3~65) winsize 63
4007 10:52:03.367479 [CA 5] Center 34 (3~65) winsize 63
4008 10:52:03.367555
4009 10:52:03.370969 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4010 10:52:03.371041
4011 10:52:03.374364 [CATrainingPosCal] consider 2 rank data
4012 10:52:03.377240 u2DelayCellTimex100 = 270/100 ps
4013 10:52:03.380934 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4014 10:52:03.387232 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4015 10:52:03.390427 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4016 10:52:03.393811 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4017 10:52:03.397261 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4018 10:52:03.400480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4019 10:52:03.400576
4020 10:52:03.403836 CA PerBit enable=1, Macro0, CA PI delay=33
4021 10:52:03.403908
4022 10:52:03.407173 [CBTSetCACLKResult] CA Dly = 33
4023 10:52:03.407255 CS Dly: 5 (0~37)
4024 10:52:03.410429
4025 10:52:03.414029 ----->DramcWriteLeveling(PI) begin...
4026 10:52:03.414100 ==
4027 10:52:03.416963 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 10:52:03.420689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 10:52:03.420838 ==
4030 10:52:03.423768 Write leveling (Byte 0): 34 => 34
4031 10:52:03.426964 Write leveling (Byte 1): 29 => 29
4032 10:52:03.430671 DramcWriteLeveling(PI) end<-----
4033 10:52:03.430746
4034 10:52:03.430808 ==
4035 10:52:03.433591 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 10:52:03.436999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 10:52:03.437084 ==
4038 10:52:03.440403 [Gating] SW mode calibration
4039 10:52:03.447253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 10:52:03.453426 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 10:52:03.456705 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 10:52:03.460178 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 10:52:03.466614 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 10:52:03.470166 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4045 10:52:03.473394 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
4046 10:52:03.479709 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 10:52:03.483344 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 10:52:03.486685 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 10:52:03.493343 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 10:52:03.496615 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 10:52:03.499904 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4052 10:52:03.506523 0 10 12 | B1->B0 | 2b2b 3a3a | 1 0 | (0 0) (1 1)
4053 10:52:03.509423 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
4054 10:52:03.512855 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 10:52:03.519587 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 10:52:03.522553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 10:52:03.525973 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 10:52:03.532916 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 10:52:03.536072 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4060 10:52:03.539323 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4061 10:52:03.545926 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 10:52:03.549364 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 10:52:03.552333 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 10:52:03.558697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 10:52:03.562365 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 10:52:03.565276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 10:52:03.572200 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 10:52:03.575330 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 10:52:03.578729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 10:52:03.585576 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 10:52:03.588773 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:52:03.591821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 10:52:03.598577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 10:52:03.601940 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 10:52:03.605012 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 10:52:03.611536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4077 10:52:03.615155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 10:52:03.618092 Total UI for P1: 0, mck2ui 16
4079 10:52:03.621588 best dqsien dly found for B0: ( 0, 13, 12)
4080 10:52:03.624970 Total UI for P1: 0, mck2ui 16
4081 10:52:03.628151 best dqsien dly found for B1: ( 0, 13, 14)
4082 10:52:03.631851 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4083 10:52:03.634934 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4084 10:52:03.635013
4085 10:52:03.637936 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4086 10:52:03.641299 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4087 10:52:03.644920 [Gating] SW calibration Done
4088 10:52:03.645034 ==
4089 10:52:03.648159 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 10:52:03.654513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 10:52:03.654601 ==
4092 10:52:03.654668 RX Vref Scan: 0
4093 10:52:03.654731
4094 10:52:03.658501 RX Vref 0 -> 0, step: 1
4095 10:52:03.658587
4096 10:52:03.661368 RX Delay -230 -> 252, step: 16
4097 10:52:03.664387 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4098 10:52:03.667856 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4099 10:52:03.671103 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4100 10:52:03.677605 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4101 10:52:03.680914 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4102 10:52:03.684479 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4103 10:52:03.687800 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4104 10:52:03.694125 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4105 10:52:03.697428 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4106 10:52:03.701040 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4107 10:52:03.703942 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4108 10:52:03.710765 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4109 10:52:03.713778 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4110 10:52:03.717082 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4111 10:52:03.720538 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4112 10:52:03.727451 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4113 10:52:03.727592 ==
4114 10:52:03.730668 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 10:52:03.733997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 10:52:03.734095 ==
4117 10:52:03.734163 DQS Delay:
4118 10:52:03.736948 DQS0 = 0, DQS1 = 0
4119 10:52:03.737064 DQM Delay:
4120 10:52:03.740271 DQM0 = 51, DQM1 = 37
4121 10:52:03.740359 DQ Delay:
4122 10:52:03.743797 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4123 10:52:03.746831 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4124 10:52:03.750400 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4125 10:52:03.753584 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4126 10:52:03.753684
4127 10:52:03.753765
4128 10:52:03.753825 ==
4129 10:52:03.756839 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 10:52:03.760197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 10:52:03.763096 ==
4132 10:52:03.763182
4133 10:52:03.763249
4134 10:52:03.763311 TX Vref Scan disable
4135 10:52:03.766540 == TX Byte 0 ==
4136 10:52:03.769898 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4137 10:52:03.772943 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4138 10:52:03.776437 == TX Byte 1 ==
4139 10:52:03.779778 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4140 10:52:03.783289 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4141 10:52:03.786261 ==
4142 10:52:03.789971 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 10:52:03.793214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 10:52:03.793299 ==
4145 10:52:03.793366
4146 10:52:03.793428
4147 10:52:03.796152 TX Vref Scan disable
4148 10:52:03.799805 == TX Byte 0 ==
4149 10:52:03.802692 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4150 10:52:03.806338 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4151 10:52:03.809350 == TX Byte 1 ==
4152 10:52:03.812537 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4153 10:52:03.816206 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4154 10:52:03.816292
4155 10:52:03.816357 [DATLAT]
4156 10:52:03.819125 Freq=600, CH0 RK0
4157 10:52:03.819211
4158 10:52:03.822441 DATLAT Default: 0x9
4159 10:52:03.822524 0, 0xFFFF, sum = 0
4160 10:52:03.826026 1, 0xFFFF, sum = 0
4161 10:52:03.826128 2, 0xFFFF, sum = 0
4162 10:52:03.829462 3, 0xFFFF, sum = 0
4163 10:52:03.829600 4, 0xFFFF, sum = 0
4164 10:52:03.832470 5, 0xFFFF, sum = 0
4165 10:52:03.832557 6, 0xFFFF, sum = 0
4166 10:52:03.835484 7, 0xFFFF, sum = 0
4167 10:52:03.835595 8, 0x0, sum = 1
4168 10:52:03.838928 9, 0x0, sum = 2
4169 10:52:03.839040 10, 0x0, sum = 3
4170 10:52:03.842310 11, 0x0, sum = 4
4171 10:52:03.842418 best_step = 9
4172 10:52:03.842509
4173 10:52:03.842601 ==
4174 10:52:03.845766 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 10:52:03.849157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 10:52:03.849247 ==
4177 10:52:03.852203 RX Vref Scan: 1
4178 10:52:03.852307
4179 10:52:03.855779 RX Vref 0 -> 0, step: 1
4180 10:52:03.855879
4181 10:52:03.855964 RX Delay -179 -> 252, step: 8
4182 10:52:03.856025
4183 10:52:03.858630 Set Vref, RX VrefLevel [Byte0]: 59
4184 10:52:03.861687 [Byte1]: 49
4185 10:52:03.866957
4186 10:52:03.867059 Final RX Vref Byte 0 = 59 to rank0
4187 10:52:03.869992 Final RX Vref Byte 1 = 49 to rank0
4188 10:52:03.873581 Final RX Vref Byte 0 = 59 to rank1
4189 10:52:03.877046 Final RX Vref Byte 1 = 49 to rank1==
4190 10:52:03.879914 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 10:52:03.886457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 10:52:03.886542 ==
4193 10:52:03.886608 DQS Delay:
4194 10:52:03.886670 DQS0 = 0, DQS1 = 0
4195 10:52:03.890001 DQM Delay:
4196 10:52:03.890084 DQM0 = 50, DQM1 = 39
4197 10:52:03.893260 DQ Delay:
4198 10:52:03.896547 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4199 10:52:03.899698 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4200 10:52:03.903190 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4201 10:52:03.906655 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4202 10:52:03.906738
4203 10:52:03.906804
4204 10:52:03.913078 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4205 10:52:03.916232 CH0 RK0: MR19=808, MR18=5D57
4206 10:52:03.922967 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4207 10:52:03.923052
4208 10:52:03.926203 ----->DramcWriteLeveling(PI) begin...
4209 10:52:03.926292 ==
4210 10:52:03.929782 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 10:52:03.932618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 10:52:03.932719 ==
4213 10:52:03.936061 Write leveling (Byte 0): 34 => 34
4214 10:52:03.939662 Write leveling (Byte 1): 29 => 29
4215 10:52:03.942788 DramcWriteLeveling(PI) end<-----
4216 10:52:03.942885
4217 10:52:03.942964 ==
4218 10:52:03.946150 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 10:52:03.949469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 10:52:03.952713 ==
4221 10:52:03.952817 [Gating] SW mode calibration
4222 10:52:03.959233 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 10:52:03.965762 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 10:52:03.969334 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 10:52:03.976115 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 10:52:03.979463 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 10:52:03.982762 0 9 12 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 1)
4228 10:52:03.989173 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4229 10:52:03.992676 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 10:52:03.995766 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 10:52:04.002267 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 10:52:04.005803 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 10:52:04.008960 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 10:52:04.015556 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 10:52:04.018914 0 10 12 | B1->B0 | 2929 2c2c | 1 0 | (0 0) (1 1)
4236 10:52:04.022291 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4237 10:52:04.029311 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 10:52:04.032110 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 10:52:04.035640 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 10:52:04.042190 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 10:52:04.045616 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 10:52:04.048662 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 10:52:04.055211 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4244 10:52:04.058634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 10:52:04.062215 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 10:52:04.068592 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 10:52:04.071831 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 10:52:04.075211 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 10:52:04.081845 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 10:52:04.085338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 10:52:04.088611 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:52:04.094728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 10:52:04.098168 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 10:52:04.101688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:52:04.108304 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:52:04.111275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 10:52:04.114942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 10:52:04.118236 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 10:52:04.124871 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4260 10:52:04.128339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4261 10:52:04.131454 Total UI for P1: 0, mck2ui 16
4262 10:52:04.134747 best dqsien dly found for B0: ( 0, 13, 12)
4263 10:52:04.138343 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 10:52:04.141784 Total UI for P1: 0, mck2ui 16
4265 10:52:04.144721 best dqsien dly found for B1: ( 0, 13, 14)
4266 10:52:04.148118 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4267 10:52:04.154461 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4268 10:52:04.154545
4269 10:52:04.158284 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4270 10:52:04.161381 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4271 10:52:04.164489 [Gating] SW calibration Done
4272 10:52:04.164572 ==
4273 10:52:04.167810 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 10:52:04.171022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 10:52:04.171106 ==
4276 10:52:04.174539 RX Vref Scan: 0
4277 10:52:04.174623
4278 10:52:04.174688 RX Vref 0 -> 0, step: 1
4279 10:52:04.174749
4280 10:52:04.177968 RX Delay -230 -> 252, step: 16
4281 10:52:04.180951 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4282 10:52:04.187651 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4283 10:52:04.190777 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4284 10:52:04.194193 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4285 10:52:04.197555 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4286 10:52:04.204108 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4287 10:52:04.207595 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4288 10:52:04.210735 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4289 10:52:04.213887 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4290 10:52:04.217442 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4291 10:52:04.223744 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4292 10:52:04.227181 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4293 10:52:04.230331 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4294 10:52:04.237163 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4295 10:52:04.240405 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4296 10:52:04.243602 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4297 10:52:04.243686 ==
4298 10:52:04.247038 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 10:52:04.249929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 10:52:04.250014 ==
4301 10:52:04.253449 DQS Delay:
4302 10:52:04.253532 DQS0 = 0, DQS1 = 0
4303 10:52:04.256750 DQM Delay:
4304 10:52:04.256855 DQM0 = 50, DQM1 = 44
4305 10:52:04.256921 DQ Delay:
4306 10:52:04.260013 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4307 10:52:04.263231 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4308 10:52:04.266569 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4309 10:52:04.270062 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4310 10:52:04.270146
4311 10:52:04.270212
4312 10:52:04.273363 ==
4313 10:52:04.276438 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 10:52:04.279801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 10:52:04.279886 ==
4316 10:52:04.279951
4317 10:52:04.280012
4318 10:52:04.283808 TX Vref Scan disable
4319 10:52:04.283892 == TX Byte 0 ==
4320 10:52:04.289551 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4321 10:52:04.292973 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4322 10:52:04.293056 == TX Byte 1 ==
4323 10:52:04.299638 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 10:52:04.302806 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 10:52:04.302891 ==
4326 10:52:04.306193 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 10:52:04.309361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 10:52:04.309445 ==
4329 10:52:04.309553
4330 10:52:04.309615
4331 10:52:04.312782 TX Vref Scan disable
4332 10:52:04.316036 == TX Byte 0 ==
4333 10:52:04.319475 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4334 10:52:04.326107 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4335 10:52:04.326195 == TX Byte 1 ==
4336 10:52:04.329185 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4337 10:52:04.335738 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4338 10:52:04.335826
4339 10:52:04.335910 [DATLAT]
4340 10:52:04.335974 Freq=600, CH0 RK1
4341 10:52:04.336034
4342 10:52:04.339392 DATLAT Default: 0x9
4343 10:52:04.339476 0, 0xFFFF, sum = 0
4344 10:52:04.342535 1, 0xFFFF, sum = 0
4345 10:52:04.345987 2, 0xFFFF, sum = 0
4346 10:52:04.346072 3, 0xFFFF, sum = 0
4347 10:52:04.349000 4, 0xFFFF, sum = 0
4348 10:52:04.349084 5, 0xFFFF, sum = 0
4349 10:52:04.352492 6, 0xFFFF, sum = 0
4350 10:52:04.352577 7, 0xFFFF, sum = 0
4351 10:52:04.355601 8, 0x0, sum = 1
4352 10:52:04.355687 9, 0x0, sum = 2
4353 10:52:04.355753 10, 0x0, sum = 3
4354 10:52:04.359268 11, 0x0, sum = 4
4355 10:52:04.359352 best_step = 9
4356 10:52:04.359418
4357 10:52:04.362334 ==
4358 10:52:04.362418 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 10:52:04.368693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 10:52:04.368787 ==
4361 10:52:04.368854 RX Vref Scan: 0
4362 10:52:04.368914
4363 10:52:04.372401 RX Vref 0 -> 0, step: 1
4364 10:52:04.372489
4365 10:52:04.375350 RX Delay -163 -> 252, step: 8
4366 10:52:04.378938 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4367 10:52:04.385421 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4368 10:52:04.388701 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4369 10:52:04.391790 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4370 10:52:04.395393 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4371 10:52:04.398657 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4372 10:52:04.405259 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4373 10:52:04.408782 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4374 10:52:04.411978 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4375 10:52:04.415586 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4376 10:52:04.421790 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4377 10:52:04.425294 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4378 10:52:04.428499 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4379 10:52:04.431762 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4380 10:52:04.435021 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4381 10:52:04.441660 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4382 10:52:04.441748 ==
4383 10:52:04.445255 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 10:52:04.448320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 10:52:04.448403 ==
4386 10:52:04.448467 DQS Delay:
4387 10:52:04.452085 DQS0 = 0, DQS1 = 0
4388 10:52:04.452167 DQM Delay:
4389 10:52:04.454909 DQM0 = 48, DQM1 = 41
4390 10:52:04.454991 DQ Delay:
4391 10:52:04.458395 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4392 10:52:04.461819 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4393 10:52:04.464701 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4394 10:52:04.468310 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4395 10:52:04.468391
4396 10:52:04.468455
4397 10:52:04.478241 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4398 10:52:04.478324 CH0 RK1: MR19=808, MR18=5E2D
4399 10:52:04.484728 CH0_RK1: MR19=0x808, MR18=0x5E2D, DQSOSC=392, MR23=63, INC=170, DEC=113
4400 10:52:04.487893 [RxdqsGatingPostProcess] freq 600
4401 10:52:04.494847 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 10:52:04.497760 Pre-setting of DQS Precalculation
4403 10:52:04.501162 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 10:52:04.501244 ==
4405 10:52:04.504635 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 10:52:04.510863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 10:52:04.510947 ==
4408 10:52:04.514388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 10:52:04.520876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4410 10:52:04.524140 [CA 0] Center 35 (5~66) winsize 62
4411 10:52:04.527506 [CA 1] Center 35 (5~66) winsize 62
4412 10:52:04.530817 [CA 2] Center 34 (4~65) winsize 62
4413 10:52:04.534093 [CA 3] Center 34 (3~65) winsize 63
4414 10:52:04.537703 [CA 4] Center 34 (4~65) winsize 62
4415 10:52:04.540797 [CA 5] Center 34 (3~65) winsize 63
4416 10:52:04.540921
4417 10:52:04.544231 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4418 10:52:04.544315
4419 10:52:04.547210 [CATrainingPosCal] consider 1 rank data
4420 10:52:04.550594 u2DelayCellTimex100 = 270/100 ps
4421 10:52:04.554031 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4422 10:52:04.557311 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4423 10:52:04.563631 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4424 10:52:04.567180 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4425 10:52:04.570291 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 10:52:04.573633 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4427 10:52:04.573717
4428 10:52:04.577017 CA PerBit enable=1, Macro0, CA PI delay=34
4429 10:52:04.577100
4430 10:52:04.580488 [CBTSetCACLKResult] CA Dly = 34
4431 10:52:04.580571 CS Dly: 4 (0~35)
4432 10:52:04.583657 ==
4433 10:52:04.583741 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 10:52:04.590222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 10:52:04.590307 ==
4436 10:52:04.593626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 10:52:04.600101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4438 10:52:04.603734 [CA 0] Center 36 (6~66) winsize 61
4439 10:52:04.607408 [CA 1] Center 35 (5~66) winsize 62
4440 10:52:04.610829 [CA 2] Center 34 (4~65) winsize 62
4441 10:52:04.613954 [CA 3] Center 34 (4~65) winsize 62
4442 10:52:04.617131 [CA 4] Center 34 (4~65) winsize 62
4443 10:52:04.620372 [CA 5] Center 34 (4~65) winsize 62
4444 10:52:04.620489
4445 10:52:04.623695 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4446 10:52:04.623809
4447 10:52:04.626878 [CATrainingPosCal] consider 2 rank data
4448 10:52:04.630495 u2DelayCellTimex100 = 270/100 ps
4449 10:52:04.633519 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4450 10:52:04.639979 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4451 10:52:04.643831 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4452 10:52:04.646890 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4453 10:52:04.650428 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4454 10:52:04.653361 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 10:52:04.653445
4456 10:52:04.656921 CA PerBit enable=1, Macro0, CA PI delay=34
4457 10:52:04.657006
4458 10:52:04.660222 [CBTSetCACLKResult] CA Dly = 34
4459 10:52:04.663478 CS Dly: 4 (0~36)
4460 10:52:04.663562
4461 10:52:04.666891 ----->DramcWriteLeveling(PI) begin...
4462 10:52:04.666976 ==
4463 10:52:04.670047 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 10:52:04.673072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 10:52:04.673196 ==
4466 10:52:04.676392 Write leveling (Byte 0): 31 => 31
4467 10:52:04.679607 Write leveling (Byte 1): 32 => 32
4468 10:52:04.683214 DramcWriteLeveling(PI) end<-----
4469 10:52:04.683299
4470 10:52:04.683365 ==
4471 10:52:04.686288 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 10:52:04.689529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 10:52:04.689613 ==
4474 10:52:04.693011 [Gating] SW mode calibration
4475 10:52:04.699661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 10:52:04.706043 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 10:52:04.709272 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 10:52:04.712702 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 10:52:04.719449 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 10:52:04.722735 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 1)
4481 10:52:04.725865 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 10:52:04.732588 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 10:52:04.735647 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 10:52:04.739113 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 10:52:04.745798 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 10:52:04.748890 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 10:52:04.752440 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 10:52:04.758779 0 10 12 | B1->B0 | 3f3f 3d3d | 0 0 | (0 0) (0 0)
4489 10:52:04.762241 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 10:52:04.765339 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 10:52:04.772206 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 10:52:04.775228 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 10:52:04.778676 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 10:52:04.785490 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 10:52:04.788615 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 10:52:04.791616 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4497 10:52:04.798711 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 10:52:04.801696 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 10:52:04.805114 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 10:52:04.811418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 10:52:04.814787 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 10:52:04.818593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 10:52:04.825005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 10:52:04.828155 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 10:52:04.831439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 10:52:04.838371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 10:52:04.841816 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 10:52:04.844721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 10:52:04.851455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 10:52:04.855093 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 10:52:04.858107 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 10:52:04.864996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 10:52:04.865082 Total UI for P1: 0, mck2ui 16
4514 10:52:04.871486 best dqsien dly found for B0: ( 0, 13, 10)
4515 10:52:04.871571 Total UI for P1: 0, mck2ui 16
4516 10:52:04.877864 best dqsien dly found for B1: ( 0, 13, 10)
4517 10:52:04.881475 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4518 10:52:04.884507 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4519 10:52:04.884591
4520 10:52:04.887814 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4521 10:52:04.891355 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4522 10:52:04.894333 [Gating] SW calibration Done
4523 10:52:04.894418 ==
4524 10:52:04.897879 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 10:52:04.901311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 10:52:04.901396 ==
4527 10:52:04.904386 RX Vref Scan: 0
4528 10:52:04.904469
4529 10:52:04.904534 RX Vref 0 -> 0, step: 1
4530 10:52:04.904595
4531 10:52:04.907847 RX Delay -230 -> 252, step: 16
4532 10:52:04.914118 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4533 10:52:04.917532 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4534 10:52:04.921012 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4535 10:52:04.924424 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4536 10:52:04.927658 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4537 10:52:04.934097 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4538 10:52:04.937448 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4539 10:52:04.940911 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4540 10:52:04.943888 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4541 10:52:04.950742 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4542 10:52:04.953747 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4543 10:52:04.957166 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4544 10:52:04.960463 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4545 10:52:04.966979 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4546 10:52:04.970501 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4547 10:52:04.973756 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4548 10:52:04.973840 ==
4549 10:52:04.976865 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 10:52:04.980427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 10:52:04.983435 ==
4552 10:52:04.983518 DQS Delay:
4553 10:52:04.983584 DQS0 = 0, DQS1 = 0
4554 10:52:04.986973 DQM Delay:
4555 10:52:04.987056 DQM0 = 52, DQM1 = 38
4556 10:52:04.990014 DQ Delay:
4557 10:52:04.990097 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4558 10:52:04.993392 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4559 10:52:04.996522 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4560 10:52:04.999841 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4561 10:52:04.999943
4562 10:52:05.003380
4563 10:52:05.003463 ==
4564 10:52:05.006533 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 10:52:05.010197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 10:52:05.010281 ==
4567 10:52:05.010347
4568 10:52:05.010408
4569 10:52:05.013251 TX Vref Scan disable
4570 10:52:05.013334 == TX Byte 0 ==
4571 10:52:05.019985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4572 10:52:05.023344 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4573 10:52:05.023429 == TX Byte 1 ==
4574 10:52:05.029974 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4575 10:52:05.033074 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4576 10:52:05.033158 ==
4577 10:52:05.036418 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 10:52:05.039872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 10:52:05.039957 ==
4580 10:52:05.040023
4581 10:52:05.040088
4582 10:52:05.043002 TX Vref Scan disable
4583 10:52:05.046435 == TX Byte 0 ==
4584 10:52:05.049543 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 10:52:05.053024 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 10:52:05.056447 == TX Byte 1 ==
4587 10:52:05.059454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4588 10:52:05.062908 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4589 10:52:05.065980
4590 10:52:05.066064 [DATLAT]
4591 10:52:05.066130 Freq=600, CH1 RK0
4592 10:52:05.066192
4593 10:52:05.069570 DATLAT Default: 0x9
4594 10:52:05.069653 0, 0xFFFF, sum = 0
4595 10:52:05.072796 1, 0xFFFF, sum = 0
4596 10:52:05.072908 2, 0xFFFF, sum = 0
4597 10:52:05.075920 3, 0xFFFF, sum = 0
4598 10:52:05.076005 4, 0xFFFF, sum = 0
4599 10:52:05.079452 5, 0xFFFF, sum = 0
4600 10:52:05.082752 6, 0xFFFF, sum = 0
4601 10:52:05.082837 7, 0xFFFF, sum = 0
4602 10:52:05.085889 8, 0x0, sum = 1
4603 10:52:05.085977 9, 0x0, sum = 2
4604 10:52:05.086043 10, 0x0, sum = 3
4605 10:52:05.089105 11, 0x0, sum = 4
4606 10:52:05.089190 best_step = 9
4607 10:52:05.089256
4608 10:52:05.089316 ==
4609 10:52:05.092506 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 10:52:05.099129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 10:52:05.099215 ==
4612 10:52:05.099281 RX Vref Scan: 1
4613 10:52:05.099342
4614 10:52:05.102719 RX Vref 0 -> 0, step: 1
4615 10:52:05.102803
4616 10:52:05.105591 RX Delay -179 -> 252, step: 8
4617 10:52:05.105674
4618 10:52:05.108947 Set Vref, RX VrefLevel [Byte0]: 51
4619 10:52:05.112225 [Byte1]: 57
4620 10:52:05.112309
4621 10:52:05.115569 Final RX Vref Byte 0 = 51 to rank0
4622 10:52:05.118758 Final RX Vref Byte 1 = 57 to rank0
4623 10:52:05.122091 Final RX Vref Byte 0 = 51 to rank1
4624 10:52:05.125586 Final RX Vref Byte 1 = 57 to rank1==
4625 10:52:05.128669 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 10:52:05.132065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 10:52:05.132150 ==
4628 10:52:05.135531 DQS Delay:
4629 10:52:05.135614 DQS0 = 0, DQS1 = 0
4630 10:52:05.138683 DQM Delay:
4631 10:52:05.138766 DQM0 = 47, DQM1 = 40
4632 10:52:05.138832 DQ Delay:
4633 10:52:05.142148 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4634 10:52:05.145422 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4635 10:52:05.148772 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4636 10:52:05.152240 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4637 10:52:05.152324
4638 10:52:05.152389
4639 10:52:05.162025 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4640 10:52:05.165003 CH1 RK0: MR19=808, MR18=4B71
4641 10:52:05.171419 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4642 10:52:05.171505
4643 10:52:05.174848 ----->DramcWriteLeveling(PI) begin...
4644 10:52:05.174935 ==
4645 10:52:05.178231 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 10:52:05.181716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 10:52:05.181800 ==
4648 10:52:05.184673 Write leveling (Byte 0): 29 => 29
4649 10:52:05.188010 Write leveling (Byte 1): 30 => 30
4650 10:52:05.191377 DramcWriteLeveling(PI) end<-----
4651 10:52:05.191461
4652 10:52:05.191526 ==
4653 10:52:05.194858 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 10:52:05.198373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 10:52:05.198457 ==
4656 10:52:05.201316 [Gating] SW mode calibration
4657 10:52:05.207970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4658 10:52:05.214597 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4659 10:52:05.217643 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 10:52:05.221270 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 10:52:05.227680 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 10:52:05.230899 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
4663 10:52:05.234192 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 10:52:05.240700 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 10:52:05.244113 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 10:52:05.247470 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 10:52:05.254287 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 10:52:05.257476 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 10:52:05.260629 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 10:52:05.267205 0 10 12 | B1->B0 | 3939 2c2c | 0 0 | (0 0) (0 0)
4671 10:52:05.270488 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
4672 10:52:05.273978 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 10:52:05.280297 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 10:52:05.283745 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 10:52:05.287027 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 10:52:05.293567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 10:52:05.296703 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4678 10:52:05.303596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4679 10:52:05.306932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 10:52:05.310019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 10:52:05.316736 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 10:52:05.319704 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 10:52:05.323104 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 10:52:05.329580 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 10:52:05.333330 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 10:52:05.336291 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 10:52:05.342744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 10:52:05.346131 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 10:52:05.349626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:52:05.356004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 10:52:05.359528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 10:52:05.362628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 10:52:05.369028 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 10:52:05.372607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 10:52:05.375922 Total UI for P1: 0, mck2ui 16
4696 10:52:05.379354 best dqsien dly found for B0: ( 0, 13, 10)
4697 10:52:05.382391 Total UI for P1: 0, mck2ui 16
4698 10:52:05.385885 best dqsien dly found for B1: ( 0, 13, 10)
4699 10:52:05.388870 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4700 10:52:05.392578 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4701 10:52:05.392662
4702 10:52:05.395522 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4703 10:52:05.398896 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4704 10:52:05.402254 [Gating] SW calibration Done
4705 10:52:05.402338 ==
4706 10:52:05.405425 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 10:52:05.408945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 10:52:05.412007 ==
4709 10:52:05.412090 RX Vref Scan: 0
4710 10:52:05.412156
4711 10:52:05.415518 RX Vref 0 -> 0, step: 1
4712 10:52:05.415601
4713 10:52:05.418465 RX Delay -230 -> 252, step: 16
4714 10:52:05.422216 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4715 10:52:05.425152 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4716 10:52:05.428581 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4717 10:52:05.435441 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4718 10:52:05.438551 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4719 10:52:05.441884 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4720 10:52:05.445205 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4721 10:52:05.448719 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4722 10:52:05.455474 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4723 10:52:05.458357 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4724 10:52:05.461695 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4725 10:52:05.465030 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4726 10:52:05.468524 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4727 10:52:05.475420 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4728 10:52:05.478544 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4729 10:52:05.481428 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4730 10:52:05.481512 ==
4731 10:52:05.484669 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 10:52:05.491584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 10:52:05.491667 ==
4734 10:52:05.491733 DQS Delay:
4735 10:52:05.494891 DQS0 = 0, DQS1 = 0
4736 10:52:05.494973 DQM Delay:
4737 10:52:05.495039 DQM0 = 52, DQM1 = 45
4738 10:52:05.498028 DQ Delay:
4739 10:52:05.501253 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4740 10:52:05.504880 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4741 10:52:05.508187 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4742 10:52:05.511114 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4743 10:52:05.511198
4744 10:52:05.511263
4745 10:52:05.511323 ==
4746 10:52:05.514364 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 10:52:05.517713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 10:52:05.517836 ==
4749 10:52:05.517943
4750 10:52:05.518052
4751 10:52:05.521163 TX Vref Scan disable
4752 10:52:05.524440 == TX Byte 0 ==
4753 10:52:05.527556 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4754 10:52:05.531056 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4755 10:52:05.534286 == TX Byte 1 ==
4756 10:52:05.537278 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4757 10:52:05.540691 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4758 10:52:05.540797 ==
4759 10:52:05.544714 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 10:52:05.550565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 10:52:05.550652 ==
4762 10:52:05.550719
4763 10:52:05.550779
4764 10:52:05.550837 TX Vref Scan disable
4765 10:52:05.554577 == TX Byte 0 ==
4766 10:52:05.558104 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4767 10:52:05.564446 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4768 10:52:05.564531 == TX Byte 1 ==
4769 10:52:05.567873 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4770 10:52:05.574449 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4771 10:52:05.574533
4772 10:52:05.574599 [DATLAT]
4773 10:52:05.574661 Freq=600, CH1 RK1
4774 10:52:05.574720
4775 10:52:05.577749 DATLAT Default: 0x9
4776 10:52:05.580871 0, 0xFFFF, sum = 0
4777 10:52:05.580955 1, 0xFFFF, sum = 0
4778 10:52:05.584133 2, 0xFFFF, sum = 0
4779 10:52:05.584216 3, 0xFFFF, sum = 0
4780 10:52:05.587436 4, 0xFFFF, sum = 0
4781 10:52:05.587521 5, 0xFFFF, sum = 0
4782 10:52:05.590857 6, 0xFFFF, sum = 0
4783 10:52:05.590941 7, 0xFFFF, sum = 0
4784 10:52:05.594400 8, 0x0, sum = 1
4785 10:52:05.594511 9, 0x0, sum = 2
4786 10:52:05.594608 10, 0x0, sum = 3
4787 10:52:05.597536 11, 0x0, sum = 4
4788 10:52:05.597619 best_step = 9
4789 10:52:05.597684
4790 10:52:05.600934 ==
4791 10:52:05.601017 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 10:52:05.607359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 10:52:05.607443 ==
4794 10:52:05.607508 RX Vref Scan: 0
4795 10:52:05.607569
4796 10:52:05.610666 RX Vref 0 -> 0, step: 1
4797 10:52:05.610749
4798 10:52:05.614425 RX Delay -179 -> 252, step: 8
4799 10:52:05.617424 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4800 10:52:05.623993 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4801 10:52:05.627287 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4802 10:52:05.631103 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4803 10:52:05.633866 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4804 10:52:05.640654 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4805 10:52:05.643768 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4806 10:52:05.646791 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4807 10:52:05.650209 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4808 10:52:05.653794 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4809 10:52:05.660207 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4810 10:52:05.663611 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4811 10:52:05.666854 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4812 10:52:05.669896 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4813 10:52:05.676676 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4814 10:52:05.679868 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4815 10:52:05.679952 ==
4816 10:52:05.683026 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 10:52:05.686468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 10:52:05.686552 ==
4819 10:52:05.689733 DQS Delay:
4820 10:52:05.689816 DQS0 = 0, DQS1 = 0
4821 10:52:05.689882 DQM Delay:
4822 10:52:05.693015 DQM0 = 48, DQM1 = 43
4823 10:52:05.693098 DQ Delay:
4824 10:52:05.696189 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4825 10:52:05.699639 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4826 10:52:05.702913 DQ8 =28, DQ9 =36, DQ10 =40, DQ11 =40
4827 10:52:05.706100 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4828 10:52:05.706183
4829 10:52:05.706248
4830 10:52:05.716131 [DQSOSCAuto] RK1, (LSB)MR18= 0x561c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4831 10:52:05.719079 CH1 RK1: MR19=808, MR18=561C
4832 10:52:05.722823 CH1_RK1: MR19=0x808, MR18=0x561C, DQSOSC=393, MR23=63, INC=169, DEC=113
4833 10:52:05.726077 [RxdqsGatingPostProcess] freq 600
4834 10:52:05.732400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4835 10:52:05.735678 Pre-setting of DQS Precalculation
4836 10:52:05.739388 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4837 10:52:05.749024 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4838 10:52:05.755702 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4839 10:52:05.755787
4840 10:52:05.755852
4841 10:52:05.759466 [Calibration Summary] 1200 Mbps
4842 10:52:05.759550 CH 0, Rank 0
4843 10:52:05.762518 SW Impedance : PASS
4844 10:52:05.762601 DUTY Scan : NO K
4845 10:52:05.765488 ZQ Calibration : PASS
4846 10:52:05.768913 Jitter Meter : NO K
4847 10:52:05.768997 CBT Training : PASS
4848 10:52:05.772079 Write leveling : PASS
4849 10:52:05.775470 RX DQS gating : PASS
4850 10:52:05.775554 RX DQ/DQS(RDDQC) : PASS
4851 10:52:05.778737 TX DQ/DQS : PASS
4852 10:52:05.782133 RX DATLAT : PASS
4853 10:52:05.782216 RX DQ/DQS(Engine): PASS
4854 10:52:05.785366 TX OE : NO K
4855 10:52:05.785449 All Pass.
4856 10:52:05.785514
4857 10:52:05.788516 CH 0, Rank 1
4858 10:52:05.788599 SW Impedance : PASS
4859 10:52:05.791930 DUTY Scan : NO K
4860 10:52:05.795356 ZQ Calibration : PASS
4861 10:52:05.795457 Jitter Meter : NO K
4862 10:52:05.798389 CBT Training : PASS
4863 10:52:05.801893 Write leveling : PASS
4864 10:52:05.801976 RX DQS gating : PASS
4865 10:52:05.805011 RX DQ/DQS(RDDQC) : PASS
4866 10:52:05.808323 TX DQ/DQS : PASS
4867 10:52:05.808406 RX DATLAT : PASS
4868 10:52:05.811945 RX DQ/DQS(Engine): PASS
4869 10:52:05.812028 TX OE : NO K
4870 10:52:05.814957 All Pass.
4871 10:52:05.815040
4872 10:52:05.815105 CH 1, Rank 0
4873 10:52:05.818095 SW Impedance : PASS
4874 10:52:05.821702 DUTY Scan : NO K
4875 10:52:05.821785 ZQ Calibration : PASS
4876 10:52:05.824735 Jitter Meter : NO K
4877 10:52:05.824822 CBT Training : PASS
4878 10:52:05.828281 Write leveling : PASS
4879 10:52:05.831368 RX DQS gating : PASS
4880 10:52:05.831452 RX DQ/DQS(RDDQC) : PASS
4881 10:52:05.835119 TX DQ/DQS : PASS
4882 10:52:05.838069 RX DATLAT : PASS
4883 10:52:05.838152 RX DQ/DQS(Engine): PASS
4884 10:52:05.841454 TX OE : NO K
4885 10:52:05.841538 All Pass.
4886 10:52:05.841603
4887 10:52:05.844710 CH 1, Rank 1
4888 10:52:05.844831 SW Impedance : PASS
4889 10:52:05.848063 DUTY Scan : NO K
4890 10:52:05.851195 ZQ Calibration : PASS
4891 10:52:05.851279 Jitter Meter : NO K
4892 10:52:05.854496 CBT Training : PASS
4893 10:52:05.857845 Write leveling : PASS
4894 10:52:05.857928 RX DQS gating : PASS
4895 10:52:05.861472 RX DQ/DQS(RDDQC) : PASS
4896 10:52:05.864944 TX DQ/DQS : PASS
4897 10:52:05.865027 RX DATLAT : PASS
4898 10:52:05.868030 RX DQ/DQS(Engine): PASS
4899 10:52:05.871185 TX OE : NO K
4900 10:52:05.871269 All Pass.
4901 10:52:05.871334
4902 10:52:05.871394 DramC Write-DBI off
4903 10:52:05.874500 PER_BANK_REFRESH: Hybrid Mode
4904 10:52:05.877948 TX_TRACKING: ON
4905 10:52:05.884483 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4906 10:52:05.887688 [FAST_K] Save calibration result to emmc
4907 10:52:05.894217 dramc_set_vcore_voltage set vcore to 662500
4908 10:52:05.894300 Read voltage for 933, 3
4909 10:52:05.897619 Vio18 = 0
4910 10:52:05.897703 Vcore = 662500
4911 10:52:05.897768 Vdram = 0
4912 10:52:05.900952 Vddq = 0
4913 10:52:05.901035 Vmddr = 0
4914 10:52:05.904467 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4915 10:52:05.911192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4916 10:52:05.914509 MEM_TYPE=3, freq_sel=17
4917 10:52:05.914592 sv_algorithm_assistance_LP4_1600
4918 10:52:05.920719 ============ PULL DRAM RESETB DOWN ============
4919 10:52:05.924201 ========== PULL DRAM RESETB DOWN end =========
4920 10:52:05.927335 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4921 10:52:05.930823 ===================================
4922 10:52:05.933856 LPDDR4 DRAM CONFIGURATION
4923 10:52:05.937061 ===================================
4924 10:52:05.940474 EX_ROW_EN[0] = 0x0
4925 10:52:05.940557 EX_ROW_EN[1] = 0x0
4926 10:52:05.943880 LP4Y_EN = 0x0
4927 10:52:05.943963 WORK_FSP = 0x0
4928 10:52:05.947061 WL = 0x3
4929 10:52:05.947144 RL = 0x3
4930 10:52:05.950557 BL = 0x2
4931 10:52:05.950640 RPST = 0x0
4932 10:52:05.953573 RD_PRE = 0x0
4933 10:52:05.957100 WR_PRE = 0x1
4934 10:52:05.957182 WR_PST = 0x0
4935 10:52:05.960493 DBI_WR = 0x0
4936 10:52:05.960576 DBI_RD = 0x0
4937 10:52:05.963674 OTF = 0x1
4938 10:52:05.967058 ===================================
4939 10:52:05.970283 ===================================
4940 10:52:05.970366 ANA top config
4941 10:52:05.973679 ===================================
4942 10:52:05.977101 DLL_ASYNC_EN = 0
4943 10:52:05.980336 ALL_SLAVE_EN = 1
4944 10:52:05.980419 NEW_RANK_MODE = 1
4945 10:52:05.983350 DLL_IDLE_MODE = 1
4946 10:52:05.986830 LP45_APHY_COMB_EN = 1
4947 10:52:05.989905 TX_ODT_DIS = 1
4948 10:52:05.989989 NEW_8X_MODE = 1
4949 10:52:05.993642 ===================================
4950 10:52:05.996702 ===================================
4951 10:52:06.000247 data_rate = 1866
4952 10:52:06.003222 CKR = 1
4953 10:52:06.006659 DQ_P2S_RATIO = 8
4954 10:52:06.010180 ===================================
4955 10:52:06.013380 CA_P2S_RATIO = 8
4956 10:52:06.016703 DQ_CA_OPEN = 0
4957 10:52:06.016822 DQ_SEMI_OPEN = 0
4958 10:52:06.020114 CA_SEMI_OPEN = 0
4959 10:52:06.023470 CA_FULL_RATE = 0
4960 10:52:06.026534 DQ_CKDIV4_EN = 1
4961 10:52:06.030044 CA_CKDIV4_EN = 1
4962 10:52:06.033326 CA_PREDIV_EN = 0
4963 10:52:06.033409 PH8_DLY = 0
4964 10:52:06.036523 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4965 10:52:06.039858 DQ_AAMCK_DIV = 4
4966 10:52:06.042961 CA_AAMCK_DIV = 4
4967 10:52:06.046501 CA_ADMCK_DIV = 4
4968 10:52:06.049673 DQ_TRACK_CA_EN = 0
4969 10:52:06.052790 CA_PICK = 933
4970 10:52:06.052887 CA_MCKIO = 933
4971 10:52:06.056244 MCKIO_SEMI = 0
4972 10:52:06.059773 PLL_FREQ = 3732
4973 10:52:06.063063 DQ_UI_PI_RATIO = 32
4974 10:52:06.066726 CA_UI_PI_RATIO = 0
4975 10:52:06.069584 ===================================
4976 10:52:06.072748 ===================================
4977 10:52:06.075860 memory_type:LPDDR4
4978 10:52:06.075943 GP_NUM : 10
4979 10:52:06.079225 SRAM_EN : 1
4980 10:52:06.079309 MD32_EN : 0
4981 10:52:06.082626 ===================================
4982 10:52:06.085828 [ANA_INIT] >>>>>>>>>>>>>>
4983 10:52:06.089235 <<<<<< [CONFIGURE PHASE]: ANA_TX
4984 10:52:06.092704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4985 10:52:06.096040 ===================================
4986 10:52:06.099105 data_rate = 1866,PCW = 0X8f00
4987 10:52:06.102486 ===================================
4988 10:52:06.105685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4989 10:52:06.112530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 10:52:06.115916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 10:52:06.121978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4992 10:52:06.125730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4993 10:52:06.128662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4994 10:52:06.128792 [ANA_INIT] flow start
4995 10:52:06.132141 [ANA_INIT] PLL >>>>>>>>
4996 10:52:06.135513 [ANA_INIT] PLL <<<<<<<<
4997 10:52:06.138984 [ANA_INIT] MIDPI >>>>>>>>
4998 10:52:06.139067 [ANA_INIT] MIDPI <<<<<<<<
4999 10:52:06.142001 [ANA_INIT] DLL >>>>>>>>
5000 10:52:06.142085 [ANA_INIT] flow end
5001 10:52:06.148513 ============ LP4 DIFF to SE enter ============
5002 10:52:06.151755 ============ LP4 DIFF to SE exit ============
5003 10:52:06.155259 [ANA_INIT] <<<<<<<<<<<<<
5004 10:52:06.158793 [Flow] Enable top DCM control >>>>>
5005 10:52:06.161751 [Flow] Enable top DCM control <<<<<
5006 10:52:06.165252 Enable DLL master slave shuffle
5007 10:52:06.168127 ==============================================================
5008 10:52:06.171661 Gating Mode config
5009 10:52:06.178337 ==============================================================
5010 10:52:06.178424 Config description:
5011 10:52:06.188319 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5012 10:52:06.194445 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5013 10:52:06.197873 SELPH_MODE 0: By rank 1: By Phase
5014 10:52:06.204422 ==============================================================
5015 10:52:06.207841 GAT_TRACK_EN = 1
5016 10:52:06.211161 RX_GATING_MODE = 2
5017 10:52:06.214601 RX_GATING_TRACK_MODE = 2
5018 10:52:06.217653 SELPH_MODE = 1
5019 10:52:06.221108 PICG_EARLY_EN = 1
5020 10:52:06.224197 VALID_LAT_VALUE = 1
5021 10:52:06.227775 ==============================================================
5022 10:52:06.230786 Enter into Gating configuration >>>>
5023 10:52:06.234029 Exit from Gating configuration <<<<
5024 10:52:06.237767 Enter into DVFS_PRE_config >>>>>
5025 10:52:06.250923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5026 10:52:06.253977 Exit from DVFS_PRE_config <<<<<
5027 10:52:06.254062 Enter into PICG configuration >>>>
5028 10:52:06.257424 Exit from PICG configuration <<<<
5029 10:52:06.260915 [RX_INPUT] configuration >>>>>
5030 10:52:06.263828 [RX_INPUT] configuration <<<<<
5031 10:52:06.270650 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5032 10:52:06.274100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5033 10:52:06.280690 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 10:52:06.286849 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 10:52:06.293585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 10:52:06.300317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 10:52:06.303513 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5038 10:52:06.306938 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5039 10:52:06.313337 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5040 10:52:06.316696 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5041 10:52:06.320173 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5042 10:52:06.323440 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 10:52:06.326705 ===================================
5044 10:52:06.330263 LPDDR4 DRAM CONFIGURATION
5045 10:52:06.333257 ===================================
5046 10:52:06.336557 EX_ROW_EN[0] = 0x0
5047 10:52:06.336642 EX_ROW_EN[1] = 0x0
5048 10:52:06.339911 LP4Y_EN = 0x0
5049 10:52:06.339996 WORK_FSP = 0x0
5050 10:52:06.343119 WL = 0x3
5051 10:52:06.343204 RL = 0x3
5052 10:52:06.346619 BL = 0x2
5053 10:52:06.346703 RPST = 0x0
5054 10:52:06.349636 RD_PRE = 0x0
5055 10:52:06.349720 WR_PRE = 0x1
5056 10:52:06.353110 WR_PST = 0x0
5057 10:52:06.356664 DBI_WR = 0x0
5058 10:52:06.356780 DBI_RD = 0x0
5059 10:52:06.359480 OTF = 0x1
5060 10:52:06.362909 ===================================
5061 10:52:06.366068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5062 10:52:06.369922 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5063 10:52:06.372785 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 10:52:06.376155 ===================================
5065 10:52:06.379559 LPDDR4 DRAM CONFIGURATION
5066 10:52:06.382834 ===================================
5067 10:52:06.386291 EX_ROW_EN[0] = 0x10
5068 10:52:06.386374 EX_ROW_EN[1] = 0x0
5069 10:52:06.389608 LP4Y_EN = 0x0
5070 10:52:06.389692 WORK_FSP = 0x0
5071 10:52:06.392962 WL = 0x3
5072 10:52:06.393045 RL = 0x3
5073 10:52:06.395840 BL = 0x2
5074 10:52:06.395924 RPST = 0x0
5075 10:52:06.399316 RD_PRE = 0x0
5076 10:52:06.399400 WR_PRE = 0x1
5077 10:52:06.402713 WR_PST = 0x0
5078 10:52:06.405747 DBI_WR = 0x0
5079 10:52:06.405830 DBI_RD = 0x0
5080 10:52:06.409074 OTF = 0x1
5081 10:52:06.412449 ===================================
5082 10:52:06.415658 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5083 10:52:06.420758 nWR fixed to 30
5084 10:52:06.424342 [ModeRegInit_LP4] CH0 RK0
5085 10:52:06.424426 [ModeRegInit_LP4] CH0 RK1
5086 10:52:06.427573 [ModeRegInit_LP4] CH1 RK0
5087 10:52:06.430973 [ModeRegInit_LP4] CH1 RK1
5088 10:52:06.431057 match AC timing 9
5089 10:52:06.437688 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5090 10:52:06.440856 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5091 10:52:06.443825 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5092 10:52:06.450515 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5093 10:52:06.453951 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5094 10:52:06.454035 ==
5095 10:52:06.457086 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 10:52:06.460408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 10:52:06.460494 ==
5098 10:52:06.467252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 10:52:06.473624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 10:52:06.476870 [CA 0] Center 38 (7~69) winsize 63
5101 10:52:06.480257 [CA 1] Center 38 (8~69) winsize 62
5102 10:52:06.483375 [CA 2] Center 35 (5~65) winsize 61
5103 10:52:06.486924 [CA 3] Center 34 (4~65) winsize 62
5104 10:52:06.490214 [CA 4] Center 34 (4~65) winsize 62
5105 10:52:06.493288 [CA 5] Center 33 (3~64) winsize 62
5106 10:52:06.493372
5107 10:52:06.496696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 10:52:06.496823
5109 10:52:06.500062 [CATrainingPosCal] consider 1 rank data
5110 10:52:06.503310 u2DelayCellTimex100 = 270/100 ps
5111 10:52:06.506717 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5112 10:52:06.510017 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5113 10:52:06.513556 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5114 10:52:06.519887 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5115 10:52:06.523292 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5116 10:52:06.526518 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5117 10:52:06.526603
5118 10:52:06.529986 CA PerBit enable=1, Macro0, CA PI delay=33
5119 10:52:06.530070
5120 10:52:06.533067 [CBTSetCACLKResult] CA Dly = 33
5121 10:52:06.533151 CS Dly: 7 (0~38)
5122 10:52:06.533216 ==
5123 10:52:06.536442 Dram Type= 6, Freq= 0, CH_0, rank 1
5124 10:52:06.543051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 10:52:06.543137 ==
5126 10:52:06.546309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 10:52:06.552953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5128 10:52:06.556336 [CA 0] Center 38 (8~69) winsize 62
5129 10:52:06.559673 [CA 1] Center 38 (8~69) winsize 62
5130 10:52:06.562690 [CA 2] Center 36 (6~66) winsize 61
5131 10:52:06.565983 [CA 3] Center 35 (5~66) winsize 62
5132 10:52:06.569370 [CA 4] Center 34 (4~65) winsize 62
5133 10:52:06.572599 [CA 5] Center 34 (4~64) winsize 61
5134 10:52:06.572697
5135 10:52:06.576006 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5136 10:52:06.576090
5137 10:52:06.579295 [CATrainingPosCal] consider 2 rank data
5138 10:52:06.582714 u2DelayCellTimex100 = 270/100 ps
5139 10:52:06.585854 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5140 10:52:06.592447 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5141 10:52:06.595929 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5142 10:52:06.598992 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5143 10:52:06.602467 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5144 10:52:06.605707 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5145 10:52:06.605790
5146 10:52:06.609341 CA PerBit enable=1, Macro0, CA PI delay=34
5147 10:52:06.609425
5148 10:52:06.612119 [CBTSetCACLKResult] CA Dly = 34
5149 10:52:06.615462 CS Dly: 7 (0~39)
5150 10:52:06.615546
5151 10:52:06.618826 ----->DramcWriteLeveling(PI) begin...
5152 10:52:06.618911 ==
5153 10:52:06.622247 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 10:52:06.625466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 10:52:06.625551 ==
5156 10:52:06.628820 Write leveling (Byte 0): 32 => 32
5157 10:52:06.632293 Write leveling (Byte 1): 31 => 31
5158 10:52:06.635208 DramcWriteLeveling(PI) end<-----
5159 10:52:06.635292
5160 10:52:06.635358 ==
5161 10:52:06.638880 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 10:52:06.641810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 10:52:06.641894 ==
5164 10:52:06.645117 [Gating] SW mode calibration
5165 10:52:06.651733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 10:52:06.658569 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5167 10:52:06.661691 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5168 10:52:06.665032 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 10:52:06.671699 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 10:52:06.674895 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 10:52:06.678564 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 10:52:06.684943 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 10:52:06.688414 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5174 10:52:06.691416 0 14 28 | B1->B0 | 3131 2525 | 0 0 | (0 1) (1 1)
5175 10:52:06.698010 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5176 10:52:06.701062 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 10:52:06.704583 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 10:52:06.710886 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 10:52:06.714153 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 10:52:06.717625 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 10:52:06.724241 0 15 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5182 10:52:06.727441 0 15 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5183 10:52:06.730862 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5184 10:52:06.737495 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 10:52:06.741307 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 10:52:06.744240 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 10:52:06.750861 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 10:52:06.754272 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 10:52:06.757423 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 10:52:06.764135 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5191 10:52:06.767285 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5192 10:52:06.770756 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 10:52:06.777395 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 10:52:06.780551 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 10:52:06.783559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 10:52:06.790256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 10:52:06.793593 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 10:52:06.797065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 10:52:06.803692 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 10:52:06.807242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 10:52:06.810231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 10:52:06.816586 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 10:52:06.819973 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 10:52:06.823539 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5205 10:52:06.830251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5206 10:52:06.833122 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5207 10:52:06.836491 Total UI for P1: 0, mck2ui 16
5208 10:52:06.840415 best dqsien dly found for B0: ( 1, 2, 22)
5209 10:52:06.843262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 10:52:06.846602 Total UI for P1: 0, mck2ui 16
5211 10:52:06.849926 best dqsien dly found for B1: ( 1, 2, 30)
5212 10:52:06.853001 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5213 10:52:06.856652 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5214 10:52:06.856747
5215 10:52:06.863025 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5216 10:52:06.866391 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5217 10:52:06.869934 [Gating] SW calibration Done
5218 10:52:06.870017 ==
5219 10:52:06.873020 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 10:52:06.876220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 10:52:06.876319 ==
5222 10:52:06.876384 RX Vref Scan: 0
5223 10:52:06.876444
5224 10:52:06.879776 RX Vref 0 -> 0, step: 1
5225 10:52:06.879860
5226 10:52:06.883077 RX Delay -80 -> 252, step: 8
5227 10:52:06.886098 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5228 10:52:06.889541 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5229 10:52:06.896037 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5230 10:52:06.899347 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5231 10:52:06.902567 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5232 10:52:06.906032 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5233 10:52:06.909389 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5234 10:52:06.915904 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5235 10:52:06.919444 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5236 10:52:06.922253 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5237 10:52:06.925871 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5238 10:52:06.929162 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5239 10:52:06.935430 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5240 10:52:06.939078 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5241 10:52:06.942214 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5242 10:52:06.945389 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5243 10:52:06.945503 ==
5244 10:52:06.948540 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 10:52:06.955556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 10:52:06.955662 ==
5247 10:52:06.955730 DQS Delay:
5248 10:52:06.955791 DQS0 = 0, DQS1 = 0
5249 10:52:06.958460 DQM Delay:
5250 10:52:06.958556 DQM0 = 107, DQM1 = 92
5251 10:52:06.961976 DQ Delay:
5252 10:52:06.965420 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5253 10:52:06.968500 DQ4 =107, DQ5 =103, DQ6 =115, DQ7 =115
5254 10:52:06.971419 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5255 10:52:06.974792 DQ12 =95, DQ13 =95, DQ14 =103, DQ15 =103
5256 10:52:06.974875
5257 10:52:06.974941
5258 10:52:06.975001 ==
5259 10:52:06.978388 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 10:52:06.981524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 10:52:06.981608 ==
5262 10:52:06.981673
5263 10:52:06.984704
5264 10:52:06.984807 TX Vref Scan disable
5265 10:52:06.988297 == TX Byte 0 ==
5266 10:52:06.991302 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5267 10:52:06.994699 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5268 10:52:06.997893 == TX Byte 1 ==
5269 10:52:07.001070 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5270 10:52:07.004487 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5271 10:52:07.004601 ==
5272 10:52:07.007804 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 10:52:07.014451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 10:52:07.014535 ==
5275 10:52:07.014601
5276 10:52:07.014662
5277 10:52:07.014720 TX Vref Scan disable
5278 10:52:07.018826 == TX Byte 0 ==
5279 10:52:07.021914 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5280 10:52:07.028718 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5281 10:52:07.028835 == TX Byte 1 ==
5282 10:52:07.032019 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5283 10:52:07.038454 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5284 10:52:07.038539
5285 10:52:07.038605 [DATLAT]
5286 10:52:07.038666 Freq=933, CH0 RK0
5287 10:52:07.038725
5288 10:52:07.042051 DATLAT Default: 0xd
5289 10:52:07.042135 0, 0xFFFF, sum = 0
5290 10:52:07.044900 1, 0xFFFF, sum = 0
5291 10:52:07.048214 2, 0xFFFF, sum = 0
5292 10:52:07.048299 3, 0xFFFF, sum = 0
5293 10:52:07.051473 4, 0xFFFF, sum = 0
5294 10:52:07.051587 5, 0xFFFF, sum = 0
5295 10:52:07.054791 6, 0xFFFF, sum = 0
5296 10:52:07.054876 7, 0xFFFF, sum = 0
5297 10:52:07.058029 8, 0xFFFF, sum = 0
5298 10:52:07.058115 9, 0xFFFF, sum = 0
5299 10:52:07.061706 10, 0x0, sum = 1
5300 10:52:07.061819 11, 0x0, sum = 2
5301 10:52:07.064401 12, 0x0, sum = 3
5302 10:52:07.064485 13, 0x0, sum = 4
5303 10:52:07.067832 best_step = 11
5304 10:52:07.067915
5305 10:52:07.067996 ==
5306 10:52:07.071113 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 10:52:07.074447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 10:52:07.074566 ==
5309 10:52:07.074632 RX Vref Scan: 1
5310 10:52:07.077932
5311 10:52:07.078029 RX Vref 0 -> 0, step: 1
5312 10:52:07.078094
5313 10:52:07.081328 RX Delay -53 -> 252, step: 4
5314 10:52:07.081411
5315 10:52:07.084429 Set Vref, RX VrefLevel [Byte0]: 59
5316 10:52:07.087702 [Byte1]: 49
5317 10:52:07.091137
5318 10:52:07.091220 Final RX Vref Byte 0 = 59 to rank0
5319 10:52:07.094469 Final RX Vref Byte 1 = 49 to rank0
5320 10:52:07.097497 Final RX Vref Byte 0 = 59 to rank1
5321 10:52:07.101015 Final RX Vref Byte 1 = 49 to rank1==
5322 10:52:07.103987 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 10:52:07.110742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 10:52:07.110845 ==
5325 10:52:07.110912 DQS Delay:
5326 10:52:07.114002 DQS0 = 0, DQS1 = 0
5327 10:52:07.114087 DQM Delay:
5328 10:52:07.114154 DQM0 = 107, DQM1 = 91
5329 10:52:07.117544 DQ Delay:
5330 10:52:07.120557 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5331 10:52:07.124110 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =114
5332 10:52:07.127676 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =90
5333 10:52:07.130629 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =100
5334 10:52:07.130715
5335 10:52:07.130795
5336 10:52:07.140192 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5337 10:52:07.140294 CH0 RK0: MR19=505, MR18=231F
5338 10:52:07.146831 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5339 10:52:07.146917
5340 10:52:07.150287 ----->DramcWriteLeveling(PI) begin...
5341 10:52:07.150373 ==
5342 10:52:07.153491 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 10:52:07.160329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 10:52:07.160413 ==
5345 10:52:07.163348 Write leveling (Byte 0): 34 => 34
5346 10:52:07.163432 Write leveling (Byte 1): 28 => 28
5347 10:52:07.166782 DramcWriteLeveling(PI) end<-----
5348 10:52:07.166894
5349 10:52:07.169934 ==
5350 10:52:07.170017 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 10:52:07.176835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 10:52:07.176922 ==
5353 10:52:07.179932 [Gating] SW mode calibration
5354 10:52:07.186458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 10:52:07.189748 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 10:52:07.196703 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 10:52:07.199820 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 10:52:07.203248 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 10:52:07.209637 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 10:52:07.213354 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 10:52:07.216697 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 10:52:07.223113 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5363 10:52:07.226322 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5364 10:52:07.229551 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 10:52:07.236296 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 10:52:07.239583 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 10:52:07.242933 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 10:52:07.249250 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 10:52:07.252659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 10:52:07.255944 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5371 10:52:07.262648 0 15 28 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5372 10:52:07.265963 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 10:52:07.269214 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 10:52:07.275655 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 10:52:07.279263 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 10:52:07.282371 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 10:52:07.289046 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 10:52:07.292619 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5379 10:52:07.295519 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5380 10:52:07.302199 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5381 10:52:07.305790 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 10:52:07.308799 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 10:52:07.315254 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 10:52:07.318693 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 10:52:07.321919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 10:52:07.328425 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 10:52:07.331873 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 10:52:07.334874 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 10:52:07.341829 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 10:52:07.344755 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 10:52:07.348182 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 10:52:07.355720 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 10:52:07.358106 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 10:52:07.361747 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5395 10:52:07.368274 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5396 10:52:07.371430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 10:52:07.374783 Total UI for P1: 0, mck2ui 16
5398 10:52:07.378314 best dqsien dly found for B0: ( 1, 2, 26)
5399 10:52:07.381539 Total UI for P1: 0, mck2ui 16
5400 10:52:07.384714 best dqsien dly found for B1: ( 1, 2, 26)
5401 10:52:07.387873 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5402 10:52:07.391402 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5403 10:52:07.391501
5404 10:52:07.394814 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5405 10:52:07.397932 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5406 10:52:07.401331 [Gating] SW calibration Done
5407 10:52:07.401416 ==
5408 10:52:07.404714 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 10:52:07.407751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 10:52:07.411014 ==
5411 10:52:07.411097 RX Vref Scan: 0
5412 10:52:07.411162
5413 10:52:07.414606 RX Vref 0 -> 0, step: 1
5414 10:52:07.414689
5415 10:52:07.417946 RX Delay -80 -> 252, step: 8
5416 10:52:07.421048 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5417 10:52:07.424149 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5418 10:52:07.427430 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5419 10:52:07.430901 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5420 10:52:07.433992 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5421 10:52:07.441025 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5422 10:52:07.444289 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5423 10:52:07.447409 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5424 10:52:07.450788 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5425 10:52:07.454276 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5426 10:52:07.460715 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5427 10:52:07.464183 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5428 10:52:07.467607 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5429 10:52:07.470883 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5430 10:52:07.473650 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5431 10:52:07.477532 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5432 10:52:07.480362 ==
5433 10:52:07.483602 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 10:52:07.486836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 10:52:07.486921 ==
5436 10:52:07.486988 DQS Delay:
5437 10:52:07.490490 DQS0 = 0, DQS1 = 0
5438 10:52:07.490573 DQM Delay:
5439 10:52:07.493497 DQM0 = 104, DQM1 = 90
5440 10:52:07.493581 DQ Delay:
5441 10:52:07.497041 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5442 10:52:07.500253 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5443 10:52:07.503554 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5444 10:52:07.506817 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5445 10:52:07.506900
5446 10:52:07.506966
5447 10:52:07.507027 ==
5448 10:52:07.510019 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 10:52:07.513488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 10:52:07.513600 ==
5451 10:52:07.516681
5452 10:52:07.516771
5453 10:52:07.516852 TX Vref Scan disable
5454 10:52:07.519980 == TX Byte 0 ==
5455 10:52:07.523309 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5456 10:52:07.526567 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5457 10:52:07.530146 == TX Byte 1 ==
5458 10:52:07.533200 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5459 10:52:07.536653 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5460 10:52:07.539620 ==
5461 10:52:07.539704 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 10:52:07.546293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 10:52:07.546377 ==
5464 10:52:07.546443
5465 10:52:07.546534
5466 10:52:07.549905 TX Vref Scan disable
5467 10:52:07.549988 == TX Byte 0 ==
5468 10:52:07.556184 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5469 10:52:07.559758 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5470 10:52:07.559843 == TX Byte 1 ==
5471 10:52:07.566240 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5472 10:52:07.569317 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5473 10:52:07.569401
5474 10:52:07.569467 [DATLAT]
5475 10:52:07.572683 Freq=933, CH0 RK1
5476 10:52:07.572774
5477 10:52:07.572856 DATLAT Default: 0xb
5478 10:52:07.576285 0, 0xFFFF, sum = 0
5479 10:52:07.576369 1, 0xFFFF, sum = 0
5480 10:52:07.579690 2, 0xFFFF, sum = 0
5481 10:52:07.579775 3, 0xFFFF, sum = 0
5482 10:52:07.582737 4, 0xFFFF, sum = 0
5483 10:52:07.582822 5, 0xFFFF, sum = 0
5484 10:52:07.586170 6, 0xFFFF, sum = 0
5485 10:52:07.586255 7, 0xFFFF, sum = 0
5486 10:52:07.589456 8, 0xFFFF, sum = 0
5487 10:52:07.592614 9, 0xFFFF, sum = 0
5488 10:52:07.592699 10, 0x0, sum = 1
5489 10:52:07.592770 11, 0x0, sum = 2
5490 10:52:07.596100 12, 0x0, sum = 3
5491 10:52:07.596185 13, 0x0, sum = 4
5492 10:52:07.599333 best_step = 11
5493 10:52:07.599416
5494 10:52:07.599483 ==
5495 10:52:07.602684 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 10:52:07.605707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 10:52:07.605790 ==
5498 10:52:07.609217 RX Vref Scan: 0
5499 10:52:07.609300
5500 10:52:07.609366 RX Vref 0 -> 0, step: 1
5501 10:52:07.612453
5502 10:52:07.612536 RX Delay -53 -> 252, step: 4
5503 10:52:07.619891 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5504 10:52:07.623440 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5505 10:52:07.626367 iDelay=203, Bit 2, Center 100 (11 ~ 190) 180
5506 10:52:07.629854 iDelay=203, Bit 3, Center 96 (11 ~ 182) 172
5507 10:52:07.633298 iDelay=203, Bit 4, Center 106 (23 ~ 190) 168
5508 10:52:07.639572 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5509 10:52:07.642893 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5510 10:52:07.646481 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5511 10:52:07.649543 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5512 10:52:07.653002 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5513 10:52:07.659363 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5514 10:52:07.662479 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5515 10:52:07.665960 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5516 10:52:07.669267 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5517 10:52:07.672363 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5518 10:52:07.679008 iDelay=203, Bit 15, Center 96 (11 ~ 182) 172
5519 10:52:07.679093 ==
5520 10:52:07.682352 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 10:52:07.685696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 10:52:07.685793 ==
5523 10:52:07.685859 DQS Delay:
5524 10:52:07.688845 DQS0 = 0, DQS1 = 0
5525 10:52:07.688928 DQM Delay:
5526 10:52:07.692553 DQM0 = 103, DQM1 = 92
5527 10:52:07.692635 DQ Delay:
5528 10:52:07.695651 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =96
5529 10:52:07.698860 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5530 10:52:07.702135 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5531 10:52:07.705744 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =96
5532 10:52:07.705885
5533 10:52:07.705980
5534 10:52:07.715231 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5535 10:52:07.718843 CH0 RK1: MR19=505, MR18=2B0C
5536 10:52:07.722121 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5537 10:52:07.725465 [RxdqsGatingPostProcess] freq 933
5538 10:52:07.731960 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 10:52:07.734936 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 10:52:07.738264 best DQS1 dly(2T, 0.5T) = (0, 10)
5541 10:52:07.741427 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 10:52:07.744990 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5543 10:52:07.748072 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 10:52:07.751507 best DQS1 dly(2T, 0.5T) = (0, 10)
5545 10:52:07.754850 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 10:52:07.758271 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5547 10:52:07.761472 Pre-setting of DQS Precalculation
5548 10:52:07.764622 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 10:52:07.764730 ==
5550 10:52:07.768171 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 10:52:07.771763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 10:52:07.774782 ==
5553 10:52:07.777772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 10:52:07.784435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5555 10:52:07.787954 [CA 0] Center 37 (7~68) winsize 62
5556 10:52:07.791559 [CA 1] Center 37 (7~68) winsize 62
5557 10:52:07.794532 [CA 2] Center 36 (6~66) winsize 61
5558 10:52:07.797623 [CA 3] Center 35 (5~65) winsize 61
5559 10:52:07.800998 [CA 4] Center 35 (5~66) winsize 62
5560 10:52:07.804354 [CA 5] Center 34 (4~65) winsize 62
5561 10:52:07.804438
5562 10:52:07.807715 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5563 10:52:07.807797
5564 10:52:07.810796 [CATrainingPosCal] consider 1 rank data
5565 10:52:07.814264 u2DelayCellTimex100 = 270/100 ps
5566 10:52:07.817469 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5567 10:52:07.820950 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5568 10:52:07.827293 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5569 10:52:07.830699 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5570 10:52:07.833982 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5571 10:52:07.837388 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5572 10:52:07.837472
5573 10:52:07.840845 CA PerBit enable=1, Macro0, CA PI delay=34
5574 10:52:07.840929
5575 10:52:07.843998 [CBTSetCACLKResult] CA Dly = 34
5576 10:52:07.844081 CS Dly: 6 (0~37)
5577 10:52:07.844147 ==
5578 10:52:07.847111 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 10:52:07.854022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 10:52:07.854107 ==
5581 10:52:07.856974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 10:52:07.863762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5583 10:52:07.867534 [CA 0] Center 38 (8~68) winsize 61
5584 10:52:07.870542 [CA 1] Center 38 (8~69) winsize 62
5585 10:52:07.874133 [CA 2] Center 36 (6~66) winsize 61
5586 10:52:07.877075 [CA 3] Center 35 (5~66) winsize 62
5587 10:52:07.880429 [CA 4] Center 36 (6~66) winsize 61
5588 10:52:07.883665 [CA 5] Center 34 (4~65) winsize 62
5589 10:52:07.883748
5590 10:52:07.886930 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5591 10:52:07.887013
5592 10:52:07.890345 [CATrainingPosCal] consider 2 rank data
5593 10:52:07.893862 u2DelayCellTimex100 = 270/100 ps
5594 10:52:07.896852 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5595 10:52:07.903601 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5596 10:52:07.907121 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5597 10:52:07.910372 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5598 10:52:07.913438 CA4 delay=36 (6~66),Diff = 2 PI (12 cell)
5599 10:52:07.916736 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5600 10:52:07.916841
5601 10:52:07.919923 CA PerBit enable=1, Macro0, CA PI delay=34
5602 10:52:07.920006
5603 10:52:07.923286 [CBTSetCACLKResult] CA Dly = 34
5604 10:52:07.926811 CS Dly: 7 (0~39)
5605 10:52:07.926895
5606 10:52:07.930256 ----->DramcWriteLeveling(PI) begin...
5607 10:52:07.930355 ==
5608 10:52:07.933942 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 10:52:07.936799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 10:52:07.936900 ==
5611 10:52:07.940071 Write leveling (Byte 0): 24 => 24
5612 10:52:07.943607 Write leveling (Byte 1): 30 => 30
5613 10:52:07.946905 DramcWriteLeveling(PI) end<-----
5614 10:52:07.946989
5615 10:52:07.947054 ==
5616 10:52:07.950153 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 10:52:07.953143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 10:52:07.953228 ==
5619 10:52:07.956528 [Gating] SW mode calibration
5620 10:52:07.963150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 10:52:07.969711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 10:52:07.973282 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 10:52:07.976641 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 10:52:07.982885 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 10:52:07.986598 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 10:52:07.989603 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 10:52:07.996458 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 10:52:07.999467 0 14 24 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
5629 10:52:08.002919 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5630 10:52:08.009602 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 10:52:08.013329 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 10:52:08.015927 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 10:52:08.023248 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 10:52:08.026050 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 10:52:08.029325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 10:52:08.036462 0 15 24 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (1 1)
5637 10:52:08.039597 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5638 10:52:08.042645 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 10:52:08.049217 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 10:52:08.052531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 10:52:08.055794 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 10:52:08.062579 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 10:52:08.066080 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5644 10:52:08.069228 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5645 10:52:08.075736 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 10:52:08.079318 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 10:52:08.082268 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 10:52:08.089326 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 10:52:08.092484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 10:52:08.095760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 10:52:08.102346 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 10:52:08.105308 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 10:52:08.108737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 10:52:08.115541 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 10:52:08.118633 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 10:52:08.122228 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 10:52:08.128628 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 10:52:08.131673 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 10:52:08.135257 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5660 10:52:08.141729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 10:52:08.145000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 10:52:08.148624 Total UI for P1: 0, mck2ui 16
5663 10:52:08.151675 best dqsien dly found for B0: ( 1, 2, 22)
5664 10:52:08.154937 Total UI for P1: 0, mck2ui 16
5665 10:52:08.158434 best dqsien dly found for B1: ( 1, 2, 24)
5666 10:52:08.161448 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5667 10:52:08.165038 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5668 10:52:08.165122
5669 10:52:08.168382 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5670 10:52:08.171668 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5671 10:52:08.174643 [Gating] SW calibration Done
5672 10:52:08.174757 ==
5673 10:52:08.178113 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 10:52:08.181539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 10:52:08.181652 ==
5676 10:52:08.184944 RX Vref Scan: 0
5677 10:52:08.185043
5678 10:52:08.188387 RX Vref 0 -> 0, step: 1
5679 10:52:08.188470
5680 10:52:08.188535 RX Delay -80 -> 252, step: 8
5681 10:52:08.194702 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5682 10:52:08.197961 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5683 10:52:08.201129 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5684 10:52:08.204729 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5685 10:52:08.208011 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5686 10:52:08.214445 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5687 10:52:08.217904 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5688 10:52:08.221549 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5689 10:52:08.224397 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5690 10:52:08.227880 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5691 10:52:08.230927 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5692 10:52:08.237875 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5693 10:52:08.240999 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5694 10:52:08.244155 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5695 10:52:08.247789 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5696 10:52:08.250920 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5697 10:52:08.251004 ==
5698 10:52:08.254383 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 10:52:08.260945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 10:52:08.261030 ==
5701 10:52:08.261096 DQS Delay:
5702 10:52:08.264198 DQS0 = 0, DQS1 = 0
5703 10:52:08.264280 DQM Delay:
5704 10:52:08.264375 DQM0 = 102, DQM1 = 95
5705 10:52:08.267544 DQ Delay:
5706 10:52:08.271007 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5707 10:52:08.274082 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5708 10:52:08.277509 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5709 10:52:08.280742 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5710 10:52:08.280847
5711 10:52:08.280913
5712 10:52:08.280975 ==
5713 10:52:08.284207 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 10:52:08.287436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 10:52:08.287521 ==
5716 10:52:08.287585
5717 10:52:08.287646
5718 10:52:08.290518 TX Vref Scan disable
5719 10:52:08.293827 == TX Byte 0 ==
5720 10:52:08.297004 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 10:52:08.300541 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 10:52:08.304168 == TX Byte 1 ==
5723 10:52:08.307090 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5724 10:52:08.310407 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5725 10:52:08.310491 ==
5726 10:52:08.314076 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 10:52:08.320574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 10:52:08.320676 ==
5729 10:52:08.320743
5730 10:52:08.320825
5731 10:52:08.320884 TX Vref Scan disable
5732 10:52:08.324495 == TX Byte 0 ==
5733 10:52:08.327573 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5734 10:52:08.334377 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5735 10:52:08.334461 == TX Byte 1 ==
5736 10:52:08.337530 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5737 10:52:08.344060 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5738 10:52:08.344145
5739 10:52:08.344211 [DATLAT]
5740 10:52:08.344272 Freq=933, CH1 RK0
5741 10:52:08.344332
5742 10:52:08.347530 DATLAT Default: 0xd
5743 10:52:08.350814 0, 0xFFFF, sum = 0
5744 10:52:08.350899 1, 0xFFFF, sum = 0
5745 10:52:08.353919 2, 0xFFFF, sum = 0
5746 10:52:08.354003 3, 0xFFFF, sum = 0
5747 10:52:08.357402 4, 0xFFFF, sum = 0
5748 10:52:08.357486 5, 0xFFFF, sum = 0
5749 10:52:08.360502 6, 0xFFFF, sum = 0
5750 10:52:08.360587 7, 0xFFFF, sum = 0
5751 10:52:08.363929 8, 0xFFFF, sum = 0
5752 10:52:08.364014 9, 0xFFFF, sum = 0
5753 10:52:08.367319 10, 0x0, sum = 1
5754 10:52:08.367404 11, 0x0, sum = 2
5755 10:52:08.370850 12, 0x0, sum = 3
5756 10:52:08.370935 13, 0x0, sum = 4
5757 10:52:08.371001 best_step = 11
5758 10:52:08.373907
5759 10:52:08.373989 ==
5760 10:52:08.377337 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 10:52:08.380435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 10:52:08.380547 ==
5763 10:52:08.380626 RX Vref Scan: 1
5764 10:52:08.380690
5765 10:52:08.384094 RX Vref 0 -> 0, step: 1
5766 10:52:08.384177
5767 10:52:08.387374 RX Delay -53 -> 252, step: 4
5768 10:52:08.387458
5769 10:52:08.390861 Set Vref, RX VrefLevel [Byte0]: 51
5770 10:52:08.394092 [Byte1]: 57
5771 10:52:08.394175
5772 10:52:08.397555 Final RX Vref Byte 0 = 51 to rank0
5773 10:52:08.400585 Final RX Vref Byte 1 = 57 to rank0
5774 10:52:08.403870 Final RX Vref Byte 0 = 51 to rank1
5775 10:52:08.406997 Final RX Vref Byte 1 = 57 to rank1==
5776 10:52:08.410485 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 10:52:08.417060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 10:52:08.417144 ==
5779 10:52:08.417210 DQS Delay:
5780 10:52:08.417271 DQS0 = 0, DQS1 = 0
5781 10:52:08.420535 DQM Delay:
5782 10:52:08.420617 DQM0 = 104, DQM1 = 98
5783 10:52:08.423590 DQ Delay:
5784 10:52:08.427057 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5785 10:52:08.430121 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5786 10:52:08.433533 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =94
5787 10:52:08.436678 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =104
5788 10:52:08.436769
5789 10:52:08.436866
5790 10:52:08.443387 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5791 10:52:08.447071 CH1 RK0: MR19=505, MR18=1C34
5792 10:52:08.453550 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5793 10:52:08.453636
5794 10:52:08.456718 ----->DramcWriteLeveling(PI) begin...
5795 10:52:08.456840 ==
5796 10:52:08.459922 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 10:52:08.463355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 10:52:08.466376 ==
5799 10:52:08.466460 Write leveling (Byte 0): 26 => 26
5800 10:52:08.469733 Write leveling (Byte 1): 27 => 27
5801 10:52:08.473481 DramcWriteLeveling(PI) end<-----
5802 10:52:08.473564
5803 10:52:08.473630 ==
5804 10:52:08.476592 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 10:52:08.483053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 10:52:08.483137 ==
5807 10:52:08.483203 [Gating] SW mode calibration
5808 10:52:08.492917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 10:52:08.496480 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 10:52:08.502745 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5811 10:52:08.506411 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 10:52:08.509647 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 10:52:08.516042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 10:52:08.519348 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 10:52:08.522643 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 10:52:08.529429 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5817 10:52:08.532612 0 14 28 | B1->B0 | 2525 2c2c | 1 1 | (1 0) (1 0)
5818 10:52:08.536081 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5819 10:52:08.542543 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 10:52:08.545991 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 10:52:08.549104 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 10:52:08.555779 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 10:52:08.558911 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 10:52:08.562524 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5825 10:52:08.568507 0 15 28 | B1->B0 | 4343 3a39 | 0 1 | (0 0) (0 0)
5826 10:52:08.571848 1 0 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
5827 10:52:08.575033 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 10:52:08.582112 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 10:52:08.584864 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 10:52:08.588121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 10:52:08.594718 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 10:52:08.598060 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5833 10:52:08.601412 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5834 10:52:08.607961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 10:52:08.611387 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 10:52:08.614461 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 10:52:08.621124 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 10:52:08.624591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 10:52:08.627592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 10:52:08.634127 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 10:52:08.637708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 10:52:08.640940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 10:52:08.647386 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 10:52:08.650835 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 10:52:08.654014 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 10:52:08.660751 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 10:52:08.664164 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 10:52:08.667317 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 10:52:08.674120 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 10:52:08.677420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 10:52:08.680590 Total UI for P1: 0, mck2ui 16
5852 10:52:08.683858 best dqsien dly found for B0: ( 1, 2, 28)
5853 10:52:08.687513 Total UI for P1: 0, mck2ui 16
5854 10:52:08.690548 best dqsien dly found for B1: ( 1, 2, 28)
5855 10:52:08.694059 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5856 10:52:08.697356 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5857 10:52:08.697439
5858 10:52:08.700417 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5859 10:52:08.703502 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5860 10:52:08.706887 [Gating] SW calibration Done
5861 10:52:08.706972 ==
5862 10:52:08.710334 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 10:52:08.713768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 10:52:08.717015 ==
5865 10:52:08.717098 RX Vref Scan: 0
5866 10:52:08.717163
5867 10:52:08.720038 RX Vref 0 -> 0, step: 1
5868 10:52:08.720121
5869 10:52:08.723520 RX Delay -80 -> 252, step: 8
5870 10:52:08.726570 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5871 10:52:08.730126 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5872 10:52:08.733650 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5873 10:52:08.737058 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5874 10:52:08.739993 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5875 10:52:08.746573 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5876 10:52:08.749747 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5877 10:52:08.753310 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5878 10:52:08.756958 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5879 10:52:08.759838 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5880 10:52:08.763358 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5881 10:52:08.769602 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5882 10:52:08.773308 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5883 10:52:08.776565 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5884 10:52:08.779851 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5885 10:52:08.782884 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5886 10:52:08.786146 ==
5887 10:52:08.789387 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 10:52:08.793002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 10:52:08.793107 ==
5890 10:52:08.793199 DQS Delay:
5891 10:52:08.796217 DQS0 = 0, DQS1 = 0
5892 10:52:08.796294 DQM Delay:
5893 10:52:08.799319 DQM0 = 101, DQM1 = 95
5894 10:52:08.799423 DQ Delay:
5895 10:52:08.803125 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5896 10:52:08.806185 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5897 10:52:08.809738 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5898 10:52:08.812685 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5899 10:52:08.812801
5900 10:52:08.812874
5901 10:52:08.812937 ==
5902 10:52:08.816130 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 10:52:08.819406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 10:52:08.823008 ==
5905 10:52:08.823129
5906 10:52:08.823233
5907 10:52:08.823324 TX Vref Scan disable
5908 10:52:08.826248 == TX Byte 0 ==
5909 10:52:08.829468 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5910 10:52:08.832746 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5911 10:52:08.835865 == TX Byte 1 ==
5912 10:52:08.839692 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 10:52:08.842605 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 10:52:08.845776 ==
5915 10:52:08.845857 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 10:52:08.852367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 10:52:08.852479 ==
5918 10:52:08.852572
5919 10:52:08.852665
5920 10:52:08.855773 TX Vref Scan disable
5921 10:52:08.855871 == TX Byte 0 ==
5922 10:52:08.862168 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5923 10:52:08.865572 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5924 10:52:08.865659 == TX Byte 1 ==
5925 10:52:08.872467 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 10:52:08.875353 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 10:52:08.875438
5928 10:52:08.875504 [DATLAT]
5929 10:52:08.878768 Freq=933, CH1 RK1
5930 10:52:08.878853
5931 10:52:08.878918 DATLAT Default: 0xb
5932 10:52:08.882023 0, 0xFFFF, sum = 0
5933 10:52:08.882108 1, 0xFFFF, sum = 0
5934 10:52:08.885176 2, 0xFFFF, sum = 0
5935 10:52:08.885261 3, 0xFFFF, sum = 0
5936 10:52:08.888540 4, 0xFFFF, sum = 0
5937 10:52:08.888624 5, 0xFFFF, sum = 0
5938 10:52:08.891939 6, 0xFFFF, sum = 0
5939 10:52:08.895259 7, 0xFFFF, sum = 0
5940 10:52:08.895343 8, 0xFFFF, sum = 0
5941 10:52:08.898978 9, 0xFFFF, sum = 0
5942 10:52:08.899063 10, 0x0, sum = 1
5943 10:52:08.902151 11, 0x0, sum = 2
5944 10:52:08.902239 12, 0x0, sum = 3
5945 10:52:08.902313 13, 0x0, sum = 4
5946 10:52:08.905154 best_step = 11
5947 10:52:08.905236
5948 10:52:08.905301 ==
5949 10:52:08.908524 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 10:52:08.911779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 10:52:08.911865 ==
5952 10:52:08.915303 RX Vref Scan: 0
5953 10:52:08.915388
5954 10:52:08.915454 RX Vref 0 -> 0, step: 1
5955 10:52:08.918568
5956 10:52:08.918651 RX Delay -53 -> 252, step: 4
5957 10:52:08.926089 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5958 10:52:08.928996 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5959 10:52:08.932403 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5960 10:52:08.936092 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5961 10:52:08.939176 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5962 10:52:08.945675 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5963 10:52:08.949324 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5964 10:52:08.952270 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5965 10:52:08.955563 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5966 10:52:08.959044 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5967 10:52:08.965610 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5968 10:52:08.968852 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5969 10:52:08.972377 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5970 10:52:08.975387 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5971 10:52:08.979066 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5972 10:52:08.985220 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5973 10:52:08.985340 ==
5974 10:52:08.988567 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 10:52:08.992013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 10:52:08.992131 ==
5977 10:52:08.992234 DQS Delay:
5978 10:52:08.995594 DQS0 = 0, DQS1 = 0
5979 10:52:08.995700 DQM Delay:
5980 10:52:08.998503 DQM0 = 105, DQM1 = 98
5981 10:52:08.998607 DQ Delay:
5982 10:52:09.001989 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5983 10:52:09.004995 DQ4 =104, DQ5 =114, DQ6 =114, DQ7 =102
5984 10:52:09.008289 DQ8 =84, DQ9 =90, DQ10 =100, DQ11 =92
5985 10:52:09.011891 DQ12 =108, DQ13 =102, DQ14 =106, DQ15 =106
5986 10:52:09.012000
5987 10:52:09.014888
5988 10:52:09.021520 [DQSOSCAuto] RK1, (LSB)MR18= 0x23ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5989 10:52:09.025052 CH1 RK1: MR19=504, MR18=23FF
5990 10:52:09.031146 CH1_RK1: MR19=0x504, MR18=0x23FF, DQSOSC=410, MR23=63, INC=64, DEC=42
5991 10:52:09.034568 [RxdqsGatingPostProcess] freq 933
5992 10:52:09.037997 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5993 10:52:09.041454 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 10:52:09.044352 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 10:52:09.047934 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 10:52:09.050788 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 10:52:09.054412 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 10:52:09.057660 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 10:52:09.060859 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 10:52:09.064291 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 10:52:09.067374 Pre-setting of DQS Precalculation
6002 10:52:09.070841 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6003 10:52:09.080360 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6004 10:52:09.087347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6005 10:52:09.087474
6006 10:52:09.087573
6007 10:52:09.090576 [Calibration Summary] 1866 Mbps
6008 10:52:09.090696 CH 0, Rank 0
6009 10:52:09.093563 SW Impedance : PASS
6010 10:52:09.093670 DUTY Scan : NO K
6011 10:52:09.096900 ZQ Calibration : PASS
6012 10:52:09.100196 Jitter Meter : NO K
6013 10:52:09.100293 CBT Training : PASS
6014 10:52:09.103663 Write leveling : PASS
6015 10:52:09.107333 RX DQS gating : PASS
6016 10:52:09.107421 RX DQ/DQS(RDDQC) : PASS
6017 10:52:09.110163 TX DQ/DQS : PASS
6018 10:52:09.113721 RX DATLAT : PASS
6019 10:52:09.113807 RX DQ/DQS(Engine): PASS
6020 10:52:09.116749 TX OE : NO K
6021 10:52:09.116855 All Pass.
6022 10:52:09.116922
6023 10:52:09.119998 CH 0, Rank 1
6024 10:52:09.120084 SW Impedance : PASS
6025 10:52:09.123465 DUTY Scan : NO K
6026 10:52:09.126670 ZQ Calibration : PASS
6027 10:52:09.126754 Jitter Meter : NO K
6028 10:52:09.130056 CBT Training : PASS
6029 10:52:09.133437 Write leveling : PASS
6030 10:52:09.133521 RX DQS gating : PASS
6031 10:52:09.136673 RX DQ/DQS(RDDQC) : PASS
6032 10:52:09.140125 TX DQ/DQS : PASS
6033 10:52:09.140211 RX DATLAT : PASS
6034 10:52:09.143220 RX DQ/DQS(Engine): PASS
6035 10:52:09.143303 TX OE : NO K
6036 10:52:09.146394 All Pass.
6037 10:52:09.146477
6038 10:52:09.146542 CH 1, Rank 0
6039 10:52:09.150014 SW Impedance : PASS
6040 10:52:09.150097 DUTY Scan : NO K
6041 10:52:09.153153 ZQ Calibration : PASS
6042 10:52:09.156408 Jitter Meter : NO K
6043 10:52:09.156491 CBT Training : PASS
6044 10:52:09.159995 Write leveling : PASS
6045 10:52:09.163049 RX DQS gating : PASS
6046 10:52:09.163132 RX DQ/DQS(RDDQC) : PASS
6047 10:52:09.166404 TX DQ/DQS : PASS
6048 10:52:09.169810 RX DATLAT : PASS
6049 10:52:09.169893 RX DQ/DQS(Engine): PASS
6050 10:52:09.172908 TX OE : NO K
6051 10:52:09.172991 All Pass.
6052 10:52:09.173057
6053 10:52:09.176261 CH 1, Rank 1
6054 10:52:09.176344 SW Impedance : PASS
6055 10:52:09.179890 DUTY Scan : NO K
6056 10:52:09.182748 ZQ Calibration : PASS
6057 10:52:09.182830 Jitter Meter : NO K
6058 10:52:09.186185 CBT Training : PASS
6059 10:52:09.189544 Write leveling : PASS
6060 10:52:09.189627 RX DQS gating : PASS
6061 10:52:09.192761 RX DQ/DQS(RDDQC) : PASS
6062 10:52:09.196151 TX DQ/DQS : PASS
6063 10:52:09.196235 RX DATLAT : PASS
6064 10:52:09.199418 RX DQ/DQS(Engine): PASS
6065 10:52:09.202517 TX OE : NO K
6066 10:52:09.202600 All Pass.
6067 10:52:09.202670
6068 10:52:09.202730 DramC Write-DBI off
6069 10:52:09.205935 PER_BANK_REFRESH: Hybrid Mode
6070 10:52:09.209146 TX_TRACKING: ON
6071 10:52:09.215758 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6072 10:52:09.219145 [FAST_K] Save calibration result to emmc
6073 10:52:09.225656 dramc_set_vcore_voltage set vcore to 650000
6074 10:52:09.225745 Read voltage for 400, 6
6075 10:52:09.228876 Vio18 = 0
6076 10:52:09.228961 Vcore = 650000
6077 10:52:09.229027 Vdram = 0
6078 10:52:09.232689 Vddq = 0
6079 10:52:09.232829 Vmddr = 0
6080 10:52:09.235760 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6081 10:52:09.242295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6082 10:52:09.245513 MEM_TYPE=3, freq_sel=20
6083 10:52:09.249072 sv_algorithm_assistance_LP4_800
6084 10:52:09.252048 ============ PULL DRAM RESETB DOWN ============
6085 10:52:09.255843 ========== PULL DRAM RESETB DOWN end =========
6086 10:52:09.258796 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6087 10:52:09.262088 ===================================
6088 10:52:09.265417 LPDDR4 DRAM CONFIGURATION
6089 10:52:09.268546 ===================================
6090 10:52:09.272196 EX_ROW_EN[0] = 0x0
6091 10:52:09.272279 EX_ROW_EN[1] = 0x0
6092 10:52:09.275559 LP4Y_EN = 0x0
6093 10:52:09.275643 WORK_FSP = 0x0
6094 10:52:09.278589 WL = 0x2
6095 10:52:09.278699 RL = 0x2
6096 10:52:09.282110 BL = 0x2
6097 10:52:09.282193 RPST = 0x0
6098 10:52:09.285144 RD_PRE = 0x0
6099 10:52:09.288465 WR_PRE = 0x1
6100 10:52:09.288548 WR_PST = 0x0
6101 10:52:09.291818 DBI_WR = 0x0
6102 10:52:09.291902 DBI_RD = 0x0
6103 10:52:09.295271 OTF = 0x1
6104 10:52:09.298799 ===================================
6105 10:52:09.301809 ===================================
6106 10:52:09.301894 ANA top config
6107 10:52:09.305030 ===================================
6108 10:52:09.308496 DLL_ASYNC_EN = 0
6109 10:52:09.311892 ALL_SLAVE_EN = 1
6110 10:52:09.311976 NEW_RANK_MODE = 1
6111 10:52:09.315063 DLL_IDLE_MODE = 1
6112 10:52:09.318384 LP45_APHY_COMB_EN = 1
6113 10:52:09.321480 TX_ODT_DIS = 1
6114 10:52:09.321565 NEW_8X_MODE = 1
6115 10:52:09.324880 ===================================
6116 10:52:09.328281 ===================================
6117 10:52:09.331321 data_rate = 800
6118 10:52:09.334724 CKR = 1
6119 10:52:09.338022 DQ_P2S_RATIO = 4
6120 10:52:09.341219 ===================================
6121 10:52:09.344551 CA_P2S_RATIO = 4
6122 10:52:09.348047 DQ_CA_OPEN = 0
6123 10:52:09.351031 DQ_SEMI_OPEN = 1
6124 10:52:09.351120 CA_SEMI_OPEN = 1
6125 10:52:09.354446 CA_FULL_RATE = 0
6126 10:52:09.358108 DQ_CKDIV4_EN = 0
6127 10:52:09.361132 CA_CKDIV4_EN = 1
6128 10:52:09.364503 CA_PREDIV_EN = 0
6129 10:52:09.367564 PH8_DLY = 0
6130 10:52:09.367648 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6131 10:52:09.371025 DQ_AAMCK_DIV = 0
6132 10:52:09.374455 CA_AAMCK_DIV = 0
6133 10:52:09.377567 CA_ADMCK_DIV = 4
6134 10:52:09.380996 DQ_TRACK_CA_EN = 0
6135 10:52:09.384491 CA_PICK = 800
6136 10:52:09.384575 CA_MCKIO = 400
6137 10:52:09.387685 MCKIO_SEMI = 400
6138 10:52:09.391017 PLL_FREQ = 3016
6139 10:52:09.394288 DQ_UI_PI_RATIO = 32
6140 10:52:09.397741 CA_UI_PI_RATIO = 32
6141 10:52:09.400936 ===================================
6142 10:52:09.404167 ===================================
6143 10:52:09.407721 memory_type:LPDDR4
6144 10:52:09.407804 GP_NUM : 10
6145 10:52:09.410889 SRAM_EN : 1
6146 10:52:09.414220 MD32_EN : 0
6147 10:52:09.417400 ===================================
6148 10:52:09.417485 [ANA_INIT] >>>>>>>>>>>>>>
6149 10:52:09.420887 <<<<<< [CONFIGURE PHASE]: ANA_TX
6150 10:52:09.424308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6151 10:52:09.427467 ===================================
6152 10:52:09.430588 data_rate = 800,PCW = 0X7400
6153 10:52:09.434035 ===================================
6154 10:52:09.437597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6155 10:52:09.444257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 10:52:09.453938 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 10:52:09.460368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6158 10:52:09.463855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6159 10:52:09.467073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6160 10:52:09.467158 [ANA_INIT] flow start
6161 10:52:09.470292 [ANA_INIT] PLL >>>>>>>>
6162 10:52:09.473721 [ANA_INIT] PLL <<<<<<<<
6163 10:52:09.473804 [ANA_INIT] MIDPI >>>>>>>>
6164 10:52:09.476853 [ANA_INIT] MIDPI <<<<<<<<
6165 10:52:09.480173 [ANA_INIT] DLL >>>>>>>>
6166 10:52:09.480257 [ANA_INIT] flow end
6167 10:52:09.486731 ============ LP4 DIFF to SE enter ============
6168 10:52:09.490167 ============ LP4 DIFF to SE exit ============
6169 10:52:09.493308 [ANA_INIT] <<<<<<<<<<<<<
6170 10:52:09.496699 [Flow] Enable top DCM control >>>>>
6171 10:52:09.499799 [Flow] Enable top DCM control <<<<<
6172 10:52:09.499882 Enable DLL master slave shuffle
6173 10:52:09.506570 ==============================================================
6174 10:52:09.509941 Gating Mode config
6175 10:52:09.512990 ==============================================================
6176 10:52:09.516374 Config description:
6177 10:52:09.526261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6178 10:52:09.532996 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6179 10:52:09.536226 SELPH_MODE 0: By rank 1: By Phase
6180 10:52:09.542796 ==============================================================
6181 10:52:09.546118 GAT_TRACK_EN = 0
6182 10:52:09.549574 RX_GATING_MODE = 2
6183 10:52:09.552708 RX_GATING_TRACK_MODE = 2
6184 10:52:09.556270 SELPH_MODE = 1
6185 10:52:09.559295 PICG_EARLY_EN = 1
6186 10:52:09.559379 VALID_LAT_VALUE = 1
6187 10:52:09.565881 ==============================================================
6188 10:52:09.569522 Enter into Gating configuration >>>>
6189 10:52:09.572826 Exit from Gating configuration <<<<
6190 10:52:09.575859 Enter into DVFS_PRE_config >>>>>
6191 10:52:09.585983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6192 10:52:09.589134 Exit from DVFS_PRE_config <<<<<
6193 10:52:09.592373 Enter into PICG configuration >>>>
6194 10:52:09.595605 Exit from PICG configuration <<<<
6195 10:52:09.598796 [RX_INPUT] configuration >>>>>
6196 10:52:09.602179 [RX_INPUT] configuration <<<<<
6197 10:52:09.608928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6198 10:52:09.612077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6199 10:52:09.618874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 10:52:09.625292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 10:52:09.632057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 10:52:09.638824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 10:52:09.641871 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6204 10:52:09.645454 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6205 10:52:09.648620 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6206 10:52:09.655323 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6207 10:52:09.658256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6208 10:52:09.661728 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 10:52:09.664744 ===================================
6210 10:52:09.668175 LPDDR4 DRAM CONFIGURATION
6211 10:52:09.671740 ===================================
6212 10:52:09.674818 EX_ROW_EN[0] = 0x0
6213 10:52:09.674902 EX_ROW_EN[1] = 0x0
6214 10:52:09.678149 LP4Y_EN = 0x0
6215 10:52:09.678232 WORK_FSP = 0x0
6216 10:52:09.681537 WL = 0x2
6217 10:52:09.681620 RL = 0x2
6218 10:52:09.684914 BL = 0x2
6219 10:52:09.684997 RPST = 0x0
6220 10:52:09.687996 RD_PRE = 0x0
6221 10:52:09.688080 WR_PRE = 0x1
6222 10:52:09.691132 WR_PST = 0x0
6223 10:52:09.691245 DBI_WR = 0x0
6224 10:52:09.694484 DBI_RD = 0x0
6225 10:52:09.694574 OTF = 0x1
6226 10:52:09.697910 ===================================
6227 10:52:09.704520 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6228 10:52:09.708182 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6229 10:52:09.711209 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 10:52:09.714409 ===================================
6231 10:52:09.717501 LPDDR4 DRAM CONFIGURATION
6232 10:52:09.720791 ===================================
6233 10:52:09.724177 EX_ROW_EN[0] = 0x10
6234 10:52:09.724254 EX_ROW_EN[1] = 0x0
6235 10:52:09.727664 LP4Y_EN = 0x0
6236 10:52:09.727742 WORK_FSP = 0x0
6237 10:52:09.730914 WL = 0x2
6238 10:52:09.730988 RL = 0x2
6239 10:52:09.734079 BL = 0x2
6240 10:52:09.734155 RPST = 0x0
6241 10:52:09.737484 RD_PRE = 0x0
6242 10:52:09.737560 WR_PRE = 0x1
6243 10:52:09.740875 WR_PST = 0x0
6244 10:52:09.740976 DBI_WR = 0x0
6245 10:52:09.744281 DBI_RD = 0x0
6246 10:52:09.744354 OTF = 0x1
6247 10:52:09.747237 ===================================
6248 10:52:09.753997 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6249 10:52:09.758509 nWR fixed to 30
6250 10:52:09.761860 [ModeRegInit_LP4] CH0 RK0
6251 10:52:09.761945 [ModeRegInit_LP4] CH0 RK1
6252 10:52:09.765064 [ModeRegInit_LP4] CH1 RK0
6253 10:52:09.768759 [ModeRegInit_LP4] CH1 RK1
6254 10:52:09.768838 match AC timing 19
6255 10:52:09.775180 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6256 10:52:09.778877 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6257 10:52:09.781926 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6258 10:52:09.788504 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6259 10:52:09.791838 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6260 10:52:09.791923 ==
6261 10:52:09.795057 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 10:52:09.798649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 10:52:09.798734 ==
6264 10:52:09.804938 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 10:52:09.811881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6266 10:52:09.814960 [CA 0] Center 36 (8~64) winsize 57
6267 10:52:09.818131 [CA 1] Center 36 (8~64) winsize 57
6268 10:52:09.821732 [CA 2] Center 36 (8~64) winsize 57
6269 10:52:09.824658 [CA 3] Center 36 (8~64) winsize 57
6270 10:52:09.828428 [CA 4] Center 36 (8~64) winsize 57
6271 10:52:09.828538 [CA 5] Center 36 (8~64) winsize 57
6272 10:52:09.828632
6273 10:52:09.834931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6274 10:52:09.835018
6275 10:52:09.837910 [CATrainingPosCal] consider 1 rank data
6276 10:52:09.841626 u2DelayCellTimex100 = 270/100 ps
6277 10:52:09.845155 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 10:52:09.848058 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 10:52:09.851397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 10:52:09.854670 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 10:52:09.857764 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 10:52:09.861429 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 10:52:09.861514
6284 10:52:09.864714 CA PerBit enable=1, Macro0, CA PI delay=36
6285 10:52:09.864848
6286 10:52:09.867732 [CBTSetCACLKResult] CA Dly = 36
6287 10:52:09.871254 CS Dly: 1 (0~32)
6288 10:52:09.871338 ==
6289 10:52:09.874402 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 10:52:09.877579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 10:52:09.877668 ==
6292 10:52:09.884377 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 10:52:09.891192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6294 10:52:09.894235 [CA 0] Center 36 (8~64) winsize 57
6295 10:52:09.894322 [CA 1] Center 36 (8~64) winsize 57
6296 10:52:09.897496 [CA 2] Center 36 (8~64) winsize 57
6297 10:52:09.900853 [CA 3] Center 36 (8~64) winsize 57
6298 10:52:09.904426 [CA 4] Center 36 (8~64) winsize 57
6299 10:52:09.907867 [CA 5] Center 36 (8~64) winsize 57
6300 10:52:09.907956
6301 10:52:09.911053 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6302 10:52:09.911137
6303 10:52:09.917307 [CATrainingPosCal] consider 2 rank data
6304 10:52:09.917394 u2DelayCellTimex100 = 270/100 ps
6305 10:52:09.924264 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 10:52:09.927488 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 10:52:09.930895 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 10:52:09.933848 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 10:52:09.937548 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 10:52:09.940523 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 10:52:09.940609
6312 10:52:09.944066 CA PerBit enable=1, Macro0, CA PI delay=36
6313 10:52:09.944181
6314 10:52:09.947418 [CBTSetCACLKResult] CA Dly = 36
6315 10:52:09.950325 CS Dly: 1 (0~32)
6316 10:52:09.950411
6317 10:52:09.954008 ----->DramcWriteLeveling(PI) begin...
6318 10:52:09.954094 ==
6319 10:52:09.957100 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 10:52:09.960255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 10:52:09.960341 ==
6322 10:52:09.963687 Write leveling (Byte 0): 40 => 8
6323 10:52:09.966910 Write leveling (Byte 1): 32 => 0
6324 10:52:09.970233 DramcWriteLeveling(PI) end<-----
6325 10:52:09.970317
6326 10:52:09.970383 ==
6327 10:52:09.973765 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 10:52:09.976928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 10:52:09.977037 ==
6330 10:52:09.980049 [Gating] SW mode calibration
6331 10:52:09.986995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6332 10:52:09.993412 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6333 10:52:09.996915 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 10:52:10.000216 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 10:52:10.006672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 10:52:10.010019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 10:52:10.013330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 10:52:10.019879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 10:52:10.023330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 10:52:10.026315 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 10:52:10.033081 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 10:52:10.036729 Total UI for P1: 0, mck2ui 16
6343 10:52:10.039507 best dqsien dly found for B0: ( 0, 14, 24)
6344 10:52:10.039595 Total UI for P1: 0, mck2ui 16
6345 10:52:10.046407 best dqsien dly found for B1: ( 0, 14, 24)
6346 10:52:10.049421 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6347 10:52:10.052913 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6348 10:52:10.052986
6349 10:52:10.056155 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 10:52:10.059779 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 10:52:10.062784 [Gating] SW calibration Done
6352 10:52:10.062895 ==
6353 10:52:10.066452 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 10:52:10.069389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 10:52:10.069462 ==
6356 10:52:10.072627 RX Vref Scan: 0
6357 10:52:10.072734
6358 10:52:10.072817 RX Vref 0 -> 0, step: 1
6359 10:52:10.075981
6360 10:52:10.076051 RX Delay -410 -> 252, step: 16
6361 10:52:10.082510 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6362 10:52:10.086025 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6363 10:52:10.089503 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6364 10:52:10.092847 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6365 10:52:10.099076 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6366 10:52:10.102434 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6367 10:52:10.105953 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6368 10:52:10.109149 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6369 10:52:10.115821 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6370 10:52:10.118925 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6371 10:52:10.122428 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6372 10:52:10.126044 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6373 10:52:10.132474 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6374 10:52:10.135440 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6375 10:52:10.138852 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6376 10:52:10.145493 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6377 10:52:10.145599 ==
6378 10:52:10.148958 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 10:52:10.152246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 10:52:10.152346 ==
6381 10:52:10.152444 DQS Delay:
6382 10:52:10.155707 DQS0 = 27, DQS1 = 43
6383 10:52:10.155777 DQM Delay:
6384 10:52:10.158646 DQM0 = 12, DQM1 = 12
6385 10:52:10.158715 DQ Delay:
6386 10:52:10.162088 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6387 10:52:10.165208 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6388 10:52:10.168397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6389 10:52:10.171865 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6390 10:52:10.171935
6391 10:52:10.172003
6392 10:52:10.172061 ==
6393 10:52:10.175117 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:52:10.178185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:52:10.178255 ==
6396 10:52:10.178322
6397 10:52:10.178380
6398 10:52:10.181608 TX Vref Scan disable
6399 10:52:10.185415 == TX Byte 0 ==
6400 10:52:10.188319 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 10:52:10.191762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 10:52:10.194957 == TX Byte 1 ==
6403 10:52:10.198395 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 10:52:10.201459 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 10:52:10.201535 ==
6406 10:52:10.204741 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 10:52:10.207839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 10:52:10.211540 ==
6409 10:52:10.211629
6410 10:52:10.211691
6411 10:52:10.211761 TX Vref Scan disable
6412 10:52:10.214569 == TX Byte 0 ==
6413 10:52:10.217995 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 10:52:10.221410 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 10:52:10.224894 == TX Byte 1 ==
6416 10:52:10.227801 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6417 10:52:10.231261 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6418 10:52:10.231341
6419 10:52:10.234481 [DATLAT]
6420 10:52:10.234558 Freq=400, CH0 RK0
6421 10:52:10.234629
6422 10:52:10.237686 DATLAT Default: 0xf
6423 10:52:10.237762 0, 0xFFFF, sum = 0
6424 10:52:10.241030 1, 0xFFFF, sum = 0
6425 10:52:10.241147 2, 0xFFFF, sum = 0
6426 10:52:10.244469 3, 0xFFFF, sum = 0
6427 10:52:10.244574 4, 0xFFFF, sum = 0
6428 10:52:10.247823 5, 0xFFFF, sum = 0
6429 10:52:10.247902 6, 0xFFFF, sum = 0
6430 10:52:10.250835 7, 0xFFFF, sum = 0
6431 10:52:10.250913 8, 0xFFFF, sum = 0
6432 10:52:10.254273 9, 0xFFFF, sum = 0
6433 10:52:10.254344 10, 0xFFFF, sum = 0
6434 10:52:10.257565 11, 0xFFFF, sum = 0
6435 10:52:10.261119 12, 0xFFFF, sum = 0
6436 10:52:10.261219 13, 0x0, sum = 1
6437 10:52:10.264710 14, 0x0, sum = 2
6438 10:52:10.264843 15, 0x0, sum = 3
6439 10:52:10.264907 16, 0x0, sum = 4
6440 10:52:10.267444 best_step = 14
6441 10:52:10.267513
6442 10:52:10.267573 ==
6443 10:52:10.270960 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 10:52:10.274378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 10:52:10.274451 ==
6446 10:52:10.277425 RX Vref Scan: 1
6447 10:52:10.277495
6448 10:52:10.277563 RX Vref 0 -> 0, step: 1
6449 10:52:10.280601
6450 10:52:10.280707 RX Delay -327 -> 252, step: 8
6451 10:52:10.280834
6452 10:52:10.284081 Set Vref, RX VrefLevel [Byte0]: 59
6453 10:52:10.287115 [Byte1]: 49
6454 10:52:10.292385
6455 10:52:10.292457 Final RX Vref Byte 0 = 59 to rank0
6456 10:52:10.295813 Final RX Vref Byte 1 = 49 to rank0
6457 10:52:10.298871 Final RX Vref Byte 0 = 59 to rank1
6458 10:52:10.302348 Final RX Vref Byte 1 = 49 to rank1==
6459 10:52:10.305524 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 10:52:10.312054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 10:52:10.312135 ==
6462 10:52:10.312209 DQS Delay:
6463 10:52:10.315942 DQS0 = 24, DQS1 = 48
6464 10:52:10.316026 DQM Delay:
6465 10:52:10.316088 DQM0 = 9, DQM1 = 15
6466 10:52:10.318660 DQ Delay:
6467 10:52:10.322272 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6468 10:52:10.322381 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6469 10:52:10.325416 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6470 10:52:10.328628 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6471 10:52:10.328740
6472 10:52:10.332002
6473 10:52:10.338645 [DQSOSCAuto] RK0, (LSB)MR18= 0xa59d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6474 10:52:10.341854 CH0 RK0: MR19=C0C, MR18=A59D
6475 10:52:10.348680 CH0_RK0: MR19=0xC0C, MR18=0xA59D, DQSOSC=389, MR23=63, INC=390, DEC=260
6476 10:52:10.348828 ==
6477 10:52:10.351925 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 10:52:10.355287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 10:52:10.355371 ==
6480 10:52:10.358439 [Gating] SW mode calibration
6481 10:52:10.365250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6482 10:52:10.371904 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6483 10:52:10.375127 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 10:52:10.378413 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 10:52:10.384868 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 10:52:10.388407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 10:52:10.391468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 10:52:10.398133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 10:52:10.401267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 10:52:10.404890 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 10:52:10.411152 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 10:52:10.411260 Total UI for P1: 0, mck2ui 16
6493 10:52:10.417975 best dqsien dly found for B0: ( 0, 14, 24)
6494 10:52:10.418064 Total UI for P1: 0, mck2ui 16
6495 10:52:10.424682 best dqsien dly found for B1: ( 0, 14, 24)
6496 10:52:10.427927 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6497 10:52:10.431215 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6498 10:52:10.431301
6499 10:52:10.434491 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 10:52:10.437511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 10:52:10.441049 [Gating] SW calibration Done
6502 10:52:10.441134 ==
6503 10:52:10.444445 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 10:52:10.447643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 10:52:10.447729 ==
6506 10:52:10.451184 RX Vref Scan: 0
6507 10:52:10.451268
6508 10:52:10.451334 RX Vref 0 -> 0, step: 1
6509 10:52:10.451395
6510 10:52:10.454260 RX Delay -410 -> 252, step: 16
6511 10:52:10.460946 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6512 10:52:10.464555 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6513 10:52:10.467544 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6514 10:52:10.470863 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6515 10:52:10.477282 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6516 10:52:10.480977 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6517 10:52:10.484242 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6518 10:52:10.487522 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6519 10:52:10.494423 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6520 10:52:10.497411 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6521 10:52:10.500712 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6522 10:52:10.503946 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6523 10:52:10.510843 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6524 10:52:10.513823 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6525 10:52:10.517429 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6526 10:52:10.523762 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6527 10:52:10.523846 ==
6528 10:52:10.526985 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 10:52:10.530502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 10:52:10.530586 ==
6531 10:52:10.530652 DQS Delay:
6532 10:52:10.533541 DQS0 = 27, DQS1 = 43
6533 10:52:10.533624 DQM Delay:
6534 10:52:10.537249 DQM0 = 9, DQM1 = 16
6535 10:52:10.537333 DQ Delay:
6536 10:52:10.540262 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6537 10:52:10.543489 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6538 10:52:10.546747 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6539 10:52:10.549909 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6540 10:52:10.549993
6541 10:52:10.550058
6542 10:52:10.550119 ==
6543 10:52:10.553600 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 10:52:10.556643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 10:52:10.556729 ==
6546 10:52:10.556833
6547 10:52:10.556893
6548 10:52:10.560018 TX Vref Scan disable
6549 10:52:10.560100 == TX Byte 0 ==
6550 10:52:10.566567 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6551 10:52:10.570295 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6552 10:52:10.570379 == TX Byte 1 ==
6553 10:52:10.576563 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6554 10:52:10.580056 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6555 10:52:10.580139 ==
6556 10:52:10.583258 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 10:52:10.586541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 10:52:10.586624 ==
6559 10:52:10.586690
6560 10:52:10.586751
6561 10:52:10.589777 TX Vref Scan disable
6562 10:52:10.589860 == TX Byte 0 ==
6563 10:52:10.596257 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6564 10:52:10.599577 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6565 10:52:10.599661 == TX Byte 1 ==
6566 10:52:10.606390 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6567 10:52:10.609437 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6568 10:52:10.609521
6569 10:52:10.609586 [DATLAT]
6570 10:52:10.613169 Freq=400, CH0 RK1
6571 10:52:10.613252
6572 10:52:10.613316 DATLAT Default: 0xe
6573 10:52:10.616157 0, 0xFFFF, sum = 0
6574 10:52:10.616242 1, 0xFFFF, sum = 0
6575 10:52:10.619653 2, 0xFFFF, sum = 0
6576 10:52:10.619737 3, 0xFFFF, sum = 0
6577 10:52:10.622691 4, 0xFFFF, sum = 0
6578 10:52:10.626197 5, 0xFFFF, sum = 0
6579 10:52:10.626281 6, 0xFFFF, sum = 0
6580 10:52:10.629679 7, 0xFFFF, sum = 0
6581 10:52:10.629763 8, 0xFFFF, sum = 0
6582 10:52:10.632880 9, 0xFFFF, sum = 0
6583 10:52:10.632964 10, 0xFFFF, sum = 0
6584 10:52:10.635976 11, 0xFFFF, sum = 0
6585 10:52:10.636060 12, 0xFFFF, sum = 0
6586 10:52:10.639456 13, 0x0, sum = 1
6587 10:52:10.639542 14, 0x0, sum = 2
6588 10:52:10.642922 15, 0x0, sum = 3
6589 10:52:10.643007 16, 0x0, sum = 4
6590 10:52:10.646712 best_step = 14
6591 10:52:10.646818
6592 10:52:10.646885 ==
6593 10:52:10.649563 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 10:52:10.652724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 10:52:10.652899 ==
6596 10:52:10.652967 RX Vref Scan: 0
6597 10:52:10.655767
6598 10:52:10.655851 RX Vref 0 -> 0, step: 1
6599 10:52:10.655917
6600 10:52:10.659175 RX Delay -327 -> 252, step: 8
6601 10:52:10.666364 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6602 10:52:10.670064 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6603 10:52:10.672987 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6604 10:52:10.679753 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6605 10:52:10.682988 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6606 10:52:10.686447 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6607 10:52:10.689488 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6608 10:52:10.693078 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6609 10:52:10.699611 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6610 10:52:10.702792 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6611 10:52:10.706033 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6612 10:52:10.712750 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6613 10:52:10.716369 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6614 10:52:10.719363 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6615 10:52:10.722874 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6616 10:52:10.729250 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6617 10:52:10.729335 ==
6618 10:52:10.732927 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 10:52:10.736056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 10:52:10.736147 ==
6621 10:52:10.736215 DQS Delay:
6622 10:52:10.739333 DQS0 = 28, DQS1 = 44
6623 10:52:10.739405 DQM Delay:
6624 10:52:10.742275 DQM0 = 10, DQM1 = 14
6625 10:52:10.742347 DQ Delay:
6626 10:52:10.745568 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6627 10:52:10.749320 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6628 10:52:10.752332 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6629 10:52:10.755595 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6630 10:52:10.755665
6631 10:52:10.755726
6632 10:52:10.762362 [DQSOSCAuto] RK1, (LSB)MR18= 0xb468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6633 10:52:10.765597 CH0 RK1: MR19=C0C, MR18=B468
6634 10:52:10.772330 CH0_RK1: MR19=0xC0C, MR18=0xB468, DQSOSC=387, MR23=63, INC=394, DEC=262
6635 10:52:10.775451 [RxdqsGatingPostProcess] freq 400
6636 10:52:10.782025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6637 10:52:10.785335 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 10:52:10.788887 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 10:52:10.792299 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 10:52:10.795612 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 10:52:10.795682 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 10:52:10.798623 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 10:52:10.801909 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 10:52:10.805771 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 10:52:10.808876 Pre-setting of DQS Precalculation
6646 10:52:10.815258 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6647 10:52:10.815329 ==
6648 10:52:10.818535 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 10:52:10.821809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 10:52:10.821883 ==
6651 10:52:10.828166 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 10:52:10.834704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6653 10:52:10.838192 [CA 0] Center 36 (8~64) winsize 57
6654 10:52:10.841531 [CA 1] Center 36 (8~64) winsize 57
6655 10:52:10.841616 [CA 2] Center 36 (8~64) winsize 57
6656 10:52:10.845016 [CA 3] Center 36 (8~64) winsize 57
6657 10:52:10.848098 [CA 4] Center 36 (8~64) winsize 57
6658 10:52:10.851656 [CA 5] Center 36 (8~64) winsize 57
6659 10:52:10.851736
6660 10:52:10.854717 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6661 10:52:10.854820
6662 10:52:10.861520 [CATrainingPosCal] consider 1 rank data
6663 10:52:10.861598 u2DelayCellTimex100 = 270/100 ps
6664 10:52:10.868073 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 10:52:10.871357 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 10:52:10.874586 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 10:52:10.877689 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 10:52:10.881201 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 10:52:10.884398 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 10:52:10.884471
6671 10:52:10.887591 CA PerBit enable=1, Macro0, CA PI delay=36
6672 10:52:10.887684
6673 10:52:10.890893 [CBTSetCACLKResult] CA Dly = 36
6674 10:52:10.894379 CS Dly: 1 (0~32)
6675 10:52:10.894476 ==
6676 10:52:10.897807 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 10:52:10.901211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 10:52:10.901311 ==
6679 10:52:10.907501 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 10:52:10.910747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6681 10:52:10.914270 [CA 0] Center 36 (8~64) winsize 57
6682 10:52:10.917734 [CA 1] Center 36 (8~64) winsize 57
6683 10:52:10.920904 [CA 2] Center 36 (8~64) winsize 57
6684 10:52:10.924240 [CA 3] Center 36 (8~64) winsize 57
6685 10:52:10.927375 [CA 4] Center 36 (8~64) winsize 57
6686 10:52:10.930940 [CA 5] Center 36 (8~64) winsize 57
6687 10:52:10.931049
6688 10:52:10.933823 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6689 10:52:10.933908
6690 10:52:10.937489 [CATrainingPosCal] consider 2 rank data
6691 10:52:10.940644 u2DelayCellTimex100 = 270/100 ps
6692 10:52:10.943940 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 10:52:10.947057 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 10:52:10.954014 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 10:52:10.956952 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 10:52:10.960266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 10:52:10.963572 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 10:52:10.963679
6699 10:52:10.966950 CA PerBit enable=1, Macro0, CA PI delay=36
6700 10:52:10.967023
6701 10:52:10.970420 [CBTSetCACLKResult] CA Dly = 36
6702 10:52:10.970518 CS Dly: 1 (0~32)
6703 10:52:10.973589
6704 10:52:10.976809 ----->DramcWriteLeveling(PI) begin...
6705 10:52:10.976889 ==
6706 10:52:10.980278 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 10:52:10.983685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 10:52:10.983759 ==
6709 10:52:10.986887 Write leveling (Byte 0): 40 => 8
6710 10:52:10.990208 Write leveling (Byte 1): 32 => 0
6711 10:52:10.993509 DramcWriteLeveling(PI) end<-----
6712 10:52:10.993584
6713 10:52:10.993669 ==
6714 10:52:10.996719 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 10:52:10.999886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 10:52:10.999976 ==
6717 10:52:11.003102 [Gating] SW mode calibration
6718 10:52:11.010037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6719 10:52:11.016633 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6720 10:52:11.019697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 10:52:11.023086 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 10:52:11.029606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 10:52:11.033047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 10:52:11.036208 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 10:52:11.042968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 10:52:11.046239 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 10:52:11.049690 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 10:52:11.056385 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 10:52:11.056497 Total UI for P1: 0, mck2ui 16
6730 10:52:11.063157 best dqsien dly found for B0: ( 0, 14, 24)
6731 10:52:11.063255 Total UI for P1: 0, mck2ui 16
6732 10:52:11.066254 best dqsien dly found for B1: ( 0, 14, 24)
6733 10:52:11.073052 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6734 10:52:11.075991 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6735 10:52:11.076082
6736 10:52:11.079613 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 10:52:11.082777 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 10:52:11.086119 [Gating] SW calibration Done
6739 10:52:11.086197 ==
6740 10:52:11.089512 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 10:52:11.092581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 10:52:11.092684 ==
6743 10:52:11.096210 RX Vref Scan: 0
6744 10:52:11.096312
6745 10:52:11.096412 RX Vref 0 -> 0, step: 1
6746 10:52:11.096502
6747 10:52:11.099354 RX Delay -410 -> 252, step: 16
6748 10:52:11.105796 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6749 10:52:11.109290 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6750 10:52:11.112341 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6751 10:52:11.115898 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6752 10:52:11.122256 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6753 10:52:11.125975 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6754 10:52:11.129061 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6755 10:52:11.132426 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6756 10:52:11.138911 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6757 10:52:11.141968 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6758 10:52:11.145505 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6759 10:52:11.149001 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6760 10:52:11.155235 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6761 10:52:11.158468 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6762 10:52:11.161999 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6763 10:52:11.168772 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6764 10:52:11.168849 ==
6765 10:52:11.171907 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 10:52:11.175038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 10:52:11.175108 ==
6768 10:52:11.175173 DQS Delay:
6769 10:52:11.178537 DQS0 = 27, DQS1 = 43
6770 10:52:11.178604 DQM Delay:
6771 10:52:11.181692 DQM0 = 7, DQM1 = 16
6772 10:52:11.181759 DQ Delay:
6773 10:52:11.184874 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6774 10:52:11.188141 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6775 10:52:11.191504 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6776 10:52:11.194689 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6777 10:52:11.194760
6778 10:52:11.194820
6779 10:52:11.194878 ==
6780 10:52:11.198312 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:52:11.201399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:52:11.201465 ==
6783 10:52:11.201524
6784 10:52:11.201581
6785 10:52:11.204751 TX Vref Scan disable
6786 10:52:11.204820 == TX Byte 0 ==
6787 10:52:11.211112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 10:52:11.214651 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 10:52:11.214716 == TX Byte 1 ==
6790 10:52:11.221375 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6791 10:52:11.224521 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6792 10:52:11.224587 ==
6793 10:52:11.228169 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 10:52:11.231297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 10:52:11.231363 ==
6796 10:52:11.231425
6797 10:52:11.234401
6798 10:52:11.234465 TX Vref Scan disable
6799 10:52:11.238039 == TX Byte 0 ==
6800 10:52:11.241058 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 10:52:11.244126 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 10:52:11.247607 == TX Byte 1 ==
6803 10:52:11.251057 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6804 10:52:11.254297 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6805 10:52:11.254365
6806 10:52:11.257574 [DATLAT]
6807 10:52:11.257651 Freq=400, CH1 RK0
6808 10:52:11.257713
6809 10:52:11.260690 DATLAT Default: 0xf
6810 10:52:11.260759 0, 0xFFFF, sum = 0
6811 10:52:11.264350 1, 0xFFFF, sum = 0
6812 10:52:11.264435 2, 0xFFFF, sum = 0
6813 10:52:11.267422 3, 0xFFFF, sum = 0
6814 10:52:11.267507 4, 0xFFFF, sum = 0
6815 10:52:11.271134 5, 0xFFFF, sum = 0
6816 10:52:11.271219 6, 0xFFFF, sum = 0
6817 10:52:11.274183 7, 0xFFFF, sum = 0
6818 10:52:11.274268 8, 0xFFFF, sum = 0
6819 10:52:11.277499 9, 0xFFFF, sum = 0
6820 10:52:11.277573 10, 0xFFFF, sum = 0
6821 10:52:11.280819 11, 0xFFFF, sum = 0
6822 10:52:11.280891 12, 0xFFFF, sum = 0
6823 10:52:11.284353 13, 0x0, sum = 1
6824 10:52:11.284422 14, 0x0, sum = 2
6825 10:52:11.287264 15, 0x0, sum = 3
6826 10:52:11.287333 16, 0x0, sum = 4
6827 10:52:11.290418 best_step = 14
6828 10:52:11.290485
6829 10:52:11.290542 ==
6830 10:52:11.293747 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 10:52:11.297403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 10:52:11.297475 ==
6833 10:52:11.300566 RX Vref Scan: 1
6834 10:52:11.300640
6835 10:52:11.300705 RX Vref 0 -> 0, step: 1
6836 10:52:11.300770
6837 10:52:11.303882 RX Delay -327 -> 252, step: 8
6838 10:52:11.303950
6839 10:52:11.307338 Set Vref, RX VrefLevel [Byte0]: 51
6840 10:52:11.310236 [Byte1]: 57
6841 10:52:11.314997
6842 10:52:11.315069 Final RX Vref Byte 0 = 51 to rank0
6843 10:52:11.318807 Final RX Vref Byte 1 = 57 to rank0
6844 10:52:11.321652 Final RX Vref Byte 0 = 51 to rank1
6845 10:52:11.325245 Final RX Vref Byte 1 = 57 to rank1==
6846 10:52:11.328197 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 10:52:11.334904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 10:52:11.334978 ==
6849 10:52:11.335040 DQS Delay:
6850 10:52:11.338488 DQS0 = 32, DQS1 = 40
6851 10:52:11.338561 DQM Delay:
6852 10:52:11.338626 DQM0 = 11, DQM1 = 12
6853 10:52:11.341829 DQ Delay:
6854 10:52:11.345027 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6855 10:52:11.348379 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6856 10:52:11.348452 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6857 10:52:11.351434 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6858 10:52:11.355020
6859 10:52:11.355092
6860 10:52:11.361599 [DQSOSCAuto] RK0, (LSB)MR18= 0x90cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6861 10:52:11.364878 CH1 RK0: MR19=C0C, MR18=90CB
6862 10:52:11.371346 CH1_RK0: MR19=0xC0C, MR18=0x90CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6863 10:52:11.371421 ==
6864 10:52:11.374906 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 10:52:11.377805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 10:52:11.377880 ==
6867 10:52:11.381273 [Gating] SW mode calibration
6868 10:52:11.387953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6869 10:52:11.394334 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6870 10:52:11.397943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 10:52:11.401156 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 10:52:11.407939 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 10:52:11.411253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 10:52:11.414619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 10:52:11.420962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 10:52:11.424200 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 10:52:11.427447 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 10:52:11.434402 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 10:52:11.434485 Total UI for P1: 0, mck2ui 16
6880 10:52:11.441120 best dqsien dly found for B0: ( 0, 14, 24)
6881 10:52:11.441271 Total UI for P1: 0, mck2ui 16
6882 10:52:11.447324 best dqsien dly found for B1: ( 0, 14, 24)
6883 10:52:11.450679 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6884 10:52:11.454174 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6885 10:52:11.454259
6886 10:52:11.457101 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 10:52:11.460556 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 10:52:11.463829 [Gating] SW calibration Done
6889 10:52:11.463913 ==
6890 10:52:11.467096 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 10:52:11.470338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 10:52:11.470422 ==
6893 10:52:11.473913 RX Vref Scan: 0
6894 10:52:11.473995
6895 10:52:11.474061 RX Vref 0 -> 0, step: 1
6896 10:52:11.474120
6897 10:52:11.477334 RX Delay -410 -> 252, step: 16
6898 10:52:11.483740 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6899 10:52:11.486764 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6900 10:52:11.490430 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6901 10:52:11.493362 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6902 10:52:11.499964 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6903 10:52:11.503612 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6904 10:52:11.506493 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6905 10:52:11.509857 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6906 10:52:11.516689 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6907 10:52:11.519978 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6908 10:52:11.523010 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6909 10:52:11.529838 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6910 10:52:11.533046 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6911 10:52:11.536039 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6912 10:52:11.539598 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6913 10:52:11.546302 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6914 10:52:11.546387 ==
6915 10:52:11.549278 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 10:52:11.552624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 10:52:11.552712 ==
6918 10:52:11.552820 DQS Delay:
6919 10:52:11.556259 DQS0 = 35, DQS1 = 43
6920 10:52:11.556342 DQM Delay:
6921 10:52:11.559311 DQM0 = 16, DQM1 = 19
6922 10:52:11.559395 DQ Delay:
6923 10:52:11.562266 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6924 10:52:11.565696 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6925 10:52:11.569288 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6926 10:52:11.572274 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6927 10:52:11.572358
6928 10:52:11.572425
6929 10:52:11.572487 ==
6930 10:52:11.575671 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 10:52:11.579098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 10:52:11.582245 ==
6933 10:52:11.582329
6934 10:52:11.582395
6935 10:52:11.582455 TX Vref Scan disable
6936 10:52:11.585706 == TX Byte 0 ==
6937 10:52:11.588796 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6938 10:52:11.592403 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6939 10:52:11.595240 == TX Byte 1 ==
6940 10:52:11.598711 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6941 10:52:11.602101 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6942 10:52:11.602185 ==
6943 10:52:11.605421 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 10:52:11.611945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 10:52:11.612029 ==
6946 10:52:11.612095
6947 10:52:11.612156
6948 10:52:11.612215 TX Vref Scan disable
6949 10:52:11.615237 == TX Byte 0 ==
6950 10:52:11.618318 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6951 10:52:11.621774 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6952 10:52:11.624751 == TX Byte 1 ==
6953 10:52:11.628329 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6954 10:52:11.631554 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6955 10:52:11.631639
6956 10:52:11.634828 [DATLAT]
6957 10:52:11.634911 Freq=400, CH1 RK1
6958 10:52:11.634978
6959 10:52:11.638053 DATLAT Default: 0xe
6960 10:52:11.638138 0, 0xFFFF, sum = 0
6961 10:52:11.641210 1, 0xFFFF, sum = 0
6962 10:52:11.641297 2, 0xFFFF, sum = 0
6963 10:52:11.644535 3, 0xFFFF, sum = 0
6964 10:52:11.644646 4, 0xFFFF, sum = 0
6965 10:52:11.648067 5, 0xFFFF, sum = 0
6966 10:52:11.648169 6, 0xFFFF, sum = 0
6967 10:52:11.651183 7, 0xFFFF, sum = 0
6968 10:52:11.654513 8, 0xFFFF, sum = 0
6969 10:52:11.654598 9, 0xFFFF, sum = 0
6970 10:52:11.658036 10, 0xFFFF, sum = 0
6971 10:52:11.658121 11, 0xFFFF, sum = 0
6972 10:52:11.661096 12, 0xFFFF, sum = 0
6973 10:52:11.661180 13, 0x0, sum = 1
6974 10:52:11.664479 14, 0x0, sum = 2
6975 10:52:11.664564 15, 0x0, sum = 3
6976 10:52:11.667662 16, 0x0, sum = 4
6977 10:52:11.667748 best_step = 14
6978 10:52:11.667814
6979 10:52:11.667875 ==
6980 10:52:11.671178 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 10:52:11.674415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 10:52:11.674500 ==
6983 10:52:11.677723 RX Vref Scan: 0
6984 10:52:11.677806
6985 10:52:11.681245 RX Vref 0 -> 0, step: 1
6986 10:52:11.681329
6987 10:52:11.681394 RX Delay -327 -> 252, step: 8
6988 10:52:11.689861 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6989 10:52:11.692921 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6990 10:52:11.696606 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6991 10:52:11.702980 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6992 10:52:11.706226 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6993 10:52:11.709824 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6994 10:52:11.713098 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6995 10:52:11.719502 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6996 10:52:11.722605 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6997 10:52:11.725977 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6998 10:52:11.729528 iDelay=217, Bit 10, Center -24 (-255 ~ 208) 464
6999 10:52:11.736047 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7000 10:52:11.739208 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7001 10:52:11.742709 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7002 10:52:11.745907 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7003 10:52:11.752444 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7004 10:52:11.752563 ==
7005 10:52:11.756085 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 10:52:11.759079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 10:52:11.759197 ==
7008 10:52:11.759297 DQS Delay:
7009 10:52:11.762364 DQS0 = 32, DQS1 = 40
7010 10:52:11.762479 DQM Delay:
7011 10:52:11.765839 DQM0 = 11, DQM1 = 14
7012 10:52:11.765943 DQ Delay:
7013 10:52:11.768902 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7014 10:52:11.772281 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7015 10:52:11.775660 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7016 10:52:11.778831 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7017 10:52:11.778943
7018 10:52:11.779049
7019 10:52:11.788976 [DQSOSCAuto] RK1, (LSB)MR18= 0xa84f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7020 10:52:11.789063 CH1 RK1: MR19=C0C, MR18=A84F
7021 10:52:11.795498 CH1_RK1: MR19=0xC0C, MR18=0xA84F, DQSOSC=388, MR23=63, INC=392, DEC=261
7022 10:52:11.798522 [RxdqsGatingPostProcess] freq 400
7023 10:52:11.805233 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7024 10:52:11.808555 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 10:52:11.811698 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 10:52:11.814963 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 10:52:11.818308 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 10:52:11.821788 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 10:52:11.821862 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 10:52:11.825055 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 10:52:11.828459 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 10:52:11.831496 Pre-setting of DQS Precalculation
7033 10:52:11.838484 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7034 10:52:11.844904 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7035 10:52:11.851527 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7036 10:52:11.851611
7037 10:52:11.851677
7038 10:52:11.854721 [Calibration Summary] 800 Mbps
7039 10:52:11.858150 CH 0, Rank 0
7040 10:52:11.858233 SW Impedance : PASS
7041 10:52:11.861173 DUTY Scan : NO K
7042 10:52:11.864660 ZQ Calibration : PASS
7043 10:52:11.864744 Jitter Meter : NO K
7044 10:52:11.868152 CBT Training : PASS
7045 10:52:11.868235 Write leveling : PASS
7046 10:52:11.871574 RX DQS gating : PASS
7047 10:52:11.874452 RX DQ/DQS(RDDQC) : PASS
7048 10:52:11.874535 TX DQ/DQS : PASS
7049 10:52:11.877825 RX DATLAT : PASS
7050 10:52:11.881186 RX DQ/DQS(Engine): PASS
7051 10:52:11.881270 TX OE : NO K
7052 10:52:11.884582 All Pass.
7053 10:52:11.884665
7054 10:52:11.884731 CH 0, Rank 1
7055 10:52:11.887686 SW Impedance : PASS
7056 10:52:11.887769 DUTY Scan : NO K
7057 10:52:11.891033 ZQ Calibration : PASS
7058 10:52:11.894486 Jitter Meter : NO K
7059 10:52:11.894569 CBT Training : PASS
7060 10:52:11.897480 Write leveling : NO K
7061 10:52:11.900673 RX DQS gating : PASS
7062 10:52:11.900757 RX DQ/DQS(RDDQC) : PASS
7063 10:52:11.904213 TX DQ/DQS : PASS
7064 10:52:11.907580 RX DATLAT : PASS
7065 10:52:11.907664 RX DQ/DQS(Engine): PASS
7066 10:52:11.910893 TX OE : NO K
7067 10:52:11.910976 All Pass.
7068 10:52:11.911041
7069 10:52:11.914387 CH 1, Rank 0
7070 10:52:11.914470 SW Impedance : PASS
7071 10:52:11.917679 DUTY Scan : NO K
7072 10:52:11.920987 ZQ Calibration : PASS
7073 10:52:11.921070 Jitter Meter : NO K
7074 10:52:11.924013 CBT Training : PASS
7075 10:52:11.927422 Write leveling : PASS
7076 10:52:11.927506 RX DQS gating : PASS
7077 10:52:11.930493 RX DQ/DQS(RDDQC) : PASS
7078 10:52:11.930576 TX DQ/DQS : PASS
7079 10:52:11.934023 RX DATLAT : PASS
7080 10:52:11.937286 RX DQ/DQS(Engine): PASS
7081 10:52:11.937369 TX OE : NO K
7082 10:52:11.940438 All Pass.
7083 10:52:11.940521
7084 10:52:11.940586 CH 1, Rank 1
7085 10:52:11.944020 SW Impedance : PASS
7086 10:52:11.944105 DUTY Scan : NO K
7087 10:52:11.946950 ZQ Calibration : PASS
7088 10:52:11.950340 Jitter Meter : NO K
7089 10:52:11.950424 CBT Training : PASS
7090 10:52:11.953743 Write leveling : NO K
7091 10:52:11.957090 RX DQS gating : PASS
7092 10:52:11.957175 RX DQ/DQS(RDDQC) : PASS
7093 10:52:11.960267 TX DQ/DQS : PASS
7094 10:52:11.963707 RX DATLAT : PASS
7095 10:52:11.963817 RX DQ/DQS(Engine): PASS
7096 10:52:11.966911 TX OE : NO K
7097 10:52:11.966994 All Pass.
7098 10:52:11.967070
7099 10:52:11.970276 DramC Write-DBI off
7100 10:52:11.973479 PER_BANK_REFRESH: Hybrid Mode
7101 10:52:11.973583 TX_TRACKING: ON
7102 10:52:11.983208 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7103 10:52:11.986482 [FAST_K] Save calibration result to emmc
7104 10:52:11.989927 dramc_set_vcore_voltage set vcore to 725000
7105 10:52:11.993098 Read voltage for 1600, 0
7106 10:52:11.993184 Vio18 = 0
7107 10:52:11.993271 Vcore = 725000
7108 10:52:11.996691 Vdram = 0
7109 10:52:11.996803 Vddq = 0
7110 10:52:11.996890 Vmddr = 0
7111 10:52:12.003052 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7112 10:52:12.006633 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7113 10:52:12.009817 MEM_TYPE=3, freq_sel=13
7114 10:52:12.012971 sv_algorithm_assistance_LP4_3733
7115 10:52:12.016463 ============ PULL DRAM RESETB DOWN ============
7116 10:52:12.022758 ========== PULL DRAM RESETB DOWN end =========
7117 10:52:12.026049 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7118 10:52:12.029656 ===================================
7119 10:52:12.032692 LPDDR4 DRAM CONFIGURATION
7120 10:52:12.035862 ===================================
7121 10:52:12.035936 EX_ROW_EN[0] = 0x0
7122 10:52:12.039222 EX_ROW_EN[1] = 0x0
7123 10:52:12.039296 LP4Y_EN = 0x0
7124 10:52:12.042747 WORK_FSP = 0x1
7125 10:52:12.042820 WL = 0x5
7126 10:52:12.046125 RL = 0x5
7127 10:52:12.049434 BL = 0x2
7128 10:52:12.049505 RPST = 0x0
7129 10:52:12.052595 RD_PRE = 0x0
7130 10:52:12.052695 WR_PRE = 0x1
7131 10:52:12.055694 WR_PST = 0x1
7132 10:52:12.055767 DBI_WR = 0x0
7133 10:52:12.059064 DBI_RD = 0x0
7134 10:52:12.059132 OTF = 0x1
7135 10:52:12.062429 ===================================
7136 10:52:12.065775 ===================================
7137 10:52:12.068914 ANA top config
7138 10:52:12.071970 ===================================
7139 10:52:12.072039 DLL_ASYNC_EN = 0
7140 10:52:12.075498 ALL_SLAVE_EN = 0
7141 10:52:12.078716 NEW_RANK_MODE = 1
7142 10:52:12.081991 DLL_IDLE_MODE = 1
7143 10:52:12.085142 LP45_APHY_COMB_EN = 1
7144 10:52:12.085212 TX_ODT_DIS = 0
7145 10:52:12.088641 NEW_8X_MODE = 1
7146 10:52:12.091945 ===================================
7147 10:52:12.095401 ===================================
7148 10:52:12.098587 data_rate = 3200
7149 10:52:12.101779 CKR = 1
7150 10:52:12.105591 DQ_P2S_RATIO = 8
7151 10:52:12.108780 ===================================
7152 10:52:12.108852 CA_P2S_RATIO = 8
7153 10:52:12.111893 DQ_CA_OPEN = 0
7154 10:52:12.115185 DQ_SEMI_OPEN = 0
7155 10:52:12.118652 CA_SEMI_OPEN = 0
7156 10:52:12.121827 CA_FULL_RATE = 0
7157 10:52:12.125129 DQ_CKDIV4_EN = 0
7158 10:52:12.128182 CA_CKDIV4_EN = 0
7159 10:52:12.128267 CA_PREDIV_EN = 0
7160 10:52:12.131462 PH8_DLY = 12
7161 10:52:12.134837 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7162 10:52:12.138160 DQ_AAMCK_DIV = 4
7163 10:52:12.141421 CA_AAMCK_DIV = 4
7164 10:52:12.145136 CA_ADMCK_DIV = 4
7165 10:52:12.145220 DQ_TRACK_CA_EN = 0
7166 10:52:12.148186 CA_PICK = 1600
7167 10:52:12.151395 CA_MCKIO = 1600
7168 10:52:12.154902 MCKIO_SEMI = 0
7169 10:52:12.157951 PLL_FREQ = 3068
7170 10:52:12.161768 DQ_UI_PI_RATIO = 32
7171 10:52:12.164641 CA_UI_PI_RATIO = 0
7172 10:52:12.167934 ===================================
7173 10:52:12.171444 ===================================
7174 10:52:12.171530 memory_type:LPDDR4
7175 10:52:12.174823 GP_NUM : 10
7176 10:52:12.178012 SRAM_EN : 1
7177 10:52:12.178091 MD32_EN : 0
7178 10:52:12.181019 ===================================
7179 10:52:12.184540 [ANA_INIT] >>>>>>>>>>>>>>
7180 10:52:12.187501 <<<<<< [CONFIGURE PHASE]: ANA_TX
7181 10:52:12.191062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7182 10:52:12.194456 ===================================
7183 10:52:12.197553 data_rate = 3200,PCW = 0X7600
7184 10:52:12.200704 ===================================
7185 10:52:12.204156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7186 10:52:12.207563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 10:52:12.213875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 10:52:12.217519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7189 10:52:12.223806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7190 10:52:12.226983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7191 10:52:12.227065 [ANA_INIT] flow start
7192 10:52:12.230512 [ANA_INIT] PLL >>>>>>>>
7193 10:52:12.233692 [ANA_INIT] PLL <<<<<<<<
7194 10:52:12.233769 [ANA_INIT] MIDPI >>>>>>>>
7195 10:52:12.237023 [ANA_INIT] MIDPI <<<<<<<<
7196 10:52:12.240194 [ANA_INIT] DLL >>>>>>>>
7197 10:52:12.240276 [ANA_INIT] DLL <<<<<<<<
7198 10:52:12.243665 [ANA_INIT] flow end
7199 10:52:12.246910 ============ LP4 DIFF to SE enter ============
7200 10:52:12.250332 ============ LP4 DIFF to SE exit ============
7201 10:52:12.253265 [ANA_INIT] <<<<<<<<<<<<<
7202 10:52:12.256435 [Flow] Enable top DCM control >>>>>
7203 10:52:12.259727 [Flow] Enable top DCM control <<<<<
7204 10:52:12.263221 Enable DLL master slave shuffle
7205 10:52:12.269967 ==============================================================
7206 10:52:12.270071 Gating Mode config
7207 10:52:12.276518 ==============================================================
7208 10:52:12.279533 Config description:
7209 10:52:12.289373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7210 10:52:12.296119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7211 10:52:12.299295 SELPH_MODE 0: By rank 1: By Phase
7212 10:52:12.306054 ==============================================================
7213 10:52:12.309221 GAT_TRACK_EN = 1
7214 10:52:12.312958 RX_GATING_MODE = 2
7215 10:52:12.313042 RX_GATING_TRACK_MODE = 2
7216 10:52:12.316025 SELPH_MODE = 1
7217 10:52:12.319194 PICG_EARLY_EN = 1
7218 10:52:12.323043 VALID_LAT_VALUE = 1
7219 10:52:12.328958 ==============================================================
7220 10:52:12.332427 Enter into Gating configuration >>>>
7221 10:52:12.335776 Exit from Gating configuration <<<<
7222 10:52:12.339005 Enter into DVFS_PRE_config >>>>>
7223 10:52:12.348678 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7224 10:52:12.352148 Exit from DVFS_PRE_config <<<<<
7225 10:52:12.355624 Enter into PICG configuration >>>>
7226 10:52:12.358963 Exit from PICG configuration <<<<
7227 10:52:12.362182 [RX_INPUT] configuration >>>>>
7228 10:52:12.365680 [RX_INPUT] configuration <<<<<
7229 10:52:12.368704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7230 10:52:12.375199 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7231 10:52:12.381771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 10:52:12.388478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 10:52:12.395264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 10:52:12.398585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 10:52:12.405314 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7236 10:52:12.408312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7237 10:52:12.412072 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7238 10:52:12.415182 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7239 10:52:12.418236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7240 10:52:12.425020 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 10:52:12.428416 ===================================
7242 10:52:12.431382 LPDDR4 DRAM CONFIGURATION
7243 10:52:12.435092 ===================================
7244 10:52:12.435177 EX_ROW_EN[0] = 0x0
7245 10:52:12.438346 EX_ROW_EN[1] = 0x0
7246 10:52:12.438432 LP4Y_EN = 0x0
7247 10:52:12.441446 WORK_FSP = 0x1
7248 10:52:12.441530 WL = 0x5
7249 10:52:12.444924 RL = 0x5
7250 10:52:12.445007 BL = 0x2
7251 10:52:12.448064 RPST = 0x0
7252 10:52:12.448148 RD_PRE = 0x0
7253 10:52:12.451434 WR_PRE = 0x1
7254 10:52:12.451528 WR_PST = 0x1
7255 10:52:12.454828 DBI_WR = 0x0
7256 10:52:12.457867 DBI_RD = 0x0
7257 10:52:12.457950 OTF = 0x1
7258 10:52:12.461054 ===================================
7259 10:52:12.464454 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7260 10:52:12.467762 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7261 10:52:12.474207 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 10:52:12.477887 ===================================
7263 10:52:12.480959 LPDDR4 DRAM CONFIGURATION
7264 10:52:12.484068 ===================================
7265 10:52:12.484151 EX_ROW_EN[0] = 0x10
7266 10:52:12.487582 EX_ROW_EN[1] = 0x0
7267 10:52:12.487665 LP4Y_EN = 0x0
7268 10:52:12.491107 WORK_FSP = 0x1
7269 10:52:12.491190 WL = 0x5
7270 10:52:12.494236 RL = 0x5
7271 10:52:12.494320 BL = 0x2
7272 10:52:12.497550 RPST = 0x0
7273 10:52:12.497633 RD_PRE = 0x0
7274 10:52:12.500802 WR_PRE = 0x1
7275 10:52:12.503952 WR_PST = 0x1
7276 10:52:12.504035 DBI_WR = 0x0
7277 10:52:12.507193 DBI_RD = 0x0
7278 10:52:12.507276 OTF = 0x1
7279 10:52:12.510575 ===================================
7280 10:52:12.517153 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7281 10:52:12.517238 ==
7282 10:52:12.520676 Dram Type= 6, Freq= 0, CH_0, rank 0
7283 10:52:12.524361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 10:52:12.524448 ==
7285 10:52:12.527029 [Duty_Offset_Calibration]
7286 10:52:12.530467 B0:2 B1:0 CA:1
7287 10:52:12.530550
7288 10:52:12.533807 [DutyScan_Calibration_Flow] k_type=0
7289 10:52:12.541151
7290 10:52:12.541242 ==CLK 0==
7291 10:52:12.544539 Final CLK duty delay cell = -4
7292 10:52:12.547591 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7293 10:52:12.551320 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7294 10:52:12.554308 [-4] AVG Duty = 4906%(X100)
7295 10:52:12.554392
7296 10:52:12.557653 CH0 CLK Duty spec in!! Max-Min= 187%
7297 10:52:12.561090 [DutyScan_Calibration_Flow] ====Done====
7298 10:52:12.561174
7299 10:52:12.564475 [DutyScan_Calibration_Flow] k_type=1
7300 10:52:12.580631
7301 10:52:12.580717 ==DQS 0 ==
7302 10:52:12.583911 Final DQS duty delay cell = 0
7303 10:52:12.586990 [0] MAX Duty = 5249%(X100), DQS PI = 32
7304 10:52:12.590430 [0] MIN Duty = 4969%(X100), DQS PI = 0
7305 10:52:12.593749 [0] AVG Duty = 5109%(X100)
7306 10:52:12.593833
7307 10:52:12.593898 ==DQS 1 ==
7308 10:52:12.597282 Final DQS duty delay cell = -4
7309 10:52:12.600255 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7310 10:52:12.603849 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7311 10:52:12.607070 [-4] AVG Duty = 5000%(X100)
7312 10:52:12.607154
7313 10:52:12.610315 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7314 10:52:12.610398
7315 10:52:12.613560 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7316 10:52:12.616994 [DutyScan_Calibration_Flow] ====Done====
7317 10:52:12.617077
7318 10:52:12.620039 [DutyScan_Calibration_Flow] k_type=3
7319 10:52:12.638052
7320 10:52:12.638159 ==DQM 0 ==
7321 10:52:12.641865 Final DQM duty delay cell = 0
7322 10:52:12.645014 [0] MAX Duty = 5093%(X100), DQS PI = 26
7323 10:52:12.648105 [0] MIN Duty = 4844%(X100), DQS PI = 2
7324 10:52:12.648191 [0] AVG Duty = 4968%(X100)
7325 10:52:12.651431
7326 10:52:12.651515 ==DQM 1 ==
7327 10:52:12.654803 Final DQM duty delay cell = 0
7328 10:52:12.657862 [0] MAX Duty = 5280%(X100), DQS PI = 46
7329 10:52:12.661652 [0] MIN Duty = 5000%(X100), DQS PI = 20
7330 10:52:12.664510 [0] AVG Duty = 5140%(X100)
7331 10:52:12.664619
7332 10:52:12.667999 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7333 10:52:12.668082
7334 10:52:12.671433 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7335 10:52:12.674268 [DutyScan_Calibration_Flow] ====Done====
7336 10:52:12.674352
7337 10:52:12.677696 [DutyScan_Calibration_Flow] k_type=2
7338 10:52:12.695362
7339 10:52:12.695478 ==DQ 0 ==
7340 10:52:12.698722 Final DQ duty delay cell = 0
7341 10:52:12.702046 [0] MAX Duty = 5156%(X100), DQS PI = 36
7342 10:52:12.705395 [0] MIN Duty = 5000%(X100), DQS PI = 16
7343 10:52:12.705479 [0] AVG Duty = 5078%(X100)
7344 10:52:12.708349
7345 10:52:12.708433 ==DQ 1 ==
7346 10:52:12.712054 Final DQ duty delay cell = 0
7347 10:52:12.715290 [0] MAX Duty = 4969%(X100), DQS PI = 44
7348 10:52:12.718413 [0] MIN Duty = 4875%(X100), DQS PI = 10
7349 10:52:12.718537 [0] AVG Duty = 4922%(X100)
7350 10:52:12.721485
7351 10:52:12.725116 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7352 10:52:12.725201
7353 10:52:12.728528 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7354 10:52:12.731646 [DutyScan_Calibration_Flow] ====Done====
7355 10:52:12.731731 ==
7356 10:52:12.734959 Dram Type= 6, Freq= 0, CH_1, rank 0
7357 10:52:12.738500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7358 10:52:12.738586 ==
7359 10:52:12.741419 [Duty_Offset_Calibration]
7360 10:52:12.741502 B0:0 B1:-1 CA:2
7361 10:52:12.741566
7362 10:52:12.744520 [DutyScan_Calibration_Flow] k_type=0
7363 10:52:12.755295
7364 10:52:12.755383 ==CLK 0==
7365 10:52:12.758833 Final CLK duty delay cell = 0
7366 10:52:12.762221 [0] MAX Duty = 5156%(X100), DQS PI = 10
7367 10:52:12.765403 [0] MIN Duty = 4938%(X100), DQS PI = 44
7368 10:52:12.768536 [0] AVG Duty = 5047%(X100)
7369 10:52:12.768618
7370 10:52:12.771900 CH1 CLK Duty spec in!! Max-Min= 218%
7371 10:52:12.775324 [DutyScan_Calibration_Flow] ====Done====
7372 10:52:12.775417
7373 10:52:12.778280 [DutyScan_Calibration_Flow] k_type=1
7374 10:52:12.795415
7375 10:52:12.795544 ==DQS 0 ==
7376 10:52:12.798440 Final DQS duty delay cell = 0
7377 10:52:12.801627 [0] MAX Duty = 5124%(X100), DQS PI = 26
7378 10:52:12.805226 [0] MIN Duty = 4969%(X100), DQS PI = 2
7379 10:52:12.808297 [0] AVG Duty = 5046%(X100)
7380 10:52:12.808394
7381 10:52:12.808484 ==DQS 1 ==
7382 10:52:12.811915 Final DQS duty delay cell = 0
7383 10:52:12.815112 [0] MAX Duty = 5187%(X100), DQS PI = 0
7384 10:52:12.818391 [0] MIN Duty = 4844%(X100), DQS PI = 32
7385 10:52:12.821812 [0] AVG Duty = 5015%(X100)
7386 10:52:12.821910
7387 10:52:12.825021 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7388 10:52:12.825119
7389 10:52:12.828351 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7390 10:52:12.831567 [DutyScan_Calibration_Flow] ====Done====
7391 10:52:12.831674
7392 10:52:12.835069 [DutyScan_Calibration_Flow] k_type=3
7393 10:52:12.852860
7394 10:52:12.852987 ==DQM 0 ==
7395 10:52:12.856184 Final DQM duty delay cell = 4
7396 10:52:12.859285 [4] MAX Duty = 5156%(X100), DQS PI = 24
7397 10:52:12.862699 [4] MIN Duty = 5000%(X100), DQS PI = 30
7398 10:52:12.865854 [4] AVG Duty = 5078%(X100)
7399 10:52:12.865970
7400 10:52:12.866069 ==DQM 1 ==
7401 10:52:12.869231 Final DQM duty delay cell = 0
7402 10:52:12.872371 [0] MAX Duty = 5249%(X100), DQS PI = 58
7403 10:52:12.875749 [0] MIN Duty = 4876%(X100), DQS PI = 34
7404 10:52:12.879038 [0] AVG Duty = 5062%(X100)
7405 10:52:12.879120
7406 10:52:12.882501 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7407 10:52:12.882609
7408 10:52:12.885533 CH1 DQM 1 Duty spec in!! Max-Min= 373%
7409 10:52:12.889271 [DutyScan_Calibration_Flow] ====Done====
7410 10:52:12.889354
7411 10:52:12.892467 [DutyScan_Calibration_Flow] k_type=2
7412 10:52:12.909637
7413 10:52:12.909728 ==DQ 0 ==
7414 10:52:12.913210 Final DQ duty delay cell = 0
7415 10:52:12.916205 [0] MAX Duty = 5093%(X100), DQS PI = 22
7416 10:52:12.919705 [0] MIN Duty = 4969%(X100), DQS PI = 46
7417 10:52:12.919788 [0] AVG Duty = 5031%(X100)
7418 10:52:12.922960
7419 10:52:12.923041 ==DQ 1 ==
7420 10:52:12.926429 Final DQ duty delay cell = 0
7421 10:52:12.929657 [0] MAX Duty = 5062%(X100), DQS PI = 2
7422 10:52:12.932653 [0] MIN Duty = 4844%(X100), DQS PI = 32
7423 10:52:12.932734 [0] AVG Duty = 4953%(X100)
7424 10:52:12.936084
7425 10:52:12.939376 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7426 10:52:12.939458
7427 10:52:12.942995 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7428 10:52:12.946049 [DutyScan_Calibration_Flow] ====Done====
7429 10:52:12.949480 nWR fixed to 30
7430 10:52:12.949563 [ModeRegInit_LP4] CH0 RK0
7431 10:52:12.952863 [ModeRegInit_LP4] CH0 RK1
7432 10:52:12.955834 [ModeRegInit_LP4] CH1 RK0
7433 10:52:12.959293 [ModeRegInit_LP4] CH1 RK1
7434 10:52:12.959375 match AC timing 5
7435 10:52:12.966004 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7436 10:52:12.969228 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7437 10:52:12.972518 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7438 10:52:12.979359 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7439 10:52:12.982465 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7440 10:52:12.982551 [MiockJmeterHQA]
7441 10:52:12.982617
7442 10:52:12.985673 [DramcMiockJmeter] u1RxGatingPI = 0
7443 10:52:12.989195 0 : 4363, 4137
7444 10:52:12.989283 4 : 4255, 4029
7445 10:52:12.992232 8 : 4252, 4027
7446 10:52:12.992317 12 : 4252, 4027
7447 10:52:12.995614 16 : 4253, 4026
7448 10:52:12.995699 20 : 4252, 4027
7449 10:52:12.995766 24 : 4253, 4027
7450 10:52:12.998973 28 : 4363, 4137
7451 10:52:12.999057 32 : 4253, 4027
7452 10:52:13.002138 36 : 4252, 4026
7453 10:52:13.002228 40 : 4249, 4027
7454 10:52:13.005340 44 : 4253, 4027
7455 10:52:13.005427 48 : 4250, 4027
7456 10:52:13.005496 52 : 4361, 4138
7457 10:52:13.008842 56 : 4361, 4137
7458 10:52:13.008928 60 : 4249, 4027
7459 10:52:13.011899 64 : 4250, 4027
7460 10:52:13.011986 68 : 4250, 4027
7461 10:52:13.015395 72 : 4249, 4027
7462 10:52:13.015482 76 : 4250, 4027
7463 10:52:13.018634 80 : 4361, 4138
7464 10:52:13.018747 84 : 4250, 4027
7465 10:52:13.018845 88 : 4250, 3687
7466 10:52:13.021827 92 : 4250, 0
7467 10:52:13.021914 96 : 4361, 0
7468 10:52:13.025392 100 : 4250, 0
7469 10:52:13.025478 104 : 4250, 0
7470 10:52:13.025547 108 : 4253, 0
7471 10:52:13.028646 112 : 4250, 0
7472 10:52:13.028760 116 : 4252, 0
7473 10:52:13.031963 120 : 4363, 0
7474 10:52:13.032051 124 : 4250, 0
7475 10:52:13.032119 128 : 4250, 0
7476 10:52:13.035672 132 : 4250, 0
7477 10:52:13.035759 136 : 4360, 0
7478 10:52:13.035827 140 : 4360, 0
7479 10:52:13.038638 144 : 4250, 0
7480 10:52:13.038725 148 : 4252, 0
7481 10:52:13.041825 152 : 4250, 0
7482 10:52:13.041913 156 : 4250, 0
7483 10:52:13.041982 160 : 4250, 0
7484 10:52:13.045377 164 : 4250, 0
7485 10:52:13.045467 168 : 4252, 0
7486 10:52:13.048400 172 : 4361, 0
7487 10:52:13.048514 176 : 4250, 0
7488 10:52:13.048611 180 : 4250, 0
7489 10:52:13.051636 184 : 4250, 0
7490 10:52:13.051724 188 : 4360, 0
7491 10:52:13.055080 192 : 4360, 0
7492 10:52:13.055185 196 : 4250, 0
7493 10:52:13.055274 200 : 4250, 21
7494 10:52:13.058370 204 : 4361, 2692
7495 10:52:13.058448 208 : 4250, 4027
7496 10:52:13.061764 212 : 4250, 4027
7497 10:52:13.061855 216 : 4250, 4027
7498 10:52:13.065229 220 : 4253, 4029
7499 10:52:13.065318 224 : 4250, 4027
7500 10:52:13.068306 228 : 4249, 4027
7501 10:52:13.068404 232 : 4360, 4137
7502 10:52:13.071767 236 : 4250, 4027
7503 10:52:13.071846 240 : 4250, 4027
7504 10:52:13.074801 244 : 4360, 4138
7505 10:52:13.074884 248 : 4249, 4027
7506 10:52:13.074966 252 : 4250, 4027
7507 10:52:13.078464 256 : 4361, 4137
7508 10:52:13.078541 260 : 4250, 4027
7509 10:52:13.081416 264 : 4249, 4027
7510 10:52:13.081498 268 : 4250, 4027
7511 10:52:13.084601 272 : 4250, 4027
7512 10:52:13.084678 276 : 4250, 4027
7513 10:52:13.087992 280 : 4250, 4027
7514 10:52:13.088070 284 : 4360, 4137
7515 10:52:13.091383 288 : 4250, 4027
7516 10:52:13.091460 292 : 4250, 4027
7517 10:52:13.094941 296 : 4361, 4138
7518 10:52:13.095020 300 : 4249, 4027
7519 10:52:13.097907 304 : 4250, 4026
7520 10:52:13.097983 308 : 4361, 4137
7521 10:52:13.101588 312 : 4250, 3849
7522 10:52:13.101664 316 : 4249, 2073
7523 10:52:13.101744
7524 10:52:13.104492 MIOCK jitter meter ch=0
7525 10:52:13.104568
7526 10:52:13.108062 1T = (316-92) = 224 dly cells
7527 10:52:13.111356 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7528 10:52:13.111435 ==
7529 10:52:13.114243 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 10:52:13.121101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 10:52:13.121184 ==
7532 10:52:13.124592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 10:52:13.131050 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 10:52:13.134269 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 10:52:13.140691 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 10:52:13.148533 [CA 0] Center 43 (13~73) winsize 61
7537 10:52:13.152073 [CA 1] Center 43 (13~73) winsize 61
7538 10:52:13.155479 [CA 2] Center 38 (8~68) winsize 61
7539 10:52:13.158392 [CA 3] Center 37 (8~67) winsize 60
7540 10:52:13.161844 [CA 4] Center 36 (6~66) winsize 61
7541 10:52:13.165098 [CA 5] Center 35 (5~65) winsize 61
7542 10:52:13.165183
7543 10:52:13.168425 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7544 10:52:13.168509
7545 10:52:13.171561 [CATrainingPosCal] consider 1 rank data
7546 10:52:13.175039 u2DelayCellTimex100 = 290/100 ps
7547 10:52:13.181943 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7548 10:52:13.184780 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7549 10:52:13.188360 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7550 10:52:13.191603 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7551 10:52:13.194906 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7552 10:52:13.198301 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7553 10:52:13.198386
7554 10:52:13.201437 CA PerBit enable=1, Macro0, CA PI delay=35
7555 10:52:13.201522
7556 10:52:13.204951 [CBTSetCACLKResult] CA Dly = 35
7557 10:52:13.208337 CS Dly: 10 (0~41)
7558 10:52:13.211312 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 10:52:13.214702 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 10:52:13.214788 ==
7561 10:52:13.217919 Dram Type= 6, Freq= 0, CH_0, rank 1
7562 10:52:13.224703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 10:52:13.224844 ==
7564 10:52:13.228272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7565 10:52:13.234729 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7566 10:52:13.238109 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7567 10:52:13.244500 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7568 10:52:13.252027 [CA 0] Center 43 (13~73) winsize 61
7569 10:52:13.255400 [CA 1] Center 43 (13~73) winsize 61
7570 10:52:13.258393 [CA 2] Center 37 (8~67) winsize 60
7571 10:52:13.261748 [CA 3] Center 38 (8~68) winsize 61
7572 10:52:13.265393 [CA 4] Center 36 (6~66) winsize 61
7573 10:52:13.268528 [CA 5] Center 36 (6~66) winsize 61
7574 10:52:13.268612
7575 10:52:13.271553 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7576 10:52:13.271636
7577 10:52:13.278227 [CATrainingPosCal] consider 2 rank data
7578 10:52:13.278317 u2DelayCellTimex100 = 290/100 ps
7579 10:52:13.284841 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7580 10:52:13.288263 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7581 10:52:13.291613 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7582 10:52:13.294722 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7583 10:52:13.297935 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7584 10:52:13.301409 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7585 10:52:13.301495
7586 10:52:13.304986 CA PerBit enable=1, Macro0, CA PI delay=35
7587 10:52:13.305070
7588 10:52:13.307945 [CBTSetCACLKResult] CA Dly = 35
7589 10:52:13.311398 CS Dly: 11 (0~43)
7590 10:52:13.314467 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7591 10:52:13.317707 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7592 10:52:13.317807
7593 10:52:13.321087 ----->DramcWriteLeveling(PI) begin...
7594 10:52:13.321176 ==
7595 10:52:13.324479 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 10:52:13.331279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 10:52:13.331423 ==
7598 10:52:13.334339 Write leveling (Byte 0): 37 => 37
7599 10:52:13.337644 Write leveling (Byte 1): 32 => 32
7600 10:52:13.337729 DramcWriteLeveling(PI) end<-----
7601 10:52:13.340801
7602 10:52:13.340898 ==
7603 10:52:13.344048 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 10:52:13.347549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 10:52:13.347656 ==
7606 10:52:13.350836 [Gating] SW mode calibration
7607 10:52:13.357595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7608 10:52:13.364034 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7609 10:52:13.367062 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 10:52:13.370520 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 10:52:13.377254 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7612 10:52:13.380409 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7613 10:52:13.383845 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 10:52:13.390369 1 4 20 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7615 10:52:13.393486 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 10:52:13.396979 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 10:52:13.403624 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 10:52:13.407107 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 10:52:13.410151 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7620 10:52:13.416843 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7621 10:52:13.419974 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7622 10:52:13.423515 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7623 10:52:13.426590 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7624 10:52:13.433321 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 10:52:13.436300 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 10:52:13.439921 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7627 10:52:13.446072 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7628 10:52:13.449486 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7629 10:52:13.456549 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7630 10:52:13.459232 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7631 10:52:13.462656 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 10:52:13.469402 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 10:52:13.472645 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 10:52:13.475981 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 10:52:13.482549 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 10:52:13.485918 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 10:52:13.489211 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7638 10:52:13.492586 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 10:52:13.499046 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 10:52:13.502517 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 10:52:13.505700 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 10:52:13.512261 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 10:52:13.515606 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 10:52:13.519108 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 10:52:13.525714 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 10:52:13.528629 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 10:52:13.535313 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 10:52:13.538669 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 10:52:13.542062 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 10:52:13.545466 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 10:52:13.552249 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 10:52:13.555025 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 10:52:13.561748 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7654 10:52:13.561845 Total UI for P1: 0, mck2ui 16
7655 10:52:13.564868 best dqsien dly found for B0: ( 1, 9, 12)
7656 10:52:13.571741 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 10:52:13.574935 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7658 10:52:13.578339 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 10:52:13.581435 Total UI for P1: 0, mck2ui 16
7660 10:52:13.584608 best dqsien dly found for B1: ( 1, 9, 22)
7661 10:52:13.587891 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7662 10:52:13.594994 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7663 10:52:13.595100
7664 10:52:13.598117 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7665 10:52:13.601542 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7666 10:52:13.604577 [Gating] SW calibration Done
7667 10:52:13.604669 ==
7668 10:52:13.607841 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 10:52:13.611401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 10:52:13.611489 ==
7671 10:52:13.614521 RX Vref Scan: 0
7672 10:52:13.614605
7673 10:52:13.614671 RX Vref 0 -> 0, step: 1
7674 10:52:13.614731
7675 10:52:13.618052 RX Delay 0 -> 252, step: 8
7676 10:52:13.621097 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7677 10:52:13.627778 iDelay=200, Bit 1, Center 143 (96 ~ 191) 96
7678 10:52:13.631195 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7679 10:52:13.634560 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7680 10:52:13.637663 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7681 10:52:13.641132 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7682 10:52:13.644022 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7683 10:52:13.650926 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7684 10:52:13.654333 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7685 10:52:13.657669 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7686 10:52:13.660546 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7687 10:52:13.667454 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7688 10:52:13.670789 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7689 10:52:13.673789 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7690 10:52:13.677487 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7691 10:52:13.680536 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7692 10:52:13.680633 ==
7693 10:52:13.684000 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 10:52:13.690716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 10:52:13.690828 ==
7696 10:52:13.690899 DQS Delay:
7697 10:52:13.693764 DQS0 = 0, DQS1 = 0
7698 10:52:13.693858 DQM Delay:
7699 10:52:13.697167 DQM0 = 139, DQM1 = 126
7700 10:52:13.697256 DQ Delay:
7701 10:52:13.700311 DQ0 =139, DQ1 =143, DQ2 =135, DQ3 =135
7702 10:52:13.703603 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7703 10:52:13.707111 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7704 10:52:13.710044 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7705 10:52:13.710138
7706 10:52:13.710205
7707 10:52:13.710264 ==
7708 10:52:13.713323 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 10:52:13.720064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 10:52:13.720184 ==
7711 10:52:13.720252
7712 10:52:13.720314
7713 10:52:13.720374 TX Vref Scan disable
7714 10:52:13.723796 == TX Byte 0 ==
7715 10:52:13.726914 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7716 10:52:13.733553 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7717 10:52:13.733674 == TX Byte 1 ==
7718 10:52:13.737009 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7719 10:52:13.743649 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7720 10:52:13.743738 ==
7721 10:52:13.747291 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 10:52:13.750018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 10:52:13.750104 ==
7724 10:52:13.763015
7725 10:52:13.765966 TX Vref early break, caculate TX vref
7726 10:52:13.769238 TX Vref=16, minBit 12, minWin=22, winSum=377
7727 10:52:13.772677 TX Vref=18, minBit 6, minWin=23, winSum=388
7728 10:52:13.776139 TX Vref=20, minBit 12, minWin=23, winSum=395
7729 10:52:13.779542 TX Vref=22, minBit 7, minWin=24, winSum=407
7730 10:52:13.782611 TX Vref=24, minBit 0, minWin=25, winSum=412
7731 10:52:13.789286 TX Vref=26, minBit 2, minWin=25, winSum=420
7732 10:52:13.792503 TX Vref=28, minBit 7, minWin=25, winSum=427
7733 10:52:13.795891 TX Vref=30, minBit 3, minWin=25, winSum=422
7734 10:52:13.799085 TX Vref=32, minBit 1, minWin=25, winSum=414
7735 10:52:13.802517 TX Vref=34, minBit 2, minWin=24, winSum=404
7736 10:52:13.809049 [TxChooseVref] Worse bit 7, Min win 25, Win sum 427, Final Vref 28
7737 10:52:13.809135
7738 10:52:13.812539 Final TX Range 0 Vref 28
7739 10:52:13.812623
7740 10:52:13.812688 ==
7741 10:52:13.815796 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 10:52:13.818969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 10:52:13.819055 ==
7744 10:52:13.819122
7745 10:52:13.819182
7746 10:52:13.822415 TX Vref Scan disable
7747 10:52:13.829050 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7748 10:52:13.829180 == TX Byte 0 ==
7749 10:52:13.831987 u2DelayCellOfst[0]=13 cells (4 PI)
7750 10:52:13.835672 u2DelayCellOfst[1]=16 cells (5 PI)
7751 10:52:13.838645 u2DelayCellOfst[2]=10 cells (3 PI)
7752 10:52:13.842284 u2DelayCellOfst[3]=13 cells (4 PI)
7753 10:52:13.845716 u2DelayCellOfst[4]=6 cells (2 PI)
7754 10:52:13.848648 u2DelayCellOfst[5]=0 cells (0 PI)
7755 10:52:13.851885 u2DelayCellOfst[6]=16 cells (5 PI)
7756 10:52:13.855411 u2DelayCellOfst[7]=13 cells (4 PI)
7757 10:52:13.858627 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7758 10:52:13.862261 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7759 10:52:13.865628 == TX Byte 1 ==
7760 10:52:13.868683 u2DelayCellOfst[8]=0 cells (0 PI)
7761 10:52:13.872446 u2DelayCellOfst[9]=0 cells (0 PI)
7762 10:52:13.872611 u2DelayCellOfst[10]=3 cells (1 PI)
7763 10:52:13.875385 u2DelayCellOfst[11]=0 cells (0 PI)
7764 10:52:13.878661 u2DelayCellOfst[12]=10 cells (3 PI)
7765 10:52:13.881642 u2DelayCellOfst[13]=10 cells (3 PI)
7766 10:52:13.884910 u2DelayCellOfst[14]=13 cells (4 PI)
7767 10:52:13.888113 u2DelayCellOfst[15]=6 cells (2 PI)
7768 10:52:13.895082 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7769 10:52:13.898165 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7770 10:52:13.898248 DramC Write-DBI on
7771 10:52:13.898315 ==
7772 10:52:13.901470 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 10:52:13.908100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 10:52:13.908185 ==
7775 10:52:13.908252
7776 10:52:13.908313
7777 10:52:13.911544 TX Vref Scan disable
7778 10:52:13.911628 == TX Byte 0 ==
7779 10:52:13.917823 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7780 10:52:13.917912 == TX Byte 1 ==
7781 10:52:13.921260 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7782 10:52:13.924521 DramC Write-DBI off
7783 10:52:13.924606
7784 10:52:13.924673 [DATLAT]
7785 10:52:13.927778 Freq=1600, CH0 RK0
7786 10:52:13.927868
7787 10:52:13.927935 DATLAT Default: 0xf
7788 10:52:13.931243 0, 0xFFFF, sum = 0
7789 10:52:13.931335 1, 0xFFFF, sum = 0
7790 10:52:13.934566 2, 0xFFFF, sum = 0
7791 10:52:13.934656 3, 0xFFFF, sum = 0
7792 10:52:13.937768 4, 0xFFFF, sum = 0
7793 10:52:13.937853 5, 0xFFFF, sum = 0
7794 10:52:13.941101 6, 0xFFFF, sum = 0
7795 10:52:13.941188 7, 0xFFFF, sum = 0
7796 10:52:13.944484 8, 0xFFFF, sum = 0
7797 10:52:13.947877 9, 0xFFFF, sum = 0
7798 10:52:13.947963 10, 0xFFFF, sum = 0
7799 10:52:13.950857 11, 0xFFFF, sum = 0
7800 10:52:13.950946 12, 0xFFFF, sum = 0
7801 10:52:13.954194 13, 0xFFFF, sum = 0
7802 10:52:13.954279 14, 0x0, sum = 1
7803 10:52:13.957345 15, 0x0, sum = 2
7804 10:52:13.957431 16, 0x0, sum = 3
7805 10:52:13.960721 17, 0x0, sum = 4
7806 10:52:13.960831 best_step = 15
7807 10:52:13.960898
7808 10:52:13.960959 ==
7809 10:52:13.964194 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 10:52:13.967893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 10:52:13.967978 ==
7812 10:52:13.970770 RX Vref Scan: 1
7813 10:52:13.970853
7814 10:52:13.973968 Set Vref Range= 24 -> 127
7815 10:52:13.974052
7816 10:52:13.974118 RX Vref 24 -> 127, step: 1
7817 10:52:13.977352
7818 10:52:13.977435 RX Delay 19 -> 252, step: 4
7819 10:52:13.977501
7820 10:52:13.981138 Set Vref, RX VrefLevel [Byte0]: 24
7821 10:52:13.983977 [Byte1]: 24
7822 10:52:13.987362
7823 10:52:13.987444 Set Vref, RX VrefLevel [Byte0]: 25
7824 10:52:13.990936 [Byte1]: 25
7825 10:52:13.994946
7826 10:52:13.995029 Set Vref, RX VrefLevel [Byte0]: 26
7827 10:52:13.998426 [Byte1]: 26
7828 10:52:14.002901
7829 10:52:14.002985 Set Vref, RX VrefLevel [Byte0]: 27
7830 10:52:14.005817 [Byte1]: 27
7831 10:52:14.010490
7832 10:52:14.010573 Set Vref, RX VrefLevel [Byte0]: 28
7833 10:52:14.013629 [Byte1]: 28
7834 10:52:14.017772
7835 10:52:14.017854 Set Vref, RX VrefLevel [Byte0]: 29
7836 10:52:14.021267 [Byte1]: 29
7837 10:52:14.025742
7838 10:52:14.025824 Set Vref, RX VrefLevel [Byte0]: 30
7839 10:52:14.028716 [Byte1]: 30
7840 10:52:14.032967
7841 10:52:14.033050 Set Vref, RX VrefLevel [Byte0]: 31
7842 10:52:14.036258 [Byte1]: 31
7843 10:52:14.040503
7844 10:52:14.040585 Set Vref, RX VrefLevel [Byte0]: 32
7845 10:52:14.043817 [Byte1]: 32
7846 10:52:14.048143
7847 10:52:14.048227 Set Vref, RX VrefLevel [Byte0]: 33
7848 10:52:14.051539 [Byte1]: 33
7849 10:52:14.055698
7850 10:52:14.055780 Set Vref, RX VrefLevel [Byte0]: 34
7851 10:52:14.058846 [Byte1]: 34
7852 10:52:14.063103
7853 10:52:14.063186 Set Vref, RX VrefLevel [Byte0]: 35
7854 10:52:14.066360 [Byte1]: 35
7855 10:52:14.071146
7856 10:52:14.071229 Set Vref, RX VrefLevel [Byte0]: 36
7857 10:52:14.073933 [Byte1]: 36
7858 10:52:14.078389
7859 10:52:14.078471 Set Vref, RX VrefLevel [Byte0]: 37
7860 10:52:14.081728 [Byte1]: 37
7861 10:52:14.086364
7862 10:52:14.086446 Set Vref, RX VrefLevel [Byte0]: 38
7863 10:52:14.089094 [Byte1]: 38
7864 10:52:14.093309
7865 10:52:14.093391 Set Vref, RX VrefLevel [Byte0]: 39
7866 10:52:14.096966 [Byte1]: 39
7867 10:52:14.101356
7868 10:52:14.101439 Set Vref, RX VrefLevel [Byte0]: 40
7869 10:52:14.104386 [Byte1]: 40
7870 10:52:14.108542
7871 10:52:14.108626 Set Vref, RX VrefLevel [Byte0]: 41
7872 10:52:14.112010 [Byte1]: 41
7873 10:52:14.116116
7874 10:52:14.116198 Set Vref, RX VrefLevel [Byte0]: 42
7875 10:52:14.119654 [Byte1]: 42
7876 10:52:14.123879
7877 10:52:14.123962 Set Vref, RX VrefLevel [Byte0]: 43
7878 10:52:14.127342 [Byte1]: 43
7879 10:52:14.131256
7880 10:52:14.131339 Set Vref, RX VrefLevel [Byte0]: 44
7881 10:52:14.134476 [Byte1]: 44
7882 10:52:14.138906
7883 10:52:14.138990 Set Vref, RX VrefLevel [Byte0]: 45
7884 10:52:14.142552 [Byte1]: 45
7885 10:52:14.146650
7886 10:52:14.146734 Set Vref, RX VrefLevel [Byte0]: 46
7887 10:52:14.150059 [Byte1]: 46
7888 10:52:14.154144
7889 10:52:14.154233 Set Vref, RX VrefLevel [Byte0]: 47
7890 10:52:14.157380 [Byte1]: 47
7891 10:52:14.161798
7892 10:52:14.161893 Set Vref, RX VrefLevel [Byte0]: 48
7893 10:52:14.165234 [Byte1]: 48
7894 10:52:14.169425
7895 10:52:14.169537 Set Vref, RX VrefLevel [Byte0]: 49
7896 10:52:14.172734 [Byte1]: 49
7897 10:52:14.176934
7898 10:52:14.177057 Set Vref, RX VrefLevel [Byte0]: 50
7899 10:52:14.180435 [Byte1]: 50
7900 10:52:14.184503
7901 10:52:14.184656 Set Vref, RX VrefLevel [Byte0]: 51
7902 10:52:14.187583 [Byte1]: 51
7903 10:52:14.191906
7904 10:52:14.192079 Set Vref, RX VrefLevel [Byte0]: 52
7905 10:52:14.195524 [Byte1]: 52
7906 10:52:14.199610
7907 10:52:14.199852 Set Vref, RX VrefLevel [Byte0]: 53
7908 10:52:14.202863 [Byte1]: 53
7909 10:52:14.207207
7910 10:52:14.207514 Set Vref, RX VrefLevel [Byte0]: 54
7911 10:52:14.211024 [Byte1]: 54
7912 10:52:14.214967
7913 10:52:14.215268 Set Vref, RX VrefLevel [Byte0]: 55
7914 10:52:14.218295 [Byte1]: 55
7915 10:52:14.222349
7916 10:52:14.222837 Set Vref, RX VrefLevel [Byte0]: 56
7917 10:52:14.225910 [Byte1]: 56
7918 10:52:14.230051
7919 10:52:14.230488 Set Vref, RX VrefLevel [Byte0]: 57
7920 10:52:14.233427 [Byte1]: 57
7921 10:52:14.237472
7922 10:52:14.237929 Set Vref, RX VrefLevel [Byte0]: 58
7923 10:52:14.240790 [Byte1]: 58
7924 10:52:14.245052
7925 10:52:14.245310 Set Vref, RX VrefLevel [Byte0]: 59
7926 10:52:14.248571 [Byte1]: 59
7927 10:52:14.252701
7928 10:52:14.252899 Set Vref, RX VrefLevel [Byte0]: 60
7929 10:52:14.255985 [Byte1]: 60
7930 10:52:14.260410
7931 10:52:14.260653 Set Vref, RX VrefLevel [Byte0]: 61
7932 10:52:14.263614 [Byte1]: 61
7933 10:52:14.267825
7934 10:52:14.268046 Set Vref, RX VrefLevel [Byte0]: 62
7935 10:52:14.271152 [Byte1]: 62
7936 10:52:14.275356
7937 10:52:14.275602 Set Vref, RX VrefLevel [Byte0]: 63
7938 10:52:14.278908 [Byte1]: 63
7939 10:52:14.282746
7940 10:52:14.282972 Set Vref, RX VrefLevel [Byte0]: 64
7941 10:52:14.286192 [Byte1]: 64
7942 10:52:14.290518
7943 10:52:14.290618 Set Vref, RX VrefLevel [Byte0]: 65
7944 10:52:14.293598 [Byte1]: 65
7945 10:52:14.297823
7946 10:52:14.297900 Set Vref, RX VrefLevel [Byte0]: 66
7947 10:52:14.301306 [Byte1]: 66
7948 10:52:14.305443
7949 10:52:14.305520 Set Vref, RX VrefLevel [Byte0]: 67
7950 10:52:14.309069 [Byte1]: 67
7951 10:52:14.313010
7952 10:52:14.313119 Set Vref, RX VrefLevel [Byte0]: 68
7953 10:52:14.316192 [Byte1]: 68
7954 10:52:14.321127
7955 10:52:14.321227 Set Vref, RX VrefLevel [Byte0]: 69
7956 10:52:14.324126 [Byte1]: 69
7957 10:52:14.328411
7958 10:52:14.328494 Set Vref, RX VrefLevel [Byte0]: 70
7959 10:52:14.331421 [Byte1]: 70
7960 10:52:14.335488
7961 10:52:14.338743 Set Vref, RX VrefLevel [Byte0]: 71
7962 10:52:14.342111 [Byte1]: 71
7963 10:52:14.342223
7964 10:52:14.345797 Set Vref, RX VrefLevel [Byte0]: 72
7965 10:52:14.348762 [Byte1]: 72
7966 10:52:14.348883
7967 10:52:14.352084 Set Vref, RX VrefLevel [Byte0]: 73
7968 10:52:14.355379 [Byte1]: 73
7969 10:52:14.355463
7970 10:52:14.358763 Set Vref, RX VrefLevel [Byte0]: 74
7971 10:52:14.361850 [Byte1]: 74
7972 10:52:14.366020
7973 10:52:14.366102 Set Vref, RX VrefLevel [Byte0]: 75
7974 10:52:14.369622 [Byte1]: 75
7975 10:52:14.373696
7976 10:52:14.373779 Set Vref, RX VrefLevel [Byte0]: 76
7977 10:52:14.376875 [Byte1]: 76
7978 10:52:14.381135
7979 10:52:14.381218 Set Vref, RX VrefLevel [Byte0]: 77
7980 10:52:14.384588 [Byte1]: 77
7981 10:52:14.389093
7982 10:52:14.389176 Set Vref, RX VrefLevel [Byte0]: 78
7983 10:52:14.392047 [Byte1]: 78
7984 10:52:14.396528
7985 10:52:14.396611 Set Vref, RX VrefLevel [Byte0]: 79
7986 10:52:14.399675 [Byte1]: 79
7987 10:52:14.403946
7988 10:52:14.404028 Set Vref, RX VrefLevel [Byte0]: 80
7989 10:52:14.407393 [Byte1]: 80
7990 10:52:14.411609
7991 10:52:14.411711 Final RX Vref Byte 0 = 64 to rank0
7992 10:52:14.414852 Final RX Vref Byte 1 = 60 to rank0
7993 10:52:14.418310 Final RX Vref Byte 0 = 64 to rank1
7994 10:52:14.421597 Final RX Vref Byte 1 = 60 to rank1==
7995 10:52:14.425043 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 10:52:14.431197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 10:52:14.431281 ==
7998 10:52:14.431363 DQS Delay:
7999 10:52:14.431442 DQS0 = 0, DQS1 = 0
8000 10:52:14.434812 DQM Delay:
8001 10:52:14.434889 DQM0 = 136, DQM1 = 123
8002 10:52:14.437755 DQ Delay:
8003 10:52:14.441237 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8004 10:52:14.444450 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =142
8005 10:52:14.447953 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8006 10:52:14.451335 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8007 10:52:14.451414
8008 10:52:14.451517
8009 10:52:14.451597
8010 10:52:14.454339 [DramC_TX_OE_Calibration] TA2
8011 10:52:14.457769 Original DQ_B0 (3 6) =30, OEN = 27
8012 10:52:14.461034 Original DQ_B1 (3 6) =30, OEN = 27
8013 10:52:14.464516 24, 0x0, End_B0=24 End_B1=24
8014 10:52:14.464603 25, 0x0, End_B0=25 End_B1=25
8015 10:52:14.467509 26, 0x0, End_B0=26 End_B1=26
8016 10:52:14.471023 27, 0x0, End_B0=27 End_B1=27
8017 10:52:14.474157 28, 0x0, End_B0=28 End_B1=28
8018 10:52:14.477756 29, 0x0, End_B0=29 End_B1=29
8019 10:52:14.477842 30, 0x0, End_B0=30 End_B1=30
8020 10:52:14.481028 31, 0x4141, End_B0=30 End_B1=30
8021 10:52:14.484030 Byte0 end_step=30 best_step=27
8022 10:52:14.487477 Byte1 end_step=30 best_step=27
8023 10:52:14.490925 Byte0 TX OE(2T, 0.5T) = (3, 3)
8024 10:52:14.494100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8025 10:52:14.494183
8026 10:52:14.494248
8027 10:52:14.500485 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8028 10:52:14.503751 CH0 RK0: MR19=303, MR18=1B1A
8029 10:52:14.510224 CH0_RK0: MR19=0x303, MR18=0x1B1A, DQSOSC=396, MR23=63, INC=23, DEC=15
8030 10:52:14.510308
8031 10:52:14.514100 ----->DramcWriteLeveling(PI) begin...
8032 10:52:14.514185 ==
8033 10:52:14.516905 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 10:52:14.520389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 10:52:14.520471 ==
8036 10:52:14.523397 Write leveling (Byte 0): 37 => 37
8037 10:52:14.526937 Write leveling (Byte 1): 31 => 31
8038 10:52:14.530126 DramcWriteLeveling(PI) end<-----
8039 10:52:14.530207
8040 10:52:14.530271 ==
8041 10:52:14.533346 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 10:52:14.539741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 10:52:14.539853 ==
8044 10:52:14.539962 [Gating] SW mode calibration
8045 10:52:14.549745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8046 10:52:14.553360 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8047 10:52:14.559940 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 10:52:14.562833 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 10:52:14.566181 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 10:52:14.573071 1 4 12 | B1->B0 | 2322 2929 | 1 1 | (0 0) (0 0)
8051 10:52:14.576197 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 10:52:14.579461 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 10:52:14.582821 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 10:52:14.589457 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 10:52:14.592761 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 10:52:14.595904 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 10:52:14.602624 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 10:52:14.606100 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8059 10:52:14.609223 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8060 10:52:14.615996 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 10:52:14.619334 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 10:52:14.622386 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 10:52:14.629111 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 10:52:14.632478 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 10:52:14.636001 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8066 10:52:14.642465 1 6 12 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
8067 10:52:14.645640 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 10:52:14.648994 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 10:52:14.655847 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 10:52:14.658971 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 10:52:14.662095 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 10:52:14.668640 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 10:52:14.671970 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 10:52:14.675202 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 10:52:14.681818 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8076 10:52:14.685060 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 10:52:14.688450 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 10:52:14.695358 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 10:52:14.698443 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 10:52:14.701460 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 10:52:14.708181 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 10:52:14.711512 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 10:52:14.715215 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 10:52:14.721236 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 10:52:14.724397 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 10:52:14.727780 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 10:52:14.734258 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 10:52:14.737630 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 10:52:14.741147 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8090 10:52:14.747577 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8091 10:52:14.750643 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8092 10:52:14.754316 Total UI for P1: 0, mck2ui 16
8093 10:52:14.757334 best dqsien dly found for B0: ( 1, 9, 10)
8094 10:52:14.761006 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 10:52:14.764157 Total UI for P1: 0, mck2ui 16
8096 10:52:14.767250 best dqsien dly found for B1: ( 1, 9, 14)
8097 10:52:14.770680 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8098 10:52:14.777342 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8099 10:52:14.777425
8100 10:52:14.780464 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8101 10:52:14.784036 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8102 10:52:14.787340 [Gating] SW calibration Done
8103 10:52:14.787423 ==
8104 10:52:14.790408 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 10:52:14.793998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 10:52:14.794093 ==
8107 10:52:14.797258 RX Vref Scan: 0
8108 10:52:14.797340
8109 10:52:14.797404 RX Vref 0 -> 0, step: 1
8110 10:52:14.797465
8111 10:52:14.800294 RX Delay 0 -> 252, step: 8
8112 10:52:14.803630 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8113 10:52:14.810278 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8114 10:52:14.813757 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8115 10:52:14.816854 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8116 10:52:14.820352 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8117 10:52:14.823883 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8118 10:52:14.830197 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8119 10:52:14.833367 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8120 10:52:14.837227 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8121 10:52:14.840077 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8122 10:52:14.843586 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8123 10:52:14.849907 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8124 10:52:14.853169 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8125 10:52:14.856630 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8126 10:52:14.859784 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8127 10:52:14.866528 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8128 10:52:14.866612 ==
8129 10:52:14.869490 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 10:52:14.873039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 10:52:14.873124 ==
8132 10:52:14.873190 DQS Delay:
8133 10:52:14.876209 DQS0 = 0, DQS1 = 0
8134 10:52:14.876292 DQM Delay:
8135 10:52:14.879335 DQM0 = 136, DQM1 = 125
8136 10:52:14.879418 DQ Delay:
8137 10:52:14.882806 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8138 10:52:14.886244 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8139 10:52:14.889357 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8140 10:52:14.892609 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8141 10:52:14.892691
8142 10:52:14.892757
8143 10:52:14.895994 ==
8144 10:52:14.899377 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 10:52:14.902361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 10:52:14.902444 ==
8147 10:52:14.902510
8148 10:52:14.902571
8149 10:52:14.905790 TX Vref Scan disable
8150 10:52:14.905874 == TX Byte 0 ==
8151 10:52:14.909390 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8152 10:52:14.915776 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8153 10:52:14.915860 == TX Byte 1 ==
8154 10:52:14.922240 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8155 10:52:14.925738 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8156 10:52:14.925821 ==
8157 10:52:14.929218 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 10:52:14.932164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 10:52:14.932247 ==
8160 10:52:14.947575
8161 10:52:14.950749 TX Vref early break, caculate TX vref
8162 10:52:14.953942 TX Vref=16, minBit 0, minWin=23, winSum=386
8163 10:52:14.957390 TX Vref=18, minBit 0, minWin=24, winSum=398
8164 10:52:14.960618 TX Vref=20, minBit 8, minWin=24, winSum=403
8165 10:52:14.963795 TX Vref=22, minBit 8, minWin=24, winSum=412
8166 10:52:14.970218 TX Vref=24, minBit 1, minWin=25, winSum=420
8167 10:52:14.973602 TX Vref=26, minBit 2, minWin=25, winSum=429
8168 10:52:14.976958 TX Vref=28, minBit 0, minWin=26, winSum=432
8169 10:52:14.980319 TX Vref=30, minBit 0, minWin=26, winSum=425
8170 10:52:14.983327 TX Vref=32, minBit 0, minWin=25, winSum=418
8171 10:52:14.986667 TX Vref=34, minBit 1, minWin=24, winSum=410
8172 10:52:14.993624 TX Vref=36, minBit 1, minWin=24, winSum=400
8173 10:52:14.996718 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8174 10:52:14.996821
8175 10:52:15.000011 Final TX Range 0 Vref 28
8176 10:52:15.000120
8177 10:52:15.000212 ==
8178 10:52:15.003272 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 10:52:15.006944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 10:52:15.009899 ==
8181 10:52:15.009982
8182 10:52:15.010047
8183 10:52:15.010108 TX Vref Scan disable
8184 10:52:15.016304 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8185 10:52:15.016388 == TX Byte 0 ==
8186 10:52:15.019861 u2DelayCellOfst[0]=13 cells (4 PI)
8187 10:52:15.023222 u2DelayCellOfst[1]=20 cells (6 PI)
8188 10:52:15.026390 u2DelayCellOfst[2]=13 cells (4 PI)
8189 10:52:15.029702 u2DelayCellOfst[3]=13 cells (4 PI)
8190 10:52:15.033212 u2DelayCellOfst[4]=10 cells (3 PI)
8191 10:52:15.036423 u2DelayCellOfst[5]=0 cells (0 PI)
8192 10:52:15.039515 u2DelayCellOfst[6]=20 cells (6 PI)
8193 10:52:15.043098 u2DelayCellOfst[7]=20 cells (6 PI)
8194 10:52:15.046201 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8195 10:52:15.049588 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8196 10:52:15.052710 == TX Byte 1 ==
8197 10:52:15.056110 u2DelayCellOfst[8]=0 cells (0 PI)
8198 10:52:15.059501 u2DelayCellOfst[9]=0 cells (0 PI)
8199 10:52:15.062578 u2DelayCellOfst[10]=3 cells (1 PI)
8200 10:52:15.066254 u2DelayCellOfst[11]=0 cells (0 PI)
8201 10:52:15.069053 u2DelayCellOfst[12]=13 cells (4 PI)
8202 10:52:15.072382 u2DelayCellOfst[13]=10 cells (3 PI)
8203 10:52:15.075638 u2DelayCellOfst[14]=13 cells (4 PI)
8204 10:52:15.078985 u2DelayCellOfst[15]=6 cells (2 PI)
8205 10:52:15.082264 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8206 10:52:15.085780 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8207 10:52:15.088921 DramC Write-DBI on
8208 10:52:15.089003 ==
8209 10:52:15.092027 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 10:52:15.095557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 10:52:15.095641 ==
8212 10:52:15.095707
8213 10:52:15.095768
8214 10:52:15.098582 TX Vref Scan disable
8215 10:52:15.102184 == TX Byte 0 ==
8216 10:52:15.105380 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8217 10:52:15.105464 == TX Byte 1 ==
8218 10:52:15.112090 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8219 10:52:15.112173 DramC Write-DBI off
8220 10:52:15.112240
8221 10:52:15.112302 [DATLAT]
8222 10:52:15.115162 Freq=1600, CH0 RK1
8223 10:52:15.115245
8224 10:52:15.118619 DATLAT Default: 0xf
8225 10:52:15.118702 0, 0xFFFF, sum = 0
8226 10:52:15.121894 1, 0xFFFF, sum = 0
8227 10:52:15.121979 2, 0xFFFF, sum = 0
8228 10:52:15.125341 3, 0xFFFF, sum = 0
8229 10:52:15.125426 4, 0xFFFF, sum = 0
8230 10:52:15.128485 5, 0xFFFF, sum = 0
8231 10:52:15.128569 6, 0xFFFF, sum = 0
8232 10:52:15.131825 7, 0xFFFF, sum = 0
8233 10:52:15.131910 8, 0xFFFF, sum = 0
8234 10:52:15.135332 9, 0xFFFF, sum = 0
8235 10:52:15.135416 10, 0xFFFF, sum = 0
8236 10:52:15.138409 11, 0xFFFF, sum = 0
8237 10:52:15.138492 12, 0xFFFF, sum = 0
8238 10:52:15.141543 13, 0xFFFF, sum = 0
8239 10:52:15.141627 14, 0x0, sum = 1
8240 10:52:15.144718 15, 0x0, sum = 2
8241 10:52:15.144838 16, 0x0, sum = 3
8242 10:52:15.148338 17, 0x0, sum = 4
8243 10:52:15.148424 best_step = 15
8244 10:52:15.148491
8245 10:52:15.148553 ==
8246 10:52:15.151286 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 10:52:15.158122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 10:52:15.158209 ==
8249 10:52:15.158276 RX Vref Scan: 0
8250 10:52:15.158340
8251 10:52:15.161740 RX Vref 0 -> 0, step: 1
8252 10:52:15.161824
8253 10:52:15.164751 RX Delay 11 -> 252, step: 4
8254 10:52:15.168017 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8255 10:52:15.171298 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8256 10:52:15.178045 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8257 10:52:15.181313 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8258 10:52:15.184528 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8259 10:52:15.187624 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8260 10:52:15.190875 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8261 10:52:15.197783 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8262 10:52:15.200787 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8263 10:52:15.204128 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8264 10:52:15.207644 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8265 10:52:15.210708 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8266 10:52:15.217638 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8267 10:52:15.220695 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8268 10:52:15.224059 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8269 10:52:15.227468 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8270 10:52:15.227553 ==
8271 10:52:15.230766 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 10:52:15.237240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 10:52:15.237325 ==
8274 10:52:15.237392 DQS Delay:
8275 10:52:15.240727 DQS0 = 0, DQS1 = 0
8276 10:52:15.240828 DQM Delay:
8277 10:52:15.243779 DQM0 = 133, DQM1 = 123
8278 10:52:15.243883 DQ Delay:
8279 10:52:15.247252 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8280 10:52:15.250300 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8281 10:52:15.253977 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8282 10:52:15.257340 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8283 10:52:15.257424
8284 10:52:15.257490
8285 10:52:15.257550
8286 10:52:15.260375 [DramC_TX_OE_Calibration] TA2
8287 10:52:15.263838 Original DQ_B0 (3 6) =30, OEN = 27
8288 10:52:15.266828 Original DQ_B1 (3 6) =30, OEN = 27
8289 10:52:15.270095 24, 0x0, End_B0=24 End_B1=24
8290 10:52:15.273670 25, 0x0, End_B0=25 End_B1=25
8291 10:52:15.273756 26, 0x0, End_B0=26 End_B1=26
8292 10:52:15.276722 27, 0x0, End_B0=27 End_B1=27
8293 10:52:15.280228 28, 0x0, End_B0=28 End_B1=28
8294 10:52:15.283504 29, 0x0, End_B0=29 End_B1=29
8295 10:52:15.283589 30, 0x0, End_B0=30 End_B1=30
8296 10:52:15.286853 31, 0x4141, End_B0=30 End_B1=30
8297 10:52:15.290093 Byte0 end_step=30 best_step=27
8298 10:52:15.293411 Byte1 end_step=30 best_step=27
8299 10:52:15.296462 Byte0 TX OE(2T, 0.5T) = (3, 3)
8300 10:52:15.299921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8301 10:52:15.299995
8302 10:52:15.300058
8303 10:52:15.306570 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8304 10:52:15.310065 CH0 RK1: MR19=303, MR18=210F
8305 10:52:15.316497 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8306 10:52:15.319517 [RxdqsGatingPostProcess] freq 1600
8307 10:52:15.326416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8308 10:52:15.326495 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 10:52:15.329671 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 10:52:15.332863 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 10:52:15.335922 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 10:52:15.339291 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 10:52:15.342642 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 10:52:15.346260 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 10:52:15.349643 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 10:52:15.352646 Pre-setting of DQS Precalculation
8317 10:52:15.355957 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8318 10:52:15.359534 ==
8319 10:52:15.359632 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 10:52:15.365871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 10:52:15.365945 ==
8322 10:52:15.369262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 10:52:15.375712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 10:52:15.379314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 10:52:15.385670 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 10:52:15.393816 [CA 0] Center 40 (11~70) winsize 60
8327 10:52:15.397214 [CA 1] Center 41 (11~71) winsize 61
8328 10:52:15.400363 [CA 2] Center 37 (8~67) winsize 60
8329 10:52:15.403798 [CA 3] Center 36 (6~66) winsize 61
8330 10:52:15.407209 [CA 4] Center 37 (7~67) winsize 61
8331 10:52:15.410400 [CA 5] Center 36 (6~66) winsize 61
8332 10:52:15.410504
8333 10:52:15.413625 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8334 10:52:15.413698
8335 10:52:15.416914 [CATrainingPosCal] consider 1 rank data
8336 10:52:15.420410 u2DelayCellTimex100 = 290/100 ps
8337 10:52:15.423770 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8338 10:52:15.430026 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8339 10:52:15.433763 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8340 10:52:15.436864 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8341 10:52:15.440342 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8342 10:52:15.443217 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8343 10:52:15.443327
8344 10:52:15.446588 CA PerBit enable=1, Macro0, CA PI delay=36
8345 10:52:15.446687
8346 10:52:15.450209 [CBTSetCACLKResult] CA Dly = 36
8347 10:52:15.453256 CS Dly: 9 (0~40)
8348 10:52:15.456836 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 10:52:15.460235 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 10:52:15.460306 ==
8351 10:52:15.463209 Dram Type= 6, Freq= 0, CH_1, rank 1
8352 10:52:15.466676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 10:52:15.469714 ==
8354 10:52:15.473167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8355 10:52:15.476575 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8356 10:52:15.482865 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8357 10:52:15.489403 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8358 10:52:15.496969 [CA 0] Center 41 (12~71) winsize 60
8359 10:52:15.500011 [CA 1] Center 41 (12~71) winsize 60
8360 10:52:15.503554 [CA 2] Center 38 (9~67) winsize 59
8361 10:52:15.506743 [CA 3] Center 37 (8~67) winsize 60
8362 10:52:15.509808 [CA 4] Center 38 (9~67) winsize 59
8363 10:52:15.513563 [CA 5] Center 37 (7~67) winsize 61
8364 10:52:15.513636
8365 10:52:15.516620 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8366 10:52:15.516719
8367 10:52:15.523410 [CATrainingPosCal] consider 2 rank data
8368 10:52:15.523485 u2DelayCellTimex100 = 290/100 ps
8369 10:52:15.529870 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8370 10:52:15.532927 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8371 10:52:15.536218 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8372 10:52:15.539502 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8373 10:52:15.542999 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8374 10:52:15.546220 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8375 10:52:15.546319
8376 10:52:15.549685 CA PerBit enable=1, Macro0, CA PI delay=36
8377 10:52:15.549784
8378 10:52:15.553138 [CBTSetCACLKResult] CA Dly = 36
8379 10:52:15.556272 CS Dly: 10 (0~42)
8380 10:52:15.559696 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8381 10:52:15.562544 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8382 10:52:15.562641
8383 10:52:15.565949 ----->DramcWriteLeveling(PI) begin...
8384 10:52:15.566025 ==
8385 10:52:15.569523 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 10:52:15.576260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 10:52:15.576343 ==
8388 10:52:15.579028 Write leveling (Byte 0): 24 => 24
8389 10:52:15.582580 Write leveling (Byte 1): 28 => 28
8390 10:52:15.582653 DramcWriteLeveling(PI) end<-----
8391 10:52:15.585812
8392 10:52:15.585884 ==
8393 10:52:15.589168 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 10:52:15.592491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 10:52:15.592563 ==
8396 10:52:15.595857 [Gating] SW mode calibration
8397 10:52:15.602353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8398 10:52:15.605651 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8399 10:52:15.612442 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 10:52:15.615597 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 10:52:15.618913 1 4 8 | B1->B0 | 2d2d 3131 | 1 0 | (0 0) (0 0)
8402 10:52:15.625464 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 10:52:15.629106 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 10:52:15.632349 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 10:52:15.638950 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 10:52:15.641814 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 10:52:15.645438 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 10:52:15.652112 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 10:52:15.655515 1 5 8 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 1)
8410 10:52:15.658529 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8411 10:52:15.665534 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 10:52:15.668476 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 10:52:15.671878 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 10:52:15.678786 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 10:52:15.681771 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 10:52:15.685317 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 10:52:15.691805 1 6 8 | B1->B0 | 3838 4242 | 0 1 | (0 0) (0 0)
8418 10:52:15.695017 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 10:52:15.698284 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 10:52:15.705225 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 10:52:15.708407 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 10:52:15.711891 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 10:52:15.718354 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 10:52:15.721488 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 10:52:15.724823 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8426 10:52:15.731800 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8427 10:52:15.734540 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 10:52:15.738030 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 10:52:15.744438 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 10:52:15.748069 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 10:52:15.751560 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 10:52:15.757815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 10:52:15.761087 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 10:52:15.764658 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 10:52:15.771049 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 10:52:15.774230 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 10:52:15.777563 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 10:52:15.784182 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 10:52:15.787512 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 10:52:15.791007 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 10:52:15.797633 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8442 10:52:15.800642 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8443 10:52:15.804170 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 10:52:15.807494 Total UI for P1: 0, mck2ui 16
8445 10:52:15.810574 best dqsien dly found for B0: ( 1, 9, 10)
8446 10:52:15.813800 Total UI for P1: 0, mck2ui 16
8447 10:52:15.817238 best dqsien dly found for B1: ( 1, 9, 10)
8448 10:52:15.820400 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8449 10:52:15.823747 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8450 10:52:15.823845
8451 10:52:15.830547 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8452 10:52:15.833927 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8453 10:52:15.837008 [Gating] SW calibration Done
8454 10:52:15.837084 ==
8455 10:52:15.840359 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 10:52:15.843776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 10:52:15.843911 ==
8458 10:52:15.844003 RX Vref Scan: 0
8459 10:52:15.844096
8460 10:52:15.847373 RX Vref 0 -> 0, step: 1
8461 10:52:15.847466
8462 10:52:15.850350 RX Delay 0 -> 252, step: 8
8463 10:52:15.853477 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8464 10:52:15.857130 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8465 10:52:15.860397 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8466 10:52:15.866738 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8467 10:52:15.870242 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8468 10:52:15.873426 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8469 10:52:15.876597 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8470 10:52:15.880027 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8471 10:52:15.886634 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8472 10:52:15.890006 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8473 10:52:15.893138 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8474 10:52:15.896525 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8475 10:52:15.899995 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8476 10:52:15.906478 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8477 10:52:15.909520 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8478 10:52:15.912936 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8479 10:52:15.913032 ==
8480 10:52:15.916379 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 10:52:15.919689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 10:52:15.923142 ==
8483 10:52:15.923216 DQS Delay:
8484 10:52:15.923288 DQS0 = 0, DQS1 = 0
8485 10:52:15.926721 DQM Delay:
8486 10:52:15.926796 DQM0 = 137, DQM1 = 131
8487 10:52:15.929625 DQ Delay:
8488 10:52:15.932747 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8489 10:52:15.935903 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8490 10:52:15.939428 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8491 10:52:15.942800 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8492 10:52:15.942891
8493 10:52:15.942981
8494 10:52:15.943072 ==
8495 10:52:15.946190 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 10:52:15.949244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 10:52:15.952782 ==
8498 10:52:15.952877
8499 10:52:15.952940
8500 10:52:15.952999 TX Vref Scan disable
8501 10:52:15.955826 == TX Byte 0 ==
8502 10:52:15.959164 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8503 10:52:15.962769 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8504 10:52:15.965758 == TX Byte 1 ==
8505 10:52:15.969229 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8506 10:52:15.972306 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8507 10:52:15.975792 ==
8508 10:52:15.975872 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 10:52:15.982140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 10:52:15.982214 ==
8511 10:52:15.994415
8512 10:52:15.997722 TX Vref early break, caculate TX vref
8513 10:52:16.000675 TX Vref=16, minBit 10, minWin=21, winSum=369
8514 10:52:16.003901 TX Vref=18, minBit 10, minWin=21, winSum=376
8515 10:52:16.007429 TX Vref=20, minBit 10, minWin=23, winSum=391
8516 10:52:16.010841 TX Vref=22, minBit 10, minWin=22, winSum=394
8517 10:52:16.017535 TX Vref=24, minBit 10, minWin=23, winSum=404
8518 10:52:16.020395 TX Vref=26, minBit 10, minWin=24, winSum=418
8519 10:52:16.023672 TX Vref=28, minBit 12, minWin=25, winSum=419
8520 10:52:16.027334 TX Vref=30, minBit 14, minWin=24, winSum=416
8521 10:52:16.030657 TX Vref=32, minBit 14, minWin=24, winSum=408
8522 10:52:16.037170 TX Vref=34, minBit 9, minWin=23, winSum=396
8523 10:52:16.040589 [TxChooseVref] Worse bit 12, Min win 25, Win sum 419, Final Vref 28
8524 10:52:16.040688
8525 10:52:16.043704 Final TX Range 0 Vref 28
8526 10:52:16.043809
8527 10:52:16.043900 ==
8528 10:52:16.047077 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 10:52:16.050255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 10:52:16.053717 ==
8531 10:52:16.053819
8532 10:52:16.053910
8533 10:52:16.054002 TX Vref Scan disable
8534 10:52:16.060403 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8535 10:52:16.060512 == TX Byte 0 ==
8536 10:52:16.063679 u2DelayCellOfst[0]=16 cells (5 PI)
8537 10:52:16.066726 u2DelayCellOfst[1]=10 cells (3 PI)
8538 10:52:16.070214 u2DelayCellOfst[2]=0 cells (0 PI)
8539 10:52:16.073541 u2DelayCellOfst[3]=3 cells (1 PI)
8540 10:52:16.076905 u2DelayCellOfst[4]=6 cells (2 PI)
8541 10:52:16.080065 u2DelayCellOfst[5]=16 cells (5 PI)
8542 10:52:16.083257 u2DelayCellOfst[6]=16 cells (5 PI)
8543 10:52:16.086587 u2DelayCellOfst[7]=6 cells (2 PI)
8544 10:52:16.090209 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8545 10:52:16.093286 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8546 10:52:16.096708 == TX Byte 1 ==
8547 10:52:16.099915 u2DelayCellOfst[8]=0 cells (0 PI)
8548 10:52:16.103237 u2DelayCellOfst[9]=3 cells (1 PI)
8549 10:52:16.106668 u2DelayCellOfst[10]=13 cells (4 PI)
8550 10:52:16.109947 u2DelayCellOfst[11]=3 cells (1 PI)
8551 10:52:16.113362 u2DelayCellOfst[12]=16 cells (5 PI)
8552 10:52:16.113433 u2DelayCellOfst[13]=16 cells (5 PI)
8553 10:52:16.116363 u2DelayCellOfst[14]=20 cells (6 PI)
8554 10:52:16.119942 u2DelayCellOfst[15]=16 cells (5 PI)
8555 10:52:16.126675 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8556 10:52:16.129618 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8557 10:52:16.133273 DramC Write-DBI on
8558 10:52:16.133345 ==
8559 10:52:16.136217 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 10:52:16.139569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 10:52:16.139669 ==
8562 10:52:16.139735
8563 10:52:16.139802
8564 10:52:16.142733 TX Vref Scan disable
8565 10:52:16.142801 == TX Byte 0 ==
8566 10:52:16.149676 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8567 10:52:16.149786 == TX Byte 1 ==
8568 10:52:16.152741 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8569 10:52:16.156061 DramC Write-DBI off
8570 10:52:16.156160
8571 10:52:16.156254 [DATLAT]
8572 10:52:16.159436 Freq=1600, CH1 RK0
8573 10:52:16.159536
8574 10:52:16.159640 DATLAT Default: 0xf
8575 10:52:16.162763 0, 0xFFFF, sum = 0
8576 10:52:16.162859 1, 0xFFFF, sum = 0
8577 10:52:16.165936 2, 0xFFFF, sum = 0
8578 10:52:16.166036 3, 0xFFFF, sum = 0
8579 10:52:16.169373 4, 0xFFFF, sum = 0
8580 10:52:16.172451 5, 0xFFFF, sum = 0
8581 10:52:16.172549 6, 0xFFFF, sum = 0
8582 10:52:16.175979 7, 0xFFFF, sum = 0
8583 10:52:16.176083 8, 0xFFFF, sum = 0
8584 10:52:16.179108 9, 0xFFFF, sum = 0
8585 10:52:16.179205 10, 0xFFFF, sum = 0
8586 10:52:16.182481 11, 0xFFFF, sum = 0
8587 10:52:16.182580 12, 0xFFFF, sum = 0
8588 10:52:16.185934 13, 0xFFFF, sum = 0
8589 10:52:16.186033 14, 0x0, sum = 1
8590 10:52:16.189016 15, 0x0, sum = 2
8591 10:52:16.189092 16, 0x0, sum = 3
8592 10:52:16.192348 17, 0x0, sum = 4
8593 10:52:16.192443 best_step = 15
8594 10:52:16.192534
8595 10:52:16.192620 ==
8596 10:52:16.195964 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 10:52:16.199013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 10:52:16.202587 ==
8599 10:52:16.202659 RX Vref Scan: 1
8600 10:52:16.202726
8601 10:52:16.205743 Set Vref Range= 24 -> 127
8602 10:52:16.205812
8603 10:52:16.208962 RX Vref 24 -> 127, step: 1
8604 10:52:16.209034
8605 10:52:16.209095 RX Delay 19 -> 252, step: 4
8606 10:52:16.209152
8607 10:52:16.212140 Set Vref, RX VrefLevel [Byte0]: 24
8608 10:52:16.215800 [Byte1]: 24
8609 10:52:16.219245
8610 10:52:16.222635 Set Vref, RX VrefLevel [Byte0]: 25
8611 10:52:16.222734 [Byte1]: 25
8612 10:52:16.227039
8613 10:52:16.227114 Set Vref, RX VrefLevel [Byte0]: 26
8614 10:52:16.230376 [Byte1]: 26
8615 10:52:16.234720
8616 10:52:16.234823 Set Vref, RX VrefLevel [Byte0]: 27
8617 10:52:16.237994 [Byte1]: 27
8618 10:52:16.242301
8619 10:52:16.242375 Set Vref, RX VrefLevel [Byte0]: 28
8620 10:52:16.245776 [Byte1]: 28
8621 10:52:16.249984
8622 10:52:16.250090 Set Vref, RX VrefLevel [Byte0]: 29
8623 10:52:16.253058 [Byte1]: 29
8624 10:52:16.257254
8625 10:52:16.257343 Set Vref, RX VrefLevel [Byte0]: 30
8626 10:52:16.260651 [Byte1]: 30
8627 10:52:16.264785
8628 10:52:16.264867 Set Vref, RX VrefLevel [Byte0]: 31
8629 10:52:16.268525 [Byte1]: 31
8630 10:52:16.272239
8631 10:52:16.272321 Set Vref, RX VrefLevel [Byte0]: 32
8632 10:52:16.275891 [Byte1]: 32
8633 10:52:16.280133
8634 10:52:16.280215 Set Vref, RX VrefLevel [Byte0]: 33
8635 10:52:16.283303 [Byte1]: 33
8636 10:52:16.287715
8637 10:52:16.287796 Set Vref, RX VrefLevel [Byte0]: 34
8638 10:52:16.290854 [Byte1]: 34
8639 10:52:16.295285
8640 10:52:16.295368 Set Vref, RX VrefLevel [Byte0]: 35
8641 10:52:16.298681 [Byte1]: 35
8642 10:52:16.302778
8643 10:52:16.302860 Set Vref, RX VrefLevel [Byte0]: 36
8644 10:52:16.305940 [Byte1]: 36
8645 10:52:16.310072
8646 10:52:16.310154 Set Vref, RX VrefLevel [Byte0]: 37
8647 10:52:16.313547 [Byte1]: 37
8648 10:52:16.317818
8649 10:52:16.317900 Set Vref, RX VrefLevel [Byte0]: 38
8650 10:52:16.321129 [Byte1]: 38
8651 10:52:16.325588
8652 10:52:16.325671 Set Vref, RX VrefLevel [Byte0]: 39
8653 10:52:16.328860 [Byte1]: 39
8654 10:52:16.333243
8655 10:52:16.333326 Set Vref, RX VrefLevel [Byte0]: 40
8656 10:52:16.336491 [Byte1]: 40
8657 10:52:16.340694
8658 10:52:16.340834 Set Vref, RX VrefLevel [Byte0]: 41
8659 10:52:16.343993 [Byte1]: 41
8660 10:52:16.348090
8661 10:52:16.348173 Set Vref, RX VrefLevel [Byte0]: 42
8662 10:52:16.351630 [Byte1]: 42
8663 10:52:16.356050
8664 10:52:16.356134 Set Vref, RX VrefLevel [Byte0]: 43
8665 10:52:16.359128 [Byte1]: 43
8666 10:52:16.363320
8667 10:52:16.363403 Set Vref, RX VrefLevel [Byte0]: 44
8668 10:52:16.366393 [Byte1]: 44
8669 10:52:16.371156
8670 10:52:16.371239 Set Vref, RX VrefLevel [Byte0]: 45
8671 10:52:16.374119 [Byte1]: 45
8672 10:52:16.378427
8673 10:52:16.378511 Set Vref, RX VrefLevel [Byte0]: 46
8674 10:52:16.381711 [Byte1]: 46
8675 10:52:16.386232
8676 10:52:16.386316 Set Vref, RX VrefLevel [Byte0]: 47
8677 10:52:16.389490 [Byte1]: 47
8678 10:52:16.393771
8679 10:52:16.393855 Set Vref, RX VrefLevel [Byte0]: 48
8680 10:52:16.396734 [Byte1]: 48
8681 10:52:16.401083
8682 10:52:16.401167 Set Vref, RX VrefLevel [Byte0]: 49
8683 10:52:16.404643 [Byte1]: 49
8684 10:52:16.408759
8685 10:52:16.408882 Set Vref, RX VrefLevel [Byte0]: 50
8686 10:52:16.412331 [Byte1]: 50
8687 10:52:16.416537
8688 10:52:16.416620 Set Vref, RX VrefLevel [Byte0]: 51
8689 10:52:16.419426 [Byte1]: 51
8690 10:52:16.424040
8691 10:52:16.424124 Set Vref, RX VrefLevel [Byte0]: 52
8692 10:52:16.427569 [Byte1]: 52
8693 10:52:16.431462
8694 10:52:16.431545 Set Vref, RX VrefLevel [Byte0]: 53
8695 10:52:16.434948 [Byte1]: 53
8696 10:52:16.439026
8697 10:52:16.439110 Set Vref, RX VrefLevel [Byte0]: 54
8698 10:52:16.442439 [Byte1]: 54
8699 10:52:16.446611
8700 10:52:16.446694 Set Vref, RX VrefLevel [Byte0]: 55
8701 10:52:16.450224 [Byte1]: 55
8702 10:52:16.454126
8703 10:52:16.454209 Set Vref, RX VrefLevel [Byte0]: 56
8704 10:52:16.457891 [Byte1]: 56
8705 10:52:16.461620
8706 10:52:16.461703 Set Vref, RX VrefLevel [Byte0]: 57
8707 10:52:16.465241 [Byte1]: 57
8708 10:52:16.469242
8709 10:52:16.469326 Set Vref, RX VrefLevel [Byte0]: 58
8710 10:52:16.472557 [Byte1]: 58
8711 10:52:16.476738
8712 10:52:16.476829 Set Vref, RX VrefLevel [Byte0]: 59
8713 10:52:16.480371 [Byte1]: 59
8714 10:52:16.484545
8715 10:52:16.484628 Set Vref, RX VrefLevel [Byte0]: 60
8716 10:52:16.487894 [Byte1]: 60
8717 10:52:16.491892
8718 10:52:16.491976 Set Vref, RX VrefLevel [Byte0]: 61
8719 10:52:16.495545 [Byte1]: 61
8720 10:52:16.499799
8721 10:52:16.499882 Set Vref, RX VrefLevel [Byte0]: 62
8722 10:52:16.503093 [Byte1]: 62
8723 10:52:16.507106
8724 10:52:16.507190 Set Vref, RX VrefLevel [Byte0]: 63
8725 10:52:16.510447 [Byte1]: 63
8726 10:52:16.514852
8727 10:52:16.514936 Set Vref, RX VrefLevel [Byte0]: 64
8728 10:52:16.518133 [Byte1]: 64
8729 10:52:16.522639
8730 10:52:16.522723 Set Vref, RX VrefLevel [Byte0]: 65
8731 10:52:16.525739 [Byte1]: 65
8732 10:52:16.529766
8733 10:52:16.529888 Set Vref, RX VrefLevel [Byte0]: 66
8734 10:52:16.533241 [Byte1]: 66
8735 10:52:16.537696
8736 10:52:16.537779 Set Vref, RX VrefLevel [Byte0]: 67
8737 10:52:16.540620 [Byte1]: 67
8738 10:52:16.544886
8739 10:52:16.544990 Set Vref, RX VrefLevel [Byte0]: 68
8740 10:52:16.548197 [Byte1]: 68
8741 10:52:16.552557
8742 10:52:16.552642 Set Vref, RX VrefLevel [Byte0]: 69
8743 10:52:16.555844 [Byte1]: 69
8744 10:52:16.560608
8745 10:52:16.560697 Set Vref, RX VrefLevel [Byte0]: 70
8746 10:52:16.563427 [Byte1]: 70
8747 10:52:16.567873
8748 10:52:16.567956 Set Vref, RX VrefLevel [Byte0]: 71
8749 10:52:16.571197 [Byte1]: 71
8750 10:52:16.575510
8751 10:52:16.575593 Set Vref, RX VrefLevel [Byte0]: 72
8752 10:52:16.578547 [Byte1]: 72
8753 10:52:16.583236
8754 10:52:16.583319 Set Vref, RX VrefLevel [Byte0]: 73
8755 10:52:16.586271 [Byte1]: 73
8756 10:52:16.590557
8757 10:52:16.590640 Set Vref, RX VrefLevel [Byte0]: 74
8758 10:52:16.593870 [Byte1]: 74
8759 10:52:16.598114
8760 10:52:16.598197 Final RX Vref Byte 0 = 57 to rank0
8761 10:52:16.601469 Final RX Vref Byte 1 = 62 to rank0
8762 10:52:16.604746 Final RX Vref Byte 0 = 57 to rank1
8763 10:52:16.608274 Final RX Vref Byte 1 = 62 to rank1==
8764 10:52:16.611035 Dram Type= 6, Freq= 0, CH_1, rank 0
8765 10:52:16.617709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 10:52:16.617793 ==
8767 10:52:16.617859 DQS Delay:
8768 10:52:16.621153 DQS0 = 0, DQS1 = 0
8769 10:52:16.621237 DQM Delay:
8770 10:52:16.621304 DQM0 = 133, DQM1 = 129
8771 10:52:16.624595 DQ Delay:
8772 10:52:16.627842 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8773 10:52:16.630923 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8774 10:52:16.634174 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8775 10:52:16.637568 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8776 10:52:16.637652
8777 10:52:16.637718
8778 10:52:16.637777
8779 10:52:16.641067 [DramC_TX_OE_Calibration] TA2
8780 10:52:16.644198 Original DQ_B0 (3 6) =30, OEN = 27
8781 10:52:16.647612 Original DQ_B1 (3 6) =30, OEN = 27
8782 10:52:16.651020 24, 0x0, End_B0=24 End_B1=24
8783 10:52:16.654152 25, 0x0, End_B0=25 End_B1=25
8784 10:52:16.654237 26, 0x0, End_B0=26 End_B1=26
8785 10:52:16.657654 27, 0x0, End_B0=27 End_B1=27
8786 10:52:16.660719 28, 0x0, End_B0=28 End_B1=28
8787 10:52:16.663995 29, 0x0, End_B0=29 End_B1=29
8788 10:52:16.664080 30, 0x0, End_B0=30 End_B1=30
8789 10:52:16.667571 31, 0x4141, End_B0=30 End_B1=30
8790 10:52:16.670695 Byte0 end_step=30 best_step=27
8791 10:52:16.673921 Byte1 end_step=30 best_step=27
8792 10:52:16.677106 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 10:52:16.680470 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 10:52:16.680554
8795 10:52:16.680619
8796 10:52:16.686958 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8797 10:52:16.690321 CH1 RK0: MR19=303, MR18=1725
8798 10:52:16.696902 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8799 10:52:16.696993
8800 10:52:16.700072 ----->DramcWriteLeveling(PI) begin...
8801 10:52:16.700145 ==
8802 10:52:16.703342 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 10:52:16.706786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 10:52:16.706861 ==
8805 10:52:16.710042 Write leveling (Byte 0): 24 => 24
8806 10:52:16.713305 Write leveling (Byte 1): 28 => 28
8807 10:52:16.716752 DramcWriteLeveling(PI) end<-----
8808 10:52:16.716856
8809 10:52:16.716920 ==
8810 10:52:16.720135 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 10:52:16.726515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 10:52:16.726592 ==
8813 10:52:16.726666 [Gating] SW mode calibration
8814 10:52:16.736327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8815 10:52:16.739748 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8816 10:52:16.743141 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 10:52:16.749415 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 10:52:16.752757 1 4 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
8819 10:52:16.756157 1 4 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8820 10:52:16.762841 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 10:52:16.766031 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 10:52:16.769336 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 10:52:16.776220 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 10:52:16.779390 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 10:52:16.782937 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 10:52:16.789132 1 5 8 | B1->B0 | 2929 3434 | 0 1 | (0 1) (1 0)
8827 10:52:16.792537 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 1)
8828 10:52:16.795908 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 10:52:16.802519 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 10:52:16.805726 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 10:52:16.809195 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 10:52:16.815856 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 10:52:16.819115 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 10:52:16.822093 1 6 8 | B1->B0 | 4242 2323 | 0 0 | (1 1) (0 0)
8835 10:52:16.828631 1 6 12 | B1->B0 | 4646 3535 | 0 1 | (0 0) (0 0)
8836 10:52:16.832094 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 10:52:16.835239 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 10:52:16.842137 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 10:52:16.845238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 10:52:16.848429 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 10:52:16.855137 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 10:52:16.858148 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8843 10:52:16.861619 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8844 10:52:16.868014 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 10:52:16.871508 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 10:52:16.874931 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 10:52:16.881417 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 10:52:16.885169 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 10:52:16.887919 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 10:52:16.894716 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 10:52:16.898295 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 10:52:16.901936 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 10:52:16.907692 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 10:52:16.911393 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 10:52:16.914431 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 10:52:16.920998 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 10:52:16.924376 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 10:52:16.927819 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 10:52:16.934160 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8860 10:52:16.937717 Total UI for P1: 0, mck2ui 16
8861 10:52:16.940762 best dqsien dly found for B1: ( 1, 9, 8)
8862 10:52:16.944114 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 10:52:16.947714 Total UI for P1: 0, mck2ui 16
8864 10:52:16.951006 best dqsien dly found for B0: ( 1, 9, 10)
8865 10:52:16.954237 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8866 10:52:16.957647 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8867 10:52:16.957730
8868 10:52:16.960891 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8869 10:52:16.963963 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8870 10:52:16.967467 [Gating] SW calibration Done
8871 10:52:16.967551 ==
8872 10:52:16.970683 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 10:52:16.977202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 10:52:16.977287 ==
8875 10:52:16.977354 RX Vref Scan: 0
8876 10:52:16.977435
8877 10:52:16.980753 RX Vref 0 -> 0, step: 1
8878 10:52:16.980872
8879 10:52:16.983945 RX Delay 0 -> 252, step: 8
8880 10:52:16.987618 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8881 10:52:16.990760 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8882 10:52:16.994177 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8883 10:52:16.997057 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8884 10:52:17.003788 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8885 10:52:17.007604 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8886 10:52:17.010489 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8887 10:52:17.014096 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8888 10:52:17.016902 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8889 10:52:17.023816 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8890 10:52:17.026874 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8891 10:52:17.030170 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8892 10:52:17.033364 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8893 10:52:17.040186 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8894 10:52:17.043427 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8895 10:52:17.046574 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8896 10:52:17.046695 ==
8897 10:52:17.049993 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 10:52:17.053288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 10:52:17.053372 ==
8900 10:52:17.056529 DQS Delay:
8901 10:52:17.056638 DQS0 = 0, DQS1 = 0
8902 10:52:17.059987 DQM Delay:
8903 10:52:17.060071 DQM0 = 136, DQM1 = 131
8904 10:52:17.060138 DQ Delay:
8905 10:52:17.066481 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8906 10:52:17.069988 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8907 10:52:17.073444 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8908 10:52:17.076516 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8909 10:52:17.076601
8910 10:52:17.076667
8911 10:52:17.076729 ==
8912 10:52:17.080080 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 10:52:17.083267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 10:52:17.083351 ==
8915 10:52:17.083417
8916 10:52:17.083477
8917 10:52:17.086380 TX Vref Scan disable
8918 10:52:17.089867 == TX Byte 0 ==
8919 10:52:17.093055 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8920 10:52:17.096453 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8921 10:52:17.099996 == TX Byte 1 ==
8922 10:52:17.102890 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8923 10:52:17.106135 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8924 10:52:17.106218 ==
8925 10:52:17.109510 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 10:52:17.116224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 10:52:17.116308 ==
8928 10:52:17.127280
8929 10:52:17.130713 TX Vref early break, caculate TX vref
8930 10:52:17.134209 TX Vref=16, minBit 9, minWin=22, winSum=384
8931 10:52:17.137218 TX Vref=18, minBit 13, minWin=22, winSum=391
8932 10:52:17.140820 TX Vref=20, minBit 9, minWin=23, winSum=399
8933 10:52:17.143854 TX Vref=22, minBit 9, minWin=24, winSum=405
8934 10:52:17.147338 TX Vref=24, minBit 10, minWin=24, winSum=413
8935 10:52:17.153798 TX Vref=26, minBit 10, minWin=25, winSum=420
8936 10:52:17.157260 TX Vref=28, minBit 9, minWin=25, winSum=423
8937 10:52:17.160457 TX Vref=30, minBit 9, minWin=24, winSum=417
8938 10:52:17.164082 TX Vref=32, minBit 10, minWin=24, winSum=407
8939 10:52:17.167028 TX Vref=34, minBit 10, minWin=23, winSum=399
8940 10:52:17.173857 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8941 10:52:17.173942
8942 10:52:17.176921 Final TX Range 0 Vref 28
8943 10:52:17.177005
8944 10:52:17.177070 ==
8945 10:52:17.180343 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 10:52:17.183406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 10:52:17.183491 ==
8948 10:52:17.183558
8949 10:52:17.186835
8950 10:52:17.186919 TX Vref Scan disable
8951 10:52:17.193617 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8952 10:52:17.193701 == TX Byte 0 ==
8953 10:52:17.197082 u2DelayCellOfst[0]=13 cells (4 PI)
8954 10:52:17.200587 u2DelayCellOfst[1]=10 cells (3 PI)
8955 10:52:17.203511 u2DelayCellOfst[2]=0 cells (0 PI)
8956 10:52:17.206750 u2DelayCellOfst[3]=6 cells (2 PI)
8957 10:52:17.210019 u2DelayCellOfst[4]=6 cells (2 PI)
8958 10:52:17.213778 u2DelayCellOfst[5]=16 cells (5 PI)
8959 10:52:17.216680 u2DelayCellOfst[6]=16 cells (5 PI)
8960 10:52:17.219850 u2DelayCellOfst[7]=3 cells (1 PI)
8961 10:52:17.223689 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8962 10:52:17.226877 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8963 10:52:17.230049 == TX Byte 1 ==
8964 10:52:17.233534 u2DelayCellOfst[8]=0 cells (0 PI)
8965 10:52:17.236904 u2DelayCellOfst[9]=6 cells (2 PI)
8966 10:52:17.236987 u2DelayCellOfst[10]=10 cells (3 PI)
8967 10:52:17.240060 u2DelayCellOfst[11]=3 cells (1 PI)
8968 10:52:17.243546 u2DelayCellOfst[12]=13 cells (4 PI)
8969 10:52:17.246468 u2DelayCellOfst[13]=20 cells (6 PI)
8970 10:52:17.249848 u2DelayCellOfst[14]=20 cells (6 PI)
8971 10:52:17.252968 u2DelayCellOfst[15]=20 cells (6 PI)
8972 10:52:17.259641 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8973 10:52:17.262998 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8974 10:52:17.263083 DramC Write-DBI on
8975 10:52:17.263149 ==
8976 10:52:17.266136 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 10:52:17.273012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 10:52:17.273114 ==
8979 10:52:17.273201
8980 10:52:17.273266
8981 10:52:17.273326 TX Vref Scan disable
8982 10:52:17.277214 == TX Byte 0 ==
8983 10:52:17.280259 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8984 10:52:17.283609 == TX Byte 1 ==
8985 10:52:17.287439 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8986 10:52:17.290240 DramC Write-DBI off
8987 10:52:17.290324
8988 10:52:17.290390 [DATLAT]
8989 10:52:17.290450 Freq=1600, CH1 RK1
8990 10:52:17.290509
8991 10:52:17.293578 DATLAT Default: 0xf
8992 10:52:17.296986 0, 0xFFFF, sum = 0
8993 10:52:17.297072 1, 0xFFFF, sum = 0
8994 10:52:17.300216 2, 0xFFFF, sum = 0
8995 10:52:17.300301 3, 0xFFFF, sum = 0
8996 10:52:17.303778 4, 0xFFFF, sum = 0
8997 10:52:17.303864 5, 0xFFFF, sum = 0
8998 10:52:17.307065 6, 0xFFFF, sum = 0
8999 10:52:17.307150 7, 0xFFFF, sum = 0
9000 10:52:17.310128 8, 0xFFFF, sum = 0
9001 10:52:17.310214 9, 0xFFFF, sum = 0
9002 10:52:17.313509 10, 0xFFFF, sum = 0
9003 10:52:17.313594 11, 0xFFFF, sum = 0
9004 10:52:17.316498 12, 0xFFFF, sum = 0
9005 10:52:17.316582 13, 0xFFFF, sum = 0
9006 10:52:17.319768 14, 0x0, sum = 1
9007 10:52:17.319854 15, 0x0, sum = 2
9008 10:52:17.323185 16, 0x0, sum = 3
9009 10:52:17.323271 17, 0x0, sum = 4
9010 10:52:17.326690 best_step = 15
9011 10:52:17.326773
9012 10:52:17.326839 ==
9013 10:52:17.329915 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 10:52:17.333270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 10:52:17.333354 ==
9016 10:52:17.336593 RX Vref Scan: 0
9017 10:52:17.336676
9018 10:52:17.336742 RX Vref 0 -> 0, step: 1
9019 10:52:17.336848
9020 10:52:17.339612 RX Delay 19 -> 252, step: 4
9021 10:52:17.346320 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9022 10:52:17.349242 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9023 10:52:17.352740 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9024 10:52:17.355973 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9025 10:52:17.359402 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9026 10:52:17.365793 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9027 10:52:17.369347 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9028 10:52:17.372440 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9029 10:52:17.375744 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9030 10:52:17.379516 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9031 10:52:17.385776 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9032 10:52:17.389001 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9033 10:52:17.392287 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9034 10:52:17.395863 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9035 10:52:17.398992 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9036 10:52:17.405473 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9037 10:52:17.405557 ==
9038 10:52:17.409041 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 10:52:17.412336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 10:52:17.412421 ==
9041 10:52:17.412487 DQS Delay:
9042 10:52:17.416046 DQS0 = 0, DQS1 = 0
9043 10:52:17.416130 DQM Delay:
9044 10:52:17.418860 DQM0 = 133, DQM1 = 129
9045 10:52:17.418944 DQ Delay:
9046 10:52:17.422348 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9047 10:52:17.425725 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9048 10:52:17.429004 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9049 10:52:17.432328 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9050 10:52:17.432412
9051 10:52:17.432478
9052 10:52:17.435457
9053 10:52:17.435541 [DramC_TX_OE_Calibration] TA2
9054 10:52:17.439042 Original DQ_B0 (3 6) =30, OEN = 27
9055 10:52:17.441897 Original DQ_B1 (3 6) =30, OEN = 27
9056 10:52:17.445475 24, 0x0, End_B0=24 End_B1=24
9057 10:52:17.448868 25, 0x0, End_B0=25 End_B1=25
9058 10:52:17.452037 26, 0x0, End_B0=26 End_B1=26
9059 10:52:17.452122 27, 0x0, End_B0=27 End_B1=27
9060 10:52:17.455165 28, 0x0, End_B0=28 End_B1=28
9061 10:52:17.458519 29, 0x0, End_B0=29 End_B1=29
9062 10:52:17.461723 30, 0x0, End_B0=30 End_B1=30
9063 10:52:17.465014 31, 0x4141, End_B0=30 End_B1=30
9064 10:52:17.465099 Byte0 end_step=30 best_step=27
9065 10:52:17.468398 Byte1 end_step=30 best_step=27
9066 10:52:17.471998 Byte0 TX OE(2T, 0.5T) = (3, 3)
9067 10:52:17.475314 Byte1 TX OE(2T, 0.5T) = (3, 3)
9068 10:52:17.475397
9069 10:52:17.475462
9070 10:52:17.485061 [DQSOSCAuto] RK1, (LSB)MR18= 0x1904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
9071 10:52:17.485145 CH1 RK1: MR19=303, MR18=1904
9072 10:52:17.491574 CH1_RK1: MR19=0x303, MR18=0x1904, DQSOSC=397, MR23=63, INC=23, DEC=15
9073 10:52:17.494991 [RxdqsGatingPostProcess] freq 1600
9074 10:52:17.501670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9075 10:52:17.504957 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 10:52:17.508032 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 10:52:17.511480 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 10:52:17.511563 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 10:52:17.514982 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 10:52:17.518359 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 10:52:17.521288 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 10:52:17.524618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 10:52:17.527716 Pre-setting of DQS Precalculation
9084 10:52:17.534554 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9085 10:52:17.541452 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9086 10:52:17.547584 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 10:52:17.547669
9088 10:52:17.547734
9089 10:52:17.550991 [Calibration Summary] 3200 Mbps
9090 10:52:17.551075 CH 0, Rank 0
9091 10:52:17.554032 SW Impedance : PASS
9092 10:52:17.557547 DUTY Scan : NO K
9093 10:52:17.557630 ZQ Calibration : PASS
9094 10:52:17.560499 Jitter Meter : NO K
9095 10:52:17.564051 CBT Training : PASS
9096 10:52:17.564134 Write leveling : PASS
9097 10:52:17.567082 RX DQS gating : PASS
9098 10:52:17.570336 RX DQ/DQS(RDDQC) : PASS
9099 10:52:17.570419 TX DQ/DQS : PASS
9100 10:52:17.573614 RX DATLAT : PASS
9101 10:52:17.577129 RX DQ/DQS(Engine): PASS
9102 10:52:17.577212 TX OE : PASS
9103 10:52:17.580197 All Pass.
9104 10:52:17.580280
9105 10:52:17.580345 CH 0, Rank 1
9106 10:52:17.583627 SW Impedance : PASS
9107 10:52:17.583710 DUTY Scan : NO K
9108 10:52:17.587073 ZQ Calibration : PASS
9109 10:52:17.590508 Jitter Meter : NO K
9110 10:52:17.590591 CBT Training : PASS
9111 10:52:17.593916 Write leveling : PASS
9112 10:52:17.596927 RX DQS gating : PASS
9113 10:52:17.597010 RX DQ/DQS(RDDQC) : PASS
9114 10:52:17.600036 TX DQ/DQS : PASS
9115 10:52:17.603791 RX DATLAT : PASS
9116 10:52:17.603875 RX DQ/DQS(Engine): PASS
9117 10:52:17.607211 TX OE : PASS
9118 10:52:17.607294 All Pass.
9119 10:52:17.607359
9120 10:52:17.610253 CH 1, Rank 0
9121 10:52:17.610335 SW Impedance : PASS
9122 10:52:17.613648 DUTY Scan : NO K
9123 10:52:17.613731 ZQ Calibration : PASS
9124 10:52:17.616853 Jitter Meter : NO K
9125 10:52:17.620267 CBT Training : PASS
9126 10:52:17.620350 Write leveling : PASS
9127 10:52:17.623256 RX DQS gating : PASS
9128 10:52:17.626683 RX DQ/DQS(RDDQC) : PASS
9129 10:52:17.626766 TX DQ/DQS : PASS
9130 10:52:17.630173 RX DATLAT : PASS
9131 10:52:17.633082 RX DQ/DQS(Engine): PASS
9132 10:52:17.633166 TX OE : PASS
9133 10:52:17.636860 All Pass.
9134 10:52:17.636942
9135 10:52:17.637007 CH 1, Rank 1
9136 10:52:17.640258 SW Impedance : PASS
9137 10:52:17.640366 DUTY Scan : NO K
9138 10:52:17.642978 ZQ Calibration : PASS
9139 10:52:17.646602 Jitter Meter : NO K
9140 10:52:17.646718 CBT Training : PASS
9141 10:52:17.649671 Write leveling : PASS
9142 10:52:17.653248 RX DQS gating : PASS
9143 10:52:17.653332 RX DQ/DQS(RDDQC) : PASS
9144 10:52:17.656461 TX DQ/DQS : PASS
9145 10:52:17.659846 RX DATLAT : PASS
9146 10:52:17.659921 RX DQ/DQS(Engine): PASS
9147 10:52:17.663218 TX OE : PASS
9148 10:52:17.663323 All Pass.
9149 10:52:17.663421
9150 10:52:17.666226 DramC Write-DBI on
9151 10:52:17.669601 PER_BANK_REFRESH: Hybrid Mode
9152 10:52:17.669699 TX_TRACKING: ON
9153 10:52:17.679735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9154 10:52:17.685896 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9155 10:52:17.692444 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9156 10:52:17.695909 [FAST_K] Save calibration result to emmc
9157 10:52:17.699344 sync common calibartion params.
9158 10:52:17.702535 sync cbt_mode0:1, 1:1
9159 10:52:17.705919 dram_init: ddr_geometry: 2
9160 10:52:17.706001 dram_init: ddr_geometry: 2
9161 10:52:17.709086 dram_init: ddr_geometry: 2
9162 10:52:17.712459 0:dram_rank_size:100000000
9163 10:52:17.715508 1:dram_rank_size:100000000
9164 10:52:17.719246 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9165 10:52:17.722400 DFS_SHUFFLE_HW_MODE: ON
9166 10:52:17.725501 dramc_set_vcore_voltage set vcore to 725000
9167 10:52:17.729167 Read voltage for 1600, 0
9168 10:52:17.729241 Vio18 = 0
9169 10:52:17.729323 Vcore = 725000
9170 10:52:17.732177 Vdram = 0
9171 10:52:17.732276 Vddq = 0
9172 10:52:17.732375 Vmddr = 0
9173 10:52:17.735926 switch to 3200 Mbps bootup
9174 10:52:17.738817 [DramcRunTimeConfig]
9175 10:52:17.738913 PHYPLL
9176 10:52:17.738976 DPM_CONTROL_AFTERK: ON
9177 10:52:17.742066 PER_BANK_REFRESH: ON
9178 10:52:17.745431 REFRESH_OVERHEAD_REDUCTION: ON
9179 10:52:17.745531 CMD_PICG_NEW_MODE: OFF
9180 10:52:17.748780 XRTWTW_NEW_MODE: ON
9181 10:52:17.752108 XRTRTR_NEW_MODE: ON
9182 10:52:17.752217 TX_TRACKING: ON
9183 10:52:17.755313 RDSEL_TRACKING: OFF
9184 10:52:17.755396 DQS Precalculation for DVFS: ON
9185 10:52:17.758630 RX_TRACKING: OFF
9186 10:52:17.758738 HW_GATING DBG: ON
9187 10:52:17.761901 ZQCS_ENABLE_LP4: ON
9188 10:52:17.765070 RX_PICG_NEW_MODE: ON
9189 10:52:17.765152 TX_PICG_NEW_MODE: ON
9190 10:52:17.768423 ENABLE_RX_DCM_DPHY: ON
9191 10:52:17.771812 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9192 10:52:17.771895 DUMMY_READ_FOR_TRACKING: OFF
9193 10:52:17.775312 !!! SPM_CONTROL_AFTERK: OFF
9194 10:52:17.778372 !!! SPM could not control APHY
9195 10:52:17.781706 IMPEDANCE_TRACKING: ON
9196 10:52:17.781807 TEMP_SENSOR: ON
9197 10:52:17.784665 HW_SAVE_FOR_SR: OFF
9198 10:52:17.788255 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9199 10:52:17.791592 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9200 10:52:17.791675 Read ODT Tracking: ON
9201 10:52:17.794823 Refresh Rate DeBounce: ON
9202 10:52:17.797895 DFS_NO_QUEUE_FLUSH: ON
9203 10:52:17.801228 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9204 10:52:17.801311 ENABLE_DFS_RUNTIME_MRW: OFF
9205 10:52:17.804426 DDR_RESERVE_NEW_MODE: ON
9206 10:52:17.807685 MR_CBT_SWITCH_FREQ: ON
9207 10:52:17.807767 =========================
9208 10:52:17.828189 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9209 10:52:17.831298 dram_init: ddr_geometry: 2
9210 10:52:17.849802 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9211 10:52:17.853015 dram_init: dram init end (result: 0)
9212 10:52:17.859919 DRAM-K: Full calibration passed in 24479 msecs
9213 10:52:17.862914 MRC: failed to locate region type 0.
9214 10:52:17.862996 DRAM rank0 size:0x100000000,
9215 10:52:17.866188 DRAM rank1 size=0x100000000
9216 10:52:17.876003 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9217 10:52:17.882731 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9218 10:52:17.889290 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9219 10:52:17.895690 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9220 10:52:17.899341 DRAM rank0 size:0x100000000,
9221 10:52:17.902647 DRAM rank1 size=0x100000000
9222 10:52:17.902729 CBMEM:
9223 10:52:17.905813 IMD: root @ 0xfffff000 254 entries.
9224 10:52:17.908892 IMD: root @ 0xffffec00 62 entries.
9225 10:52:17.912692 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9226 10:52:17.918823 WARNING: RO_VPD is uninitialized or empty.
9227 10:52:17.922428 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9228 10:52:17.929845 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9229 10:52:17.942189 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9230 10:52:17.954296 BS: romstage times (exec / console): total (unknown) / 23984 ms
9231 10:52:17.954385
9232 10:52:17.954451
9233 10:52:17.963920 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9234 10:52:17.967190 ARM64: Exception handlers installed.
9235 10:52:17.970165 ARM64: Testing exception
9236 10:52:17.973750 ARM64: Done test exception
9237 10:52:17.973832 Enumerating buses...
9238 10:52:17.976899 Show all devs... Before device enumeration.
9239 10:52:17.980304 Root Device: enabled 1
9240 10:52:17.983644 CPU_CLUSTER: 0: enabled 1
9241 10:52:17.983727 CPU: 00: enabled 1
9242 10:52:17.987008 Compare with tree...
9243 10:52:17.987090 Root Device: enabled 1
9244 10:52:17.990050 CPU_CLUSTER: 0: enabled 1
9245 10:52:17.993508 CPU: 00: enabled 1
9246 10:52:17.993591 Root Device scanning...
9247 10:52:17.996901 scan_static_bus for Root Device
9248 10:52:17.999950 CPU_CLUSTER: 0 enabled
9249 10:52:18.003521 scan_static_bus for Root Device done
9250 10:52:18.006693 scan_bus: bus Root Device finished in 8 msecs
9251 10:52:18.006776 done
9252 10:52:18.013166 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9253 10:52:18.016655 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9254 10:52:18.023127 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9255 10:52:18.026633 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9256 10:52:18.029675 Allocating resources...
9257 10:52:18.033227 Reading resources...
9258 10:52:18.036169 Root Device read_resources bus 0 link: 0
9259 10:52:18.039500 DRAM rank0 size:0x100000000,
9260 10:52:18.039584 DRAM rank1 size=0x100000000
9261 10:52:18.043082 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9262 10:52:18.046119 CPU: 00 missing read_resources
9263 10:52:18.053027 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9264 10:52:18.056035 Root Device read_resources bus 0 link: 0 done
9265 10:52:18.059789 Done reading resources.
9266 10:52:18.062548 Show resources in subtree (Root Device)...After reading.
9267 10:52:18.065889 Root Device child on link 0 CPU_CLUSTER: 0
9268 10:52:18.069410 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 10:52:18.079341 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 10:52:18.079425 CPU: 00
9271 10:52:18.082404 Root Device assign_resources, bus 0 link: 0
9272 10:52:18.085771 CPU_CLUSTER: 0 missing set_resources
9273 10:52:18.092497 Root Device assign_resources, bus 0 link: 0 done
9274 10:52:18.092579 Done setting resources.
9275 10:52:18.099169 Show resources in subtree (Root Device)...After assigning values.
9276 10:52:18.102173 Root Device child on link 0 CPU_CLUSTER: 0
9277 10:52:18.105450 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 10:52:18.115448 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 10:52:18.115532 CPU: 00
9280 10:52:18.118889 Done allocating resources.
9281 10:52:18.125266 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9282 10:52:18.125388 Enabling resources...
9283 10:52:18.125491 done.
9284 10:52:18.132011 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9285 10:52:18.135543 Initializing devices...
9286 10:52:18.135626 Root Device init
9287 10:52:18.138641 init hardware done!
9288 10:52:18.138724 0x00000018: ctrlr->caps
9289 10:52:18.142116 52.000 MHz: ctrlr->f_max
9290 10:52:18.145463 0.400 MHz: ctrlr->f_min
9291 10:52:18.145549 0x40ff8080: ctrlr->voltages
9292 10:52:18.148483 sclk: 390625
9293 10:52:18.148567 Bus Width = 1
9294 10:52:18.148633 sclk: 390625
9295 10:52:18.151901 Bus Width = 1
9296 10:52:18.155393 Early init status = 3
9297 10:52:18.158769 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9298 10:52:18.162089 in-header: 03 fc 00 00 01 00 00 00
9299 10:52:18.165072 in-data: 00
9300 10:52:18.168317 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9301 10:52:18.172718 in-header: 03 fd 00 00 00 00 00 00
9302 10:52:18.176199 in-data:
9303 10:52:18.179201 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9304 10:52:18.183328 in-header: 03 fc 00 00 01 00 00 00
9305 10:52:18.186773 in-data: 00
9306 10:52:18.190149 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9307 10:52:18.195836 in-header: 03 fd 00 00 00 00 00 00
9308 10:52:18.198809 in-data:
9309 10:52:18.202337 [SSUSB] Setting up USB HOST controller...
9310 10:52:18.205352 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 10:52:18.208903 [SSUSB] phy power-on done.
9312 10:52:18.212171 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 10:52:18.218596 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 10:52:18.222257 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 10:52:18.228708 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 10:52:18.235229 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9317 10:52:18.241601 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 10:52:18.248463 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 10:52:18.254969 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9320 10:52:18.258136 SPM: binary array size = 0x9dc
9321 10:52:18.261508 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 10:52:18.268390 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 10:52:18.274466 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 10:52:18.281215 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 10:52:18.284741 configure_display: Starting display init
9326 10:52:18.318834 anx7625_power_on_init: Init interface.
9327 10:52:18.322232 anx7625_disable_pd_protocol: Disabled PD feature.
9328 10:52:18.325526 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 10:52:18.353263 anx7625_start_dp_work: Secure OCM version=00
9330 10:52:18.356552 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 10:52:18.371248 sp_tx_get_edid_block: EDID Block = 1
9332 10:52:18.473964 Extracted contents:
9333 10:52:18.477203 header: 00 ff ff ff ff ff ff 00
9334 10:52:18.480729 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 10:52:18.483889 version: 01 04
9336 10:52:18.487016 basic params: 95 1f 11 78 0a
9337 10:52:18.490455 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 10:52:18.493834 established: 00 00 00
9339 10:52:18.500434 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 10:52:18.503664 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 10:52:18.510362 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 10:52:18.516884 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 10:52:18.523671 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 10:52:18.526737 extensions: 00
9345 10:52:18.526840 checksum: fb
9346 10:52:18.526943
9347 10:52:18.530144 Manufacturer: IVO Model 57d Serial Number 0
9348 10:52:18.533678 Made week 0 of 2020
9349 10:52:18.533762 EDID version: 1.4
9350 10:52:18.536655 Digital display
9351 10:52:18.540121 6 bits per primary color channel
9352 10:52:18.540227 DisplayPort interface
9353 10:52:18.543267 Maximum image size: 31 cm x 17 cm
9354 10:52:18.546682 Gamma: 220%
9355 10:52:18.546765 Check DPMS levels
9356 10:52:18.549802 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 10:52:18.556437 First detailed timing is preferred timing
9358 10:52:18.556551 Established timings supported:
9359 10:52:18.559642 Standard timings supported:
9360 10:52:18.563219 Detailed timings
9361 10:52:18.566376 Hex of detail: 383680a07038204018303c0035ae10000019
9362 10:52:18.573348 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 10:52:18.576408 0780 0798 07c8 0820 hborder 0
9364 10:52:18.579573 0438 043b 0447 0458 vborder 0
9365 10:52:18.583075 -hsync -vsync
9366 10:52:18.583180 Did detailed timing
9367 10:52:18.589595 Hex of detail: 000000000000000000000000000000000000
9368 10:52:18.592887 Manufacturer-specified data, tag 0
9369 10:52:18.596331 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 10:52:18.599789 ASCII string: InfoVision
9371 10:52:18.602661 Hex of detail: 000000fe00523134304e574635205248200a
9372 10:52:18.606440 ASCII string: R140NWF5 RH
9373 10:52:18.606539 Checksum
9374 10:52:18.609416 Checksum: 0xfb (valid)
9375 10:52:18.612568 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 10:52:18.615955 DSI data_rate: 832800000 bps
9377 10:52:18.622341 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 10:52:18.625826 anx7625_parse_edid: pixelclock(138800).
9379 10:52:18.629101 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 10:52:18.632718 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 10:52:18.635730 anx7625_dsi_config: config dsi.
9382 10:52:18.642274 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 10:52:18.655987 anx7625_dsi_config: success to config DSI
9384 10:52:18.659274 anx7625_dp_start: MIPI phy setup OK.
9385 10:52:18.662420 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 10:52:18.665853 mtk_ddp_mode_set invalid vrefresh 60
9387 10:52:18.669048 main_disp_path_setup
9388 10:52:18.669128 ovl_layer_smi_id_en
9389 10:52:18.672369 ovl_layer_smi_id_en
9390 10:52:18.672478 ccorr_config
9391 10:52:18.672570 aal_config
9392 10:52:18.675996 gamma_config
9393 10:52:18.676068 postmask_config
9394 10:52:18.678802 dither_config
9395 10:52:18.682237 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 10:52:18.689010 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 10:52:18.692296 Root Device init finished in 553 msecs
9398 10:52:18.695434 CPU_CLUSTER: 0 init
9399 10:52:18.701967 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 10:52:18.708873 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 10:52:18.708952 APU_MBOX 0x190000b0 = 0x10001
9402 10:52:18.711992 APU_MBOX 0x190001b0 = 0x10001
9403 10:52:18.715608 APU_MBOX 0x190005b0 = 0x10001
9404 10:52:18.718736 APU_MBOX 0x190006b0 = 0x10001
9405 10:52:18.725022 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 10:52:18.734776 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9407 10:52:18.747257 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 10:52:18.753775 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 10:52:18.765931 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9410 10:52:18.774480 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 10:52:18.778109 CPU_CLUSTER: 0 init finished in 81 msecs
9412 10:52:18.781211 Devices initialized
9413 10:52:18.784741 Show all devs... After init.
9414 10:52:18.784877 Root Device: enabled 1
9415 10:52:18.787843 CPU_CLUSTER: 0: enabled 1
9416 10:52:18.790957 CPU: 00: enabled 1
9417 10:52:18.794322 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9418 10:52:18.797711 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 10:52:18.800919 ELOG: NV offset 0x57f000 size 0x1000
9420 10:52:18.808045 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9421 10:52:18.814223 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 10:52:18.817581 ELOG: Event(17) added with size 13 at 2023-06-05 10:52:16 UTC
9423 10:52:18.824508 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 10:52:18.827556 in-header: 03 41 00 00 2c 00 00 00
9425 10:52:18.837551 in-data: 1e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 10:52:18.843878 ELOG: Event(A1) added with size 10 at 2023-06-05 10:52:16 UTC
9427 10:52:18.850801 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 10:52:18.857428 ELOG: Event(A0) added with size 9 at 2023-06-05 10:52:16 UTC
9429 10:52:18.860445 elog_add_boot_reason: Logged dev mode boot
9430 10:52:18.867082 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9431 10:52:18.867189 Finalize devices...
9432 10:52:18.870265 Devices finalized
9433 10:52:18.873838 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 10:52:18.876939 Writing coreboot table at 0xffe64000
9435 10:52:18.880311 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 10:52:18.886808 1. 0000000040000000-00000000400fffff: RAM
9437 10:52:18.890402 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 10:52:18.893991 3. 000000004032b000-00000000545fffff: RAM
9439 10:52:18.896860 4. 0000000054600000-000000005465ffff: BL31
9440 10:52:18.900460 5. 0000000054660000-00000000ffe63fff: RAM
9441 10:52:18.906964 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 10:52:18.910249 7. 0000000100000000-000000023fffffff: RAM
9443 10:52:18.913533 Passing 5 GPIOs to payload:
9444 10:52:18.916538 NAME | PORT | POLARITY | VALUE
9445 10:52:18.923036 EC in RW | 0x000000aa | low | undefined
9446 10:52:18.926303 EC interrupt | 0x00000005 | low | undefined
9447 10:52:18.929657 TPM interrupt | 0x000000ab | high | undefined
9448 10:52:18.936521 SD card detect | 0x00000011 | high | undefined
9449 10:52:18.939622 speaker enable | 0x00000093 | high | undefined
9450 10:52:18.943153 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 10:52:18.946247 in-header: 03 f9 00 00 02 00 00 00
9452 10:52:18.949619 in-data: 02 00
9453 10:52:18.952630 ADC[4]: Raw value=900663 ID=7
9454 10:52:18.956038 ADC[3]: Raw value=213179 ID=1
9455 10:52:18.956122 RAM Code: 0x71
9456 10:52:18.959524 ADC[6]: Raw value=74502 ID=0
9457 10:52:18.963060 ADC[5]: Raw value=212441 ID=1
9458 10:52:18.963143 SKU Code: 0x1
9459 10:52:18.969337 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9460 10:52:18.969428 coreboot table: 964 bytes.
9461 10:52:18.972725 IMD ROOT 0. 0xfffff000 0x00001000
9462 10:52:18.976407 IMD SMALL 1. 0xffffe000 0x00001000
9463 10:52:18.979487 RO MCACHE 2. 0xffffc000 0x00001104
9464 10:52:18.982513 CONSOLE 3. 0xfff7c000 0x00080000
9465 10:52:18.986050 FMAP 4. 0xfff7b000 0x00000452
9466 10:52:18.989498 TIME STAMP 5. 0xfff7a000 0x00000910
9467 10:52:18.992601 VBOOT WORK 6. 0xfff66000 0x00014000
9468 10:52:18.995851 RAMOOPS 7. 0xffe66000 0x00100000
9469 10:52:18.999170 COREBOOT 8. 0xffe64000 0x00002000
9470 10:52:19.002869 IMD small region:
9471 10:52:19.005889 IMD ROOT 0. 0xffffec00 0x00000400
9472 10:52:19.009417 VPD 1. 0xffffeba0 0x0000004c
9473 10:52:19.012448 MMC STATUS 2. 0xffffeb80 0x00000004
9474 10:52:19.016036 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 10:52:19.019203 Probing TPM: done!
9476 10:52:19.022897 Connected to device vid:did:rid of 1ae0:0028:00
9477 10:52:19.033663 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9478 10:52:19.037093 Initialized TPM device CR50 revision 0
9479 10:52:19.040230 Checking cr50 for pending updates
9480 10:52:19.044558 Reading cr50 TPM mode
9481 10:52:19.053319 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 10:52:19.059841 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 10:52:19.099946 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9484 10:52:19.102875 Checking segment from ROM address 0x40100000
9485 10:52:19.106165 Checking segment from ROM address 0x4010001c
9486 10:52:19.112997 Loading segment from ROM address 0x40100000
9487 10:52:19.113080 code (compression=0)
9488 10:52:19.123095 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 10:52:19.129388 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 10:52:19.129472 it's not compressed!
9491 10:52:19.136003 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 10:52:19.142736 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 10:52:19.160538 Loading segment from ROM address 0x4010001c
9494 10:52:19.160626 Entry Point 0x80000000
9495 10:52:19.163621 Loaded segments
9496 10:52:19.166725 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 10:52:19.173639 Jumping to boot code at 0x80000000(0xffe64000)
9498 10:52:19.180120 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 10:52:19.186877 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 10:52:19.194833 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9501 10:52:19.197790 Checking segment from ROM address 0x40100000
9502 10:52:19.201087 Checking segment from ROM address 0x4010001c
9503 10:52:19.207812 Loading segment from ROM address 0x40100000
9504 10:52:19.207895 code (compression=1)
9505 10:52:19.214321 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 10:52:19.224414 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 10:52:19.224498 using LZMA
9508 10:52:19.232811 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 10:52:19.239369 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 10:52:19.242589 Loading segment from ROM address 0x4010001c
9511 10:52:19.242672 Entry Point 0x54601000
9512 10:52:19.246161 Loaded segments
9513 10:52:19.249238 NOTICE: MT8192 bl31_setup
9514 10:52:19.256325 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 10:52:19.259935 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 10:52:19.263135 WARNING: region 0:
9517 10:52:19.266815 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 10:52:19.266898 WARNING: region 1:
9519 10:52:19.273226 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 10:52:19.276769 WARNING: region 2:
9521 10:52:19.279974 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 10:52:19.282953 WARNING: region 3:
9523 10:52:19.286455 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 10:52:19.289408 WARNING: region 4:
9525 10:52:19.296295 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 10:52:19.296391 WARNING: region 5:
9527 10:52:19.299816 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 10:52:19.302786 WARNING: region 6:
9529 10:52:19.306214 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 10:52:19.309907 WARNING: region 7:
9531 10:52:19.312660 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 10:52:19.319549 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 10:52:19.322820 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 10:52:19.329160 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 10:52:19.332944 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 10:52:19.335990 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 10:52:19.342492 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 10:52:19.345950 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 10:52:19.349316 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 10:52:19.355947 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 10:52:19.359257 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 10:52:19.362494 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 10:52:19.369304 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 10:52:19.372421 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 10:52:19.379324 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 10:52:19.382571 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 10:52:19.386024 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 10:52:19.392520 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 10:52:19.395629 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 10:52:19.399049 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 10:52:19.405641 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 10:52:19.408960 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 10:52:19.415562 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 10:52:19.418870 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 10:52:19.422330 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 10:52:19.429188 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 10:52:19.432214 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 10:52:19.439097 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 10:52:19.442347 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 10:52:19.445370 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 10:52:19.452136 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 10:52:19.455511 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 10:52:19.462127 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 10:52:19.465427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 10:52:19.468645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 10:52:19.472200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 10:52:19.478726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 10:52:19.481930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 10:52:19.485377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 10:52:19.488704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 10:52:19.495603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 10:52:19.498693 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 10:52:19.501837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 10:52:19.505382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 10:52:19.512069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 10:52:19.515373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 10:52:19.518556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 10:52:19.521916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 10:52:19.528457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 10:52:19.531920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 10:52:19.538258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 10:52:19.541900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 10:52:19.544775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 10:52:19.551631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 10:52:19.555081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 10:52:19.562000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 10:52:19.565245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 10:52:19.571531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 10:52:19.575185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 10:52:19.578584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 10:52:19.584968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 10:52:19.588480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 10:52:19.594936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 10:52:19.598404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 10:52:19.604683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 10:52:19.608029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 10:52:19.614762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 10:52:19.618287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 10:52:19.621381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 10:52:19.628228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 10:52:19.631394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 10:52:19.638074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 10:52:19.641289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 10:52:19.648019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 10:52:19.651237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 10:52:19.654664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 10:52:19.661017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 10:52:19.664362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 10:52:19.670991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 10:52:19.674360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 10:52:19.680840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 10:52:19.684300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 10:52:19.690913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 10:52:19.694091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 10:52:19.700725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 10:52:19.703931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 10:52:19.707455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 10:52:19.713901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 10:52:19.717330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 10:52:19.723885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 10:52:19.727194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 10:52:19.733937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 10:52:19.737371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 10:52:19.740710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 10:52:19.747549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 10:52:19.750562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 10:52:19.757303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 10:52:19.760695 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 10:52:19.763784 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 10:52:19.770382 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 10:52:19.773909 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 10:52:19.777214 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 10:52:19.780423 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 10:52:19.787029 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 10:52:19.790376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 10:52:19.797169 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 10:52:19.800433 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 10:52:19.803779 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 10:52:19.810621 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 10:52:19.813724 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 10:52:19.820467 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 10:52:19.823981 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 10:52:19.826891 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 10:52:19.833806 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 10:52:19.837001 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 10:52:19.843523 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 10:52:19.847035 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 10:52:19.850788 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 10:52:19.856707 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 10:52:19.860380 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 10:52:19.863599 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 10:52:19.867036 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 10:52:19.873416 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 10:52:19.876703 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 10:52:19.880144 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 10:52:19.886628 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 10:52:19.889980 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 10:52:19.893671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 10:52:19.900067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 10:52:19.903483 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 10:52:19.910387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 10:52:19.913530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 10:52:19.916777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 10:52:19.923192 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 10:52:19.926701 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 10:52:19.933108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 10:52:19.936655 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 10:52:19.939789 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 10:52:19.946368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 10:52:19.949755 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 10:52:19.952890 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 10:52:19.959470 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 10:52:19.962928 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 10:52:19.969566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 10:52:19.973498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 10:52:19.976340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 10:52:19.982810 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 10:52:19.986368 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 10:52:19.992649 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 10:52:19.995990 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 10:52:19.999234 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 10:52:20.006272 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 10:52:20.009182 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 10:52:20.016241 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 10:52:20.019231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 10:52:20.022655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 10:52:20.029197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 10:52:20.032666 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 10:52:20.039231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 10:52:20.042557 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 10:52:20.045658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 10:52:20.052142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 10:52:20.055883 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 10:52:20.062099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 10:52:20.065523 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 10:52:20.068780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 10:52:20.075321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 10:52:20.078581 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 10:52:20.085134 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 10:52:20.088671 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 10:52:20.091840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 10:52:20.098480 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 10:52:20.101687 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 10:52:20.108639 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 10:52:20.111934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 10:52:20.115106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 10:52:20.121391 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 10:52:20.125002 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 10:52:20.131419 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 10:52:20.134553 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 10:52:20.137821 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 10:52:22.384546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 10:52:22.385582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 10:52:22.385971 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 10:52:22.386305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 10:52:22.386624 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 10:52:22.386945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 10:52:22.387050 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 10:52:22.387124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 10:52:22.387195 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 10:52:22.387257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 10:52:22.387348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 10:52:22.387422 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 10:52:22.387479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 10:52:22.387535 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 10:52:22.387592 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 10:52:22.387661 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 10:52:22.387748 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 10:52:22.387803 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 10:52:22.387873 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 10:52:22.387929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 10:52:22.387985 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 10:52:22.388041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 10:52:22.388124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 10:52:22.388210 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 10:52:22.388309 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 10:52:22.388413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 10:52:22.388469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 10:52:22.388585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 10:52:22.388671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 10:52:22.388727 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 10:52:22.388789 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 10:52:22.388892 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 10:52:22.388946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 10:52:22.389000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 10:52:22.389077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 10:52:22.389147 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 10:52:22.389201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 10:52:22.389288 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 10:52:22.389342 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 10:52:22.389397 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 10:52:22.389483 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 10:52:22.389538 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 10:52:22.389609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 10:52:22.389680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 10:52:22.389734 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 10:52:22.389788 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 10:52:22.389874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 10:52:22.389928 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 10:52:22.389997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 10:52:22.390052 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 10:52:22.390108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 10:52:22.390164 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 10:52:22.390219 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 10:52:22.390274 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 10:52:22.390330 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 10:52:22.390385 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 10:52:22.390440 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 10:52:22.390495 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 10:52:22.390551 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 10:52:22.390609 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 10:52:22.390667 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 10:52:22.390723 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 10:52:22.390778 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 10:52:22.390834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 10:52:22.390889 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 10:52:22.390944 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 10:52:22.391000 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 10:52:22.391056 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 10:52:22.391111 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 10:52:22.391167 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 10:52:22.391222 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 10:52:22.391277 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 10:52:22.391333 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 10:52:22.391388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 10:52:22.391444 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 10:52:22.391499 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 10:52:22.391555 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 10:52:22.391611 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 10:52:22.391854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 10:52:22.391917 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 10:52:22.391975 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 10:52:22.392032 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 10:52:22.392088 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 10:52:22.392143 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 10:52:22.392199 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 10:52:22.392254 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 10:52:22.392310 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 10:52:22.392366 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 10:52:22.392422 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 10:52:22.392478 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 10:52:22.392534 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 10:52:22.392589 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 10:52:22.392645 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 10:52:22.392700 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 10:52:22.392757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 10:52:22.392819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 10:52:22.392876 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 10:52:22.392932 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 10:52:22.392988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 10:52:22.393044 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 10:52:22.393100 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 10:52:22.393156 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 10:52:22.393212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 10:52:22.393267 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 10:52:22.393323 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 10:52:22.393379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 10:52:22.393434 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 10:52:22.393490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 10:52:22.393546 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 10:52:22.393601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 10:52:22.393657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 10:52:22.393713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 10:52:22.393768 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 10:52:22.393825 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 10:52:22.393881 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 10:52:22.393936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 10:52:22.393992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 10:52:22.394048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 10:52:22.394104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 10:52:22.394159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 10:52:22.394215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 10:52:22.394271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 10:52:22.394327 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 10:52:22.394385 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 10:52:22.394442 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 10:52:22.394498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 10:52:22.394553 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 10:52:22.394609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 10:52:22.394665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 10:52:22.394720 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 10:52:22.394776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 10:52:22.394832 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 10:52:22.394887 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 10:52:22.394942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 10:52:22.394998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 10:52:22.395053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 10:52:22.395109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 10:52:22.395165 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 10:52:22.395221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 10:52:22.395277 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 10:52:22.395333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 10:52:22.395388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 10:52:22.395444 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 10:52:22.395499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 10:52:22.395555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 10:52:22.395610 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 10:52:22.395666 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 10:52:22.395721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 10:52:22.395777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 10:52:22.395832 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 10:52:22.395889 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 10:52:22.395944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 10:52:22.395999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 10:52:22.396055 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 10:52:22.396111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 10:52:22.396350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 10:52:22.396412 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 10:52:22.396469 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 10:52:22.396526 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 10:52:22.396582 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 10:52:22.396637 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 10:52:22.396693 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 10:52:22.396749 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 10:52:22.396836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 10:52:22.396906 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 10:52:22.396975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 10:52:22.397031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 10:52:22.397101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 10:52:22.397171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 10:52:22.397225 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 10:52:22.397294 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 10:52:22.397364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 10:52:22.397418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 10:52:22.397487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 10:52:22.397557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 10:52:22.397611 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 10:52:22.397679 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 10:52:22.397749 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 10:52:22.397803 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 10:52:22.397871 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 10:52:22.397941 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 10:52:22.397996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 10:52:22.398064 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 10:52:22.398134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 10:52:22.398188 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 10:52:22.398258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 10:52:22.398314 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 10:52:22.398369 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 10:52:22.398425 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 10:52:22.398494 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 10:52:22.398548 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 10:52:22.398603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 10:52:22.398672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 10:52:22.398742 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 10:52:22.398796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 10:52:22.398881 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 10:52:22.398936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 10:52:22.398990 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 10:52:22.399060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 10:52:22.399116 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 10:52:22.399171 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 10:52:22.399227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 10:52:22.399282 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 10:52:22.399337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 10:52:22.399393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 10:52:22.399448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 10:52:22.399504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 10:52:22.399559 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 10:52:22.399615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 10:52:22.399670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 10:52:22.399726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 10:52:22.399781 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 10:52:22.399851 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 10:52:22.399905 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 10:52:22.399960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 10:52:22.400045 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 10:52:22.400099 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 10:52:22.400154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 10:52:22.400240 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 10:52:22.400294 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 10:52:22.400349 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 10:52:22.400433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 10:52:22.400487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 10:52:22.400557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 10:52:22.400613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 10:52:22.400669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 10:52:22.400725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 10:52:22.400784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 10:52:22.400854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 10:52:22.401091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 10:52:22.401168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 10:52:22.401238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 10:52:22.401294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 10:52:22.401381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 10:52:22.401435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 10:52:22.401490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 10:52:22.401577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 10:52:22.401632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 10:52:22.401687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 10:52:22.401771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 10:52:22.401826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 10:52:22.401880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 10:52:22.401965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 10:52:22.402019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 10:52:22.402074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 10:52:22.402158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 10:52:22.402212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 10:52:22.402280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 10:52:22.402336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 10:52:22.402391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 10:52:22.402447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 10:52:22.402502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 10:52:22.402558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 10:52:22.402614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 10:52:22.402669 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 10:52:22.402725 INFO: [APUAPC] vio 0
9968 10:52:22.402781 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 10:52:22.402836 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 10:52:22.402907 INFO: [APUAPC] D0_APC_0: 0x400510
9971 10:52:22.402960 INFO: [APUAPC] D0_APC_1: 0x0
9972 10:52:22.403014 INFO: [APUAPC] D0_APC_2: 0x1540
9973 10:52:22.403098 INFO: [APUAPC] D0_APC_3: 0x0
9974 10:52:22.403152 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 10:52:22.403207 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 10:52:22.403277 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 10:52:22.403332 INFO: [APUAPC] D1_APC_3: 0x0
9978 10:52:22.403401 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 10:52:22.403456 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 10:52:22.403510 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 10:52:22.403564 INFO: [APUAPC] D2_APC_3: 0x0
9982 10:52:22.403618 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 10:52:22.403673 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 10:52:22.403726 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 10:52:22.403780 INFO: [APUAPC] D3_APC_3: 0x0
9986 10:52:22.403834 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 10:52:22.403889 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 10:52:22.403943 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 10:52:22.403996 INFO: [APUAPC] D4_APC_3: 0x0
9990 10:52:22.404050 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 10:52:22.404104 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 10:52:22.404159 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 10:52:22.404216 INFO: [APUAPC] D5_APC_3: 0x0
9994 10:52:22.404304 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 10:52:22.404362 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 10:52:22.404449 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 10:52:22.404503 INFO: [APUAPC] D6_APC_3: 0x0
9998 10:52:22.404557 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 10:52:22.404612 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 10:52:22.404667 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 10:52:22.404721 INFO: [APUAPC] D7_APC_3: 0x0
10002 10:52:22.404814 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 10:52:22.404871 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 10:52:22.404924 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 10:52:22.405006 INFO: [APUAPC] D8_APC_3: 0x0
10006 10:52:22.405075 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 10:52:22.405129 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 10:52:22.405208 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 10:52:22.405279 INFO: [APUAPC] D9_APC_3: 0x0
10010 10:52:22.405335 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 10:52:22.405431 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 10:52:22.405485 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 10:52:22.405567 INFO: [APUAPC] D10_APC_3: 0x0
10014 10:52:22.405637 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 10:52:22.405692 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 10:52:22.405775 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 10:52:22.405846 INFO: [APUAPC] D11_APC_3: 0x0
10018 10:52:22.405920 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 10:52:22.405990 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 10:52:22.406045 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 10:52:22.406124 INFO: [APUAPC] D12_APC_3: 0x0
10022 10:52:22.406197 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 10:52:22.406251 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 10:52:22.406320 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 10:52:22.406375 INFO: [APUAPC] D13_APC_3: 0x0
10026 10:52:22.406430 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 10:52:22.406485 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 10:52:22.406540 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 10:52:22.406596 INFO: [APUAPC] D14_APC_3: 0x0
10030 10:52:22.406651 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 10:52:22.406720 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 10:52:22.406774 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 10:52:22.406860 INFO: [APUAPC] D15_APC_3: 0x0
10034 10:52:22.406929 INFO: [APUAPC] APC_CON: 0x4
10035 10:52:22.406984 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 10:52:22.407221 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 10:52:22.407287 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 10:52:22.407344 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 10:52:22.407400 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 10:52:22.407460 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 10:52:22.407516 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 10:52:22.407571 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 10:52:22.407627 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 10:52:22.407682 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 10:52:22.407738 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 10:52:22.407795 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 10:52:22.407853 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 10:52:22.407908 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 10:52:22.407964 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 10:52:22.408022 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 10:52:22.408077 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 10:52:22.408133 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 10:52:22.408191 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 10:52:22.408248 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 10:52:22.408303 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 10:52:22.408359 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 10:52:22.408420 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 10:52:22.408477 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 10:52:22.408532 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 10:52:22.408591 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 10:52:22.408647 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 10:52:22.408703 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 10:52:22.408760 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 10:52:22.408825 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 10:52:22.408880 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 10:52:22.408938 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 10:52:22.408994 INFO: [NOCDAPC] APC_CON: 0x4
10068 10:52:22.409050 INFO: [APUAPC] set_apusys_apc done
10069 10:52:22.409107 INFO: [DEVAPC] devapc_init done
10070 10:52:22.409166 INFO: GICv3 without legacy support detected.
10071 10:52:22.409222 INFO: ARM GICv3 driver initialized in EL3
10072 10:52:22.409278 INFO: Maximum SPI INTID supported: 639
10073 10:52:22.409337 INFO: BL31: Initializing runtime services
10074 10:52:22.409393 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 10:52:22.409449 INFO: SPM: enable CPC mode
10076 10:52:22.409508 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 10:52:22.409566 INFO: BL31: Preparing for EL3 exit to normal world
10078 10:52:22.409622 INFO: Entry point address = 0x80000000
10079 10:52:22.409677 INFO: SPSR = 0x8
10080 10:52:22.409734
10081 10:52:22.409789
10082 10:52:22.409844
10083 10:52:22.409900 Starting depthcharge on Spherion...
10084 10:52:22.409955
10085 10:52:22.410011 Wipe memory regions:
10086 10:52:22.410066
10087 10:52:22.410122 [0x00000040000000, 0x00000054600000)
10088 10:52:22.410177
10089 10:52:22.410232 [0x00000054660000, 0x00000080000000)
10090 10:52:22.410288
10091 10:52:22.410343 [0x000000821a7280, 0x000000ffe64000)
10092 10:52:22.410949 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10093 10:52:22.411052 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10094 10:52:22.411143 Setting prompt string to ['asurada:']
10095 10:52:22.411232 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10096 10:52:22.839341
10097 10:52:22.839859 [0x00000100000000, 0x00000240000000)
10098 10:52:24.729145
10099 10:52:24.732446 Initializing XHCI USB controller at 0x11200000.
10100 10:52:25.770233
10101 10:52:25.773216 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 10:52:25.773309
10103 10:52:25.773415
10104 10:52:25.773506
10105 10:52:25.773827 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 10:52:25.874155 asurada: tftpboot 192.168.201.1 10590964/tftp-deploy-yzu6itfl/kernel/image.itb 10590964/tftp-deploy-yzu6itfl/kernel/cmdline
10108 10:52:25.874328 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 10:52:25.874452 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10110 10:52:25.878393 tftpboot 192.168.201.1 10590964/tftp-deploy-yzu6itfl/kernel/image.itp-deploy-yzu6itfl/kernel/cmdline
10111 10:52:25.878503
10112 10:52:25.878598 Waiting for link
10113 10:52:26.038737
10114 10:52:26.038893 R8152: Initializing
10115 10:52:26.038960
10116 10:52:26.042097 Version 9 (ocp_data = 6010)
10117 10:52:26.042183
10118 10:52:26.045594 R8152: Done initializing
10119 10:52:26.045679
10120 10:52:26.045746 Adding net device
10121 10:52:27.918241
10122 10:52:27.918398 done.
10123 10:52:27.918468
10124 10:52:27.918531 MAC: 00:e0:4c:72:2d:d6
10125 10:52:27.918591
10126 10:52:27.921390 Sending DHCP discover... done.
10127 10:52:27.921479
10128 10:52:27.924979 Waiting for reply... done.
10129 10:52:27.925099
10130 10:52:27.928231 Sending DHCP request... done.
10131 10:52:27.928321
10132 10:52:27.936637 Waiting for reply... done.
10133 10:52:27.936770
10134 10:52:27.936909 My ip is 192.168.201.21
10135 10:52:27.937013
10136 10:52:27.939809 The DHCP server ip is 192.168.201.1
10137 10:52:27.939921
10138 10:52:27.946664 TFTP server IP predefined by user: 192.168.201.1
10139 10:52:27.946794
10140 10:52:27.953324 Bootfile predefined by user: 10590964/tftp-deploy-yzu6itfl/kernel/image.itb
10141 10:52:27.953441
10142 10:52:27.956444 Sending tftp read request... done.
10143 10:52:27.956559
10144 10:52:27.956676 Waiting for the transfer...
10145 10:52:27.959904
10146 10:52:28.300906 00000000 ################################################################
10147 10:52:28.301083
10148 10:52:28.628760 00080000 ################################################################
10149 10:52:28.628906
10150 10:52:28.964322 00100000 ################################################################
10151 10:52:28.964472
10152 10:52:29.308450 00180000 ################################################################
10153 10:52:29.308607
10154 10:52:29.664269 00200000 ################################################################
10155 10:52:29.664420
10156 10:52:30.020198 00280000 ################################################################
10157 10:52:30.020350
10158 10:52:30.375187 00300000 ################################################################
10159 10:52:30.375338
10160 10:52:30.714547 00380000 ################################################################
10161 10:52:30.714700
10162 10:52:31.061996 00400000 ################################################################
10163 10:52:31.062147
10164 10:52:31.417712 00480000 ################################################################
10165 10:52:31.417865
10166 10:52:31.765845 00500000 ################################################################
10167 10:52:31.765985
10168 10:52:32.123282 00580000 ################################################################
10169 10:52:32.123432
10170 10:52:32.471208 00600000 ################################################################
10171 10:52:32.471359
10172 10:52:32.822724 00680000 ################################################################
10173 10:52:32.822863
10174 10:52:33.184074 00700000 ################################################################
10175 10:52:33.184227
10176 10:52:33.529978 00780000 ################################################################
10177 10:52:33.530181
10178 10:52:33.876123 00800000 ################################################################
10179 10:52:33.876311
10180 10:52:34.221709 00880000 ################################################################
10181 10:52:34.221864
10182 10:52:34.561430 00900000 ################################################################
10183 10:52:34.561585
10184 10:52:34.903639 00980000 ################################################################
10185 10:52:34.903792
10186 10:52:35.245283 00a00000 ################################################################
10187 10:52:35.245467
10188 10:52:35.587679 00a80000 ################################################################
10189 10:52:35.587894
10190 10:52:35.928654 00b00000 ################################################################
10191 10:52:35.928808
10192 10:52:36.270635 00b80000 ################################################################
10193 10:52:36.270770
10194 10:52:36.627497 00c00000 ################################################################
10195 10:52:36.627636
10196 10:52:36.980358 00c80000 ################################################################
10197 10:52:36.980516
10198 10:52:37.324892 00d00000 ################################################################
10199 10:52:37.325045
10200 10:52:37.678958 00d80000 ################################################################
10201 10:52:37.679117
10202 10:52:38.031105 00e00000 ################################################################
10203 10:52:38.031250
10204 10:52:38.388368 00e80000 ################################################################
10205 10:52:38.388511
10206 10:52:38.743704 00f00000 ################################################################
10207 10:52:38.743851
10208 10:52:39.091920 00f80000 ################################################################
10209 10:52:39.092064
10210 10:52:39.429424 01000000 ################################################################
10211 10:52:39.429594
10212 10:52:39.778615 01080000 ################################################################
10213 10:52:39.778766
10214 10:52:40.111301 01100000 ################################################################
10215 10:52:40.111445
10216 10:52:40.453814 01180000 ################################################################
10217 10:52:40.453967
10218 10:52:40.797739 01200000 ################################################################
10219 10:52:40.797893
10220 10:52:41.141069 01280000 ################################################################
10221 10:52:41.141215
10222 10:52:41.497952 01300000 ################################################################
10223 10:52:41.498137
10224 10:52:41.851064 01380000 ################################################################
10225 10:52:41.851247
10226 10:52:42.202192 01400000 ################################################################
10227 10:52:42.202345
10228 10:52:42.549731 01480000 ################################################################
10229 10:52:42.549881
10230 10:52:42.890472 01500000 ################################################################
10231 10:52:42.890619
10232 10:52:43.250635 01580000 ################################################################
10233 10:52:43.250783
10234 10:52:43.593017 01600000 ################################################################
10235 10:52:43.593187
10236 10:52:43.945382 01680000 ################################################################
10237 10:52:43.945538
10238 10:52:44.301468 01700000 ################################################################
10239 10:52:44.301629
10240 10:52:44.648313 01780000 ################################################################
10241 10:52:44.648465
10242 10:52:44.985088 01800000 ################################################################
10243 10:52:44.985233
10244 10:52:45.337276 01880000 ################################################################
10245 10:52:45.337445
10246 10:52:45.687928 01900000 ################################################################
10247 10:52:45.688119
10248 10:52:46.048442 01980000 ################################################################
10249 10:52:46.048627
10250 10:52:46.385218 01a00000 ############################################################### done.
10251 10:52:46.385393
10252 10:52:46.388468 The bootfile was 27774210 bytes long.
10253 10:52:46.388549
10254 10:52:46.392183 Sending tftp read request... done.
10255 10:52:46.392287
10256 10:52:46.395253 Waiting for the transfer...
10257 10:52:46.395361
10258 10:52:46.398583 00000000 # done.
10259 10:52:46.398662
10260 10:52:46.405049 Command line loaded dynamically from TFTP file: 10590964/tftp-deploy-yzu6itfl/kernel/cmdline
10261 10:52:46.405213
10262 10:52:46.424718 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10263 10:52:46.424904
10264 10:52:46.424976 Loading FIT.
10265 10:52:46.425040
10266 10:52:46.428024 Image ramdisk-1 has 17643313 bytes.
10267 10:52:46.428131
10268 10:52:46.431559 Image fdt-1 has 46924 bytes.
10269 10:52:46.431668
10270 10:52:46.434703 Image kernel-1 has 10081937 bytes.
10271 10:52:46.434805
10272 10:52:46.444662 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10273 10:52:46.444866
10274 10:52:46.461027 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10275 10:52:46.461212
10276 10:52:46.467705 Choosing best match conf-1 for compat google,spherion-rev2.
10277 10:52:46.467842
10278 10:52:46.474789 Connected to device vid:did:rid of 1ae0:0028:00
10279 10:52:46.481999
10280 10:52:46.485163 tpm_get_response: command 0x17b, return code 0x0
10281 10:52:46.485265
10282 10:52:46.491747 ec_init: CrosEC protocol v3 supported (256, 248)
10283 10:52:46.491872
10284 10:52:46.495056 tpm_cleanup: add release locality here.
10285 10:52:46.495164
10286 10:52:46.498568 Shutting down all USB controllers.
10287 10:52:46.498675
10288 10:52:46.501995 Removing current net device
10289 10:52:46.502101
10290 10:52:46.505037 Exiting depthcharge with code 4 at timestamp: 54079535
10291 10:52:46.505119
10292 10:52:46.511702 LZMA decompressing kernel-1 to 0x821a6718
10293 10:52:46.511832
10294 10:52:46.515106 LZMA decompressing kernel-1 to 0x40000000
10295 10:52:47.780486
10296 10:52:47.780643 jumping to kernel
10297 10:52:47.781047 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10298 10:52:47.781148 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10299 10:52:47.781225 Setting prompt string to ['Linux version [0-9]']
10300 10:52:47.781294 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10301 10:52:47.781363 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10302 10:52:47.862041
10303 10:52:47.865265 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10304 10:52:47.868829 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10305 10:52:47.868958 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10306 10:52:47.869062 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10307 10:52:47.869168 Using line separator: #'\n'#
10308 10:52:47.869230 No login prompt set.
10309 10:52:47.869291 Parsing kernel messages
10310 10:52:47.869376 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10311 10:52:47.869479 [login-action] Waiting for messages, (timeout 00:03:59)
10312 10:52:47.888118 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10313 10:52:47.891673 [ 0.000000] random: crng init done
10314 10:52:47.895027 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 10:52:47.898198 [ 0.000000] efi: UEFI not found.
10316 10:52:47.907970 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 10:52:47.914617 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 10:52:47.924425 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 10:52:47.934709 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 10:52:47.941039 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 10:52:47.947423 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 10:52:47.954441 [ 0.000000] NUMA: No NUMA configuration found
10323 10:52:47.960563 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 10:52:47.964073 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10325 10:52:47.967316 [ 0.000000] Zone ranges:
10326 10:52:47.973793 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 10:52:47.977280 [ 0.000000] DMA32 empty
10328 10:52:47.983694 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 10:52:47.987093 [ 0.000000] Movable zone start for each node
10330 10:52:47.990382 [ 0.000000] Early memory node ranges
10331 10:52:47.996989 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 10:52:48.003546 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 10:52:48.010361 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 10:52:48.016933 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 10:52:48.020589 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 10:52:48.030172 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 10:52:48.085879 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 10:52:48.092241 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 10:52:48.099151 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 10:52:48.102142 [ 0.000000] psci: probing for conduit method from DT.
10341 10:52:48.108680 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 10:52:48.112352 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 10:52:48.118664 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 10:52:48.122372 [ 0.000000] psci: SMC Calling Convention v1.2
10345 10:52:48.128681 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10346 10:52:48.132176 [ 0.000000] Detected VIPT I-cache on CPU0
10347 10:52:48.138799 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 10:52:48.145559 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 10:52:48.151836 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 10:52:48.158507 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 10:52:48.168204 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 10:52:48.175034 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 10:52:48.178242 [ 0.000000] alternatives: applying boot alternatives
10354 10:52:48.184965 [ 0.000000] Fallback order for Node 0: 0
10355 10:52:48.191332 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 10:52:48.194695 [ 0.000000] Policy zone: Normal
10357 10:52:48.214786 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10358 10:52:48.224470 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 10:52:48.235497 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 10:52:48.245464 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 10:52:48.251748 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 10:52:48.255187 <6>[ 0.000000] software IO TLB: area num 8.
10363 10:52:48.311893 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 10:52:48.461010 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10365 10:52:48.467463 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 10:52:48.474092 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 10:52:48.477571 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 10:52:48.484054 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 10:52:48.490932 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 10:52:48.494304 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 10:52:48.503591 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 10:52:48.510334 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 10:52:48.516936 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 10:52:48.523669 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 10:52:48.526871 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 10:52:48.530196 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 10:52:48.536609 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 10:52:48.540324 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 10:52:48.546791 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 10:52:48.559777 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 10:52:48.572836 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 10:52:48.579470 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 10:52:48.587440 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 10:52:48.600702 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 10:52:48.607073 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 10:52:48.614120 <6>[ 0.009177] Console: colour dummy device 80x25
10387 10:52:48.623741 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 10:52:48.630047 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10389 10:52:48.633757 <6>[ 0.029285] LSM: Security Framework initializing
10390 10:52:48.640096 <6>[ 0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 10:52:48.650212 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 10:52:48.659936 <6>[ 0.051465] cblist_init_generic: Setting adjustable number of callback queues.
10393 10:52:48.663002 <6>[ 0.058963] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 10:52:48.669856 <6>[ 0.065340] cblist_init_generic: Setting shift to 3 and lim to 1.
10395 10:52:48.676881 <6>[ 0.071746] rcu: Hierarchical SRCU implementation.
10396 10:52:48.683023 <6>[ 0.076759] rcu: Max phase no-delay instances is 1000.
10397 10:52:48.689687 <6>[ 0.083777] EFI services will not be available.
10398 10:52:48.692995 <6>[ 0.088780] smp: Bringing up secondary CPUs ...
10399 10:52:48.700938 <6>[ 0.093863] Detected VIPT I-cache on CPU1
10400 10:52:48.707321 <6>[ 0.093936] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10401 10:52:48.714002 <6>[ 0.093968] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10402 10:52:48.717678 <6>[ 0.094301] Detected VIPT I-cache on CPU2
10403 10:52:48.723815 <6>[ 0.094349] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10404 10:52:48.733806 <6>[ 0.094364] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10405 10:52:48.737410 <6>[ 0.094626] Detected VIPT I-cache on CPU3
10406 10:52:48.743931 <6>[ 0.094672] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10407 10:52:48.750507 <6>[ 0.094685] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10408 10:52:48.753440 <6>[ 0.094989] CPU features: detected: Spectre-v4
10409 10:52:48.760211 <6>[ 0.094995] CPU features: detected: Spectre-BHB
10410 10:52:48.763444 <6>[ 0.095001] Detected PIPT I-cache on CPU4
10411 10:52:48.769819 <6>[ 0.095056] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10412 10:52:48.776429 <6>[ 0.095073] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10413 10:52:48.783309 <6>[ 0.095357] Detected PIPT I-cache on CPU5
10414 10:52:48.789650 <6>[ 0.095413] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10415 10:52:48.796444 <6>[ 0.095429] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10416 10:52:48.799743 <6>[ 0.095698] Detected PIPT I-cache on CPU6
10417 10:52:48.806396 <6>[ 0.095762] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10418 10:52:48.816543 <6>[ 0.095778] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10419 10:52:48.819738 <6>[ 0.096075] Detected PIPT I-cache on CPU7
10420 10:52:48.826112 <6>[ 0.096141] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10421 10:52:48.832598 <6>[ 0.096157] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10422 10:52:48.835969 <6>[ 0.096203] smp: Brought up 1 node, 8 CPUs
10423 10:52:48.842504 <6>[ 0.237506] SMP: Total of 8 processors activated.
10424 10:52:48.846085 <6>[ 0.242427] CPU features: detected: 32-bit EL0 Support
10425 10:52:48.855925 <6>[ 0.247790] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10426 10:52:48.862447 <6>[ 0.256644] CPU features: detected: Common not Private translations
10427 10:52:48.869105 <6>[ 0.263119] CPU features: detected: CRC32 instructions
10428 10:52:48.872637 <6>[ 0.268471] CPU features: detected: RCpc load-acquire (LDAPR)
10429 10:52:48.879219 <6>[ 0.274430] CPU features: detected: LSE atomic instructions
10430 10:52:48.885531 <6>[ 0.280211] CPU features: detected: Privileged Access Never
10431 10:52:48.891970 <6>[ 0.286027] CPU features: detected: RAS Extension Support
10432 10:52:48.898833 <6>[ 0.291635] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10433 10:52:48.902000 <6>[ 0.298858] CPU: All CPU(s) started at EL2
10434 10:52:48.908588 <6>[ 0.303174] alternatives: applying system-wide alternatives
10435 10:52:48.918177 <6>[ 0.313916] devtmpfs: initialized
10436 10:52:48.930973 <6>[ 0.323039] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10437 10:52:48.940983 <6>[ 0.333004] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10438 10:52:48.947385 <6>[ 0.341226] pinctrl core: initialized pinctrl subsystem
10439 10:52:48.950950 <6>[ 0.347879] DMI not present or invalid.
10440 10:52:48.957246 <6>[ 0.352283] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10441 10:52:48.967410 <6>[ 0.359175] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10442 10:52:48.973542 <6>[ 0.366751] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10443 10:52:48.983492 <6>[ 0.374972] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10444 10:52:48.987119 <6>[ 0.383211] audit: initializing netlink subsys (disabled)
10445 10:52:48.996970 <5>[ 0.388905] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10446 10:52:49.003400 <6>[ 0.389616] thermal_sys: Registered thermal governor 'step_wise'
10447 10:52:49.009973 <6>[ 0.396874] thermal_sys: Registered thermal governor 'power_allocator'
10448 10:52:49.013571 <6>[ 0.403129] cpuidle: using governor menu
10449 10:52:49.020005 <6>[ 0.414081] NET: Registered PF_QIPCRTR protocol family
10450 10:52:49.026945 <6>[ 0.419571] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10451 10:52:49.033455 <6>[ 0.426674] ASID allocator initialised with 32768 entries
10452 10:52:49.036669 <6>[ 0.433236] Serial: AMBA PL011 UART driver
10453 10:52:49.046361 <4>[ 0.441937] Trying to register duplicate clock ID: 134
10454 10:52:49.100434 <6>[ 0.499369] KASLR enabled
10455 10:52:49.115298 <6>[ 0.507271] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10456 10:52:49.121517 <6>[ 0.514286] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10457 10:52:49.128355 <6>[ 0.520777] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10458 10:52:49.135033 <6>[ 0.527782] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10459 10:52:49.141728 <6>[ 0.534269] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10460 10:52:49.148042 <6>[ 0.541273] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10461 10:52:49.154606 <6>[ 0.547761] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10462 10:52:49.161203 <6>[ 0.554766] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10463 10:52:49.164245 <6>[ 0.562278] ACPI: Interpreter disabled.
10464 10:52:49.173183 <6>[ 0.568683] iommu: Default domain type: Translated
10465 10:52:49.179640 <6>[ 0.573794] iommu: DMA domain TLB invalidation policy: strict mode
10466 10:52:49.183143 <5>[ 0.580447] SCSI subsystem initialized
10467 10:52:49.189458 <6>[ 0.584611] usbcore: registered new interface driver usbfs
10468 10:52:49.196266 <6>[ 0.590343] usbcore: registered new interface driver hub
10469 10:52:49.199503 <6>[ 0.595893] usbcore: registered new device driver usb
10470 10:52:49.206500 <6>[ 0.601969] pps_core: LinuxPPS API ver. 1 registered
10471 10:52:49.216282 <6>[ 0.607160] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10472 10:52:49.219652 <6>[ 0.616508] PTP clock support registered
10473 10:52:49.222716 <6>[ 0.620750] EDAC MC: Ver: 3.0.0
10474 10:52:49.230308 <6>[ 0.625885] FPGA manager framework
10475 10:52:49.236946 <6>[ 0.629566] Advanced Linux Sound Architecture Driver Initialized.
10476 10:52:49.240622 <6>[ 0.636335] vgaarb: loaded
10477 10:52:49.247274 <6>[ 0.639510] clocksource: Switched to clocksource arch_sys_counter
10478 10:52:49.249950 <5>[ 0.645939] VFS: Disk quotas dquot_6.6.0
10479 10:52:49.256502 <6>[ 0.650121] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10480 10:52:49.259984 <6>[ 0.657307] pnp: PnP ACPI: disabled
10481 10:52:49.268350 <6>[ 0.663981] NET: Registered PF_INET protocol family
10482 10:52:49.278467 <6>[ 0.669561] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10483 10:52:49.289763 <6>[ 0.681839] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10484 10:52:49.299541 <6>[ 0.690653] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10485 10:52:49.306197 <6>[ 0.698619] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10486 10:52:49.316035 <6>[ 0.707316] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10487 10:52:49.322609 <6>[ 0.717036] TCP: Hash tables configured (established 65536 bind 65536)
10488 10:52:49.328726 <6>[ 0.723888] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10489 10:52:49.338957 <6>[ 0.731086] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 10:52:49.345845 <6>[ 0.738788] NET: Registered PF_UNIX/PF_LOCAL protocol family
10491 10:52:49.352020 <6>[ 0.744960] RPC: Registered named UNIX socket transport module.
10492 10:52:49.355433 <6>[ 0.751114] RPC: Registered udp transport module.
10493 10:52:49.361578 <6>[ 0.756044] RPC: Registered tcp transport module.
10494 10:52:49.368435 <6>[ 0.760977] RPC: Registered tcp NFSv4.1 backchannel transport module.
10495 10:52:49.371998 <6>[ 0.767647] PCI: CLS 0 bytes, default 64
10496 10:52:49.374980 <6>[ 0.772004] Unpacking initramfs...
10497 10:52:49.392067 <6>[ 0.784151] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10498 10:52:49.401654 <6>[ 0.792805] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10499 10:52:49.404983 <6>[ 0.801643] kvm [1]: IPA Size Limit: 40 bits
10500 10:52:49.411539 <6>[ 0.806172] kvm [1]: GICv3: no GICV resource entry
10501 10:52:49.414985 <6>[ 0.811194] kvm [1]: disabling GICv2 emulation
10502 10:52:49.421327 <6>[ 0.815878] kvm [1]: GIC system register CPU interface enabled
10503 10:52:49.424919 <6>[ 0.822043] kvm [1]: vgic interrupt IRQ18
10504 10:52:49.431285 <6>[ 0.826408] kvm [1]: VHE mode initialized successfully
10505 10:52:49.437848 <5>[ 0.832877] Initialise system trusted keyrings
10506 10:52:49.444680 <6>[ 0.837702] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10507 10:52:49.452684 <6>[ 0.847888] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10508 10:52:49.458850 <5>[ 0.854287] NFS: Registering the id_resolver key type
10509 10:52:49.462132 <5>[ 0.859591] Key type id_resolver registered
10510 10:52:49.468755 <5>[ 0.864009] Key type id_legacy registered
10511 10:52:49.475578 <6>[ 0.868290] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10512 10:52:49.482144 <6>[ 0.875210] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10513 10:52:49.488665 <6>[ 0.882920] 9p: Installing v9fs 9p2000 file system support
10514 10:52:49.525958 <5>[ 0.921096] Key type asymmetric registered
10515 10:52:49.528878 <5>[ 0.925426] Asymmetric key parser 'x509' registered
10516 10:52:49.538612 <6>[ 0.930565] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10517 10:52:49.542075 <6>[ 0.938182] io scheduler mq-deadline registered
10518 10:52:49.545286 <6>[ 0.942942] io scheduler kyber registered
10519 10:52:49.564387 <6>[ 0.959990] EINJ: ACPI disabled.
10520 10:52:49.596773 <4>[ 0.985809] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10521 10:52:49.606766 <4>[ 0.996440] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 10:52:49.621720 <6>[ 1.017208] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10523 10:52:49.629583 <6>[ 1.025255] printk: console [ttyS0] disabled
10524 10:52:49.657772 <6>[ 1.049902] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10525 10:52:49.664218 <6>[ 1.059389] printk: console [ttyS0] enabled
10526 10:52:49.668291 <6>[ 1.059389] printk: console [ttyS0] enabled
10527 10:52:49.674174 <6>[ 1.068282] printk: bootconsole [mtk8250] disabled
10528 10:52:49.677602 <6>[ 1.068282] printk: bootconsole [mtk8250] disabled
10529 10:52:49.684038 <6>[ 1.079558] SuperH (H)SCI(F) driver initialized
10530 10:52:49.687385 <6>[ 1.084838] msm_serial: driver initialized
10531 10:52:49.701798 <6>[ 1.093775] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10532 10:52:49.711285 <6>[ 1.102326] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10533 10:52:49.718153 <6>[ 1.110868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10534 10:52:49.727900 <6>[ 1.119504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10535 10:52:49.737953 <6>[ 1.128211] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10536 10:52:49.744322 <6>[ 1.136931] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10537 10:52:49.754224 <6>[ 1.145475] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10538 10:52:49.761000 <6>[ 1.154287] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10539 10:52:49.770582 <6>[ 1.162835] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10540 10:52:49.783083 <6>[ 1.178550] loop: module loaded
10541 10:52:49.789540 <6>[ 1.184592] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10542 10:52:49.812252 <4>[ 1.208026] mtk-pmic-keys: Failed to locate of_node [id: -1]
10543 10:52:49.819325 <6>[ 1.214763] megasas: 07.719.03.00-rc1
10544 10:52:49.828773 <6>[ 1.224285] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10545 10:52:49.839436 <6>[ 1.234881] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10546 10:52:49.855844 <6>[ 1.251613] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10547 10:52:49.916162 <6>[ 1.305183] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10548 10:52:50.096095 <6>[ 1.491576] Freeing initrd memory: 17224K
10549 10:52:50.105951 <6>[ 1.501723] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10550 10:52:50.116920 <6>[ 1.512601] tun: Universal TUN/TAP device driver, 1.6
10551 10:52:50.120280 <6>[ 1.518643] thunder_xcv, ver 1.0
10552 10:52:50.123897 <6>[ 1.522146] thunder_bgx, ver 1.0
10553 10:52:50.126970 <6>[ 1.525641] nicpf, ver 1.0
10554 10:52:50.137616 <6>[ 1.529642] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10555 10:52:50.140629 <6>[ 1.537118] hns3: Copyright (c) 2017 Huawei Corporation.
10556 10:52:50.147528 <6>[ 1.542704] hclge is initializing
10557 10:52:50.150576 <6>[ 1.546281] e1000: Intel(R) PRO/1000 Network Driver
10558 10:52:50.157129 <6>[ 1.551410] e1000: Copyright (c) 1999-2006 Intel Corporation.
10559 10:52:50.160606 <6>[ 1.557423] e1000e: Intel(R) PRO/1000 Network Driver
10560 10:52:50.167133 <6>[ 1.562638] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10561 10:52:50.173765 <6>[ 1.568825] igb: Intel(R) Gigabit Ethernet Network Driver
10562 10:52:50.180237 <6>[ 1.574475] igb: Copyright (c) 2007-2014 Intel Corporation.
10563 10:52:50.187137 <6>[ 1.580312] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10564 10:52:50.193468 <6>[ 1.586829] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10565 10:52:50.197149 <6>[ 1.593285] sky2: driver version 1.30
10566 10:52:50.203452 <6>[ 1.598265] VFIO - User Level meta-driver version: 0.3
10567 10:52:50.210810 <6>[ 1.606376] usbcore: registered new interface driver usb-storage
10568 10:52:50.217661 <6>[ 1.612828] usbcore: registered new device driver onboard-usb-hub
10569 10:52:50.226086 <6>[ 1.621832] mt6397-rtc mt6359-rtc: registered as rtc0
10570 10:52:50.236040 <6>[ 1.627297] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:52:47 UTC (1685962367)
10571 10:52:50.239593 <6>[ 1.636866] i2c_dev: i2c /dev entries driver
10572 10:52:50.255992 <6>[ 1.648567] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10573 10:52:50.263156 <6>[ 1.658729] sdhci: Secure Digital Host Controller Interface driver
10574 10:52:50.269743 <6>[ 1.665169] sdhci: Copyright(c) Pierre Ossman
10575 10:52:50.276525 <6>[ 1.670563] Synopsys Designware Multimedia Card Interface Driver
10576 10:52:50.279823 <6>[ 1.677188] mmc0: CQHCI version 5.10
10577 10:52:50.286146 <6>[ 1.677714] sdhci-pltfm: SDHCI platform and OF driver helper
10578 10:52:50.293755 <6>[ 1.689328] ledtrig-cpu: registered to indicate activity on CPUs
10579 10:52:50.304234 <6>[ 1.696759] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10580 10:52:50.307778 <6>[ 1.704151] usbcore: registered new interface driver usbhid
10581 10:52:50.314455 <6>[ 1.709979] usbhid: USB HID core driver
10582 10:52:50.320912 <6>[ 1.714235] spi_master spi0: will run message pump with realtime priority
10583 10:52:50.368675 <6>[ 1.757639] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10584 10:52:50.387937 <6>[ 1.773011] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10585 10:52:50.391022 <6>[ 1.786583] mmc0: Command Queue Engine enabled
10586 10:52:50.397837 <6>[ 1.788008] cros-ec-spi spi0.0: Chrome EC device registered
10587 10:52:50.404566 <6>[ 1.791332] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10588 10:52:50.407929 <6>[ 1.804592] mmcblk0: mmc0:0001 DA4128 116 GiB
10589 10:52:50.423013 <6>[ 1.815338] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10590 10:52:50.429471 <6>[ 1.816968] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 10:52:50.436561 <6>[ 1.826781] NET: Registered PF_PACKET protocol family
10592 10:52:50.440005 <6>[ 1.831621] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10593 10:52:50.446691 <6>[ 1.836001] 9pnet: Installing 9P2000 support
10594 10:52:50.449685 <6>[ 1.841818] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10595 10:52:50.456467 <5>[ 1.845679] Key type dns_resolver registered
10596 10:52:50.462802 <6>[ 1.851539] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10597 10:52:50.466653 <6>[ 1.855998] registered taskstats version 1
10598 10:52:50.469536 <5>[ 1.866307] Loading compiled-in X.509 certificates
10599 10:52:50.504934 <4>[ 1.893680] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 10:52:50.514441 <4>[ 1.904401] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 10:52:50.524956 <3>[ 1.917248] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10602 10:52:50.536996 <6>[ 1.932653] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10603 10:52:50.544021 <6>[ 1.939403] xhci-mtk 11200000.usb: xHCI Host Controller
10604 10:52:50.550441 <6>[ 1.944908] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10605 10:52:50.560531 <6>[ 1.952777] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10606 10:52:50.567122 <6>[ 1.962226] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10607 10:52:50.573787 <6>[ 1.968413] xhci-mtk 11200000.usb: xHCI Host Controller
10608 10:52:50.580283 <6>[ 1.973909] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10609 10:52:50.587079 <6>[ 1.981570] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10610 10:52:50.594055 <6>[ 1.989374] hub 1-0:1.0: USB hub found
10611 10:52:50.597532 <6>[ 1.993424] hub 1-0:1.0: 1 port detected
10612 10:52:50.606978 <6>[ 1.997784] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10613 10:52:50.610516 <6>[ 2.006595] hub 2-0:1.0: USB hub found
10614 10:52:50.613865 <6>[ 2.010636] hub 2-0:1.0: 1 port detected
10615 10:52:50.622617 <6>[ 2.017944] mtk-msdc 11f70000.mmc: Got CD GPIO
10616 10:52:50.643767 <6>[ 2.036142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10617 10:52:50.650852 <6>[ 2.044177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10618 10:52:50.660501 <4>[ 2.052204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10619 10:52:50.670633 <6>[ 2.061868] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10620 10:52:50.677082 <6>[ 2.069989] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10621 10:52:50.687352 <6>[ 2.078032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10622 10:52:50.693754 <6>[ 2.085985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10623 10:52:50.700255 <6>[ 2.093814] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10624 10:52:50.710248 <6>[ 2.101661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10625 10:52:50.720494 <6>[ 2.112548] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10626 10:52:50.730827 <6>[ 2.120952] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10627 10:52:50.736963 <6>[ 2.129301] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10628 10:52:50.747101 <6>[ 2.137670] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10629 10:52:50.753503 <6>[ 2.146023] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10630 10:52:50.763823 <6>[ 2.154391] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10631 10:52:50.770160 <6>[ 2.162736] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10632 10:52:50.780562 <6>[ 2.171099] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10633 10:52:50.786760 <6>[ 2.179443] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10634 10:52:50.797076 <6>[ 2.187787] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10635 10:52:50.803326 <6>[ 2.196130] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10636 10:52:50.813477 <6>[ 2.204474] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10637 10:52:50.819900 <6>[ 2.212817] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10638 10:52:50.829929 <6>[ 2.221161] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10639 10:52:50.836421 <6>[ 2.229504] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10640 10:52:50.843095 <6>[ 2.238447] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10641 10:52:50.850544 <6>[ 2.245893] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10642 10:52:50.857239 <6>[ 2.252917] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10643 10:52:50.867751 <6>[ 2.260007] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10644 10:52:50.874348 <6>[ 2.267273] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10645 10:52:50.884215 <6>[ 2.274115] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10646 10:52:50.890693 <6>[ 2.283295] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10647 10:52:50.900682 <6>[ 2.292568] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10648 10:52:50.910444 <6>[ 2.302023] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10649 10:52:50.920612 <6>[ 2.311506] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10650 10:52:50.930190 <6>[ 2.320981] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10651 10:52:50.940256 <6>[ 2.330109] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10652 10:52:50.947098 <6>[ 2.339583] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10653 10:52:50.956662 <6>[ 2.348710] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10654 10:52:50.966489 <6>[ 2.358011] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10655 10:52:50.976688 <6>[ 2.368211] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10656 10:52:50.987692 <6>[ 2.380050] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10657 10:52:50.994535 <6>[ 2.389972] Trying to probe devices needed for running init ...
10658 10:52:51.035197 <6>[ 2.427785] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10659 10:52:51.187356 <6>[ 2.583187] hub 1-1:1.0: USB hub found
10660 10:52:51.190550 <6>[ 2.587480] hub 1-1:1.0: 4 ports detected
10661 10:52:51.315561 <6>[ 2.707944] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10662 10:52:51.340010 <6>[ 2.735734] hub 2-1:1.0: USB hub found
10663 10:52:51.343244 <6>[ 2.740097] hub 2-1:1.0: 3 ports detected
10664 10:52:51.511144 <6>[ 2.903808] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10665 10:52:51.644150 <6>[ 3.040017] hub 1-1.4:1.0: USB hub found
10666 10:52:51.647738 <6>[ 3.044692] hub 1-1.4:1.0: 2 ports detected
10667 10:52:51.723615 <6>[ 3.116031] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10668 10:52:51.943094 <6>[ 3.335781] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10669 10:52:52.135510 <6>[ 3.527780] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10670 10:53:03.267892 <6>[ 14.668395] ALSA device list:
10671 10:53:03.274525 <6>[ 14.671649] No soundcards found.
10672 10:53:03.287083 <6>[ 14.684048] Freeing unused kernel memory: 8384K
10673 10:53:03.290007 <6>[ 14.688980] Run /init as init process
10674 10:53:03.300535 Loading, please wait...
10675 10:53:03.319611 Starting version 247.3-7+deb11u2
10676 10:53:03.636031 <6>[ 15.029953] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10677 10:53:03.645165 <6>[ 15.042183] remoteproc remoteproc0: scp is available
10678 10:53:03.655231 <4>[ 15.047897] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10679 10:53:03.661506 <6>[ 15.058023] remoteproc remoteproc0: powering up scp
10680 10:53:03.671474 <4>[ 15.063211] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10681 10:53:03.678099 <3>[ 15.073045] remoteproc remoteproc0: request_firmware failed: -2
10682 10:53:03.684912 <3>[ 15.075079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 10:53:03.691476 <6>[ 15.080350] mc: Linux media interface: v0.10
10684 10:53:03.697682 <3>[ 15.087532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 10:53:03.704456 <6>[ 15.099601] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10686 10:53:03.714768 <3>[ 15.100113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 10:53:03.720994 <6>[ 15.107693] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10688 10:53:03.731311 <3>[ 15.124122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 10:53:03.737453 <6>[ 15.124472] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10690 10:53:03.743992 <6>[ 15.132076] videodev: Linux video capture interface: v2.00
10691 10:53:03.754036 <3>[ 15.132524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 10:53:03.757172 <6>[ 15.147873] usbcore: registered new interface driver r8152
10693 10:53:03.767292 <3>[ 15.155133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 10:53:03.773943 <3>[ 15.168930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 10:53:03.783672 <3>[ 15.177024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 10:53:03.790441 <6>[ 15.179145] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10697 10:53:03.805097 <4>[ 15.198994] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10698 10:53:03.808264 <6>[ 15.199990] Bluetooth: Core ver 2.22
10699 10:53:03.815171 <3>[ 15.200197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 10:53:03.824691 <3>[ 15.200328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 10:53:03.831498 <3>[ 15.200339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 10:53:03.841504 <3>[ 15.200990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 10:53:03.848298 <3>[ 15.205203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 10:53:03.858243 <3>[ 15.205220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 10:53:03.865195 <3>[ 15.205230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 10:53:03.871918 <3>[ 15.205245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 10:53:03.881690 <3>[ 15.205254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 10:53:03.888369 <3>[ 15.205312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 10:53:03.895065 <4>[ 15.206823] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10710 10:53:03.901694 <6>[ 15.211091] NET: Registered PF_BLUETOOTH protocol family
10711 10:53:03.911949 <4>[ 15.234878] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10712 10:53:03.915428 <4>[ 15.234878] Fallback method does not support PEC.
10713 10:53:03.922469 <6>[ 15.242708] Bluetooth: HCI device and connection manager initialized
10714 10:53:03.928723 <6>[ 15.242728] Bluetooth: HCI socket layer initialized
10715 10:53:03.935508 <6>[ 15.261145] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10716 10:53:03.938716 <6>[ 15.266994] Bluetooth: L2CAP socket layer initialized
10717 10:53:03.945239 <6>[ 15.267012] Bluetooth: SCO socket layer initialized
10718 10:53:03.951757 <3>[ 15.268758] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 10:53:03.958621 <6>[ 15.275280] pci_bus 0000:00: root bus resource [bus 00-ff]
10720 10:53:03.965300 <6>[ 15.291832] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10721 10:53:03.975080 <6>[ 15.298804] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10722 10:53:03.978170 <3>[ 15.319676] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10723 10:53:03.988374 <6>[ 15.324526] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10724 10:53:03.994901 <6>[ 15.324574] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10725 10:53:04.005018 <6>[ 15.329735] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10726 10:53:04.014547 <3>[ 15.329803] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 10:53:04.024367 <4>[ 15.332593] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10728 10:53:04.031187 <4>[ 15.332602] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10729 10:53:04.040845 <6>[ 15.336546] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10730 10:53:04.047805 <6>[ 15.342302] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10731 10:53:04.054167 <6>[ 15.347050] pci 0000:00:00.0: supports D1 D2
10732 10:53:04.057509 <6>[ 15.391613] r8152 2-1.3:1.0 eth0: v1.12.13
10733 10:53:04.064058 <6>[ 15.392078] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10734 10:53:04.070741 <3>[ 15.435669] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10735 10:53:04.077494 <6>[ 15.443667] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10736 10:53:04.084130 <6>[ 15.481322] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10737 10:53:04.094304 <6>[ 15.487612] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10738 10:53:04.100589 <6>[ 15.495108] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10739 10:53:04.107050 <6>[ 15.502595] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10740 10:53:04.113931 <6>[ 15.510180] pci 0000:01:00.0: supports D1 D2
10741 10:53:04.120378 <6>[ 15.514705] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10742 10:53:04.137748 <6>[ 15.531688] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10743 10:53:04.144272 <6>[ 15.538597] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10744 10:53:04.150852 <6>[ 15.546687] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10745 10:53:04.157403 <3>[ 15.547760] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10746 10:53:04.167495 <6>[ 15.554691] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10747 10:53:04.174141 <3>[ 15.561445] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10748 10:53:04.180633 <6>[ 15.569123] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10749 10:53:04.190458 <6>[ 15.576021] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10750 10:53:04.200348 <6>[ 15.583896] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10751 10:53:04.203552 <6>[ 15.601195] pci 0000:00:00.0: PCI bridge to [bus 01]
10752 10:53:04.210392 <6>[ 15.601919] usbcore: registered new interface driver cdc_ether
10753 10:53:04.216931 <6>[ 15.606447] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10754 10:53:04.226827 <6>[ 15.607564] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10755 10:53:04.236892 <6>[ 15.608964] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10756 10:53:04.243336 <6>[ 15.609155] usbcore: registered new interface driver uvcvideo
10757 10:53:04.250258 <6>[ 15.620773] usbcore: registered new interface driver r8153_ecm
10758 10:53:04.256591 <6>[ 15.627804] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10759 10:53:04.263374 <6>[ 15.629033] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10760 10:53:04.269982 <6>[ 15.640905] usbcore: registered new interface driver btusb
10761 10:53:04.279825 <4>[ 15.641742] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10762 10:53:04.286348 <3>[ 15.641752] Bluetooth: hci0: Failed to load firmware file (-2)
10763 10:53:04.289895 <3>[ 15.641755] Bluetooth: hci0: Failed to set up firmware (-2)
10764 10:53:04.299456 <4>[ 15.641758] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10765 10:53:04.306407 <6>[ 15.647089] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10766 10:53:04.312733 <6>[ 15.649240] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10767 10:53:04.319414 <6>[ 15.716304] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10768 10:53:04.338445 <5>[ 15.732235] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10769 10:53:04.357690 <5>[ 15.751560] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10770 10:53:04.364495 <4>[ 15.758474] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10771 10:53:04.370879 <6>[ 15.767386] cfg80211: failed to load regulatory.db
10772 10:53:04.417037 <6>[ 15.810728] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10773 10:53:04.423397 <6>[ 15.818263] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10774 10:53:04.447726 <6>[ 15.845034] mt7921e 0000:01:00.0: ASIC revision: 79610010
10775 10:53:04.553348 <4>[ 15.943923] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 10:53:04.556743 Begin: Loading essential drivers ... done.
10777 10:53:04.563140 Begin: Running /scripts/init-premount ... done.
10778 10:53:04.569688 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10779 10:53:04.576471 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10780 10:53:04.579678 Device /sys/class/net/enx00e04c722dd6 found
10781 10:53:04.582881 done.
10782 10:53:04.621671 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10783 10:53:04.675027 <4>[ 16.065812] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 10:53:04.794799 <4>[ 16.185436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 10:53:04.910518 <4>[ 16.301359] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 10:53:05.026502 <4>[ 16.417260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 10:53:05.142330 <4>[ 16.533159] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 10:53:05.258764 <4>[ 16.649186] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 10:53:05.374471 <4>[ 16.765090] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 10:53:05.490346 <4>[ 16.881058] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 10:53:05.605940 <4>[ 16.997020] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 10:53:05.621312 <6>[ 17.018564] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10793 10:53:05.713238 <3>[ 17.110897] mt7921e 0000:01:00.0: hardware init failed
10794 10:53:05.730036 IP-Config: no response after 2 secs - giving up
10795 10:53:05.761804 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10796 10:53:06.863382 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10797 10:53:06.869909 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10798 10:53:06.876304 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10799 10:53:06.882749 host : mt8192-asurada-spherion-r0-cbg-1
10800 10:53:06.889679 domain : lava-rack
10801 10:53:06.896039 rootserver: 192.168.201.1 rootpath:
10802 10:53:06.896162 filename :
10803 10:53:06.919757 done.
10804 10:53:06.926193 Begin: Running /scripts/nfs-bottom ... done.
10805 10:53:06.944742 Begin: Running /scripts/init-bottom ... done.
10806 10:53:08.021163 <6>[ 19.418930] NET: Registered PF_INET6 protocol family
10807 10:53:08.028242 <6>[ 19.425743] Segment Routing with IPv6
10808 10:53:08.031535 <6>[ 19.429736] In-situ OAM (IOAM) with IPv6
10809 10:53:08.132379 <30>[ 19.510298] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10810 10:53:08.135378 <30>[ 19.534106] systemd[1]: Detected architecture arm64.
10811 10:53:08.153990
10812 10:53:08.156995 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10813 10:53:08.157074
10814 10:53:08.171842 <30>[ 19.569506] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10815 10:53:08.641304 <30>[ 20.035825] systemd[1]: Queued start job for default target Graphical Interface.
10816 10:53:08.659287 <30>[ 20.057046] systemd[1]: Created slice system-getty.slice.
10817 10:53:08.665904 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10818 10:53:08.683063 <30>[ 20.080533] systemd[1]: Created slice system-modprobe.slice.
10819 10:53:08.689218 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10820 10:53:08.706733 <30>[ 20.104297] systemd[1]: Created slice system-serial\x2dgetty.slice.
10821 10:53:08.716317 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10822 10:53:08.730213 <30>[ 20.128213] systemd[1]: Created slice User and Session Slice.
10823 10:53:08.737050 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10824 10:53:08.757602 <30>[ 20.152250] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10825 10:53:08.767381 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10826 10:53:08.785668 <30>[ 20.180312] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10827 10:53:08.792591 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10828 10:53:08.812541 <30>[ 20.203844] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10829 10:53:08.819384 <30>[ 20.215882] systemd[1]: Reached target Local Encrypted Volumes.
10830 10:53:08.825899 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10831 10:53:08.842279 <30>[ 20.240144] systemd[1]: Reached target Paths.
10832 10:53:08.845928 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10833 10:53:08.862233 <30>[ 20.259821] systemd[1]: Reached target Remote File Systems.
10834 10:53:08.868779 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10835 10:53:08.882256 <30>[ 20.279751] systemd[1]: Reached target Slices.
10836 10:53:08.885462 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10837 10:53:08.902378 <30>[ 20.300003] systemd[1]: Reached target Swap.
10838 10:53:08.905605 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10839 10:53:08.925631 <30>[ 20.320097] systemd[1]: Listening on initctl Compatibility Named Pipe.
10840 10:53:08.932021 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10841 10:53:08.939054 <30>[ 20.335314] systemd[1]: Listening on Journal Audit Socket.
10842 10:53:08.945372 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10843 10:53:08.958850 <30>[ 20.356536] systemd[1]: Listening on Journal Socket (/dev/log).
10844 10:53:08.965196 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10845 10:53:08.982409 <30>[ 20.380106] systemd[1]: Listening on Journal Socket.
10846 10:53:08.988750 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10847 10:53:09.006261 <30>[ 20.400665] systemd[1]: Listening on Network Service Netlink Socket.
10848 10:53:09.012740 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10849 10:53:09.028776 <30>[ 20.426485] systemd[1]: Listening on udev Control Socket.
10850 10:53:09.035294 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10851 10:53:09.050353 <30>[ 20.448066] systemd[1]: Listening on udev Kernel Socket.
10852 10:53:09.056818 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10853 10:53:09.082235 <30>[ 20.480062] systemd[1]: Mounting Huge Pages File System...
10854 10:53:09.088755 Mounting [0;1;39mHuge Pages File System[0m...
10855 10:53:09.104288 <30>[ 20.502098] systemd[1]: Mounting POSIX Message Queue File System...
10856 10:53:09.110835 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10857 10:53:09.128221 <30>[ 20.526015] systemd[1]: Mounting Kernel Debug File System...
10858 10:53:09.134564 Mounting [0;1;39mKernel Debug File System[0m...
10859 10:53:09.153643 <30>[ 20.548151] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10860 10:53:09.205702 <30>[ 20.600294] systemd[1]: Starting Create list of static device nodes for the current kernel...
10861 10:53:09.212323 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10862 10:53:09.232586 <30>[ 20.630425] systemd[1]: Starting Load Kernel Module configfs...
10863 10:53:09.239249 Starting [0;1;39mLoad Kernel Module configfs[0m...
10864 10:53:09.256439 <30>[ 20.654369] systemd[1]: Starting Load Kernel Module drm...
10865 10:53:09.263228 Starting [0;1;39mLoad Kernel Module drm[0m...
10866 10:53:09.280678 <30>[ 20.678509] systemd[1]: Starting Load Kernel Module fuse...
10867 10:53:09.287108 Starting [0;1;39mLoad Kernel Module fuse[0m...
10868 10:53:09.313480 <6>[ 20.711228] fuse: init (API version 7.37)
10869 10:53:09.323305 <30>[ 20.711355] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10870 10:53:09.358736 <30>[ 20.756642] systemd[1]: Starting Journal Service...
10871 10:53:09.362369 Starting [0;1;39mJournal Service[0m...
10872 10:53:09.384252 <30>[ 20.782182] systemd[1]: Starting Load Kernel Modules...
10873 10:53:09.391029 Starting [0;1;39mLoad Kernel Modules[0m...
10874 10:53:09.412186 <30>[ 20.806779] systemd[1]: Starting Remount Root and Kernel File Systems...
10875 10:53:09.418945 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10876 10:53:09.436700 <30>[ 20.834439] systemd[1]: Starting Coldplug All udev Devices...
10877 10:53:09.443018 Starting [0;1;39mColdplug All udev Devices[0m...
10878 10:53:09.460940 <30>[ 20.858709] systemd[1]: Mounted Huge Pages File System.
10879 10:53:09.467455 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10880 10:53:09.482488 <30>[ 20.880366] systemd[1]: Mounted POSIX Message Queue File System.
10881 10:53:09.488786 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10882 10:53:09.509205 <3>[ 20.903776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 10:53:09.516089 <30>[ 20.904180] systemd[1]: Mounted Kernel Debug File System.
10884 10:53:09.522324 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10885 10:53:09.541914 <30>[ 20.936562] systemd[1]: Finished Create list of static device nodes for the current kernel.
10886 10:53:09.551581 <3>[ 20.936871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 10:53:09.558290 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10888 10:53:09.575330 <30>[ 20.973166] systemd[1]: modprobe@configfs.service: Succeeded.
10889 10:53:09.582306 <30>[ 20.979841] systemd[1]: Finished Load Kernel Module configfs.
10890 10:53:09.598743 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configf<3>[ 20.990760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 10:53:09.598831 s[0m.
10892 10:53:09.615061 <30>[ 21.012741] systemd[1]: modprobe@drm.service: Succeeded.
10893 10:53:09.621735 <30>[ 21.018990] systemd[1]: Finished Load Kernel Module drm.
10894 10:53:09.631622 <3>[ 21.020613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 10:53:09.638300 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10896 10:53:09.651415 <30>[ 21.048649] systemd[1]: modprobe@fuse.service: Succeeded.
10897 10:53:09.657906 <30>[ 21.054960] systemd[1]: Finished Load Kernel Module fuse.
10898 10:53:09.667903 <3>[ 21.057504] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 10:53:09.674271 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10900 10:53:09.687607 <30>[ 21.084903] systemd[1]: Finished Load Kernel Modules.
10901 10:53:09.697781 <3>[ 21.090487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 10:53:09.700853 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10903 10:53:09.719352 <30>[ 21.117084] systemd[1]: Finished Remount Root and Kernel File Systems.
10904 10:53:09.729491 <3>[ 21.121166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 10:53:09.736434 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10906 10:53:09.759823 <3>[ 21.154582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 10:53:09.782750 <30>[ 21.180055] systemd[1]: Mounting FUSE Control File System...
10908 10:53:09.792468 <3>[ 21.186727] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 10:53:09.799135 Mounting [0;1;39mFUSE Control File System[0m...
10910 10:53:09.816775 <30>[ 21.214512] systemd[1]: Mounting Kernel Configuration File System...
10911 10:53:09.826916 <3>[ 21.217072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 10:53:09.833362 Mounting [0;1;39mKernel Configuration File System[0m...
10913 10:53:09.856747 <30>[ 21.251333] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10914 10:53:09.866831 <30>[ 21.260453] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10915 10:53:09.894223 <30>[ 21.292255] systemd[1]: Starting Load/Save Random Seed...
10916 10:53:09.900788 Starting [0;1;39mLoad/Save Random Seed[0m...
10917 10:53:09.917483 <30>[ 21.315259] systemd[1]: Starting Apply Kernel Variables...
10918 10:53:09.924225 Starting [0;1;39mApply Kernel Variables[0m...
10919 10:53:09.941456 <30>[ 21.339450] systemd[1]: Starting Create System Users...
10920 10:53:09.947873 Starting [0;1;39mCreate System Users[0m...
10921 10:53:09.964108 <30>[ 21.362142] systemd[1]: Started Journal Service.
10922 10:53:09.971001 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10923 10:53:09.988029 <4>[ 21.374791] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10924 10:53:09.994505 <3>[ 21.390479] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10925 10:53:10.000762 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10926 10:53:10.019492 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10927 10:53:10.038805 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10928 10:53:10.050255 See 'systemctl status systemd-udev-trigger.service' for details.
10929 10:53:10.066881 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10930 10:53:10.082850 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10931 10:53:10.098910 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10932 10:53:10.142906 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10933 10:53:10.165281 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10934 10:53:10.184369 <46>[ 21.579085] systemd-journald[294]: Received client request to flush runtime journal.
10935 10:53:10.940769 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10936 10:53:10.958143 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10937 10:53:10.973631 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10938 10:53:11.025248 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10939 10:53:11.565267 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10940 10:53:11.606388 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10941 10:53:11.626320 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10942 10:53:11.649493 Starting [0;1;39mNetwork Service[0m...
10943 10:53:11.968336 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10944 10:53:11.988667 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10945 10:53:12.046148 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10946 10:53:12.191930 <6>[ 23.589773] remoteproc remoteproc0: powering up scp
10947 10:53:12.218005 <4>[ 23.612710] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10948 10:53:12.224502 <3>[ 23.622609] remoteproc remoteproc0: request_firmware failed: -2
10949 10:53:12.233960 <3>[ 23.628808] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10950 10:53:12.346634 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10951 10:53:12.366545 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10952 10:53:12.390028 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10953 10:53:12.474575 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10954 10:53:12.493137 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10955 10:53:12.534071 Starting [0;1;39mNetwork Name Resolution[0m...
10956 10:53:12.562464 Starting [0;1;39mNetwork Time Synchronization[0m...
10957 10:53:12.580381 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10958 10:53:12.601828 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10959 10:53:12.631219 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10960 10:53:12.650404 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10961 10:53:12.759486 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10962 10:53:12.777872 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10963 10:53:12.800877 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 10:53:12.817620 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10965 10:53:12.837809 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10966 10:53:12.987532 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10967 10:53:13.039412 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10968 10:53:13.072189 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10969 10:53:13.100212 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 10:53:13.113677 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 10:53:13.136255 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 10:53:13.153474 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10973 10:53:13.173713 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10974 10:53:13.218118 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10975 10:53:13.285990 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10976 10:53:13.333751 Starting [0;1;39mUser Login Management[0m...
10977 10:53:13.350490 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10978 10:53:13.366381 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10979 10:53:13.385215 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10980 10:53:13.422422 Starting [0;1;39mPermit User Sessions[0m...
10981 10:53:13.575878 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10982 10:53:13.595899 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10983 10:53:13.634536 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10984 10:53:13.656664 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10985 10:53:13.678142 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10986 10:53:13.695536 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10987 10:53:13.702374 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10988 10:53:13.717806 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10989 10:53:13.766626 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10990 10:53:13.833493 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10991 10:53:13.901437
10992 10:53:13.901546
10993 10:53:13.904524 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10994 10:53:13.904610
10995 10:53:13.907789 debian-bullseye-arm64 login: root (automatic login)
10996 10:53:13.907871
10997 10:53:13.907980
10998 10:53:14.195236 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
10999 10:53:14.195391
11000 10:53:14.201554 The programs included with the Debian GNU/Linux system are free software;
11001 10:53:14.208269 the exact distribution terms for each program are described in the
11002 10:53:14.211579 individual files in /usr/share/doc/*/copyright.
11003 10:53:14.211658
11004 10:53:14.218033 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11005 10:53:14.221717 permitted by applicable law.
11006 10:53:14.933133 Matched prompt #10: / #
11008 10:53:14.933523 Setting prompt string to ['/ #']
11009 10:53:14.933647 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11011 10:53:14.933945 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11012 10:53:14.934067 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
11013 10:53:14.934166 Setting prompt string to ['/ #']
11014 10:53:14.934255 Forcing a shell prompt, looking for ['/ #']
11016 10:53:14.984537 / #
11017 10:53:14.984690 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 10:53:14.984812 Waiting using forced prompt support (timeout 00:02:30)
11019 10:53:14.989521
11020 10:53:14.989797 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11021 10:53:14.989892 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11023 10:53:15.090230 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8'
11024 10:53:15.095416 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10590964/extract-nfsrootfs-w76pvth8'
11026 10:53:15.195928 / # export NFS_SERVER_IP='192.168.201.1'
11027 10:53:15.201367 export NFS_SERVER_IP='192.168.201.1'
11028 10:53:15.201649 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 10:53:15.201748 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11030 10:53:15.201842 end: 2 depthcharge-action (duration 00:01:28) [common]
11031 10:53:15.201931 start: 3 lava-test-retry (timeout 00:07:47) [common]
11032 10:53:15.202019 start: 3.1 lava-test-shell (timeout 00:07:47) [common]
11033 10:53:15.202095 Using namespace: common
11035 10:53:15.302421 / # #
11036 10:53:15.302533 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11037 10:53:15.307080 #
11038 10:53:15.307347 Using /lava-10590964
11040 10:53:15.407644 / # export SHELL=/bin/bash
11041 10:53:15.412622 export SHELL=/bin/bash
11043 10:53:15.513131 / # . /lava-10590964/environment
11044 10:53:15.518564 . /lava-10590964/environment
11046 10:53:15.623554 / # /lava-10590964/bin/lava-test-runner /lava-10590964/0
11047 10:53:15.623663 Test shell timeout: 10s (minimum of the action and connection timeout)
11048 10:53:15.628737 /lava-10590964/bin/lava-test-runner /lava-10590964/0
11049 10:53:15.828670 + export TESTRUN_ID=0_timesync-off
11050 10:53:15.832029 + TESTRUN_ID=0_timesync-off
11051 10:53:15.835226 + cd /lava-10590964/0/tests/0_timesync-off
11052 10:53:15.838710 ++ cat uuid
11053 10:53:15.838795 + UUID=10590964_1.6.2.3.1
11054 10:53:15.841779 + set +x
11055 10:53:15.845147 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10590964_1.6.2.3.1>
11056 10:53:15.845409 Received signal: <STARTRUN> 0_timesync-off 10590964_1.6.2.3.1
11057 10:53:15.845483 Starting test lava.0_timesync-off (10590964_1.6.2.3.1)
11058 10:53:15.845568 Skipping test definition patterns.
11059 10:53:15.848621 + systemctl stop systemd-timesyncd
11060 10:53:15.870582 + set +x
11061 10:53:15.874001 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10590964_1.6.2.3.1>
11062 10:53:15.874256 Received signal: <ENDRUN> 0_timesync-off 10590964_1.6.2.3.1
11063 10:53:15.874340 Ending use of test pattern.
11064 10:53:15.874404 Ending test lava.0_timesync-off (10590964_1.6.2.3.1), duration 0.03
11066 10:53:15.912751 + export TESTRUN_ID=1_kselftest-tpm2
11067 10:53:15.916030 + TESTRUN_ID=1_kselftest-tpm2
11068 10:53:15.922719 + cd /lava-10590964/0/tests/1_kselftest-tpm2
11069 10:53:15.922804 ++ cat uuid
11070 10:53:15.926138 + UUID=10590964_1.6.2.3.5
11071 10:53:15.926259 + set +x
11072 10:53:15.929110 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10590964_1.6.2.3.5>
11073 10:53:15.929359 Received signal: <STARTRUN> 1_kselftest-tpm2 10590964_1.6.2.3.5
11074 10:53:15.929428 Starting test lava.1_kselftest-tpm2 (10590964_1.6.2.3.5)
11075 10:53:15.929507 Skipping test definition patterns.
11076 10:53:15.932430 + cd ./automated/linux/kselftest/
11077 10:53:15.961885 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11078 10:53:15.968855 INFO: install_deps skipped
11079 10:53:16.069004 --2023-06-05 10:53:13-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11080 10:53:16.081373 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11081 10:53:16.225529 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11082 10:53:16.369764 HTTP request sent, awaiting response... 200 OK
11083 10:53:16.372852 Length: 2712696 (2.6M) [application/octet-stream]
11084 10:53:16.376098 Saving to: 'kselftest.tar.xz'
11085 10:53:16.376180
11086 10:53:16.376260
11087 10:53:16.657289 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11088 10:53:16.946690 kselftest.tar.xz 1%[ ] 44.98K 159KB/s
11089 10:53:17.282368 kselftest.tar.xz 8%[> ] 216.08K 380KB/s
11090 10:53:17.585681 kselftest.tar.xz 31%[=====> ] 822.71K 913KB/s
11091 10:53:17.681590 kselftest.tar.xz 60%[===========> ] 1.57M 1.31MB/s
11092 10:53:17.688023 kselftest.tar.xz 100%[===================>] 2.59M 2.00MB/s in 1.3s
11093 10:53:17.688117
11094 10:53:17.921881 2023-06-05 10:53:15 (2.00 MB/s) - 'kselftest.tar.xz' saved [2712696/2712696]
11095 10:53:17.922037
11096 10:53:22.308710 skiplist:
11097 10:53:22.311941 ========================================
11098 10:53:22.315142 ========================================
11099 10:53:22.349332 tpm2:test_smoke.sh
11100 10:53:22.352521 tpm2:test_space.sh
11101 10:53:22.365943 ============== Tests to run ===============
11102 10:53:22.366026 tpm2:test_smoke.sh
11103 10:53:22.369124 tpm2:test_space.sh
11104 10:53:22.372511 ===========End Tests to run ===============
11105 10:53:22.450740 <12>[ 33.849957] kselftest: Running tests in tpm2
11106 10:53:22.458467 TAP version 13
11107 10:53:22.470344 1..2
11108 10:53:22.495420 # selftests: tpm2: test_smoke.sh
11109 10:53:23.612653 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11110 10:53:23.615917 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11111 10:53:23.622481 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11112 10:53:23.625734 # Traceback (most recent call last):
11113 10:53:23.635572 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11114 10:53:23.639030 # if self.tpm:
11115 10:53:23.642410 # AttributeError: 'Client' object has no attribute 'tpm'
11116 10:53:23.645612 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11117 10:53:23.652101 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11118 10:53:23.655916 # Traceback (most recent call last):
11119 10:53:23.665682 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11120 10:53:23.668853 # if self.tpm:
11121 10:53:23.672304 # AttributeError: 'Client' object has no attribute 'tpm'
11122 10:53:23.678918 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11123 10:53:23.685224 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11124 10:53:23.688916 # Traceback (most recent call last):
11125 10:53:23.699041 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11126 10:53:23.699124 # if self.tpm:
11127 10:53:23.705358 # AttributeError: 'Client' object has no attribute 'tpm'
11128 10:53:23.709152 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11129 10:53:23.715380 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11130 10:53:23.718635 # Traceback (most recent call last):
11131 10:53:23.728874 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11132 10:53:23.732083 # if self.tpm:
11133 10:53:23.735221 # AttributeError: 'Client' object has no attribute 'tpm'
11134 10:53:23.741742 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11135 10:53:23.745378 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11136 10:53:23.748630 # Traceback (most recent call last):
11137 10:53:23.758456 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11138 10:53:23.761853 # if self.tpm:
11139 10:53:23.764965 # AttributeError: 'Client' object has no attribute 'tpm'
11140 10:53:23.771908 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11141 10:53:23.778163 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11142 10:53:23.781526 # Traceback (most recent call last):
11143 10:53:23.791675 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11144 10:53:23.791759 # if self.tpm:
11145 10:53:23.798385 # AttributeError: 'Client' object has no attribute 'tpm'
11146 10:53:23.801852 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11147 10:53:23.808384 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11148 10:53:23.811657 # Traceback (most recent call last):
11149 10:53:23.821419 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11150 10:53:23.824498 # if self.tpm:
11151 10:53:23.828247 # AttributeError: 'Client' object has no attribute 'tpm'
11152 10:53:23.834555 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11153 10:53:23.841179 # Exception ignored in: <function Client.__del__ at 0xffffa441bd30>
11154 10:53:23.844904 # Traceback (most recent call last):
11155 10:53:23.854707 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11156 10:53:23.854790 # if self.tpm:
11157 10:53:23.861362 # AttributeError: 'Client' object has no attribute 'tpm'
11158 10:53:23.861445 #
11159 10:53:23.867784 # ======================================================================
11160 10:53:23.871426 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11161 10:53:23.877976 # ----------------------------------------------------------------------
11162 10:53:23.881500 # Traceback (most recent call last):
11163 10:53:23.891334 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11164 10:53:23.898159 # self.root_key = self.client.create_root_key()
11165 10:53:23.907983 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11166 10:53:23.911305 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11167 10:53:23.921120 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11168 10:53:23.924375 # raise ProtocolError(cc, rc)
11169 10:53:23.930979 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11170 10:53:23.931062 #
11171 10:53:23.937835 # ======================================================================
11172 10:53:23.944246 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11173 10:53:23.951044 # ----------------------------------------------------------------------
11174 10:53:23.954351 # Traceback (most recent call last):
11175 10:53:23.964194 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11176 10:53:23.967457 # self.client = tpm2.Client()
11177 10:53:23.977539 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11178 10:53:23.980985 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11179 10:53:23.987548 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11180 10:53:23.987633 #
11181 10:53:23.994153 # ======================================================================
11182 10:53:23.997399 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11183 10:53:24.003879 # ----------------------------------------------------------------------
11184 10:53:24.007268 # Traceback (most recent call last):
11185 10:53:24.017370 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11186 10:53:24.020626 # self.client = tpm2.Client()
11187 10:53:24.030774 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11188 10:53:24.033698 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11189 10:53:24.040755 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11190 10:53:24.040848 #
11191 10:53:24.047173 # ======================================================================
11192 10:53:24.050535 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11193 10:53:24.057157 # ----------------------------------------------------------------------
11194 10:53:24.060412 # Traceback (most recent call last):
11195 10:53:24.070523 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11196 10:53:24.073834 # self.client = tpm2.Client()
11197 10:53:24.083799 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11198 10:53:24.090235 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11199 10:53:24.093691 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11200 10:53:24.093774 #
11201 10:53:24.100159 # ======================================================================
11202 10:53:24.106781 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11203 10:53:24.113303 # ----------------------------------------------------------------------
11204 10:53:24.116519 # Traceback (most recent call last):
11205 10:53:24.126902 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11206 10:53:24.130179 # self.client = tpm2.Client()
11207 10:53:24.139804 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11208 10:53:24.143483 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11209 10:53:24.149725 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11210 10:53:24.149809 #
11211 10:53:24.156654 # ======================================================================
11212 10:53:24.159858 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11213 10:53:24.166558 # ----------------------------------------------------------------------
11214 10:53:24.170121 # Traceback (most recent call last):
11215 10:53:24.180713 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11216 10:53:24.184411 # self.client = tpm2.Client()
11217 10:53:24.194400 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11218 10:53:24.197632 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11219 10:53:24.204213 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11220 10:53:24.204297 #
11221 10:53:24.214028 # ======================================================================
11222 10:53:24.214113 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11223 10:53:24.220809 # ----------------------------------------------------------------------
11224 10:53:24.224214 # Traceback (most recent call last):
11225 10:53:24.233840 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11226 10:53:24.237172 # self.client = tpm2.Client()
11227 10:53:24.246958 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11228 10:53:24.253852 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11229 10:53:24.257023 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11230 10:53:24.257108 #
11231 10:53:24.263349 # ======================================================================
11232 10:53:24.270274 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11233 10:53:24.276879 # ----------------------------------------------------------------------
11234 10:53:24.279921 # Traceback (most recent call last):
11235 10:53:24.290182 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11236 10:53:24.293486 # self.client = tpm2.Client()
11237 10:53:24.303179 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11238 10:53:24.306447 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11239 10:53:24.313291 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11240 10:53:24.313373 #
11241 10:53:24.319882 # ======================================================================
11242 10:53:24.326252 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11243 10:53:24.332946 # ----------------------------------------------------------------------
11244 10:53:24.336415 # Traceback (most recent call last):
11245 10:53:24.345955 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11246 10:53:24.349524 # self.client = tpm2.Client()
11247 10:53:24.359184 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11248 10:53:24.363038 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11249 10:53:24.369009 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11250 10:53:24.369093 #
11251 10:53:24.375923 # ----------------------------------------------------------------------
11252 10:53:24.376007 # Ran 9 tests in 0.028s
11253 10:53:24.376087 #
11254 10:53:24.379274 # FAILED (errors=9)
11255 10:53:24.382443 # test_async (tpm2_tests.AsyncTest) ... ok
11256 10:53:24.389182 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11257 10:53:24.389260 #
11258 10:53:24.395629 # ----------------------------------------------------------------------
11259 10:53:24.395705 # Ran 2 tests in 0.031s
11260 10:53:24.395792 #
11261 10:53:24.398963 # OK
11262 10:53:24.402111 ok 1 selftests: tpm2: test_smoke.sh
11263 10:53:24.402190 # selftests: tpm2: test_space.sh
11264 10:53:24.408857 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11265 10:53:24.412494 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11266 10:53:24.418917 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11267 10:53:24.421946 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11268 10:53:24.422021 #
11269 10:53:24.428746 # ======================================================================
11270 10:53:24.435191 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11271 10:53:24.442308 # ----------------------------------------------------------------------
11272 10:53:24.445243 # Traceback (most recent call last):
11273 10:53:24.455241 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11274 10:53:24.458685 # root1 = space1.create_root_key()
11275 10:53:24.468501 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11276 10:53:24.475230 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11277 10:53:24.484842 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11278 10:53:24.488121 # raise ProtocolError(cc, rc)
11279 10:53:24.494713 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11280 10:53:24.494796 #
11281 10:53:24.501606 # ======================================================================
11282 10:53:24.504728 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11283 10:53:24.511534 # ----------------------------------------------------------------------
11284 10:53:24.514813 # Traceback (most recent call last):
11285 10:53:24.524854 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11286 10:53:24.527726 # space1.create_root_key()
11287 10:53:24.538036 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11288 10:53:24.544541 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11289 10:53:24.554342 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11290 10:53:24.557981 # raise ProtocolError(cc, rc)
11291 10:53:24.564218 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11292 10:53:24.564307 #
11293 10:53:24.570981 # ======================================================================
11294 10:53:24.574103 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11295 10:53:24.580845 # ----------------------------------------------------------------------
11296 10:53:24.584157 # Traceback (most recent call last):
11297 10:53:24.594349 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11298 10:53:24.597154 # root1 = space1.create_root_key()
11299 10:53:24.607357 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11300 10:53:24.613680 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11301 10:53:24.624013 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11302 10:53:24.626905 # raise ProtocolError(cc, rc)
11303 10:53:24.633703 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11304 10:53:24.633822 #
11305 10:53:24.639982 # ======================================================================
11306 10:53:24.643374 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11307 10:53:24.650274 # ----------------------------------------------------------------------
11308 10:53:24.653445 # Traceback (most recent call last):
11309 10:53:24.666786 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11310 10:53:24.669931 # root1 = space1.create_root_key()
11311 10:53:24.679826 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11312 10:53:24.686662 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11313 10:53:24.696492 # File "/lava-10590964/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11314 10:53:24.699537 # raise ProtocolError(cc, rc)
11315 10:53:24.702885 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11316 10:53:24.706127 #
11317 10:53:24.709767 # ----------------------------------------------------------------------
11318 10:53:24.712990 # Ran 4 tests in 0.076s
11319 10:53:24.713072 #
11320 10:53:24.716271 # FAILED (errors=4)
11321 10:53:24.719633 not ok 2 selftests: tpm2: test_space.sh # exit=1
11322 10:53:24.722840 tpm2_test_smoke_sh pass
11323 10:53:24.722928 tpm2_test_space_sh fail
11324 10:53:24.735416 + ../../utils/send-to-lava.sh ./output/result.txt
11325 10:53:24.783167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11326 10:53:24.783450 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11328 10:53:24.814149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11329 10:53:24.814403 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11331 10:53:24.817355 + set +x
11332 10:53:24.820939 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10590964_1.6.2.3.5>
11333 10:53:24.821210 Received signal: <ENDRUN> 1_kselftest-tpm2 10590964_1.6.2.3.5
11334 10:53:24.821285 Ending use of test pattern.
11335 10:53:24.821350 Ending test lava.1_kselftest-tpm2 (10590964_1.6.2.3.5), duration 8.89
11337 10:53:24.823860 <LAVA_TEST_RUNNER EXIT>
11338 10:53:24.824110 ok: lava_test_shell seems to have completed
11339 10:53:24.824211 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11340 10:53:24.824300 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11341 10:53:24.824384 end: 3 lava-test-retry (duration 00:00:10) [common]
11342 10:53:24.824475 start: 4 finalize (timeout 00:07:37) [common]
11343 10:53:24.824564 start: 4.1 power-off (timeout 00:00:30) [common]
11344 10:53:24.824718 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11345 10:53:24.902737 >> Command sent successfully.
11346 10:53:24.905022 Returned 0 in 0 seconds
11347 10:53:25.005398 end: 4.1 power-off (duration 00:00:00) [common]
11349 10:53:25.005708 start: 4.2 read-feedback (timeout 00:07:37) [common]
11350 10:53:25.005957 Listened to connection for namespace 'common' for up to 1s
11351 10:53:26.006922 Finalising connection for namespace 'common'
11352 10:53:26.007095 Disconnecting from shell: Finalise
11353 10:53:26.007175 / #
11354 10:53:26.107499 end: 4.2 read-feedback (duration 00:00:01) [common]
11355 10:53:26.107679 end: 4 finalize (duration 00:00:01) [common]
11356 10:53:26.107795 Cleaning after the job
11357 10:53:26.107892 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/ramdisk
11358 10:53:26.110116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/kernel
11359 10:53:26.118603 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/dtb
11360 10:53:26.118791 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/nfsrootfs
11361 10:53:26.181074 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590964/tftp-deploy-yzu6itfl/modules
11362 10:53:26.186155 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10590964
11363 10:53:26.694844 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10590964
11364 10:53:26.695027 Job finished correctly