Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 37
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 23
1 10:57:00.593432 lava-dispatcher, installed at version: 2023.05.1
2 10:57:00.593635 start: 0 validate
3 10:57:00.593762 Start time: 2023-06-05 10:57:00.593755+00:00 (UTC)
4 10:57:00.593884 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:57:00.594014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:57:00.890861 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:57:00.891604 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:57:01.186958 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:57:01.187673 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:57:01.481902 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:57:01.482607 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:57:01.773016 validate duration: 1.18
14 10:57:01.773273 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:57:01.773392 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:57:01.773509 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:57:01.773674 Not decompressing ramdisk as can be used compressed.
18 10:57:01.773760 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 10:57:01.773823 saving as /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/ramdisk/rootfs.cpio.gz
20 10:57:01.773883 total size: 84903995 (80MB)
21 10:57:01.776696 progress 0% (0MB)
22 10:57:01.798137 progress 5% (4MB)
23 10:57:01.819871 progress 10% (8MB)
24 10:57:01.840996 progress 15% (12MB)
25 10:57:01.862142 progress 20% (16MB)
26 10:57:01.882971 progress 25% (20MB)
27 10:57:01.904203 progress 30% (24MB)
28 10:57:01.925409 progress 35% (28MB)
29 10:57:01.946684 progress 40% (32MB)
30 10:57:01.967628 progress 45% (36MB)
31 10:57:01.988550 progress 50% (40MB)
32 10:57:02.009997 progress 55% (44MB)
33 10:57:02.031219 progress 60% (48MB)
34 10:57:02.052506 progress 65% (52MB)
35 10:57:02.073254 progress 70% (56MB)
36 10:57:02.094144 progress 75% (60MB)
37 10:57:02.115501 progress 80% (64MB)
38 10:57:02.137171 progress 85% (68MB)
39 10:57:02.158326 progress 90% (72MB)
40 10:57:02.179634 progress 95% (76MB)
41 10:57:02.200407 progress 100% (80MB)
42 10:57:02.200568 80MB downloaded in 0.43s (189.77MB/s)
43 10:57:02.200737 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:57:02.200979 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:57:02.201065 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:57:02.201148 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:57:02.201284 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:57:02.201357 saving as /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/kernel/Image
50 10:57:02.201417 total size: 45746688 (43MB)
51 10:57:02.201477 No compression specified
52 10:57:02.202608 progress 0% (0MB)
53 10:57:02.214125 progress 5% (2MB)
54 10:57:02.225584 progress 10% (4MB)
55 10:57:02.237075 progress 15% (6MB)
56 10:57:02.248814 progress 20% (8MB)
57 10:57:02.260306 progress 25% (10MB)
58 10:57:02.271501 progress 30% (13MB)
59 10:57:02.282754 progress 35% (15MB)
60 10:57:02.294131 progress 40% (17MB)
61 10:57:02.305442 progress 45% (19MB)
62 10:57:02.317083 progress 50% (21MB)
63 10:57:02.328436 progress 55% (24MB)
64 10:57:02.340009 progress 60% (26MB)
65 10:57:02.351666 progress 65% (28MB)
66 10:57:02.363130 progress 70% (30MB)
67 10:57:02.374498 progress 75% (32MB)
68 10:57:02.385645 progress 80% (34MB)
69 10:57:02.396960 progress 85% (37MB)
70 10:57:02.408202 progress 90% (39MB)
71 10:57:02.419601 progress 95% (41MB)
72 10:57:02.430876 progress 100% (43MB)
73 10:57:02.431018 43MB downloaded in 0.23s (190.02MB/s)
74 10:57:02.431171 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:57:02.431417 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:57:02.431504 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:57:02.431588 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:57:02.431728 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:57:02.431802 saving as /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/dtb/mt8192-asurada-spherion-r0.dtb
81 10:57:02.431865 total size: 46924 (0MB)
82 10:57:02.431923 No compression specified
83 10:57:02.433136 progress 69% (0MB)
84 10:57:02.433411 progress 100% (0MB)
85 10:57:02.433572 0MB downloaded in 0.00s (26.24MB/s)
86 10:57:02.433695 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:57:02.433913 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:57:02.433996 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:57:02.434077 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:57:02.434185 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:57:02.434251 saving as /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/modules/modules.tar
93 10:57:02.434310 total size: 8542412 (8MB)
94 10:57:02.434368 Using unxz to decompress xz
95 10:57:02.437975 progress 0% (0MB)
96 10:57:02.459385 progress 5% (0MB)
97 10:57:02.483951 progress 10% (0MB)
98 10:57:02.509517 progress 15% (1MB)
99 10:57:02.534141 progress 20% (1MB)
100 10:57:02.559657 progress 25% (2MB)
101 10:57:02.584219 progress 30% (2MB)
102 10:57:02.608955 progress 35% (2MB)
103 10:57:02.633376 progress 40% (3MB)
104 10:57:02.658497 progress 45% (3MB)
105 10:57:02.682022 progress 50% (4MB)
106 10:57:02.704413 progress 55% (4MB)
107 10:57:02.728931 progress 60% (4MB)
108 10:57:02.753941 progress 65% (5MB)
109 10:57:02.778929 progress 70% (5MB)
110 10:57:02.805057 progress 75% (6MB)
111 10:57:02.833657 progress 80% (6MB)
112 10:57:02.855771 progress 85% (6MB)
113 10:57:02.880509 progress 90% (7MB)
114 10:57:02.903388 progress 95% (7MB)
115 10:57:02.926597 progress 100% (8MB)
116 10:57:02.932195 8MB downloaded in 0.50s (16.36MB/s)
117 10:57:02.932479 end: 1.4.1 http-download (duration 00:00:00) [common]
119 10:57:02.932736 end: 1.4 download-retry (duration 00:00:00) [common]
120 10:57:02.932864 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:57:02.932964 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:57:02.933094 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:57:02.933187 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:57:02.933410 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks
125 10:57:02.933536 makedir: /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin
126 10:57:02.933637 makedir: /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/tests
127 10:57:02.933732 makedir: /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/results
128 10:57:02.933840 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-add-keys
129 10:57:02.933987 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-add-sources
130 10:57:02.934131 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-background-process-start
131 10:57:02.934260 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-background-process-stop
132 10:57:02.934383 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-common-functions
133 10:57:02.934503 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-echo-ipv4
134 10:57:02.934623 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-install-packages
135 10:57:02.934741 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-installed-packages
136 10:57:02.934857 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-os-build
137 10:57:02.934974 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-probe-channel
138 10:57:02.935091 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-probe-ip
139 10:57:02.935208 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-target-ip
140 10:57:02.935325 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-target-mac
141 10:57:02.935442 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-target-storage
142 10:57:02.935563 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-case
143 10:57:02.935681 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-event
144 10:57:02.935797 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-feedback
145 10:57:02.935914 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-raise
146 10:57:02.936038 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-reference
147 10:57:02.936168 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-runner
148 10:57:02.936287 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-set
149 10:57:02.936405 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-test-shell
150 10:57:02.936525 Updating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-install-packages (oe)
151 10:57:02.936672 Updating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/bin/lava-installed-packages (oe)
152 10:57:02.936835 Creating /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/environment
153 10:57:02.936931 LAVA metadata
154 10:57:02.937004 - LAVA_JOB_ID=10591025
155 10:57:02.937073 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:57:02.937176 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:57:02.937241 skipped lava-vland-overlay
158 10:57:02.937316 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:57:02.937394 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:57:02.937455 skipped lava-multinode-overlay
161 10:57:02.937526 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:57:02.937611 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:57:02.937686 Loading test definitions
164 10:57:02.937777 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 10:57:02.937849 Using /lava-10591025 at stage 0
166 10:57:02.937943 Fetching tests from https://github.com/kernelci/kernelci-core
167 10:57:02.938027 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/0/tests/0_sleep'
168 10:57:03.592501 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/0/tests/0_sleep
169 10:57:03.593682 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 10:57:03.594057 uuid=10591025_1.5.2.3.1 testdef=None
171 10:57:03.594201 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 10:57:03.594443 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 10:57:03.595065 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 10:57:03.595293 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 10:57:03.595980 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 10:57:03.596207 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 10:57:03.596896 runner path: /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/0/tests/0_sleep test_uuid 10591025_1.5.2.3.1
181 10:57:03.596981 sleep_params='mem freeze'
182 10:57:03.597118 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 10:57:03.597326 Creating lava-test-runner.conf files
185 10:57:03.597388 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591025/lava-overlay-bf76cwks/lava-10591025/0 for stage 0
186 10:57:03.597475 - 0_sleep
187 10:57:03.597575 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 10:57:03.597659 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 10:57:03.714454 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 10:57:03.714615 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 10:57:03.714707 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 10:57:03.714807 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 10:57:03.714896 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 10:57:05.982955 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 10:57:05.983299 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 10:57:05.983408 extracting modules file /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591025/extract-overlay-ramdisk-4aoaoarp/ramdisk
197 10:57:06.194535 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 10:57:06.194705 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
199 10:57:06.194802 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591025/compress-overlay-hi7mpf4x/overlay-1.5.2.4.tar.gz to ramdisk
200 10:57:06.194874 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591025/compress-overlay-hi7mpf4x/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591025/extract-overlay-ramdisk-4aoaoarp/ramdisk
201 10:57:06.283459 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 10:57:06.283613 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 10:57:06.283708 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 10:57:06.283796 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 10:57:06.283877 Building ramdisk /var/lib/lava/dispatcher/tmp/10591025/extract-overlay-ramdisk-4aoaoarp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591025/extract-overlay-ramdisk-4aoaoarp/ramdisk
206 10:57:07.693974 >> 561590 blocks
207 10:57:17.264738 rename /var/lib/lava/dispatcher/tmp/10591025/extract-overlay-ramdisk-4aoaoarp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/ramdisk/ramdisk.cpio.gz
208 10:57:17.265209 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 10:57:17.265344 start: 1.5.8 prepare-kernel (timeout 00:09:45) [common]
210 10:57:17.265461 start: 1.5.8.1 prepare-fit (timeout 00:09:45) [common]
211 10:57:17.265582 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/kernel/Image'
212 10:57:28.690114 Returned 0 in 11 seconds
213 10:57:28.791117 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/kernel/image.itb
214 10:57:30.013306 output: FIT description: Kernel Image image with one or more FDT blobs
215 10:57:30.013650 output: Created: Mon Jun 5 11:57:29 2023
216 10:57:30.013727 output: Image 0 (kernel-1)
217 10:57:30.013792 output: Description:
218 10:57:30.013852 output: Created: Mon Jun 5 11:57:29 2023
219 10:57:30.013910 output: Type: Kernel Image
220 10:57:30.013969 output: Compression: lzma compressed
221 10:57:30.014027 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
222 10:57:30.014082 output: Architecture: AArch64
223 10:57:30.014138 output: OS: Linux
224 10:57:30.014193 output: Load Address: 0x00000000
225 10:57:30.014250 output: Entry Point: 0x00000000
226 10:57:30.014303 output: Hash algo: crc32
227 10:57:30.014354 output: Hash value: 8ce42972
228 10:57:30.014404 output: Image 1 (fdt-1)
229 10:57:30.014455 output: Description: mt8192-asurada-spherion-r0
230 10:57:30.014506 output: Created: Mon Jun 5 11:57:29 2023
231 10:57:30.014556 output: Type: Flat Device Tree
232 10:57:30.014607 output: Compression: uncompressed
233 10:57:30.014658 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 10:57:30.014709 output: Architecture: AArch64
235 10:57:30.014759 output: Hash algo: crc32
236 10:57:30.014810 output: Hash value: 1df858fa
237 10:57:30.014860 output: Image 2 (ramdisk-1)
238 10:57:30.014911 output: Description: unavailable
239 10:57:30.014961 output: Created: Mon Jun 5 11:57:29 2023
240 10:57:30.015012 output: Type: RAMDisk Image
241 10:57:30.015063 output: Compression: Unknown Compression
242 10:57:30.015113 output: Data Size: 98154484 Bytes = 95853.99 KiB = 93.61 MiB
243 10:57:30.015164 output: Architecture: AArch64
244 10:57:30.015214 output: OS: Linux
245 10:57:30.015264 output: Load Address: unavailable
246 10:57:30.015315 output: Entry Point: unavailable
247 10:57:30.015365 output: Hash algo: crc32
248 10:57:30.015415 output: Hash value: 3687bb79
249 10:57:30.015465 output: Default Configuration: 'conf-1'
250 10:57:30.015516 output: Configuration 0 (conf-1)
251 10:57:30.015566 output: Description: mt8192-asurada-spherion-r0
252 10:57:30.015617 output: Kernel: kernel-1
253 10:57:30.015666 output: Init Ramdisk: ramdisk-1
254 10:57:30.015716 output: FDT: fdt-1
255 10:57:30.015767 output: Loadables: kernel-1
256 10:57:30.015817 output:
257 10:57:30.016003 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 10:57:30.016095 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 10:57:30.016195 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
260 10:57:30.016283 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:32) [common]
261 10:57:30.016360 No LXC device requested
262 10:57:30.016435 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 10:57:30.016520 start: 1.7 deploy-device-env (timeout 00:09:32) [common]
264 10:57:30.016596 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 10:57:30.016661 Checking files for TFTP limit of 4294967296 bytes.
266 10:57:30.017176 end: 1 tftp-deploy (duration 00:00:28) [common]
267 10:57:30.017279 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 10:57:30.017370 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 10:57:30.017485 substitutions:
270 10:57:30.017551 - {DTB}: 10591025/tftp-deploy-op8g5veo/dtb/mt8192-asurada-spherion-r0.dtb
271 10:57:30.017614 - {INITRD}: 10591025/tftp-deploy-op8g5veo/ramdisk/ramdisk.cpio.gz
272 10:57:30.017671 - {KERNEL}: 10591025/tftp-deploy-op8g5veo/kernel/Image
273 10:57:30.017727 - {LAVA_MAC}: None
274 10:57:30.017781 - {PRESEED_CONFIG}: None
275 10:57:30.017835 - {PRESEED_LOCAL}: None
276 10:57:30.017888 - {RAMDISK}: 10591025/tftp-deploy-op8g5veo/ramdisk/ramdisk.cpio.gz
277 10:57:30.017942 - {ROOT_PART}: None
278 10:57:30.017996 - {ROOT}: None
279 10:57:30.018049 - {SERVER_IP}: 192.168.201.1
280 10:57:30.018101 - {TEE}: None
281 10:57:30.018153 Parsed boot commands:
282 10:57:30.018204 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 10:57:30.018375 Parsed boot commands: tftpboot 192.168.201.1 10591025/tftp-deploy-op8g5veo/kernel/image.itb 10591025/tftp-deploy-op8g5veo/kernel/cmdline
284 10:57:30.018461 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 10:57:30.018542 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 10:57:30.018630 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 10:57:30.018711 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 10:57:30.018779 Not connected, no need to disconnect.
289 10:57:30.018848 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 10:57:30.018921 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 10:57:30.018984 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
292 10:57:30.022255 Setting prompt string to ['lava-test: # ']
293 10:57:30.022608 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 10:57:30.022711 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 10:57:30.022807 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 10:57:30.022896 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 10:57:30.023085 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 10:57:35.155712 >> Command sent successfully.
299 10:57:35.158200 Returned 0 in 5 seconds
300 10:57:35.258607 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 10:57:35.258955 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 10:57:35.259070 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 10:57:35.259165 Setting prompt string to 'Starting depthcharge on Spherion...'
305 10:57:35.259243 Changing prompt to 'Starting depthcharge on Spherion...'
306 10:57:35.259332 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 10:57:35.259680 [Enter `^Ec?' for help]
308 10:57:35.432806
309 10:57:35.432958
310 10:57:35.433054 F0: 102B 0000
311 10:57:35.433136
312 10:57:35.433214 F3: 1001 0000 [0200]
313 10:57:35.433291
314 10:57:35.436317 F3: 1001 0000
315 10:57:35.436416
316 10:57:35.436544 F7: 102D 0000
317 10:57:35.436640
318 10:57:35.439413 F1: 0000 0000
319 10:57:35.439511
320 10:57:35.439588 V0: 0000 0000 [0001]
321 10:57:35.439663
322 10:57:35.442744 00: 0007 8000
323 10:57:35.442848
324 10:57:35.442928 01: 0000 0000
325 10:57:35.443005
326 10:57:35.446597 BP: 0C00 0209 [0000]
327 10:57:35.446683
328 10:57:35.446768 G0: 1182 0000
329 10:57:35.446848
330 10:57:35.449854 EC: 0000 0021 [4000]
331 10:57:35.449940
332 10:57:35.450026 S7: 0000 0000 [0000]
333 10:57:35.450106
334 10:57:35.452903 CC: 0000 0000 [0001]
335 10:57:35.452988
336 10:57:35.453073 T0: 0000 0040 [010F]
337 10:57:35.453153
338 10:57:35.453252 Jump to BL
339 10:57:35.456580
340 10:57:35.479468
341 10:57:35.479555
342 10:57:35.479639
343 10:57:35.486628 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 10:57:35.489739 ARM64: Exception handlers installed.
345 10:57:35.493838 ARM64: Testing exception
346 10:57:35.497622 ARM64: Done test exception
347 10:57:35.503946 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 10:57:35.513716 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 10:57:35.520533 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 10:57:35.530735 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 10:57:35.536945 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 10:57:35.547822 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 10:57:35.557372 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 10:57:35.564397 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 10:57:35.582435 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 10:57:35.585831 WDT: Last reset was cold boot
357 10:57:35.589448 SPI1(PAD0) initialized at 2873684 Hz
358 10:57:35.592525 SPI5(PAD0) initialized at 992727 Hz
359 10:57:35.596161 VBOOT: Loading verstage.
360 10:57:35.602653 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 10:57:35.605890 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 10:57:35.609168 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 10:57:35.612681 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 10:57:35.620226 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 10:57:35.626487 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 10:57:35.637592 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 10:57:35.637679
368 10:57:35.637763
369 10:57:35.647618 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 10:57:35.650717 ARM64: Exception handlers installed.
371 10:57:35.654147 ARM64: Testing exception
372 10:57:35.654240 ARM64: Done test exception
373 10:57:35.660650 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 10:57:35.664039 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 10:57:35.678741 Probing TPM: . done!
376 10:57:35.678826 TPM ready after 0 ms
377 10:57:35.685307 Connected to device vid:did:rid of 1ae0:0028:00
378 10:57:35.692402 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 10:57:35.696038 Initialized TPM device CR50 revision 0
380 10:57:35.761461 tlcl_send_startup: Startup return code is 0
381 10:57:35.761565 TPM: setup succeeded
382 10:57:35.773034 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 10:57:35.781704 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 10:57:35.792108 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 10:57:35.801163 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 10:57:35.804802 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 10:57:35.812177 in-header: 03 07 00 00 08 00 00 00
388 10:57:35.815274 in-data: aa e4 47 04 13 02 00 00
389 10:57:35.819078 Chrome EC: UHEPI supported
390 10:57:35.826038 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 10:57:35.829747 in-header: 03 ad 00 00 08 00 00 00
392 10:57:35.833471 in-data: 00 20 20 08 00 00 00 00
393 10:57:35.833598 Phase 1
394 10:57:35.837162 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 10:57:35.844246 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 10:57:35.851440 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 10:57:35.851525 Recovery requested (1009000e)
398 10:57:35.861668 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 10:57:35.867943 tlcl_extend: response is 0
400 10:57:35.877687 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 10:57:35.883760 tlcl_extend: response is 0
402 10:57:35.891033 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 10:57:35.911161 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 10:57:35.917960 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 10:57:35.918047
406 10:57:35.918114
407 10:57:35.927934 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 10:57:35.931230 ARM64: Exception handlers installed.
409 10:57:35.934575 ARM64: Testing exception
410 10:57:35.934679 ARM64: Done test exception
411 10:57:35.956476 pmic_efuse_setting: Set efuses in 11 msecs
412 10:57:35.959839 pmwrap_interface_init: Select PMIF_VLD_RDY
413 10:57:35.966723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 10:57:35.970122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 10:57:35.973302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 10:57:35.980057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 10:57:35.983467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 10:57:35.991355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 10:57:35.994828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 10:57:35.998177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 10:57:36.001941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 10:57:36.009307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 10:57:36.013003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 10:57:36.016680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 10:57:36.023264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 10:57:36.030071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 10:57:36.033356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 10:57:36.040082 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 10:57:36.044008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 10:57:36.050702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 10:57:36.057576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 10:57:36.061185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 10:57:36.068071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 10:57:36.074977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 10:57:36.077964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 10:57:36.084717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 10:57:36.091354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 10:57:36.094678 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 10:57:36.101194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 10:57:36.104310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 10:57:36.111345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 10:57:36.114450 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 10:57:36.121018 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 10:57:36.124216 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 10:57:36.131082 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 10:57:36.134766 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 10:57:36.141160 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 10:57:36.144339 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 10:57:36.151093 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 10:57:36.154422 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 10:57:36.160728 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 10:57:36.164055 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 10:57:36.167669 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 10:57:36.172305 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 10:57:36.178840 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 10:57:36.182168 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 10:57:36.185444 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 10:57:36.191720 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 10:57:36.195163 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 10:57:36.198478 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 10:57:36.201823 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 10:57:36.208514 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 10:57:36.212081 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 10:57:36.219622 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 10:57:36.226941 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 10:57:36.230624 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 10:57:36.241848 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 10:57:36.249091 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 10:57:36.252883 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 10:57:36.256491 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 10:57:36.264055 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 10:57:36.271002 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
473 10:57:36.274433 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 10:57:36.281264 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 10:57:36.284152 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 10:57:36.293713 [RTC]rtc_get_frequency_meter,154: input=15, output=770
477 10:57:36.303002 [RTC]rtc_get_frequency_meter,154: input=23, output=957
478 10:57:36.312331 [RTC]rtc_get_frequency_meter,154: input=19, output=864
479 10:57:36.322154 [RTC]rtc_get_frequency_meter,154: input=17, output=817
480 10:57:36.332118 [RTC]rtc_get_frequency_meter,154: input=16, output=795
481 10:57:36.335795 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 10:57:36.339959 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 10:57:36.343682 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 10:57:36.350604 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 10:57:36.354168 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 10:57:36.357629 ADC[4]: Raw value=903614 ID=7
487 10:57:36.357704 ADC[3]: Raw value=213179 ID=1
488 10:57:36.360736 RAM Code: 0x71
489 10:57:36.364021 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 10:57:36.370502 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 10:57:36.377449 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 10:57:36.383807 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 10:57:36.387281 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 10:57:36.390793 in-header: 03 07 00 00 08 00 00 00
495 10:57:36.393737 in-data: aa e4 47 04 13 02 00 00
496 10:57:36.397292 Chrome EC: UHEPI supported
497 10:57:36.403686 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 10:57:36.407246 in-header: 03 ed 00 00 08 00 00 00
499 10:57:36.410716 in-data: 80 20 60 08 00 00 00 00
500 10:57:36.413914 MRC: failed to locate region type 0.
501 10:57:36.420528 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 10:57:36.423855 DRAM-K: Running full calibration
503 10:57:36.430590 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 10:57:36.433826 header.status = 0x0
505 10:57:36.436917 header.version = 0x6 (expected: 0x6)
506 10:57:36.440209 header.size = 0xd00 (expected: 0xd00)
507 10:57:36.440292 header.flags = 0x0
508 10:57:36.446993 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 10:57:36.464157 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
510 10:57:36.470809 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 10:57:36.473949 dram_init: ddr_geometry: 2
512 10:57:36.477765 [EMI] MDL number = 2
513 10:57:36.477847 [EMI] Get MDL freq = 0
514 10:57:36.480808 dram_init: ddr_type: 0
515 10:57:36.480905 is_discrete_lpddr4: 1
516 10:57:36.484173 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 10:57:36.484255
518 10:57:36.484322
519 10:57:36.487841 [Bian_co] ETT version 0.0.0.1
520 10:57:36.494174 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 10:57:36.494257
522 10:57:36.497433 dramc_set_vcore_voltage set vcore to 650000
523 10:57:36.497517 Read voltage for 800, 4
524 10:57:36.500718 Vio18 = 0
525 10:57:36.500823 Vcore = 650000
526 10:57:36.500925 Vdram = 0
527 10:57:36.504336 Vddq = 0
528 10:57:36.504436 Vmddr = 0
529 10:57:36.507313 dram_init: config_dvfs: 1
530 10:57:36.511218 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 10:57:36.517393 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 10:57:36.521044 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 10:57:36.524338 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 10:57:36.527385 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 10:57:36.530858 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 10:57:36.534001 MEM_TYPE=3, freq_sel=18
537 10:57:36.537606 sv_algorithm_assistance_LP4_1600
538 10:57:36.540813 ============ PULL DRAM RESETB DOWN ============
539 10:57:36.547687 ========== PULL DRAM RESETB DOWN end =========
540 10:57:36.550911 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 10:57:36.554116 ===================================
542 10:57:36.557367 LPDDR4 DRAM CONFIGURATION
543 10:57:36.560596 ===================================
544 10:57:36.560683 EX_ROW_EN[0] = 0x0
545 10:57:36.564267 EX_ROW_EN[1] = 0x0
546 10:57:36.564354 LP4Y_EN = 0x0
547 10:57:36.567361 WORK_FSP = 0x0
548 10:57:36.567447 WL = 0x2
549 10:57:36.570968 RL = 0x2
550 10:57:36.571055 BL = 0x2
551 10:57:36.574157 RPST = 0x0
552 10:57:36.574244 RD_PRE = 0x0
553 10:57:36.577807 WR_PRE = 0x1
554 10:57:36.577894 WR_PST = 0x0
555 10:57:36.580957 DBI_WR = 0x0
556 10:57:36.581044 DBI_RD = 0x0
557 10:57:36.584564 OTF = 0x1
558 10:57:36.588240 ===================================
559 10:57:36.591851 ===================================
560 10:57:36.591938 ANA top config
561 10:57:36.595513 ===================================
562 10:57:36.599146 DLL_ASYNC_EN = 0
563 10:57:36.599233 ALL_SLAVE_EN = 1
564 10:57:36.603234 NEW_RANK_MODE = 1
565 10:57:36.606552 DLL_IDLE_MODE = 1
566 10:57:36.606664 LP45_APHY_COMB_EN = 1
567 10:57:36.610286 TX_ODT_DIS = 1
568 10:57:36.614067 NEW_8X_MODE = 1
569 10:57:36.617184 ===================================
570 10:57:36.620829 ===================================
571 10:57:36.624956 data_rate = 1600
572 10:57:36.625061 CKR = 1
573 10:57:36.628218 DQ_P2S_RATIO = 8
574 10:57:36.631879 ===================================
575 10:57:36.635730 CA_P2S_RATIO = 8
576 10:57:36.639418 DQ_CA_OPEN = 0
577 10:57:36.639522 DQ_SEMI_OPEN = 0
578 10:57:36.642717 CA_SEMI_OPEN = 0
579 10:57:36.646522 CA_FULL_RATE = 0
580 10:57:36.646634 DQ_CKDIV4_EN = 1
581 10:57:36.650275 CA_CKDIV4_EN = 1
582 10:57:36.654044 CA_PREDIV_EN = 0
583 10:57:36.657754 PH8_DLY = 0
584 10:57:36.661292 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 10:57:36.661409 DQ_AAMCK_DIV = 4
586 10:57:36.665170 CA_AAMCK_DIV = 4
587 10:57:36.668706 CA_ADMCK_DIV = 4
588 10:57:36.672687 DQ_TRACK_CA_EN = 0
589 10:57:36.672835 CA_PICK = 800
590 10:57:36.675957 CA_MCKIO = 800
591 10:57:36.679576 MCKIO_SEMI = 0
592 10:57:36.683085 PLL_FREQ = 3068
593 10:57:36.683196 DQ_UI_PI_RATIO = 32
594 10:57:36.686707 CA_UI_PI_RATIO = 0
595 10:57:36.690774 ===================================
596 10:57:36.694569 ===================================
597 10:57:36.698305 memory_type:LPDDR4
598 10:57:36.698419 GP_NUM : 10
599 10:57:36.701927 SRAM_EN : 1
600 10:57:36.702038 MD32_EN : 0
601 10:57:36.705095 ===================================
602 10:57:36.708680 [ANA_INIT] >>>>>>>>>>>>>>
603 10:57:36.712487 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 10:57:36.715922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 10:57:36.719746 ===================================
606 10:57:36.719852 data_rate = 1600,PCW = 0X7600
607 10:57:36.723338 ===================================
608 10:57:36.727092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 10:57:36.734495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 10:57:36.738547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 10:57:36.742202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 10:57:36.745899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 10:57:36.749962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 10:57:36.753795 [ANA_INIT] flow start
615 10:57:36.753901 [ANA_INIT] PLL >>>>>>>>
616 10:57:36.757338 [ANA_INIT] PLL <<<<<<<<
617 10:57:36.757423 [ANA_INIT] MIDPI >>>>>>>>
618 10:57:36.761114 [ANA_INIT] MIDPI <<<<<<<<
619 10:57:36.764708 [ANA_INIT] DLL >>>>>>>>
620 10:57:36.764854 [ANA_INIT] flow end
621 10:57:36.768653 ============ LP4 DIFF to SE enter ============
622 10:57:36.772194 ============ LP4 DIFF to SE exit ============
623 10:57:36.776203 [ANA_INIT] <<<<<<<<<<<<<
624 10:57:36.779668 [Flow] Enable top DCM control >>>>>
625 10:57:36.783368 [Flow] Enable top DCM control <<<<<
626 10:57:36.787323 Enable DLL master slave shuffle
627 10:57:36.790641 ==============================================================
628 10:57:36.794289 Gating Mode config
629 10:57:36.798646 ==============================================================
630 10:57:36.802210 Config description:
631 10:57:36.809307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 10:57:36.816575 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 10:57:36.820247 SELPH_MODE 0: By rank 1: By Phase
634 10:57:36.827723 ==============================================================
635 10:57:36.831736 GAT_TRACK_EN = 1
636 10:57:36.831843 RX_GATING_MODE = 2
637 10:57:36.835710 RX_GATING_TRACK_MODE = 2
638 10:57:36.839147 SELPH_MODE = 1
639 10:57:36.843127 PICG_EARLY_EN = 1
640 10:57:36.846769 VALID_LAT_VALUE = 1
641 10:57:36.850327 ==============================================================
642 10:57:36.853954 Enter into Gating configuration >>>>
643 10:57:36.858201 Exit from Gating configuration <<<<
644 10:57:36.861808 Enter into DVFS_PRE_config >>>>>
645 10:57:36.872345 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 10:57:36.876046 Exit from DVFS_PRE_config <<<<<
647 10:57:36.876149 Enter into PICG configuration >>>>
648 10:57:36.879683 Exit from PICG configuration <<<<
649 10:57:36.883396 [RX_INPUT] configuration >>>>>
650 10:57:36.887156 [RX_INPUT] configuration <<<<<
651 10:57:36.891096 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 10:57:36.898048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 10:57:36.902263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 10:57:36.909575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 10:57:36.917674 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 10:57:36.920334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 10:57:36.923775 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 10:57:36.930302 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 10:57:36.934014 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 10:57:36.937728 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 10:57:36.941060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 10:57:36.947505 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 10:57:36.950829 ===================================
664 10:57:36.950932 LPDDR4 DRAM CONFIGURATION
665 10:57:36.954374 ===================================
666 10:57:36.957719 EX_ROW_EN[0] = 0x0
667 10:57:36.960912 EX_ROW_EN[1] = 0x0
668 10:57:36.960987 LP4Y_EN = 0x0
669 10:57:36.964050 WORK_FSP = 0x0
670 10:57:36.964149 WL = 0x2
671 10:57:36.967835 RL = 0x2
672 10:57:36.967935 BL = 0x2
673 10:57:36.971032 RPST = 0x0
674 10:57:36.971131 RD_PRE = 0x0
675 10:57:36.974434 WR_PRE = 0x1
676 10:57:36.974509 WR_PST = 0x0
677 10:57:36.977498 DBI_WR = 0x0
678 10:57:36.977572 DBI_RD = 0x0
679 10:57:36.981044 OTF = 0x1
680 10:57:36.984231 ===================================
681 10:57:36.987655 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 10:57:36.990884 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 10:57:36.997558 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 10:57:36.997665 ===================================
685 10:57:37.000686 LPDDR4 DRAM CONFIGURATION
686 10:57:37.004495 ===================================
687 10:57:37.007835 EX_ROW_EN[0] = 0x10
688 10:57:37.007919 EX_ROW_EN[1] = 0x0
689 10:57:37.010853 LP4Y_EN = 0x0
690 10:57:37.010936 WORK_FSP = 0x0
691 10:57:37.014540 WL = 0x2
692 10:57:37.014624 RL = 0x2
693 10:57:37.017596 BL = 0x2
694 10:57:37.017680 RPST = 0x0
695 10:57:37.021164 RD_PRE = 0x0
696 10:57:37.021247 WR_PRE = 0x1
697 10:57:37.024307 WR_PST = 0x0
698 10:57:37.027754 DBI_WR = 0x0
699 10:57:37.027855 DBI_RD = 0x0
700 10:57:37.030940 OTF = 0x1
701 10:57:37.034116 ===================================
702 10:57:37.037342 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 10:57:37.043266 nWR fixed to 40
704 10:57:37.046073 [ModeRegInit_LP4] CH0 RK0
705 10:57:37.046156 [ModeRegInit_LP4] CH0 RK1
706 10:57:37.049544 [ModeRegInit_LP4] CH1 RK0
707 10:57:37.052797 [ModeRegInit_LP4] CH1 RK1
708 10:57:37.052894 match AC timing 13
709 10:57:37.059706 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 10:57:37.062951 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 10:57:37.066162 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 10:57:37.072987 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 10:57:37.076254 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 10:57:37.076343 [EMI DOE] emi_dcm 0
715 10:57:37.082769 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 10:57:37.082845 ==
717 10:57:37.086284 Dram Type= 6, Freq= 0, CH_0, rank 0
718 10:57:37.089488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 10:57:37.089568 ==
720 10:57:37.096155 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 10:57:37.102506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 10:57:37.110487 [CA 0] Center 38 (7~69) winsize 63
723 10:57:37.113802 [CA 1] Center 38 (7~69) winsize 63
724 10:57:37.116948 [CA 2] Center 35 (5~66) winsize 62
725 10:57:37.120167 [CA 3] Center 35 (5~66) winsize 62
726 10:57:37.123816 [CA 4] Center 34 (4~65) winsize 62
727 10:57:37.126946 [CA 5] Center 33 (3~64) winsize 62
728 10:57:37.127016
729 10:57:37.130119 [CmdBusTrainingLP45] Vref(ca) range 1: 32
730 10:57:37.130188
731 10:57:37.133620 [CATrainingPosCal] consider 1 rank data
732 10:57:37.137046 u2DelayCellTimex100 = 270/100 ps
733 10:57:37.140093 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
734 10:57:37.146881 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
735 10:57:37.150282 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
736 10:57:37.153466 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
737 10:57:37.157073 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
738 10:57:37.160130 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
739 10:57:37.160203
740 10:57:37.163469 CA PerBit enable=1, Macro0, CA PI delay=33
741 10:57:37.163543
742 10:57:37.166648 [CBTSetCACLKResult] CA Dly = 33
743 10:57:37.166720 CS Dly: 6 (0~37)
744 10:57:37.169982 ==
745 10:57:37.173654 Dram Type= 6, Freq= 0, CH_0, rank 1
746 10:57:37.176965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 10:57:37.177039 ==
748 10:57:37.180271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 10:57:37.186741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 10:57:37.196651 [CA 0] Center 38 (8~69) winsize 62
751 10:57:37.200272 [CA 1] Center 38 (8~69) winsize 62
752 10:57:37.203264 [CA 2] Center 36 (6~67) winsize 62
753 10:57:37.206988 [CA 3] Center 36 (5~67) winsize 63
754 10:57:37.210159 [CA 4] Center 35 (4~66) winsize 63
755 10:57:37.213301 [CA 5] Center 34 (4~65) winsize 62
756 10:57:37.213373
757 10:57:37.216565 [CmdBusTrainingLP45] Vref(ca) range 1: 34
758 10:57:37.216640
759 10:57:37.219788 [CATrainingPosCal] consider 2 rank data
760 10:57:37.223533 u2DelayCellTimex100 = 270/100 ps
761 10:57:37.226713 CA0 delay=38 (8~69),Diff = 4 PI (28 cell)
762 10:57:37.233110 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
763 10:57:37.236799 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
764 10:57:37.240087 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 10:57:37.243268 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
766 10:57:37.246336 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
767 10:57:37.246410
768 10:57:37.250041 CA PerBit enable=1, Macro0, CA PI delay=34
769 10:57:37.250109
770 10:57:37.253067 [CBTSetCACLKResult] CA Dly = 34
771 10:57:37.253140 CS Dly: 7 (0~39)
772 10:57:37.256642
773 10:57:37.259578 ----->DramcWriteLeveling(PI) begin...
774 10:57:37.259657 ==
775 10:57:37.262969 Dram Type= 6, Freq= 0, CH_0, rank 0
776 10:57:37.266540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 10:57:37.266619 ==
778 10:57:37.269685 Write leveling (Byte 0): 32 => 32
779 10:57:37.272926 Write leveling (Byte 1): 30 => 30
780 10:57:37.276209 DramcWriteLeveling(PI) end<-----
781 10:57:37.276282
782 10:57:37.276342 ==
783 10:57:37.279546 Dram Type= 6, Freq= 0, CH_0, rank 0
784 10:57:37.283233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 10:57:37.283305 ==
786 10:57:37.286964 [Gating] SW mode calibration
787 10:57:37.293895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 10:57:37.298049 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 10:57:37.301750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
790 10:57:37.308191 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
791 10:57:37.311439 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
792 10:57:37.315361 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:57:37.319020 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:57:37.325863 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:57:37.329004 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:57:37.332352 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:57:37.338827 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:57:37.342106 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:57:37.345432 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:57:37.352139 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:57:37.355385 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:57:37.359130 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:57:37.365683 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:57:37.368967 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 10:57:37.372496 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
806 10:57:37.379147 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
807 10:57:37.381994 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
808 10:57:37.385675 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:57:37.388845 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:57:37.395833 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:57:37.399099 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:57:37.402272 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 10:57:37.408901 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 10:57:37.412074 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
815 10:57:37.415318 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
816 10:57:37.422019 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
817 10:57:37.425320 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:57:37.428869 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:57:37.435396 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 10:57:37.438522 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 10:57:37.442231 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 10:57:37.448717 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
823 10:57:37.451756 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
824 10:57:37.455366 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
825 10:57:37.461958 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:57:37.465041 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:57:37.468595 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:57:37.474965 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 10:57:37.478651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 10:57:37.481783 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
831 10:57:37.488462 0 11 8 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
832 10:57:37.491812 0 11 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
833 10:57:37.495054 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:57:37.501481 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:57:37.505133 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 10:57:37.508089 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 10:57:37.514848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 10:57:37.518222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
839 10:57:37.521381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
840 10:57:37.528269 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:57:37.531395 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:57:37.534732 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:57:37.541501 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:57:37.544700 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:57:37.547889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:57:37.554662 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:57:37.557819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:57:37.561125 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:57:37.567764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:57:37.571241 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:57:37.574393 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:57:37.581269 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 10:57:37.584265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 10:57:37.587785 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
855 10:57:37.590978 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:57:37.594232 Total UI for P1: 0, mck2ui 16
857 10:57:37.597744 best dqsien dly found for B0: ( 0, 14, 4)
858 10:57:37.600959 Total UI for P1: 0, mck2ui 16
859 10:57:37.604314 best dqsien dly found for B1: ( 0, 14, 6)
860 10:57:37.607560 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
861 10:57:37.614129 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
862 10:57:37.614234
863 10:57:37.617474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
864 10:57:37.620700 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
865 10:57:37.624264 [Gating] SW calibration Done
866 10:57:37.624350 ==
867 10:57:37.627472 Dram Type= 6, Freq= 0, CH_0, rank 0
868 10:57:37.630779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
869 10:57:37.630858 ==
870 10:57:37.630937 RX Vref Scan: 0
871 10:57:37.631009
872 10:57:37.634329 RX Vref 0 -> 0, step: 1
873 10:57:37.634403
874 10:57:37.637738 RX Delay -130 -> 252, step: 16
875 10:57:37.640984 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
876 10:57:37.644653 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
877 10:57:37.651081 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
878 10:57:37.654112 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
879 10:57:37.657585 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
880 10:57:37.661180 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
881 10:57:37.664355 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
882 10:57:37.670870 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
883 10:57:37.674267 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
884 10:57:37.677837 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
885 10:57:37.680893 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
886 10:57:37.684273 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
887 10:57:37.690866 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
888 10:57:37.693829 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
889 10:57:37.697541 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
890 10:57:37.701084 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
891 10:57:37.701163 ==
892 10:57:37.703842 Dram Type= 6, Freq= 0, CH_0, rank 0
893 10:57:37.710707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
894 10:57:37.710787 ==
895 10:57:37.710856 DQS Delay:
896 10:57:37.713774 DQS0 = 0, DQS1 = 0
897 10:57:37.713849 DQM Delay:
898 10:57:37.713916 DQM0 = 92, DQM1 = 79
899 10:57:37.717306 DQ Delay:
900 10:57:37.720429 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
901 10:57:37.723682 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
902 10:57:37.727263 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
903 10:57:37.730586 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
904 10:57:37.730655
905 10:57:37.730717
906 10:57:37.730779 ==
907 10:57:37.733899 Dram Type= 6, Freq= 0, CH_0, rank 0
908 10:57:37.737127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 10:57:37.737196 ==
910 10:57:37.737259
911 10:57:37.737317
912 10:57:37.740354 TX Vref Scan disable
913 10:57:37.743551 == TX Byte 0 ==
914 10:57:37.746787 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
915 10:57:37.750435 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
916 10:57:37.753679 == TX Byte 1 ==
917 10:57:37.757155 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
918 10:57:37.760221 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
919 10:57:37.760288 ==
920 10:57:37.763711 Dram Type= 6, Freq= 0, CH_0, rank 0
921 10:57:37.766905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 10:57:37.770263 ==
923 10:57:37.781536 TX Vref=22, minBit 6, minWin=27, winSum=440
924 10:57:37.784889 TX Vref=24, minBit 6, minWin=27, winSum=446
925 10:57:37.788375 TX Vref=26, minBit 8, minWin=27, winSum=448
926 10:57:37.791437 TX Vref=28, minBit 13, minWin=27, winSum=452
927 10:57:37.794733 TX Vref=30, minBit 5, minWin=28, winSum=456
928 10:57:37.801690 TX Vref=32, minBit 10, minWin=27, winSum=453
929 10:57:37.804915 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
930 10:57:37.805002
931 10:57:37.808187 Final TX Range 1 Vref 30
932 10:57:37.808319
933 10:57:37.808387 ==
934 10:57:37.811358 Dram Type= 6, Freq= 0, CH_0, rank 0
935 10:57:37.814453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 10:57:37.818321 ==
937 10:57:37.818415
938 10:57:37.818515
939 10:57:37.818622 TX Vref Scan disable
940 10:57:37.821593 == TX Byte 0 ==
941 10:57:37.824865 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
942 10:57:37.828733 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
943 10:57:37.831874 == TX Byte 1 ==
944 10:57:37.835085 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
945 10:57:37.838377 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
946 10:57:37.841673
947 10:57:37.841789 [DATLAT]
948 10:57:37.841886 Freq=800, CH0 RK0
949 10:57:37.841978
950 10:57:37.844951 DATLAT Default: 0xa
951 10:57:37.845065 0, 0xFFFF, sum = 0
952 10:57:37.848175 1, 0xFFFF, sum = 0
953 10:57:37.848306 2, 0xFFFF, sum = 0
954 10:57:37.851807 3, 0xFFFF, sum = 0
955 10:57:37.851916 4, 0xFFFF, sum = 0
956 10:57:37.855131 5, 0xFFFF, sum = 0
957 10:57:37.858374 6, 0xFFFF, sum = 0
958 10:57:37.858509 7, 0xFFFF, sum = 0
959 10:57:37.861737 8, 0xFFFF, sum = 0
960 10:57:37.861849 9, 0x0, sum = 1
961 10:57:37.861954 10, 0x0, sum = 2
962 10:57:37.864905 11, 0x0, sum = 3
963 10:57:37.864993 12, 0x0, sum = 4
964 10:57:37.868395 best_step = 10
965 10:57:37.868502
966 10:57:37.868598 ==
967 10:57:37.871544 Dram Type= 6, Freq= 0, CH_0, rank 0
968 10:57:37.874780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 10:57:37.874922 ==
970 10:57:37.878023 RX Vref Scan: 1
971 10:57:37.878127
972 10:57:37.878231 Set Vref Range= 32 -> 127
973 10:57:37.881289
974 10:57:37.881365 RX Vref 32 -> 127, step: 1
975 10:57:37.881467
976 10:57:37.884744 RX Delay -95 -> 252, step: 8
977 10:57:37.884884
978 10:57:37.888174 Set Vref, RX VrefLevel [Byte0]: 32
979 10:57:37.891686 [Byte1]: 32
980 10:57:37.891810
981 10:57:37.894912 Set Vref, RX VrefLevel [Byte0]: 33
982 10:57:37.898310 [Byte1]: 33
983 10:57:37.901875
984 10:57:37.901966 Set Vref, RX VrefLevel [Byte0]: 34
985 10:57:37.905212 [Byte1]: 34
986 10:57:37.909387
987 10:57:37.909492 Set Vref, RX VrefLevel [Byte0]: 35
988 10:57:37.915874 [Byte1]: 35
989 10:57:37.915982
990 10:57:37.919139 Set Vref, RX VrefLevel [Byte0]: 36
991 10:57:37.922403 [Byte1]: 36
992 10:57:37.922508
993 10:57:37.925759 Set Vref, RX VrefLevel [Byte0]: 37
994 10:57:37.929469 [Byte1]: 37
995 10:57:37.929567
996 10:57:37.932965 Set Vref, RX VrefLevel [Byte0]: 38
997 10:57:37.935934 [Byte1]: 38
998 10:57:37.939773
999 10:57:37.939888 Set Vref, RX VrefLevel [Byte0]: 39
1000 10:57:37.943400 [Byte1]: 39
1001 10:57:37.947554
1002 10:57:37.947667 Set Vref, RX VrefLevel [Byte0]: 40
1003 10:57:37.950916 [Byte1]: 40
1004 10:57:37.955061
1005 10:57:37.955172 Set Vref, RX VrefLevel [Byte0]: 41
1006 10:57:37.958351 [Byte1]: 41
1007 10:57:37.963423
1008 10:57:37.963534 Set Vref, RX VrefLevel [Byte0]: 42
1009 10:57:37.966464 [Byte1]: 42
1010 10:57:37.971236
1011 10:57:37.971347 Set Vref, RX VrefLevel [Byte0]: 43
1012 10:57:37.973904 [Byte1]: 43
1013 10:57:37.978245
1014 10:57:37.978337 Set Vref, RX VrefLevel [Byte0]: 44
1015 10:57:37.981442 [Byte1]: 44
1016 10:57:37.985514
1017 10:57:37.985620 Set Vref, RX VrefLevel [Byte0]: 45
1018 10:57:37.988662 [Byte1]: 45
1019 10:57:37.993109
1020 10:57:37.993202 Set Vref, RX VrefLevel [Byte0]: 46
1021 10:57:37.996329 [Byte1]: 46
1022 10:57:38.001128
1023 10:57:38.001213 Set Vref, RX VrefLevel [Byte0]: 47
1024 10:57:38.003842 [Byte1]: 47
1025 10:57:38.008258
1026 10:57:38.008343 Set Vref, RX VrefLevel [Byte0]: 48
1027 10:57:38.011778 [Byte1]: 48
1028 10:57:38.016058
1029 10:57:38.016141 Set Vref, RX VrefLevel [Byte0]: 49
1030 10:57:38.019237 [Byte1]: 49
1031 10:57:38.023689
1032 10:57:38.023771 Set Vref, RX VrefLevel [Byte0]: 50
1033 10:57:38.026844 [Byte1]: 50
1034 10:57:38.031250
1035 10:57:38.031358 Set Vref, RX VrefLevel [Byte0]: 51
1036 10:57:38.034421 [Byte1]: 51
1037 10:57:38.038666
1038 10:57:38.038749 Set Vref, RX VrefLevel [Byte0]: 52
1039 10:57:38.041756 [Byte1]: 52
1040 10:57:38.046441
1041 10:57:38.046524 Set Vref, RX VrefLevel [Byte0]: 53
1042 10:57:38.049638 [Byte1]: 53
1043 10:57:38.053770
1044 10:57:38.053852 Set Vref, RX VrefLevel [Byte0]: 54
1045 10:57:38.057354 [Byte1]: 54
1046 10:57:38.061294
1047 10:57:38.061376 Set Vref, RX VrefLevel [Byte0]: 55
1048 10:57:38.064877 [Byte1]: 55
1049 10:57:38.069032
1050 10:57:38.069114 Set Vref, RX VrefLevel [Byte0]: 56
1051 10:57:38.072463 [Byte1]: 56
1052 10:57:38.076803
1053 10:57:38.076885 Set Vref, RX VrefLevel [Byte0]: 57
1054 10:57:38.080262 [Byte1]: 57
1055 10:57:38.084449
1056 10:57:38.084531 Set Vref, RX VrefLevel [Byte0]: 58
1057 10:57:38.087499 [Byte1]: 58
1058 10:57:38.091719
1059 10:57:38.091802 Set Vref, RX VrefLevel [Byte0]: 59
1060 10:57:38.095267 [Byte1]: 59
1061 10:57:38.099266
1062 10:57:38.099348 Set Vref, RX VrefLevel [Byte0]: 60
1063 10:57:38.102493 [Byte1]: 60
1064 10:57:38.107021
1065 10:57:38.107103 Set Vref, RX VrefLevel [Byte0]: 61
1066 10:57:38.110638 [Byte1]: 61
1067 10:57:38.114711
1068 10:57:38.114793 Set Vref, RX VrefLevel [Byte0]: 62
1069 10:57:38.117792 [Byte1]: 62
1070 10:57:38.122103
1071 10:57:38.122186 Set Vref, RX VrefLevel [Byte0]: 63
1072 10:57:38.125470 [Byte1]: 63
1073 10:57:38.129693
1074 10:57:38.129775 Set Vref, RX VrefLevel [Byte0]: 64
1075 10:57:38.133057 [Byte1]: 64
1076 10:57:38.137269
1077 10:57:38.137352 Set Vref, RX VrefLevel [Byte0]: 65
1078 10:57:38.140794 [Byte1]: 65
1079 10:57:38.145004
1080 10:57:38.145085 Set Vref, RX VrefLevel [Byte0]: 66
1081 10:57:38.148175 [Byte1]: 66
1082 10:57:38.152674
1083 10:57:38.152759 Set Vref, RX VrefLevel [Byte0]: 67
1084 10:57:38.155946 [Byte1]: 67
1085 10:57:38.160143
1086 10:57:38.160225 Set Vref, RX VrefLevel [Byte0]: 68
1087 10:57:38.163894 [Byte1]: 68
1088 10:57:38.167816
1089 10:57:38.167904 Set Vref, RX VrefLevel [Byte0]: 69
1090 10:57:38.171430 [Byte1]: 69
1091 10:57:38.175245
1092 10:57:38.175338 Set Vref, RX VrefLevel [Byte0]: 70
1093 10:57:38.178957 [Byte1]: 70
1094 10:57:38.183405
1095 10:57:38.183496 Set Vref, RX VrefLevel [Byte0]: 71
1096 10:57:38.186394 [Byte1]: 71
1097 10:57:38.190755
1098 10:57:38.190838 Set Vref, RX VrefLevel [Byte0]: 72
1099 10:57:38.193993 [Byte1]: 72
1100 10:57:38.198094
1101 10:57:38.198177 Set Vref, RX VrefLevel [Byte0]: 73
1102 10:57:38.201647 [Byte1]: 73
1103 10:57:38.205810
1104 10:57:38.205893 Set Vref, RX VrefLevel [Byte0]: 74
1105 10:57:38.208950 [Byte1]: 74
1106 10:57:38.213761
1107 10:57:38.213844 Set Vref, RX VrefLevel [Byte0]: 75
1108 10:57:38.216878 [Byte1]: 75
1109 10:57:38.221508
1110 10:57:38.221592 Set Vref, RX VrefLevel [Byte0]: 76
1111 10:57:38.224185 [Byte1]: 76
1112 10:57:38.228622
1113 10:57:38.228702 Final RX Vref Byte 0 = 59 to rank0
1114 10:57:38.231933 Final RX Vref Byte 1 = 62 to rank0
1115 10:57:38.235458 Final RX Vref Byte 0 = 59 to rank1
1116 10:57:38.238517 Final RX Vref Byte 1 = 62 to rank1==
1117 10:57:38.241793 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 10:57:38.248407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 10:57:38.248489 ==
1120 10:57:38.248555 DQS Delay:
1121 10:57:38.248614 DQS0 = 0, DQS1 = 0
1122 10:57:38.252006 DQM Delay:
1123 10:57:38.252087 DQM0 = 93, DQM1 = 83
1124 10:57:38.255086 DQ Delay:
1125 10:57:38.258421 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1126 10:57:38.261535 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1127 10:57:38.264978 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1128 10:57:38.268255 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1129 10:57:38.268336
1130 10:57:38.268401
1131 10:57:38.274942 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1132 10:57:38.278503 CH0 RK0: MR19=606, MR18=3E39
1133 10:57:38.284888 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1134 10:57:38.284969
1135 10:57:38.288047 ----->DramcWriteLeveling(PI) begin...
1136 10:57:38.288130 ==
1137 10:57:38.291437 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 10:57:38.295116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 10:57:38.295198 ==
1140 10:57:38.298334 Write leveling (Byte 0): 33 => 33
1141 10:57:38.301365 Write leveling (Byte 1): 29 => 29
1142 10:57:38.304781 DramcWriteLeveling(PI) end<-----
1143 10:57:38.304877
1144 10:57:38.304942 ==
1145 10:57:38.307874 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 10:57:38.311194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 10:57:38.311276 ==
1148 10:57:38.314582 [Gating] SW mode calibration
1149 10:57:38.321127 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 10:57:38.327872 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 10:57:38.331098 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 10:57:38.337750 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 10:57:38.341429 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 10:57:38.344513 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 10:57:38.351262 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:57:38.354490 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:57:38.357687 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:57:38.401960 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:57:38.402579 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:57:38.402893 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:57:38.402963 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:57:38.403026 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:57:38.403315 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:57:38.403863 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:57:38.404131 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:57:38.404211 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:57:38.404274 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1168 10:57:38.444255 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1169 10:57:38.444725 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:57:38.445034 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:57:38.445107 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:57:38.445528 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:57:38.445803 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:57:38.446426 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:57:38.446696 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:57:38.446794 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:57:38.447092 0 9 8 | B1->B0 | 2e2e 3434 | 0 0 | (1 1) (0 0)
1178 10:57:38.449853 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 10:57:38.456684 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:57:38.459782 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:57:38.463499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:57:38.469913 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:57:38.473469 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:57:38.476564 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1185 10:57:38.482951 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1186 10:57:38.486026 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:57:38.489596 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:57:38.496368 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:57:38.499478 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:57:38.502982 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:57:38.509362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:57:38.512717 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1193 10:57:38.515781 0 11 8 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
1194 10:57:38.522632 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 10:57:38.525748 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 10:57:38.529046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:57:38.536186 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:57:38.539711 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:57:38.543760 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:57:38.546997 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:57:38.550721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 10:57:38.557884 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 10:57:38.560752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:57:38.564804 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:57:38.568316 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:57:38.574710 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:57:38.578179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:57:38.581560 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:57:38.588263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:57:38.591442 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:57:38.594763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:57:38.601308 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:57:38.604543 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:57:38.607862 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:57:38.614921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:57:38.618015 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 10:57:38.621192 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 10:57:38.624604 Total UI for P1: 0, mck2ui 16
1219 10:57:38.627956 best dqsien dly found for B0: ( 0, 14, 4)
1220 10:57:38.631149 Total UI for P1: 0, mck2ui 16
1221 10:57:38.634936 best dqsien dly found for B1: ( 0, 14, 6)
1222 10:57:38.638092 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 10:57:38.641074 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1224 10:57:38.641157
1225 10:57:38.644783 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 10:57:38.651295 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 10:57:38.651378 [Gating] SW calibration Done
1228 10:57:38.651443 ==
1229 10:57:38.654375 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 10:57:38.661276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 10:57:38.661358 ==
1232 10:57:38.661423 RX Vref Scan: 0
1233 10:57:38.661485
1234 10:57:38.664373 RX Vref 0 -> 0, step: 1
1235 10:57:38.664454
1236 10:57:38.667655 RX Delay -130 -> 252, step: 16
1237 10:57:38.670858 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1238 10:57:38.674385 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1239 10:57:38.677939 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1240 10:57:38.684446 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1241 10:57:38.687707 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1242 10:57:38.690938 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 10:57:38.694599 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1244 10:57:38.697928 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1245 10:57:38.704479 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1246 10:57:38.707705 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1247 10:57:38.710913 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 10:57:38.714638 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1249 10:57:38.717720 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1250 10:57:38.724559 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1251 10:57:38.727745 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1252 10:57:38.730826 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1253 10:57:38.730909 ==
1254 10:57:38.734218 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 10:57:38.737471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 10:57:38.737554 ==
1257 10:57:38.740784 DQS Delay:
1258 10:57:38.740881 DQS0 = 0, DQS1 = 0
1259 10:57:38.744371 DQM Delay:
1260 10:57:38.744454 DQM0 = 93, DQM1 = 82
1261 10:57:38.744520 DQ Delay:
1262 10:57:38.747413 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1263 10:57:38.750705 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1264 10:57:38.753999 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =85
1265 10:57:38.757604 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1266 10:57:38.757688
1267 10:57:38.757754
1268 10:57:38.760898 ==
1269 10:57:38.763925 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 10:57:38.767559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 10:57:38.767643 ==
1272 10:57:38.767709
1273 10:57:38.767803
1274 10:57:38.770669 TX Vref Scan disable
1275 10:57:38.770753 == TX Byte 0 ==
1276 10:57:38.777175 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1277 10:57:38.780800 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1278 10:57:38.780897 == TX Byte 1 ==
1279 10:57:38.787310 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 10:57:38.790885 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 10:57:38.790983 ==
1282 10:57:38.794204 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 10:57:38.797251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 10:57:38.797334 ==
1285 10:57:38.811339 TX Vref=22, minBit 3, minWin=27, winSum=444
1286 10:57:38.814478 TX Vref=24, minBit 8, minWin=27, winSum=450
1287 10:57:38.817632 TX Vref=26, minBit 8, minWin=27, winSum=449
1288 10:57:38.821067 TX Vref=28, minBit 8, minWin=27, winSum=452
1289 10:57:38.824579 TX Vref=30, minBit 8, minWin=27, winSum=454
1290 10:57:38.831260 TX Vref=32, minBit 10, minWin=27, winSum=456
1291 10:57:38.834334 [TxChooseVref] Worse bit 10, Min win 27, Win sum 456, Final Vref 32
1292 10:57:38.834417
1293 10:57:38.837956 Final TX Range 1 Vref 32
1294 10:57:38.838039
1295 10:57:38.838105 ==
1296 10:57:38.841184 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 10:57:38.844405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 10:57:38.847555 ==
1299 10:57:38.847636
1300 10:57:38.847699
1301 10:57:38.847758 TX Vref Scan disable
1302 10:57:38.851543 == TX Byte 0 ==
1303 10:57:38.854969 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1304 10:57:38.858139 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1305 10:57:38.861387 == TX Byte 1 ==
1306 10:57:38.864980 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 10:57:38.868162 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 10:57:38.871285
1309 10:57:38.871365 [DATLAT]
1310 10:57:38.871429 Freq=800, CH0 RK1
1311 10:57:38.871489
1312 10:57:38.875216 DATLAT Default: 0xa
1313 10:57:38.875296 0, 0xFFFF, sum = 0
1314 10:57:38.878247 1, 0xFFFF, sum = 0
1315 10:57:38.878329 2, 0xFFFF, sum = 0
1316 10:57:38.881216 3, 0xFFFF, sum = 0
1317 10:57:38.881298 4, 0xFFFF, sum = 0
1318 10:57:38.884528 5, 0xFFFF, sum = 0
1319 10:57:38.888211 6, 0xFFFF, sum = 0
1320 10:57:38.888314 7, 0xFFFF, sum = 0
1321 10:57:38.891405 8, 0xFFFF, sum = 0
1322 10:57:38.891487 9, 0x0, sum = 1
1323 10:57:38.891552 10, 0x0, sum = 2
1324 10:57:38.894666 11, 0x0, sum = 3
1325 10:57:38.894748 12, 0x0, sum = 4
1326 10:57:38.897895 best_step = 10
1327 10:57:38.897975
1328 10:57:38.898038 ==
1329 10:57:38.901186 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 10:57:38.904489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 10:57:38.904570 ==
1332 10:57:38.908081 RX Vref Scan: 0
1333 10:57:38.908163
1334 10:57:38.908233 RX Vref 0 -> 0, step: 1
1335 10:57:38.908324
1336 10:57:38.911051 RX Delay -95 -> 252, step: 8
1337 10:57:38.918042 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 10:57:38.921718 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1339 10:57:38.924735 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1340 10:57:38.927814 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1341 10:57:38.931456 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1342 10:57:38.937948 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1343 10:57:38.941334 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1344 10:57:38.944399 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 10:57:38.947987 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1346 10:57:38.951315 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1347 10:57:38.957712 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1348 10:57:38.961336 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1349 10:57:38.964496 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1350 10:57:38.967749 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1351 10:57:38.971292 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 10:57:38.977792 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 10:57:38.977863 ==
1354 10:57:38.981230 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 10:57:38.984699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 10:57:38.984796 ==
1357 10:57:38.984858 DQS Delay:
1358 10:57:38.988107 DQS0 = 0, DQS1 = 0
1359 10:57:38.988205 DQM Delay:
1360 10:57:38.991261 DQM0 = 91, DQM1 = 81
1361 10:57:38.991356 DQ Delay:
1362 10:57:38.994704 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1363 10:57:38.997873 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1364 10:57:39.001127 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1365 10:57:39.004643 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1366 10:57:39.004743
1367 10:57:39.004875
1368 10:57:39.014227 [DQSOSCAuto] RK1, (LSB)MR18= 0x401b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1369 10:57:39.014312 CH0 RK1: MR19=606, MR18=401B
1370 10:57:39.021360 CH0_RK1: MR19=0x606, MR18=0x401B, DQSOSC=393, MR23=63, INC=95, DEC=63
1371 10:57:39.024612 [RxdqsGatingPostProcess] freq 800
1372 10:57:39.031116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 10:57:39.034424 Pre-setting of DQS Precalculation
1374 10:57:39.037731 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 10:57:39.037815 ==
1376 10:57:39.041344 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 10:57:39.044461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 10:57:39.047649 ==
1379 10:57:39.051091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 10:57:39.057949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 10:57:39.066861 [CA 0] Center 36 (6~67) winsize 62
1382 10:57:39.069741 [CA 1] Center 36 (6~67) winsize 62
1383 10:57:39.073312 [CA 2] Center 34 (4~65) winsize 62
1384 10:57:39.076646 [CA 3] Center 34 (4~65) winsize 62
1385 10:57:39.079810 [CA 4] Center 34 (4~65) winsize 62
1386 10:57:39.083187 [CA 5] Center 34 (3~65) winsize 63
1387 10:57:39.083270
1388 10:57:39.086318 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1389 10:57:39.086428
1390 10:57:39.089714 [CATrainingPosCal] consider 1 rank data
1391 10:57:39.092874 u2DelayCellTimex100 = 270/100 ps
1392 10:57:39.096407 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 10:57:39.099910 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 10:57:39.106132 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 10:57:39.109840 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 10:57:39.112870 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 10:57:39.116604 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1398 10:57:39.116704
1399 10:57:39.119450 CA PerBit enable=1, Macro0, CA PI delay=34
1400 10:57:39.119552
1401 10:57:39.122817 [CBTSetCACLKResult] CA Dly = 34
1402 10:57:39.122919 CS Dly: 5 (0~36)
1403 10:57:39.126360 ==
1404 10:57:39.129300 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 10:57:39.133061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 10:57:39.133134 ==
1407 10:57:39.135929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 10:57:39.142695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 10:57:39.152614 [CA 0] Center 37 (6~68) winsize 63
1410 10:57:39.155711 [CA 1] Center 37 (6~68) winsize 63
1411 10:57:39.159409 [CA 2] Center 35 (5~66) winsize 62
1412 10:57:39.162600 [CA 3] Center 34 (4~65) winsize 62
1413 10:57:39.165826 [CA 4] Center 34 (4~65) winsize 62
1414 10:57:39.169094 [CA 5] Center 34 (4~65) winsize 62
1415 10:57:39.169173
1416 10:57:39.172571 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 10:57:39.172673
1418 10:57:39.175640 [CATrainingPosCal] consider 2 rank data
1419 10:57:39.179085 u2DelayCellTimex100 = 270/100 ps
1420 10:57:39.182473 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 10:57:39.189172 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 10:57:39.192531 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 10:57:39.195692 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 10:57:39.199055 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 10:57:39.202728 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 10:57:39.202838
1427 10:57:39.206203 CA PerBit enable=1, Macro0, CA PI delay=34
1428 10:57:39.206315
1429 10:57:39.209479 [CBTSetCACLKResult] CA Dly = 34
1430 10:57:39.209582 CS Dly: 6 (0~38)
1431 10:57:39.209677
1432 10:57:39.213387 ----->DramcWriteLeveling(PI) begin...
1433 10:57:39.213491 ==
1434 10:57:39.217034 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 10:57:39.221214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 10:57:39.221295 ==
1437 10:57:39.224758 Write leveling (Byte 0): 27 => 27
1438 10:57:39.228317 Write leveling (Byte 1): 27 => 27
1439 10:57:39.231961 DramcWriteLeveling(PI) end<-----
1440 10:57:39.232036
1441 10:57:39.232102 ==
1442 10:57:39.236127 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 10:57:39.239211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 10:57:39.239310 ==
1445 10:57:39.242663 [Gating] SW mode calibration
1446 10:57:39.249439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 10:57:39.252659 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 10:57:39.259464 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 10:57:39.262667 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 10:57:39.265539 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 10:57:39.272860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 10:57:39.275873 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:57:39.278980 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:57:39.285587 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:57:39.288881 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:57:39.292391 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:57:39.299279 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:57:39.302182 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:57:39.305720 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:57:39.312152 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:57:39.315479 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:57:39.318815 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:57:39.325629 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:57:39.328683 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1465 10:57:39.332168 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:57:39.338945 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:57:39.342221 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:57:39.345350 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:57:39.352178 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:57:39.355443 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:57:39.358840 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:57:39.365643 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:57:39.368700 0 9 4 | B1->B0 | 2424 2a2a | 1 1 | (1 1) (1 1)
1474 10:57:39.372122 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 10:57:39.375342 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 10:57:39.382054 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 10:57:39.385322 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 10:57:39.388905 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:57:39.395225 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:57:39.398533 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 10:57:39.401792 0 10 4 | B1->B0 | 2c2c 2c2c | 0 0 | (1 0) (1 1)
1482 10:57:39.408371 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:57:39.411765 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:57:39.415087 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:57:39.421597 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:57:39.425254 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:57:39.428245 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:57:39.434928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:57:39.438239 0 11 4 | B1->B0 | 2f2f 3b3b | 0 0 | (0 0) (0 0)
1490 10:57:39.441550 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 10:57:39.448171 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 10:57:39.451583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 10:57:39.454925 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 10:57:39.461303 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:57:39.464786 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:57:39.468000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 10:57:39.474730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 10:57:39.478116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 10:57:39.481524 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 10:57:39.488395 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 10:57:39.491562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:57:39.495123 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:57:39.501678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:57:39.504963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:57:39.507913 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:57:39.514570 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:57:39.518040 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:57:39.522017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:57:39.527888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:57:39.531492 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:57:39.534527 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:57:39.541345 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:57:39.544335 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1514 10:57:39.547750 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 10:57:39.551288 Total UI for P1: 0, mck2ui 16
1516 10:57:39.554274 best dqsien dly found for B0: ( 0, 14, 4)
1517 10:57:39.557667 Total UI for P1: 0, mck2ui 16
1518 10:57:39.560972 best dqsien dly found for B1: ( 0, 14, 6)
1519 10:57:39.564455 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1520 10:57:39.567440 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 10:57:39.567539
1522 10:57:39.570740 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 10:57:39.577456 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 10:57:39.577529 [Gating] SW calibration Done
1525 10:57:39.577591 ==
1526 10:57:39.580947 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 10:57:39.587796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 10:57:39.587894 ==
1529 10:57:39.587994 RX Vref Scan: 0
1530 10:57:39.588081
1531 10:57:39.590978 RX Vref 0 -> 0, step: 1
1532 10:57:39.591072
1533 10:57:39.594144 RX Delay -130 -> 252, step: 16
1534 10:57:39.597275 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 10:57:39.600570 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1536 10:57:39.604316 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 10:57:39.610443 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 10:57:39.614270 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1539 10:57:39.617340 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1540 10:57:39.620867 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1541 10:57:39.623898 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1542 10:57:39.630563 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1543 10:57:39.633935 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1544 10:57:39.637343 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1545 10:57:39.640943 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1546 10:57:39.643804 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 10:57:39.650628 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1548 10:57:39.653928 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1549 10:57:39.657043 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1550 10:57:39.657125 ==
1551 10:57:39.660539 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 10:57:39.663974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 10:57:39.664060 ==
1554 10:57:39.667519 DQS Delay:
1555 10:57:39.667604 DQS0 = 0, DQS1 = 0
1556 10:57:39.670724 DQM Delay:
1557 10:57:39.670805 DQM0 = 91, DQM1 = 83
1558 10:57:39.670869 DQ Delay:
1559 10:57:39.673938 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1560 10:57:39.677199 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1561 10:57:39.680689 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1562 10:57:39.683735 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1563 10:57:39.683817
1564 10:57:39.687255
1565 10:57:39.687340 ==
1566 10:57:39.690760 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 10:57:39.693981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 10:57:39.694063 ==
1569 10:57:39.694127
1570 10:57:39.694186
1571 10:57:39.697336 TX Vref Scan disable
1572 10:57:39.697417 == TX Byte 0 ==
1573 10:57:39.703757 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1574 10:57:39.707119 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1575 10:57:39.707201 == TX Byte 1 ==
1576 10:57:39.713863 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 10:57:39.717090 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 10:57:39.717172 ==
1579 10:57:39.720155 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 10:57:39.723607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 10:57:39.723689 ==
1582 10:57:39.737068 TX Vref=22, minBit 8, minWin=27, winSum=450
1583 10:57:39.740336 TX Vref=24, minBit 15, minWin=27, winSum=454
1584 10:57:39.743485 TX Vref=26, minBit 15, minWin=27, winSum=456
1585 10:57:39.746897 TX Vref=28, minBit 1, minWin=28, winSum=458
1586 10:57:39.750404 TX Vref=30, minBit 9, minWin=28, winSum=462
1587 10:57:39.756963 TX Vref=32, minBit 8, minWin=28, winSum=459
1588 10:57:39.760603 [TxChooseVref] Worse bit 9, Min win 28, Win sum 462, Final Vref 30
1589 10:57:39.760685
1590 10:57:39.763436 Final TX Range 1 Vref 30
1591 10:57:39.763519
1592 10:57:39.763583 ==
1593 10:57:39.766994 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 10:57:39.770271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 10:57:39.773971 ==
1596 10:57:39.774053
1597 10:57:39.774117
1598 10:57:39.774177 TX Vref Scan disable
1599 10:57:39.777212 == TX Byte 0 ==
1600 10:57:39.780499 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1601 10:57:39.783891 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1602 10:57:39.787828 == TX Byte 1 ==
1603 10:57:39.790841 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 10:57:39.794095 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 10:57:39.794178
1606 10:57:39.797506 [DATLAT]
1607 10:57:39.797588 Freq=800, CH1 RK0
1608 10:57:39.797654
1609 10:57:39.800929 DATLAT Default: 0xa
1610 10:57:39.801011 0, 0xFFFF, sum = 0
1611 10:57:39.804246 1, 0xFFFF, sum = 0
1612 10:57:39.804330 2, 0xFFFF, sum = 0
1613 10:57:39.807341 3, 0xFFFF, sum = 0
1614 10:57:39.807428 4, 0xFFFF, sum = 0
1615 10:57:39.810724 5, 0xFFFF, sum = 0
1616 10:57:39.810808 6, 0xFFFF, sum = 0
1617 10:57:39.813732 7, 0xFFFF, sum = 0
1618 10:57:39.817584 8, 0xFFFF, sum = 0
1619 10:57:39.817663 9, 0x0, sum = 1
1620 10:57:39.817726 10, 0x0, sum = 2
1621 10:57:39.820587 11, 0x0, sum = 3
1622 10:57:39.820657 12, 0x0, sum = 4
1623 10:57:39.823585 best_step = 10
1624 10:57:39.823653
1625 10:57:39.823712 ==
1626 10:57:39.827211 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 10:57:39.830205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 10:57:39.830275 ==
1629 10:57:39.833738 RX Vref Scan: 1
1630 10:57:39.833813
1631 10:57:39.833874 Set Vref Range= 32 -> 127
1632 10:57:39.833932
1633 10:57:39.836884 RX Vref 32 -> 127, step: 1
1634 10:57:39.836951
1635 10:57:39.840100 RX Delay -95 -> 252, step: 8
1636 10:57:39.840176
1637 10:57:39.843774 Set Vref, RX VrefLevel [Byte0]: 32
1638 10:57:39.846935 [Byte1]: 32
1639 10:57:39.847013
1640 10:57:39.850476 Set Vref, RX VrefLevel [Byte0]: 33
1641 10:57:39.853328 [Byte1]: 33
1642 10:57:39.857246
1643 10:57:39.857316 Set Vref, RX VrefLevel [Byte0]: 34
1644 10:57:39.860522 [Byte1]: 34
1645 10:57:39.865066
1646 10:57:39.865142 Set Vref, RX VrefLevel [Byte0]: 35
1647 10:57:39.868181 [Byte1]: 35
1648 10:57:39.872584
1649 10:57:39.872653 Set Vref, RX VrefLevel [Byte0]: 36
1650 10:57:39.876204 [Byte1]: 36
1651 10:57:39.880098
1652 10:57:39.880167 Set Vref, RX VrefLevel [Byte0]: 37
1653 10:57:39.883477 [Byte1]: 37
1654 10:57:39.887915
1655 10:57:39.887983 Set Vref, RX VrefLevel [Byte0]: 38
1656 10:57:39.890956 [Byte1]: 38
1657 10:57:39.895216
1658 10:57:39.895286 Set Vref, RX VrefLevel [Byte0]: 39
1659 10:57:39.898439 [Byte1]: 39
1660 10:57:39.902951
1661 10:57:39.903037 Set Vref, RX VrefLevel [Byte0]: 40
1662 10:57:39.906542 [Byte1]: 40
1663 10:57:39.910749
1664 10:57:39.910900 Set Vref, RX VrefLevel [Byte0]: 41
1665 10:57:39.913746 [Byte1]: 41
1666 10:57:39.918142
1667 10:57:39.918259 Set Vref, RX VrefLevel [Byte0]: 42
1668 10:57:39.921666 [Byte1]: 42
1669 10:57:39.925566
1670 10:57:39.925678 Set Vref, RX VrefLevel [Byte0]: 43
1671 10:57:39.929042 [Byte1]: 43
1672 10:57:39.933450
1673 10:57:39.933530 Set Vref, RX VrefLevel [Byte0]: 44
1674 10:57:39.939752 [Byte1]: 44
1675 10:57:39.939833
1676 10:57:39.942937 Set Vref, RX VrefLevel [Byte0]: 45
1677 10:57:39.946734 [Byte1]: 45
1678 10:57:39.946806
1679 10:57:39.949936 Set Vref, RX VrefLevel [Byte0]: 46
1680 10:57:39.953586 [Byte1]: 46
1681 10:57:39.953665
1682 10:57:39.956565 Set Vref, RX VrefLevel [Byte0]: 47
1683 10:57:39.959831 [Byte1]: 47
1684 10:57:39.964051
1685 10:57:39.964145 Set Vref, RX VrefLevel [Byte0]: 48
1686 10:57:39.967083 [Byte1]: 48
1687 10:57:39.971555
1688 10:57:39.971625 Set Vref, RX VrefLevel [Byte0]: 49
1689 10:57:39.974926 [Byte1]: 49
1690 10:57:39.979209
1691 10:57:39.979279 Set Vref, RX VrefLevel [Byte0]: 50
1692 10:57:39.982314 [Byte1]: 50
1693 10:57:39.986477
1694 10:57:39.986547 Set Vref, RX VrefLevel [Byte0]: 51
1695 10:57:39.990019 [Byte1]: 51
1696 10:57:39.994136
1697 10:57:39.994213 Set Vref, RX VrefLevel [Byte0]: 52
1698 10:57:39.997686 [Byte1]: 52
1699 10:57:40.001753
1700 10:57:40.001823 Set Vref, RX VrefLevel [Byte0]: 53
1701 10:57:40.004852 [Byte1]: 53
1702 10:57:40.009203
1703 10:57:40.009281 Set Vref, RX VrefLevel [Byte0]: 54
1704 10:57:40.012476 [Byte1]: 54
1705 10:57:40.017014
1706 10:57:40.017099 Set Vref, RX VrefLevel [Byte0]: 55
1707 10:57:40.019934 [Byte1]: 55
1708 10:57:40.024591
1709 10:57:40.024697 Set Vref, RX VrefLevel [Byte0]: 56
1710 10:57:40.027727 [Byte1]: 56
1711 10:57:40.032038
1712 10:57:40.032118 Set Vref, RX VrefLevel [Byte0]: 57
1713 10:57:40.035299 [Byte1]: 57
1714 10:57:40.039509
1715 10:57:40.039593 Set Vref, RX VrefLevel [Byte0]: 58
1716 10:57:40.043007 [Byte1]: 58
1717 10:57:40.047130
1718 10:57:40.047210 Set Vref, RX VrefLevel [Byte0]: 59
1719 10:57:40.050437 [Byte1]: 59
1720 10:57:40.054969
1721 10:57:40.055049 Set Vref, RX VrefLevel [Byte0]: 60
1722 10:57:40.058190 [Byte1]: 60
1723 10:57:40.062644
1724 10:57:40.062725 Set Vref, RX VrefLevel [Byte0]: 61
1725 10:57:40.065637 [Byte1]: 61
1726 10:57:40.070060
1727 10:57:40.070141 Set Vref, RX VrefLevel [Byte0]: 62
1728 10:57:40.073467 [Byte1]: 62
1729 10:57:40.077840
1730 10:57:40.077922 Set Vref, RX VrefLevel [Byte0]: 63
1731 10:57:40.080879 [Byte1]: 63
1732 10:57:40.085561
1733 10:57:40.085668 Set Vref, RX VrefLevel [Byte0]: 64
1734 10:57:40.088669 [Byte1]: 64
1735 10:57:40.092676
1736 10:57:40.092787 Set Vref, RX VrefLevel [Byte0]: 65
1737 10:57:40.096186 [Byte1]: 65
1738 10:57:40.100385
1739 10:57:40.100466 Set Vref, RX VrefLevel [Byte0]: 66
1740 10:57:40.103774 [Byte1]: 66
1741 10:57:40.108264
1742 10:57:40.108345 Set Vref, RX VrefLevel [Byte0]: 67
1743 10:57:40.111262 [Byte1]: 67
1744 10:57:40.115811
1745 10:57:40.115892 Set Vref, RX VrefLevel [Byte0]: 68
1746 10:57:40.118930 [Byte1]: 68
1747 10:57:40.123318
1748 10:57:40.123398 Set Vref, RX VrefLevel [Byte0]: 69
1749 10:57:40.126728 [Byte1]: 69
1750 10:57:40.131094
1751 10:57:40.131175 Set Vref, RX VrefLevel [Byte0]: 70
1752 10:57:40.134138 [Byte1]: 70
1753 10:57:40.138532
1754 10:57:40.138613 Set Vref, RX VrefLevel [Byte0]: 71
1755 10:57:40.142118 [Byte1]: 71
1756 10:57:40.146088
1757 10:57:40.146169 Set Vref, RX VrefLevel [Byte0]: 72
1758 10:57:40.149328 [Byte1]: 72
1759 10:57:40.153823
1760 10:57:40.153904 Set Vref, RX VrefLevel [Byte0]: 73
1761 10:57:40.157064 [Byte1]: 73
1762 10:57:40.161095
1763 10:57:40.161176 Set Vref, RX VrefLevel [Byte0]: 74
1764 10:57:40.164949 [Byte1]: 74
1765 10:57:40.168700
1766 10:57:40.168796 Set Vref, RX VrefLevel [Byte0]: 75
1767 10:57:40.172000 [Byte1]: 75
1768 10:57:40.176329
1769 10:57:40.176410 Set Vref, RX VrefLevel [Byte0]: 76
1770 10:57:40.179623 [Byte1]: 76
1771 10:57:40.184535
1772 10:57:40.184616 Set Vref, RX VrefLevel [Byte0]: 77
1773 10:57:40.187387 [Byte1]: 77
1774 10:57:40.191831
1775 10:57:40.191923 Final RX Vref Byte 0 = 50 to rank0
1776 10:57:40.195045 Final RX Vref Byte 1 = 63 to rank0
1777 10:57:40.198182 Final RX Vref Byte 0 = 50 to rank1
1778 10:57:40.201565 Final RX Vref Byte 1 = 63 to rank1==
1779 10:57:40.205140 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 10:57:40.212059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 10:57:40.212141 ==
1782 10:57:40.212206 DQS Delay:
1783 10:57:40.212266 DQS0 = 0, DQS1 = 0
1784 10:57:40.215113 DQM Delay:
1785 10:57:40.215194 DQM0 = 92, DQM1 = 83
1786 10:57:40.218352 DQ Delay:
1787 10:57:40.221759 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1788 10:57:40.224685 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1789 10:57:40.228148 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1790 10:57:40.231451 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1791 10:57:40.231533
1792 10:57:40.231596
1793 10:57:40.238583 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 398 ps
1794 10:57:40.241788 CH1 RK0: MR19=606, MR18=2E4C
1795 10:57:40.248414 CH1_RK0: MR19=0x606, MR18=0x2E4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1796 10:57:40.248496
1797 10:57:40.251597 ----->DramcWriteLeveling(PI) begin...
1798 10:57:40.251680 ==
1799 10:57:40.254971 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 10:57:40.258388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 10:57:40.258470 ==
1802 10:57:40.261451 Write leveling (Byte 0): 26 => 26
1803 10:57:40.264955 Write leveling (Byte 1): 28 => 28
1804 10:57:40.268037 DramcWriteLeveling(PI) end<-----
1805 10:57:40.268118
1806 10:57:40.268182 ==
1807 10:57:40.271979 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 10:57:40.274729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 10:57:40.274814 ==
1810 10:57:40.278183 [Gating] SW mode calibration
1811 10:57:40.284640 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 10:57:40.291526 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 10:57:40.294911 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 10:57:40.297878 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1815 10:57:40.305013 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:57:40.308113 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:57:40.311559 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:57:40.317829 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:57:40.321549 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:57:40.325043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:57:40.331194 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:57:40.334536 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:57:40.337772 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:57:40.344671 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:57:40.347796 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:57:40.351187 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:57:40.357635 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:57:40.361285 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:57:40.364221 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1830 10:57:40.370839 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1831 10:57:40.374073 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1832 10:57:40.377615 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:57:40.384153 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:57:40.387510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:57:40.391107 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:57:40.397727 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:57:40.401148 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:57:40.404318 0 9 4 | B1->B0 | 2525 2626 | 0 1 | (0 0) (1 1)
1839 10:57:40.411037 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1840 10:57:40.414782 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 10:57:40.417731 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 10:57:40.421192 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 10:57:40.427806 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 10:57:40.430766 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 10:57:40.434089 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 10:57:40.440745 0 10 4 | B1->B0 | 2f2f 3030 | 1 0 | (1 0) (0 1)
1847 10:57:40.444220 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:57:40.447424 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:57:40.454516 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 10:57:40.457328 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 10:57:40.460988 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 10:57:40.467388 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 10:57:40.470848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:57:40.474053 0 11 4 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
1855 10:57:40.480752 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 10:57:40.483962 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 10:57:40.487397 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 10:57:40.493969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 10:57:40.497287 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 10:57:40.500505 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 10:57:40.507004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 10:57:40.510590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1863 10:57:40.514007 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:57:40.520504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:57:40.523962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:57:40.527054 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:57:40.534029 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:57:40.537326 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:57:40.540291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:57:40.546991 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:57:40.550532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:57:40.553912 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:57:40.560693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:57:40.563593 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:57:40.567111 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:57:40.570473 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:57:40.577066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1878 10:57:40.580153 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 10:57:40.583872 Total UI for P1: 0, mck2ui 16
1880 10:57:40.587021 best dqsien dly found for B0: ( 0, 14, 0)
1881 10:57:40.590387 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1882 10:57:40.593627 Total UI for P1: 0, mck2ui 16
1883 10:57:40.597192 best dqsien dly found for B1: ( 0, 14, 2)
1884 10:57:40.600383 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1885 10:57:40.603780 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1886 10:57:40.603863
1887 10:57:40.610714 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1888 10:57:40.613595 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1889 10:57:40.616939 [Gating] SW calibration Done
1890 10:57:40.617022 ==
1891 10:57:40.620288 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 10:57:40.623743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 10:57:40.623826 ==
1894 10:57:40.623892 RX Vref Scan: 0
1895 10:57:40.623954
1896 10:57:40.626906 RX Vref 0 -> 0, step: 1
1897 10:57:40.626988
1898 10:57:40.630089 RX Delay -130 -> 252, step: 16
1899 10:57:40.633602 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1900 10:57:40.636918 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1901 10:57:40.643689 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1902 10:57:40.646520 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1903 10:57:40.649806 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1904 10:57:40.653395 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1905 10:57:40.656597 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1906 10:57:40.663139 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1907 10:57:40.666305 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1908 10:57:40.669783 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1909 10:57:40.673160 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1910 10:57:40.676916 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1911 10:57:40.682985 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1912 10:57:40.686415 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1913 10:57:40.689942 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1914 10:57:40.692871 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1915 10:57:40.692953 ==
1916 10:57:40.696201 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 10:57:40.703014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 10:57:40.703098 ==
1919 10:57:40.703163 DQS Delay:
1920 10:57:40.706419 DQS0 = 0, DQS1 = 0
1921 10:57:40.706501 DQM Delay:
1922 10:57:40.706567 DQM0 = 91, DQM1 = 80
1923 10:57:40.709913 DQ Delay:
1924 10:57:40.712761 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1925 10:57:40.716227 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =85
1926 10:57:40.719442 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
1927 10:57:40.722758 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1928 10:57:40.722841
1929 10:57:40.722906
1930 10:57:40.722967 ==
1931 10:57:40.726388 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 10:57:40.729736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 10:57:40.729820 ==
1934 10:57:40.729886
1935 10:57:40.729947
1936 10:57:40.732920 TX Vref Scan disable
1937 10:57:40.733002 == TX Byte 0 ==
1938 10:57:40.739537 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1939 10:57:40.743133 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1940 10:57:40.743216 == TX Byte 1 ==
1941 10:57:40.749835 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1942 10:57:40.753032 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1943 10:57:40.753115 ==
1944 10:57:40.756321 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 10:57:40.759560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 10:57:40.759644 ==
1947 10:57:40.773455 TX Vref=22, minBit 13, minWin=27, winSum=453
1948 10:57:40.776999 TX Vref=24, minBit 13, minWin=27, winSum=459
1949 10:57:40.780552 TX Vref=26, minBit 10, minWin=28, winSum=460
1950 10:57:40.783590 TX Vref=28, minBit 8, minWin=28, winSum=460
1951 10:57:40.787065 TX Vref=30, minBit 8, minWin=28, winSum=460
1952 10:57:40.793778 TX Vref=32, minBit 9, minWin=27, winSum=458
1953 10:57:40.796822 [TxChooseVref] Worse bit 10, Min win 28, Win sum 460, Final Vref 26
1954 10:57:40.796905
1955 10:57:40.800206 Final TX Range 1 Vref 26
1956 10:57:40.800293
1957 10:57:40.800361 ==
1958 10:57:40.803943 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 10:57:40.807063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 10:57:40.810478 ==
1961 10:57:40.810581
1962 10:57:40.810648
1963 10:57:40.810709 TX Vref Scan disable
1964 10:57:40.813918 == TX Byte 0 ==
1965 10:57:40.817030 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1966 10:57:40.824025 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1967 10:57:40.824107 == TX Byte 1 ==
1968 10:57:40.827215 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1969 10:57:40.833480 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1970 10:57:40.833563
1971 10:57:40.833630 [DATLAT]
1972 10:57:40.833691 Freq=800, CH1 RK1
1973 10:57:40.833751
1974 10:57:40.837205 DATLAT Default: 0xa
1975 10:57:40.837288 0, 0xFFFF, sum = 0
1976 10:57:40.840238 1, 0xFFFF, sum = 0
1977 10:57:40.843826 2, 0xFFFF, sum = 0
1978 10:57:40.843910 3, 0xFFFF, sum = 0
1979 10:57:40.847013 4, 0xFFFF, sum = 0
1980 10:57:40.847098 5, 0xFFFF, sum = 0
1981 10:57:40.850251 6, 0xFFFF, sum = 0
1982 10:57:40.850335 7, 0xFFFF, sum = 0
1983 10:57:40.853749 8, 0xFFFF, sum = 0
1984 10:57:40.853833 9, 0x0, sum = 1
1985 10:57:40.856796 10, 0x0, sum = 2
1986 10:57:40.856881 11, 0x0, sum = 3
1987 10:57:40.856949 12, 0x0, sum = 4
1988 10:57:40.860188 best_step = 10
1989 10:57:40.860270
1990 10:57:40.860335 ==
1991 10:57:40.863561 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 10:57:40.866956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 10:57:40.867039 ==
1994 10:57:40.870457 RX Vref Scan: 0
1995 10:57:40.870540
1996 10:57:40.870605 RX Vref 0 -> 0, step: 1
1997 10:57:40.873439
1998 10:57:40.873522 RX Delay -95 -> 252, step: 8
1999 10:57:40.880370 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2000 10:57:40.883907 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2001 10:57:40.887542 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2002 10:57:40.890460 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2003 10:57:40.893908 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2004 10:57:40.900712 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2005 10:57:40.903755 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2006 10:57:40.907308 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2007 10:57:40.910612 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2008 10:57:40.913977 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2009 10:57:40.920555 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2010 10:57:40.923901 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2011 10:57:40.927334 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2012 10:57:40.930396 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2013 10:57:40.933862 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2014 10:57:40.940632 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2015 10:57:40.940716 ==
2016 10:57:40.943870 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 10:57:40.947231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 10:57:40.947315 ==
2019 10:57:40.947382 DQS Delay:
2020 10:57:40.950401 DQS0 = 0, DQS1 = 0
2021 10:57:40.950484 DQM Delay:
2022 10:57:40.953762 DQM0 = 90, DQM1 = 84
2023 10:57:40.953844 DQ Delay:
2024 10:57:40.957082 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2025 10:57:40.960700 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2026 10:57:40.963785 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2027 10:57:40.966961 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2028 10:57:40.967044
2029 10:57:40.967110
2030 10:57:40.976948 [DQSOSCAuto] RK1, (LSB)MR18= 0x390e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2031 10:57:40.977032 CH1 RK1: MR19=606, MR18=390E
2032 10:57:40.983580 CH1_RK1: MR19=0x606, MR18=0x390E, DQSOSC=395, MR23=63, INC=94, DEC=63
2033 10:57:40.987110 [RxdqsGatingPostProcess] freq 800
2034 10:57:40.993687 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 10:57:40.997108 Pre-setting of DQS Precalculation
2036 10:57:41.000397 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 10:57:41.006819 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 10:57:41.013465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 10:57:41.013549
2040 10:57:41.016711
2041 10:57:41.016828 [Calibration Summary] 1600 Mbps
2042 10:57:41.020180 CH 0, Rank 0
2043 10:57:41.020263 SW Impedance : PASS
2044 10:57:41.023561 DUTY Scan : NO K
2045 10:57:41.027067 ZQ Calibration : PASS
2046 10:57:41.027150 Jitter Meter : NO K
2047 10:57:41.030280 CBT Training : PASS
2048 10:57:41.033717 Write leveling : PASS
2049 10:57:41.033800 RX DQS gating : PASS
2050 10:57:41.036948 RX DQ/DQS(RDDQC) : PASS
2051 10:57:41.040446 TX DQ/DQS : PASS
2052 10:57:41.040530 RX DATLAT : PASS
2053 10:57:41.043229 RX DQ/DQS(Engine): PASS
2054 10:57:41.046989 TX OE : NO K
2055 10:57:41.047072 All Pass.
2056 10:57:41.047138
2057 10:57:41.047199 CH 0, Rank 1
2058 10:57:41.050008 SW Impedance : PASS
2059 10:57:41.053659 DUTY Scan : NO K
2060 10:57:41.053743 ZQ Calibration : PASS
2061 10:57:41.056654 Jitter Meter : NO K
2062 10:57:41.060109 CBT Training : PASS
2063 10:57:41.060192 Write leveling : PASS
2064 10:57:41.063211 RX DQS gating : PASS
2065 10:57:41.063295 RX DQ/DQS(RDDQC) : PASS
2066 10:57:41.066618 TX DQ/DQS : PASS
2067 10:57:41.069777 RX DATLAT : PASS
2068 10:57:41.069861 RX DQ/DQS(Engine): PASS
2069 10:57:41.073357 TX OE : NO K
2070 10:57:41.073440 All Pass.
2071 10:57:41.073506
2072 10:57:41.076721 CH 1, Rank 0
2073 10:57:41.076809 SW Impedance : PASS
2074 10:57:41.079781 DUTY Scan : NO K
2075 10:57:41.083369 ZQ Calibration : PASS
2076 10:57:41.083452 Jitter Meter : NO K
2077 10:57:41.086855 CBT Training : PASS
2078 10:57:41.090026 Write leveling : PASS
2079 10:57:41.090109 RX DQS gating : PASS
2080 10:57:41.093154 RX DQ/DQS(RDDQC) : PASS
2081 10:57:41.096740 TX DQ/DQS : PASS
2082 10:57:41.096871 RX DATLAT : PASS
2083 10:57:41.099727 RX DQ/DQS(Engine): PASS
2084 10:57:41.103166 TX OE : NO K
2085 10:57:41.103249 All Pass.
2086 10:57:41.103316
2087 10:57:41.103377 CH 1, Rank 1
2088 10:57:41.106489 SW Impedance : PASS
2089 10:57:41.109732 DUTY Scan : NO K
2090 10:57:41.109815 ZQ Calibration : PASS
2091 10:57:41.113596 Jitter Meter : NO K
2092 10:57:41.113679 CBT Training : PASS
2093 10:57:41.116494 Write leveling : PASS
2094 10:57:41.119737 RX DQS gating : PASS
2095 10:57:41.119820 RX DQ/DQS(RDDQC) : PASS
2096 10:57:41.123109 TX DQ/DQS : PASS
2097 10:57:41.126559 RX DATLAT : PASS
2098 10:57:41.126642 RX DQ/DQS(Engine): PASS
2099 10:57:41.130199 TX OE : NO K
2100 10:57:41.130283 All Pass.
2101 10:57:41.130349
2102 10:57:41.133030 DramC Write-DBI off
2103 10:57:41.136679 PER_BANK_REFRESH: Hybrid Mode
2104 10:57:41.136822 TX_TRACKING: ON
2105 10:57:41.140116 [GetDramInforAfterCalByMRR] Vendor 6.
2106 10:57:41.142905 [GetDramInforAfterCalByMRR] Revision 606.
2107 10:57:41.146340 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 10:57:41.149637 MR0 0x3b3b
2109 10:57:41.149720 MR8 0x5151
2110 10:57:41.153117 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 10:57:41.153200
2112 10:57:41.156207 MR0 0x3b3b
2113 10:57:41.156290 MR8 0x5151
2114 10:57:41.159842 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 10:57:41.159925
2116 10:57:41.169534 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 10:57:41.172748 [FAST_K] Save calibration result to emmc
2118 10:57:41.175959 [FAST_K] Save calibration result to emmc
2119 10:57:41.179306 dram_init: config_dvfs: 1
2120 10:57:41.183000 dramc_set_vcore_voltage set vcore to 662500
2121 10:57:41.183084 Read voltage for 1200, 2
2122 10:57:41.185809 Vio18 = 0
2123 10:57:41.185892 Vcore = 662500
2124 10:57:41.185958 Vdram = 0
2125 10:57:41.189498 Vddq = 0
2126 10:57:41.189581 Vmddr = 0
2127 10:57:41.192892 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 10:57:41.199610 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 10:57:41.202854 MEM_TYPE=3, freq_sel=15
2130 10:57:41.206091 sv_algorithm_assistance_LP4_1600
2131 10:57:41.209368 ============ PULL DRAM RESETB DOWN ============
2132 10:57:41.212488 ========== PULL DRAM RESETB DOWN end =========
2133 10:57:41.219145 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 10:57:41.222369 ===================================
2135 10:57:41.222452 LPDDR4 DRAM CONFIGURATION
2136 10:57:41.225948 ===================================
2137 10:57:41.229043 EX_ROW_EN[0] = 0x0
2138 10:57:41.229126 EX_ROW_EN[1] = 0x0
2139 10:57:41.232524 LP4Y_EN = 0x0
2140 10:57:41.232636 WORK_FSP = 0x0
2141 10:57:41.236088 WL = 0x4
2142 10:57:41.236171 RL = 0x4
2143 10:57:41.239425 BL = 0x2
2144 10:57:41.242280 RPST = 0x0
2145 10:57:41.242362 RD_PRE = 0x0
2146 10:57:41.245798 WR_PRE = 0x1
2147 10:57:41.245881 WR_PST = 0x0
2148 10:57:41.248958 DBI_WR = 0x0
2149 10:57:41.249041 DBI_RD = 0x0
2150 10:57:41.252608 OTF = 0x1
2151 10:57:41.255946 ===================================
2152 10:57:41.259145 ===================================
2153 10:57:41.259228 ANA top config
2154 10:57:41.262330 ===================================
2155 10:57:41.265485 DLL_ASYNC_EN = 0
2156 10:57:41.269072 ALL_SLAVE_EN = 0
2157 10:57:41.269154 NEW_RANK_MODE = 1
2158 10:57:41.272515 DLL_IDLE_MODE = 1
2159 10:57:41.275541 LP45_APHY_COMB_EN = 1
2160 10:57:41.278734 TX_ODT_DIS = 1
2161 10:57:41.278818 NEW_8X_MODE = 1
2162 10:57:41.282054 ===================================
2163 10:57:41.285385 ===================================
2164 10:57:41.288886 data_rate = 2400
2165 10:57:41.291875 CKR = 1
2166 10:57:41.295497 DQ_P2S_RATIO = 8
2167 10:57:41.298865 ===================================
2168 10:57:41.302106 CA_P2S_RATIO = 8
2169 10:57:41.305466 DQ_CA_OPEN = 0
2170 10:57:41.309025 DQ_SEMI_OPEN = 0
2171 10:57:41.309107 CA_SEMI_OPEN = 0
2172 10:57:41.311973 CA_FULL_RATE = 0
2173 10:57:41.315509 DQ_CKDIV4_EN = 0
2174 10:57:41.318928 CA_CKDIV4_EN = 0
2175 10:57:41.321931 CA_PREDIV_EN = 0
2176 10:57:41.325171 PH8_DLY = 17
2177 10:57:41.325253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 10:57:41.328719 DQ_AAMCK_DIV = 4
2179 10:57:41.331829 CA_AAMCK_DIV = 4
2180 10:57:41.335200 CA_ADMCK_DIV = 4
2181 10:57:41.338687 DQ_TRACK_CA_EN = 0
2182 10:57:41.341935 CA_PICK = 1200
2183 10:57:41.345578 CA_MCKIO = 1200
2184 10:57:41.345676 MCKIO_SEMI = 0
2185 10:57:41.348435 PLL_FREQ = 2366
2186 10:57:41.351589 DQ_UI_PI_RATIO = 32
2187 10:57:41.355227 CA_UI_PI_RATIO = 0
2188 10:57:41.358460 ===================================
2189 10:57:41.361621 ===================================
2190 10:57:41.365105 memory_type:LPDDR4
2191 10:57:41.365173 GP_NUM : 10
2192 10:57:41.368543 SRAM_EN : 1
2193 10:57:41.368636 MD32_EN : 0
2194 10:57:41.371962 ===================================
2195 10:57:41.374990 [ANA_INIT] >>>>>>>>>>>>>>
2196 10:57:41.378681 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 10:57:41.381689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 10:57:41.385124 ===================================
2199 10:57:41.388198 data_rate = 2400,PCW = 0X5b00
2200 10:57:41.391459 ===================================
2201 10:57:41.394759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 10:57:41.401461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 10:57:41.405129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 10:57:41.411242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 10:57:41.414911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 10:57:41.418164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 10:57:41.418260 [ANA_INIT] flow start
2208 10:57:41.421511 [ANA_INIT] PLL >>>>>>>>
2209 10:57:41.424656 [ANA_INIT] PLL <<<<<<<<
2210 10:57:41.424753 [ANA_INIT] MIDPI >>>>>>>>
2211 10:57:41.428004 [ANA_INIT] MIDPI <<<<<<<<
2212 10:57:41.431274 [ANA_INIT] DLL >>>>>>>>
2213 10:57:41.434623 [ANA_INIT] DLL <<<<<<<<
2214 10:57:41.434719 [ANA_INIT] flow end
2215 10:57:41.438206 ============ LP4 DIFF to SE enter ============
2216 10:57:41.444475 ============ LP4 DIFF to SE exit ============
2217 10:57:41.444573 [ANA_INIT] <<<<<<<<<<<<<
2218 10:57:41.447959 [Flow] Enable top DCM control >>>>>
2219 10:57:41.451171 [Flow] Enable top DCM control <<<<<
2220 10:57:41.454510 Enable DLL master slave shuffle
2221 10:57:41.461308 ==============================================================
2222 10:57:41.461404 Gating Mode config
2223 10:57:41.468103 ==============================================================
2224 10:57:41.471202 Config description:
2225 10:57:41.481045 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 10:57:41.487592 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 10:57:41.491010 SELPH_MODE 0: By rank 1: By Phase
2228 10:57:41.497678 ==============================================================
2229 10:57:41.501173 GAT_TRACK_EN = 1
2230 10:57:41.501241 RX_GATING_MODE = 2
2231 10:57:41.504674 RX_GATING_TRACK_MODE = 2
2232 10:57:41.507725 SELPH_MODE = 1
2233 10:57:41.511186 PICG_EARLY_EN = 1
2234 10:57:41.514278 VALID_LAT_VALUE = 1
2235 10:57:41.520965 ==============================================================
2236 10:57:41.524539 Enter into Gating configuration >>>>
2237 10:57:41.527392 Exit from Gating configuration <<<<
2238 10:57:41.530868 Enter into DVFS_PRE_config >>>>>
2239 10:57:41.541023 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 10:57:41.544140 Exit from DVFS_PRE_config <<<<<
2241 10:57:41.547421 Enter into PICG configuration >>>>
2242 10:57:41.550987 Exit from PICG configuration <<<<
2243 10:57:41.554578 [RX_INPUT] configuration >>>>>
2244 10:57:41.554664 [RX_INPUT] configuration <<<<<
2245 10:57:41.560691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 10:57:41.567398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 10:57:41.573834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 10:57:41.577241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 10:57:41.583883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 10:57:41.590689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 10:57:41.593982 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 10:57:41.600459 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 10:57:41.603837 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 10:57:41.606857 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 10:57:41.610293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 10:57:41.617010 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 10:57:41.620253 ===================================
2258 10:57:41.620328 LPDDR4 DRAM CONFIGURATION
2259 10:57:41.623848 ===================================
2260 10:57:41.626889 EX_ROW_EN[0] = 0x0
2261 10:57:41.630315 EX_ROW_EN[1] = 0x0
2262 10:57:41.630390 LP4Y_EN = 0x0
2263 10:57:41.633709 WORK_FSP = 0x0
2264 10:57:41.633780 WL = 0x4
2265 10:57:41.636956 RL = 0x4
2266 10:57:41.637041 BL = 0x2
2267 10:57:41.640313 RPST = 0x0
2268 10:57:41.640383 RD_PRE = 0x0
2269 10:57:41.643493 WR_PRE = 0x1
2270 10:57:41.643563 WR_PST = 0x0
2271 10:57:41.647014 DBI_WR = 0x0
2272 10:57:41.647091 DBI_RD = 0x0
2273 10:57:41.650336 OTF = 0x1
2274 10:57:41.653376 ===================================
2275 10:57:41.657186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 10:57:41.660052 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 10:57:41.666774 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 10:57:41.670332 ===================================
2279 10:57:41.670413 LPDDR4 DRAM CONFIGURATION
2280 10:57:41.673360 ===================================
2281 10:57:41.676952 EX_ROW_EN[0] = 0x10
2282 10:57:41.677023 EX_ROW_EN[1] = 0x0
2283 10:57:41.680023 LP4Y_EN = 0x0
2284 10:57:41.683460 WORK_FSP = 0x0
2285 10:57:41.683534 WL = 0x4
2286 10:57:41.686957 RL = 0x4
2287 10:57:41.687026 BL = 0x2
2288 10:57:41.689992 RPST = 0x0
2289 10:57:41.690060 RD_PRE = 0x0
2290 10:57:41.693518 WR_PRE = 0x1
2291 10:57:41.693616 WR_PST = 0x0
2292 10:57:41.696674 DBI_WR = 0x0
2293 10:57:41.696775 DBI_RD = 0x0
2294 10:57:41.700042 OTF = 0x1
2295 10:57:41.703450 ===================================
2296 10:57:41.709816 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 10:57:41.709890 ==
2298 10:57:41.713181 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 10:57:41.716725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 10:57:41.716851 ==
2301 10:57:41.719992 [Duty_Offset_Calibration]
2302 10:57:41.720065 B0:2 B1:0 CA:1
2303 10:57:41.720124
2304 10:57:41.723367 [DutyScan_Calibration_Flow] k_type=0
2305 10:57:41.732438
2306 10:57:41.732541 ==CLK 0==
2307 10:57:41.735952 Final CLK duty delay cell = -4
2308 10:57:41.738802 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2309 10:57:41.742594 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2310 10:57:41.745561 [-4] AVG Duty = 4953%(X100)
2311 10:57:41.745629
2312 10:57:41.749449 CH0 CLK Duty spec in!! Max-Min= 156%
2313 10:57:41.752531 [DutyScan_Calibration_Flow] ====Done====
2314 10:57:41.752609
2315 10:57:41.755487 [DutyScan_Calibration_Flow] k_type=1
2316 10:57:41.771564
2317 10:57:41.771643 ==DQS 0 ==
2318 10:57:41.774765 Final DQS duty delay cell = 0
2319 10:57:41.778018 [0] MAX Duty = 5187%(X100), DQS PI = 30
2320 10:57:41.781181 [0] MIN Duty = 4938%(X100), DQS PI = 2
2321 10:57:41.781260 [0] AVG Duty = 5062%(X100)
2322 10:57:41.784621
2323 10:57:41.784700 ==DQS 1 ==
2324 10:57:41.787710 Final DQS duty delay cell = -4
2325 10:57:41.791026 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2326 10:57:41.794952 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2327 10:57:41.797597 [-4] AVG Duty = 5031%(X100)
2328 10:57:41.797676
2329 10:57:41.800806 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2330 10:57:41.800885
2331 10:57:41.804211 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2332 10:57:41.807727 [DutyScan_Calibration_Flow] ====Done====
2333 10:57:41.807805
2334 10:57:41.810772 [DutyScan_Calibration_Flow] k_type=3
2335 10:57:41.827330
2336 10:57:41.827426 ==DQM 0 ==
2337 10:57:41.830330 Final DQM duty delay cell = 0
2338 10:57:41.834061 [0] MAX Duty = 5062%(X100), DQS PI = 24
2339 10:57:41.837198 [0] MIN Duty = 4844%(X100), DQS PI = 0
2340 10:57:41.837266 [0] AVG Duty = 4953%(X100)
2341 10:57:41.840552
2342 10:57:41.840651 ==DQM 1 ==
2343 10:57:41.844043 Final DQM duty delay cell = -4
2344 10:57:41.846967 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2345 10:57:41.850274 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2346 10:57:41.853968 [-4] AVG Duty = 4906%(X100)
2347 10:57:41.854051
2348 10:57:41.856987 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2349 10:57:41.857079
2350 10:57:41.860668 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2351 10:57:41.863769 [DutyScan_Calibration_Flow] ====Done====
2352 10:57:41.863867
2353 10:57:41.867110 [DutyScan_Calibration_Flow] k_type=2
2354 10:57:41.884189
2355 10:57:41.884292 ==DQ 0 ==
2356 10:57:41.887082 Final DQ duty delay cell = -4
2357 10:57:41.890662 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2358 10:57:41.894209 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2359 10:57:41.897221 [-4] AVG Duty = 4953%(X100)
2360 10:57:41.897300
2361 10:57:41.897363 ==DQ 1 ==
2362 10:57:41.900949 Final DQ duty delay cell = 4
2363 10:57:41.903941 [4] MAX Duty = 5093%(X100), DQS PI = 4
2364 10:57:41.907078 [4] MIN Duty = 5031%(X100), DQS PI = 0
2365 10:57:41.907153 [4] AVG Duty = 5062%(X100)
2366 10:57:41.910482
2367 10:57:41.913652 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2368 10:57:41.913721
2369 10:57:41.916958 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2370 10:57:41.920621 [DutyScan_Calibration_Flow] ====Done====
2371 10:57:41.920689 ==
2372 10:57:41.923920 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 10:57:41.927021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 10:57:41.927118 ==
2375 10:57:41.930717 [Duty_Offset_Calibration]
2376 10:57:41.930787 B0:0 B1:-1 CA:2
2377 10:57:41.930848
2378 10:57:41.933948 [DutyScan_Calibration_Flow] k_type=0
2379 10:57:41.944180
2380 10:57:41.944253 ==CLK 0==
2381 10:57:41.947787 Final CLK duty delay cell = 0
2382 10:57:41.950959 [0] MAX Duty = 5156%(X100), DQS PI = 16
2383 10:57:41.954180 [0] MIN Duty = 4938%(X100), DQS PI = 44
2384 10:57:41.954252 [0] AVG Duty = 5047%(X100)
2385 10:57:41.957545
2386 10:57:41.960647 CH1 CLK Duty spec in!! Max-Min= 218%
2387 10:57:41.964316 [DutyScan_Calibration_Flow] ====Done====
2388 10:57:41.964388
2389 10:57:41.967237 [DutyScan_Calibration_Flow] k_type=1
2390 10:57:41.983893
2391 10:57:41.983972 ==DQS 0 ==
2392 10:57:41.986997 Final DQS duty delay cell = 0
2393 10:57:41.990528 [0] MAX Duty = 5093%(X100), DQS PI = 24
2394 10:57:41.993504 [0] MIN Duty = 4969%(X100), DQS PI = 0
2395 10:57:41.997054 [0] AVG Duty = 5031%(X100)
2396 10:57:41.997136
2397 10:57:41.997201 ==DQS 1 ==
2398 10:57:41.999961 Final DQS duty delay cell = 0
2399 10:57:42.003617 [0] MAX Duty = 5156%(X100), DQS PI = 0
2400 10:57:42.006909 [0] MIN Duty = 4875%(X100), DQS PI = 34
2401 10:57:42.010236 [0] AVG Duty = 5015%(X100)
2402 10:57:42.010318
2403 10:57:42.013426 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2404 10:57:42.013508
2405 10:57:42.017045 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2406 10:57:42.020345 [DutyScan_Calibration_Flow] ====Done====
2407 10:57:42.020444
2408 10:57:42.023269 [DutyScan_Calibration_Flow] k_type=3
2409 10:57:42.041038
2410 10:57:42.041120 ==DQM 0 ==
2411 10:57:42.044237 Final DQM duty delay cell = 4
2412 10:57:42.048387 [4] MAX Duty = 5093%(X100), DQS PI = 4
2413 10:57:42.050845 [4] MIN Duty = 4969%(X100), DQS PI = 28
2414 10:57:42.050928 [4] AVG Duty = 5031%(X100)
2415 10:57:42.054587
2416 10:57:42.054669 ==DQM 1 ==
2417 10:57:42.057493 Final DQM duty delay cell = 0
2418 10:57:42.060733 [0] MAX Duty = 5249%(X100), DQS PI = 58
2419 10:57:42.064358 [0] MIN Duty = 4875%(X100), DQS PI = 36
2420 10:57:42.067512 [0] AVG Duty = 5062%(X100)
2421 10:57:42.067595
2422 10:57:42.071139 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2423 10:57:42.071222
2424 10:57:42.074373 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2425 10:57:42.077414 [DutyScan_Calibration_Flow] ====Done====
2426 10:57:42.077497
2427 10:57:42.080869 [DutyScan_Calibration_Flow] k_type=2
2428 10:57:42.097667
2429 10:57:42.097749 ==DQ 0 ==
2430 10:57:42.100715 Final DQ duty delay cell = 0
2431 10:57:42.104077 [0] MAX Duty = 5062%(X100), DQS PI = 20
2432 10:57:42.107303 [0] MIN Duty = 4938%(X100), DQS PI = 0
2433 10:57:42.107386 [0] AVG Duty = 5000%(X100)
2434 10:57:42.107452
2435 10:57:42.111075 ==DQ 1 ==
2436 10:57:42.114119 Final DQ duty delay cell = 0
2437 10:57:42.117261 [0] MAX Duty = 5031%(X100), DQS PI = 2
2438 10:57:42.120786 [0] MIN Duty = 4813%(X100), DQS PI = 36
2439 10:57:42.120875 [0] AVG Duty = 4922%(X100)
2440 10:57:42.120939
2441 10:57:42.124278 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 10:57:42.124347
2443 10:57:42.127593 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2444 10:57:42.134147 [DutyScan_Calibration_Flow] ====Done====
2445 10:57:42.137363 nWR fixed to 30
2446 10:57:42.137433 [ModeRegInit_LP4] CH0 RK0
2447 10:57:42.140749 [ModeRegInit_LP4] CH0 RK1
2448 10:57:42.144088 [ModeRegInit_LP4] CH1 RK0
2449 10:57:42.144170 [ModeRegInit_LP4] CH1 RK1
2450 10:57:42.147626 match AC timing 7
2451 10:57:42.150705 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 10:57:42.154268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 10:57:42.160658 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 10:57:42.164068 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 10:57:42.170901 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 10:57:42.170975 ==
2457 10:57:42.174127 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 10:57:42.177340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 10:57:42.177411 ==
2460 10:57:42.184194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 10:57:42.187200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2462 10:57:42.197234 [CA 0] Center 38 (8~69) winsize 62
2463 10:57:42.200584 [CA 1] Center 38 (8~69) winsize 62
2464 10:57:42.204207 [CA 2] Center 35 (5~66) winsize 62
2465 10:57:42.207365 [CA 3] Center 35 (5~66) winsize 62
2466 10:57:42.210441 [CA 4] Center 34 (4~65) winsize 62
2467 10:57:42.213729 [CA 5] Center 33 (3~63) winsize 61
2468 10:57:42.213814
2469 10:57:42.217240 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2470 10:57:42.217324
2471 10:57:42.220540 [CATrainingPosCal] consider 1 rank data
2472 10:57:42.223871 u2DelayCellTimex100 = 270/100 ps
2473 10:57:42.227006 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2474 10:57:42.230301 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 10:57:42.237268 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 10:57:42.240387 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 10:57:42.243877 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 10:57:42.247570 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 10:57:42.247651
2480 10:57:42.250366 CA PerBit enable=1, Macro0, CA PI delay=33
2481 10:57:42.250448
2482 10:57:42.253741 [CBTSetCACLKResult] CA Dly = 33
2483 10:57:42.253823 CS Dly: 6 (0~37)
2484 10:57:42.256953 ==
2485 10:57:42.260072 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 10:57:42.263677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 10:57:42.263759 ==
2488 10:57:42.266646 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 10:57:42.273423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 10:57:42.282878 [CA 0] Center 39 (8~70) winsize 63
2491 10:57:42.286305 [CA 1] Center 38 (8~69) winsize 62
2492 10:57:42.289950 [CA 2] Center 35 (5~66) winsize 62
2493 10:57:42.292748 [CA 3] Center 35 (5~66) winsize 62
2494 10:57:42.296236 [CA 4] Center 34 (4~65) winsize 62
2495 10:57:42.299375 [CA 5] Center 34 (4~64) winsize 61
2496 10:57:42.299456
2497 10:57:42.302732 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2498 10:57:42.302803
2499 10:57:42.306314 [CATrainingPosCal] consider 2 rank data
2500 10:57:42.309436 u2DelayCellTimex100 = 270/100 ps
2501 10:57:42.312783 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2502 10:57:42.319600 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 10:57:42.322904 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 10:57:42.326190 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 10:57:42.329195 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 10:57:42.332699 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2507 10:57:42.332819
2508 10:57:42.335987 CA PerBit enable=1, Macro0, CA PI delay=33
2509 10:57:42.336071
2510 10:57:42.339227 [CBTSetCACLKResult] CA Dly = 33
2511 10:57:42.339310 CS Dly: 7 (0~39)
2512 10:57:42.342754
2513 10:57:42.346028 ----->DramcWriteLeveling(PI) begin...
2514 10:57:42.346113 ==
2515 10:57:42.349477 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 10:57:42.352515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 10:57:42.352599 ==
2518 10:57:42.356043 Write leveling (Byte 0): 35 => 35
2519 10:57:42.359145 Write leveling (Byte 1): 30 => 30
2520 10:57:42.362755 DramcWriteLeveling(PI) end<-----
2521 10:57:42.362839
2522 10:57:42.362923 ==
2523 10:57:42.365756 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 10:57:42.369073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 10:57:42.369157 ==
2526 10:57:42.372782 [Gating] SW mode calibration
2527 10:57:42.379098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 10:57:42.385720 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 10:57:42.388990 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2530 10:57:42.392304 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2531 10:57:42.398691 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 10:57:42.402371 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 10:57:42.405599 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 10:57:42.412254 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 10:57:42.415593 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2536 10:57:42.418910 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2537 10:57:42.425856 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2538 10:57:42.428715 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2539 10:57:42.432215 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 10:57:42.435420 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 10:57:42.442174 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 10:57:42.445617 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 10:57:42.449107 1 0 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2544 10:57:42.455305 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2545 10:57:42.458514 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2546 10:57:42.461848 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 10:57:42.468325 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 10:57:42.471803 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 10:57:42.475151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 10:57:42.481640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 10:57:42.485140 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 10:57:42.488371 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 10:57:42.495342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 10:57:42.498854 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:57:42.501707 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:57:42.508374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:57:42.511521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:57:42.514977 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:57:42.521392 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:57:42.524819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:57:42.528888 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:57:42.534927 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:57:42.538232 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:57:42.541372 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:57:42.548113 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:57:42.551518 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:57:42.554863 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:57:42.561403 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 10:57:42.564690 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 10:57:42.567904 Total UI for P1: 0, mck2ui 16
2571 10:57:42.571390 best dqsien dly found for B0: ( 1, 3, 28)
2572 10:57:42.574865 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 10:57:42.581313 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 10:57:42.581397 Total UI for P1: 0, mck2ui 16
2575 10:57:42.584601 best dqsien dly found for B1: ( 1, 4, 2)
2576 10:57:42.591167 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2577 10:57:42.594567 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 10:57:42.594651
2579 10:57:42.597968 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2580 10:57:42.601222 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 10:57:42.604547 [Gating] SW calibration Done
2582 10:57:42.604630 ==
2583 10:57:42.608178 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 10:57:42.611703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 10:57:42.611787 ==
2586 10:57:42.611871 RX Vref Scan: 0
2587 10:57:42.614855
2588 10:57:42.614938 RX Vref 0 -> 0, step: 1
2589 10:57:42.615021
2590 10:57:42.618126 RX Delay -40 -> 252, step: 8
2591 10:57:42.621671 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2592 10:57:42.624641 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2593 10:57:42.631602 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2594 10:57:42.634818 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2595 10:57:42.638067 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2596 10:57:42.641131 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2597 10:57:42.644560 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2598 10:57:42.651524 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2599 10:57:42.654502 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2600 10:57:42.657988 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2601 10:57:42.661400 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2602 10:57:42.664441 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2603 10:57:42.671028 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2604 10:57:42.674827 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2605 10:57:42.678224 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2606 10:57:42.681445 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2607 10:57:42.681529 ==
2608 10:57:42.684734 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 10:57:42.690946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 10:57:42.691031 ==
2611 10:57:42.691114 DQS Delay:
2612 10:57:42.694707 DQS0 = 0, DQS1 = 0
2613 10:57:42.694791 DQM Delay:
2614 10:57:42.694874 DQM0 = 123, DQM1 = 110
2615 10:57:42.697928 DQ Delay:
2616 10:57:42.701238 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2617 10:57:42.704822 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2618 10:57:42.707804 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2619 10:57:42.711469 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2620 10:57:42.711554
2621 10:57:42.711637
2622 10:57:42.711715 ==
2623 10:57:42.714290 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 10:57:42.717634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 10:57:42.721357 ==
2626 10:57:42.721440
2627 10:57:42.721522
2628 10:57:42.721600 TX Vref Scan disable
2629 10:57:42.724435 == TX Byte 0 ==
2630 10:57:42.727794 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2631 10:57:42.731032 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2632 10:57:42.734478 == TX Byte 1 ==
2633 10:57:42.737686 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2634 10:57:42.740824 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2635 10:57:42.744207 ==
2636 10:57:42.744288 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 10:57:42.750905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 10:57:42.750987 ==
2639 10:57:42.762052 TX Vref=22, minBit 4, minWin=24, winSum=409
2640 10:57:42.765519 TX Vref=24, minBit 3, minWin=24, winSum=413
2641 10:57:42.768634 TX Vref=26, minBit 5, minWin=24, winSum=417
2642 10:57:42.771875 TX Vref=28, minBit 3, minWin=25, winSum=422
2643 10:57:42.775641 TX Vref=30, minBit 5, minWin=25, winSum=426
2644 10:57:42.781854 TX Vref=32, minBit 0, minWin=25, winSum=418
2645 10:57:42.785358 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 30
2646 10:57:42.785439
2647 10:57:42.788358 Final TX Range 1 Vref 30
2648 10:57:42.788439
2649 10:57:42.788503 ==
2650 10:57:42.791646 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 10:57:42.795237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 10:57:42.798819 ==
2653 10:57:42.798900
2654 10:57:42.798965
2655 10:57:42.799025 TX Vref Scan disable
2656 10:57:42.801752 == TX Byte 0 ==
2657 10:57:42.805370 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2658 10:57:42.808439 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2659 10:57:42.811955 == TX Byte 1 ==
2660 10:57:42.814979 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2661 10:57:42.821793 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2662 10:57:42.821876
2663 10:57:42.821942 [DATLAT]
2664 10:57:42.822001 Freq=1200, CH0 RK0
2665 10:57:42.822060
2666 10:57:42.824962 DATLAT Default: 0xd
2667 10:57:42.825047 0, 0xFFFF, sum = 0
2668 10:57:42.828500 1, 0xFFFF, sum = 0
2669 10:57:42.828584 2, 0xFFFF, sum = 0
2670 10:57:42.831916 3, 0xFFFF, sum = 0
2671 10:57:42.835040 4, 0xFFFF, sum = 0
2672 10:57:42.835124 5, 0xFFFF, sum = 0
2673 10:57:42.838427 6, 0xFFFF, sum = 0
2674 10:57:42.838511 7, 0xFFFF, sum = 0
2675 10:57:42.841573 8, 0xFFFF, sum = 0
2676 10:57:42.841657 9, 0xFFFF, sum = 0
2677 10:57:42.844780 10, 0xFFFF, sum = 0
2678 10:57:42.844865 11, 0xFFFF, sum = 0
2679 10:57:42.848312 12, 0x0, sum = 1
2680 10:57:42.848395 13, 0x0, sum = 2
2681 10:57:42.851653 14, 0x0, sum = 3
2682 10:57:42.851737 15, 0x0, sum = 4
2683 10:57:42.854851 best_step = 13
2684 10:57:42.854934
2685 10:57:42.855000 ==
2686 10:57:42.858032 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 10:57:42.861569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 10:57:42.861654 ==
2689 10:57:42.861720 RX Vref Scan: 1
2690 10:57:42.864825
2691 10:57:42.864908 Set Vref Range= 32 -> 127
2692 10:57:42.864975
2693 10:57:42.868348 RX Vref 32 -> 127, step: 1
2694 10:57:42.868432
2695 10:57:42.871392 RX Delay -13 -> 252, step: 4
2696 10:57:42.871475
2697 10:57:42.874848 Set Vref, RX VrefLevel [Byte0]: 32
2698 10:57:42.877922 [Byte1]: 32
2699 10:57:42.878005
2700 10:57:42.881271 Set Vref, RX VrefLevel [Byte0]: 33
2701 10:57:42.884685 [Byte1]: 33
2702 10:57:42.888228
2703 10:57:42.888310 Set Vref, RX VrefLevel [Byte0]: 34
2704 10:57:42.891827 [Byte1]: 34
2705 10:57:42.896370
2706 10:57:42.896452 Set Vref, RX VrefLevel [Byte0]: 35
2707 10:57:42.899535 [Byte1]: 35
2708 10:57:42.904162
2709 10:57:42.904245 Set Vref, RX VrefLevel [Byte0]: 36
2710 10:57:42.907341 [Byte1]: 36
2711 10:57:42.911814
2712 10:57:42.911899 Set Vref, RX VrefLevel [Byte0]: 37
2713 10:57:42.915220 [Byte1]: 37
2714 10:57:42.919611
2715 10:57:42.919693 Set Vref, RX VrefLevel [Byte0]: 38
2716 10:57:42.923143 [Byte1]: 38
2717 10:57:42.927566
2718 10:57:42.927649 Set Vref, RX VrefLevel [Byte0]: 39
2719 10:57:42.931083 [Byte1]: 39
2720 10:57:42.935567
2721 10:57:42.935649 Set Vref, RX VrefLevel [Byte0]: 40
2722 10:57:42.938818 [Byte1]: 40
2723 10:57:42.943334
2724 10:57:42.943416 Set Vref, RX VrefLevel [Byte0]: 41
2725 10:57:42.946821 [Byte1]: 41
2726 10:57:42.951357
2727 10:57:42.951440 Set Vref, RX VrefLevel [Byte0]: 42
2728 10:57:42.954770 [Byte1]: 42
2729 10:57:42.959907
2730 10:57:42.959995 Set Vref, RX VrefLevel [Byte0]: 43
2731 10:57:42.962378 [Byte1]: 43
2732 10:57:42.967169
2733 10:57:42.967252 Set Vref, RX VrefLevel [Byte0]: 44
2734 10:57:42.970436 [Byte1]: 44
2735 10:57:42.975137
2736 10:57:42.975220 Set Vref, RX VrefLevel [Byte0]: 45
2737 10:57:42.978909 [Byte1]: 45
2738 10:57:42.983172
2739 10:57:42.983268 Set Vref, RX VrefLevel [Byte0]: 46
2740 10:57:42.986234 [Byte1]: 46
2741 10:57:42.990709
2742 10:57:42.990792 Set Vref, RX VrefLevel [Byte0]: 47
2743 10:57:42.994262 [Byte1]: 47
2744 10:57:42.998911
2745 10:57:42.998994 Set Vref, RX VrefLevel [Byte0]: 48
2746 10:57:43.002351 [Byte1]: 48
2747 10:57:43.006550
2748 10:57:43.006632 Set Vref, RX VrefLevel [Byte0]: 49
2749 10:57:43.009990 [Byte1]: 49
2750 10:57:43.014752
2751 10:57:43.014855 Set Vref, RX VrefLevel [Byte0]: 50
2752 10:57:43.017730 [Byte1]: 50
2753 10:57:43.022507
2754 10:57:43.022581 Set Vref, RX VrefLevel [Byte0]: 51
2755 10:57:43.025844 [Byte1]: 51
2756 10:57:43.030318
2757 10:57:43.030420 Set Vref, RX VrefLevel [Byte0]: 52
2758 10:57:43.033730 [Byte1]: 52
2759 10:57:43.038198
2760 10:57:43.038281 Set Vref, RX VrefLevel [Byte0]: 53
2761 10:57:43.041420 [Byte1]: 53
2762 10:57:43.045867
2763 10:57:43.045941 Set Vref, RX VrefLevel [Byte0]: 54
2764 10:57:43.049539 [Byte1]: 54
2765 10:57:43.053955
2766 10:57:43.054030 Set Vref, RX VrefLevel [Byte0]: 55
2767 10:57:43.057202 [Byte1]: 55
2768 10:57:43.061811
2769 10:57:43.061910 Set Vref, RX VrefLevel [Byte0]: 56
2770 10:57:43.065200 [Byte1]: 56
2771 10:57:43.069857
2772 10:57:43.069956 Set Vref, RX VrefLevel [Byte0]: 57
2773 10:57:43.073069 [Byte1]: 57
2774 10:57:43.077661
2775 10:57:43.077736 Set Vref, RX VrefLevel [Byte0]: 58
2776 10:57:43.081139 [Byte1]: 58
2777 10:57:43.085641
2778 10:57:43.085718 Set Vref, RX VrefLevel [Byte0]: 59
2779 10:57:43.088892 [Byte1]: 59
2780 10:57:43.093377
2781 10:57:43.093450 Set Vref, RX VrefLevel [Byte0]: 60
2782 10:57:43.096548 [Byte1]: 60
2783 10:57:43.101409
2784 10:57:43.101483 Set Vref, RX VrefLevel [Byte0]: 61
2785 10:57:43.104571 [Byte1]: 61
2786 10:57:43.109023
2787 10:57:43.109098 Set Vref, RX VrefLevel [Byte0]: 62
2788 10:57:43.112897 [Byte1]: 62
2789 10:57:43.117172
2790 10:57:43.117253 Set Vref, RX VrefLevel [Byte0]: 63
2791 10:57:43.120556 [Byte1]: 63
2792 10:57:43.125281
2793 10:57:43.125362 Set Vref, RX VrefLevel [Byte0]: 64
2794 10:57:43.128602 [Byte1]: 64
2795 10:57:43.132861
2796 10:57:43.132942 Set Vref, RX VrefLevel [Byte0]: 65
2797 10:57:43.136567 [Byte1]: 65
2798 10:57:43.140574
2799 10:57:43.140655 Set Vref, RX VrefLevel [Byte0]: 66
2800 10:57:43.143947 [Byte1]: 66
2801 10:57:43.148473
2802 10:57:43.148554 Set Vref, RX VrefLevel [Byte0]: 67
2803 10:57:43.151876 [Byte1]: 67
2804 10:57:43.156733
2805 10:57:43.156851 Set Vref, RX VrefLevel [Byte0]: 68
2806 10:57:43.160005 [Byte1]: 68
2807 10:57:43.164459
2808 10:57:43.164540 Set Vref, RX VrefLevel [Byte0]: 69
2809 10:57:43.167967 [Byte1]: 69
2810 10:57:43.172335
2811 10:57:43.172416 Set Vref, RX VrefLevel [Byte0]: 70
2812 10:57:43.175564 [Byte1]: 70
2813 10:57:43.180181
2814 10:57:43.180264 Final RX Vref Byte 0 = 60 to rank0
2815 10:57:43.183649 Final RX Vref Byte 1 = 49 to rank0
2816 10:57:43.186753 Final RX Vref Byte 0 = 60 to rank1
2817 10:57:43.190258 Final RX Vref Byte 1 = 49 to rank1==
2818 10:57:43.193605 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 10:57:43.200237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 10:57:43.200319 ==
2821 10:57:43.200384 DQS Delay:
2822 10:57:43.200442 DQS0 = 0, DQS1 = 0
2823 10:57:43.203770 DQM Delay:
2824 10:57:43.203851 DQM0 = 123, DQM1 = 108
2825 10:57:43.206894 DQ Delay:
2826 10:57:43.210082 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2827 10:57:43.213589 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2828 10:57:43.216904 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2829 10:57:43.220158 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2830 10:57:43.220239
2831 10:57:43.220304
2832 10:57:43.226566 [DQSOSCAuto] RK0, (LSB)MR18= 0x805, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2833 10:57:43.230055 CH0 RK0: MR19=404, MR18=805
2834 10:57:43.236955 CH0_RK0: MR19=0x404, MR18=0x805, DQSOSC=406, MR23=63, INC=39, DEC=26
2835 10:57:43.237037
2836 10:57:43.240069 ----->DramcWriteLeveling(PI) begin...
2837 10:57:43.240152 ==
2838 10:57:43.243551 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 10:57:43.246807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 10:57:43.249774 ==
2841 10:57:43.249855 Write leveling (Byte 0): 36 => 36
2842 10:57:43.253382 Write leveling (Byte 1): 29 => 29
2843 10:57:43.256558 DramcWriteLeveling(PI) end<-----
2844 10:57:43.256639
2845 10:57:43.256704 ==
2846 10:57:43.259889 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 10:57:43.266602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 10:57:43.266684 ==
2849 10:57:43.266749 [Gating] SW mode calibration
2850 10:57:43.276540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 10:57:43.279975 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 10:57:43.286605 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2853 10:57:43.289628 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 10:57:43.293039 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 10:57:43.296626 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 10:57:43.302843 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 10:57:43.306222 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 10:57:43.309719 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 10:57:43.316873 0 15 28 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
2860 10:57:43.319768 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 10:57:43.323105 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 10:57:43.329615 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 10:57:43.332741 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 10:57:43.336078 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 10:57:43.342927 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 10:57:43.346414 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2867 10:57:43.349774 1 0 28 | B1->B0 | 3939 4141 | 0 1 | (0 0) (0 0)
2868 10:57:43.356339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 10:57:43.359541 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 10:57:43.363289 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 10:57:43.369603 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 10:57:43.373027 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 10:57:43.376229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 10:57:43.382729 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 10:57:43.386269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2876 10:57:43.389701 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 10:57:43.396155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 10:57:43.399622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 10:57:43.402921 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 10:57:43.409204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 10:57:43.412826 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 10:57:43.415832 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 10:57:43.422656 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 10:57:43.426011 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 10:57:43.429161 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 10:57:43.435865 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 10:57:43.439347 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 10:57:43.442295 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 10:57:43.445933 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 10:57:43.452660 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 10:57:43.455966 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 10:57:43.458922 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 10:57:43.462376 Total UI for P1: 0, mck2ui 16
2894 10:57:43.465577 best dqsien dly found for B0: ( 1, 3, 28)
2895 10:57:43.468979 Total UI for P1: 0, mck2ui 16
2896 10:57:43.472479 best dqsien dly found for B1: ( 1, 3, 30)
2897 10:57:43.475818 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2898 10:57:43.479277 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2899 10:57:43.482289
2900 10:57:43.485895 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2901 10:57:43.489423 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2902 10:57:43.492822 [Gating] SW calibration Done
2903 10:57:43.492905 ==
2904 10:57:43.495506 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 10:57:43.499286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 10:57:43.499370 ==
2907 10:57:43.499436 RX Vref Scan: 0
2908 10:57:43.499498
2909 10:57:43.502413 RX Vref 0 -> 0, step: 1
2910 10:57:43.502495
2911 10:57:43.505472 RX Delay -40 -> 252, step: 8
2912 10:57:43.508757 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2913 10:57:43.512420 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2914 10:57:43.518586 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2915 10:57:43.522162 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2916 10:57:43.525444 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2917 10:57:43.528581 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2918 10:57:43.532010 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2919 10:57:43.538544 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2920 10:57:43.541873 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2921 10:57:43.545193 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2922 10:57:43.548667 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2923 10:57:43.551792 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2924 10:57:43.558914 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2925 10:57:43.561938 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2926 10:57:43.565245 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2927 10:57:43.569028 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2928 10:57:43.569111 ==
2929 10:57:43.572242 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 10:57:43.578624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 10:57:43.578708 ==
2932 10:57:43.578774 DQS Delay:
2933 10:57:43.578835 DQS0 = 0, DQS1 = 0
2934 10:57:43.582224 DQM Delay:
2935 10:57:43.582307 DQM0 = 120, DQM1 = 108
2936 10:57:43.585165 DQ Delay:
2937 10:57:43.588471 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2938 10:57:43.591658 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2939 10:57:43.595043 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2940 10:57:43.598366 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2941 10:57:43.598438
2942 10:57:43.598500
2943 10:57:43.598557 ==
2944 10:57:43.602011 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 10:57:43.605219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 10:57:43.605293 ==
2947 10:57:43.608134
2948 10:57:43.608203
2949 10:57:43.608263 TX Vref Scan disable
2950 10:57:43.611413 == TX Byte 0 ==
2951 10:57:43.614820 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2952 10:57:43.618566 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2953 10:57:43.621565 == TX Byte 1 ==
2954 10:57:43.624660 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2955 10:57:43.628178 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2956 10:57:43.628254 ==
2957 10:57:43.631763 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 10:57:43.638147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 10:57:43.638223 ==
2960 10:57:43.649715 TX Vref=22, minBit 5, minWin=25, winSum=417
2961 10:57:43.653287 TX Vref=24, minBit 7, minWin=24, winSum=420
2962 10:57:43.656338 TX Vref=26, minBit 7, minWin=25, winSum=428
2963 10:57:43.659659 TX Vref=28, minBit 3, minWin=26, winSum=430
2964 10:57:43.662994 TX Vref=30, minBit 0, minWin=27, winSum=436
2965 10:57:43.669299 TX Vref=32, minBit 0, minWin=26, winSum=428
2966 10:57:43.672871 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 30
2967 10:57:43.672941
2968 10:57:43.676273 Final TX Range 1 Vref 30
2969 10:57:43.676341
2970 10:57:43.676400 ==
2971 10:57:43.679404 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 10:57:43.682740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 10:57:43.685983 ==
2974 10:57:43.686051
2975 10:57:43.686109
2976 10:57:43.686169 TX Vref Scan disable
2977 10:57:43.689668 == TX Byte 0 ==
2978 10:57:43.693048 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2979 10:57:43.696163 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2980 10:57:43.699556 == TX Byte 1 ==
2981 10:57:43.702882 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2982 10:57:43.706533 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2983 10:57:43.709347
2984 10:57:43.709416 [DATLAT]
2985 10:57:43.709481 Freq=1200, CH0 RK1
2986 10:57:43.709539
2987 10:57:43.713027 DATLAT Default: 0xd
2988 10:57:43.713104 0, 0xFFFF, sum = 0
2989 10:57:43.716134 1, 0xFFFF, sum = 0
2990 10:57:43.716203 2, 0xFFFF, sum = 0
2991 10:57:43.719216 3, 0xFFFF, sum = 0
2992 10:57:43.722603 4, 0xFFFF, sum = 0
2993 10:57:43.722673 5, 0xFFFF, sum = 0
2994 10:57:43.725882 6, 0xFFFF, sum = 0
2995 10:57:43.725955 7, 0xFFFF, sum = 0
2996 10:57:43.729060 8, 0xFFFF, sum = 0
2997 10:57:43.729132 9, 0xFFFF, sum = 0
2998 10:57:43.732648 10, 0xFFFF, sum = 0
2999 10:57:43.732738 11, 0xFFFF, sum = 0
3000 10:57:43.736094 12, 0x0, sum = 1
3001 10:57:43.736170 13, 0x0, sum = 2
3002 10:57:43.739075 14, 0x0, sum = 3
3003 10:57:43.739144 15, 0x0, sum = 4
3004 10:57:43.742390 best_step = 13
3005 10:57:43.742457
3006 10:57:43.742518 ==
3007 10:57:43.745820 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 10:57:43.749186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 10:57:43.749256 ==
3010 10:57:43.749316 RX Vref Scan: 0
3011 10:57:43.749374
3012 10:57:43.752991 RX Vref 0 -> 0, step: 1
3013 10:57:43.753064
3014 10:57:43.756193 RX Delay -21 -> 252, step: 4
3015 10:57:43.759281 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3016 10:57:43.765815 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3017 10:57:43.769206 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3018 10:57:43.772593 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3019 10:57:43.776209 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3020 10:57:43.779323 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3021 10:57:43.785969 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3022 10:57:43.789102 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3023 10:57:43.792428 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3024 10:57:43.795901 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3025 10:57:43.799023 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3026 10:57:43.805560 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3027 10:57:43.808883 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3028 10:57:43.812576 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3029 10:57:43.815971 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3030 10:57:43.819228 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3031 10:57:43.822394 ==
3032 10:57:43.822464 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 10:57:43.828860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 10:57:43.828934 ==
3035 10:57:43.828998 DQS Delay:
3036 10:57:43.832428 DQS0 = 0, DQS1 = 0
3037 10:57:43.832497 DQM Delay:
3038 10:57:43.835840 DQM0 = 119, DQM1 = 107
3039 10:57:43.835910 DQ Delay:
3040 10:57:43.838979 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3041 10:57:43.842178 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3042 10:57:43.845508 DQ8 =98, DQ9 =92, DQ10 =110, DQ11 =106
3043 10:57:43.849053 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3044 10:57:43.849123
3045 10:57:43.849186
3046 10:57:43.858948 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
3047 10:57:43.859024 CH0 RK1: MR19=403, MR18=AF2
3048 10:57:43.865675 CH0_RK1: MR19=0x403, MR18=0xAF2, DQSOSC=406, MR23=63, INC=39, DEC=26
3049 10:57:43.868935 [RxdqsGatingPostProcess] freq 1200
3050 10:57:43.875388 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 10:57:43.878945 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 10:57:43.882190 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 10:57:43.885720 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 10:57:43.888728 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 10:57:43.888822 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 10:57:43.892455 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 10:57:43.895455 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 10:57:43.898845 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 10:57:43.902081 Pre-setting of DQS Precalculation
3060 10:57:43.909063 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 10:57:43.909142 ==
3062 10:57:43.912454 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 10:57:43.915431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 10:57:43.915506 ==
3065 10:57:43.921906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 10:57:43.928403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3067 10:57:43.935660 [CA 0] Center 37 (7~68) winsize 62
3068 10:57:43.938801 [CA 1] Center 37 (7~68) winsize 62
3069 10:57:43.942227 [CA 2] Center 35 (5~65) winsize 61
3070 10:57:43.945526 [CA 3] Center 34 (4~65) winsize 62
3071 10:57:43.948941 [CA 4] Center 34 (3~65) winsize 63
3072 10:57:43.952375 [CA 5] Center 33 (3~64) winsize 62
3073 10:57:43.952447
3074 10:57:43.955360 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3075 10:57:43.955442
3076 10:57:43.958654 [CATrainingPosCal] consider 1 rank data
3077 10:57:43.961986 u2DelayCellTimex100 = 270/100 ps
3078 10:57:43.965502 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 10:57:43.968697 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 10:57:43.975225 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 10:57:43.978710 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3082 10:57:43.981803 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3083 10:57:43.985629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 10:57:43.985699
3085 10:57:43.988767 CA PerBit enable=1, Macro0, CA PI delay=33
3086 10:57:43.988839
3087 10:57:43.992058 [CBTSetCACLKResult] CA Dly = 33
3088 10:57:43.992133 CS Dly: 6 (0~37)
3089 10:57:43.995312 ==
3090 10:57:43.998554 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 10:57:44.002276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 10:57:44.002347 ==
3093 10:57:44.005383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 10:57:44.011854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3095 10:57:44.020975 [CA 0] Center 38 (8~68) winsize 61
3096 10:57:44.024520 [CA 1] Center 38 (8~68) winsize 61
3097 10:57:44.027986 [CA 2] Center 35 (5~66) winsize 62
3098 10:57:44.031252 [CA 3] Center 34 (4~65) winsize 62
3099 10:57:44.034655 [CA 4] Center 35 (5~65) winsize 61
3100 10:57:44.037938 [CA 5] Center 34 (4~64) winsize 61
3101 10:57:44.038008
3102 10:57:44.041265 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3103 10:57:44.041353
3104 10:57:44.044509 [CATrainingPosCal] consider 2 rank data
3105 10:57:44.047516 u2DelayCellTimex100 = 270/100 ps
3106 10:57:44.051028 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3107 10:57:44.057597 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3108 10:57:44.060869 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3109 10:57:44.064326 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3110 10:57:44.067704 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3111 10:57:44.070705 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3112 10:57:44.070777
3113 10:57:44.074265 CA PerBit enable=1, Macro0, CA PI delay=34
3114 10:57:44.074335
3115 10:57:44.077660 [CBTSetCACLKResult] CA Dly = 34
3116 10:57:44.077733 CS Dly: 7 (0~39)
3117 10:57:44.080986
3118 10:57:44.084483 ----->DramcWriteLeveling(PI) begin...
3119 10:57:44.084560 ==
3120 10:57:44.087792 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 10:57:44.090924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 10:57:44.090993 ==
3123 10:57:44.094428 Write leveling (Byte 0): 24 => 24
3124 10:57:44.097443 Write leveling (Byte 1): 28 => 28
3125 10:57:44.100935 DramcWriteLeveling(PI) end<-----
3126 10:57:44.101019
3127 10:57:44.101081 ==
3128 10:57:44.103982 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 10:57:44.107490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 10:57:44.107561 ==
3131 10:57:44.110964 [Gating] SW mode calibration
3132 10:57:44.117377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 10:57:44.124045 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 10:57:44.127231 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 10:57:44.130391 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 10:57:44.137172 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 10:57:44.140441 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 10:57:44.143753 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 10:57:44.150343 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3140 10:57:44.153675 0 15 24 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 1)
3141 10:57:44.157146 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3142 10:57:44.164174 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 10:57:44.167200 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 10:57:44.170748 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 10:57:44.173805 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 10:57:44.180976 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 10:57:44.183795 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3148 10:57:44.187125 1 0 24 | B1->B0 | 3f3f 4444 | 0 0 | (1 1) (0 0)
3149 10:57:44.193855 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 10:57:44.197285 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 10:57:44.200507 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 10:57:44.207056 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 10:57:44.210537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 10:57:44.213708 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 10:57:44.220211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 10:57:44.223667 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 10:57:44.227044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3158 10:57:44.233394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 10:57:44.236940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 10:57:44.240188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 10:57:44.246875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 10:57:44.250184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 10:57:44.253406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 10:57:44.260089 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 10:57:44.263319 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 10:57:44.266518 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 10:57:44.273571 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 10:57:44.276592 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 10:57:44.279851 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 10:57:44.286419 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 10:57:44.289843 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 10:57:44.293275 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 10:57:44.299801 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3174 10:57:44.299876 Total UI for P1: 0, mck2ui 16
3175 10:57:44.306745 best dqsien dly found for B0: ( 1, 3, 22)
3176 10:57:44.309771 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 10:57:44.312776 Total UI for P1: 0, mck2ui 16
3178 10:57:44.316294 best dqsien dly found for B1: ( 1, 3, 26)
3179 10:57:44.319781 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3180 10:57:44.322992 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3181 10:57:44.323073
3182 10:57:44.326299 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3183 10:57:44.329985 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3184 10:57:44.333430 [Gating] SW calibration Done
3185 10:57:44.333512 ==
3186 10:57:44.336536 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 10:57:44.339714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 10:57:44.339800 ==
3189 10:57:44.343102 RX Vref Scan: 0
3190 10:57:44.343183
3191 10:57:44.346035 RX Vref 0 -> 0, step: 1
3192 10:57:44.346116
3193 10:57:44.346181 RX Delay -40 -> 252, step: 8
3194 10:57:44.353153 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3195 10:57:44.356145 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3196 10:57:44.359669 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3197 10:57:44.362979 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3198 10:57:44.366187 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3199 10:57:44.372700 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3200 10:57:44.375944 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3201 10:57:44.379339 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3202 10:57:44.382540 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3203 10:57:44.386152 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3204 10:57:44.392499 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3205 10:57:44.396133 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3206 10:57:44.399469 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3207 10:57:44.402599 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3208 10:57:44.409198 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3209 10:57:44.412445 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3210 10:57:44.412528 ==
3211 10:57:44.416180 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 10:57:44.419486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 10:57:44.419567 ==
3214 10:57:44.419644 DQS Delay:
3215 10:57:44.422559 DQS0 = 0, DQS1 = 0
3216 10:57:44.422640 DQM Delay:
3217 10:57:44.425888 DQM0 = 120, DQM1 = 112
3218 10:57:44.425968 DQ Delay:
3219 10:57:44.429501 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3220 10:57:44.432596 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3221 10:57:44.435929 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3222 10:57:44.439351 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3223 10:57:44.439431
3224 10:57:44.442762
3225 10:57:44.442842 ==
3226 10:57:44.446061 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 10:57:44.449376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 10:57:44.449457 ==
3229 10:57:44.449522
3230 10:57:44.449582
3231 10:57:44.452654 TX Vref Scan disable
3232 10:57:44.452735 == TX Byte 0 ==
3233 10:57:44.455864 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3234 10:57:44.462492 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3235 10:57:44.462574 == TX Byte 1 ==
3236 10:57:44.469486 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3237 10:57:44.472349 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3238 10:57:44.472430 ==
3239 10:57:44.476050 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 10:57:44.479000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 10:57:44.479081 ==
3242 10:57:44.491072 TX Vref=22, minBit 10, minWin=24, winSum=406
3243 10:57:44.494443 TX Vref=24, minBit 3, minWin=25, winSum=411
3244 10:57:44.498283 TX Vref=26, minBit 9, minWin=25, winSum=419
3245 10:57:44.501387 TX Vref=28, minBit 10, minWin=25, winSum=422
3246 10:57:44.504756 TX Vref=30, minBit 10, minWin=25, winSum=419
3247 10:57:44.511241 TX Vref=32, minBit 0, minWin=26, winSum=423
3248 10:57:44.514462 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 32
3249 10:57:44.514544
3250 10:57:44.517754 Final TX Range 1 Vref 32
3251 10:57:44.517835
3252 10:57:44.517899 ==
3253 10:57:44.521606 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 10:57:44.524643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 10:57:44.528157 ==
3256 10:57:44.528238
3257 10:57:44.528301
3258 10:57:44.528360 TX Vref Scan disable
3259 10:57:44.531501 == TX Byte 0 ==
3260 10:57:44.534760 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3261 10:57:44.538149 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3262 10:57:44.541789 == TX Byte 1 ==
3263 10:57:44.544748 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3264 10:57:44.548092 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3265 10:57:44.551703
3266 10:57:44.551784 [DATLAT]
3267 10:57:44.551848 Freq=1200, CH1 RK0
3268 10:57:44.551908
3269 10:57:44.555098 DATLAT Default: 0xd
3270 10:57:44.555178 0, 0xFFFF, sum = 0
3271 10:57:44.558018 1, 0xFFFF, sum = 0
3272 10:57:44.558100 2, 0xFFFF, sum = 0
3273 10:57:44.561287 3, 0xFFFF, sum = 0
3274 10:57:44.561369 4, 0xFFFF, sum = 0
3275 10:57:44.564655 5, 0xFFFF, sum = 0
3276 10:57:44.564737 6, 0xFFFF, sum = 0
3277 10:57:44.568252 7, 0xFFFF, sum = 0
3278 10:57:44.571690 8, 0xFFFF, sum = 0
3279 10:57:44.571773 9, 0xFFFF, sum = 0
3280 10:57:44.574717 10, 0xFFFF, sum = 0
3281 10:57:44.574813 11, 0xFFFF, sum = 0
3282 10:57:44.578234 12, 0x0, sum = 1
3283 10:57:44.578317 13, 0x0, sum = 2
3284 10:57:44.578382 14, 0x0, sum = 3
3285 10:57:44.581332 15, 0x0, sum = 4
3286 10:57:44.581415 best_step = 13
3287 10:57:44.581489
3288 10:57:44.584885 ==
3289 10:57:44.584966 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 10:57:44.591500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 10:57:44.591581 ==
3292 10:57:44.591645 RX Vref Scan: 1
3293 10:57:44.591704
3294 10:57:44.594851 Set Vref Range= 32 -> 127
3295 10:57:44.594931
3296 10:57:44.597983 RX Vref 32 -> 127, step: 1
3297 10:57:44.598064
3298 10:57:44.601368 RX Delay -13 -> 252, step: 4
3299 10:57:44.601448
3300 10:57:44.604737 Set Vref, RX VrefLevel [Byte0]: 32
3301 10:57:44.608079 [Byte1]: 32
3302 10:57:44.608158
3303 10:57:44.611277 Set Vref, RX VrefLevel [Byte0]: 33
3304 10:57:44.614689 [Byte1]: 33
3305 10:57:44.614768
3306 10:57:44.618107 Set Vref, RX VrefLevel [Byte0]: 34
3307 10:57:44.621269 [Byte1]: 34
3308 10:57:44.625416
3309 10:57:44.625495 Set Vref, RX VrefLevel [Byte0]: 35
3310 10:57:44.628961 [Byte1]: 35
3311 10:57:44.633289
3312 10:57:44.633368 Set Vref, RX VrefLevel [Byte0]: 36
3313 10:57:44.636795 [Byte1]: 36
3314 10:57:44.641215
3315 10:57:44.641293 Set Vref, RX VrefLevel [Byte0]: 37
3316 10:57:44.644524 [Byte1]: 37
3317 10:57:44.649243
3318 10:57:44.649322 Set Vref, RX VrefLevel [Byte0]: 38
3319 10:57:44.652423 [Byte1]: 38
3320 10:57:44.657142
3321 10:57:44.657220 Set Vref, RX VrefLevel [Byte0]: 39
3322 10:57:44.660459 [Byte1]: 39
3323 10:57:44.665202
3324 10:57:44.665281 Set Vref, RX VrefLevel [Byte0]: 40
3325 10:57:44.668376 [Byte1]: 40
3326 10:57:44.673045
3327 10:57:44.673124 Set Vref, RX VrefLevel [Byte0]: 41
3328 10:57:44.676111 [Byte1]: 41
3329 10:57:44.680685
3330 10:57:44.680769 Set Vref, RX VrefLevel [Byte0]: 42
3331 10:57:44.683843 [Byte1]: 42
3332 10:57:44.688586
3333 10:57:44.688667 Set Vref, RX VrefLevel [Byte0]: 43
3334 10:57:44.691817 [Byte1]: 43
3335 10:57:44.696569
3336 10:57:44.696648 Set Vref, RX VrefLevel [Byte0]: 44
3337 10:57:44.699743 [Byte1]: 44
3338 10:57:44.704295
3339 10:57:44.704374 Set Vref, RX VrefLevel [Byte0]: 45
3340 10:57:44.707977 [Byte1]: 45
3341 10:57:44.712217
3342 10:57:44.712296 Set Vref, RX VrefLevel [Byte0]: 46
3343 10:57:44.715770 [Byte1]: 46
3344 10:57:44.720333
3345 10:57:44.720412 Set Vref, RX VrefLevel [Byte0]: 47
3346 10:57:44.723970 [Byte1]: 47
3347 10:57:44.728193
3348 10:57:44.728271 Set Vref, RX VrefLevel [Byte0]: 48
3349 10:57:44.731555 [Byte1]: 48
3350 10:57:44.736277
3351 10:57:44.736355 Set Vref, RX VrefLevel [Byte0]: 49
3352 10:57:44.738986 [Byte1]: 49
3353 10:57:44.743695
3354 10:57:44.743774 Set Vref, RX VrefLevel [Byte0]: 50
3355 10:57:44.747211 [Byte1]: 50
3356 10:57:44.751548
3357 10:57:44.751626 Set Vref, RX VrefLevel [Byte0]: 51
3358 10:57:44.755000 [Byte1]: 51
3359 10:57:44.759580
3360 10:57:44.759658 Set Vref, RX VrefLevel [Byte0]: 52
3361 10:57:44.762729 [Byte1]: 52
3362 10:57:44.767264
3363 10:57:44.770455 Set Vref, RX VrefLevel [Byte0]: 53
3364 10:57:44.773679 [Byte1]: 53
3365 10:57:44.773761
3366 10:57:44.777421 Set Vref, RX VrefLevel [Byte0]: 54
3367 10:57:44.780949 [Byte1]: 54
3368 10:57:44.781028
3369 10:57:44.783687 Set Vref, RX VrefLevel [Byte0]: 55
3370 10:57:44.787164 [Byte1]: 55
3371 10:57:44.791012
3372 10:57:44.791090 Set Vref, RX VrefLevel [Byte0]: 56
3373 10:57:44.794336 [Byte1]: 56
3374 10:57:44.799198
3375 10:57:44.799276 Set Vref, RX VrefLevel [Byte0]: 57
3376 10:57:44.802440 [Byte1]: 57
3377 10:57:44.807111
3378 10:57:44.807189 Set Vref, RX VrefLevel [Byte0]: 58
3379 10:57:44.810324 [Byte1]: 58
3380 10:57:44.814725
3381 10:57:44.814803 Set Vref, RX VrefLevel [Byte0]: 59
3382 10:57:44.818319 [Byte1]: 59
3383 10:57:44.822767
3384 10:57:44.822845 Set Vref, RX VrefLevel [Byte0]: 60
3385 10:57:44.825834 [Byte1]: 60
3386 10:57:44.830567
3387 10:57:44.830646 Set Vref, RX VrefLevel [Byte0]: 61
3388 10:57:44.833839 [Byte1]: 61
3389 10:57:44.838365
3390 10:57:44.838444 Set Vref, RX VrefLevel [Byte0]: 62
3391 10:57:44.841713 [Byte1]: 62
3392 10:57:44.846605
3393 10:57:44.846685 Set Vref, RX VrefLevel [Byte0]: 63
3394 10:57:44.849528 [Byte1]: 63
3395 10:57:44.854051
3396 10:57:44.854132 Set Vref, RX VrefLevel [Byte0]: 64
3397 10:57:44.857805 [Byte1]: 64
3398 10:57:44.862220
3399 10:57:44.862301 Set Vref, RX VrefLevel [Byte0]: 65
3400 10:57:44.865760 [Byte1]: 65
3401 10:57:44.869968
3402 10:57:44.870049 Set Vref, RX VrefLevel [Byte0]: 66
3403 10:57:44.873277 [Byte1]: 66
3404 10:57:44.878113
3405 10:57:44.878194 Final RX Vref Byte 0 = 54 to rank0
3406 10:57:44.881168 Final RX Vref Byte 1 = 53 to rank0
3407 10:57:44.884418 Final RX Vref Byte 0 = 54 to rank1
3408 10:57:44.887996 Final RX Vref Byte 1 = 53 to rank1==
3409 10:57:44.891131 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 10:57:44.897926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 10:57:44.898008 ==
3412 10:57:44.898073 DQS Delay:
3413 10:57:44.898130 DQS0 = 0, DQS1 = 0
3414 10:57:44.901126 DQM Delay:
3415 10:57:44.901206 DQM0 = 119, DQM1 = 112
3416 10:57:44.904417 DQ Delay:
3417 10:57:44.907829 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3418 10:57:44.911142 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3419 10:57:44.914266 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3420 10:57:44.917927 DQ12 =122, DQ13 =116, DQ14 =122, DQ15 =120
3421 10:57:44.918008
3422 10:57:44.918072
3423 10:57:44.927918 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3424 10:57:44.928032 CH1 RK0: MR19=404, MR18=316
3425 10:57:44.934285 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3426 10:57:44.934369
3427 10:57:44.937560 ----->DramcWriteLeveling(PI) begin...
3428 10:57:44.937643 ==
3429 10:57:44.941167 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 10:57:44.944305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 10:57:44.947610 ==
3432 10:57:44.947691 Write leveling (Byte 0): 24 => 24
3433 10:57:44.950864 Write leveling (Byte 1): 29 => 29
3434 10:57:44.954296 DramcWriteLeveling(PI) end<-----
3435 10:57:44.954377
3436 10:57:44.954441 ==
3437 10:57:44.957930 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 10:57:44.964188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 10:57:44.964270 ==
3440 10:57:44.967490 [Gating] SW mode calibration
3441 10:57:44.974255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 10:57:44.977552 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 10:57:44.984437 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 10:57:44.987493 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 10:57:44.990410 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 10:57:44.997246 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 10:57:45.000503 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 10:57:45.003923 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 10:57:45.010280 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 1)
3450 10:57:45.013721 0 15 28 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
3451 10:57:45.017014 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 10:57:45.024163 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 10:57:45.026769 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 10:57:45.030377 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 10:57:45.036810 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 10:57:45.040259 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 10:57:45.043489 1 0 24 | B1->B0 | 4242 2e2e | 0 0 | (0 0) (0 0)
3458 10:57:45.046968 1 0 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (1 1)
3459 10:57:45.053544 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 10:57:45.057274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 10:57:45.060425 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 10:57:45.066935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 10:57:45.070007 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 10:57:45.073582 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 10:57:45.079960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 10:57:45.083605 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 10:57:45.086896 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:57:45.093283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:57:45.096622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:57:45.100227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:57:45.106497 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 10:57:45.109949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 10:57:45.113446 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 10:57:45.120016 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 10:57:45.123437 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 10:57:45.126402 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 10:57:45.133221 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 10:57:45.136557 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 10:57:45.139936 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 10:57:45.146446 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3481 10:57:45.149879 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 10:57:45.152964 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3483 10:57:45.159686 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 10:57:45.159767 Total UI for P1: 0, mck2ui 16
3485 10:57:45.166100 best dqsien dly found for B0: ( 1, 3, 24)
3486 10:57:45.166181 Total UI for P1: 0, mck2ui 16
3487 10:57:45.172791 best dqsien dly found for B1: ( 1, 3, 26)
3488 10:57:45.176339 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3489 10:57:45.179210 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3490 10:57:45.179317
3491 10:57:45.182584 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3492 10:57:45.186041 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3493 10:57:45.189120 [Gating] SW calibration Done
3494 10:57:45.189201 ==
3495 10:57:45.192519 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 10:57:45.195984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 10:57:45.196065 ==
3498 10:57:45.199048 RX Vref Scan: 0
3499 10:57:45.199128
3500 10:57:45.199192 RX Vref 0 -> 0, step: 1
3501 10:57:45.202281
3502 10:57:45.202361 RX Delay -40 -> 252, step: 8
3503 10:57:45.209009 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3504 10:57:45.212251 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3505 10:57:45.215535 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3506 10:57:45.218799 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3507 10:57:45.221924 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3508 10:57:45.228510 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3509 10:57:45.232337 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3510 10:57:45.235427 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3511 10:57:45.238650 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3512 10:57:45.241744 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3513 10:57:45.248497 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3514 10:57:45.251972 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3515 10:57:45.255014 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3516 10:57:45.258213 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3517 10:57:45.265083 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3518 10:57:45.268026 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3519 10:57:45.268108 ==
3520 10:57:45.271491 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 10:57:45.274897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 10:57:45.274978 ==
3523 10:57:45.275043 DQS Delay:
3524 10:57:45.278227 DQS0 = 0, DQS1 = 0
3525 10:57:45.278308 DQM Delay:
3526 10:57:45.281242 DQM0 = 120, DQM1 = 112
3527 10:57:45.281338 DQ Delay:
3528 10:57:45.284598 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3529 10:57:45.288070 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3530 10:57:45.291124 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3531 10:57:45.298383 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3532 10:57:45.298465
3533 10:57:45.298529
3534 10:57:45.298589 ==
3535 10:57:45.301517 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 10:57:45.304414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 10:57:45.304495 ==
3538 10:57:45.304560
3539 10:57:45.304620
3540 10:57:45.307684 TX Vref Scan disable
3541 10:57:45.307765 == TX Byte 0 ==
3542 10:57:45.314338 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3543 10:57:45.317436 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3544 10:57:45.317518 == TX Byte 1 ==
3545 10:57:45.324165 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3546 10:57:45.327688 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3547 10:57:45.327770 ==
3548 10:57:45.331215 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 10:57:45.334188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 10:57:45.334270 ==
3551 10:57:45.347240 TX Vref=22, minBit 1, minWin=25, winSum=417
3552 10:57:45.350878 TX Vref=24, minBit 3, minWin=25, winSum=423
3553 10:57:45.354197 TX Vref=26, minBit 1, minWin=26, winSum=427
3554 10:57:45.357209 TX Vref=28, minBit 3, minWin=26, winSum=430
3555 10:57:45.360679 TX Vref=30, minBit 8, minWin=26, winSum=427
3556 10:57:45.367048 TX Vref=32, minBit 0, minWin=26, winSum=427
3557 10:57:45.370239 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
3558 10:57:45.370321
3559 10:57:45.373749 Final TX Range 1 Vref 28
3560 10:57:45.373830
3561 10:57:45.373894 ==
3562 10:57:45.377111 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 10:57:45.380477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 10:57:45.380559 ==
3565 10:57:45.383613
3566 10:57:45.383693
3567 10:57:45.383757 TX Vref Scan disable
3568 10:57:45.386808 == TX Byte 0 ==
3569 10:57:45.389976 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3570 10:57:45.396821 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3571 10:57:45.396902 == TX Byte 1 ==
3572 10:57:45.400181 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3573 10:57:45.407128 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3574 10:57:45.407210
3575 10:57:45.407274 [DATLAT]
3576 10:57:45.407334 Freq=1200, CH1 RK1
3577 10:57:45.407393
3578 10:57:45.410065 DATLAT Default: 0xd
3579 10:57:45.410146 0, 0xFFFF, sum = 0
3580 10:57:45.413368 1, 0xFFFF, sum = 0
3581 10:57:45.416937 2, 0xFFFF, sum = 0
3582 10:57:45.417019 3, 0xFFFF, sum = 0
3583 10:57:45.420324 4, 0xFFFF, sum = 0
3584 10:57:45.420406 5, 0xFFFF, sum = 0
3585 10:57:45.423301 6, 0xFFFF, sum = 0
3586 10:57:45.423384 7, 0xFFFF, sum = 0
3587 10:57:45.426707 8, 0xFFFF, sum = 0
3588 10:57:45.426789 9, 0xFFFF, sum = 0
3589 10:57:45.429965 10, 0xFFFF, sum = 0
3590 10:57:45.430047 11, 0xFFFF, sum = 0
3591 10:57:45.433417 12, 0x0, sum = 1
3592 10:57:45.433499 13, 0x0, sum = 2
3593 10:57:45.436904 14, 0x0, sum = 3
3594 10:57:45.436987 15, 0x0, sum = 4
3595 10:57:45.439834 best_step = 13
3596 10:57:45.439914
3597 10:57:45.439978 ==
3598 10:57:45.443170 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 10:57:45.446424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 10:57:45.446520 ==
3601 10:57:45.446613 RX Vref Scan: 0
3602 10:57:45.449811
3603 10:57:45.449898 RX Vref 0 -> 0, step: 1
3604 10:57:45.449974
3605 10:57:45.453132 RX Delay -13 -> 252, step: 4
3606 10:57:45.459892 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3607 10:57:45.463122 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3608 10:57:45.466220 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3609 10:57:45.469888 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3610 10:57:45.473044 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3611 10:57:45.479368 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3612 10:57:45.482833 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3613 10:57:45.486260 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3614 10:57:45.489711 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3615 10:57:45.492884 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3616 10:57:45.499370 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3617 10:57:45.502568 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3618 10:57:45.505829 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3619 10:57:45.509156 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3620 10:57:45.515571 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3621 10:57:45.519269 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3622 10:57:45.519350 ==
3623 10:57:45.522213 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 10:57:45.525608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 10:57:45.525690 ==
3626 10:57:45.525755 DQS Delay:
3627 10:57:45.528708 DQS0 = 0, DQS1 = 0
3628 10:57:45.528795 DQM Delay:
3629 10:57:45.532486 DQM0 = 119, DQM1 = 113
3630 10:57:45.532567 DQ Delay:
3631 10:57:45.535373 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3632 10:57:45.538977 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3633 10:57:45.541981 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3634 10:57:45.548775 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3635 10:57:45.548856
3636 10:57:45.548920
3637 10:57:45.555696 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3638 10:57:45.558712 CH1 RK1: MR19=403, MR18=6EA
3639 10:57:45.565137 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3640 10:57:45.568295 [RxdqsGatingPostProcess] freq 1200
3641 10:57:45.571761 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3642 10:57:45.575090 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 10:57:45.578604 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 10:57:45.581739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 10:57:45.585089 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 10:57:45.588255 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 10:57:45.591461 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 10:57:45.594711 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 10:57:45.598019 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 10:57:45.601403 Pre-setting of DQS Precalculation
3651 10:57:45.604897 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3652 10:57:45.614816 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3653 10:57:45.621582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3654 10:57:45.621664
3655 10:57:45.621727
3656 10:57:45.624662 [Calibration Summary] 2400 Mbps
3657 10:57:45.624770 CH 0, Rank 0
3658 10:57:45.628216 SW Impedance : PASS
3659 10:57:45.628297 DUTY Scan : NO K
3660 10:57:45.631378 ZQ Calibration : PASS
3661 10:57:45.634787 Jitter Meter : NO K
3662 10:57:45.634868 CBT Training : PASS
3663 10:57:45.637879 Write leveling : PASS
3664 10:57:45.641474 RX DQS gating : PASS
3665 10:57:45.641555 RX DQ/DQS(RDDQC) : PASS
3666 10:57:45.644434 TX DQ/DQS : PASS
3667 10:57:45.648035 RX DATLAT : PASS
3668 10:57:45.648119 RX DQ/DQS(Engine): PASS
3669 10:57:45.651109 TX OE : NO K
3670 10:57:45.651190 All Pass.
3671 10:57:45.651255
3672 10:57:45.654379 CH 0, Rank 1
3673 10:57:45.654460 SW Impedance : PASS
3674 10:57:45.657718 DUTY Scan : NO K
3675 10:57:45.661078 ZQ Calibration : PASS
3676 10:57:45.661159 Jitter Meter : NO K
3677 10:57:45.664448 CBT Training : PASS
3678 10:57:45.664529 Write leveling : PASS
3679 10:57:45.667783 RX DQS gating : PASS
3680 10:57:45.670776 RX DQ/DQS(RDDQC) : PASS
3681 10:57:45.670858 TX DQ/DQS : PASS
3682 10:57:45.673999 RX DATLAT : PASS
3683 10:57:45.677478 RX DQ/DQS(Engine): PASS
3684 10:57:45.677560 TX OE : NO K
3685 10:57:45.680872 All Pass.
3686 10:57:45.680954
3687 10:57:45.681018 CH 1, Rank 0
3688 10:57:45.684657 SW Impedance : PASS
3689 10:57:45.684762 DUTY Scan : NO K
3690 10:57:45.687303 ZQ Calibration : PASS
3691 10:57:45.690777 Jitter Meter : NO K
3692 10:57:45.690886 CBT Training : PASS
3693 10:57:45.694042 Write leveling : PASS
3694 10:57:45.697539 RX DQS gating : PASS
3695 10:57:45.697621 RX DQ/DQS(RDDQC) : PASS
3696 10:57:45.700681 TX DQ/DQS : PASS
3697 10:57:45.704048 RX DATLAT : PASS
3698 10:57:45.704130 RX DQ/DQS(Engine): PASS
3699 10:57:45.706981 TX OE : NO K
3700 10:57:45.707063 All Pass.
3701 10:57:45.707128
3702 10:57:45.710630 CH 1, Rank 1
3703 10:57:45.710712 SW Impedance : PASS
3704 10:57:45.714060 DUTY Scan : NO K
3705 10:57:45.717047 ZQ Calibration : PASS
3706 10:57:45.717129 Jitter Meter : NO K
3707 10:57:45.720680 CBT Training : PASS
3708 10:57:45.723745 Write leveling : PASS
3709 10:57:45.723827 RX DQS gating : PASS
3710 10:57:45.726925 RX DQ/DQS(RDDQC) : PASS
3711 10:57:45.730664 TX DQ/DQS : PASS
3712 10:57:45.730747 RX DATLAT : PASS
3713 10:57:45.733567 RX DQ/DQS(Engine): PASS
3714 10:57:45.733649 TX OE : NO K
3715 10:57:45.737100 All Pass.
3716 10:57:45.737181
3717 10:57:45.737245 DramC Write-DBI off
3718 10:57:45.740015 PER_BANK_REFRESH: Hybrid Mode
3719 10:57:45.743409 TX_TRACKING: ON
3720 10:57:45.750368 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3721 10:57:45.753267 [FAST_K] Save calibration result to emmc
3722 10:57:45.759907 dramc_set_vcore_voltage set vcore to 650000
3723 10:57:45.759990 Read voltage for 600, 5
3724 10:57:45.763801 Vio18 = 0
3725 10:57:45.763883 Vcore = 650000
3726 10:57:45.763948 Vdram = 0
3727 10:57:45.766811 Vddq = 0
3728 10:57:45.766892 Vmddr = 0
3729 10:57:45.769784 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3730 10:57:45.776680 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3731 10:57:45.780018 MEM_TYPE=3, freq_sel=19
3732 10:57:45.783405 sv_algorithm_assistance_LP4_1600
3733 10:57:45.786507 ============ PULL DRAM RESETB DOWN ============
3734 10:57:45.789840 ========== PULL DRAM RESETB DOWN end =========
3735 10:57:45.792980 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3736 10:57:45.796242 ===================================
3737 10:57:45.799752 LPDDR4 DRAM CONFIGURATION
3738 10:57:45.802855 ===================================
3739 10:57:45.806239 EX_ROW_EN[0] = 0x0
3740 10:57:45.806325 EX_ROW_EN[1] = 0x0
3741 10:57:45.809508 LP4Y_EN = 0x0
3742 10:57:45.809590 WORK_FSP = 0x0
3743 10:57:45.812833 WL = 0x2
3744 10:57:45.812916 RL = 0x2
3745 10:57:45.816395 BL = 0x2
3746 10:57:45.816502 RPST = 0x0
3747 10:57:45.819308 RD_PRE = 0x0
3748 10:57:45.822755 WR_PRE = 0x1
3749 10:57:45.822851 WR_PST = 0x0
3750 10:57:45.825890 DBI_WR = 0x0
3751 10:57:45.825989 DBI_RD = 0x0
3752 10:57:45.829234 OTF = 0x1
3753 10:57:45.832557 ===================================
3754 10:57:45.835968 ===================================
3755 10:57:45.836039 ANA top config
3756 10:57:45.839307 ===================================
3757 10:57:45.842579 DLL_ASYNC_EN = 0
3758 10:57:45.846072 ALL_SLAVE_EN = 1
3759 10:57:45.846171 NEW_RANK_MODE = 1
3760 10:57:45.849271 DLL_IDLE_MODE = 1
3761 10:57:45.852720 LP45_APHY_COMB_EN = 1
3762 10:57:45.855817 TX_ODT_DIS = 1
3763 10:57:45.855889 NEW_8X_MODE = 1
3764 10:57:45.859073 ===================================
3765 10:57:45.862818 ===================================
3766 10:57:45.865935 data_rate = 1200
3767 10:57:45.869179 CKR = 1
3768 10:57:45.872477 DQ_P2S_RATIO = 8
3769 10:57:45.875472 ===================================
3770 10:57:45.878893 CA_P2S_RATIO = 8
3771 10:57:45.882557 DQ_CA_OPEN = 0
3772 10:57:45.882653 DQ_SEMI_OPEN = 0
3773 10:57:45.885703 CA_SEMI_OPEN = 0
3774 10:57:45.888818 CA_FULL_RATE = 0
3775 10:57:45.891978 DQ_CKDIV4_EN = 1
3776 10:57:45.895803 CA_CKDIV4_EN = 1
3777 10:57:45.898806 CA_PREDIV_EN = 0
3778 10:57:45.898907 PH8_DLY = 0
3779 10:57:45.902476 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3780 10:57:45.905340 DQ_AAMCK_DIV = 4
3781 10:57:45.908755 CA_AAMCK_DIV = 4
3782 10:57:45.912243 CA_ADMCK_DIV = 4
3783 10:57:45.915689 DQ_TRACK_CA_EN = 0
3784 10:57:45.918607 CA_PICK = 600
3785 10:57:45.918712 CA_MCKIO = 600
3786 10:57:45.922154 MCKIO_SEMI = 0
3787 10:57:45.925597 PLL_FREQ = 2288
3788 10:57:45.928469 DQ_UI_PI_RATIO = 32
3789 10:57:45.931928 CA_UI_PI_RATIO = 0
3790 10:57:45.935096 ===================================
3791 10:57:45.938708 ===================================
3792 10:57:45.941956 memory_type:LPDDR4
3793 10:57:45.942051 GP_NUM : 10
3794 10:57:45.945104 SRAM_EN : 1
3795 10:57:45.945200 MD32_EN : 0
3796 10:57:45.948352 ===================================
3797 10:57:45.951965 [ANA_INIT] >>>>>>>>>>>>>>
3798 10:57:45.955118 <<<<<< [CONFIGURE PHASE]: ANA_TX
3799 10:57:45.958188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3800 10:57:45.961409 ===================================
3801 10:57:45.964701 data_rate = 1200,PCW = 0X5800
3802 10:57:45.967971 ===================================
3803 10:57:45.971419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3804 10:57:45.978250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 10:57:45.981215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 10:57:45.987940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3807 10:57:45.991381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3808 10:57:45.994473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3809 10:57:45.994571 [ANA_INIT] flow start
3810 10:57:45.997828 [ANA_INIT] PLL >>>>>>>>
3811 10:57:46.001246 [ANA_INIT] PLL <<<<<<<<
3812 10:57:46.001345 [ANA_INIT] MIDPI >>>>>>>>
3813 10:57:46.004447 [ANA_INIT] MIDPI <<<<<<<<
3814 10:57:46.007718 [ANA_INIT] DLL >>>>>>>>
3815 10:57:46.007818 [ANA_INIT] flow end
3816 10:57:46.014627 ============ LP4 DIFF to SE enter ============
3817 10:57:46.017690 ============ LP4 DIFF to SE exit ============
3818 10:57:46.021152 [ANA_INIT] <<<<<<<<<<<<<
3819 10:57:46.024633 [Flow] Enable top DCM control >>>>>
3820 10:57:46.027434 [Flow] Enable top DCM control <<<<<
3821 10:57:46.030996 Enable DLL master slave shuffle
3822 10:57:46.034100 ==============================================================
3823 10:57:46.037607 Gating Mode config
3824 10:57:46.040847 ==============================================================
3825 10:57:46.044398 Config description:
3826 10:57:46.053907 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3827 10:57:46.060842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3828 10:57:46.064044 SELPH_MODE 0: By rank 1: By Phase
3829 10:57:46.070623 ==============================================================
3830 10:57:46.073911 GAT_TRACK_EN = 1
3831 10:57:46.077509 RX_GATING_MODE = 2
3832 10:57:46.080453 RX_GATING_TRACK_MODE = 2
3833 10:57:46.084147 SELPH_MODE = 1
3834 10:57:46.087360 PICG_EARLY_EN = 1
3835 10:57:46.087460 VALID_LAT_VALUE = 1
3836 10:57:46.093635 ==============================================================
3837 10:57:46.096946 Enter into Gating configuration >>>>
3838 10:57:46.100180 Exit from Gating configuration <<<<
3839 10:57:46.103647 Enter into DVFS_PRE_config >>>>>
3840 10:57:46.113697 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3841 10:57:46.117015 Exit from DVFS_PRE_config <<<<<
3842 10:57:46.120118 Enter into PICG configuration >>>>
3843 10:57:46.123508 Exit from PICG configuration <<<<
3844 10:57:46.126544 [RX_INPUT] configuration >>>>>
3845 10:57:46.130063 [RX_INPUT] configuration <<<<<
3846 10:57:46.136742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3847 10:57:46.139915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3848 10:57:46.146429 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 10:57:46.152918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 10:57:46.159778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 10:57:46.166322 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 10:57:46.169617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3853 10:57:46.172858 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3854 10:57:46.176047 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3855 10:57:46.182431 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3856 10:57:46.185839 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3857 10:57:46.189299 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 10:57:46.192487 ===================================
3859 10:57:46.195819 LPDDR4 DRAM CONFIGURATION
3860 10:57:46.199326 ===================================
3861 10:57:46.202503 EX_ROW_EN[0] = 0x0
3862 10:57:46.202575 EX_ROW_EN[1] = 0x0
3863 10:57:46.205638 LP4Y_EN = 0x0
3864 10:57:46.205714 WORK_FSP = 0x0
3865 10:57:46.209179 WL = 0x2
3866 10:57:46.209276 RL = 0x2
3867 10:57:46.212303 BL = 0x2
3868 10:57:46.212370 RPST = 0x0
3869 10:57:46.215700 RD_PRE = 0x0
3870 10:57:46.215800 WR_PRE = 0x1
3871 10:57:46.219112 WR_PST = 0x0
3872 10:57:46.219211 DBI_WR = 0x0
3873 10:57:46.222220 DBI_RD = 0x0
3874 10:57:46.222286 OTF = 0x1
3875 10:57:46.225624 ===================================
3876 10:57:46.232172 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3877 10:57:46.235336 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3878 10:57:46.238577 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 10:57:46.242222 ===================================
3880 10:57:46.245207 LPDDR4 DRAM CONFIGURATION
3881 10:57:46.248635 ===================================
3882 10:57:46.251709 EX_ROW_EN[0] = 0x10
3883 10:57:46.251783 EX_ROW_EN[1] = 0x0
3884 10:57:46.255343 LP4Y_EN = 0x0
3885 10:57:46.255413 WORK_FSP = 0x0
3886 10:57:46.258399 WL = 0x2
3887 10:57:46.258470 RL = 0x2
3888 10:57:46.261655 BL = 0x2
3889 10:57:46.261726 RPST = 0x0
3890 10:57:46.265190 RD_PRE = 0x0
3891 10:57:46.265263 WR_PRE = 0x1
3892 10:57:46.268112 WR_PST = 0x0
3893 10:57:46.271869 DBI_WR = 0x0
3894 10:57:46.271940 DBI_RD = 0x0
3895 10:57:46.274655 OTF = 0x1
3896 10:57:46.278161 ===================================
3897 10:57:46.281452 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3898 10:57:46.286949 nWR fixed to 30
3899 10:57:46.289959 [ModeRegInit_LP4] CH0 RK0
3900 10:57:46.290031 [ModeRegInit_LP4] CH0 RK1
3901 10:57:46.293189 [ModeRegInit_LP4] CH1 RK0
3902 10:57:46.296607 [ModeRegInit_LP4] CH1 RK1
3903 10:57:46.296703 match AC timing 17
3904 10:57:46.303488 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3905 10:57:46.306687 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3906 10:57:46.309746 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3907 10:57:46.316512 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3908 10:57:46.319724 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3909 10:57:46.319823 ==
3910 10:57:46.323048 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 10:57:46.326607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3912 10:57:46.326702 ==
3913 10:57:46.333099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3914 10:57:46.339607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3915 10:57:46.342612 [CA 0] Center 36 (5~67) winsize 63
3916 10:57:46.345936 [CA 1] Center 36 (6~67) winsize 62
3917 10:57:46.349505 [CA 2] Center 34 (4~65) winsize 62
3918 10:57:46.352557 [CA 3] Center 34 (4~65) winsize 62
3919 10:57:46.355936 [CA 4] Center 33 (3~64) winsize 62
3920 10:57:46.359203 [CA 5] Center 33 (2~64) winsize 63
3921 10:57:46.359275
3922 10:57:46.362312 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3923 10:57:46.362408
3924 10:57:46.365673 [CATrainingPosCal] consider 1 rank data
3925 10:57:46.369253 u2DelayCellTimex100 = 270/100 ps
3926 10:57:46.372311 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3927 10:57:46.375639 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 10:57:46.379054 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 10:57:46.382277 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 10:57:46.389395 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 10:57:46.392389 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3932 10:57:46.392461
3933 10:57:46.395673 CA PerBit enable=1, Macro0, CA PI delay=33
3934 10:57:46.395746
3935 10:57:46.398762 [CBTSetCACLKResult] CA Dly = 33
3936 10:57:46.398861 CS Dly: 4 (0~35)
3937 10:57:46.398950 ==
3938 10:57:46.402204 Dram Type= 6, Freq= 0, CH_0, rank 1
3939 10:57:46.408780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 10:57:46.408857 ==
3941 10:57:46.412102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 10:57:46.418865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3943 10:57:46.422176 [CA 0] Center 36 (6~67) winsize 62
3944 10:57:46.425516 [CA 1] Center 36 (6~67) winsize 62
3945 10:57:46.428554 [CA 2] Center 35 (4~66) winsize 63
3946 10:57:46.431969 [CA 3] Center 35 (4~66) winsize 63
3947 10:57:46.435475 [CA 4] Center 34 (3~65) winsize 63
3948 10:57:46.438817 [CA 5] Center 34 (3~65) winsize 63
3949 10:57:46.438893
3950 10:57:46.441939 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3951 10:57:46.442011
3952 10:57:46.445234 [CATrainingPosCal] consider 2 rank data
3953 10:57:46.448334 u2DelayCellTimex100 = 270/100 ps
3954 10:57:46.451826 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 10:57:46.458401 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 10:57:46.461763 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 10:57:46.465123 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 10:57:46.468073 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 10:57:46.471622 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 10:57:46.471718
3961 10:57:46.474857 CA PerBit enable=1, Macro0, CA PI delay=33
3962 10:57:46.474955
3963 10:57:46.478298 [CBTSetCACLKResult] CA Dly = 33
3964 10:57:46.481826 CS Dly: 5 (0~37)
3965 10:57:46.481901
3966 10:57:46.485428 ----->DramcWriteLeveling(PI) begin...
3967 10:57:46.485501 ==
3968 10:57:46.488209 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 10:57:46.491338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 10:57:46.491413 ==
3971 10:57:46.494987 Write leveling (Byte 0): 34 => 34
3972 10:57:46.497926 Write leveling (Byte 1): 30 => 30
3973 10:57:46.501440 DramcWriteLeveling(PI) end<-----
3974 10:57:46.501512
3975 10:57:46.501573 ==
3976 10:57:46.504486 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 10:57:46.508233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 10:57:46.508309 ==
3979 10:57:46.511239 [Gating] SW mode calibration
3980 10:57:46.517891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 10:57:46.524484 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3982 10:57:46.527872 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 10:57:46.531121 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 10:57:46.537771 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 10:57:46.541093 0 9 12 | B1->B0 | 3333 2929 | 0 0 | (1 0) (1 0)
3986 10:57:46.544276 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
3987 10:57:46.550441 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:57:46.553958 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 10:57:46.557203 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 10:57:46.563603 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 10:57:46.567024 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 10:57:46.570641 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3993 10:57:46.576759 0 10 12 | B1->B0 | 2828 3a3a | 1 0 | (0 0) (0 0)
3994 10:57:46.580710 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
3995 10:57:46.583785 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:57:46.590113 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:57:46.593573 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 10:57:46.596564 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 10:57:46.603254 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 10:57:46.606416 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 10:57:46.609644 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4002 10:57:46.616299 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4003 10:57:46.619554 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:57:46.622678 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:57:46.629385 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:57:46.632864 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:57:46.636081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:57:46.642659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:57:46.646111 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:57:46.649371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:57:46.655774 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:57:46.659204 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 10:57:46.662565 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 10:57:46.669097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 10:57:46.672408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 10:57:46.675801 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 10:57:46.682138 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 10:57:46.685703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4019 10:57:46.689000 Total UI for P1: 0, mck2ui 16
4020 10:57:46.692052 best dqsien dly found for B0: ( 0, 13, 14)
4021 10:57:46.695524 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 10:57:46.698650 Total UI for P1: 0, mck2ui 16
4023 10:57:46.702073 best dqsien dly found for B1: ( 0, 13, 16)
4024 10:57:46.705097 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4025 10:57:46.711956 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4026 10:57:46.712057
4027 10:57:46.715055 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4028 10:57:46.718602 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4029 10:57:46.721929 [Gating] SW calibration Done
4030 10:57:46.722001 ==
4031 10:57:46.725283 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 10:57:46.728788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 10:57:46.728900 ==
4034 10:57:46.731649 RX Vref Scan: 0
4035 10:57:46.731744
4036 10:57:46.731831 RX Vref 0 -> 0, step: 1
4037 10:57:46.731919
4038 10:57:46.735040 RX Delay -230 -> 252, step: 16
4039 10:57:46.738313 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4040 10:57:46.745233 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4041 10:57:46.748305 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4042 10:57:46.751591 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4043 10:57:46.755049 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4044 10:57:46.761173 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4045 10:57:46.764449 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4046 10:57:46.768023 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4047 10:57:46.771346 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4048 10:57:46.777791 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4049 10:57:46.782170 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4050 10:57:46.784752 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4051 10:57:46.787646 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4052 10:57:46.794540 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4053 10:57:46.797744 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4054 10:57:46.800966 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4055 10:57:46.801036 ==
4056 10:57:46.804218 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 10:57:46.807893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 10:57:46.807995 ==
4059 10:57:46.811108 DQS Delay:
4060 10:57:46.811210 DQS0 = 0, DQS1 = 0
4061 10:57:46.814278 DQM Delay:
4062 10:57:46.814375 DQM0 = 52, DQM1 = 42
4063 10:57:46.814467 DQ Delay:
4064 10:57:46.817567 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4065 10:57:46.820988 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4066 10:57:46.824533 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4067 10:57:46.827777 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4068 10:57:46.827871
4069 10:57:46.827959
4070 10:57:46.830792 ==
4071 10:57:46.834356 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 10:57:46.837645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 10:57:46.837730 ==
4074 10:57:46.837792
4075 10:57:46.837850
4076 10:57:46.840719 TX Vref Scan disable
4077 10:57:46.840850 == TX Byte 0 ==
4078 10:57:46.847319 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4079 10:57:46.850521 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4080 10:57:46.850598 == TX Byte 1 ==
4081 10:57:46.857091 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4082 10:57:46.860484 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4083 10:57:46.860555 ==
4084 10:57:46.863767 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 10:57:46.867046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 10:57:46.867143 ==
4087 10:57:46.867234
4088 10:57:46.867321
4089 10:57:46.870230 TX Vref Scan disable
4090 10:57:46.873449 == TX Byte 0 ==
4091 10:57:46.876750 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4092 10:57:46.883493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4093 10:57:46.883594 == TX Byte 1 ==
4094 10:57:46.886641 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4095 10:57:46.893486 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4096 10:57:46.893563
4097 10:57:46.893626 [DATLAT]
4098 10:57:46.893686 Freq=600, CH0 RK0
4099 10:57:46.893749
4100 10:57:46.896953 DATLAT Default: 0x9
4101 10:57:46.897055 0, 0xFFFF, sum = 0
4102 10:57:46.899799 1, 0xFFFF, sum = 0
4103 10:57:46.903135 2, 0xFFFF, sum = 0
4104 10:57:46.903207 3, 0xFFFF, sum = 0
4105 10:57:46.906553 4, 0xFFFF, sum = 0
4106 10:57:46.906624 5, 0xFFFF, sum = 0
4107 10:57:46.909841 6, 0xFFFF, sum = 0
4108 10:57:46.909916 7, 0xFFFF, sum = 0
4109 10:57:46.913369 8, 0x0, sum = 1
4110 10:57:46.913468 9, 0x0, sum = 2
4111 10:57:46.913558 10, 0x0, sum = 3
4112 10:57:46.916356 11, 0x0, sum = 4
4113 10:57:46.916454 best_step = 9
4114 10:57:46.916545
4115 10:57:46.919722 ==
4116 10:57:46.919819 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 10:57:46.926222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 10:57:46.926322 ==
4119 10:57:46.926412 RX Vref Scan: 1
4120 10:57:46.926498
4121 10:57:46.929555 RX Vref 0 -> 0, step: 1
4122 10:57:46.929650
4123 10:57:46.932860 RX Delay -179 -> 252, step: 8
4124 10:57:46.932931
4125 10:57:46.936118 Set Vref, RX VrefLevel [Byte0]: 60
4126 10:57:46.939764 [Byte1]: 49
4127 10:57:46.939840
4128 10:57:46.942644 Final RX Vref Byte 0 = 60 to rank0
4129 10:57:46.945860 Final RX Vref Byte 1 = 49 to rank0
4130 10:57:46.949294 Final RX Vref Byte 0 = 60 to rank1
4131 10:57:46.952650 Final RX Vref Byte 1 = 49 to rank1==
4132 10:57:46.956062 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 10:57:46.959231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 10:57:46.962424 ==
4135 10:57:46.962495 DQS Delay:
4136 10:57:46.962557 DQS0 = 0, DQS1 = 0
4137 10:57:46.965779 DQM Delay:
4138 10:57:46.965849 DQM0 = 47, DQM1 = 39
4139 10:57:46.969301 DQ Delay:
4140 10:57:46.969374 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =44
4141 10:57:46.972300 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4142 10:57:46.975712 DQ8 =36, DQ9 =20, DQ10 =36, DQ11 =36
4143 10:57:46.979016 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4144 10:57:46.982910
4145 10:57:46.983005
4146 10:57:46.988629 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4147 10:57:46.992250 CH0 RK0: MR19=808, MR18=5751
4148 10:57:46.999027 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4149 10:57:46.999129
4150 10:57:47.001950 ----->DramcWriteLeveling(PI) begin...
4151 10:57:47.002023 ==
4152 10:57:47.005699 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 10:57:47.008573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 10:57:47.008672 ==
4155 10:57:47.012026 Write leveling (Byte 0): 32 => 32
4156 10:57:47.015097 Write leveling (Byte 1): 31 => 31
4157 10:57:47.018428 DramcWriteLeveling(PI) end<-----
4158 10:57:47.018524
4159 10:57:47.018613 ==
4160 10:57:47.021631 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 10:57:47.025198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 10:57:47.025276 ==
4163 10:57:47.028404 [Gating] SW mode calibration
4164 10:57:47.035283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 10:57:47.041533 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 10:57:47.045016 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 10:57:47.051556 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 10:57:47.055093 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 10:57:47.058181 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 1)
4170 10:57:47.065070 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 0)
4171 10:57:47.068401 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 10:57:47.071627 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 10:57:47.078271 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 10:57:47.081613 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 10:57:47.084664 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 10:57:47.091452 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 10:57:47.094739 0 10 12 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0)
4178 10:57:47.098137 0 10 16 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
4179 10:57:47.104523 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 10:57:47.108138 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 10:57:47.111015 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 10:57:47.117683 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 10:57:47.121087 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 10:57:47.124587 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 10:57:47.127816 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 10:57:47.134450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:57:47.137421 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:57:47.141153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:57:47.147544 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:57:47.151089 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:57:47.154151 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 10:57:47.160517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 10:57:47.164128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 10:57:47.167264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 10:57:47.173660 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 10:57:47.177612 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 10:57:47.180519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 10:57:47.187163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 10:57:47.190400 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 10:57:47.193408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 10:57:47.200182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4202 10:57:47.203554 Total UI for P1: 0, mck2ui 16
4203 10:57:47.206624 best dqsien dly found for B1: ( 0, 13, 10)
4204 10:57:47.210248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 10:57:47.213677 Total UI for P1: 0, mck2ui 16
4206 10:57:47.216444 best dqsien dly found for B0: ( 0, 13, 12)
4207 10:57:47.219877 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4208 10:57:47.223287 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4209 10:57:47.223386
4210 10:57:47.226344 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4211 10:57:47.233278 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4212 10:57:47.233376 [Gating] SW calibration Done
4213 10:57:47.233469 ==
4214 10:57:47.236705 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 10:57:47.243127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 10:57:47.243228 ==
4217 10:57:47.243317 RX Vref Scan: 0
4218 10:57:47.243403
4219 10:57:47.246458 RX Vref 0 -> 0, step: 1
4220 10:57:47.246524
4221 10:57:47.249872 RX Delay -230 -> 252, step: 16
4222 10:57:47.253016 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4223 10:57:47.256240 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4224 10:57:47.262757 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4225 10:57:47.266288 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4226 10:57:47.269592 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4227 10:57:47.272923 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 10:57:47.279597 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 10:57:47.282563 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4230 10:57:47.286026 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4231 10:57:47.289099 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 10:57:47.292307 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4233 10:57:47.298988 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4234 10:57:47.302167 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 10:57:47.305541 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4236 10:57:47.309052 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4237 10:57:47.315698 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 10:57:47.315800 ==
4239 10:57:47.318673 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 10:57:47.322068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 10:57:47.322167 ==
4242 10:57:47.322258 DQS Delay:
4243 10:57:47.326010 DQS0 = 0, DQS1 = 0
4244 10:57:47.326104 DQM Delay:
4245 10:57:47.328906 DQM0 = 50, DQM1 = 41
4246 10:57:47.329000 DQ Delay:
4247 10:57:47.332183 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4248 10:57:47.335255 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4249 10:57:47.338959 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4250 10:57:47.342027 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4251 10:57:47.342125
4252 10:57:47.342213
4253 10:57:47.342299 ==
4254 10:57:47.345328 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 10:57:47.348856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 10:57:47.351764 ==
4257 10:57:47.351840
4258 10:57:47.351936
4259 10:57:47.352023 TX Vref Scan disable
4260 10:57:47.355361 == TX Byte 0 ==
4261 10:57:47.358506 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4262 10:57:47.365183 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4263 10:57:47.365255 == TX Byte 1 ==
4264 10:57:47.368569 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4265 10:57:47.374964 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4266 10:57:47.375037 ==
4267 10:57:47.378431 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 10:57:47.381548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 10:57:47.381617 ==
4270 10:57:47.381681
4271 10:57:47.381740
4272 10:57:47.384907 TX Vref Scan disable
4273 10:57:47.388492 == TX Byte 0 ==
4274 10:57:47.391679 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4275 10:57:47.394967 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4276 10:57:47.398228 == TX Byte 1 ==
4277 10:57:47.401595 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4278 10:57:47.404832 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4279 10:57:47.404906
4280 10:57:47.404969 [DATLAT]
4281 10:57:47.408197 Freq=600, CH0 RK1
4282 10:57:47.408265
4283 10:57:47.411702 DATLAT Default: 0x9
4284 10:57:47.411799 0, 0xFFFF, sum = 0
4285 10:57:47.414678 1, 0xFFFF, sum = 0
4286 10:57:47.414767 2, 0xFFFF, sum = 0
4287 10:57:47.417780 3, 0xFFFF, sum = 0
4288 10:57:47.417879 4, 0xFFFF, sum = 0
4289 10:57:47.421311 5, 0xFFFF, sum = 0
4290 10:57:47.421387 6, 0xFFFF, sum = 0
4291 10:57:47.424595 7, 0xFFFF, sum = 0
4292 10:57:47.424692 8, 0x0, sum = 1
4293 10:57:47.428193 9, 0x0, sum = 2
4294 10:57:47.428289 10, 0x0, sum = 3
4295 10:57:47.431037 11, 0x0, sum = 4
4296 10:57:47.431139 best_step = 9
4297 10:57:47.431232
4298 10:57:47.431319 ==
4299 10:57:47.434456 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 10:57:47.437544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 10:57:47.437619 ==
4302 10:57:47.440926 RX Vref Scan: 0
4303 10:57:47.441006
4304 10:57:47.444433 RX Vref 0 -> 0, step: 1
4305 10:57:47.444527
4306 10:57:47.444613 RX Delay -179 -> 252, step: 8
4307 10:57:47.452793 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4308 10:57:47.455466 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4309 10:57:47.458833 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4310 10:57:47.462051 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4311 10:57:47.465573 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4312 10:57:47.472037 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4313 10:57:47.475110 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4314 10:57:47.478686 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4315 10:57:47.481990 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4316 10:57:47.488412 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4317 10:57:47.491717 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4318 10:57:47.494919 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4319 10:57:47.498234 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4320 10:57:47.505204 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4321 10:57:47.508191 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4322 10:57:47.511353 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4323 10:57:47.511423 ==
4324 10:57:47.514504 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 10:57:47.518004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 10:57:47.521350 ==
4327 10:57:47.521419 DQS Delay:
4328 10:57:47.521479 DQS0 = 0, DQS1 = 0
4329 10:57:47.524669 DQM Delay:
4330 10:57:47.524762 DQM0 = 48, DQM1 = 40
4331 10:57:47.527581 DQ Delay:
4332 10:57:47.531222 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =40
4333 10:57:47.531320 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4334 10:57:47.534378 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4335 10:57:47.537816 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =52
4336 10:57:47.541169
4337 10:57:47.541242
4338 10:57:47.547771 [DQSOSCAuto] RK1, (LSB)MR18= 0x6432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4339 10:57:47.551262 CH0 RK1: MR19=808, MR18=6432
4340 10:57:47.557551 CH0_RK1: MR19=0x808, MR18=0x6432, DQSOSC=391, MR23=63, INC=171, DEC=114
4341 10:57:47.560722 [RxdqsGatingPostProcess] freq 600
4342 10:57:47.564207 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 10:57:47.567350 Pre-setting of DQS Precalculation
4344 10:57:47.574463 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 10:57:47.574535 ==
4346 10:57:47.577490 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 10:57:47.580915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 10:57:47.581000 ==
4349 10:57:47.587393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 10:57:47.590811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4351 10:57:47.595146 [CA 0] Center 35 (5~66) winsize 62
4352 10:57:47.598338 [CA 1] Center 35 (5~66) winsize 62
4353 10:57:47.601833 [CA 2] Center 34 (4~65) winsize 62
4354 10:57:47.604688 [CA 3] Center 34 (3~65) winsize 63
4355 10:57:47.608252 [CA 4] Center 34 (3~65) winsize 63
4356 10:57:47.611313 [CA 5] Center 33 (3~64) winsize 62
4357 10:57:47.611381
4358 10:57:47.614794 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4359 10:57:47.614864
4360 10:57:47.618163 [CATrainingPosCal] consider 1 rank data
4361 10:57:47.621263 u2DelayCellTimex100 = 270/100 ps
4362 10:57:47.624472 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 10:57:47.631217 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 10:57:47.634770 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 10:57:47.638138 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4366 10:57:47.641206 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 10:57:47.644689 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 10:57:47.644803
4369 10:57:47.647921 CA PerBit enable=1, Macro0, CA PI delay=33
4370 10:57:47.647994
4371 10:57:47.651088 [CBTSetCACLKResult] CA Dly = 33
4372 10:57:47.654762 CS Dly: 5 (0~36)
4373 10:57:47.654832 ==
4374 10:57:47.657782 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 10:57:47.661267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 10:57:47.661336 ==
4377 10:57:47.667581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 10:57:47.671100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4379 10:57:47.675316 [CA 0] Center 35 (5~66) winsize 62
4380 10:57:47.678335 [CA 1] Center 35 (5~66) winsize 62
4381 10:57:47.681677 [CA 2] Center 34 (4~65) winsize 62
4382 10:57:47.685151 [CA 3] Center 34 (4~65) winsize 62
4383 10:57:47.688471 [CA 4] Center 34 (4~65) winsize 62
4384 10:57:47.691681 [CA 5] Center 34 (3~65) winsize 63
4385 10:57:47.691784
4386 10:57:47.694955 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4387 10:57:47.695024
4388 10:57:47.698526 [CATrainingPosCal] consider 2 rank data
4389 10:57:47.702029 u2DelayCellTimex100 = 270/100 ps
4390 10:57:47.705112 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4391 10:57:47.711493 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 10:57:47.715304 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 10:57:47.718332 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 10:57:47.721265 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 10:57:47.725137 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 10:57:47.725207
4397 10:57:47.728251 CA PerBit enable=1, Macro0, CA PI delay=33
4398 10:57:47.728352
4399 10:57:47.731235 [CBTSetCACLKResult] CA Dly = 33
4400 10:57:47.734807 CS Dly: 5 (0~37)
4401 10:57:47.734908
4402 10:57:47.738185 ----->DramcWriteLeveling(PI) begin...
4403 10:57:47.738282 ==
4404 10:57:47.741255 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 10:57:47.744950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 10:57:47.745020 ==
4407 10:57:47.748062 Write leveling (Byte 0): 30 => 30
4408 10:57:47.751439 Write leveling (Byte 1): 30 => 30
4409 10:57:47.754906 DramcWriteLeveling(PI) end<-----
4410 10:57:47.755008
4411 10:57:47.755096 ==
4412 10:57:47.757694 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 10:57:47.761394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 10:57:47.761466 ==
4415 10:57:47.764941 [Gating] SW mode calibration
4416 10:57:47.771054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 10:57:47.777843 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 10:57:47.781294 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 10:57:47.784660 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 10:57:47.790940 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
4421 10:57:47.794201 0 9 12 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
4422 10:57:47.797701 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4423 10:57:47.804373 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 10:57:47.807450 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 10:57:47.810922 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 10:57:47.817796 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 10:57:47.820746 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 10:57:47.824169 0 10 8 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4429 10:57:47.830539 0 10 12 | B1->B0 | 3737 3d3d | 0 0 | (0 0) (1 1)
4430 10:57:47.834009 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 10:57:47.837115 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 10:57:47.843704 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 10:57:47.846975 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 10:57:47.850257 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 10:57:47.856919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 10:57:47.860154 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 10:57:47.863486 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 10:57:47.869966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:57:47.873360 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:57:47.876746 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:57:47.883537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:57:47.886546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:57:47.889633 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:57:47.896414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:57:47.899635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 10:57:47.903066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 10:57:47.909672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 10:57:47.912661 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 10:57:47.916211 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 10:57:47.922713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 10:57:47.925970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 10:57:47.929595 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4453 10:57:47.936000 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4454 10:57:47.936095 Total UI for P1: 0, mck2ui 16
4455 10:57:47.942549 best dqsien dly found for B0: ( 0, 13, 8)
4456 10:57:47.945801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 10:57:47.949067 Total UI for P1: 0, mck2ui 16
4458 10:57:47.952777 best dqsien dly found for B1: ( 0, 13, 10)
4459 10:57:47.956014 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4460 10:57:47.959423 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4461 10:57:47.959489
4462 10:57:47.962207 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4463 10:57:47.965721 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4464 10:57:47.968980 [Gating] SW calibration Done
4465 10:57:47.969045 ==
4466 10:57:47.972035 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 10:57:47.975611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 10:57:47.978775 ==
4469 10:57:47.978840 RX Vref Scan: 0
4470 10:57:47.978902
4471 10:57:47.982467 RX Vref 0 -> 0, step: 1
4472 10:57:47.982538
4473 10:57:47.985336 RX Delay -230 -> 252, step: 16
4474 10:57:47.988879 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4475 10:57:47.992018 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4476 10:57:47.995238 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4477 10:57:48.002197 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4478 10:57:48.005453 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4479 10:57:48.008688 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4480 10:57:48.011764 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4481 10:57:48.018579 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4482 10:57:48.022091 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4483 10:57:48.024918 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4484 10:57:48.028158 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4485 10:57:48.031779 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4486 10:57:48.038551 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4487 10:57:48.041666 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4488 10:57:48.045008 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4489 10:57:48.047950 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4490 10:57:48.051351 ==
4491 10:57:48.054886 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 10:57:48.058266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 10:57:48.058332 ==
4494 10:57:48.058392 DQS Delay:
4495 10:57:48.061675 DQS0 = 0, DQS1 = 0
4496 10:57:48.061739 DQM Delay:
4497 10:57:48.064807 DQM0 = 48, DQM1 = 43
4498 10:57:48.064877 DQ Delay:
4499 10:57:48.068023 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =49
4500 10:57:48.071214 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4501 10:57:48.074571 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4502 10:57:48.078307 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =41
4503 10:57:48.078373
4504 10:57:48.078431
4505 10:57:48.078487 ==
4506 10:57:48.081487 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 10:57:48.084651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 10:57:48.084715 ==
4509 10:57:48.084777
4510 10:57:48.084840
4511 10:57:48.087760 TX Vref Scan disable
4512 10:57:48.091018 == TX Byte 0 ==
4513 10:57:48.094471 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4514 10:57:48.097592 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4515 10:57:48.101017 == TX Byte 1 ==
4516 10:57:48.104668 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 10:57:48.107727 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 10:57:48.107800 ==
4519 10:57:48.111050 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 10:57:48.117486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 10:57:48.117564 ==
4522 10:57:48.117627
4523 10:57:48.117686
4524 10:57:48.117743 TX Vref Scan disable
4525 10:57:48.121628 == TX Byte 0 ==
4526 10:57:48.125107 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4527 10:57:48.131843 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4528 10:57:48.131939 == TX Byte 1 ==
4529 10:57:48.134922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 10:57:48.141592 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 10:57:48.141665
4532 10:57:48.141727 [DATLAT]
4533 10:57:48.141786 Freq=600, CH1 RK0
4534 10:57:48.141842
4535 10:57:48.144795 DATLAT Default: 0x9
4536 10:57:48.144876 0, 0xFFFF, sum = 0
4537 10:57:48.148413 1, 0xFFFF, sum = 0
4538 10:57:48.151481 2, 0xFFFF, sum = 0
4539 10:57:48.151548 3, 0xFFFF, sum = 0
4540 10:57:48.154942 4, 0xFFFF, sum = 0
4541 10:57:48.155012 5, 0xFFFF, sum = 0
4542 10:57:48.158058 6, 0xFFFF, sum = 0
4543 10:57:48.158123 7, 0xFFFF, sum = 0
4544 10:57:48.161386 8, 0x0, sum = 1
4545 10:57:48.161451 9, 0x0, sum = 2
4546 10:57:48.161509 10, 0x0, sum = 3
4547 10:57:48.164993 11, 0x0, sum = 4
4548 10:57:48.165057 best_step = 9
4549 10:57:48.165114
4550 10:57:48.165169 ==
4551 10:57:48.168008 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 10:57:48.174807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 10:57:48.174877 ==
4554 10:57:48.174939 RX Vref Scan: 1
4555 10:57:48.174998
4556 10:57:48.177929 RX Vref 0 -> 0, step: 1
4557 10:57:48.177991
4558 10:57:48.181533 RX Delay -163 -> 252, step: 8
4559 10:57:48.181601
4560 10:57:48.184713 Set Vref, RX VrefLevel [Byte0]: 54
4561 10:57:48.187789 [Byte1]: 53
4562 10:57:48.187853
4563 10:57:48.191574 Final RX Vref Byte 0 = 54 to rank0
4564 10:57:48.194853 Final RX Vref Byte 1 = 53 to rank0
4565 10:57:48.197784 Final RX Vref Byte 0 = 54 to rank1
4566 10:57:48.200975 Final RX Vref Byte 1 = 53 to rank1==
4567 10:57:48.204406 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 10:57:48.207983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 10:57:48.208052 ==
4570 10:57:48.211144 DQS Delay:
4571 10:57:48.211237 DQS0 = 0, DQS1 = 0
4572 10:57:48.214450 DQM Delay:
4573 10:57:48.214545 DQM0 = 46, DQM1 = 38
4574 10:57:48.214631 DQ Delay:
4575 10:57:48.217767 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4576 10:57:48.220686 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4577 10:57:48.224092 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4578 10:57:48.227433 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4579 10:57:48.227526
4580 10:57:48.230956
4581 10:57:48.237243 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4582 10:57:48.240626 CH1 RK0: MR19=808, MR18=4C73
4583 10:57:48.247302 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4584 10:57:48.247388
4585 10:57:48.250534 ----->DramcWriteLeveling(PI) begin...
4586 10:57:48.250619 ==
4587 10:57:48.253934 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 10:57:48.257023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:57:48.257098 ==
4590 10:57:48.260568 Write leveling (Byte 0): 28 => 28
4591 10:57:48.263508 Write leveling (Byte 1): 31 => 31
4592 10:57:48.266975 DramcWriteLeveling(PI) end<-----
4593 10:57:48.267056
4594 10:57:48.267120 ==
4595 10:57:48.270470 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 10:57:48.273927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 10:57:48.274009 ==
4598 10:57:48.276966 [Gating] SW mode calibration
4599 10:57:48.283678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 10:57:48.290418 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 10:57:48.293500 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 10:57:48.297277 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 10:57:48.303340 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
4604 10:57:48.307019 0 9 12 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 1)
4605 10:57:48.310227 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 10:57:48.316929 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 10:57:48.319833 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 10:57:48.323147 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 10:57:48.329912 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 10:57:48.333405 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 10:57:48.336694 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4612 10:57:48.343003 0 10 12 | B1->B0 | 3939 3434 | 0 0 | (0 0) (0 0)
4613 10:57:48.346607 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 10:57:48.349628 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 10:57:48.356516 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 10:57:48.359495 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 10:57:48.363021 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 10:57:48.369438 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 10:57:48.372838 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4620 10:57:48.376120 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4621 10:57:48.382845 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:57:48.386003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:57:48.389541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:57:48.395910 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:57:48.399635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:57:48.402773 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:57:48.408996 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 10:57:48.412362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 10:57:48.415962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 10:57:48.422284 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 10:57:48.425672 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 10:57:48.429064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 10:57:48.435371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 10:57:48.438746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 10:57:48.441931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 10:57:48.448449 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4637 10:57:48.451976 Total UI for P1: 0, mck2ui 16
4638 10:57:48.455254 best dqsien dly found for B0: ( 0, 13, 10)
4639 10:57:48.458773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 10:57:48.462010 Total UI for P1: 0, mck2ui 16
4641 10:57:48.465238 best dqsien dly found for B1: ( 0, 13, 12)
4642 10:57:48.468422 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4643 10:57:48.471825 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4644 10:57:48.471900
4645 10:57:48.474784 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4646 10:57:48.481645 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4647 10:57:48.481717 [Gating] SW calibration Done
4648 10:57:48.481778 ==
4649 10:57:48.484825 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 10:57:48.491711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 10:57:48.491783 ==
4652 10:57:48.491865 RX Vref Scan: 0
4653 10:57:48.491934
4654 10:57:48.494748 RX Vref 0 -> 0, step: 1
4655 10:57:48.494821
4656 10:57:48.498214 RX Delay -230 -> 252, step: 16
4657 10:57:48.501466 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4658 10:57:48.504746 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4659 10:57:48.510955 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4660 10:57:48.514397 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4661 10:57:48.517776 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4662 10:57:48.521308 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4663 10:57:48.524529 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4664 10:57:48.531258 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4665 10:57:48.534131 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4666 10:57:48.537641 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4667 10:57:48.541022 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4668 10:57:48.547552 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4669 10:57:48.550851 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4670 10:57:48.553990 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4671 10:57:48.557180 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4672 10:57:48.563836 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4673 10:57:48.563914 ==
4674 10:57:48.567280 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 10:57:48.570129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 10:57:48.570199 ==
4677 10:57:48.570265 DQS Delay:
4678 10:57:48.573440 DQS0 = 0, DQS1 = 0
4679 10:57:48.573508 DQM Delay:
4680 10:57:48.577251 DQM0 = 46, DQM1 = 44
4681 10:57:48.577319 DQ Delay:
4682 10:57:48.580117 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4683 10:57:48.583348 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4684 10:57:48.586657 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4685 10:57:48.590081 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4686 10:57:48.590150
4687 10:57:48.590210
4688 10:57:48.590267 ==
4689 10:57:48.593478 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 10:57:48.599755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 10:57:48.599831 ==
4692 10:57:48.599893
4693 10:57:48.599950
4694 10:57:48.600006 TX Vref Scan disable
4695 10:57:48.603294 == TX Byte 0 ==
4696 10:57:48.607100 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4697 10:57:48.613300 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4698 10:57:48.613372 == TX Byte 1 ==
4699 10:57:48.616973 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4700 10:57:48.623263 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4701 10:57:48.623347 ==
4702 10:57:48.626620 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 10:57:48.629904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 10:57:48.629983 ==
4705 10:57:48.630046
4706 10:57:48.630104
4707 10:57:48.633034 TX Vref Scan disable
4708 10:57:48.636814 == TX Byte 0 ==
4709 10:57:48.640255 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4710 10:57:48.643572 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4711 10:57:48.646309 == TX Byte 1 ==
4712 10:57:48.649755 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4713 10:57:48.653120 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4714 10:57:48.653203
4715 10:57:48.653286 [DATLAT]
4716 10:57:48.656647 Freq=600, CH1 RK1
4717 10:57:48.656754
4718 10:57:48.660066 DATLAT Default: 0x9
4719 10:57:48.660149 0, 0xFFFF, sum = 0
4720 10:57:48.662924 1, 0xFFFF, sum = 0
4721 10:57:48.663009 2, 0xFFFF, sum = 0
4722 10:57:48.666388 3, 0xFFFF, sum = 0
4723 10:57:48.666473 4, 0xFFFF, sum = 0
4724 10:57:48.669885 5, 0xFFFF, sum = 0
4725 10:57:48.669970 6, 0xFFFF, sum = 0
4726 10:57:48.672919 7, 0xFFFF, sum = 0
4727 10:57:48.673003 8, 0x0, sum = 1
4728 10:57:48.676410 9, 0x0, sum = 2
4729 10:57:48.676495 10, 0x0, sum = 3
4730 10:57:48.679591 11, 0x0, sum = 4
4731 10:57:48.679675 best_step = 9
4732 10:57:48.679776
4733 10:57:48.679873 ==
4734 10:57:48.683103 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 10:57:48.686205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 10:57:48.686289 ==
4737 10:57:48.689511 RX Vref Scan: 0
4738 10:57:48.689628
4739 10:57:48.692925 RX Vref 0 -> 0, step: 1
4740 10:57:48.693006
4741 10:57:48.693070 RX Delay -179 -> 252, step: 8
4742 10:57:48.700532 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4743 10:57:48.703805 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4744 10:57:48.706971 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4745 10:57:48.710482 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4746 10:57:48.716804 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4747 10:57:48.720054 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4748 10:57:48.723793 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4749 10:57:48.726661 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4750 10:57:48.730291 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4751 10:57:48.736968 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4752 10:57:48.740038 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4753 10:57:48.743355 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4754 10:57:48.746599 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4755 10:57:48.753417 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4756 10:57:48.756626 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4757 10:57:48.759865 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4758 10:57:48.759941 ==
4759 10:57:48.763511 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 10:57:48.766371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 10:57:48.769894 ==
4762 10:57:48.769973 DQS Delay:
4763 10:57:48.770053 DQS0 = 0, DQS1 = 0
4764 10:57:48.772996 DQM Delay:
4765 10:57:48.773073 DQM0 = 45, DQM1 = 40
4766 10:57:48.776402 DQ Delay:
4767 10:57:48.776499 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4768 10:57:48.779685 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4769 10:57:48.783057 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =36
4770 10:57:48.786357 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =52
4771 10:57:48.789485
4772 10:57:48.789592
4773 10:57:48.795939 [DQSOSCAuto] RK1, (LSB)MR18= 0x571d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4774 10:57:48.799854 CH1 RK1: MR19=808, MR18=571D
4775 10:57:48.805966 CH1_RK1: MR19=0x808, MR18=0x571D, DQSOSC=393, MR23=63, INC=169, DEC=113
4776 10:57:48.809169 [RxdqsGatingPostProcess] freq 600
4777 10:57:48.812623 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4778 10:57:48.815994 Pre-setting of DQS Precalculation
4779 10:57:48.822406 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4780 10:57:48.829221 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4781 10:57:48.835634 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4782 10:57:48.835718
4783 10:57:48.835800
4784 10:57:48.839003 [Calibration Summary] 1200 Mbps
4785 10:57:48.839086 CH 0, Rank 0
4786 10:57:48.842373 SW Impedance : PASS
4787 10:57:48.845803 DUTY Scan : NO K
4788 10:57:48.845887 ZQ Calibration : PASS
4789 10:57:48.849163 Jitter Meter : NO K
4790 10:57:48.852480 CBT Training : PASS
4791 10:57:48.852588 Write leveling : PASS
4792 10:57:48.855468 RX DQS gating : PASS
4793 10:57:48.859065 RX DQ/DQS(RDDQC) : PASS
4794 10:57:48.859149 TX DQ/DQS : PASS
4795 10:57:48.862285 RX DATLAT : PASS
4796 10:57:48.862393 RX DQ/DQS(Engine): PASS
4797 10:57:48.865245 TX OE : NO K
4798 10:57:48.865331 All Pass.
4799 10:57:48.865398
4800 10:57:48.868716 CH 0, Rank 1
4801 10:57:48.872407 SW Impedance : PASS
4802 10:57:48.872519 DUTY Scan : NO K
4803 10:57:48.875313 ZQ Calibration : PASS
4804 10:57:48.875420 Jitter Meter : NO K
4805 10:57:48.878775 CBT Training : PASS
4806 10:57:48.881835 Write leveling : PASS
4807 10:57:48.881917 RX DQS gating : PASS
4808 10:57:48.885578 RX DQ/DQS(RDDQC) : PASS
4809 10:57:48.888501 TX DQ/DQS : PASS
4810 10:57:48.888608 RX DATLAT : PASS
4811 10:57:48.892157 RX DQ/DQS(Engine): PASS
4812 10:57:48.895296 TX OE : NO K
4813 10:57:48.895377 All Pass.
4814 10:57:48.895441
4815 10:57:48.895499 CH 1, Rank 0
4816 10:57:48.898686 SW Impedance : PASS
4817 10:57:48.901896 DUTY Scan : NO K
4818 10:57:48.901977 ZQ Calibration : PASS
4819 10:57:48.905177 Jitter Meter : NO K
4820 10:57:48.908546 CBT Training : PASS
4821 10:57:48.908627 Write leveling : PASS
4822 10:57:48.912230 RX DQS gating : PASS
4823 10:57:48.915150 RX DQ/DQS(RDDQC) : PASS
4824 10:57:48.915230 TX DQ/DQS : PASS
4825 10:57:48.918532 RX DATLAT : PASS
4826 10:57:48.918613 RX DQ/DQS(Engine): PASS
4827 10:57:48.921942 TX OE : NO K
4828 10:57:48.922023 All Pass.
4829 10:57:48.922088
4830 10:57:48.925035 CH 1, Rank 1
4831 10:57:48.925116 SW Impedance : PASS
4832 10:57:48.928395 DUTY Scan : NO K
4833 10:57:48.932018 ZQ Calibration : PASS
4834 10:57:48.932100 Jitter Meter : NO K
4835 10:57:48.935375 CBT Training : PASS
4836 10:57:48.938561 Write leveling : PASS
4837 10:57:48.938644 RX DQS gating : PASS
4838 10:57:48.941588 RX DQ/DQS(RDDQC) : PASS
4839 10:57:48.945238 TX DQ/DQS : PASS
4840 10:57:48.945324 RX DATLAT : PASS
4841 10:57:48.948427 RX DQ/DQS(Engine): PASS
4842 10:57:48.951489 TX OE : NO K
4843 10:57:48.951571 All Pass.
4844 10:57:48.951637
4845 10:57:48.954869 DramC Write-DBI off
4846 10:57:48.954952 PER_BANK_REFRESH: Hybrid Mode
4847 10:57:48.958106 TX_TRACKING: ON
4848 10:57:48.968012 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4849 10:57:48.971310 [FAST_K] Save calibration result to emmc
4850 10:57:48.974680 dramc_set_vcore_voltage set vcore to 662500
4851 10:57:48.974795 Read voltage for 933, 3
4852 10:57:48.977826 Vio18 = 0
4853 10:57:48.977908 Vcore = 662500
4854 10:57:48.977974 Vdram = 0
4855 10:57:48.981276 Vddq = 0
4856 10:57:48.981358 Vmddr = 0
4857 10:57:48.984395 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4858 10:57:48.990980 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4859 10:57:48.994343 MEM_TYPE=3, freq_sel=17
4860 10:57:48.997592 sv_algorithm_assistance_LP4_1600
4861 10:57:49.000816 ============ PULL DRAM RESETB DOWN ============
4862 10:57:49.004146 ========== PULL DRAM RESETB DOWN end =========
4863 10:57:49.010683 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4864 10:57:49.014426 ===================================
4865 10:57:49.014508 LPDDR4 DRAM CONFIGURATION
4866 10:57:49.017457 ===================================
4867 10:57:49.020648 EX_ROW_EN[0] = 0x0
4868 10:57:49.024289 EX_ROW_EN[1] = 0x0
4869 10:57:49.024391 LP4Y_EN = 0x0
4870 10:57:49.027272 WORK_FSP = 0x0
4871 10:57:49.027373 WL = 0x3
4872 10:57:49.030476 RL = 0x3
4873 10:57:49.030582 BL = 0x2
4874 10:57:49.033848 RPST = 0x0
4875 10:57:49.033949 RD_PRE = 0x0
4876 10:57:49.037267 WR_PRE = 0x1
4877 10:57:49.037364 WR_PST = 0x0
4878 10:57:49.040855 DBI_WR = 0x0
4879 10:57:49.040924 DBI_RD = 0x0
4880 10:57:49.043749 OTF = 0x1
4881 10:57:49.047065 ===================================
4882 10:57:49.050456 ===================================
4883 10:57:49.050529 ANA top config
4884 10:57:49.053825 ===================================
4885 10:57:49.057188 DLL_ASYNC_EN = 0
4886 10:57:49.060325 ALL_SLAVE_EN = 1
4887 10:57:49.063436 NEW_RANK_MODE = 1
4888 10:57:49.063531 DLL_IDLE_MODE = 1
4889 10:57:49.067215 LP45_APHY_COMB_EN = 1
4890 10:57:49.070141 TX_ODT_DIS = 1
4891 10:57:49.073598 NEW_8X_MODE = 1
4892 10:57:49.076987 ===================================
4893 10:57:49.079990 ===================================
4894 10:57:49.083225 data_rate = 1866
4895 10:57:49.083293 CKR = 1
4896 10:57:49.086774 DQ_P2S_RATIO = 8
4897 10:57:49.089758 ===================================
4898 10:57:49.093087 CA_P2S_RATIO = 8
4899 10:57:49.096587 DQ_CA_OPEN = 0
4900 10:57:49.099853 DQ_SEMI_OPEN = 0
4901 10:57:49.103486 CA_SEMI_OPEN = 0
4902 10:57:49.103581 CA_FULL_RATE = 0
4903 10:57:49.106745 DQ_CKDIV4_EN = 1
4904 10:57:49.109686 CA_CKDIV4_EN = 1
4905 10:57:49.112973 CA_PREDIV_EN = 0
4906 10:57:49.116404 PH8_DLY = 0
4907 10:57:49.119479 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4908 10:57:49.119583 DQ_AAMCK_DIV = 4
4909 10:57:49.123019 CA_AAMCK_DIV = 4
4910 10:57:49.126179 CA_ADMCK_DIV = 4
4911 10:57:49.129702 DQ_TRACK_CA_EN = 0
4912 10:57:49.132814 CA_PICK = 933
4913 10:57:49.136401 CA_MCKIO = 933
4914 10:57:49.139545 MCKIO_SEMI = 0
4915 10:57:49.139641 PLL_FREQ = 3732
4916 10:57:49.142718 DQ_UI_PI_RATIO = 32
4917 10:57:49.145983 CA_UI_PI_RATIO = 0
4918 10:57:49.149361 ===================================
4919 10:57:49.152829 ===================================
4920 10:57:49.155897 memory_type:LPDDR4
4921 10:57:49.159352 GP_NUM : 10
4922 10:57:49.159421 SRAM_EN : 1
4923 10:57:49.162561 MD32_EN : 0
4924 10:57:49.166139 ===================================
4925 10:57:49.166233 [ANA_INIT] >>>>>>>>>>>>>>
4926 10:57:49.169249 <<<<<< [CONFIGURE PHASE]: ANA_TX
4927 10:57:49.172859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4928 10:57:49.175778 ===================================
4929 10:57:49.179235 data_rate = 1866,PCW = 0X8f00
4930 10:57:49.182679 ===================================
4931 10:57:49.185988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4932 10:57:49.192228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 10:57:49.198843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 10:57:49.202176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4935 10:57:49.205788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4936 10:57:49.208664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4937 10:57:49.211895 [ANA_INIT] flow start
4938 10:57:49.211990 [ANA_INIT] PLL >>>>>>>>
4939 10:57:49.215485 [ANA_INIT] PLL <<<<<<<<
4940 10:57:49.218897 [ANA_INIT] MIDPI >>>>>>>>
4941 10:57:49.221941 [ANA_INIT] MIDPI <<<<<<<<
4942 10:57:49.222038 [ANA_INIT] DLL >>>>>>>>
4943 10:57:49.225209 [ANA_INIT] flow end
4944 10:57:49.228529 ============ LP4 DIFF to SE enter ============
4945 10:57:49.231856 ============ LP4 DIFF to SE exit ============
4946 10:57:49.235074 [ANA_INIT] <<<<<<<<<<<<<
4947 10:57:49.238735 [Flow] Enable top DCM control >>>>>
4948 10:57:49.241738 [Flow] Enable top DCM control <<<<<
4949 10:57:49.245295 Enable DLL master slave shuffle
4950 10:57:49.251598 ==============================================================
4951 10:57:49.251694 Gating Mode config
4952 10:57:49.258455 ==============================================================
4953 10:57:49.258526 Config description:
4954 10:57:49.268068 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4955 10:57:49.274685 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4956 10:57:49.281749 SELPH_MODE 0: By rank 1: By Phase
4957 10:57:49.284746 ==============================================================
4958 10:57:49.288232 GAT_TRACK_EN = 1
4959 10:57:49.291289 RX_GATING_MODE = 2
4960 10:57:49.294644 RX_GATING_TRACK_MODE = 2
4961 10:57:49.298322 SELPH_MODE = 1
4962 10:57:49.301183 PICG_EARLY_EN = 1
4963 10:57:49.304643 VALID_LAT_VALUE = 1
4964 10:57:49.311153 ==============================================================
4965 10:57:49.314718 Enter into Gating configuration >>>>
4966 10:57:49.317638 Exit from Gating configuration <<<<
4967 10:57:49.317743 Enter into DVFS_PRE_config >>>>>
4968 10:57:49.330994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4969 10:57:49.334163 Exit from DVFS_PRE_config <<<<<
4970 10:57:49.337420 Enter into PICG configuration >>>>
4971 10:57:49.340672 Exit from PICG configuration <<<<
4972 10:57:49.344375 [RX_INPUT] configuration >>>>>
4973 10:57:49.344470 [RX_INPUT] configuration <<<<<
4974 10:57:49.350708 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4975 10:57:49.357377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4976 10:57:49.360527 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 10:57:49.367024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 10:57:49.373647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 10:57:49.380750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 10:57:49.383825 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4981 10:57:49.387010 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4982 10:57:49.393519 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4983 10:57:49.396939 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4984 10:57:49.400205 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4985 10:57:49.406703 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 10:57:49.410184 ===================================
4987 10:57:49.410264 LPDDR4 DRAM CONFIGURATION
4988 10:57:49.413593 ===================================
4989 10:57:49.416794 EX_ROW_EN[0] = 0x0
4990 10:57:49.416882 EX_ROW_EN[1] = 0x0
4991 10:57:49.420031 LP4Y_EN = 0x0
4992 10:57:49.423641 WORK_FSP = 0x0
4993 10:57:49.423742 WL = 0x3
4994 10:57:49.426623 RL = 0x3
4995 10:57:49.426717 BL = 0x2
4996 10:57:49.429977 RPST = 0x0
4997 10:57:49.430072 RD_PRE = 0x0
4998 10:57:49.433298 WR_PRE = 0x1
4999 10:57:49.433369 WR_PST = 0x0
5000 10:57:49.436577 DBI_WR = 0x0
5001 10:57:49.436680 DBI_RD = 0x0
5002 10:57:49.440846 OTF = 0x1
5003 10:57:49.443188 ===================================
5004 10:57:49.446426 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5005 10:57:49.449899 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5006 10:57:49.456252 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 10:57:49.459706 ===================================
5008 10:57:49.459804 LPDDR4 DRAM CONFIGURATION
5009 10:57:49.462781 ===================================
5010 10:57:49.466412 EX_ROW_EN[0] = 0x10
5011 10:57:49.469380 EX_ROW_EN[1] = 0x0
5012 10:57:49.469474 LP4Y_EN = 0x0
5013 10:57:49.473025 WORK_FSP = 0x0
5014 10:57:49.473119 WL = 0x3
5015 10:57:49.476123 RL = 0x3
5016 10:57:49.476215 BL = 0x2
5017 10:57:49.479871 RPST = 0x0
5018 10:57:49.479965 RD_PRE = 0x0
5019 10:57:49.482738 WR_PRE = 0x1
5020 10:57:49.482830 WR_PST = 0x0
5021 10:57:49.486254 DBI_WR = 0x0
5022 10:57:49.486345 DBI_RD = 0x0
5023 10:57:49.489443 OTF = 0x1
5024 10:57:49.492829 ===================================
5025 10:57:49.499406 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5026 10:57:49.502520 nWR fixed to 30
5027 10:57:49.502616 [ModeRegInit_LP4] CH0 RK0
5028 10:57:49.505842 [ModeRegInit_LP4] CH0 RK1
5029 10:57:49.509287 [ModeRegInit_LP4] CH1 RK0
5030 10:57:49.512527 [ModeRegInit_LP4] CH1 RK1
5031 10:57:49.512625 match AC timing 9
5032 10:57:49.519509 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5033 10:57:49.522331 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5034 10:57:49.525760 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5035 10:57:49.532240 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5036 10:57:49.535710 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5037 10:57:49.535809 ==
5038 10:57:49.538716 Dram Type= 6, Freq= 0, CH_0, rank 0
5039 10:57:49.542537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5040 10:57:49.542632 ==
5041 10:57:49.548997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5042 10:57:49.555333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5043 10:57:49.558695 [CA 0] Center 38 (7~69) winsize 63
5044 10:57:49.562248 [CA 1] Center 38 (7~69) winsize 63
5045 10:57:49.565302 [CA 2] Center 35 (5~66) winsize 62
5046 10:57:49.568975 [CA 3] Center 35 (4~66) winsize 63
5047 10:57:49.572043 [CA 4] Center 34 (4~65) winsize 62
5048 10:57:49.575231 [CA 5] Center 33 (3~64) winsize 62
5049 10:57:49.575298
5050 10:57:49.578713 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5051 10:57:49.578782
5052 10:57:49.582212 [CATrainingPosCal] consider 1 rank data
5053 10:57:49.585085 u2DelayCellTimex100 = 270/100 ps
5054 10:57:49.588067 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5055 10:57:49.591716 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5056 10:57:49.595058 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5057 10:57:49.598108 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5058 10:57:49.601695 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5059 10:57:49.608070 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5060 10:57:49.608141
5061 10:57:49.611576 CA PerBit enable=1, Macro0, CA PI delay=33
5062 10:57:49.611672
5063 10:57:49.614585 [CBTSetCACLKResult] CA Dly = 33
5064 10:57:49.614684 CS Dly: 7 (0~38)
5065 10:57:49.614773 ==
5066 10:57:49.618296 Dram Type= 6, Freq= 0, CH_0, rank 1
5067 10:57:49.621406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5068 10:57:49.624689 ==
5069 10:57:49.627964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5070 10:57:49.634589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5071 10:57:49.637889 [CA 0] Center 38 (8~69) winsize 62
5072 10:57:49.641167 [CA 1] Center 38 (8~69) winsize 62
5073 10:57:49.644345 [CA 2] Center 36 (6~66) winsize 61
5074 10:57:49.647651 [CA 3] Center 35 (5~66) winsize 62
5075 10:57:49.651002 [CA 4] Center 34 (4~65) winsize 62
5076 10:57:49.654596 [CA 5] Center 34 (4~64) winsize 61
5077 10:57:49.654673
5078 10:57:49.657685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5079 10:57:49.657779
5080 10:57:49.661101 [CATrainingPosCal] consider 2 rank data
5081 10:57:49.664296 u2DelayCellTimex100 = 270/100 ps
5082 10:57:49.667905 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5083 10:57:49.670939 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 10:57:49.674450 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5085 10:57:49.677606 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5086 10:57:49.684656 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5087 10:57:49.687679 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5088 10:57:49.687774
5089 10:57:49.690987 CA PerBit enable=1, Macro0, CA PI delay=34
5090 10:57:49.691083
5091 10:57:49.694438 [CBTSetCACLKResult] CA Dly = 34
5092 10:57:49.694507 CS Dly: 7 (0~39)
5093 10:57:49.694570
5094 10:57:49.697723 ----->DramcWriteLeveling(PI) begin...
5095 10:57:49.697818 ==
5096 10:57:49.700894 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 10:57:49.707433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 10:57:49.707505 ==
5099 10:57:49.710543 Write leveling (Byte 0): 32 => 32
5100 10:57:49.713789 Write leveling (Byte 1): 29 => 29
5101 10:57:49.713860 DramcWriteLeveling(PI) end<-----
5102 10:57:49.717158
5103 10:57:49.717234 ==
5104 10:57:49.720730 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 10:57:49.723827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 10:57:49.723902 ==
5107 10:57:49.727270 [Gating] SW mode calibration
5108 10:57:49.733739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5109 10:57:49.737177 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5110 10:57:49.743779 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5111 10:57:49.746949 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 10:57:49.750465 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 10:57:49.757080 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 10:57:49.760501 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 10:57:49.763595 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 10:57:49.770420 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5117 10:57:49.773520 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5118 10:57:49.777130 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5119 10:57:49.783772 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 10:57:49.786646 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 10:57:49.790237 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 10:57:49.796785 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 10:57:49.799955 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 10:57:49.803707 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5125 10:57:49.810206 0 15 28 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
5126 10:57:49.813675 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5127 10:57:49.816706 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 10:57:49.823371 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 10:57:49.826636 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 10:57:49.830109 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 10:57:49.836512 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 10:57:49.840021 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 10:57:49.843321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 10:57:49.849855 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 10:57:49.852960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:57:49.856266 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:57:49.862874 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:57:49.866043 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:57:49.869331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:57:49.875895 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 10:57:49.879429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 10:57:49.882843 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 10:57:49.889605 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 10:57:49.892683 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 10:57:49.896049 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 10:57:49.902823 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 10:57:49.906024 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 10:57:49.909033 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5149 10:57:49.915819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5150 10:57:49.915920 Total UI for P1: 0, mck2ui 16
5151 10:57:49.922242 best dqsien dly found for B0: ( 1, 2, 24)
5152 10:57:49.925577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 10:57:49.928984 Total UI for P1: 0, mck2ui 16
5154 10:57:49.932635 best dqsien dly found for B1: ( 1, 2, 30)
5155 10:57:49.935893 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5156 10:57:49.939310 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5157 10:57:49.939407
5158 10:57:49.942125 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5159 10:57:49.945881 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5160 10:57:49.948727 [Gating] SW calibration Done
5161 10:57:49.948846 ==
5162 10:57:49.952316 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 10:57:49.955576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 10:57:49.958944 ==
5165 10:57:49.959049 RX Vref Scan: 0
5166 10:57:49.959118
5167 10:57:49.962258 RX Vref 0 -> 0, step: 1
5168 10:57:49.962327
5169 10:57:49.965197 RX Delay -80 -> 252, step: 8
5170 10:57:49.968610 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5171 10:57:49.972073 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5172 10:57:49.975433 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5173 10:57:49.978793 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5174 10:57:49.985220 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5175 10:57:49.988391 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5176 10:57:49.991859 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5177 10:57:49.995403 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5178 10:57:49.998173 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5179 10:57:50.005177 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5180 10:57:50.008435 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5181 10:57:50.011720 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5182 10:57:50.015107 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5183 10:57:50.018222 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5184 10:57:50.024669 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5185 10:57:50.027929 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5186 10:57:50.028003 ==
5187 10:57:50.031522 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 10:57:50.035057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 10:57:50.035157 ==
5190 10:57:50.035247 DQS Delay:
5191 10:57:50.038048 DQS0 = 0, DQS1 = 0
5192 10:57:50.038119 DQM Delay:
5193 10:57:50.041407 DQM0 = 107, DQM1 = 90
5194 10:57:50.041477 DQ Delay:
5195 10:57:50.044794 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5196 10:57:50.048070 DQ4 =107, DQ5 =103, DQ6 =115, DQ7 =115
5197 10:57:50.051209 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =87
5198 10:57:50.054661 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =103
5199 10:57:50.054733
5200 10:57:50.054794
5201 10:57:50.058015 ==
5202 10:57:50.060984 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 10:57:50.064366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 10:57:50.064438 ==
5205 10:57:50.064499
5206 10:57:50.064561
5207 10:57:50.068139 TX Vref Scan disable
5208 10:57:50.068234 == TX Byte 0 ==
5209 10:57:50.070893 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5210 10:57:50.077721 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5211 10:57:50.077820 == TX Byte 1 ==
5212 10:57:50.080853 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5213 10:57:50.087775 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5214 10:57:50.087877 ==
5215 10:57:50.091191 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 10:57:50.094102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 10:57:50.094174 ==
5218 10:57:50.094239
5219 10:57:50.094297
5220 10:57:50.097754 TX Vref Scan disable
5221 10:57:50.101216 == TX Byte 0 ==
5222 10:57:50.103991 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5223 10:57:50.107509 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5224 10:57:50.110831 == TX Byte 1 ==
5225 10:57:50.114034 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5226 10:57:50.117133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5227 10:57:50.117232
5228 10:57:50.120528 [DATLAT]
5229 10:57:50.120624 Freq=933, CH0 RK0
5230 10:57:50.120716
5231 10:57:50.123744 DATLAT Default: 0xd
5232 10:57:50.123838 0, 0xFFFF, sum = 0
5233 10:57:50.127341 1, 0xFFFF, sum = 0
5234 10:57:50.127438 2, 0xFFFF, sum = 0
5235 10:57:50.130931 3, 0xFFFF, sum = 0
5236 10:57:50.131031 4, 0xFFFF, sum = 0
5237 10:57:50.133766 5, 0xFFFF, sum = 0
5238 10:57:50.133833 6, 0xFFFF, sum = 0
5239 10:57:50.137288 7, 0xFFFF, sum = 0
5240 10:57:50.137387 8, 0xFFFF, sum = 0
5241 10:57:50.140205 9, 0xFFFF, sum = 0
5242 10:57:50.140275 10, 0x0, sum = 1
5243 10:57:50.143635 11, 0x0, sum = 2
5244 10:57:50.143703 12, 0x0, sum = 3
5245 10:57:50.146794 13, 0x0, sum = 4
5246 10:57:50.146861 best_step = 11
5247 10:57:50.146919
5248 10:57:50.146981 ==
5249 10:57:50.150249 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 10:57:50.156864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 10:57:50.156943 ==
5252 10:57:50.157006 RX Vref Scan: 1
5253 10:57:50.157064
5254 10:57:50.160243 RX Vref 0 -> 0, step: 1
5255 10:57:50.160335
5256 10:57:50.163882 RX Delay -61 -> 252, step: 4
5257 10:57:50.163949
5258 10:57:50.167091 Set Vref, RX VrefLevel [Byte0]: 60
5259 10:57:50.170479 [Byte1]: 49
5260 10:57:50.170554
5261 10:57:50.173617 Final RX Vref Byte 0 = 60 to rank0
5262 10:57:50.177081 Final RX Vref Byte 1 = 49 to rank0
5263 10:57:50.180612 Final RX Vref Byte 0 = 60 to rank1
5264 10:57:50.183578 Final RX Vref Byte 1 = 49 to rank1==
5265 10:57:50.186690 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 10:57:50.189920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 10:57:50.189992 ==
5268 10:57:50.193443 DQS Delay:
5269 10:57:50.193510 DQS0 = 0, DQS1 = 0
5270 10:57:50.193578 DQM Delay:
5271 10:57:50.196685 DQM0 = 107, DQM1 = 92
5272 10:57:50.196780 DQ Delay:
5273 10:57:50.200302 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5274 10:57:50.203465 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =116
5275 10:57:50.206592 DQ8 =86, DQ9 =78, DQ10 =90, DQ11 =90
5276 10:57:50.210069 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =102
5277 10:57:50.213103
5278 10:57:50.213170
5279 10:57:50.219743 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5280 10:57:50.222925 CH0 RK0: MR19=505, MR18=221E
5281 10:57:50.229820 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5282 10:57:50.229916
5283 10:57:50.232906 ----->DramcWriteLeveling(PI) begin...
5284 10:57:50.232978 ==
5285 10:57:50.236139 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 10:57:50.239477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 10:57:50.239549 ==
5288 10:57:50.243267 Write leveling (Byte 0): 35 => 35
5289 10:57:50.246070 Write leveling (Byte 1): 32 => 32
5290 10:57:50.249503 DramcWriteLeveling(PI) end<-----
5291 10:57:50.249574
5292 10:57:50.249634 ==
5293 10:57:50.252655 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 10:57:50.256166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 10:57:50.256237 ==
5296 10:57:50.259394 [Gating] SW mode calibration
5297 10:57:50.266230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 10:57:50.272522 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 10:57:50.275991 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 10:57:50.282474 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 10:57:50.285868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 10:57:50.289132 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 10:57:50.295635 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 10:57:50.298896 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 10:57:50.302106 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5306 10:57:50.308847 0 14 28 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 1)
5307 10:57:50.312362 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 10:57:50.315337 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 10:57:50.322271 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 10:57:50.325566 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 10:57:50.328709 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 10:57:50.335516 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 10:57:50.338624 0 15 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5314 10:57:50.342009 0 15 28 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
5315 10:57:50.348425 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 10:57:50.352084 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 10:57:50.355029 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 10:57:50.361662 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 10:57:50.364876 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 10:57:50.368214 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 10:57:50.374714 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 10:57:50.378159 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5323 10:57:50.381398 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 10:57:50.387820 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:57:50.391616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:57:50.394326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:57:50.401000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:57:50.404274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:57:50.407821 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:57:50.414518 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 10:57:50.417613 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 10:57:50.421195 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 10:57:50.427314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 10:57:50.430631 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 10:57:50.434061 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 10:57:50.440705 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 10:57:50.444059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 10:57:50.447412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5339 10:57:50.453835 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 10:57:50.453914 Total UI for P1: 0, mck2ui 16
5341 10:57:50.460630 best dqsien dly found for B0: ( 1, 2, 28)
5342 10:57:50.460726 Total UI for P1: 0, mck2ui 16
5343 10:57:50.467313 best dqsien dly found for B1: ( 1, 2, 28)
5344 10:57:50.470606 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5345 10:57:50.473819 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5346 10:57:50.473886
5347 10:57:50.476884 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5348 10:57:50.480200 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 10:57:50.483687 [Gating] SW calibration Done
5350 10:57:50.483751 ==
5351 10:57:50.486753 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 10:57:50.490115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 10:57:50.490181 ==
5354 10:57:50.493319 RX Vref Scan: 0
5355 10:57:50.493414
5356 10:57:50.493511 RX Vref 0 -> 0, step: 1
5357 10:57:50.493596
5358 10:57:50.496543 RX Delay -80 -> 252, step: 8
5359 10:57:50.499869 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5360 10:57:50.506719 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5361 10:57:50.509830 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5362 10:57:50.513249 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5363 10:57:50.516632 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5364 10:57:50.519750 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5365 10:57:50.526407 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5366 10:57:50.529791 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5367 10:57:50.533200 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5368 10:57:50.536350 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5369 10:57:50.539761 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5370 10:57:50.542775 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5371 10:57:50.549591 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5372 10:57:50.552911 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5373 10:57:50.556296 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5374 10:57:50.559731 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5375 10:57:50.559826 ==
5376 10:57:50.562919 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 10:57:50.566067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 10:57:50.569570 ==
5379 10:57:50.569641 DQS Delay:
5380 10:57:50.569702 DQS0 = 0, DQS1 = 0
5381 10:57:50.573172 DQM Delay:
5382 10:57:50.573278 DQM0 = 104, DQM1 = 90
5383 10:57:50.575837 DQ Delay:
5384 10:57:50.579477 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5385 10:57:50.582549 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5386 10:57:50.585958 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5387 10:57:50.589179 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5388 10:57:50.589272
5389 10:57:50.589360
5390 10:57:50.589450 ==
5391 10:57:50.592239 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 10:57:50.595756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 10:57:50.595834 ==
5394 10:57:50.595894
5395 10:57:50.595951
5396 10:57:50.598907 TX Vref Scan disable
5397 10:57:50.598977 == TX Byte 0 ==
5398 10:57:50.605742 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5399 10:57:50.608987 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5400 10:57:50.612142 == TX Byte 1 ==
5401 10:57:50.615666 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5402 10:57:50.618929 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5403 10:57:50.618999 ==
5404 10:57:50.621958 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 10:57:50.625407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 10:57:50.628533 ==
5407 10:57:50.628626
5408 10:57:50.628716
5409 10:57:50.628803 TX Vref Scan disable
5410 10:57:50.631952 == TX Byte 0 ==
5411 10:57:50.635537 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5412 10:57:50.642059 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5413 10:57:50.642134 == TX Byte 1 ==
5414 10:57:50.645494 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5415 10:57:50.651858 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5416 10:57:50.651953
5417 10:57:50.652052 [DATLAT]
5418 10:57:50.652139 Freq=933, CH0 RK1
5419 10:57:50.652226
5420 10:57:50.655249 DATLAT Default: 0xb
5421 10:57:50.658585 0, 0xFFFF, sum = 0
5422 10:57:50.658661 1, 0xFFFF, sum = 0
5423 10:57:50.661628 2, 0xFFFF, sum = 0
5424 10:57:50.661697 3, 0xFFFF, sum = 0
5425 10:57:50.664920 4, 0xFFFF, sum = 0
5426 10:57:50.665023 5, 0xFFFF, sum = 0
5427 10:57:50.668568 6, 0xFFFF, sum = 0
5428 10:57:50.668670 7, 0xFFFF, sum = 0
5429 10:57:50.671880 8, 0xFFFF, sum = 0
5430 10:57:50.671975 9, 0xFFFF, sum = 0
5431 10:57:50.675125 10, 0x0, sum = 1
5432 10:57:50.675196 11, 0x0, sum = 2
5433 10:57:50.678518 12, 0x0, sum = 3
5434 10:57:50.678618 13, 0x0, sum = 4
5435 10:57:50.678717 best_step = 11
5436 10:57:50.681603
5437 10:57:50.681682 ==
5438 10:57:50.684978 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 10:57:50.688154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 10:57:50.688254 ==
5441 10:57:50.688342 RX Vref Scan: 0
5442 10:57:50.688427
5443 10:57:50.691695 RX Vref 0 -> 0, step: 1
5444 10:57:50.691786
5445 10:57:50.694788 RX Delay -53 -> 252, step: 4
5446 10:57:50.701441 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5447 10:57:50.704752 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5448 10:57:50.707894 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5449 10:57:50.711264 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5450 10:57:50.714546 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5451 10:57:50.721005 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5452 10:57:50.724628 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5453 10:57:50.727936 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5454 10:57:50.731184 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5455 10:57:50.734396 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5456 10:57:50.737707 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5457 10:57:50.744360 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5458 10:57:50.747649 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5459 10:57:50.751187 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5460 10:57:50.754129 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5461 10:57:50.757756 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5462 10:57:50.760960 ==
5463 10:57:50.764580 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 10:57:50.767603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 10:57:50.767686 ==
5466 10:57:50.767749 DQS Delay:
5467 10:57:50.770925 DQS0 = 0, DQS1 = 0
5468 10:57:50.771019 DQM Delay:
5469 10:57:50.774390 DQM0 = 104, DQM1 = 92
5470 10:57:50.774459 DQ Delay:
5471 10:57:50.777720 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5472 10:57:50.780933 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =110
5473 10:57:50.784162 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5474 10:57:50.787340 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5475 10:57:50.787417
5476 10:57:50.787486
5477 10:57:50.797159 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5478 10:57:50.797261 CH0 RK1: MR19=505, MR18=2B0C
5479 10:57:50.803668 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5480 10:57:50.807137 [RxdqsGatingPostProcess] freq 933
5481 10:57:50.813670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 10:57:50.817004 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 10:57:50.820313 best DQS1 dly(2T, 0.5T) = (0, 10)
5484 10:57:50.823836 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 10:57:50.826960 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5486 10:57:50.830386 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 10:57:50.830465 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 10:57:50.833545 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 10:57:50.837072 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 10:57:50.840318 Pre-setting of DQS Precalculation
5491 10:57:50.846851 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 10:57:50.846950 ==
5493 10:57:50.850064 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 10:57:50.853153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 10:57:50.853252 ==
5496 10:57:50.859718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 10:57:50.866515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5498 10:57:50.869877 [CA 0] Center 37 (7~68) winsize 62
5499 10:57:50.873293 [CA 1] Center 37 (7~68) winsize 62
5500 10:57:50.876399 [CA 2] Center 36 (6~66) winsize 61
5501 10:57:50.879458 [CA 3] Center 34 (4~65) winsize 62
5502 10:57:50.882637 [CA 4] Center 35 (4~66) winsize 63
5503 10:57:50.886445 [CA 5] Center 34 (4~65) winsize 62
5504 10:57:50.886522
5505 10:57:50.889596 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5506 10:57:50.889664
5507 10:57:50.892581 [CATrainingPosCal] consider 1 rank data
5508 10:57:50.895933 u2DelayCellTimex100 = 270/100 ps
5509 10:57:50.899402 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5510 10:57:50.902507 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 10:57:50.906038 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5512 10:57:50.909291 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5513 10:57:50.915879 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5514 10:57:50.918950 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 10:57:50.919018
5516 10:57:50.922229 CA PerBit enable=1, Macro0, CA PI delay=34
5517 10:57:50.922304
5518 10:57:50.925808 [CBTSetCACLKResult] CA Dly = 34
5519 10:57:50.925876 CS Dly: 6 (0~37)
5520 10:57:50.925942 ==
5521 10:57:50.928757 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 10:57:50.935586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 10:57:50.935683 ==
5524 10:57:50.938692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 10:57:50.945769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5526 10:57:50.948624 [CA 0] Center 38 (8~69) winsize 62
5527 10:57:50.951793 [CA 1] Center 38 (7~69) winsize 63
5528 10:57:50.955316 [CA 2] Center 36 (6~67) winsize 62
5529 10:57:50.959159 [CA 3] Center 35 (5~66) winsize 62
5530 10:57:50.961797 [CA 4] Center 36 (6~66) winsize 61
5531 10:57:50.965555 [CA 5] Center 35 (5~65) winsize 61
5532 10:57:50.965647
5533 10:57:50.968533 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5534 10:57:50.968623
5535 10:57:50.971788 [CATrainingPosCal] consider 2 rank data
5536 10:57:50.975216 u2DelayCellTimex100 = 270/100 ps
5537 10:57:50.978620 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5538 10:57:50.981609 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5539 10:57:50.988246 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5540 10:57:50.991569 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5541 10:57:50.995154 CA4 delay=36 (6~66),Diff = 1 PI (6 cell)
5542 10:57:50.998283 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5543 10:57:50.998355
5544 10:57:51.001343 CA PerBit enable=1, Macro0, CA PI delay=35
5545 10:57:51.001409
5546 10:57:51.004870 [CBTSetCACLKResult] CA Dly = 35
5547 10:57:51.004963 CS Dly: 7 (0~39)
5548 10:57:51.008154
5549 10:57:51.011258 ----->DramcWriteLeveling(PI) begin...
5550 10:57:51.011351 ==
5551 10:57:51.014823 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 10:57:51.017859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 10:57:51.017951 ==
5554 10:57:51.021462 Write leveling (Byte 0): 28 => 28
5555 10:57:51.024673 Write leveling (Byte 1): 29 => 29
5556 10:57:51.027814 DramcWriteLeveling(PI) end<-----
5557 10:57:51.027907
5558 10:57:51.027994 ==
5559 10:57:51.031563 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 10:57:51.034542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 10:57:51.034624 ==
5562 10:57:51.037854 [Gating] SW mode calibration
5563 10:57:51.044297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 10:57:51.051011 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 10:57:51.054201 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 10:57:51.057698 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 10:57:51.064336 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 10:57:51.067658 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 10:57:51.070679 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 10:57:51.077305 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5571 10:57:51.080358 0 14 24 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
5572 10:57:51.083600 0 14 28 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (0 0)
5573 10:57:51.090768 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 10:57:51.093648 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 10:57:51.097143 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 10:57:51.103632 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 10:57:51.107133 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 10:57:51.110208 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 10:57:51.116585 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5580 10:57:51.119929 0 15 28 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
5581 10:57:51.123289 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 10:57:51.129924 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 10:57:51.133100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 10:57:51.136376 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 10:57:51.143316 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 10:57:51.146527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5587 10:57:51.149907 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 10:57:51.156188 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5589 10:57:51.159567 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:57:51.162715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:57:51.169819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:57:51.172958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:57:51.176049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:57:51.182744 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:57:51.186091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:57:51.189515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:57:51.195832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 10:57:51.199303 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 10:57:51.202630 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 10:57:51.209019 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 10:57:51.212494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 10:57:51.215961 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5603 10:57:51.222651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5604 10:57:51.225584 Total UI for P1: 0, mck2ui 16
5605 10:57:51.229053 best dqsien dly found for B0: ( 1, 2, 20)
5606 10:57:51.232265 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5607 10:57:51.235577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 10:57:51.239267 Total UI for P1: 0, mck2ui 16
5609 10:57:51.242077 best dqsien dly found for B1: ( 1, 2, 26)
5610 10:57:51.245437 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5611 10:57:51.248607 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5612 10:57:51.251813
5613 10:57:51.255324 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5614 10:57:51.258638 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5615 10:57:51.261515 [Gating] SW calibration Done
5616 10:57:51.261599 ==
5617 10:57:51.264903 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 10:57:51.268224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 10:57:51.268308 ==
5620 10:57:51.268396 RX Vref Scan: 0
5621 10:57:51.271887
5622 10:57:51.271970 RX Vref 0 -> 0, step: 1
5623 10:57:51.272053
5624 10:57:51.274913 RX Delay -80 -> 252, step: 8
5625 10:57:51.278410 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5626 10:57:51.281439 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5627 10:57:51.288102 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5628 10:57:51.291466 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5629 10:57:51.294671 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5630 10:57:51.297948 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5631 10:57:51.301264 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5632 10:57:51.304864 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5633 10:57:51.311399 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5634 10:57:51.314624 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5635 10:57:51.317766 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5636 10:57:51.321022 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5637 10:57:51.324353 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5638 10:57:51.330877 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5639 10:57:51.334536 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5640 10:57:51.337650 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5641 10:57:51.337731 ==
5642 10:57:51.340978 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 10:57:51.344029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 10:57:51.344111 ==
5645 10:57:51.347432 DQS Delay:
5646 10:57:51.347514 DQS0 = 0, DQS1 = 0
5647 10:57:51.350605 DQM Delay:
5648 10:57:51.350686 DQM0 = 101, DQM1 = 95
5649 10:57:51.350750 DQ Delay:
5650 10:57:51.354104 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5651 10:57:51.357421 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5652 10:57:51.360642 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5653 10:57:51.363929 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5654 10:57:51.367266
5655 10:57:51.367346
5656 10:57:51.367410 ==
5657 10:57:51.370444 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 10:57:51.374155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 10:57:51.374236 ==
5660 10:57:51.374301
5661 10:57:51.374359
5662 10:57:51.377090 TX Vref Scan disable
5663 10:57:51.377171 == TX Byte 0 ==
5664 10:57:51.383811 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5665 10:57:51.386964 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5666 10:57:51.387045 == TX Byte 1 ==
5667 10:57:51.393685 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5668 10:57:51.396955 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5669 10:57:51.397037 ==
5670 10:57:51.400420 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 10:57:51.403484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 10:57:51.403566 ==
5673 10:57:51.403630
5674 10:57:51.403689
5675 10:57:51.406714 TX Vref Scan disable
5676 10:57:51.410263 == TX Byte 0 ==
5677 10:57:51.413413 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5678 10:57:51.416616 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5679 10:57:51.420035 == TX Byte 1 ==
5680 10:57:51.423279 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5681 10:57:51.426443 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5682 10:57:51.429777
5683 10:57:51.429858 [DATLAT]
5684 10:57:51.429922 Freq=933, CH1 RK0
5685 10:57:51.429981
5686 10:57:51.433178 DATLAT Default: 0xd
5687 10:57:51.433259 0, 0xFFFF, sum = 0
5688 10:57:51.436494 1, 0xFFFF, sum = 0
5689 10:57:51.436576 2, 0xFFFF, sum = 0
5690 10:57:51.439566 3, 0xFFFF, sum = 0
5691 10:57:51.443043 4, 0xFFFF, sum = 0
5692 10:57:51.443126 5, 0xFFFF, sum = 0
5693 10:57:51.446509 6, 0xFFFF, sum = 0
5694 10:57:51.446592 7, 0xFFFF, sum = 0
5695 10:57:51.449742 8, 0xFFFF, sum = 0
5696 10:57:51.449824 9, 0xFFFF, sum = 0
5697 10:57:51.453284 10, 0x0, sum = 1
5698 10:57:51.453366 11, 0x0, sum = 2
5699 10:57:51.456272 12, 0x0, sum = 3
5700 10:57:51.456354 13, 0x0, sum = 4
5701 10:57:51.456419 best_step = 11
5702 10:57:51.456477
5703 10:57:51.459505 ==
5704 10:57:51.462659 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 10:57:51.466046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 10:57:51.466128 ==
5707 10:57:51.466193 RX Vref Scan: 1
5708 10:57:51.466252
5709 10:57:51.469138 RX Vref 0 -> 0, step: 1
5710 10:57:51.469225
5711 10:57:51.472944 RX Delay -53 -> 252, step: 4
5712 10:57:51.473025
5713 10:57:51.475894 Set Vref, RX VrefLevel [Byte0]: 54
5714 10:57:51.478942 [Byte1]: 53
5715 10:57:51.479023
5716 10:57:51.482541 Final RX Vref Byte 0 = 54 to rank0
5717 10:57:51.485714 Final RX Vref Byte 1 = 53 to rank0
5718 10:57:51.488839 Final RX Vref Byte 0 = 54 to rank1
5719 10:57:51.492267 Final RX Vref Byte 1 = 53 to rank1==
5720 10:57:51.495659 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 10:57:51.502256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 10:57:51.502338 ==
5723 10:57:51.502403 DQS Delay:
5724 10:57:51.502463 DQS0 = 0, DQS1 = 0
5725 10:57:51.505852 DQM Delay:
5726 10:57:51.505934 DQM0 = 105, DQM1 = 98
5727 10:57:51.509215 DQ Delay:
5728 10:57:51.512364 DQ0 =110, DQ1 =98, DQ2 =98, DQ3 =102
5729 10:57:51.515458 DQ4 =104, DQ5 =114, DQ6 =114, DQ7 =102
5730 10:57:51.518668 DQ8 =88, DQ9 =84, DQ10 =102, DQ11 =92
5731 10:57:51.522077 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =104
5732 10:57:51.522158
5733 10:57:51.522222
5734 10:57:51.528515 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5735 10:57:51.531848 CH1 RK0: MR19=505, MR18=1A32
5736 10:57:51.538730 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5737 10:57:51.538811
5738 10:57:51.541920 ----->DramcWriteLeveling(PI) begin...
5739 10:57:51.542002 ==
5740 10:57:51.545601 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 10:57:51.548616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 10:57:51.551952 ==
5743 10:57:51.552034 Write leveling (Byte 0): 28 => 28
5744 10:57:51.555247 Write leveling (Byte 1): 28 => 28
5745 10:57:51.559175 DramcWriteLeveling(PI) end<-----
5746 10:57:51.559258
5747 10:57:51.559321 ==
5748 10:57:51.561978 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 10:57:51.568647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 10:57:51.568729 ==
5751 10:57:51.568835 [Gating] SW mode calibration
5752 10:57:51.578562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5753 10:57:51.582192 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5754 10:57:51.585374 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5755 10:57:51.591731 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 10:57:51.595025 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 10:57:51.598385 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 10:57:51.604941 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 10:57:51.608557 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 10:57:51.611846 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
5761 10:57:51.618007 0 14 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 0)
5762 10:57:51.621917 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 10:57:51.624747 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 10:57:51.631402 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 10:57:51.634892 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 10:57:51.638041 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 10:57:51.644588 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 10:57:51.647803 0 15 24 | B1->B0 | 2928 2727 | 1 0 | (0 0) (0 0)
5769 10:57:51.654281 0 15 28 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (0 0)
5770 10:57:51.657675 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 10:57:51.661001 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 10:57:51.664133 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 10:57:51.670845 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 10:57:51.674306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 10:57:51.677218 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 10:57:51.684158 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5777 10:57:51.687333 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5778 10:57:51.690531 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:57:51.697487 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:57:51.700477 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:57:51.703793 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:57:51.710837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:57:51.713761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 10:57:51.716889 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 10:57:51.723876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 10:57:51.727012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 10:57:51.730288 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 10:57:51.736943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 10:57:51.740467 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 10:57:51.743437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 10:57:51.750310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 10:57:51.753420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 10:57:51.757001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5794 10:57:51.760077 Total UI for P1: 0, mck2ui 16
5795 10:57:51.763704 best dqsien dly found for B1: ( 1, 2, 24)
5796 10:57:51.770019 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 10:57:51.770101 Total UI for P1: 0, mck2ui 16
5798 10:57:51.776887 best dqsien dly found for B0: ( 1, 2, 26)
5799 10:57:51.779995 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5800 10:57:51.783108 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5801 10:57:51.783190
5802 10:57:51.786390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5803 10:57:51.790068 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 10:57:51.793219 [Gating] SW calibration Done
5805 10:57:51.793301 ==
5806 10:57:51.796716 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 10:57:51.799877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 10:57:51.799960 ==
5809 10:57:51.803119 RX Vref Scan: 0
5810 10:57:51.803200
5811 10:57:51.803265 RX Vref 0 -> 0, step: 1
5812 10:57:51.806211
5813 10:57:51.806293 RX Delay -80 -> 252, step: 8
5814 10:57:51.812956 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5815 10:57:51.816654 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5816 10:57:51.819831 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5817 10:57:51.822766 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5818 10:57:51.825953 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5819 10:57:51.829201 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5820 10:57:51.835963 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5821 10:57:51.839224 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5822 10:57:51.842354 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5823 10:57:51.846074 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5824 10:57:51.849095 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5825 10:57:51.855696 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5826 10:57:51.858964 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5827 10:57:51.862233 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5828 10:57:51.865398 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5829 10:57:51.868737 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5830 10:57:51.872406 ==
5831 10:57:51.872488 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 10:57:51.878465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 10:57:51.878548 ==
5834 10:57:51.878612 DQS Delay:
5835 10:57:51.881905 DQS0 = 0, DQS1 = 0
5836 10:57:51.881987 DQM Delay:
5837 10:57:51.885287 DQM0 = 102, DQM1 = 95
5838 10:57:51.885369 DQ Delay:
5839 10:57:51.888703 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5840 10:57:51.892026 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5841 10:57:51.895286 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5842 10:57:51.898644 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5843 10:57:51.898726
5844 10:57:51.898790
5845 10:57:51.898851 ==
5846 10:57:51.901662 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 10:57:51.905078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 10:57:51.908812 ==
5849 10:57:51.908894
5850 10:57:51.908958
5851 10:57:51.909017 TX Vref Scan disable
5852 10:57:51.911542 == TX Byte 0 ==
5853 10:57:51.915103 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5854 10:57:51.918290 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5855 10:57:51.921711 == TX Byte 1 ==
5856 10:57:51.924753 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 10:57:51.928066 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 10:57:51.931733 ==
5859 10:57:51.931814 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 10:57:51.938177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 10:57:51.938260 ==
5862 10:57:51.938325
5863 10:57:51.938385
5864 10:57:51.941301 TX Vref Scan disable
5865 10:57:51.941382 == TX Byte 0 ==
5866 10:57:51.947967 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5867 10:57:51.951536 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5868 10:57:51.951618 == TX Byte 1 ==
5869 10:57:51.958145 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5870 10:57:51.961561 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5871 10:57:51.961643
5872 10:57:51.961708 [DATLAT]
5873 10:57:51.964660 Freq=933, CH1 RK1
5874 10:57:51.964742
5875 10:57:51.964812 DATLAT Default: 0xb
5876 10:57:51.967739 0, 0xFFFF, sum = 0
5877 10:57:51.967823 1, 0xFFFF, sum = 0
5878 10:57:51.971036 2, 0xFFFF, sum = 0
5879 10:57:51.971118 3, 0xFFFF, sum = 0
5880 10:57:51.974419 4, 0xFFFF, sum = 0
5881 10:57:51.974502 5, 0xFFFF, sum = 0
5882 10:57:51.977745 6, 0xFFFF, sum = 0
5883 10:57:51.977828 7, 0xFFFF, sum = 0
5884 10:57:51.981259 8, 0xFFFF, sum = 0
5885 10:57:51.984288 9, 0xFFFF, sum = 0
5886 10:57:51.984372 10, 0x0, sum = 1
5887 10:57:51.984437 11, 0x0, sum = 2
5888 10:57:51.987556 12, 0x0, sum = 3
5889 10:57:51.987639 13, 0x0, sum = 4
5890 10:57:51.991328 best_step = 11
5891 10:57:51.991410
5892 10:57:51.991474 ==
5893 10:57:51.994419 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 10:57:51.997452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 10:57:51.997535 ==
5896 10:57:52.000931 RX Vref Scan: 0
5897 10:57:52.001012
5898 10:57:52.001077 RX Vref 0 -> 0, step: 1
5899 10:57:52.001136
5900 10:57:52.004108 RX Delay -53 -> 252, step: 4
5901 10:57:52.011791 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5902 10:57:52.014683 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5903 10:57:52.018030 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5904 10:57:52.021507 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5905 10:57:52.024787 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5906 10:57:52.031467 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5907 10:57:52.034758 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5908 10:57:52.038056 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5909 10:57:52.041212 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5910 10:57:52.044398 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5911 10:57:52.051295 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5912 10:57:52.054464 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5913 10:57:52.057659 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5914 10:57:52.061203 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5915 10:57:52.064521 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5916 10:57:52.071219 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5917 10:57:52.071306 ==
5918 10:57:52.074601 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 10:57:52.077659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 10:57:52.077741 ==
5921 10:57:52.077806 DQS Delay:
5922 10:57:52.081147 DQS0 = 0, DQS1 = 0
5923 10:57:52.081228 DQM Delay:
5924 10:57:52.084220 DQM0 = 104, DQM1 = 98
5925 10:57:52.084301 DQ Delay:
5926 10:57:52.087752 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5927 10:57:52.091469 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =100
5928 10:57:52.094369 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5929 10:57:52.097635 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =106
5930 10:57:52.097717
5931 10:57:52.097782
5932 10:57:52.107454 [DQSOSCAuto] RK1, (LSB)MR18= 0x1efa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 412 ps
5933 10:57:52.111087 CH1 RK1: MR19=504, MR18=1EFA
5934 10:57:52.114172 CH1_RK1: MR19=0x504, MR18=0x1EFA, DQSOSC=412, MR23=63, INC=63, DEC=42
5935 10:57:52.117664 [RxdqsGatingPostProcess] freq 933
5936 10:57:52.124361 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 10:57:52.127296 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 10:57:52.130717 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 10:57:52.134178 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 10:57:52.137250 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 10:57:52.140592 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 10:57:52.143829 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 10:57:52.147599 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 10:57:52.150518 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 10:57:52.150600 Pre-setting of DQS Precalculation
5946 10:57:52.157207 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 10:57:52.163764 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 10:57:52.170314 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 10:57:52.170396
5950 10:57:52.170462
5951 10:57:52.173722 [Calibration Summary] 1866 Mbps
5952 10:57:52.177197 CH 0, Rank 0
5953 10:57:52.177278 SW Impedance : PASS
5954 10:57:52.180594 DUTY Scan : NO K
5955 10:57:52.184056 ZQ Calibration : PASS
5956 10:57:52.184138 Jitter Meter : NO K
5957 10:57:52.186746 CBT Training : PASS
5958 10:57:52.190818 Write leveling : PASS
5959 10:57:52.190899 RX DQS gating : PASS
5960 10:57:52.193517 RX DQ/DQS(RDDQC) : PASS
5961 10:57:52.196946 TX DQ/DQS : PASS
5962 10:57:52.197054 RX DATLAT : PASS
5963 10:57:52.200247 RX DQ/DQS(Engine): PASS
5964 10:57:52.203272 TX OE : NO K
5965 10:57:52.203356 All Pass.
5966 10:57:52.203422
5967 10:57:52.203483 CH 0, Rank 1
5968 10:57:52.206734 SW Impedance : PASS
5969 10:57:52.210016 DUTY Scan : NO K
5970 10:57:52.210131 ZQ Calibration : PASS
5971 10:57:52.213536 Jitter Meter : NO K
5972 10:57:52.216688 CBT Training : PASS
5973 10:57:52.216793 Write leveling : PASS
5974 10:57:52.219936 RX DQS gating : PASS
5975 10:57:52.220018 RX DQ/DQS(RDDQC) : PASS
5976 10:57:52.223243 TX DQ/DQS : PASS
5977 10:57:52.226711 RX DATLAT : PASS
5978 10:57:52.226793 RX DQ/DQS(Engine): PASS
5979 10:57:52.230074 TX OE : NO K
5980 10:57:52.230157 All Pass.
5981 10:57:52.230224
5982 10:57:52.233699 CH 1, Rank 0
5983 10:57:52.233782 SW Impedance : PASS
5984 10:57:52.236624 DUTY Scan : NO K
5985 10:57:52.240102 ZQ Calibration : PASS
5986 10:57:52.240185 Jitter Meter : NO K
5987 10:57:52.243075 CBT Training : PASS
5988 10:57:52.246279 Write leveling : PASS
5989 10:57:52.246361 RX DQS gating : PASS
5990 10:57:52.250107 RX DQ/DQS(RDDQC) : PASS
5991 10:57:52.252995 TX DQ/DQS : PASS
5992 10:57:52.253078 RX DATLAT : PASS
5993 10:57:52.256378 RX DQ/DQS(Engine): PASS
5994 10:57:52.259575 TX OE : NO K
5995 10:57:52.259659 All Pass.
5996 10:57:52.259724
5997 10:57:52.259785 CH 1, Rank 1
5998 10:57:52.262930 SW Impedance : PASS
5999 10:57:52.266242 DUTY Scan : NO K
6000 10:57:52.266325 ZQ Calibration : PASS
6001 10:57:52.269842 Jitter Meter : NO K
6002 10:57:52.272716 CBT Training : PASS
6003 10:57:52.272807 Write leveling : PASS
6004 10:57:52.276094 RX DQS gating : PASS
6005 10:57:52.276200 RX DQ/DQS(RDDQC) : PASS
6006 10:57:52.279356 TX DQ/DQS : PASS
6007 10:57:52.282937 RX DATLAT : PASS
6008 10:57:52.283020 RX DQ/DQS(Engine): PASS
6009 10:57:52.286017 TX OE : NO K
6010 10:57:52.286100 All Pass.
6011 10:57:52.286167
6012 10:57:52.289814 DramC Write-DBI off
6013 10:57:52.292438 PER_BANK_REFRESH: Hybrid Mode
6014 10:57:52.292548 TX_TRACKING: ON
6015 10:57:52.302468 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 10:57:52.306095 [FAST_K] Save calibration result to emmc
6017 10:57:52.309181 dramc_set_vcore_voltage set vcore to 650000
6018 10:57:52.312575 Read voltage for 400, 6
6019 10:57:52.312658 Vio18 = 0
6020 10:57:52.315795 Vcore = 650000
6021 10:57:52.315877 Vdram = 0
6022 10:57:52.315943 Vddq = 0
6023 10:57:52.316004 Vmddr = 0
6024 10:57:52.322211 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 10:57:52.329051 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 10:57:52.329165 MEM_TYPE=3, freq_sel=20
6027 10:57:52.332219 sv_algorithm_assistance_LP4_800
6028 10:57:52.336058 ============ PULL DRAM RESETB DOWN ============
6029 10:57:52.342297 ========== PULL DRAM RESETB DOWN end =========
6030 10:57:52.345465 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 10:57:52.348993 ===================================
6032 10:57:52.352150 LPDDR4 DRAM CONFIGURATION
6033 10:57:52.355483 ===================================
6034 10:57:52.355566 EX_ROW_EN[0] = 0x0
6035 10:57:52.358644 EX_ROW_EN[1] = 0x0
6036 10:57:52.358727 LP4Y_EN = 0x0
6037 10:57:52.362000 WORK_FSP = 0x0
6038 10:57:52.365087 WL = 0x2
6039 10:57:52.365170 RL = 0x2
6040 10:57:52.368618 BL = 0x2
6041 10:57:52.368700 RPST = 0x0
6042 10:57:52.371814 RD_PRE = 0x0
6043 10:57:52.371897 WR_PRE = 0x1
6044 10:57:52.375269 WR_PST = 0x0
6045 10:57:52.375352 DBI_WR = 0x0
6046 10:57:52.378336 DBI_RD = 0x0
6047 10:57:52.378418 OTF = 0x1
6048 10:57:52.381645 ===================================
6049 10:57:52.384796 ===================================
6050 10:57:52.388138 ANA top config
6051 10:57:52.391633 ===================================
6052 10:57:52.391716 DLL_ASYNC_EN = 0
6053 10:57:52.395208 ALL_SLAVE_EN = 1
6054 10:57:52.398212 NEW_RANK_MODE = 1
6055 10:57:52.401481 DLL_IDLE_MODE = 1
6056 10:57:52.404689 LP45_APHY_COMB_EN = 1
6057 10:57:52.404777 TX_ODT_DIS = 1
6058 10:57:52.408292 NEW_8X_MODE = 1
6059 10:57:52.411590 ===================================
6060 10:57:52.414986 ===================================
6061 10:57:52.418124 data_rate = 800
6062 10:57:52.421532 CKR = 1
6063 10:57:52.424730 DQ_P2S_RATIO = 4
6064 10:57:52.428113 ===================================
6065 10:57:52.428196 CA_P2S_RATIO = 4
6066 10:57:52.431448 DQ_CA_OPEN = 0
6067 10:57:52.434615 DQ_SEMI_OPEN = 1
6068 10:57:52.437982 CA_SEMI_OPEN = 1
6069 10:57:52.441304 CA_FULL_RATE = 0
6070 10:57:52.444634 DQ_CKDIV4_EN = 0
6071 10:57:52.444718 CA_CKDIV4_EN = 1
6072 10:57:52.447990 CA_PREDIV_EN = 0
6073 10:57:52.451440 PH8_DLY = 0
6074 10:57:52.454737 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 10:57:52.457808 DQ_AAMCK_DIV = 0
6076 10:57:52.461357 CA_AAMCK_DIV = 0
6077 10:57:52.461439 CA_ADMCK_DIV = 4
6078 10:57:52.464681 DQ_TRACK_CA_EN = 0
6079 10:57:52.467823 CA_PICK = 800
6080 10:57:52.471019 CA_MCKIO = 400
6081 10:57:52.474255 MCKIO_SEMI = 400
6082 10:57:52.477693 PLL_FREQ = 3016
6083 10:57:52.480762 DQ_UI_PI_RATIO = 32
6084 10:57:52.484407 CA_UI_PI_RATIO = 32
6085 10:57:52.487428 ===================================
6086 10:57:52.490831 ===================================
6087 10:57:52.490914 memory_type:LPDDR4
6088 10:57:52.493904 GP_NUM : 10
6089 10:57:52.497520 SRAM_EN : 1
6090 10:57:52.497603 MD32_EN : 0
6091 10:57:52.500691 ===================================
6092 10:57:52.504334 [ANA_INIT] >>>>>>>>>>>>>>
6093 10:57:52.507157 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 10:57:52.510695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 10:57:52.513944 ===================================
6096 10:57:52.517170 data_rate = 800,PCW = 0X7400
6097 10:57:52.520588 ===================================
6098 10:57:52.523717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 10:57:52.527309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 10:57:52.540254 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 10:57:52.543606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 10:57:52.547049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 10:57:52.550182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 10:57:52.553690 [ANA_INIT] flow start
6105 10:57:52.556812 [ANA_INIT] PLL >>>>>>>>
6106 10:57:52.556894 [ANA_INIT] PLL <<<<<<<<
6107 10:57:52.559776 [ANA_INIT] MIDPI >>>>>>>>
6108 10:57:52.563451 [ANA_INIT] MIDPI <<<<<<<<
6109 10:57:52.563534 [ANA_INIT] DLL >>>>>>>>
6110 10:57:52.566640 [ANA_INIT] flow end
6111 10:57:52.569908 ============ LP4 DIFF to SE enter ============
6112 10:57:52.573309 ============ LP4 DIFF to SE exit ============
6113 10:57:52.576801 [ANA_INIT] <<<<<<<<<<<<<
6114 10:57:52.579953 [Flow] Enable top DCM control >>>>>
6115 10:57:52.583208 [Flow] Enable top DCM control <<<<<
6116 10:57:52.586621 Enable DLL master slave shuffle
6117 10:57:52.593150 ==============================================================
6118 10:57:52.593234 Gating Mode config
6119 10:57:52.600017 ==============================================================
6120 10:57:52.600100 Config description:
6121 10:57:52.609941 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 10:57:52.616495 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 10:57:52.622940 SELPH_MODE 0: By rank 1: By Phase
6124 10:57:52.626368 ==============================================================
6125 10:57:52.629404 GAT_TRACK_EN = 0
6126 10:57:52.632921 RX_GATING_MODE = 2
6127 10:57:52.636111 RX_GATING_TRACK_MODE = 2
6128 10:57:52.639419 SELPH_MODE = 1
6129 10:57:52.642695 PICG_EARLY_EN = 1
6130 10:57:52.645841 VALID_LAT_VALUE = 1
6131 10:57:52.652627 ==============================================================
6132 10:57:52.656075 Enter into Gating configuration >>>>
6133 10:57:52.659210 Exit from Gating configuration <<<<
6134 10:57:52.662786 Enter into DVFS_PRE_config >>>>>
6135 10:57:52.672797 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 10:57:52.676056 Exit from DVFS_PRE_config <<<<<
6137 10:57:52.679078 Enter into PICG configuration >>>>
6138 10:57:52.682607 Exit from PICG configuration <<<<
6139 10:57:52.685887 [RX_INPUT] configuration >>>>>
6140 10:57:52.685957 [RX_INPUT] configuration <<<<<
6141 10:57:52.692323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 10:57:52.698933 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 10:57:52.705406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 10:57:52.709110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 10:57:52.715651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 10:57:52.722095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 10:57:52.725315 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 10:57:52.731761 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 10:57:52.735692 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 10:57:52.738486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 10:57:52.741928 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 10:57:52.748457 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 10:57:52.751900 ===================================
6154 10:57:52.751982 LPDDR4 DRAM CONFIGURATION
6155 10:57:52.755300 ===================================
6156 10:57:52.758232 EX_ROW_EN[0] = 0x0
6157 10:57:52.761643 EX_ROW_EN[1] = 0x0
6158 10:57:52.761725 LP4Y_EN = 0x0
6159 10:57:52.765269 WORK_FSP = 0x0
6160 10:57:52.765351 WL = 0x2
6161 10:57:52.768086 RL = 0x2
6162 10:57:52.768168 BL = 0x2
6163 10:57:52.771665 RPST = 0x0
6164 10:57:52.771747 RD_PRE = 0x0
6165 10:57:52.774617 WR_PRE = 0x1
6166 10:57:52.774699 WR_PST = 0x0
6167 10:57:52.778239 DBI_WR = 0x0
6168 10:57:52.778321 DBI_RD = 0x0
6169 10:57:52.781234 OTF = 0x1
6170 10:57:52.784711 ===================================
6171 10:57:52.788097 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 10:57:52.791634 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 10:57:52.798158 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 10:57:52.801118 ===================================
6175 10:57:52.801201 LPDDR4 DRAM CONFIGURATION
6176 10:57:52.804600 ===================================
6177 10:57:52.807573 EX_ROW_EN[0] = 0x10
6178 10:57:52.811020 EX_ROW_EN[1] = 0x0
6179 10:57:52.811102 LP4Y_EN = 0x0
6180 10:57:52.814494 WORK_FSP = 0x0
6181 10:57:52.814576 WL = 0x2
6182 10:57:52.817552 RL = 0x2
6183 10:57:52.817634 BL = 0x2
6184 10:57:52.820973 RPST = 0x0
6185 10:57:52.821055 RD_PRE = 0x0
6186 10:57:52.824501 WR_PRE = 0x1
6187 10:57:52.824584 WR_PST = 0x0
6188 10:57:52.827424 DBI_WR = 0x0
6189 10:57:52.827507 DBI_RD = 0x0
6190 10:57:52.830924 OTF = 0x1
6191 10:57:52.833930 ===================================
6192 10:57:52.840656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 10:57:52.844071 nWR fixed to 30
6194 10:57:52.847295 [ModeRegInit_LP4] CH0 RK0
6195 10:57:52.847379 [ModeRegInit_LP4] CH0 RK1
6196 10:57:52.850644 [ModeRegInit_LP4] CH1 RK0
6197 10:57:52.853790 [ModeRegInit_LP4] CH1 RK1
6198 10:57:52.853873 match AC timing 19
6199 10:57:52.860727 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 10:57:52.863652 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 10:57:52.867140 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 10:57:52.873605 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 10:57:52.876965 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 10:57:52.877049 ==
6205 10:57:52.880366 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 10:57:52.883521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 10:57:52.883605 ==
6208 10:57:52.890115 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 10:57:52.896969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6210 10:57:52.900122 [CA 0] Center 36 (8~64) winsize 57
6211 10:57:52.903482 [CA 1] Center 36 (8~64) winsize 57
6212 10:57:52.906930 [CA 2] Center 36 (8~64) winsize 57
6213 10:57:52.909783 [CA 3] Center 36 (8~64) winsize 57
6214 10:57:52.913484 [CA 4] Center 36 (8~64) winsize 57
6215 10:57:52.913567 [CA 5] Center 36 (8~64) winsize 57
6216 10:57:52.916436
6217 10:57:52.919730 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6218 10:57:52.919813
6219 10:57:52.923075 [CATrainingPosCal] consider 1 rank data
6220 10:57:52.926411 u2DelayCellTimex100 = 270/100 ps
6221 10:57:52.929788 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 10:57:52.933092 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 10:57:52.936586 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 10:57:52.939935 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 10:57:52.943034 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 10:57:52.946380 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 10:57:52.946463
6228 10:57:52.949694 CA PerBit enable=1, Macro0, CA PI delay=36
6229 10:57:52.949777
6230 10:57:52.953131 [CBTSetCACLKResult] CA Dly = 36
6231 10:57:52.956350 CS Dly: 1 (0~32)
6232 10:57:52.956433 ==
6233 10:57:52.959921 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 10:57:52.962883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 10:57:52.962967 ==
6236 10:57:52.969905 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 10:57:52.976370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6238 10:57:52.979987 [CA 0] Center 36 (8~64) winsize 57
6239 10:57:52.980070 [CA 1] Center 36 (8~64) winsize 57
6240 10:57:52.983242 [CA 2] Center 36 (8~64) winsize 57
6241 10:57:52.986278 [CA 3] Center 36 (8~64) winsize 57
6242 10:57:52.989770 [CA 4] Center 36 (8~64) winsize 57
6243 10:57:52.992783 [CA 5] Center 36 (8~64) winsize 57
6244 10:57:52.992880
6245 10:57:52.996180 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6246 10:57:52.996262
6247 10:57:53.003192 [CATrainingPosCal] consider 2 rank data
6248 10:57:53.003275 u2DelayCellTimex100 = 270/100 ps
6249 10:57:53.006349 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:57:53.013007 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 10:57:53.016157 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 10:57:53.019185 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 10:57:53.022497 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 10:57:53.025962 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 10:57:53.026045
6256 10:57:53.029426 CA PerBit enable=1, Macro0, CA PI delay=36
6257 10:57:53.029509
6258 10:57:53.032692 [CBTSetCACLKResult] CA Dly = 36
6259 10:57:53.035738 CS Dly: 1 (0~32)
6260 10:57:53.035846
6261 10:57:53.039113 ----->DramcWriteLeveling(PI) begin...
6262 10:57:53.039198 ==
6263 10:57:53.042534 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 10:57:53.045716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 10:57:53.045799 ==
6266 10:57:53.048876 Write leveling (Byte 0): 40 => 8
6267 10:57:53.052268 Write leveling (Byte 1): 32 => 0
6268 10:57:53.055572 DramcWriteLeveling(PI) end<-----
6269 10:57:53.055655
6270 10:57:53.055721 ==
6271 10:57:53.058811 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 10:57:53.062213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 10:57:53.062297 ==
6274 10:57:53.066185 [Gating] SW mode calibration
6275 10:57:53.072176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 10:57:53.078866 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 10:57:53.081937 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 10:57:53.085313 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 10:57:53.092001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 10:57:53.095163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 10:57:53.098548 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 10:57:53.105222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 10:57:53.108233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 10:57:53.111953 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 10:57:53.118316 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 10:57:53.121442 Total UI for P1: 0, mck2ui 16
6287 10:57:53.125208 best dqsien dly found for B0: ( 0, 14, 24)
6288 10:57:53.125279 Total UI for P1: 0, mck2ui 16
6289 10:57:53.131580 best dqsien dly found for B1: ( 0, 14, 24)
6290 10:57:53.135091 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 10:57:53.138194 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 10:57:53.138297
6293 10:57:53.141389 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 10:57:53.144900 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 10:57:53.147853 [Gating] SW calibration Done
6296 10:57:53.147923 ==
6297 10:57:53.151846 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 10:57:53.154582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 10:57:53.154661 ==
6300 10:57:53.158233 RX Vref Scan: 0
6301 10:57:53.158299
6302 10:57:53.161112 RX Vref 0 -> 0, step: 1
6303 10:57:53.161183
6304 10:57:53.161242 RX Delay -410 -> 252, step: 16
6305 10:57:53.168221 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6306 10:57:53.171073 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6307 10:57:53.174586 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6308 10:57:53.181076 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6309 10:57:53.184309 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6310 10:57:53.187516 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6311 10:57:53.191003 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6312 10:57:53.197295 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6313 10:57:53.200923 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6314 10:57:53.203955 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6315 10:57:53.207465 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6316 10:57:53.214287 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6317 10:57:53.217513 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6318 10:57:53.220428 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6319 10:57:53.224011 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6320 10:57:53.230618 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6321 10:57:53.230689 ==
6322 10:57:53.233677 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 10:57:53.237259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 10:57:53.237354 ==
6325 10:57:53.237442 DQS Delay:
6326 10:57:53.240310 DQS0 = 27, DQS1 = 43
6327 10:57:53.240401 DQM Delay:
6328 10:57:53.243735 DQM0 = 12, DQM1 = 13
6329 10:57:53.243804 DQ Delay:
6330 10:57:53.246915 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6331 10:57:53.250412 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6332 10:57:53.254210 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6333 10:57:53.256740 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6334 10:57:53.256819
6335 10:57:53.256877
6336 10:57:53.256932 ==
6337 10:57:53.260103 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 10:57:53.263308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 10:57:53.263379 ==
6340 10:57:53.263439
6341 10:57:53.266839
6342 10:57:53.266903 TX Vref Scan disable
6343 10:57:53.269970 == TX Byte 0 ==
6344 10:57:53.273603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 10:57:53.276449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 10:57:53.279922 == TX Byte 1 ==
6347 10:57:53.283239 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6348 10:57:53.286624 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6349 10:57:53.286716 ==
6350 10:57:53.289970 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 10:57:53.296506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 10:57:53.296575 ==
6353 10:57:53.296639
6354 10:57:53.296724
6355 10:57:53.296803 TX Vref Scan disable
6356 10:57:53.299759 == TX Byte 0 ==
6357 10:57:53.303262 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 10:57:53.306355 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 10:57:53.309912 == TX Byte 1 ==
6360 10:57:53.313252 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6361 10:57:53.316267 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6362 10:57:53.316360
6363 10:57:53.319375 [DATLAT]
6364 10:57:53.319476 Freq=400, CH0 RK0
6365 10:57:53.319564
6366 10:57:53.322800 DATLAT Default: 0xf
6367 10:57:53.322891 0, 0xFFFF, sum = 0
6368 10:57:53.326141 1, 0xFFFF, sum = 0
6369 10:57:53.326211 2, 0xFFFF, sum = 0
6370 10:57:53.329521 3, 0xFFFF, sum = 0
6371 10:57:53.329594 4, 0xFFFF, sum = 0
6372 10:57:53.332550 5, 0xFFFF, sum = 0
6373 10:57:53.332620 6, 0xFFFF, sum = 0
6374 10:57:53.335819 7, 0xFFFF, sum = 0
6375 10:57:53.335892 8, 0xFFFF, sum = 0
6376 10:57:53.339239 9, 0xFFFF, sum = 0
6377 10:57:53.342637 10, 0xFFFF, sum = 0
6378 10:57:53.342710 11, 0xFFFF, sum = 0
6379 10:57:53.345762 12, 0xFFFF, sum = 0
6380 10:57:53.345830 13, 0x0, sum = 1
6381 10:57:53.349490 14, 0x0, sum = 2
6382 10:57:53.349558 15, 0x0, sum = 3
6383 10:57:53.352495 16, 0x0, sum = 4
6384 10:57:53.352561 best_step = 14
6385 10:57:53.352618
6386 10:57:53.352678 ==
6387 10:57:53.355693 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 10:57:53.359183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 10:57:53.359250 ==
6390 10:57:53.362639 RX Vref Scan: 1
6391 10:57:53.362731
6392 10:57:53.365972 RX Vref 0 -> 0, step: 1
6393 10:57:53.366039
6394 10:57:53.366104 RX Delay -327 -> 252, step: 8
6395 10:57:53.366161
6396 10:57:53.369116 Set Vref, RX VrefLevel [Byte0]: 60
6397 10:57:53.372378 [Byte1]: 49
6398 10:57:53.377586
6399 10:57:53.377681 Final RX Vref Byte 0 = 60 to rank0
6400 10:57:53.381146 Final RX Vref Byte 1 = 49 to rank0
6401 10:57:53.384490 Final RX Vref Byte 0 = 60 to rank1
6402 10:57:53.387558 Final RX Vref Byte 1 = 49 to rank1==
6403 10:57:53.391072 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 10:57:53.397552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 10:57:53.397626 ==
6406 10:57:53.397690 DQS Delay:
6407 10:57:53.400713 DQS0 = 28, DQS1 = 48
6408 10:57:53.400803 DQM Delay:
6409 10:57:53.400862 DQM0 = 12, DQM1 = 15
6410 10:57:53.404197 DQ Delay:
6411 10:57:53.407423 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6412 10:57:53.410701 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6413 10:57:53.410770 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6414 10:57:53.414154 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6415 10:57:53.417412
6416 10:57:53.417493
6417 10:57:53.423685 [DQSOSCAuto] RK0, (LSB)MR18= 0xaba3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6418 10:57:53.427401 CH0 RK0: MR19=C0C, MR18=ABA3
6419 10:57:53.433855 CH0_RK0: MR19=0xC0C, MR18=0xABA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6420 10:57:53.433933 ==
6421 10:57:53.437151 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 10:57:53.440564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:57:53.440662 ==
6424 10:57:53.443896 [Gating] SW mode calibration
6425 10:57:53.450377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 10:57:53.457160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 10:57:53.460277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 10:57:53.463480 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 10:57:53.470227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 10:57:53.473654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 10:57:53.476897 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 10:57:53.483519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 10:57:53.486862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 10:57:53.490217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 10:57:53.496972 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 10:57:53.497047 Total UI for P1: 0, mck2ui 16
6437 10:57:53.503267 best dqsien dly found for B0: ( 0, 14, 24)
6438 10:57:53.503341 Total UI for P1: 0, mck2ui 16
6439 10:57:53.509844 best dqsien dly found for B1: ( 0, 14, 24)
6440 10:57:53.513110 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 10:57:53.516525 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 10:57:53.516596
6443 10:57:53.519981 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 10:57:53.523060 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 10:57:53.526484 [Gating] SW calibration Done
6446 10:57:53.526590 ==
6447 10:57:53.529625 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 10:57:53.533092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 10:57:53.533168 ==
6450 10:57:53.536138 RX Vref Scan: 0
6451 10:57:53.536232
6452 10:57:53.536329 RX Vref 0 -> 0, step: 1
6453 10:57:53.539456
6454 10:57:53.539554 RX Delay -410 -> 252, step: 16
6455 10:57:53.546178 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6456 10:57:53.549697 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6457 10:57:53.553012 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6458 10:57:53.556212 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6459 10:57:53.562744 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6460 10:57:53.565966 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6461 10:57:53.569672 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6462 10:57:53.572606 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6463 10:57:53.579435 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6464 10:57:53.582576 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6465 10:57:53.585620 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6466 10:57:53.592588 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6467 10:57:53.595430 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6468 10:57:53.598804 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6469 10:57:53.602191 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6470 10:57:53.609103 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6471 10:57:53.609205 ==
6472 10:57:53.612058 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 10:57:53.615417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 10:57:53.615514 ==
6475 10:57:53.615603 DQS Delay:
6476 10:57:53.618905 DQS0 = 27, DQS1 = 43
6477 10:57:53.619002 DQM Delay:
6478 10:57:53.621948 DQM0 = 9, DQM1 = 14
6479 10:57:53.622046 DQ Delay:
6480 10:57:53.625541 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6481 10:57:53.628716 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6482 10:57:53.632147 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6483 10:57:53.635704 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6484 10:57:53.635801
6485 10:57:53.635869
6486 10:57:53.635930 ==
6487 10:57:53.638776 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 10:57:53.642055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 10:57:53.642143 ==
6490 10:57:53.642206
6491 10:57:53.642292
6492 10:57:53.645432 TX Vref Scan disable
6493 10:57:53.645505 == TX Byte 0 ==
6494 10:57:53.651728 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6495 10:57:53.655152 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6496 10:57:53.655225 == TX Byte 1 ==
6497 10:57:53.661925 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6498 10:57:53.665324 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6499 10:57:53.665398 ==
6500 10:57:53.668729 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 10:57:53.671887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 10:57:53.671958 ==
6503 10:57:53.672018
6504 10:57:53.672075
6505 10:57:53.675352 TX Vref Scan disable
6506 10:57:53.678380 == TX Byte 0 ==
6507 10:57:53.681958 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6508 10:57:53.685156 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6509 10:57:53.685226 == TX Byte 1 ==
6510 10:57:53.691711 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6511 10:57:53.694940 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6512 10:57:53.695034
6513 10:57:53.695122 [DATLAT]
6514 10:57:53.698416 Freq=400, CH0 RK1
6515 10:57:53.698485
6516 10:57:53.698543 DATLAT Default: 0xe
6517 10:57:53.701688 0, 0xFFFF, sum = 0
6518 10:57:53.701762 1, 0xFFFF, sum = 0
6519 10:57:53.704945 2, 0xFFFF, sum = 0
6520 10:57:53.705020 3, 0xFFFF, sum = 0
6521 10:57:53.708363 4, 0xFFFF, sum = 0
6522 10:57:53.711535 5, 0xFFFF, sum = 0
6523 10:57:53.711606 6, 0xFFFF, sum = 0
6524 10:57:53.714654 7, 0xFFFF, sum = 0
6525 10:57:53.714757 8, 0xFFFF, sum = 0
6526 10:57:53.717891 9, 0xFFFF, sum = 0
6527 10:57:53.717962 10, 0xFFFF, sum = 0
6528 10:57:53.721233 11, 0xFFFF, sum = 0
6529 10:57:53.721338 12, 0xFFFF, sum = 0
6530 10:57:53.724711 13, 0x0, sum = 1
6531 10:57:53.724837 14, 0x0, sum = 2
6532 10:57:53.728012 15, 0x0, sum = 3
6533 10:57:53.728109 16, 0x0, sum = 4
6534 10:57:53.731550 best_step = 14
6535 10:57:53.731643
6536 10:57:53.731739 ==
6537 10:57:53.734914 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 10:57:53.737934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 10:57:53.738003 ==
6540 10:57:53.738075 RX Vref Scan: 0
6541 10:57:53.741409
6542 10:57:53.741503 RX Vref 0 -> 0, step: 1
6543 10:57:53.741600
6544 10:57:53.744385 RX Delay -327 -> 252, step: 8
6545 10:57:53.752035 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6546 10:57:53.754924 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6547 10:57:53.758448 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6548 10:57:53.764925 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6549 10:57:53.768466 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6550 10:57:53.771475 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6551 10:57:53.774965 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6552 10:57:53.778284 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6553 10:57:53.785078 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6554 10:57:53.788617 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6555 10:57:53.792058 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6556 10:57:53.795032 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6557 10:57:53.801716 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6558 10:57:53.804911 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6559 10:57:53.808917 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6560 10:57:53.814829 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6561 10:57:53.814910 ==
6562 10:57:53.818530 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 10:57:53.821367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 10:57:53.821449 ==
6565 10:57:53.821516 DQS Delay:
6566 10:57:53.824906 DQS0 = 28, DQS1 = 44
6567 10:57:53.824988 DQM Delay:
6568 10:57:53.828041 DQM0 = 9, DQM1 = 14
6569 10:57:53.828125 DQ Delay:
6570 10:57:53.831719 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6571 10:57:53.834685 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6572 10:57:53.837995 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6573 10:57:53.841417 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6574 10:57:53.841499
6575 10:57:53.841564
6576 10:57:53.847941 [DQSOSCAuto] RK1, (LSB)MR18= 0xb164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 387 ps
6577 10:57:53.851243 CH0 RK1: MR19=C0C, MR18=B164
6578 10:57:53.857792 CH0_RK1: MR19=0xC0C, MR18=0xB164, DQSOSC=387, MR23=63, INC=394, DEC=262
6579 10:57:53.861192 [RxdqsGatingPostProcess] freq 400
6580 10:57:53.867918 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 10:57:53.871218 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 10:57:53.871301 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 10:57:53.874121 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 10:57:53.877579 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 10:57:53.880825 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 10:57:53.884219 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 10:57:53.887353 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 10:57:53.890992 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 10:57:53.894365 Pre-setting of DQS Precalculation
6590 10:57:53.900675 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 10:57:53.900759 ==
6592 10:57:53.904077 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 10:57:53.907265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 10:57:53.907347 ==
6595 10:57:53.913769 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 10:57:53.920528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6597 10:57:53.920610 [CA 0] Center 36 (8~64) winsize 57
6598 10:57:53.923475 [CA 1] Center 36 (8~64) winsize 57
6599 10:57:53.927129 [CA 2] Center 36 (8~64) winsize 57
6600 10:57:53.930182 [CA 3] Center 36 (8~64) winsize 57
6601 10:57:53.933643 [CA 4] Center 36 (8~64) winsize 57
6602 10:57:53.937009 [CA 5] Center 36 (8~64) winsize 57
6603 10:57:53.937091
6604 10:57:53.939995 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6605 10:57:53.940090
6606 10:57:53.943625 [CATrainingPosCal] consider 1 rank data
6607 10:57:53.946829 u2DelayCellTimex100 = 270/100 ps
6608 10:57:53.950222 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 10:57:53.957053 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 10:57:53.959971 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 10:57:53.963649 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 10:57:53.966856 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 10:57:53.969947 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 10:57:53.970029
6615 10:57:53.973109 CA PerBit enable=1, Macro0, CA PI delay=36
6616 10:57:53.973192
6617 10:57:53.976359 [CBTSetCACLKResult] CA Dly = 36
6618 10:57:53.979778 CS Dly: 1 (0~32)
6619 10:57:53.979860 ==
6620 10:57:53.983381 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 10:57:53.986266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 10:57:53.986349 ==
6623 10:57:53.993167 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 10:57:53.996474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6625 10:57:53.999487 [CA 0] Center 36 (8~64) winsize 57
6626 10:57:54.002984 [CA 1] Center 36 (8~64) winsize 57
6627 10:57:54.006372 [CA 2] Center 36 (8~64) winsize 57
6628 10:57:54.009655 [CA 3] Center 36 (8~64) winsize 57
6629 10:57:54.012873 [CA 4] Center 36 (8~64) winsize 57
6630 10:57:54.016238 [CA 5] Center 36 (8~64) winsize 57
6631 10:57:54.016320
6632 10:57:54.019980 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6633 10:57:54.020062
6634 10:57:54.022724 [CATrainingPosCal] consider 2 rank data
6635 10:57:54.026127 u2DelayCellTimex100 = 270/100 ps
6636 10:57:54.029485 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:57:54.032520 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 10:57:54.036327 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 10:57:54.042818 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 10:57:54.045787 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 10:57:54.049512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 10:57:54.049594
6643 10:57:54.052460 CA PerBit enable=1, Macro0, CA PI delay=36
6644 10:57:54.052542
6645 10:57:54.056040 [CBTSetCACLKResult] CA Dly = 36
6646 10:57:54.056122 CS Dly: 1 (0~32)
6647 10:57:54.056187
6648 10:57:54.059512 ----->DramcWriteLeveling(PI) begin...
6649 10:57:54.062619 ==
6650 10:57:54.062701 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 10:57:54.069272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 10:57:54.069355 ==
6653 10:57:54.072322 Write leveling (Byte 0): 40 => 8
6654 10:57:54.075802 Write leveling (Byte 1): 32 => 0
6655 10:57:54.075885 DramcWriteLeveling(PI) end<-----
6656 10:57:54.079388
6657 10:57:54.079470 ==
6658 10:57:54.082237 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 10:57:54.085932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 10:57:54.086023 ==
6661 10:57:54.088917 [Gating] SW mode calibration
6662 10:57:54.095510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 10:57:54.098648 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 10:57:54.105463 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 10:57:54.108623 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 10:57:54.112143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 10:57:54.118841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 10:57:54.122015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 10:57:54.128508 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 10:57:54.131728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 10:57:54.135256 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 10:57:54.138303 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 10:57:54.141928 Total UI for P1: 0, mck2ui 16
6674 10:57:54.145012 best dqsien dly found for B0: ( 0, 14, 24)
6675 10:57:54.148459 Total UI for P1: 0, mck2ui 16
6676 10:57:54.151823 best dqsien dly found for B1: ( 0, 14, 24)
6677 10:57:54.158217 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 10:57:54.161135 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 10:57:54.161220
6680 10:57:54.164980 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 10:57:54.168001 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 10:57:54.171438 [Gating] SW calibration Done
6683 10:57:54.171520 ==
6684 10:57:54.174632 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 10:57:54.177848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 10:57:54.177930 ==
6687 10:57:54.181070 RX Vref Scan: 0
6688 10:57:54.181151
6689 10:57:54.181214 RX Vref 0 -> 0, step: 1
6690 10:57:54.181274
6691 10:57:54.184687 RX Delay -410 -> 252, step: 16
6692 10:57:54.190909 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6693 10:57:54.194435 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6694 10:57:54.197988 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6695 10:57:54.200888 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6696 10:57:54.207389 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6697 10:57:54.210720 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6698 10:57:54.214132 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6699 10:57:54.217201 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6700 10:57:54.223854 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6701 10:57:54.227328 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6702 10:57:54.230732 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6703 10:57:54.234327 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6704 10:57:54.240654 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6705 10:57:54.243673 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6706 10:57:54.247291 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6707 10:57:54.253797 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6708 10:57:54.253879 ==
6709 10:57:54.257114 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 10:57:54.260390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 10:57:54.260471 ==
6712 10:57:54.260536 DQS Delay:
6713 10:57:54.263472 DQS0 = 27, DQS1 = 43
6714 10:57:54.263553 DQM Delay:
6715 10:57:54.267072 DQM0 = 4, DQM1 = 14
6716 10:57:54.267153 DQ Delay:
6717 10:57:54.270824 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6718 10:57:54.273414 DQ4 =0, DQ5 =8, DQ6 =16, DQ7 =0
6719 10:57:54.276713 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6720 10:57:54.280125 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6721 10:57:54.280206
6722 10:57:54.280270
6723 10:57:54.280329 ==
6724 10:57:54.283751 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 10:57:54.286767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 10:57:54.286852 ==
6727 10:57:54.286915
6728 10:57:54.286974
6729 10:57:54.290010 TX Vref Scan disable
6730 10:57:54.290091 == TX Byte 0 ==
6731 10:57:54.296466 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 10:57:54.299962 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 10:57:54.300043 == TX Byte 1 ==
6734 10:57:54.306856 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6735 10:57:54.310088 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6736 10:57:54.310171 ==
6737 10:57:54.313123 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 10:57:54.316759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 10:57:54.316863 ==
6740 10:57:54.316928
6741 10:57:54.316989
6742 10:57:54.319710 TX Vref Scan disable
6743 10:57:54.323273 == TX Byte 0 ==
6744 10:57:54.326271 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 10:57:54.329863 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 10:57:54.333025 == TX Byte 1 ==
6747 10:57:54.336161 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6748 10:57:54.339593 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6749 10:57:54.339676
6750 10:57:54.339741 [DATLAT]
6751 10:57:54.342877 Freq=400, CH1 RK0
6752 10:57:54.342959
6753 10:57:54.346137 DATLAT Default: 0xf
6754 10:57:54.346257 0, 0xFFFF, sum = 0
6755 10:57:54.349438 1, 0xFFFF, sum = 0
6756 10:57:54.349521 2, 0xFFFF, sum = 0
6757 10:57:54.352753 3, 0xFFFF, sum = 0
6758 10:57:54.352845 4, 0xFFFF, sum = 0
6759 10:57:54.355873 5, 0xFFFF, sum = 0
6760 10:57:54.355956 6, 0xFFFF, sum = 0
6761 10:57:54.359331 7, 0xFFFF, sum = 0
6762 10:57:54.359415 8, 0xFFFF, sum = 0
6763 10:57:54.362510 9, 0xFFFF, sum = 0
6764 10:57:54.362593 10, 0xFFFF, sum = 0
6765 10:57:54.366104 11, 0xFFFF, sum = 0
6766 10:57:54.366188 12, 0xFFFF, sum = 0
6767 10:57:54.369085 13, 0x0, sum = 1
6768 10:57:54.369168 14, 0x0, sum = 2
6769 10:57:54.372629 15, 0x0, sum = 3
6770 10:57:54.372711 16, 0x0, sum = 4
6771 10:57:54.375613 best_step = 14
6772 10:57:54.375695
6773 10:57:54.375759 ==
6774 10:57:54.379424 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 10:57:54.382538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 10:57:54.382620 ==
6777 10:57:54.385762 RX Vref Scan: 1
6778 10:57:54.385843
6779 10:57:54.385908 RX Vref 0 -> 0, step: 1
6780 10:57:54.385969
6781 10:57:54.388741 RX Delay -327 -> 252, step: 8
6782 10:57:54.388831
6783 10:57:54.392333 Set Vref, RX VrefLevel [Byte0]: 54
6784 10:57:54.395822 [Byte1]: 53
6785 10:57:54.400123
6786 10:57:54.400205 Final RX Vref Byte 0 = 54 to rank0
6787 10:57:54.403497 Final RX Vref Byte 1 = 53 to rank0
6788 10:57:54.406927 Final RX Vref Byte 0 = 54 to rank1
6789 10:57:54.410245 Final RX Vref Byte 1 = 53 to rank1==
6790 10:57:54.413539 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 10:57:54.419826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 10:57:54.419908 ==
6793 10:57:54.419973 DQS Delay:
6794 10:57:54.423176 DQS0 = 28, DQS1 = 40
6795 10:57:54.423257 DQM Delay:
6796 10:57:54.423322 DQM0 = 8, DQM1 = 12
6797 10:57:54.426756 DQ Delay:
6798 10:57:54.429888 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6799 10:57:54.429970 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6800 10:57:54.433350 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6801 10:57:54.436741 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6802 10:57:54.436859
6803 10:57:54.436924
6804 10:57:54.446438 [DQSOSCAuto] RK0, (LSB)MR18= 0x93ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6805 10:57:54.449869 CH1 RK0: MR19=C0C, MR18=93CE
6806 10:57:54.456693 CH1_RK0: MR19=0xC0C, MR18=0x93CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6807 10:57:54.456797 ==
6808 10:57:54.459739 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 10:57:54.462923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:57:54.463005 ==
6811 10:57:54.466055 [Gating] SW mode calibration
6812 10:57:54.472925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 10:57:54.479215 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 10:57:54.482529 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 10:57:54.486254 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 10:57:54.492557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 10:57:54.495696 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 10:57:54.499422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 10:57:54.505748 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 10:57:54.509333 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 10:57:54.512383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 10:57:54.518994 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 10:57:54.519105 Total UI for P1: 0, mck2ui 16
6824 10:57:54.525821 best dqsien dly found for B0: ( 0, 14, 24)
6825 10:57:54.525905 Total UI for P1: 0, mck2ui 16
6826 10:57:54.532169 best dqsien dly found for B1: ( 0, 14, 24)
6827 10:57:54.535461 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 10:57:54.539019 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 10:57:54.539105
6830 10:57:54.542207 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 10:57:54.545484 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 10:57:54.549280 [Gating] SW calibration Done
6833 10:57:54.549363 ==
6834 10:57:54.551928 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 10:57:54.555161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 10:57:54.555245 ==
6837 10:57:54.558456 RX Vref Scan: 0
6838 10:57:54.558539
6839 10:57:54.558605 RX Vref 0 -> 0, step: 1
6840 10:57:54.558666
6841 10:57:54.561845 RX Delay -410 -> 252, step: 16
6842 10:57:54.568577 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6843 10:57:54.571791 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6844 10:57:54.575034 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6845 10:57:54.578654 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6846 10:57:54.585146 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6847 10:57:54.588376 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6848 10:57:54.591568 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6849 10:57:54.595053 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6850 10:57:54.601650 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6851 10:57:54.604820 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6852 10:57:54.608067 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6853 10:57:54.611462 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6854 10:57:54.618112 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6855 10:57:54.621688 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6856 10:57:54.624738 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6857 10:57:54.631252 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6858 10:57:54.631336 ==
6859 10:57:54.634596 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 10:57:54.638326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 10:57:54.638409 ==
6862 10:57:54.638474 DQS Delay:
6863 10:57:54.641670 DQS0 = 35, DQS1 = 43
6864 10:57:54.641753 DQM Delay:
6865 10:57:54.644519 DQM0 = 16, DQM1 = 19
6866 10:57:54.644601 DQ Delay:
6867 10:57:54.647827 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6868 10:57:54.651567 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6869 10:57:54.654558 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6870 10:57:54.657729 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6871 10:57:54.657812
6872 10:57:54.657879
6873 10:57:54.657940 ==
6874 10:57:54.661328 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 10:57:54.664594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 10:57:54.664703 ==
6877 10:57:54.664839
6878 10:57:54.664929
6879 10:57:54.667642 TX Vref Scan disable
6880 10:57:54.671015 == TX Byte 0 ==
6881 10:57:54.674705 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6882 10:57:54.677972 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6883 10:57:54.681013 == TX Byte 1 ==
6884 10:57:54.684428 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6885 10:57:54.687488 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6886 10:57:54.687572 ==
6887 10:57:54.690968 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 10:57:54.694401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 10:57:54.694484 ==
6890 10:57:54.697664
6891 10:57:54.697747
6892 10:57:54.697812 TX Vref Scan disable
6893 10:57:54.701000 == TX Byte 0 ==
6894 10:57:54.704200 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6895 10:57:54.707262 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6896 10:57:54.710638 == TX Byte 1 ==
6897 10:57:54.714178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6898 10:57:54.717178 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6899 10:57:54.717261
6900 10:57:54.717331 [DATLAT]
6901 10:57:54.720546 Freq=400, CH1 RK1
6902 10:57:54.720630
6903 10:57:54.724006 DATLAT Default: 0xe
6904 10:57:54.724090 0, 0xFFFF, sum = 0
6905 10:57:54.727080 1, 0xFFFF, sum = 0
6906 10:57:54.727198 2, 0xFFFF, sum = 0
6907 10:57:54.730824 3, 0xFFFF, sum = 0
6908 10:57:54.730930 4, 0xFFFF, sum = 0
6909 10:57:54.733809 5, 0xFFFF, sum = 0
6910 10:57:54.733906 6, 0xFFFF, sum = 0
6911 10:57:54.737204 7, 0xFFFF, sum = 0
6912 10:57:54.737280 8, 0xFFFF, sum = 0
6913 10:57:54.740483 9, 0xFFFF, sum = 0
6914 10:57:54.740579 10, 0xFFFF, sum = 0
6915 10:57:54.743792 11, 0xFFFF, sum = 0
6916 10:57:54.743898 12, 0xFFFF, sum = 0
6917 10:57:54.747105 13, 0x0, sum = 1
6918 10:57:54.747202 14, 0x0, sum = 2
6919 10:57:54.750038 15, 0x0, sum = 3
6920 10:57:54.750107 16, 0x0, sum = 4
6921 10:57:54.753520 best_step = 14
6922 10:57:54.753588
6923 10:57:54.753655 ==
6924 10:57:54.756933 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 10:57:54.759972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 10:57:54.760074 ==
6927 10:57:54.763426 RX Vref Scan: 0
6928 10:57:54.763528
6929 10:57:54.763617 RX Vref 0 -> 0, step: 1
6930 10:57:54.763706
6931 10:57:54.766811 RX Delay -327 -> 252, step: 8
6932 10:57:54.774698 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6933 10:57:54.778140 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6934 10:57:54.781072 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6935 10:57:54.787713 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6936 10:57:54.790773 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6937 10:57:54.794273 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6938 10:57:54.797732 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6939 10:57:54.804229 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6940 10:57:54.807743 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6941 10:57:54.810862 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6942 10:57:54.814431 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6943 10:57:54.820850 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6944 10:57:54.824416 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6945 10:57:54.827672 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6946 10:57:54.831230 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6947 10:57:54.837286 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6948 10:57:54.837358 ==
6949 10:57:54.840747 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 10:57:54.843981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 10:57:54.844078 ==
6952 10:57:54.844170 DQS Delay:
6953 10:57:54.847110 DQS0 = 32, DQS1 = 36
6954 10:57:54.847211 DQM Delay:
6955 10:57:54.850658 DQM0 = 12, DQM1 = 10
6956 10:57:54.850750 DQ Delay:
6957 10:57:54.853906 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6958 10:57:54.857133 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6959 10:57:54.860318 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6960 10:57:54.863736 DQ12 =16, DQ13 =16, DQ14 =12, DQ15 =20
6961 10:57:54.863805
6962 10:57:54.863864
6963 10:57:54.870273 [DQSOSCAuto] RK1, (LSB)MR18= 0xa951, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6964 10:57:54.874074 CH1 RK1: MR19=C0C, MR18=A951
6965 10:57:54.880152 CH1_RK1: MR19=0xC0C, MR18=0xA951, DQSOSC=388, MR23=63, INC=392, DEC=261
6966 10:57:54.883761 [RxdqsGatingPostProcess] freq 400
6967 10:57:54.890242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 10:57:54.893610 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 10:57:54.896706 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 10:57:54.900065 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 10:57:54.903284 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 10:57:54.906713 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 10:57:54.906795 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 10:57:54.910043 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 10:57:54.913452 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 10:57:54.916686 Pre-setting of DQS Precalculation
6977 10:57:54.923225 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 10:57:54.929792 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 10:57:54.936588 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 10:57:54.936696
6981 10:57:54.936823
6982 10:57:54.939911 [Calibration Summary] 800 Mbps
6983 10:57:54.939993 CH 0, Rank 0
6984 10:57:54.942908 SW Impedance : PASS
6985 10:57:54.946343 DUTY Scan : NO K
6986 10:57:54.946425 ZQ Calibration : PASS
6987 10:57:54.949668 Jitter Meter : NO K
6988 10:57:54.953184 CBT Training : PASS
6989 10:57:54.953266 Write leveling : PASS
6990 10:57:54.956245 RX DQS gating : PASS
6991 10:57:54.959394 RX DQ/DQS(RDDQC) : PASS
6992 10:57:54.959476 TX DQ/DQS : PASS
6993 10:57:54.962556 RX DATLAT : PASS
6994 10:57:54.966075 RX DQ/DQS(Engine): PASS
6995 10:57:54.966157 TX OE : NO K
6996 10:57:54.969257 All Pass.
6997 10:57:54.969339
6998 10:57:54.969404 CH 0, Rank 1
6999 10:57:54.972575 SW Impedance : PASS
7000 10:57:54.972658 DUTY Scan : NO K
7001 10:57:54.976156 ZQ Calibration : PASS
7002 10:57:54.979793 Jitter Meter : NO K
7003 10:57:54.979875 CBT Training : PASS
7004 10:57:54.982480 Write leveling : NO K
7005 10:57:54.986040 RX DQS gating : PASS
7006 10:57:54.986122 RX DQ/DQS(RDDQC) : PASS
7007 10:57:54.989130 TX DQ/DQS : PASS
7008 10:57:54.992357 RX DATLAT : PASS
7009 10:57:54.992438 RX DQ/DQS(Engine): PASS
7010 10:57:54.995858 TX OE : NO K
7011 10:57:54.995940 All Pass.
7012 10:57:54.996006
7013 10:57:54.999090 CH 1, Rank 0
7014 10:57:54.999172 SW Impedance : PASS
7015 10:57:55.002370 DUTY Scan : NO K
7016 10:57:55.005734 ZQ Calibration : PASS
7017 10:57:55.005816 Jitter Meter : NO K
7018 10:57:55.009262 CBT Training : PASS
7019 10:57:55.009345 Write leveling : PASS
7020 10:57:55.012332 RX DQS gating : PASS
7021 10:57:55.015772 RX DQ/DQS(RDDQC) : PASS
7022 10:57:55.015854 TX DQ/DQS : PASS
7023 10:57:55.019318 RX DATLAT : PASS
7024 10:57:55.022426 RX DQ/DQS(Engine): PASS
7025 10:57:55.022508 TX OE : NO K
7026 10:57:55.025733 All Pass.
7027 10:57:55.025815
7028 10:57:55.025880 CH 1, Rank 1
7029 10:57:55.028954 SW Impedance : PASS
7030 10:57:55.029036 DUTY Scan : NO K
7031 10:57:55.032500 ZQ Calibration : PASS
7032 10:57:55.035814 Jitter Meter : NO K
7033 10:57:55.035896 CBT Training : PASS
7034 10:57:55.038972 Write leveling : NO K
7035 10:57:55.042514 RX DQS gating : PASS
7036 10:57:55.042596 RX DQ/DQS(RDDQC) : PASS
7037 10:57:55.045546 TX DQ/DQS : PASS
7038 10:57:55.048889 RX DATLAT : PASS
7039 10:57:55.048996 RX DQ/DQS(Engine): PASS
7040 10:57:55.052336 TX OE : NO K
7041 10:57:55.052419 All Pass.
7042 10:57:55.052483
7043 10:57:55.055283 DramC Write-DBI off
7044 10:57:55.058695 PER_BANK_REFRESH: Hybrid Mode
7045 10:57:55.058777 TX_TRACKING: ON
7046 10:57:55.068512 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 10:57:55.071910 [FAST_K] Save calibration result to emmc
7048 10:57:55.075130 dramc_set_vcore_voltage set vcore to 725000
7049 10:57:55.078327 Read voltage for 1600, 0
7050 10:57:55.078410 Vio18 = 0
7051 10:57:55.078475 Vcore = 725000
7052 10:57:55.081793 Vdram = 0
7053 10:57:55.081875 Vddq = 0
7054 10:57:55.081940 Vmddr = 0
7055 10:57:55.088710 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 10:57:55.091824 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 10:57:55.095208 MEM_TYPE=3, freq_sel=13
7058 10:57:55.098167 sv_algorithm_assistance_LP4_3733
7059 10:57:55.101761 ============ PULL DRAM RESETB DOWN ============
7060 10:57:55.104731 ========== PULL DRAM RESETB DOWN end =========
7061 10:57:55.111557 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 10:57:55.115145 ===================================
7063 10:57:55.117972 LPDDR4 DRAM CONFIGURATION
7064 10:57:55.121398 ===================================
7065 10:57:55.121481 EX_ROW_EN[0] = 0x0
7066 10:57:55.124735 EX_ROW_EN[1] = 0x0
7067 10:57:55.124846 LP4Y_EN = 0x0
7068 10:57:55.127916 WORK_FSP = 0x1
7069 10:57:55.127995 WL = 0x5
7070 10:57:55.131214 RL = 0x5
7071 10:57:55.131292 BL = 0x2
7072 10:57:55.134761 RPST = 0x0
7073 10:57:55.134835 RD_PRE = 0x0
7074 10:57:55.138232 WR_PRE = 0x1
7075 10:57:55.138308 WR_PST = 0x1
7076 10:57:55.141133 DBI_WR = 0x0
7077 10:57:55.144585 DBI_RD = 0x0
7078 10:57:55.144658 OTF = 0x1
7079 10:57:55.147763 ===================================
7080 10:57:55.151307 ===================================
7081 10:57:55.151380 ANA top config
7082 10:57:55.154768 ===================================
7083 10:57:55.157676 DLL_ASYNC_EN = 0
7084 10:57:55.161188 ALL_SLAVE_EN = 0
7085 10:57:55.164216 NEW_RANK_MODE = 1
7086 10:57:55.167415 DLL_IDLE_MODE = 1
7087 10:57:55.167494 LP45_APHY_COMB_EN = 1
7088 10:57:55.171047 TX_ODT_DIS = 0
7089 10:57:55.174076 NEW_8X_MODE = 1
7090 10:57:55.177546 ===================================
7091 10:57:55.180631 ===================================
7092 10:57:55.184095 data_rate = 3200
7093 10:57:55.187337 CKR = 1
7094 10:57:55.187413 DQ_P2S_RATIO = 8
7095 10:57:55.190758 ===================================
7096 10:57:55.193872 CA_P2S_RATIO = 8
7097 10:57:55.197664 DQ_CA_OPEN = 0
7098 10:57:55.200523 DQ_SEMI_OPEN = 0
7099 10:57:55.204421 CA_SEMI_OPEN = 0
7100 10:57:55.206986 CA_FULL_RATE = 0
7101 10:57:55.207062 DQ_CKDIV4_EN = 0
7102 10:57:55.210425 CA_CKDIV4_EN = 0
7103 10:57:55.213682 CA_PREDIV_EN = 0
7104 10:57:55.216845 PH8_DLY = 12
7105 10:57:55.220634 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 10:57:55.223471 DQ_AAMCK_DIV = 4
7107 10:57:55.227163 CA_AAMCK_DIV = 4
7108 10:57:55.227241 CA_ADMCK_DIV = 4
7109 10:57:55.230264 DQ_TRACK_CA_EN = 0
7110 10:57:55.233313 CA_PICK = 1600
7111 10:57:55.236844 CA_MCKIO = 1600
7112 10:57:55.240141 MCKIO_SEMI = 0
7113 10:57:55.243317 PLL_FREQ = 3068
7114 10:57:55.246816 DQ_UI_PI_RATIO = 32
7115 10:57:55.249789 CA_UI_PI_RATIO = 0
7116 10:57:55.253535 ===================================
7117 10:57:55.256665 ===================================
7118 10:57:55.256735 memory_type:LPDDR4
7119 10:57:55.259780 GP_NUM : 10
7120 10:57:55.259849 SRAM_EN : 1
7121 10:57:55.263122 MD32_EN : 0
7122 10:57:55.266499 ===================================
7123 10:57:55.269756 [ANA_INIT] >>>>>>>>>>>>>>
7124 10:57:55.273153 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 10:57:55.276469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 10:57:55.279891 ===================================
7127 10:57:55.282872 data_rate = 3200,PCW = 0X7600
7128 10:57:55.286429 ===================================
7129 10:57:55.289749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 10:57:55.292725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 10:57:55.299648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 10:57:55.303009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 10:57:55.306189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 10:57:55.309666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 10:57:55.312606 [ANA_INIT] flow start
7136 10:57:55.315807 [ANA_INIT] PLL >>>>>>>>
7137 10:57:55.315882 [ANA_INIT] PLL <<<<<<<<
7138 10:57:55.319371 [ANA_INIT] MIDPI >>>>>>>>
7139 10:57:55.322457 [ANA_INIT] MIDPI <<<<<<<<
7140 10:57:55.322529 [ANA_INIT] DLL >>>>>>>>
7141 10:57:55.325769 [ANA_INIT] DLL <<<<<<<<
7142 10:57:55.329312 [ANA_INIT] flow end
7143 10:57:55.332546 ============ LP4 DIFF to SE enter ============
7144 10:57:55.335789 ============ LP4 DIFF to SE exit ============
7145 10:57:55.339062 [ANA_INIT] <<<<<<<<<<<<<
7146 10:57:55.342183 [Flow] Enable top DCM control >>>>>
7147 10:57:55.345546 [Flow] Enable top DCM control <<<<<
7148 10:57:55.348954 Enable DLL master slave shuffle
7149 10:57:55.355778 ==============================================================
7150 10:57:55.355856 Gating Mode config
7151 10:57:55.362099 ==============================================================
7152 10:57:55.362177 Config description:
7153 10:57:55.372319 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 10:57:55.378703 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 10:57:55.385477 SELPH_MODE 0: By rank 1: By Phase
7156 10:57:55.388642 ==============================================================
7157 10:57:55.391836 GAT_TRACK_EN = 1
7158 10:57:55.395318 RX_GATING_MODE = 2
7159 10:57:55.398434 RX_GATING_TRACK_MODE = 2
7160 10:57:55.402023 SELPH_MODE = 1
7161 10:57:55.405372 PICG_EARLY_EN = 1
7162 10:57:55.408666 VALID_LAT_VALUE = 1
7163 10:57:55.411890 ==============================================================
7164 10:57:55.415352 Enter into Gating configuration >>>>
7165 10:57:55.418462 Exit from Gating configuration <<<<
7166 10:57:55.422082 Enter into DVFS_PRE_config >>>>>
7167 10:57:55.435190 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 10:57:55.438444 Exit from DVFS_PRE_config <<<<<
7169 10:57:55.441571 Enter into PICG configuration >>>>
7170 10:57:55.444891 Exit from PICG configuration <<<<
7171 10:57:55.444973 [RX_INPUT] configuration >>>>>
7172 10:57:55.448278 [RX_INPUT] configuration <<<<<
7173 10:57:55.454692 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 10:57:55.461481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 10:57:55.464725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 10:57:55.471144 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 10:57:55.477910 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 10:57:55.484300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 10:57:55.487532 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 10:57:55.491345 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 10:57:55.497810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 10:57:55.501086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 10:57:55.504128 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 10:57:55.510802 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 10:57:55.514284 ===================================
7186 10:57:55.514366 LPDDR4 DRAM CONFIGURATION
7187 10:57:55.517289 ===================================
7188 10:57:55.520733 EX_ROW_EN[0] = 0x0
7189 10:57:55.520838 EX_ROW_EN[1] = 0x0
7190 10:57:55.524269 LP4Y_EN = 0x0
7191 10:57:55.527441 WORK_FSP = 0x1
7192 10:57:55.527523 WL = 0x5
7193 10:57:55.530636 RL = 0x5
7194 10:57:55.530719 BL = 0x2
7195 10:57:55.534018 RPST = 0x0
7196 10:57:55.534100 RD_PRE = 0x0
7197 10:57:55.537685 WR_PRE = 0x1
7198 10:57:55.537767 WR_PST = 0x1
7199 10:57:55.540341 DBI_WR = 0x0
7200 10:57:55.540423 DBI_RD = 0x0
7201 10:57:55.544030 OTF = 0x1
7202 10:57:55.547233 ===================================
7203 10:57:55.550684 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 10:57:55.553991 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 10:57:55.560407 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 10:57:55.563828 ===================================
7207 10:57:55.563910 LPDDR4 DRAM CONFIGURATION
7208 10:57:55.567115 ===================================
7209 10:57:55.570228 EX_ROW_EN[0] = 0x10
7210 10:57:55.573743 EX_ROW_EN[1] = 0x0
7211 10:57:55.573825 LP4Y_EN = 0x0
7212 10:57:55.577119 WORK_FSP = 0x1
7213 10:57:55.577204 WL = 0x5
7214 10:57:55.580135 RL = 0x5
7215 10:57:55.580218 BL = 0x2
7216 10:57:55.583594 RPST = 0x0
7217 10:57:55.583677 RD_PRE = 0x0
7218 10:57:55.586733 WR_PRE = 0x1
7219 10:57:55.586816 WR_PST = 0x1
7220 10:57:55.590125 DBI_WR = 0x0
7221 10:57:55.590208 DBI_RD = 0x0
7222 10:57:55.593159 OTF = 0x1
7223 10:57:55.596444 ===================================
7224 10:57:55.603382 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 10:57:55.603464 ==
7226 10:57:55.606657 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 10:57:55.609682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 10:57:55.609784 ==
7229 10:57:55.613449 [Duty_Offset_Calibration]
7230 10:57:55.613531 B0:2 B1:0 CA:1
7231 10:57:55.613597
7232 10:57:55.616450 [DutyScan_Calibration_Flow] k_type=0
7233 10:57:55.625944
7234 10:57:55.626025 ==CLK 0==
7235 10:57:55.629383 Final CLK duty delay cell = -4
7236 10:57:55.632834 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7237 10:57:55.636201 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7238 10:57:55.639447 [-4] AVG Duty = 4922%(X100)
7239 10:57:55.639530
7240 10:57:55.642705 CH0 CLK Duty spec in!! Max-Min= 218%
7241 10:57:55.646014 [DutyScan_Calibration_Flow] ====Done====
7242 10:57:55.646097
7243 10:57:55.649167 [DutyScan_Calibration_Flow] k_type=1
7244 10:57:55.665632
7245 10:57:55.665716 ==DQS 0 ==
7246 10:57:55.669015 Final DQS duty delay cell = 0
7247 10:57:55.672355 [0] MAX Duty = 5249%(X100), DQS PI = 32
7248 10:57:55.675602 [0] MIN Duty = 4969%(X100), DQS PI = 0
7249 10:57:55.678748 [0] AVG Duty = 5109%(X100)
7250 10:57:55.678831
7251 10:57:55.678898 ==DQS 1 ==
7252 10:57:55.682031 Final DQS duty delay cell = -4
7253 10:57:55.685142 [-4] MAX Duty = 5156%(X100), DQS PI = 46
7254 10:57:55.688819 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7255 10:57:55.691820 [-4] AVG Duty = 5015%(X100)
7256 10:57:55.691903
7257 10:57:55.695095 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7258 10:57:55.695208
7259 10:57:55.698520 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7260 10:57:55.701974 [DutyScan_Calibration_Flow] ====Done====
7261 10:57:55.702057
7262 10:57:55.704991 [DutyScan_Calibration_Flow] k_type=3
7263 10:57:55.722036
7264 10:57:55.722119 ==DQM 0 ==
7265 10:57:55.725724 Final DQM duty delay cell = 0
7266 10:57:55.728675 [0] MAX Duty = 5093%(X100), DQS PI = 26
7267 10:57:55.732195 [0] MIN Duty = 4844%(X100), DQS PI = 2
7268 10:57:55.735460 [0] AVG Duty = 4968%(X100)
7269 10:57:55.735544
7270 10:57:55.735608 ==DQM 1 ==
7271 10:57:55.738443 Final DQM duty delay cell = -4
7272 10:57:55.741728 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7273 10:57:55.744883 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7274 10:57:55.748489 [-4] AVG Duty = 4875%(X100)
7275 10:57:55.748571
7276 10:57:55.751758 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7277 10:57:55.751841
7278 10:57:55.755421 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7279 10:57:55.758182 [DutyScan_Calibration_Flow] ====Done====
7280 10:57:55.758264
7281 10:57:55.761453 [DutyScan_Calibration_Flow] k_type=2
7282 10:57:55.779841
7283 10:57:55.779950 ==DQ 0 ==
7284 10:57:55.782916 Final DQ duty delay cell = 0
7285 10:57:55.786068 [0] MAX Duty = 5124%(X100), DQS PI = 32
7286 10:57:55.789516 [0] MIN Duty = 5000%(X100), DQS PI = 16
7287 10:57:55.789600 [0] AVG Duty = 5062%(X100)
7288 10:57:55.792641
7289 10:57:55.792723 ==DQ 1 ==
7290 10:57:55.796477 Final DQ duty delay cell = 0
7291 10:57:55.799498 [0] MAX Duty = 4969%(X100), DQS PI = 42
7292 10:57:55.802987 [0] MIN Duty = 4875%(X100), DQS PI = 10
7293 10:57:55.803070 [0] AVG Duty = 4922%(X100)
7294 10:57:55.806203
7295 10:57:55.809626 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7296 10:57:55.809709
7297 10:57:55.812651 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7298 10:57:55.816106 [DutyScan_Calibration_Flow] ====Done====
7299 10:57:55.816187 ==
7300 10:57:55.819252 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 10:57:55.822925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 10:57:55.823007 ==
7303 10:57:55.826080 [Duty_Offset_Calibration]
7304 10:57:55.826160 B0:0 B1:-1 CA:2
7305 10:57:55.826223
7306 10:57:55.828990 [DutyScan_Calibration_Flow] k_type=0
7307 10:57:55.839828
7308 10:57:55.839908 ==CLK 0==
7309 10:57:55.843481 Final CLK duty delay cell = 0
7310 10:57:55.846925 [0] MAX Duty = 5187%(X100), DQS PI = 14
7311 10:57:55.849900 [0] MIN Duty = 4938%(X100), DQS PI = 44
7312 10:57:55.853021 [0] AVG Duty = 5062%(X100)
7313 10:57:55.853101
7314 10:57:55.856370 CH1 CLK Duty spec in!! Max-Min= 249%
7315 10:57:55.859694 [DutyScan_Calibration_Flow] ====Done====
7316 10:57:55.859774
7317 10:57:55.862735 [DutyScan_Calibration_Flow] k_type=1
7318 10:57:55.879493
7319 10:57:55.879574 ==DQS 0 ==
7320 10:57:55.883315 Final DQS duty delay cell = 0
7321 10:57:55.886044 [0] MAX Duty = 5093%(X100), DQS PI = 24
7322 10:57:55.889707 [0] MIN Duty = 4969%(X100), DQS PI = 2
7323 10:57:55.892694 [0] AVG Duty = 5031%(X100)
7324 10:57:55.892839
7325 10:57:55.892929 ==DQS 1 ==
7326 10:57:55.896247 Final DQS duty delay cell = 0
7327 10:57:55.899276 [0] MAX Duty = 5187%(X100), DQS PI = 0
7328 10:57:55.902880 [0] MIN Duty = 4844%(X100), DQS PI = 32
7329 10:57:55.905921 [0] AVG Duty = 5015%(X100)
7330 10:57:55.906007
7331 10:57:55.909294 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7332 10:57:55.909374
7333 10:57:55.912358 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7334 10:57:55.915695 [DutyScan_Calibration_Flow] ====Done====
7335 10:57:55.915775
7336 10:57:55.918867 [DutyScan_Calibration_Flow] k_type=3
7337 10:57:55.937018
7338 10:57:55.937098 ==DQM 0 ==
7339 10:57:55.940693 Final DQM duty delay cell = 4
7340 10:57:55.943908 [4] MAX Duty = 5125%(X100), DQS PI = 22
7341 10:57:55.947131 [4] MIN Duty = 4938%(X100), DQS PI = 48
7342 10:57:55.950254 [4] AVG Duty = 5031%(X100)
7343 10:57:55.950360
7344 10:57:55.950439 ==DQM 1 ==
7345 10:57:55.953739 Final DQM duty delay cell = 0
7346 10:57:55.956731 [0] MAX Duty = 5281%(X100), DQS PI = 58
7347 10:57:55.960273 [0] MIN Duty = 4844%(X100), DQS PI = 34
7348 10:57:55.963677 [0] AVG Duty = 5062%(X100)
7349 10:57:55.963759
7350 10:57:55.966894 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7351 10:57:55.966978
7352 10:57:55.970097 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7353 10:57:55.973316 [DutyScan_Calibration_Flow] ====Done====
7354 10:57:55.973398
7355 10:57:55.976742 [DutyScan_Calibration_Flow] k_type=2
7356 10:57:55.994214
7357 10:57:55.994297 ==DQ 0 ==
7358 10:57:55.997477 Final DQ duty delay cell = 0
7359 10:57:56.000877 [0] MAX Duty = 5093%(X100), DQS PI = 22
7360 10:57:56.004084 [0] MIN Duty = 4969%(X100), DQS PI = 46
7361 10:57:56.004166 [0] AVG Duty = 5031%(X100)
7362 10:57:56.007376
7363 10:57:56.007458 ==DQ 1 ==
7364 10:57:56.010662 Final DQ duty delay cell = 0
7365 10:57:56.013937 [0] MAX Duty = 5062%(X100), DQS PI = 2
7366 10:57:56.017339 [0] MIN Duty = 4813%(X100), DQS PI = 34
7367 10:57:56.017423 [0] AVG Duty = 4937%(X100)
7368 10:57:56.017489
7369 10:57:56.023849 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7370 10:57:56.023932
7371 10:57:56.027187 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7372 10:57:56.030467 [DutyScan_Calibration_Flow] ====Done====
7373 10:57:56.033948 nWR fixed to 30
7374 10:57:56.034032 [ModeRegInit_LP4] CH0 RK0
7375 10:57:56.037116 [ModeRegInit_LP4] CH0 RK1
7376 10:57:56.040358 [ModeRegInit_LP4] CH1 RK0
7377 10:57:56.043511 [ModeRegInit_LP4] CH1 RK1
7378 10:57:56.043594 match AC timing 5
7379 10:57:56.050206 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 10:57:56.053885 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 10:57:56.056776 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 10:57:56.063567 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 10:57:56.067222 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 10:57:56.067332 [MiockJmeterHQA]
7385 10:57:56.067431
7386 10:57:56.070040 [DramcMiockJmeter] u1RxGatingPI = 0
7387 10:57:56.073701 0 : 4252, 4027
7388 10:57:56.073786 4 : 4255, 4027
7389 10:57:56.076890 8 : 4363, 4137
7390 10:57:56.076996 12 : 4363, 4137
7391 10:57:56.077065 16 : 4363, 4138
7392 10:57:56.079861 20 : 4252, 4027
7393 10:57:56.079945 24 : 4252, 4027
7394 10:57:56.083760 28 : 4253, 4027
7395 10:57:56.083843 32 : 4253, 4026
7396 10:57:56.086701 36 : 4255, 4029
7397 10:57:56.086785 40 : 4363, 4137
7398 10:57:56.089992 44 : 4252, 4027
7399 10:57:56.090076 48 : 4252, 4027
7400 10:57:56.090143 52 : 4252, 4027
7401 10:57:56.093316 56 : 4255, 4029
7402 10:57:56.093400 60 : 4250, 4026
7403 10:57:56.096519 64 : 4363, 4137
7404 10:57:56.096603 68 : 4361, 4138
7405 10:57:56.099905 72 : 4250, 4026
7406 10:57:56.099988 76 : 4250, 4027
7407 10:57:56.103006 80 : 4249, 4027
7408 10:57:56.103090 84 : 4250, 4026
7409 10:57:56.103157 88 : 4252, 3485
7410 10:57:56.106585 92 : 4361, 0
7411 10:57:56.106670 96 : 4250, 0
7412 10:57:56.109729 100 : 4252, 0
7413 10:57:56.109813 104 : 4250, 0
7414 10:57:56.109881 108 : 4361, 0
7415 10:57:56.113379 112 : 4361, 0
7416 10:57:56.113463 116 : 4250, 0
7417 10:57:56.113548 120 : 4250, 0
7418 10:57:56.116375 124 : 4250, 0
7419 10:57:56.116459 128 : 4252, 0
7420 10:57:56.119716 132 : 4250, 0
7421 10:57:56.119800 136 : 4250, 0
7422 10:57:56.119867 140 : 4253, 0
7423 10:57:56.123252 144 : 4252, 0
7424 10:57:56.123336 148 : 4250, 0
7425 10:57:56.126211 152 : 4363, 0
7426 10:57:56.126295 156 : 4363, 0
7427 10:57:56.126363 160 : 4252, 0
7428 10:57:56.129923 164 : 4361, 0
7429 10:57:56.130007 168 : 4250, 0
7430 10:57:56.132937 172 : 4253, 0
7431 10:57:56.133021 176 : 4249, 0
7432 10:57:56.133087 180 : 4252, 0
7433 10:57:56.136271 184 : 4252, 0
7434 10:57:56.136355 188 : 4250, 0
7435 10:57:56.139254 192 : 4252, 0
7436 10:57:56.139338 196 : 4252, 0
7437 10:57:56.139405 200 : 4250, 12
7438 10:57:56.142753 204 : 4252, 2689
7439 10:57:56.142837 208 : 4360, 4138
7440 10:57:56.145927 212 : 4363, 4140
7441 10:57:56.146010 216 : 4250, 4027
7442 10:57:56.149458 220 : 4250, 4027
7443 10:57:56.149542 224 : 4363, 4140
7444 10:57:56.152542 228 : 4250, 4027
7445 10:57:56.152625 232 : 4250, 4026
7446 10:57:56.155938 236 : 4250, 4027
7447 10:57:56.156022 240 : 4252, 4030
7448 10:57:56.159232 244 : 4250, 4026
7449 10:57:56.159316 248 : 4250, 4026
7450 10:57:56.159383 252 : 4361, 4137
7451 10:57:56.163174 256 : 4250, 4027
7452 10:57:56.163258 260 : 4249, 4027
7453 10:57:56.166303 264 : 4361, 4138
7454 10:57:56.166387 268 : 4250, 4026
7455 10:57:56.169425 272 : 4250, 4027
7456 10:57:56.169509 276 : 4363, 4140
7457 10:57:56.172947 280 : 4250, 4027
7458 10:57:56.173031 284 : 4250, 4026
7459 10:57:56.175878 288 : 4250, 4027
7460 10:57:56.175962 292 : 4252, 4030
7461 10:57:56.179281 296 : 4250, 4027
7462 10:57:56.179364 300 : 4250, 4026
7463 10:57:56.179431 304 : 4361, 4137
7464 10:57:56.182622 308 : 4250, 4027
7465 10:57:56.182707 312 : 4250, 3803
7466 10:57:56.185891 316 : 4360, 1906
7467 10:57:56.186003
7468 10:57:56.189274 MIOCK jitter meter ch=0
7469 10:57:56.189356
7470 10:57:56.189422 1T = (316-92) = 224 dly cells
7471 10:57:56.195768 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7472 10:57:56.195852 ==
7473 10:57:56.199428 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 10:57:56.202561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7475 10:57:56.205985 ==
7476 10:57:56.209017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7477 10:57:56.212623 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7478 10:57:56.219014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7479 10:57:56.225591 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7480 10:57:56.233020 [CA 0] Center 43 (13~73) winsize 61
7481 10:57:56.236211 [CA 1] Center 43 (13~73) winsize 61
7482 10:57:56.239598 [CA 2] Center 38 (8~68) winsize 61
7483 10:57:56.242777 [CA 3] Center 37 (8~67) winsize 60
7484 10:57:56.246245 [CA 4] Center 36 (6~66) winsize 61
7485 10:57:56.249601 [CA 5] Center 35 (5~65) winsize 61
7486 10:57:56.249710
7487 10:57:56.252872 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7488 10:57:56.252955
7489 10:57:56.256338 [CATrainingPosCal] consider 1 rank data
7490 10:57:56.259333 u2DelayCellTimex100 = 290/100 ps
7491 10:57:56.266163 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7492 10:57:56.269139 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7493 10:57:56.272425 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7494 10:57:56.275977 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7495 10:57:56.278958 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7496 10:57:56.282332 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7497 10:57:56.282415
7498 10:57:56.285587 CA PerBit enable=1, Macro0, CA PI delay=35
7499 10:57:56.285671
7500 10:57:56.289302 [CBTSetCACLKResult] CA Dly = 35
7501 10:57:56.292544 CS Dly: 9 (0~40)
7502 10:57:56.295506 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7503 10:57:56.298860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7504 10:57:56.298943 ==
7505 10:57:56.302111 Dram Type= 6, Freq= 0, CH_0, rank 1
7506 10:57:56.308783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 10:57:56.308866 ==
7508 10:57:56.312241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 10:57:56.318937 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 10:57:56.321987 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 10:57:56.328448 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 10:57:56.336214 [CA 0] Center 43 (13~73) winsize 61
7513 10:57:56.339417 [CA 1] Center 43 (13~73) winsize 61
7514 10:57:56.342822 [CA 2] Center 38 (9~67) winsize 59
7515 10:57:56.345992 [CA 3] Center 38 (8~68) winsize 61
7516 10:57:56.349281 [CA 4] Center 37 (7~67) winsize 61
7517 10:57:56.352738 [CA 5] Center 36 (6~66) winsize 61
7518 10:57:56.352826
7519 10:57:56.356043 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 10:57:56.356126
7521 10:57:56.359261 [CATrainingPosCal] consider 2 rank data
7522 10:57:56.362914 u2DelayCellTimex100 = 290/100 ps
7523 10:57:56.369286 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7524 10:57:56.372687 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7525 10:57:56.376010 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7526 10:57:56.379242 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7527 10:57:56.382506 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7528 10:57:56.386011 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7529 10:57:56.386093
7530 10:57:56.389057 CA PerBit enable=1, Macro0, CA PI delay=35
7531 10:57:56.389161
7532 10:57:56.392453 [CBTSetCACLKResult] CA Dly = 35
7533 10:57:56.396074 CS Dly: 11 (0~44)
7534 10:57:56.399025 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 10:57:56.402338 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 10:57:56.402445
7537 10:57:56.405651 ----->DramcWriteLeveling(PI) begin...
7538 10:57:56.405735 ==
7539 10:57:56.408822 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 10:57:56.415755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 10:57:56.415847 ==
7542 10:57:56.418664 Write leveling (Byte 0): 36 => 36
7543 10:57:56.422170 Write leveling (Byte 1): 31 => 31
7544 10:57:56.422253 DramcWriteLeveling(PI) end<-----
7545 10:57:56.425264
7546 10:57:56.425346 ==
7547 10:57:56.428683 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 10:57:56.431842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 10:57:56.431926 ==
7550 10:57:56.435458 [Gating] SW mode calibration
7551 10:57:56.441846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7552 10:57:56.445158 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7553 10:57:56.451893 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 10:57:56.455114 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 10:57:56.458388 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
7556 10:57:56.465164 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7557 10:57:56.468576 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7558 10:57:56.471872 1 4 20 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7559 10:57:56.478413 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 10:57:56.481867 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 10:57:56.485055 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 10:57:56.491484 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 10:57:56.495124 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7564 10:57:56.498252 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7565 10:57:56.504812 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7566 10:57:56.508196 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7567 10:57:56.511430 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7568 10:57:56.518094 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 10:57:56.521388 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 10:57:56.524554 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 10:57:56.530854 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7572 10:57:56.534425 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7573 10:57:56.537771 1 6 16 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
7574 10:57:56.544437 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7575 10:57:56.547627 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 10:57:56.550972 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 10:57:56.557765 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 10:57:56.560830 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 10:57:56.564052 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 10:57:56.570753 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 10:57:56.574171 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7582 10:57:56.577601 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7583 10:57:56.584228 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:57:56.587314 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:57:56.590631 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:57:56.597110 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:57:56.600500 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:57:56.603680 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:57:56.610373 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 10:57:56.613687 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 10:57:56.617348 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 10:57:56.623720 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 10:57:56.627032 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 10:57:56.630390 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 10:57:56.636951 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7596 10:57:56.640196 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 10:57:56.643352 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 10:57:56.650100 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 10:57:56.650176 Total UI for P1: 0, mck2ui 16
7600 10:57:56.656880 best dqsien dly found for B0: ( 1, 9, 12)
7601 10:57:56.659937 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 10:57:56.663051 Total UI for P1: 0, mck2ui 16
7603 10:57:56.666772 best dqsien dly found for B1: ( 1, 9, 20)
7604 10:57:56.669790 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7605 10:57:56.672951 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7606 10:57:56.673049
7607 10:57:56.676683 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7608 10:57:56.679696 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7609 10:57:56.682871 [Gating] SW calibration Done
7610 10:57:56.682940 ==
7611 10:57:56.686140 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 10:57:56.693128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 10:57:56.693225 ==
7614 10:57:56.693314 RX Vref Scan: 0
7615 10:57:56.693404
7616 10:57:56.696069 RX Vref 0 -> 0, step: 1
7617 10:57:56.696136
7618 10:57:56.699482 RX Delay 0 -> 252, step: 8
7619 10:57:56.703105 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7620 10:57:56.706077 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7621 10:57:56.709660 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7622 10:57:56.712845 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7623 10:57:56.719314 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7624 10:57:56.722774 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7625 10:57:56.725994 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7626 10:57:56.729161 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7627 10:57:56.732888 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7628 10:57:56.739334 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7629 10:57:56.742781 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7630 10:57:56.745837 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7631 10:57:56.749234 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7632 10:57:56.752609 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7633 10:57:56.758887 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7634 10:57:56.762119 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7635 10:57:56.762223 ==
7636 10:57:56.765713 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 10:57:56.768772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 10:57:56.768868 ==
7639 10:57:56.772470 DQS Delay:
7640 10:57:56.772572 DQS0 = 0, DQS1 = 0
7641 10:57:56.772661 DQM Delay:
7642 10:57:56.775303 DQM0 = 138, DQM1 = 127
7643 10:57:56.775406 DQ Delay:
7644 10:57:56.778706 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7645 10:57:56.782095 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7646 10:57:56.788775 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7647 10:57:56.792280 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7648 10:57:56.792383
7649 10:57:56.792474
7650 10:57:56.792559 ==
7651 10:57:56.795387 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 10:57:56.798623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 10:57:56.798726 ==
7654 10:57:56.798814
7655 10:57:56.798899
7656 10:57:56.801893 TX Vref Scan disable
7657 10:57:56.805193 == TX Byte 0 ==
7658 10:57:56.808524 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7659 10:57:56.811851 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7660 10:57:56.815326 == TX Byte 1 ==
7661 10:57:56.818827 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7662 10:57:56.821981 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7663 10:57:56.822053 ==
7664 10:57:56.825129 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 10:57:56.828406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 10:57:56.828500 ==
7667 10:57:56.842995
7668 10:57:56.846215 TX Vref early break, caculate TX vref
7669 10:57:56.849688 TX Vref=16, minBit 7, minWin=22, winSum=373
7670 10:57:56.853080 TX Vref=18, minBit 2, minWin=23, winSum=385
7671 10:57:56.856220 TX Vref=20, minBit 7, minWin=23, winSum=391
7672 10:57:56.859576 TX Vref=22, minBit 7, minWin=24, winSum=408
7673 10:57:56.862731 TX Vref=24, minBit 0, minWin=25, winSum=412
7674 10:57:56.870146 TX Vref=26, minBit 2, minWin=25, winSum=422
7675 10:57:56.872930 TX Vref=28, minBit 2, minWin=26, winSum=430
7676 10:57:56.876267 TX Vref=30, minBit 0, minWin=25, winSum=420
7677 10:57:56.879615 TX Vref=32, minBit 0, minWin=25, winSum=411
7678 10:57:56.882469 TX Vref=34, minBit 0, minWin=24, winSum=403
7679 10:57:56.889464 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 28
7680 10:57:56.889562
7681 10:57:56.892592 Final TX Range 0 Vref 28
7682 10:57:56.892689
7683 10:57:56.892782 ==
7684 10:57:56.895897 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 10:57:56.899005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 10:57:56.899099 ==
7687 10:57:56.899186
7688 10:57:56.899274
7689 10:57:56.902579 TX Vref Scan disable
7690 10:57:56.908895 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7691 10:57:56.908991 == TX Byte 0 ==
7692 10:57:56.912421 u2DelayCellOfst[0]=10 cells (3 PI)
7693 10:57:56.915581 u2DelayCellOfst[1]=16 cells (5 PI)
7694 10:57:56.919143 u2DelayCellOfst[2]=10 cells (3 PI)
7695 10:57:56.922331 u2DelayCellOfst[3]=10 cells (3 PI)
7696 10:57:56.925378 u2DelayCellOfst[4]=6 cells (2 PI)
7697 10:57:56.928700 u2DelayCellOfst[5]=0 cells (0 PI)
7698 10:57:56.932116 u2DelayCellOfst[6]=16 cells (5 PI)
7699 10:57:56.935487 u2DelayCellOfst[7]=16 cells (5 PI)
7700 10:57:56.938827 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7701 10:57:56.942016 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7702 10:57:56.945256 == TX Byte 1 ==
7703 10:57:56.948925 u2DelayCellOfst[8]=3 cells (1 PI)
7704 10:57:56.948996 u2DelayCellOfst[9]=0 cells (0 PI)
7705 10:57:56.952126 u2DelayCellOfst[10]=6 cells (2 PI)
7706 10:57:56.955312 u2DelayCellOfst[11]=3 cells (1 PI)
7707 10:57:56.958526 u2DelayCellOfst[12]=13 cells (4 PI)
7708 10:57:56.961940 u2DelayCellOfst[13]=13 cells (4 PI)
7709 10:57:56.965294 u2DelayCellOfst[14]=16 cells (5 PI)
7710 10:57:56.968601 u2DelayCellOfst[15]=10 cells (3 PI)
7711 10:57:56.975244 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7712 10:57:56.978170 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7713 10:57:56.978265 DramC Write-DBI on
7714 10:57:56.978352 ==
7715 10:57:56.981386 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 10:57:56.988273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 10:57:56.988374 ==
7718 10:57:56.988462
7719 10:57:56.988547
7720 10:57:56.988635 TX Vref Scan disable
7721 10:57:56.992373 == TX Byte 0 ==
7722 10:57:56.995861 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7723 10:57:56.999109 == TX Byte 1 ==
7724 10:57:57.002236 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7725 10:57:57.005573 DramC Write-DBI off
7726 10:57:57.005641
7727 10:57:57.005700 [DATLAT]
7728 10:57:57.005756 Freq=1600, CH0 RK0
7729 10:57:57.005819
7730 10:57:57.008738 DATLAT Default: 0xf
7731 10:57:57.012025 0, 0xFFFF, sum = 0
7732 10:57:57.012121 1, 0xFFFF, sum = 0
7733 10:57:57.015120 2, 0xFFFF, sum = 0
7734 10:57:57.015190 3, 0xFFFF, sum = 0
7735 10:57:57.018540 4, 0xFFFF, sum = 0
7736 10:57:57.018636 5, 0xFFFF, sum = 0
7737 10:57:57.022021 6, 0xFFFF, sum = 0
7738 10:57:57.022090 7, 0xFFFF, sum = 0
7739 10:57:57.025075 8, 0xFFFF, sum = 0
7740 10:57:57.025169 9, 0xFFFF, sum = 0
7741 10:57:57.028605 10, 0xFFFF, sum = 0
7742 10:57:57.028700 11, 0xFFFF, sum = 0
7743 10:57:57.031690 12, 0xFFFF, sum = 0
7744 10:57:57.031785 13, 0xFFFF, sum = 0
7745 10:57:57.035207 14, 0x0, sum = 1
7746 10:57:57.035276 15, 0x0, sum = 2
7747 10:57:57.038450 16, 0x0, sum = 3
7748 10:57:57.038518 17, 0x0, sum = 4
7749 10:57:57.041667 best_step = 15
7750 10:57:57.041738
7751 10:57:57.041796 ==
7752 10:57:57.045033 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 10:57:57.048152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 10:57:57.048227 ==
7755 10:57:57.051637 RX Vref Scan: 1
7756 10:57:57.051704
7757 10:57:57.051766 Set Vref Range= 24 -> 127
7758 10:57:57.054652
7759 10:57:57.054717 RX Vref 24 -> 127, step: 1
7760 10:57:57.054783
7761 10:57:57.058232 RX Delay 19 -> 252, step: 4
7762 10:57:57.058327
7763 10:57:57.061787 Set Vref, RX VrefLevel [Byte0]: 24
7764 10:57:57.064712 [Byte1]: 24
7765 10:57:57.064837
7766 10:57:57.067918 Set Vref, RX VrefLevel [Byte0]: 25
7767 10:57:57.071522 [Byte1]: 25
7768 10:57:57.075059
7769 10:57:57.075153 Set Vref, RX VrefLevel [Byte0]: 26
7770 10:57:57.078356 [Byte1]: 26
7771 10:57:57.082711
7772 10:57:57.082779 Set Vref, RX VrefLevel [Byte0]: 27
7773 10:57:57.085735 [Byte1]: 27
7774 10:57:57.090220
7775 10:57:57.090301 Set Vref, RX VrefLevel [Byte0]: 28
7776 10:57:57.093837 [Byte1]: 28
7777 10:57:57.097509
7778 10:57:57.097590 Set Vref, RX VrefLevel [Byte0]: 29
7779 10:57:57.100905 [Byte1]: 29
7780 10:57:57.105224
7781 10:57:57.105305 Set Vref, RX VrefLevel [Byte0]: 30
7782 10:57:57.108722 [Byte1]: 30
7783 10:57:57.112775
7784 10:57:57.112857 Set Vref, RX VrefLevel [Byte0]: 31
7785 10:57:57.116128 [Byte1]: 31
7786 10:57:57.120552
7787 10:57:57.120634 Set Vref, RX VrefLevel [Byte0]: 32
7788 10:57:57.124322 [Byte1]: 32
7789 10:57:57.127938
7790 10:57:57.128020 Set Vref, RX VrefLevel [Byte0]: 33
7791 10:57:57.131349 [Byte1]: 33
7792 10:57:57.135720
7793 10:57:57.135801 Set Vref, RX VrefLevel [Byte0]: 34
7794 10:57:57.138860 [Byte1]: 34
7795 10:57:57.143293
7796 10:57:57.143375 Set Vref, RX VrefLevel [Byte0]: 35
7797 10:57:57.146364 [Byte1]: 35
7798 10:57:57.150806
7799 10:57:57.150887 Set Vref, RX VrefLevel [Byte0]: 36
7800 10:57:57.154075 [Byte1]: 36
7801 10:57:57.158142
7802 10:57:57.158223 Set Vref, RX VrefLevel [Byte0]: 37
7803 10:57:57.161482 [Byte1]: 37
7804 10:57:57.165976
7805 10:57:57.166058 Set Vref, RX VrefLevel [Byte0]: 38
7806 10:57:57.169248 [Byte1]: 38
7807 10:57:57.173781
7808 10:57:57.173863 Set Vref, RX VrefLevel [Byte0]: 39
7809 10:57:57.176997 [Byte1]: 39
7810 10:57:57.180957
7811 10:57:57.181065 Set Vref, RX VrefLevel [Byte0]: 40
7812 10:57:57.184721 [Byte1]: 40
7813 10:57:57.188534
7814 10:57:57.188615 Set Vref, RX VrefLevel [Byte0]: 41
7815 10:57:57.191740 [Byte1]: 41
7816 10:57:57.196185
7817 10:57:57.196267 Set Vref, RX VrefLevel [Byte0]: 42
7818 10:57:57.199566 [Byte1]: 42
7819 10:57:57.203746
7820 10:57:57.203827 Set Vref, RX VrefLevel [Byte0]: 43
7821 10:57:57.207045 [Byte1]: 43
7822 10:57:57.211395
7823 10:57:57.211476 Set Vref, RX VrefLevel [Byte0]: 44
7824 10:57:57.214457 [Byte1]: 44
7825 10:57:57.218784
7826 10:57:57.218868 Set Vref, RX VrefLevel [Byte0]: 45
7827 10:57:57.222274 [Byte1]: 45
7828 10:57:57.226433
7829 10:57:57.226515 Set Vref, RX VrefLevel [Byte0]: 46
7830 10:57:57.229814 [Byte1]: 46
7831 10:57:57.234122
7832 10:57:57.234204 Set Vref, RX VrefLevel [Byte0]: 47
7833 10:57:57.237363 [Byte1]: 47
7834 10:57:57.241999
7835 10:57:57.242081 Set Vref, RX VrefLevel [Byte0]: 48
7836 10:57:57.244974 [Byte1]: 48
7837 10:57:57.249329
7838 10:57:57.249411 Set Vref, RX VrefLevel [Byte0]: 49
7839 10:57:57.252620 [Byte1]: 49
7840 10:57:57.256712
7841 10:57:57.256815 Set Vref, RX VrefLevel [Byte0]: 50
7842 10:57:57.260003 [Byte1]: 50
7843 10:57:57.264512
7844 10:57:57.264594 Set Vref, RX VrefLevel [Byte0]: 51
7845 10:57:57.267599 [Byte1]: 51
7846 10:57:57.272031
7847 10:57:57.272113 Set Vref, RX VrefLevel [Byte0]: 52
7848 10:57:57.275298 [Byte1]: 52
7849 10:57:57.279479
7850 10:57:57.279561 Set Vref, RX VrefLevel [Byte0]: 53
7851 10:57:57.282839 [Byte1]: 53
7852 10:57:57.286973
7853 10:57:57.287056 Set Vref, RX VrefLevel [Byte0]: 54
7854 10:57:57.290196 [Byte1]: 54
7855 10:57:57.294698
7856 10:57:57.294781 Set Vref, RX VrefLevel [Byte0]: 55
7857 10:57:57.298013 [Byte1]: 55
7858 10:57:57.302058
7859 10:57:57.302141 Set Vref, RX VrefLevel [Byte0]: 56
7860 10:57:57.305446 [Byte1]: 56
7861 10:57:57.309881
7862 10:57:57.309969 Set Vref, RX VrefLevel [Byte0]: 57
7863 10:57:57.313307 [Byte1]: 57
7864 10:57:57.317489
7865 10:57:57.317571 Set Vref, RX VrefLevel [Byte0]: 58
7866 10:57:57.320988 [Byte1]: 58
7867 10:57:57.325013
7868 10:57:57.325095 Set Vref, RX VrefLevel [Byte0]: 59
7869 10:57:57.328141 [Byte1]: 59
7870 10:57:57.332382
7871 10:57:57.332465 Set Vref, RX VrefLevel [Byte0]: 60
7872 10:57:57.335693 [Byte1]: 60
7873 10:57:57.339865
7874 10:57:57.339948 Set Vref, RX VrefLevel [Byte0]: 61
7875 10:57:57.343395 [Byte1]: 61
7876 10:57:57.347907
7877 10:57:57.347988 Set Vref, RX VrefLevel [Byte0]: 62
7878 10:57:57.350880 [Byte1]: 62
7879 10:57:57.355072
7880 10:57:57.355155 Set Vref, RX VrefLevel [Byte0]: 63
7881 10:57:57.358624 [Byte1]: 63
7882 10:57:57.363136
7883 10:57:57.363219 Set Vref, RX VrefLevel [Byte0]: 64
7884 10:57:57.366110 [Byte1]: 64
7885 10:57:57.370371
7886 10:57:57.370454 Set Vref, RX VrefLevel [Byte0]: 65
7887 10:57:57.373461 [Byte1]: 65
7888 10:57:57.377753
7889 10:57:57.377838 Set Vref, RX VrefLevel [Byte0]: 66
7890 10:57:57.381108 [Byte1]: 66
7891 10:57:57.385690
7892 10:57:57.385772 Set Vref, RX VrefLevel [Byte0]: 67
7893 10:57:57.388610 [Byte1]: 67
7894 10:57:57.393188
7895 10:57:57.393270 Set Vref, RX VrefLevel [Byte0]: 68
7896 10:57:57.396223 [Byte1]: 68
7897 10:57:57.400670
7898 10:57:57.400752 Set Vref, RX VrefLevel [Byte0]: 69
7899 10:57:57.403967 [Byte1]: 69
7900 10:57:57.408398
7901 10:57:57.408481 Set Vref, RX VrefLevel [Byte0]: 70
7902 10:57:57.411796 [Byte1]: 70
7903 10:57:57.415691
7904 10:57:57.415772 Set Vref, RX VrefLevel [Byte0]: 71
7905 10:57:57.418986 [Byte1]: 71
7906 10:57:57.423233
7907 10:57:57.423315 Set Vref, RX VrefLevel [Byte0]: 72
7908 10:57:57.426715 [Byte1]: 72
7909 10:57:57.430990
7910 10:57:57.431072 Set Vref, RX VrefLevel [Byte0]: 73
7911 10:57:57.434041 [Byte1]: 73
7912 10:57:57.438388
7913 10:57:57.438470 Set Vref, RX VrefLevel [Byte0]: 74
7914 10:57:57.441724 [Byte1]: 74
7915 10:57:57.446191
7916 10:57:57.446273 Set Vref, RX VrefLevel [Byte0]: 75
7917 10:57:57.449442 [Byte1]: 75
7918 10:57:57.453808
7919 10:57:57.453890 Set Vref, RX VrefLevel [Byte0]: 76
7920 10:57:57.456886 [Byte1]: 76
7921 10:57:57.461329
7922 10:57:57.461411 Set Vref, RX VrefLevel [Byte0]: 77
7923 10:57:57.464547 [Byte1]: 77
7924 10:57:57.468943
7925 10:57:57.469026 Set Vref, RX VrefLevel [Byte0]: 78
7926 10:57:57.472032 [Byte1]: 78
7927 10:57:57.476206
7928 10:57:57.476288 Set Vref, RX VrefLevel [Byte0]: 79
7929 10:57:57.479468 [Byte1]: 79
7930 10:57:57.484071
7931 10:57:57.484154 Final RX Vref Byte 0 = 61 to rank0
7932 10:57:57.487138 Final RX Vref Byte 1 = 61 to rank0
7933 10:57:57.490419 Final RX Vref Byte 0 = 61 to rank1
7934 10:57:57.493984 Final RX Vref Byte 1 = 61 to rank1==
7935 10:57:57.497408 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 10:57:57.503796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 10:57:57.503880 ==
7938 10:57:57.503945 DQS Delay:
7939 10:57:57.504007 DQS0 = 0, DQS1 = 0
7940 10:57:57.507425 DQM Delay:
7941 10:57:57.507526 DQM0 = 136, DQM1 = 124
7942 10:57:57.510470 DQ Delay:
7943 10:57:57.513785 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7944 10:57:57.517053 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7945 10:57:57.520668 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7946 10:57:57.523589 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7947 10:57:57.523672
7948 10:57:57.523737
7949 10:57:57.523798
7950 10:57:57.526945 [DramC_TX_OE_Calibration] TA2
7951 10:57:57.530483 Original DQ_B0 (3 6) =30, OEN = 27
7952 10:57:57.533671 Original DQ_B1 (3 6) =30, OEN = 27
7953 10:57:57.537010 24, 0x0, End_B0=24 End_B1=24
7954 10:57:57.537094 25, 0x0, End_B0=25 End_B1=25
7955 10:57:57.540365 26, 0x0, End_B0=26 End_B1=26
7956 10:57:57.543621 27, 0x0, End_B0=27 End_B1=27
7957 10:57:57.546690 28, 0x0, End_B0=28 End_B1=28
7958 10:57:57.550154 29, 0x0, End_B0=29 End_B1=29
7959 10:57:57.550238 30, 0x0, End_B0=30 End_B1=30
7960 10:57:57.553237 31, 0x4545, End_B0=30 End_B1=30
7961 10:57:57.556771 Byte0 end_step=30 best_step=27
7962 10:57:57.560358 Byte1 end_step=30 best_step=27
7963 10:57:57.563452 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 10:57:57.566958 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 10:57:57.567041
7966 10:57:57.567107
7967 10:57:57.573224 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7968 10:57:57.576791 CH0 RK0: MR19=303, MR18=1E1C
7969 10:57:57.583262 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7970 10:57:57.583345
7971 10:57:57.586441 ----->DramcWriteLeveling(PI) begin...
7972 10:57:57.586525 ==
7973 10:57:57.589689 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 10:57:57.593094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 10:57:57.593177 ==
7976 10:57:57.596441 Write leveling (Byte 0): 38 => 38
7977 10:57:57.599659 Write leveling (Byte 1): 29 => 29
7978 10:57:57.603154 DramcWriteLeveling(PI) end<-----
7979 10:57:57.603237
7980 10:57:57.603302 ==
7981 10:57:57.606212 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 10:57:57.609433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 10:57:57.609517 ==
7984 10:57:57.612997 [Gating] SW mode calibration
7985 10:57:57.619321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 10:57:57.626080 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 10:57:57.629402 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 10:57:57.636310 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 10:57:57.639291 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 10:57:57.642666 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7991 10:57:57.649587 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 10:57:57.652622 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 10:57:57.656010 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 10:57:57.662517 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 10:57:57.666065 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 10:57:57.668801 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 10:57:57.675644 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 10:57:57.679222 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7999 10:57:57.682295 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8000 10:57:57.688745 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 10:57:57.692476 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 10:57:57.695749 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 10:57:57.702240 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 10:57:57.705470 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 10:57:57.709056 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8006 10:57:57.715590 1 6 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
8007 10:57:57.718991 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8008 10:57:57.722006 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 10:57:57.728339 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 10:57:57.731797 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 10:57:57.735235 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 10:57:57.741473 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 10:57:57.745156 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 10:57:57.748449 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8015 10:57:57.754572 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 10:57:57.758045 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8017 10:57:57.761398 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 10:57:57.768007 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 10:57:57.771195 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 10:57:57.774600 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 10:57:57.781430 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 10:57:57.784580 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 10:57:57.788346 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 10:57:57.794296 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 10:57:57.797906 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 10:57:57.800989 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 10:57:57.807513 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 10:57:57.811024 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 10:57:57.814267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 10:57:57.820682 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8031 10:57:57.824373 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 10:57:57.827319 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 10:57:57.830820 Total UI for P1: 0, mck2ui 16
8034 10:57:57.834100 best dqsien dly found for B0: ( 1, 9, 14)
8035 10:57:57.837368 Total UI for P1: 0, mck2ui 16
8036 10:57:57.840636 best dqsien dly found for B1: ( 1, 9, 14)
8037 10:57:57.844299 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8038 10:57:57.847357 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8039 10:57:57.847428
8040 10:57:57.850673 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8041 10:57:57.857290 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8042 10:57:57.857364 [Gating] SW calibration Done
8043 10:57:57.860223 ==
8044 10:57:57.863638 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 10:57:57.867144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 10:57:57.867214 ==
8047 10:57:57.867277 RX Vref Scan: 0
8048 10:57:57.867336
8049 10:57:57.870228 RX Vref 0 -> 0, step: 1
8050 10:57:57.870298
8051 10:57:57.873584 RX Delay 0 -> 252, step: 8
8052 10:57:57.877050 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8053 10:57:57.879910 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8054 10:57:57.883574 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8055 10:57:57.890115 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8056 10:57:57.893348 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8057 10:57:57.896732 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8058 10:57:57.899760 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8059 10:57:57.903272 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8060 10:57:57.909826 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8061 10:57:57.913339 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8062 10:57:57.916601 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8063 10:57:57.919945 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8064 10:57:57.926618 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8065 10:57:57.929706 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8066 10:57:57.932938 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8067 10:57:57.936334 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8068 10:57:57.936412 ==
8069 10:57:57.939952 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 10:57:57.946181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 10:57:57.946260 ==
8072 10:57:57.946324 DQS Delay:
8073 10:57:57.946386 DQS0 = 0, DQS1 = 0
8074 10:57:57.949742 DQM Delay:
8075 10:57:57.949813 DQM0 = 136, DQM1 = 124
8076 10:57:57.952877 DQ Delay:
8077 10:57:57.956015 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8078 10:57:57.959190 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8079 10:57:57.962669 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8080 10:57:57.966228 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8081 10:57:57.966298
8082 10:57:57.966362
8083 10:57:57.966420 ==
8084 10:57:57.969414 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 10:57:57.975428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 10:57:57.975499 ==
8087 10:57:57.975559
8088 10:57:57.975620
8089 10:57:57.975675 TX Vref Scan disable
8090 10:57:57.979224 == TX Byte 0 ==
8091 10:57:57.982466 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8092 10:57:57.989409 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8093 10:57:57.989482 == TX Byte 1 ==
8094 10:57:57.992419 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8095 10:57:57.998803 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8096 10:57:57.998877 ==
8097 10:57:58.002099 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 10:57:58.005366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 10:57:58.005442 ==
8100 10:57:58.018678
8101 10:57:58.022248 TX Vref early break, caculate TX vref
8102 10:57:58.025611 TX Vref=16, minBit 8, minWin=22, winSum=388
8103 10:57:58.028907 TX Vref=18, minBit 0, minWin=24, winSum=400
8104 10:57:58.032231 TX Vref=20, minBit 3, minWin=24, winSum=407
8105 10:57:58.035417 TX Vref=22, minBit 8, minWin=24, winSum=413
8106 10:57:58.039067 TX Vref=24, minBit 0, minWin=25, winSum=422
8107 10:57:58.045687 TX Vref=26, minBit 8, minWin=25, winSum=427
8108 10:57:58.048711 TX Vref=28, minBit 0, minWin=26, winSum=433
8109 10:57:58.052250 TX Vref=30, minBit 0, minWin=26, winSum=428
8110 10:57:58.055478 TX Vref=32, minBit 0, minWin=25, winSum=420
8111 10:57:58.058628 TX Vref=34, minBit 4, minWin=24, winSum=409
8112 10:57:58.065407 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8113 10:57:58.065479
8114 10:57:58.068960 Final TX Range 0 Vref 28
8115 10:57:58.069033
8116 10:57:58.069093 ==
8117 10:57:58.071742 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 10:57:58.075281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 10:57:58.075348 ==
8120 10:57:58.075410
8121 10:57:58.075467
8122 10:57:58.078712 TX Vref Scan disable
8123 10:57:58.084950 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8124 10:57:58.085020 == TX Byte 0 ==
8125 10:57:58.088178 u2DelayCellOfst[0]=13 cells (4 PI)
8126 10:57:58.091767 u2DelayCellOfst[1]=20 cells (6 PI)
8127 10:57:58.095017 u2DelayCellOfst[2]=13 cells (4 PI)
8128 10:57:58.098500 u2DelayCellOfst[3]=13 cells (4 PI)
8129 10:57:58.101486 u2DelayCellOfst[4]=10 cells (3 PI)
8130 10:57:58.104714 u2DelayCellOfst[5]=0 cells (0 PI)
8131 10:57:58.108178 u2DelayCellOfst[6]=20 cells (6 PI)
8132 10:57:58.111661 u2DelayCellOfst[7]=20 cells (6 PI)
8133 10:57:58.114682 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8134 10:57:58.118197 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8135 10:57:58.121242 == TX Byte 1 ==
8136 10:57:58.124677 u2DelayCellOfst[8]=0 cells (0 PI)
8137 10:57:58.127921 u2DelayCellOfst[9]=0 cells (0 PI)
8138 10:57:58.127988 u2DelayCellOfst[10]=3 cells (1 PI)
8139 10:57:58.131047 u2DelayCellOfst[11]=0 cells (0 PI)
8140 10:57:58.134427 u2DelayCellOfst[12]=10 cells (3 PI)
8141 10:57:58.137922 u2DelayCellOfst[13]=10 cells (3 PI)
8142 10:57:58.141219 u2DelayCellOfst[14]=10 cells (3 PI)
8143 10:57:58.144752 u2DelayCellOfst[15]=6 cells (2 PI)
8144 10:57:58.150888 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8145 10:57:58.154174 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8146 10:57:58.154247 DramC Write-DBI on
8147 10:57:58.154310 ==
8148 10:57:58.157555 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 10:57:58.164167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 10:57:58.164239 ==
8151 10:57:58.164302
8152 10:57:58.164359
8153 10:57:58.167598 TX Vref Scan disable
8154 10:57:58.167663 == TX Byte 0 ==
8155 10:57:58.174116 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8156 10:57:58.174189 == TX Byte 1 ==
8157 10:57:58.177209 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8158 10:57:58.180600 DramC Write-DBI off
8159 10:57:58.180664
8160 10:57:58.180724 [DATLAT]
8161 10:57:58.184069 Freq=1600, CH0 RK1
8162 10:57:58.184135
8163 10:57:58.184198 DATLAT Default: 0xf
8164 10:57:58.187232 0, 0xFFFF, sum = 0
8165 10:57:58.187298 1, 0xFFFF, sum = 0
8166 10:57:58.190934 2, 0xFFFF, sum = 0
8167 10:57:58.191002 3, 0xFFFF, sum = 0
8168 10:57:58.193659 4, 0xFFFF, sum = 0
8169 10:57:58.193727 5, 0xFFFF, sum = 0
8170 10:57:58.197282 6, 0xFFFF, sum = 0
8171 10:57:58.200649 7, 0xFFFF, sum = 0
8172 10:57:58.200719 8, 0xFFFF, sum = 0
8173 10:57:58.203752 9, 0xFFFF, sum = 0
8174 10:57:58.203824 10, 0xFFFF, sum = 0
8175 10:57:58.207077 11, 0xFFFF, sum = 0
8176 10:57:58.207153 12, 0xFFFF, sum = 0
8177 10:57:58.210359 13, 0xFFFF, sum = 0
8178 10:57:58.210429 14, 0x0, sum = 1
8179 10:57:58.213672 15, 0x0, sum = 2
8180 10:57:58.213739 16, 0x0, sum = 3
8181 10:57:58.216897 17, 0x0, sum = 4
8182 10:57:58.216975 best_step = 15
8183 10:57:58.217037
8184 10:57:58.217097 ==
8185 10:57:58.220307 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 10:57:58.223358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 10:57:58.223429 ==
8188 10:57:58.226792 RX Vref Scan: 0
8189 10:57:58.226862
8190 10:57:58.230325 RX Vref 0 -> 0, step: 1
8191 10:57:58.230399
8192 10:57:58.230466 RX Delay 11 -> 252, step: 4
8193 10:57:58.237361 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8194 10:57:58.241023 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8195 10:57:58.244292 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8196 10:57:58.248022 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8197 10:57:58.250797 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8198 10:57:58.257533 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8199 10:57:58.260877 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8200 10:57:58.263659 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8201 10:57:58.267298 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8202 10:57:58.270337 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8203 10:57:58.277169 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8204 10:57:58.280644 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8205 10:57:58.283795 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8206 10:57:58.286825 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8207 10:57:58.293678 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8208 10:57:58.297059 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8209 10:57:58.297126 ==
8210 10:57:58.300094 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 10:57:58.303809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 10:57:58.303878 ==
8213 10:57:58.306741 DQS Delay:
8214 10:57:58.306806 DQS0 = 0, DQS1 = 0
8215 10:57:58.306865 DQM Delay:
8216 10:57:58.310338 DQM0 = 133, DQM1 = 123
8217 10:57:58.310405 DQ Delay:
8218 10:57:58.313383 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8219 10:57:58.316605 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8220 10:57:58.323585 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8221 10:57:58.326411 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8222 10:57:58.326480
8223 10:57:58.326545
8224 10:57:58.326605
8225 10:57:58.329754 [DramC_TX_OE_Calibration] TA2
8226 10:57:58.332814 Original DQ_B0 (3 6) =30, OEN = 27
8227 10:57:58.336389 Original DQ_B1 (3 6) =30, OEN = 27
8228 10:57:58.336469 24, 0x0, End_B0=24 End_B1=24
8229 10:57:58.339449 25, 0x0, End_B0=25 End_B1=25
8230 10:57:58.342864 26, 0x0, End_B0=26 End_B1=26
8231 10:57:58.345979 27, 0x0, End_B0=27 End_B1=27
8232 10:57:58.346051 28, 0x0, End_B0=28 End_B1=28
8233 10:57:58.349602 29, 0x0, End_B0=29 End_B1=29
8234 10:57:58.352861 30, 0x0, End_B0=30 End_B1=30
8235 10:57:58.356139 31, 0x4141, End_B0=30 End_B1=30
8236 10:57:58.359616 Byte0 end_step=30 best_step=27
8237 10:57:58.362640 Byte1 end_step=30 best_step=27
8238 10:57:58.362711 Byte0 TX OE(2T, 0.5T) = (3, 3)
8239 10:57:58.366264 Byte1 TX OE(2T, 0.5T) = (3, 3)
8240 10:57:58.366334
8241 10:57:58.366395
8242 10:57:58.376041 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8243 10:57:58.379197 CH0 RK1: MR19=303, MR18=220F
8244 10:57:58.382794 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8245 10:57:58.385588 [RxdqsGatingPostProcess] freq 1600
8246 10:57:58.392226 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8247 10:57:58.395920 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 10:57:58.399564 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 10:57:58.402214 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 10:57:58.405861 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 10:57:58.409248 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 10:57:58.412180 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 10:57:58.415359 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 10:57:58.415431 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 10:57:58.418865 Pre-setting of DQS Precalculation
8256 10:57:58.425348 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8257 10:57:58.425420 ==
8258 10:57:58.428943 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 10:57:58.432050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 10:57:58.432126 ==
8261 10:57:58.438368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 10:57:58.441929 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 10:57:58.448371 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 10:57:58.451665 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 10:57:58.461554 [CA 0] Center 42 (12~72) winsize 61
8266 10:57:58.464754 [CA 1] Center 42 (12~72) winsize 61
8267 10:57:58.468139 [CA 2] Center 38 (9~67) winsize 59
8268 10:57:58.471382 [CA 3] Center 36 (7~66) winsize 60
8269 10:57:58.474737 [CA 4] Center 37 (7~68) winsize 62
8270 10:57:58.477977 [CA 5] Center 37 (7~67) winsize 61
8271 10:57:58.478052
8272 10:57:58.481149 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8273 10:57:58.481219
8274 10:57:58.487503 [CATrainingPosCal] consider 1 rank data
8275 10:57:58.487578 u2DelayCellTimex100 = 290/100 ps
8276 10:57:58.494777 CA0 delay=42 (12~72),Diff = 6 PI (20 cell)
8277 10:57:58.497731 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8278 10:57:58.501005 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8279 10:57:58.504308 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8280 10:57:58.507659 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8281 10:57:58.511107 CA5 delay=37 (7~67),Diff = 1 PI (3 cell)
8282 10:57:58.511174
8283 10:57:58.514366 CA PerBit enable=1, Macro0, CA PI delay=36
8284 10:57:58.514432
8285 10:57:58.517801 [CBTSetCACLKResult] CA Dly = 36
8286 10:57:58.520912 CS Dly: 8 (0~39)
8287 10:57:58.524116 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 10:57:58.527671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 10:57:58.527746 ==
8290 10:57:58.531108 Dram Type= 6, Freq= 0, CH_1, rank 1
8291 10:57:58.537570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 10:57:58.537650 ==
8293 10:57:58.540737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 10:57:58.544011 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 10:57:58.551001 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 10:57:58.557474 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 10:57:58.564388 [CA 0] Center 42 (13~71) winsize 59
8298 10:57:58.567886 [CA 1] Center 41 (12~71) winsize 60
8299 10:57:58.571222 [CA 2] Center 38 (9~67) winsize 59
8300 10:57:58.574409 [CA 3] Center 37 (8~67) winsize 60
8301 10:57:58.577455 [CA 4] Center 37 (8~67) winsize 60
8302 10:57:58.580987 [CA 5] Center 37 (7~67) winsize 61
8303 10:57:58.581053
8304 10:57:58.584283 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8305 10:57:58.584348
8306 10:57:58.591197 [CATrainingPosCal] consider 2 rank data
8307 10:57:58.591265 u2DelayCellTimex100 = 290/100 ps
8308 10:57:58.597315 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8309 10:57:58.600908 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8310 10:57:58.603944 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8311 10:57:58.607273 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8312 10:57:58.610382 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8313 10:57:58.614069 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8314 10:57:58.614134
8315 10:57:58.617001 CA PerBit enable=1, Macro0, CA PI delay=37
8316 10:57:58.617071
8317 10:57:58.620669 [CBTSetCACLKResult] CA Dly = 37
8318 10:57:58.623728 CS Dly: 9 (0~42)
8319 10:57:58.627101 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 10:57:58.630578 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 10:57:58.630648
8322 10:57:58.633458 ----->DramcWriteLeveling(PI) begin...
8323 10:57:58.633526 ==
8324 10:57:58.636755 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 10:57:58.643534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 10:57:58.643610 ==
8327 10:57:58.646707 Write leveling (Byte 0): 23 => 23
8328 10:57:58.650318 Write leveling (Byte 1): 27 => 27
8329 10:57:58.653336 DramcWriteLeveling(PI) end<-----
8330 10:57:58.653410
8331 10:57:58.653470 ==
8332 10:57:58.656732 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 10:57:58.659892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 10:57:58.659965 ==
8335 10:57:58.663581 [Gating] SW mode calibration
8336 10:57:58.669960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8337 10:57:58.673340 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8338 10:57:58.679763 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 10:57:58.683148 1 4 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8340 10:57:58.686655 1 4 8 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 1)
8341 10:57:58.693422 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 10:57:58.696256 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 10:57:58.699676 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 10:57:58.706270 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 10:57:58.709780 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 10:57:58.713086 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 10:57:58.720043 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 10:57:58.722944 1 5 8 | B1->B0 | 2828 2727 | 0 0 | (0 1) (0 1)
8349 10:57:58.726204 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 10:57:58.732709 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 10:57:58.736258 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 10:57:58.739819 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 10:57:58.746123 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 10:57:58.749644 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 10:57:58.752644 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 10:57:58.759301 1 6 8 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
8357 10:57:58.762667 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 10:57:58.765730 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 10:57:58.772638 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 10:57:58.775740 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 10:57:58.779082 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 10:57:58.785882 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 10:57:58.788755 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8364 10:57:58.792543 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8365 10:57:58.798775 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8366 10:57:58.802007 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 10:57:58.805539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 10:57:58.811889 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 10:57:58.815137 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 10:57:58.818601 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 10:57:58.825088 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 10:57:58.828527 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 10:57:58.831986 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 10:57:58.838500 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 10:57:58.841859 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 10:57:58.844899 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 10:57:58.852145 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 10:57:58.854864 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 10:57:58.857957 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8380 10:57:58.864569 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 10:57:58.868465 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8382 10:57:58.871525 Total UI for P1: 0, mck2ui 16
8383 10:57:58.874554 best dqsien dly found for B0: ( 1, 9, 6)
8384 10:57:58.877916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 10:57:58.881255 Total UI for P1: 0, mck2ui 16
8386 10:57:58.884675 best dqsien dly found for B1: ( 1, 9, 10)
8387 10:57:58.888223 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8388 10:57:58.891200 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8389 10:57:58.891271
8390 10:57:58.897548 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8391 10:57:58.900927 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 10:57:58.904183 [Gating] SW calibration Done
8393 10:57:58.904253 ==
8394 10:57:58.907821 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 10:57:58.910997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 10:57:58.911073 ==
8397 10:57:58.911135 RX Vref Scan: 0
8398 10:57:58.911203
8399 10:57:58.914207 RX Vref 0 -> 0, step: 1
8400 10:57:58.914285
8401 10:57:58.917572 RX Delay 0 -> 252, step: 8
8402 10:57:58.921031 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8403 10:57:58.924168 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8404 10:57:58.930746 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8405 10:57:58.934019 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8406 10:57:58.937241 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8407 10:57:58.940707 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8408 10:57:58.943869 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8409 10:57:58.950567 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8410 10:57:58.953813 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8411 10:57:58.957145 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8412 10:57:58.960434 iDelay=200, Bit 10, Center 135 (88 ~ 183) 96
8413 10:57:58.963582 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8414 10:57:58.970146 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8415 10:57:58.973524 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8416 10:57:58.976915 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8417 10:57:58.980507 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8418 10:57:58.980589 ==
8419 10:57:58.983311 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 10:57:58.989974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 10:57:58.990057 ==
8422 10:57:58.990128 DQS Delay:
8423 10:57:58.993506 DQS0 = 0, DQS1 = 0
8424 10:57:58.993614 DQM Delay:
8425 10:57:58.993683 DQM0 = 136, DQM1 = 131
8426 10:57:58.996730 DQ Delay:
8427 10:57:58.999777 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8428 10:57:59.003088 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8429 10:57:59.006683 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8430 10:57:59.009687 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8431 10:57:59.009774
8432 10:57:59.009839
8433 10:57:59.009897 ==
8434 10:57:59.013139 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 10:57:59.019655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 10:57:59.019737 ==
8437 10:57:59.019802
8438 10:57:59.019862
8439 10:57:59.019919 TX Vref Scan disable
8440 10:57:59.022967 == TX Byte 0 ==
8441 10:57:59.026043 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8442 10:57:59.032760 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8443 10:57:59.032877 == TX Byte 1 ==
8444 10:57:59.035847 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8445 10:57:59.042971 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8446 10:57:59.043052 ==
8447 10:57:59.045936 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 10:57:59.049428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 10:57:59.049509 ==
8450 10:57:59.062929
8451 10:57:59.065999 TX Vref early break, caculate TX vref
8452 10:57:59.069286 TX Vref=16, minBit 10, minWin=22, winSum=372
8453 10:57:59.072610 TX Vref=18, minBit 9, minWin=23, winSum=381
8454 10:57:59.076603 TX Vref=20, minBit 10, minWin=23, winSum=392
8455 10:57:59.079264 TX Vref=22, minBit 9, minWin=24, winSum=403
8456 10:57:59.085888 TX Vref=24, minBit 14, minWin=24, winSum=411
8457 10:57:59.089416 TX Vref=26, minBit 10, minWin=24, winSum=420
8458 10:57:59.092404 TX Vref=28, minBit 12, minWin=25, winSum=422
8459 10:57:59.095588 TX Vref=30, minBit 8, minWin=25, winSum=417
8460 10:57:59.099138 TX Vref=32, minBit 12, minWin=24, winSum=408
8461 10:57:59.102275 TX Vref=34, minBit 12, minWin=23, winSum=401
8462 10:57:59.108829 TX Vref=36, minBit 11, minWin=23, winSum=390
8463 10:57:59.115720 [TxChooseVref] Worse bit 12, Min win 25, Win sum 422, Final Vref 28
8464 10:57:59.115801
8465 10:57:59.115866 Final TX Range 0 Vref 28
8466 10:57:59.115926
8467 10:57:59.115983 ==
8468 10:57:59.118863 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 10:57:59.125591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 10:57:59.125673 ==
8471 10:57:59.125737
8472 10:57:59.125795
8473 10:57:59.125852 TX Vref Scan disable
8474 10:57:59.132636 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8475 10:57:59.132717 == TX Byte 0 ==
8476 10:57:59.135985 u2DelayCellOfst[0]=16 cells (5 PI)
8477 10:57:59.139140 u2DelayCellOfst[1]=10 cells (3 PI)
8478 10:57:59.142767 u2DelayCellOfst[2]=0 cells (0 PI)
8479 10:57:59.145913 u2DelayCellOfst[3]=6 cells (2 PI)
8480 10:57:59.149373 u2DelayCellOfst[4]=6 cells (2 PI)
8481 10:57:59.152542 u2DelayCellOfst[5]=16 cells (5 PI)
8482 10:57:59.156220 u2DelayCellOfst[6]=16 cells (5 PI)
8483 10:57:59.159074 u2DelayCellOfst[7]=6 cells (2 PI)
8484 10:57:59.162090 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8485 10:57:59.165663 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8486 10:57:59.168716 == TX Byte 1 ==
8487 10:57:59.172358 u2DelayCellOfst[8]=0 cells (0 PI)
8488 10:57:59.175357 u2DelayCellOfst[9]=3 cells (1 PI)
8489 10:57:59.178614 u2DelayCellOfst[10]=10 cells (3 PI)
8490 10:57:59.182279 u2DelayCellOfst[11]=3 cells (1 PI)
8491 10:57:59.185225 u2DelayCellOfst[12]=13 cells (4 PI)
8492 10:57:59.188667 u2DelayCellOfst[13]=20 cells (6 PI)
8493 10:57:59.191922 u2DelayCellOfst[14]=20 cells (6 PI)
8494 10:57:59.192003 u2DelayCellOfst[15]=16 cells (5 PI)
8495 10:57:59.198625 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8496 10:57:59.202072 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8497 10:57:59.205345 DramC Write-DBI on
8498 10:57:59.205426 ==
8499 10:57:59.208518 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 10:57:59.211829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 10:57:59.211911 ==
8502 10:57:59.211977
8503 10:57:59.212035
8504 10:57:59.215251 TX Vref Scan disable
8505 10:57:59.215332 == TX Byte 0 ==
8506 10:57:59.221501 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8507 10:57:59.221583 == TX Byte 1 ==
8508 10:57:59.224842 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8509 10:57:59.228741 DramC Write-DBI off
8510 10:57:59.228832
8511 10:57:59.228898 [DATLAT]
8512 10:57:59.231686 Freq=1600, CH1 RK0
8513 10:57:59.231767
8514 10:57:59.231833 DATLAT Default: 0xf
8515 10:57:59.234980 0, 0xFFFF, sum = 0
8516 10:57:59.235065 1, 0xFFFF, sum = 0
8517 10:57:59.238111 2, 0xFFFF, sum = 0
8518 10:57:59.241936 3, 0xFFFF, sum = 0
8519 10:57:59.242019 4, 0xFFFF, sum = 0
8520 10:57:59.245244 5, 0xFFFF, sum = 0
8521 10:57:59.245327 6, 0xFFFF, sum = 0
8522 10:57:59.248089 7, 0xFFFF, sum = 0
8523 10:57:59.248173 8, 0xFFFF, sum = 0
8524 10:57:59.251671 9, 0xFFFF, sum = 0
8525 10:57:59.251754 10, 0xFFFF, sum = 0
8526 10:57:59.254699 11, 0xFFFF, sum = 0
8527 10:57:59.254782 12, 0xFFFF, sum = 0
8528 10:57:59.258267 13, 0xFFFF, sum = 0
8529 10:57:59.258351 14, 0x0, sum = 1
8530 10:57:59.261395 15, 0x0, sum = 2
8531 10:57:59.261479 16, 0x0, sum = 3
8532 10:57:59.264960 17, 0x0, sum = 4
8533 10:57:59.265043 best_step = 15
8534 10:57:59.265108
8535 10:57:59.265169 ==
8536 10:57:59.268140 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 10:57:59.271361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 10:57:59.274591 ==
8539 10:57:59.274673 RX Vref Scan: 1
8540 10:57:59.274739
8541 10:57:59.278546 Set Vref Range= 24 -> 127
8542 10:57:59.278628
8543 10:57:59.281448 RX Vref 24 -> 127, step: 1
8544 10:57:59.281530
8545 10:57:59.281595 RX Delay 19 -> 252, step: 4
8546 10:57:59.281655
8547 10:57:59.284698 Set Vref, RX VrefLevel [Byte0]: 24
8548 10:57:59.287970 [Byte1]: 24
8549 10:57:59.291834
8550 10:57:59.291917 Set Vref, RX VrefLevel [Byte0]: 25
8551 10:57:59.294972 [Byte1]: 25
8552 10:57:59.299151
8553 10:57:59.299233 Set Vref, RX VrefLevel [Byte0]: 26
8554 10:57:59.302573 [Byte1]: 26
8555 10:57:59.306857
8556 10:57:59.306938 Set Vref, RX VrefLevel [Byte0]: 27
8557 10:57:59.310463 [Byte1]: 27
8558 10:57:59.314604
8559 10:57:59.314687 Set Vref, RX VrefLevel [Byte0]: 28
8560 10:57:59.317508 [Byte1]: 28
8561 10:57:59.322036
8562 10:57:59.322118 Set Vref, RX VrefLevel [Byte0]: 29
8563 10:57:59.325097 [Byte1]: 29
8564 10:57:59.329645
8565 10:57:59.329727 Set Vref, RX VrefLevel [Byte0]: 30
8566 10:57:59.333105 [Byte1]: 30
8567 10:57:59.337117
8568 10:57:59.337199 Set Vref, RX VrefLevel [Byte0]: 31
8569 10:57:59.340534 [Byte1]: 31
8570 10:57:59.345221
8571 10:57:59.345304 Set Vref, RX VrefLevel [Byte0]: 32
8572 10:57:59.348167 [Byte1]: 32
8573 10:57:59.352579
8574 10:57:59.352661 Set Vref, RX VrefLevel [Byte0]: 33
8575 10:57:59.355619 [Byte1]: 33
8576 10:57:59.359826
8577 10:57:59.359908 Set Vref, RX VrefLevel [Byte0]: 34
8578 10:57:59.363424 [Byte1]: 34
8579 10:57:59.367439
8580 10:57:59.367522 Set Vref, RX VrefLevel [Byte0]: 35
8581 10:57:59.370875 [Byte1]: 35
8582 10:57:59.375087
8583 10:57:59.375169 Set Vref, RX VrefLevel [Byte0]: 36
8584 10:57:59.378531 [Byte1]: 36
8585 10:57:59.382396
8586 10:57:59.382478 Set Vref, RX VrefLevel [Byte0]: 37
8587 10:57:59.385900 [Byte1]: 37
8588 10:57:59.390531
8589 10:57:59.390613 Set Vref, RX VrefLevel [Byte0]: 38
8590 10:57:59.393706 [Byte1]: 38
8591 10:57:59.397922
8592 10:57:59.398004 Set Vref, RX VrefLevel [Byte0]: 39
8593 10:57:59.400942 [Byte1]: 39
8594 10:57:59.405249
8595 10:57:59.405331 Set Vref, RX VrefLevel [Byte0]: 40
8596 10:57:59.408787 [Byte1]: 40
8597 10:57:59.413021
8598 10:57:59.413103 Set Vref, RX VrefLevel [Byte0]: 41
8599 10:57:59.416005 [Byte1]: 41
8600 10:57:59.420301
8601 10:57:59.420383 Set Vref, RX VrefLevel [Byte0]: 42
8602 10:57:59.423914 [Byte1]: 42
8603 10:57:59.428505
8604 10:57:59.428587 Set Vref, RX VrefLevel [Byte0]: 43
8605 10:57:59.431409 [Byte1]: 43
8606 10:57:59.435663
8607 10:57:59.435745 Set Vref, RX VrefLevel [Byte0]: 44
8608 10:57:59.438741 [Byte1]: 44
8609 10:57:59.443306
8610 10:57:59.443389 Set Vref, RX VrefLevel [Byte0]: 45
8611 10:57:59.446559 [Byte1]: 45
8612 10:57:59.450816
8613 10:57:59.450898 Set Vref, RX VrefLevel [Byte0]: 46
8614 10:57:59.453942 [Byte1]: 46
8615 10:57:59.458687
8616 10:57:59.458769 Set Vref, RX VrefLevel [Byte0]: 47
8617 10:57:59.461773 [Byte1]: 47
8618 10:57:59.465855
8619 10:57:59.465937 Set Vref, RX VrefLevel [Byte0]: 48
8620 10:57:59.469305 [Byte1]: 48
8621 10:57:59.473512
8622 10:57:59.473594 Set Vref, RX VrefLevel [Byte0]: 49
8623 10:57:59.476640 [Byte1]: 49
8624 10:57:59.481167
8625 10:57:59.481253 Set Vref, RX VrefLevel [Byte0]: 50
8626 10:57:59.484230 [Byte1]: 50
8627 10:57:59.488504
8628 10:57:59.488586 Set Vref, RX VrefLevel [Byte0]: 51
8629 10:57:59.491920 [Byte1]: 51
8630 10:57:59.496477
8631 10:57:59.496558 Set Vref, RX VrefLevel [Byte0]: 52
8632 10:57:59.499329 [Byte1]: 52
8633 10:57:59.503728
8634 10:57:59.503810 Set Vref, RX VrefLevel [Byte0]: 53
8635 10:57:59.507204 [Byte1]: 53
8636 10:57:59.511187
8637 10:57:59.511268 Set Vref, RX VrefLevel [Byte0]: 54
8638 10:57:59.514418 [Byte1]: 54
8639 10:57:59.518773
8640 10:57:59.518855 Set Vref, RX VrefLevel [Byte0]: 55
8641 10:57:59.522051 [Byte1]: 55
8642 10:57:59.526395
8643 10:57:59.526477 Set Vref, RX VrefLevel [Byte0]: 56
8644 10:57:59.529893 [Byte1]: 56
8645 10:57:59.534091
8646 10:57:59.534200 Set Vref, RX VrefLevel [Byte0]: 57
8647 10:57:59.537546 [Byte1]: 57
8648 10:57:59.541599
8649 10:57:59.541682 Set Vref, RX VrefLevel [Byte0]: 58
8650 10:57:59.545254 [Byte1]: 58
8651 10:57:59.549325
8652 10:57:59.549407 Set Vref, RX VrefLevel [Byte0]: 59
8653 10:57:59.552549 [Byte1]: 59
8654 10:57:59.556887
8655 10:57:59.556970 Set Vref, RX VrefLevel [Byte0]: 60
8656 10:57:59.560044 [Byte1]: 60
8657 10:57:59.564430
8658 10:57:59.564513 Set Vref, RX VrefLevel [Byte0]: 61
8659 10:57:59.567458 [Byte1]: 61
8660 10:57:59.571891
8661 10:57:59.571974 Set Vref, RX VrefLevel [Byte0]: 62
8662 10:57:59.575250 [Byte1]: 62
8663 10:57:59.579892
8664 10:57:59.579975 Set Vref, RX VrefLevel [Byte0]: 63
8665 10:57:59.583179 [Byte1]: 63
8666 10:57:59.587069
8667 10:57:59.587152 Set Vref, RX VrefLevel [Byte0]: 64
8668 10:57:59.590361 [Byte1]: 64
8669 10:57:59.594550
8670 10:57:59.594632 Set Vref, RX VrefLevel [Byte0]: 65
8671 10:57:59.597875 [Byte1]: 65
8672 10:57:59.602003
8673 10:57:59.605512 Set Vref, RX VrefLevel [Byte0]: 66
8674 10:57:59.608664 [Byte1]: 66
8675 10:57:59.608748
8676 10:57:59.612214 Set Vref, RX VrefLevel [Byte0]: 67
8677 10:57:59.615640 [Byte1]: 67
8678 10:57:59.615754
8679 10:57:59.618775 Set Vref, RX VrefLevel [Byte0]: 68
8680 10:57:59.621951 [Byte1]: 68
8681 10:57:59.622023
8682 10:57:59.625317 Set Vref, RX VrefLevel [Byte0]: 69
8683 10:57:59.628264 [Byte1]: 69
8684 10:57:59.632576
8685 10:57:59.632675 Set Vref, RX VrefLevel [Byte0]: 70
8686 10:57:59.638846 [Byte1]: 70
8687 10:57:59.638946
8688 10:57:59.642187 Set Vref, RX VrefLevel [Byte0]: 71
8689 10:57:59.645716 [Byte1]: 71
8690 10:57:59.645813
8691 10:57:59.649069 Set Vref, RX VrefLevel [Byte0]: 72
8692 10:57:59.652136 [Byte1]: 72
8693 10:57:59.652232
8694 10:57:59.655482 Set Vref, RX VrefLevel [Byte0]: 73
8695 10:57:59.658809 [Byte1]: 73
8696 10:57:59.662874
8697 10:57:59.662969 Set Vref, RX VrefLevel [Byte0]: 74
8698 10:57:59.666045 [Byte1]: 74
8699 10:57:59.670595
8700 10:57:59.670699 Set Vref, RX VrefLevel [Byte0]: 75
8701 10:57:59.673841 [Byte1]: 75
8702 10:57:59.678017
8703 10:57:59.678112 Set Vref, RX VrefLevel [Byte0]: 76
8704 10:57:59.681159 [Byte1]: 76
8705 10:57:59.685442
8706 10:57:59.685513 Final RX Vref Byte 0 = 59 to rank0
8707 10:57:59.688892 Final RX Vref Byte 1 = 63 to rank0
8708 10:57:59.692216 Final RX Vref Byte 0 = 59 to rank1
8709 10:57:59.695295 Final RX Vref Byte 1 = 63 to rank1==
8710 10:57:59.698644 Dram Type= 6, Freq= 0, CH_1, rank 0
8711 10:57:59.704939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8712 10:57:59.705009 ==
8713 10:57:59.705088 DQS Delay:
8714 10:57:59.708520 DQS0 = 0, DQS1 = 0
8715 10:57:59.708614 DQM Delay:
8716 10:57:59.711615 DQM0 = 134, DQM1 = 130
8717 10:57:59.711709 DQ Delay:
8718 10:57:59.715011 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8719 10:57:59.718483 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8720 10:57:59.721975 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8721 10:57:59.725095 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8722 10:57:59.725167
8723 10:57:59.725229
8724 10:57:59.725287
8725 10:57:59.728183 [DramC_TX_OE_Calibration] TA2
8726 10:57:59.731435 Original DQ_B0 (3 6) =30, OEN = 27
8727 10:57:59.734680 Original DQ_B1 (3 6) =30, OEN = 27
8728 10:57:59.737975 24, 0x0, End_B0=24 End_B1=24
8729 10:57:59.741187 25, 0x0, End_B0=25 End_B1=25
8730 10:57:59.741297 26, 0x0, End_B0=26 End_B1=26
8731 10:57:59.744500 27, 0x0, End_B0=27 End_B1=27
8732 10:57:59.747783 28, 0x0, End_B0=28 End_B1=28
8733 10:57:59.750979 29, 0x0, End_B0=29 End_B1=29
8734 10:57:59.754820 30, 0x0, End_B0=30 End_B1=30
8735 10:57:59.754894 31, 0x4141, End_B0=30 End_B1=30
8736 10:57:59.757765 Byte0 end_step=30 best_step=27
8737 10:57:59.761137 Byte1 end_step=30 best_step=27
8738 10:57:59.764731 Byte0 TX OE(2T, 0.5T) = (3, 3)
8739 10:57:59.767567 Byte1 TX OE(2T, 0.5T) = (3, 3)
8740 10:57:59.767637
8741 10:57:59.767699
8742 10:57:59.774301 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8743 10:57:59.777450 CH1 RK0: MR19=303, MR18=1523
8744 10:57:59.784285 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8745 10:57:59.784390
8746 10:57:59.787519 ----->DramcWriteLeveling(PI) begin...
8747 10:57:59.787605 ==
8748 10:57:59.790605 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 10:57:59.794255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 10:57:59.794327 ==
8751 10:57:59.797629 Write leveling (Byte 0): 24 => 24
8752 10:57:59.800667 Write leveling (Byte 1): 27 => 27
8753 10:57:59.803914 DramcWriteLeveling(PI) end<-----
8754 10:57:59.803988
8755 10:57:59.804049 ==
8756 10:57:59.807187 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 10:57:59.814086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 10:57:59.814194 ==
8759 10:57:59.814285 [Gating] SW mode calibration
8760 10:57:59.823832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8761 10:57:59.827214 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8762 10:57:59.830279 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 10:57:59.837011 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 10:57:59.840145 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8765 10:57:59.846854 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8766 10:57:59.850301 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 10:57:59.853461 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 10:57:59.860006 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 10:57:59.863540 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 10:57:59.866640 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 10:57:59.873066 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 10:57:59.876492 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8773 10:57:59.879542 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8774 10:57:59.886492 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 10:57:59.889982 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 10:57:59.892728 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 10:57:59.899595 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 10:57:59.902816 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 10:57:59.906514 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8780 10:57:59.912520 1 6 8 | B1->B0 | 4545 2525 | 0 0 | (0 0) (0 0)
8781 10:57:59.916344 1 6 12 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
8782 10:57:59.919436 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 10:57:59.925907 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 10:57:59.929128 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 10:57:59.932560 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 10:57:59.939277 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 10:57:59.942501 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 10:57:59.945732 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 10:57:59.952275 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8790 10:57:59.955516 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 10:57:59.958811 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 10:57:59.965577 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 10:57:59.968588 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 10:57:59.971966 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 10:57:59.978720 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 10:57:59.981733 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 10:57:59.985076 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 10:57:59.992033 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 10:57:59.995007 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 10:57:59.998375 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:58:00.001665 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:58:00.008311 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:58:00.011798 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8804 10:58:00.015002 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8805 10:58:00.021982 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8806 10:58:00.024742 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 10:58:00.028401 Total UI for P1: 0, mck2ui 16
8808 10:58:00.031632 best dqsien dly found for B0: ( 1, 9, 8)
8809 10:58:00.034729 Total UI for P1: 0, mck2ui 16
8810 10:58:00.038244 best dqsien dly found for B1: ( 1, 9, 8)
8811 10:58:00.041257 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8812 10:58:00.044676 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8813 10:58:00.044794
8814 10:58:00.047730 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8815 10:58:00.054664 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8816 10:58:00.054759 [Gating] SW calibration Done
8817 10:58:00.054823 ==
8818 10:58:00.057778 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 10:58:00.064365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 10:58:00.064439 ==
8821 10:58:00.064508 RX Vref Scan: 0
8822 10:58:00.064567
8823 10:58:00.067538 RX Vref 0 -> 0, step: 1
8824 10:58:00.067605
8825 10:58:00.070913 RX Delay 0 -> 252, step: 8
8826 10:58:00.074251 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8827 10:58:00.077643 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8828 10:58:00.080545 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8829 10:58:00.087357 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8830 10:58:00.090625 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8831 10:58:00.093999 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8832 10:58:00.097040 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8833 10:58:00.100502 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8834 10:58:00.107643 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8835 10:58:00.110596 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8836 10:58:00.113919 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8837 10:58:00.117081 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8838 10:58:00.120302 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8839 10:58:00.127424 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8840 10:58:00.130329 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8841 10:58:00.133665 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8842 10:58:00.133738 ==
8843 10:58:00.137288 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 10:58:00.140349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 10:58:00.140447 ==
8846 10:58:00.143698 DQS Delay:
8847 10:58:00.143792 DQS0 = 0, DQS1 = 0
8848 10:58:00.146881 DQM Delay:
8849 10:58:00.146974 DQM0 = 136, DQM1 = 131
8850 10:58:00.150675 DQ Delay:
8851 10:58:00.153373 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8852 10:58:00.156888 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8853 10:58:00.160185 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8854 10:58:00.163566 DQ12 =135, DQ13 =143, DQ14 =139, DQ15 =143
8855 10:58:00.163634
8856 10:58:00.163702
8857 10:58:00.163758 ==
8858 10:58:00.166666 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 10:58:00.169762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 10:58:00.169834 ==
8861 10:58:00.173023
8862 10:58:00.173091
8863 10:58:00.173155 TX Vref Scan disable
8864 10:58:00.176690 == TX Byte 0 ==
8865 10:58:00.179872 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8866 10:58:00.183254 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8867 10:58:00.186263 == TX Byte 1 ==
8868 10:58:00.189674 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8869 10:58:00.192762 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8870 10:58:00.192869 ==
8871 10:58:00.196228 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 10:58:00.202991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 10:58:00.203061 ==
8874 10:58:00.215792
8875 10:58:00.219325 TX Vref early break, caculate TX vref
8876 10:58:00.222597 TX Vref=16, minBit 9, minWin=22, winSum=386
8877 10:58:00.225488 TX Vref=18, minBit 10, minWin=23, winSum=389
8878 10:58:00.228927 TX Vref=20, minBit 8, minWin=24, winSum=403
8879 10:58:00.232425 TX Vref=22, minBit 10, minWin=23, winSum=405
8880 10:58:00.238850 TX Vref=24, minBit 9, minWin=25, winSum=418
8881 10:58:00.242171 TX Vref=26, minBit 8, minWin=25, winSum=425
8882 10:58:00.245331 TX Vref=28, minBit 10, minWin=25, winSum=425
8883 10:58:00.248572 TX Vref=30, minBit 12, minWin=25, winSum=420
8884 10:58:00.252011 TX Vref=32, minBit 10, minWin=24, winSum=413
8885 10:58:00.255626 TX Vref=34, minBit 0, minWin=24, winSum=405
8886 10:58:00.261862 TX Vref=36, minBit 9, minWin=23, winSum=391
8887 10:58:00.265315 [TxChooseVref] Worse bit 8, Min win 25, Win sum 425, Final Vref 26
8888 10:58:00.265390
8889 10:58:00.268658 Final TX Range 0 Vref 26
8890 10:58:00.268759
8891 10:58:00.268861 ==
8892 10:58:00.271767 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 10:58:00.278321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 10:58:00.278407 ==
8895 10:58:00.278491
8896 10:58:00.278568
8897 10:58:00.278644 TX Vref Scan disable
8898 10:58:00.285349 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8899 10:58:00.285433 == TX Byte 0 ==
8900 10:58:00.288692 u2DelayCellOfst[0]=13 cells (4 PI)
8901 10:58:00.291779 u2DelayCellOfst[1]=10 cells (3 PI)
8902 10:58:00.295065 u2DelayCellOfst[2]=0 cells (0 PI)
8903 10:58:00.298746 u2DelayCellOfst[3]=3 cells (1 PI)
8904 10:58:00.301721 u2DelayCellOfst[4]=6 cells (2 PI)
8905 10:58:00.305257 u2DelayCellOfst[5]=16 cells (5 PI)
8906 10:58:00.308667 u2DelayCellOfst[6]=16 cells (5 PI)
8907 10:58:00.311918 u2DelayCellOfst[7]=3 cells (1 PI)
8908 10:58:00.315013 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8909 10:58:00.318392 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8910 10:58:00.321787 == TX Byte 1 ==
8911 10:58:00.324905 u2DelayCellOfst[8]=0 cells (0 PI)
8912 10:58:00.328252 u2DelayCellOfst[9]=3 cells (1 PI)
8913 10:58:00.331576 u2DelayCellOfst[10]=6 cells (2 PI)
8914 10:58:00.334802 u2DelayCellOfst[11]=3 cells (1 PI)
8915 10:58:00.338005 u2DelayCellOfst[12]=13 cells (4 PI)
8916 10:58:00.338087 u2DelayCellOfst[13]=16 cells (5 PI)
8917 10:58:00.341384 u2DelayCellOfst[14]=16 cells (5 PI)
8918 10:58:00.344812 u2DelayCellOfst[15]=16 cells (5 PI)
8919 10:58:00.351654 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8920 10:58:00.354692 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8921 10:58:00.354775 DramC Write-DBI on
8922 10:58:00.358129 ==
8923 10:58:00.361388 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 10:58:00.364368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 10:58:00.364451 ==
8926 10:58:00.364517
8927 10:58:00.364577
8928 10:58:00.367844 TX Vref Scan disable
8929 10:58:00.367926 == TX Byte 0 ==
8930 10:58:00.374610 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8931 10:58:00.374693 == TX Byte 1 ==
8932 10:58:00.377692 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8933 10:58:00.381168 DramC Write-DBI off
8934 10:58:00.381250
8935 10:58:00.381315 [DATLAT]
8936 10:58:00.384179 Freq=1600, CH1 RK1
8937 10:58:00.384261
8938 10:58:00.384326 DATLAT Default: 0xf
8939 10:58:00.387636 0, 0xFFFF, sum = 0
8940 10:58:00.387720 1, 0xFFFF, sum = 0
8941 10:58:00.391205 2, 0xFFFF, sum = 0
8942 10:58:00.391288 3, 0xFFFF, sum = 0
8943 10:58:00.394150 4, 0xFFFF, sum = 0
8944 10:58:00.397415 5, 0xFFFF, sum = 0
8945 10:58:00.397498 6, 0xFFFF, sum = 0
8946 10:58:00.401123 7, 0xFFFF, sum = 0
8947 10:58:00.401207 8, 0xFFFF, sum = 0
8948 10:58:00.404256 9, 0xFFFF, sum = 0
8949 10:58:00.404339 10, 0xFFFF, sum = 0
8950 10:58:00.407870 11, 0xFFFF, sum = 0
8951 10:58:00.407953 12, 0xFFFF, sum = 0
8952 10:58:00.410722 13, 0xFFFF, sum = 0
8953 10:58:00.410805 14, 0x0, sum = 1
8954 10:58:00.414098 15, 0x0, sum = 2
8955 10:58:00.414181 16, 0x0, sum = 3
8956 10:58:00.417439 17, 0x0, sum = 4
8957 10:58:00.417522 best_step = 15
8958 10:58:00.417587
8959 10:58:00.417648 ==
8960 10:58:00.420605 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 10:58:00.423988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 10:58:00.427370 ==
8963 10:58:00.427473 RX Vref Scan: 0
8964 10:58:00.427554
8965 10:58:00.430737 RX Vref 0 -> 0, step: 1
8966 10:58:00.430819
8967 10:58:00.430921 RX Delay 19 -> 252, step: 4
8968 10:58:00.437973 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8969 10:58:00.441391 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8970 10:58:00.444950 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8971 10:58:00.447846 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8972 10:58:00.451405 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8973 10:58:00.457839 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8974 10:58:00.461175 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8975 10:58:00.464224 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8976 10:58:00.467723 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8977 10:58:00.471760 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8978 10:58:00.477676 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8979 10:58:00.480962 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8980 10:58:00.484286 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8981 10:58:00.487707 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8982 10:58:00.490783 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8983 10:58:00.497494 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8984 10:58:00.497577 ==
8985 10:58:00.500692 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 10:58:00.504012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 10:58:00.504094 ==
8988 10:58:00.504159 DQS Delay:
8989 10:58:00.507563 DQS0 = 0, DQS1 = 0
8990 10:58:00.507645 DQM Delay:
8991 10:58:00.510690 DQM0 = 133, DQM1 = 130
8992 10:58:00.510771 DQ Delay:
8993 10:58:00.513824 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8994 10:58:00.517323 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
8995 10:58:00.520524 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8996 10:58:00.527269 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8997 10:58:00.527351
8998 10:58:00.527418
8999 10:58:00.527478
9000 10:58:00.527535 [DramC_TX_OE_Calibration] TA2
9001 10:58:00.530433 Original DQ_B0 (3 6) =30, OEN = 27
9002 10:58:00.533991 Original DQ_B1 (3 6) =30, OEN = 27
9003 10:58:00.536853 24, 0x0, End_B0=24 End_B1=24
9004 10:58:00.540438 25, 0x0, End_B0=25 End_B1=25
9005 10:58:00.543817 26, 0x0, End_B0=26 End_B1=26
9006 10:58:00.543901 27, 0x0, End_B0=27 End_B1=27
9007 10:58:00.546752 28, 0x0, End_B0=28 End_B1=28
9008 10:58:00.550274 29, 0x0, End_B0=29 End_B1=29
9009 10:58:00.553748 30, 0x0, End_B0=30 End_B1=30
9010 10:58:00.556740 31, 0x4141, End_B0=30 End_B1=30
9011 10:58:00.560297 Byte0 end_step=30 best_step=27
9012 10:58:00.560382 Byte1 end_step=30 best_step=27
9013 10:58:00.563269 Byte0 TX OE(2T, 0.5T) = (3, 3)
9014 10:58:00.566869 Byte1 TX OE(2T, 0.5T) = (3, 3)
9015 10:58:00.566954
9016 10:58:00.567037
9017 10:58:00.576584 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a04, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
9018 10:58:00.576670 CH1 RK1: MR19=303, MR18=1A04
9019 10:58:00.583127 CH1_RK1: MR19=0x303, MR18=0x1A04, DQSOSC=396, MR23=63, INC=23, DEC=15
9020 10:58:00.586509 [RxdqsGatingPostProcess] freq 1600
9021 10:58:00.593188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9022 10:58:00.596440 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 10:58:00.599539 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 10:58:00.603045 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 10:58:00.606304 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 10:58:00.609915 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 10:58:00.610000 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 10:58:00.612809 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 10:58:00.616477 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 10:58:00.619522 Pre-setting of DQS Precalculation
9031 10:58:00.626372 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9032 10:58:00.632627 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9033 10:58:00.639603 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9034 10:58:00.639689
9035 10:58:00.639773
9036 10:58:00.642663 [Calibration Summary] 3200 Mbps
9037 10:58:00.642747 CH 0, Rank 0
9038 10:58:00.646373 SW Impedance : PASS
9039 10:58:00.649459 DUTY Scan : NO K
9040 10:58:00.649543 ZQ Calibration : PASS
9041 10:58:00.652514 Jitter Meter : NO K
9042 10:58:00.655944 CBT Training : PASS
9043 10:58:00.656029 Write leveling : PASS
9044 10:58:00.659069 RX DQS gating : PASS
9045 10:58:00.662412 RX DQ/DQS(RDDQC) : PASS
9046 10:58:00.662496 TX DQ/DQS : PASS
9047 10:58:00.665899 RX DATLAT : PASS
9048 10:58:00.669027 RX DQ/DQS(Engine): PASS
9049 10:58:00.669111 TX OE : PASS
9050 10:58:00.672281 All Pass.
9051 10:58:00.672365
9052 10:58:00.672449 CH 0, Rank 1
9053 10:58:00.675669 SW Impedance : PASS
9054 10:58:00.675753 DUTY Scan : NO K
9055 10:58:00.679280 ZQ Calibration : PASS
9056 10:58:00.682461 Jitter Meter : NO K
9057 10:58:00.682545 CBT Training : PASS
9058 10:58:00.685858 Write leveling : PASS
9059 10:58:00.688756 RX DQS gating : PASS
9060 10:58:00.688847 RX DQ/DQS(RDDQC) : PASS
9061 10:58:00.692043 TX DQ/DQS : PASS
9062 10:58:00.695606 RX DATLAT : PASS
9063 10:58:00.695690 RX DQ/DQS(Engine): PASS
9064 10:58:00.698779 TX OE : PASS
9065 10:58:00.698862 All Pass.
9066 10:58:00.698928
9067 10:58:00.702198 CH 1, Rank 0
9068 10:58:00.702281 SW Impedance : PASS
9069 10:58:00.705528 DUTY Scan : NO K
9070 10:58:00.705611 ZQ Calibration : PASS
9071 10:58:00.708806 Jitter Meter : NO K
9072 10:58:00.712301 CBT Training : PASS
9073 10:58:00.712394 Write leveling : PASS
9074 10:58:00.715331 RX DQS gating : PASS
9075 10:58:00.718593 RX DQ/DQS(RDDQC) : PASS
9076 10:58:00.718675 TX DQ/DQS : PASS
9077 10:58:00.722051 RX DATLAT : PASS
9078 10:58:00.725260 RX DQ/DQS(Engine): PASS
9079 10:58:00.725342 TX OE : PASS
9080 10:58:00.728698 All Pass.
9081 10:58:00.728817
9082 10:58:00.728883 CH 1, Rank 1
9083 10:58:00.731780 SW Impedance : PASS
9084 10:58:00.731863 DUTY Scan : NO K
9085 10:58:00.735091 ZQ Calibration : PASS
9086 10:58:00.738501 Jitter Meter : NO K
9087 10:58:00.738584 CBT Training : PASS
9088 10:58:00.741867 Write leveling : PASS
9089 10:58:00.745295 RX DQS gating : PASS
9090 10:58:00.745378 RX DQ/DQS(RDDQC) : PASS
9091 10:58:00.748727 TX DQ/DQS : PASS
9092 10:58:00.751843 RX DATLAT : PASS
9093 10:58:00.751926 RX DQ/DQS(Engine): PASS
9094 10:58:00.755245 TX OE : PASS
9095 10:58:00.755329 All Pass.
9096 10:58:00.755394
9097 10:58:00.758437 DramC Write-DBI on
9098 10:58:00.762160 PER_BANK_REFRESH: Hybrid Mode
9099 10:58:00.762244 TX_TRACKING: ON
9100 10:58:00.771765 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9101 10:58:00.778130 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9102 10:58:00.784746 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 10:58:00.788349 [FAST_K] Save calibration result to emmc
9104 10:58:00.791550 sync common calibartion params.
9105 10:58:00.794647 sync cbt_mode0:1, 1:1
9106 10:58:00.797986 dram_init: ddr_geometry: 2
9107 10:58:00.798069 dram_init: ddr_geometry: 2
9108 10:58:00.801112 dram_init: ddr_geometry: 2
9109 10:58:00.804562 0:dram_rank_size:100000000
9110 10:58:00.808077 1:dram_rank_size:100000000
9111 10:58:00.811241 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9112 10:58:00.814516 DFS_SHUFFLE_HW_MODE: ON
9113 10:58:00.817782 dramc_set_vcore_voltage set vcore to 725000
9114 10:58:00.821058 Read voltage for 1600, 0
9115 10:58:00.821140 Vio18 = 0
9116 10:58:00.821206 Vcore = 725000
9117 10:58:00.824230 Vdram = 0
9118 10:58:00.824313 Vddq = 0
9119 10:58:00.824380 Vmddr = 0
9120 10:58:00.827351 switch to 3200 Mbps bootup
9121 10:58:00.830790 [DramcRunTimeConfig]
9122 10:58:00.830873 PHYPLL
9123 10:58:00.830939 DPM_CONTROL_AFTERK: ON
9124 10:58:00.834067 PER_BANK_REFRESH: ON
9125 10:58:00.837218 REFRESH_OVERHEAD_REDUCTION: ON
9126 10:58:00.837302 CMD_PICG_NEW_MODE: OFF
9127 10:58:00.840760 XRTWTW_NEW_MODE: ON
9128 10:58:00.843777 XRTRTR_NEW_MODE: ON
9129 10:58:00.843860 TX_TRACKING: ON
9130 10:58:00.847132 RDSEL_TRACKING: OFF
9131 10:58:00.847215 DQS Precalculation for DVFS: ON
9132 10:58:00.850543 RX_TRACKING: OFF
9133 10:58:00.850631 HW_GATING DBG: ON
9134 10:58:00.853795 ZQCS_ENABLE_LP4: ON
9135 10:58:00.857570 RX_PICG_NEW_MODE: ON
9136 10:58:00.857653 TX_PICG_NEW_MODE: ON
9137 10:58:00.860423 ENABLE_RX_DCM_DPHY: ON
9138 10:58:00.863747 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9139 10:58:00.863830 DUMMY_READ_FOR_TRACKING: OFF
9140 10:58:00.866956 !!! SPM_CONTROL_AFTERK: OFF
9141 10:58:00.870391 !!! SPM could not control APHY
9142 10:58:00.873707 IMPEDANCE_TRACKING: ON
9143 10:58:00.873789 TEMP_SENSOR: ON
9144 10:58:00.876729 HW_SAVE_FOR_SR: OFF
9145 10:58:00.880090 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9146 10:58:00.883692 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9147 10:58:00.883775 Read ODT Tracking: ON
9148 10:58:00.886816 Refresh Rate DeBounce: ON
9149 10:58:00.890457 DFS_NO_QUEUE_FLUSH: ON
9150 10:58:00.893266 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9151 10:58:00.893349 ENABLE_DFS_RUNTIME_MRW: OFF
9152 10:58:00.896630 DDR_RESERVE_NEW_MODE: ON
9153 10:58:00.899819 MR_CBT_SWITCH_FREQ: ON
9154 10:58:00.899902 =========================
9155 10:58:00.919937 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9156 10:58:00.923159 dram_init: ddr_geometry: 2
9157 10:58:00.941600 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9158 10:58:00.944906 dram_init: dram init end (result: 0)
9159 10:58:00.951404 DRAM-K: Full calibration passed in 24515 msecs
9160 10:58:00.954671 MRC: failed to locate region type 0.
9161 10:58:00.954754 DRAM rank0 size:0x100000000,
9162 10:58:00.958311 DRAM rank1 size=0x100000000
9163 10:58:00.967868 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9164 10:58:00.974629 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9165 10:58:00.981185 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9166 10:58:00.991082 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9167 10:58:00.991166 DRAM rank0 size:0x100000000,
9168 10:58:00.994472 DRAM rank1 size=0x100000000
9169 10:58:00.994555 CBMEM:
9170 10:58:00.997856 IMD: root @ 0xfffff000 254 entries.
9171 10:58:01.001131 IMD: root @ 0xffffec00 62 entries.
9172 10:58:01.004417 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9173 10:58:01.010943 WARNING: RO_VPD is uninitialized or empty.
9174 10:58:01.014136 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9175 10:58:01.022001 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9176 10:58:01.034381 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9177 10:58:01.045830 BS: romstage times (exec / console): total (unknown) / 24013 ms
9178 10:58:01.045914
9179 10:58:01.045981
9180 10:58:01.055747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9181 10:58:01.059020 ARM64: Exception handlers installed.
9182 10:58:01.062184 ARM64: Testing exception
9183 10:58:01.065621 ARM64: Done test exception
9184 10:58:01.065704 Enumerating buses...
9185 10:58:01.068904 Show all devs... Before device enumeration.
9186 10:58:01.072257 Root Device: enabled 1
9187 10:58:01.075565 CPU_CLUSTER: 0: enabled 1
9188 10:58:01.075648 CPU: 00: enabled 1
9189 10:58:01.078704 Compare with tree...
9190 10:58:01.078787 Root Device: enabled 1
9191 10:58:01.082218 CPU_CLUSTER: 0: enabled 1
9192 10:58:01.085100 CPU: 00: enabled 1
9193 10:58:01.085182 Root Device scanning...
9194 10:58:01.088693 scan_static_bus for Root Device
9195 10:58:01.091735 CPU_CLUSTER: 0 enabled
9196 10:58:01.095060 scan_static_bus for Root Device done
9197 10:58:01.098778 scan_bus: bus Root Device finished in 8 msecs
9198 10:58:01.098862 done
9199 10:58:01.105033 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9200 10:58:01.108253 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9201 10:58:01.115058 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9202 10:58:01.121514 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9203 10:58:01.121597 Allocating resources...
9204 10:58:01.125434 Reading resources...
9205 10:58:01.128587 Root Device read_resources bus 0 link: 0
9206 10:58:01.131566 DRAM rank0 size:0x100000000,
9207 10:58:01.131648 DRAM rank1 size=0x100000000
9208 10:58:01.138004 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9209 10:58:01.138129 CPU: 00 missing read_resources
9210 10:58:01.144373 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9211 10:58:01.147764 Root Device read_resources bus 0 link: 0 done
9212 10:58:01.151285 Done reading resources.
9213 10:58:01.154775 Show resources in subtree (Root Device)...After reading.
9214 10:58:01.157817 Root Device child on link 0 CPU_CLUSTER: 0
9215 10:58:01.161263 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 10:58:01.171193 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 10:58:01.171277 CPU: 00
9218 10:58:01.177555 Root Device assign_resources, bus 0 link: 0
9219 10:58:01.180783 CPU_CLUSTER: 0 missing set_resources
9220 10:58:01.184144 Root Device assign_resources, bus 0 link: 0 done
9221 10:58:01.184226 Done setting resources.
9222 10:58:01.190848 Show resources in subtree (Root Device)...After assigning values.
9223 10:58:01.194012 Root Device child on link 0 CPU_CLUSTER: 0
9224 10:58:01.200682 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 10:58:01.207507 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 10:58:01.207591 CPU: 00
9227 10:58:01.210726 Done allocating resources.
9228 10:58:01.217372 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9229 10:58:01.217456 Enabling resources...
9230 10:58:01.220596 done.
9231 10:58:01.224059 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9232 10:58:01.227192 Initializing devices...
9233 10:58:01.227275 Root Device init
9234 10:58:01.230722 init hardware done!
9235 10:58:01.230805 0x00000018: ctrlr->caps
9236 10:58:01.233967 52.000 MHz: ctrlr->f_max
9237 10:58:01.237453 0.400 MHz: ctrlr->f_min
9238 10:58:01.237556 0x40ff8080: ctrlr->voltages
9239 10:58:01.240359 sclk: 390625
9240 10:58:01.240442 Bus Width = 1
9241 10:58:01.243680 sclk: 390625
9242 10:58:01.243763 Bus Width = 1
9243 10:58:01.247327 Early init status = 3
9244 10:58:01.250180 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9245 10:58:01.254048 in-header: 03 fc 00 00 01 00 00 00
9246 10:58:01.257698 in-data: 00
9247 10:58:01.260822 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9248 10:58:01.266772 in-header: 03 fd 00 00 00 00 00 00
9249 10:58:01.270057 in-data:
9250 10:58:01.272945 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9251 10:58:01.277471 in-header: 03 fc 00 00 01 00 00 00
9252 10:58:01.280984 in-data: 00
9253 10:58:01.283901 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9254 10:58:01.289773 in-header: 03 fd 00 00 00 00 00 00
9255 10:58:01.293325 in-data:
9256 10:58:01.296819 [SSUSB] Setting up USB HOST controller...
9257 10:58:01.299913 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9258 10:58:01.303195 [SSUSB] phy power-on done.
9259 10:58:01.306577 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9260 10:58:01.313294 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9261 10:58:01.316446 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9262 10:58:01.323088 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9263 10:58:01.329495 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9264 10:58:01.336129 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9265 10:58:01.343044 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9266 10:58:01.349715 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9267 10:58:01.352623 SPM: binary array size = 0x9dc
9268 10:58:01.355964 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9269 10:58:01.362640 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9270 10:58:01.369471 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9271 10:58:01.376290 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9272 10:58:01.379312 configure_display: Starting display init
9273 10:58:01.412953 anx7625_power_on_init: Init interface.
9274 10:58:01.416453 anx7625_disable_pd_protocol: Disabled PD feature.
9275 10:58:01.419754 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9276 10:58:01.448029 anx7625_start_dp_work: Secure OCM version=00
9277 10:58:01.450689 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9278 10:58:01.465606 sp_tx_get_edid_block: EDID Block = 1
9279 10:58:01.568284 Extracted contents:
9280 10:58:01.571432 header: 00 ff ff ff ff ff ff 00
9281 10:58:01.574920 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9282 10:58:01.577948 version: 01 04
9283 10:58:01.581292 basic params: 95 1f 11 78 0a
9284 10:58:01.584792 chroma info: 76 90 94 55 54 90 27 21 50 54
9285 10:58:01.587828 established: 00 00 00
9286 10:58:01.594640 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9287 10:58:01.597690 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9288 10:58:01.604312 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9289 10:58:01.611367 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9290 10:58:01.617561 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9291 10:58:01.620914 extensions: 00
9292 10:58:01.620995 checksum: fb
9293 10:58:01.621060
9294 10:58:01.624208 Manufacturer: IVO Model 57d Serial Number 0
9295 10:58:01.627491 Made week 0 of 2020
9296 10:58:01.630885 EDID version: 1.4
9297 10:58:01.630966 Digital display
9298 10:58:01.634338 6 bits per primary color channel
9299 10:58:01.634419 DisplayPort interface
9300 10:58:01.637365 Maximum image size: 31 cm x 17 cm
9301 10:58:01.640932 Gamma: 220%
9302 10:58:01.641012 Check DPMS levels
9303 10:58:01.644162 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9304 10:58:01.651124 First detailed timing is preferred timing
9305 10:58:01.651204 Established timings supported:
9306 10:58:01.654035 Standard timings supported:
9307 10:58:01.657445 Detailed timings
9308 10:58:01.660682 Hex of detail: 383680a07038204018303c0035ae10000019
9309 10:58:01.667693 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9310 10:58:01.670656 0780 0798 07c8 0820 hborder 0
9311 10:58:01.673856 0438 043b 0447 0458 vborder 0
9312 10:58:01.677225 -hsync -vsync
9313 10:58:01.677304 Did detailed timing
9314 10:58:01.684126 Hex of detail: 000000000000000000000000000000000000
9315 10:58:01.686985 Manufacturer-specified data, tag 0
9316 10:58:01.690601 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9317 10:58:01.693744 ASCII string: InfoVision
9318 10:58:01.697194 Hex of detail: 000000fe00523134304e574635205248200a
9319 10:58:01.700667 ASCII string: R140NWF5 RH
9320 10:58:01.700776 Checksum
9321 10:58:01.703616 Checksum: 0xfb (valid)
9322 10:58:01.707008 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9323 10:58:01.710234 DSI data_rate: 832800000 bps
9324 10:58:01.716819 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9325 10:58:01.720363 anx7625_parse_edid: pixelclock(138800).
9326 10:58:01.723376 hactive(1920), hsync(48), hfp(24), hbp(88)
9327 10:58:01.726650 vactive(1080), vsync(12), vfp(3), vbp(17)
9328 10:58:01.730169 anx7625_dsi_config: config dsi.
9329 10:58:01.736423 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9330 10:58:01.750039 anx7625_dsi_config: success to config DSI
9331 10:58:01.753653 anx7625_dp_start: MIPI phy setup OK.
9332 10:58:01.756706 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9333 10:58:01.760023 mtk_ddp_mode_set invalid vrefresh 60
9334 10:58:01.763216 main_disp_path_setup
9335 10:58:01.763367 ovl_layer_smi_id_en
9336 10:58:01.766783 ovl_layer_smi_id_en
9337 10:58:01.766956 ccorr_config
9338 10:58:01.767095 aal_config
9339 10:58:01.769880 gamma_config
9340 10:58:01.770047 postmask_config
9341 10:58:01.773148 dither_config
9342 10:58:01.776482 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9343 10:58:01.783136 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9344 10:58:01.786755 Root Device init finished in 555 msecs
9345 10:58:01.789789 CPU_CLUSTER: 0 init
9346 10:58:01.796173 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9347 10:58:01.802843 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9348 10:58:01.802928 APU_MBOX 0x190000b0 = 0x10001
9349 10:58:01.805970 APU_MBOX 0x190001b0 = 0x10001
9350 10:58:01.809785 APU_MBOX 0x190005b0 = 0x10001
9351 10:58:01.813059 APU_MBOX 0x190006b0 = 0x10001
9352 10:58:01.819488 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9353 10:58:01.829252 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9354 10:58:01.841966 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9355 10:58:01.848500 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9356 10:58:01.860485 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9357 10:58:01.869518 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9358 10:58:01.873056 CPU_CLUSTER: 0 init finished in 81 msecs
9359 10:58:01.876479 Devices initialized
9360 10:58:01.879653 Show all devs... After init.
9361 10:58:01.880228 Root Device: enabled 1
9362 10:58:01.882549 CPU_CLUSTER: 0: enabled 1
9363 10:58:01.886399 CPU: 00: enabled 1
9364 10:58:01.889469 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9365 10:58:01.892815 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9366 10:58:01.895691 ELOG: NV offset 0x57f000 size 0x1000
9367 10:58:01.902533 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9368 10:58:01.908999 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9369 10:58:01.912757 ELOG: Event(17) added with size 13 at 2023-06-05 10:57:59 UTC
9370 10:58:01.919029 out: cmd=0x121: 03 db 21 01 00 00 00 00
9371 10:58:01.922393 in-header: 03 1b 00 00 2c 00 00 00
9372 10:58:01.932142 in-data: 44 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 10:58:01.938650 ELOG: Event(A1) added with size 10 at 2023-06-05 10:57:59 UTC
9374 10:58:01.945415 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9375 10:58:01.951885 ELOG: Event(A0) added with size 9 at 2023-06-05 10:57:59 UTC
9376 10:58:01.955737 elog_add_boot_reason: Logged dev mode boot
9377 10:58:01.961921 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9378 10:58:01.962486 Finalize devices...
9379 10:58:01.965602 Devices finalized
9380 10:58:01.968695 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9381 10:58:01.971689 Writing coreboot table at 0xffe64000
9382 10:58:01.974873 0. 000000000010a000-0000000000113fff: RAMSTAGE
9383 10:58:01.981621 1. 0000000040000000-00000000400fffff: RAM
9384 10:58:01.984933 2. 0000000040100000-000000004032afff: RAMSTAGE
9385 10:58:01.988225 3. 000000004032b000-00000000545fffff: RAM
9386 10:58:01.991921 4. 0000000054600000-000000005465ffff: BL31
9387 10:58:01.994891 5. 0000000054660000-00000000ffe63fff: RAM
9388 10:58:02.001532 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9389 10:58:02.004473 7. 0000000100000000-000000023fffffff: RAM
9390 10:58:02.008515 Passing 5 GPIOs to payload:
9391 10:58:02.011290 NAME | PORT | POLARITY | VALUE
9392 10:58:02.017661 EC in RW | 0x000000aa | low | undefined
9393 10:58:02.021029 EC interrupt | 0x00000005 | low | undefined
9394 10:58:02.027659 TPM interrupt | 0x000000ab | high | undefined
9395 10:58:02.031318 SD card detect | 0x00000011 | high | undefined
9396 10:58:02.034522 speaker enable | 0x00000093 | high | undefined
9397 10:58:02.037763 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9398 10:58:02.040968 in-header: 03 f9 00 00 02 00 00 00
9399 10:58:02.044092 in-data: 02 00
9400 10:58:02.047434 ADC[4]: Raw value=901032 ID=7
9401 10:58:02.051301 ADC[3]: Raw value=213179 ID=1
9402 10:58:02.051875 RAM Code: 0x71
9403 10:58:02.054454 ADC[6]: Raw value=74502 ID=0
9404 10:58:02.057631 ADC[5]: Raw value=212072 ID=1
9405 10:58:02.058193 SKU Code: 0x1
9406 10:58:02.064759 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9407 10:58:02.065371 coreboot table: 964 bytes.
9408 10:58:02.067762 IMD ROOT 0. 0xfffff000 0x00001000
9409 10:58:02.070607 IMD SMALL 1. 0xffffe000 0x00001000
9410 10:58:02.074435 RO MCACHE 2. 0xffffc000 0x00001104
9411 10:58:02.077524 CONSOLE 3. 0xfff7c000 0x00080000
9412 10:58:02.081377 FMAP 4. 0xfff7b000 0x00000452
9413 10:58:02.084238 TIME STAMP 5. 0xfff7a000 0x00000910
9414 10:58:02.087348 VBOOT WORK 6. 0xfff66000 0x00014000
9415 10:58:02.090983 RAMOOPS 7. 0xffe66000 0x00100000
9416 10:58:02.093854 COREBOOT 8. 0xffe64000 0x00002000
9417 10:58:02.097565 IMD small region:
9418 10:58:02.100486 IMD ROOT 0. 0xffffec00 0x00000400
9419 10:58:02.104389 VPD 1. 0xffffeba0 0x0000004c
9420 10:58:02.107188 MMC STATUS 2. 0xffffeb80 0x00000004
9421 10:58:02.110357 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9422 10:58:02.113826 Probing TPM: done!
9423 10:58:02.117418 Connected to device vid:did:rid of 1ae0:0028:00
9424 10:58:02.128325 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9425 10:58:02.131664 Initialized TPM device CR50 revision 0
9426 10:58:02.135454 Checking cr50 for pending updates
9427 10:58:02.138897 Reading cr50 TPM mode
9428 10:58:02.147677 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9429 10:58:02.154101 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9430 10:58:02.194341 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9431 10:58:02.197978 Checking segment from ROM address 0x40100000
9432 10:58:02.201242 Checking segment from ROM address 0x4010001c
9433 10:58:02.208012 Loading segment from ROM address 0x40100000
9434 10:58:02.208588 code (compression=0)
9435 10:58:02.217663 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9436 10:58:02.224124 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9437 10:58:02.224700 it's not compressed!
9438 10:58:02.230880 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9439 10:58:02.237459 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9440 10:58:02.254971 Loading segment from ROM address 0x4010001c
9441 10:58:02.255530 Entry Point 0x80000000
9442 10:58:02.258417 Loaded segments
9443 10:58:02.261455 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9444 10:58:02.268315 Jumping to boot code at 0x80000000(0xffe64000)
9445 10:58:02.274826 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9446 10:58:02.281429 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9447 10:58:02.289552 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9448 10:58:02.292543 Checking segment from ROM address 0x40100000
9449 10:58:02.296279 Checking segment from ROM address 0x4010001c
9450 10:58:02.302624 Loading segment from ROM address 0x40100000
9451 10:58:02.303194 code (compression=1)
9452 10:58:02.309516 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9453 10:58:02.319266 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9454 10:58:02.319841 using LZMA
9455 10:58:02.328017 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9456 10:58:02.334006 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9457 10:58:02.337357 Loading segment from ROM address 0x4010001c
9458 10:58:02.337826 Entry Point 0x54601000
9459 10:58:02.340748 Loaded segments
9460 10:58:02.344174 NOTICE: MT8192 bl31_setup
9461 10:58:02.351144 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9462 10:58:02.354528 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9463 10:58:02.358134 WARNING: region 0:
9464 10:58:02.361158 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 10:58:02.361629 WARNING: region 1:
9466 10:58:02.368181 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9467 10:58:02.371272 WARNING: region 2:
9468 10:58:02.374290 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9469 10:58:02.378094 WARNING: region 3:
9470 10:58:02.381609 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 10:58:02.384487 WARNING: region 4:
9472 10:58:02.391592 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 10:58:02.392183 WARNING: region 5:
9474 10:58:02.394843 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 10:58:02.397808 WARNING: region 6:
9476 10:58:02.401475 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 10:58:02.404665 WARNING: region 7:
9478 10:58:02.407836 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 10:58:02.414704 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9480 10:58:02.417783 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9481 10:58:02.421202 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9482 10:58:02.428035 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9483 10:58:02.431141 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9484 10:58:02.434073 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9485 10:58:02.440919 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9486 10:58:02.444123 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9487 10:58:02.450813 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9488 10:58:02.454379 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9489 10:58:02.457418 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9490 10:58:02.464077 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9491 10:58:02.468152 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9492 10:58:02.471322 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9493 10:58:02.478207 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9494 10:58:02.481543 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9495 10:58:02.487670 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9496 10:58:02.491272 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9497 10:58:02.494578 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9498 10:58:02.501521 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9499 10:58:02.504549 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9500 10:58:02.507950 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9501 10:58:02.514335 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9502 10:58:02.518039 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9503 10:58:02.524697 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9504 10:58:02.527847 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9505 10:58:02.530704 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9506 10:58:02.537380 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9507 10:58:02.540690 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9508 10:58:02.547610 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9509 10:58:02.550738 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9510 10:58:02.554203 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9511 10:58:02.560518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9512 10:58:02.564102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9513 10:58:02.567395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9514 10:58:02.570830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9515 10:58:02.577401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9516 10:58:02.581088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9517 10:58:02.584221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9518 10:58:02.587666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9519 10:58:02.594061 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9520 10:58:02.597583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9521 10:58:02.601039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9522 10:58:02.603822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9523 10:58:02.610673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9524 10:58:02.613894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9525 10:58:02.617388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9526 10:58:02.623899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9527 10:58:02.627316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9528 10:58:02.630609 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9529 10:58:02.637379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9530 10:58:02.640376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9531 10:58:02.647406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9532 10:58:02.650049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9533 10:58:02.657176 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9534 10:58:02.660320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9535 10:58:02.663590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9536 10:58:02.670077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9537 10:58:02.673595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9538 10:58:02.680181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9539 10:58:02.683829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9540 10:58:02.690557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9541 10:58:02.693371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9542 10:58:02.700448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9543 10:58:02.703372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9544 10:58:02.706756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9545 10:58:02.713357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9546 10:58:02.716881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9547 10:58:02.723428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9548 10:58:02.726315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9549 10:58:02.733323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9550 10:58:02.736431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9551 10:58:02.739976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9552 10:58:02.746559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9553 10:58:02.749732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9554 10:58:02.756073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9555 10:58:02.759329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9556 10:58:02.766192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9557 10:58:02.769669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9558 10:58:02.776528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9559 10:58:02.779762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9560 10:58:02.782560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9561 10:58:02.789739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9562 10:58:02.792990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9563 10:58:02.799604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9564 10:58:02.803042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9565 10:58:02.809678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9566 10:58:02.812922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9567 10:58:02.816297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9568 10:58:02.822827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9569 10:58:02.826334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9570 10:58:02.832926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9571 10:58:02.836533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9572 10:58:02.842641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9573 10:58:02.845983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9574 10:58:02.852482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9575 10:58:02.855723 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9576 10:58:02.859111 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9577 10:58:02.862508 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9578 10:58:02.869368 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9579 10:58:02.872548 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9580 10:58:02.875757 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9581 10:58:02.882624 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9582 10:58:02.886101 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9583 10:58:02.892495 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9584 10:58:02.895509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9585 10:58:02.899334 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9586 10:58:02.906115 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9587 10:58:02.909209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9588 10:58:02.915671 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9589 10:58:02.918986 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9590 10:58:02.922206 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9591 10:58:02.928833 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9592 10:58:02.932577 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9593 10:58:02.939153 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9594 10:58:02.942031 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9595 10:58:02.945453 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9596 10:58:02.949086 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9597 10:58:02.955359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9598 10:58:02.958699 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9599 10:58:02.961958 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9600 10:58:02.965460 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9601 10:58:02.971964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9602 10:58:02.975593 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9603 10:58:02.978626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9604 10:58:02.985032 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9605 10:58:02.988731 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9606 10:58:02.995604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9607 10:58:02.998329 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9608 10:58:03.002163 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9609 10:58:03.008825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9610 10:58:03.011745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9611 10:58:03.018652 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9612 10:58:03.021634 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9613 10:58:03.025606 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9614 10:58:03.031535 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9615 10:58:03.035074 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9616 10:58:03.041556 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9617 10:58:03.044698 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9618 10:58:03.048031 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9619 10:58:03.054992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9620 10:58:03.058227 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9621 10:58:03.064882 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9622 10:58:03.067987 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9623 10:58:03.071439 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9624 10:58:03.077977 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9625 10:58:03.081099 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9626 10:58:03.087857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9627 10:58:03.091270 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9628 10:58:03.094872 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9629 10:58:03.101501 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9630 10:58:03.104508 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9631 10:58:03.107729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9632 10:58:03.114515 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9633 10:58:03.117843 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9634 10:58:03.124511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9635 10:58:03.127889 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9636 10:58:03.131403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9637 10:58:03.137726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9638 10:58:03.141004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9639 10:58:03.147510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9640 10:58:03.150805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9641 10:58:03.154060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9642 10:58:03.160578 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9643 10:58:03.163953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9644 10:58:03.170975 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9645 10:58:03.173962 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9646 10:58:03.177389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9647 10:58:03.183894 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9648 10:58:03.187351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9649 10:58:03.193922 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9650 10:58:03.197108 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9651 10:58:03.200783 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9652 10:58:03.206882 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9653 10:58:03.210237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9654 10:58:03.216949 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9655 10:58:03.220276 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9656 10:58:03.223788 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9657 10:58:03.230276 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9658 10:58:03.233668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9659 10:58:03.240134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9660 10:58:03.243383 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9661 10:58:03.246652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9662 10:58:03.253720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9663 10:58:03.256599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9664 10:58:03.263238 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9665 10:58:03.266454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9666 10:58:03.269704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9667 10:58:03.276649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9668 10:58:03.280264 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9669 10:58:03.286671 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9670 10:58:03.289678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9671 10:58:03.296228 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9672 10:58:03.299351 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9673 10:58:03.302809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9674 10:58:03.309363 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9675 10:58:03.313040 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9676 10:58:03.319074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9677 10:58:03.322697 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9678 10:58:03.326055 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9679 10:58:03.332500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9680 10:58:03.335645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9681 10:58:03.342272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9682 10:58:03.345915 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9683 10:58:03.352525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9684 10:58:03.355749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9685 10:58:03.358862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9686 10:58:03.365598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9687 10:58:03.369140 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9688 10:58:03.375656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9689 10:58:03.379077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9690 10:58:03.385462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9691 10:58:03.388487 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9692 10:58:03.392532 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9693 10:58:03.398703 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9694 10:58:03.402097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9695 10:58:03.408689 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9696 10:58:03.411925 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9697 10:58:03.418532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9698 10:58:03.421586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9699 10:58:03.424973 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9700 10:58:03.432080 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9701 10:58:03.435056 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9702 10:58:03.441440 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9703 10:58:03.444870 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9704 10:58:03.451910 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9705 10:58:03.455035 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9706 10:58:03.458158 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9707 10:58:03.464616 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9708 10:58:03.468098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9709 10:58:03.470862 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9710 10:58:03.474088 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9711 10:58:03.481179 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9712 10:58:03.484310 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9713 10:58:03.487991 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9714 10:58:03.494084 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9715 10:58:03.497301 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9716 10:58:03.504039 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9717 10:58:03.507237 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9718 10:58:03.510550 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9719 10:58:03.517359 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9720 10:58:03.520801 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9721 10:58:03.523470 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9722 10:58:03.530144 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9723 10:58:03.533770 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9724 10:58:03.537306 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9725 10:58:03.543774 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9726 10:58:03.546773 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9727 10:58:03.553586 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9728 10:58:03.557006 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9729 10:58:03.560103 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9730 10:58:03.567108 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9731 10:58:03.569725 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9732 10:58:03.572975 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9733 10:58:03.580253 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9734 10:58:03.583163 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9735 10:58:03.589527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9736 10:58:03.593015 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9737 10:58:03.596873 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9738 10:58:03.602836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9739 10:58:03.606449 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9740 10:58:03.609691 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9741 10:58:03.615932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9742 10:58:03.619179 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9743 10:58:03.625740 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9744 10:58:03.628855 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9745 10:58:03.632160 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9746 10:58:03.638703 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9747 10:58:03.642076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9748 10:58:03.645697 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9749 10:58:03.648697 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9750 10:58:03.655248 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9751 10:58:03.658989 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9752 10:58:03.662026 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9753 10:58:03.664915 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9754 10:58:03.671940 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9755 10:58:03.675145 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9756 10:58:03.678456 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9757 10:58:03.681794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9758 10:58:03.688343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9759 10:58:03.691912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9760 10:58:03.695140 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9761 10:58:03.701377 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9762 10:58:03.705294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9763 10:58:03.712117 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9764 10:58:03.715266 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9765 10:58:03.718101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9766 10:58:03.724875 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9767 10:58:03.728337 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9768 10:58:03.734589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9769 10:58:03.738065 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9770 10:58:03.744570 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9771 10:58:03.747535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9772 10:58:03.750857 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9773 10:58:03.757663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9774 10:58:03.760655 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9775 10:58:03.767425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9776 10:58:03.770477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9777 10:58:03.774020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9778 10:58:03.780436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9779 10:58:03.783931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9780 10:58:03.790613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9781 10:58:03.793731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9782 10:58:03.800319 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9783 10:58:03.803729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9784 10:58:03.807369 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9785 10:58:03.813754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9786 10:58:03.816958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9787 10:58:03.823387 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9788 10:58:03.826823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9789 10:58:03.830208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9790 10:58:03.836662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9791 10:58:03.839928 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9792 10:58:03.846631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9793 10:58:03.850338 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9794 10:58:03.856714 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9795 10:58:03.859869 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9796 10:58:03.863458 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9797 10:58:03.869573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9798 10:58:03.872742 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9799 10:58:03.879602 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9800 10:58:03.883031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9801 10:58:03.886383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9802 10:58:03.892724 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9803 10:58:03.896615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9804 10:58:03.903038 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9805 10:58:03.906438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9806 10:58:03.912883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9807 10:58:03.915806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9808 10:58:03.919073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9809 10:58:03.925918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9810 10:58:03.929207 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9811 10:58:03.935772 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9812 10:58:03.938988 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9813 10:58:03.942462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9814 10:58:03.948993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9815 10:58:03.952371 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9816 10:58:03.958887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9817 10:58:03.962451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9818 10:58:03.968595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9819 10:58:03.971986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9820 10:58:03.975190 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9821 10:58:03.981809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9822 10:58:03.985371 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9823 10:58:03.991675 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9824 10:58:03.995114 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9825 10:58:03.998398 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9826 10:58:04.005424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9827 10:58:04.008366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9828 10:58:04.015016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9829 10:58:04.018252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9830 10:58:04.025297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9831 10:58:04.028133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9832 10:58:04.031519 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9833 10:58:04.038007 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9834 10:58:04.041248 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9835 10:58:04.048256 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9836 10:58:04.051260 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9837 10:58:04.058564 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9838 10:58:04.061178 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9839 10:58:04.064980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9840 10:58:04.071862 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9841 10:58:04.075151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9842 10:58:04.081613 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9843 10:58:04.085148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9844 10:58:04.091330 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9845 10:58:04.094680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9846 10:58:04.101425 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9847 10:58:04.104622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9848 10:58:04.108175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9849 10:58:04.114510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9850 10:58:04.117705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9851 10:58:04.124208 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9852 10:58:04.127481 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9853 10:58:04.134116 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9854 10:58:04.137619 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9855 10:58:04.144259 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9856 10:58:04.147422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9857 10:58:04.150956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9858 10:58:04.157223 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9859 10:58:04.160559 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9860 10:58:04.167040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9861 10:58:04.170584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9862 10:58:04.177404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9863 10:58:04.180373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9864 10:58:04.183834 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9865 10:58:04.190392 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9866 10:58:04.193188 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9867 10:58:04.200068 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9868 10:58:04.203258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9869 10:58:04.209791 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9870 10:58:04.213603 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9871 10:58:04.219769 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9872 10:58:04.223490 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9873 10:58:04.226456 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9874 10:58:04.232911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9875 10:58:04.236193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9876 10:58:04.243209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9877 10:58:04.246247 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9878 10:58:04.252932 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9879 10:58:04.256343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9880 10:58:04.259687 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9881 10:58:04.266183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9882 10:58:04.269512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9883 10:58:04.276414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9884 10:58:04.279474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9885 10:58:04.285989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9886 10:58:04.289572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9887 10:58:04.296151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9888 10:58:04.299105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9889 10:58:04.305550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9890 10:58:04.309310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9891 10:58:04.315615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9892 10:58:04.318678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9893 10:58:04.325462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9894 10:58:04.328714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9895 10:58:04.335631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9896 10:58:04.338959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9897 10:58:04.345045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9898 10:58:04.348437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9899 10:58:04.355454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9900 10:58:04.358508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9901 10:58:04.365202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9902 10:58:04.368332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9903 10:58:04.374679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9904 10:58:04.378169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9905 10:58:04.384596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9906 10:58:04.387931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9907 10:58:04.394674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9908 10:58:04.397879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9909 10:58:04.404261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9910 10:58:04.407691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9911 10:58:04.414314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9912 10:58:04.417353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9913 10:58:04.420696 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9914 10:58:04.424234 INFO: [APUAPC] vio 0
9915 10:58:04.430679 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9916 10:58:04.434211 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9917 10:58:04.437343 INFO: [APUAPC] D0_APC_0: 0x400510
9918 10:58:04.440671 INFO: [APUAPC] D0_APC_1: 0x0
9919 10:58:04.444053 INFO: [APUAPC] D0_APC_2: 0x1540
9920 10:58:04.447327 INFO: [APUAPC] D0_APC_3: 0x0
9921 10:58:04.450755 INFO: [APUAPC] D1_APC_0: 0xffffffff
9922 10:58:04.453826 INFO: [APUAPC] D1_APC_1: 0xffffffff
9923 10:58:04.457224 INFO: [APUAPC] D1_APC_2: 0x3fffff
9924 10:58:04.460805 INFO: [APUAPC] D1_APC_3: 0x0
9925 10:58:04.463636 INFO: [APUAPC] D2_APC_0: 0xffffffff
9926 10:58:04.467038 INFO: [APUAPC] D2_APC_1: 0xffffffff
9927 10:58:04.470556 INFO: [APUAPC] D2_APC_2: 0x3fffff
9928 10:58:04.473521 INFO: [APUAPC] D2_APC_3: 0x0
9929 10:58:04.476884 INFO: [APUAPC] D3_APC_0: 0xffffffff
9930 10:58:04.480114 INFO: [APUAPC] D3_APC_1: 0xffffffff
9931 10:58:04.483486 INFO: [APUAPC] D3_APC_2: 0x3fffff
9932 10:58:04.487293 INFO: [APUAPC] D3_APC_3: 0x0
9933 10:58:04.490225 INFO: [APUAPC] D4_APC_0: 0xffffffff
9934 10:58:04.493326 INFO: [APUAPC] D4_APC_1: 0xffffffff
9935 10:58:04.496514 INFO: [APUAPC] D4_APC_2: 0x3fffff
9936 10:58:04.496599 INFO: [APUAPC] D4_APC_3: 0x0
9937 10:58:04.503402 INFO: [APUAPC] D5_APC_0: 0xffffffff
9938 10:58:04.506526 INFO: [APUAPC] D5_APC_1: 0xffffffff
9939 10:58:04.510028 INFO: [APUAPC] D5_APC_2: 0x3fffff
9940 10:58:04.510112 INFO: [APUAPC] D5_APC_3: 0x0
9941 10:58:04.513160 INFO: [APUAPC] D6_APC_0: 0xffffffff
9942 10:58:04.519924 INFO: [APUAPC] D6_APC_1: 0xffffffff
9943 10:58:04.520010 INFO: [APUAPC] D6_APC_2: 0x3fffff
9944 10:58:04.523175 INFO: [APUAPC] D6_APC_3: 0x0
9945 10:58:04.526501 INFO: [APUAPC] D7_APC_0: 0xffffffff
9946 10:58:04.529718 INFO: [APUAPC] D7_APC_1: 0xffffffff
9947 10:58:04.533149 INFO: [APUAPC] D7_APC_2: 0x3fffff
9948 10:58:04.536507 INFO: [APUAPC] D7_APC_3: 0x0
9949 10:58:04.540005 INFO: [APUAPC] D8_APC_0: 0xffffffff
9950 10:58:04.543213 INFO: [APUAPC] D8_APC_1: 0xffffffff
9951 10:58:04.546557 INFO: [APUAPC] D8_APC_2: 0x3fffff
9952 10:58:04.549548 INFO: [APUAPC] D8_APC_3: 0x0
9953 10:58:04.552973 INFO: [APUAPC] D9_APC_0: 0xffffffff
9954 10:58:04.556304 INFO: [APUAPC] D9_APC_1: 0xffffffff
9955 10:58:04.559502 INFO: [APUAPC] D9_APC_2: 0x3fffff
9956 10:58:04.562992 INFO: [APUAPC] D9_APC_3: 0x0
9957 10:58:04.566488 INFO: [APUAPC] D10_APC_0: 0xffffffff
9958 10:58:04.569471 INFO: [APUAPC] D10_APC_1: 0xffffffff
9959 10:58:04.572652 INFO: [APUAPC] D10_APC_2: 0x3fffff
9960 10:58:04.576271 INFO: [APUAPC] D10_APC_3: 0x0
9961 10:58:04.579232 INFO: [APUAPC] D11_APC_0: 0xffffffff
9962 10:58:04.582944 INFO: [APUAPC] D11_APC_1: 0xffffffff
9963 10:58:04.586035 INFO: [APUAPC] D11_APC_2: 0x3fffff
9964 10:58:04.589394 INFO: [APUAPC] D11_APC_3: 0x0
9965 10:58:04.592745 INFO: [APUAPC] D12_APC_0: 0xffffffff
9966 10:58:04.595974 INFO: [APUAPC] D12_APC_1: 0xffffffff
9967 10:58:04.599344 INFO: [APUAPC] D12_APC_2: 0x3fffff
9968 10:58:04.602228 INFO: [APUAPC] D12_APC_3: 0x0
9969 10:58:04.605906 INFO: [APUAPC] D13_APC_0: 0xffffffff
9970 10:58:04.612388 INFO: [APUAPC] D13_APC_1: 0xffffffff
9971 10:58:04.615628 INFO: [APUAPC] D13_APC_2: 0x3fffff
9972 10:58:04.615744 INFO: [APUAPC] D13_APC_3: 0x0
9973 10:58:04.618874 INFO: [APUAPC] D14_APC_0: 0xffffffff
9974 10:58:04.625547 INFO: [APUAPC] D14_APC_1: 0xffffffff
9975 10:58:04.628597 INFO: [APUAPC] D14_APC_2: 0x3fffff
9976 10:58:04.628724 INFO: [APUAPC] D14_APC_3: 0x0
9977 10:58:04.635153 INFO: [APUAPC] D15_APC_0: 0xffffffff
9978 10:58:04.638581 INFO: [APUAPC] D15_APC_1: 0xffffffff
9979 10:58:04.641863 INFO: [APUAPC] D15_APC_2: 0x3fffff
9980 10:58:04.642030 INFO: [APUAPC] D15_APC_3: 0x0
9981 10:58:04.645202 INFO: [APUAPC] APC_CON: 0x4
9982 10:58:04.648788 INFO: [NOCDAPC] D0_APC_0: 0x0
9983 10:58:04.651814 INFO: [NOCDAPC] D0_APC_1: 0x0
9984 10:58:04.655377 INFO: [NOCDAPC] D1_APC_0: 0x0
9985 10:58:04.658584 INFO: [NOCDAPC] D1_APC_1: 0xfff
9986 10:58:04.661577 INFO: [NOCDAPC] D2_APC_0: 0x0
9987 10:58:04.665344 INFO: [NOCDAPC] D2_APC_1: 0xfff
9988 10:58:04.668225 INFO: [NOCDAPC] D3_APC_0: 0x0
9989 10:58:04.672168 INFO: [NOCDAPC] D3_APC_1: 0xfff
9990 10:58:04.674894 INFO: [NOCDAPC] D4_APC_0: 0x0
9991 10:58:04.675355 INFO: [NOCDAPC] D4_APC_1: 0xfff
9992 10:58:04.678455 INFO: [NOCDAPC] D5_APC_0: 0x0
9993 10:58:04.681604 INFO: [NOCDAPC] D5_APC_1: 0xfff
9994 10:58:04.685082 INFO: [NOCDAPC] D6_APC_0: 0x0
9995 10:58:04.688307 INFO: [NOCDAPC] D6_APC_1: 0xfff
9996 10:58:04.692108 INFO: [NOCDAPC] D7_APC_0: 0x0
9997 10:58:04.695137 INFO: [NOCDAPC] D7_APC_1: 0xfff
9998 10:58:04.698266 INFO: [NOCDAPC] D8_APC_0: 0x0
9999 10:58:04.701375 INFO: [NOCDAPC] D8_APC_1: 0xfff
10000 10:58:04.704788 INFO: [NOCDAPC] D9_APC_0: 0x0
10001 10:58:04.708155 INFO: [NOCDAPC] D9_APC_1: 0xfff
10002 10:58:04.708674 INFO: [NOCDAPC] D10_APC_0: 0x0
10003 10:58:04.711187 INFO: [NOCDAPC] D10_APC_1: 0xfff
10004 10:58:04.715021 INFO: [NOCDAPC] D11_APC_0: 0x0
10005 10:58:04.717817 INFO: [NOCDAPC] D11_APC_1: 0xfff
10006 10:58:04.721053 INFO: [NOCDAPC] D12_APC_0: 0x0
10007 10:58:04.724706 INFO: [NOCDAPC] D12_APC_1: 0xfff
10008 10:58:04.727685 INFO: [NOCDAPC] D13_APC_0: 0x0
10009 10:58:04.731612 INFO: [NOCDAPC] D13_APC_1: 0xfff
10010 10:58:04.734518 INFO: [NOCDAPC] D14_APC_0: 0x0
10011 10:58:04.737993 INFO: [NOCDAPC] D14_APC_1: 0xfff
10012 10:58:04.740930 INFO: [NOCDAPC] D15_APC_0: 0x0
10013 10:58:04.744602 INFO: [NOCDAPC] D15_APC_1: 0xfff
10014 10:58:04.747732 INFO: [NOCDAPC] APC_CON: 0x4
10015 10:58:04.750868 INFO: [APUAPC] set_apusys_apc done
10016 10:58:04.754548 INFO: [DEVAPC] devapc_init done
10017 10:58:04.757938 INFO: GICv3 without legacy support detected.
10018 10:58:04.760909 INFO: ARM GICv3 driver initialized in EL3
10019 10:58:04.763954 INFO: Maximum SPI INTID supported: 639
10020 10:58:04.767472 INFO: BL31: Initializing runtime services
10021 10:58:04.774261 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10022 10:58:04.777389 INFO: SPM: enable CPC mode
10023 10:58:04.783941 INFO: mcdi ready for mcusys-off-idle and system suspend
10024 10:58:04.787088 INFO: BL31: Preparing for EL3 exit to normal world
10025 10:58:04.790733 INFO: Entry point address = 0x80000000
10026 10:58:04.793664 INFO: SPSR = 0x8
10027 10:58:04.799033
10028 10:58:04.799214
10029 10:58:04.799356
10030 10:58:04.802289 Starting depthcharge on Spherion...
10031 10:58:04.802501
10032 10:58:04.802670 Wipe memory regions:
10033 10:58:04.802826
10034 10:58:04.803991 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10035 10:58:04.804248 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10036 10:58:04.804455 Setting prompt string to ['asurada:']
10037 10:58:04.804653 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10038 10:58:04.805508 [0x00000040000000, 0x00000054600000)
10039 10:58:04.927500
10040 10:58:04.927616 [0x00000054660000, 0x00000080000000)
10041 10:58:05.188705
10042 10:58:05.189269 [0x000000821a7280, 0x000000ffe64000)
10043 10:58:05.933649
10044 10:58:05.934214 [0x00000100000000, 0x00000240000000)
10045 10:58:07.823941
10046 10:58:07.826959 Initializing XHCI USB controller at 0x11200000.
10047 10:58:08.865139
10048 10:58:08.867969 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10049 10:58:08.868486
10050 10:58:08.868913
10051 10:58:08.869267
10052 10:58:08.870050 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 10:58:08.971438 asurada: tftpboot 192.168.201.1 10591025/tftp-deploy-op8g5veo/kernel/image.itb 10591025/tftp-deploy-op8g5veo/kernel/cmdline
10055 10:58:08.972109 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 10:58:08.972625 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10057 10:58:08.976997 tftpboot 192.168.201.1 10591025/tftp-deploy-op8g5veo/kernel/image.itp-deploy-op8g5veo/kernel/cmdline
10058 10:58:08.977472
10059 10:58:08.977836 Waiting for link
10060 10:58:09.137890
10061 10:58:09.138450 R8152: Initializing
10062 10:58:09.138819
10063 10:58:09.140561 Version 9 (ocp_data = 6010)
10064 10:58:09.141163
10065 10:58:09.144012 R8152: Done initializing
10066 10:58:09.144570
10067 10:58:09.144975 Adding net device
10068 10:58:11.013237
10069 10:58:11.013795 done.
10070 10:58:11.014166
10071 10:58:11.014502 MAC: 00:e0:4c:72:2d:d6
10072 10:58:11.014832
10073 10:58:11.016599 Sending DHCP discover... done.
10074 10:58:11.017202
10075 10:58:16.742369 Waiting for reply... done.
10076 10:58:16.742930
10077 10:58:16.743301 Sending DHCP request... done.
10078 10:58:16.745180
10079 10:58:16.751682 Waiting for reply... done.
10080 10:58:16.752254
10081 10:58:16.752629 My ip is 192.168.201.21
10082 10:58:16.753031
10083 10:58:16.755031 The DHCP server ip is 192.168.201.1
10084 10:58:16.755629
10085 10:58:16.761609 TFTP server IP predefined by user: 192.168.201.1
10086 10:58:16.762200
10087 10:58:16.768523 Bootfile predefined by user: 10591025/tftp-deploy-op8g5veo/kernel/image.itb
10088 10:58:16.769162
10089 10:58:16.771243 Sending tftp read request... done.
10090 10:58:16.771754
10091 10:58:16.776198 Waiting for the transfer...
10092 10:58:16.776868
10093 10:58:17.153337 00000000 ################################################################
10094 10:58:17.153883
10095 10:58:17.536885 00080000 ################################################################
10096 10:58:17.537381
10097 10:58:17.841235 00100000 ################################################################
10098 10:58:17.841374
10099 10:58:18.140020 00180000 ################################################################
10100 10:58:18.140147
10101 10:58:18.403165 00200000 ################################################################
10102 10:58:18.403300
10103 10:58:18.654373 00280000 ################################################################
10104 10:58:18.654502
10105 10:58:18.904135 00300000 ################################################################
10106 10:58:18.904278
10107 10:58:19.197026 00380000 ################################################################
10108 10:58:19.197169
10109 10:58:19.491200 00400000 ################################################################
10110 10:58:19.491342
10111 10:58:19.785330 00480000 ################################################################
10112 10:58:19.785466
10113 10:58:20.035328 00500000 ################################################################
10114 10:58:20.035452
10115 10:58:20.323424 00580000 ################################################################
10116 10:58:20.323565
10117 10:58:20.612476 00600000 ################################################################
10118 10:58:20.612618
10119 10:58:20.903024 00680000 ################################################################
10120 10:58:20.903185
10121 10:58:21.165877 00700000 ################################################################
10122 10:58:21.166035
10123 10:58:21.414947 00780000 ################################################################
10124 10:58:21.415101
10125 10:58:21.698079 00800000 ################################################################
10126 10:58:21.698218
10127 10:58:21.967062 00880000 ################################################################
10128 10:58:21.967196
10129 10:58:22.234833 00900000 ################################################################
10130 10:58:22.234969
10131 10:58:22.522643 00980000 ################################################################
10132 10:58:22.522782
10133 10:58:22.782476 00a00000 ################################################################
10134 10:58:22.782612
10135 10:58:23.049830 00a80000 ################################################################
10136 10:58:23.049966
10137 10:58:23.311542 00b00000 ################################################################
10138 10:58:23.311695
10139 10:58:23.580636 00b80000 ################################################################
10140 10:58:23.580810
10141 10:58:23.847251 00c00000 ################################################################
10142 10:58:23.847391
10143 10:58:24.117094 00c80000 ################################################################
10144 10:58:24.117234
10145 10:58:24.376127 00d00000 ################################################################
10146 10:58:24.376269
10147 10:58:24.629358 00d80000 ################################################################
10148 10:58:24.629510
10149 10:58:24.883740 00e00000 ################################################################
10150 10:58:24.883880
10151 10:58:25.170954 00e80000 ################################################################
10152 10:58:25.171128
10153 10:58:25.430652 00f00000 ################################################################
10154 10:58:25.430791
10155 10:58:25.702239 00f80000 ################################################################
10156 10:58:25.702374
10157 10:58:25.985873 01000000 ################################################################
10158 10:58:25.986027
10159 10:58:26.266674 01080000 ################################################################
10160 10:58:26.266823
10161 10:58:26.542091 01100000 ################################################################
10162 10:58:26.542237
10163 10:58:26.802532 01180000 ################################################################
10164 10:58:26.802686
10165 10:58:27.085005 01200000 ################################################################
10166 10:58:27.085154
10167 10:58:27.338903 01280000 ################################################################
10168 10:58:27.339052
10169 10:58:27.621088 01300000 ################################################################
10170 10:58:27.621233
10171 10:58:27.892562 01380000 ################################################################
10172 10:58:27.892705
10173 10:58:28.187009 01400000 ################################################################
10174 10:58:28.187159
10175 10:58:28.448362 01480000 ################################################################
10176 10:58:28.448519
10177 10:58:28.729034 01500000 ################################################################
10178 10:58:28.729180
10179 10:58:29.010040 01580000 ################################################################
10180 10:58:29.010179
10181 10:58:29.306164 01600000 ################################################################
10182 10:58:29.306309
10183 10:58:29.602754 01680000 ################################################################
10184 10:58:29.602909
10185 10:58:29.894080 01700000 ################################################################
10186 10:58:29.894230
10187 10:58:30.193594 01780000 ################################################################
10188 10:58:30.193741
10189 10:58:30.492731 01800000 ################################################################
10190 10:58:30.492899
10191 10:58:30.778662 01880000 ################################################################
10192 10:58:30.778806
10193 10:58:31.064752 01900000 ################################################################
10194 10:58:31.064932
10195 10:58:31.356542 01980000 ################################################################
10196 10:58:31.356705
10197 10:58:31.640213 01a00000 ################################################################
10198 10:58:31.640361
10199 10:58:31.933393 01a80000 ################################################################
10200 10:58:31.933544
10201 10:58:32.230190 01b00000 ################################################################
10202 10:58:32.230340
10203 10:58:32.514907 01b80000 ################################################################
10204 10:58:32.515055
10205 10:58:32.808142 01c00000 ################################################################
10206 10:58:32.808294
10207 10:58:33.103360 01c80000 ################################################################
10208 10:58:33.103512
10209 10:58:33.384797 01d00000 ################################################################
10210 10:58:33.384940
10211 10:58:33.676459 01d80000 ################################################################
10212 10:58:33.676604
10213 10:58:33.966742 01e00000 ################################################################
10214 10:58:33.966919
10215 10:58:34.255529 01e80000 ################################################################
10216 10:58:34.255686
10217 10:58:34.525269 01f00000 ################################################################
10218 10:58:34.525421
10219 10:58:34.794015 01f80000 ################################################################
10220 10:58:34.794177
10221 10:58:35.069555 02000000 ################################################################
10222 10:58:35.069706
10223 10:58:35.340455 02080000 ################################################################
10224 10:58:35.340636
10225 10:58:35.604979 02100000 ################################################################
10226 10:58:35.605130
10227 10:58:35.852981 02180000 ################################################################
10228 10:58:35.853132
10229 10:58:36.111802 02200000 ################################################################
10230 10:58:36.111957
10231 10:58:36.370955 02280000 ################################################################
10232 10:58:36.371108
10233 10:58:36.632636 02300000 ################################################################
10234 10:58:36.632820
10235 10:58:36.894799 02380000 ################################################################
10236 10:58:36.894947
10237 10:58:37.176148 02400000 ################################################################
10238 10:58:37.176298
10239 10:58:37.475401 02480000 ################################################################
10240 10:58:37.475590
10241 10:58:37.739237 02500000 ################################################################
10242 10:58:37.739420
10243 10:58:38.035409 02580000 ################################################################
10244 10:58:38.035596
10245 10:58:38.327295 02600000 ################################################################
10246 10:58:38.327486
10247 10:58:38.608769 02680000 ################################################################
10248 10:58:38.608967
10249 10:58:38.858892 02700000 ################################################################
10250 10:58:38.859075
10251 10:58:39.154899 02780000 ################################################################
10252 10:58:39.155079
10253 10:58:39.451195 02800000 ################################################################
10254 10:58:39.451370
10255 10:58:39.687005 02880000 ################################################################
10256 10:58:39.687181
10257 10:58:39.919758 02900000 ################################################################
10258 10:58:39.919910
10259 10:58:40.151624 02980000 ################################################################
10260 10:58:40.151777
10261 10:58:40.387800 02a00000 ################################################################
10262 10:58:40.387964
10263 10:58:40.637037 02a80000 ################################################################
10264 10:58:40.637175
10265 10:58:40.909153 02b00000 ################################################################
10266 10:58:40.909293
10267 10:58:41.169627 02b80000 ################################################################
10268 10:58:41.169766
10269 10:58:41.466206 02c00000 ################################################################
10270 10:58:41.466346
10271 10:58:41.746899 02c80000 ################################################################
10272 10:58:41.747038
10273 10:58:42.023572 02d00000 ################################################################
10274 10:58:42.023712
10275 10:58:42.314048 02d80000 ################################################################
10276 10:58:42.314192
10277 10:58:42.610679 02e00000 ################################################################
10278 10:58:42.610822
10279 10:58:42.899762 02e80000 ################################################################
10280 10:58:42.899902
10281 10:58:43.188857 02f00000 ################################################################
10282 10:58:43.188998
10283 10:58:43.482778 02f80000 ################################################################
10284 10:58:43.482917
10285 10:58:43.773942 03000000 ################################################################
10286 10:58:43.774088
10287 10:58:44.057947 03080000 ################################################################
10288 10:58:44.058086
10289 10:58:44.307376 03100000 ################################################################
10290 10:58:44.307509
10291 10:58:44.556323 03180000 ################################################################
10292 10:58:44.556456
10293 10:58:44.806082 03200000 ################################################################
10294 10:58:44.806213
10295 10:58:45.072784 03280000 ################################################################
10296 10:58:45.072948
10297 10:58:45.359221 03300000 ################################################################
10298 10:58:45.359366
10299 10:58:45.625144 03380000 ################################################################
10300 10:58:45.625293
10301 10:58:45.900465 03400000 ################################################################
10302 10:58:45.900609
10303 10:58:46.161603 03480000 ################################################################
10304 10:58:46.161745
10305 10:58:46.428946 03500000 ################################################################
10306 10:58:46.429094
10307 10:58:46.720754 03580000 ################################################################
10308 10:58:46.720900
10309 10:58:47.086507 03600000 ################################################################
10310 10:58:47.086953
10311 10:58:47.487900 03680000 ################################################################
10312 10:58:47.488331
10313 10:58:47.811029 03700000 ################################################################
10314 10:58:47.811168
10315 10:58:48.104618 03780000 ################################################################
10316 10:58:48.104778
10317 10:58:48.401158 03800000 ################################################################
10318 10:58:48.401306
10319 10:58:48.700819 03880000 ################################################################
10320 10:58:48.700958
10321 10:58:48.997345 03900000 ################################################################
10322 10:58:48.997480
10323 10:58:49.279291 03980000 ################################################################
10324 10:58:49.279424
10325 10:58:49.569302 03a00000 ################################################################
10326 10:58:49.569427
10327 10:58:49.863608 03a80000 ################################################################
10328 10:58:49.863732
10329 10:58:50.147781 03b00000 ################################################################
10330 10:58:50.147920
10331 10:58:50.427222 03b80000 ################################################################
10332 10:58:50.427351
10333 10:58:50.676747 03c00000 ################################################################
10334 10:58:50.676903
10335 10:58:50.939412 03c80000 ################################################################
10336 10:58:50.939532
10337 10:58:51.205780 03d00000 ################################################################
10338 10:58:51.205923
10339 10:58:51.457274 03d80000 ################################################################
10340 10:58:51.457395
10341 10:58:51.748550 03e00000 ################################################################
10342 10:58:51.748676
10343 10:58:52.037638 03e80000 ################################################################
10344 10:58:52.037775
10345 10:58:52.310745 03f00000 ################################################################
10346 10:58:52.310882
10347 10:58:52.568643 03f80000 ################################################################
10348 10:58:52.568776
10349 10:58:52.845120 04000000 ################################################################
10350 10:58:52.845251
10351 10:58:53.115540 04080000 ################################################################
10352 10:58:53.115671
10353 10:58:53.365063 04100000 ################################################################
10354 10:58:53.365193
10355 10:58:53.635170 04180000 ################################################################
10356 10:58:53.635297
10357 10:58:53.890666 04200000 ################################################################
10358 10:58:53.890794
10359 10:58:54.153521 04280000 ################################################################
10360 10:58:54.153656
10361 10:58:54.403430 04300000 ################################################################
10362 10:58:54.403554
10363 10:58:54.652883 04380000 ################################################################
10364 10:58:54.653011
10365 10:58:54.943152 04400000 ################################################################
10366 10:58:54.943284
10367 10:58:55.239225 04480000 ################################################################
10368 10:58:55.239349
10369 10:58:55.523311 04500000 ################################################################
10370 10:58:55.523467
10371 10:58:55.791271 04580000 ################################################################
10372 10:58:55.791399
10373 10:58:56.081045 04600000 ################################################################
10374 10:58:56.081177
10375 10:58:56.377907 04680000 ################################################################
10376 10:58:56.378039
10377 10:58:56.630264 04700000 ################################################################
10378 10:58:56.630389
10379 10:58:56.880252 04780000 ################################################################
10380 10:58:56.880384
10381 10:58:57.145034 04800000 ################################################################
10382 10:58:57.145164
10383 10:58:57.423968 04880000 ################################################################
10384 10:58:57.424096
10385 10:58:57.717612 04900000 ################################################################
10386 10:58:57.717742
10387 10:58:57.997446 04980000 ################################################################
10388 10:58:57.997576
10389 10:58:58.264127 04a00000 ################################################################
10390 10:58:58.264254
10391 10:58:58.518531 04a80000 ################################################################
10392 10:58:58.518655
10393 10:58:58.768178 04b00000 ################################################################
10394 10:58:58.768313
10395 10:58:59.019043 04b80000 ################################################################
10396 10:58:59.019177
10397 10:58:59.269880 04c00000 ################################################################
10398 10:58:59.270006
10399 10:58:59.528567 04c80000 ################################################################
10400 10:58:59.528697
10401 10:58:59.785501 04d00000 ################################################################
10402 10:58:59.785632
10403 10:59:00.047916 04d80000 ################################################################
10404 10:59:00.048055
10405 10:59:00.324287 04e00000 ################################################################
10406 10:59:00.324448
10407 10:59:00.578586 04e80000 ################################################################
10408 10:59:00.578716
10409 10:59:00.845075 04f00000 ################################################################
10410 10:59:00.845231
10411 10:59:01.093568 04f80000 ################################################################
10412 10:59:01.093700
10413 10:59:01.341319 05000000 ################################################################
10414 10:59:01.341451
10415 10:59:01.588258 05080000 ################################################################
10416 10:59:01.588381
10417 10:59:01.864581 05100000 ################################################################
10418 10:59:01.864716
10419 10:59:02.141596 05180000 ################################################################
10420 10:59:02.141727
10421 10:59:02.428034 05200000 ################################################################
10422 10:59:02.428197
10423 10:59:02.695143 05280000 ################################################################
10424 10:59:02.695285
10425 10:59:02.956032 05300000 ################################################################
10426 10:59:02.956166
10427 10:59:03.208805 05380000 ################################################################
10428 10:59:03.208954
10429 10:59:03.455307 05400000 ################################################################
10430 10:59:03.455448
10431 10:59:03.701080 05480000 ################################################################
10432 10:59:03.701237
10433 10:59:03.961458 05500000 ################################################################
10434 10:59:03.961619
10435 10:59:04.210391 05580000 ################################################################
10436 10:59:04.210574
10437 10:59:04.468610 05600000 ################################################################
10438 10:59:04.468773
10439 10:59:04.742128 05680000 ################################################################
10440 10:59:04.742256
10441 10:59:05.009344 05700000 ################################################################
10442 10:59:05.009514
10443 10:59:05.261214 05780000 ################################################################
10444 10:59:05.261351
10445 10:59:05.519181 05800000 ################################################################
10446 10:59:05.519340
10447 10:59:05.766210 05880000 ################################################################
10448 10:59:05.766338
10449 10:59:06.021685 05900000 ################################################################
10450 10:59:06.021845
10451 10:59:06.278265 05980000 ################################################################
10452 10:59:06.278420
10453 10:59:06.535550 05a00000 ################################################################
10454 10:59:06.535701
10455 10:59:06.794759 05a80000 ################################################################
10456 10:59:06.794916
10457 10:59:07.058793 05b00000 ################################################################
10458 10:59:07.058928
10459 10:59:07.315233 05b80000 ################################################################
10460 10:59:07.315367
10461 10:59:07.563052 05c00000 ################################################################
10462 10:59:07.563215
10463 10:59:07.809390 05c80000 ################################################################
10464 10:59:07.809545
10465 10:59:08.055804 05d00000 ################################################################
10466 10:59:08.055957
10467 10:59:08.314931 05d80000 ################################################################
10468 10:59:08.315090
10469 10:59:08.572196 05e00000 ################################################################
10470 10:59:08.572356
10471 10:59:08.820934 05e80000 ################################################################
10472 10:59:08.821069
10473 10:59:09.083600 05f00000 ################################################################
10474 10:59:09.083720
10475 10:59:09.380383 05f80000 ################################################################
10476 10:59:09.380517
10477 10:59:09.678278 06000000 ################################################################
10478 10:59:09.678403
10479 10:59:09.951883 06080000 ################################################################
10480 10:59:09.952007
10481 10:59:10.248040 06100000 ################################################################
10482 10:59:10.248169
10483 10:59:10.542736 06180000 ################################################################
10484 10:59:10.542862
10485 10:59:10.820674 06200000 ################################################################
10486 10:59:10.820827
10487 10:59:11.102243 06280000 ################################################################
10488 10:59:11.102398
10489 10:59:11.369660 06300000 ################################################################
10490 10:59:11.369791
10491 10:59:11.627746 06380000 ################################################################
10492 10:59:11.627875
10493 10:59:11.905142 06400000 ################################################################
10494 10:59:11.905272
10495 10:59:12.194975 06480000 ################################################################
10496 10:59:12.195111
10497 10:59:12.459115 06500000 ################################################################
10498 10:59:12.459240
10499 10:59:12.714693 06580000 ################################################################
10500 10:59:12.714835
10501 10:59:12.984988 06600000 ################################################################
10502 10:59:12.985112
10503 10:59:13.234015 06680000 ################################################################
10504 10:59:13.234143
10505 10:59:13.367228 06700000 ################################### done.
10506 10:59:13.367338
10507 10:59:13.370371 The bootfile was 108285378 bytes long.
10508 10:59:13.370455
10509 10:59:13.374006 Sending tftp read request... done.
10510 10:59:13.374096
10511 10:59:13.377139 Waiting for the transfer...
10512 10:59:13.377309
10513 10:59:13.377397 00000000 # done.
10514 10:59:13.377477
10515 10:59:13.386801 Command line loaded dynamically from TFTP file: 10591025/tftp-deploy-op8g5veo/kernel/cmdline
10516 10:59:13.386975
10517 10:59:13.397539 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10518 10:59:13.397678
10519 10:59:13.400139 Loading FIT.
10520 10:59:13.400274
10521 10:59:13.403533 Image ramdisk-1 has 98154484 bytes.
10522 10:59:13.403686
10523 10:59:13.403806 Image fdt-1 has 46924 bytes.
10524 10:59:13.403919
10525 10:59:13.406868 Image kernel-1 has 10081937 bytes.
10526 10:59:13.407134
10527 10:59:13.416921 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10528 10:59:13.417272
10529 10:59:13.433466 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10530 10:59:13.434020
10531 10:59:13.440101 Choosing best match conf-1 for compat google,spherion-rev2.
10532 10:59:13.444566
10533 10:59:13.448317 Connected to device vid:did:rid of 1ae0:0028:00
10534 10:59:13.455339
10535 10:59:13.458511 tpm_get_response: command 0x17b, return code 0x0
10536 10:59:13.459071
10537 10:59:13.461832 ec_init: CrosEC protocol v3 supported (256, 248)
10538 10:59:13.465815
10539 10:59:13.469074 tpm_cleanup: add release locality here.
10540 10:59:13.469534
10541 10:59:13.469898 Shutting down all USB controllers.
10542 10:59:13.472659
10543 10:59:13.473188 Removing current net device
10544 10:59:13.473574
10545 10:59:13.479306 Exiting depthcharge with code 4 at timestamp: 97995639
10546 10:59:13.479857
10547 10:59:13.482805 LZMA decompressing kernel-1 to 0x821a6718
10548 10:59:13.483267
10549 10:59:13.485854 LZMA decompressing kernel-1 to 0x40000000
10550 10:59:14.752440
10551 10:59:14.753049 jumping to kernel
10552 10:59:14.754847 end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10553 10:59:14.755348 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10554 10:59:14.755717 Setting prompt string to ['Linux version [0-9]']
10555 10:59:14.756059 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10556 10:59:14.756399 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10557 10:59:14.834701
10558 10:59:14.837904 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10559 10:59:14.841861 start: 2.2.5.1 login-action (timeout 00:03:15) [common]
10560 10:59:14.842434 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10561 10:59:14.842908 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10562 10:59:14.843339 Using line separator: #'\n'#
10563 10:59:14.843685 No login prompt set.
10564 10:59:14.844031 Parsing kernel messages
10565 10:59:14.844347 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10566 10:59:14.844959 [login-action] Waiting for messages, (timeout 00:03:15)
10567 10:59:14.860790 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10568 10:59:14.864400 [ 0.000000] random: crng init done
10569 10:59:14.870667 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10570 10:59:14.873864 [ 0.000000] efi: UEFI not found.
10571 10:59:14.880809 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10572 10:59:14.887312 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10573 10:59:14.897154 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10574 10:59:14.907060 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10575 10:59:14.913888 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10576 10:59:14.920632 [ 0.000000] printk: bootconsole [mtk8250] enabled
10577 10:59:14.926884 [ 0.000000] NUMA: No NUMA configuration found
10578 10:59:14.933692 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10579 10:59:14.936919 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10580 10:59:14.940204 [ 0.000000] Zone ranges:
10581 10:59:14.946944 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10582 10:59:14.950242 [ 0.000000] DMA32 empty
10583 10:59:14.956862 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10584 10:59:14.960302 [ 0.000000] Movable zone start for each node
10585 10:59:14.963560 [ 0.000000] Early memory node ranges
10586 10:59:14.969863 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10587 10:59:14.976465 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10588 10:59:14.983128 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10589 10:59:14.989922 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10590 10:59:14.996735 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10591 10:59:15.002563 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10592 10:59:15.059143 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10593 10:59:15.065710 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10594 10:59:15.072319 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10595 10:59:15.075720 [ 0.000000] psci: probing for conduit method from DT.
10596 10:59:15.082354 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10597 10:59:15.085575 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10598 10:59:15.092916 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10599 10:59:15.095573 [ 0.000000] psci: SMC Calling Convention v1.2
10600 10:59:15.101951 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10601 10:59:15.105465 [ 0.000000] Detected VIPT I-cache on CPU0
10602 10:59:15.111873 [ 0.000000] CPU features: detected: GIC system register CPU interface
10603 10:59:15.118974 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10604 10:59:15.125199 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10605 10:59:15.131717 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10606 10:59:15.138423 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10607 10:59:15.148352 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10608 10:59:15.151403 [ 0.000000] alternatives: applying boot alternatives
10609 10:59:15.158194 [ 0.000000] Fallback order for Node 0: 0
10610 10:59:15.164795 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10611 10:59:15.167990 [ 0.000000] Policy zone: Normal
10612 10:59:15.177745 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10613 10:59:15.191105 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10614 10:59:15.200980 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10615 10:59:15.211082 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10616 10:59:15.217296 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10617 10:59:15.220987 <6>[ 0.000000] software IO TLB: area num 8.
10618 10:59:15.276817 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10619 10:59:15.426049 <6>[ 0.000000] Memory: 7877088K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475680K reserved, 32768K cma-reserved)
10620 10:59:15.432553 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10621 10:59:15.439471 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10622 10:59:15.443030 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10623 10:59:15.449508 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10624 10:59:15.455751 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10625 10:59:15.459035 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10626 10:59:15.469182 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10627 10:59:15.475479 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10628 10:59:15.481951 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10629 10:59:15.488915 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10630 10:59:15.492062 <6>[ 0.000000] GICv3: 608 SPIs implemented
10631 10:59:15.495489 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10632 10:59:15.501998 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10633 10:59:15.505397 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10634 10:59:15.511553 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10635 10:59:15.525634 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10636 10:59:15.538016 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10637 10:59:15.544879 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10638 10:59:15.553003 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10639 10:59:15.566020 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10640 10:59:15.572423 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10641 10:59:15.579324 <6>[ 0.009225] Console: colour dummy device 80x25
10642 10:59:15.589341 <6>[ 0.013982] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10643 10:59:15.595917 <6>[ 0.024424] pid_max: default: 32768 minimum: 301
10644 10:59:15.599033 <6>[ 0.029327] LSM: Security Framework initializing
10645 10:59:15.605684 <6>[ 0.034268] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10646 10:59:15.615607 <6>[ 0.042083] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10647 10:59:15.625189 <6>[ 0.051507] cblist_init_generic: Setting adjustable number of callback queues.
10648 10:59:15.628641 <6>[ 0.059006] cblist_init_generic: Setting shift to 3 and lim to 1.
10649 10:59:15.635604 <6>[ 0.065383] cblist_init_generic: Setting shift to 3 and lim to 1.
10650 10:59:15.642154 <6>[ 0.071790] rcu: Hierarchical SRCU implementation.
10651 10:59:15.648382 <6>[ 0.076835] rcu: Max phase no-delay instances is 1000.
10652 10:59:15.654695 <6>[ 0.083890] EFI services will not be available.
10653 10:59:15.657889 <6>[ 0.088865] smp: Bringing up secondary CPUs ...
10654 10:59:15.666364 <6>[ 0.093906] Detected VIPT I-cache on CPU1
10655 10:59:15.673126 <6>[ 0.093966] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10656 10:59:15.679529 <6>[ 0.093989] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10657 10:59:15.683083 <6>[ 0.094298] Detected VIPT I-cache on CPU2
10658 10:59:15.689355 <6>[ 0.094347] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10659 10:59:15.696215 <6>[ 0.094363] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10660 10:59:15.702834 <6>[ 0.094621] Detected VIPT I-cache on CPU3
10661 10:59:15.709460 <6>[ 0.094667] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10662 10:59:15.715910 <6>[ 0.094681] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10663 10:59:15.719597 <6>[ 0.094988] CPU features: detected: Spectre-v4
10664 10:59:15.726222 <6>[ 0.094994] CPU features: detected: Spectre-BHB
10665 10:59:15.728761 <6>[ 0.095000] Detected PIPT I-cache on CPU4
10666 10:59:15.735567 <6>[ 0.095058] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10667 10:59:15.742283 <6>[ 0.095074] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10668 10:59:15.749005 <6>[ 0.095371] Detected PIPT I-cache on CPU5
10669 10:59:15.755724 <6>[ 0.095434] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10670 10:59:15.761820 <6>[ 0.095451] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10671 10:59:15.765401 <6>[ 0.095734] Detected PIPT I-cache on CPU6
10672 10:59:15.772036 <6>[ 0.095798] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10673 10:59:15.778947 <6>[ 0.095815] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10674 10:59:15.785194 <6>[ 0.096112] Detected PIPT I-cache on CPU7
10675 10:59:15.792001 <6>[ 0.096176] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10676 10:59:15.798622 <6>[ 0.096192] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10677 10:59:15.801471 <6>[ 0.096239] smp: Brought up 1 node, 8 CPUs
10678 10:59:15.808559 <6>[ 0.237502] SMP: Total of 8 processors activated.
10679 10:59:15.811732 <6>[ 0.242423] CPU features: detected: 32-bit EL0 Support
10680 10:59:15.821634 <6>[ 0.247819] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10681 10:59:15.828320 <6>[ 0.256619] CPU features: detected: Common not Private translations
10682 10:59:15.834332 <6>[ 0.263094] CPU features: detected: CRC32 instructions
10683 10:59:15.837871 <6>[ 0.268445] CPU features: detected: RCpc load-acquire (LDAPR)
10684 10:59:15.844846 <6>[ 0.274404] CPU features: detected: LSE atomic instructions
10685 10:59:15.851354 <6>[ 0.280221] CPU features: detected: Privileged Access Never
10686 10:59:15.857497 <6>[ 0.286007] CPU features: detected: RAS Extension Support
10687 10:59:15.864465 <6>[ 0.291617] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10688 10:59:15.868022 <6>[ 0.298837] CPU: All CPU(s) started at EL2
10689 10:59:15.874530 <6>[ 0.303153] alternatives: applying system-wide alternatives
10690 10:59:15.883987 <6>[ 0.313823] devtmpfs: initialized
10691 10:59:15.896498 <6>[ 0.322985] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10692 10:59:15.906187 <6>[ 0.332948] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10693 10:59:15.912587 <6>[ 0.341167] pinctrl core: initialized pinctrl subsystem
10694 10:59:15.915865 <6>[ 0.347837] DMI not present or invalid.
10695 10:59:15.923083 <6>[ 0.352247] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10696 10:59:15.932853 <6>[ 0.359126] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10697 10:59:15.938990 <6>[ 0.366712] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10698 10:59:15.948972 <6>[ 0.374935] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10699 10:59:15.951868 <6>[ 0.383178] audit: initializing netlink subsys (disabled)
10700 10:59:15.962045 <5>[ 0.388874] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10701 10:59:15.968859 <6>[ 0.389578] thermal_sys: Registered thermal governor 'step_wise'
10702 10:59:15.975089 <6>[ 0.396842] thermal_sys: Registered thermal governor 'power_allocator'
10703 10:59:15.978136 <6>[ 0.403099] cpuidle: using governor menu
10704 10:59:15.984679 <6>[ 0.414063] NET: Registered PF_QIPCRTR protocol family
10705 10:59:15.991788 <6>[ 0.419539] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10706 10:59:15.998299 <6>[ 0.426640] ASID allocator initialised with 32768 entries
10707 10:59:16.001355 <6>[ 0.433216] Serial: AMBA PL011 UART driver
10708 10:59:16.011781 <4>[ 0.441890] Trying to register duplicate clock ID: 134
10709 10:59:16.065613 <6>[ 0.499268] KASLR enabled
10710 10:59:16.080048 <6>[ 0.507089] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10711 10:59:16.086710 <6>[ 0.514100] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10712 10:59:16.093139 <6>[ 0.520590] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10713 10:59:16.100144 <6>[ 0.527595] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10714 10:59:16.106719 <6>[ 0.534083] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10715 10:59:16.112751 <6>[ 0.541088] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10716 10:59:16.119702 <6>[ 0.547577] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10717 10:59:16.126029 <6>[ 0.554582] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10718 10:59:16.129320 <6>[ 0.562103] ACPI: Interpreter disabled.
10719 10:59:16.138342 <6>[ 0.568473] iommu: Default domain type: Translated
10720 10:59:16.144565 <6>[ 0.573586] iommu: DMA domain TLB invalidation policy: strict mode
10721 10:59:16.147804 <5>[ 0.580214] SCSI subsystem initialized
10722 10:59:16.154361 <6>[ 0.584383] usbcore: registered new interface driver usbfs
10723 10:59:16.161123 <6>[ 0.590114] usbcore: registered new interface driver hub
10724 10:59:16.164313 <6>[ 0.595666] usbcore: registered new device driver usb
10725 10:59:16.171317 <6>[ 0.601747] pps_core: LinuxPPS API ver. 1 registered
10726 10:59:16.180912 <6>[ 0.606939] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10727 10:59:16.184261 <6>[ 0.616286] PTP clock support registered
10728 10:59:16.187473 <6>[ 0.620524] EDAC MC: Ver: 3.0.0
10729 10:59:16.195143 <6>[ 0.625676] FPGA manager framework
10730 10:59:16.201842 <6>[ 0.629358] Advanced Linux Sound Architecture Driver Initialized.
10731 10:59:16.204979 <6>[ 0.636127] vgaarb: loaded
10732 10:59:16.211558 <6>[ 0.639297] clocksource: Switched to clocksource arch_sys_counter
10733 10:59:16.214624 <5>[ 0.645736] VFS: Disk quotas dquot_6.6.0
10734 10:59:16.221375 <6>[ 0.649920] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10735 10:59:16.224817 <6>[ 0.657111] pnp: PnP ACPI: disabled
10736 10:59:16.233497 <6>[ 0.663841] NET: Registered PF_INET protocol family
10737 10:59:16.243572 <6>[ 0.669434] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10738 10:59:16.255108 <6>[ 0.681753] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10739 10:59:16.264811 <6>[ 0.690568] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10740 10:59:16.271149 <6>[ 0.698539] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10741 10:59:16.281249 <6>[ 0.707234] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10742 10:59:16.287669 <6>[ 0.716977] TCP: Hash tables configured (established 65536 bind 65536)
10743 10:59:16.294611 <6>[ 0.723832] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10744 10:59:16.304104 <6>[ 0.731031] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10745 10:59:16.310715 <6>[ 0.738735] NET: Registered PF_UNIX/PF_LOCAL protocol family
10746 10:59:16.317314 <6>[ 0.744894] RPC: Registered named UNIX socket transport module.
10747 10:59:16.320278 <6>[ 0.751049] RPC: Registered udp transport module.
10748 10:59:16.327386 <6>[ 0.755982] RPC: Registered tcp transport module.
10749 10:59:16.333835 <6>[ 0.760913] RPC: Registered tcp NFSv4.1 backchannel transport module.
10750 10:59:16.337343 <6>[ 0.767581] PCI: CLS 0 bytes, default 64
10751 10:59:16.340013 <6>[ 0.771957] Unpacking initramfs...
10752 10:59:16.364296 <6>[ 0.791406] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10753 10:59:16.374483 <6>[ 0.800075] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10754 10:59:16.377636 <6>[ 0.808918] kvm [1]: IPA Size Limit: 40 bits
10755 10:59:16.384465 <6>[ 0.813444] kvm [1]: GICv3: no GICV resource entry
10756 10:59:16.387620 <6>[ 0.818465] kvm [1]: disabling GICv2 emulation
10757 10:59:16.394352 <6>[ 0.823155] kvm [1]: GIC system register CPU interface enabled
10758 10:59:16.397668 <6>[ 0.829324] kvm [1]: vgic interrupt IRQ18
10759 10:59:16.404455 <6>[ 0.833689] kvm [1]: VHE mode initialized successfully
10760 10:59:16.410902 <5>[ 0.840141] Initialise system trusted keyrings
10761 10:59:16.417679 <6>[ 0.844942] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10762 10:59:16.424478 <6>[ 0.855045] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10763 10:59:16.431320 <5>[ 0.861431] NFS: Registering the id_resolver key type
10764 10:59:16.434387 <5>[ 0.866736] Key type id_resolver registered
10765 10:59:16.440957 <5>[ 0.871152] Key type id_legacy registered
10766 10:59:16.448149 <6>[ 0.875437] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10767 10:59:16.454252 <6>[ 0.882357] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10768 10:59:16.460892 <6>[ 0.890085] 9p: Installing v9fs 9p2000 file system support
10769 10:59:16.497558 <5>[ 0.927712] Key type asymmetric registered
10770 10:59:16.500810 <5>[ 0.932044] Asymmetric key parser 'x509' registered
10771 10:59:16.510563 <6>[ 0.937191] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10772 10:59:16.513832 <6>[ 0.944831] io scheduler mq-deadline registered
10773 10:59:16.517177 <6>[ 0.949596] io scheduler kyber registered
10774 10:59:16.536512 <6>[ 0.966508] EINJ: ACPI disabled.
10775 10:59:16.568987 <4>[ 0.992200] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10776 10:59:16.578438 <4>[ 1.002851] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10777 10:59:16.593222 <6>[ 1.023401] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10778 10:59:16.601230 <6>[ 1.031412] printk: console [ttyS0] disabled
10779 10:59:16.629105 <6>[ 1.056057] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10780 10:59:16.635563 <6>[ 1.065524] printk: console [ttyS0] enabled
10781 10:59:16.639117 <6>[ 1.065524] printk: console [ttyS0] enabled
10782 10:59:16.645475 <6>[ 1.074423] printk: bootconsole [mtk8250] disabled
10783 10:59:16.648931 <6>[ 1.074423] printk: bootconsole [mtk8250] disabled
10784 10:59:16.655860 <6>[ 1.085459] SuperH (H)SCI(F) driver initialized
10785 10:59:16.659002 <6>[ 1.090738] msm_serial: driver initialized
10786 10:59:16.672918 <6>[ 1.099563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10787 10:59:16.682844 <6>[ 1.108107] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10788 10:59:16.689243 <6>[ 1.116648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10789 10:59:16.699116 <6>[ 1.125276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10790 10:59:16.709121 <6>[ 1.133985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10791 10:59:16.715797 <6>[ 1.142698] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10792 10:59:16.725251 <6>[ 1.151237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10793 10:59:16.732144 <6>[ 1.160030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10794 10:59:16.741676 <6>[ 1.168572] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10795 10:59:16.753591 <6>[ 1.183778] loop: module loaded
10796 10:59:16.760208 <6>[ 1.189830] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10797 10:59:16.782738 <4>[ 1.212996] mtk-pmic-keys: Failed to locate of_node [id: -1]
10798 10:59:16.789677 <6>[ 1.219645] megasas: 07.719.03.00-rc1
10799 10:59:16.798745 <6>[ 1.229116] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10800 10:59:16.808682 <6>[ 1.238696] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10801 10:59:16.825571 <6>[ 1.255397] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10802 10:59:16.885975 <6>[ 1.309597] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10803 10:59:20.329949 <6>[ 4.760938] Freeing initrd memory: 95848K
10804 10:59:20.339892 <6>[ 4.771327] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10805 10:59:20.351347 <6>[ 4.782216] tun: Universal TUN/TAP device driver, 1.6
10806 10:59:20.354591 <6>[ 4.788268] thunder_xcv, ver 1.0
10807 10:59:20.358199 <6>[ 4.791772] thunder_bgx, ver 1.0
10808 10:59:20.361159 <6>[ 4.795264] nicpf, ver 1.0
10809 10:59:20.371610 <6>[ 4.799260] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10810 10:59:20.374894 <6>[ 4.806736] hns3: Copyright (c) 2017 Huawei Corporation.
10811 10:59:20.381764 <6>[ 4.812325] hclge is initializing
10812 10:59:20.384670 <6>[ 4.815905] e1000: Intel(R) PRO/1000 Network Driver
10813 10:59:20.391460 <6>[ 4.821034] e1000: Copyright (c) 1999-2006 Intel Corporation.
10814 10:59:20.394872 <6>[ 4.827047] e1000e: Intel(R) PRO/1000 Network Driver
10815 10:59:20.401505 <6>[ 4.832262] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10816 10:59:20.407983 <6>[ 4.838446] igb: Intel(R) Gigabit Ethernet Network Driver
10817 10:59:20.414443 <6>[ 4.844096] igb: Copyright (c) 2007-2014 Intel Corporation.
10818 10:59:20.421625 <6>[ 4.849933] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10819 10:59:20.427891 <6>[ 4.856451] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10820 10:59:20.431323 <6>[ 4.862916] sky2: driver version 1.30
10821 10:59:20.437626 <6>[ 4.867896] VFIO - User Level meta-driver version: 0.3
10822 10:59:20.445120 <6>[ 4.876052] usbcore: registered new interface driver usb-storage
10823 10:59:20.451574 <6>[ 4.882492] usbcore: registered new device driver onboard-usb-hub
10824 10:59:20.460418 <6>[ 4.891496] mt6397-rtc mt6359-rtc: registered as rtc0
10825 10:59:20.470459 <6>[ 4.896958] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:59:17 UTC (1685962757)
10826 10:59:20.473504 <6>[ 4.906526] i2c_dev: i2c /dev entries driver
10827 10:59:20.490301 <6>[ 4.918225] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10828 10:59:20.497211 <6>[ 4.928439] sdhci: Secure Digital Host Controller Interface driver
10829 10:59:20.504175 <6>[ 4.934877] sdhci: Copyright(c) Pierre Ossman
10830 10:59:20.510581 <6>[ 4.940272] Synopsys Designware Multimedia Card Interface Driver
10831 10:59:20.513708 <6>[ 4.946845] mmc0: CQHCI version 5.10
10832 10:59:20.520294 <6>[ 4.947427] sdhci-pltfm: SDHCI platform and OF driver helper
10833 10:59:20.527737 <6>[ 4.958701] ledtrig-cpu: registered to indicate activity on CPUs
10834 10:59:20.537992 <6>[ 4.966045] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10835 10:59:20.541455 <6>[ 4.973429] usbcore: registered new interface driver usbhid
10836 10:59:20.548254 <6>[ 4.979255] usbhid: USB HID core driver
10837 10:59:20.554935 <6>[ 4.983490] spi_master spi0: will run message pump with realtime priority
10838 10:59:20.600897 <6>[ 5.025385] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10839 10:59:20.619480 <6>[ 5.040778] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10840 10:59:20.623217 <6>[ 5.054344] mmc0: Command Queue Engine enabled
10841 10:59:20.629997 <6>[ 5.056146] cros-ec-spi spi0.0: Chrome EC device registered
10842 10:59:20.636361 <6>[ 5.059103] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10843 10:59:20.639850 <6>[ 5.072220] mmcblk0: mmc0:0001 DA4128 116 GiB
10844 10:59:20.655112 <6>[ 5.082790] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10845 10:59:20.661936 <6>[ 5.085828] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10846 10:59:20.668330 <6>[ 5.094267] NET: Registered PF_PACKET protocol family
10847 10:59:20.671589 <6>[ 5.099205] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10848 10:59:20.678358 <6>[ 5.103467] 9pnet: Installing 9P2000 support
10849 10:59:20.681654 <6>[ 5.109239] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10850 10:59:20.688377 <5>[ 5.113133] Key type dns_resolver registered
10851 10:59:20.694848 <6>[ 5.118902] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10852 10:59:20.698699 <6>[ 5.123447] registered taskstats version 1
10853 10:59:20.701666 <5>[ 5.133741] Loading compiled-in X.509 certificates
10854 10:59:20.737161 <4>[ 5.161539] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10855 10:59:20.747344 <4>[ 5.172206] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10856 10:59:20.757257 <3>[ 5.185057] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10857 10:59:20.769426 <6>[ 5.200462] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10858 10:59:20.776464 <6>[ 5.207215] xhci-mtk 11200000.usb: xHCI Host Controller
10859 10:59:20.782920 <6>[ 5.212715] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10860 10:59:20.792897 <6>[ 5.220573] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10861 10:59:20.799449 <6>[ 5.230001] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10862 10:59:20.806045 <6>[ 5.236230] xhci-mtk 11200000.usb: xHCI Host Controller
10863 10:59:20.812753 <6>[ 5.241726] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10864 10:59:20.819247 <6>[ 5.249386] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10865 10:59:20.826427 <6>[ 5.257260] hub 1-0:1.0: USB hub found
10866 10:59:20.829449 <6>[ 5.261295] hub 1-0:1.0: 1 port detected
10867 10:59:20.839580 <6>[ 5.265645] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10868 10:59:20.843038 <6>[ 5.274453] hub 2-0:1.0: USB hub found
10869 10:59:20.846120 <6>[ 5.278488] hub 2-0:1.0: 1 port detected
10870 10:59:20.854649 <6>[ 5.285786] mtk-msdc 11f70000.mmc: Got CD GPIO
10871 10:59:20.872334 <6>[ 5.299990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10872 10:59:20.879355 <6>[ 5.308032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10873 10:59:20.888902 <4>[ 5.315995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10874 10:59:20.899047 <6>[ 5.325648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10875 10:59:20.905807 <6>[ 5.333729] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10876 10:59:20.912271 <6>[ 5.341752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10877 10:59:20.922112 <6>[ 5.349666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10878 10:59:20.928493 <6>[ 5.357487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10879 10:59:20.938464 <6>[ 5.365314] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10880 10:59:20.948474 <6>[ 5.376076] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10881 10:59:20.958232 <6>[ 5.384447] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10882 10:59:20.965018 <6>[ 5.392794] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10883 10:59:20.974665 <6>[ 5.401136] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10884 10:59:20.981786 <6>[ 5.409488] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10885 10:59:20.991409 <6>[ 5.417830] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10886 10:59:20.997965 <6>[ 5.426172] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10887 10:59:21.007563 <6>[ 5.434514] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10888 10:59:21.014666 <6>[ 5.442857] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10889 10:59:21.024544 <6>[ 5.451199] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10890 10:59:21.031052 <6>[ 5.459542] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10891 10:59:21.041086 <6>[ 5.467885] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10892 10:59:21.047502 <6>[ 5.476234] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10893 10:59:21.057361 <6>[ 5.484580] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10894 10:59:21.063796 <6>[ 5.492928] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10895 10:59:21.070836 <6>[ 5.501836] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10896 10:59:21.078330 <6>[ 5.509283] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10897 10:59:21.085297 <6>[ 5.516323] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10898 10:59:21.095853 <6>[ 5.523431] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10899 10:59:21.102634 <6>[ 5.530713] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10900 10:59:21.112729 <6>[ 5.537615] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10901 10:59:21.119108 <6>[ 5.546756] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10902 10:59:21.128923 <6>[ 5.555883] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10903 10:59:21.138342 <6>[ 5.565185] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10904 10:59:21.148387 <6>[ 5.574660] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10905 10:59:21.158226 <6>[ 5.584133] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10906 10:59:21.164777 <6>[ 5.593260] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10907 10:59:21.174915 <6>[ 5.602734] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10908 10:59:21.184982 <6>[ 5.611860] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10909 10:59:21.195001 <6>[ 5.621172] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10910 10:59:21.204823 <6>[ 5.631338] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10911 10:59:21.214962 <6>[ 5.642819] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10912 10:59:21.235634 <6>[ 5.663576] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10913 10:59:21.262628 <6>[ 5.694177] hub 2-1:1.0: USB hub found
10914 10:59:21.266695 <6>[ 5.698582] hub 2-1:1.0: 3 ports detected
10915 10:59:21.387813 <6>[ 5.815567] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10916 10:59:21.542201 <6>[ 5.973377] hub 1-1:1.0: USB hub found
10917 10:59:21.545453 <6>[ 5.977810] hub 1-1:1.0: 4 ports detected
10918 10:59:21.623697 <6>[ 6.051826] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10919 10:59:21.867310 <6>[ 6.295575] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10920 10:59:21.999973 <6>[ 6.431592] hub 1-1.4:1.0: USB hub found
10921 10:59:22.003442 <6>[ 6.436246] hub 1-1.4:1.0: 2 ports detected
10922 10:59:22.299494 <6>[ 6.727568] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10923 10:59:22.491604 <6>[ 6.919569] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10924 10:59:33.496043 <6>[ 17.932162] ALSA device list:
10925 10:59:33.502437 <6>[ 17.935415] No soundcards found.
10926 10:59:33.515233 <6>[ 17.947864] Freeing unused kernel memory: 8384K
10927 10:59:33.518221 <6>[ 17.952792] Run /init as init process
10928 10:59:33.548726 <6>[ 17.981692] NET: Registered PF_INET6 protocol family
10929 10:59:33.555400 <6>[ 17.988029] Segment Routing with IPv6
10930 10:59:33.559094 <6>[ 17.991977] In-situ OAM (IOAM) with IPv6
10931 10:59:33.593146 <30>[ 18.006365] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10932 10:59:33.596559 <30>[ 18.030330] systemd[1]: Detected architecture arm64.
10933 10:59:33.599957
10934 10:59:33.603061 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10935 10:59:33.603185
10936 10:59:33.618959 <30>[ 18.051688] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10937 10:59:33.750037 <30>[ 18.179644] systemd[1]: Queued start job for default target Graphical Interface.
10938 10:59:33.792169 <30>[ 18.224778] systemd[1]: Created slice system-getty.slice.
10939 10:59:33.798535 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10940 10:59:33.815221 <30>[ 18.248166] systemd[1]: Created slice system-modprobe.slice.
10941 10:59:33.822101 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10942 10:59:33.839956 <30>[ 18.272689] systemd[1]: Created slice system-serial\x2dgetty.slice.
10943 10:59:33.850093 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10944 10:59:33.863487 <30>[ 18.296065] systemd[1]: Created slice User and Session Slice.
10945 10:59:33.869662 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10946 10:59:33.890791 <30>[ 18.320122] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10947 10:59:33.900479 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10948 10:59:33.918736 <30>[ 18.347741] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10949 10:59:33.924933 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10950 10:59:33.945685 <30>[ 18.371657] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10951 10:59:33.952112 <30>[ 18.383692] systemd[1]: Reached target Local Encrypted Volumes.
10952 10:59:33.958586 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10953 10:59:33.974999 <30>[ 18.407638] systemd[1]: Reached target Paths.
10954 10:59:33.978111 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10955 10:59:33.994912 <30>[ 18.427605] systemd[1]: Reached target Remote File Systems.
10956 10:59:34.001073 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10957 10:59:34.014843 <30>[ 18.447573] systemd[1]: Reached target Slices.
10958 10:59:34.017952 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10959 10:59:34.035033 <30>[ 18.467623] systemd[1]: Reached target Swap.
10960 10:59:34.037856 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10961 10:59:34.058113 <30>[ 18.487853] systemd[1]: Listening on initctl Compatibility Named Pipe.
10962 10:59:34.064653 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10963 10:59:34.071356 <30>[ 18.502573] systemd[1]: Listening on Journal Audit Socket.
10964 10:59:34.078238 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10965 10:59:34.091109 <30>[ 18.523862] systemd[1]: Listening on Journal Socket (/dev/log).
10966 10:59:34.097363 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10967 10:59:34.115331 <30>[ 18.548351] systemd[1]: Listening on Journal Socket.
10968 10:59:34.122059 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10969 10:59:34.135166 <30>[ 18.567906] systemd[1]: Listening on udev Control Socket.
10970 10:59:34.141753 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10971 10:59:34.159448 <30>[ 18.592245] systemd[1]: Listening on udev Kernel Socket.
10972 10:59:34.165869 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10973 10:59:34.202865 <30>[ 18.635890] systemd[1]: Mounting Huge Pages File System...
10974 10:59:34.209483 Mounting [0;1;39mHuge Pages File System[0m...
10975 10:59:34.224814 <30>[ 18.657739] systemd[1]: Mounting POSIX Message Queue File System...
10976 10:59:34.231519 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10977 10:59:34.248707 <30>[ 18.681675] systemd[1]: Mounting Kernel Debug File System...
10978 10:59:34.255933 Mounting [0;1;39mKernel Debug File System[0m...
10979 10:59:34.274477 <30>[ 18.703887] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10980 10:59:34.285389 <30>[ 18.714945] systemd[1]: Starting Create list of static device nodes for the current kernel...
10981 10:59:34.292124 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10982 10:59:34.309443 <30>[ 18.741941] systemd[1]: Starting Load Kernel Module configfs...
10983 10:59:34.315738 Starting [0;1;39mLoad Kernel Module configfs[0m...
10984 10:59:34.333447 <30>[ 18.766043] systemd[1]: Starting Load Kernel Module drm...
10985 10:59:34.339610 Starting [0;1;39mLoad Kernel Module drm[0m...
10986 10:59:34.358114 <30>[ 18.787746] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10987 10:59:34.368961 <30>[ 18.801617] systemd[1]: Starting Journal Service...
10988 10:59:34.372164 Starting [0;1;39mJournal Service[0m...
10989 10:59:34.389292 <30>[ 18.822229] systemd[1]: Starting Load Kernel Modules...
10990 10:59:34.395883 Starting [0;1;39mLoad Kernel Modules[0m...
10991 10:59:34.416500 <30>[ 18.846019] systemd[1]: Starting Remount Root and Kernel File Systems...
10992 10:59:34.422899 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10993 10:59:34.437648 <30>[ 18.870507] systemd[1]: Starting Coldplug All udev Devices...
10994 10:59:34.444081 Starting [0;1;39mColdplug All udev Devices[0m...
10995 10:59:34.461680 <30>[ 18.894580] systemd[1]: Mounted Huge Pages File System.
10996 10:59:34.468319 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10997 10:59:34.483602 <30>[ 18.916371] systemd[1]: Started Journal Service.
10998 10:59:34.490196 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10999 10:59:34.504314 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11000 10:59:34.519465 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11001 10:59:34.539928 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11002 10:59:34.556527 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11003 10:59:34.572725 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11004 10:59:34.588207 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11005 10:59:34.607953 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11006 10:59:34.622769 See 'systemctl status systemd-remount-fs.service' for details.
11007 10:59:34.671248 Mounting [0;1;39mKernel Configuration File System[0m...
11008 10:59:34.693352 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11009 10:59:34.711289 <46>[ 19.141081] systemd-journald[174]: Received client request to flush runtime journal.
11010 10:59:34.720082 Starting [0;1;39mLoad/Save Random Seed[0m...
11011 10:59:34.738308 Starting [0;1;39mApply Kernel Variables[0m...
11012 10:59:34.757676 Starting [0;1;39mCreate System Users[0m...
11013 10:59:34.776566 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11014 10:59:34.795033 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11015 10:59:34.807971 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11016 10:59:34.823623 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11017 10:59:34.839713 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11018 10:59:34.855770 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11019 10:59:34.899417 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11020 10:59:34.921961 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11021 10:59:34.935171 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11022 10:59:34.950393 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11023 10:59:35.002824 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11024 10:59:35.026235 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11025 10:59:35.043554 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11026 10:59:35.064085 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11027 10:59:35.084376 Starting [0;1;39mNetwork Time Synchronization[0m...
11028 10:59:35.105938 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11029 10:59:35.136723 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11030 10:59:35.191510 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11031 10:59:35.211876 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11032 10:59:35.234294 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11033 10:59:35.247733 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11034 10:59:35.270258 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchron<6>[ 19.701017] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11035 10:59:35.273265 ized[0m.
11036 10:59:35.286438 <3>[ 19.715973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11037 10:59:35.292935 <3>[ 19.724201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 10:59:35.299332 <6>[ 19.729385] remoteproc remoteproc0: scp is available
11039 10:59:35.305957 <3>[ 19.732539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 10:59:35.315838 <4>[ 19.738196] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11041 10:59:35.325902 <6>[ 19.754286] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11042 10:59:35.329189 <6>[ 19.755899] remoteproc remoteproc0: powering up scp
11043 10:59:35.338868 <3>[ 19.756525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 10:59:35.345768 <3>[ 19.756544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11045 10:59:35.355897 <3>[ 19.756553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11046 10:59:35.362281 <3>[ 19.756573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11047 10:59:35.372055 <3>[ 19.756588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 10:59:35.378819 <3>[ 19.761266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 10:59:35.388634 <6>[ 19.763168] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11050 10:59:35.398510 <4>[ 19.768297] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11051 10:59:35.405314 <6>[ 19.776374] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11052 10:59:35.414825 <3>[ 19.780345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 10:59:35.421515 <3>[ 19.780375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11054 10:59:35.431274 <3>[ 19.780387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11055 10:59:35.437992 <3>[ 19.784473] remoteproc remoteproc0: request_firmware failed: -2
11056 10:59:35.444619 <3>[ 19.801616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 10:59:35.448193 <6>[ 19.840109] mc: Linux media interface: v0.10
11058 10:59:35.457689 <3>[ 19.844157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11059 10:59:35.464718 <4>[ 19.851693] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11060 10:59:35.471273 <4>[ 19.861947] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11061 10:59:35.481180 <3>[ 19.868465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11062 10:59:35.487659 <3>[ 19.868481] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 10:59:35.497589 <3>[ 19.868488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11064 10:59:35.504418 <3>[ 19.872585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11065 10:59:35.510992 <6>[ 19.894198] videodev: Linux video capture interface: v2.00
11066 10:59:35.517184 <6>[ 19.903421] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11067 10:59:35.523856 <6>[ 19.910843] usbcore: registered new interface driver r8152
11068 10:59:35.530627 <6>[ 19.916172] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11069 10:59:35.537281 <6>[ 19.916182] pci_bus 0000:00: root bus resource [bus 00-ff]
11070 10:59:35.544006 <6>[ 19.916189] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11071 10:59:35.553710 <6>[ 19.916195] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11072 10:59:35.560254 <6>[ 19.916226] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11073 10:59:35.566849 <6>[ 19.916244] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11074 10:59:35.573358 <6>[ 19.916315] pci 0000:00:00.0: supports D1 D2
11075 10:59:35.579867 <6>[ 19.916319] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11076 10:59:35.586520 <6>[ 19.918095] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11077 10:59:35.593556 <6>[ 19.918196] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11078 10:59:35.599982 <6>[ 19.918225] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11079 10:59:35.609667 <6>[ 19.918244] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11080 10:59:35.616457 <6>[ 19.918262] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11081 10:59:35.619822 <6>[ 19.918379] pci 0000:01:00.0: supports D1 D2
11082 10:59:35.629463 <4>[ 19.949997] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11083 10:59:35.633317 <4>[ 19.949997] Fallback method does not support PEC.
11084 10:59:35.639432 <6>[ 19.956169] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11085 10:59:35.649527 <6>[ 19.960006] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11086 10:59:35.659555 <6>[ 19.971896] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11087 10:59:35.666133 <6>[ 19.978282] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11088 10:59:35.675713 <6>[ 19.982052] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11089 10:59:35.682279 <3>[ 19.992119] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11090 10:59:35.688935 <6>[ 19.998160] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11091 10:59:35.695669 <6>[ 20.008220] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11092 10:59:35.705455 <6>[ 20.010631] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11093 10:59:35.712121 <4>[ 20.039414] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11094 10:59:35.722101 <6>[ 20.046545] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11095 10:59:35.728669 <4>[ 20.053965] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11096 10:59:35.738563 <6>[ 20.058516] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11097 10:59:35.745332 <3>[ 20.107662] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11098 10:59:35.748572 <6>[ 20.113088] pci 0000:00:00.0: PCI bridge to [bus 01]
11099 10:59:35.755120 <6>[ 20.135680] r8152 2-1.3:1.0 eth0: v1.12.13
11100 10:59:35.761657 <6>[ 20.142647] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11101 10:59:35.768689 <6>[ 20.200048] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11102 10:59:35.775199 [[0;32m OK [<6>[ 20.207744] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11103 10:59:35.782261 0m] Started [0;<6>[ 20.214678] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11104 10:59:35.792381 1;39mDiscard unused blocks once <3>[ 20.223533] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11105 10:59:35.792468 a week[0m.
11106 10:59:35.801642 <3>[ 20.230865] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
11107 10:59:35.808412 <6>[ 20.238643] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11108 10:59:35.822305 [[0;32m OK [0m] Reached targ<3>[ 20.250211] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11109 10:59:35.825836 et [0;1;39mTimers[0m.
11110 10:59:35.835543 <6>[ 20.268713] usbcore: registered new interface driver cdc_ether
11111 10:59:35.845406 [[0;32m OK [0m] Listening on<6>[ 20.279873] Bluetooth: Core ver 2.22
11112 10:59:35.855199 [0;1;39mD-Bus <6>[ 20.281604] usbcore: registered new interface driver r8153_ecm
11113 10:59:35.861730 System Message B<6>[ 20.285147] NET: Registered PF_BLUETOOTH protocol family
11114 10:59:35.861846 us Socket[0m.
11115 10:59:35.871880 <5>[ 20.295104] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11116 10:59:35.878250 <6>[ 20.299460] Bluetooth: HCI device and connection manager initialized
11117 10:59:35.881393 <6>[ 20.299484] Bluetooth: HCI socket layer initialized
11118 10:59:35.888420 <6>[ 20.301002] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11119 10:59:35.901664 <6>[ 20.302318] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11120 10:59:35.908235 <6>[ 20.302604] usbcore: registered new interface driver uvcvideo
11121 10:59:35.914642 <6>[ 20.308106] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11122 10:59:35.921114 <5>[ 20.323484] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11123 10:59:35.927665 <6>[ 20.327663] Bluetooth: L2CAP socket layer initialized
11124 10:59:35.931126 <6>[ 20.328574] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11125 10:59:35.937510 <6>[ 20.332448] remoteproc remoteproc0: powering up scp
11126 10:59:35.947434 <4>[ 20.332500] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11127 10:59:35.954345 <3>[ 20.332508] remoteproc remoteproc0: request_firmware failed: -2
11128 10:59:35.960583 <3>[ 20.332512] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11129 10:59:35.967302 <6>[ 20.399670] Bluetooth: SCO socket layer initialized
11130 10:59:35.974414 <4>[ 20.404288] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11131 10:59:35.981263 [[0;32m OK [<6>[ 20.413726] cfg80211: failed to load regulatory.db
11132 10:59:35.984904 0m] Reached target [0;1;39mSockets[0m.
11133 10:59:35.993797 <6>[ 20.426609] usbcore: registered new interface driver btusb
11134 10:59:36.004085 <3>[ 20.427162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11135 10:59:36.013768 <4>[ 20.427203] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11136 10:59:36.020276 <3>[ 20.427226] Bluetooth: hci0: Failed to load firmware file (-2)
11137 10:59:36.027246 <3>[ 20.427231] Bluetooth: hci0: Failed to set up firmware (-2)
11138 10:59:36.037893 <4>[ 20.427235] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11139 10:59:36.044238 <3>[ 20.428012] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11140 10:59:36.053961 <3>[ 20.434790] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11141 10:59:36.064284 <3>[ 20.435644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11142 10:59:36.070885 <6>[ 20.455864] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11143 10:59:36.077698 <3>[ 20.469922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11144 10:59:36.084142 <6>[ 20.474352] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11145 10:59:36.093835 <3>[ 20.504886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11146 10:59:36.100639 <6>[ 20.528731] mt7921e 0000:01:00.0: ASIC revision: 79610010
11147 10:59:36.103800 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11148 10:59:36.125283 <3>[ 20.555372] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11149 10:59:36.143053 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11150 10:59:36.156724 <3>[ 20.586438] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11151 10:59:36.172523 Starting [0;1;39mUser Login Management[0m...
11152 10:59:36.189762 <3>[ 20.619373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11153 10:59:36.201584 Starting [0;1;39mPermit User Sessions[0m...
11154 10:59:36.221621 <4>[ 20.647436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11155 10:59:36.228059 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11156 10:59:36.256917 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11157 10:59:36.352037 <4>[ 20.778386] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11158 10:59:36.442058 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11159 10:59:36.471652 [[0;32m OK [<4>[ 20.898686] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11160 10:59:36.478308 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11161 10:59:36.485585 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11162 10:59:36.502275 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11163 10:59:36.543827 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11164 10:59:36.590707 [[0;32m OK [<4>[ 21.018361] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11165 10:59:36.597295 0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11166 10:59:36.605084 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11167 10:59:36.618935 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11168 10:59:36.634518 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11169 10:59:36.674884 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11170 10:59:36.714985 Starting [0;1;39mUpdate UTMP about System Runlevel Cha<4>[ 21.140431] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11171 10:59:36.715172 nges[0m...
11172 10:59:36.740336 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11173 10:59:36.763020 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11174 10:59:36.779763 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11175 10:59:36.803355 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11176 10:59:36.837240 <4>[ 21.263638] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11177 10:59:36.858059
11178 10:59:36.858216
11179 10:59:36.860996 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11180 10:59:36.861081
11181 10:59:36.864314 debian-bullseye-arm64 login: root (automatic login)
11182 10:59:36.864390
11183 10:59:36.864453
11184 10:59:36.880547 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11185 10:59:36.880683
11186 10:59:36.887000 The programs included with the Debian GNU/Linux system are free software;
11187 10:59:36.893961 the exact distribution terms for each program are described in the
11188 10:59:36.897313 individual files in /usr/share/doc/*/copyright.
11189 10:59:36.897395
11190 10:59:36.903743 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11191 10:59:36.906764 permitted by applicable law.
11192 10:59:36.907095 Matched prompt #10: / #
11194 10:59:36.907307 Setting prompt string to ['/ #']
11195 10:59:36.907411 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11197 10:59:36.907621 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11198 10:59:36.907721 start: 2.2.6 expect-shell-connection (timeout 00:02:53) [common]
11199 10:59:36.907793 Setting prompt string to ['/ #']
11200 10:59:36.907856 Forcing a shell prompt, looking for ['/ #']
11202 10:59:36.958078 / #
11203 10:59:36.958265 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11204 10:59:36.958380 Waiting using forced prompt support (timeout 00:02:30)
11205 10:59:36.958515 <4>[ 21.382206] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11206 10:59:36.963429
11207 10:59:37.005386 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11208 10:59:37.005860 start: 2.2.7 export-device-env (timeout 00:02:53) [common]
11209 10:59:37.006234 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11210 10:59:37.006558 end: 2.2 depthcharge-retry (duration 00:02:07) [common]
11211 10:59:37.006878 end: 2 depthcharge-action (duration 00:02:07) [common]
11212 10:59:37.007274 start: 3 lava-test-retry (timeout 00:05:00) [common]
11213 10:59:37.007672 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11214 10:59:37.008024 Using namespace: common
11216 10:59:37.108919 / # #
11217 10:59:37.109171 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11218 10:59:37.109426 #<4>[ 21.502182] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11219 10:59:37.113949
11220 10:59:37.114293 Using /lava-10591025
11222 10:59:37.214973 / # export SHELL=/bin/sh
11223 10:59:37.215192 export SHELL=/bin/sh<4>[ 21.621549] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11224 10:59:37.220029
11226 10:59:37.320682 / # . /lava-10591025/environment
11227 10:59:37.321204 . /lava-10591025/environment<4>[ 21.741421] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11228 10:59:37.326554
11230 10:59:37.470410 / # /lava-10591025/bin/lava-test-runner /lava-10591025/0
11231 10:59:37.470799 Test shell timeout: 10s (minimum of the action and connection timeout)
11232 10:59:37.472140 <3>[ 21.860002] mt7921e 0000:01:00.0: hardware init failed
11233 10:59:37.476022 /lava-10591025/bin/lava-test-run591025/0
11234 10:59:37.479228 -sh: 5: /lava-10591025/bin/lava-test-run591025/0: not found
11235 11:00:03.764664 / # <6>[ 48.203638] vpu: disabling
11236 11:00:03.767766 <6>[ 48.206696] vproc2: disabling
11237 11:00:03.770820 <6>[ 48.209977] vproc1: disabling
11238 11:00:03.774225 <6>[ 48.213239] vaud18: disabling
11239 11:00:03.781027 <6>[ 48.216647] vsram_others: disabling
11240 11:00:03.784130 <6>[ 48.220521] va09: disabling
11241 11:00:03.787627 <6>[ 48.223625] vsram_md: disabling
11242 11:00:03.790691 <6>[ 48.227109] Vgpu: disabling
11244 11:04:37.007889 end: 3.1 lava-test-shell (duration 00:05:00) [common]
11246 11:04:37.008286 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 300 seconds'
11248 11:04:37.008442 end: 3 lava-test-retry (duration 00:05:00) [common]
11250 11:04:37.008660 Cleaning after the job
11251 11:04:37.008751 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/ramdisk
11252 11:04:37.018755 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/kernel
11253 11:04:37.035482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/dtb
11254 11:04:37.035703 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591025/tftp-deploy-op8g5veo/modules
11255 11:04:37.041013 start: 4.1 power-off (timeout 00:00:30) [common]
11256 11:04:37.041183 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11257 11:04:37.120320 >> Command sent successfully.
11258 11:04:37.122676 Returned 0 in 0 seconds
11259 11:04:37.223052 end: 4.1 power-off (duration 00:00:00) [common]
11261 11:04:37.223381 start: 4.2 read-feedback (timeout 00:10:00) [common]
11262 11:04:37.223640 Listened to connection for namespace 'common' for up to 1s
11263 11:04:38.224579 Finalising connection for namespace 'common'
11264 11:04:38.224773 Disconnecting from shell: Finalise
11265 11:04:38.325203 end: 4.2 read-feedback (duration 00:00:01) [common]
11266 11:04:38.325374 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591025
11267 11:04:38.468621 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591025
11268 11:04:38.469239 TestError: A test failed to run, look at the error message.