Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 71
1 10:54:53.735141 lava-dispatcher, installed at version: 2023.05.1
2 10:54:53.735335 start: 0 validate
3 10:54:53.735465 Start time: 2023-06-05 10:54:53.735457+00:00 (UTC)
4 10:54:53.735579 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:54:53.735709 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:54:54.034912 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:54:54.035723 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:54:54.335221 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:54:54.335468 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:54:54.629698 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:54:54.630487 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:54:54.925809 validate duration: 1.19
14 10:54:54.926185 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:54:54.926331 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:54:54.926464 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:54:54.926642 Not decompressing ramdisk as can be used compressed.
18 10:54:54.926799 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 10:54:54.926901 saving as /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/ramdisk/rootfs.cpio.gz
20 10:54:54.926995 total size: 27151647 (25MB)
21 10:54:54.928470 progress 0% (0MB)
22 10:54:54.939870 progress 5% (1MB)
23 10:54:54.950856 progress 10% (2MB)
24 10:54:54.960879 progress 15% (3MB)
25 10:54:54.968863 progress 20% (5MB)
26 10:54:54.976003 progress 25% (6MB)
27 10:54:54.982762 progress 30% (7MB)
28 10:54:54.989686 progress 35% (9MB)
29 10:54:54.996376 progress 40% (10MB)
30 10:54:55.003075 progress 45% (11MB)
31 10:54:55.009921 progress 50% (12MB)
32 10:54:55.016588 progress 55% (14MB)
33 10:54:55.023397 progress 60% (15MB)
34 10:54:55.030060 progress 65% (16MB)
35 10:54:55.036960 progress 70% (18MB)
36 10:54:55.043717 progress 75% (19MB)
37 10:54:55.050385 progress 80% (20MB)
38 10:54:55.057351 progress 85% (22MB)
39 10:54:55.063842 progress 90% (23MB)
40 10:54:55.070535 progress 95% (24MB)
41 10:54:55.077174 progress 100% (25MB)
42 10:54:55.077362 25MB downloaded in 0.15s (172.21MB/s)
43 10:54:55.077518 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:54:55.077753 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:54:55.077846 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:54:55.077971 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:54:55.078102 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:54:55.078177 saving as /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/kernel/Image
50 10:54:55.078239 total size: 45746688 (43MB)
51 10:54:55.078299 No compression specified
52 10:54:55.079416 progress 0% (0MB)
53 10:54:55.091044 progress 5% (2MB)
54 10:54:55.102414 progress 10% (4MB)
55 10:54:55.113700 progress 15% (6MB)
56 10:54:55.124834 progress 20% (8MB)
57 10:54:55.136072 progress 25% (10MB)
58 10:54:55.147608 progress 30% (13MB)
59 10:54:55.159082 progress 35% (15MB)
60 10:54:55.170456 progress 40% (17MB)
61 10:54:55.181987 progress 45% (19MB)
62 10:54:55.193470 progress 50% (21MB)
63 10:54:55.204752 progress 55% (24MB)
64 10:54:55.216060 progress 60% (26MB)
65 10:54:55.227386 progress 65% (28MB)
66 10:54:55.238718 progress 70% (30MB)
67 10:54:55.250147 progress 75% (32MB)
68 10:54:55.261533 progress 80% (34MB)
69 10:54:55.272947 progress 85% (37MB)
70 10:54:55.284365 progress 90% (39MB)
71 10:54:55.295673 progress 95% (41MB)
72 10:54:55.306907 progress 100% (43MB)
73 10:54:55.307027 43MB downloaded in 0.23s (190.69MB/s)
74 10:54:55.307173 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:54:55.307405 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:54:55.307494 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:54:55.307583 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:54:55.307720 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:54:55.307799 saving as /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/dtb/mt8192-asurada-spherion-r0.dtb
81 10:54:55.307862 total size: 46924 (0MB)
82 10:54:55.307924 No compression specified
83 10:54:55.309074 progress 69% (0MB)
84 10:54:55.309344 progress 100% (0MB)
85 10:54:55.309496 0MB downloaded in 0.00s (27.42MB/s)
86 10:54:55.309618 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:54:55.309840 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:54:55.309926 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:54:55.310011 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:54:55.310121 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:54:55.310190 saving as /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/modules/modules.tar
93 10:54:55.310252 total size: 8542412 (8MB)
94 10:54:55.310313 Using unxz to decompress xz
95 10:54:55.313631 progress 0% (0MB)
96 10:54:55.334863 progress 5% (0MB)
97 10:54:55.359329 progress 10% (0MB)
98 10:54:55.385251 progress 15% (1MB)
99 10:54:55.409445 progress 20% (1MB)
100 10:54:55.434207 progress 25% (2MB)
101 10:54:55.458780 progress 30% (2MB)
102 10:54:55.483815 progress 35% (2MB)
103 10:54:55.507985 progress 40% (3MB)
104 10:54:55.532850 progress 45% (3MB)
105 10:54:55.555823 progress 50% (4MB)
106 10:54:55.578440 progress 55% (4MB)
107 10:54:55.605009 progress 60% (4MB)
108 10:54:55.630984 progress 65% (5MB)
109 10:54:55.656710 progress 70% (5MB)
110 10:54:55.683820 progress 75% (6MB)
111 10:54:55.714471 progress 80% (6MB)
112 10:54:55.738057 progress 85% (6MB)
113 10:54:55.764317 progress 90% (7MB)
114 10:54:55.787535 progress 95% (7MB)
115 10:54:55.811106 progress 100% (8MB)
116 10:54:55.816681 8MB downloaded in 0.51s (16.09MB/s)
117 10:54:55.816964 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:54:55.817224 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:54:55.817317 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:54:55.817411 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:54:55.817495 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:54:55.817581 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:54:55.817807 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv
125 10:54:55.817934 makedir: /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin
126 10:54:55.818036 makedir: /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/tests
127 10:54:55.818133 makedir: /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/results
128 10:54:55.818248 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-add-keys
129 10:54:55.818398 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-add-sources
130 10:54:55.818523 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-background-process-start
131 10:54:55.818649 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-background-process-stop
132 10:54:55.818772 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-common-functions
133 10:54:55.818893 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-echo-ipv4
134 10:54:55.819013 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-install-packages
135 10:54:55.819133 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-installed-packages
136 10:54:55.819252 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-os-build
137 10:54:55.819372 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-probe-channel
138 10:54:55.819492 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-probe-ip
139 10:54:55.819611 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-target-ip
140 10:54:55.819735 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-target-mac
141 10:54:55.819853 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-target-storage
142 10:54:55.819976 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-case
143 10:54:55.820095 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-event
144 10:54:55.820213 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-feedback
145 10:54:55.820331 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-raise
146 10:54:55.820451 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-reference
147 10:54:55.820607 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-runner
148 10:54:55.820727 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-set
149 10:54:55.820848 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-test-shell
150 10:54:55.820969 Updating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-install-packages (oe)
151 10:54:55.821118 Updating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/bin/lava-installed-packages (oe)
152 10:54:55.821235 Creating /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/environment
153 10:54:55.821333 LAVA metadata
154 10:54:55.821414 - LAVA_JOB_ID=10591017
155 10:54:55.821480 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:54:55.821584 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:54:55.821652 skipped lava-vland-overlay
158 10:54:55.821729 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:54:55.821811 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:54:55.821875 skipped lava-multinode-overlay
161 10:54:55.821948 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:54:55.822031 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:54:55.822106 Loading test definitions
164 10:54:55.822201 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:54:55.822274 Using /lava-10591017 at stage 0
166 10:54:55.822596 uuid=10591017_1.5.2.3.1 testdef=None
167 10:54:55.822684 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:54:55.822770 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:54:55.823276 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:54:55.823502 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:54:55.824097 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:54:55.824333 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:54:55.824941 runner path: /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10591017_1.5.2.3.1
176 10:54:55.825092 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:54:55.825299 Creating lava-test-runner.conf files
179 10:54:55.825362 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591017/lava-overlay-l6rye2uv/lava-10591017/0 for stage 0
180 10:54:55.825449 - 0_v4l2-compliance-mtk-vcodec-enc
181 10:54:55.825543 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:54:55.825629 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:54:55.832076 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:54:55.832179 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:54:55.832266 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:54:55.832353 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:54:55.832443 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:54:56.537577 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:54:56.537944 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:54:56.538064 extracting modules file /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591017/extract-overlay-ramdisk-sypmbuwq/ramdisk
191 10:54:56.750160 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:54:56.750331 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:54:56.750434 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591017/compress-overlay-zsotaxx6/overlay-1.5.2.4.tar.gz to ramdisk
194 10:54:56.750509 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591017/compress-overlay-zsotaxx6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591017/extract-overlay-ramdisk-sypmbuwq/ramdisk
195 10:54:56.756865 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:54:56.756980 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:54:56.757074 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:54:56.757163 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:54:56.757242 Building ramdisk /var/lib/lava/dispatcher/tmp/10591017/extract-overlay-ramdisk-sypmbuwq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591017/extract-overlay-ramdisk-sypmbuwq/ramdisk
200 10:54:57.287815 >> 230336 blocks
201 10:55:01.497095 rename /var/lib/lava/dispatcher/tmp/10591017/extract-overlay-ramdisk-sypmbuwq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/ramdisk/ramdisk.cpio.gz
202 10:55:01.497556 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:55:01.497711 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 10:55:01.497846 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 10:55:01.497987 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/kernel/Image'
206 10:55:13.077219 Returned 0 in 11 seconds
207 10:55:13.178234 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/kernel/image.itb
208 10:55:13.807962 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:55:13.808317 output: Created: Mon Jun 5 11:55:13 2023
210 10:55:13.808393 output: Image 0 (kernel-1)
211 10:55:13.808459 output: Description:
212 10:55:13.808577 output: Created: Mon Jun 5 11:55:13 2023
213 10:55:13.808641 output: Type: Kernel Image
214 10:55:13.808702 output: Compression: lzma compressed
215 10:55:13.808760 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
216 10:55:13.808818 output: Architecture: AArch64
217 10:55:13.808877 output: OS: Linux
218 10:55:13.808936 output: Load Address: 0x00000000
219 10:55:13.808994 output: Entry Point: 0x00000000
220 10:55:13.809049 output: Hash algo: crc32
221 10:55:13.809103 output: Hash value: 8ce42972
222 10:55:13.809156 output: Image 1 (fdt-1)
223 10:55:13.809209 output: Description: mt8192-asurada-spherion-r0
224 10:55:13.809261 output: Created: Mon Jun 5 11:55:13 2023
225 10:55:13.809314 output: Type: Flat Device Tree
226 10:55:13.809366 output: Compression: uncompressed
227 10:55:13.809419 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:55:13.809472 output: Architecture: AArch64
229 10:55:13.809524 output: Hash algo: crc32
230 10:55:13.809577 output: Hash value: 1df858fa
231 10:55:13.809629 output: Image 2 (ramdisk-1)
232 10:55:13.809681 output: Description: unavailable
233 10:55:13.809733 output: Created: Mon Jun 5 11:55:13 2023
234 10:55:13.809785 output: Type: RAMDisk Image
235 10:55:13.809837 output: Compression: Unknown Compression
236 10:55:13.809890 output: Data Size: 40141485 Bytes = 39200.67 KiB = 38.28 MiB
237 10:55:13.809942 output: Architecture: AArch64
238 10:55:13.809994 output: OS: Linux
239 10:55:13.810047 output: Load Address: unavailable
240 10:55:13.810109 output: Entry Point: unavailable
241 10:55:13.810162 output: Hash algo: crc32
242 10:55:13.810214 output: Hash value: 2a6d0fa2
243 10:55:13.810266 output: Default Configuration: 'conf-1'
244 10:55:13.810318 output: Configuration 0 (conf-1)
245 10:55:13.810388 output: Description: mt8192-asurada-spherion-r0
246 10:55:13.810449 output: Kernel: kernel-1
247 10:55:13.810514 output: Init Ramdisk: ramdisk-1
248 10:55:13.810573 output: FDT: fdt-1
249 10:55:13.810625 output: Loadables: kernel-1
250 10:55:13.810677 output:
251 10:55:13.810883 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 10:55:13.810982 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 10:55:13.811089 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 10:55:13.811179 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 10:55:13.811258 No LXC device requested
256 10:55:13.811335 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:55:13.811422 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 10:55:13.811499 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:55:13.811568 Checking files for TFTP limit of 4294967296 bytes.
260 10:55:13.812043 end: 1 tftp-deploy (duration 00:00:19) [common]
261 10:55:13.812144 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:55:13.812233 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:55:13.812353 substitutions:
264 10:55:13.812421 - {DTB}: 10591017/tftp-deploy-nytt7b6b/dtb/mt8192-asurada-spherion-r0.dtb
265 10:55:13.812486 - {INITRD}: 10591017/tftp-deploy-nytt7b6b/ramdisk/ramdisk.cpio.gz
266 10:55:13.812592 - {KERNEL}: 10591017/tftp-deploy-nytt7b6b/kernel/Image
267 10:55:13.812651 - {LAVA_MAC}: None
268 10:55:13.812708 - {PRESEED_CONFIG}: None
269 10:55:13.812764 - {PRESEED_LOCAL}: None
270 10:55:13.812820 - {RAMDISK}: 10591017/tftp-deploy-nytt7b6b/ramdisk/ramdisk.cpio.gz
271 10:55:13.812875 - {ROOT_PART}: None
272 10:55:13.812929 - {ROOT}: None
273 10:55:13.812983 - {SERVER_IP}: 192.168.201.1
274 10:55:13.813037 - {TEE}: None
275 10:55:13.813104 Parsed boot commands:
276 10:55:13.813159 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:55:13.813333 Parsed boot commands: tftpboot 192.168.201.1 10591017/tftp-deploy-nytt7b6b/kernel/image.itb 10591017/tftp-deploy-nytt7b6b/kernel/cmdline
278 10:55:13.813430 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:55:13.813515 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:55:13.813606 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:55:13.813687 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:55:13.813758 Not connected, no need to disconnect.
283 10:55:13.813831 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:55:13.813910 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:55:13.813975 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
286 10:55:13.817168 Setting prompt string to ['lava-test: # ']
287 10:55:13.817513 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:55:13.817619 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:55:13.817714 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:55:13.817808 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:55:13.818004 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 10:55:18.950591 >> Command sent successfully.
293 10:55:18.953074 Returned 0 in 5 seconds
294 10:55:19.053490 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:55:19.054048 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:55:19.054145 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:55:19.054234 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:55:19.054302 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:55:19.054374 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:55:19.054624 [Enter `^Ec?' for help]
302 10:55:19.228682
303 10:55:19.228845
304 10:55:19.228919 F0: 102B 0000
305 10:55:19.228984
306 10:55:19.229045 F3: 1001 0000 [0200]
307 10:55:19.229105
308 10:55:19.232341 F3: 1001 0000
309 10:55:19.232426
310 10:55:19.232494 F7: 102D 0000
311 10:55:19.232597
312 10:55:19.232660 F1: 0000 0000
313 10:55:19.232720
314 10:55:19.236585 V0: 0000 0000 [0001]
315 10:55:19.236670
316 10:55:19.236738 00: 0007 8000
317 10:55:19.236802
318 10:55:19.239919 01: 0000 0000
319 10:55:19.240004
320 10:55:19.240071 BP: 0C00 0209 [0000]
321 10:55:19.240133
322 10:55:19.243778 G0: 1182 0000
323 10:55:19.243883
324 10:55:19.243952 EC: 0000 0021 [4000]
325 10:55:19.244016
326 10:55:19.247011 S7: 0000 0000 [0000]
327 10:55:19.247095
328 10:55:19.247161 CC: 0000 0000 [0001]
329 10:55:19.247223
330 10:55:19.250891 T0: 0000 0040 [010F]
331 10:55:19.251017
332 10:55:19.251133 Jump to BL
333 10:55:19.251198
334 10:55:19.275581
335 10:55:19.275696
336 10:55:19.275767
337 10:55:19.282067 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:55:19.285805 ARM64: Exception handlers installed.
339 10:55:19.289642 ARM64: Testing exception
340 10:55:19.292521 ARM64: Done test exception
341 10:55:19.299854 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:55:19.310718 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:55:19.317673 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:55:19.328752 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:55:19.335233 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:55:19.341377 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:55:19.351857 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:55:19.358882 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:55:19.378040 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:55:19.381188 WDT: Last reset was cold boot
351 10:55:19.384619 SPI1(PAD0) initialized at 2873684 Hz
352 10:55:19.388231 SPI5(PAD0) initialized at 992727 Hz
353 10:55:19.391129 VBOOT: Loading verstage.
354 10:55:19.398104 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:55:19.401138 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:55:19.404423 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:55:19.407699 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:55:19.415320 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:55:19.422112 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:55:19.433531 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 10:55:19.433630
362 10:55:19.433699
363 10:55:19.442982 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:55:19.446669 ARM64: Exception handlers installed.
365 10:55:19.449935 ARM64: Testing exception
366 10:55:19.450020 ARM64: Done test exception
367 10:55:19.456126 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:55:19.459910 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:55:19.473950 Probing TPM: . done!
370 10:55:19.474042 TPM ready after 0 ms
371 10:55:19.480758 Connected to device vid:did:rid of 1ae0:0028:00
372 10:55:19.491072 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 10:55:19.529076 Initialized TPM device CR50 revision 0
374 10:55:19.542132 tlcl_send_startup: Startup return code is 0
375 10:55:19.542254 TPM: setup succeeded
376 10:55:19.553950 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:55:19.562256 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:55:19.573002 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:55:19.582478 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:55:19.585559 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:55:19.588930 in-header: 03 07 00 00 08 00 00 00
382 10:55:19.592533 in-data: aa e4 47 04 13 02 00 00
383 10:55:19.595546 Chrome EC: UHEPI supported
384 10:55:19.602073 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:55:19.605608 in-header: 03 ad 00 00 08 00 00 00
386 10:55:19.608892 in-data: 00 20 20 08 00 00 00 00
387 10:55:19.608976 Phase 1
388 10:55:19.612377 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:55:19.619733 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:55:19.625753 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:55:19.628684 Recovery requested (1009000e)
392 10:55:19.633360 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:55:19.640818 tlcl_extend: response is 0
394 10:55:19.649540 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:55:19.654915 tlcl_extend: response is 0
396 10:55:19.660888 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:55:19.681708 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:55:19.688790 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:55:19.688883
400 10:55:19.688949
401 10:55:19.699381 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:55:19.702445 ARM64: Exception handlers installed.
403 10:55:19.702533 ARM64: Testing exception
404 10:55:19.706011 ARM64: Done test exception
405 10:55:19.727732 pmic_efuse_setting: Set efuses in 11 msecs
406 10:55:19.731511 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:55:19.735369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:55:19.741508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:55:19.745120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:55:19.752020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:55:19.754555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:55:19.762135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:55:19.764803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:55:19.771345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:55:19.774598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:55:19.778091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:55:19.784675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:55:19.788304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:55:19.794661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:55:19.797958 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:55:19.804630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:55:19.810903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:55:19.817836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:55:19.820773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:55:19.827751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:55:19.834337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:55:19.837660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:55:19.845365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:55:19.852377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:55:19.855433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:55:19.862616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:55:19.865766 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:55:19.872871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:55:19.876234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:55:19.879875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:55:19.887065 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:55:19.890505 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:55:19.897577 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:55:19.900211 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:55:19.906976 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:55:19.910354 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:55:19.916965 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:55:19.920101 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:55:19.926700 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:55:19.930654 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:55:19.933971 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:55:19.938223 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:55:19.945107 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:55:19.948293 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:55:19.951410 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:55:19.958257 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:55:19.961388 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:55:19.964828 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:55:19.971206 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:55:19.974740 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:55:19.978283 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:55:19.981242 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:55:19.991317 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:55:19.998017 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:55:20.004647 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:55:20.011540 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:55:20.020931 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:55:20.024302 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:55:20.027706 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:55:20.034994 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:55:20.041092 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
467 10:55:20.044483 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:55:20.051340 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 10:55:20.055218 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:55:20.064257 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 10:55:20.074105 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 10:55:20.083777 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 10:55:20.092655 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 10:55:20.102662 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 10:55:20.112056 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 10:55:20.121685 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 10:55:20.124372 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 10:55:20.132349 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 10:55:20.135499 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:55:20.140391 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:55:20.145245 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:55:20.148425 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:55:20.152090 ADC[4]: Raw value=906357 ID=7
484 10:55:20.152173 ADC[3]: Raw value=213282 ID=1
485 10:55:20.155273 RAM Code: 0x71
486 10:55:20.158804 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:55:20.165248 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:55:20.171695 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:55:20.178299 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:55:20.181994 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:55:20.185502 in-header: 03 07 00 00 08 00 00 00
492 10:55:20.188206 in-data: aa e4 47 04 13 02 00 00
493 10:55:20.192273 Chrome EC: UHEPI supported
494 10:55:20.198444 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:55:20.201632 in-header: 03 dd 00 00 08 00 00 00
496 10:55:20.205058 in-data: 90 20 60 08 00 00 00 00
497 10:55:20.208724 MRC: failed to locate region type 0.
498 10:55:20.215147 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:55:20.218015 DRAM-K: Running full calibration
500 10:55:20.225388 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:55:20.225472 header.status = 0x0
502 10:55:20.227777 header.version = 0x6 (expected: 0x6)
503 10:55:20.231185 header.size = 0xd00 (expected: 0xd00)
504 10:55:20.235451 header.flags = 0x0
505 10:55:20.241437 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:55:20.258065 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 10:55:20.264558 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:55:20.268274 dram_init: ddr_geometry: 2
509 10:55:20.271689 [EMI] MDL number = 2
510 10:55:20.271771 [EMI] Get MDL freq = 0
511 10:55:20.274463 dram_init: ddr_type: 0
512 10:55:20.274545 is_discrete_lpddr4: 1
513 10:55:20.278196 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:55:20.278279
515 10:55:20.281463
516 10:55:20.281572 [Bian_co] ETT version 0.0.0.1
517 10:55:20.288261 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:55:20.288345
519 10:55:20.291287 dramc_set_vcore_voltage set vcore to 650000
520 10:55:20.294357 Read voltage for 800, 4
521 10:55:20.294440 Vio18 = 0
522 10:55:20.294506 Vcore = 650000
523 10:55:20.297686 Vdram = 0
524 10:55:20.297768 Vddq = 0
525 10:55:20.297834 Vmddr = 0
526 10:55:20.301487 dram_init: config_dvfs: 1
527 10:55:20.304452 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:55:20.311276 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:55:20.315105 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 10:55:20.317638 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 10:55:20.320893 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 10:55:20.327479 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 10:55:20.327563 MEM_TYPE=3, freq_sel=18
534 10:55:20.331059 sv_algorithm_assistance_LP4_1600
535 10:55:20.334102 ============ PULL DRAM RESETB DOWN ============
536 10:55:20.341452 ========== PULL DRAM RESETB DOWN end =========
537 10:55:20.344474 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:55:20.347533 ===================================
539 10:55:20.350596 LPDDR4 DRAM CONFIGURATION
540 10:55:20.354191 ===================================
541 10:55:20.354275 EX_ROW_EN[0] = 0x0
542 10:55:20.357492 EX_ROW_EN[1] = 0x0
543 10:55:20.357575 LP4Y_EN = 0x0
544 10:55:20.361419 WORK_FSP = 0x0
545 10:55:20.361501 WL = 0x2
546 10:55:20.364447 RL = 0x2
547 10:55:20.364563 BL = 0x2
548 10:55:20.367222 RPST = 0x0
549 10:55:20.370663 RD_PRE = 0x0
550 10:55:20.370746 WR_PRE = 0x1
551 10:55:20.373947 WR_PST = 0x0
552 10:55:20.374030 DBI_WR = 0x0
553 10:55:20.377905 DBI_RD = 0x0
554 10:55:20.377987 OTF = 0x1
555 10:55:20.380490 ===================================
556 10:55:20.384090 ===================================
557 10:55:20.384172 ANA top config
558 10:55:20.387781 ===================================
559 10:55:20.390732 DLL_ASYNC_EN = 0
560 10:55:20.393946 ALL_SLAVE_EN = 1
561 10:55:20.397348 NEW_RANK_MODE = 1
562 10:55:20.400750 DLL_IDLE_MODE = 1
563 10:55:20.400832 LP45_APHY_COMB_EN = 1
564 10:55:20.403967 TX_ODT_DIS = 1
565 10:55:20.407245 NEW_8X_MODE = 1
566 10:55:20.410797 ===================================
567 10:55:20.413842 ===================================
568 10:55:20.417431 data_rate = 1600
569 10:55:20.420418 CKR = 1
570 10:55:20.420503 DQ_P2S_RATIO = 8
571 10:55:20.423715 ===================================
572 10:55:20.427654 CA_P2S_RATIO = 8
573 10:55:20.430694 DQ_CA_OPEN = 0
574 10:55:20.433999 DQ_SEMI_OPEN = 0
575 10:55:20.436950 CA_SEMI_OPEN = 0
576 10:55:20.440489 CA_FULL_RATE = 0
577 10:55:20.440623 DQ_CKDIV4_EN = 1
578 10:55:20.444446 CA_CKDIV4_EN = 1
579 10:55:20.447102 CA_PREDIV_EN = 0
580 10:55:20.450423 PH8_DLY = 0
581 10:55:20.453717 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:55:20.457191 DQ_AAMCK_DIV = 4
583 10:55:20.457323 CA_AAMCK_DIV = 4
584 10:55:20.460390 CA_ADMCK_DIV = 4
585 10:55:20.464093 DQ_TRACK_CA_EN = 0
586 10:55:20.467305 CA_PICK = 800
587 10:55:20.470968 CA_MCKIO = 800
588 10:55:20.474010 MCKIO_SEMI = 0
589 10:55:20.477584 PLL_FREQ = 3068
590 10:55:20.477687 DQ_UI_PI_RATIO = 32
591 10:55:20.480426 CA_UI_PI_RATIO = 0
592 10:55:20.483903 ===================================
593 10:55:20.487386 ===================================
594 10:55:20.490465 memory_type:LPDDR4
595 10:55:20.493658 GP_NUM : 10
596 10:55:20.493744 SRAM_EN : 1
597 10:55:20.496927 MD32_EN : 0
598 10:55:20.500635 ===================================
599 10:55:20.503577 [ANA_INIT] >>>>>>>>>>>>>>
600 10:55:20.503661 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:55:20.506756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:55:20.510454 ===================================
603 10:55:20.513380 data_rate = 1600,PCW = 0X7600
604 10:55:20.516675 ===================================
605 10:55:20.520097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:55:20.527023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:55:20.533934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:55:20.536449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:55:20.540202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:55:20.543224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:55:20.546840 [ANA_INIT] flow start
612 10:55:20.546923 [ANA_INIT] PLL >>>>>>>>
613 10:55:20.550232 [ANA_INIT] PLL <<<<<<<<
614 10:55:20.553582 [ANA_INIT] MIDPI >>>>>>>>
615 10:55:20.553667 [ANA_INIT] MIDPI <<<<<<<<
616 10:55:20.556643 [ANA_INIT] DLL >>>>>>>>
617 10:55:20.560065 [ANA_INIT] flow end
618 10:55:20.563478 ============ LP4 DIFF to SE enter ============
619 10:55:20.566663 ============ LP4 DIFF to SE exit ============
620 10:55:20.570082 [ANA_INIT] <<<<<<<<<<<<<
621 10:55:20.573149 [Flow] Enable top DCM control >>>>>
622 10:55:20.576408 [Flow] Enable top DCM control <<<<<
623 10:55:20.580117 Enable DLL master slave shuffle
624 10:55:20.583677 ==============================================================
625 10:55:20.586359 Gating Mode config
626 10:55:20.593320 ==============================================================
627 10:55:20.593404 Config description:
628 10:55:20.603006 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:55:20.609566 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:55:20.616709 SELPH_MODE 0: By rank 1: By Phase
631 10:55:20.619753 ==============================================================
632 10:55:20.622990 GAT_TRACK_EN = 1
633 10:55:20.626150 RX_GATING_MODE = 2
634 10:55:20.629552 RX_GATING_TRACK_MODE = 2
635 10:55:20.632824 SELPH_MODE = 1
636 10:55:20.636245 PICG_EARLY_EN = 1
637 10:55:20.639663 VALID_LAT_VALUE = 1
638 10:55:20.642481 ==============================================================
639 10:55:20.645853 Enter into Gating configuration >>>>
640 10:55:20.649671 Exit from Gating configuration <<<<
641 10:55:20.652352 Enter into DVFS_PRE_config >>>>>
642 10:55:20.665978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:55:20.669067 Exit from DVFS_PRE_config <<<<<
644 10:55:20.672397 Enter into PICG configuration >>>>
645 10:55:20.675611 Exit from PICG configuration <<<<
646 10:55:20.675693 [RX_INPUT] configuration >>>>>
647 10:55:20.678999 [RX_INPUT] configuration <<<<<
648 10:55:20.685542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:55:20.689028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:55:20.696399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:55:20.703528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:55:20.707523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:55:20.714462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:55:20.717982 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:55:20.721880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:55:20.729051 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:55:20.732601 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:55:20.736061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:55:20.740210 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:55:20.743234 ===================================
661 10:55:20.746821 LPDDR4 DRAM CONFIGURATION
662 10:55:20.751245 ===================================
663 10:55:20.751329 EX_ROW_EN[0] = 0x0
664 10:55:20.754078 EX_ROW_EN[1] = 0x0
665 10:55:20.754162 LP4Y_EN = 0x0
666 10:55:20.758359 WORK_FSP = 0x0
667 10:55:20.758443 WL = 0x2
668 10:55:20.761718 RL = 0x2
669 10:55:20.761802 BL = 0x2
670 10:55:20.764953 RPST = 0x0
671 10:55:20.765037 RD_PRE = 0x0
672 10:55:20.765104 WR_PRE = 0x1
673 10:55:20.768796 WR_PST = 0x0
674 10:55:20.768880 DBI_WR = 0x0
675 10:55:20.772726 DBI_RD = 0x0
676 10:55:20.772810 OTF = 0x1
677 10:55:20.777111 ===================================
678 10:55:20.780176 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:55:20.783555 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:55:20.790901 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:55:20.794440 ===================================
682 10:55:20.794524 LPDDR4 DRAM CONFIGURATION
683 10:55:20.797846 ===================================
684 10:55:20.801688 EX_ROW_EN[0] = 0x10
685 10:55:20.801771 EX_ROW_EN[1] = 0x0
686 10:55:20.805661 LP4Y_EN = 0x0
687 10:55:20.805745 WORK_FSP = 0x0
688 10:55:20.810016 WL = 0x2
689 10:55:20.810101 RL = 0x2
690 10:55:20.813024 BL = 0x2
691 10:55:20.813108 RPST = 0x0
692 10:55:20.813175 RD_PRE = 0x0
693 10:55:20.817478 WR_PRE = 0x1
694 10:55:20.817562 WR_PST = 0x0
695 10:55:20.820905 DBI_WR = 0x0
696 10:55:20.820991 DBI_RD = 0x0
697 10:55:20.824369 OTF = 0x1
698 10:55:20.827901 ===================================
699 10:55:20.831578 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:55:20.836692 nWR fixed to 40
701 10:55:20.840817 [ModeRegInit_LP4] CH0 RK0
702 10:55:20.840901 [ModeRegInit_LP4] CH0 RK1
703 10:55:20.843515 [ModeRegInit_LP4] CH1 RK0
704 10:55:20.847236 [ModeRegInit_LP4] CH1 RK1
705 10:55:20.847320 match AC timing 13
706 10:55:20.853984 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:55:20.857138 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:55:20.860286 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:55:20.864348 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:55:20.870936 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:55:20.871021 [EMI DOE] emi_dcm 0
712 10:55:20.877704 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:55:20.877788 ==
714 10:55:20.880468 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:55:20.883602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:55:20.883686 ==
717 10:55:20.890510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:55:20.893785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:55:20.904400 [CA 0] Center 37 (7~68) winsize 62
720 10:55:20.907014 [CA 1] Center 37 (6~68) winsize 63
721 10:55:20.910601 [CA 2] Center 34 (4~65) winsize 62
722 10:55:20.914378 [CA 3] Center 34 (4~65) winsize 62
723 10:55:20.917563 [CA 4] Center 33 (3~64) winsize 62
724 10:55:20.921207 [CA 5] Center 33 (3~64) winsize 62
725 10:55:20.921292
726 10:55:20.924106 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:55:20.924190
728 10:55:20.927861 [CATrainingPosCal] consider 1 rank data
729 10:55:20.930726 u2DelayCellTimex100 = 270/100 ps
730 10:55:20.934113 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 10:55:20.937940 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 10:55:20.941088 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 10:55:20.944475 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 10:55:20.951056 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 10:55:20.954435 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 10:55:20.954519
737 10:55:20.957988 CA PerBit enable=1, Macro0, CA PI delay=33
738 10:55:20.958072
739 10:55:20.960991 [CBTSetCACLKResult] CA Dly = 33
740 10:55:20.961076 CS Dly: 7 (0~38)
741 10:55:20.961143 ==
742 10:55:20.964206 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:55:20.970812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:55:20.970897 ==
745 10:55:20.974016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:55:20.980443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:55:20.990064 [CA 0] Center 37 (6~68) winsize 63
748 10:55:20.993522 [CA 1] Center 37 (7~68) winsize 62
749 10:55:20.997305 [CA 2] Center 34 (4~65) winsize 62
750 10:55:20.999976 [CA 3] Center 34 (4~65) winsize 62
751 10:55:21.003615 [CA 4] Center 33 (3~64) winsize 62
752 10:55:21.006803 [CA 5] Center 33 (2~64) winsize 63
753 10:55:21.006887
754 10:55:21.010375 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:55:21.010460
756 10:55:21.013433 [CATrainingPosCal] consider 2 rank data
757 10:55:21.017122 u2DelayCellTimex100 = 270/100 ps
758 10:55:21.019804 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 10:55:21.023152 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 10:55:21.030317 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 10:55:21.033733 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 10:55:21.037571 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 10:55:21.040753 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 10:55:21.040837
765 10:55:21.044278 CA PerBit enable=1, Macro0, CA PI delay=33
766 10:55:21.044362
767 10:55:21.047996 [CBTSetCACLKResult] CA Dly = 33
768 10:55:21.048080 CS Dly: 7 (0~38)
769 10:55:21.048147
770 10:55:21.051831 ----->DramcWriteLeveling(PI) begin...
771 10:55:21.051917 ==
772 10:55:21.054944 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:55:21.059096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:55:21.059181 ==
775 10:55:21.062322 Write leveling (Byte 0): 30 => 30
776 10:55:21.065779 Write leveling (Byte 1): 30 => 30
777 10:55:21.068657 DramcWriteLeveling(PI) end<-----
778 10:55:21.068741
779 10:55:21.068807 ==
780 10:55:21.073112 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:55:21.075401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:55:21.075485 ==
783 10:55:21.079558 [Gating] SW mode calibration
784 10:55:21.085532 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:55:21.092357 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:55:21.096230 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:55:21.099326 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 10:55:21.105547 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 10:55:21.108860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 10:55:21.112221 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:55:21.118675 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:55:21.122050 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:55:21.125803 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:55:21.132126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:55:21.135940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:55:21.139025 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:55:21.145337 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:55:21.148990 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:55:21.152352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:55:21.159632 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:55:21.161943 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:55:21.165534 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:55:21.172067 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 10:55:21.176182 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 10:55:21.178789 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:55:21.185325 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:55:21.188904 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:55:21.192069 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:55:21.198709 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:55:21.202376 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:55:21.205152 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:55:21.208862 0 9 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
813 10:55:21.215109 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
814 10:55:21.218500 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:55:21.221993 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:55:21.228666 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:55:21.232247 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:55:21.235107 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:55:21.241968 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 10:55:21.245502 0 10 8 | B1->B0 | 3434 2828 | 0 0 | (0 1) (1 1)
821 10:55:21.248489 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
822 10:55:21.254878 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:55:21.258945 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:55:21.261486 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:55:21.268768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:55:21.271520 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:55:21.275222 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:55:21.281638 0 11 8 | B1->B0 | 2929 3b3b | 1 0 | (0 0) (1 1)
829 10:55:21.284744 0 11 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
830 10:55:21.288324 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:55:21.294898 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:55:21.298276 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:55:21.301671 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:55:21.308484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:55:21.311413 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 10:55:21.314586 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 10:55:21.321469 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 10:55:21.324686 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:55:21.328196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:55:21.334613 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:55:21.338069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:55:21.341460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:55:21.348205 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:55:21.351530 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:55:21.355112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:55:21.357774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:55:21.364620 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:55:21.367706 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:55:21.372346 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:55:21.378105 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:55:21.381692 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 10:55:21.385387 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:55:21.389432 Total UI for P1: 0, mck2ui 16
854 10:55:21.392543 best dqsien dly found for B0: ( 0, 14, 4)
855 10:55:21.396809 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:55:21.400178 Total UI for P1: 0, mck2ui 16
857 10:55:21.404045 best dqsien dly found for B1: ( 0, 14, 8)
858 10:55:21.407151 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 10:55:21.411353 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 10:55:21.411494
861 10:55:21.414616 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 10:55:21.418629 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:55:21.421915 [Gating] SW calibration Done
864 10:55:21.422024 ==
865 10:55:21.425576 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:55:21.429528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:55:21.429630 ==
868 10:55:21.429697 RX Vref Scan: 0
869 10:55:21.429759
870 10:55:21.432829 RX Vref 0 -> 0, step: 1
871 10:55:21.432914
872 10:55:21.436657 RX Delay -130 -> 252, step: 16
873 10:55:21.440008 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 10:55:21.443739 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 10:55:21.446681 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 10:55:21.450726 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 10:55:21.453576 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 10:55:21.459889 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 10:55:21.463399 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 10:55:21.466977 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 10:55:21.470217 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 10:55:21.473891 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 10:55:21.480602 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 10:55:21.483548 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
885 10:55:21.486657 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
886 10:55:21.490659 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 10:55:21.493803 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 10:55:21.497780 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 10:55:21.501329 ==
890 10:55:21.501423 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:55:21.508812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:55:21.508917 ==
893 10:55:21.509010 DQS Delay:
894 10:55:21.509111 DQS0 = 0, DQS1 = 0
895 10:55:21.512727 DQM Delay:
896 10:55:21.512816 DQM0 = 87, DQM1 = 70
897 10:55:21.512903 DQ Delay:
898 10:55:21.515612 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
899 10:55:21.519090 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
900 10:55:21.522310 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
901 10:55:21.525891 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
902 10:55:21.525985
903 10:55:21.528735
904 10:55:21.528822 ==
905 10:55:21.532314 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:55:21.535753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:55:21.535843 ==
908 10:55:21.535931
909 10:55:21.536012
910 10:55:21.538815 TX Vref Scan disable
911 10:55:21.538926 == TX Byte 0 ==
912 10:55:21.545373 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 10:55:21.548728 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 10:55:21.548813 == TX Byte 1 ==
915 10:55:21.555741 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 10:55:21.559612 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 10:55:21.559697 ==
918 10:55:21.562271 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:55:21.565936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:55:21.566020 ==
921 10:55:21.578654 TX Vref=22, minBit 1, minWin=27, winSum=441
922 10:55:21.582101 TX Vref=24, minBit 5, minWin=27, winSum=443
923 10:55:21.585537 TX Vref=26, minBit 5, minWin=27, winSum=444
924 10:55:21.588443 TX Vref=28, minBit 4, minWin=27, winSum=444
925 10:55:21.591979 TX Vref=30, minBit 8, minWin=27, winSum=446
926 10:55:21.598393 TX Vref=32, minBit 9, minWin=26, winSum=440
927 10:55:21.601519 [TxChooseVref] Worse bit 8, Min win 27, Win sum 446, Final Vref 30
928 10:55:21.601604
929 10:55:21.604874 Final TX Range 1 Vref 30
930 10:55:21.604958
931 10:55:21.605025 ==
932 10:55:21.608423 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:55:21.611654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:55:21.614689 ==
935 10:55:21.614773
936 10:55:21.614840
937 10:55:21.614901 TX Vref Scan disable
938 10:55:21.618842 == TX Byte 0 ==
939 10:55:21.621735 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 10:55:21.625332 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 10:55:21.628629 == TX Byte 1 ==
942 10:55:21.631898 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 10:55:21.638506 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 10:55:21.638591
945 10:55:21.638657 [DATLAT]
946 10:55:21.638719 Freq=800, CH0 RK0
947 10:55:21.638778
948 10:55:21.641724 DATLAT Default: 0xa
949 10:55:21.641808 0, 0xFFFF, sum = 0
950 10:55:21.645195 1, 0xFFFF, sum = 0
951 10:55:21.645283 2, 0xFFFF, sum = 0
952 10:55:21.648254 3, 0xFFFF, sum = 0
953 10:55:21.651835 4, 0xFFFF, sum = 0
954 10:55:21.651920 5, 0xFFFF, sum = 0
955 10:55:21.655095 6, 0xFFFF, sum = 0
956 10:55:21.655179 7, 0xFFFF, sum = 0
957 10:55:21.658284 8, 0xFFFF, sum = 0
958 10:55:21.658369 9, 0x0, sum = 1
959 10:55:21.658436 10, 0x0, sum = 2
960 10:55:21.661873 11, 0x0, sum = 3
961 10:55:21.661956 12, 0x0, sum = 4
962 10:55:21.665159 best_step = 10
963 10:55:21.665242
964 10:55:21.665307 ==
965 10:55:21.668351 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:55:21.672248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:55:21.672332 ==
968 10:55:21.675023 RX Vref Scan: 1
969 10:55:21.675106
970 10:55:21.675172 Set Vref Range= 32 -> 127
971 10:55:21.679014
972 10:55:21.679099 RX Vref 32 -> 127, step: 1
973 10:55:21.679167
974 10:55:21.681901 RX Delay -111 -> 252, step: 8
975 10:55:21.681987
976 10:55:21.685049 Set Vref, RX VrefLevel [Byte0]: 32
977 10:55:21.688484 [Byte1]: 32
978 10:55:21.688616
979 10:55:21.691728 Set Vref, RX VrefLevel [Byte0]: 33
980 10:55:21.694614 [Byte1]: 33
981 10:55:21.698874
982 10:55:21.698957 Set Vref, RX VrefLevel [Byte0]: 34
983 10:55:21.702645 [Byte1]: 34
984 10:55:21.707282
985 10:55:21.707366 Set Vref, RX VrefLevel [Byte0]: 35
986 10:55:21.710135 [Byte1]: 35
987 10:55:21.714159
988 10:55:21.714242 Set Vref, RX VrefLevel [Byte0]: 36
989 10:55:21.717654 [Byte1]: 36
990 10:55:21.722171
991 10:55:21.722293 Set Vref, RX VrefLevel [Byte0]: 37
992 10:55:21.725504 [Byte1]: 37
993 10:55:21.730079
994 10:55:21.730162 Set Vref, RX VrefLevel [Byte0]: 38
995 10:55:21.733296 [Byte1]: 38
996 10:55:21.737119
997 10:55:21.737203 Set Vref, RX VrefLevel [Byte0]: 39
998 10:55:21.740513 [Byte1]: 39
999 10:55:21.744979
1000 10:55:21.745062 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:55:21.748376 [Byte1]: 40
1002 10:55:21.752397
1003 10:55:21.752480 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:55:21.755964 [Byte1]: 41
1005 10:55:21.760467
1006 10:55:21.760557 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:55:21.763935 [Byte1]: 42
1008 10:55:21.767735
1009 10:55:21.767821 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:55:21.771832 [Byte1]: 43
1011 10:55:21.775383
1012 10:55:21.775468 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:55:21.778567 [Byte1]: 44
1014 10:55:21.783478
1015 10:55:21.783579 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:55:21.786885 [Byte1]: 45
1017 10:55:21.791147
1018 10:55:21.791256 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:55:21.794709 [Byte1]: 46
1020 10:55:21.798101
1021 10:55:21.801918 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:55:21.802013 [Byte1]: 47
1023 10:55:21.806535
1024 10:55:21.806621 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:55:21.810269 [Byte1]: 48
1026 10:55:21.813838
1027 10:55:21.813921 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:55:21.817120 [Byte1]: 49
1029 10:55:21.821640
1030 10:55:21.821727 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:55:21.825023 [Byte1]: 50
1032 10:55:21.830467
1033 10:55:21.830550 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:55:21.833018 [Byte1]: 51
1035 10:55:21.836978
1036 10:55:21.837061 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:55:21.840837 [Byte1]: 52
1038 10:55:21.844525
1039 10:55:21.844626 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:55:21.848119 [Byte1]: 53
1041 10:55:21.852139
1042 10:55:21.852222 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:55:21.855931 [Byte1]: 54
1044 10:55:21.859792
1045 10:55:21.859875 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:55:21.862918 [Byte1]: 55
1047 10:55:21.867582
1048 10:55:21.867664 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:55:21.871079 [Byte1]: 56
1050 10:55:21.874981
1051 10:55:21.875064 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:55:21.878650 [Byte1]: 57
1053 10:55:21.882273
1054 10:55:21.882355 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:55:21.889021 [Byte1]: 58
1056 10:55:21.889106
1057 10:55:21.892935 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:55:21.896620 [Byte1]: 59
1059 10:55:21.896702
1060 10:55:21.899347 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:55:21.903109 [Byte1]: 60
1062 10:55:21.903193
1063 10:55:21.906402 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:55:21.910117 [Byte1]: 61
1065 10:55:21.910200
1066 10:55:21.913548 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:55:21.917211 [Byte1]: 62
1068 10:55:21.921208
1069 10:55:21.921293 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:55:21.924919 [Byte1]: 63
1071 10:55:21.928494
1072 10:55:21.928617 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:55:21.932951 [Byte1]: 64
1074 10:55:21.936718
1075 10:55:21.936811 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:55:21.940783 [Byte1]: 65
1077 10:55:21.943705
1078 10:55:21.943787 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:55:21.946942 [Byte1]: 66
1080 10:55:21.951387
1081 10:55:21.951470 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:55:21.954895 [Byte1]: 67
1083 10:55:21.959174
1084 10:55:21.959257 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:55:21.962760 [Byte1]: 68
1086 10:55:21.966814
1087 10:55:21.966898 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:55:21.970576 [Byte1]: 69
1089 10:55:21.974335
1090 10:55:21.974422 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:55:21.977833 [Byte1]: 70
1092 10:55:21.981989
1093 10:55:21.982080 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:55:21.985549 [Byte1]: 71
1095 10:55:21.990105
1096 10:55:21.990194 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:55:21.993284 [Byte1]: 72
1098 10:55:21.997919
1099 10:55:21.998004 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:55:22.001030 [Byte1]: 73
1101 10:55:22.005049
1102 10:55:22.005133 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:55:22.008239 [Byte1]: 74
1104 10:55:22.012488
1105 10:55:22.012598 Set Vref, RX VrefLevel [Byte0]: 75
1106 10:55:22.016387 [Byte1]: 75
1107 10:55:22.020214
1108 10:55:22.020299 Set Vref, RX VrefLevel [Byte0]: 76
1109 10:55:22.023930 [Byte1]: 76
1110 10:55:22.027999
1111 10:55:22.028085 Set Vref, RX VrefLevel [Byte0]: 77
1112 10:55:22.031036 [Byte1]: 77
1113 10:55:22.035393
1114 10:55:22.035477 Set Vref, RX VrefLevel [Byte0]: 78
1115 10:55:22.038523 [Byte1]: 78
1116 10:55:22.043478
1117 10:55:22.043562 Set Vref, RX VrefLevel [Byte0]: 79
1118 10:55:22.046630 [Byte1]: 79
1119 10:55:22.051254
1120 10:55:22.051339 Set Vref, RX VrefLevel [Byte0]: 80
1121 10:55:22.054279 [Byte1]: 80
1122 10:55:22.058810
1123 10:55:22.058894 Set Vref, RX VrefLevel [Byte0]: 81
1124 10:55:22.062783 [Byte1]: 81
1125 10:55:22.066325
1126 10:55:22.066408 Final RX Vref Byte 0 = 65 to rank0
1127 10:55:22.069877 Final RX Vref Byte 1 = 58 to rank0
1128 10:55:22.073315 Final RX Vref Byte 0 = 65 to rank1
1129 10:55:22.077018 Final RX Vref Byte 1 = 58 to rank1==
1130 10:55:22.080488 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 10:55:22.085026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 10:55:22.085113 ==
1133 10:55:22.085181 DQS Delay:
1134 10:55:22.087953 DQS0 = 0, DQS1 = 0
1135 10:55:22.088037 DQM Delay:
1136 10:55:22.091455 DQM0 = 87, DQM1 = 75
1137 10:55:22.091538 DQ Delay:
1138 10:55:22.095262 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1139 10:55:22.098703 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1140 10:55:22.103150 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1141 10:55:22.105934 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1142 10:55:22.106019
1143 10:55:22.106085
1144 10:55:22.114157 [DQSOSCAuto] RK0, (LSB)MR18= 0x4526, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1145 10:55:22.116880 CH0 RK0: MR19=606, MR18=4526
1146 10:55:22.120544 CH0_RK0: MR19=0x606, MR18=0x4526, DQSOSC=392, MR23=63, INC=96, DEC=64
1147 10:55:22.120643
1148 10:55:22.124831 ----->DramcWriteLeveling(PI) begin...
1149 10:55:22.124920 ==
1150 10:55:22.128423 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 10:55:22.131565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 10:55:22.131650 ==
1153 10:55:22.135506 Write leveling (Byte 0): 32 => 32
1154 10:55:22.139460 Write leveling (Byte 1): 30 => 30
1155 10:55:22.142552 DramcWriteLeveling(PI) end<-----
1156 10:55:22.142637
1157 10:55:22.142703 ==
1158 10:55:22.146371 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 10:55:22.150193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 10:55:22.150278 ==
1161 10:55:22.193970 [Gating] SW mode calibration
1162 10:55:22.194307 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 10:55:22.194592 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 10:55:22.194988 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 10:55:22.195550 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1166 10:55:22.195652 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1167 10:55:22.195898 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:55:22.196437 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:55:22.196765 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:55:22.196840 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:55:22.238231 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:55:22.238574 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:55:22.238846 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:55:22.239252 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:55:22.239341 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:55:22.239588 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:55:22.239660 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:55:22.240208 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:55:22.240475 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:55:22.240584 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:55:22.282033 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:55:22.282629 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1183 10:55:22.282716 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1184 10:55:22.283103 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:55:22.283188 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:55:22.283538 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:55:22.283988 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:55:22.284441 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:55:22.285077 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1190 10:55:22.285161 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1191 10:55:22.288132 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1192 10:55:22.294053 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 10:55:22.297486 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 10:55:22.300700 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 10:55:22.307261 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 10:55:22.310180 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 10:55:22.313443 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1198 10:55:22.319989 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (1 1)
1199 10:55:22.323857 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1200 10:55:22.327355 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:55:22.333635 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:55:22.336857 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 10:55:22.340233 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 10:55:22.346672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 10:55:22.349908 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1206 10:55:22.353168 0 11 8 | B1->B0 | 2f2f 3b3b | 1 0 | (0 0) (1 1)
1207 10:55:22.359931 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1208 10:55:22.363444 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 10:55:22.366428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 10:55:22.370028 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 10:55:22.376521 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 10:55:22.379793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 10:55:22.383422 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 10:55:22.389932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1215 10:55:22.393067 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:55:22.396822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:55:22.403278 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:55:22.406731 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:55:22.410228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:55:22.416851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:55:22.420220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:55:22.423586 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:55:22.430010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:55:22.433088 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 10:55:22.436240 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 10:55:22.442938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 10:55:22.446604 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 10:55:22.449652 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 10:55:22.456412 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 10:55:22.459584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1231 10:55:22.463131 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 10:55:22.466156 Total UI for P1: 0, mck2ui 16
1233 10:55:22.469443 best dqsien dly found for B0: ( 0, 14, 8)
1234 10:55:22.472818 Total UI for P1: 0, mck2ui 16
1235 10:55:22.476630 best dqsien dly found for B1: ( 0, 14, 8)
1236 10:55:22.479375 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1237 10:55:22.482514 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1238 10:55:22.482599
1239 10:55:22.486127 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1240 10:55:22.493189 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1241 10:55:22.493275 [Gating] SW calibration Done
1242 10:55:22.493342 ==
1243 10:55:22.496191 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 10:55:22.502711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 10:55:22.502796 ==
1246 10:55:22.502863 RX Vref Scan: 0
1247 10:55:22.502925
1248 10:55:22.505941 RX Vref 0 -> 0, step: 1
1249 10:55:22.506024
1250 10:55:22.509788 RX Delay -130 -> 252, step: 16
1251 10:55:22.513221 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1252 10:55:22.516251 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1253 10:55:22.519294 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1254 10:55:22.525826 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1255 10:55:22.529334 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1256 10:55:22.532546 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1257 10:55:22.535870 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1258 10:55:22.538912 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1259 10:55:22.545714 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1260 10:55:22.548886 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1261 10:55:22.552529 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1262 10:55:22.555681 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1263 10:55:22.558973 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1264 10:55:22.565838 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1265 10:55:22.568811 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1266 10:55:22.572265 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1267 10:55:22.572349 ==
1268 10:55:22.575621 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 10:55:22.579130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 10:55:22.582293 ==
1271 10:55:22.582377 DQS Delay:
1272 10:55:22.582443 DQS0 = 0, DQS1 = 0
1273 10:55:22.585555 DQM Delay:
1274 10:55:22.585638 DQM0 = 83, DQM1 = 76
1275 10:55:22.589219 DQ Delay:
1276 10:55:22.589302 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1277 10:55:22.592396 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1278 10:55:22.595466 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1279 10:55:22.598911 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1280 10:55:22.598995
1281 10:55:22.602032
1282 10:55:22.602115 ==
1283 10:55:22.605567 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 10:55:22.609005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 10:55:22.609090 ==
1286 10:55:22.609157
1287 10:55:22.609216
1288 10:55:22.611865 TX Vref Scan disable
1289 10:55:22.611948 == TX Byte 0 ==
1290 10:55:22.619235 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1291 10:55:22.622132 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1292 10:55:22.622224 == TX Byte 1 ==
1293 10:55:22.628760 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 10:55:22.631745 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 10:55:22.631831 ==
1296 10:55:22.635273 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 10:55:22.639339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 10:55:22.639421 ==
1299 10:55:22.652091 TX Vref=22, minBit 5, minWin=27, winSum=444
1300 10:55:22.655516 TX Vref=24, minBit 8, minWin=27, winSum=447
1301 10:55:22.659519 TX Vref=26, minBit 9, minWin=27, winSum=450
1302 10:55:22.662594 TX Vref=28, minBit 8, minWin=27, winSum=447
1303 10:55:22.665672 TX Vref=30, minBit 8, minWin=27, winSum=447
1304 10:55:22.669047 TX Vref=32, minBit 8, minWin=27, winSum=444
1305 10:55:22.675376 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 26
1306 10:55:22.675459
1307 10:55:22.678631 Final TX Range 1 Vref 26
1308 10:55:22.678713
1309 10:55:22.678777 ==
1310 10:55:22.682357 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 10:55:22.685281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 10:55:22.685364 ==
1313 10:55:22.688858
1314 10:55:22.688939
1315 10:55:22.689004 TX Vref Scan disable
1316 10:55:22.691856 == TX Byte 0 ==
1317 10:55:22.695416 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1318 10:55:22.702053 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1319 10:55:22.702135 == TX Byte 1 ==
1320 10:55:22.705853 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1321 10:55:22.712170 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1322 10:55:22.712253
1323 10:55:22.712317 [DATLAT]
1324 10:55:22.712378 Freq=800, CH0 RK1
1325 10:55:22.712438
1326 10:55:22.716194 DATLAT Default: 0xa
1327 10:55:22.716274 0, 0xFFFF, sum = 0
1328 10:55:22.718797 1, 0xFFFF, sum = 0
1329 10:55:22.718880 2, 0xFFFF, sum = 0
1330 10:55:22.721976 3, 0xFFFF, sum = 0
1331 10:55:22.725557 4, 0xFFFF, sum = 0
1332 10:55:22.725640 5, 0xFFFF, sum = 0
1333 10:55:22.728739 6, 0xFFFF, sum = 0
1334 10:55:22.728821 7, 0xFFFF, sum = 0
1335 10:55:22.732100 8, 0xFFFF, sum = 0
1336 10:55:22.732183 9, 0x0, sum = 1
1337 10:55:22.732249 10, 0x0, sum = 2
1338 10:55:22.735126 11, 0x0, sum = 3
1339 10:55:22.735209 12, 0x0, sum = 4
1340 10:55:22.738483 best_step = 10
1341 10:55:22.738564
1342 10:55:22.738629 ==
1343 10:55:22.742263 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 10:55:22.745621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 10:55:22.745703 ==
1346 10:55:22.748400 RX Vref Scan: 0
1347 10:55:22.748482
1348 10:55:22.748555 RX Vref 0 -> 0, step: 1
1349 10:55:22.748617
1350 10:55:22.751936 RX Delay -111 -> 252, step: 8
1351 10:55:22.759425 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1352 10:55:22.763576 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1353 10:55:22.765739 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1354 10:55:22.769666 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1355 10:55:22.772711 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1356 10:55:22.779533 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1357 10:55:22.782109 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1358 10:55:22.785835 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1359 10:55:22.789231 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1360 10:55:22.792218 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1361 10:55:22.799201 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1362 10:55:22.802312 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1363 10:55:22.805481 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1364 10:55:22.809146 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1365 10:55:22.815379 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1366 10:55:22.818897 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1367 10:55:22.818980 ==
1368 10:55:22.821898 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 10:55:22.825181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 10:55:22.825265 ==
1371 10:55:22.828484 DQS Delay:
1372 10:55:22.828574 DQS0 = 0, DQS1 = 0
1373 10:55:22.828640 DQM Delay:
1374 10:55:22.832713 DQM0 = 86, DQM1 = 76
1375 10:55:22.832795 DQ Delay:
1376 10:55:22.835361 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1377 10:55:22.838323 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1378 10:55:22.842086 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1379 10:55:22.845394 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1380 10:55:22.845475
1381 10:55:22.845540
1382 10:55:22.854864 [DQSOSCAuto] RK1, (LSB)MR18= 0x4209, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1383 10:55:22.854948 CH0 RK1: MR19=606, MR18=4209
1384 10:55:22.861524 CH0_RK1: MR19=0x606, MR18=0x4209, DQSOSC=393, MR23=63, INC=95, DEC=63
1385 10:55:22.864735 [RxdqsGatingPostProcess] freq 800
1386 10:55:22.871850 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1387 10:55:22.875008 Pre-setting of DQS Precalculation
1388 10:55:22.878150 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1389 10:55:22.878231 ==
1390 10:55:22.881742 Dram Type= 6, Freq= 0, CH_1, rank 0
1391 10:55:22.888329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 10:55:22.888412 ==
1393 10:55:22.892345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 10:55:22.898166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 10:55:22.907911 [CA 0] Center 36 (6~67) winsize 62
1396 10:55:22.911330 [CA 1] Center 36 (6~67) winsize 62
1397 10:55:22.914014 [CA 2] Center 34 (4~65) winsize 62
1398 10:55:22.917251 [CA 3] Center 34 (4~65) winsize 62
1399 10:55:22.920453 [CA 4] Center 34 (4~65) winsize 62
1400 10:55:22.923829 [CA 5] Center 34 (3~65) winsize 63
1401 10:55:22.923912
1402 10:55:22.927369 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1403 10:55:22.927452
1404 10:55:22.930518 [CATrainingPosCal] consider 1 rank data
1405 10:55:22.934503 u2DelayCellTimex100 = 270/100 ps
1406 10:55:22.937378 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1407 10:55:22.941221 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 10:55:22.947584 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 10:55:22.950643 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 10:55:22.954261 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 10:55:22.957557 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1412 10:55:22.957638
1413 10:55:22.960944 CA PerBit enable=1, Macro0, CA PI delay=34
1414 10:55:22.961025
1415 10:55:22.964426 [CBTSetCACLKResult] CA Dly = 34
1416 10:55:22.964527 CS Dly: 4 (0~35)
1417 10:55:22.967185 ==
1418 10:55:22.970581 Dram Type= 6, Freq= 0, CH_1, rank 1
1419 10:55:22.974025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 10:55:22.974106 ==
1421 10:55:22.978088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 10:55:22.983936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 10:55:22.994467 [CA 0] Center 36 (6~67) winsize 62
1424 10:55:22.996531 [CA 1] Center 36 (6~67) winsize 62
1425 10:55:23.000199 [CA 2] Center 34 (4~65) winsize 62
1426 10:55:23.003722 [CA 3] Center 34 (3~65) winsize 63
1427 10:55:23.006733 [CA 4] Center 34 (4~65) winsize 62
1428 10:55:23.010337 [CA 5] Center 34 (3~65) winsize 63
1429 10:55:23.010420
1430 10:55:23.013694 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1431 10:55:23.013778
1432 10:55:23.016794 [CATrainingPosCal] consider 2 rank data
1433 10:55:23.020162 u2DelayCellTimex100 = 270/100 ps
1434 10:55:23.023177 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 10:55:23.029997 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 10:55:23.033179 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 10:55:23.036305 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 10:55:23.040087 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1439 10:55:23.043252 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1440 10:55:23.043335
1441 10:55:23.046579 CA PerBit enable=1, Macro0, CA PI delay=34
1442 10:55:23.046663
1443 10:55:23.050359 [CBTSetCACLKResult] CA Dly = 34
1444 10:55:23.050443 CS Dly: 5 (0~38)
1445 10:55:23.053172
1446 10:55:23.056457 ----->DramcWriteLeveling(PI) begin...
1447 10:55:23.056584 ==
1448 10:55:23.059892 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 10:55:23.063218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 10:55:23.063303 ==
1451 10:55:23.066403 Write leveling (Byte 0): 27 => 27
1452 10:55:23.069699 Write leveling (Byte 1): 28 => 28
1453 10:55:23.072903 DramcWriteLeveling(PI) end<-----
1454 10:55:23.072986
1455 10:55:23.073052 ==
1456 10:55:23.076707 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 10:55:23.079782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 10:55:23.079866 ==
1459 10:55:23.082960 [Gating] SW mode calibration
1460 10:55:23.089512 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1461 10:55:23.096349 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1462 10:55:23.099381 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1463 10:55:23.102791 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1464 10:55:23.110073 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1465 10:55:23.112671 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:55:23.116296 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:55:23.122913 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:55:23.125914 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:55:23.129342 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:55:23.136017 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:55:23.139258 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:55:23.142876 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:55:23.149466 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:55:23.152449 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:55:23.156103 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:55:23.162337 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:55:23.165866 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:55:23.169147 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1479 10:55:23.175894 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1480 10:55:23.179137 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:55:23.182171 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:55:23.189083 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:55:23.192175 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:55:23.195613 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:55:23.198617 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:55:23.206496 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:55:23.208711 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:55:23.215618 0 9 8 | B1->B0 | 2a2a 3232 | 0 1 | (0 0) (1 1)
1489 10:55:23.218768 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 10:55:23.221609 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 10:55:23.228328 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 10:55:23.231900 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 10:55:23.235302 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 10:55:23.238838 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 10:55:23.245397 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
1496 10:55:23.248108 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1497 10:55:23.252057 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:55:23.259007 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 10:55:23.261657 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 10:55:23.265005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:55:23.271900 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 10:55:23.274874 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 10:55:23.278057 0 11 4 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (1 1)
1504 10:55:23.284781 0 11 8 | B1->B0 | 3636 3e3e | 0 0 | (0 0) (0 0)
1505 10:55:23.288136 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 10:55:23.291305 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 10:55:23.298400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 10:55:23.301664 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 10:55:23.304370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 10:55:23.311300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 10:55:23.314398 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 10:55:23.318588 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:55:23.324608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:55:23.327736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:55:23.331363 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:55:23.337856 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:55:23.340958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:55:23.344432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:55:23.351029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:55:23.354451 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:55:23.358162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 10:55:23.364490 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 10:55:23.367702 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 10:55:23.371240 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 10:55:23.377364 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 10:55:23.381169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 10:55:23.384339 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1528 10:55:23.391471 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1529 10:55:23.394614 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 10:55:23.397335 Total UI for P1: 0, mck2ui 16
1531 10:55:23.401210 best dqsien dly found for B0: ( 0, 14, 6)
1532 10:55:23.404250 Total UI for P1: 0, mck2ui 16
1533 10:55:23.407414 best dqsien dly found for B1: ( 0, 14, 6)
1534 10:55:23.410611 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1535 10:55:23.414550 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1536 10:55:23.414634
1537 10:55:23.417792 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1538 10:55:23.420532 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1539 10:55:23.423870 [Gating] SW calibration Done
1540 10:55:23.423954 ==
1541 10:55:23.427575 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 10:55:23.430703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 10:55:23.430788 ==
1544 10:55:23.433894 RX Vref Scan: 0
1545 10:55:23.433977
1546 10:55:23.437389 RX Vref 0 -> 0, step: 1
1547 10:55:23.437473
1548 10:55:23.437540 RX Delay -130 -> 252, step: 16
1549 10:55:23.444169 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1550 10:55:23.447203 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1551 10:55:23.451035 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1552 10:55:23.454122 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1553 10:55:23.456888 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1554 10:55:23.463631 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1555 10:55:23.468331 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1556 10:55:23.471041 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1557 10:55:23.473628 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1558 10:55:23.477313 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1559 10:55:23.483918 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1560 10:55:23.487444 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1561 10:55:23.490145 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1562 10:55:23.493824 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 10:55:23.500481 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 10:55:23.504263 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 10:55:23.504364 ==
1566 10:55:23.506897 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 10:55:23.510310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 10:55:23.510404 ==
1569 10:55:23.510472 DQS Delay:
1570 10:55:23.513817 DQS0 = 0, DQS1 = 0
1571 10:55:23.513905 DQM Delay:
1572 10:55:23.517002 DQM0 = 88, DQM1 = 79
1573 10:55:23.517089 DQ Delay:
1574 10:55:23.520659 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1575 10:55:23.524441 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1576 10:55:23.527207 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1577 10:55:23.530610 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1578 10:55:23.530707
1579 10:55:23.530775
1580 10:55:23.530835 ==
1581 10:55:23.533687 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 10:55:23.540128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 10:55:23.540243 ==
1584 10:55:23.540315
1585 10:55:23.540377
1586 10:55:23.540437 TX Vref Scan disable
1587 10:55:23.543935 == TX Byte 0 ==
1588 10:55:23.546995 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1589 10:55:23.553786 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1590 10:55:23.553907 == TX Byte 1 ==
1591 10:55:23.556929 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1592 10:55:23.563396 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1593 10:55:23.563518 ==
1594 10:55:23.566470 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 10:55:23.570042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 10:55:23.570140 ==
1597 10:55:23.582490 TX Vref=22, minBit 0, minWin=27, winSum=443
1598 10:55:23.585635 TX Vref=24, minBit 0, minWin=27, winSum=446
1599 10:55:23.589508 TX Vref=26, minBit 10, minWin=27, winSum=448
1600 10:55:23.592394 TX Vref=28, minBit 13, minWin=27, winSum=452
1601 10:55:23.595680 TX Vref=30, minBit 8, minWin=27, winSum=447
1602 10:55:23.602275 TX Vref=32, minBit 8, minWin=27, winSum=448
1603 10:55:23.605755 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1604 10:55:23.605859
1605 10:55:23.609188 Final TX Range 1 Vref 28
1606 10:55:23.609279
1607 10:55:23.609347 ==
1608 10:55:23.612467 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 10:55:23.615392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 10:55:23.619346 ==
1611 10:55:23.619441
1612 10:55:23.619509
1613 10:55:23.619571 TX Vref Scan disable
1614 10:55:23.622657 == TX Byte 0 ==
1615 10:55:23.626370 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1616 10:55:23.630027 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1617 10:55:23.632792 == TX Byte 1 ==
1618 10:55:23.635962 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1619 10:55:23.639619 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1620 10:55:23.643047
1621 10:55:23.643146 [DATLAT]
1622 10:55:23.643214 Freq=800, CH1 RK0
1623 10:55:23.643275
1624 10:55:23.646047 DATLAT Default: 0xa
1625 10:55:23.646134 0, 0xFFFF, sum = 0
1626 10:55:23.649189 1, 0xFFFF, sum = 0
1627 10:55:23.649278 2, 0xFFFF, sum = 0
1628 10:55:23.652466 3, 0xFFFF, sum = 0
1629 10:55:23.652596 4, 0xFFFF, sum = 0
1630 10:55:23.656332 5, 0xFFFF, sum = 0
1631 10:55:23.656422 6, 0xFFFF, sum = 0
1632 10:55:23.659683 7, 0xFFFF, sum = 0
1633 10:55:23.662753 8, 0xFFFF, sum = 0
1634 10:55:23.662847 9, 0x0, sum = 1
1635 10:55:23.662917 10, 0x0, sum = 2
1636 10:55:23.666055 11, 0x0, sum = 3
1637 10:55:23.666146 12, 0x0, sum = 4
1638 10:55:23.669854 best_step = 10
1639 10:55:23.669944
1640 10:55:23.670011 ==
1641 10:55:23.673133 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 10:55:23.676058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 10:55:23.676151 ==
1644 10:55:23.679584 RX Vref Scan: 1
1645 10:55:23.679671
1646 10:55:23.679739 Set Vref Range= 32 -> 127
1647 10:55:23.679802
1648 10:55:23.682858 RX Vref 32 -> 127, step: 1
1649 10:55:23.682942
1650 10:55:23.686047 RX Delay -95 -> 252, step: 8
1651 10:55:23.686132
1652 10:55:23.689742 Set Vref, RX VrefLevel [Byte0]: 32
1653 10:55:23.692963 [Byte1]: 32
1654 10:55:23.693046
1655 10:55:23.696336 Set Vref, RX VrefLevel [Byte0]: 33
1656 10:55:23.699476 [Byte1]: 33
1657 10:55:23.703376
1658 10:55:23.703459 Set Vref, RX VrefLevel [Byte0]: 34
1659 10:55:23.706165 [Byte1]: 34
1660 10:55:23.710466
1661 10:55:23.710553 Set Vref, RX VrefLevel [Byte0]: 35
1662 10:55:23.714088 [Byte1]: 35
1663 10:55:23.718052
1664 10:55:23.718135 Set Vref, RX VrefLevel [Byte0]: 36
1665 10:55:23.721352 [Byte1]: 36
1666 10:55:23.725810
1667 10:55:23.725895 Set Vref, RX VrefLevel [Byte0]: 37
1668 10:55:23.729331 [Byte1]: 37
1669 10:55:23.733344
1670 10:55:23.733428 Set Vref, RX VrefLevel [Byte0]: 38
1671 10:55:23.736777 [Byte1]: 38
1672 10:55:23.741107
1673 10:55:23.741190 Set Vref, RX VrefLevel [Byte0]: 39
1674 10:55:23.744648 [Byte1]: 39
1675 10:55:23.748394
1676 10:55:23.748478 Set Vref, RX VrefLevel [Byte0]: 40
1677 10:55:23.752263 [Byte1]: 40
1678 10:55:23.756100
1679 10:55:23.756184 Set Vref, RX VrefLevel [Byte0]: 41
1680 10:55:23.759592 [Byte1]: 41
1681 10:55:23.764032
1682 10:55:23.764115 Set Vref, RX VrefLevel [Byte0]: 42
1683 10:55:23.767199 [Byte1]: 42
1684 10:55:23.771647
1685 10:55:23.771731 Set Vref, RX VrefLevel [Byte0]: 43
1686 10:55:23.778228 [Byte1]: 43
1687 10:55:23.778313
1688 10:55:23.780923 Set Vref, RX VrefLevel [Byte0]: 44
1689 10:55:23.784304 [Byte1]: 44
1690 10:55:23.784387
1691 10:55:23.787491 Set Vref, RX VrefLevel [Byte0]: 45
1692 10:55:23.790996 [Byte1]: 45
1693 10:55:23.791081
1694 10:55:23.795241 Set Vref, RX VrefLevel [Byte0]: 46
1695 10:55:23.797411 [Byte1]: 46
1696 10:55:23.801631
1697 10:55:23.801714 Set Vref, RX VrefLevel [Byte0]: 47
1698 10:55:23.804932 [Byte1]: 47
1699 10:55:23.809167
1700 10:55:23.809277 Set Vref, RX VrefLevel [Byte0]: 48
1701 10:55:23.812718 [Byte1]: 48
1702 10:55:23.816938
1703 10:55:23.817021 Set Vref, RX VrefLevel [Byte0]: 49
1704 10:55:23.820096 [Byte1]: 49
1705 10:55:23.824416
1706 10:55:23.824530 Set Vref, RX VrefLevel [Byte0]: 50
1707 10:55:23.827771 [Byte1]: 50
1708 10:55:23.832580
1709 10:55:23.832663 Set Vref, RX VrefLevel [Byte0]: 51
1710 10:55:23.835424 [Byte1]: 51
1711 10:55:23.839544
1712 10:55:23.839627 Set Vref, RX VrefLevel [Byte0]: 52
1713 10:55:23.843035 [Byte1]: 52
1714 10:55:23.847152
1715 10:55:23.847234 Set Vref, RX VrefLevel [Byte0]: 53
1716 10:55:23.851091 [Byte1]: 53
1717 10:55:23.855045
1718 10:55:23.855128 Set Vref, RX VrefLevel [Byte0]: 54
1719 10:55:23.858233 [Byte1]: 54
1720 10:55:23.862798
1721 10:55:23.862885 Set Vref, RX VrefLevel [Byte0]: 55
1722 10:55:23.866130 [Byte1]: 55
1723 10:55:23.870334
1724 10:55:23.870429 Set Vref, RX VrefLevel [Byte0]: 56
1725 10:55:23.873843 [Byte1]: 56
1726 10:55:23.878142
1727 10:55:23.878251 Set Vref, RX VrefLevel [Byte0]: 57
1728 10:55:23.880730 [Byte1]: 57
1729 10:55:23.885217
1730 10:55:23.885385 Set Vref, RX VrefLevel [Byte0]: 58
1731 10:55:23.888720 [Byte1]: 58
1732 10:55:23.892735
1733 10:55:23.892890 Set Vref, RX VrefLevel [Byte0]: 59
1734 10:55:23.896219 [Byte1]: 59
1735 10:55:23.900480
1736 10:55:23.900651 Set Vref, RX VrefLevel [Byte0]: 60
1737 10:55:23.904150 [Byte1]: 60
1738 10:55:23.908202
1739 10:55:23.908364 Set Vref, RX VrefLevel [Byte0]: 61
1740 10:55:23.911610 [Byte1]: 61
1741 10:55:23.916241
1742 10:55:23.916402 Set Vref, RX VrefLevel [Byte0]: 62
1743 10:55:23.918803 [Byte1]: 62
1744 10:55:23.923319
1745 10:55:23.923480 Set Vref, RX VrefLevel [Byte0]: 63
1746 10:55:23.927679 [Byte1]: 63
1747 10:55:23.931188
1748 10:55:23.931348 Set Vref, RX VrefLevel [Byte0]: 64
1749 10:55:23.933946 [Byte1]: 64
1750 10:55:23.938557
1751 10:55:23.938711 Set Vref, RX VrefLevel [Byte0]: 65
1752 10:55:23.941710 [Byte1]: 65
1753 10:55:23.946496
1754 10:55:23.946657 Set Vref, RX VrefLevel [Byte0]: 66
1755 10:55:23.949509 [Byte1]: 66
1756 10:55:23.953603
1757 10:55:23.953757 Set Vref, RX VrefLevel [Byte0]: 67
1758 10:55:23.957449 [Byte1]: 67
1759 10:55:23.961772
1760 10:55:23.961917 Set Vref, RX VrefLevel [Byte0]: 68
1761 10:55:23.964274 [Byte1]: 68
1762 10:55:23.968869
1763 10:55:23.969002 Set Vref, RX VrefLevel [Byte0]: 69
1764 10:55:23.972597 [Byte1]: 69
1765 10:55:23.976944
1766 10:55:23.977075 Set Vref, RX VrefLevel [Byte0]: 70
1767 10:55:23.980245 [Byte1]: 70
1768 10:55:23.984099
1769 10:55:23.984230 Set Vref, RX VrefLevel [Byte0]: 71
1770 10:55:23.987343 [Byte1]: 71
1771 10:55:23.991459
1772 10:55:23.991593 Set Vref, RX VrefLevel [Byte0]: 72
1773 10:55:23.994925 [Byte1]: 72
1774 10:55:24.000419
1775 10:55:24.000599 Set Vref, RX VrefLevel [Byte0]: 73
1776 10:55:24.002366 [Byte1]: 73
1777 10:55:24.007342
1778 10:55:24.007492 Set Vref, RX VrefLevel [Byte0]: 74
1779 10:55:24.010286 [Byte1]: 74
1780 10:55:24.014683
1781 10:55:24.014837 Set Vref, RX VrefLevel [Byte0]: 75
1782 10:55:24.017500 [Byte1]: 75
1783 10:55:24.021953
1784 10:55:24.022103 Final RX Vref Byte 0 = 56 to rank0
1785 10:55:24.025373 Final RX Vref Byte 1 = 63 to rank0
1786 10:55:24.028567 Final RX Vref Byte 0 = 56 to rank1
1787 10:55:24.032193 Final RX Vref Byte 1 = 63 to rank1==
1788 10:55:24.035440 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 10:55:24.042078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 10:55:24.042228 ==
1791 10:55:24.042354 DQS Delay:
1792 10:55:24.042474 DQS0 = 0, DQS1 = 0
1793 10:55:24.045109 DQM Delay:
1794 10:55:24.045254 DQM0 = 86, DQM1 = 79
1795 10:55:24.048842 DQ Delay:
1796 10:55:24.052366 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1797 10:55:24.055617 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1798 10:55:24.058613 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1799 10:55:24.062102 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1800 10:55:24.062252
1801 10:55:24.062387
1802 10:55:24.068778 [DQSOSCAuto] RK0, (LSB)MR18= 0x321f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1803 10:55:24.071855 CH1 RK0: MR19=606, MR18=321F
1804 10:55:24.078399 CH1_RK0: MR19=0x606, MR18=0x321F, DQSOSC=397, MR23=63, INC=93, DEC=62
1805 10:55:24.078543
1806 10:55:24.081684 ----->DramcWriteLeveling(PI) begin...
1807 10:55:24.081838 ==
1808 10:55:24.084809 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 10:55:24.088473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 10:55:24.088671 ==
1811 10:55:24.091972 Write leveling (Byte 0): 26 => 26
1812 10:55:24.095087 Write leveling (Byte 1): 31 => 31
1813 10:55:24.098222 DramcWriteLeveling(PI) end<-----
1814 10:55:24.098376
1815 10:55:24.098512 ==
1816 10:55:24.101644 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 10:55:24.104848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 10:55:24.104999 ==
1819 10:55:24.108270 [Gating] SW mode calibration
1820 10:55:24.115047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 10:55:24.121243 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 10:55:24.125092 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 10:55:24.131273 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1824 10:55:24.134434 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1825 10:55:24.137681 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:55:24.144222 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:55:24.147871 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:55:24.151047 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:55:24.158117 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:55:24.160797 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:55:24.164478 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:55:24.170658 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:55:24.174032 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:55:24.177466 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:55:24.184071 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:55:24.187376 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:55:24.191554 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:55:24.197152 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 10:55:24.200505 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1840 10:55:24.203789 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1841 10:55:24.210634 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:55:24.214168 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:55:24.216986 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:55:24.223734 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:55:24.227476 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:55:24.230946 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:55:24.233970 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:55:24.240470 0 9 8 | B1->B0 | 3232 2827 | 1 1 | (1 1) (1 1)
1849 10:55:24.243980 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 10:55:24.247395 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 10:55:24.254162 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 10:55:24.256837 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 10:55:24.260044 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 10:55:24.267151 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 10:55:24.270094 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1856 10:55:24.273271 0 10 8 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (1 0)
1857 10:55:24.280138 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 10:55:24.283052 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:55:24.286715 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 10:55:24.293055 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 10:55:24.296475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:55:24.299877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 10:55:24.306684 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1864 10:55:24.309626 0 11 8 | B1->B0 | 4545 3232 | 0 1 | (0 0) (0 0)
1865 10:55:24.312827 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 10:55:24.319870 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 10:55:24.323471 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 10:55:24.326665 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 10:55:24.333169 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 10:55:24.335768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 10:55:24.339370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 10:55:24.346272 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:55:24.349193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:55:24.352511 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:55:24.359347 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:55:24.362678 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:55:24.365806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:55:24.372491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:55:24.376055 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 10:55:24.378883 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 10:55:24.386026 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 10:55:24.389472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 10:55:24.392572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 10:55:24.399233 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 10:55:24.402127 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 10:55:24.405376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1887 10:55:24.412283 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1888 10:55:24.415038 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 10:55:24.418343 Total UI for P1: 0, mck2ui 16
1890 10:55:24.422240 best dqsien dly found for B0: ( 0, 14, 6)
1891 10:55:24.425515 Total UI for P1: 0, mck2ui 16
1892 10:55:24.428879 best dqsien dly found for B1: ( 0, 14, 2)
1893 10:55:24.431757 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1894 10:55:24.435038 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1895 10:55:24.435180
1896 10:55:24.438416 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 10:55:24.441521 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1898 10:55:24.445160 [Gating] SW calibration Done
1899 10:55:24.445311 ==
1900 10:55:24.448152 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 10:55:24.451607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 10:55:24.455226 ==
1903 10:55:24.455376 RX Vref Scan: 0
1904 10:55:24.455505
1905 10:55:24.458748 RX Vref 0 -> 0, step: 1
1906 10:55:24.458892
1907 10:55:24.461526 RX Delay -130 -> 252, step: 16
1908 10:55:24.465012 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1909 10:55:24.468024 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1910 10:55:24.471447 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1911 10:55:24.475163 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1912 10:55:24.481734 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1913 10:55:24.484441 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1914 10:55:24.487805 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1915 10:55:24.491430 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1916 10:55:24.497978 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1917 10:55:24.501380 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1918 10:55:24.504859 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1919 10:55:24.507741 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1920 10:55:24.511750 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1921 10:55:24.518121 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1922 10:55:24.521166 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1923 10:55:24.524820 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1924 10:55:24.524954 ==
1925 10:55:24.528089 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 10:55:24.531368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 10:55:24.531477 ==
1928 10:55:24.534918 DQS Delay:
1929 10:55:24.535035 DQS0 = 0, DQS1 = 0
1930 10:55:24.538062 DQM Delay:
1931 10:55:24.538144 DQM0 = 87, DQM1 = 79
1932 10:55:24.538212 DQ Delay:
1933 10:55:24.541117 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1934 10:55:24.544218 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1935 10:55:24.547591 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1936 10:55:24.550848 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 10:55:24.550931
1938 10:55:24.554557
1939 10:55:24.554639 ==
1940 10:55:24.557541 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 10:55:24.561123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 10:55:24.561207 ==
1943 10:55:24.561272
1944 10:55:24.561331
1945 10:55:24.564199 TX Vref Scan disable
1946 10:55:24.564281 == TX Byte 0 ==
1947 10:55:24.570611 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1948 10:55:24.573951 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1949 10:55:24.574041 == TX Byte 1 ==
1950 10:55:24.580412 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1951 10:55:24.583791 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1952 10:55:24.583875 ==
1953 10:55:24.587163 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 10:55:24.590423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 10:55:24.590506 ==
1956 10:55:24.604476 TX Vref=22, minBit 1, minWin=27, winSum=445
1957 10:55:24.608219 TX Vref=24, minBit 8, minWin=26, winSum=446
1958 10:55:24.611390 TX Vref=26, minBit 10, minWin=27, winSum=451
1959 10:55:24.615365 TX Vref=28, minBit 13, minWin=27, winSum=452
1960 10:55:24.617925 TX Vref=30, minBit 8, minWin=27, winSum=449
1961 10:55:24.624709 TX Vref=32, minBit 8, minWin=27, winSum=448
1962 10:55:24.628100 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1963 10:55:24.628192
1964 10:55:24.631534 Final TX Range 1 Vref 28
1965 10:55:24.631618
1966 10:55:24.631684 ==
1967 10:55:24.634607 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 10:55:24.637511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 10:55:24.641052 ==
1970 10:55:24.641157
1971 10:55:24.641224
1972 10:55:24.641285 TX Vref Scan disable
1973 10:55:24.645305 == TX Byte 0 ==
1974 10:55:24.648832 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 10:55:24.651493 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 10:55:24.654869 == TX Byte 1 ==
1977 10:55:24.658298 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1978 10:55:24.661954 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1979 10:55:24.664784
1980 10:55:24.664873 [DATLAT]
1981 10:55:24.664939 Freq=800, CH1 RK1
1982 10:55:24.665000
1983 10:55:24.668230 DATLAT Default: 0xa
1984 10:55:24.668317 0, 0xFFFF, sum = 0
1985 10:55:24.671634 1, 0xFFFF, sum = 0
1986 10:55:24.671722 2, 0xFFFF, sum = 0
1987 10:55:24.674729 3, 0xFFFF, sum = 0
1988 10:55:24.674817 4, 0xFFFF, sum = 0
1989 10:55:24.678732 5, 0xFFFF, sum = 0
1990 10:55:24.681413 6, 0xFFFF, sum = 0
1991 10:55:24.681505 7, 0xFFFF, sum = 0
1992 10:55:24.685681 8, 0x0, sum = 1
1993 10:55:24.685772 9, 0x0, sum = 2
1994 10:55:24.685839 10, 0x0, sum = 3
1995 10:55:24.688003 11, 0x0, sum = 4
1996 10:55:24.688088 best_step = 9
1997 10:55:24.688153
1998 10:55:24.688213 ==
1999 10:55:24.691172 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 10:55:24.698047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 10:55:24.698182 ==
2002 10:55:24.698256 RX Vref Scan: 0
2003 10:55:24.698318
2004 10:55:24.701117 RX Vref 0 -> 0, step: 1
2005 10:55:24.701215
2006 10:55:24.704842 RX Delay -95 -> 252, step: 8
2007 10:55:24.708395 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2008 10:55:24.711023 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2009 10:55:24.717601 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2010 10:55:24.721250 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
2011 10:55:24.724713 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2012 10:55:24.728111 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2013 10:55:24.731301 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2014 10:55:24.737772 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2015 10:55:24.741177 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2016 10:55:24.744469 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2017 10:55:24.748038 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2018 10:55:24.751013 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2019 10:55:24.757866 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2020 10:55:24.760721 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2021 10:55:24.763939 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2022 10:55:24.767407 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2023 10:55:24.767512 ==
2024 10:55:24.771102 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 10:55:24.777599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 10:55:24.777714 ==
2027 10:55:24.777783 DQS Delay:
2028 10:55:24.780777 DQS0 = 0, DQS1 = 0
2029 10:55:24.780862 DQM Delay:
2030 10:55:24.780928 DQM0 = 87, DQM1 = 78
2031 10:55:24.784280 DQ Delay:
2032 10:55:24.787165 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2033 10:55:24.790907 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2034 10:55:24.793975 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2035 10:55:24.797237 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2036 10:55:24.797320
2037 10:55:24.797386
2038 10:55:24.803747 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2039 10:55:24.807385 CH1 RK1: MR19=606, MR18=1A11
2040 10:55:24.814063 CH1_RK1: MR19=0x606, MR18=0x1A11, DQSOSC=403, MR23=63, INC=90, DEC=60
2041 10:55:24.817161 [RxdqsGatingPostProcess] freq 800
2042 10:55:24.820359 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 10:55:24.823954 Pre-setting of DQS Precalculation
2044 10:55:24.830631 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
2045 10:55:24.837243 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 10:55:24.843801 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 10:55:24.843929
2048 10:55:24.844000
2049 10:55:24.846954 [Calibration Summary] 1600 Mbps
2050 10:55:24.847039 CH 0, Rank 0
2051 10:55:24.850252 SW Impedance : PASS
2052 10:55:24.853664 DUTY Scan : NO K
2053 10:55:24.853797 ZQ Calibration : PASS
2054 10:55:24.856925 Jitter Meter : NO K
2055 10:55:24.860861 CBT Training : PASS
2056 10:55:24.860957 Write leveling : PASS
2057 10:55:24.864091 RX DQS gating : PASS
2058 10:55:24.867248 RX DQ/DQS(RDDQC) : PASS
2059 10:55:24.867339 TX DQ/DQS : PASS
2060 10:55:24.870514 RX DATLAT : PASS
2061 10:55:24.873668 RX DQ/DQS(Engine): PASS
2062 10:55:24.873758 TX OE : NO K
2063 10:55:24.877083 All Pass.
2064 10:55:24.877169
2065 10:55:24.877265 CH 0, Rank 1
2066 10:55:24.880703 SW Impedance : PASS
2067 10:55:24.880807 DUTY Scan : NO K
2068 10:55:24.883830 ZQ Calibration : PASS
2069 10:55:24.887538 Jitter Meter : NO K
2070 10:55:24.887622 CBT Training : PASS
2071 10:55:24.890299 Write leveling : PASS
2072 10:55:24.890385 RX DQS gating : PASS
2073 10:55:24.893602 RX DQ/DQS(RDDQC) : PASS
2074 10:55:24.896947 TX DQ/DQS : PASS
2075 10:55:24.897037 RX DATLAT : PASS
2076 10:55:24.900567 RX DQ/DQS(Engine): PASS
2077 10:55:24.903371 TX OE : NO K
2078 10:55:24.903458 All Pass.
2079 10:55:24.903523
2080 10:55:24.903582 CH 1, Rank 0
2081 10:55:24.907006 SW Impedance : PASS
2082 10:55:24.910204 DUTY Scan : NO K
2083 10:55:24.910292 ZQ Calibration : PASS
2084 10:55:24.914095 Jitter Meter : NO K
2085 10:55:24.917306 CBT Training : PASS
2086 10:55:24.917400 Write leveling : PASS
2087 10:55:24.920188 RX DQS gating : PASS
2088 10:55:24.923579 RX DQ/DQS(RDDQC) : PASS
2089 10:55:24.923664 TX DQ/DQS : PASS
2090 10:55:24.927091 RX DATLAT : PASS
2091 10:55:24.929819 RX DQ/DQS(Engine): PASS
2092 10:55:24.929910 TX OE : NO K
2093 10:55:24.933397 All Pass.
2094 10:55:24.933528
2095 10:55:24.933606 CH 1, Rank 1
2096 10:55:24.936866 SW Impedance : PASS
2097 10:55:24.936951 DUTY Scan : NO K
2098 10:55:24.940330 ZQ Calibration : PASS
2099 10:55:24.943576 Jitter Meter : NO K
2100 10:55:24.943662 CBT Training : PASS
2101 10:55:24.946817 Write leveling : PASS
2102 10:55:24.949917 RX DQS gating : PASS
2103 10:55:24.950006 RX DQ/DQS(RDDQC) : PASS
2104 10:55:24.953760 TX DQ/DQS : PASS
2105 10:55:24.953847 RX DATLAT : PASS
2106 10:55:24.956307 RX DQ/DQS(Engine): PASS
2107 10:55:24.960461 TX OE : NO K
2108 10:55:24.960559 All Pass.
2109 10:55:24.960628
2110 10:55:24.963535 DramC Write-DBI off
2111 10:55:24.963619 PER_BANK_REFRESH: Hybrid Mode
2112 10:55:24.967543 TX_TRACKING: ON
2113 10:55:24.969794 [GetDramInforAfterCalByMRR] Vendor 6.
2114 10:55:24.973180 [GetDramInforAfterCalByMRR] Revision 606.
2115 10:55:24.976520 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 10:55:24.979794 MR0 0x3b3b
2117 10:55:24.979885 MR8 0x5151
2118 10:55:24.983098 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 10:55:24.983189
2120 10:55:24.983257 MR0 0x3b3b
2121 10:55:24.986397 MR8 0x5151
2122 10:55:24.989477 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 10:55:24.989573
2124 10:55:24.996127 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 10:55:25.002696 [FAST_K] Save calibration result to emmc
2126 10:55:25.006045 [FAST_K] Save calibration result to emmc
2127 10:55:25.006145 dram_init: config_dvfs: 1
2128 10:55:25.009393 dramc_set_vcore_voltage set vcore to 662500
2129 10:55:25.012804 Read voltage for 1200, 2
2130 10:55:25.012903 Vio18 = 0
2131 10:55:25.016174 Vcore = 662500
2132 10:55:25.016267 Vdram = 0
2133 10:55:25.016336 Vddq = 0
2134 10:55:25.019576 Vmddr = 0
2135 10:55:25.023105 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 10:55:25.029561 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 10:55:25.029687 MEM_TYPE=3, freq_sel=15
2138 10:55:25.032859 sv_algorithm_assistance_LP4_1600
2139 10:55:25.039351 ============ PULL DRAM RESETB DOWN ============
2140 10:55:25.043190 ========== PULL DRAM RESETB DOWN end =========
2141 10:55:25.046469 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 10:55:25.049454 ===================================
2143 10:55:25.052912 LPDDR4 DRAM CONFIGURATION
2144 10:55:25.055890 ===================================
2145 10:55:25.060124 EX_ROW_EN[0] = 0x0
2146 10:55:25.060224 EX_ROW_EN[1] = 0x0
2147 10:55:25.062809 LP4Y_EN = 0x0
2148 10:55:25.062895 WORK_FSP = 0x0
2149 10:55:25.065798 WL = 0x4
2150 10:55:25.065889 RL = 0x4
2151 10:55:25.069676 BL = 0x2
2152 10:55:25.069763 RPST = 0x0
2153 10:55:25.073046 RD_PRE = 0x0
2154 10:55:25.073131 WR_PRE = 0x1
2155 10:55:25.075643 WR_PST = 0x0
2156 10:55:25.075728 DBI_WR = 0x0
2157 10:55:25.079087 DBI_RD = 0x0
2158 10:55:25.079175 OTF = 0x1
2159 10:55:25.082938 ===================================
2160 10:55:25.085619 ===================================
2161 10:55:25.089023 ANA top config
2162 10:55:25.092314 ===================================
2163 10:55:25.095673 DLL_ASYNC_EN = 0
2164 10:55:25.095765 ALL_SLAVE_EN = 0
2165 10:55:25.098801 NEW_RANK_MODE = 1
2166 10:55:25.102689 DLL_IDLE_MODE = 1
2167 10:55:25.105372 LP45_APHY_COMB_EN = 1
2168 10:55:25.109002 TX_ODT_DIS = 1
2169 10:55:25.109092 NEW_8X_MODE = 1
2170 10:55:25.112088 ===================================
2171 10:55:25.115664 ===================================
2172 10:55:25.119049 data_rate = 2400
2173 10:55:25.121854 CKR = 1
2174 10:55:25.125235 DQ_P2S_RATIO = 8
2175 10:55:25.128453 ===================================
2176 10:55:25.132714 CA_P2S_RATIO = 8
2177 10:55:25.135697 DQ_CA_OPEN = 0
2178 10:55:25.135788 DQ_SEMI_OPEN = 0
2179 10:55:25.138699 CA_SEMI_OPEN = 0
2180 10:55:25.142149 CA_FULL_RATE = 0
2181 10:55:25.145518 DQ_CKDIV4_EN = 0
2182 10:55:25.148735 CA_CKDIV4_EN = 0
2183 10:55:25.151673 CA_PREDIV_EN = 0
2184 10:55:25.151767 PH8_DLY = 17
2185 10:55:25.155603 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 10:55:25.158566 DQ_AAMCK_DIV = 4
2187 10:55:25.162577 CA_AAMCK_DIV = 4
2188 10:55:25.164964 CA_ADMCK_DIV = 4
2189 10:55:25.168739 DQ_TRACK_CA_EN = 0
2190 10:55:25.168840 CA_PICK = 1200
2191 10:55:25.171843 CA_MCKIO = 1200
2192 10:55:25.174836 MCKIO_SEMI = 0
2193 10:55:25.178327 PLL_FREQ = 2366
2194 10:55:25.181721 DQ_UI_PI_RATIO = 32
2195 10:55:25.185514 CA_UI_PI_RATIO = 0
2196 10:55:25.188483 ===================================
2197 10:55:25.191635 ===================================
2198 10:55:25.194945 memory_type:LPDDR4
2199 10:55:25.195034 GP_NUM : 10
2200 10:55:25.198572 SRAM_EN : 1
2201 10:55:25.198659 MD32_EN : 0
2202 10:55:25.201762 ===================================
2203 10:55:25.205044 [ANA_INIT] >>>>>>>>>>>>>>
2204 10:55:25.208564 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 10:55:25.211602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 10:55:25.215038 ===================================
2207 10:55:25.218060 data_rate = 2400,PCW = 0X5b00
2208 10:55:25.221501 ===================================
2209 10:55:25.224960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 10:55:25.228025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 10:55:25.234659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 10:55:25.241531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 10:55:25.244773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 10:55:25.247795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 10:55:25.247880 [ANA_INIT] flow start
2216 10:55:25.251636 [ANA_INIT] PLL >>>>>>>>
2217 10:55:25.254512 [ANA_INIT] PLL <<<<<<<<
2218 10:55:25.254596 [ANA_INIT] MIDPI >>>>>>>>
2219 10:55:25.258108 [ANA_INIT] MIDPI <<<<<<<<
2220 10:55:25.261064 [ANA_INIT] DLL >>>>>>>>
2221 10:55:25.261148 [ANA_INIT] DLL <<<<<<<<
2222 10:55:25.264382 [ANA_INIT] flow end
2223 10:55:25.268063 ============ LP4 DIFF to SE enter ============
2224 10:55:25.270915 ============ LP4 DIFF to SE exit ============
2225 10:55:25.274365 [ANA_INIT] <<<<<<<<<<<<<
2226 10:55:25.278225 [Flow] Enable top DCM control >>>>>
2227 10:55:25.281796 [Flow] Enable top DCM control <<<<<
2228 10:55:25.284883 Enable DLL master slave shuffle
2229 10:55:25.290645 ==============================================================
2230 10:55:25.290738 Gating Mode config
2231 10:55:25.297226 ==============================================================
2232 10:55:25.300664 Config description:
2233 10:55:25.307331 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 10:55:25.314248 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 10:55:25.321458 SELPH_MODE 0: By rank 1: By Phase
2236 10:55:25.327749 ==============================================================
2237 10:55:25.327876 GAT_TRACK_EN = 1
2238 10:55:25.330856 RX_GATING_MODE = 2
2239 10:55:25.333692 RX_GATING_TRACK_MODE = 2
2240 10:55:25.337091 SELPH_MODE = 1
2241 10:55:25.340510 PICG_EARLY_EN = 1
2242 10:55:25.343715 VALID_LAT_VALUE = 1
2243 10:55:25.350895 ==============================================================
2244 10:55:25.354346 Enter into Gating configuration >>>>
2245 10:55:25.357100 Exit from Gating configuration <<<<
2246 10:55:25.360563 Enter into DVFS_PRE_config >>>>>
2247 10:55:25.370441 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 10:55:25.374639 Exit from DVFS_PRE_config <<<<<
2249 10:55:25.377038 Enter into PICG configuration >>>>
2250 10:55:25.379894 Exit from PICG configuration <<<<
2251 10:55:25.383445 [RX_INPUT] configuration >>>>>
2252 10:55:25.386667 [RX_INPUT] configuration <<<<<
2253 10:55:25.390713 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 10:55:25.397329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 10:55:25.403602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 10:55:25.406756 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 10:55:25.413340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 10:55:25.420062 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 10:55:25.423587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 10:55:25.426476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 10:55:25.433257 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 10:55:25.436438 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 10:55:25.440139 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 10:55:25.446437 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 10:55:25.449974 ===================================
2266 10:55:25.450066 LPDDR4 DRAM CONFIGURATION
2267 10:55:25.453287 ===================================
2268 10:55:25.457305 EX_ROW_EN[0] = 0x0
2269 10:55:25.460105 EX_ROW_EN[1] = 0x0
2270 10:55:25.460189 LP4Y_EN = 0x0
2271 10:55:25.463344 WORK_FSP = 0x0
2272 10:55:25.463427 WL = 0x4
2273 10:55:25.467117 RL = 0x4
2274 10:55:25.467201 BL = 0x2
2275 10:55:25.469559 RPST = 0x0
2276 10:55:25.469641 RD_PRE = 0x0
2277 10:55:25.473025 WR_PRE = 0x1
2278 10:55:25.473108 WR_PST = 0x0
2279 10:55:25.476346 DBI_WR = 0x0
2280 10:55:25.476428 DBI_RD = 0x0
2281 10:55:25.479888 OTF = 0x1
2282 10:55:25.483310 ===================================
2283 10:55:25.486352 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 10:55:25.489770 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 10:55:25.495971 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 10:55:25.499599 ===================================
2287 10:55:25.499685 LPDDR4 DRAM CONFIGURATION
2288 10:55:25.503000 ===================================
2289 10:55:25.506155 EX_ROW_EN[0] = 0x10
2290 10:55:25.506242 EX_ROW_EN[1] = 0x0
2291 10:55:25.509313 LP4Y_EN = 0x0
2292 10:55:25.513472 WORK_FSP = 0x0
2293 10:55:25.513577 WL = 0x4
2294 10:55:25.516273 RL = 0x4
2295 10:55:25.516358 BL = 0x2
2296 10:55:25.519767 RPST = 0x0
2297 10:55:25.519848 RD_PRE = 0x0
2298 10:55:25.522710 WR_PRE = 0x1
2299 10:55:25.522790 WR_PST = 0x0
2300 10:55:25.525921 DBI_WR = 0x0
2301 10:55:25.526002 DBI_RD = 0x0
2302 10:55:25.529333 OTF = 0x1
2303 10:55:25.532699 ===================================
2304 10:55:25.539309 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 10:55:25.539394 ==
2306 10:55:25.542695 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 10:55:25.546030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 10:55:25.546114 ==
2309 10:55:25.549422 [Duty_Offset_Calibration]
2310 10:55:25.549502 B0:1 B1:-1 CA:0
2311 10:55:25.549565
2312 10:55:25.553404 [DutyScan_Calibration_Flow] k_type=0
2313 10:55:25.562923
2314 10:55:25.563003 ==CLK 0==
2315 10:55:25.565688 Final CLK duty delay cell = 0
2316 10:55:25.569920 [0] MAX Duty = 5125%(X100), DQS PI = 24
2317 10:55:25.572565 [0] MIN Duty = 4907%(X100), DQS PI = 6
2318 10:55:25.572646 [0] AVG Duty = 5016%(X100)
2319 10:55:25.576467
2320 10:55:25.579612 CH0 CLK Duty spec in!! Max-Min= 218%
2321 10:55:25.582704 [DutyScan_Calibration_Flow] ====Done====
2322 10:55:25.582784
2323 10:55:25.586035 [DutyScan_Calibration_Flow] k_type=1
2324 10:55:25.600769
2325 10:55:25.600881 ==DQS 0 ==
2326 10:55:25.603554 Final DQS duty delay cell = -4
2327 10:55:25.607081 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2328 10:55:25.610032 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2329 10:55:25.613645 [-4] AVG Duty = 4968%(X100)
2330 10:55:25.613726
2331 10:55:25.613789 ==DQS 1 ==
2332 10:55:25.616770 Final DQS duty delay cell = -4
2333 10:55:25.620390 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2334 10:55:25.623869 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2335 10:55:25.627157 [-4] AVG Duty = 4938%(X100)
2336 10:55:25.627238
2337 10:55:25.629857 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2338 10:55:25.629939
2339 10:55:25.633290 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2340 10:55:25.636488 [DutyScan_Calibration_Flow] ====Done====
2341 10:55:25.636615
2342 10:55:25.640139 [DutyScan_Calibration_Flow] k_type=3
2343 10:55:25.658532
2344 10:55:25.658615 ==DQM 0 ==
2345 10:55:25.661532 Final DQM duty delay cell = 0
2346 10:55:25.664909 [0] MAX Duty = 5031%(X100), DQS PI = 16
2347 10:55:25.668027 [0] MIN Duty = 4875%(X100), DQS PI = 8
2348 10:55:25.671316 [0] AVG Duty = 4953%(X100)
2349 10:55:25.671397
2350 10:55:25.671460 ==DQM 1 ==
2351 10:55:25.675006 Final DQM duty delay cell = 4
2352 10:55:25.678131 [4] MAX Duty = 5187%(X100), DQS PI = 16
2353 10:55:25.681542 [4] MIN Duty = 5000%(X100), DQS PI = 24
2354 10:55:25.684406 [4] AVG Duty = 5093%(X100)
2355 10:55:25.684485
2356 10:55:25.687922 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2357 10:55:25.688002
2358 10:55:25.691307 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 10:55:25.694886 [DutyScan_Calibration_Flow] ====Done====
2360 10:55:25.694968
2361 10:55:25.697651 [DutyScan_Calibration_Flow] k_type=2
2362 10:55:25.714159
2363 10:55:25.714242 ==DQ 0 ==
2364 10:55:25.717508 Final DQ duty delay cell = -4
2365 10:55:25.720316 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2366 10:55:25.723757 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2367 10:55:25.727369 [-4] AVG Duty = 4969%(X100)
2368 10:55:25.727451
2369 10:55:25.727516 ==DQ 1 ==
2370 10:55:25.730537 Final DQ duty delay cell = 0
2371 10:55:25.733773 [0] MAX Duty = 5093%(X100), DQS PI = 4
2372 10:55:25.737301 [0] MIN Duty = 4969%(X100), DQS PI = 40
2373 10:55:25.740440 [0] AVG Duty = 5031%(X100)
2374 10:55:25.740583
2375 10:55:25.744116 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2376 10:55:25.744199
2377 10:55:25.747321 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2378 10:55:25.750386 [DutyScan_Calibration_Flow] ====Done====
2379 10:55:25.750469 ==
2380 10:55:25.754066 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 10:55:25.756989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 10:55:25.757073 ==
2383 10:55:25.761396 [Duty_Offset_Calibration]
2384 10:55:25.761479 B0:-1 B1:1 CA:1
2385 10:55:25.761544
2386 10:55:25.763581 [DutyScan_Calibration_Flow] k_type=0
2387 10:55:25.774435
2388 10:55:25.774520 ==CLK 0==
2389 10:55:25.777894 Final CLK duty delay cell = 0
2390 10:55:25.780613 [0] MAX Duty = 5156%(X100), DQS PI = 20
2391 10:55:25.783752 [0] MIN Duty = 4969%(X100), DQS PI = 62
2392 10:55:25.787692 [0] AVG Duty = 5062%(X100)
2393 10:55:25.787780
2394 10:55:25.790161 CH1 CLK Duty spec in!! Max-Min= 187%
2395 10:55:25.793759 [DutyScan_Calibration_Flow] ====Done====
2396 10:55:25.793864
2397 10:55:25.796974 [DutyScan_Calibration_Flow] k_type=1
2398 10:55:25.813802
2399 10:55:25.813912 ==DQS 0 ==
2400 10:55:25.817291 Final DQS duty delay cell = 0
2401 10:55:25.820233 [0] MAX Duty = 5156%(X100), DQS PI = 48
2402 10:55:25.823640 [0] MIN Duty = 4938%(X100), DQS PI = 6
2403 10:55:25.823724 [0] AVG Duty = 5047%(X100)
2404 10:55:25.826504
2405 10:55:25.826587 ==DQS 1 ==
2406 10:55:25.830191 Final DQS duty delay cell = 0
2407 10:55:25.833902 [0] MAX Duty = 5062%(X100), DQS PI = 10
2408 10:55:25.836686 [0] MIN Duty = 4969%(X100), DQS PI = 58
2409 10:55:25.839998 [0] AVG Duty = 5015%(X100)
2410 10:55:25.840102
2411 10:55:25.843014 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2412 10:55:25.843097
2413 10:55:25.846844 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2414 10:55:25.849773 [DutyScan_Calibration_Flow] ====Done====
2415 10:55:25.849856
2416 10:55:25.853226 [DutyScan_Calibration_Flow] k_type=3
2417 10:55:25.868796
2418 10:55:25.868890 ==DQM 0 ==
2419 10:55:25.872354 Final DQM duty delay cell = -4
2420 10:55:25.875999 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2421 10:55:25.879561 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2422 10:55:25.882661 [-4] AVG Duty = 4969%(X100)
2423 10:55:25.882744
2424 10:55:25.882810 ==DQM 1 ==
2425 10:55:25.885830 Final DQM duty delay cell = 0
2426 10:55:25.889203 [0] MAX Duty = 5187%(X100), DQS PI = 6
2427 10:55:25.892383 [0] MIN Duty = 5000%(X100), DQS PI = 28
2428 10:55:25.895793 [0] AVG Duty = 5093%(X100)
2429 10:55:25.895878
2430 10:55:25.898909 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2431 10:55:25.898993
2432 10:55:25.902136 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2433 10:55:25.905636 [DutyScan_Calibration_Flow] ====Done====
2434 10:55:25.905720
2435 10:55:25.909141 [DutyScan_Calibration_Flow] k_type=2
2436 10:55:25.925806
2437 10:55:25.925911 ==DQ 0 ==
2438 10:55:25.929193 Final DQ duty delay cell = 0
2439 10:55:25.932142 [0] MAX Duty = 5156%(X100), DQS PI = 28
2440 10:55:25.935718 [0] MIN Duty = 4907%(X100), DQS PI = 8
2441 10:55:25.935807 [0] AVG Duty = 5031%(X100)
2442 10:55:25.935875
2443 10:55:25.939081 ==DQ 1 ==
2444 10:55:25.942072 Final DQ duty delay cell = 0
2445 10:55:25.945613 [0] MAX Duty = 5124%(X100), DQS PI = 10
2446 10:55:25.948890 [0] MIN Duty = 4969%(X100), DQS PI = 0
2447 10:55:25.948981 [0] AVG Duty = 5046%(X100)
2448 10:55:25.949049
2449 10:55:25.952257 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2450 10:55:25.955408
2451 10:55:25.958451 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2452 10:55:25.962218 [DutyScan_Calibration_Flow] ====Done====
2453 10:55:25.965201 nWR fixed to 30
2454 10:55:25.965289 [ModeRegInit_LP4] CH0 RK0
2455 10:55:25.968748 [ModeRegInit_LP4] CH0 RK1
2456 10:55:25.971935 [ModeRegInit_LP4] CH1 RK0
2457 10:55:25.974991 [ModeRegInit_LP4] CH1 RK1
2458 10:55:25.975077 match AC timing 7
2459 10:55:25.981589 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 10:55:25.985051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 10:55:25.988485 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 10:55:25.994999 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 10:55:25.998782 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 10:55:25.998869 ==
2465 10:55:26.001810 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 10:55:26.005055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 10:55:26.005142 ==
2468 10:55:26.012098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 10:55:26.017913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 10:55:26.025689 [CA 0] Center 39 (9~70) winsize 62
2471 10:55:26.028831 [CA 1] Center 39 (9~69) winsize 61
2472 10:55:26.031995 [CA 2] Center 35 (5~66) winsize 62
2473 10:55:26.035824 [CA 3] Center 35 (5~66) winsize 62
2474 10:55:26.038677 [CA 4] Center 33 (4~63) winsize 60
2475 10:55:26.042051 [CA 5] Center 33 (3~63) winsize 61
2476 10:55:26.042140
2477 10:55:26.045426 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2478 10:55:26.045512
2479 10:55:26.048916 [CATrainingPosCal] consider 1 rank data
2480 10:55:26.052207 u2DelayCellTimex100 = 270/100 ps
2481 10:55:26.055489 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 10:55:26.061957 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2483 10:55:26.065848 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 10:55:26.068622 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 10:55:26.072191 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2486 10:55:26.075312 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 10:55:26.075399
2488 10:55:26.078438 CA PerBit enable=1, Macro0, CA PI delay=33
2489 10:55:26.078528
2490 10:55:26.082650 [CBTSetCACLKResult] CA Dly = 33
2491 10:55:26.082737 CS Dly: 8 (0~39)
2492 10:55:26.085238 ==
2493 10:55:26.088337 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 10:55:26.091618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 10:55:26.091705 ==
2496 10:55:26.095662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 10:55:26.101469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2498 10:55:26.111346 [CA 0] Center 39 (8~70) winsize 63
2499 10:55:26.114661 [CA 1] Center 39 (9~70) winsize 62
2500 10:55:26.117923 [CA 2] Center 35 (5~66) winsize 62
2501 10:55:26.121123 [CA 3] Center 34 (4~65) winsize 62
2502 10:55:26.124471 [CA 4] Center 33 (3~64) winsize 62
2503 10:55:26.127810 [CA 5] Center 33 (3~63) winsize 61
2504 10:55:26.127895
2505 10:55:26.131190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 10:55:26.131280
2507 10:55:26.134430 [CATrainingPosCal] consider 2 rank data
2508 10:55:26.138343 u2DelayCellTimex100 = 270/100 ps
2509 10:55:26.140854 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2510 10:55:26.147389 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2511 10:55:26.151316 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 10:55:26.154332 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2513 10:55:26.157512 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2514 10:55:26.160715 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2515 10:55:26.160801
2516 10:55:26.164427 CA PerBit enable=1, Macro0, CA PI delay=33
2517 10:55:26.164512
2518 10:55:26.167244 [CBTSetCACLKResult] CA Dly = 33
2519 10:55:26.170790 CS Dly: 9 (0~41)
2520 10:55:26.170876
2521 10:55:26.174415 ----->DramcWriteLeveling(PI) begin...
2522 10:55:26.174503 ==
2523 10:55:26.177742 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 10:55:26.180864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 10:55:26.180951 ==
2526 10:55:26.184030 Write leveling (Byte 0): 33 => 33
2527 10:55:26.187257 Write leveling (Byte 1): 31 => 31
2528 10:55:26.190742 DramcWriteLeveling(PI) end<-----
2529 10:55:26.190830
2530 10:55:26.190898 ==
2531 10:55:26.194120 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 10:55:26.197259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 10:55:26.197345 ==
2534 10:55:26.201142 [Gating] SW mode calibration
2535 10:55:26.207048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 10:55:26.213787 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 10:55:26.217318 0 15 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2538 10:55:26.220881 0 15 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2539 10:55:26.227178 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 10:55:26.230854 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 10:55:26.233939 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 10:55:26.240198 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 10:55:26.244138 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2544 10:55:26.247220 0 15 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
2545 10:55:26.253277 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (1 0)
2546 10:55:26.256471 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 10:55:26.260007 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 10:55:26.266795 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 10:55:26.270361 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 10:55:26.273302 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 10:55:26.280376 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 10:55:26.283178 1 0 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2553 10:55:26.286909 1 1 0 | B1->B0 | 2424 4141 | 0 1 | (0 0) (0 0)
2554 10:55:26.293458 1 1 4 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2555 10:55:26.296498 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 10:55:26.300181 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 10:55:26.306599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 10:55:26.309591 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 10:55:26.313056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 10:55:26.319603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 10:55:26.323653 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2562 10:55:26.326640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 10:55:26.329831 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:55:26.336355 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:55:26.339480 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:55:26.343207 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:55:26.349770 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:55:26.352757 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 10:55:26.356203 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 10:55:26.362680 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 10:55:26.366157 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 10:55:26.369438 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 10:55:26.375973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 10:55:26.379374 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 10:55:26.382855 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 10:55:26.389875 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 10:55:26.392823 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 10:55:26.395974 Total UI for P1: 0, mck2ui 16
2579 10:55:26.399259 best dqsien dly found for B0: ( 1, 3, 26)
2580 10:55:26.402881 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 10:55:26.406411 Total UI for P1: 0, mck2ui 16
2582 10:55:26.409624 best dqsien dly found for B1: ( 1, 4, 0)
2583 10:55:26.412464 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2584 10:55:26.416162 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2585 10:55:26.416250
2586 10:55:26.422852 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2587 10:55:26.425823 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2588 10:55:26.425912 [Gating] SW calibration Done
2589 10:55:26.429136 ==
2590 10:55:26.432361 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 10:55:26.435882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 10:55:26.435972 ==
2593 10:55:26.436038 RX Vref Scan: 0
2594 10:55:26.436101
2595 10:55:26.439377 RX Vref 0 -> 0, step: 1
2596 10:55:26.439462
2597 10:55:26.442343 RX Delay -40 -> 252, step: 8
2598 10:55:26.445853 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2599 10:55:26.449264 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2600 10:55:26.455643 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2601 10:55:26.459042 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2602 10:55:26.462340 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2603 10:55:26.465521 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2604 10:55:26.469434 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2605 10:55:26.472673 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2606 10:55:26.478795 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 10:55:26.482333 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 10:55:26.485434 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2609 10:55:26.490122 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2610 10:55:26.492410 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 10:55:26.499230 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2612 10:55:26.502358 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 10:55:26.505286 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2614 10:55:26.505372 ==
2615 10:55:26.508702 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 10:55:26.512156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 10:55:26.516167 ==
2618 10:55:26.516253 DQS Delay:
2619 10:55:26.516320 DQS0 = 0, DQS1 = 0
2620 10:55:26.518547 DQM Delay:
2621 10:55:26.518630 DQM0 = 119, DQM1 = 106
2622 10:55:26.522275 DQ Delay:
2623 10:55:26.525666 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2624 10:55:26.528908 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2625 10:55:26.531910 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2626 10:55:26.535525 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2627 10:55:26.535618
2628 10:55:26.535684
2629 10:55:26.535744 ==
2630 10:55:26.538812 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 10:55:26.541995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 10:55:26.542082 ==
2633 10:55:26.542148
2634 10:55:26.542209
2635 10:55:26.545485 TX Vref Scan disable
2636 10:55:26.548639 == TX Byte 0 ==
2637 10:55:26.551976 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2638 10:55:26.555054 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2639 10:55:26.558753 == TX Byte 1 ==
2640 10:55:26.561953 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2641 10:55:26.565076 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2642 10:55:26.565162 ==
2643 10:55:26.569139 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 10:55:26.574984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 10:55:26.575076 ==
2646 10:55:26.586258 TX Vref=22, minBit 7, minWin=25, winSum=415
2647 10:55:26.589186 TX Vref=24, minBit 1, minWin=26, winSum=426
2648 10:55:26.592311 TX Vref=26, minBit 1, minWin=26, winSum=430
2649 10:55:26.595882 TX Vref=28, minBit 5, minWin=26, winSum=434
2650 10:55:26.599433 TX Vref=30, minBit 4, minWin=26, winSum=433
2651 10:55:26.605477 TX Vref=32, minBit 4, minWin=26, winSum=426
2652 10:55:26.608726 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 28
2653 10:55:26.608819
2654 10:55:26.612322 Final TX Range 1 Vref 28
2655 10:55:26.612408
2656 10:55:26.612474 ==
2657 10:55:26.615801 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 10:55:26.618419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 10:55:26.622022 ==
2660 10:55:26.622110
2661 10:55:26.622176
2662 10:55:26.622238 TX Vref Scan disable
2663 10:55:26.625401 == TX Byte 0 ==
2664 10:55:26.628819 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2665 10:55:26.635469 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2666 10:55:26.635583 == TX Byte 1 ==
2667 10:55:26.638495 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2668 10:55:26.645367 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2669 10:55:26.645471
2670 10:55:26.645540 [DATLAT]
2671 10:55:26.645602 Freq=1200, CH0 RK0
2672 10:55:26.645660
2673 10:55:26.648093 DATLAT Default: 0xd
2674 10:55:26.652073 0, 0xFFFF, sum = 0
2675 10:55:26.652160 1, 0xFFFF, sum = 0
2676 10:55:26.654783 2, 0xFFFF, sum = 0
2677 10:55:26.654869 3, 0xFFFF, sum = 0
2678 10:55:26.658320 4, 0xFFFF, sum = 0
2679 10:55:26.658406 5, 0xFFFF, sum = 0
2680 10:55:26.661611 6, 0xFFFF, sum = 0
2681 10:55:26.661697 7, 0xFFFF, sum = 0
2682 10:55:26.665540 8, 0xFFFF, sum = 0
2683 10:55:26.665625 9, 0xFFFF, sum = 0
2684 10:55:26.668426 10, 0xFFFF, sum = 0
2685 10:55:26.668512 11, 0xFFFF, sum = 0
2686 10:55:26.671514 12, 0x0, sum = 1
2687 10:55:26.671600 13, 0x0, sum = 2
2688 10:55:26.674916 14, 0x0, sum = 3
2689 10:55:26.675002 15, 0x0, sum = 4
2690 10:55:26.678447 best_step = 13
2691 10:55:26.678531
2692 10:55:26.678597 ==
2693 10:55:26.681945 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 10:55:26.685267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 10:55:26.685354 ==
2696 10:55:26.685420 RX Vref Scan: 1
2697 10:55:26.688199
2698 10:55:26.688283 Set Vref Range= 32 -> 127
2699 10:55:26.688348
2700 10:55:26.691309 RX Vref 32 -> 127, step: 1
2701 10:55:26.691393
2702 10:55:26.695322 RX Delay -21 -> 252, step: 4
2703 10:55:26.695424
2704 10:55:26.698525 Set Vref, RX VrefLevel [Byte0]: 32
2705 10:55:26.701416 [Byte1]: 32
2706 10:55:26.701503
2707 10:55:26.705192 Set Vref, RX VrefLevel [Byte0]: 33
2708 10:55:26.708166 [Byte1]: 33
2709 10:55:26.711798
2710 10:55:26.711886 Set Vref, RX VrefLevel [Byte0]: 34
2711 10:55:26.718108 [Byte1]: 34
2712 10:55:26.718206
2713 10:55:26.721705 Set Vref, RX VrefLevel [Byte0]: 35
2714 10:55:26.724827 [Byte1]: 35
2715 10:55:26.724915
2716 10:55:26.727855 Set Vref, RX VrefLevel [Byte0]: 36
2717 10:55:26.731524 [Byte1]: 36
2718 10:55:26.735512
2719 10:55:26.735604 Set Vref, RX VrefLevel [Byte0]: 37
2720 10:55:26.739003 [Byte1]: 37
2721 10:55:26.743616
2722 10:55:26.743705 Set Vref, RX VrefLevel [Byte0]: 38
2723 10:55:26.746674 [Byte1]: 38
2724 10:55:26.751619
2725 10:55:26.751708 Set Vref, RX VrefLevel [Byte0]: 39
2726 10:55:26.755033 [Byte1]: 39
2727 10:55:26.759064
2728 10:55:26.759150 Set Vref, RX VrefLevel [Byte0]: 40
2729 10:55:26.763021 [Byte1]: 40
2730 10:55:26.767208
2731 10:55:26.767295 Set Vref, RX VrefLevel [Byte0]: 41
2732 10:55:26.770544 [Byte1]: 41
2733 10:55:26.774962
2734 10:55:26.775051 Set Vref, RX VrefLevel [Byte0]: 42
2735 10:55:26.778606 [Byte1]: 42
2736 10:55:26.783587
2737 10:55:26.783677 Set Vref, RX VrefLevel [Byte0]: 43
2738 10:55:26.786362 [Byte1]: 43
2739 10:55:26.791167
2740 10:55:26.791265 Set Vref, RX VrefLevel [Byte0]: 44
2741 10:55:26.794480 [Byte1]: 44
2742 10:55:26.798852
2743 10:55:26.798939 Set Vref, RX VrefLevel [Byte0]: 45
2744 10:55:26.802100 [Byte1]: 45
2745 10:55:26.807027
2746 10:55:26.807126 Set Vref, RX VrefLevel [Byte0]: 46
2747 10:55:26.810219 [Byte1]: 46
2748 10:55:26.815444
2749 10:55:26.815540 Set Vref, RX VrefLevel [Byte0]: 47
2750 10:55:26.817877 [Byte1]: 47
2751 10:55:26.822688
2752 10:55:26.822783 Set Vref, RX VrefLevel [Byte0]: 48
2753 10:55:26.826020 [Byte1]: 48
2754 10:55:26.830897
2755 10:55:26.831065 Set Vref, RX VrefLevel [Byte0]: 49
2756 10:55:26.834081 [Byte1]: 49
2757 10:55:26.838606
2758 10:55:26.838696 Set Vref, RX VrefLevel [Byte0]: 50
2759 10:55:26.842137 [Byte1]: 50
2760 10:55:26.846637
2761 10:55:26.846729 Set Vref, RX VrefLevel [Byte0]: 51
2762 10:55:26.849639 [Byte1]: 51
2763 10:55:26.854605
2764 10:55:26.854696 Set Vref, RX VrefLevel [Byte0]: 52
2765 10:55:26.858343 [Byte1]: 52
2766 10:55:26.862624
2767 10:55:26.862714 Set Vref, RX VrefLevel [Byte0]: 53
2768 10:55:26.865431 [Byte1]: 53
2769 10:55:26.870184
2770 10:55:26.870272 Set Vref, RX VrefLevel [Byte0]: 54
2771 10:55:26.873717 [Byte1]: 54
2772 10:55:26.878429
2773 10:55:26.878531 Set Vref, RX VrefLevel [Byte0]: 55
2774 10:55:26.881847 [Byte1]: 55
2775 10:55:26.886236
2776 10:55:26.886325 Set Vref, RX VrefLevel [Byte0]: 56
2777 10:55:26.889404 [Byte1]: 56
2778 10:55:26.894031
2779 10:55:26.894122 Set Vref, RX VrefLevel [Byte0]: 57
2780 10:55:26.897334 [Byte1]: 57
2781 10:55:26.901901
2782 10:55:26.901993 Set Vref, RX VrefLevel [Byte0]: 58
2783 10:55:26.905054 [Byte1]: 58
2784 10:55:26.909905
2785 10:55:26.909996 Set Vref, RX VrefLevel [Byte0]: 59
2786 10:55:26.916662 [Byte1]: 59
2787 10:55:26.916761
2788 10:55:26.919963 Set Vref, RX VrefLevel [Byte0]: 60
2789 10:55:26.923168 [Byte1]: 60
2790 10:55:26.923256
2791 10:55:26.926452 Set Vref, RX VrefLevel [Byte0]: 61
2792 10:55:26.929607 [Byte1]: 61
2793 10:55:26.933864
2794 10:55:26.933978 Set Vref, RX VrefLevel [Byte0]: 62
2795 10:55:26.936784 [Byte1]: 62
2796 10:55:26.942172
2797 10:55:26.942268 Set Vref, RX VrefLevel [Byte0]: 63
2798 10:55:26.945340 [Byte1]: 63
2799 10:55:26.949950
2800 10:55:26.950041 Set Vref, RX VrefLevel [Byte0]: 64
2801 10:55:26.952788 [Byte1]: 64
2802 10:55:26.957520
2803 10:55:26.957610 Set Vref, RX VrefLevel [Byte0]: 65
2804 10:55:26.961041 [Byte1]: 65
2805 10:55:26.965783
2806 10:55:26.965870 Set Vref, RX VrefLevel [Byte0]: 66
2807 10:55:26.969015 [Byte1]: 66
2808 10:55:26.973893
2809 10:55:26.974000 Set Vref, RX VrefLevel [Byte0]: 67
2810 10:55:26.976816 [Byte1]: 67
2811 10:55:26.981259
2812 10:55:26.981348 Set Vref, RX VrefLevel [Byte0]: 68
2813 10:55:26.984392 [Byte1]: 68
2814 10:55:26.989167
2815 10:55:26.989257 Set Vref, RX VrefLevel [Byte0]: 69
2816 10:55:26.993328 [Byte1]: 69
2817 10:55:26.997488
2818 10:55:26.997575 Set Vref, RX VrefLevel [Byte0]: 70
2819 10:55:27.000163 [Byte1]: 70
2820 10:55:27.005329
2821 10:55:27.005419 Set Vref, RX VrefLevel [Byte0]: 71
2822 10:55:27.008452 [Byte1]: 71
2823 10:55:27.013226
2824 10:55:27.013357 Set Vref, RX VrefLevel [Byte0]: 72
2825 10:55:27.016347 [Byte1]: 72
2826 10:55:27.020861
2827 10:55:27.020949 Set Vref, RX VrefLevel [Byte0]: 73
2828 10:55:27.024105 [Byte1]: 73
2829 10:55:27.028494
2830 10:55:27.028640 Set Vref, RX VrefLevel [Byte0]: 74
2831 10:55:27.032138 [Byte1]: 74
2832 10:55:27.037039
2833 10:55:27.037157 Set Vref, RX VrefLevel [Byte0]: 75
2834 10:55:27.040016 [Byte1]: 75
2835 10:55:27.044548
2836 10:55:27.044669 Final RX Vref Byte 0 = 61 to rank0
2837 10:55:27.047720 Final RX Vref Byte 1 = 50 to rank0
2838 10:55:27.051255 Final RX Vref Byte 0 = 61 to rank1
2839 10:55:27.054607 Final RX Vref Byte 1 = 50 to rank1==
2840 10:55:27.057889 Dram Type= 6, Freq= 0, CH_0, rank 0
2841 10:55:27.064797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 10:55:27.064912 ==
2843 10:55:27.064981 DQS Delay:
2844 10:55:27.065041 DQS0 = 0, DQS1 = 0
2845 10:55:27.068056 DQM Delay:
2846 10:55:27.068139 DQM0 = 119, DQM1 = 106
2847 10:55:27.070993 DQ Delay:
2848 10:55:27.074688 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =118
2849 10:55:27.077866 DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =126
2850 10:55:27.080910 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2851 10:55:27.084498 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2852 10:55:27.084616
2853 10:55:27.084681
2854 10:55:27.091213 [DQSOSCAuto] RK0, (LSB)MR18= 0xcf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2855 10:55:27.094159 CH0 RK0: MR19=403, MR18=CF8
2856 10:55:27.100958 CH0_RK0: MR19=0x403, MR18=0xCF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2857 10:55:27.101060
2858 10:55:27.104372 ----->DramcWriteLeveling(PI) begin...
2859 10:55:27.104466 ==
2860 10:55:27.107995 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 10:55:27.110723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 10:55:27.114229 ==
2863 10:55:27.114314 Write leveling (Byte 0): 31 => 31
2864 10:55:27.117515 Write leveling (Byte 1): 30 => 30
2865 10:55:27.121791 DramcWriteLeveling(PI) end<-----
2866 10:55:27.121875
2867 10:55:27.121941 ==
2868 10:55:27.124388 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 10:55:27.131174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 10:55:27.131275 ==
2871 10:55:27.134047 [Gating] SW mode calibration
2872 10:55:27.140523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2873 10:55:27.143717 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2874 10:55:27.150744 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2875 10:55:27.154189 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2876 10:55:27.157358 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 10:55:27.163824 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 10:55:27.167343 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 10:55:27.170263 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 10:55:27.176950 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2881 10:55:27.180340 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2882 10:55:27.183630 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
2883 10:55:27.190233 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 10:55:27.193686 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 10:55:27.197255 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 10:55:27.203655 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 10:55:27.206735 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 10:55:27.210066 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 10:55:27.216877 1 0 28 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
2890 10:55:27.219853 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2891 10:55:27.223168 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 10:55:27.229815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 10:55:27.233104 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 10:55:27.236360 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 10:55:27.239716 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 10:55:27.246163 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 10:55:27.249842 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2898 10:55:27.253198 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 10:55:27.260135 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 10:55:27.263537 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 10:55:27.266114 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 10:55:27.273189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 10:55:27.276281 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 10:55:27.279545 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 10:55:27.285956 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:55:27.289841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:55:27.293360 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 10:55:27.299465 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 10:55:27.302719 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 10:55:27.306182 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 10:55:27.312965 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 10:55:27.316069 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2913 10:55:27.319093 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2914 10:55:27.326090 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 10:55:27.329644 Total UI for P1: 0, mck2ui 16
2916 10:55:27.332512 best dqsien dly found for B0: ( 1, 3, 26)
2917 10:55:27.332659 Total UI for P1: 0, mck2ui 16
2918 10:55:27.339524 best dqsien dly found for B1: ( 1, 3, 30)
2919 10:55:27.343173 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2920 10:55:27.346101 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2921 10:55:27.346195
2922 10:55:27.349279 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2923 10:55:27.352455 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2924 10:55:27.355841 [Gating] SW calibration Done
2925 10:55:27.355931 ==
2926 10:55:27.359377 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 10:55:27.362555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 10:55:27.362648 ==
2929 10:55:27.365808 RX Vref Scan: 0
2930 10:55:27.365894
2931 10:55:27.365959 RX Vref 0 -> 0, step: 1
2932 10:55:27.366020
2933 10:55:27.369024 RX Delay -40 -> 252, step: 8
2934 10:55:27.372229 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2935 10:55:27.378746 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2936 10:55:27.382446 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2937 10:55:27.385320 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2938 10:55:27.388895 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2939 10:55:27.391929 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2940 10:55:27.398811 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2941 10:55:27.402069 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2942 10:55:27.405400 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2943 10:55:27.409227 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2944 10:55:27.412646 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2945 10:55:27.418937 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2946 10:55:27.421789 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2947 10:55:27.425478 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2948 10:55:27.429323 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2949 10:55:27.435630 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2950 10:55:27.435738 ==
2951 10:55:27.438693 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 10:55:27.442032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 10:55:27.442122 ==
2954 10:55:27.442201 DQS Delay:
2955 10:55:27.445964 DQS0 = 0, DQS1 = 0
2956 10:55:27.446049 DQM Delay:
2957 10:55:27.448911 DQM0 = 116, DQM1 = 108
2958 10:55:27.448997 DQ Delay:
2959 10:55:27.451818 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2960 10:55:27.455888 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2961 10:55:27.458335 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2962 10:55:27.461664 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2963 10:55:27.461755
2964 10:55:27.461836
2965 10:55:27.465423 ==
2966 10:55:27.465510 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 10:55:27.471737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 10:55:27.471841 ==
2969 10:55:27.471914
2970 10:55:27.471987
2971 10:55:27.474883 TX Vref Scan disable
2972 10:55:27.474968 == TX Byte 0 ==
2973 10:55:27.478105 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2974 10:55:27.485002 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2975 10:55:27.485117 == TX Byte 1 ==
2976 10:55:27.487975 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2977 10:55:27.495185 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2978 10:55:27.495293 ==
2979 10:55:27.498028 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 10:55:27.500985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 10:55:27.501074 ==
2982 10:55:27.513710 TX Vref=22, minBit 4, minWin=25, winSum=414
2983 10:55:27.516787 TX Vref=24, minBit 5, minWin=25, winSum=419
2984 10:55:27.520149 TX Vref=26, minBit 13, minWin=25, winSum=424
2985 10:55:27.523076 TX Vref=28, minBit 13, minWin=25, winSum=426
2986 10:55:27.526659 TX Vref=30, minBit 13, minWin=25, winSum=422
2987 10:55:27.533674 TX Vref=32, minBit 12, minWin=25, winSum=424
2988 10:55:27.536486 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 28
2989 10:55:27.536626
2990 10:55:27.540098 Final TX Range 1 Vref 28
2991 10:55:27.540186
2992 10:55:27.540251 ==
2993 10:55:27.543144 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 10:55:27.546898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 10:55:27.549773 ==
2996 10:55:27.549862
2997 10:55:27.549929
2998 10:55:27.550003 TX Vref Scan disable
2999 10:55:27.553638 == TX Byte 0 ==
3000 10:55:27.556694 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3001 10:55:27.563637 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3002 10:55:27.563744 == TX Byte 1 ==
3003 10:55:27.567120 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3004 10:55:27.573496 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3005 10:55:27.573609
3006 10:55:27.573680 [DATLAT]
3007 10:55:27.573742 Freq=1200, CH0 RK1
3008 10:55:27.573801
3009 10:55:27.576499 DATLAT Default: 0xd
3010 10:55:27.576630 0, 0xFFFF, sum = 0
3011 10:55:27.580179 1, 0xFFFF, sum = 0
3012 10:55:27.583435 2, 0xFFFF, sum = 0
3013 10:55:27.583526 3, 0xFFFF, sum = 0
3014 10:55:27.586712 4, 0xFFFF, sum = 0
3015 10:55:27.586803 5, 0xFFFF, sum = 0
3016 10:55:27.590395 6, 0xFFFF, sum = 0
3017 10:55:27.590485 7, 0xFFFF, sum = 0
3018 10:55:27.593311 8, 0xFFFF, sum = 0
3019 10:55:27.593403 9, 0xFFFF, sum = 0
3020 10:55:27.596842 10, 0xFFFF, sum = 0
3021 10:55:27.596930 11, 0xFFFF, sum = 0
3022 10:55:27.599990 12, 0x0, sum = 1
3023 10:55:27.600077 13, 0x0, sum = 2
3024 10:55:27.603208 14, 0x0, sum = 3
3025 10:55:27.603294 15, 0x0, sum = 4
3026 10:55:27.606752 best_step = 13
3027 10:55:27.606838
3028 10:55:27.606904 ==
3029 10:55:27.610169 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 10:55:27.613206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 10:55:27.613295 ==
3032 10:55:27.613363 RX Vref Scan: 0
3033 10:55:27.613425
3034 10:55:27.616444 RX Vref 0 -> 0, step: 1
3035 10:55:27.616567
3036 10:55:27.619588 RX Delay -21 -> 252, step: 4
3037 10:55:27.626782 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3038 10:55:27.629593 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3039 10:55:27.633187 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3040 10:55:27.636459 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3041 10:55:27.639566 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3042 10:55:27.643265 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3043 10:55:27.650363 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3044 10:55:27.653163 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3045 10:55:27.656452 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3046 10:55:27.659931 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3047 10:55:27.663320 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3048 10:55:27.669637 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3049 10:55:27.672954 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3050 10:55:27.676377 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3051 10:55:27.679716 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3052 10:55:27.686009 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3053 10:55:27.686116 ==
3054 10:55:27.689299 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 10:55:27.692627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 10:55:27.692719 ==
3057 10:55:27.692787 DQS Delay:
3058 10:55:27.696080 DQS0 = 0, DQS1 = 0
3059 10:55:27.696166 DQM Delay:
3060 10:55:27.699627 DQM0 = 116, DQM1 = 107
3061 10:55:27.699714 DQ Delay:
3062 10:55:27.702668 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3063 10:55:27.706098 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3064 10:55:27.709713 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3065 10:55:27.712992 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3066 10:55:27.713083
3067 10:55:27.713149
3068 10:55:27.722713 [DQSOSCAuto] RK1, (LSB)MR18= 0xae4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3069 10:55:27.725952 CH0 RK1: MR19=403, MR18=AE4
3070 10:55:27.729670 CH0_RK1: MR19=0x403, MR18=0xAE4, DQSOSC=406, MR23=63, INC=39, DEC=26
3071 10:55:27.732446 [RxdqsGatingPostProcess] freq 1200
3072 10:55:27.739097 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3073 10:55:27.742163 best DQS0 dly(2T, 0.5T) = (0, 11)
3074 10:55:27.746236 best DQS1 dly(2T, 0.5T) = (0, 12)
3075 10:55:27.749733 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3076 10:55:27.752421 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3077 10:55:27.755942 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 10:55:27.758840 best DQS1 dly(2T, 0.5T) = (0, 11)
3079 10:55:27.762137 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 10:55:27.765542 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3081 10:55:27.765634 Pre-setting of DQS Precalculation
3082 10:55:27.772451 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3083 10:55:27.772598 ==
3084 10:55:27.775249 Dram Type= 6, Freq= 0, CH_1, rank 0
3085 10:55:27.778714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 10:55:27.778840 ==
3087 10:55:27.785438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 10:55:27.791823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3089 10:55:27.800131 [CA 0] Center 37 (7~68) winsize 62
3090 10:55:27.802991 [CA 1] Center 37 (7~68) winsize 62
3091 10:55:27.806417 [CA 2] Center 34 (4~64) winsize 61
3092 10:55:27.810572 [CA 3] Center 33 (3~64) winsize 62
3093 10:55:27.813252 [CA 4] Center 34 (4~64) winsize 61
3094 10:55:27.816446 [CA 5] Center 33 (3~64) winsize 62
3095 10:55:27.816575
3096 10:55:27.819419 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 10:55:27.819505
3098 10:55:27.822901 [CATrainingPosCal] consider 1 rank data
3099 10:55:27.826160 u2DelayCellTimex100 = 270/100 ps
3100 10:55:27.829603 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 10:55:27.836360 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 10:55:27.839257 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3103 10:55:27.842530 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3104 10:55:27.846217 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 10:55:27.849223 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3106 10:55:27.849312
3107 10:55:27.853016 CA PerBit enable=1, Macro0, CA PI delay=33
3108 10:55:27.853104
3109 10:55:27.856151 [CBTSetCACLKResult] CA Dly = 33
3110 10:55:27.856236 CS Dly: 6 (0~37)
3111 10:55:27.859226 ==
3112 10:55:27.862428 Dram Type= 6, Freq= 0, CH_1, rank 1
3113 10:55:27.866263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 10:55:27.866356 ==
3115 10:55:27.869477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 10:55:27.876067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 10:55:27.885406 [CA 0] Center 37 (7~67) winsize 61
3118 10:55:27.889209 [CA 1] Center 38 (8~68) winsize 61
3119 10:55:27.892187 [CA 2] Center 34 (4~65) winsize 62
3120 10:55:27.895179 [CA 3] Center 33 (3~64) winsize 62
3121 10:55:27.898713 [CA 4] Center 34 (4~65) winsize 62
3122 10:55:27.902108 [CA 5] Center 33 (3~64) winsize 62
3123 10:55:27.902206
3124 10:55:27.905781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3125 10:55:27.905871
3126 10:55:27.908456 [CATrainingPosCal] consider 2 rank data
3127 10:55:27.912281 u2DelayCellTimex100 = 270/100 ps
3128 10:55:27.915404 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3129 10:55:27.921997 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3130 10:55:27.924947 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 10:55:27.928116 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3132 10:55:27.931398 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 10:55:27.935209 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 10:55:27.935309
3135 10:55:27.938163 CA PerBit enable=1, Macro0, CA PI delay=33
3136 10:55:27.938250
3137 10:55:27.941131 [CBTSetCACLKResult] CA Dly = 33
3138 10:55:27.945024 CS Dly: 7 (0~40)
3139 10:55:27.945112
3140 10:55:27.947900 ----->DramcWriteLeveling(PI) begin...
3141 10:55:27.947987 ==
3142 10:55:27.951438 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 10:55:27.954832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 10:55:27.954920 ==
3145 10:55:27.958075 Write leveling (Byte 0): 24 => 24
3146 10:55:27.961598 Write leveling (Byte 1): 28 => 28
3147 10:55:27.964488 DramcWriteLeveling(PI) end<-----
3148 10:55:27.964614
3149 10:55:27.964680 ==
3150 10:55:27.968324 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 10:55:27.970901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 10:55:27.970987 ==
3153 10:55:27.974774 [Gating] SW mode calibration
3154 10:55:27.981166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3155 10:55:27.987962 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3156 10:55:27.990816 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3157 10:55:27.994315 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 10:55:28.001505 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 10:55:28.005222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 10:55:28.007369 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 10:55:28.014431 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 10:55:28.017525 0 15 24 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
3163 10:55:28.021001 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 1) (1 0)
3164 10:55:28.027619 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 10:55:28.030744 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 10:55:28.033937 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 10:55:28.040448 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 10:55:28.043794 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 10:55:28.047375 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 10:55:28.054239 1 0 24 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
3171 10:55:28.057695 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 10:55:28.060314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 10:55:28.067740 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 10:55:28.070643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 10:55:28.074099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 10:55:28.081094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 10:55:28.084941 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 10:55:28.086883 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3179 10:55:28.093820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3180 10:55:28.097208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 10:55:28.100250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 10:55:28.107072 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 10:55:28.110102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 10:55:28.113606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 10:55:28.120056 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 10:55:28.123424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 10:55:28.127032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:55:28.130054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:55:28.136629 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 10:55:28.140647 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 10:55:28.143519 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 10:55:28.149944 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 10:55:28.153589 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 10:55:28.156816 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3195 10:55:28.163082 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3196 10:55:28.166902 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 10:55:28.170082 Total UI for P1: 0, mck2ui 16
3198 10:55:28.173581 best dqsien dly found for B0: ( 1, 3, 26)
3199 10:55:28.176963 Total UI for P1: 0, mck2ui 16
3200 10:55:28.179986 best dqsien dly found for B1: ( 1, 3, 28)
3201 10:55:28.183101 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3202 10:55:28.186747 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3203 10:55:28.186839
3204 10:55:28.190055 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3205 10:55:28.193217 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3206 10:55:28.196987 [Gating] SW calibration Done
3207 10:55:28.197081 ==
3208 10:55:28.200023 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 10:55:28.207466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 10:55:28.207576 ==
3211 10:55:28.207645 RX Vref Scan: 0
3212 10:55:28.207707
3213 10:55:28.209949 RX Vref 0 -> 0, step: 1
3214 10:55:28.210034
3215 10:55:28.213034 RX Delay -40 -> 252, step: 8
3216 10:55:28.216688 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3217 10:55:28.220323 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3218 10:55:28.222918 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3219 10:55:28.226445 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3220 10:55:28.233088 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3221 10:55:28.236226 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3222 10:55:28.239493 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3223 10:55:28.243515 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3224 10:55:28.246435 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3225 10:55:28.253594 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3226 10:55:28.256404 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3227 10:55:28.259769 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3228 10:55:28.262726 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3229 10:55:28.266157 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3230 10:55:28.272852 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3231 10:55:28.276224 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3232 10:55:28.276320 ==
3233 10:55:28.279553 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 10:55:28.282719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 10:55:28.282804 ==
3236 10:55:28.286304 DQS Delay:
3237 10:55:28.286388 DQS0 = 0, DQS1 = 0
3238 10:55:28.286454 DQM Delay:
3239 10:55:28.289205 DQM0 = 117, DQM1 = 109
3240 10:55:28.289289 DQ Delay:
3241 10:55:28.292748 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3242 10:55:28.296047 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3243 10:55:28.299247 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3244 10:55:28.306470 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3245 10:55:28.306574
3246 10:55:28.306640
3247 10:55:28.306700 ==
3248 10:55:28.309317 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 10:55:28.312646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 10:55:28.312732 ==
3251 10:55:28.312798
3252 10:55:28.312859
3253 10:55:28.315868 TX Vref Scan disable
3254 10:55:28.315951 == TX Byte 0 ==
3255 10:55:28.322914 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3256 10:55:28.325981 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3257 10:55:28.326070 == TX Byte 1 ==
3258 10:55:28.332698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 10:55:28.336194 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 10:55:28.336298 ==
3261 10:55:28.339577 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 10:55:28.342353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 10:55:28.342443 ==
3264 10:55:28.355418 TX Vref=22, minBit 8, minWin=25, winSum=420
3265 10:55:28.358816 TX Vref=24, minBit 9, minWin=25, winSum=423
3266 10:55:28.361762 TX Vref=26, minBit 8, minWin=25, winSum=431
3267 10:55:28.365325 TX Vref=28, minBit 11, minWin=25, winSum=435
3268 10:55:28.368756 TX Vref=30, minBit 11, minWin=25, winSum=431
3269 10:55:28.375046 TX Vref=32, minBit 9, minWin=24, winSum=426
3270 10:55:28.378911 [TxChooseVref] Worse bit 11, Min win 25, Win sum 435, Final Vref 28
3271 10:55:28.379007
3272 10:55:28.381660 Final TX Range 1 Vref 28
3273 10:55:28.381746
3274 10:55:28.381813 ==
3275 10:55:28.384839 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 10:55:28.388525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 10:55:28.391399 ==
3278 10:55:28.391486
3279 10:55:28.391554
3280 10:55:28.391615 TX Vref Scan disable
3281 10:55:28.395442 == TX Byte 0 ==
3282 10:55:28.398971 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3283 10:55:28.405279 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3284 10:55:28.405385 == TX Byte 1 ==
3285 10:55:28.408825 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3286 10:55:28.415158 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3287 10:55:28.415258
3288 10:55:28.415328 [DATLAT]
3289 10:55:28.415389 Freq=1200, CH1 RK0
3290 10:55:28.415450
3291 10:55:28.418201 DATLAT Default: 0xd
3292 10:55:28.418287 0, 0xFFFF, sum = 0
3293 10:55:28.422130 1, 0xFFFF, sum = 0
3294 10:55:28.425444 2, 0xFFFF, sum = 0
3295 10:55:28.425536 3, 0xFFFF, sum = 0
3296 10:55:28.428918 4, 0xFFFF, sum = 0
3297 10:55:28.429006 5, 0xFFFF, sum = 0
3298 10:55:28.431522 6, 0xFFFF, sum = 0
3299 10:55:28.431606 7, 0xFFFF, sum = 0
3300 10:55:28.434822 8, 0xFFFF, sum = 0
3301 10:55:28.434924 9, 0xFFFF, sum = 0
3302 10:55:28.438201 10, 0xFFFF, sum = 0
3303 10:55:28.438288 11, 0xFFFF, sum = 0
3304 10:55:28.441648 12, 0x0, sum = 1
3305 10:55:28.441735 13, 0x0, sum = 2
3306 10:55:28.444673 14, 0x0, sum = 3
3307 10:55:28.444757 15, 0x0, sum = 4
3308 10:55:28.448060 best_step = 13
3309 10:55:28.448142
3310 10:55:28.448206 ==
3311 10:55:28.451480 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 10:55:28.454863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 10:55:28.454948 ==
3314 10:55:28.458004 RX Vref Scan: 1
3315 10:55:28.458087
3316 10:55:28.458150 Set Vref Range= 32 -> 127
3317 10:55:28.458209
3318 10:55:28.461611 RX Vref 32 -> 127, step: 1
3319 10:55:28.461693
3320 10:55:28.464590 RX Delay -21 -> 252, step: 4
3321 10:55:28.464672
3322 10:55:28.468152 Set Vref, RX VrefLevel [Byte0]: 32
3323 10:55:28.471441 [Byte1]: 32
3324 10:55:28.471524
3325 10:55:28.475380 Set Vref, RX VrefLevel [Byte0]: 33
3326 10:55:28.478026 [Byte1]: 33
3327 10:55:28.481699
3328 10:55:28.481783 Set Vref, RX VrefLevel [Byte0]: 34
3329 10:55:28.485426 [Byte1]: 34
3330 10:55:28.489699
3331 10:55:28.489785 Set Vref, RX VrefLevel [Byte0]: 35
3332 10:55:28.493026 [Byte1]: 35
3333 10:55:28.497846
3334 10:55:28.497935 Set Vref, RX VrefLevel [Byte0]: 36
3335 10:55:28.501013 [Byte1]: 36
3336 10:55:28.505327
3337 10:55:28.505416 Set Vref, RX VrefLevel [Byte0]: 37
3338 10:55:28.508975 [Byte1]: 37
3339 10:55:28.513209
3340 10:55:28.513299 Set Vref, RX VrefLevel [Byte0]: 38
3341 10:55:28.516876 [Byte1]: 38
3342 10:55:28.521979
3343 10:55:28.522070 Set Vref, RX VrefLevel [Byte0]: 39
3344 10:55:28.524483 [Byte1]: 39
3345 10:55:28.529683
3346 10:55:28.529774 Set Vref, RX VrefLevel [Byte0]: 40
3347 10:55:28.532462 [Byte1]: 40
3348 10:55:28.537271
3349 10:55:28.537374 Set Vref, RX VrefLevel [Byte0]: 41
3350 10:55:28.540625 [Byte1]: 41
3351 10:55:28.545526
3352 10:55:28.545620 Set Vref, RX VrefLevel [Byte0]: 42
3353 10:55:28.548763 [Byte1]: 42
3354 10:55:28.552798
3355 10:55:28.552885 Set Vref, RX VrefLevel [Byte0]: 43
3356 10:55:28.556426 [Byte1]: 43
3357 10:55:28.560896
3358 10:55:28.560987 Set Vref, RX VrefLevel [Byte0]: 44
3359 10:55:28.564175 [Byte1]: 44
3360 10:55:28.569224
3361 10:55:28.569312 Set Vref, RX VrefLevel [Byte0]: 45
3362 10:55:28.572321 [Byte1]: 45
3363 10:55:28.577178
3364 10:55:28.577265 Set Vref, RX VrefLevel [Byte0]: 46
3365 10:55:28.580090 [Byte1]: 46
3366 10:55:28.584947
3367 10:55:28.585034 Set Vref, RX VrefLevel [Byte0]: 47
3368 10:55:28.587966 [Byte1]: 47
3369 10:55:28.592863
3370 10:55:28.592953 Set Vref, RX VrefLevel [Byte0]: 48
3371 10:55:28.595696 [Byte1]: 48
3372 10:55:28.600473
3373 10:55:28.600573 Set Vref, RX VrefLevel [Byte0]: 49
3374 10:55:28.603689 [Byte1]: 49
3375 10:55:28.608734
3376 10:55:28.608826 Set Vref, RX VrefLevel [Byte0]: 50
3377 10:55:28.611750 [Byte1]: 50
3378 10:55:28.616163
3379 10:55:28.616251 Set Vref, RX VrefLevel [Byte0]: 51
3380 10:55:28.619769 [Byte1]: 51
3381 10:55:28.624061
3382 10:55:28.624150 Set Vref, RX VrefLevel [Byte0]: 52
3383 10:55:28.628011 [Byte1]: 52
3384 10:55:28.632258
3385 10:55:28.632345 Set Vref, RX VrefLevel [Byte0]: 53
3386 10:55:28.635584 [Byte1]: 53
3387 10:55:28.639998
3388 10:55:28.640092 Set Vref, RX VrefLevel [Byte0]: 54
3389 10:55:28.643311 [Byte1]: 54
3390 10:55:28.647937
3391 10:55:28.648059 Set Vref, RX VrefLevel [Byte0]: 55
3392 10:55:28.651562 [Byte1]: 55
3393 10:55:28.656114
3394 10:55:28.656218 Set Vref, RX VrefLevel [Byte0]: 56
3395 10:55:28.659387 [Byte1]: 56
3396 10:55:28.663684
3397 10:55:28.663771 Set Vref, RX VrefLevel [Byte0]: 57
3398 10:55:28.667081 [Byte1]: 57
3399 10:55:28.672074
3400 10:55:28.672162 Set Vref, RX VrefLevel [Byte0]: 58
3401 10:55:28.675202 [Byte1]: 58
3402 10:55:28.679688
3403 10:55:28.679773 Set Vref, RX VrefLevel [Byte0]: 59
3404 10:55:28.683167 [Byte1]: 59
3405 10:55:28.687752
3406 10:55:28.687838 Set Vref, RX VrefLevel [Byte0]: 60
3407 10:55:28.691531 [Byte1]: 60
3408 10:55:28.695665
3409 10:55:28.695775 Set Vref, RX VrefLevel [Byte0]: 61
3410 10:55:28.698704 [Byte1]: 61
3411 10:55:28.703386
3412 10:55:28.703474 Set Vref, RX VrefLevel [Byte0]: 62
3413 10:55:28.707507 [Byte1]: 62
3414 10:55:28.711952
3415 10:55:28.712104 Set Vref, RX VrefLevel [Byte0]: 63
3416 10:55:28.714608 [Byte1]: 63
3417 10:55:28.719661
3418 10:55:28.719749 Set Vref, RX VrefLevel [Byte0]: 64
3419 10:55:28.722548 [Byte1]: 64
3420 10:55:28.727446
3421 10:55:28.727533 Set Vref, RX VrefLevel [Byte0]: 65
3422 10:55:28.733893 [Byte1]: 65
3423 10:55:28.733983
3424 10:55:28.737291 Set Vref, RX VrefLevel [Byte0]: 66
3425 10:55:28.740867 [Byte1]: 66
3426 10:55:28.740956
3427 10:55:28.743516 Set Vref, RX VrefLevel [Byte0]: 67
3428 10:55:28.747050 [Byte1]: 67
3429 10:55:28.751205
3430 10:55:28.751293 Set Vref, RX VrefLevel [Byte0]: 68
3431 10:55:28.755215 [Byte1]: 68
3432 10:55:28.758784
3433 10:55:28.758871 Set Vref, RX VrefLevel [Byte0]: 69
3434 10:55:28.762143 [Byte1]: 69
3435 10:55:28.766665
3436 10:55:28.766755 Final RX Vref Byte 0 = 47 to rank0
3437 10:55:28.770489 Final RX Vref Byte 1 = 54 to rank0
3438 10:55:28.773237 Final RX Vref Byte 0 = 47 to rank1
3439 10:55:28.777055 Final RX Vref Byte 1 = 54 to rank1==
3440 10:55:28.781074 Dram Type= 6, Freq= 0, CH_1, rank 0
3441 10:55:28.787163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 10:55:28.787254 ==
3443 10:55:28.787320 DQS Delay:
3444 10:55:28.787380 DQS0 = 0, DQS1 = 0
3445 10:55:28.790460 DQM Delay:
3446 10:55:28.790542 DQM0 = 116, DQM1 = 110
3447 10:55:28.793374 DQ Delay:
3448 10:55:28.797318 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3449 10:55:28.800126 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3450 10:55:28.803475 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3451 10:55:28.806821 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3452 10:55:28.806907
3453 10:55:28.806972
3454 10:55:28.813513 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3455 10:55:28.816501 CH1 RK0: MR19=403, MR18=F4
3456 10:55:28.823468 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3457 10:55:28.823570
3458 10:55:28.827101 ----->DramcWriteLeveling(PI) begin...
3459 10:55:28.827187 ==
3460 10:55:28.830103 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 10:55:28.833324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 10:55:28.833409 ==
3463 10:55:28.836457 Write leveling (Byte 0): 24 => 24
3464 10:55:28.840117 Write leveling (Byte 1): 28 => 28
3465 10:55:28.843353 DramcWriteLeveling(PI) end<-----
3466 10:55:28.843439
3467 10:55:28.843503 ==
3468 10:55:28.847413 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 10:55:28.853565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 10:55:28.853663 ==
3471 10:55:28.853730 [Gating] SW mode calibration
3472 10:55:28.863054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3473 10:55:28.866410 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3474 10:55:28.870184 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 10:55:28.876401 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 10:55:28.879762 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 10:55:28.883154 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 10:55:28.889203 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 10:55:28.892399 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 10:55:28.899273 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 1)
3481 10:55:28.902745 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 1)
3482 10:55:28.906243 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 10:55:28.912843 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 10:55:28.915690 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 10:55:28.918965 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 10:55:28.925617 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 10:55:28.928818 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3488 10:55:28.932249 1 0 24 | B1->B0 | 3636 2828 | 0 0 | (0 0) (0 0)
3489 10:55:28.935576 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3490 10:55:28.942542 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 10:55:28.945447 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 10:55:28.948586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 10:55:28.956372 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 10:55:28.959121 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 10:55:28.961764 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 10:55:28.968720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3497 10:55:28.971652 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3498 10:55:28.975322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 10:55:28.981507 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 10:55:28.985013 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 10:55:28.988667 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 10:55:28.994746 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 10:55:28.998252 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 10:55:29.004815 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 10:55:29.008159 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 10:55:29.011072 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 10:55:29.014550 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 10:55:29.020942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 10:55:29.024263 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:55:29.030898 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:55:29.034087 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 10:55:29.037369 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 10:55:29.044310 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3514 10:55:29.044445 Total UI for P1: 0, mck2ui 16
3515 10:55:29.050673 best dqsien dly found for B1: ( 1, 3, 24)
3516 10:55:29.053970 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 10:55:29.057346 Total UI for P1: 0, mck2ui 16
3518 10:55:29.060762 best dqsien dly found for B0: ( 1, 3, 26)
3519 10:55:29.063968 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3520 10:55:29.066885 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3521 10:55:29.066973
3522 10:55:29.070478 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 10:55:29.074500 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3524 10:55:29.076758 [Gating] SW calibration Done
3525 10:55:29.076846 ==
3526 10:55:29.080024 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 10:55:29.083637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 10:55:29.086800 ==
3529 10:55:29.086890 RX Vref Scan: 0
3530 10:55:29.086958
3531 10:55:29.089872 RX Vref 0 -> 0, step: 1
3532 10:55:29.089956
3533 10:55:29.093603 RX Delay -40 -> 252, step: 8
3534 10:55:29.096890 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3535 10:55:29.100348 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3536 10:55:29.103864 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3537 10:55:29.107037 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3538 10:55:29.113681 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3539 10:55:29.116286 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3540 10:55:29.119652 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3541 10:55:29.122813 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3542 10:55:29.126219 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3543 10:55:29.132736 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3544 10:55:29.136044 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3545 10:55:29.139384 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3546 10:55:29.142594 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3547 10:55:29.149141 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3548 10:55:29.152801 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3549 10:55:29.156198 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3550 10:55:29.156289 ==
3551 10:55:29.158874 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 10:55:29.163172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 10:55:29.163260 ==
3554 10:55:29.165626 DQS Delay:
3555 10:55:29.165711 DQS0 = 0, DQS1 = 0
3556 10:55:29.170245 DQM Delay:
3557 10:55:29.170335 DQM0 = 116, DQM1 = 110
3558 10:55:29.170402 DQ Delay:
3559 10:55:29.175522 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3560 10:55:29.178901 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3561 10:55:29.182017 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3562 10:55:29.185518 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3563 10:55:29.185610
3564 10:55:29.185675
3565 10:55:29.185735 ==
3566 10:55:29.188965 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 10:55:29.192721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 10:55:29.192811 ==
3569 10:55:29.192882
3570 10:55:29.192944
3571 10:55:29.195374 TX Vref Scan disable
3572 10:55:29.198570 == TX Byte 0 ==
3573 10:55:29.202027 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3574 10:55:29.205615 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3575 10:55:29.208833 == TX Byte 1 ==
3576 10:55:29.212072 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 10:55:29.215663 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 10:55:29.215754 ==
3579 10:55:29.218912 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 10:55:29.222253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 10:55:29.225060 ==
3582 10:55:29.235351 TX Vref=22, minBit 9, minWin=24, winSum=424
3583 10:55:29.238840 TX Vref=24, minBit 9, minWin=26, winSum=431
3584 10:55:29.242329 TX Vref=26, minBit 9, minWin=25, winSum=435
3585 10:55:29.245427 TX Vref=28, minBit 9, minWin=26, winSum=436
3586 10:55:29.248804 TX Vref=30, minBit 8, minWin=26, winSum=438
3587 10:55:29.255207 TX Vref=32, minBit 9, minWin=26, winSum=437
3588 10:55:29.259691 [TxChooseVref] Worse bit 8, Min win 26, Win sum 438, Final Vref 30
3589 10:55:29.259791
3590 10:55:29.262345 Final TX Range 1 Vref 30
3591 10:55:29.262439
3592 10:55:29.262507 ==
3593 10:55:29.265071 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 10:55:29.271738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 10:55:29.271835 ==
3596 10:55:29.271905
3597 10:55:29.271965
3598 10:55:29.272023 TX Vref Scan disable
3599 10:55:29.275204 == TX Byte 0 ==
3600 10:55:29.278509 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3601 10:55:29.285456 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3602 10:55:29.285564 == TX Byte 1 ==
3603 10:55:29.288350 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 10:55:29.295154 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 10:55:29.295261
3606 10:55:29.295372 [DATLAT]
3607 10:55:29.295453 Freq=1200, CH1 RK1
3608 10:55:29.295545
3609 10:55:29.298153 DATLAT Default: 0xd
3610 10:55:29.301381 0, 0xFFFF, sum = 0
3611 10:55:29.301494 1, 0xFFFF, sum = 0
3612 10:55:29.305027 2, 0xFFFF, sum = 0
3613 10:55:29.305113 3, 0xFFFF, sum = 0
3614 10:55:29.308142 4, 0xFFFF, sum = 0
3615 10:55:29.308228 5, 0xFFFF, sum = 0
3616 10:55:29.311819 6, 0xFFFF, sum = 0
3617 10:55:29.311907 7, 0xFFFF, sum = 0
3618 10:55:29.314554 8, 0xFFFF, sum = 0
3619 10:55:29.314638 9, 0xFFFF, sum = 0
3620 10:55:29.318844 10, 0xFFFF, sum = 0
3621 10:55:29.318931 11, 0xFFFF, sum = 0
3622 10:55:29.321132 12, 0x0, sum = 1
3623 10:55:29.321217 13, 0x0, sum = 2
3624 10:55:29.324948 14, 0x0, sum = 3
3625 10:55:29.325034 15, 0x0, sum = 4
3626 10:55:29.327552 best_step = 13
3627 10:55:29.327636
3628 10:55:29.327702 ==
3629 10:55:29.331161 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 10:55:29.334890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 10:55:29.334981 ==
3632 10:55:29.338047 RX Vref Scan: 0
3633 10:55:29.338136
3634 10:55:29.338203 RX Vref 0 -> 0, step: 1
3635 10:55:29.338264
3636 10:55:29.340827 RX Delay -21 -> 252, step: 4
3637 10:55:29.347401 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3638 10:55:29.350747 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3639 10:55:29.354123 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3640 10:55:29.357744 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3641 10:55:29.363728 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3642 10:55:29.367455 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3643 10:55:29.370629 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3644 10:55:29.374135 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3645 10:55:29.376926 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3646 10:55:29.383423 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3647 10:55:29.387100 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3648 10:55:29.392863 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3649 10:55:29.393415 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3650 10:55:29.396439 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3651 10:55:29.403333 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3652 10:55:29.406904 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3653 10:55:29.407008 ==
3654 10:55:29.409893 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 10:55:29.413739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 10:55:29.413829 ==
3657 10:55:29.416749 DQS Delay:
3658 10:55:29.416834 DQS0 = 0, DQS1 = 0
3659 10:55:29.419790 DQM Delay:
3660 10:55:29.419879 DQM0 = 116, DQM1 = 110
3661 10:55:29.419946 DQ Delay:
3662 10:55:29.423079 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3663 10:55:29.429628 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3664 10:55:29.432771 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3665 10:55:29.436405 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3666 10:55:29.436570
3667 10:55:29.436642
3668 10:55:29.442523 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3669 10:55:29.446114 CH1 RK1: MR19=303, MR18=F3EE
3670 10:55:29.452623 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3671 10:55:29.456283 [RxdqsGatingPostProcess] freq 1200
3672 10:55:29.462498 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 10:55:29.465840 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 10:55:29.465935 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 10:55:29.469228 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 10:55:29.472761 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 10:55:29.475590 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 10:55:29.478770 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 10:55:29.482005 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 10:55:29.485305 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 10:55:29.489241 Pre-setting of DQS Precalculation
3682 10:55:29.495391 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 10:55:29.502474 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 10:55:29.508634 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 10:55:29.508754
3686 10:55:29.508826
3687 10:55:29.511803 [Calibration Summary] 2400 Mbps
3688 10:55:29.511890 CH 0, Rank 0
3689 10:55:29.515206 SW Impedance : PASS
3690 10:55:29.518437 DUTY Scan : NO K
3691 10:55:29.518526 ZQ Calibration : PASS
3692 10:55:29.521733 Jitter Meter : NO K
3693 10:55:29.525111 CBT Training : PASS
3694 10:55:29.525200 Write leveling : PASS
3695 10:55:29.528489 RX DQS gating : PASS
3696 10:55:29.531788 RX DQ/DQS(RDDQC) : PASS
3697 10:55:29.531878 TX DQ/DQS : PASS
3698 10:55:29.535066 RX DATLAT : PASS
3699 10:55:29.538517 RX DQ/DQS(Engine): PASS
3700 10:55:29.538614 TX OE : NO K
3701 10:55:29.541572 All Pass.
3702 10:55:29.541658
3703 10:55:29.541725 CH 0, Rank 1
3704 10:55:29.544865 SW Impedance : PASS
3705 10:55:29.544950 DUTY Scan : NO K
3706 10:55:29.548441 ZQ Calibration : PASS
3707 10:55:29.551106 Jitter Meter : NO K
3708 10:55:29.551192 CBT Training : PASS
3709 10:55:29.554680 Write leveling : PASS
3710 10:55:29.558070 RX DQS gating : PASS
3711 10:55:29.558158 RX DQ/DQS(RDDQC) : PASS
3712 10:55:29.561333 TX DQ/DQS : PASS
3713 10:55:29.564870 RX DATLAT : PASS
3714 10:55:29.564958 RX DQ/DQS(Engine): PASS
3715 10:55:29.568042 TX OE : NO K
3716 10:55:29.568128 All Pass.
3717 10:55:29.568195
3718 10:55:29.571162 CH 1, Rank 0
3719 10:55:29.571247 SW Impedance : PASS
3720 10:55:29.574459 DUTY Scan : NO K
3721 10:55:29.574544 ZQ Calibration : PASS
3722 10:55:29.578158 Jitter Meter : NO K
3723 10:55:29.581566 CBT Training : PASS
3724 10:55:29.581654 Write leveling : PASS
3725 10:55:29.584763 RX DQS gating : PASS
3726 10:55:29.587498 RX DQ/DQS(RDDQC) : PASS
3727 10:55:29.587584 TX DQ/DQS : PASS
3728 10:55:29.591077 RX DATLAT : PASS
3729 10:55:29.594464 RX DQ/DQS(Engine): PASS
3730 10:55:29.594552 TX OE : NO K
3731 10:55:29.598473 All Pass.
3732 10:55:29.598561
3733 10:55:29.598628 CH 1, Rank 1
3734 10:55:29.601260 SW Impedance : PASS
3735 10:55:29.601345 DUTY Scan : NO K
3736 10:55:29.604387 ZQ Calibration : PASS
3737 10:55:29.607491 Jitter Meter : NO K
3738 10:55:29.607578 CBT Training : PASS
3739 10:55:29.611236 Write leveling : PASS
3740 10:55:29.613864 RX DQS gating : PASS
3741 10:55:29.613960 RX DQ/DQS(RDDQC) : PASS
3742 10:55:29.618719 TX DQ/DQS : PASS
3743 10:55:29.620829 RX DATLAT : PASS
3744 10:55:29.620916 RX DQ/DQS(Engine): PASS
3745 10:55:29.624414 TX OE : NO K
3746 10:55:29.624500 All Pass.
3747 10:55:29.624610
3748 10:55:29.627347 DramC Write-DBI off
3749 10:55:29.630722 PER_BANK_REFRESH: Hybrid Mode
3750 10:55:29.630809 TX_TRACKING: ON
3751 10:55:29.640341 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 10:55:29.643644 [FAST_K] Save calibration result to emmc
3753 10:55:29.647124 dramc_set_vcore_voltage set vcore to 650000
3754 10:55:29.650433 Read voltage for 600, 5
3755 10:55:29.650523 Vio18 = 0
3756 10:55:29.650590 Vcore = 650000
3757 10:55:29.653891 Vdram = 0
3758 10:55:29.653974 Vddq = 0
3759 10:55:29.654040 Vmddr = 0
3760 10:55:29.660793 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 10:55:29.663656 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 10:55:29.667143 MEM_TYPE=3, freq_sel=19
3763 10:55:29.670393 sv_algorithm_assistance_LP4_1600
3764 10:55:29.673621 ============ PULL DRAM RESETB DOWN ============
3765 10:55:29.676721 ========== PULL DRAM RESETB DOWN end =========
3766 10:55:29.683198 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 10:55:29.686605 ===================================
3768 10:55:29.689704 LPDDR4 DRAM CONFIGURATION
3769 10:55:29.693619 ===================================
3770 10:55:29.693712 EX_ROW_EN[0] = 0x0
3771 10:55:29.696393 EX_ROW_EN[1] = 0x0
3772 10:55:29.696477 LP4Y_EN = 0x0
3773 10:55:29.700306 WORK_FSP = 0x0
3774 10:55:29.700394 WL = 0x2
3775 10:55:29.703274 RL = 0x2
3776 10:55:29.703359 BL = 0x2
3777 10:55:29.707284 RPST = 0x0
3778 10:55:29.707369 RD_PRE = 0x0
3779 10:55:29.709832 WR_PRE = 0x1
3780 10:55:29.709917 WR_PST = 0x0
3781 10:55:29.712904 DBI_WR = 0x0
3782 10:55:29.716123 DBI_RD = 0x0
3783 10:55:29.716209 OTF = 0x1
3784 10:55:29.719517 ===================================
3785 10:55:29.723737 ===================================
3786 10:55:29.723827 ANA top config
3787 10:55:29.726268 ===================================
3788 10:55:29.729513 DLL_ASYNC_EN = 0
3789 10:55:29.732773 ALL_SLAVE_EN = 1
3790 10:55:29.736395 NEW_RANK_MODE = 1
3791 10:55:29.739834 DLL_IDLE_MODE = 1
3792 10:55:29.739926 LP45_APHY_COMB_EN = 1
3793 10:55:29.742743 TX_ODT_DIS = 1
3794 10:55:29.745720 NEW_8X_MODE = 1
3795 10:55:29.749009 ===================================
3796 10:55:29.752421 ===================================
3797 10:55:29.756242 data_rate = 1200
3798 10:55:29.759036 CKR = 1
3799 10:55:29.762294 DQ_P2S_RATIO = 8
3800 10:55:29.765301 ===================================
3801 10:55:29.765392 CA_P2S_RATIO = 8
3802 10:55:29.768886 DQ_CA_OPEN = 0
3803 10:55:29.772430 DQ_SEMI_OPEN = 0
3804 10:55:29.775447 CA_SEMI_OPEN = 0
3805 10:55:29.779294 CA_FULL_RATE = 0
3806 10:55:29.782364 DQ_CKDIV4_EN = 1
3807 10:55:29.782454 CA_CKDIV4_EN = 1
3808 10:55:29.785397 CA_PREDIV_EN = 0
3809 10:55:29.788955 PH8_DLY = 0
3810 10:55:29.792195 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 10:55:29.795542 DQ_AAMCK_DIV = 4
3812 10:55:29.798346 CA_AAMCK_DIV = 4
3813 10:55:29.798435 CA_ADMCK_DIV = 4
3814 10:55:29.801950 DQ_TRACK_CA_EN = 0
3815 10:55:29.804937 CA_PICK = 600
3816 10:55:29.809015 CA_MCKIO = 600
3817 10:55:29.811611 MCKIO_SEMI = 0
3818 10:55:29.814994 PLL_FREQ = 2288
3819 10:55:29.818375 DQ_UI_PI_RATIO = 32
3820 10:55:29.821459 CA_UI_PI_RATIO = 0
3821 10:55:29.825136 ===================================
3822 10:55:29.828218 ===================================
3823 10:55:29.828306 memory_type:LPDDR4
3824 10:55:29.831523 GP_NUM : 10
3825 10:55:29.831609 SRAM_EN : 1
3826 10:55:29.835120 MD32_EN : 0
3827 10:55:29.837880 ===================================
3828 10:55:29.841398 [ANA_INIT] >>>>>>>>>>>>>>
3829 10:55:29.845218 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 10:55:29.848162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 10:55:29.851377 ===================================
3832 10:55:29.854963 data_rate = 1200,PCW = 0X5800
3833 10:55:29.858286 ===================================
3834 10:55:29.860955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 10:55:29.864795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 10:55:29.870974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 10:55:29.874413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 10:55:29.877437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 10:55:29.881210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 10:55:29.884944 [ANA_INIT] flow start
3841 10:55:29.887744 [ANA_INIT] PLL >>>>>>>>
3842 10:55:29.887833 [ANA_INIT] PLL <<<<<<<<
3843 10:55:29.891256 [ANA_INIT] MIDPI >>>>>>>>
3844 10:55:29.894273 [ANA_INIT] MIDPI <<<<<<<<
3845 10:55:29.897782 [ANA_INIT] DLL >>>>>>>>
3846 10:55:29.897872 [ANA_INIT] flow end
3847 10:55:29.900665 ============ LP4 DIFF to SE enter ============
3848 10:55:29.907863 ============ LP4 DIFF to SE exit ============
3849 10:55:29.907967 [ANA_INIT] <<<<<<<<<<<<<
3850 10:55:29.910842 [Flow] Enable top DCM control >>>>>
3851 10:55:29.914125 [Flow] Enable top DCM control <<<<<
3852 10:55:29.917783 Enable DLL master slave shuffle
3853 10:55:29.923677 ==============================================================
3854 10:55:29.923779 Gating Mode config
3855 10:55:29.930460 ==============================================================
3856 10:55:29.933950 Config description:
3857 10:55:29.943655 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 10:55:29.950314 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 10:55:29.953501 SELPH_MODE 0: By rank 1: By Phase
3860 10:55:29.960374 ==============================================================
3861 10:55:29.963522 GAT_TRACK_EN = 1
3862 10:55:29.966796 RX_GATING_MODE = 2
3863 10:55:29.966889 RX_GATING_TRACK_MODE = 2
3864 10:55:29.969976 SELPH_MODE = 1
3865 10:55:29.973812 PICG_EARLY_EN = 1
3866 10:55:29.976673 VALID_LAT_VALUE = 1
3867 10:55:29.983966 ==============================================================
3868 10:55:29.986762 Enter into Gating configuration >>>>
3869 10:55:29.989860 Exit from Gating configuration <<<<
3870 10:55:29.993416 Enter into DVFS_PRE_config >>>>>
3871 10:55:30.002774 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 10:55:30.006643 Exit from DVFS_PRE_config <<<<<
3873 10:55:30.009454 Enter into PICG configuration >>>>
3874 10:55:30.012999 Exit from PICG configuration <<<<
3875 10:55:30.016208 [RX_INPUT] configuration >>>>>
3876 10:55:30.019258 [RX_INPUT] configuration <<<<<
3877 10:55:30.022864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 10:55:30.029114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 10:55:30.036147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 10:55:30.042369 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 10:55:30.049058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 10:55:30.055571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 10:55:30.059250 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 10:55:30.062176 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 10:55:30.065674 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 10:55:30.072181 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 10:55:30.075320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 10:55:30.078820 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 10:55:30.082575 ===================================
3890 10:55:30.085044 LPDDR4 DRAM CONFIGURATION
3891 10:55:30.088638 ===================================
3892 10:55:30.088737 EX_ROW_EN[0] = 0x0
3893 10:55:30.091667 EX_ROW_EN[1] = 0x0
3894 10:55:30.091756 LP4Y_EN = 0x0
3895 10:55:30.095133 WORK_FSP = 0x0
3896 10:55:30.098304 WL = 0x2
3897 10:55:30.098391 RL = 0x2
3898 10:55:30.101791 BL = 0x2
3899 10:55:30.101877 RPST = 0x0
3900 10:55:30.105543 RD_PRE = 0x0
3901 10:55:30.105629 WR_PRE = 0x1
3902 10:55:30.108296 WR_PST = 0x0
3903 10:55:30.108380 DBI_WR = 0x0
3904 10:55:30.111689 DBI_RD = 0x0
3905 10:55:30.111773 OTF = 0x1
3906 10:55:30.114976 ===================================
3907 10:55:30.118278 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 10:55:30.125047 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 10:55:30.128246 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 10:55:30.131326 ===================================
3911 10:55:30.134646 LPDDR4 DRAM CONFIGURATION
3912 10:55:30.137798 ===================================
3913 10:55:30.137899 EX_ROW_EN[0] = 0x10
3914 10:55:30.141383 EX_ROW_EN[1] = 0x0
3915 10:55:30.141476 LP4Y_EN = 0x0
3916 10:55:30.144912 WORK_FSP = 0x0
3917 10:55:30.148356 WL = 0x2
3918 10:55:30.148476 RL = 0x2
3919 10:55:30.151412 BL = 0x2
3920 10:55:30.151497 RPST = 0x0
3921 10:55:30.154578 RD_PRE = 0x0
3922 10:55:30.154663 WR_PRE = 0x1
3923 10:55:30.157987 WR_PST = 0x0
3924 10:55:30.158075 DBI_WR = 0x0
3925 10:55:30.161383 DBI_RD = 0x0
3926 10:55:30.161470 OTF = 0x1
3927 10:55:30.164466 ===================================
3928 10:55:30.171134 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 10:55:30.175370 nWR fixed to 30
3930 10:55:30.178655 [ModeRegInit_LP4] CH0 RK0
3931 10:55:30.178745 [ModeRegInit_LP4] CH0 RK1
3932 10:55:30.181773 [ModeRegInit_LP4] CH1 RK0
3933 10:55:30.185121 [ModeRegInit_LP4] CH1 RK1
3934 10:55:30.185211 match AC timing 17
3935 10:55:30.191464 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 10:55:30.194938 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 10:55:30.198482 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 10:55:30.205102 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 10:55:30.208452 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 10:55:30.208562 ==
3941 10:55:30.212162 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 10:55:30.215126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 10:55:30.215217 ==
3944 10:55:30.221370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 10:55:30.227783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3946 10:55:30.231218 [CA 0] Center 36 (6~66) winsize 61
3947 10:55:30.235025 [CA 1] Center 36 (6~66) winsize 61
3948 10:55:30.237937 [CA 2] Center 34 (4~64) winsize 61
3949 10:55:30.240864 [CA 3] Center 34 (4~65) winsize 62
3950 10:55:30.244175 [CA 4] Center 33 (3~64) winsize 62
3951 10:55:30.247700 [CA 5] Center 33 (3~64) winsize 62
3952 10:55:30.247793
3953 10:55:30.250853 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3954 10:55:30.250942
3955 10:55:30.254382 [CATrainingPosCal] consider 1 rank data
3956 10:55:30.257609 u2DelayCellTimex100 = 270/100 ps
3957 10:55:30.260675 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 10:55:30.264103 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3959 10:55:30.267468 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3960 10:55:30.273986 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 10:55:30.277400 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 10:55:30.280326 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 10:55:30.280417
3964 10:55:30.283659 CA PerBit enable=1, Macro0, CA PI delay=33
3965 10:55:30.283747
3966 10:55:30.287399 [CBTSetCACLKResult] CA Dly = 33
3967 10:55:30.287486 CS Dly: 5 (0~36)
3968 10:55:30.287572 ==
3969 10:55:30.290700 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 10:55:30.296963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 10:55:30.297068 ==
3972 10:55:30.300571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 10:55:30.306661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 10:55:30.310753 [CA 0] Center 35 (5~66) winsize 62
3975 10:55:30.313652 [CA 1] Center 36 (6~66) winsize 61
3976 10:55:30.317264 [CA 2] Center 34 (4~64) winsize 61
3977 10:55:30.320385 [CA 3] Center 34 (4~64) winsize 61
3978 10:55:30.323552 [CA 4] Center 33 (2~64) winsize 63
3979 10:55:30.326795 [CA 5] Center 33 (2~64) winsize 63
3980 10:55:30.326883
3981 10:55:30.330465 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 10:55:30.330553
3983 10:55:30.334324 [CATrainingPosCal] consider 2 rank data
3984 10:55:30.337030 u2DelayCellTimex100 = 270/100 ps
3985 10:55:30.340639 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 10:55:30.346778 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3987 10:55:30.350124 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3988 10:55:30.353264 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3989 10:55:30.356855 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 10:55:30.360367 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 10:55:30.360459
3992 10:55:30.363118 CA PerBit enable=1, Macro0, CA PI delay=33
3993 10:55:30.363206
3994 10:55:30.366706 [CBTSetCACLKResult] CA Dly = 33
3995 10:55:30.369869 CS Dly: 5 (0~36)
3996 10:55:30.369958
3997 10:55:30.373376 ----->DramcWriteLeveling(PI) begin...
3998 10:55:30.373466 ==
3999 10:55:30.376363 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 10:55:30.379841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 10:55:30.379930 ==
4002 10:55:30.383654 Write leveling (Byte 0): 32 => 32
4003 10:55:30.386262 Write leveling (Byte 1): 30 => 30
4004 10:55:30.389835 DramcWriteLeveling(PI) end<-----
4005 10:55:30.389925
4006 10:55:30.390013 ==
4007 10:55:30.393061 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 10:55:30.396236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 10:55:30.396327 ==
4010 10:55:30.399759 [Gating] SW mode calibration
4011 10:55:30.406666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 10:55:30.413173 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 10:55:30.416227 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 10:55:30.419515 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 10:55:30.426255 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 10:55:30.429367 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
4017 10:55:30.432465 0 9 16 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
4018 10:55:30.439829 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 10:55:30.442453 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 10:55:30.446428 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 10:55:30.452487 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 10:55:30.455867 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 10:55:30.459380 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 10:55:30.465518 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 10:55:30.469251 0 10 16 | B1->B0 | 3030 4242 | 1 0 | (0 0) (0 0)
4026 10:55:30.472567 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 10:55:30.478920 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 10:55:30.481898 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 10:55:30.485176 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 10:55:30.492009 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 10:55:30.495245 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 10:55:30.498710 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 10:55:30.505653 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4034 10:55:30.508758 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 10:55:30.511962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 10:55:30.518068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 10:55:30.521952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 10:55:30.525166 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 10:55:30.532112 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 10:55:30.534634 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 10:55:30.537933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 10:55:30.545004 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 10:55:30.548268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 10:55:30.551371 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 10:55:30.558021 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:55:30.561747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:55:30.564627 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:55:30.571158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4049 10:55:30.574474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4050 10:55:30.577815 Total UI for P1: 0, mck2ui 16
4051 10:55:30.581802 best dqsien dly found for B0: ( 0, 13, 12)
4052 10:55:30.584393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 10:55:30.587730 Total UI for P1: 0, mck2ui 16
4054 10:55:30.590738 best dqsien dly found for B1: ( 0, 13, 16)
4055 10:55:30.594011 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4056 10:55:30.597592 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4057 10:55:30.600821
4058 10:55:30.604277 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4059 10:55:30.607717 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4060 10:55:30.611177 [Gating] SW calibration Done
4061 10:55:30.611274 ==
4062 10:55:30.614042 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 10:55:30.618121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 10:55:30.618228 ==
4065 10:55:30.618301 RX Vref Scan: 0
4066 10:55:30.620431
4067 10:55:30.620541 RX Vref 0 -> 0, step: 1
4068 10:55:30.620622
4069 10:55:30.624061 RX Delay -230 -> 252, step: 16
4070 10:55:30.627291 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4071 10:55:30.634067 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4072 10:55:30.637035 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4073 10:55:30.640694 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4074 10:55:30.644076 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4075 10:55:30.646836 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4076 10:55:30.653926 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4077 10:55:30.657659 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4078 10:55:30.660449 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4079 10:55:30.663386 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4080 10:55:30.670552 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4081 10:55:30.673387 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4082 10:55:30.677048 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4083 10:55:30.680084 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4084 10:55:30.686801 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4085 10:55:30.690037 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4086 10:55:30.690133 ==
4087 10:55:30.693266 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 10:55:30.696425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 10:55:30.696511 ==
4090 10:55:30.700340 DQS Delay:
4091 10:55:30.700426 DQS0 = 0, DQS1 = 0
4092 10:55:30.700492 DQM Delay:
4093 10:55:30.703186 DQM0 = 46, DQM1 = 33
4094 10:55:30.703269 DQ Delay:
4095 10:55:30.707082 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4096 10:55:30.709604 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4097 10:55:30.713252 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4098 10:55:30.716772 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4099 10:55:30.716862
4100 10:55:30.716927
4101 10:55:30.716988 ==
4102 10:55:30.719874 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 10:55:30.726598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 10:55:30.726699 ==
4105 10:55:30.726768
4106 10:55:30.726828
4107 10:55:30.726887 TX Vref Scan disable
4108 10:55:30.730046 == TX Byte 0 ==
4109 10:55:30.733602 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4110 10:55:30.740328 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4111 10:55:30.740468 == TX Byte 1 ==
4112 10:55:30.743591 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4113 10:55:30.750112 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4114 10:55:30.750213 ==
4115 10:55:30.753277 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 10:55:30.757359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 10:55:30.757465 ==
4118 10:55:30.757561
4119 10:55:30.757635
4120 10:55:30.760233 TX Vref Scan disable
4121 10:55:30.763144 == TX Byte 0 ==
4122 10:55:30.766749 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4123 10:55:30.769808 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4124 10:55:30.773038 == TX Byte 1 ==
4125 10:55:30.776907 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4126 10:55:30.779899 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4127 10:55:30.779987
4128 10:55:30.780071 [DATLAT]
4129 10:55:30.782984 Freq=600, CH0 RK0
4130 10:55:30.783069
4131 10:55:30.786280 DATLAT Default: 0x9
4132 10:55:30.786363 0, 0xFFFF, sum = 0
4133 10:55:30.789618 1, 0xFFFF, sum = 0
4134 10:55:30.789704 2, 0xFFFF, sum = 0
4135 10:55:30.792884 3, 0xFFFF, sum = 0
4136 10:55:30.792970 4, 0xFFFF, sum = 0
4137 10:55:30.796360 5, 0xFFFF, sum = 0
4138 10:55:30.796448 6, 0xFFFF, sum = 0
4139 10:55:30.799749 7, 0xFFFF, sum = 0
4140 10:55:30.799837 8, 0x0, sum = 1
4141 10:55:30.802932 9, 0x0, sum = 2
4142 10:55:30.803019 10, 0x0, sum = 3
4143 10:55:30.806252 11, 0x0, sum = 4
4144 10:55:30.806340 best_step = 9
4145 10:55:30.806407
4146 10:55:30.806467 ==
4147 10:55:30.809635 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 10:55:30.813130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 10:55:30.813217 ==
4150 10:55:30.816212 RX Vref Scan: 1
4151 10:55:30.816311
4152 10:55:30.819058 RX Vref 0 -> 0, step: 1
4153 10:55:30.819142
4154 10:55:30.819209 RX Delay -179 -> 252, step: 8
4155 10:55:30.822617
4156 10:55:30.822701 Set Vref, RX VrefLevel [Byte0]: 61
4157 10:55:30.825914 [Byte1]: 50
4158 10:55:30.830677
4159 10:55:30.830769 Final RX Vref Byte 0 = 61 to rank0
4160 10:55:30.834024 Final RX Vref Byte 1 = 50 to rank0
4161 10:55:30.837078 Final RX Vref Byte 0 = 61 to rank1
4162 10:55:30.840446 Final RX Vref Byte 1 = 50 to rank1==
4163 10:55:30.844157 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 10:55:30.850365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 10:55:30.850472 ==
4166 10:55:30.850541 DQS Delay:
4167 10:55:30.853987 DQS0 = 0, DQS1 = 0
4168 10:55:30.854073 DQM Delay:
4169 10:55:30.854140 DQM0 = 43, DQM1 = 32
4170 10:55:30.857027 DQ Delay:
4171 10:55:30.860096 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4172 10:55:30.863438 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4173 10:55:30.866915 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4174 10:55:30.870542 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4175 10:55:30.870631
4176 10:55:30.870697
4177 10:55:30.877046 [DQSOSCAuto] RK0, (LSB)MR18= 0x643b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4178 10:55:30.880460 CH0 RK0: MR19=808, MR18=643B
4179 10:55:30.886551 CH0_RK0: MR19=0x808, MR18=0x643B, DQSOSC=391, MR23=63, INC=171, DEC=114
4180 10:55:30.886652
4181 10:55:30.889897 ----->DramcWriteLeveling(PI) begin...
4182 10:55:30.889986 ==
4183 10:55:30.893309 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 10:55:30.896768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 10:55:30.896857 ==
4186 10:55:30.900139 Write leveling (Byte 0): 33 => 33
4187 10:55:30.903304 Write leveling (Byte 1): 32 => 32
4188 10:55:30.906301 DramcWriteLeveling(PI) end<-----
4189 10:55:30.906387
4190 10:55:30.906453 ==
4191 10:55:30.909575 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 10:55:30.916347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 10:55:30.916480 ==
4194 10:55:30.916556 [Gating] SW mode calibration
4195 10:55:30.926667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4196 10:55:30.929635 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4197 10:55:30.932788 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 10:55:30.939251 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 10:55:30.942427 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 10:55:30.945874 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (0 0) (0 0)
4201 10:55:30.952292 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
4202 10:55:30.956492 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 10:55:30.959010 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 10:55:30.966441 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 10:55:30.968739 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 10:55:30.972294 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 10:55:30.979394 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 10:55:30.982426 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4209 10:55:30.985312 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4210 10:55:30.991996 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 10:55:30.995287 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 10:55:30.998536 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 10:55:31.005228 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 10:55:31.008784 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 10:55:31.011629 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 10:55:31.018309 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4217 10:55:31.022091 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4218 10:55:31.024899 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 10:55:31.031620 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 10:55:31.034566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 10:55:31.038127 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 10:55:31.044652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 10:55:31.047950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 10:55:31.051345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 10:55:31.057979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 10:55:31.061170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 10:55:31.065387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 10:55:31.071985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:55:31.074566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:55:31.078540 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:55:31.084482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 10:55:31.088034 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4233 10:55:31.091370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 10:55:31.094630 Total UI for P1: 0, mck2ui 16
4235 10:55:31.098098 best dqsien dly found for B0: ( 0, 13, 12)
4236 10:55:31.101109 Total UI for P1: 0, mck2ui 16
4237 10:55:31.104447 best dqsien dly found for B1: ( 0, 13, 12)
4238 10:55:31.107366 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4239 10:55:31.111005 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4240 10:55:31.114484
4241 10:55:31.117737 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4242 10:55:31.120948 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4243 10:55:31.123878 [Gating] SW calibration Done
4244 10:55:31.123963 ==
4245 10:55:31.127133 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 10:55:31.131135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 10:55:31.131222 ==
4248 10:55:31.133861 RX Vref Scan: 0
4249 10:55:31.133945
4250 10:55:31.134011 RX Vref 0 -> 0, step: 1
4251 10:55:31.134071
4252 10:55:31.137598 RX Delay -230 -> 252, step: 16
4253 10:55:31.140500 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4254 10:55:31.147672 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4255 10:55:31.150471 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4256 10:55:31.153768 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4257 10:55:31.157275 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4258 10:55:31.163612 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4259 10:55:31.166900 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4260 10:55:31.170720 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4261 10:55:31.173396 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4262 10:55:31.176787 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4263 10:55:31.183886 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4264 10:55:31.186737 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4265 10:55:31.190013 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4266 10:55:31.193244 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4267 10:55:31.199570 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4268 10:55:31.202939 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4269 10:55:31.203037 ==
4270 10:55:31.206486 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 10:55:31.210215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 10:55:31.210306 ==
4273 10:55:31.212990 DQS Delay:
4274 10:55:31.213082 DQS0 = 0, DQS1 = 0
4275 10:55:31.216376 DQM Delay:
4276 10:55:31.216482 DQM0 = 42, DQM1 = 35
4277 10:55:31.216594 DQ Delay:
4278 10:55:31.219675 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4279 10:55:31.222706 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4280 10:55:31.226067 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4281 10:55:31.229340 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4282 10:55:31.229449
4283 10:55:31.229545
4284 10:55:31.233032 ==
4285 10:55:31.236037 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 10:55:31.239540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 10:55:31.239638 ==
4288 10:55:31.239720
4289 10:55:31.239811
4290 10:55:31.242457 TX Vref Scan disable
4291 10:55:31.242542 == TX Byte 0 ==
4292 10:55:31.249489 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4293 10:55:31.252498 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4294 10:55:31.252633 == TX Byte 1 ==
4295 10:55:31.259019 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4296 10:55:31.262120 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4297 10:55:31.262214 ==
4298 10:55:31.265451 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 10:55:31.269185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 10:55:31.269291 ==
4301 10:55:31.269360
4302 10:55:31.269420
4303 10:55:31.271904 TX Vref Scan disable
4304 10:55:31.275212 == TX Byte 0 ==
4305 10:55:31.278630 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4306 10:55:31.285491 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4307 10:55:31.285605 == TX Byte 1 ==
4308 10:55:31.288898 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4309 10:55:31.295834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4310 10:55:31.295943
4311 10:55:31.296041 [DATLAT]
4312 10:55:31.296130 Freq=600, CH0 RK1
4313 10:55:31.296218
4314 10:55:31.298531 DATLAT Default: 0x9
4315 10:55:31.298615 0, 0xFFFF, sum = 0
4316 10:55:31.301616 1, 0xFFFF, sum = 0
4317 10:55:31.305090 2, 0xFFFF, sum = 0
4318 10:55:31.305177 3, 0xFFFF, sum = 0
4319 10:55:31.308165 4, 0xFFFF, sum = 0
4320 10:55:31.308252 5, 0xFFFF, sum = 0
4321 10:55:31.311732 6, 0xFFFF, sum = 0
4322 10:55:31.311819 7, 0xFFFF, sum = 0
4323 10:55:31.314895 8, 0x0, sum = 1
4324 10:55:31.314982 9, 0x0, sum = 2
4325 10:55:31.315085 10, 0x0, sum = 3
4326 10:55:31.318756 11, 0x0, sum = 4
4327 10:55:31.318842 best_step = 9
4328 10:55:31.318906
4329 10:55:31.321467 ==
4330 10:55:31.321537 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 10:55:31.328358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 10:55:31.328454 ==
4333 10:55:31.328526 RX Vref Scan: 0
4334 10:55:31.328624
4335 10:55:31.331645 RX Vref 0 -> 0, step: 1
4336 10:55:31.331728
4337 10:55:31.334748 RX Delay -195 -> 252, step: 8
4338 10:55:31.341619 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4339 10:55:31.345035 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4340 10:55:31.347713 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4341 10:55:31.351842 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4342 10:55:31.354516 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4343 10:55:31.361128 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4344 10:55:31.364228 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4345 10:55:31.367583 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4346 10:55:31.371738 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4347 10:55:31.378257 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4348 10:55:31.380802 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4349 10:55:31.384116 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4350 10:55:31.387611 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4351 10:55:31.393975 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4352 10:55:31.397287 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4353 10:55:31.400807 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4354 10:55:31.400897 ==
4355 10:55:31.403768 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 10:55:31.407063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 10:55:31.410784 ==
4358 10:55:31.410872 DQS Delay:
4359 10:55:31.410937 DQS0 = 0, DQS1 = 0
4360 10:55:31.413903 DQM Delay:
4361 10:55:31.413987 DQM0 = 41, DQM1 = 37
4362 10:55:31.417123 DQ Delay:
4363 10:55:31.417212 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4364 10:55:31.420764 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4365 10:55:31.423567 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4366 10:55:31.427659 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4367 10:55:31.430247
4368 10:55:31.430339
4369 10:55:31.436980 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b0e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4370 10:55:31.439968 CH0 RK1: MR19=808, MR18=5B0E
4371 10:55:31.446625 CH0_RK1: MR19=0x808, MR18=0x5B0E, DQSOSC=392, MR23=63, INC=170, DEC=113
4372 10:55:31.450037 [RxdqsGatingPostProcess] freq 600
4373 10:55:31.453054 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4374 10:55:31.456459 Pre-setting of DQS Precalculation
4375 10:55:31.463196 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4376 10:55:31.463298 ==
4377 10:55:31.466361 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 10:55:31.469796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 10:55:31.469884 ==
4380 10:55:31.476265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 10:55:31.479749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 10:55:31.484211 [CA 0] Center 35 (5~66) winsize 62
4383 10:55:31.487995 [CA 1] Center 36 (6~66) winsize 61
4384 10:55:31.490857 [CA 2] Center 34 (4~65) winsize 62
4385 10:55:31.494166 [CA 3] Center 33 (3~64) winsize 62
4386 10:55:31.497645 [CA 4] Center 34 (4~64) winsize 61
4387 10:55:31.500874 [CA 5] Center 33 (3~64) winsize 62
4388 10:55:31.500980
4389 10:55:31.504397 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 10:55:31.504500
4391 10:55:31.507799 [CATrainingPosCal] consider 1 rank data
4392 10:55:31.510797 u2DelayCellTimex100 = 270/100 ps
4393 10:55:31.514292 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 10:55:31.520808 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4395 10:55:31.523854 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 10:55:31.527297 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 10:55:31.530255 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4398 10:55:31.533706 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 10:55:31.533799
4400 10:55:31.536964 CA PerBit enable=1, Macro0, CA PI delay=33
4401 10:55:31.537054
4402 10:55:31.540428 [CBTSetCACLKResult] CA Dly = 33
4403 10:55:31.543544 CS Dly: 4 (0~35)
4404 10:55:31.543635 ==
4405 10:55:31.547109 Dram Type= 6, Freq= 0, CH_1, rank 1
4406 10:55:31.550476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 10:55:31.550568 ==
4408 10:55:31.557420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 10:55:31.560233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4410 10:55:31.564222 [CA 0] Center 35 (5~66) winsize 62
4411 10:55:31.567669 [CA 1] Center 36 (6~66) winsize 61
4412 10:55:31.570849 [CA 2] Center 34 (4~65) winsize 62
4413 10:55:31.574739 [CA 3] Center 34 (3~65) winsize 63
4414 10:55:31.577301 [CA 4] Center 34 (4~65) winsize 62
4415 10:55:31.580890 [CA 5] Center 33 (3~64) winsize 62
4416 10:55:31.580983
4417 10:55:31.584720 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4418 10:55:31.584811
4419 10:55:31.587447 [CATrainingPosCal] consider 2 rank data
4420 10:55:31.590856 u2DelayCellTimex100 = 270/100 ps
4421 10:55:31.594470 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 10:55:31.600257 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4423 10:55:31.603671 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 10:55:31.607236 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 10:55:31.610391 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4426 10:55:31.613603 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 10:55:31.613694
4428 10:55:31.617299 CA PerBit enable=1, Macro0, CA PI delay=33
4429 10:55:31.617387
4430 10:55:31.620170 [CBTSetCACLKResult] CA Dly = 33
4431 10:55:31.623618 CS Dly: 5 (0~37)
4432 10:55:31.623710
4433 10:55:31.627484 ----->DramcWriteLeveling(PI) begin...
4434 10:55:31.627573 ==
4435 10:55:31.630431 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 10:55:31.633953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 10:55:31.634043 ==
4438 10:55:31.637164 Write leveling (Byte 0): 30 => 30
4439 10:55:31.640880 Write leveling (Byte 1): 31 => 31
4440 10:55:31.643172 DramcWriteLeveling(PI) end<-----
4441 10:55:31.643263
4442 10:55:31.643328 ==
4443 10:55:31.646628 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 10:55:31.650055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 10:55:31.650149 ==
4446 10:55:31.653541 [Gating] SW mode calibration
4447 10:55:31.659935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4448 10:55:31.666481 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4449 10:55:31.669671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 10:55:31.673540 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 10:55:31.679862 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 10:55:31.683147 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 0)
4453 10:55:31.686869 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 10:55:31.692771 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 10:55:31.695885 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 10:55:31.699700 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 10:55:31.705869 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 10:55:31.709080 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 10:55:31.712549 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4460 10:55:31.719376 0 10 12 | B1->B0 | 3232 3939 | 1 0 | (0 0) (0 0)
4461 10:55:31.722244 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 10:55:31.725679 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 10:55:31.732099 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 10:55:31.735324 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 10:55:31.738687 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 10:55:31.745442 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 10:55:31.749126 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 10:55:31.752061 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4469 10:55:31.758494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4470 10:55:31.762114 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 10:55:31.765319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 10:55:31.771937 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 10:55:31.774855 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 10:55:31.778304 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 10:55:31.785113 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:55:31.788165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 10:55:31.791710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 10:55:31.798182 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:55:31.801851 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:55:31.805481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:55:31.811666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:55:31.814882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:55:31.818328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:55:31.825244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4485 10:55:31.828052 Total UI for P1: 0, mck2ui 16
4486 10:55:31.831614 best dqsien dly found for B0: ( 0, 13, 10)
4487 10:55:31.835041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 10:55:31.838638 Total UI for P1: 0, mck2ui 16
4489 10:55:31.842400 best dqsien dly found for B1: ( 0, 13, 12)
4490 10:55:31.844781 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4491 10:55:31.847738 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4492 10:55:31.847826
4493 10:55:31.851076 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4494 10:55:31.858152 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4495 10:55:31.858254 [Gating] SW calibration Done
4496 10:55:31.858323 ==
4497 10:55:31.861506 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 10:55:31.867841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 10:55:31.867952 ==
4500 10:55:31.868052 RX Vref Scan: 0
4501 10:55:31.868142
4502 10:55:31.870850 RX Vref 0 -> 0, step: 1
4503 10:55:31.870935
4504 10:55:31.874352 RX Delay -230 -> 252, step: 16
4505 10:55:31.878121 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4506 10:55:31.880809 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4507 10:55:31.887171 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4508 10:55:31.890899 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4509 10:55:31.893933 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4510 10:55:31.897556 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4511 10:55:31.900388 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4512 10:55:31.907715 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4513 10:55:31.910625 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4514 10:55:31.913961 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4515 10:55:31.917428 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4516 10:55:31.923713 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4517 10:55:31.927403 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4518 10:55:31.930727 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4519 10:55:31.933760 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4520 10:55:31.940505 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4521 10:55:31.940638 ==
4522 10:55:31.943314 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 10:55:31.947121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 10:55:31.947204 ==
4525 10:55:31.947287 DQS Delay:
4526 10:55:31.950152 DQS0 = 0, DQS1 = 0
4527 10:55:31.950229 DQM Delay:
4528 10:55:31.953467 DQM0 = 45, DQM1 = 36
4529 10:55:31.953547 DQ Delay:
4530 10:55:31.957200 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4531 10:55:31.960146 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4532 10:55:31.963116 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4533 10:55:31.966790 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4534 10:55:31.966907
4535 10:55:31.967010
4536 10:55:31.967110 ==
4537 10:55:31.969845 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 10:55:31.973963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 10:55:31.976604 ==
4540 10:55:31.976696
4541 10:55:31.976782
4542 10:55:31.976863 TX Vref Scan disable
4543 10:55:31.979875 == TX Byte 0 ==
4544 10:55:31.983217 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4545 10:55:31.986327 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4546 10:55:31.989910 == TX Byte 1 ==
4547 10:55:31.992949 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4548 10:55:31.996674 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4549 10:55:31.999643 ==
4550 10:55:32.003098 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 10:55:32.006333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 10:55:32.006426 ==
4553 10:55:32.006514
4554 10:55:32.006595
4555 10:55:32.009721 TX Vref Scan disable
4556 10:55:32.012860 == TX Byte 0 ==
4557 10:55:32.016013 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4558 10:55:32.019236 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4559 10:55:32.022518 == TX Byte 1 ==
4560 10:55:32.025762 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4561 10:55:32.030013 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4562 10:55:32.030099
4563 10:55:32.030162 [DATLAT]
4564 10:55:32.032502 Freq=600, CH1 RK0
4565 10:55:32.032608
4566 10:55:32.032675 DATLAT Default: 0x9
4567 10:55:32.036282 0, 0xFFFF, sum = 0
4568 10:55:32.039199 1, 0xFFFF, sum = 0
4569 10:55:32.039286 2, 0xFFFF, sum = 0
4570 10:55:32.042597 3, 0xFFFF, sum = 0
4571 10:55:32.042692 4, 0xFFFF, sum = 0
4572 10:55:32.045719 5, 0xFFFF, sum = 0
4573 10:55:32.045839 6, 0xFFFF, sum = 0
4574 10:55:32.049079 7, 0xFFFF, sum = 0
4575 10:55:32.049168 8, 0x0, sum = 1
4576 10:55:32.052707 9, 0x0, sum = 2
4577 10:55:32.052794 10, 0x0, sum = 3
4578 10:55:32.052864 11, 0x0, sum = 4
4579 10:55:32.055607 best_step = 9
4580 10:55:32.055717
4581 10:55:32.055811 ==
4582 10:55:32.058824 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 10:55:32.062312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 10:55:32.062388 ==
4585 10:55:32.065605 RX Vref Scan: 1
4586 10:55:32.065674
4587 10:55:32.068745 RX Vref 0 -> 0, step: 1
4588 10:55:32.068827
4589 10:55:32.068892 RX Delay -195 -> 252, step: 8
4590 10:55:32.068954
4591 10:55:32.072181 Set Vref, RX VrefLevel [Byte0]: 47
4592 10:55:32.075571 [Byte1]: 54
4593 10:55:32.080407
4594 10:55:32.080491 Final RX Vref Byte 0 = 47 to rank0
4595 10:55:32.083786 Final RX Vref Byte 1 = 54 to rank0
4596 10:55:32.086632 Final RX Vref Byte 0 = 47 to rank1
4597 10:55:32.089753 Final RX Vref Byte 1 = 54 to rank1==
4598 10:55:32.093537 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 10:55:32.100023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 10:55:32.100113 ==
4601 10:55:32.100180 DQS Delay:
4602 10:55:32.103579 DQS0 = 0, DQS1 = 0
4603 10:55:32.103663 DQM Delay:
4604 10:55:32.103729 DQM0 = 47, DQM1 = 38
4605 10:55:32.106577 DQ Delay:
4606 10:55:32.109545 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4607 10:55:32.113293 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4608 10:55:32.116160 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4609 10:55:32.119821 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4610 10:55:32.119934
4611 10:55:32.120031
4612 10:55:32.126282 [DQSOSCAuto] RK0, (LSB)MR18= 0x472c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4613 10:55:32.129653 CH1 RK0: MR19=808, MR18=472C
4614 10:55:32.136393 CH1_RK0: MR19=0x808, MR18=0x472C, DQSOSC=396, MR23=63, INC=167, DEC=111
4615 10:55:32.136497
4616 10:55:32.139494 ----->DramcWriteLeveling(PI) begin...
4617 10:55:32.139568 ==
4618 10:55:32.143660 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 10:55:32.146339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 10:55:32.146443 ==
4621 10:55:32.149332 Write leveling (Byte 0): 28 => 28
4622 10:55:32.152404 Write leveling (Byte 1): 29 => 29
4623 10:55:32.155761 DramcWriteLeveling(PI) end<-----
4624 10:55:32.155844
4625 10:55:32.155910 ==
4626 10:55:32.159398 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 10:55:32.162404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 10:55:32.165443 ==
4629 10:55:32.165544 [Gating] SW mode calibration
4630 10:55:32.175720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4631 10:55:32.179194 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4632 10:55:32.182307 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 10:55:32.188845 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 10:55:32.192088 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 10:55:32.195945 0 9 12 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 1)
4636 10:55:32.202058 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4637 10:55:32.205731 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 10:55:32.208837 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 10:55:32.215208 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 10:55:32.218929 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 10:55:32.221820 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 10:55:32.228300 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 10:55:32.231766 0 10 12 | B1->B0 | 2e2e 2e2e | 0 1 | (0 0) (0 0)
4644 10:55:32.235140 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
4645 10:55:32.241620 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 10:55:32.245101 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 10:55:32.248723 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 10:55:32.254577 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 10:55:32.258025 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 10:55:32.260983 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 10:55:32.267790 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4652 10:55:32.270925 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 10:55:32.274521 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 10:55:32.280947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 10:55:32.284537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 10:55:32.287573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 10:55:32.294136 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 10:55:32.297279 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 10:55:32.300461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 10:55:32.307224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 10:55:32.310306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 10:55:32.313692 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:55:32.320192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:55:32.323543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:55:32.327200 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:55:32.333741 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:55:32.336896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 10:55:32.340383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 10:55:32.343542 Total UI for P1: 0, mck2ui 16
4670 10:55:32.346909 best dqsien dly found for B0: ( 0, 13, 14)
4671 10:55:32.350037 Total UI for P1: 0, mck2ui 16
4672 10:55:32.353699 best dqsien dly found for B1: ( 0, 13, 14)
4673 10:55:32.356968 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4674 10:55:32.363508 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4675 10:55:32.363591
4676 10:55:32.366225 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4677 10:55:32.369664 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4678 10:55:32.373016 [Gating] SW calibration Done
4679 10:55:32.373100 ==
4680 10:55:32.376332 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 10:55:32.379832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 10:55:32.379915 ==
4683 10:55:32.383104 RX Vref Scan: 0
4684 10:55:32.383186
4685 10:55:32.383251 RX Vref 0 -> 0, step: 1
4686 10:55:32.383312
4687 10:55:32.386593 RX Delay -230 -> 252, step: 16
4688 10:55:32.389609 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4689 10:55:32.396719 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4690 10:55:32.400308 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4691 10:55:32.402789 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4692 10:55:32.406177 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4693 10:55:32.412951 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4694 10:55:32.415932 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4695 10:55:32.419253 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4696 10:55:32.422582 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4697 10:55:32.425946 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4698 10:55:32.432469 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4699 10:55:32.435817 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4700 10:55:32.438949 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4701 10:55:32.442325 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4702 10:55:32.448872 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4703 10:55:32.452359 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4704 10:55:32.452450 ==
4705 10:55:32.456188 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 10:55:32.459094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 10:55:32.459178 ==
4708 10:55:32.463256 DQS Delay:
4709 10:55:32.463339 DQS0 = 0, DQS1 = 0
4710 10:55:32.465446 DQM Delay:
4711 10:55:32.465529 DQM0 = 47, DQM1 = 41
4712 10:55:32.465596 DQ Delay:
4713 10:55:32.469106 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4714 10:55:32.472052 DQ4 =41, DQ5 =57, DQ6 =65, DQ7 =41
4715 10:55:32.475497 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4716 10:55:32.479111 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4717 10:55:32.479194
4718 10:55:32.479260
4719 10:55:32.482183 ==
4720 10:55:32.485578 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 10:55:32.488466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 10:55:32.488586 ==
4723 10:55:32.488653
4724 10:55:32.488713
4725 10:55:32.491577 TX Vref Scan disable
4726 10:55:32.491663 == TX Byte 0 ==
4727 10:55:32.498613 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4728 10:55:32.502133 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4729 10:55:32.502217 == TX Byte 1 ==
4730 10:55:32.508594 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4731 10:55:32.511650 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4732 10:55:32.511733 ==
4733 10:55:32.514757 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 10:55:32.518331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 10:55:32.518415 ==
4736 10:55:32.518480
4737 10:55:32.518540
4738 10:55:32.521261 TX Vref Scan disable
4739 10:55:32.524801 == TX Byte 0 ==
4740 10:55:32.528196 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4741 10:55:32.531615 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4742 10:55:32.534691 == TX Byte 1 ==
4743 10:55:32.538036 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4744 10:55:32.541612 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4745 10:55:32.541715
4746 10:55:32.544685 [DATLAT]
4747 10:55:32.544770 Freq=600, CH1 RK1
4748 10:55:32.544838
4749 10:55:32.548191 DATLAT Default: 0x9
4750 10:55:32.548275 0, 0xFFFF, sum = 0
4751 10:55:32.551707 1, 0xFFFF, sum = 0
4752 10:55:32.551793 2, 0xFFFF, sum = 0
4753 10:55:32.554407 3, 0xFFFF, sum = 0
4754 10:55:32.554492 4, 0xFFFF, sum = 0
4755 10:55:32.558238 5, 0xFFFF, sum = 0
4756 10:55:32.558323 6, 0xFFFF, sum = 0
4757 10:55:32.561094 7, 0xFFFF, sum = 0
4758 10:55:32.561179 8, 0x0, sum = 1
4759 10:55:32.564789 9, 0x0, sum = 2
4760 10:55:32.564874 10, 0x0, sum = 3
4761 10:55:32.567817 11, 0x0, sum = 4
4762 10:55:32.567901 best_step = 9
4763 10:55:32.567967
4764 10:55:32.568028 ==
4765 10:55:32.571217 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 10:55:32.577502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 10:55:32.577587 ==
4768 10:55:32.577653 RX Vref Scan: 0
4769 10:55:32.577716
4770 10:55:32.580913 RX Vref 0 -> 0, step: 1
4771 10:55:32.580996
4772 10:55:32.584220 RX Delay -179 -> 252, step: 8
4773 10:55:32.587808 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4774 10:55:32.594270 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4775 10:55:32.597841 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4776 10:55:32.600757 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4777 10:55:32.604055 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4778 10:55:32.610801 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4779 10:55:32.614533 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4780 10:55:32.617554 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4781 10:55:32.620656 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4782 10:55:32.623891 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4783 10:55:32.630361 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4784 10:55:32.633380 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4785 10:55:32.636821 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4786 10:55:32.639961 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4787 10:55:32.646879 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4788 10:55:32.649750 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4789 10:55:32.649828 ==
4790 10:55:32.653915 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 10:55:32.656446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 10:55:32.656583 ==
4793 10:55:32.659640 DQS Delay:
4794 10:55:32.659712 DQS0 = 0, DQS1 = 0
4795 10:55:32.662909 DQM Delay:
4796 10:55:32.662979 DQM0 = 45, DQM1 = 36
4797 10:55:32.663040 DQ Delay:
4798 10:55:32.666649 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4799 10:55:32.670226 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4800 10:55:32.672900 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4801 10:55:32.676149 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4802 10:55:32.676232
4803 10:55:32.676297
4804 10:55:32.686070 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4805 10:55:32.689788 CH1 RK1: MR19=808, MR18=2F24
4806 10:55:32.695966 CH1_RK1: MR19=0x808, MR18=0x2F24, DQSOSC=400, MR23=63, INC=163, DEC=109
4807 10:55:32.699561 [RxdqsGatingPostProcess] freq 600
4808 10:55:32.702464 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4809 10:55:32.705648 Pre-setting of DQS Precalculation
4810 10:55:32.712879 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4811 10:55:32.719135 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4812 10:55:32.725728 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4813 10:55:32.725814
4814 10:55:32.725879
4815 10:55:32.729179 [Calibration Summary] 1200 Mbps
4816 10:55:32.729262 CH 0, Rank 0
4817 10:55:32.732494 SW Impedance : PASS
4818 10:55:32.735375 DUTY Scan : NO K
4819 10:55:32.735460 ZQ Calibration : PASS
4820 10:55:32.738641 Jitter Meter : NO K
4821 10:55:32.742124 CBT Training : PASS
4822 10:55:32.742285 Write leveling : PASS
4823 10:55:32.745194 RX DQS gating : PASS
4824 10:55:32.748681 RX DQ/DQS(RDDQC) : PASS
4825 10:55:32.748764 TX DQ/DQS : PASS
4826 10:55:32.752017 RX DATLAT : PASS
4827 10:55:32.752102 RX DQ/DQS(Engine): PASS
4828 10:55:32.755271 TX OE : NO K
4829 10:55:32.755357 All Pass.
4830 10:55:32.755443
4831 10:55:32.758333 CH 0, Rank 1
4832 10:55:32.762245 SW Impedance : PASS
4833 10:55:32.762330 DUTY Scan : NO K
4834 10:55:32.765111 ZQ Calibration : PASS
4835 10:55:32.765196 Jitter Meter : NO K
4836 10:55:32.768863 CBT Training : PASS
4837 10:55:32.772241 Write leveling : PASS
4838 10:55:32.772327 RX DQS gating : PASS
4839 10:55:32.775080 RX DQ/DQS(RDDQC) : PASS
4840 10:55:32.778158 TX DQ/DQS : PASS
4841 10:55:32.778245 RX DATLAT : PASS
4842 10:55:32.781911 RX DQ/DQS(Engine): PASS
4843 10:55:32.785111 TX OE : NO K
4844 10:55:32.785197 All Pass.
4845 10:55:32.785282
4846 10:55:32.785362 CH 1, Rank 0
4847 10:55:32.788330 SW Impedance : PASS
4848 10:55:32.791893 DUTY Scan : NO K
4849 10:55:32.791979 ZQ Calibration : PASS
4850 10:55:32.794815 Jitter Meter : NO K
4851 10:55:32.798110 CBT Training : PASS
4852 10:55:32.798196 Write leveling : PASS
4853 10:55:32.801611 RX DQS gating : PASS
4854 10:55:32.805004 RX DQ/DQS(RDDQC) : PASS
4855 10:55:32.805090 TX DQ/DQS : PASS
4856 10:55:32.808420 RX DATLAT : PASS
4857 10:55:32.811814 RX DQ/DQS(Engine): PASS
4858 10:55:32.811907 TX OE : NO K
4859 10:55:32.814333 All Pass.
4860 10:55:32.814419
4861 10:55:32.814505 CH 1, Rank 1
4862 10:55:32.818262 SW Impedance : PASS
4863 10:55:32.818347 DUTY Scan : NO K
4864 10:55:32.821096 ZQ Calibration : PASS
4865 10:55:32.824883 Jitter Meter : NO K
4866 10:55:32.824968 CBT Training : PASS
4867 10:55:32.827669 Write leveling : PASS
4868 10:55:32.831202 RX DQS gating : PASS
4869 10:55:32.831288 RX DQ/DQS(RDDQC) : PASS
4870 10:55:32.834139 TX DQ/DQS : PASS
4871 10:55:32.837891 RX DATLAT : PASS
4872 10:55:32.837977 RX DQ/DQS(Engine): PASS
4873 10:55:32.841321 TX OE : NO K
4874 10:55:32.841411 All Pass.
4875 10:55:32.841498
4876 10:55:32.844253 DramC Write-DBI off
4877 10:55:32.847879 PER_BANK_REFRESH: Hybrid Mode
4878 10:55:32.847967 TX_TRACKING: ON
4879 10:55:32.857606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4880 10:55:32.860548 [FAST_K] Save calibration result to emmc
4881 10:55:32.864077 dramc_set_vcore_voltage set vcore to 662500
4882 10:55:32.867432 Read voltage for 933, 3
4883 10:55:32.867547 Vio18 = 0
4884 10:55:32.867633 Vcore = 662500
4885 10:55:32.870347 Vdram = 0
4886 10:55:32.870432 Vddq = 0
4887 10:55:32.870517 Vmddr = 0
4888 10:55:32.877171 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4889 10:55:32.880285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4890 10:55:32.883676 MEM_TYPE=3, freq_sel=17
4891 10:55:32.887085 sv_algorithm_assistance_LP4_1600
4892 10:55:32.891048 ============ PULL DRAM RESETB DOWN ============
4893 10:55:32.894052 ========== PULL DRAM RESETB DOWN end =========
4894 10:55:32.900109 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4895 10:55:32.903714 ===================================
4896 10:55:32.903800 LPDDR4 DRAM CONFIGURATION
4897 10:55:32.907085 ===================================
4898 10:55:32.910237 EX_ROW_EN[0] = 0x0
4899 10:55:32.913706 EX_ROW_EN[1] = 0x0
4900 10:55:32.913791 LP4Y_EN = 0x0
4901 10:55:32.916859 WORK_FSP = 0x0
4902 10:55:32.916943 WL = 0x3
4903 10:55:32.920102 RL = 0x3
4904 10:55:32.920186 BL = 0x2
4905 10:55:32.923096 RPST = 0x0
4906 10:55:32.923180 RD_PRE = 0x0
4907 10:55:32.926930 WR_PRE = 0x1
4908 10:55:32.927014 WR_PST = 0x0
4909 10:55:32.930093 DBI_WR = 0x0
4910 10:55:32.930176 DBI_RD = 0x0
4911 10:55:32.933180 OTF = 0x1
4912 10:55:32.936496 ===================================
4913 10:55:32.939961 ===================================
4914 10:55:32.940045 ANA top config
4915 10:55:32.942941 ===================================
4916 10:55:32.946246 DLL_ASYNC_EN = 0
4917 10:55:32.949533 ALL_SLAVE_EN = 1
4918 10:55:32.952959 NEW_RANK_MODE = 1
4919 10:55:32.953045 DLL_IDLE_MODE = 1
4920 10:55:32.956376 LP45_APHY_COMB_EN = 1
4921 10:55:32.959725 TX_ODT_DIS = 1
4922 10:55:32.962964 NEW_8X_MODE = 1
4923 10:55:32.966158 ===================================
4924 10:55:32.969383 ===================================
4925 10:55:32.973072 data_rate = 1866
4926 10:55:32.975914 CKR = 1
4927 10:55:32.975998 DQ_P2S_RATIO = 8
4928 10:55:32.979173 ===================================
4929 10:55:32.982596 CA_P2S_RATIO = 8
4930 10:55:32.985833 DQ_CA_OPEN = 0
4931 10:55:32.989353 DQ_SEMI_OPEN = 0
4932 10:55:32.992469 CA_SEMI_OPEN = 0
4933 10:55:32.995855 CA_FULL_RATE = 0
4934 10:55:32.995955 DQ_CKDIV4_EN = 1
4935 10:55:32.999585 CA_CKDIV4_EN = 1
4936 10:55:33.003059 CA_PREDIV_EN = 0
4937 10:55:33.005821 PH8_DLY = 0
4938 10:55:33.009034 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4939 10:55:33.012286 DQ_AAMCK_DIV = 4
4940 10:55:33.012371 CA_AAMCK_DIV = 4
4941 10:55:33.015629 CA_ADMCK_DIV = 4
4942 10:55:33.019051 DQ_TRACK_CA_EN = 0
4943 10:55:33.022055 CA_PICK = 933
4944 10:55:33.025500 CA_MCKIO = 933
4945 10:55:33.028762 MCKIO_SEMI = 0
4946 10:55:33.032075 PLL_FREQ = 3732
4947 10:55:33.032159 DQ_UI_PI_RATIO = 32
4948 10:55:33.036232 CA_UI_PI_RATIO = 0
4949 10:55:33.038505 ===================================
4950 10:55:33.042388 ===================================
4951 10:55:33.045526 memory_type:LPDDR4
4952 10:55:33.048338 GP_NUM : 10
4953 10:55:33.048422 SRAM_EN : 1
4954 10:55:33.051718 MD32_EN : 0
4955 10:55:33.055132 ===================================
4956 10:55:33.058398 [ANA_INIT] >>>>>>>>>>>>>>
4957 10:55:33.062184 <<<<<< [CONFIGURE PHASE]: ANA_TX
4958 10:55:33.065300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4959 10:55:33.068711 ===================================
4960 10:55:33.068796 data_rate = 1866,PCW = 0X8f00
4961 10:55:33.072269 ===================================
4962 10:55:33.074684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4963 10:55:33.081801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 10:55:33.088314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4965 10:55:33.091931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4966 10:55:33.094703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4967 10:55:33.098315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4968 10:55:33.101208 [ANA_INIT] flow start
4969 10:55:33.105442 [ANA_INIT] PLL >>>>>>>>
4970 10:55:33.105530 [ANA_INIT] PLL <<<<<<<<
4971 10:55:33.108625 [ANA_INIT] MIDPI >>>>>>>>
4972 10:55:33.110961 [ANA_INIT] MIDPI <<<<<<<<
4973 10:55:33.111046 [ANA_INIT] DLL >>>>>>>>
4974 10:55:33.114479 [ANA_INIT] flow end
4975 10:55:33.118101 ============ LP4 DIFF to SE enter ============
4976 10:55:33.121435 ============ LP4 DIFF to SE exit ============
4977 10:55:33.124485 [ANA_INIT] <<<<<<<<<<<<<
4978 10:55:33.127761 [Flow] Enable top DCM control >>>>>
4979 10:55:33.131049 [Flow] Enable top DCM control <<<<<
4980 10:55:33.134358 Enable DLL master slave shuffle
4981 10:55:33.141498 ==============================================================
4982 10:55:33.141589 Gating Mode config
4983 10:55:33.147219 ==============================================================
4984 10:55:33.150521 Config description:
4985 10:55:33.157287 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4986 10:55:33.163708 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4987 10:55:33.170965 SELPH_MODE 0: By rank 1: By Phase
4988 10:55:33.177026 ==============================================================
4989 10:55:33.180266 GAT_TRACK_EN = 1
4990 10:55:33.180350 RX_GATING_MODE = 2
4991 10:55:33.183930 RX_GATING_TRACK_MODE = 2
4992 10:55:33.186788 SELPH_MODE = 1
4993 10:55:33.190128 PICG_EARLY_EN = 1
4994 10:55:33.193299 VALID_LAT_VALUE = 1
4995 10:55:33.200074 ==============================================================
4996 10:55:33.204199 Enter into Gating configuration >>>>
4997 10:55:33.206658 Exit from Gating configuration <<<<
4998 10:55:33.210004 Enter into DVFS_PRE_config >>>>>
4999 10:55:33.220032 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5000 10:55:33.222925 Exit from DVFS_PRE_config <<<<<
5001 10:55:33.226604 Enter into PICG configuration >>>>
5002 10:55:33.229896 Exit from PICG configuration <<<<
5003 10:55:33.233651 [RX_INPUT] configuration >>>>>
5004 10:55:33.236872 [RX_INPUT] configuration <<<<<
5005 10:55:33.239741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5006 10:55:33.246518 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5007 10:55:33.253130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 10:55:33.259765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 10:55:33.262774 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5010 10:55:33.269439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5011 10:55:33.273164 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5012 10:55:33.279280 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5013 10:55:33.282961 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5014 10:55:33.286337 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5015 10:55:33.289609 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5016 10:55:33.296621 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5017 10:55:33.299082 ===================================
5018 10:55:33.303282 LPDDR4 DRAM CONFIGURATION
5019 10:55:33.305904 ===================================
5020 10:55:33.305990 EX_ROW_EN[0] = 0x0
5021 10:55:33.309460 EX_ROW_EN[1] = 0x0
5022 10:55:33.309546 LP4Y_EN = 0x0
5023 10:55:33.312439 WORK_FSP = 0x0
5024 10:55:33.312583 WL = 0x3
5025 10:55:33.315399 RL = 0x3
5026 10:55:33.315483 BL = 0x2
5027 10:55:33.318899 RPST = 0x0
5028 10:55:33.318984 RD_PRE = 0x0
5029 10:55:33.322981 WR_PRE = 0x1
5030 10:55:33.323066 WR_PST = 0x0
5031 10:55:33.325954 DBI_WR = 0x0
5032 10:55:33.326038 DBI_RD = 0x0
5033 10:55:33.328756 OTF = 0x1
5034 10:55:33.332009 ===================================
5035 10:55:33.335760 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5036 10:55:33.338782 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5037 10:55:33.345766 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5038 10:55:33.348868 ===================================
5039 10:55:33.348956 LPDDR4 DRAM CONFIGURATION
5040 10:55:33.352314 ===================================
5041 10:55:33.355100 EX_ROW_EN[0] = 0x10
5042 10:55:33.358530 EX_ROW_EN[1] = 0x0
5043 10:55:33.358614 LP4Y_EN = 0x0
5044 10:55:33.362054 WORK_FSP = 0x0
5045 10:55:33.362139 WL = 0x3
5046 10:55:33.365559 RL = 0x3
5047 10:55:33.365650 BL = 0x2
5048 10:55:33.368263 RPST = 0x0
5049 10:55:33.368373 RD_PRE = 0x0
5050 10:55:33.371874 WR_PRE = 0x1
5051 10:55:33.371958 WR_PST = 0x0
5052 10:55:33.374940 DBI_WR = 0x0
5053 10:55:33.375023 DBI_RD = 0x0
5054 10:55:33.378424 OTF = 0x1
5055 10:55:33.381603 ===================================
5056 10:55:33.388134 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5057 10:55:33.391762 nWR fixed to 30
5058 10:55:33.394701 [ModeRegInit_LP4] CH0 RK0
5059 10:55:33.394786 [ModeRegInit_LP4] CH0 RK1
5060 10:55:33.398235 [ModeRegInit_LP4] CH1 RK0
5061 10:55:33.401637 [ModeRegInit_LP4] CH1 RK1
5062 10:55:33.401722 match AC timing 9
5063 10:55:33.407760 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5064 10:55:33.411245 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5065 10:55:33.414312 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5066 10:55:33.421503 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5067 10:55:33.424694 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5068 10:55:33.424783 ==
5069 10:55:33.427871 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 10:55:33.431668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 10:55:33.431756 ==
5072 10:55:33.438388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 10:55:33.444548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5074 10:55:33.447933 [CA 0] Center 38 (7~69) winsize 63
5075 10:55:33.450964 [CA 1] Center 37 (7~68) winsize 62
5076 10:55:33.454992 [CA 2] Center 34 (4~65) winsize 62
5077 10:55:33.457623 [CA 3] Center 34 (4~65) winsize 62
5078 10:55:33.461522 [CA 4] Center 33 (3~64) winsize 62
5079 10:55:33.464197 [CA 5] Center 33 (3~63) winsize 61
5080 10:55:33.464281
5081 10:55:33.467477 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5082 10:55:33.467561
5083 10:55:33.471075 [CATrainingPosCal] consider 1 rank data
5084 10:55:33.474453 u2DelayCellTimex100 = 270/100 ps
5085 10:55:33.477478 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5086 10:55:33.480799 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5087 10:55:33.483929 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5088 10:55:33.487410 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5089 10:55:33.493995 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5090 10:55:33.497023 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5091 10:55:33.497111
5092 10:55:33.501244 CA PerBit enable=1, Macro0, CA PI delay=33
5093 10:55:33.501332
5094 10:55:33.503864 [CBTSetCACLKResult] CA Dly = 33
5095 10:55:33.503948 CS Dly: 7 (0~38)
5096 10:55:33.504015 ==
5097 10:55:33.506970 Dram Type= 6, Freq= 0, CH_0, rank 1
5098 10:55:33.513756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 10:55:33.513854 ==
5100 10:55:33.516884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 10:55:33.523240 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5102 10:55:33.526742 [CA 0] Center 37 (7~68) winsize 62
5103 10:55:33.530183 [CA 1] Center 37 (7~68) winsize 62
5104 10:55:33.534093 [CA 2] Center 34 (4~65) winsize 62
5105 10:55:33.536826 [CA 3] Center 34 (4~65) winsize 62
5106 10:55:33.541360 [CA 4] Center 33 (3~64) winsize 62
5107 10:55:33.542978 [CA 5] Center 32 (2~63) winsize 62
5108 10:55:33.543064
5109 10:55:33.546618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5110 10:55:33.546711
5111 10:55:33.549771 [CATrainingPosCal] consider 2 rank data
5112 10:55:33.553103 u2DelayCellTimex100 = 270/100 ps
5113 10:55:33.556606 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5114 10:55:33.563199 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5115 10:55:33.566493 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5116 10:55:33.569750 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5117 10:55:33.572800 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5118 10:55:33.576279 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5119 10:55:33.576369
5120 10:55:33.579418 CA PerBit enable=1, Macro0, CA PI delay=33
5121 10:55:33.579503
5122 10:55:33.582765 [CBTSetCACLKResult] CA Dly = 33
5123 10:55:33.585823 CS Dly: 7 (0~39)
5124 10:55:33.585908
5125 10:55:33.589222 ----->DramcWriteLeveling(PI) begin...
5126 10:55:33.589308 ==
5127 10:55:33.592462 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 10:55:33.596475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 10:55:33.596612 ==
5130 10:55:33.599566 Write leveling (Byte 0): 34 => 34
5131 10:55:33.603148 Write leveling (Byte 1): 30 => 30
5132 10:55:33.606061 DramcWriteLeveling(PI) end<-----
5133 10:55:33.606148
5134 10:55:33.606214 ==
5135 10:55:33.609385 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 10:55:33.612448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 10:55:33.612590 ==
5138 10:55:33.616280 [Gating] SW mode calibration
5139 10:55:33.622273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5140 10:55:33.628842 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5141 10:55:33.632584 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5142 10:55:33.635769 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5143 10:55:33.642545 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 10:55:33.645927 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 10:55:33.649404 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 10:55:33.655844 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 10:55:33.659019 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 10:55:33.662095 0 14 28 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (1 0)
5149 10:55:33.668690 0 15 0 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
5150 10:55:33.671769 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5151 10:55:33.675235 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 10:55:33.682218 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 10:55:33.685589 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 10:55:33.688790 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 10:55:33.695089 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 10:55:33.698537 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5157 10:55:33.702429 1 0 0 | B1->B0 | 3131 4545 | 1 0 | (0 0) (0 0)
5158 10:55:33.708954 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5159 10:55:33.711733 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 10:55:33.715076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 10:55:33.721586 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 10:55:33.724806 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 10:55:33.728183 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5164 10:55:33.735285 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5165 10:55:33.738401 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5166 10:55:33.741592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5167 10:55:33.748078 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 10:55:33.752257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 10:55:33.755223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 10:55:33.761138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 10:55:33.764414 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 10:55:33.768179 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 10:55:33.774625 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 10:55:33.777816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 10:55:33.781120 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:55:33.787650 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:55:33.791048 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:55:33.794622 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:55:33.801181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:55:33.803972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 10:55:33.807315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5182 10:55:33.810670 Total UI for P1: 0, mck2ui 16
5183 10:55:33.814148 best dqsien dly found for B0: ( 1, 2, 30)
5184 10:55:33.820951 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5185 10:55:33.823765 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 10:55:33.827455 Total UI for P1: 0, mck2ui 16
5187 10:55:33.830407 best dqsien dly found for B1: ( 1, 3, 2)
5188 10:55:33.833854 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5189 10:55:33.836953 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5190 10:55:33.837038
5191 10:55:33.840216 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5192 10:55:33.843667 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5193 10:55:33.846716 [Gating] SW calibration Done
5194 10:55:33.846809 ==
5195 10:55:33.850268 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 10:55:33.853515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 10:55:33.856860 ==
5198 10:55:33.856946 RX Vref Scan: 0
5199 10:55:33.857013
5200 10:55:33.860162 RX Vref 0 -> 0, step: 1
5201 10:55:33.860271
5202 10:55:33.860365 RX Delay -80 -> 252, step: 8
5203 10:55:33.867261 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5204 10:55:33.870495 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5205 10:55:33.873892 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5206 10:55:33.876920 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5207 10:55:33.880231 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5208 10:55:33.887162 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5209 10:55:33.889961 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5210 10:55:33.893535 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5211 10:55:33.896659 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5212 10:55:33.900644 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5213 10:55:33.903191 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5214 10:55:33.909673 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5215 10:55:33.913606 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5216 10:55:33.916387 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5217 10:55:33.919733 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5218 10:55:33.926331 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5219 10:55:33.926418 ==
5220 10:55:33.929643 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 10:55:33.933038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 10:55:33.933123 ==
5223 10:55:33.933191 DQS Delay:
5224 10:55:33.936427 DQS0 = 0, DQS1 = 0
5225 10:55:33.936572 DQM Delay:
5226 10:55:33.939572 DQM0 = 96, DQM1 = 86
5227 10:55:33.939656 DQ Delay:
5228 10:55:33.942620 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5229 10:55:33.946115 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5230 10:55:33.949492 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5231 10:55:33.952415 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5232 10:55:33.952550
5233 10:55:33.952633
5234 10:55:33.952695 ==
5235 10:55:33.956123 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 10:55:33.960319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 10:55:33.960432 ==
5238 10:55:33.962354
5239 10:55:33.962437
5240 10:55:33.962505 TX Vref Scan disable
5241 10:55:33.966408 == TX Byte 0 ==
5242 10:55:33.968919 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5243 10:55:33.972160 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5244 10:55:33.975802 == TX Byte 1 ==
5245 10:55:33.979347 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5246 10:55:33.981996 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5247 10:55:33.985836 ==
5248 10:55:33.988811 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 10:55:33.992457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 10:55:33.992595 ==
5251 10:55:33.992704
5252 10:55:33.992767
5253 10:55:33.995308 TX Vref Scan disable
5254 10:55:33.995392 == TX Byte 0 ==
5255 10:55:34.002342 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5256 10:55:34.005620 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5257 10:55:34.005706 == TX Byte 1 ==
5258 10:55:34.012365 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5259 10:55:34.015932 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5260 10:55:34.016017
5261 10:55:34.016083 [DATLAT]
5262 10:55:34.018542 Freq=933, CH0 RK0
5263 10:55:34.018627
5264 10:55:34.018693 DATLAT Default: 0xd
5265 10:55:34.021961 0, 0xFFFF, sum = 0
5266 10:55:34.022046 1, 0xFFFF, sum = 0
5267 10:55:34.025106 2, 0xFFFF, sum = 0
5268 10:55:34.025190 3, 0xFFFF, sum = 0
5269 10:55:34.028318 4, 0xFFFF, sum = 0
5270 10:55:34.028404 5, 0xFFFF, sum = 0
5271 10:55:34.031507 6, 0xFFFF, sum = 0
5272 10:55:34.035454 7, 0xFFFF, sum = 0
5273 10:55:34.035539 8, 0xFFFF, sum = 0
5274 10:55:34.038763 9, 0xFFFF, sum = 0
5275 10:55:34.038847 10, 0x0, sum = 1
5276 10:55:34.042061 11, 0x0, sum = 2
5277 10:55:34.042146 12, 0x0, sum = 3
5278 10:55:34.042214 13, 0x0, sum = 4
5279 10:55:34.045004 best_step = 11
5280 10:55:34.045093
5281 10:55:34.045160 ==
5282 10:55:34.047926 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 10:55:34.051675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 10:55:34.051760 ==
5285 10:55:34.054862 RX Vref Scan: 1
5286 10:55:34.054945
5287 10:55:34.055010 RX Vref 0 -> 0, step: 1
5288 10:55:34.058448
5289 10:55:34.058534 RX Delay -61 -> 252, step: 4
5290 10:55:34.058601
5291 10:55:34.061516 Set Vref, RX VrefLevel [Byte0]: 61
5292 10:55:34.064738 [Byte1]: 50
5293 10:55:34.069318
5294 10:55:34.069401 Final RX Vref Byte 0 = 61 to rank0
5295 10:55:34.072498 Final RX Vref Byte 1 = 50 to rank0
5296 10:55:34.076078 Final RX Vref Byte 0 = 61 to rank1
5297 10:55:34.079501 Final RX Vref Byte 1 = 50 to rank1==
5298 10:55:34.082717 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 10:55:34.089711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 10:55:34.089793 ==
5301 10:55:34.089857 DQS Delay:
5302 10:55:34.092623 DQS0 = 0, DQS1 = 0
5303 10:55:34.092704 DQM Delay:
5304 10:55:34.092767 DQM0 = 96, DQM1 = 85
5305 10:55:34.095658 DQ Delay:
5306 10:55:34.099065 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5307 10:55:34.102544 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5308 10:55:34.105538 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5309 10:55:34.109338 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =92
5310 10:55:34.109419
5311 10:55:34.109482
5312 10:55:34.115396 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5313 10:55:34.119558 CH0 RK0: MR19=505, MR18=2A11
5314 10:55:34.125470 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5315 10:55:34.125552
5316 10:55:34.128487 ----->DramcWriteLeveling(PI) begin...
5317 10:55:34.128605 ==
5318 10:55:34.132081 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 10:55:34.135618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 10:55:34.135704 ==
5321 10:55:34.138787 Write leveling (Byte 0): 31 => 31
5322 10:55:34.141657 Write leveling (Byte 1): 28 => 28
5323 10:55:34.144810 DramcWriteLeveling(PI) end<-----
5324 10:55:34.144943
5325 10:55:34.145073 ==
5326 10:55:34.148734 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 10:55:34.152142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 10:55:34.155427 ==
5329 10:55:34.155527 [Gating] SW mode calibration
5330 10:55:34.164781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5331 10:55:34.168195 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5332 10:55:34.171470 0 14 0 | B1->B0 | 2727 3232 | 1 1 | (0 0) (1 1)
5333 10:55:34.177742 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 10:55:34.181192 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 10:55:34.184797 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 10:55:34.191244 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 10:55:34.194654 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 10:55:34.197664 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 10:55:34.204722 0 14 28 | B1->B0 | 3232 2c2c | 1 0 | (1 1) (0 0)
5340 10:55:34.207457 0 15 0 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
5341 10:55:34.210814 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 10:55:34.217768 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 10:55:34.220878 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 10:55:34.224088 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 10:55:34.230527 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 10:55:34.234505 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 10:55:34.237234 0 15 28 | B1->B0 | 2727 3636 | 0 1 | (0 0) (0 0)
5348 10:55:34.243739 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5349 10:55:34.247379 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 10:55:34.250380 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 10:55:34.257395 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 10:55:34.260270 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 10:55:34.263837 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 10:55:34.270224 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 10:55:34.273871 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5356 10:55:34.276936 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5357 10:55:34.283205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 10:55:34.287076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 10:55:34.290951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 10:55:34.296411 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 10:55:34.300268 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 10:55:34.303526 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 10:55:34.309735 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 10:55:34.313502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 10:55:34.316463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:55:34.323142 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:55:34.326362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:55:34.329344 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:55:34.336173 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:55:34.339511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 10:55:34.343061 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5372 10:55:34.349661 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5373 10:55:34.353303 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 10:55:34.356783 Total UI for P1: 0, mck2ui 16
5375 10:55:34.359135 best dqsien dly found for B0: ( 1, 2, 30)
5376 10:55:34.362542 Total UI for P1: 0, mck2ui 16
5377 10:55:34.366218 best dqsien dly found for B1: ( 1, 2, 30)
5378 10:55:34.369292 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5379 10:55:34.372274 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5380 10:55:34.372358
5381 10:55:34.375822 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5382 10:55:34.382446 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5383 10:55:34.382529 [Gating] SW calibration Done
5384 10:55:34.382596 ==
5385 10:55:34.385947 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 10:55:34.392501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 10:55:34.392594 ==
5388 10:55:34.392660 RX Vref Scan: 0
5389 10:55:34.392722
5390 10:55:34.395555 RX Vref 0 -> 0, step: 1
5391 10:55:34.395679
5392 10:55:34.398853 RX Delay -80 -> 252, step: 8
5393 10:55:34.402281 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5394 10:55:34.405407 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5395 10:55:34.408819 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5396 10:55:34.412350 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5397 10:55:34.418790 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5398 10:55:34.422341 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5399 10:55:34.425259 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5400 10:55:34.428410 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5401 10:55:34.431925 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5402 10:55:34.435364 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5403 10:55:34.441668 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5404 10:55:34.444832 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5405 10:55:34.449174 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5406 10:55:34.451734 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5407 10:55:34.458254 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5408 10:55:34.461243 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5409 10:55:34.461328 ==
5410 10:55:34.464795 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 10:55:34.468247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 10:55:34.468358 ==
5413 10:55:34.468463 DQS Delay:
5414 10:55:34.471170 DQS0 = 0, DQS1 = 0
5415 10:55:34.471268 DQM Delay:
5416 10:55:34.474907 DQM0 = 98, DQM1 = 87
5417 10:55:34.475010 DQ Delay:
5418 10:55:34.478336 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5419 10:55:34.481202 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5420 10:55:34.484790 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5421 10:55:34.487934 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5422 10:55:34.488018
5423 10:55:34.488083
5424 10:55:34.488144 ==
5425 10:55:34.492158 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 10:55:34.497846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 10:55:34.497932 ==
5428 10:55:34.498000
5429 10:55:34.498061
5430 10:55:34.498119 TX Vref Scan disable
5431 10:55:34.501225 == TX Byte 0 ==
5432 10:55:34.504521 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5433 10:55:34.511641 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5434 10:55:34.511728 == TX Byte 1 ==
5435 10:55:34.514710 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5436 10:55:34.521094 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5437 10:55:34.521181 ==
5438 10:55:34.524199 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 10:55:34.528183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 10:55:34.528272 ==
5441 10:55:34.528339
5442 10:55:34.528414
5443 10:55:34.530659 TX Vref Scan disable
5444 10:55:34.534367 == TX Byte 0 ==
5445 10:55:34.537434 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5446 10:55:34.541101 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5447 10:55:34.544652 == TX Byte 1 ==
5448 10:55:34.547425 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5449 10:55:34.551170 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5450 10:55:34.551260
5451 10:55:34.551327 [DATLAT]
5452 10:55:34.554195 Freq=933, CH0 RK1
5453 10:55:34.554279
5454 10:55:34.554345 DATLAT Default: 0xb
5455 10:55:34.557178 0, 0xFFFF, sum = 0
5456 10:55:34.560678 1, 0xFFFF, sum = 0
5457 10:55:34.560767 2, 0xFFFF, sum = 0
5458 10:55:34.563616 3, 0xFFFF, sum = 0
5459 10:55:34.563701 4, 0xFFFF, sum = 0
5460 10:55:34.567167 5, 0xFFFF, sum = 0
5461 10:55:34.567252 6, 0xFFFF, sum = 0
5462 10:55:34.570355 7, 0xFFFF, sum = 0
5463 10:55:34.570440 8, 0xFFFF, sum = 0
5464 10:55:34.573673 9, 0xFFFF, sum = 0
5465 10:55:34.573758 10, 0x0, sum = 1
5466 10:55:34.577268 11, 0x0, sum = 2
5467 10:55:34.577353 12, 0x0, sum = 3
5468 10:55:34.580400 13, 0x0, sum = 4
5469 10:55:34.580484 best_step = 11
5470 10:55:34.580588
5471 10:55:34.580651 ==
5472 10:55:34.583739 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 10:55:34.587378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 10:55:34.590075 ==
5475 10:55:34.590158 RX Vref Scan: 0
5476 10:55:34.590224
5477 10:55:34.593319 RX Vref 0 -> 0, step: 1
5478 10:55:34.593402
5479 10:55:34.596526 RX Delay -61 -> 252, step: 4
5480 10:55:34.600274 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5481 10:55:34.604054 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5482 10:55:34.610181 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5483 10:55:34.613191 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5484 10:55:34.616376 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5485 10:55:34.619834 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5486 10:55:34.622749 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5487 10:55:34.626224 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5488 10:55:34.632991 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5489 10:55:34.636125 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5490 10:55:34.639686 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5491 10:55:34.642832 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5492 10:55:34.645858 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5493 10:55:34.652995 iDelay=203, Bit 13, Center 92 (-5 ~ 190) 196
5494 10:55:34.656335 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5495 10:55:34.659594 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5496 10:55:34.659678 ==
5497 10:55:34.662573 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 10:55:34.666101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 10:55:34.666184 ==
5500 10:55:34.669991 DQS Delay:
5501 10:55:34.670074 DQS0 = 0, DQS1 = 0
5502 10:55:34.672162 DQM Delay:
5503 10:55:34.672244 DQM0 = 94, DQM1 = 86
5504 10:55:34.675999 DQ Delay:
5505 10:55:34.676083 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5506 10:55:34.678981 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5507 10:55:34.682464 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5508 10:55:34.685846 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5509 10:55:34.688963
5510 10:55:34.689047
5511 10:55:34.695408 [DQSOSCAuto] RK1, (LSB)MR18= 0x24f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5512 10:55:34.699035 CH0 RK1: MR19=504, MR18=24F5
5513 10:55:34.705438 CH0_RK1: MR19=0x504, MR18=0x24F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5514 10:55:34.709188 [RxdqsGatingPostProcess] freq 933
5515 10:55:34.712649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 10:55:34.715553 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 10:55:34.719008 best DQS1 dly(2T, 0.5T) = (0, 11)
5518 10:55:34.722448 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 10:55:34.725092 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5520 10:55:34.728470 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 10:55:34.732132 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 10:55:34.735138 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 10:55:34.738810 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 10:55:34.741705 Pre-setting of DQS Precalculation
5525 10:55:34.745314 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 10:55:34.745399 ==
5527 10:55:34.748222 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 10:55:34.755763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 10:55:34.755850 ==
5530 10:55:34.758297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 10:55:34.765210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 10:55:34.768332 [CA 0] Center 37 (7~67) winsize 61
5533 10:55:34.771306 [CA 1] Center 37 (7~68) winsize 62
5534 10:55:34.774908 [CA 2] Center 34 (4~65) winsize 62
5535 10:55:34.778294 [CA 3] Center 33 (3~64) winsize 62
5536 10:55:34.781801 [CA 4] Center 34 (4~65) winsize 62
5537 10:55:34.784779 [CA 5] Center 33 (3~64) winsize 62
5538 10:55:34.784861
5539 10:55:34.788338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 10:55:34.788420
5541 10:55:34.791519 [CATrainingPosCal] consider 1 rank data
5542 10:55:34.794847 u2DelayCellTimex100 = 270/100 ps
5543 10:55:34.797895 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5544 10:55:34.804770 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5545 10:55:34.807857 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 10:55:34.811093 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 10:55:34.814395 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5548 10:55:34.817921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5549 10:55:34.818004
5550 10:55:34.821288 CA PerBit enable=1, Macro0, CA PI delay=33
5551 10:55:34.821370
5552 10:55:34.824643 [CBTSetCACLKResult] CA Dly = 33
5553 10:55:34.824763 CS Dly: 6 (0~37)
5554 10:55:34.827608 ==
5555 10:55:34.831472 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 10:55:34.834200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 10:55:34.834286 ==
5558 10:55:34.840883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 10:55:34.844425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 10:55:34.847920 [CA 0] Center 36 (6~67) winsize 62
5561 10:55:34.851149 [CA 1] Center 37 (7~68) winsize 62
5562 10:55:34.855332 [CA 2] Center 34 (4~65) winsize 62
5563 10:55:34.858042 [CA 3] Center 34 (4~65) winsize 62
5564 10:55:34.861462 [CA 4] Center 34 (4~65) winsize 62
5565 10:55:34.864741 [CA 5] Center 33 (3~64) winsize 62
5566 10:55:34.864849
5567 10:55:34.867690 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 10:55:34.867763
5569 10:55:34.871621 [CATrainingPosCal] consider 2 rank data
5570 10:55:34.874206 u2DelayCellTimex100 = 270/100 ps
5571 10:55:34.877755 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5572 10:55:34.884203 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5573 10:55:34.888269 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 10:55:34.891076 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5575 10:55:34.894167 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 10:55:34.897692 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5577 10:55:34.897775
5578 10:55:34.901055 CA PerBit enable=1, Macro0, CA PI delay=33
5579 10:55:34.901139
5580 10:55:34.904121 [CBTSetCACLKResult] CA Dly = 33
5581 10:55:34.907248 CS Dly: 7 (0~39)
5582 10:55:34.907331
5583 10:55:34.911086 ----->DramcWriteLeveling(PI) begin...
5584 10:55:34.911171 ==
5585 10:55:34.913973 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 10:55:34.917619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 10:55:34.917704 ==
5588 10:55:34.920821 Write leveling (Byte 0): 23 => 23
5589 10:55:34.923996 Write leveling (Byte 1): 30 => 30
5590 10:55:34.927319 DramcWriteLeveling(PI) end<-----
5591 10:55:34.927403
5592 10:55:34.927469 ==
5593 10:55:34.930462 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 10:55:34.933798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 10:55:34.933883 ==
5596 10:55:34.937056 [Gating] SW mode calibration
5597 10:55:34.943839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 10:55:34.950445 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 10:55:34.953425 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 10:55:34.956508 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 10:55:34.963456 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 10:55:34.966718 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 10:55:34.969979 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 10:55:34.976984 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5605 10:55:34.980018 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5606 10:55:34.984090 0 14 28 | B1->B0 | 2c2c 2929 | 0 1 | (1 1) (0 0)
5607 10:55:34.989810 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5608 10:55:34.993118 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 10:55:34.996767 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 10:55:35.003079 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 10:55:35.006696 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 10:55:35.010009 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 10:55:35.016951 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5614 10:55:35.019767 0 15 28 | B1->B0 | 3636 3a3a | 0 1 | (0 0) (0 0)
5615 10:55:35.023229 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 10:55:35.029919 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 10:55:35.033275 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 10:55:35.036492 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 10:55:35.043145 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 10:55:35.047693 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 10:55:35.049385 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5622 10:55:35.056498 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5623 10:55:35.059462 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 10:55:35.062957 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 10:55:35.070027 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 10:55:35.072956 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 10:55:35.076001 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 10:55:35.082840 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 10:55:35.086194 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 10:55:35.089250 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 10:55:35.095710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:55:35.099342 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:55:35.102483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:55:35.109234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:55:35.112429 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:55:35.115770 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:55:35.122466 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5638 10:55:35.125440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 10:55:35.128821 Total UI for P1: 0, mck2ui 16
5640 10:55:35.132071 best dqsien dly found for B0: ( 1, 2, 24)
5641 10:55:35.135170 Total UI for P1: 0, mck2ui 16
5642 10:55:35.138484 best dqsien dly found for B1: ( 1, 2, 24)
5643 10:55:35.141962 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5644 10:55:35.145356 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5645 10:55:35.145441
5646 10:55:35.148376 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5647 10:55:35.152119 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5648 10:55:35.155022 [Gating] SW calibration Done
5649 10:55:35.155107 ==
5650 10:55:35.159492 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 10:55:35.162230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 10:55:35.165286 ==
5653 10:55:35.165371 RX Vref Scan: 0
5654 10:55:35.165437
5655 10:55:35.168452 RX Vref 0 -> 0, step: 1
5656 10:55:35.168575
5657 10:55:35.171766 RX Delay -80 -> 252, step: 8
5658 10:55:35.174890 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5659 10:55:35.178270 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5660 10:55:35.181384 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5661 10:55:35.184877 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5662 10:55:35.187962 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5663 10:55:35.194709 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5664 10:55:35.198134 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5665 10:55:35.201430 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5666 10:55:35.204583 iDelay=208, Bit 8, Center 83 (-16 ~ 183) 200
5667 10:55:35.208155 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5668 10:55:35.214694 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5669 10:55:35.218033 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5670 10:55:35.221260 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5671 10:55:35.224252 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5672 10:55:35.227862 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5673 10:55:35.234697 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5674 10:55:35.234784 ==
5675 10:55:35.237504 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 10:55:35.240825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 10:55:35.240911 ==
5678 10:55:35.240977 DQS Delay:
5679 10:55:35.244402 DQS0 = 0, DQS1 = 0
5680 10:55:35.244484 DQM Delay:
5681 10:55:35.247269 DQM0 = 102, DQM1 = 93
5682 10:55:35.247365 DQ Delay:
5683 10:55:35.250678 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5684 10:55:35.254173 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5685 10:55:35.257286 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =79
5686 10:55:35.260904 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5687 10:55:35.260986
5688 10:55:35.261050
5689 10:55:35.261110 ==
5690 10:55:35.263900 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 10:55:35.270808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 10:55:35.270894 ==
5693 10:55:35.270960
5694 10:55:35.271021
5695 10:55:35.271078 TX Vref Scan disable
5696 10:55:35.273653 == TX Byte 0 ==
5697 10:55:35.277709 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5698 10:55:35.283696 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5699 10:55:35.283780 == TX Byte 1 ==
5700 10:55:35.287042 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5701 10:55:35.293722 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5702 10:55:35.293806 ==
5703 10:55:35.297051 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 10:55:35.300428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 10:55:35.300547 ==
5706 10:55:35.300614
5707 10:55:35.300705
5708 10:55:35.303413 TX Vref Scan disable
5709 10:55:35.303531 == TX Byte 0 ==
5710 10:55:35.310561 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5711 10:55:35.313539 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5712 10:55:35.317163 == TX Byte 1 ==
5713 10:55:35.320064 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5714 10:55:35.323569 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5715 10:55:35.323652
5716 10:55:35.323717 [DATLAT]
5717 10:55:35.327045 Freq=933, CH1 RK0
5718 10:55:35.327128
5719 10:55:35.327193 DATLAT Default: 0xd
5720 10:55:35.329714 0, 0xFFFF, sum = 0
5721 10:55:35.333269 1, 0xFFFF, sum = 0
5722 10:55:35.333353 2, 0xFFFF, sum = 0
5723 10:55:35.336523 3, 0xFFFF, sum = 0
5724 10:55:35.336607 4, 0xFFFF, sum = 0
5725 10:55:35.339963 5, 0xFFFF, sum = 0
5726 10:55:35.340046 6, 0xFFFF, sum = 0
5727 10:55:35.343151 7, 0xFFFF, sum = 0
5728 10:55:35.343234 8, 0xFFFF, sum = 0
5729 10:55:35.346516 9, 0xFFFF, sum = 0
5730 10:55:35.346600 10, 0x0, sum = 1
5731 10:55:35.350071 11, 0x0, sum = 2
5732 10:55:35.350159 12, 0x0, sum = 3
5733 10:55:35.353050 13, 0x0, sum = 4
5734 10:55:35.353134 best_step = 11
5735 10:55:35.353200
5736 10:55:35.353262 ==
5737 10:55:35.356454 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 10:55:35.359872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 10:55:35.359956 ==
5740 10:55:35.363814 RX Vref Scan: 1
5741 10:55:35.363897
5742 10:55:35.367006 RX Vref 0 -> 0, step: 1
5743 10:55:35.367119
5744 10:55:35.367234 RX Delay -61 -> 252, step: 4
5745 10:55:35.367330
5746 10:55:35.370288 Set Vref, RX VrefLevel [Byte0]: 47
5747 10:55:35.373831 [Byte1]: 54
5748 10:55:35.378582
5749 10:55:35.378665 Final RX Vref Byte 0 = 47 to rank0
5750 10:55:35.381028 Final RX Vref Byte 1 = 54 to rank0
5751 10:55:35.385111 Final RX Vref Byte 0 = 47 to rank1
5752 10:55:35.388107 Final RX Vref Byte 1 = 54 to rank1==
5753 10:55:35.390743 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 10:55:35.397562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 10:55:35.397638 ==
5756 10:55:35.397702 DQS Delay:
5757 10:55:35.400566 DQS0 = 0, DQS1 = 0
5758 10:55:35.400656 DQM Delay:
5759 10:55:35.400718 DQM0 = 101, DQM1 = 94
5760 10:55:35.404160 DQ Delay:
5761 10:55:35.407664 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5762 10:55:35.410443 DQ4 =100, DQ5 =112, DQ6 =108, DQ7 =96
5763 10:55:35.413966 DQ8 =82, DQ9 =86, DQ10 =96, DQ11 =86
5764 10:55:35.417221 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =104
5765 10:55:35.417298
5766 10:55:35.417365
5767 10:55:35.423714 [DQSOSCAuto] RK0, (LSB)MR18= 0x1707, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5768 10:55:35.427344 CH1 RK0: MR19=505, MR18=1707
5769 10:55:35.433997 CH1_RK0: MR19=0x505, MR18=0x1707, DQSOSC=414, MR23=63, INC=63, DEC=42
5770 10:55:35.434089
5771 10:55:35.436832 ----->DramcWriteLeveling(PI) begin...
5772 10:55:35.436914 ==
5773 10:55:35.440561 Dram Type= 6, Freq= 0, CH_1, rank 1
5774 10:55:35.446819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 10:55:35.446906 ==
5776 10:55:35.450148 Write leveling (Byte 0): 26 => 26
5777 10:55:35.450234 Write leveling (Byte 1): 31 => 31
5778 10:55:35.453529 DramcWriteLeveling(PI) end<-----
5779 10:55:35.453612
5780 10:55:35.456465 ==
5781 10:55:35.459987 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 10:55:35.463022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 10:55:35.463096 ==
5784 10:55:35.466544 [Gating] SW mode calibration
5785 10:55:35.473122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5786 10:55:35.476406 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5787 10:55:35.483378 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5788 10:55:35.486086 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 10:55:35.489548 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 10:55:35.495947 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 10:55:35.499351 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 10:55:35.503162 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5793 10:55:35.509174 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
5794 10:55:35.512462 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (1 0)
5795 10:55:35.516145 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5796 10:55:35.522372 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 10:55:35.526071 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 10:55:35.528885 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 10:55:35.535405 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 10:55:35.538898 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 10:55:35.542790 0 15 24 | B1->B0 | 2d2c 2323 | 1 0 | (0 0) (0 0)
5802 10:55:35.548946 0 15 28 | B1->B0 | 3c3c 3030 | 0 0 | (0 0) (0 0)
5803 10:55:35.552311 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5804 10:55:35.555820 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 10:55:35.561912 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 10:55:35.565604 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 10:55:35.568934 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 10:55:35.575403 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 10:55:35.578505 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5810 10:55:35.581727 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5811 10:55:35.588502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 10:55:35.591904 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 10:55:35.594902 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 10:55:35.601667 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 10:55:35.604889 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 10:55:35.608410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 10:55:35.614567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 10:55:35.617811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 10:55:35.621312 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:55:35.627843 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:55:35.631593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:55:35.634365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:55:35.641398 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:55:35.644300 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5825 10:55:35.647924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5826 10:55:35.653950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5827 10:55:35.657152 Total UI for P1: 0, mck2ui 16
5828 10:55:35.660823 best dqsien dly found for B0: ( 1, 2, 24)
5829 10:55:35.663739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 10:55:35.666905 Total UI for P1: 0, mck2ui 16
5831 10:55:35.670698 best dqsien dly found for B1: ( 1, 2, 24)
5832 10:55:35.673903 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5833 10:55:35.677322 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5834 10:55:35.677405
5835 10:55:35.680208 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5836 10:55:35.687521 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5837 10:55:35.687607 [Gating] SW calibration Done
5838 10:55:35.687673 ==
5839 10:55:35.690268 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 10:55:35.697008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 10:55:35.697096 ==
5842 10:55:35.697163 RX Vref Scan: 0
5843 10:55:35.697225
5844 10:55:35.700319 RX Vref 0 -> 0, step: 1
5845 10:55:35.700402
5846 10:55:35.703218 RX Delay -80 -> 252, step: 8
5847 10:55:35.706486 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5848 10:55:35.709737 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5849 10:55:35.713234 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5850 10:55:35.719748 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5851 10:55:35.723414 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5852 10:55:35.726469 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5853 10:55:35.729296 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5854 10:55:35.732682 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5855 10:55:35.739260 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5856 10:55:35.743341 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5857 10:55:35.746082 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5858 10:55:35.749959 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5859 10:55:35.752704 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5860 10:55:35.755857 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5861 10:55:35.762798 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5862 10:55:35.766037 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5863 10:55:35.766124 ==
5864 10:55:35.769476 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 10:55:35.772632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 10:55:35.772718 ==
5867 10:55:35.776211 DQS Delay:
5868 10:55:35.776294 DQS0 = 0, DQS1 = 0
5869 10:55:35.776360 DQM Delay:
5870 10:55:35.779433 DQM0 = 99, DQM1 = 91
5871 10:55:35.779518 DQ Delay:
5872 10:55:35.782293 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5873 10:55:35.785775 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5874 10:55:35.789101 DQ8 =75, DQ9 =83, DQ10 =95, DQ11 =83
5875 10:55:35.792349 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5876 10:55:35.792431
5877 10:55:35.792497
5878 10:55:35.792603 ==
5879 10:55:35.795689 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 10:55:35.802344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 10:55:35.802434 ==
5882 10:55:35.802500
5883 10:55:35.802560
5884 10:55:35.802618 TX Vref Scan disable
5885 10:55:35.806053 == TX Byte 0 ==
5886 10:55:35.809387 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5887 10:55:35.815991 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5888 10:55:35.816082 == TX Byte 1 ==
5889 10:55:35.819086 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5890 10:55:35.825929 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5891 10:55:35.826018 ==
5892 10:55:35.829325 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 10:55:35.832767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 10:55:35.832847 ==
5895 10:55:35.832916
5896 10:55:35.832976
5897 10:55:35.835784 TX Vref Scan disable
5898 10:55:35.835854 == TX Byte 0 ==
5899 10:55:35.842278 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5900 10:55:35.845765 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5901 10:55:35.845841 == TX Byte 1 ==
5902 10:55:35.852377 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5903 10:55:35.855291 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5904 10:55:35.855371
5905 10:55:35.855435 [DATLAT]
5906 10:55:35.858996 Freq=933, CH1 RK1
5907 10:55:35.859068
5908 10:55:35.859129 DATLAT Default: 0xb
5909 10:55:35.861900 0, 0xFFFF, sum = 0
5910 10:55:35.865630 1, 0xFFFF, sum = 0
5911 10:55:35.865712 2, 0xFFFF, sum = 0
5912 10:55:35.868612 3, 0xFFFF, sum = 0
5913 10:55:35.868686 4, 0xFFFF, sum = 0
5914 10:55:35.872083 5, 0xFFFF, sum = 0
5915 10:55:35.872153 6, 0xFFFF, sum = 0
5916 10:55:35.874958 7, 0xFFFF, sum = 0
5917 10:55:35.875029 8, 0xFFFF, sum = 0
5918 10:55:35.879054 9, 0xFFFF, sum = 0
5919 10:55:35.879124 10, 0x0, sum = 1
5920 10:55:35.881860 11, 0x0, sum = 2
5921 10:55:35.881931 12, 0x0, sum = 3
5922 10:55:35.885074 13, 0x0, sum = 4
5923 10:55:35.885148 best_step = 11
5924 10:55:35.885208
5925 10:55:35.885265 ==
5926 10:55:35.888577 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 10:55:35.892011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 10:55:35.892081 ==
5929 10:55:35.895071 RX Vref Scan: 0
5930 10:55:35.895142
5931 10:55:35.898188 RX Vref 0 -> 0, step: 1
5932 10:55:35.898257
5933 10:55:35.898316 RX Delay -69 -> 252, step: 4
5934 10:55:35.906440 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5935 10:55:35.909593 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
5936 10:55:35.913022 iDelay=203, Bit 2, Center 92 (7 ~ 178) 172
5937 10:55:35.916165 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5938 10:55:35.919766 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5939 10:55:35.926508 iDelay=203, Bit 5, Center 112 (27 ~ 198) 172
5940 10:55:35.929739 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5941 10:55:35.933193 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5942 10:55:35.936668 iDelay=203, Bit 8, Center 84 (-5 ~ 174) 180
5943 10:55:35.939392 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5944 10:55:35.942819 iDelay=203, Bit 10, Center 96 (7 ~ 186) 180
5945 10:55:35.949148 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5946 10:55:35.953254 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5947 10:55:35.956153 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5948 10:55:35.959198 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5949 10:55:35.965628 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5950 10:55:35.965706 ==
5951 10:55:35.969008 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 10:55:35.972686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 10:55:35.972759 ==
5954 10:55:35.972820 DQS Delay:
5955 10:55:35.975615 DQS0 = 0, DQS1 = 0
5956 10:55:35.975685 DQM Delay:
5957 10:55:35.979670 DQM0 = 102, DQM1 = 94
5958 10:55:35.979740 DQ Delay:
5959 10:55:35.982544 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =100
5960 10:55:35.986405 DQ4 =100, DQ5 =112, DQ6 =114, DQ7 =96
5961 10:55:35.988701 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =84
5962 10:55:35.992011 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5963 10:55:35.992081
5964 10:55:35.992144
5965 10:55:36.002051 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5966 10:55:36.005392 CH1 RK1: MR19=505, MR18=701
5967 10:55:36.008470 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
5968 10:55:36.011962 [RxdqsGatingPostProcess] freq 933
5969 10:55:36.018494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5970 10:55:36.021605 best DQS0 dly(2T, 0.5T) = (0, 10)
5971 10:55:36.025051 best DQS1 dly(2T, 0.5T) = (0, 10)
5972 10:55:36.028255 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5973 10:55:36.031636 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5974 10:55:36.034881 best DQS0 dly(2T, 0.5T) = (0, 10)
5975 10:55:36.038357 best DQS1 dly(2T, 0.5T) = (0, 10)
5976 10:55:36.042211 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5977 10:55:36.045121 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5978 10:55:36.048116 Pre-setting of DQS Precalculation
5979 10:55:36.051777 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5980 10:55:36.059026 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5981 10:55:36.064775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5982 10:55:36.064857
5983 10:55:36.064922
5984 10:55:36.068164 [Calibration Summary] 1866 Mbps
5985 10:55:36.071596 CH 0, Rank 0
5986 10:55:36.071669 SW Impedance : PASS
5987 10:55:36.074697 DUTY Scan : NO K
5988 10:55:36.078121 ZQ Calibration : PASS
5989 10:55:36.078192 Jitter Meter : NO K
5990 10:55:36.081471 CBT Training : PASS
5991 10:55:36.084497 Write leveling : PASS
5992 10:55:36.084604 RX DQS gating : PASS
5993 10:55:36.087696 RX DQ/DQS(RDDQC) : PASS
5994 10:55:36.091098 TX DQ/DQS : PASS
5995 10:55:36.091172 RX DATLAT : PASS
5996 10:55:36.095144 RX DQ/DQS(Engine): PASS
5997 10:55:36.098232 TX OE : NO K
5998 10:55:36.098303 All Pass.
5999 10:55:36.098363
6000 10:55:36.098421 CH 0, Rank 1
6001 10:55:36.101504 SW Impedance : PASS
6002 10:55:36.104203 DUTY Scan : NO K
6003 10:55:36.104300 ZQ Calibration : PASS
6004 10:55:36.107720 Jitter Meter : NO K
6005 10:55:36.107806 CBT Training : PASS
6006 10:55:36.111169 Write leveling : PASS
6007 10:55:36.114209 RX DQS gating : PASS
6008 10:55:36.114285 RX DQ/DQS(RDDQC) : PASS
6009 10:55:36.118328 TX DQ/DQS : PASS
6010 10:55:36.120982 RX DATLAT : PASS
6011 10:55:36.121059 RX DQ/DQS(Engine): PASS
6012 10:55:36.124173 TX OE : NO K
6013 10:55:36.124257 All Pass.
6014 10:55:36.124321
6015 10:55:36.127468 CH 1, Rank 0
6016 10:55:36.127572 SW Impedance : PASS
6017 10:55:36.131047 DUTY Scan : NO K
6018 10:55:36.134315 ZQ Calibration : PASS
6019 10:55:36.134389 Jitter Meter : NO K
6020 10:55:36.137614 CBT Training : PASS
6021 10:55:36.141396 Write leveling : PASS
6022 10:55:36.141467 RX DQS gating : PASS
6023 10:55:36.144669 RX DQ/DQS(RDDQC) : PASS
6024 10:55:36.147359 TX DQ/DQS : PASS
6025 10:55:36.147430 RX DATLAT : PASS
6026 10:55:36.150399 RX DQ/DQS(Engine): PASS
6027 10:55:36.154019 TX OE : NO K
6028 10:55:36.154096 All Pass.
6029 10:55:36.154163
6030 10:55:36.154227 CH 1, Rank 1
6031 10:55:36.157588 SW Impedance : PASS
6032 10:55:36.160215 DUTY Scan : NO K
6033 10:55:36.160287 ZQ Calibration : PASS
6034 10:55:36.163738 Jitter Meter : NO K
6035 10:55:36.167167 CBT Training : PASS
6036 10:55:36.167246 Write leveling : PASS
6037 10:55:36.170459 RX DQS gating : PASS
6038 10:55:36.173512 RX DQ/DQS(RDDQC) : PASS
6039 10:55:36.173584 TX DQ/DQS : PASS
6040 10:55:36.176936 RX DATLAT : PASS
6041 10:55:36.177008 RX DQ/DQS(Engine): PASS
6042 10:55:36.180500 TX OE : NO K
6043 10:55:36.180578 All Pass.
6044 10:55:36.180638
6045 10:55:36.183773 DramC Write-DBI off
6046 10:55:36.187599 PER_BANK_REFRESH: Hybrid Mode
6047 10:55:36.187669 TX_TRACKING: ON
6048 10:55:36.196739 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6049 10:55:36.200094 [FAST_K] Save calibration result to emmc
6050 10:55:36.203319 dramc_set_vcore_voltage set vcore to 650000
6051 10:55:36.206547 Read voltage for 400, 6
6052 10:55:36.206619 Vio18 = 0
6053 10:55:36.210244 Vcore = 650000
6054 10:55:36.210315 Vdram = 0
6055 10:55:36.210376 Vddq = 0
6056 10:55:36.210435 Vmddr = 0
6057 10:55:36.216834 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6058 10:55:36.223074 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6059 10:55:36.223152 MEM_TYPE=3, freq_sel=20
6060 10:55:36.226333 sv_algorithm_assistance_LP4_800
6061 10:55:36.229409 ============ PULL DRAM RESETB DOWN ============
6062 10:55:36.236290 ========== PULL DRAM RESETB DOWN end =========
6063 10:55:36.239882 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6064 10:55:36.243228 ===================================
6065 10:55:36.246174 LPDDR4 DRAM CONFIGURATION
6066 10:55:36.249799 ===================================
6067 10:55:36.249885 EX_ROW_EN[0] = 0x0
6068 10:55:36.253127 EX_ROW_EN[1] = 0x0
6069 10:55:36.255827 LP4Y_EN = 0x0
6070 10:55:36.255900 WORK_FSP = 0x0
6071 10:55:36.259440 WL = 0x2
6072 10:55:36.259514 RL = 0x2
6073 10:55:36.262891 BL = 0x2
6074 10:55:36.262964 RPST = 0x0
6075 10:55:36.265708 RD_PRE = 0x0
6076 10:55:36.265779 WR_PRE = 0x1
6077 10:55:36.269251 WR_PST = 0x0
6078 10:55:36.269328 DBI_WR = 0x0
6079 10:55:36.272603 DBI_RD = 0x0
6080 10:55:36.272674 OTF = 0x1
6081 10:55:36.276303 ===================================
6082 10:55:36.279240 ===================================
6083 10:55:36.282404 ANA top config
6084 10:55:36.286022 ===================================
6085 10:55:36.286096 DLL_ASYNC_EN = 0
6086 10:55:36.289054 ALL_SLAVE_EN = 1
6087 10:55:36.292082 NEW_RANK_MODE = 1
6088 10:55:36.295567 DLL_IDLE_MODE = 1
6089 10:55:36.298982 LP45_APHY_COMB_EN = 1
6090 10:55:36.299058 TX_ODT_DIS = 1
6091 10:55:36.302143 NEW_8X_MODE = 1
6092 10:55:36.305910 ===================================
6093 10:55:36.308798 ===================================
6094 10:55:36.313043 data_rate = 800
6095 10:55:36.315603 CKR = 1
6096 10:55:36.318815 DQ_P2S_RATIO = 4
6097 10:55:36.321797 ===================================
6098 10:55:36.325484 CA_P2S_RATIO = 4
6099 10:55:36.325557 DQ_CA_OPEN = 0
6100 10:55:36.328442 DQ_SEMI_OPEN = 1
6101 10:55:36.331976 CA_SEMI_OPEN = 1
6102 10:55:36.335200 CA_FULL_RATE = 0
6103 10:55:36.338598 DQ_CKDIV4_EN = 0
6104 10:55:36.342473 CA_CKDIV4_EN = 1
6105 10:55:36.342550 CA_PREDIV_EN = 0
6106 10:55:36.345303 PH8_DLY = 0
6107 10:55:36.349115 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6108 10:55:36.352167 DQ_AAMCK_DIV = 0
6109 10:55:36.355077 CA_AAMCK_DIV = 0
6110 10:55:36.358623 CA_ADMCK_DIV = 4
6111 10:55:36.358712 DQ_TRACK_CA_EN = 0
6112 10:55:36.361966 CA_PICK = 800
6113 10:55:36.364975 CA_MCKIO = 400
6114 10:55:36.368391 MCKIO_SEMI = 400
6115 10:55:36.372066 PLL_FREQ = 3016
6116 10:55:36.375294 DQ_UI_PI_RATIO = 32
6117 10:55:36.378332 CA_UI_PI_RATIO = 32
6118 10:55:36.381997 ===================================
6119 10:55:36.385481 ===================================
6120 10:55:36.385713 memory_type:LPDDR4
6121 10:55:36.388146 GP_NUM : 10
6122 10:55:36.391845 SRAM_EN : 1
6123 10:55:36.392076 MD32_EN : 0
6124 10:55:36.394660 ===================================
6125 10:55:36.398023 [ANA_INIT] >>>>>>>>>>>>>>
6126 10:55:36.401676 <<<<<< [CONFIGURE PHASE]: ANA_TX
6127 10:55:36.404883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6128 10:55:36.408334 ===================================
6129 10:55:36.411471 data_rate = 800,PCW = 0X7400
6130 10:55:36.414883 ===================================
6131 10:55:36.417600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6132 10:55:36.420812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6133 10:55:36.434303 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 10:55:36.437414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6135 10:55:36.440679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6136 10:55:36.444022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6137 10:55:36.448224 [ANA_INIT] flow start
6138 10:55:36.450818 [ANA_INIT] PLL >>>>>>>>
6139 10:55:36.450908 [ANA_INIT] PLL <<<<<<<<
6140 10:55:36.454010 [ANA_INIT] MIDPI >>>>>>>>
6141 10:55:36.457656 [ANA_INIT] MIDPI <<<<<<<<
6142 10:55:36.460505 [ANA_INIT] DLL >>>>>>>>
6143 10:55:36.460631 [ANA_INIT] flow end
6144 10:55:36.463705 ============ LP4 DIFF to SE enter ============
6145 10:55:36.470976 ============ LP4 DIFF to SE exit ============
6146 10:55:36.471063 [ANA_INIT] <<<<<<<<<<<<<
6147 10:55:36.473839 [Flow] Enable top DCM control >>>>>
6148 10:55:36.477180 [Flow] Enable top DCM control <<<<<
6149 10:55:36.481178 Enable DLL master slave shuffle
6150 10:55:36.487035 ==============================================================
6151 10:55:36.487125 Gating Mode config
6152 10:55:36.494058 ==============================================================
6153 10:55:36.496555 Config description:
6154 10:55:36.506773 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6155 10:55:36.513508 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6156 10:55:36.516794 SELPH_MODE 0: By rank 1: By Phase
6157 10:55:36.523484 ==============================================================
6158 10:55:36.526515 GAT_TRACK_EN = 0
6159 10:55:36.530344 RX_GATING_MODE = 2
6160 10:55:36.530430 RX_GATING_TRACK_MODE = 2
6161 10:55:36.532994 SELPH_MODE = 1
6162 10:55:36.536336 PICG_EARLY_EN = 1
6163 10:55:36.539626 VALID_LAT_VALUE = 1
6164 10:55:36.546332 ==============================================================
6165 10:55:36.549413 Enter into Gating configuration >>>>
6166 10:55:36.552782 Exit from Gating configuration <<<<
6167 10:55:36.556063 Enter into DVFS_PRE_config >>>>>
6168 10:55:36.566109 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6169 10:55:36.569288 Exit from DVFS_PRE_config <<<<<
6170 10:55:36.572909 Enter into PICG configuration >>>>
6171 10:55:36.575702 Exit from PICG configuration <<<<
6172 10:55:36.579365 [RX_INPUT] configuration >>>>>
6173 10:55:36.582246 [RX_INPUT] configuration <<<<<
6174 10:55:36.585917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6175 10:55:36.592470 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6176 10:55:36.598995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 10:55:36.605659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 10:55:36.612261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6179 10:55:36.615477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6180 10:55:36.621974 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6181 10:55:36.625415 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6182 10:55:36.628554 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6183 10:55:36.634922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6184 10:55:36.638652 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6185 10:55:36.641746 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6186 10:55:36.645593 ===================================
6187 10:55:36.648963 LPDDR4 DRAM CONFIGURATION
6188 10:55:36.651694 ===================================
6189 10:55:36.651779 EX_ROW_EN[0] = 0x0
6190 10:55:36.654842 EX_ROW_EN[1] = 0x0
6191 10:55:36.654926 LP4Y_EN = 0x0
6192 10:55:36.658491 WORK_FSP = 0x0
6193 10:55:36.661698 WL = 0x2
6194 10:55:36.661780 RL = 0x2
6195 10:55:36.664840 BL = 0x2
6196 10:55:36.664923 RPST = 0x0
6197 10:55:36.668142 RD_PRE = 0x0
6198 10:55:36.668226 WR_PRE = 0x1
6199 10:55:36.671293 WR_PST = 0x0
6200 10:55:36.671377 DBI_WR = 0x0
6201 10:55:36.674577 DBI_RD = 0x0
6202 10:55:36.674661 OTF = 0x1
6203 10:55:36.678192 ===================================
6204 10:55:36.681082 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6205 10:55:36.688163 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6206 10:55:36.691298 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6207 10:55:36.694604 ===================================
6208 10:55:36.697692 LPDDR4 DRAM CONFIGURATION
6209 10:55:36.701189 ===================================
6210 10:55:36.701278 EX_ROW_EN[0] = 0x10
6211 10:55:36.704693 EX_ROW_EN[1] = 0x0
6212 10:55:36.704788 LP4Y_EN = 0x0
6213 10:55:36.708016 WORK_FSP = 0x0
6214 10:55:36.711361 WL = 0x2
6215 10:55:36.711540 RL = 0x2
6216 10:55:36.714768 BL = 0x2
6217 10:55:36.714958 RPST = 0x0
6218 10:55:36.717934 RD_PRE = 0x0
6219 10:55:36.718123 WR_PRE = 0x1
6220 10:55:36.721217 WR_PST = 0x0
6221 10:55:36.721418 DBI_WR = 0x0
6222 10:55:36.724623 DBI_RD = 0x0
6223 10:55:36.724835 OTF = 0x1
6224 10:55:36.728037 ===================================
6225 10:55:36.734559 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6226 10:55:36.738949 nWR fixed to 30
6227 10:55:36.741832 [ModeRegInit_LP4] CH0 RK0
6228 10:55:36.742123 [ModeRegInit_LP4] CH0 RK1
6229 10:55:36.745153 [ModeRegInit_LP4] CH1 RK0
6230 10:55:36.748512 [ModeRegInit_LP4] CH1 RK1
6231 10:55:36.748826 match AC timing 19
6232 10:55:36.754909 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6233 10:55:36.758283 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6234 10:55:36.761529 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6235 10:55:36.768069 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6236 10:55:36.771485 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6237 10:55:36.771851 ==
6238 10:55:36.775422 Dram Type= 6, Freq= 0, CH_0, rank 0
6239 10:55:36.778419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 10:55:36.778786 ==
6241 10:55:36.785036 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6242 10:55:36.791497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6243 10:55:36.795183 [CA 0] Center 36 (8~64) winsize 57
6244 10:55:36.798212 [CA 1] Center 36 (8~64) winsize 57
6245 10:55:36.801898 [CA 2] Center 36 (8~64) winsize 57
6246 10:55:36.805269 [CA 3] Center 36 (8~64) winsize 57
6247 10:55:36.807726 [CA 4] Center 36 (8~64) winsize 57
6248 10:55:36.810899 [CA 5] Center 36 (8~64) winsize 57
6249 10:55:36.810983
6250 10:55:36.814294 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6251 10:55:36.814378
6252 10:55:36.817647 [CATrainingPosCal] consider 1 rank data
6253 10:55:36.820550 u2DelayCellTimex100 = 270/100 ps
6254 10:55:36.824205 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 10:55:36.827336 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 10:55:36.830465 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 10:55:36.833875 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 10:55:36.836902 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 10:55:36.840969 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 10:55:36.841052
6261 10:55:36.843828 CA PerBit enable=1, Macro0, CA PI delay=36
6262 10:55:36.847311
6263 10:55:36.847394 [CBTSetCACLKResult] CA Dly = 36
6264 10:55:36.850303 CS Dly: 1 (0~32)
6265 10:55:36.850388 ==
6266 10:55:36.853806 Dram Type= 6, Freq= 0, CH_0, rank 1
6267 10:55:36.857097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 10:55:36.857172 ==
6269 10:55:36.863669 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 10:55:36.869933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6271 10:55:36.873211 [CA 0] Center 36 (8~64) winsize 57
6272 10:55:36.876642 [CA 1] Center 36 (8~64) winsize 57
6273 10:55:36.880597 [CA 2] Center 36 (8~64) winsize 57
6274 10:55:36.883260 [CA 3] Center 36 (8~64) winsize 57
6275 10:55:36.883338 [CA 4] Center 36 (8~64) winsize 57
6276 10:55:36.886685 [CA 5] Center 36 (8~64) winsize 57
6277 10:55:36.886757
6278 10:55:36.893475 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6279 10:55:36.893557
6280 10:55:36.896509 [CATrainingPosCal] consider 2 rank data
6281 10:55:36.900284 u2DelayCellTimex100 = 270/100 ps
6282 10:55:36.903622 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 10:55:36.906216 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 10:55:36.909792 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 10:55:36.913191 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 10:55:36.916225 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 10:55:36.919861 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 10:55:36.919940
6289 10:55:36.922792 CA PerBit enable=1, Macro0, CA PI delay=36
6290 10:55:36.922869
6291 10:55:36.926202 [CBTSetCACLKResult] CA Dly = 36
6292 10:55:36.930159 CS Dly: 1 (0~32)
6293 10:55:36.930241
6294 10:55:36.933424 ----->DramcWriteLeveling(PI) begin...
6295 10:55:36.933491 ==
6296 10:55:36.936082 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 10:55:36.939370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 10:55:36.939445 ==
6299 10:55:36.942734 Write leveling (Byte 0): 40 => 8
6300 10:55:36.946195 Write leveling (Byte 1): 32 => 0
6301 10:55:36.949405 DramcWriteLeveling(PI) end<-----
6302 10:55:36.949485
6303 10:55:36.949548 ==
6304 10:55:36.952503 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 10:55:36.955842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 10:55:36.955925 ==
6307 10:55:36.959481 [Gating] SW mode calibration
6308 10:55:36.965971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6309 10:55:36.972592 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6310 10:55:36.975701 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6311 10:55:36.982916 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 10:55:36.986036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 10:55:36.989371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 10:55:36.995481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 10:55:36.999096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 10:55:37.001889 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 10:55:37.008645 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 10:55:37.011806 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 10:55:37.015418 Total UI for P1: 0, mck2ui 16
6320 10:55:37.018349 best dqsien dly found for B0: ( 0, 14, 24)
6321 10:55:37.021859 Total UI for P1: 0, mck2ui 16
6322 10:55:37.025038 best dqsien dly found for B1: ( 0, 14, 24)
6323 10:55:37.028287 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6324 10:55:37.031850 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6325 10:55:37.031917
6326 10:55:37.034738 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6327 10:55:37.038227 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 10:55:37.041610 [Gating] SW calibration Done
6329 10:55:37.041684 ==
6330 10:55:37.045359 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 10:55:37.048470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 10:55:37.051488 ==
6333 10:55:37.051576 RX Vref Scan: 0
6334 10:55:37.051648
6335 10:55:37.055281 RX Vref 0 -> 0, step: 1
6336 10:55:37.055374
6337 10:55:37.058000 RX Delay -410 -> 252, step: 16
6338 10:55:37.061409 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6339 10:55:37.065237 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6340 10:55:37.068025 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6341 10:55:37.075035 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6342 10:55:37.077829 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6343 10:55:37.081039 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6344 10:55:37.087834 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6345 10:55:37.091170 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6346 10:55:37.094901 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6347 10:55:37.098046 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6348 10:55:37.104609 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6349 10:55:37.108020 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6350 10:55:37.111285 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6351 10:55:37.114536 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6352 10:55:37.121206 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6353 10:55:37.124026 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6354 10:55:37.124405 ==
6355 10:55:37.127774 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 10:55:37.131018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 10:55:37.131412 ==
6358 10:55:37.134469 DQS Delay:
6359 10:55:37.134842 DQS0 = 43, DQS1 = 59
6360 10:55:37.137764 DQM Delay:
6361 10:55:37.138138 DQM0 = 10, DQM1 = 12
6362 10:55:37.138435 DQ Delay:
6363 10:55:37.141002 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6364 10:55:37.144370 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6365 10:55:37.147599 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6366 10:55:37.150720 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6367 10:55:37.151233
6368 10:55:37.151525
6369 10:55:37.151804 ==
6370 10:55:37.153728 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 10:55:37.160470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 10:55:37.160856 ==
6373 10:55:37.161131
6374 10:55:37.161473
6375 10:55:37.161730 TX Vref Scan disable
6376 10:55:37.164272 == TX Byte 0 ==
6377 10:55:37.167327 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 10:55:37.170244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 10:55:37.174048 == TX Byte 1 ==
6380 10:55:37.177681 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6381 10:55:37.180176 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6382 10:55:37.183762 ==
6383 10:55:37.186787 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 10:55:37.190477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 10:55:37.190855 ==
6386 10:55:37.191150
6387 10:55:37.191423
6388 10:55:37.193599 TX Vref Scan disable
6389 10:55:37.193973 == TX Byte 0 ==
6390 10:55:37.197005 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 10:55:37.203700 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 10:55:37.204068 == TX Byte 1 ==
6393 10:55:37.206711 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6394 10:55:37.213265 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6395 10:55:37.213350
6396 10:55:37.213415 [DATLAT]
6397 10:55:37.213474 Freq=400, CH0 RK0
6398 10:55:37.216407
6399 10:55:37.216494 DATLAT Default: 0xf
6400 10:55:37.219628 0, 0xFFFF, sum = 0
6401 10:55:37.219732 1, 0xFFFF, sum = 0
6402 10:55:37.223065 2, 0xFFFF, sum = 0
6403 10:55:37.223159 3, 0xFFFF, sum = 0
6404 10:55:37.226669 4, 0xFFFF, sum = 0
6405 10:55:37.226772 5, 0xFFFF, sum = 0
6406 10:55:37.229531 6, 0xFFFF, sum = 0
6407 10:55:37.229643 7, 0xFFFF, sum = 0
6408 10:55:37.232754 8, 0xFFFF, sum = 0
6409 10:55:37.232865 9, 0xFFFF, sum = 0
6410 10:55:37.236059 10, 0xFFFF, sum = 0
6411 10:55:37.236183 11, 0xFFFF, sum = 0
6412 10:55:37.239651 12, 0xFFFF, sum = 0
6413 10:55:37.239797 13, 0x0, sum = 1
6414 10:55:37.242526 14, 0x0, sum = 2
6415 10:55:37.242662 15, 0x0, sum = 3
6416 10:55:37.245934 16, 0x0, sum = 4
6417 10:55:37.246087 best_step = 14
6418 10:55:37.246207
6419 10:55:37.246319 ==
6420 10:55:37.249174 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 10:55:37.256283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 10:55:37.256497 ==
6423 10:55:37.256679 RX Vref Scan: 1
6424 10:55:37.256830
6425 10:55:37.259012 RX Vref 0 -> 0, step: 1
6426 10:55:37.259219
6427 10:55:37.262486 RX Delay -359 -> 252, step: 8
6428 10:55:37.262726
6429 10:55:37.265852 Set Vref, RX VrefLevel [Byte0]: 61
6430 10:55:37.269448 [Byte1]: 50
6431 10:55:37.272362
6432 10:55:37.272798 Final RX Vref Byte 0 = 61 to rank0
6433 10:55:37.275551 Final RX Vref Byte 1 = 50 to rank0
6434 10:55:37.279206 Final RX Vref Byte 0 = 61 to rank1
6435 10:55:37.282711 Final RX Vref Byte 1 = 50 to rank1==
6436 10:55:37.285734 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 10:55:37.292425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 10:55:37.292836 ==
6439 10:55:37.293142 DQS Delay:
6440 10:55:37.295430 DQS0 = 48, DQS1 = 60
6441 10:55:37.295803 DQM Delay:
6442 10:55:37.296107 DQM0 = 11, DQM1 = 12
6443 10:55:37.299080 DQ Delay:
6444 10:55:37.302252 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6445 10:55:37.305594 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6446 10:55:37.305976 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6447 10:55:37.312115 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6448 10:55:37.312502
6449 10:55:37.312879
6450 10:55:37.318554 [DQSOSCAuto] RK0, (LSB)MR18= 0xb679, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6451 10:55:37.322239 CH0 RK0: MR19=C0C, MR18=B679
6452 10:55:37.328624 CH0_RK0: MR19=0xC0C, MR18=0xB679, DQSOSC=387, MR23=63, INC=394, DEC=262
6453 10:55:37.329012 ==
6454 10:55:37.331948 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 10:55:37.335035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 10:55:37.335422 ==
6457 10:55:37.338384 [Gating] SW mode calibration
6458 10:55:37.345241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6459 10:55:37.351656 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6460 10:55:37.354836 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6461 10:55:37.358617 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 10:55:37.364686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 10:55:37.367931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 10:55:37.371580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 10:55:37.378199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 10:55:37.381089 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 10:55:37.384477 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 10:55:37.390948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 10:55:37.394729 Total UI for P1: 0, mck2ui 16
6470 10:55:37.397743 best dqsien dly found for B0: ( 0, 14, 24)
6471 10:55:37.401110 Total UI for P1: 0, mck2ui 16
6472 10:55:37.404388 best dqsien dly found for B1: ( 0, 14, 24)
6473 10:55:37.408085 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6474 10:55:37.411235 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6475 10:55:37.411627
6476 10:55:37.414642 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6477 10:55:37.417569 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 10:55:37.420721 [Gating] SW calibration Done
6479 10:55:37.421150 ==
6480 10:55:37.423909 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 10:55:37.427988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 10:55:37.428385 ==
6483 10:55:37.430865 RX Vref Scan: 0
6484 10:55:37.431257
6485 10:55:37.433993 RX Vref 0 -> 0, step: 1
6486 10:55:37.434383
6487 10:55:37.434698 RX Delay -410 -> 252, step: 16
6488 10:55:37.441104 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6489 10:55:37.444764 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6490 10:55:37.447398 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6491 10:55:37.453970 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6492 10:55:37.457071 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6493 10:55:37.460503 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6494 10:55:37.464077 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6495 10:55:37.467191 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6496 10:55:37.474027 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6497 10:55:37.477022 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6498 10:55:37.480374 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6499 10:55:37.487317 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6500 10:55:37.490927 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6501 10:55:37.493672 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6502 10:55:37.497318 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6503 10:55:37.504323 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6504 10:55:37.504770 ==
6505 10:55:37.507045 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 10:55:37.510446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 10:55:37.510872 ==
6508 10:55:37.511390 DQS Delay:
6509 10:55:37.514090 DQS0 = 43, DQS1 = 59
6510 10:55:37.514512 DQM Delay:
6511 10:55:37.517294 DQM0 = 10, DQM1 = 16
6512 10:55:37.517861 DQ Delay:
6513 10:55:37.520467 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6514 10:55:37.523982 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6515 10:55:37.526797 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6516 10:55:37.530853 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6517 10:55:37.531388
6518 10:55:37.531832
6519 10:55:37.532186 ==
6520 10:55:37.533394 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 10:55:37.537044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 10:55:37.537458 ==
6523 10:55:37.537886
6524 10:55:37.538371
6525 10:55:37.539996 TX Vref Scan disable
6526 10:55:37.543535 == TX Byte 0 ==
6527 10:55:37.546978 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6528 10:55:37.549916 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6529 10:55:37.553193 == TX Byte 1 ==
6530 10:55:37.556606 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6531 10:55:37.560077 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6532 10:55:37.560506 ==
6533 10:55:37.563210 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 10:55:37.566506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 10:55:37.566903 ==
6536 10:55:37.567220
6537 10:55:37.569528
6538 10:55:37.569950 TX Vref Scan disable
6539 10:55:37.573149 == TX Byte 0 ==
6540 10:55:37.576245 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6541 10:55:37.579534 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6542 10:55:37.583171 == TX Byte 1 ==
6543 10:55:37.586984 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6544 10:55:37.589769 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6545 10:55:37.590294
6546 10:55:37.590637 [DATLAT]
6547 10:55:37.593542 Freq=400, CH0 RK1
6548 10:55:37.593971
6549 10:55:37.596286 DATLAT Default: 0xe
6550 10:55:37.596788 0, 0xFFFF, sum = 0
6551 10:55:37.599412 1, 0xFFFF, sum = 0
6552 10:55:37.599871 2, 0xFFFF, sum = 0
6553 10:55:37.603032 3, 0xFFFF, sum = 0
6554 10:55:37.603466 4, 0xFFFF, sum = 0
6555 10:55:37.606152 5, 0xFFFF, sum = 0
6556 10:55:37.606584 6, 0xFFFF, sum = 0
6557 10:55:37.609523 7, 0xFFFF, sum = 0
6558 10:55:37.609960 8, 0xFFFF, sum = 0
6559 10:55:37.613283 9, 0xFFFF, sum = 0
6560 10:55:37.613717 10, 0xFFFF, sum = 0
6561 10:55:37.615884 11, 0xFFFF, sum = 0
6562 10:55:37.616314 12, 0xFFFF, sum = 0
6563 10:55:37.619528 13, 0x0, sum = 1
6564 10:55:37.619959 14, 0x0, sum = 2
6565 10:55:37.622657 15, 0x0, sum = 3
6566 10:55:37.623091 16, 0x0, sum = 4
6567 10:55:37.626041 best_step = 14
6568 10:55:37.626467
6569 10:55:37.626803 ==
6570 10:55:37.629471 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 10:55:37.632497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 10:55:37.632978 ==
6573 10:55:37.636042 RX Vref Scan: 0
6574 10:55:37.636469
6575 10:55:37.636893 RX Vref 0 -> 0, step: 1
6576 10:55:37.637222
6577 10:55:37.639048 RX Delay -359 -> 252, step: 8
6578 10:55:37.647036 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6579 10:55:37.650443 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6580 10:55:37.653614 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6581 10:55:37.660359 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6582 10:55:37.663385 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6583 10:55:37.666709 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6584 10:55:37.669837 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6585 10:55:37.676934 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6586 10:55:37.679960 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6587 10:55:37.683565 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6588 10:55:37.686403 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6589 10:55:37.693623 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6590 10:55:37.696283 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6591 10:55:37.700069 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6592 10:55:37.703461 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6593 10:55:37.709678 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6594 10:55:37.710110 ==
6595 10:55:37.712550 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 10:55:37.716268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 10:55:37.716747 ==
6598 10:55:37.717094 DQS Delay:
6599 10:55:37.719325 DQS0 = 44, DQS1 = 60
6600 10:55:37.719754 DQM Delay:
6601 10:55:37.722784 DQM0 = 7, DQM1 = 14
6602 10:55:37.723211 DQ Delay:
6603 10:55:37.726130 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6604 10:55:37.729159 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6605 10:55:37.732613 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6606 10:55:37.736850 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6607 10:55:37.737280
6608 10:55:37.737620
6609 10:55:37.742513 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf3d, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6610 10:55:37.745789 CH0 RK1: MR19=C0C, MR18=AF3D
6611 10:55:37.752306 CH0_RK1: MR19=0xC0C, MR18=0xAF3D, DQSOSC=388, MR23=63, INC=392, DEC=261
6612 10:55:37.755704 [RxdqsGatingPostProcess] freq 400
6613 10:55:37.762858 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6614 10:55:37.765609 best DQS0 dly(2T, 0.5T) = (0, 10)
6615 10:55:37.769391 best DQS1 dly(2T, 0.5T) = (0, 10)
6616 10:55:37.772218 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6617 10:55:37.776142 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6618 10:55:37.776616 best DQS0 dly(2T, 0.5T) = (0, 10)
6619 10:55:37.778635 best DQS1 dly(2T, 0.5T) = (0, 10)
6620 10:55:37.781930 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6621 10:55:37.785556 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6622 10:55:37.788727 Pre-setting of DQS Precalculation
6623 10:55:37.795718 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6624 10:55:37.796287 ==
6625 10:55:37.798665 Dram Type= 6, Freq= 0, CH_1, rank 0
6626 10:55:37.802397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 10:55:37.802832 ==
6628 10:55:37.808956 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6629 10:55:37.815024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6630 10:55:37.818304 [CA 0] Center 36 (8~64) winsize 57
6631 10:55:37.822081 [CA 1] Center 36 (8~64) winsize 57
6632 10:55:37.822522 [CA 2] Center 36 (8~64) winsize 57
6633 10:55:37.824885 [CA 3] Center 36 (8~64) winsize 57
6634 10:55:37.828145 [CA 4] Center 36 (8~64) winsize 57
6635 10:55:37.832096 [CA 5] Center 36 (8~64) winsize 57
6636 10:55:37.832558
6637 10:55:37.835777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6638 10:55:37.838800
6639 10:55:37.841812 [CATrainingPosCal] consider 1 rank data
6640 10:55:37.842335 u2DelayCellTimex100 = 270/100 ps
6641 10:55:37.847895 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 10:55:37.851603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 10:55:37.855120 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 10:55:37.857804 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 10:55:37.861380 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 10:55:37.864828 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 10:55:37.865247
6648 10:55:37.867970 CA PerBit enable=1, Macro0, CA PI delay=36
6649 10:55:37.868387
6650 10:55:37.870956 [CBTSetCACLKResult] CA Dly = 36
6651 10:55:37.874651 CS Dly: 1 (0~32)
6652 10:55:37.875170 ==
6653 10:55:37.878163 Dram Type= 6, Freq= 0, CH_1, rank 1
6654 10:55:37.881427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 10:55:37.881853 ==
6656 10:55:37.887532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 10:55:37.894466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6658 10:55:37.897414 [CA 0] Center 36 (8~64) winsize 57
6659 10:55:37.897840 [CA 1] Center 36 (8~64) winsize 57
6660 10:55:37.900415 [CA 2] Center 36 (8~64) winsize 57
6661 10:55:37.904624 [CA 3] Center 36 (8~64) winsize 57
6662 10:55:37.907358 [CA 4] Center 36 (8~64) winsize 57
6663 10:55:37.910459 [CA 5] Center 36 (8~64) winsize 57
6664 10:55:37.910899
6665 10:55:37.913772 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6666 10:55:37.914193
6667 10:55:37.920382 [CATrainingPosCal] consider 2 rank data
6668 10:55:37.920830 u2DelayCellTimex100 = 270/100 ps
6669 10:55:37.923644 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 10:55:37.931113 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 10:55:37.934021 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 10:55:37.937520 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 10:55:37.940692 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 10:55:37.944023 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 10:55:37.944444
6676 10:55:37.946713 CA PerBit enable=1, Macro0, CA PI delay=36
6677 10:55:37.946794
6678 10:55:37.950643 [CBTSetCACLKResult] CA Dly = 36
6679 10:55:37.950725 CS Dly: 1 (0~32)
6680 10:55:37.953776
6681 10:55:37.957026 ----->DramcWriteLeveling(PI) begin...
6682 10:55:37.957125 ==
6683 10:55:37.960130 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 10:55:37.963606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 10:55:37.963689 ==
6686 10:55:37.966621 Write leveling (Byte 0): 40 => 8
6687 10:55:37.969673 Write leveling (Byte 1): 40 => 8
6688 10:55:37.973042 DramcWriteLeveling(PI) end<-----
6689 10:55:37.973123
6690 10:55:37.973187 ==
6691 10:55:37.976622 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 10:55:37.980033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 10:55:37.980114 ==
6694 10:55:37.983257 [Gating] SW mode calibration
6695 10:55:37.989583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6696 10:55:37.996019 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6697 10:55:37.999194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6698 10:55:38.003105 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 10:55:38.009078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 10:55:38.012872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 10:55:38.016159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 10:55:38.022856 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 10:55:38.026577 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 10:55:38.029401 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 10:55:38.036269 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 10:55:38.036470 Total UI for P1: 0, mck2ui 16
6707 10:55:38.042952 best dqsien dly found for B0: ( 0, 14, 24)
6708 10:55:38.043193 Total UI for P1: 0, mck2ui 16
6709 10:55:38.049045 best dqsien dly found for B1: ( 0, 14, 24)
6710 10:55:38.052488 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6711 10:55:38.055734 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6712 10:55:38.056305
6713 10:55:38.058811 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6714 10:55:38.062716 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 10:55:38.065717 [Gating] SW calibration Done
6716 10:55:38.066135 ==
6717 10:55:38.069102 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 10:55:38.072424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 10:55:38.072872 ==
6720 10:55:38.075643 RX Vref Scan: 0
6721 10:55:38.076063
6722 10:55:38.078963 RX Vref 0 -> 0, step: 1
6723 10:55:38.079380
6724 10:55:38.079711 RX Delay -410 -> 252, step: 16
6725 10:55:38.085454 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6726 10:55:38.089115 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6727 10:55:38.092655 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6728 10:55:38.095502 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6729 10:55:38.102094 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6730 10:55:38.105447 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6731 10:55:38.108773 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6732 10:55:38.115460 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6733 10:55:38.118482 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6734 10:55:38.122141 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6735 10:55:38.125280 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6736 10:55:38.131837 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6737 10:55:38.135385 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6738 10:55:38.138447 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6739 10:55:38.141994 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6740 10:55:38.148779 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6741 10:55:38.149202 ==
6742 10:55:38.151734 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 10:55:38.154896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 10:55:38.155492 ==
6745 10:55:38.155948 DQS Delay:
6746 10:55:38.158610 DQS0 = 43, DQS1 = 51
6747 10:55:38.159032 DQM Delay:
6748 10:55:38.161760 DQM0 = 12, DQM1 = 14
6749 10:55:38.162177 DQ Delay:
6750 10:55:38.165331 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6751 10:55:38.168551 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6752 10:55:38.171752 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6753 10:55:38.175147 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6754 10:55:38.175566
6755 10:55:38.175895
6756 10:55:38.176203 ==
6757 10:55:38.178162 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 10:55:38.181293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 10:55:38.181716 ==
6760 10:55:38.182051
6761 10:55:38.182360
6762 10:55:38.185077 TX Vref Scan disable
6763 10:55:38.188407 == TX Byte 0 ==
6764 10:55:38.191684 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 10:55:38.195439 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 10:55:38.195823 == TX Byte 1 ==
6767 10:55:38.201497 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 10:55:38.204479 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 10:55:38.204913 ==
6770 10:55:38.208450 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 10:55:38.211436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 10:55:38.211823 ==
6773 10:55:38.212129
6774 10:55:38.214594
6775 10:55:38.214980 TX Vref Scan disable
6776 10:55:38.217758 == TX Byte 0 ==
6777 10:55:38.220787 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 10:55:38.224163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 10:55:38.227509 == TX Byte 1 ==
6780 10:55:38.230844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 10:55:38.234078 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 10:55:38.234159
6783 10:55:38.234224 [DATLAT]
6784 10:55:38.237424 Freq=400, CH1 RK0
6785 10:55:38.237505
6786 10:55:38.240320 DATLAT Default: 0xf
6787 10:55:38.240431 0, 0xFFFF, sum = 0
6788 10:55:38.244019 1, 0xFFFF, sum = 0
6789 10:55:38.244102 2, 0xFFFF, sum = 0
6790 10:55:38.246983 3, 0xFFFF, sum = 0
6791 10:55:38.247066 4, 0xFFFF, sum = 0
6792 10:55:38.250463 5, 0xFFFF, sum = 0
6793 10:55:38.250545 6, 0xFFFF, sum = 0
6794 10:55:38.253600 7, 0xFFFF, sum = 0
6795 10:55:38.253682 8, 0xFFFF, sum = 0
6796 10:55:38.256991 9, 0xFFFF, sum = 0
6797 10:55:38.257074 10, 0xFFFF, sum = 0
6798 10:55:38.260710 11, 0xFFFF, sum = 0
6799 10:55:38.260792 12, 0xFFFF, sum = 0
6800 10:55:38.263679 13, 0x0, sum = 1
6801 10:55:38.263762 14, 0x0, sum = 2
6802 10:55:38.267237 15, 0x0, sum = 3
6803 10:55:38.267320 16, 0x0, sum = 4
6804 10:55:38.270810 best_step = 14
6805 10:55:38.270891
6806 10:55:38.270955 ==
6807 10:55:38.273468 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 10:55:38.276497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 10:55:38.276603 ==
6810 10:55:38.280437 RX Vref Scan: 1
6811 10:55:38.280524
6812 10:55:38.280618 RX Vref 0 -> 0, step: 1
6813 10:55:38.280678
6814 10:55:38.283471 RX Delay -343 -> 252, step: 8
6815 10:55:38.283552
6816 10:55:38.286396 Set Vref, RX VrefLevel [Byte0]: 47
6817 10:55:38.290046 [Byte1]: 54
6818 10:55:38.294701
6819 10:55:38.294782 Final RX Vref Byte 0 = 47 to rank0
6820 10:55:38.297781 Final RX Vref Byte 1 = 54 to rank0
6821 10:55:38.301329 Final RX Vref Byte 0 = 47 to rank1
6822 10:55:38.304386 Final RX Vref Byte 1 = 54 to rank1==
6823 10:55:38.307634 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 10:55:38.314632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 10:55:38.314714 ==
6826 10:55:38.314780 DQS Delay:
6827 10:55:38.317710 DQS0 = 44, DQS1 = 56
6828 10:55:38.317791 DQM Delay:
6829 10:55:38.317855 DQM0 = 9, DQM1 = 12
6830 10:55:38.321048 DQ Delay:
6831 10:55:38.324231 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6832 10:55:38.327662 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6833 10:55:38.327744 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6834 10:55:38.330711 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6835 10:55:38.334019
6836 10:55:38.334100
6837 10:55:38.340619 [DQSOSCAuto] RK0, (LSB)MR18= 0x9168, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6838 10:55:38.344099 CH1 RK0: MR19=C0C, MR18=9168
6839 10:55:38.351004 CH1_RK0: MR19=0xC0C, MR18=0x9168, DQSOSC=391, MR23=63, INC=386, DEC=257
6840 10:55:38.351087 ==
6841 10:55:38.353763 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 10:55:38.357006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 10:55:38.357090 ==
6844 10:55:38.360903 [Gating] SW mode calibration
6845 10:55:38.366730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6846 10:55:38.373848 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6847 10:55:38.376498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6848 10:55:38.380169 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 10:55:38.386567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 10:55:38.390227 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 10:55:38.393400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 10:55:38.399609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 10:55:38.403303 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 10:55:38.406248 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 10:55:38.412908 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 10:55:38.416435 Total UI for P1: 0, mck2ui 16
6857 10:55:38.419494 best dqsien dly found for B0: ( 0, 14, 24)
6858 10:55:38.422983 Total UI for P1: 0, mck2ui 16
6859 10:55:38.426238 best dqsien dly found for B1: ( 0, 14, 24)
6860 10:55:38.429497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6861 10:55:38.432562 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6862 10:55:38.432643
6863 10:55:38.436385 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6864 10:55:38.439974 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 10:55:38.443034 [Gating] SW calibration Done
6866 10:55:38.443115 ==
6867 10:55:38.445874 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 10:55:38.449159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 10:55:38.449242 ==
6870 10:55:38.452846 RX Vref Scan: 0
6871 10:55:38.452927
6872 10:55:38.455860 RX Vref 0 -> 0, step: 1
6873 10:55:38.455941
6874 10:55:38.456006 RX Delay -410 -> 252, step: 16
6875 10:55:38.463193 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6876 10:55:38.465775 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6877 10:55:38.469521 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6878 10:55:38.475501 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6879 10:55:38.479157 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6880 10:55:38.482920 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6881 10:55:38.485891 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6882 10:55:38.492187 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6883 10:55:38.495694 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6884 10:55:38.499060 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6885 10:55:38.503014 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6886 10:55:38.508468 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6887 10:55:38.511850 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6888 10:55:38.515219 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6889 10:55:38.522175 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6890 10:55:38.525313 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6891 10:55:38.525395 ==
6892 10:55:38.528248 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 10:55:38.531286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 10:55:38.531367 ==
6895 10:55:38.535063 DQS Delay:
6896 10:55:38.535144 DQS0 = 43, DQS1 = 51
6897 10:55:38.535209 DQM Delay:
6898 10:55:38.538121 DQM0 = 13, DQM1 = 14
6899 10:55:38.538202 DQ Delay:
6900 10:55:38.541840 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6901 10:55:38.544923 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6902 10:55:38.547918 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6903 10:55:38.551427 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6904 10:55:38.551509
6905 10:55:38.551573
6906 10:55:38.551633 ==
6907 10:55:38.554571 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 10:55:38.557976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 10:55:38.558060 ==
6910 10:55:38.561786
6911 10:55:38.561867
6912 10:55:38.561931 TX Vref Scan disable
6913 10:55:38.565392 == TX Byte 0 ==
6914 10:55:38.568102 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6915 10:55:38.571248 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6916 10:55:38.575082 == TX Byte 1 ==
6917 10:55:38.578095 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6918 10:55:38.581146 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6919 10:55:38.581228 ==
6920 10:55:38.584845 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 10:55:38.587782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 10:55:38.591097 ==
6923 10:55:38.591179
6924 10:55:38.591243
6925 10:55:38.591301 TX Vref Scan disable
6926 10:55:38.595022 == TX Byte 0 ==
6927 10:55:38.597989 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6928 10:55:38.601299 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6929 10:55:38.604807 == TX Byte 1 ==
6930 10:55:38.607671 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6931 10:55:38.610963 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6932 10:55:38.611045
6933 10:55:38.614456 [DATLAT]
6934 10:55:38.614537 Freq=400, CH1 RK1
6935 10:55:38.614602
6936 10:55:38.617374 DATLAT Default: 0xe
6937 10:55:38.617455 0, 0xFFFF, sum = 0
6938 10:55:38.620626 1, 0xFFFF, sum = 0
6939 10:55:38.620709 2, 0xFFFF, sum = 0
6940 10:55:38.624100 3, 0xFFFF, sum = 0
6941 10:55:38.624183 4, 0xFFFF, sum = 0
6942 10:55:38.627953 5, 0xFFFF, sum = 0
6943 10:55:38.628036 6, 0xFFFF, sum = 0
6944 10:55:38.630805 7, 0xFFFF, sum = 0
6945 10:55:38.630889 8, 0xFFFF, sum = 0
6946 10:55:38.634321 9, 0xFFFF, sum = 0
6947 10:55:38.634405 10, 0xFFFF, sum = 0
6948 10:55:38.637136 11, 0xFFFF, sum = 0
6949 10:55:38.640763 12, 0xFFFF, sum = 0
6950 10:55:38.640846 13, 0x0, sum = 1
6951 10:55:38.640913 14, 0x0, sum = 2
6952 10:55:38.643976 15, 0x0, sum = 3
6953 10:55:38.644059 16, 0x0, sum = 4
6954 10:55:38.647595 best_step = 14
6955 10:55:38.647677
6956 10:55:38.647742 ==
6957 10:55:38.650721 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 10:55:38.653725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 10:55:38.653808 ==
6960 10:55:38.657074 RX Vref Scan: 0
6961 10:55:38.657157
6962 10:55:38.657221 RX Vref 0 -> 0, step: 1
6963 10:55:38.657282
6964 10:55:38.660667 RX Delay -343 -> 252, step: 8
6965 10:55:38.668436 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6966 10:55:38.672205 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6967 10:55:38.675200 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6968 10:55:38.682299 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6969 10:55:38.685507 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6970 10:55:38.688438 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6971 10:55:38.691560 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6972 10:55:38.698410 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6973 10:55:38.701719 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6974 10:55:38.704704 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6975 10:55:38.708216 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6976 10:55:38.714627 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6977 10:55:38.718097 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6978 10:55:38.721240 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6979 10:55:38.724750 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6980 10:55:38.731664 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6981 10:55:38.731743 ==
6982 10:55:38.734617 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 10:55:38.738160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 10:55:38.738252 ==
6985 10:55:38.738316 DQS Delay:
6986 10:55:38.741649 DQS0 = 48, DQS1 = 56
6987 10:55:38.741736 DQM Delay:
6988 10:55:38.744578 DQM0 = 12, DQM1 = 10
6989 10:55:38.744750 DQ Delay:
6990 10:55:38.747829 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6991 10:55:38.751099 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6992 10:55:38.754691 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6993 10:55:38.757639 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6994 10:55:38.757756
6995 10:55:38.757846
6996 10:55:38.767876 [DQSOSCAuto] RK1, (LSB)MR18= 0x6150, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
6997 10:55:38.768015 CH1 RK1: MR19=C0C, MR18=6150
6998 10:55:38.774399 CH1_RK1: MR19=0xC0C, MR18=0x6150, DQSOSC=397, MR23=63, INC=374, DEC=249
6999 10:55:38.778229 [RxdqsGatingPostProcess] freq 400
7000 10:55:38.784198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7001 10:55:38.787557 best DQS0 dly(2T, 0.5T) = (0, 10)
7002 10:55:38.791308 best DQS1 dly(2T, 0.5T) = (0, 10)
7003 10:55:38.795024 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7004 10:55:38.797852 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7005 10:55:38.801293 best DQS0 dly(2T, 0.5T) = (0, 10)
7006 10:55:38.801751 best DQS1 dly(2T, 0.5T) = (0, 10)
7007 10:55:38.804416 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7008 10:55:38.807595 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7009 10:55:38.811042 Pre-setting of DQS Precalculation
7010 10:55:38.817395 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7011 10:55:38.824119 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7012 10:55:38.831018 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7013 10:55:38.831528
7014 10:55:38.831864
7015 10:55:38.833841 [Calibration Summary] 800 Mbps
7016 10:55:38.837406 CH 0, Rank 0
7017 10:55:38.837939 SW Impedance : PASS
7018 10:55:38.840803 DUTY Scan : NO K
7019 10:55:38.841272 ZQ Calibration : PASS
7020 10:55:38.843709 Jitter Meter : NO K
7021 10:55:38.847025 CBT Training : PASS
7022 10:55:38.847479 Write leveling : PASS
7023 10:55:38.850285 RX DQS gating : PASS
7024 10:55:38.854256 RX DQ/DQS(RDDQC) : PASS
7025 10:55:38.854732 TX DQ/DQS : PASS
7026 10:55:38.857183 RX DATLAT : PASS
7027 10:55:38.860341 RX DQ/DQS(Engine): PASS
7028 10:55:38.860999 TX OE : NO K
7029 10:55:38.863393 All Pass.
7030 10:55:38.864032
7031 10:55:38.864644 CH 0, Rank 1
7032 10:55:38.866850 SW Impedance : PASS
7033 10:55:38.867398 DUTY Scan : NO K
7034 10:55:38.869898 ZQ Calibration : PASS
7035 10:55:38.873614 Jitter Meter : NO K
7036 10:55:38.874282 CBT Training : PASS
7037 10:55:38.876784 Write leveling : NO K
7038 10:55:38.880055 RX DQS gating : PASS
7039 10:55:38.880734 RX DQ/DQS(RDDQC) : PASS
7040 10:55:38.883523 TX DQ/DQS : PASS
7041 10:55:38.887054 RX DATLAT : PASS
7042 10:55:38.887719 RX DQ/DQS(Engine): PASS
7043 10:55:38.889838 TX OE : NO K
7044 10:55:38.890433 All Pass.
7045 10:55:38.890974
7046 10:55:38.893624 CH 1, Rank 0
7047 10:55:38.894206 SW Impedance : PASS
7048 10:55:38.896823 DUTY Scan : NO K
7049 10:55:38.899814 ZQ Calibration : PASS
7050 10:55:38.900398 Jitter Meter : NO K
7051 10:55:38.903348 CBT Training : PASS
7052 10:55:38.906313 Write leveling : PASS
7053 10:55:38.906773 RX DQS gating : PASS
7054 10:55:38.909737 RX DQ/DQS(RDDQC) : PASS
7055 10:55:38.910245 TX DQ/DQS : PASS
7056 10:55:38.913309 RX DATLAT : PASS
7057 10:55:38.916805 RX DQ/DQS(Engine): PASS
7058 10:55:38.917324 TX OE : NO K
7059 10:55:38.920304 All Pass.
7060 10:55:38.920826
7061 10:55:38.921165 CH 1, Rank 1
7062 10:55:38.923461 SW Impedance : PASS
7063 10:55:38.923881 DUTY Scan : NO K
7064 10:55:38.926241 ZQ Calibration : PASS
7065 10:55:38.930040 Jitter Meter : NO K
7066 10:55:38.930464 CBT Training : PASS
7067 10:55:38.933056 Write leveling : NO K
7068 10:55:38.936846 RX DQS gating : PASS
7069 10:55:38.937366 RX DQ/DQS(RDDQC) : PASS
7070 10:55:38.939839 TX DQ/DQS : PASS
7071 10:55:38.943117 RX DATLAT : PASS
7072 10:55:38.943675 RX DQ/DQS(Engine): PASS
7073 10:55:38.946235 TX OE : NO K
7074 10:55:38.946761 All Pass.
7075 10:55:38.947263
7076 10:55:38.949521 DramC Write-DBI off
7077 10:55:38.952943 PER_BANK_REFRESH: Hybrid Mode
7078 10:55:38.953464 TX_TRACKING: ON
7079 10:55:38.962776 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7080 10:55:38.966273 [FAST_K] Save calibration result to emmc
7081 10:55:38.969247 dramc_set_vcore_voltage set vcore to 725000
7082 10:55:38.972480 Read voltage for 1600, 0
7083 10:55:38.973066 Vio18 = 0
7084 10:55:38.973547 Vcore = 725000
7085 10:55:38.975858 Vdram = 0
7086 10:55:38.976347 Vddq = 0
7087 10:55:38.976764 Vmddr = 0
7088 10:55:38.982609 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7089 10:55:38.986021 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7090 10:55:38.989022 MEM_TYPE=3, freq_sel=13
7091 10:55:38.992440 sv_algorithm_assistance_LP4_3733
7092 10:55:38.995997 ============ PULL DRAM RESETB DOWN ============
7093 10:55:39.002607 ========== PULL DRAM RESETB DOWN end =========
7094 10:55:39.005324 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7095 10:55:39.009203 ===================================
7096 10:55:39.011979 LPDDR4 DRAM CONFIGURATION
7097 10:55:39.015551 ===================================
7098 10:55:39.015977 EX_ROW_EN[0] = 0x0
7099 10:55:39.018684 EX_ROW_EN[1] = 0x0
7100 10:55:39.019107 LP4Y_EN = 0x0
7101 10:55:39.021970 WORK_FSP = 0x1
7102 10:55:39.022395 WL = 0x5
7103 10:55:39.025309 RL = 0x5
7104 10:55:39.028620 BL = 0x2
7105 10:55:39.029045 RPST = 0x0
7106 10:55:39.031598 RD_PRE = 0x0
7107 10:55:39.032063 WR_PRE = 0x1
7108 10:55:39.035087 WR_PST = 0x1
7109 10:55:39.035532 DBI_WR = 0x0
7110 10:55:39.038609 DBI_RD = 0x0
7111 10:55:39.039161 OTF = 0x1
7112 10:55:39.042141 ===================================
7113 10:55:39.044818 ===================================
7114 10:55:39.048124 ANA top config
7115 10:55:39.051522 ===================================
7116 10:55:39.052043 DLL_ASYNC_EN = 0
7117 10:55:39.055148 ALL_SLAVE_EN = 0
7118 10:55:39.058024 NEW_RANK_MODE = 1
7119 10:55:39.061312 DLL_IDLE_MODE = 1
7120 10:55:39.064781 LP45_APHY_COMB_EN = 1
7121 10:55:39.065296 TX_ODT_DIS = 0
7122 10:55:39.067748 NEW_8X_MODE = 1
7123 10:55:39.071416 ===================================
7124 10:55:39.075103 ===================================
7125 10:55:39.078229 data_rate = 3200
7126 10:55:39.080944 CKR = 1
7127 10:55:39.085061 DQ_P2S_RATIO = 8
7128 10:55:39.088129 ===================================
7129 10:55:39.088703 CA_P2S_RATIO = 8
7130 10:55:39.091204 DQ_CA_OPEN = 0
7131 10:55:39.094495 DQ_SEMI_OPEN = 0
7132 10:55:39.097381 CA_SEMI_OPEN = 0
7133 10:55:39.101162 CA_FULL_RATE = 0
7134 10:55:39.104346 DQ_CKDIV4_EN = 0
7135 10:55:39.107763 CA_CKDIV4_EN = 0
7136 10:55:39.108326 CA_PREDIV_EN = 0
7137 10:55:39.110978 PH8_DLY = 12
7138 10:55:39.114082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7139 10:55:39.117666 DQ_AAMCK_DIV = 4
7140 10:55:39.120497 CA_AAMCK_DIV = 4
7141 10:55:39.123732 CA_ADMCK_DIV = 4
7142 10:55:39.124152 DQ_TRACK_CA_EN = 0
7143 10:55:39.127294 CA_PICK = 1600
7144 10:55:39.130416 CA_MCKIO = 1600
7145 10:55:39.133692 MCKIO_SEMI = 0
7146 10:55:39.137136 PLL_FREQ = 3068
7147 10:55:39.140400 DQ_UI_PI_RATIO = 32
7148 10:55:39.143688 CA_UI_PI_RATIO = 0
7149 10:55:39.147502 ===================================
7150 10:55:39.150382 ===================================
7151 10:55:39.150807 memory_type:LPDDR4
7152 10:55:39.153802 GP_NUM : 10
7153 10:55:39.157140 SRAM_EN : 1
7154 10:55:39.157683 MD32_EN : 0
7155 10:55:39.160058 ===================================
7156 10:55:39.163166 [ANA_INIT] >>>>>>>>>>>>>>
7157 10:55:39.166425 <<<<<< [CONFIGURE PHASE]: ANA_TX
7158 10:55:39.170154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7159 10:55:39.173025 ===================================
7160 10:55:39.176484 data_rate = 3200,PCW = 0X7600
7161 10:55:39.179547 ===================================
7162 10:55:39.183484 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7163 10:55:39.186288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7164 10:55:39.193173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 10:55:39.199696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7166 10:55:39.203051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7167 10:55:39.206166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7168 10:55:39.206591 [ANA_INIT] flow start
7169 10:55:39.209378 [ANA_INIT] PLL >>>>>>>>
7170 10:55:39.212737 [ANA_INIT] PLL <<<<<<<<
7171 10:55:39.213156 [ANA_INIT] MIDPI >>>>>>>>
7172 10:55:39.216206 [ANA_INIT] MIDPI <<<<<<<<
7173 10:55:39.219390 [ANA_INIT] DLL >>>>>>>>
7174 10:55:39.219852 [ANA_INIT] DLL <<<<<<<<
7175 10:55:39.222640 [ANA_INIT] flow end
7176 10:55:39.226115 ============ LP4 DIFF to SE enter ============
7177 10:55:39.232195 ============ LP4 DIFF to SE exit ============
7178 10:55:39.232653 [ANA_INIT] <<<<<<<<<<<<<
7179 10:55:39.236180 [Flow] Enable top DCM control >>>>>
7180 10:55:39.239374 [Flow] Enable top DCM control <<<<<
7181 10:55:39.242578 Enable DLL master slave shuffle
7182 10:55:39.248989 ==============================================================
7183 10:55:39.249413 Gating Mode config
7184 10:55:39.255845 ==============================================================
7185 10:55:39.259099 Config description:
7186 10:55:39.265445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7187 10:55:39.275669 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7188 10:55:39.278633 SELPH_MODE 0: By rank 1: By Phase
7189 10:55:39.285547 ==============================================================
7190 10:55:39.288871 GAT_TRACK_EN = 1
7191 10:55:39.289320 RX_GATING_MODE = 2
7192 10:55:39.291811 RX_GATING_TRACK_MODE = 2
7193 10:55:39.295532 SELPH_MODE = 1
7194 10:55:39.298493 PICG_EARLY_EN = 1
7195 10:55:39.301749 VALID_LAT_VALUE = 1
7196 10:55:39.308208 ==============================================================
7197 10:55:39.311941 Enter into Gating configuration >>>>
7198 10:55:39.315375 Exit from Gating configuration <<<<
7199 10:55:39.318406 Enter into DVFS_PRE_config >>>>>
7200 10:55:39.328658 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7201 10:55:39.331766 Exit from DVFS_PRE_config <<<<<
7202 10:55:39.335193 Enter into PICG configuration >>>>
7203 10:55:39.338137 Exit from PICG configuration <<<<
7204 10:55:39.341616 [RX_INPUT] configuration >>>>>
7205 10:55:39.344595 [RX_INPUT] configuration <<<<<
7206 10:55:39.348183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7207 10:55:39.354604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7208 10:55:39.361017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 10:55:39.367768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 10:55:39.370998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7211 10:55:39.377592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7212 10:55:39.381428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7213 10:55:39.388057 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7214 10:55:39.391350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7215 10:55:39.393932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7216 10:55:39.400906 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7217 10:55:39.404194 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7218 10:55:39.407179 ===================================
7219 10:55:39.410501 LPDDR4 DRAM CONFIGURATION
7220 10:55:39.413847 ===================================
7221 10:55:39.414278 EX_ROW_EN[0] = 0x0
7222 10:55:39.417194 EX_ROW_EN[1] = 0x0
7223 10:55:39.417619 LP4Y_EN = 0x0
7224 10:55:39.420644 WORK_FSP = 0x1
7225 10:55:39.421070 WL = 0x5
7226 10:55:39.424082 RL = 0x5
7227 10:55:39.424669 BL = 0x2
7228 10:55:39.426944 RPST = 0x0
7229 10:55:39.427370 RD_PRE = 0x0
7230 10:55:39.431143 WR_PRE = 0x1
7231 10:55:39.433557 WR_PST = 0x1
7232 10:55:39.433983 DBI_WR = 0x0
7233 10:55:39.437389 DBI_RD = 0x0
7234 10:55:39.437815 OTF = 0x1
7235 10:55:39.440595 ===================================
7236 10:55:39.443730 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7237 10:55:39.450156 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7238 10:55:39.453836 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7239 10:55:39.456718 ===================================
7240 10:55:39.460219 LPDDR4 DRAM CONFIGURATION
7241 10:55:39.463418 ===================================
7242 10:55:39.463842 EX_ROW_EN[0] = 0x10
7243 10:55:39.466459 EX_ROW_EN[1] = 0x0
7244 10:55:39.466882 LP4Y_EN = 0x0
7245 10:55:39.469689 WORK_FSP = 0x1
7246 10:55:39.470112 WL = 0x5
7247 10:55:39.473064 RL = 0x5
7248 10:55:39.473486 BL = 0x2
7249 10:55:39.476831 RPST = 0x0
7250 10:55:39.477252 RD_PRE = 0x0
7251 10:55:39.479844 WR_PRE = 0x1
7252 10:55:39.483311 WR_PST = 0x1
7253 10:55:39.483734 DBI_WR = 0x0
7254 10:55:39.486623 DBI_RD = 0x0
7255 10:55:39.487047 OTF = 0x1
7256 10:55:39.489786 ===================================
7257 10:55:39.496277 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7258 10:55:39.496732 ==
7259 10:55:39.499505 Dram Type= 6, Freq= 0, CH_0, rank 0
7260 10:55:39.503039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7261 10:55:39.503464 ==
7262 10:55:39.506266 [Duty_Offset_Calibration]
7263 10:55:39.509428 B0:1 B1:-1 CA:0
7264 10:55:39.509849
7265 10:55:39.512478 [DutyScan_Calibration_Flow] k_type=0
7266 10:55:39.521514
7267 10:55:39.521934 ==CLK 0==
7268 10:55:39.524844 Final CLK duty delay cell = 0
7269 10:55:39.527850 [0] MAX Duty = 5125%(X100), DQS PI = 20
7270 10:55:39.531371 [0] MIN Duty = 4907%(X100), DQS PI = 6
7271 10:55:39.531817 [0] AVG Duty = 5016%(X100)
7272 10:55:39.534822
7273 10:55:39.538061 CH0 CLK Duty spec in!! Max-Min= 218%
7274 10:55:39.541471 [DutyScan_Calibration_Flow] ====Done====
7275 10:55:39.541895
7276 10:55:39.544302 [DutyScan_Calibration_Flow] k_type=1
7277 10:55:39.560434
7278 10:55:39.561225 ==DQS 0 ==
7279 10:55:39.563730 Final DQS duty delay cell = -4
7280 10:55:39.567340 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7281 10:55:39.570585 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7282 10:55:39.573432 [-4] AVG Duty = 4922%(X100)
7283 10:55:39.573897
7284 10:55:39.574282 ==DQS 1 ==
7285 10:55:39.576933 Final DQS duty delay cell = 0
7286 10:55:39.580632 [0] MAX Duty = 5156%(X100), DQS PI = 0
7287 10:55:39.583432 [0] MIN Duty = 5031%(X100), DQS PI = 20
7288 10:55:39.587195 [0] AVG Duty = 5093%(X100)
7289 10:55:39.587657
7290 10:55:39.590140 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7291 10:55:39.590618
7292 10:55:39.593734 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7293 10:55:39.597012 [DutyScan_Calibration_Flow] ====Done====
7294 10:55:39.597422
7295 10:55:39.600077 [DutyScan_Calibration_Flow] k_type=3
7296 10:55:39.618086
7297 10:55:39.618565 ==DQM 0 ==
7298 10:55:39.621331 Final DQM duty delay cell = 0
7299 10:55:39.624591 [0] MAX Duty = 5124%(X100), DQS PI = 22
7300 10:55:39.628130 [0] MIN Duty = 4907%(X100), DQS PI = 10
7301 10:55:39.631211 [0] AVG Duty = 5015%(X100)
7302 10:55:39.631677
7303 10:55:39.632007 ==DQM 1 ==
7304 10:55:39.634811 Final DQM duty delay cell = 0
7305 10:55:39.638070 [0] MAX Duty = 5031%(X100), DQS PI = 4
7306 10:55:39.641022 [0] MIN Duty = 4813%(X100), DQS PI = 18
7307 10:55:39.644215 [0] AVG Duty = 4922%(X100)
7308 10:55:39.644714
7309 10:55:39.647880 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7310 10:55:39.648300
7311 10:55:39.650689 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7312 10:55:39.654028 [DutyScan_Calibration_Flow] ====Done====
7313 10:55:39.654489
7314 10:55:39.657382 [DutyScan_Calibration_Flow] k_type=2
7315 10:55:39.674092
7316 10:55:39.674510 ==DQ 0 ==
7317 10:55:39.677867 Final DQ duty delay cell = -4
7318 10:55:39.681129 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7319 10:55:39.684032 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7320 10:55:39.687471 [-4] AVG Duty = 4953%(X100)
7321 10:55:39.688030
7322 10:55:39.688428 ==DQ 1 ==
7323 10:55:39.690845 Final DQ duty delay cell = 0
7324 10:55:39.693809 [0] MAX Duty = 5125%(X100), DQS PI = 4
7325 10:55:39.697570 [0] MIN Duty = 5000%(X100), DQS PI = 36
7326 10:55:39.701265 [0] AVG Duty = 5062%(X100)
7327 10:55:39.701677
7328 10:55:39.703839 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7329 10:55:39.704256
7330 10:55:39.707745 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7331 10:55:39.711366 [DutyScan_Calibration_Flow] ====Done====
7332 10:55:39.711867 ==
7333 10:55:39.713950 Dram Type= 6, Freq= 0, CH_1, rank 0
7334 10:55:39.717376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7335 10:55:39.717815 ==
7336 10:55:39.720599 [Duty_Offset_Calibration]
7337 10:55:39.721015 B0:-1 B1:1 CA:1
7338 10:55:39.721345
7339 10:55:39.724049 [DutyScan_Calibration_Flow] k_type=0
7340 10:55:39.734892
7341 10:55:39.735306 ==CLK 0==
7342 10:55:39.738637 Final CLK duty delay cell = 0
7343 10:55:39.741658 [0] MAX Duty = 5187%(X100), DQS PI = 24
7344 10:55:39.744938 [0] MIN Duty = 5000%(X100), DQS PI = 0
7345 10:55:39.747992 [0] AVG Duty = 5093%(X100)
7346 10:55:39.748425
7347 10:55:39.751197 CH1 CLK Duty spec in!! Max-Min= 187%
7348 10:55:39.755174 [DutyScan_Calibration_Flow] ====Done====
7349 10:55:39.755585
7350 10:55:39.757671 [DutyScan_Calibration_Flow] k_type=1
7351 10:55:39.774387
7352 10:55:39.774899 ==DQS 0 ==
7353 10:55:39.778131 Final DQS duty delay cell = 0
7354 10:55:39.781031 [0] MAX Duty = 5124%(X100), DQS PI = 18
7355 10:55:39.784398 [0] MIN Duty = 4938%(X100), DQS PI = 10
7356 10:55:39.787518 [0] AVG Duty = 5031%(X100)
7357 10:55:39.788036
7358 10:55:39.788370 ==DQS 1 ==
7359 10:55:39.791210 Final DQS duty delay cell = 0
7360 10:55:39.794660 [0] MAX Duty = 5093%(X100), DQS PI = 26
7361 10:55:39.797506 [0] MIN Duty = 4969%(X100), DQS PI = 56
7362 10:55:39.800620 [0] AVG Duty = 5031%(X100)
7363 10:55:39.801039
7364 10:55:39.803972 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7365 10:55:39.804491
7366 10:55:39.807258 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7367 10:55:39.810937 [DutyScan_Calibration_Flow] ====Done====
7368 10:55:39.811361
7369 10:55:39.813841 [DutyScan_Calibration_Flow] k_type=3
7370 10:55:39.831610
7371 10:55:39.832024 ==DQM 0 ==
7372 10:55:39.835293 Final DQM duty delay cell = 0
7373 10:55:39.838607 [0] MAX Duty = 5218%(X100), DQS PI = 18
7374 10:55:39.841382 [0] MIN Duty = 5031%(X100), DQS PI = 8
7375 10:55:39.845455 [0] AVG Duty = 5124%(X100)
7376 10:55:39.845976
7377 10:55:39.846313 ==DQM 1 ==
7378 10:55:39.848420 Final DQM duty delay cell = 0
7379 10:55:39.851260 [0] MAX Duty = 5156%(X100), DQS PI = 0
7380 10:55:39.854825 [0] MIN Duty = 4969%(X100), DQS PI = 32
7381 10:55:39.857833 [0] AVG Duty = 5062%(X100)
7382 10:55:39.858256
7383 10:55:39.861324 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7384 10:55:39.861767
7385 10:55:39.864629 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7386 10:55:39.868170 [DutyScan_Calibration_Flow] ====Done====
7387 10:55:39.868632
7388 10:55:39.871117 [DutyScan_Calibration_Flow] k_type=2
7389 10:55:39.888594
7390 10:55:39.889016 ==DQ 0 ==
7391 10:55:39.891729 Final DQ duty delay cell = 0
7392 10:55:39.894972 [0] MAX Duty = 5156%(X100), DQS PI = 28
7393 10:55:39.898032 [0] MIN Duty = 4906%(X100), DQS PI = 8
7394 10:55:39.898448 [0] AVG Duty = 5031%(X100)
7395 10:55:39.901450
7396 10:55:39.901890 ==DQ 1 ==
7397 10:55:39.905081 Final DQ duty delay cell = 0
7398 10:55:39.907924 [0] MAX Duty = 5156%(X100), DQS PI = 8
7399 10:55:39.911322 [0] MIN Duty = 4969%(X100), DQS PI = 56
7400 10:55:39.911743 [0] AVG Duty = 5062%(X100)
7401 10:55:39.912076
7402 10:55:39.917932 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7403 10:55:39.918350
7404 10:55:39.921593 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7405 10:55:39.924884 [DutyScan_Calibration_Flow] ====Done====
7406 10:55:39.927664 nWR fixed to 30
7407 10:55:39.928090 [ModeRegInit_LP4] CH0 RK0
7408 10:55:39.931349 [ModeRegInit_LP4] CH0 RK1
7409 10:55:39.934503 [ModeRegInit_LP4] CH1 RK0
7410 10:55:39.938009 [ModeRegInit_LP4] CH1 RK1
7411 10:55:39.938542 match AC timing 5
7412 10:55:39.944311 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7413 10:55:39.947893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7414 10:55:39.951249 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7415 10:55:39.958085 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7416 10:55:39.960665 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7417 10:55:39.961095 [MiockJmeterHQA]
7418 10:55:39.961430
7419 10:55:39.964089 [DramcMiockJmeter] u1RxGatingPI = 0
7420 10:55:39.967732 0 : 4252, 4027
7421 10:55:39.968282 4 : 4255, 4030
7422 10:55:39.970835 8 : 4252, 4027
7423 10:55:39.971433 12 : 4255, 4029
7424 10:55:39.971818 16 : 4253, 4026
7425 10:55:39.974373 20 : 4252, 4027
7426 10:55:39.974870 24 : 4255, 4029
7427 10:55:39.977253 28 : 4363, 4137
7428 10:55:39.977740 32 : 4252, 4027
7429 10:55:39.980626 36 : 4253, 4027
7430 10:55:39.981056 40 : 4252, 4027
7431 10:55:39.983916 44 : 4255, 4029
7432 10:55:39.984347 48 : 4252, 4027
7433 10:55:39.984753 52 : 4363, 4137
7434 10:55:39.987239 56 : 4363, 4137
7435 10:55:39.987803 60 : 4250, 4027
7436 10:55:39.990767 64 : 4250, 4027
7437 10:55:39.991355 68 : 4250, 4027
7438 10:55:39.994046 72 : 4250, 4027
7439 10:55:39.994516 76 : 4252, 4029
7440 10:55:39.996879 80 : 4360, 4138
7441 10:55:39.997357 84 : 4249, 4027
7442 10:55:39.997825 88 : 4250, 4027
7443 10:55:40.000950 92 : 4250, 447
7444 10:55:40.001410 96 : 4363, 0
7445 10:55:40.003880 100 : 4249, 0
7446 10:55:40.004492 104 : 4252, 0
7447 10:55:40.005005 108 : 4250, 0
7448 10:55:40.007206 112 : 4252, 0
7449 10:55:40.007637 116 : 4252, 0
7450 10:55:40.010311 120 : 4250, 0
7451 10:55:40.010742 124 : 4252, 0
7452 10:55:40.011088 128 : 4360, 0
7453 10:55:40.013553 132 : 4360, 0
7454 10:55:40.013987 136 : 4363, 0
7455 10:55:40.017183 140 : 4250, 0
7456 10:55:40.017702 144 : 4249, 0
7457 10:55:40.018047 148 : 4250, 0
7458 10:55:40.020097 152 : 4250, 0
7459 10:55:40.020551 156 : 4252, 0
7460 10:55:40.020903 160 : 4250, 0
7461 10:55:40.023739 164 : 4252, 0
7462 10:55:40.024168 168 : 4252, 0
7463 10:55:40.026899 172 : 4250, 0
7464 10:55:40.027343 176 : 4253, 0
7465 10:55:40.027688 180 : 4365, 0
7466 10:55:40.029998 184 : 4360, 0
7467 10:55:40.030427 188 : 4363, 0
7468 10:55:40.033607 192 : 4253, 0
7469 10:55:40.034041 196 : 4249, 0
7470 10:55:40.034384 200 : 4250, 0
7471 10:55:40.036663 204 : 4250, 0
7472 10:55:40.037093 208 : 4249, 0
7473 10:55:40.040040 212 : 4250, 0
7474 10:55:40.040468 216 : 4253, 0
7475 10:55:40.040838 220 : 4252, 0
7476 10:55:40.043627 224 : 4250, 199
7477 10:55:40.044057 228 : 4249, 3672
7478 10:55:40.046926 232 : 4249, 4027
7479 10:55:40.047358 236 : 4250, 4026
7480 10:55:40.049778 240 : 4250, 4027
7481 10:55:40.050208 244 : 4360, 4138
7482 10:55:40.053362 248 : 4250, 4027
7483 10:55:40.053793 252 : 4250, 4027
7484 10:55:40.056725 256 : 4361, 4137
7485 10:55:40.057255 260 : 4250, 4027
7486 10:55:40.060175 264 : 4249, 4027
7487 10:55:40.060749 268 : 4363, 4140
7488 10:55:40.061102 272 : 4250, 4027
7489 10:55:40.063303 276 : 4250, 4027
7490 10:55:40.063766 280 : 4249, 4027
7491 10:55:40.066830 284 : 4252, 4029
7492 10:55:40.067375 288 : 4250, 4027
7493 10:55:40.070032 292 : 4250, 4027
7494 10:55:40.070575 296 : 4360, 4138
7495 10:55:40.073231 300 : 4250, 4027
7496 10:55:40.073663 304 : 4250, 4027
7497 10:55:40.076290 308 : 4361, 4137
7498 10:55:40.076757 312 : 4250, 4027
7499 10:55:40.079892 316 : 4250, 4027
7500 10:55:40.080325 320 : 4363, 4140
7501 10:55:40.083841 324 : 4250, 4027
7502 10:55:40.084272 328 : 4250, 4027
7503 10:55:40.084642 332 : 4250, 4027
7504 10:55:40.086700 336 : 4252, 3554
7505 10:55:40.087130 340 : 4250, 1694
7506 10:55:40.087476
7507 10:55:40.089738 MIOCK jitter meter ch=0
7508 10:55:40.090158
7509 10:55:40.093161 1T = (340-92) = 248 dly cells
7510 10:55:40.099862 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7511 10:55:40.100292 ==
7512 10:55:40.102924 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 10:55:40.106398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 10:55:40.106824 ==
7515 10:55:40.112758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 10:55:40.116600 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 10:55:40.120056 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 10:55:40.126250 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 10:55:40.135134 [CA 0] Center 43 (12~74) winsize 63
7520 10:55:40.138978 [CA 1] Center 42 (12~73) winsize 62
7521 10:55:40.142471 [CA 2] Center 38 (9~68) winsize 60
7522 10:55:40.145422 [CA 3] Center 38 (8~68) winsize 61
7523 10:55:40.148681 [CA 4] Center 36 (7~66) winsize 60
7524 10:55:40.152250 [CA 5] Center 35 (6~65) winsize 60
7525 10:55:40.152891
7526 10:55:40.155418 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 10:55:40.155992
7528 10:55:40.161434 [CATrainingPosCal] consider 1 rank data
7529 10:55:40.161956 u2DelayCellTimex100 = 262/100 ps
7530 10:55:40.168899 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7531 10:55:40.171281 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7532 10:55:40.174733 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7533 10:55:40.177879 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7534 10:55:40.181455 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7535 10:55:40.184835 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7536 10:55:40.185261
7537 10:55:40.187973 CA PerBit enable=1, Macro0, CA PI delay=35
7538 10:55:40.188401
7539 10:55:40.191293 [CBTSetCACLKResult] CA Dly = 35
7540 10:55:40.194881 CS Dly: 11 (0~42)
7541 10:55:40.197910 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 10:55:40.201946 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 10:55:40.202375 ==
7544 10:55:40.204647 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 10:55:40.211366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 10:55:40.211795 ==
7547 10:55:40.214798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 10:55:40.221343 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 10:55:40.224202 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 10:55:40.231001 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 10:55:40.239019 [CA 0] Center 43 (13~74) winsize 62
7552 10:55:40.242017 [CA 1] Center 44 (14~74) winsize 61
7553 10:55:40.245356 [CA 2] Center 38 (9~68) winsize 60
7554 10:55:40.248931 [CA 3] Center 38 (9~68) winsize 60
7555 10:55:40.252202 [CA 4] Center 36 (7~66) winsize 60
7556 10:55:40.255629 [CA 5] Center 36 (7~66) winsize 60
7557 10:55:40.256154
7558 10:55:40.259042 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 10:55:40.259604
7560 10:55:40.261979 [CATrainingPosCal] consider 2 rank data
7561 10:55:40.264977 u2DelayCellTimex100 = 262/100 ps
7562 10:55:40.272248 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7563 10:55:40.275253 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7564 10:55:40.278400 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7565 10:55:40.282147 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7566 10:55:40.284803 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7567 10:55:40.288383 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7568 10:55:40.289027
7569 10:55:40.291942 CA PerBit enable=1, Macro0, CA PI delay=36
7570 10:55:40.292418
7571 10:55:40.295299 [CBTSetCACLKResult] CA Dly = 36
7572 10:55:40.297929 CS Dly: 12 (0~44)
7573 10:55:40.301836 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 10:55:40.304891 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 10:55:40.305322
7576 10:55:40.307895 ----->DramcWriteLeveling(PI) begin...
7577 10:55:40.308329 ==
7578 10:55:40.311540 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 10:55:40.317815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 10:55:40.318300 ==
7581 10:55:40.321278 Write leveling (Byte 0): 35 => 35
7582 10:55:40.324579 Write leveling (Byte 1): 29 => 29
7583 10:55:40.325009 DramcWriteLeveling(PI) end<-----
7584 10:55:40.327666
7585 10:55:40.328090 ==
7586 10:55:40.331326 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 10:55:40.334754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 10:55:40.335188 ==
7589 10:55:40.337787 [Gating] SW mode calibration
7590 10:55:40.344288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 10:55:40.348107 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 10:55:40.354223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 10:55:40.357468 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 10:55:40.361162 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 10:55:40.368141 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7596 10:55:40.370755 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7597 10:55:40.374736 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7598 10:55:40.381073 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
7599 10:55:40.384500 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 10:55:40.387625 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 10:55:40.394265 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 10:55:40.397334 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7603 10:55:40.400483 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7604 10:55:40.408217 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7605 10:55:40.410829 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7606 10:55:40.414078 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7607 10:55:40.421206 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 10:55:40.423715 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 10:55:40.426923 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 10:55:40.434007 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 10:55:40.436816 1 6 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
7612 10:55:40.440210 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7613 10:55:40.447037 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7614 10:55:40.450191 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7615 10:55:40.453834 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 10:55:40.460178 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 10:55:40.463184 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 10:55:40.466341 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7619 10:55:40.473151 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 10:55:40.476344 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7621 10:55:40.480064 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 10:55:40.485944 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:55:40.489450 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:55:40.492840 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:55:40.499113 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:55:40.502724 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 10:55:40.506671 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:55:40.512793 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 10:55:40.515516 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:55:40.518983 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:55:40.525681 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:55:40.529276 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:55:40.532127 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 10:55:40.539149 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 10:55:40.542124 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 10:55:40.545541 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 10:55:40.548561 Total UI for P1: 0, mck2ui 16
7638 10:55:40.552124 best dqsien dly found for B0: ( 1, 9, 12)
7639 10:55:40.558729 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 10:55:40.562188 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 10:55:40.565089 Total UI for P1: 0, mck2ui 16
7642 10:55:40.568685 best dqsien dly found for B1: ( 1, 9, 18)
7643 10:55:40.572077 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7644 10:55:40.575377 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7645 10:55:40.575911
7646 10:55:40.578537 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7647 10:55:40.584932 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7648 10:55:40.585365 [Gating] SW calibration Done
7649 10:55:40.585706 ==
7650 10:55:40.588507 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 10:55:40.595222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 10:55:40.595755 ==
7653 10:55:40.596107 RX Vref Scan: 0
7654 10:55:40.596431
7655 10:55:40.598026 RX Vref 0 -> 0, step: 1
7656 10:55:40.598453
7657 10:55:40.601639 RX Delay 0 -> 252, step: 8
7658 10:55:40.604920 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7659 10:55:40.607966 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7660 10:55:40.611410 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7661 10:55:40.617833 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7662 10:55:40.621297 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7663 10:55:40.624797 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
7664 10:55:40.627729 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7665 10:55:40.630756 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7666 10:55:40.637568 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7667 10:55:40.641146 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7668 10:55:40.644165 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7669 10:55:40.647794 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7670 10:55:40.654582 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7671 10:55:40.657524 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7672 10:55:40.660769 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7673 10:55:40.663897 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7674 10:55:40.664469 ==
7675 10:55:40.667423 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 10:55:40.673852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 10:55:40.674291 ==
7678 10:55:40.674740 DQS Delay:
7679 10:55:40.675217 DQS0 = 0, DQS1 = 0
7680 10:55:40.677009 DQM Delay:
7681 10:55:40.677461 DQM0 = 134, DQM1 = 126
7682 10:55:40.680120 DQ Delay:
7683 10:55:40.683794 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7684 10:55:40.687252 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =143
7685 10:55:40.690357 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7686 10:55:40.693891 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7687 10:55:40.694355
7688 10:55:40.694696
7689 10:55:40.695049 ==
7690 10:55:40.697185 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 10:55:40.700328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 10:55:40.703481 ==
7693 10:55:40.703934
7694 10:55:40.704274
7695 10:55:40.704705 TX Vref Scan disable
7696 10:55:40.707018 == TX Byte 0 ==
7697 10:55:40.710432 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7698 10:55:40.713582 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7699 10:55:40.716692 == TX Byte 1 ==
7700 10:55:40.720202 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7701 10:55:40.723203 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7702 10:55:40.726481 ==
7703 10:55:40.730115 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 10:55:40.733315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 10:55:40.733749 ==
7706 10:55:40.745662
7707 10:55:40.748771 TX Vref early break, caculate TX vref
7708 10:55:40.751850 TX Vref=16, minBit 4, minWin=22, winSum=369
7709 10:55:40.755339 TX Vref=18, minBit 1, minWin=23, winSum=383
7710 10:55:40.758667 TX Vref=20, minBit 1, minWin=23, winSum=393
7711 10:55:40.761981 TX Vref=22, minBit 1, minWin=24, winSum=401
7712 10:55:40.765540 TX Vref=24, minBit 0, minWin=25, winSum=416
7713 10:55:40.771655 TX Vref=26, minBit 4, minWin=25, winSum=421
7714 10:55:40.775670 TX Vref=28, minBit 0, minWin=25, winSum=422
7715 10:55:40.779125 TX Vref=30, minBit 7, minWin=24, winSum=416
7716 10:55:40.781916 TX Vref=32, minBit 4, minWin=23, winSum=401
7717 10:55:40.784917 TX Vref=34, minBit 0, minWin=23, winSum=392
7718 10:55:40.791518 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
7719 10:55:40.791722
7720 10:55:40.795076 Final TX Range 0 Vref 28
7721 10:55:40.795296
7722 10:55:40.795420 ==
7723 10:55:40.798277 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 10:55:40.802202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 10:55:40.802461 ==
7726 10:55:40.802618
7727 10:55:40.802755
7728 10:55:40.805496 TX Vref Scan disable
7729 10:55:40.811836 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7730 10:55:40.812171 == TX Byte 0 ==
7731 10:55:40.814680 u2DelayCellOfst[0]=14 cells (4 PI)
7732 10:55:40.818330 u2DelayCellOfst[1]=18 cells (5 PI)
7733 10:55:40.821468 u2DelayCellOfst[2]=14 cells (4 PI)
7734 10:55:40.825204 u2DelayCellOfst[3]=14 cells (4 PI)
7735 10:55:40.828896 u2DelayCellOfst[4]=14 cells (4 PI)
7736 10:55:40.832225 u2DelayCellOfst[5]=0 cells (0 PI)
7737 10:55:40.834937 u2DelayCellOfst[6]=18 cells (5 PI)
7738 10:55:40.838635 u2DelayCellOfst[7]=22 cells (6 PI)
7739 10:55:40.841507 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7740 10:55:40.844866 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7741 10:55:40.848589 == TX Byte 1 ==
7742 10:55:40.851317 u2DelayCellOfst[8]=0 cells (0 PI)
7743 10:55:40.855628 u2DelayCellOfst[9]=3 cells (1 PI)
7744 10:55:40.856190 u2DelayCellOfst[10]=7 cells (2 PI)
7745 10:55:40.857941 u2DelayCellOfst[11]=3 cells (1 PI)
7746 10:55:40.861529 u2DelayCellOfst[12]=11 cells (3 PI)
7747 10:55:40.864858 u2DelayCellOfst[13]=11 cells (3 PI)
7748 10:55:40.868235 u2DelayCellOfst[14]=14 cells (4 PI)
7749 10:55:40.871692 u2DelayCellOfst[15]=11 cells (3 PI)
7750 10:55:40.878473 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7751 10:55:40.881325 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7752 10:55:40.881798 DramC Write-DBI on
7753 10:55:40.882171 ==
7754 10:55:40.884365 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 10:55:40.891184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 10:55:40.891775 ==
7757 10:55:40.892159
7758 10:55:40.892512
7759 10:55:40.892884 TX Vref Scan disable
7760 10:55:40.895733 == TX Byte 0 ==
7761 10:55:40.898916 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7762 10:55:40.902518 == TX Byte 1 ==
7763 10:55:40.905162 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7764 10:55:40.908320 DramC Write-DBI off
7765 10:55:40.908808
7766 10:55:40.909182 [DATLAT]
7767 10:55:40.909531 Freq=1600, CH0 RK0
7768 10:55:40.909869
7769 10:55:40.912168 DATLAT Default: 0xf
7770 10:55:40.915056 0, 0xFFFF, sum = 0
7771 10:55:40.915540 1, 0xFFFF, sum = 0
7772 10:55:40.918721 2, 0xFFFF, sum = 0
7773 10:55:40.919305 3, 0xFFFF, sum = 0
7774 10:55:40.921906 4, 0xFFFF, sum = 0
7775 10:55:40.922384 5, 0xFFFF, sum = 0
7776 10:55:40.925220 6, 0xFFFF, sum = 0
7777 10:55:40.925768 7, 0xFFFF, sum = 0
7778 10:55:40.928302 8, 0xFFFF, sum = 0
7779 10:55:40.928814 9, 0xFFFF, sum = 0
7780 10:55:40.931561 10, 0xFFFF, sum = 0
7781 10:55:40.932148 11, 0xFFFF, sum = 0
7782 10:55:40.936120 12, 0xFFFF, sum = 0
7783 10:55:40.936753 13, 0xFFFF, sum = 0
7784 10:55:40.939001 14, 0x0, sum = 1
7785 10:55:40.939584 15, 0x0, sum = 2
7786 10:55:40.942032 16, 0x0, sum = 3
7787 10:55:40.942619 17, 0x0, sum = 4
7788 10:55:40.945357 best_step = 15
7789 10:55:40.945923
7790 10:55:40.946296 ==
7791 10:55:40.948556 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 10:55:40.951391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 10:55:40.951864 ==
7794 10:55:40.954645 RX Vref Scan: 1
7795 10:55:40.955134
7796 10:55:40.955512 Set Vref Range= 24 -> 127
7797 10:55:40.955866
7798 10:55:40.958381 RX Vref 24 -> 127, step: 1
7799 10:55:40.958970
7800 10:55:40.961615 RX Delay 11 -> 252, step: 4
7801 10:55:40.962109
7802 10:55:40.964985 Set Vref, RX VrefLevel [Byte0]: 24
7803 10:55:40.968291 [Byte1]: 24
7804 10:55:40.968888
7805 10:55:40.971475 Set Vref, RX VrefLevel [Byte0]: 25
7806 10:55:40.974569 [Byte1]: 25
7807 10:55:40.978266
7808 10:55:40.978848 Set Vref, RX VrefLevel [Byte0]: 26
7809 10:55:40.981711 [Byte1]: 26
7810 10:55:40.985568
7811 10:55:40.986047 Set Vref, RX VrefLevel [Byte0]: 27
7812 10:55:40.988907 [Byte1]: 27
7813 10:55:40.993199
7814 10:55:40.993670 Set Vref, RX VrefLevel [Byte0]: 28
7815 10:55:40.996625 [Byte1]: 28
7816 10:55:41.000846
7817 10:55:41.001434 Set Vref, RX VrefLevel [Byte0]: 29
7818 10:55:41.004014 [Byte1]: 29
7819 10:55:41.009006
7820 10:55:41.012001 Set Vref, RX VrefLevel [Byte0]: 30
7821 10:55:41.012478 [Byte1]: 30
7822 10:55:41.016465
7823 10:55:41.017105 Set Vref, RX VrefLevel [Byte0]: 31
7824 10:55:41.019564 [Byte1]: 31
7825 10:55:41.024629
7826 10:55:41.025200 Set Vref, RX VrefLevel [Byte0]: 32
7827 10:55:41.027113 [Byte1]: 32
7828 10:55:41.031373
7829 10:55:41.031949 Set Vref, RX VrefLevel [Byte0]: 33
7830 10:55:41.034888 [Byte1]: 33
7831 10:55:41.039412
7832 10:55:41.039983 Set Vref, RX VrefLevel [Byte0]: 34
7833 10:55:41.042641 [Byte1]: 34
7834 10:55:41.046833
7835 10:55:41.047407 Set Vref, RX VrefLevel [Byte0]: 35
7836 10:55:41.050058 [Byte1]: 35
7837 10:55:41.054755
7838 10:55:41.055332 Set Vref, RX VrefLevel [Byte0]: 36
7839 10:55:41.057490 [Byte1]: 36
7840 10:55:41.062210
7841 10:55:41.062794 Set Vref, RX VrefLevel [Byte0]: 37
7842 10:55:41.065455 [Byte1]: 37
7843 10:55:41.069764
7844 10:55:41.070232 Set Vref, RX VrefLevel [Byte0]: 38
7845 10:55:41.072704 [Byte1]: 38
7846 10:55:41.077533
7847 10:55:41.078097 Set Vref, RX VrefLevel [Byte0]: 39
7848 10:55:41.080322 [Byte1]: 39
7849 10:55:41.084733
7850 10:55:41.085323 Set Vref, RX VrefLevel [Byte0]: 40
7851 10:55:41.088013 [Byte1]: 40
7852 10:55:41.092091
7853 10:55:41.092718 Set Vref, RX VrefLevel [Byte0]: 41
7854 10:55:41.095836 [Byte1]: 41
7855 10:55:41.100168
7856 10:55:41.100784 Set Vref, RX VrefLevel [Byte0]: 42
7857 10:55:41.103292 [Byte1]: 42
7858 10:55:41.107567
7859 10:55:41.108122 Set Vref, RX VrefLevel [Byte0]: 43
7860 10:55:41.111468 [Byte1]: 43
7861 10:55:41.115385
7862 10:55:41.115870 Set Vref, RX VrefLevel [Byte0]: 44
7863 10:55:41.118139 [Byte1]: 44
7864 10:55:41.122537
7865 10:55:41.123007 Set Vref, RX VrefLevel [Byte0]: 45
7866 10:55:41.125870 [Byte1]: 45
7867 10:55:41.130410
7868 10:55:41.130986 Set Vref, RX VrefLevel [Byte0]: 46
7869 10:55:41.133994 [Byte1]: 46
7870 10:55:41.138424
7871 10:55:41.138992 Set Vref, RX VrefLevel [Byte0]: 47
7872 10:55:41.141433 [Byte1]: 47
7873 10:55:41.145654
7874 10:55:41.146216 Set Vref, RX VrefLevel [Byte0]: 48
7875 10:55:41.149829 [Byte1]: 48
7876 10:55:41.153600
7877 10:55:41.154169 Set Vref, RX VrefLevel [Byte0]: 49
7878 10:55:41.156490 [Byte1]: 49
7879 10:55:41.161373
7880 10:55:41.161958 Set Vref, RX VrefLevel [Byte0]: 50
7881 10:55:41.164173 [Byte1]: 50
7882 10:55:41.168940
7883 10:55:41.169665 Set Vref, RX VrefLevel [Byte0]: 51
7884 10:55:41.172258 [Byte1]: 51
7885 10:55:41.176129
7886 10:55:41.176635 Set Vref, RX VrefLevel [Byte0]: 52
7887 10:55:41.179047 [Byte1]: 52
7888 10:55:41.183628
7889 10:55:41.184190 Set Vref, RX VrefLevel [Byte0]: 53
7890 10:55:41.187115 [Byte1]: 53
7891 10:55:41.191535
7892 10:55:41.192095 Set Vref, RX VrefLevel [Byte0]: 54
7893 10:55:41.194943 [Byte1]: 54
7894 10:55:41.199154
7895 10:55:41.199730 Set Vref, RX VrefLevel [Byte0]: 55
7896 10:55:41.202002 [Byte1]: 55
7897 10:55:41.206645
7898 10:55:41.207110 Set Vref, RX VrefLevel [Byte0]: 56
7899 10:55:41.209845 [Byte1]: 56
7900 10:55:41.214509
7901 10:55:41.215072 Set Vref, RX VrefLevel [Byte0]: 57
7902 10:55:41.217352 [Byte1]: 57
7903 10:55:41.221883
7904 10:55:41.222367 Set Vref, RX VrefLevel [Byte0]: 58
7905 10:55:41.224982 [Byte1]: 58
7906 10:55:41.229145
7907 10:55:41.229568 Set Vref, RX VrefLevel [Byte0]: 59
7908 10:55:41.232964 [Byte1]: 59
7909 10:55:41.236908
7910 10:55:41.237484 Set Vref, RX VrefLevel [Byte0]: 60
7911 10:55:41.240302 [Byte1]: 60
7912 10:55:41.244668
7913 10:55:41.245240 Set Vref, RX VrefLevel [Byte0]: 61
7914 10:55:41.248146 [Byte1]: 61
7915 10:55:41.252138
7916 10:55:41.252752 Set Vref, RX VrefLevel [Byte0]: 62
7917 10:55:41.255164 [Byte1]: 62
7918 10:55:41.260672
7919 10:55:41.261245 Set Vref, RX VrefLevel [Byte0]: 63
7920 10:55:41.262751 [Byte1]: 63
7921 10:55:41.267469
7922 10:55:41.268064 Set Vref, RX VrefLevel [Byte0]: 64
7923 10:55:41.270677 [Byte1]: 64
7924 10:55:41.275646
7925 10:55:41.276221 Set Vref, RX VrefLevel [Byte0]: 65
7926 10:55:41.278028 [Byte1]: 65
7927 10:55:41.282618
7928 10:55:41.283092 Set Vref, RX VrefLevel [Byte0]: 66
7929 10:55:41.286054 [Byte1]: 66
7930 10:55:41.290108
7931 10:55:41.290580 Set Vref, RX VrefLevel [Byte0]: 67
7932 10:55:41.293714 [Byte1]: 67
7933 10:55:41.298160
7934 10:55:41.298728 Set Vref, RX VrefLevel [Byte0]: 68
7935 10:55:41.301441 [Byte1]: 68
7936 10:55:41.305719
7937 10:55:41.306191 Set Vref, RX VrefLevel [Byte0]: 69
7938 10:55:41.309010 [Byte1]: 69
7939 10:55:41.313028
7940 10:55:41.313476 Set Vref, RX VrefLevel [Byte0]: 70
7941 10:55:41.316158 [Byte1]: 70
7942 10:55:41.320463
7943 10:55:41.320984 Set Vref, RX VrefLevel [Byte0]: 71
7944 10:55:41.324130 [Byte1]: 71
7945 10:55:41.328185
7946 10:55:41.328695 Set Vref, RX VrefLevel [Byte0]: 72
7947 10:55:41.331678 [Byte1]: 72
7948 10:55:41.335795
7949 10:55:41.336322 Set Vref, RX VrefLevel [Byte0]: 73
7950 10:55:41.339494 [Byte1]: 73
7951 10:55:41.343863
7952 10:55:41.344357 Set Vref, RX VrefLevel [Byte0]: 74
7953 10:55:41.346824 [Byte1]: 74
7954 10:55:41.351316
7955 10:55:41.351835 Set Vref, RX VrefLevel [Byte0]: 75
7956 10:55:41.354876 [Byte1]: 75
7957 10:55:41.358766
7958 10:55:41.359285 Set Vref, RX VrefLevel [Byte0]: 76
7959 10:55:41.362146 [Byte1]: 76
7960 10:55:41.366632
7961 10:55:41.367160 Set Vref, RX VrefLevel [Byte0]: 77
7962 10:55:41.369440 [Byte1]: 77
7963 10:55:41.375032
7964 10:55:41.375559 Final RX Vref Byte 0 = 67 to rank0
7965 10:55:41.377004 Final RX Vref Byte 1 = 56 to rank0
7966 10:55:41.380681 Final RX Vref Byte 0 = 67 to rank1
7967 10:55:41.384157 Final RX Vref Byte 1 = 56 to rank1==
7968 10:55:41.387126 Dram Type= 6, Freq= 0, CH_0, rank 0
7969 10:55:41.394012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 10:55:41.394446 ==
7971 10:55:41.394792 DQS Delay:
7972 10:55:41.397266 DQS0 = 0, DQS1 = 0
7973 10:55:41.397693 DQM Delay:
7974 10:55:41.398036 DQM0 = 133, DQM1 = 123
7975 10:55:41.400026 DQ Delay:
7976 10:55:41.403370 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
7977 10:55:41.406982 DQ4 =132, DQ5 =120, DQ6 =142, DQ7 =142
7978 10:55:41.409908 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
7979 10:55:41.413369 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =130
7980 10:55:41.413799
7981 10:55:41.414144
7982 10:55:41.414497
7983 10:55:41.416431 [DramC_TX_OE_Calibration] TA2
7984 10:55:41.419743 Original DQ_B0 (3 6) =30, OEN = 27
7985 10:55:41.423383 Original DQ_B1 (3 6) =30, OEN = 27
7986 10:55:41.426951 24, 0x0, End_B0=24 End_B1=24
7987 10:55:41.430014 25, 0x0, End_B0=25 End_B1=25
7988 10:55:41.430449 26, 0x0, End_B0=26 End_B1=26
7989 10:55:41.433403 27, 0x0, End_B0=27 End_B1=27
7990 10:55:41.436764 28, 0x0, End_B0=28 End_B1=28
7991 10:55:41.439707 29, 0x0, End_B0=29 End_B1=29
7992 10:55:41.440139 30, 0x0, End_B0=30 End_B1=30
7993 10:55:41.443356 31, 0x4141, End_B0=30 End_B1=30
7994 10:55:41.446224 Byte0 end_step=30 best_step=27
7995 10:55:41.449720 Byte1 end_step=30 best_step=27
7996 10:55:41.452668 Byte0 TX OE(2T, 0.5T) = (3, 3)
7997 10:55:41.456135 Byte1 TX OE(2T, 0.5T) = (3, 3)
7998 10:55:41.456590
7999 10:55:41.456966
8000 10:55:41.462913 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8001 10:55:41.466101 CH0 RK0: MR19=303, MR18=2314
8002 10:55:41.472585 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8003 10:55:41.473020
8004 10:55:41.476137 ----->DramcWriteLeveling(PI) begin...
8005 10:55:41.476624 ==
8006 10:55:41.479206 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 10:55:41.482671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 10:55:41.483117 ==
8009 10:55:41.485842 Write leveling (Byte 0): 34 => 34
8010 10:55:41.489346 Write leveling (Byte 1): 29 => 29
8011 10:55:41.492661 DramcWriteLeveling(PI) end<-----
8012 10:55:41.493091
8013 10:55:41.493465 ==
8014 10:55:41.495666 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 10:55:41.499082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 10:55:41.502467 ==
8017 10:55:41.503074 [Gating] SW mode calibration
8018 10:55:41.512500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8019 10:55:41.515506 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8020 10:55:41.519316 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 10:55:41.525606 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 10:55:41.529024 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 10:55:41.532303 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8024 10:55:41.538706 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8025 10:55:41.542286 1 4 20 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
8026 10:55:41.545483 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 10:55:41.552586 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 10:55:41.555315 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 10:55:41.559101 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 10:55:41.565211 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8031 10:55:41.568344 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8032 10:55:41.571737 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 1)
8033 10:55:41.579064 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8034 10:55:41.581621 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 10:55:41.585027 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 10:55:41.591706 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 10:55:41.595400 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 10:55:41.598075 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 10:55:41.604989 1 6 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8040 10:55:41.608404 1 6 16 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8041 10:55:41.612079 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8042 10:55:41.618419 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 10:55:41.621554 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 10:55:41.624839 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 10:55:41.631440 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 10:55:41.634671 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 10:55:41.637663 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 10:55:41.644936 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 10:55:41.647805 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 10:55:41.651020 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 10:55:41.657985 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:55:41.661199 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:55:41.664128 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 10:55:41.670736 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 10:55:41.674183 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 10:55:41.677349 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:55:41.684061 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 10:55:41.687692 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:55:41.690748 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:55:41.697502 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:55:41.700740 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 10:55:41.704083 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 10:55:41.710696 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8064 10:55:41.713389 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 10:55:41.717225 Total UI for P1: 0, mck2ui 16
8066 10:55:41.720470 best dqsien dly found for B0: ( 1, 9, 10)
8067 10:55:41.723370 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 10:55:41.726655 Total UI for P1: 0, mck2ui 16
8069 10:55:41.730514 best dqsien dly found for B1: ( 1, 9, 16)
8070 10:55:41.733441 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8071 10:55:41.736464 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8072 10:55:41.736930
8073 10:55:41.743241 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8074 10:55:41.746720 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8075 10:55:41.749781 [Gating] SW calibration Done
8076 10:55:41.750205 ==
8077 10:55:41.753021 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 10:55:41.756177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 10:55:41.756644 ==
8080 10:55:41.759778 RX Vref Scan: 0
8081 10:55:41.760199
8082 10:55:41.760574 RX Vref 0 -> 0, step: 1
8083 10:55:41.760905
8084 10:55:41.762901 RX Delay 0 -> 252, step: 8
8085 10:55:41.766702 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8086 10:55:41.769759 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8087 10:55:41.776243 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8088 10:55:41.779531 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8089 10:55:41.783132 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8090 10:55:41.786376 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8091 10:55:41.789275 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8092 10:55:41.796175 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8093 10:55:41.799181 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8094 10:55:41.802470 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8095 10:55:41.805902 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8096 10:55:41.812906 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8097 10:55:41.815583 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8098 10:55:41.819332 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8099 10:55:41.822373 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8100 10:55:41.825406 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8101 10:55:41.829219 ==
8102 10:55:41.829773 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 10:55:41.835513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 10:55:41.835963 ==
8105 10:55:41.836305 DQS Delay:
8106 10:55:41.838807 DQS0 = 0, DQS1 = 0
8107 10:55:41.839247 DQM Delay:
8108 10:55:41.842259 DQM0 = 133, DQM1 = 128
8109 10:55:41.842682 DQ Delay:
8110 10:55:41.845636 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8111 10:55:41.848727 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8112 10:55:41.852296 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8113 10:55:41.855343 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8114 10:55:41.855765
8115 10:55:41.856099
8116 10:55:41.856412 ==
8117 10:55:41.858924 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 10:55:41.865013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 10:55:41.865550 ==
8120 10:55:41.865907
8121 10:55:41.866224
8122 10:55:41.866523 TX Vref Scan disable
8123 10:55:41.869423 == TX Byte 0 ==
8124 10:55:41.872020 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8125 10:55:41.879285 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8126 10:55:41.879722 == TX Byte 1 ==
8127 10:55:41.882287 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8128 10:55:41.889169 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8129 10:55:41.889595 ==
8130 10:55:41.892076 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 10:55:41.895358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 10:55:41.895812 ==
8133 10:55:41.908190
8134 10:55:41.911342 TX Vref early break, caculate TX vref
8135 10:55:41.914576 TX Vref=16, minBit 1, minWin=22, winSum=378
8136 10:55:41.918162 TX Vref=18, minBit 1, minWin=22, winSum=390
8137 10:55:41.921371 TX Vref=20, minBit 0, minWin=23, winSum=394
8138 10:55:41.925050 TX Vref=22, minBit 7, minWin=23, winSum=403
8139 10:55:41.928909 TX Vref=24, minBit 0, minWin=24, winSum=412
8140 10:55:41.934606 TX Vref=26, minBit 4, minWin=24, winSum=417
8141 10:55:41.937769 TX Vref=28, minBit 1, minWin=24, winSum=415
8142 10:55:41.941751 TX Vref=30, minBit 0, minWin=24, winSum=410
8143 10:55:41.944632 TX Vref=32, minBit 1, minWin=23, winSum=397
8144 10:55:41.948631 TX Vref=34, minBit 2, minWin=23, winSum=393
8145 10:55:41.954347 [TxChooseVref] Worse bit 4, Min win 24, Win sum 417, Final Vref 26
8146 10:55:41.954779
8147 10:55:41.957858 Final TX Range 0 Vref 26
8148 10:55:41.958306
8149 10:55:41.958665 ==
8150 10:55:41.961278 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 10:55:41.964825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 10:55:41.965256 ==
8153 10:55:41.965597
8154 10:55:41.965937
8155 10:55:41.967753 TX Vref Scan disable
8156 10:55:41.974063 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8157 10:55:41.974487 == TX Byte 0 ==
8158 10:55:41.977478 u2DelayCellOfst[0]=11 cells (3 PI)
8159 10:55:41.981172 u2DelayCellOfst[1]=18 cells (5 PI)
8160 10:55:41.984611 u2DelayCellOfst[2]=11 cells (3 PI)
8161 10:55:41.987460 u2DelayCellOfst[3]=11 cells (3 PI)
8162 10:55:41.990789 u2DelayCellOfst[4]=7 cells (2 PI)
8163 10:55:41.994177 u2DelayCellOfst[5]=0 cells (0 PI)
8164 10:55:41.997328 u2DelayCellOfst[6]=14 cells (4 PI)
8165 10:55:42.001196 u2DelayCellOfst[7]=18 cells (5 PI)
8166 10:55:42.003965 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8167 10:55:42.007158 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8168 10:55:42.010456 == TX Byte 1 ==
8169 10:55:42.014671 u2DelayCellOfst[8]=0 cells (0 PI)
8170 10:55:42.015097 u2DelayCellOfst[9]=3 cells (1 PI)
8171 10:55:42.017259 u2DelayCellOfst[10]=7 cells (2 PI)
8172 10:55:42.021156 u2DelayCellOfst[11]=3 cells (1 PI)
8173 10:55:42.024274 u2DelayCellOfst[12]=14 cells (4 PI)
8174 10:55:42.026916 u2DelayCellOfst[13]=14 cells (4 PI)
8175 10:55:42.030437 u2DelayCellOfst[14]=18 cells (5 PI)
8176 10:55:42.033711 u2DelayCellOfst[15]=11 cells (3 PI)
8177 10:55:42.040406 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8178 10:55:42.043690 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8179 10:55:42.044186 DramC Write-DBI on
8180 10:55:42.044697 ==
8181 10:55:42.047189 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 10:55:42.053730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 10:55:42.054160 ==
8184 10:55:42.054502
8185 10:55:42.054846
8186 10:55:42.055155 TX Vref Scan disable
8187 10:55:42.057689 == TX Byte 0 ==
8188 10:55:42.060827 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8189 10:55:42.063980 == TX Byte 1 ==
8190 10:55:42.067710 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8191 10:55:42.071030 DramC Write-DBI off
8192 10:55:42.071506
8193 10:55:42.071998 [DATLAT]
8194 10:55:42.072439 Freq=1600, CH0 RK1
8195 10:55:42.073051
8196 10:55:42.074076 DATLAT Default: 0xf
8197 10:55:42.077001 0, 0xFFFF, sum = 0
8198 10:55:42.077449 1, 0xFFFF, sum = 0
8199 10:55:42.080318 2, 0xFFFF, sum = 0
8200 10:55:42.080872 3, 0xFFFF, sum = 0
8201 10:55:42.083592 4, 0xFFFF, sum = 0
8202 10:55:42.084047 5, 0xFFFF, sum = 0
8203 10:55:42.087303 6, 0xFFFF, sum = 0
8204 10:55:42.087858 7, 0xFFFF, sum = 0
8205 10:55:42.090868 8, 0xFFFF, sum = 0
8206 10:55:42.091442 9, 0xFFFF, sum = 0
8207 10:55:42.093854 10, 0xFFFF, sum = 0
8208 10:55:42.094433 11, 0xFFFF, sum = 0
8209 10:55:42.097318 12, 0xFFFF, sum = 0
8210 10:55:42.097839 13, 0xFFFF, sum = 0
8211 10:55:42.100666 14, 0x0, sum = 1
8212 10:55:42.101117 15, 0x0, sum = 2
8213 10:55:42.103633 16, 0x0, sum = 3
8214 10:55:42.104067 17, 0x0, sum = 4
8215 10:55:42.107397 best_step = 15
8216 10:55:42.107947
8217 10:55:42.108297 ==
8218 10:55:42.110180 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 10:55:42.113547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 10:55:42.113978 ==
8221 10:55:42.117071 RX Vref Scan: 0
8222 10:55:42.117690
8223 10:55:42.118100 RX Vref 0 -> 0, step: 1
8224 10:55:42.118429
8225 10:55:42.120452 RX Delay 11 -> 252, step: 4
8226 10:55:42.127047 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8227 10:55:42.131106 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8228 10:55:42.133731 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8229 10:55:42.136981 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8230 10:55:42.140016 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8231 10:55:42.147301 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8232 10:55:42.150198 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8233 10:55:42.153401 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8234 10:55:42.156566 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8235 10:55:42.160046 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8236 10:55:42.166846 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8237 10:55:42.170034 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8238 10:55:42.173530 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8239 10:55:42.176490 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8240 10:55:42.183328 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8241 10:55:42.186224 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8242 10:55:42.186653 ==
8243 10:55:42.189341 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 10:55:42.192774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 10:55:42.193210 ==
8246 10:55:42.196433 DQS Delay:
8247 10:55:42.196895 DQS0 = 0, DQS1 = 0
8248 10:55:42.197332 DQM Delay:
8249 10:55:42.199276 DQM0 = 130, DQM1 = 125
8250 10:55:42.199654 DQ Delay:
8251 10:55:42.202777 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8252 10:55:42.205971 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8253 10:55:42.209550 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8254 10:55:42.215777 DQ12 =132, DQ13 =130, DQ14 =136, DQ15 =132
8255 10:55:42.216392
8256 10:55:42.216938
8257 10:55:42.217430
8258 10:55:42.219476 [DramC_TX_OE_Calibration] TA2
8259 10:55:42.222513 Original DQ_B0 (3 6) =30, OEN = 27
8260 10:55:42.223037 Original DQ_B1 (3 6) =30, OEN = 27
8261 10:55:42.225501 24, 0x0, End_B0=24 End_B1=24
8262 10:55:42.229061 25, 0x0, End_B0=25 End_B1=25
8263 10:55:42.232374 26, 0x0, End_B0=26 End_B1=26
8264 10:55:42.235714 27, 0x0, End_B0=27 End_B1=27
8265 10:55:42.236196 28, 0x0, End_B0=28 End_B1=28
8266 10:55:42.239239 29, 0x0, End_B0=29 End_B1=29
8267 10:55:42.242227 30, 0x0, End_B0=30 End_B1=30
8268 10:55:42.245760 31, 0x4141, End_B0=30 End_B1=30
8269 10:55:42.248616 Byte0 end_step=30 best_step=27
8270 10:55:42.252087 Byte1 end_step=30 best_step=27
8271 10:55:42.252555 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 10:55:42.255465 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 10:55:42.255899
8274 10:55:42.256335
8275 10:55:42.265243 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8276 10:55:42.268684 CH0 RK1: MR19=303, MR18=1E01
8277 10:55:42.271990 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8278 10:55:42.275238 [RxdqsGatingPostProcess] freq 1600
8279 10:55:42.281849 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 10:55:42.285028 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 10:55:42.288610 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 10:55:42.291895 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 10:55:42.295411 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 10:55:42.298443 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 10:55:42.302152 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 10:55:42.302674 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 10:55:42.305063 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 10:55:42.308689 Pre-setting of DQS Precalculation
8289 10:55:42.314675 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 10:55:42.315239 ==
8291 10:55:42.318065 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 10:55:42.321394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 10:55:42.321862 ==
8294 10:55:42.328068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 10:55:42.331469 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 10:55:42.334646 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 10:55:42.340919 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 10:55:42.350897 [CA 0] Center 41 (12~70) winsize 59
8299 10:55:42.354232 [CA 1] Center 41 (12~71) winsize 60
8300 10:55:42.357335 [CA 2] Center 37 (8~66) winsize 59
8301 10:55:42.360987 [CA 3] Center 36 (6~66) winsize 61
8302 10:55:42.364181 [CA 4] Center 37 (7~67) winsize 61
8303 10:55:42.367264 [CA 5] Center 36 (7~65) winsize 59
8304 10:55:42.367779
8305 10:55:42.370868 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8306 10:55:42.371387
8307 10:55:42.373924 [CATrainingPosCal] consider 1 rank data
8308 10:55:42.377295 u2DelayCellTimex100 = 262/100 ps
8309 10:55:42.383952 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8310 10:55:42.387587 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8311 10:55:42.390684 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 10:55:42.393906 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8313 10:55:42.396973 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8314 10:55:42.400669 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8315 10:55:42.401133
8316 10:55:42.404087 CA PerBit enable=1, Macro0, CA PI delay=36
8317 10:55:42.404699
8318 10:55:42.407247 [CBTSetCACLKResult] CA Dly = 36
8319 10:55:42.410670 CS Dly: 9 (0~40)
8320 10:55:42.414257 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 10:55:42.416986 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 10:55:42.417557 ==
8323 10:55:42.420818 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 10:55:42.423592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 10:55:42.427574 ==
8326 10:55:42.430172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 10:55:42.433442 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 10:55:42.440475 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 10:55:42.446722 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 10:55:42.454040 [CA 0] Center 42 (14~71) winsize 58
8331 10:55:42.457348 [CA 1] Center 42 (13~72) winsize 60
8332 10:55:42.460639 [CA 2] Center 37 (8~67) winsize 60
8333 10:55:42.464339 [CA 3] Center 37 (7~67) winsize 61
8334 10:55:42.467413 [CA 4] Center 37 (8~67) winsize 60
8335 10:55:42.471088 [CA 5] Center 37 (8~66) winsize 59
8336 10:55:42.471656
8337 10:55:42.473733 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8338 10:55:42.474200
8339 10:55:42.480036 [CATrainingPosCal] consider 2 rank data
8340 10:55:42.480502 u2DelayCellTimex100 = 262/100 ps
8341 10:55:42.486861 CA0 delay=42 (14~70),Diff = 6 PI (22 cell)
8342 10:55:42.489964 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8343 10:55:42.494014 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8344 10:55:42.496914 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8345 10:55:42.500670 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8346 10:55:42.503465 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8347 10:55:42.503962
8348 10:55:42.506807 CA PerBit enable=1, Macro0, CA PI delay=36
8349 10:55:42.507278
8350 10:55:42.510131 [CBTSetCACLKResult] CA Dly = 36
8351 10:55:42.513222 CS Dly: 10 (0~43)
8352 10:55:42.516749 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 10:55:42.520350 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 10:55:42.520864
8355 10:55:42.522966 ----->DramcWriteLeveling(PI) begin...
8356 10:55:42.523488 ==
8357 10:55:42.526157 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 10:55:42.533136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 10:55:42.533680 ==
8360 10:55:42.536670 Write leveling (Byte 0): 26 => 26
8361 10:55:42.539994 Write leveling (Byte 1): 27 => 27
8362 10:55:42.540549 DramcWriteLeveling(PI) end<-----
8363 10:55:42.542660
8364 10:55:42.543087 ==
8365 10:55:42.546347 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 10:55:42.549437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 10:55:42.549870 ==
8368 10:55:42.553221 [Gating] SW mode calibration
8369 10:55:42.559566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 10:55:42.562783 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 10:55:42.569365 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 10:55:42.573197 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 10:55:42.576346 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 10:55:42.582870 1 4 12 | B1->B0 | 2e2d 3030 | 1 1 | (0 0) (0 0)
8375 10:55:42.585924 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8376 10:55:42.589162 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 10:55:42.595644 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 10:55:42.599541 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 10:55:42.602700 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 10:55:42.609130 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 10:55:42.612567 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8382 10:55:42.615484 1 5 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
8383 10:55:42.621977 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8384 10:55:42.625383 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 10:55:42.628721 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 10:55:42.635450 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 10:55:42.639018 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 10:55:42.642046 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 10:55:42.648559 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8390 10:55:42.651920 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
8391 10:55:42.655569 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 10:55:42.661945 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 10:55:42.665286 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 10:55:42.668432 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 10:55:42.675500 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 10:55:42.678338 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 10:55:42.682091 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 10:55:42.688479 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 10:55:42.692164 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 10:55:42.695391 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 10:55:42.701265 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:55:42.704778 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:55:42.707818 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:55:42.714525 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:55:42.718217 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:55:42.721166 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:55:42.728257 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:55:42.731812 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:55:42.734601 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:55:42.741330 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:55:42.744903 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:55:42.748119 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:55:42.754407 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 10:55:42.757329 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 10:55:42.760955 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8416 10:55:42.764020 Total UI for P1: 0, mck2ui 16
8417 10:55:42.767106 best dqsien dly found for B0: ( 1, 9, 10)
8418 10:55:42.773926 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 10:55:42.777473 Total UI for P1: 0, mck2ui 16
8420 10:55:42.780810 best dqsien dly found for B1: ( 1, 9, 12)
8421 10:55:42.784026 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8422 10:55:42.787569 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8423 10:55:42.788150
8424 10:55:42.790734 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 10:55:42.793823 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8426 10:55:42.796989 [Gating] SW calibration Done
8427 10:55:42.797455 ==
8428 10:55:42.800069 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 10:55:42.803687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 10:55:42.804261 ==
8431 10:55:42.806899 RX Vref Scan: 0
8432 10:55:42.807368
8433 10:55:42.810276 RX Vref 0 -> 0, step: 1
8434 10:55:42.810853
8435 10:55:42.811235 RX Delay 0 -> 252, step: 8
8436 10:55:42.817113 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8437 10:55:42.819801 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8438 10:55:42.822993 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8439 10:55:42.827258 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8440 10:55:42.829816 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8441 10:55:42.836584 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8442 10:55:42.839373 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8443 10:55:42.842828 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8444 10:55:42.845872 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8445 10:55:42.849570 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8446 10:55:42.856148 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8447 10:55:42.858927 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8448 10:55:42.862686 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8449 10:55:42.865742 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8450 10:55:42.872202 iDelay=208, Bit 14, Center 143 (88 ~ 199) 112
8451 10:55:42.875761 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8452 10:55:42.875991 ==
8453 10:55:42.879174 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 10:55:42.882389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 10:55:42.882658 ==
8456 10:55:42.886061 DQS Delay:
8457 10:55:42.886354 DQS0 = 0, DQS1 = 0
8458 10:55:42.886545 DQM Delay:
8459 10:55:42.889079 DQM0 = 138, DQM1 = 130
8460 10:55:42.889330 DQ Delay:
8461 10:55:42.892298 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8462 10:55:42.895757 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8463 10:55:42.899308 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8464 10:55:42.905814 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =143
8465 10:55:42.906393
8466 10:55:42.906787
8467 10:55:42.907223 ==
8468 10:55:42.908740 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 10:55:42.912106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 10:55:42.912610 ==
8471 10:55:42.913057
8472 10:55:42.913430
8473 10:55:42.915899 TX Vref Scan disable
8474 10:55:42.916371 == TX Byte 0 ==
8475 10:55:42.922330 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 10:55:42.925655 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 10:55:42.928587 == TX Byte 1 ==
8478 10:55:42.932268 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8479 10:55:42.935304 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8480 10:55:42.935802 ==
8481 10:55:42.938383 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 10:55:42.941926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 10:55:42.945242 ==
8484 10:55:42.955803
8485 10:55:42.959198 TX Vref early break, caculate TX vref
8486 10:55:42.962627 TX Vref=16, minBit 5, minWin=22, winSum=377
8487 10:55:42.965798 TX Vref=18, minBit 0, minWin=23, winSum=389
8488 10:55:42.968812 TX Vref=20, minBit 5, minWin=23, winSum=397
8489 10:55:42.972584 TX Vref=22, minBit 6, minWin=24, winSum=409
8490 10:55:42.975642 TX Vref=24, minBit 0, minWin=25, winSum=416
8491 10:55:42.982407 TX Vref=26, minBit 0, minWin=25, winSum=423
8492 10:55:42.985882 TX Vref=28, minBit 5, minWin=25, winSum=424
8493 10:55:42.988998 TX Vref=30, minBit 1, minWin=24, winSum=416
8494 10:55:42.992425 TX Vref=32, minBit 5, minWin=24, winSum=408
8495 10:55:42.995534 TX Vref=34, minBit 0, minWin=24, winSum=400
8496 10:55:43.002071 [TxChooseVref] Worse bit 5, Min win 25, Win sum 424, Final Vref 28
8497 10:55:43.002496
8498 10:55:43.005371 Final TX Range 0 Vref 28
8499 10:55:43.005793
8500 10:55:43.006126 ==
8501 10:55:43.008832 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 10:55:43.012692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 10:55:43.013215 ==
8504 10:55:43.013556
8505 10:55:43.013864
8506 10:55:43.015377 TX Vref Scan disable
8507 10:55:43.021765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8508 10:55:43.022292 == TX Byte 0 ==
8509 10:55:43.025187 u2DelayCellOfst[0]=18 cells (5 PI)
8510 10:55:43.028722 u2DelayCellOfst[1]=14 cells (4 PI)
8511 10:55:43.031836 u2DelayCellOfst[2]=0 cells (0 PI)
8512 10:55:43.035008 u2DelayCellOfst[3]=7 cells (2 PI)
8513 10:55:43.039101 u2DelayCellOfst[4]=11 cells (3 PI)
8514 10:55:43.041335 u2DelayCellOfst[5]=22 cells (6 PI)
8515 10:55:43.044661 u2DelayCellOfst[6]=22 cells (6 PI)
8516 10:55:43.048224 u2DelayCellOfst[7]=7 cells (2 PI)
8517 10:55:43.051772 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 10:55:43.055076 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8519 10:55:43.058032 == TX Byte 1 ==
8520 10:55:43.061294 u2DelayCellOfst[8]=0 cells (0 PI)
8521 10:55:43.064805 u2DelayCellOfst[9]=3 cells (1 PI)
8522 10:55:43.067859 u2DelayCellOfst[10]=11 cells (3 PI)
8523 10:55:43.068280 u2DelayCellOfst[11]=3 cells (1 PI)
8524 10:55:43.071218 u2DelayCellOfst[12]=14 cells (4 PI)
8525 10:55:43.074238 u2DelayCellOfst[13]=18 cells (5 PI)
8526 10:55:43.077982 u2DelayCellOfst[14]=18 cells (5 PI)
8527 10:55:43.081074 u2DelayCellOfst[15]=18 cells (5 PI)
8528 10:55:43.088081 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8529 10:55:43.091209 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 10:55:43.091727 DramC Write-DBI on
8531 10:55:43.094323 ==
8532 10:55:43.097560 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 10:55:43.100726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 10:55:43.101250 ==
8535 10:55:43.101591
8536 10:55:43.101900
8537 10:55:43.103969 TX Vref Scan disable
8538 10:55:43.104388 == TX Byte 0 ==
8539 10:55:43.110579 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8540 10:55:43.111020 == TX Byte 1 ==
8541 10:55:43.114100 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8542 10:55:43.117856 DramC Write-DBI off
8543 10:55:43.118277
8544 10:55:43.118615 [DATLAT]
8545 10:55:43.120893 Freq=1600, CH1 RK0
8546 10:55:43.121314
8547 10:55:43.121644 DATLAT Default: 0xf
8548 10:55:43.124223 0, 0xFFFF, sum = 0
8549 10:55:43.124701 1, 0xFFFF, sum = 0
8550 10:55:43.127224 2, 0xFFFF, sum = 0
8551 10:55:43.127652 3, 0xFFFF, sum = 0
8552 10:55:43.130531 4, 0xFFFF, sum = 0
8553 10:55:43.131023 5, 0xFFFF, sum = 0
8554 10:55:43.133567 6, 0xFFFF, sum = 0
8555 10:55:43.134154 7, 0xFFFF, sum = 0
8556 10:55:43.137203 8, 0xFFFF, sum = 0
8557 10:55:43.140356 9, 0xFFFF, sum = 0
8558 10:55:43.140857 10, 0xFFFF, sum = 0
8559 10:55:43.143733 11, 0xFFFF, sum = 0
8560 10:55:43.144168 12, 0xFFFF, sum = 0
8561 10:55:43.146891 13, 0xFFFF, sum = 0
8562 10:55:43.147325 14, 0x0, sum = 1
8563 10:55:43.150810 15, 0x0, sum = 2
8564 10:55:43.151250 16, 0x0, sum = 3
8565 10:55:43.154154 17, 0x0, sum = 4
8566 10:55:43.154590 best_step = 15
8567 10:55:43.154930
8568 10:55:43.155249 ==
8569 10:55:43.157148 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 10:55:43.160586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 10:55:43.161121 ==
8572 10:55:43.163335 RX Vref Scan: 1
8573 10:55:43.163762
8574 10:55:43.166893 Set Vref Range= 24 -> 127
8575 10:55:43.167323
8576 10:55:43.167667 RX Vref 24 -> 127, step: 1
8577 10:55:43.170085
8578 10:55:43.170511 RX Delay 11 -> 252, step: 4
8579 10:55:43.170871
8580 10:55:43.173335 Set Vref, RX VrefLevel [Byte0]: 24
8581 10:55:43.176724 [Byte1]: 24
8582 10:55:43.180475
8583 10:55:43.180965 Set Vref, RX VrefLevel [Byte0]: 25
8584 10:55:43.183842 [Byte1]: 25
8585 10:55:43.188036
8586 10:55:43.188594 Set Vref, RX VrefLevel [Byte0]: 26
8587 10:55:43.191829 [Byte1]: 26
8588 10:55:43.196027
8589 10:55:43.196743 Set Vref, RX VrefLevel [Byte0]: 27
8590 10:55:43.199066 [Byte1]: 27
8591 10:55:43.203152
8592 10:55:43.203655 Set Vref, RX VrefLevel [Byte0]: 28
8593 10:55:43.206601 [Byte1]: 28
8594 10:55:43.211252
8595 10:55:43.211679 Set Vref, RX VrefLevel [Byte0]: 29
8596 10:55:43.214362 [Byte1]: 29
8597 10:55:43.218306
8598 10:55:43.218748 Set Vref, RX VrefLevel [Byte0]: 30
8599 10:55:43.221776 [Byte1]: 30
8600 10:55:43.225904
8601 10:55:43.226329 Set Vref, RX VrefLevel [Byte0]: 31
8602 10:55:43.229649 [Byte1]: 31
8603 10:55:43.233622
8604 10:55:43.234048 Set Vref, RX VrefLevel [Byte0]: 32
8605 10:55:43.237355 [Byte1]: 32
8606 10:55:43.241443
8607 10:55:43.241982 Set Vref, RX VrefLevel [Byte0]: 33
8608 10:55:43.244628 [Byte1]: 33
8609 10:55:43.249046
8610 10:55:43.249551 Set Vref, RX VrefLevel [Byte0]: 34
8611 10:55:43.252471 [Byte1]: 34
8612 10:55:43.256903
8613 10:55:43.257326 Set Vref, RX VrefLevel [Byte0]: 35
8614 10:55:43.260004 [Byte1]: 35
8615 10:55:43.264206
8616 10:55:43.264663 Set Vref, RX VrefLevel [Byte0]: 36
8617 10:55:43.267219 [Byte1]: 36
8618 10:55:43.271656
8619 10:55:43.272117 Set Vref, RX VrefLevel [Byte0]: 37
8620 10:55:43.275359 [Byte1]: 37
8621 10:55:43.279258
8622 10:55:43.279751 Set Vref, RX VrefLevel [Byte0]: 38
8623 10:55:43.282306 [Byte1]: 38
8624 10:55:43.286827
8625 10:55:43.287282 Set Vref, RX VrefLevel [Byte0]: 39
8626 10:55:43.290118 [Byte1]: 39
8627 10:55:43.294573
8628 10:55:43.294989 Set Vref, RX VrefLevel [Byte0]: 40
8629 10:55:43.298505 [Byte1]: 40
8630 10:55:43.302075
8631 10:55:43.302496 Set Vref, RX VrefLevel [Byte0]: 41
8632 10:55:43.305736 [Byte1]: 41
8633 10:55:43.310531
8634 10:55:43.310954 Set Vref, RX VrefLevel [Byte0]: 42
8635 10:55:43.313444 [Byte1]: 42
8636 10:55:43.317718
8637 10:55:43.318137 Set Vref, RX VrefLevel [Byte0]: 43
8638 10:55:43.321062 [Byte1]: 43
8639 10:55:43.325229
8640 10:55:43.325775 Set Vref, RX VrefLevel [Byte0]: 44
8641 10:55:43.328288 [Byte1]: 44
8642 10:55:43.333188
8643 10:55:43.333713 Set Vref, RX VrefLevel [Byte0]: 45
8644 10:55:43.335726 [Byte1]: 45
8645 10:55:43.341064
8646 10:55:43.341592 Set Vref, RX VrefLevel [Byte0]: 46
8647 10:55:43.343677 [Byte1]: 46
8648 10:55:43.348216
8649 10:55:43.348844 Set Vref, RX VrefLevel [Byte0]: 47
8650 10:55:43.352060 [Byte1]: 47
8651 10:55:43.355614
8652 10:55:43.356178 Set Vref, RX VrefLevel [Byte0]: 48
8653 10:55:43.358793 [Byte1]: 48
8654 10:55:43.363236
8655 10:55:43.363801 Set Vref, RX VrefLevel [Byte0]: 49
8656 10:55:43.366352 [Byte1]: 49
8657 10:55:43.371092
8658 10:55:43.371669 Set Vref, RX VrefLevel [Byte0]: 50
8659 10:55:43.374281 [Byte1]: 50
8660 10:55:43.378228
8661 10:55:43.378704 Set Vref, RX VrefLevel [Byte0]: 51
8662 10:55:43.381721 [Byte1]: 51
8663 10:55:43.386346
8664 10:55:43.386982 Set Vref, RX VrefLevel [Byte0]: 52
8665 10:55:43.389351 [Byte1]: 52
8666 10:55:43.393459
8667 10:55:43.393931 Set Vref, RX VrefLevel [Byte0]: 53
8668 10:55:43.396692 [Byte1]: 53
8669 10:55:43.400895
8670 10:55:43.401321 Set Vref, RX VrefLevel [Byte0]: 54
8671 10:55:43.404940 [Byte1]: 54
8672 10:55:43.408656
8673 10:55:43.409085 Set Vref, RX VrefLevel [Byte0]: 55
8674 10:55:43.412552 [Byte1]: 55
8675 10:55:43.416655
8676 10:55:43.417085 Set Vref, RX VrefLevel [Byte0]: 56
8677 10:55:43.419505 [Byte1]: 56
8678 10:55:43.423891
8679 10:55:43.424347 Set Vref, RX VrefLevel [Byte0]: 57
8680 10:55:43.427020 [Byte1]: 57
8681 10:55:43.431813
8682 10:55:43.432278 Set Vref, RX VrefLevel [Byte0]: 58
8683 10:55:43.434774 [Byte1]: 58
8684 10:55:43.439050
8685 10:55:43.439487 Set Vref, RX VrefLevel [Byte0]: 59
8686 10:55:43.442109 [Byte1]: 59
8687 10:55:43.446592
8688 10:55:43.446677 Set Vref, RX VrefLevel [Byte0]: 60
8689 10:55:43.449895 [Byte1]: 60
8690 10:55:43.454034
8691 10:55:43.454119 Set Vref, RX VrefLevel [Byte0]: 61
8692 10:55:43.457493 [Byte1]: 61
8693 10:55:43.461737
8694 10:55:43.461827 Set Vref, RX VrefLevel [Byte0]: 62
8695 10:55:43.464951 [Byte1]: 62
8696 10:55:43.469899
8697 10:55:43.470336 Set Vref, RX VrefLevel [Byte0]: 63
8698 10:55:43.472780 [Byte1]: 63
8699 10:55:43.477258
8700 10:55:43.477696 Set Vref, RX VrefLevel [Byte0]: 64
8701 10:55:43.480811 [Byte1]: 64
8702 10:55:43.484844
8703 10:55:43.485290 Set Vref, RX VrefLevel [Byte0]: 65
8704 10:55:43.488722 [Byte1]: 65
8705 10:55:43.492251
8706 10:55:43.492729 Set Vref, RX VrefLevel [Byte0]: 66
8707 10:55:43.496042 [Byte1]: 66
8708 10:55:43.500247
8709 10:55:43.500794 Set Vref, RX VrefLevel [Byte0]: 67
8710 10:55:43.503423 [Byte1]: 67
8711 10:55:43.508611
8712 10:55:43.509175 Set Vref, RX VrefLevel [Byte0]: 68
8713 10:55:43.511168 [Byte1]: 68
8714 10:55:43.515639
8715 10:55:43.516173 Set Vref, RX VrefLevel [Byte0]: 69
8716 10:55:43.518629 [Byte1]: 69
8717 10:55:43.523617
8718 10:55:43.524049 Set Vref, RX VrefLevel [Byte0]: 70
8719 10:55:43.526128 [Byte1]: 70
8720 10:55:43.531117
8721 10:55:43.531651 Set Vref, RX VrefLevel [Byte0]: 71
8722 10:55:43.533925 [Byte1]: 71
8723 10:55:43.538875
8724 10:55:43.539418 Final RX Vref Byte 0 = 53 to rank0
8725 10:55:43.541666 Final RX Vref Byte 1 = 60 to rank0
8726 10:55:43.545109 Final RX Vref Byte 0 = 53 to rank1
8727 10:55:43.548571 Final RX Vref Byte 1 = 60 to rank1==
8728 10:55:43.551372 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 10:55:43.558027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 10:55:43.558528 ==
8731 10:55:43.558873 DQS Delay:
8732 10:55:43.561282 DQS0 = 0, DQS1 = 0
8733 10:55:43.561712 DQM Delay:
8734 10:55:43.562055 DQM0 = 134, DQM1 = 129
8735 10:55:43.564679 DQ Delay:
8736 10:55:43.567875 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8737 10:55:43.571359 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8738 10:55:43.574289 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8739 10:55:43.578252 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8740 10:55:43.578695
8741 10:55:43.579049
8742 10:55:43.579361
8743 10:55:43.580997 [DramC_TX_OE_Calibration] TA2
8744 10:55:43.584350 Original DQ_B0 (3 6) =30, OEN = 27
8745 10:55:43.587369 Original DQ_B1 (3 6) =30, OEN = 27
8746 10:55:43.590888 24, 0x0, End_B0=24 End_B1=24
8747 10:55:43.591385 25, 0x0, End_B0=25 End_B1=25
8748 10:55:43.594159 26, 0x0, End_B0=26 End_B1=26
8749 10:55:43.597637 27, 0x0, End_B0=27 End_B1=27
8750 10:55:43.601359 28, 0x0, End_B0=28 End_B1=28
8751 10:55:43.604169 29, 0x0, End_B0=29 End_B1=29
8752 10:55:43.604642 30, 0x0, End_B0=30 End_B1=30
8753 10:55:43.607640 31, 0x4141, End_B0=30 End_B1=30
8754 10:55:43.610551 Byte0 end_step=30 best_step=27
8755 10:55:43.614742 Byte1 end_step=30 best_step=27
8756 10:55:43.617392 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 10:55:43.621420 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 10:55:43.621845
8759 10:55:43.622183
8760 10:55:43.627524 [DQSOSCAuto] RK0, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8761 10:55:43.630761 CH1 RK0: MR19=303, MR18=160C
8762 10:55:43.637046 CH1_RK0: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8763 10:55:43.637473
8764 10:55:43.640757 ----->DramcWriteLeveling(PI) begin...
8765 10:55:43.641185 ==
8766 10:55:43.643769 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 10:55:43.647006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 10:55:43.647507 ==
8769 10:55:43.650273 Write leveling (Byte 0): 24 => 24
8770 10:55:43.653812 Write leveling (Byte 1): 27 => 27
8771 10:55:43.657016 DramcWriteLeveling(PI) end<-----
8772 10:55:43.657515
8773 10:55:43.657853 ==
8774 10:55:43.660509 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 10:55:43.663760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 10:55:43.666991 ==
8777 10:55:43.667432 [Gating] SW mode calibration
8778 10:55:43.676878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 10:55:43.680266 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 10:55:43.683368 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 10:55:43.690334 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 10:55:43.693448 1 4 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
8783 10:55:43.696488 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8784 10:55:43.703286 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 10:55:43.706446 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 10:55:43.710223 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 10:55:43.716542 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 10:55:43.719949 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 10:55:43.723025 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 10:55:43.729406 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8791 10:55:43.733269 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8792 10:55:43.736324 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8793 10:55:43.742799 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 10:55:43.746088 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 10:55:43.749538 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 10:55:43.756012 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 10:55:43.759149 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 10:55:43.762466 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 10:55:43.769407 1 6 12 | B1->B0 | 4646 2525 | 0 0 | (0 0) (0 0)
8800 10:55:43.772687 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 10:55:43.775844 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 10:55:43.782321 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 10:55:43.786040 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 10:55:43.789312 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 10:55:43.795967 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 10:55:43.799445 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8807 10:55:43.802356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8808 10:55:43.809031 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8809 10:55:43.812678 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 10:55:43.815911 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 10:55:43.822182 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 10:55:43.825267 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 10:55:43.828770 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 10:55:43.835361 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 10:55:43.838562 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 10:55:43.842180 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 10:55:43.848597 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 10:55:43.851982 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 10:55:43.855395 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 10:55:43.861788 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:55:43.865032 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 10:55:43.867877 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8823 10:55:43.874201 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8824 10:55:43.877560 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 10:55:43.881205 Total UI for P1: 0, mck2ui 16
8826 10:55:43.884842 best dqsien dly found for B0: ( 1, 9, 12)
8827 10:55:43.887628 Total UI for P1: 0, mck2ui 16
8828 10:55:43.890783 best dqsien dly found for B1: ( 1, 9, 10)
8829 10:55:43.894597 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8830 10:55:43.897705 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8831 10:55:43.897795
8832 10:55:43.900763 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8833 10:55:43.904047 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8834 10:55:43.907431 [Gating] SW calibration Done
8835 10:55:43.907514 ==
8836 10:55:43.910565 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 10:55:43.917554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 10:55:43.917638 ==
8839 10:55:43.917704 RX Vref Scan: 0
8840 10:55:43.917767
8841 10:55:43.920667 RX Vref 0 -> 0, step: 1
8842 10:55:43.920751
8843 10:55:43.923864 RX Delay 0 -> 252, step: 8
8844 10:55:43.927280 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8845 10:55:43.931418 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8846 10:55:43.933560 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8847 10:55:43.937273 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8848 10:55:43.943557 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8849 10:55:43.947026 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8850 10:55:43.950590 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8851 10:55:43.953890 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8852 10:55:43.956897 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8853 10:55:43.963359 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8854 10:55:43.966580 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8855 10:55:43.970034 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8856 10:55:43.973319 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8857 10:55:43.980119 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8858 10:55:43.983788 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8859 10:55:43.986848 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8860 10:55:43.986932 ==
8861 10:55:43.989988 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 10:55:43.993303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 10:55:43.993388 ==
8864 10:55:43.996277 DQS Delay:
8865 10:55:43.996360 DQS0 = 0, DQS1 = 0
8866 10:55:43.999882 DQM Delay:
8867 10:55:43.999965 DQM0 = 136, DQM1 = 129
8868 10:55:44.000031 DQ Delay:
8869 10:55:44.006559 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8870 10:55:44.009815 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8871 10:55:44.013048 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8872 10:55:44.016226 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8873 10:55:44.016308
8874 10:55:44.016375
8875 10:55:44.016436 ==
8876 10:55:44.019721 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 10:55:44.023150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 10:55:44.023234 ==
8879 10:55:44.023301
8880 10:55:44.023362
8881 10:55:44.026168 TX Vref Scan disable
8882 10:55:44.029655 == TX Byte 0 ==
8883 10:55:44.032830 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 10:55:44.036078 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 10:55:44.041313 == TX Byte 1 ==
8886 10:55:44.042582 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8887 10:55:44.045759 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8888 10:55:44.045842 ==
8889 10:55:44.049075 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 10:55:44.055912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 10:55:44.055996 ==
8892 10:55:44.067860
8893 10:55:44.070759 TX Vref early break, caculate TX vref
8894 10:55:44.073981 TX Vref=16, minBit 1, minWin=22, winSum=379
8895 10:55:44.077180 TX Vref=18, minBit 0, minWin=23, winSum=394
8896 10:55:44.080819 TX Vref=20, minBit 1, minWin=24, winSum=403
8897 10:55:44.083719 TX Vref=22, minBit 1, minWin=24, winSum=406
8898 10:55:44.087428 TX Vref=24, minBit 0, minWin=24, winSum=415
8899 10:55:44.093860 TX Vref=26, minBit 1, minWin=24, winSum=418
8900 10:55:44.097007 TX Vref=28, minBit 1, minWin=25, winSum=422
8901 10:55:44.100302 TX Vref=30, minBit 0, minWin=24, winSum=419
8902 10:55:44.103630 TX Vref=32, minBit 0, minWin=24, winSum=409
8903 10:55:44.106641 TX Vref=34, minBit 0, minWin=23, winSum=397
8904 10:55:44.113610 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8905 10:55:44.113694
8906 10:55:44.116529 Final TX Range 0 Vref 28
8907 10:55:44.116613
8908 10:55:44.116679 ==
8909 10:55:44.119931 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 10:55:44.123410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 10:55:44.123488 ==
8912 10:55:44.123554
8913 10:55:44.123614
8914 10:55:44.126707 TX Vref Scan disable
8915 10:55:44.133135 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8916 10:55:44.133245 == TX Byte 0 ==
8917 10:55:44.136920 u2DelayCellOfst[0]=18 cells (5 PI)
8918 10:55:44.140241 u2DelayCellOfst[1]=14 cells (4 PI)
8919 10:55:44.143560 u2DelayCellOfst[2]=0 cells (0 PI)
8920 10:55:44.146744 u2DelayCellOfst[3]=7 cells (2 PI)
8921 10:55:44.150041 u2DelayCellOfst[4]=11 cells (3 PI)
8922 10:55:44.152998 u2DelayCellOfst[5]=22 cells (6 PI)
8923 10:55:44.156649 u2DelayCellOfst[6]=22 cells (6 PI)
8924 10:55:44.159561 u2DelayCellOfst[7]=3 cells (1 PI)
8925 10:55:44.163124 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 10:55:44.166425 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 10:55:44.169902 == TX Byte 1 ==
8928 10:55:44.172987 u2DelayCellOfst[8]=0 cells (0 PI)
8929 10:55:44.176123 u2DelayCellOfst[9]=3 cells (1 PI)
8930 10:55:44.179656 u2DelayCellOfst[10]=11 cells (3 PI)
8931 10:55:44.179907 u2DelayCellOfst[11]=3 cells (1 PI)
8932 10:55:44.182865 u2DelayCellOfst[12]=14 cells (4 PI)
8933 10:55:44.186497 u2DelayCellOfst[13]=14 cells (4 PI)
8934 10:55:44.189687 u2DelayCellOfst[14]=18 cells (5 PI)
8935 10:55:44.192986 u2DelayCellOfst[15]=14 cells (4 PI)
8936 10:55:44.199425 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8937 10:55:44.202843 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8938 10:55:44.203275 DramC Write-DBI on
8939 10:55:44.203617 ==
8940 10:55:44.207160 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 10:55:44.212957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 10:55:44.213041 ==
8943 10:55:44.213108
8944 10:55:44.213170
8945 10:55:44.216046 TX Vref Scan disable
8946 10:55:44.216128 == TX Byte 0 ==
8947 10:55:44.222845 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8948 10:55:44.222929 == TX Byte 1 ==
8949 10:55:44.225509 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8950 10:55:44.228949 DramC Write-DBI off
8951 10:55:44.229038
8952 10:55:44.229109 [DATLAT]
8953 10:55:44.232648 Freq=1600, CH1 RK1
8954 10:55:44.232743
8955 10:55:44.232819 DATLAT Default: 0xf
8956 10:55:44.236316 0, 0xFFFF, sum = 0
8957 10:55:44.236421 1, 0xFFFF, sum = 0
8958 10:55:44.238811 2, 0xFFFF, sum = 0
8959 10:55:44.238915 3, 0xFFFF, sum = 0
8960 10:55:44.242068 4, 0xFFFF, sum = 0
8961 10:55:44.242183 5, 0xFFFF, sum = 0
8962 10:55:44.245383 6, 0xFFFF, sum = 0
8963 10:55:44.245508 7, 0xFFFF, sum = 0
8964 10:55:44.249171 8, 0xFFFF, sum = 0
8965 10:55:44.251914 9, 0xFFFF, sum = 0
8966 10:55:44.252053 10, 0xFFFF, sum = 0
8967 10:55:44.255527 11, 0xFFFF, sum = 0
8968 10:55:44.255699 12, 0xFFFF, sum = 0
8969 10:55:44.259474 13, 0xFFFF, sum = 0
8970 10:55:44.259666 14, 0x0, sum = 1
8971 10:55:44.262762 15, 0x0, sum = 2
8972 10:55:44.262940 16, 0x0, sum = 3
8973 10:55:44.265091 17, 0x0, sum = 4
8974 10:55:44.265299 best_step = 15
8975 10:55:44.265461
8976 10:55:44.265612 ==
8977 10:55:44.268714 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 10:55:44.271992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 10:55:44.272241 ==
8980 10:55:44.275297 RX Vref Scan: 0
8981 10:55:44.275602
8982 10:55:44.278599 RX Vref 0 -> 0, step: 1
8983 10:55:44.278906
8984 10:55:44.279151 RX Delay 11 -> 252, step: 4
8985 10:55:44.286134 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
8986 10:55:44.289191 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
8987 10:55:44.292503 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
8988 10:55:44.296249 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
8989 10:55:44.299167 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
8990 10:55:44.305722 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
8991 10:55:44.308784 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
8992 10:55:44.312370 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
8993 10:55:44.315762 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
8994 10:55:44.322147 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
8995 10:55:44.325339 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
8996 10:55:44.328628 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
8997 10:55:44.331807 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
8998 10:55:44.335050 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
8999 10:55:44.341844 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9000 10:55:44.345596 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9001 10:55:44.346185 ==
9002 10:55:44.348593 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 10:55:44.352082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 10:55:44.352693 ==
9005 10:55:44.355431 DQS Delay:
9006 10:55:44.356020 DQS0 = 0, DQS1 = 0
9007 10:55:44.356375 DQM Delay:
9008 10:55:44.358795 DQM0 = 134, DQM1 = 127
9009 10:55:44.359334 DQ Delay:
9010 10:55:44.362020 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9011 10:55:44.365764 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9012 10:55:44.371726 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9013 10:55:44.374981 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9014 10:55:44.375482
9015 10:55:44.375825
9016 10:55:44.376135
9017 10:55:44.378043 [DramC_TX_OE_Calibration] TA2
9018 10:55:44.381333 Original DQ_B0 (3 6) =30, OEN = 27
9019 10:55:44.384580 Original DQ_B1 (3 6) =30, OEN = 27
9020 10:55:44.385036 24, 0x0, End_B0=24 End_B1=24
9021 10:55:44.388356 25, 0x0, End_B0=25 End_B1=25
9022 10:55:44.391265 26, 0x0, End_B0=26 End_B1=26
9023 10:55:44.394628 27, 0x0, End_B0=27 End_B1=27
9024 10:55:44.398321 28, 0x0, End_B0=28 End_B1=28
9025 10:55:44.398755 29, 0x0, End_B0=29 End_B1=29
9026 10:55:44.401526 30, 0x0, End_B0=30 End_B1=30
9027 10:55:44.404868 31, 0x4141, End_B0=30 End_B1=30
9028 10:55:44.407962 Byte0 end_step=30 best_step=27
9029 10:55:44.411161 Byte1 end_step=30 best_step=27
9030 10:55:44.414600 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 10:55:44.415032 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 10:55:44.415404
9033 10:55:44.415728
9034 10:55:44.424205 [DQSOSCAuto] RK1, (LSB)MR18= 0x906, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
9035 10:55:44.427843 CH1 RK1: MR19=303, MR18=906
9036 10:55:44.430795 CH1_RK1: MR19=0x303, MR18=0x906, DQSOSC=405, MR23=63, INC=22, DEC=15
9037 10:55:44.434798 [RxdqsGatingPostProcess] freq 1600
9038 10:55:44.440718 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 10:55:44.444581 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 10:55:44.447598 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 10:55:44.450604 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 10:55:44.454157 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 10:55:44.457123 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 10:55:44.460595 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 10:55:44.464143 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 10:55:44.467141 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 10:55:44.470134 Pre-setting of DQS Precalculation
9048 10:55:44.473560 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 10:55:44.480290 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 10:55:44.486272 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 10:55:44.489788
9052 10:55:44.489871
9053 10:55:44.489934 [Calibration Summary] 3200 Mbps
9054 10:55:44.492755 CH 0, Rank 0
9055 10:55:44.492838 SW Impedance : PASS
9056 10:55:44.496326 DUTY Scan : NO K
9057 10:55:44.499610 ZQ Calibration : PASS
9058 10:55:44.499689 Jitter Meter : NO K
9059 10:55:44.503000 CBT Training : PASS
9060 10:55:44.506481 Write leveling : PASS
9061 10:55:44.506560 RX DQS gating : PASS
9062 10:55:44.509125 RX DQ/DQS(RDDQC) : PASS
9063 10:55:44.512472 TX DQ/DQS : PASS
9064 10:55:44.512612 RX DATLAT : PASS
9065 10:55:44.516237 RX DQ/DQS(Engine): PASS
9066 10:55:44.519193 TX OE : PASS
9067 10:55:44.519270 All Pass.
9068 10:55:44.519333
9069 10:55:44.519393 CH 0, Rank 1
9070 10:55:44.522579 SW Impedance : PASS
9071 10:55:44.525908 DUTY Scan : NO K
9072 10:55:44.526014 ZQ Calibration : PASS
9073 10:55:44.529551 Jitter Meter : NO K
9074 10:55:44.532478 CBT Training : PASS
9075 10:55:44.532589 Write leveling : PASS
9076 10:55:44.535844 RX DQS gating : PASS
9077 10:55:44.539019 RX DQ/DQS(RDDQC) : PASS
9078 10:55:44.539093 TX DQ/DQS : PASS
9079 10:55:44.542969 RX DATLAT : PASS
9080 10:55:44.543070 RX DQ/DQS(Engine): PASS
9081 10:55:44.545935 TX OE : PASS
9082 10:55:44.546006 All Pass.
9083 10:55:44.546066
9084 10:55:44.549057 CH 1, Rank 0
9085 10:55:44.552266 SW Impedance : PASS
9086 10:55:44.552340 DUTY Scan : NO K
9087 10:55:44.555426 ZQ Calibration : PASS
9088 10:55:44.555495 Jitter Meter : NO K
9089 10:55:44.558822 CBT Training : PASS
9090 10:55:44.562191 Write leveling : PASS
9091 10:55:44.562280 RX DQS gating : PASS
9092 10:55:44.565356 RX DQ/DQS(RDDQC) : PASS
9093 10:55:44.568615 TX DQ/DQS : PASS
9094 10:55:44.568718 RX DATLAT : PASS
9095 10:55:44.572184 RX DQ/DQS(Engine): PASS
9096 10:55:44.576448 TX OE : PASS
9097 10:55:44.576980 All Pass.
9098 10:55:44.577405
9099 10:55:44.577736 CH 1, Rank 1
9100 10:55:44.579038 SW Impedance : PASS
9101 10:55:44.582395 DUTY Scan : NO K
9102 10:55:44.582824 ZQ Calibration : PASS
9103 10:55:44.585755 Jitter Meter : NO K
9104 10:55:44.589002 CBT Training : PASS
9105 10:55:44.589430 Write leveling : PASS
9106 10:55:44.592477 RX DQS gating : PASS
9107 10:55:44.595919 RX DQ/DQS(RDDQC) : PASS
9108 10:55:44.596344 TX DQ/DQS : PASS
9109 10:55:44.599108 RX DATLAT : PASS
9110 10:55:44.602760 RX DQ/DQS(Engine): PASS
9111 10:55:44.603185 TX OE : PASS
9112 10:55:44.603525 All Pass.
9113 10:55:44.605979
9114 10:55:44.606425 DramC Write-DBI on
9115 10:55:44.608970 PER_BANK_REFRESH: Hybrid Mode
9116 10:55:44.609400 TX_TRACKING: ON
9117 10:55:44.618216 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 10:55:44.625278 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 10:55:44.635004 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 10:55:44.638680 [FAST_K] Save calibration result to emmc
9121 10:55:44.641637 sync common calibartion params.
9122 10:55:44.641775 sync cbt_mode0:1, 1:1
9123 10:55:44.645621 dram_init: ddr_geometry: 2
9124 10:55:44.648438 dram_init: ddr_geometry: 2
9125 10:55:44.648610 dram_init: ddr_geometry: 2
9126 10:55:44.652082 0:dram_rank_size:100000000
9127 10:55:44.655617 1:dram_rank_size:100000000
9128 10:55:44.661676 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 10:55:44.661923 DFS_SHUFFLE_HW_MODE: ON
9130 10:55:44.664849 dramc_set_vcore_voltage set vcore to 725000
9131 10:55:44.668371 Read voltage for 1600, 0
9132 10:55:44.668706 Vio18 = 0
9133 10:55:44.671670 Vcore = 725000
9134 10:55:44.672059 Vdram = 0
9135 10:55:44.672371 Vddq = 0
9136 10:55:44.674781 Vmddr = 0
9137 10:55:44.675210 switch to 3200 Mbps bootup
9138 10:55:44.678021 [DramcRunTimeConfig]
9139 10:55:44.678448 PHYPLL
9140 10:55:44.681863 DPM_CONTROL_AFTERK: ON
9141 10:55:44.682445 PER_BANK_REFRESH: ON
9142 10:55:44.684767 REFRESH_OVERHEAD_REDUCTION: ON
9143 10:55:44.688149 CMD_PICG_NEW_MODE: OFF
9144 10:55:44.688231 XRTWTW_NEW_MODE: ON
9145 10:55:44.691790 XRTRTR_NEW_MODE: ON
9146 10:55:44.691872 TX_TRACKING: ON
9147 10:55:44.694818 RDSEL_TRACKING: OFF
9148 10:55:44.697790 DQS Precalculation for DVFS: ON
9149 10:55:44.697893 RX_TRACKING: OFF
9150 10:55:44.700909 HW_GATING DBG: ON
9151 10:55:44.700983 ZQCS_ENABLE_LP4: ON
9152 10:55:44.704773 RX_PICG_NEW_MODE: ON
9153 10:55:44.704849 TX_PICG_NEW_MODE: ON
9154 10:55:44.707713 ENABLE_RX_DCM_DPHY: ON
9155 10:55:44.710929 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 10:55:44.714485 DUMMY_READ_FOR_TRACKING: OFF
9157 10:55:44.714586 !!! SPM_CONTROL_AFTERK: OFF
9158 10:55:44.717979 !!! SPM could not control APHY
9159 10:55:44.720839 IMPEDANCE_TRACKING: ON
9160 10:55:44.720937 TEMP_SENSOR: ON
9161 10:55:44.724169 HW_SAVE_FOR_SR: OFF
9162 10:55:44.727451 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 10:55:44.731422 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 10:55:44.734231 Read ODT Tracking: ON
9165 10:55:44.734313 Refresh Rate DeBounce: ON
9166 10:55:44.737951 DFS_NO_QUEUE_FLUSH: ON
9167 10:55:44.741135 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 10:55:44.744389 ENABLE_DFS_RUNTIME_MRW: OFF
9169 10:55:44.744472 DDR_RESERVE_NEW_MODE: ON
9170 10:55:44.747325 MR_CBT_SWITCH_FREQ: ON
9171 10:55:44.750835 =========================
9172 10:55:44.768445 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 10:55:44.771968 dram_init: ddr_geometry: 2
9174 10:55:44.789707 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 10:55:44.792861 dram_init: dram init end (result: 0)
9176 10:55:44.799784 DRAM-K: Full calibration passed in 24569 msecs
9177 10:55:44.803000 MRC: failed to locate region type 0.
9178 10:55:44.803079 DRAM rank0 size:0x100000000,
9179 10:55:44.806216 DRAM rank1 size=0x100000000
9180 10:55:44.816379 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 10:55:44.822658 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 10:55:44.829363 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 10:55:44.839034 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 10:55:44.839139 DRAM rank0 size:0x100000000,
9185 10:55:44.842548 DRAM rank1 size=0x100000000
9186 10:55:44.842623 CBMEM:
9187 10:55:44.845701 IMD: root @ 0xfffff000 254 entries.
9188 10:55:44.848991 IMD: root @ 0xffffec00 62 entries.
9189 10:55:44.852429 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 10:55:44.858620 WARNING: RO_VPD is uninitialized or empty.
9191 10:55:44.861980 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 10:55:44.869896 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 10:55:44.882363 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9194 10:55:44.893857 BS: romstage times (exec / console): total (unknown) / 24069 ms
9195 10:55:44.893964
9196 10:55:44.894052
9197 10:55:44.903729 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 10:55:44.906993 ARM64: Exception handlers installed.
9199 10:55:44.910412 ARM64: Testing exception
9200 10:55:44.913427 ARM64: Done test exception
9201 10:55:44.913527 Enumerating buses...
9202 10:55:44.917512 Show all devs... Before device enumeration.
9203 10:55:44.920434 Root Device: enabled 1
9204 10:55:44.923435 CPU_CLUSTER: 0: enabled 1
9205 10:55:44.923522 CPU: 00: enabled 1
9206 10:55:44.926958 Compare with tree...
9207 10:55:44.927041 Root Device: enabled 1
9208 10:55:44.929953 CPU_CLUSTER: 0: enabled 1
9209 10:55:44.933269 CPU: 00: enabled 1
9210 10:55:44.933352 Root Device scanning...
9211 10:55:44.936794 scan_static_bus for Root Device
9212 10:55:44.940063 CPU_CLUSTER: 0 enabled
9213 10:55:44.943209 scan_static_bus for Root Device done
9214 10:55:44.947136 scan_bus: bus Root Device finished in 8 msecs
9215 10:55:44.947225 done
9216 10:55:44.953302 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 10:55:44.957245 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 10:55:44.963547 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 10:55:44.966691 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 10:55:44.970034 Allocating resources...
9221 10:55:44.973668 Reading resources...
9222 10:55:44.976255 Root Device read_resources bus 0 link: 0
9223 10:55:44.979754 DRAM rank0 size:0x100000000,
9224 10:55:44.979852 DRAM rank1 size=0x100000000
9225 10:55:44.983508 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 10:55:44.986302 CPU: 00 missing read_resources
9227 10:55:44.993476 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 10:55:44.996295 Root Device read_resources bus 0 link: 0 done
9229 10:55:44.996408 Done reading resources.
9230 10:55:45.002853 Show resources in subtree (Root Device)...After reading.
9231 10:55:45.006403 Root Device child on link 0 CPU_CLUSTER: 0
9232 10:55:45.009778 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 10:55:45.019389 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 10:55:45.019568 CPU: 00
9235 10:55:45.022673 Root Device assign_resources, bus 0 link: 0
9236 10:55:45.025931 CPU_CLUSTER: 0 missing set_resources
9237 10:55:45.032463 Root Device assign_resources, bus 0 link: 0 done
9238 10:55:45.032790 Done setting resources.
9239 10:55:45.039298 Show resources in subtree (Root Device)...After assigning values.
9240 10:55:45.042564 Root Device child on link 0 CPU_CLUSTER: 0
9241 10:55:45.046586 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 10:55:45.055891 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 10:55:45.056325 CPU: 00
9244 10:55:45.059265 Done allocating resources.
9245 10:55:45.066454 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 10:55:45.066883 Enabling resources...
9247 10:55:45.067225 done.
9248 10:55:45.072453 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 10:55:45.076043 Initializing devices...
9250 10:55:45.076472 Root Device init
9251 10:55:45.078938 init hardware done!
9252 10:55:45.079362 0x00000018: ctrlr->caps
9253 10:55:45.082128 52.000 MHz: ctrlr->f_max
9254 10:55:45.085705 0.400 MHz: ctrlr->f_min
9255 10:55:45.086145 0x40ff8080: ctrlr->voltages
9256 10:55:45.088846 sclk: 390625
9257 10:55:45.089273 Bus Width = 1
9258 10:55:45.092547 sclk: 390625
9259 10:55:45.092976 Bus Width = 1
9260 10:55:45.095379 Early init status = 3
9261 10:55:45.098962 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 10:55:45.102423 in-header: 03 fc 00 00 01 00 00 00
9263 10:55:45.105772 in-data: 00
9264 10:55:45.109003 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 10:55:45.114693 in-header: 03 fd 00 00 00 00 00 00
9266 10:55:45.117978 in-data:
9267 10:55:45.121257 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 10:55:45.125142 in-header: 03 fc 00 00 01 00 00 00
9269 10:55:45.128742 in-data: 00
9270 10:55:45.132277 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 10:55:45.139448 in-header: 03 fd 00 00 00 00 00 00
9272 10:55:45.142550 in-data:
9273 10:55:45.146482 [SSUSB] Setting up USB HOST controller...
9274 10:55:45.149779 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 10:55:45.152416 [SSUSB] phy power-on done.
9276 10:55:45.155961 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 10:55:45.162536 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 10:55:45.165837 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 10:55:45.172815 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 10:55:45.179518 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9281 10:55:45.185763 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 10:55:45.191913 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 10:55:45.198971 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 10:55:45.201866 SPM: binary array size = 0x9dc
9285 10:55:45.205756 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 10:55:45.212063 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 10:55:45.218553 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 10:55:45.225033 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 10:55:45.228093 configure_display: Starting display init
9290 10:55:45.262525 anx7625_power_on_init: Init interface.
9291 10:55:45.265868 anx7625_disable_pd_protocol: Disabled PD feature.
9292 10:55:45.272383 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 10:55:45.296924 anx7625_start_dp_work: Secure OCM version=00
9294 10:55:45.300183 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 10:55:45.315355 sp_tx_get_edid_block: EDID Block = 1
9296 10:55:45.417747 Extracted contents:
9297 10:55:45.421099 header: 00 ff ff ff ff ff ff 00
9298 10:55:45.424733 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 10:55:45.427624 version: 01 04
9300 10:55:45.431068 basic params: 95 1f 11 78 0a
9301 10:55:45.434056 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 10:55:45.438099 established: 00 00 00
9303 10:55:45.443893 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 10:55:45.450544 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 10:55:45.454435 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 10:55:45.460349 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 10:55:45.466905 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 10:55:45.470044 extensions: 00
9309 10:55:45.470528 checksum: fb
9310 10:55:45.470866
9311 10:55:45.476714 Manufacturer: IVO Model 57d Serial Number 0
9312 10:55:45.477175 Made week 0 of 2020
9313 10:55:45.480118 EDID version: 1.4
9314 10:55:45.480572 Digital display
9315 10:55:45.483189 6 bits per primary color channel
9316 10:55:45.487150 DisplayPort interface
9317 10:55:45.487617 Maximum image size: 31 cm x 17 cm
9318 10:55:45.489914 Gamma: 220%
9319 10:55:45.490327 Check DPMS levels
9320 10:55:45.496142 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 10:55:45.499848 First detailed timing is preferred timing
9322 10:55:45.503234 Established timings supported:
9323 10:55:45.503732 Standard timings supported:
9324 10:55:45.506113 Detailed timings
9325 10:55:45.509664 Hex of detail: 383680a07038204018303c0035ae10000019
9326 10:55:45.516375 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 10:55:45.519796 0780 0798 07c8 0820 hborder 0
9328 10:55:45.522870 0438 043b 0447 0458 vborder 0
9329 10:55:45.526047 -hsync -vsync
9330 10:55:45.529664 Did detailed timing
9331 10:55:45.532582 Hex of detail: 000000000000000000000000000000000000
9332 10:55:45.535744 Manufacturer-specified data, tag 0
9333 10:55:45.539198 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 10:55:45.542583 ASCII string: InfoVision
9335 10:55:45.545978 Hex of detail: 000000fe00523134304e574635205248200a
9336 10:55:45.549071 ASCII string: R140NWF5 RH
9337 10:55:45.549484 Checksum
9338 10:55:45.552376 Checksum: 0xfb (valid)
9339 10:55:45.555857 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 10:55:45.558886 DSI data_rate: 832800000 bps
9341 10:55:45.565388 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 10:55:45.568552 anx7625_parse_edid: pixelclock(138800).
9343 10:55:45.572195 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 10:55:45.575172 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 10:55:45.578723 anx7625_dsi_config: config dsi.
9346 10:55:45.585718 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 10:55:45.599844 anx7625_dsi_config: success to config DSI
9348 10:55:45.603115 anx7625_dp_start: MIPI phy setup OK.
9349 10:55:45.606327 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 10:55:45.609597 mtk_ddp_mode_set invalid vrefresh 60
9351 10:55:45.612838 main_disp_path_setup
9352 10:55:45.613258 ovl_layer_smi_id_en
9353 10:55:45.616547 ovl_layer_smi_id_en
9354 10:55:45.616995 ccorr_config
9355 10:55:45.617333 aal_config
9356 10:55:45.619369 gamma_config
9357 10:55:45.619784 postmask_config
9358 10:55:45.622742 dither_config
9359 10:55:45.626088 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 10:55:45.632618 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 10:55:45.635998 Root Device init finished in 556 msecs
9362 10:55:45.639158 CPU_CLUSTER: 0 init
9363 10:55:45.645537 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 10:55:45.652452 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 10:55:45.652899 APU_MBOX 0x190000b0 = 0x10001
9366 10:55:45.655556 APU_MBOX 0x190001b0 = 0x10001
9367 10:55:45.658911 APU_MBOX 0x190005b0 = 0x10001
9368 10:55:45.662250 APU_MBOX 0x190006b0 = 0x10001
9369 10:55:45.668954 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 10:55:45.678740 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9371 10:55:45.691020 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 10:55:45.698284 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 10:55:45.709500 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9374 10:55:45.718811 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 10:55:45.721879 CPU_CLUSTER: 0 init finished in 81 msecs
9376 10:55:45.725396 Devices initialized
9377 10:55:45.728402 Show all devs... After init.
9378 10:55:45.728887 Root Device: enabled 1
9379 10:55:45.731671 CPU_CLUSTER: 0: enabled 1
9380 10:55:45.735058 CPU: 00: enabled 1
9381 10:55:45.738592 BS: BS_DEV_INIT run times (exec / console): 215 / 447 ms
9382 10:55:45.741870 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 10:55:45.745511 ELOG: NV offset 0x57f000 size 0x1000
9384 10:55:45.751354 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9385 10:55:45.758661 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 10:55:45.761388 ELOG: Event(17) added with size 13 at 2023-06-05 10:55:45 UTC
9387 10:55:45.768276 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 10:55:45.771655 in-header: 03 ee 00 00 2c 00 00 00
9389 10:55:45.781407 in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 10:55:45.787807 ELOG: Event(A1) added with size 10 at 2023-06-05 10:55:45 UTC
9391 10:55:45.794770 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 10:55:45.801169 ELOG: Event(A0) added with size 9 at 2023-06-05 10:55:45 UTC
9393 10:55:45.804569 elog_add_boot_reason: Logged dev mode boot
9394 10:55:45.811056 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9395 10:55:45.811485 Finalize devices...
9396 10:55:45.814513 Devices finalized
9397 10:55:45.818072 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 10:55:45.821452 Writing coreboot table at 0xffe64000
9399 10:55:45.824378 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 10:55:45.827968 1. 0000000040000000-00000000400fffff: RAM
9401 10:55:45.834004 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 10:55:45.837569 3. 000000004032b000-00000000545fffff: RAM
9403 10:55:45.841010 4. 0000000054600000-000000005465ffff: BL31
9404 10:55:45.844386 5. 0000000054660000-00000000ffe63fff: RAM
9405 10:55:45.850707 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 10:55:45.854403 7. 0000000100000000-000000023fffffff: RAM
9407 10:55:45.857786 Passing 5 GPIOs to payload:
9408 10:55:45.860393 NAME | PORT | POLARITY | VALUE
9409 10:55:45.867244 EC in RW | 0x000000aa | low | undefined
9410 10:55:45.870459 EC interrupt | 0x00000005 | low | undefined
9411 10:55:45.874005 TPM interrupt | 0x000000ab | high | undefined
9412 10:55:45.880254 SD card detect | 0x00000011 | high | undefined
9413 10:55:45.883520 speaker enable | 0x00000093 | high | undefined
9414 10:55:45.887132 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 10:55:45.890315 in-header: 03 f9 00 00 02 00 00 00
9416 10:55:45.893453 in-data: 02 00
9417 10:55:45.896776 ADC[4]: Raw value=903770 ID=7
9418 10:55:45.897200 ADC[3]: Raw value=213652 ID=1
9419 10:55:45.900799 RAM Code: 0x71
9420 10:55:45.903660 ADC[6]: Raw value=75036 ID=0
9421 10:55:45.906920 ADC[5]: Raw value=212543 ID=1
9422 10:55:45.907344 SKU Code: 0x1
9423 10:55:45.913284 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9424 10:55:45.913711 coreboot table: 964 bytes.
9425 10:55:45.916449 IMD ROOT 0. 0xfffff000 0x00001000
9426 10:55:45.919840 IMD SMALL 1. 0xffffe000 0x00001000
9427 10:55:45.922979 RO MCACHE 2. 0xffffc000 0x00001104
9428 10:55:45.927376 CONSOLE 3. 0xfff7c000 0x00080000
9429 10:55:45.930087 FMAP 4. 0xfff7b000 0x00000452
9430 10:55:45.932992 TIME STAMP 5. 0xfff7a000 0x00000910
9431 10:55:45.936946 VBOOT WORK 6. 0xfff66000 0x00014000
9432 10:55:45.939417 RAMOOPS 7. 0xffe66000 0x00100000
9433 10:55:45.943350 COREBOOT 8. 0xffe64000 0x00002000
9434 10:55:45.946671 IMD small region:
9435 10:55:45.949360 IMD ROOT 0. 0xffffec00 0x00000400
9436 10:55:45.953266 VPD 1. 0xffffeba0 0x0000004c
9437 10:55:45.955890 MMC STATUS 2. 0xffffeb80 0x00000004
9438 10:55:45.962536 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 10:55:45.962967 Probing TPM: done!
9440 10:55:45.969769 Connected to device vid:did:rid of 1ae0:0028:00
9441 10:55:45.975687 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9442 10:55:45.979435 Initialized TPM device CR50 revision 0
9443 10:55:45.982974 Checking cr50 for pending updates
9444 10:55:45.987704 Reading cr50 TPM mode
9445 10:55:45.996649 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 10:55:46.003505 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 10:55:46.043546 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9448 10:55:46.046798 Checking segment from ROM address 0x40100000
9449 10:55:46.050174 Checking segment from ROM address 0x4010001c
9450 10:55:46.056929 Loading segment from ROM address 0x40100000
9451 10:55:46.057361 code (compression=0)
9452 10:55:46.066551 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 10:55:46.073443 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 10:55:46.073875 it's not compressed!
9455 10:55:46.080316 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 10:55:46.086813 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 10:55:46.104221 Loading segment from ROM address 0x4010001c
9458 10:55:46.104743 Entry Point 0x80000000
9459 10:55:46.107330 Loaded segments
9460 10:55:46.110510 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 10:55:46.117352 Jumping to boot code at 0x80000000(0xffe64000)
9462 10:55:46.123520 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 10:55:46.130485 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 10:55:46.138341 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9465 10:55:46.142038 Checking segment from ROM address 0x40100000
9466 10:55:46.144920 Checking segment from ROM address 0x4010001c
9467 10:55:46.151516 Loading segment from ROM address 0x40100000
9468 10:55:46.151705 code (compression=1)
9469 10:55:46.158175 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 10:55:46.167846 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 10:55:46.167990 using LZMA
9472 10:55:46.176664 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 10:55:46.183416 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 10:55:46.186345 Loading segment from ROM address 0x4010001c
9475 10:55:46.186420 Entry Point 0x54601000
9476 10:55:46.189600 Loaded segments
9477 10:55:46.192650 NOTICE: MT8192 bl31_setup
9478 10:55:46.200295 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 10:55:46.203917 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 10:55:46.206806 WARNING: region 0:
9481 10:55:46.210549 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 10:55:46.210981 WARNING: region 1:
9483 10:55:46.217903 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 10:55:46.220632 WARNING: region 2:
9485 10:55:46.223853 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 10:55:46.227111 WARNING: region 3:
9487 10:55:46.230371 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 10:55:46.233383 WARNING: region 4:
9489 10:55:46.240108 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 10:55:46.240673 WARNING: region 5:
9491 10:55:46.243961 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 10:55:46.247133 WARNING: region 6:
9493 10:55:46.250543 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 10:55:46.253537 WARNING: region 7:
9495 10:55:46.256569 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 10:55:46.263577 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 10:55:46.266888 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 10:55:46.269867 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 10:55:46.276606 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 10:55:46.279789 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 10:55:46.286506 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 10:55:46.289749 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 10:55:46.293409 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 10:55:46.299806 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 10:55:46.302909 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 10:55:46.306371 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 10:55:46.313404 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 10:55:46.316991 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 10:55:46.322932 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 10:55:46.326352 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 10:55:46.329849 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 10:55:46.336100 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 10:55:46.339454 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 10:55:46.346124 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 10:55:46.349589 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 10:55:46.352609 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 10:55:46.359405 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 10:55:46.362481 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 10:55:46.365745 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 10:55:46.372807 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 10:55:46.375922 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 10:55:46.382301 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 10:55:46.385259 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 10:55:46.392079 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 10:55:46.395345 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 10:55:46.398909 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 10:55:46.405363 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 10:55:46.408626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 10:55:46.411558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 10:55:46.415226 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 10:55:46.422059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 10:55:46.425984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 10:55:46.428899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 10:55:46.431991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 10:55:46.438505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 10:55:46.441978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 10:55:46.445479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 10:55:46.451703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 10:55:46.455390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 10:55:46.458805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 10:55:46.461826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 10:55:46.468089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 10:55:46.471612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 10:55:46.475019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 10:55:46.481682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 10:55:46.484812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 10:55:46.491488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 10:55:46.494888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 10:55:46.498042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 10:55:46.505065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 10:55:46.508239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 10:55:46.514828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 10:55:46.518418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 10:55:46.525213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 10:55:46.528722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 10:55:46.535125 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 10:55:46.538019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 10:55:46.541659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 10:55:46.548259 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 10:55:46.551596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 10:55:46.558815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 10:55:46.561956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 10:55:46.568183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 10:55:46.571764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 10:55:46.574836 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 10:55:46.581291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 10:55:46.584778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 10:55:46.591196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 10:55:46.594413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 10:55:46.600768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 10:55:46.604142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 10:55:46.610701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 10:55:46.614376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 10:55:46.617506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 10:55:46.624094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 10:55:46.627279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 10:55:46.633767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 10:55:46.637453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 10:55:46.644350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 10:55:46.647046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 10:55:46.650642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 10:55:46.657312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 10:55:46.660303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 10:55:46.667332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 10:55:46.670471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 10:55:46.677337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 10:55:46.680271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 10:55:46.686825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 10:55:46.690586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 10:55:46.694189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 10:55:46.700645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 10:55:46.704001 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 10:55:46.706608 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 10:55:46.713464 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 10:55:46.717185 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 10:55:46.720485 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 10:55:46.727070 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 10:55:46.730560 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 10:55:46.733821 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 10:55:46.740871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 10:55:46.743659 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 10:55:46.750168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 10:55:46.753654 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 10:55:46.757021 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 10:55:46.763554 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 10:55:46.767120 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 10:55:46.773563 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 10:55:46.776507 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 10:55:46.783472 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 10:55:46.786673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 10:55:46.790358 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 10:55:46.793678 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 10:55:46.799992 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 10:55:46.803684 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 10:55:46.806986 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 10:55:46.813356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 10:55:46.816989 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 10:55:46.820120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 10:55:46.823288 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 10:55:46.829808 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 10:55:46.833574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 10:55:46.840048 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 10:55:46.842963 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 10:55:46.846440 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 10:55:46.852860 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 10:55:46.856466 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 10:55:46.862893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 10:55:46.866279 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 10:55:46.869981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 10:55:46.876812 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 10:55:46.880017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 10:55:46.886137 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 10:55:46.889621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 10:55:46.892626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 10:55:46.899539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 10:55:46.902388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 10:55:46.906388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 10:55:46.912188 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 10:55:46.915488 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 10:55:46.922361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 10:55:46.925784 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 10:55:46.928802 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 10:55:46.935392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 10:55:46.938719 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 10:55:46.946005 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 10:55:46.948884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 10:55:46.951949 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 10:55:46.958554 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 10:55:46.962179 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 10:55:46.968474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 10:55:46.972017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 10:55:46.975177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 10:55:46.981653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 10:55:46.985120 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 10:55:46.991541 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 10:55:46.995298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 10:55:46.999318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 10:55:47.005229 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 10:55:47.008671 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 10:55:47.015350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 10:55:47.018705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 10:55:47.022052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 10:55:47.028778 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 10:55:47.031462 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 10:55:47.038269 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 10:55:47.041533 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 10:55:47.045288 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 10:55:47.051380 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 10:55:47.054853 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 10:55:47.061114 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 10:55:47.064449 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 10:55:47.067866 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 10:55:47.074342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 10:55:47.078157 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 10:55:47.084512 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 10:55:47.087672 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 10:55:47.090833 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 10:55:47.097548 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 10:55:47.100577 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 10:55:47.107650 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 10:55:47.110717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 10:55:47.113716 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 10:55:47.120762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 10:55:47.123772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 10:55:47.130404 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 10:55:47.133810 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 10:55:47.140201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 10:55:47.143381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 10:55:47.147072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 10:55:47.153348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 10:55:47.157021 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 10:55:47.163113 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 10:55:47.167054 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 10:55:47.173248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 10:55:47.177063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 10:55:47.179882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 10:55:47.186236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 10:55:47.189760 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 10:55:47.196156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 10:55:47.199037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 10:55:47.206185 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 10:55:47.209353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 10:55:47.212415 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 10:55:47.218936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 10:55:47.222117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 10:55:47.229481 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 10:55:47.232114 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 10:55:47.239217 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 10:55:47.242536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 10:55:47.245494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 10:55:47.252226 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 10:55:47.255212 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 10:55:47.261992 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 10:55:47.265259 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 10:55:47.271947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 10:55:47.275124 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 10:55:47.278908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 10:55:47.284918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 10:55:47.288435 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 10:55:47.294720 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 10:55:47.298597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 10:55:47.305057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 10:55:47.308477 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 10:55:47.311908 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 10:55:47.318166 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 10:55:47.321530 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 10:55:47.324877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 10:55:47.328122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 10:55:47.334735 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 10:55:47.338251 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 10:55:47.341098 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 10:55:47.347650 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 10:55:47.351462 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 10:55:47.355023 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 10:55:47.361288 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 10:55:47.364862 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 10:55:47.371301 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 10:55:47.374237 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 10:55:47.377505 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 10:55:47.384259 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 10:55:47.387353 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 10:55:47.391230 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 10:55:47.397592 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 10:55:47.400482 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 10:55:47.407431 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 10:55:47.410710 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 10:55:47.414070 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 10:55:47.420438 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 10:55:47.423418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 10:55:47.427053 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 10:55:47.433729 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 10:55:47.436911 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 10:55:47.443285 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 10:55:47.446522 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 10:55:47.449786 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 10:55:47.456120 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 10:55:47.459505 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 10:55:47.466200 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 10:55:47.469619 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 10:55:47.472759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 10:55:47.479238 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 10:55:47.482851 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 10:55:47.485690 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 10:55:47.492675 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 10:55:47.496032 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 10:55:47.499272 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 10:55:47.502787 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 10:55:47.509010 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 10:55:47.512452 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 10:55:47.515861 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 10:55:47.518790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 10:55:47.525697 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 10:55:47.529375 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 10:55:47.532131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 10:55:47.535586 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 10:55:47.542283 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 10:55:47.545345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 10:55:47.548638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 10:55:47.555646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 10:55:47.558772 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 10:55:47.565173 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 10:55:47.568294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 10:55:47.574838 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 10:55:47.578253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 10:55:47.581288 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 10:55:47.588202 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 10:55:47.591390 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 10:55:47.597815 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 10:55:47.601335 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 10:55:47.608000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 10:55:47.611308 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 10:55:47.614552 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 10:55:47.620999 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 10:55:47.624122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 10:55:47.630867 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 10:55:47.634334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 10:55:47.637264 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 10:55:47.643945 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 10:55:47.647116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 10:55:47.653940 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 10:55:47.657287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 10:55:47.660840 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 10:55:47.667132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 10:55:47.670692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 10:55:47.677084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 10:55:47.680102 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 10:55:47.686921 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 10:55:47.690121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 10:55:47.693177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 10:55:47.699787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 10:55:47.703489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 10:55:47.710428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 10:55:47.713429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 10:55:47.719790 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 10:55:47.722989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 10:55:47.726730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 10:55:47.733435 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 10:55:47.736495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 10:55:47.743251 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 10:55:47.746684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 10:55:47.750021 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 10:55:47.756503 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 10:55:47.759777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 10:55:47.766462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 10:55:47.770428 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 10:55:47.773283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 10:55:47.778967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 10:55:47.782538 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 10:55:47.788854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 10:55:47.792525 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 10:55:47.798937 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 10:55:47.802216 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 10:55:47.805674 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 10:55:47.812026 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 10:55:47.815732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 10:55:47.822412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 10:55:47.825467 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 10:55:47.831907 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 10:55:47.835272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 10:55:47.838377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 10:55:47.845184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 10:55:47.848531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 10:55:47.854987 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 10:55:47.858599 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 10:55:47.862094 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 10:55:47.868528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 10:55:47.872079 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 10:55:47.878493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 10:55:47.882055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 10:55:47.885237 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 10:55:47.892092 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 10:55:47.895228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 10:55:47.902188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 10:55:47.905404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 10:55:47.912457 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 10:55:47.915133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 10:55:47.918701 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 10:55:47.924877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 10:55:47.928747 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 10:55:47.935205 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 10:55:47.938162 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 10:55:47.944761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 10:55:47.948403 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 10:55:47.954501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 10:55:47.957656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 10:55:47.964575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 10:55:47.968076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 10:55:47.970977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 10:55:47.977864 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 10:55:47.980746 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 10:55:47.987559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 10:55:47.990837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 10:55:47.997338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 10:55:48.000543 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 10:55:48.007422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 10:55:48.010912 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 10:55:48.013642 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 10:55:48.020823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 10:55:48.023815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 10:55:48.030319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 10:55:48.034297 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 10:55:48.040282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 10:55:48.043689 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 10:55:48.050238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 10:55:48.053279 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 10:55:48.057350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 10:55:48.063521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 10:55:48.066326 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 10:55:48.073136 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 10:55:48.076167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 10:55:48.083497 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 10:55:48.085928 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 10:55:48.092491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 10:55:48.096166 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 10:55:48.103176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 10:55:48.105722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 10:55:48.109146 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 10:55:48.115844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 10:55:48.119237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 10:55:48.126126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 10:55:48.130138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 10:55:48.135577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 10:55:48.139046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 10:55:48.142169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 10:55:48.149686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 10:55:48.152246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 10:55:48.158634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 10:55:48.161842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 10:55:48.168868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 10:55:48.172192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 10:55:48.179221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 10:55:48.181853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 10:55:48.188419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 10:55:48.191905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 10:55:48.198656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 10:55:48.201517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 10:55:48.208900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 10:55:48.211361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 10:55:48.218356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 10:55:48.221142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 10:55:48.227964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 10:55:48.234166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 10:55:48.237952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 10:55:48.243977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 10:55:48.247525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 10:55:48.254359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 10:55:48.257553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 10:55:48.263909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 10:55:48.267887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 10:55:48.270788 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 10:55:48.274237 INFO: [APUAPC] vio 0
9932 10:55:48.280426 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 10:55:48.283740 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 10:55:48.287478 INFO: [APUAPC] D0_APC_0: 0x400510
9935 10:55:48.290258 INFO: [APUAPC] D0_APC_1: 0x0
9936 10:55:48.293790 INFO: [APUAPC] D0_APC_2: 0x1540
9937 10:55:48.297241 INFO: [APUAPC] D0_APC_3: 0x0
9938 10:55:48.300785 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 10:55:48.303739 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 10:55:48.307086 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 10:55:48.307169 INFO: [APUAPC] D1_APC_3: 0x0
9942 10:55:48.313421 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 10:55:48.317432 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 10:55:48.320735 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 10:55:48.320819 INFO: [APUAPC] D2_APC_3: 0x0
9946 10:55:48.323747 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 10:55:48.330661 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 10:55:48.333627 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 10:55:48.333715 INFO: [APUAPC] D3_APC_3: 0x0
9950 10:55:48.336479 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 10:55:48.340364 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 10:55:48.343510 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 10:55:48.347060 INFO: [APUAPC] D4_APC_3: 0x0
9954 10:55:48.350101 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 10:55:48.353174 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 10:55:48.356351 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 10:55:48.359985 INFO: [APUAPC] D5_APC_3: 0x0
9958 10:55:48.363144 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 10:55:48.366283 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 10:55:48.369778 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 10:55:48.372686 INFO: [APUAPC] D6_APC_3: 0x0
9962 10:55:48.376053 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 10:55:48.379600 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 10:55:48.383225 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 10:55:48.386589 INFO: [APUAPC] D7_APC_3: 0x0
9966 10:55:48.389185 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 10:55:48.392709 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 10:55:48.395848 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 10:55:48.399402 INFO: [APUAPC] D8_APC_3: 0x0
9970 10:55:48.402752 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 10:55:48.405982 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 10:55:48.409785 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 10:55:48.412431 INFO: [APUAPC] D9_APC_3: 0x0
9974 10:55:48.416186 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 10:55:48.418995 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 10:55:48.422443 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 10:55:48.426047 INFO: [APUAPC] D10_APC_3: 0x0
9978 10:55:48.429082 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 10:55:48.432221 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 10:55:48.435830 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 10:55:48.438817 INFO: [APUAPC] D11_APC_3: 0x0
9982 10:55:48.441970 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 10:55:48.445067 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 10:55:48.448506 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 10:55:48.451973 INFO: [APUAPC] D12_APC_3: 0x0
9986 10:55:48.455376 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 10:55:48.458744 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 10:55:48.462075 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 10:55:48.465608 INFO: [APUAPC] D13_APC_3: 0x0
9990 10:55:48.468844 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 10:55:48.471894 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 10:55:48.475343 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 10:55:48.478316 INFO: [APUAPC] D14_APC_3: 0x0
9994 10:55:48.481476 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 10:55:48.485341 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 10:55:48.488630 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 10:55:48.492369 INFO: [APUAPC] D15_APC_3: 0x0
9998 10:55:48.494851 INFO: [APUAPC] APC_CON: 0x4
9999 10:55:48.498575 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 10:55:48.501568 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 10:55:48.505044 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 10:55:48.508400 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 10:55:48.511411 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 10:55:48.514395 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 10:55:48.517664 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 10:55:48.517747 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 10:55:48.521066 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 10:55:48.524741 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 10:55:48.527738 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 10:55:48.531063 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 10:55:48.534233 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 10:55:48.537840 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 10:55:48.540610 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 10:55:48.544602 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 10:55:48.547670 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 10:55:48.550619 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 10:55:48.554435 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 10:55:48.554518 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 10:55:48.557513 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 10:55:48.560940 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 10:55:48.564245 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 10:55:48.567014 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 10:55:48.570703 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 10:55:48.574390 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 10:55:48.577113 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 10:55:48.580576 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 10:55:48.584285 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 10:55:48.587326 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 10:55:48.590741 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 10:55:48.593729 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 10:55:48.597022 INFO: [NOCDAPC] APC_CON: 0x4
10032 10:55:48.600959 INFO: [APUAPC] set_apusys_apc done
10033 10:55:48.603599 INFO: [DEVAPC] devapc_init done
10034 10:55:48.607243 INFO: GICv3 without legacy support detected.
10035 10:55:48.610221 INFO: ARM GICv3 driver initialized in EL3
10036 10:55:48.613952 INFO: Maximum SPI INTID supported: 639
10037 10:55:48.617221 INFO: BL31: Initializing runtime services
10038 10:55:48.623770 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 10:55:48.626872 INFO: SPM: enable CPC mode
10040 10:55:48.633842 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 10:55:48.636426 INFO: BL31: Preparing for EL3 exit to normal world
10042 10:55:48.639805 INFO: Entry point address = 0x80000000
10043 10:55:48.643655 INFO: SPSR = 0x8
10044 10:55:48.648304
10045 10:55:48.648389
10046 10:55:48.648458
10047 10:55:48.651113 Starting depthcharge on Spherion...
10048 10:55:48.651195
10049 10:55:48.651264 Wipe memory regions:
10050 10:55:48.651332
10051 10:55:48.651984 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 10:55:48.652105 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 10:55:48.652203 Setting prompt string to ['asurada:']
10054 10:55:48.652292 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 10:55:48.654504 [0x00000040000000, 0x00000054600000)
10056 10:55:48.776866
10057 10:55:48.777020 [0x00000054660000, 0x00000080000000)
10058 10:55:49.037347
10059 10:55:49.037504 [0x000000821a7280, 0x000000ffe64000)
10060 10:55:49.782525
10061 10:55:49.782684 [0x00000100000000, 0x00000240000000)
10062 10:55:51.672660
10063 10:55:51.675963 Initializing XHCI USB controller at 0x11200000.
10064 10:55:52.657170
10065 10:55:52.657330 R8152: Initializing
10066 10:55:52.657404
10067 10:55:52.660423 Version 9 (ocp_data = 6010)
10068 10:55:52.660504
10069 10:55:52.663673 R8152: Done initializing
10070 10:55:52.663755
10071 10:55:52.663818 Adding net device
10072 10:55:53.185617
10073 10:55:53.188923 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10074 10:55:53.189335
10075 10:55:53.189660
10076 10:55:53.189966
10077 10:55:53.190674 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10079 10:55:53.291765 asurada: tftpboot 192.168.201.1 10591017/tftp-deploy-nytt7b6b/kernel/image.itb 10591017/tftp-deploy-nytt7b6b/kernel/cmdline
10080 10:55:53.292323 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 10:55:53.292782 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10082 10:55:53.296981 tftpboot 192.168.201.1 10591017/tftp-deploy-nytt7b6b/kernel/image.itp-deploy-nytt7b6b/kernel/cmdline
10083 10:55:53.297401
10084 10:55:53.297728 Waiting for link
10085 10:55:53.499294
10086 10:55:53.499762 done.
10087 10:55:53.500096
10088 10:55:53.500403 MAC: f4:f5:e8:50:de:0a
10089 10:55:53.500765
10090 10:55:53.502797 Sending DHCP discover... done.
10091 10:55:53.503209
10092 10:55:53.505910 Waiting for reply... done.
10093 10:55:53.506325
10094 10:55:53.508927 Sending DHCP request... done.
10095 10:55:53.509344
10096 10:55:53.521300 Waiting for reply... done.
10097 10:55:53.521718
10098 10:55:53.522049 My ip is 192.168.201.14
10099 10:55:53.522360
10100 10:55:53.524094 The DHCP server ip is 192.168.201.1
10101 10:55:53.524508
10102 10:55:53.531075 TFTP server IP predefined by user: 192.168.201.1
10103 10:55:53.531492
10104 10:55:53.537948 Bootfile predefined by user: 10591017/tftp-deploy-nytt7b6b/kernel/image.itb
10105 10:55:53.538363
10106 10:55:53.541384 Sending tftp read request... done.
10107 10:55:53.541797
10108 10:55:53.546369 Waiting for the transfer...
10109 10:55:53.546788
10110 10:55:53.806251 00000000 ################################################################
10111 10:55:53.806383
10112 10:55:54.044477 00080000 ################################################################
10113 10:55:54.044656
10114 10:55:54.271898 00100000 ################################################################
10115 10:55:54.272032
10116 10:55:54.495088 00180000 ################################################################
10117 10:55:54.495216
10118 10:55:54.716166 00200000 ################################################################
10119 10:55:54.716297
10120 10:55:54.938477 00280000 ################################################################
10121 10:55:54.938643
10122 10:55:55.166937 00300000 ################################################################
10123 10:55:55.167101
10124 10:55:55.394212 00380000 ################################################################
10125 10:55:55.394375
10126 10:55:55.620370 00400000 ################################################################
10127 10:55:55.620573
10128 10:55:55.846214 00480000 ################################################################
10129 10:55:55.846352
10130 10:55:56.076993 00500000 ################################################################
10131 10:55:56.077160
10132 10:55:56.302010 00580000 ################################################################
10133 10:55:56.302172
10134 10:55:56.529852 00600000 ################################################################
10135 10:55:56.530017
10136 10:55:56.754084 00680000 ################################################################
10137 10:55:56.754250
10138 10:55:56.993972 00700000 ################################################################
10139 10:55:56.994116
10140 10:55:57.217102 00780000 ################################################################
10141 10:55:57.217289
10142 10:55:57.457959 00800000 ################################################################
10143 10:55:57.458113
10144 10:55:57.687789 00880000 ################################################################
10145 10:55:57.687963
10146 10:55:57.913703 00900000 ################################################################
10147 10:55:57.913912
10148 10:55:58.126750 00980000 ################################################################
10149 10:55:58.126908
10150 10:55:58.337675 00a00000 ################################################################
10151 10:55:58.337893
10152 10:55:58.548315 00a80000 ################################################################
10153 10:55:58.548584
10154 10:55:58.759518 00b00000 ################################################################
10155 10:55:58.759694
10156 10:55:58.984407 00b80000 ################################################################
10157 10:55:58.984592
10158 10:55:59.218380 00c00000 ################################################################
10159 10:55:59.218512
10160 10:55:59.445211 00c80000 ################################################################
10161 10:55:59.445343
10162 10:55:59.692676 00d00000 ################################################################
10163 10:55:59.692809
10164 10:55:59.931327 00d80000 ################################################################
10165 10:55:59.931467
10166 10:56:00.168907 00e00000 ################################################################
10167 10:56:00.169042
10168 10:56:00.424284 00e80000 ################################################################
10169 10:56:00.424452
10170 10:56:00.661527 00f00000 ################################################################
10171 10:56:00.661682
10172 10:56:00.887312 00f80000 ################################################################
10173 10:56:00.887540
10174 10:56:01.113530 01000000 ################################################################
10175 10:56:01.113690
10176 10:56:01.344786 01080000 ################################################################
10177 10:56:01.344946
10178 10:56:01.582133 01100000 ################################################################
10179 10:56:01.582277
10180 10:56:01.814820 01180000 ################################################################
10181 10:56:01.814947
10182 10:56:02.059396 01200000 ################################################################
10183 10:56:02.059528
10184 10:56:02.308211 01280000 ################################################################
10185 10:56:02.308338
10186 10:56:02.541101 01300000 ################################################################
10187 10:56:02.541231
10188 10:56:02.781652 01380000 ################################################################
10189 10:56:02.781809
10190 10:56:03.029632 01400000 ################################################################
10191 10:56:03.029761
10192 10:56:03.269675 01480000 ################################################################
10193 10:56:03.269802
10194 10:56:03.509755 01500000 ################################################################
10195 10:56:03.509887
10196 10:56:03.733800 01580000 ################################################################
10197 10:56:03.733959
10198 10:56:03.978276 01600000 ################################################################
10199 10:56:03.978412
10200 10:56:04.208659 01680000 ################################################################
10201 10:56:04.208793
10202 10:56:04.433801 01700000 ################################################################
10203 10:56:04.433933
10204 10:56:04.667055 01780000 ################################################################
10205 10:56:04.667193
10206 10:56:04.912367 01800000 ################################################################
10207 10:56:04.912502
10208 10:56:05.156392 01880000 ################################################################
10209 10:56:05.156607
10210 10:56:05.412714 01900000 ################################################################
10211 10:56:05.412862
10212 10:56:05.683667 01980000 ################################################################
10213 10:56:05.683815
10214 10:56:05.929901 01a00000 ################################################################
10215 10:56:05.930082
10216 10:56:06.201886 01a80000 ################################################################
10217 10:56:06.202037
10218 10:56:06.434709 01b00000 ################################################################
10219 10:56:06.434862
10220 10:56:06.673734 01b80000 ################################################################
10221 10:56:06.673885
10222 10:56:06.905084 01c00000 ################################################################
10223 10:56:06.905239
10224 10:56:07.137964 01c80000 ################################################################
10225 10:56:07.138115
10226 10:56:07.377160 01d00000 ################################################################
10227 10:56:07.377313
10228 10:56:07.617341 01d80000 ################################################################
10229 10:56:07.617493
10230 10:56:07.859383 01e00000 ################################################################
10231 10:56:07.859588
10232 10:56:08.105941 01e80000 ################################################################
10233 10:56:08.106121
10234 10:56:08.371400 01f00000 ################################################################
10235 10:56:08.371599
10236 10:56:08.612512 01f80000 ################################################################
10237 10:56:08.612677
10238 10:56:08.859096 02000000 ################################################################
10239 10:56:08.859249
10240 10:56:09.107262 02080000 ################################################################
10241 10:56:09.107410
10242 10:56:09.338290 02100000 ################################################################
10243 10:56:09.338444
10244 10:56:09.568635 02180000 ################################################################
10245 10:56:09.568769
10246 10:56:09.815391 02200000 ################################################################
10247 10:56:09.815530
10248 10:56:10.055285 02280000 ################################################################
10249 10:56:10.055430
10250 10:56:10.321854 02300000 ################################################################
10251 10:56:10.322005
10252 10:56:10.572596 02380000 ################################################################
10253 10:56:10.572742
10254 10:56:10.846140 02400000 ################################################################
10255 10:56:10.846318
10256 10:56:11.111830 02480000 ################################################################
10257 10:56:11.111969
10258 10:56:11.348437 02500000 ################################################################
10259 10:56:11.348618
10260 10:56:11.610937 02580000 ################################################################
10261 10:56:11.611097
10262 10:56:11.854865 02600000 ################################################################
10263 10:56:11.855018
10264 10:56:12.117311 02680000 ################################################################
10265 10:56:12.117452
10266 10:56:12.373452 02700000 ################################################################
10267 10:56:12.373606
10268 10:56:12.628990 02780000 ################################################################
10269 10:56:12.629145
10270 10:56:12.873836 02800000 ################################################################
10271 10:56:12.874017
10272 10:56:13.116958 02880000 ################################################################
10273 10:56:13.117129
10274 10:56:13.365326 02900000 ################################################################
10275 10:56:13.365497
10276 10:56:13.619701 02980000 ################################################################
10277 10:56:13.619873
10278 10:56:13.873761 02a00000 ################################################################
10279 10:56:13.873913
10280 10:56:14.110213 02a80000 ################################################################
10281 10:56:14.110371
10282 10:56:14.333499 02b00000 ################################################################
10283 10:56:14.333707
10284 10:56:14.550917 02b80000 ################################################################
10285 10:56:14.551065
10286 10:56:14.773202 02c00000 ################################################################
10287 10:56:14.773369
10288 10:56:14.988929 02c80000 ################################################################
10289 10:56:14.989086
10290 10:56:15.246674 02d00000 ################################################################
10291 10:56:15.246961
10292 10:56:15.453698 02d80000 ################################################################
10293 10:56:15.453839
10294 10:56:15.708327 02e00000 ################################################################
10295 10:56:15.708484
10296 10:56:15.958450 02e80000 ################################################################
10297 10:56:15.958625
10298 10:56:16.182070 02f00000 ################################################################
10299 10:56:16.182230
10300 10:56:16.377148 02f80000 ######################################################### done.
10301 10:56:16.379956
10302 10:56:16.380056 The bootfile was 50272382 bytes long.
10303 10:56:16.383223
10304 10:56:16.383307 Sending tftp read request... done.
10305 10:56:16.383374
10306 10:56:16.387309 Waiting for the transfer...
10307 10:56:16.387396
10308 10:56:16.390468 00000000 # done.
10309 10:56:16.390553
10310 10:56:16.396409 Command line loaded dynamically from TFTP file: 10591017/tftp-deploy-nytt7b6b/kernel/cmdline
10311 10:56:16.396528
10312 10:56:16.409931 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10313 10:56:16.410043
10314 10:56:16.410116 Loading FIT.
10315 10:56:16.410179
10316 10:56:16.412759 Image ramdisk-1 has 40141485 bytes.
10317 10:56:16.412839
10318 10:56:16.416386 Image fdt-1 has 46924 bytes.
10319 10:56:16.416466
10320 10:56:16.420239 Image kernel-1 has 10081937 bytes.
10321 10:56:16.420318
10322 10:56:16.426583 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10323 10:56:16.426673
10324 10:56:16.446227 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10325 10:56:16.446357
10326 10:56:16.449996 Choosing best match conf-1 for compat google,spherion-rev2.
10327 10:56:16.454160
10328 10:56:16.459057 Connected to device vid:did:rid of 1ae0:0028:00
10329 10:56:16.466270
10330 10:56:16.469159 tpm_get_response: command 0x17b, return code 0x0
10331 10:56:16.469248
10332 10:56:16.472940 ec_init: CrosEC protocol v3 supported (256, 248)
10333 10:56:16.476436
10334 10:56:16.480296 tpm_cleanup: add release locality here.
10335 10:56:16.480383
10336 10:56:16.480449 Shutting down all USB controllers.
10337 10:56:16.482901
10338 10:56:16.482998 Removing current net device
10339 10:56:16.483094
10340 10:56:16.490288 Exiting depthcharge with code 4 at timestamp: 57210812
10341 10:56:16.490377
10342 10:56:16.493356 LZMA decompressing kernel-1 to 0x821a6718
10343 10:56:16.493440
10344 10:56:16.496440 LZMA decompressing kernel-1 to 0x40000000
10345 10:56:17.762865
10346 10:56:17.763007 jumping to kernel
10347 10:56:17.763432 end: 2.2.4 bootloader-commands (duration 00:00:29) [common]
10348 10:56:17.763534 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10349 10:56:17.763611 Setting prompt string to ['Linux version [0-9]']
10350 10:56:17.763682 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10351 10:56:17.763751 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10352 10:56:17.844213
10353 10:56:17.847508 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10354 10:56:17.851015 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10355 10:56:17.851142 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10356 10:56:17.851327 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10357 10:56:17.851461 Using line separator: #'\n'#
10358 10:56:17.851569 No login prompt set.
10359 10:56:17.851635 Parsing kernel messages
10360 10:56:17.851695 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10361 10:56:17.851834 [login-action] Waiting for messages, (timeout 00:03:56)
10362 10:56:17.870957 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10363 10:56:17.874022 [ 0.000000] random: crng init done
10364 10:56:17.877287 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10365 10:56:17.880726 [ 0.000000] efi: UEFI not found.
10366 10:56:17.890539 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10367 10:56:17.897030 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10368 10:56:17.906834 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10369 10:56:17.917081 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10370 10:56:17.924128 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10371 10:56:17.926682 [ 0.000000] printk: bootconsole [mtk8250] enabled
10372 10:56:17.936447 [ 0.000000] NUMA: No NUMA configuration found
10373 10:56:17.942337 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10374 10:56:17.949362 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10375 10:56:17.949450 [ 0.000000] Zone ranges:
10376 10:56:17.955270 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10377 10:56:17.958873 [ 0.000000] DMA32 empty
10378 10:56:17.965507 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10379 10:56:17.969331 [ 0.000000] Movable zone start for each node
10380 10:56:17.972406 [ 0.000000] Early memory node ranges
10381 10:56:17.978712 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10382 10:56:17.985280 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10383 10:56:17.991471 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10384 10:56:17.997987 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10385 10:56:18.004992 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10386 10:56:18.011367 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10387 10:56:18.068460 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10388 10:56:18.075184 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10389 10:56:18.081923 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10390 10:56:18.084645 [ 0.000000] psci: probing for conduit method from DT.
10391 10:56:18.091173 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10392 10:56:18.094542 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10393 10:56:18.101147 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10394 10:56:18.105433 [ 0.000000] psci: SMC Calling Convention v1.2
10395 10:56:18.111496 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10396 10:56:18.114663 [ 0.000000] Detected VIPT I-cache on CPU0
10397 10:56:18.121284 [ 0.000000] CPU features: detected: GIC system register CPU interface
10398 10:56:18.127771 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10399 10:56:18.134250 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10400 10:56:18.140926 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10401 10:56:18.150783 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10402 10:56:18.157311 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10403 10:56:18.160441 [ 0.000000] alternatives: applying boot alternatives
10404 10:56:18.167504 [ 0.000000] Fallback order for Node 0: 0
10405 10:56:18.173722 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10406 10:56:18.177195 [ 0.000000] Policy zone: Normal
10407 10:56:18.190335 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10408 10:56:18.200685 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10409 10:56:18.210506 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10410 10:56:18.220188 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10411 10:56:18.227243 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10412 10:56:18.230420 <6>[ 0.000000] software IO TLB: area num 8.
10413 10:56:18.286991 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10414 10:56:18.436131 <6>[ 0.000000] Memory: 7933740K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419028K reserved, 32768K cma-reserved)
10415 10:56:18.442422 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10416 10:56:18.449075 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10417 10:56:18.452449 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10418 10:56:18.459155 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10419 10:56:18.465856 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10420 10:56:18.469173 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10421 10:56:18.479112 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10422 10:56:18.485748 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10423 10:56:18.492348 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10424 10:56:18.498758 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10425 10:56:18.501924 <6>[ 0.000000] GICv3: 608 SPIs implemented
10426 10:56:18.505626 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10427 10:56:18.512216 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10428 10:56:18.515445 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10429 10:56:18.521792 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10430 10:56:18.535522 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10431 10:56:18.548423 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10432 10:56:18.555676 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10433 10:56:18.562691 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10434 10:56:18.576084 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10435 10:56:18.582967 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10436 10:56:18.589686 <6>[ 0.009178] Console: colour dummy device 80x25
10437 10:56:18.599047 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10438 10:56:18.606301 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10439 10:56:18.609379 <6>[ 0.029286] LSM: Security Framework initializing
10440 10:56:18.615845 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 10:56:18.626277 <6>[ 0.042117] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10442 10:56:18.635306 <6>[ 0.051585] cblist_init_generic: Setting adjustable number of callback queues.
10443 10:56:18.642066 <6>[ 0.059039] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 10:56:18.645595 <6>[ 0.065376] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 10:56:18.652000 <6>[ 0.071786] rcu: Hierarchical SRCU implementation.
10446 10:56:18.658865 <6>[ 0.076829] rcu: Max phase no-delay instances is 1000.
10447 10:56:18.665327 <6>[ 0.083848] EFI services will not be available.
10448 10:56:18.668270 <6>[ 0.088825] smp: Bringing up secondary CPUs ...
10449 10:56:18.676291 <6>[ 0.093878] Detected VIPT I-cache on CPU1
10450 10:56:18.682642 <6>[ 0.093951] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 10:56:18.689908 <6>[ 0.093983] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 10:56:18.693453 <6>[ 0.094320] Detected VIPT I-cache on CPU2
10453 10:56:18.699449 <6>[ 0.094374] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 10:56:18.706196 <6>[ 0.094390] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 10:56:18.712747 <6>[ 0.094653] Detected VIPT I-cache on CPU3
10456 10:56:18.719652 <6>[ 0.094701] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 10:56:18.725826 <6>[ 0.094715] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 10:56:18.729415 <6>[ 0.095021] CPU features: detected: Spectre-v4
10459 10:56:18.735851 <6>[ 0.095027] CPU features: detected: Spectre-BHB
10460 10:56:18.739072 <6>[ 0.095033] Detected PIPT I-cache on CPU4
10461 10:56:18.746170 <6>[ 0.095091] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 10:56:18.752502 <6>[ 0.095109] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 10:56:18.758864 <6>[ 0.095404] Detected PIPT I-cache on CPU5
10464 10:56:18.765418 <6>[ 0.095465] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 10:56:18.772190 <6>[ 0.095481] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 10:56:18.775809 <6>[ 0.095765] Detected PIPT I-cache on CPU6
10467 10:56:18.782013 <6>[ 0.095831] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 10:56:18.788606 <6>[ 0.095847] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 10:56:18.795133 <6>[ 0.096144] Detected PIPT I-cache on CPU7
10470 10:56:18.802053 <6>[ 0.096211] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 10:56:18.808711 <6>[ 0.096226] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 10:56:18.811723 <6>[ 0.096275] smp: Brought up 1 node, 8 CPUs
10473 10:56:18.818236 <6>[ 0.237599] SMP: Total of 8 processors activated.
10474 10:56:18.821966 <6>[ 0.242520] CPU features: detected: 32-bit EL0 Support
10475 10:56:18.831719 <6>[ 0.247883] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 10:56:18.838019 <6>[ 0.256683] CPU features: detected: Common not Private translations
10477 10:56:18.845264 <6>[ 0.263199] CPU features: detected: CRC32 instructions
10478 10:56:18.847926 <6>[ 0.268583] CPU features: detected: RCpc load-acquire (LDAPR)
10479 10:56:18.854912 <6>[ 0.274542] CPU features: detected: LSE atomic instructions
10480 10:56:18.861449 <6>[ 0.280323] CPU features: detected: Privileged Access Never
10481 10:56:18.868268 <6>[ 0.286103] CPU features: detected: RAS Extension Support
10482 10:56:18.874801 <6>[ 0.291711] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 10:56:18.877992 <6>[ 0.298977] CPU: All CPU(s) started at EL2
10484 10:56:18.884082 <6>[ 0.303293] alternatives: applying system-wide alternatives
10485 10:56:18.894199 <6>[ 0.313991] devtmpfs: initialized
10486 10:56:18.909757 <6>[ 0.323116] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 10:56:18.916010 <6>[ 0.333083] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 10:56:18.922740 <6>[ 0.341323] pinctrl core: initialized pinctrl subsystem
10489 10:56:18.926579 <6>[ 0.347951] DMI not present or invalid.
10490 10:56:18.932911 <6>[ 0.352355] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 10:56:18.942748 <6>[ 0.359246] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 10:56:18.949662 <6>[ 0.366820] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 10:56:18.959380 <6>[ 0.375042] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 10:56:18.962420 <6>[ 0.383285] audit: initializing netlink subsys (disabled)
10495 10:56:18.972460 <5>[ 0.388980] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10496 10:56:18.978959 <6>[ 0.389692] thermal_sys: Registered thermal governor 'step_wise'
10497 10:56:18.985445 <6>[ 0.396947] thermal_sys: Registered thermal governor 'power_allocator'
10498 10:56:18.989125 <6>[ 0.403202] cpuidle: using governor menu
10499 10:56:18.995771 <6>[ 0.414165] NET: Registered PF_QIPCRTR protocol family
10500 10:56:19.001813 <6>[ 0.419640] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 10:56:19.008861 <6>[ 0.426740] ASID allocator initialised with 32768 entries
10502 10:56:19.011748 <6>[ 0.433313] Serial: AMBA PL011 UART driver
10503 10:56:19.021795 <4>[ 0.441972] Trying to register duplicate clock ID: 134
10504 10:56:19.075579 <6>[ 0.499098] KASLR enabled
10505 10:56:19.090230 <6>[ 0.506916] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 10:56:19.096873 <6>[ 0.513932] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 10:56:19.103743 <6>[ 0.520423] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 10:56:19.110137 <6>[ 0.527430] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 10:56:19.116467 <6>[ 0.533921] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 10:56:19.123001 <6>[ 0.540923] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 10:56:19.130175 <6>[ 0.547407] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 10:56:19.136462 <6>[ 0.554411] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 10:56:19.139813 <6>[ 0.561921] ACPI: Interpreter disabled.
10514 10:56:19.148483 <6>[ 0.568293] iommu: Default domain type: Translated
10515 10:56:19.154656 <6>[ 0.573406] iommu: DMA domain TLB invalidation policy: strict mode
10516 10:56:19.158021 <5>[ 0.580060] SCSI subsystem initialized
10517 10:56:19.164884 <6>[ 0.584223] usbcore: registered new interface driver usbfs
10518 10:56:19.171339 <6>[ 0.589957] usbcore: registered new interface driver hub
10519 10:56:19.174679 <6>[ 0.595509] usbcore: registered new device driver usb
10520 10:56:19.181329 <6>[ 0.601586] pps_core: LinuxPPS API ver. 1 registered
10521 10:56:19.191959 <6>[ 0.606781] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 10:56:19.194688 <6>[ 0.616121] PTP clock support registered
10523 10:56:19.198091 <6>[ 0.620364] EDAC MC: Ver: 3.0.0
10524 10:56:19.205255 <6>[ 0.625518] FPGA manager framework
10525 10:56:19.212145 <6>[ 0.629199] Advanced Linux Sound Architecture Driver Initialized.
10526 10:56:19.215179 <6>[ 0.635971] vgaarb: loaded
10527 10:56:19.221501 <6>[ 0.639132] clocksource: Switched to clocksource arch_sys_counter
10528 10:56:19.225109 <5>[ 0.645574] VFS: Disk quotas dquot_6.6.0
10529 10:56:19.231477 <6>[ 0.649755] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 10:56:19.235286 <6>[ 0.656947] pnp: PnP ACPI: disabled
10531 10:56:19.244169 <6>[ 0.663713] NET: Registered PF_INET protocol family
10532 10:56:19.253467 <6>[ 0.669294] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 10:56:19.264861 <6>[ 0.681599] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 10:56:19.274507 <6>[ 0.690416] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 10:56:19.281146 <6>[ 0.698387] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 10:56:19.290980 <6>[ 0.707086] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 10:56:19.297588 <6>[ 0.716806] TCP: Hash tables configured (established 65536 bind 65536)
10538 10:56:19.304559 <6>[ 0.723657] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 10:56:19.314084 <6>[ 0.730854] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 10:56:19.321035 <6>[ 0.738555] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 10:56:19.327232 <6>[ 0.744729] RPC: Registered named UNIX socket transport module.
10542 10:56:19.330810 <6>[ 0.750886] RPC: Registered udp transport module.
10543 10:56:19.337206 <6>[ 0.755818] RPC: Registered tcp transport module.
10544 10:56:19.343842 <6>[ 0.760747] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 10:56:19.347611 <6>[ 0.767415] PCI: CLS 0 bytes, default 64
10546 10:56:19.350357 <6>[ 0.771808] Unpacking initramfs...
10547 10:56:19.360488 <6>[ 0.775901] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 10:56:19.367108 <6>[ 0.784534] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 10:56:19.374285 <6>[ 0.793367] kvm [1]: IPA Size Limit: 40 bits
10550 10:56:19.377221 <6>[ 0.797892] kvm [1]: GICv3: no GICV resource entry
10551 10:56:19.383356 <6>[ 0.802909] kvm [1]: disabling GICv2 emulation
10552 10:56:19.390024 <6>[ 0.807592] kvm [1]: GIC system register CPU interface enabled
10553 10:56:19.393438 <6>[ 0.813755] kvm [1]: vgic interrupt IRQ18
10554 10:56:19.399989 <6>[ 0.818110] kvm [1]: VHE mode initialized successfully
10555 10:56:19.403321 <5>[ 0.824419] Initialise system trusted keyrings
10556 10:56:19.409761 <6>[ 0.829179] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 10:56:19.419265 <6>[ 0.839254] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 10:56:19.425778 <5>[ 0.845619] NFS: Registering the id_resolver key type
10559 10:56:19.429618 <5>[ 0.850916] Key type id_resolver registered
10560 10:56:19.435734 <5>[ 0.855328] Key type id_legacy registered
10561 10:56:19.442442 <6>[ 0.859607] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 10:56:19.449338 <6>[ 0.866527] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 10:56:19.455971 <6>[ 0.874230] 9p: Installing v9fs 9p2000 file system support
10564 10:56:19.492712 <5>[ 0.912435] Key type asymmetric registered
10565 10:56:19.495831 <5>[ 0.916765] Asymmetric key parser 'x509' registered
10566 10:56:19.505604 <6>[ 0.921898] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 10:56:19.509223 <6>[ 0.929513] io scheduler mq-deadline registered
10568 10:56:19.512364 <6>[ 0.934275] io scheduler kyber registered
10569 10:56:19.530791 <6>[ 0.950866] EINJ: ACPI disabled.
10570 10:56:19.562409 <4>[ 0.975967] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 10:56:19.572412 <4>[ 0.986578] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 10:56:19.587308 <6>[ 1.007426] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 10:56:19.595672 <6>[ 1.015306] printk: console [ttyS0] disabled
10574 10:56:19.623933 <6>[ 1.039946] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 10:56:19.630135 <6>[ 1.049417] printk: console [ttyS0] enabled
10576 10:56:19.633263 <6>[ 1.049417] printk: console [ttyS0] enabled
10577 10:56:19.639921 <6>[ 1.058312] printk: bootconsole [mtk8250] disabled
10578 10:56:19.643305 <6>[ 1.058312] printk: bootconsole [mtk8250] disabled
10579 10:56:19.649501 <6>[ 1.069272] SuperH (H)SCI(F) driver initialized
10580 10:56:19.652943 <6>[ 1.074540] msm_serial: driver initialized
10581 10:56:19.666705 <6>[ 1.083375] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 10:56:19.676479 <6>[ 1.091918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 10:56:19.683187 <6>[ 1.100460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 10:56:19.693017 <6>[ 1.109088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 10:56:19.703048 <6>[ 1.117795] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 10:56:19.710178 <6>[ 1.126511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 10:56:19.719706 <6>[ 1.135052] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 10:56:19.726086 <6>[ 1.143849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 10:56:19.735663 <6>[ 1.152391] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 10:56:19.747993 <6>[ 1.167792] loop: module loaded
10591 10:56:19.754304 <6>[ 1.173809] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 10:56:19.777125 <4>[ 1.197167] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 10:56:19.783995 <6>[ 1.203837] megasas: 07.719.03.00-rc1
10594 10:56:19.793228 <6>[ 1.213264] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 10:56:19.806512 <6>[ 1.226509] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 10:56:19.822659 <6>[ 1.242418] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 10:56:19.882711 <6>[ 1.295766] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10598 10:56:21.000987 <6>[ 2.420662] Freeing initrd memory: 39196K
10599 10:56:21.010430 <6>[ 2.430799] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 10:56:21.022062 <6>[ 2.441731] tun: Universal TUN/TAP device driver, 1.6
10601 10:56:21.024760 <6>[ 2.447786] thunder_xcv, ver 1.0
10602 10:56:21.028218 <6>[ 2.451291] thunder_bgx, ver 1.0
10603 10:56:21.031858 <6>[ 2.454783] nicpf, ver 1.0
10604 10:56:21.042149 <6>[ 2.458771] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 10:56:21.045889 <6>[ 2.466246] hns3: Copyright (c) 2017 Huawei Corporation.
10606 10:56:21.048889 <6>[ 2.471833] hclge is initializing
10607 10:56:21.055812 <6>[ 2.475414] e1000: Intel(R) PRO/1000 Network Driver
10608 10:56:21.062193 <6>[ 2.480544] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 10:56:21.065017 <6>[ 2.486559] e1000e: Intel(R) PRO/1000 Network Driver
10610 10:56:21.071713 <6>[ 2.491775] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 10:56:21.078253 <6>[ 2.497959] igb: Intel(R) Gigabit Ethernet Network Driver
10612 10:56:21.085382 <6>[ 2.503608] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 10:56:21.091565 <6>[ 2.509444] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 10:56:21.098200 <6>[ 2.515963] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 10:56:21.101622 <6>[ 2.522425] sky2: driver version 1.30
10616 10:56:21.108233 <6>[ 2.527414] VFIO - User Level meta-driver version: 0.3
10617 10:56:21.115605 <6>[ 2.535556] usbcore: registered new interface driver usb-storage
10618 10:56:21.122615 <6>[ 2.541994] usbcore: registered new device driver onboard-usb-hub
10619 10:56:21.131265 <6>[ 2.550997] mt6397-rtc mt6359-rtc: registered as rtc0
10620 10:56:21.140931 <6>[ 2.556465] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:56:21 UTC (1685962581)
10621 10:56:21.144122 <6>[ 2.566023] i2c_dev: i2c /dev entries driver
10622 10:56:21.160508 <6>[ 2.577700] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 10:56:21.167765 <6>[ 2.587891] sdhci: Secure Digital Host Controller Interface driver
10624 10:56:21.174789 <6>[ 2.594329] sdhci: Copyright(c) Pierre Ossman
10625 10:56:21.180965 <6>[ 2.599722] Synopsys Designware Multimedia Card Interface Driver
10626 10:56:21.184684 <6>[ 2.606329] mmc0: CQHCI version 5.10
10627 10:56:21.190704 <6>[ 2.606869] sdhci-pltfm: SDHCI platform and OF driver helper
10628 10:56:21.197921 <6>[ 2.618168] ledtrig-cpu: registered to indicate activity on CPUs
10629 10:56:21.208650 <6>[ 2.625482] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10630 10:56:21.215464 <6>[ 2.632875] usbcore: registered new interface driver usbhid
10631 10:56:21.218790 <6>[ 2.638703] usbhid: USB HID core driver
10632 10:56:21.224936 <6>[ 2.642943] spi_master spi0: will run message pump with realtime priority
10633 10:56:21.274641 <6>[ 2.687785] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10634 10:56:21.293278 <6>[ 2.703197] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10635 10:56:21.296671 <6>[ 2.716756] mmc0: Command Queue Engine enabled
10636 10:56:21.303531 <6>[ 2.718332] cros-ec-spi spi0.0: Chrome EC device registered
10637 10:56:21.310197 <6>[ 2.721491] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 10:56:21.313696 <6>[ 2.734552] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 10:56:21.327416 <6>[ 2.744164] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10640 10:56:21.334216 <6>[ 2.745088] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10641 10:56:21.340344 <6>[ 2.755672] NET: Registered PF_PACKET protocol family
10642 10:56:21.343614 <6>[ 2.760795] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 10:56:21.350207 <6>[ 2.764836] 9pnet: Installing 9P2000 support
10644 10:56:21.353547 <6>[ 2.770545] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10645 10:56:21.360412 <5>[ 2.774503] Key type dns_resolver registered
10646 10:56:21.366603 <6>[ 2.780306] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10647 10:56:21.370305 <6>[ 2.784821] registered taskstats version 1
10648 10:56:21.373429 <5>[ 2.795115] Loading compiled-in X.509 certificates
10649 10:56:21.409782 <4>[ 2.823168] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 10:56:21.419357 <4>[ 2.833869] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 10:56:21.429445 <3>[ 2.846593] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10652 10:56:21.441836 <6>[ 2.861944] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10653 10:56:21.449195 <6>[ 2.868749] xhci-mtk 11200000.usb: xHCI Host Controller
10654 10:56:21.454975 <6>[ 2.874261] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10655 10:56:21.465106 <6>[ 2.882123] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10656 10:56:21.471649 <6>[ 2.891556] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10657 10:56:21.478603 <6>[ 2.897737] xhci-mtk 11200000.usb: xHCI Host Controller
10658 10:56:21.485494 <6>[ 2.903251] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10659 10:56:21.491885 <6>[ 2.910908] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10660 10:56:21.498594 <6>[ 2.918782] hub 1-0:1.0: USB hub found
10661 10:56:21.502028 <6>[ 2.922819] hub 1-0:1.0: 1 port detected
10662 10:56:21.511716 <6>[ 2.927165] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10663 10:56:21.514840 <6>[ 2.935966] hub 2-0:1.0: USB hub found
10664 10:56:21.518124 <6>[ 2.940001] hub 2-0:1.0: 1 port detected
10665 10:56:21.526511 <6>[ 2.946983] mtk-msdc 11f70000.mmc: Got CD GPIO
10666 10:56:21.545058 <6>[ 2.961802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10667 10:56:21.551282 <6>[ 2.969855] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10668 10:56:21.561208 <4>[ 2.977822] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10669 10:56:21.571219 <6>[ 2.987481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10670 10:56:21.578018 <6>[ 2.995574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10671 10:56:21.587645 <6>[ 3.003613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10672 10:56:21.594412 <6>[ 3.011528] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10673 10:56:21.601340 <6>[ 3.019350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10674 10:56:21.611040 <6>[ 3.027172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10675 10:56:21.620984 <6>[ 3.037965] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10676 10:56:21.631174 <6>[ 3.046332] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10677 10:56:21.637455 <6>[ 3.054685] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10678 10:56:21.647421 <6>[ 3.063031] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10679 10:56:21.654474 <6>[ 3.071374] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10680 10:56:21.663855 <6>[ 3.079717] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10681 10:56:21.670360 <6>[ 3.088059] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10682 10:56:21.680392 <6>[ 3.096401] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10683 10:56:21.686977 <6>[ 3.104744] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10684 10:56:21.697486 <6>[ 3.113087] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10685 10:56:21.703427 <6>[ 3.121429] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10686 10:56:21.713231 <6>[ 3.129772] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10687 10:56:21.720146 <6>[ 3.138116] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10688 10:56:21.729839 <6>[ 3.146459] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10689 10:56:21.736832 <6>[ 3.154815] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10690 10:56:21.743427 <6>[ 3.163642] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10691 10:56:21.751065 <6>[ 3.171065] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10692 10:56:21.758063 <6>[ 3.178108] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10693 10:56:21.768438 <6>[ 3.185240] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10694 10:56:21.775064 <6>[ 3.192526] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10695 10:56:21.785412 <6>[ 3.199437] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10696 10:56:21.791722 <6>[ 3.208579] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10697 10:56:21.801106 <6>[ 3.217707] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10698 10:56:21.810940 <6>[ 3.227008] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10699 10:56:21.821001 <6>[ 3.236483] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10700 10:56:21.830857 <6>[ 3.245959] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10701 10:56:21.841249 <6>[ 3.255085] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10702 10:56:21.847632 <6>[ 3.264560] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10703 10:56:21.857805 <6>[ 3.273686] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10704 10:56:21.867233 <6>[ 3.282987] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10705 10:56:21.877061 <6>[ 3.293153] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10706 10:56:21.887716 <6>[ 3.304623] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10707 10:56:21.930384 <6>[ 3.347377] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10708 10:56:22.082907 <6>[ 3.503364] hub 1-1:1.0: USB hub found
10709 10:56:22.086031 <6>[ 3.507715] hub 1-1:1.0: 4 ports detected
10710 10:56:22.210201 <6>[ 3.627475] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10711 10:56:22.236991 <6>[ 3.657341] hub 2-1:1.0: USB hub found
10712 10:56:22.240064 <6>[ 3.661852] hub 2-1:1.0: 3 ports detected
10713 10:56:22.406287 <6>[ 3.823405] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10714 10:56:22.536860 <6>[ 3.957281] hub 1-1.1:1.0: USB hub found
10715 10:56:22.539926 <6>[ 3.961564] hub 1-1.1:1.0: 4 ports detected
10716 10:56:22.653982 <6>[ 4.071263] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10717 10:56:22.787253 <6>[ 4.207413] hub 1-1.4:1.0: USB hub found
10718 10:56:22.789990 <6>[ 4.212092] hub 1-1.4:1.0: 2 ports detected
10719 10:56:22.870158 <6>[ 4.287409] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10720 10:56:23.058324 <6>[ 4.475405] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10721 10:56:23.143217 <3>[ 4.563497] usb 1-1.1.4: device descriptor read/64, error -32
10722 10:56:23.335082 <3>[ 4.755483] usb 1-1.1.4: device descriptor read/64, error -32
10723 10:56:23.530867 <6>[ 4.947407] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10724 10:56:23.718178 <6>[ 5.135275] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10725 10:56:23.803125 <3>[ 5.223618] usb 1-1.1.4: device descriptor read/64, error -32
10726 10:56:23.994943 <3>[ 5.415611] usb 1-1.1.4: device descriptor read/64, error -32
10727 10:56:24.107109 <6>[ 5.527972] usb 1-1.1-port4: attempt power cycle
10728 10:56:24.193938 <6>[ 5.611405] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10729 10:56:24.717915 <6>[ 6.135406] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10730 10:56:24.724685 <4>[ 6.142861] usb 1-1.1.4: Device not responding to setup address.
10731 10:56:24.935668 <4>[ 6.355663] usb 1-1.1.4: Device not responding to setup address.
10732 10:56:25.146830 <3>[ 6.567393] usb 1-1.1.4: device not accepting address 10, error -71
10733 10:56:25.233793 <6>[ 6.651407] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10734 10:56:25.240843 <4>[ 6.658860] usb 1-1.1.4: Device not responding to setup address.
10735 10:56:25.450949 <4>[ 6.871693] usb 1-1.1.4: Device not responding to setup address.
10736 10:56:25.662805 <3>[ 7.083394] usb 1-1.1.4: device not accepting address 11, error -71
10737 10:56:25.669597 <3>[ 7.090348] usb 1-1.1-port4: unable to enumerate USB device
10738 10:56:34.171039 <6>[ 15.595975] ALSA device list:
10739 10:56:34.177456 <6>[ 15.599231] No soundcards found.
10740 10:56:34.190466 <6>[ 15.611634] Freeing unused kernel memory: 8384K
10741 10:56:34.193326 <6>[ 15.616565] Run /init as init process
10742 10:56:34.223758 <6>[ 15.645410] NET: Registered PF_INET6 protocol family
10743 10:56:34.230338 <6>[ 15.651611] Segment Routing with IPv6
10744 10:56:34.233572 <6>[ 15.655563] In-situ OAM (IOAM) with IPv6
10745 10:56:34.268281 <30>[ 15.670124] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10746 10:56:34.272041 <30>[ 15.693994] systemd[1]: Detected architecture arm64.
10747 10:56:34.274932
10748 10:56:34.277917 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10749 10:56:34.278093
10750 10:56:34.293674 <30>[ 15.715529] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10751 10:56:34.438828 <30>[ 15.857323] systemd[1]: Queued start job for default target Graphical Interface.
10752 10:56:34.482940 <30>[ 15.904740] systemd[1]: Created slice system-getty.slice.
10753 10:56:34.489577 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10754 10:56:34.506456 <30>[ 15.927983] systemd[1]: Created slice system-modprobe.slice.
10755 10:56:34.512660 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10756 10:56:34.531022 <30>[ 15.952525] systemd[1]: Created slice system-serial\x2dgetty.slice.
10757 10:56:34.541372 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10758 10:56:34.554209 <30>[ 15.975897] systemd[1]: Created slice User and Session Slice.
10759 10:56:34.560792 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10760 10:56:34.581356 <30>[ 15.999963] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10761 10:56:34.591557 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10762 10:56:34.609359 <30>[ 16.027570] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10763 10:56:34.615682 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10764 10:56:34.636509 <30>[ 16.051497] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10765 10:56:34.642874 <30>[ 16.063525] systemd[1]: Reached target Local Encrypted Volumes.
10766 10:56:34.649227 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10767 10:56:34.665864 <30>[ 16.087500] systemd[1]: Reached target Paths.
10768 10:56:34.668903 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10769 10:56:34.685697 <30>[ 16.107445] systemd[1]: Reached target Remote File Systems.
10770 10:56:34.692188 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10771 10:56:34.710071 <30>[ 16.131679] systemd[1]: Reached target Slices.
10772 10:56:34.716222 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10773 10:56:34.729700 <30>[ 16.151470] systemd[1]: Reached target Swap.
10774 10:56:34.733004 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10775 10:56:34.753095 <30>[ 16.171745] systemd[1]: Listening on initctl Compatibility Named Pipe.
10776 10:56:34.759720 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10777 10:56:34.766256 <30>[ 16.186486] systemd[1]: Listening on Journal Audit Socket.
10778 10:56:34.772829 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10779 10:56:34.785967 <30>[ 16.207712] systemd[1]: Listening on Journal Socket (/dev/log).
10780 10:56:34.792400 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10781 10:56:34.810538 <30>[ 16.231728] systemd[1]: Listening on Journal Socket.
10782 10:56:34.816479 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10783 10:56:34.833811 <30>[ 16.251755] systemd[1]: Listening on Network Service Netlink Socket.
10784 10:56:34.839976 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10785 10:56:34.854139 <30>[ 16.276174] systemd[1]: Listening on udev Control Socket.
10786 10:56:34.860698 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10787 10:56:34.878576 <30>[ 16.300138] systemd[1]: Listening on udev Kernel Socket.
10788 10:56:34.884851 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10789 10:56:34.917646 <30>[ 16.339547] systemd[1]: Mounting Huge Pages File System...
10790 10:56:34.924321 Mounting [0;1;39mHuge Pages File System[0m...
10791 10:56:34.939416 <30>[ 16.361496] systemd[1]: Mounting POSIX Message Queue File System...
10792 10:56:34.946760 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10793 10:56:34.963761 <30>[ 16.385381] systemd[1]: Mounting Kernel Debug File System...
10794 10:56:34.970587 Mounting [0;1;39mKernel Debug File System[0m...
10795 10:56:34.989594 <30>[ 16.407650] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10796 10:56:34.999643 <30>[ 16.418464] systemd[1]: Starting Create list of static device nodes for the current kernel...
10797 10:56:35.006851 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10798 10:56:35.058058 <30>[ 16.479748] systemd[1]: Starting Load Kernel Module configfs...
10799 10:56:35.064774 Starting [0;1;39mLoad Kernel Module configfs[0m...
10800 10:56:35.079851 <30>[ 16.501655] systemd[1]: Starting Load Kernel Module drm...
10801 10:56:35.086033 Starting [0;1;39mLoad Kernel Module drm[0m...
10802 10:56:35.105102 <30>[ 16.523544] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10803 10:56:35.115149 <30>[ 16.537058] systemd[1]: Starting Journal Service...
10804 10:56:35.118301 Starting [0;1;39mJournal Service[0m...
10805 10:56:35.136104 <30>[ 16.557981] systemd[1]: Starting Load Kernel Modules...
10806 10:56:35.142522 Starting [0;1;39mLoad Kernel Modules[0m...
10807 10:56:35.163558 <30>[ 16.582208] systemd[1]: Starting Remount Root and Kernel File Systems...
10808 10:56:35.170252 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10809 10:56:35.188373 <30>[ 16.610082] systemd[1]: Starting Coldplug All udev Devices...
10810 10:56:35.194675 Starting [0;1;39mColdplug All udev Devices[0m...
10811 10:56:35.212510 <30>[ 16.634189] systemd[1]: Mounted Huge Pages File System.
10812 10:56:35.218690 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10813 10:56:35.234317 <30>[ 16.656183] systemd[1]: Started Journal Service.
10814 10:56:35.240728 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10815 10:56:35.255953 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10816 10:56:35.274590 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10817 10:56:35.294235 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10818 10:56:35.311348 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10819 10:56:35.331937 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10820 10:56:35.351061 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10821 10:56:35.370555 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10822 10:56:35.385847 See 'systemctl status systemd-remount-fs.service' for details.
10823 10:56:35.442271 Mounting [0;1;39mKernel Configuration File System[0m...
10824 10:56:35.459812 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10825 10:56:35.477725 <46>[ 16.896043] systemd-journald[179]: Received client request to flush runtime journal.
10826 10:56:35.486354 Starting [0;1;39mLoad/Save Random Seed[0m...
10827 10:56:35.504695 Starting [0;1;39mApply Kernel Variables[0m...
10828 10:56:35.525433 Starting [0;1;39mCreate System Users[0m...
10829 10:56:35.547312 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10830 10:56:35.566798 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10831 10:56:35.578586 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10832 10:56:35.598923 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10833 10:56:35.618813 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10834 10:56:35.638267 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10835 10:56:35.678086 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10836 10:56:35.702259 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10837 10:56:35.717778 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10838 10:56:35.733984 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10839 10:56:35.793779 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10840 10:56:35.817643 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10841 10:56:35.835137 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10842 10:56:35.854756 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10843 10:56:35.914906 Starting [0;1;39mNetwork Service[0m...
10844 10:56:35.938674 Starting [0;1;39mNetwork Time Synchronization[0m...
10845 10:56:35.960545 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10846 10:56:35.996665 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10847 10:56:36.020949 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10848 10:56:36.050857 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10849 10:56:36.064604 <6>[ 17.483346] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10850 10:56:36.090910 <6>[ 17.512501] remoteproc remoteproc0: scp is available
10851 10:56:36.097440 <6>[ 17.518705] remoteproc remoteproc0: powering up scp
10852 10:56:36.106855 <6>[ 17.523997] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10853 10:56:36.113547 <3>[ 17.530269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 10:56:36.120427 <6>[ 17.532472] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10855 10:56:36.127105 <6>[ 17.532694] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10856 10:56:36.137220 <6>[ 17.532744] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10857 10:56:36.143966 <6>[ 17.532760] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10858 10:56:36.153320 <3>[ 17.540572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 10:56:36.163256 Startin<3>[ 17.579735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 10:56:36.167003 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10861 10:56:36.177097 <3>[ 17.595312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 10:56:36.180318 <6>[ 17.596761] mc: Linux media interface: v0.10
10863 10:56:36.189884 <3>[ 17.603766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 10:56:36.196481 <4>[ 17.608613] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10865 10:56:36.203113 <3>[ 17.616167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 10:56:36.212988 <3>[ 17.616179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 10:56:36.219687 <3>[ 17.616187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 10:56:36.229382 <3>[ 17.624103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 10:56:36.236289 <6>[ 17.642665] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10870 10:56:36.242627 <4>[ 17.642724] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10871 10:56:36.252656 <3>[ 17.668277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 10:56:36.259015 <6>[ 17.672346] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10873 10:56:36.269127 <6>[ 17.672350] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10874 10:56:36.275887 <3>[ 17.679043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 10:56:36.282576 <3>[ 17.679053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 10:56:36.292314 <3>[ 17.680248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 10:56:36.298875 <6>[ 17.682483] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10878 10:56:36.305470 <6>[ 17.682494] pci_bus 0000:00: root bus resource [bus 00-ff]
10879 10:56:36.311910 <6>[ 17.682502] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10880 10:56:36.321893 <6>[ 17.682509] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10881 10:56:36.329279 <6>[ 17.682546] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10882 10:56:36.335128 <6>[ 17.682565] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10883 10:56:36.341642 <6>[ 17.682640] pci 0000:00:00.0: supports D1 D2
10884 10:56:36.348686 <6>[ 17.682644] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10885 10:56:36.352181 <6>[ 17.688031] remoteproc remoteproc0: remote processor scp is now up
10886 10:56:36.362001 <3>[ 17.694896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 10:56:36.371974 <4>[ 17.712767] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10888 10:56:36.375551 <4>[ 17.712767] Fallback method does not support PEC.
10889 10:56:36.384876 <3>[ 17.719090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 10:56:36.392069 <6>[ 17.730712] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10891 10:56:36.401652 <3>[ 17.731688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 10:56:36.408198 <3>[ 17.731702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 10:56:36.415367 <6>[ 17.739256] usbcore: registered new interface driver r8152
10894 10:56:36.418181 <6>[ 17.740731] videodev: Linux video capture interface: v2.00
10895 10:56:36.428129 <3>[ 17.742166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 10:56:36.434488 <6>[ 17.764004] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10897 10:56:36.441081 <3>[ 17.779496] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 10:56:36.451337 <6>[ 17.781337] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10899 10:56:36.458293 <6>[ 17.785386] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10900 10:56:36.471417 <6>[ 17.788828] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10901 10:56:36.478229 <6>[ 17.802715] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10902 10:56:36.485352 <6>[ 17.830619] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10903 10:56:36.494999 <6>[ 17.835252] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10904 10:56:36.501989 <6>[ 17.847799] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10905 10:56:36.508194 <6>[ 17.849132] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10906 10:56:36.518852 <6>[ 17.850790] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10907 10:56:36.521780 <6>[ 17.855352] pci 0000:01:00.0: supports D1 D2
10908 10:56:36.528483 <6>[ 17.861375] usbcore: registered new interface driver cdc_ether
10909 10:56:36.535422 <6>[ 17.869839] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10910 10:56:36.541718 <6>[ 17.883254] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10911 10:56:36.548121 <6>[ 17.897202] usbcore: registered new interface driver r8153_ecm
10912 10:56:36.551255 <6>[ 17.898822] Bluetooth: Core ver 2.22
10913 10:56:36.558180 <6>[ 17.898889] NET: Registered PF_BLUETOOTH protocol family
10914 10:56:36.565047 <6>[ 17.898892] Bluetooth: HCI device and connection manager initialized
10915 10:56:36.569184 <6>[ 17.898911] Bluetooth: HCI socket layer initialized
10916 10:56:36.576054 <6>[ 17.898918] Bluetooth: L2CAP socket layer initialized
10917 10:56:36.579255 <6>[ 17.898930] Bluetooth: SCO socket layer initialized
10918 10:56:36.589129 <6>[ 17.904310] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10919 10:56:36.595738 <6>[ 17.916398] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10920 10:56:36.603163 <6>[ 17.920801] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10921 10:56:36.616684 <6>[ 17.929813] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10922 10:56:36.622725 <6>[ 17.936391] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10923 10:56:36.629891 <6>[ 17.936409] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10924 10:56:36.637334 <6>[ 17.945086] usbcore: registered new interface driver uvcvideo
10925 10:56:36.642863 <6>[ 17.945740] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10926 10:56:36.649929 <6>[ 17.945755] usbcore: registered new interface driver btusb
10927 10:56:36.659906 <6>[ 17.949213] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10928 10:56:36.662733 <6>[ 17.949231] pci 0000:00:00.0: PCI bridge to [bus 01]
10929 10:56:36.669713 <6>[ 17.949240] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10930 10:56:36.676850 <6>[ 17.949547] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10931 10:56:36.686731 <4>[ 17.955834] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10932 10:56:36.693223 <6>[ 17.964251] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10933 10:56:36.703058 <3>[ 17.964300] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:56:36.713314 <3>[ 17.965195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10935 10:56:36.716420 <3>[ 17.969224] Bluetooth: hci0: Failed to load firmware file (-2)
10936 10:56:36.723188 <6>[ 17.975703] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10937 10:56:36.729412 <3>[ 17.979118] Bluetooth: hci0: Failed to set up firmware (-2)
10938 10:56:36.739592 <4>[ 17.982425] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10939 10:56:36.746080 <4>[ 17.982432] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10940 10:56:36.756134 <5>[ 18.004652] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10941 10:56:36.762878 <3>[ 18.006898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 10:56:36.775854 <4>[ 18.006901] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10943 10:56:36.782834 <3>[ 18.016253] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10944 10:56:36.789293 <5>[ 18.027409] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10945 10:56:36.795894 <3>[ 18.029621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 10:56:36.803025 <6>[ 18.047310] r8152 1-1.1.1:1.0 eth0: v1.12.13
10947 10:56:36.809350 <4>[ 18.050659] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10948 10:56:36.819579 <3>[ 18.066361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 10:56:36.823183 <6>[ 18.071649] cfg80211: failed to load regulatory.db
10950 10:56:36.829750 <6>[ 18.073817] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10951 10:56:36.839636 <3>[ 18.100179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 10:56:36.846055 <6>[ 18.200934] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10953 10:56:36.855920 <3>[ 18.221723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 10:56:36.862959 <6>[ 18.224585] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10955 10:56:36.869715 <3>[ 18.249467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 10:56:36.876035 <6>[ 18.271355] mt7921e 0000:01:00.0: ASIC revision: 79610010
10957 10:56:36.882742 Starting [0;1;39mNetwork Name Resolution[0m...
10958 10:56:36.901913 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10959 10:56:36.917864 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10960 10:56:36.942365 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 10:56:36.959987 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10962 10:56:36.983025 <4>[ 18.398742] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10963 10:56:37.101979 <4>[ 18.517600] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10964 10:56:37.153870 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10965 10:56:37.169683 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10966 10:56:37.188522 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10967 10:56:37.201806 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10968 10:56:37.222847 <4>[ 18.638101] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 10:56:37.232698 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10970 10:56:37.239207 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10971 10:56:37.253390 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10972 10:56:37.273264 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10973 10:56:37.285772 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10974 10:56:37.305550 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10975 10:56:37.317775 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10976 10:56:37.340623 [[0;32m OK [<4>[ 18.757346] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 10:56:37.347433 0m] Reached target [0;1;39mBasic System[0m.
10978 10:56:37.366083 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 10:56:37.409988 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10980 10:56:37.439918 Starting [0;1;39mUser Login Management[0m...
10981 10:56:37.462847 <4>[ 18.878338] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 10:56:37.469678 Starting [0;1;39mPermit User Sessions[0m...
10983 10:56:37.486708 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10984 10:56:37.504933 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10985 10:56:37.521488 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10986 10:56:37.541875 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10987 10:56:37.559929 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10988 10:56:37.587059 <4>[ 19.002524] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 10:56:37.593708 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10990 10:56:37.602692 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10991 10:56:37.622628 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10992 10:56:37.637255 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10993 10:56:37.691169 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10994 10:56:37.709737 <4>[ 19.125086] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10995 10:56:37.735041 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10996 10:56:37.781832
10997 10:56:37.781962
10998 10:56:37.785503 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10999 10:56:37.785589
11000 10:56:37.788603 debian-bullseye-arm64 login: root (automatic login)
11001 10:56:37.788689
11002 10:56:37.788755
11003 10:56:37.805077 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
11004 10:56:37.805177
11005 10:56:37.811884 The programs included with the Debian GNU/Linux system are free software;
11006 10:56:37.819056 the exact distribution terms for each program are described in the
11007 10:56:37.831836 individual files in /usr/share/doc/*/co<4>[ 19.247085] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 10:56:37.831933 pyright.
11009 10:56:37.832000
11010 10:56:37.837954 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11011 10:56:37.841286 permitted by applicable law.
11012 10:56:37.841629 Matched prompt #10: / #
11014 10:56:37.841833 Setting prompt string to ['/ #']
11015 10:56:37.841926 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11017 10:56:37.842123 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11018 10:56:37.842210 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11019 10:56:37.842282 Setting prompt string to ['/ #']
11020 10:56:37.842343 Forcing a shell prompt, looking for ['/ #']
11022 10:56:37.892556 / #
11023 10:56:37.892730 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11024 10:56:37.892849 Waiting using forced prompt support (timeout 00:02:30)
11025 10:56:37.898125
11026 10:56:37.898408 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11027 10:56:37.898520 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11028 10:56:37.898637 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 10:56:37.898739 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11030 10:56:37.898835 end: 2 depthcharge-action (duration 00:01:24) [common]
11031 10:56:37.898946 start: 3 lava-test-retry (timeout 00:08:17) [common]
11032 10:56:37.899043 start: 3.1 lava-test-shell (timeout 00:08:17) [common]
11033 10:56:37.899133 Using namespace: common
11035 10:56:37.999508 / # #
11036 10:56:37.999693 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11037 10:56:37.999868 <4>[ 19.365724] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 10:56:38.004544 #
11039 10:56:38.004836 Using /lava-10591017
11041 10:56:38.105127 / # export SHELL=/bin/sh
11042 10:56:38.105372 export<4>[ 19.485696] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11043 10:56:38.110154 SHELL=/bin/sh
11045 10:56:38.210658 / # . /lava-10591017/environment
11046 10:56:38.210882 . /lava-10591017/environment<3>[ 19.603460] mt7921e 0000:01:00.0: hardware init failed
11047 10:56:38.215883
11049 10:56:38.316391 / # /lava-10591017/bin/lava-test-runner /lava-10591017/0
11050 10:56:38.316600 Test shell timeout: 10s (minimum of the action and connection timeout)
11051 10:56:38.316939 <6>[ 19.675609] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11052 10:56:38.317025 <6>[ 19.683826] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11053 10:56:38.322042 /lava-10591017/bin/lava-test-runner /lava-10591017/0
11054 10:56:38.364680 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11055 10:56:38.364803 + cd /lava-10591017/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11056 10:56:38.364872 + cat uuid
11057 10:56:38.364946 + UUID=10591017_1.5.2.3.1
11058 10:56:38.365008 + set +x
11059 10:56:38.365068 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10591017_1.5.2.3.1>
11060 10:56:38.365126 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11061 10:56:38.365362 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10591017_1.5.2.3.1
11062 10:56:38.365427 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10591017_1.5.2.3.1)
11063 10:56:38.365508 Skipping test definition patterns.
11064 10:56:38.370049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11065 10:56:38.370295 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11067 10:56:38.380147 device: /dev/video2<4>[ 19.796583] use of bytesused == 0 is deprecated and will be removed in the future,
11068 10:56:38.380234
11069 10:56:38.383231 <4>[ 19.805753] use the actual size instead.
11070 10:56:38.390600 <4>[ 19.812461] ------------[ cut here ]------------
11071 10:56:38.396863 <4>[ 19.817394] get_vaddr_frames() cannot follow VM_IO mapping
11072 10:56:38.410103 <4>[ 19.817563] WARNING: CPU: 4 PID: 314 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11073 10:56:38.456929 <4>[ 19.835663] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common btusb btintel btmtk mtk_vpu btrtl btbcm uvcvideo v4l2_mem2mem r8153_ecm videobuf2_dma_contig videobuf2_vmalloc bluetooth videobuf2_memops cdc_ether videobuf2_v4l2 ecdh_generic usbnet videobuf2_common ecc cros_ec_rpmsg rfkill videodev r8152 crct10dif_ce elan_i2c elants_i2c mc cros_ec_chardev sbs_battery cros_ec_typec pcie_mediatek_gen3 hid_google_hammer hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11074 10:56:38.466304 <4>[ 19.885050] CPU: 4 PID: 314 Comm: v4l2-compliance Not tainted 6.1.31 #1
11075 10:56:38.469724 <4>[ 19.891916] Hardware name: Google Spherion (rev0 - 3) (DT)
11076 10:56:38.475872 <4>[ 19.897650] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11077 10:56:38.482729 <4>[ 19.904864] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11078 10:56:38.489166 <4>[ 19.910961] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11079 10:56:38.492452 <4>[ 19.917058] sp : ffff8000091bb850
11080 10:56:38.499173 <4>[ 19.920622] x29: ffff8000091bb850 x28: ffffbd7bf32a5000 x27: ffffbd7bf32a1238
11081 10:56:38.509244 <4>[ 19.928010] x26: 0000000000000000 x25: ffffbd7c3badae18 x24: ffff730bcec81298
11082 10:56:38.515932 <4>[ 19.935397] x23: ffff730bc958e400 x22: ffff730bc0d48010 x21: 0000000000000000
11083 10:56:38.522460 <4>[ 19.942784] x20: 00000000fffffff2 x19: ffff730bce5f9b80 x18: fffffffffffe9a88
11084 10:56:38.529741 <4>[ 19.950172] x17: 0000000000000000 x16: ffffbd7c39c8bb60 x15: 0000a6bd5036a128
11085 10:56:38.539052 <4>[ 19.957559] x14: 0000000000000021 x13: 0000000000000021 x12: 0000000000000001
11086 10:56:38.545471 <4>[ 19.964945] x11: 0000000000000001 x10: 0000000000000a60 x9 : ffff8000091bb700
11087 10:56:38.552459 <4>[ 19.972333] x8 : ffff730bce6545c0 x7 : ffff730cfef6de40 x6 : 00000000ffffffff
11088 10:56:38.558626 <4>[ 19.979721] x5 : 00000000410fd0b0 x4 : 0000000000c0000e x3 : 0000000000400000
11089 10:56:38.568347 <4>[ 19.987108] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff730bce653b00
11090 10:56:38.568450 <4>[ 19.994495] Call trace:
11091 10:56:38.574956 <4>[ 19.997192] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11092 10:56:38.581558 <4>[ 20.002942] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11093 10:56:38.588006 <4>[ 20.008947] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11094 10:56:38.594859 <4>[ 20.015302] __prepare_userptr+0x280/0x410 [videobuf2_common]
11095 10:56:38.598070 <4>[ 20.021313] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11096 10:56:38.605191 <4>[ 20.026976] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11097 10:56:38.611437 <4>[ 20.033160] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11098 10:56:38.618533 <4>[ 20.038657] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11099 10:56:38.624796 <4>[ 20.044419] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11100 10:56:38.629208 <4>[ 20.050689] v4l_prepare_buf+0x48/0x60 [videodev]
11101 10:56:38.634594 <4>[ 20.055719] __video_do_ioctl+0x184/0x3d0 [videodev]
11102 10:56:38.637922 <4>[ 20.060969] video_usercopy+0x358/0x680 [videodev]
11103 10:56:38.644156 <4>[ 20.066046] video_ioctl2+0x18/0x30 [videodev]
11104 10:56:38.647889 <4>[ 20.070774] v4l2_ioctl+0x40/0x60 [videodev]
11105 10:56:38.651075 <4>[ 20.075330] __arm64_sys_ioctl+0xa8/0xf0
11106 10:56:38.657905 <4>[ 20.079516] invoke_syscall+0x48/0x114
11107 10:56:38.661160 <4>[ 20.083524] el0_svc_common.constprop.0+0x44/0xec
11108 10:56:38.664361 <4>[ 20.088483] do_el0_svc+0x2c/0xd0
11109 10:56:38.667507 <4>[ 20.092052] el0_svc+0x2c/0x84
11110 10:56:38.674022 <4>[ 20.095366] el0t_64_sync_handler+0xb8/0xc0
11111 10:56:38.677282 <4>[ 20.099805] el0t_64_sync+0x18c/0x190
11112 10:56:38.680815 <4>[ 20.103719] ---[ end trace 0000000000000000 ]---
11113 10:56:38.694577 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11114 10:56:38.704133 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11115 10:56:38.709754
11116 10:56:38.720805 Compliance test for mtk-vcodec-enc device /dev/video2:
11117 10:56:38.727085
11118 10:56:38.736994 Driver Info:
11119 10:56:38.746042 Driver name : mtk-vcodec-enc
11120 10:56:38.758726 Card type : MT8192 video encoder
11121 10:56:38.768108 Bus info : platform:17020000.vcodec
11122 10:56:38.774778 Driver version : 6.1.31
11123 10:56:38.783612 Capabilities : 0x84204000
11124 10:56:38.793281 Video Memory-to-Memory Multiplanar
11125 10:56:38.802053 Streaming
11126 10:56:38.810886 Extended Pix Format
11127 10:56:38.820842 Device Capabilities
11128 10:56:38.830434 Device Caps : 0x04204000
11129 10:56:38.840522 Video Memory-to-Memory Multiplanar
11130 10:56:38.849513 Streaming
11131 10:56:38.859192 Extended Pix Format
11132 10:56:38.868713 Detected Stateful Encoder
11133 10:56:38.878834
11134 10:56:38.887929 Required ioctls:
11135 10:56:38.902291 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11136 10:56:38.902390 test VIDIOC_QUERYCAP: OK
11137 10:56:38.902664 Received signal: <TESTSET> START Required-ioctls
11138 10:56:38.902763 Starting test_set Required-ioctls
11139 10:56:38.924323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11140 10:56:38.924612 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11142 10:56:38.927798 test invalid ioctls: OK
11143 10:56:38.946739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11144 10:56:38.946830
11145 10:56:38.947066 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11147 10:56:38.956979 Allow for multiple opens:
11148 10:56:38.964101 <LAVA_SIGNAL_TESTSET STOP>
11149 10:56:38.964360 Received signal: <TESTSET> STOP
11150 10:56:38.964436 Closing test_set Required-ioctls
11151 10:56:38.973397 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11152 10:56:38.973651 Received signal: <TESTSET> START Allow-for-multiple-opens
11153 10:56:38.973753 Starting test_set Allow-for-multiple-opens
11154 10:56:38.976393 test second /dev/video2 open: OK
11155 10:56:38.996404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11156 10:56:38.996732 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11158 10:56:38.999519 test VIDIOC_QUERYCAP: OK
11159 10:56:39.019473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11160 10:56:39.019744 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11162 10:56:39.022739 test VIDIOC_G/S_PRIORITY: OK
11163 10:56:39.043745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11164 10:56:39.044048 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11166 10:56:39.046898 test for unlimited opens: OK
11167 10:56:39.068082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11168 10:56:39.068181
11169 10:56:39.068418 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11171 10:56:39.077363 Debug ioctls:
11172 10:56:39.084388 <LAVA_SIGNAL_TESTSET STOP>
11173 10:56:39.084648 Received signal: <TESTSET> STOP
11174 10:56:39.084721 Closing test_set Allow-for-multiple-opens
11175 10:56:39.093351 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11176 10:56:39.093662 Received signal: <TESTSET> START Debug-ioctls
11177 10:56:39.093767 Starting test_set Debug-ioctls
11178 10:56:39.096616 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11179 10:56:39.116704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11180 10:56:39.117012 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11182 10:56:39.123512 test VIDIOC_LOG_STATUS: OK (Not Supported)
11183 10:56:39.140192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11184 10:56:39.140308
11185 10:56:39.140553 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11187 10:56:39.151262 Input ioctls:
11188 10:56:39.158070 <LAVA_SIGNAL_TESTSET STOP>
11189 10:56:39.158329 Received signal: <TESTSET> STOP
11190 10:56:39.158400 Closing test_set Debug-ioctls
11191 10:56:39.167976 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11192 10:56:39.168230 Received signal: <TESTSET> START Input-ioctls
11193 10:56:39.168335 Starting test_set Input-ioctls
11194 10:56:39.171209 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11195 10:56:39.194907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11196 10:56:39.195186 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11198 10:56:39.198218 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11199 10:56:39.216739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11200 10:56:39.217012 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11202 10:56:39.222521 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11203 10:56:39.241016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11204 10:56:39.241291 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11206 10:56:39.247331 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11207 10:56:39.263740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11208 10:56:39.264073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11210 10:56:39.267154 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11211 10:56:39.288661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11212 10:56:39.288978 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11214 10:56:39.292382 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11215 10:56:39.312464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11216 10:56:39.312809 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11218 10:56:39.315397 Inputs: 0 Audio Inputs: 0 Tuners: 0
11219 10:56:39.322580
11220 10:56:39.338905 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11221 10:56:39.359829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11222 10:56:39.360152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11224 10:56:39.366179 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11225 10:56:39.382967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11226 10:56:39.383279 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11228 10:56:39.389742 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11229 10:56:39.408660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11230 10:56:39.408964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11232 10:56:39.414704 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11233 10:56:39.432501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11234 10:56:39.432881 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11236 10:56:39.439080 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11237 10:56:39.455490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11238 10:56:39.455606
11239 10:56:39.455847 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11241 10:56:39.475815 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11242 10:56:39.496750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11243 10:56:39.497056 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11245 10:56:39.503488 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11246 10:56:39.524384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11247 10:56:39.524749 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11249 10:56:39.527858 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11250 10:56:39.544845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11251 10:56:39.545145 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11253 10:56:39.548156 test VIDIOC_G/S_EDID: OK (Not Supported)
11254 10:56:39.568488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11255 10:56:39.568655
11256 10:56:39.568898 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11258 10:56:39.578646 Control ioctls:
11259 10:56:39.585310 <LAVA_SIGNAL_TESTSET STOP>
11260 10:56:39.585585 Received signal: <TESTSET> STOP
11261 10:56:39.585660 Closing test_set Input-ioctls
11262 10:56:39.595802 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11263 10:56:39.596087 Received signal: <TESTSET> START Control-ioctls
11264 10:56:39.596163 Starting test_set Control-ioctls
11265 10:56:39.599025 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11266 10:56:39.622930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11267 10:56:39.623080 test VIDIOC_QUERYCTRL: OK
11268 10:56:39.623337 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11270 10:56:39.644420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11271 10:56:39.644731 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11273 10:56:39.647311 test VIDIOC_G/S_CTRL: OK
11274 10:56:39.673380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11275 10:56:39.673662 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11277 10:56:39.676271 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11278 10:56:39.698528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11279 10:56:39.698828 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11281 10:56:39.708798 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11282 10:56:39.711743 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11283 10:56:39.735976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11284 10:56:39.736273 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11286 10:56:39.739092 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11287 10:56:39.756312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11288 10:56:39.756596 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11290 10:56:39.759841 Standard Controls: 16 Private Controls: 0
11291 10:56:39.765836
11292 10:56:39.775530 Format ioctls:
11293 10:56:39.782202 <LAVA_SIGNAL_TESTSET STOP>
11294 10:56:39.782499 Received signal: <TESTSET> STOP
11295 10:56:39.782600 Closing test_set Control-ioctls
11296 10:56:39.791743 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11297 10:56:39.792010 Received signal: <TESTSET> START Format-ioctls
11298 10:56:39.792115 Starting test_set Format-ioctls
11299 10:56:39.794738 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11300 10:56:39.819313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11301 10:56:39.819607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11303 10:56:39.822052 test VIDIOC_G/S_PARM: OK
11304 10:56:39.839330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11305 10:56:39.839615 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11307 10:56:39.843095 test VIDIOC_G_FBUF: OK (Not Supported)
11308 10:56:39.863366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11309 10:56:39.863624 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11311 10:56:39.866436 test VIDIOC_G_FMT: OK
11312 10:56:39.886215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11313 10:56:39.886530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11315 10:56:39.889733 test VIDIOC_TRY_FMT: OK
11316 10:56:39.911132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11317 10:56:39.911436 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11319 10:56:39.921057 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11320 10:56:39.921145 test VIDIOC_S_FMT: FAIL
11321 10:56:39.946154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11322 10:56:39.946453 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11324 10:56:39.949455 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11325 10:56:39.970942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11326 10:56:39.971211 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11328 10:56:39.974346 test Cropping: OK
11329 10:56:39.994941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11330 10:56:39.995242 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11332 10:56:39.998275 test Composing: OK (Not Supported)
11333 10:56:40.019011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11334 10:56:40.019326 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11336 10:56:40.022285 test Scaling: OK (Not Supported)
11337 10:56:40.044560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11338 10:56:40.044655
11339 10:56:40.044894 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11341 10:56:40.052560 Codec ioctls:
11342 10:56:40.059366 <LAVA_SIGNAL_TESTSET STOP>
11343 10:56:40.059620 Received signal: <TESTSET> STOP
11344 10:56:40.059691 Closing test_set Format-ioctls
11345 10:56:40.068178 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11346 10:56:40.068465 Received signal: <TESTSET> START Codec-ioctls
11347 10:56:40.068564 Starting test_set Codec-ioctls
11348 10:56:40.071138 test VIDIOC_(TRY_)ENCODER_CMD: OK
11349 10:56:40.090876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11350 10:56:40.091194 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11352 10:56:40.097387 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11353 10:56:40.115178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11354 10:56:40.115510 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11356 10:56:40.121827 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11357 10:56:40.138989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11358 10:56:40.139143
11359 10:56:40.139423 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11361 10:56:40.149422 Buffer ioctls:
11362 10:56:40.156187 <LAVA_SIGNAL_TESTSET STOP>
11363 10:56:40.156478 Received signal: <TESTSET> STOP
11364 10:56:40.156589 Closing test_set Codec-ioctls
11365 10:56:40.165249 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11366 10:56:40.165531 Received signal: <TESTSET> START Buffer-ioctls
11367 10:56:40.165637 Starting test_set Buffer-ioctls
11368 10:56:40.168336 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11369 10:56:40.192375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11370 10:56:40.192530 test VIDIOC_EXPBUF: OK
11371 10:56:40.192813 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11373 10:56:40.214925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11374 10:56:40.215234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11376 10:56:40.217999 test Requests: OK (Not Supported)
11377 10:56:40.238858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11378 10:56:40.239004
11379 10:56:40.239292 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11381 10:56:40.249097 Test input 0:
11382 10:56:40.258766
11383 10:56:40.268358 Streaming ioctls:
11384 10:56:40.274719 <LAVA_SIGNAL_TESTSET STOP>
11385 10:56:40.275008 Received signal: <TESTSET> STOP
11386 10:56:40.275105 Closing test_set Buffer-ioctls
11387 10:56:40.284213 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11388 10:56:40.284476 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11389 10:56:40.284569 Starting test_set Streaming-ioctls_Test-input-0
11390 10:56:40.287410 test read/write: OK (Not Supported)
11391 10:56:40.306732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11392 10:56:40.307043 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11394 10:56:40.313367 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11395 10:56:40.322982 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11396 10:56:40.326184 test blocking wait: FAIL
11397 10:56:40.347118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11398 10:56:40.347411 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11400 10:56:40.353869 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11401 10:56:40.356825 test MMAP (select): FAIL
11402 10:56:40.379532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11403 10:56:40.379823 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11405 10:56:40.386038 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11406 10:56:40.389079 test MMAP (epoll): FAIL
11407 10:56:40.410960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11408 10:56:40.411260 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11410 10:56:40.420954 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11411 10:56:40.428435 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11412 10:56:40.430664 test USERPTR (select): FAIL
11413 10:56:40.455109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11414 10:56:40.455403 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11416 10:56:40.461216 test DMABUF: Cannot test, specify --expbuf-device
11417 10:56:40.464979
11418 10:56:40.482277 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11419 10:56:40.485741 <LAVA_TEST_RUNNER EXIT>
11420 10:56:40.486000 ok: lava_test_shell seems to have completed
11421 10:56:40.486072 Marking unfinished test run as failed
11423 10:56:40.486983 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11424 10:56:40.487109 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11425 10:56:40.487199 end: 3 lava-test-retry (duration 00:00:03) [common]
11426 10:56:40.487287 start: 4 finalize (timeout 00:08:14) [common]
11427 10:56:40.487379 start: 4.1 power-off (timeout 00:00:30) [common]
11428 10:56:40.487531 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11429 10:56:40.563573 >> Command sent successfully.
11430 10:56:40.565891 Returned 0 in 0 seconds
11431 10:56:40.666332 end: 4.1 power-off (duration 00:00:00) [common]
11433 10:56:40.666660 start: 4.2 read-feedback (timeout 00:08:14) [common]
11434 10:56:40.666956 Listened to connection for namespace 'common' for up to 1s
11435 10:56:41.667705 Finalising connection for namespace 'common'
11436 10:56:41.667869 Disconnecting from shell: Finalise
11437 10:56:41.667952 / #
11438 10:56:41.768257 end: 4.2 read-feedback (duration 00:00:01) [common]
11439 10:56:41.768449 end: 4 finalize (duration 00:00:01) [common]
11440 10:56:41.768594 Cleaning after the job
11441 10:56:41.768694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/ramdisk
11442 10:56:41.772786 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/kernel
11443 10:56:41.778382 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/dtb
11444 10:56:41.778545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591017/tftp-deploy-nytt7b6b/modules
11445 10:56:41.783554 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591017
11446 10:56:41.837216 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591017
11447 10:56:41.837377 Job finished correctly