Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 63
1 10:54:41.301427 lava-dispatcher, installed at version: 2023.05.1
2 10:54:41.301616 start: 0 validate
3 10:54:41.301743 Start time: 2023-06-05 10:54:41.301736+00:00 (UTC)
4 10:54:41.301864 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:54:41.301989 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 10:54:41.601237 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:54:41.601430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:54:41.894546 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:54:41.894715 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:54:42.179940 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:54:42.180115 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:54:42.466792 validate duration: 1.17
14 10:54:42.467190 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:54:42.467321 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:54:42.467469 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:54:42.467591 Not decompressing ramdisk as can be used compressed.
18 10:54:42.467689 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 10:54:42.467756 saving as /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/ramdisk/rootfs.cpio.gz
20 10:54:42.467818 total size: 27151647 (25MB)
21 10:54:42.469445 progress 0% (0MB)
22 10:54:42.477297 progress 5% (1MB)
23 10:54:42.484736 progress 10% (2MB)
24 10:54:42.492365 progress 15% (3MB)
25 10:54:42.499837 progress 20% (5MB)
26 10:54:42.507284 progress 25% (6MB)
27 10:54:42.514551 progress 30% (7MB)
28 10:54:42.522162 progress 35% (9MB)
29 10:54:42.529651 progress 40% (10MB)
30 10:54:42.537031 progress 45% (11MB)
31 10:54:42.544637 progress 50% (12MB)
32 10:54:42.551712 progress 55% (14MB)
33 10:54:42.558897 progress 60% (15MB)
34 10:54:42.565872 progress 65% (16MB)
35 10:54:42.573182 progress 70% (18MB)
36 10:54:42.580386 progress 75% (19MB)
37 10:54:42.587549 progress 80% (20MB)
38 10:54:42.594845 progress 85% (22MB)
39 10:54:42.601898 progress 90% (23MB)
40 10:54:42.609019 progress 95% (24MB)
41 10:54:42.616086 progress 100% (25MB)
42 10:54:42.616286 25MB downloaded in 0.15s (174.41MB/s)
43 10:54:42.616440 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:54:42.616693 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:54:42.616786 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:54:42.616870 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:54:42.616996 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:54:42.617078 saving as /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/kernel/Image
50 10:54:42.617138 total size: 45746688 (43MB)
51 10:54:42.617197 No compression specified
52 10:54:42.618464 progress 0% (0MB)
53 10:54:42.631039 progress 5% (2MB)
54 10:54:42.642922 progress 10% (4MB)
55 10:54:42.654870 progress 15% (6MB)
56 10:54:42.666833 progress 20% (8MB)
57 10:54:42.678638 progress 25% (10MB)
58 10:54:42.690352 progress 30% (13MB)
59 10:54:42.702271 progress 35% (15MB)
60 10:54:42.714184 progress 40% (17MB)
61 10:54:42.726082 progress 45% (19MB)
62 10:54:42.738089 progress 50% (21MB)
63 10:54:42.749660 progress 55% (24MB)
64 10:54:42.761416 progress 60% (26MB)
65 10:54:42.773088 progress 65% (28MB)
66 10:54:42.784735 progress 70% (30MB)
67 10:54:42.796366 progress 75% (32MB)
68 10:54:42.808052 progress 80% (34MB)
69 10:54:42.819899 progress 85% (37MB)
70 10:54:42.831638 progress 90% (39MB)
71 10:54:42.843441 progress 95% (41MB)
72 10:54:42.855013 progress 100% (43MB)
73 10:54:42.855156 43MB downloaded in 0.24s (183.30MB/s)
74 10:54:42.855402 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:54:42.855671 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:54:42.855774 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:54:42.855883 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:54:42.856042 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:54:42.856156 saving as /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/dtb/mt8192-asurada-spherion-r0.dtb
81 10:54:42.856256 total size: 46924 (0MB)
82 10:54:42.856354 No compression specified
83 10:54:42.858075 progress 69% (0MB)
84 10:54:42.858384 progress 100% (0MB)
85 10:54:42.858580 0MB downloaded in 0.00s (19.27MB/s)
86 10:54:42.858719 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:54:42.858977 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:54:42.859112 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:54:42.859236 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:54:42.859437 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:54:42.859511 saving as /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/modules/modules.tar
93 10:54:42.859592 total size: 8542412 (8MB)
94 10:54:42.859680 Using unxz to decompress xz
95 10:54:42.863104 progress 0% (0MB)
96 10:54:42.884659 progress 5% (0MB)
97 10:54:42.909139 progress 10% (0MB)
98 10:54:42.935009 progress 15% (1MB)
99 10:54:42.959632 progress 20% (1MB)
100 10:54:42.984888 progress 25% (2MB)
101 10:54:43.009458 progress 30% (2MB)
102 10:54:43.035047 progress 35% (2MB)
103 10:54:43.059838 progress 40% (3MB)
104 10:54:43.084562 progress 45% (3MB)
105 10:54:43.108065 progress 50% (4MB)
106 10:54:43.131204 progress 55% (4MB)
107 10:54:43.156726 progress 60% (4MB)
108 10:54:43.181849 progress 65% (5MB)
109 10:54:43.207646 progress 70% (5MB)
110 10:54:43.235450 progress 75% (6MB)
111 10:54:43.265355 progress 80% (6MB)
112 10:54:43.287782 progress 85% (6MB)
113 10:54:43.312756 progress 90% (7MB)
114 10:54:43.336188 progress 95% (7MB)
115 10:54:43.359940 progress 100% (8MB)
116 10:54:43.365682 8MB downloaded in 0.51s (16.10MB/s)
117 10:54:43.365978 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:54:43.366272 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:54:43.366382 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:54:43.366498 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:54:43.366636 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:54:43.366770 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:54:43.367046 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv
125 10:54:43.367216 makedir: /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin
126 10:54:43.367403 makedir: /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/tests
127 10:54:43.367541 makedir: /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/results
128 10:54:43.367701 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-add-keys
129 10:54:43.367895 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-add-sources
130 10:54:43.368043 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-background-process-start
131 10:54:43.368203 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-background-process-stop
132 10:54:43.368373 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-common-functions
133 10:54:43.368552 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-echo-ipv4
134 10:54:43.368731 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-install-packages
135 10:54:43.368885 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-installed-packages
136 10:54:43.369034 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-os-build
137 10:54:43.369201 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-probe-channel
138 10:54:43.369372 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-probe-ip
139 10:54:43.369512 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-target-ip
140 10:54:43.369660 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-target-mac
141 10:54:43.369802 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-target-storage
142 10:54:43.369977 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-case
143 10:54:43.370118 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-event
144 10:54:43.370264 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-feedback
145 10:54:43.370405 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-raise
146 10:54:43.370583 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-reference
147 10:54:43.370754 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-runner
148 10:54:43.370896 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-set
149 10:54:43.371044 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-test-shell
150 10:54:43.371193 Updating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-install-packages (oe)
151 10:54:43.371431 Updating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/bin/lava-installed-packages (oe)
152 10:54:43.371609 Creating /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/environment
153 10:54:43.371746 LAVA metadata
154 10:54:43.371841 - LAVA_JOB_ID=10590987
155 10:54:43.371931 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:54:43.372062 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:54:43.372135 skipped lava-vland-overlay
158 10:54:43.372266 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:54:43.372390 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:54:43.372494 skipped lava-multinode-overlay
161 10:54:43.372613 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:54:43.372749 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:54:43.372875 Loading test definitions
164 10:54:43.373013 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:54:43.373108 Using /lava-10590987 at stage 0
166 10:54:43.373505 uuid=10590987_1.5.2.3.1 testdef=None
167 10:54:43.373628 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:54:43.373762 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:54:43.374286 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:54:43.374536 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:54:43.375306 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:54:43.375613 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:54:43.376223 runner path: /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/0/tests/0_v4l2-compliance-uvc test_uuid 10590987_1.5.2.3.1
176 10:54:43.376401 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:54:43.376632 Creating lava-test-runner.conf files
179 10:54:43.376719 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10590987/lava-overlay-wc37y0wv/lava-10590987/0 for stage 0
180 10:54:43.376863 - 0_v4l2-compliance-uvc
181 10:54:43.377007 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:54:43.377130 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:54:43.383967 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:54:43.384092 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:54:43.384193 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:54:43.384295 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:54:43.384409 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:54:44.098374 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:54:44.098763 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:54:44.098926 extracting modules file /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10590987/extract-overlay-ramdisk-1hylddgg/ramdisk
191 10:54:44.315254 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:54:44.315471 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:54:44.315588 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590987/compress-overlay-y7xiktr9/overlay-1.5.2.4.tar.gz to ramdisk
194 10:54:44.315703 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10590987/compress-overlay-y7xiktr9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10590987/extract-overlay-ramdisk-1hylddgg/ramdisk
195 10:54:44.322313 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:54:44.322444 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:54:44.322552 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:54:44.322668 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:54:44.322786 Building ramdisk /var/lib/lava/dispatcher/tmp/10590987/extract-overlay-ramdisk-1hylddgg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10590987/extract-overlay-ramdisk-1hylddgg/ramdisk
200 10:54:44.854646 >> 230336 blocks
201 10:54:48.952754 rename /var/lib/lava/dispatcher/tmp/10590987/extract-overlay-ramdisk-1hylddgg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/ramdisk/ramdisk.cpio.gz
202 10:54:48.953312 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:54:48.953491 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 10:54:48.953644 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 10:54:48.953794 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/kernel/Image'
206 10:55:01.174765 Returned 0 in 12 seconds
207 10:55:01.275746 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/kernel/image.itb
208 10:55:01.872063 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:55:01.872413 output: Created: Mon Jun 5 11:55:01 2023
210 10:55:01.872490 output: Image 0 (kernel-1)
211 10:55:01.872556 output: Description:
212 10:55:01.872618 output: Created: Mon Jun 5 11:55:01 2023
213 10:55:01.872681 output: Type: Kernel Image
214 10:55:01.872744 output: Compression: lzma compressed
215 10:55:01.872803 output: Data Size: 10081937 Bytes = 9845.64 KiB = 9.61 MiB
216 10:55:01.872860 output: Architecture: AArch64
217 10:55:01.872918 output: OS: Linux
218 10:55:01.872975 output: Load Address: 0x00000000
219 10:55:01.873031 output: Entry Point: 0x00000000
220 10:55:01.873085 output: Hash algo: crc32
221 10:55:01.873140 output: Hash value: 8ce42972
222 10:55:01.873193 output: Image 1 (fdt-1)
223 10:55:01.873246 output: Description: mt8192-asurada-spherion-r0
224 10:55:01.873299 output: Created: Mon Jun 5 11:55:01 2023
225 10:55:01.873352 output: Type: Flat Device Tree
226 10:55:01.873405 output: Compression: uncompressed
227 10:55:01.873458 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 10:55:01.873511 output: Architecture: AArch64
229 10:55:01.873564 output: Hash algo: crc32
230 10:55:01.873617 output: Hash value: 1df858fa
231 10:55:01.873670 output: Image 2 (ramdisk-1)
232 10:55:01.873723 output: Description: unavailable
233 10:55:01.873775 output: Created: Mon Jun 5 11:55:01 2023
234 10:55:01.873828 output: Type: RAMDisk Image
235 10:55:01.873881 output: Compression: Unknown Compression
236 10:55:01.873934 output: Data Size: 40121099 Bytes = 39180.76 KiB = 38.26 MiB
237 10:55:01.873988 output: Architecture: AArch64
238 10:55:01.874041 output: OS: Linux
239 10:55:01.874094 output: Load Address: unavailable
240 10:55:01.874147 output: Entry Point: unavailable
241 10:55:01.874200 output: Hash algo: crc32
242 10:55:01.874252 output: Hash value: 5b947d36
243 10:55:01.874304 output: Default Configuration: 'conf-1'
244 10:55:01.874358 output: Configuration 0 (conf-1)
245 10:55:01.874411 output: Description: mt8192-asurada-spherion-r0
246 10:55:01.874464 output: Kernel: kernel-1
247 10:55:01.874517 output: Init Ramdisk: ramdisk-1
248 10:55:01.874570 output: FDT: fdt-1
249 10:55:01.874623 output: Loadables: kernel-1
250 10:55:01.874675 output:
251 10:55:01.874866 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:55:01.874963 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:55:01.875066 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 10:55:01.875162 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 10:55:01.875241 No LXC device requested
256 10:55:01.875320 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:55:01.875452 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 10:55:01.875531 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:55:01.875600 Checking files for TFTP limit of 4294967296 bytes.
260 10:55:01.876090 end: 1 tftp-deploy (duration 00:00:19) [common]
261 10:55:01.876194 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:55:01.876282 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:55:01.876402 substitutions:
264 10:55:01.876469 - {DTB}: 10590987/tftp-deploy-k5gx8mcg/dtb/mt8192-asurada-spherion-r0.dtb
265 10:55:01.876572 - {INITRD}: 10590987/tftp-deploy-k5gx8mcg/ramdisk/ramdisk.cpio.gz
266 10:55:01.876632 - {KERNEL}: 10590987/tftp-deploy-k5gx8mcg/kernel/Image
267 10:55:01.876689 - {LAVA_MAC}: None
268 10:55:01.876746 - {PRESEED_CONFIG}: None
269 10:55:01.876801 - {PRESEED_LOCAL}: None
270 10:55:01.876856 - {RAMDISK}: 10590987/tftp-deploy-k5gx8mcg/ramdisk/ramdisk.cpio.gz
271 10:55:01.876911 - {ROOT_PART}: None
272 10:55:01.876965 - {ROOT}: None
273 10:55:01.877019 - {SERVER_IP}: 192.168.201.1
274 10:55:01.877074 - {TEE}: None
275 10:55:01.877127 Parsed boot commands:
276 10:55:01.877181 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:55:01.877342 Parsed boot commands: tftpboot 192.168.201.1 10590987/tftp-deploy-k5gx8mcg/kernel/image.itb 10590987/tftp-deploy-k5gx8mcg/kernel/cmdline
278 10:55:01.877430 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:55:01.877516 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:55:01.877608 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:55:01.877695 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:55:01.877767 Not connected, no need to disconnect.
283 10:55:01.877842 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:55:01.877923 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:55:01.877993 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 10:55:01.881190 Setting prompt string to ['lava-test: # ']
287 10:55:01.881524 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:55:01.881632 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:55:01.881731 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:55:01.881828 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:55:01.882027 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 10:55:07.033420 >> Command sent successfully.
293 10:55:07.044806 Returned 0 in 5 seconds
294 10:55:07.146030 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:55:07.149269 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:55:07.149893 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:55:07.150550 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:55:07.151094 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:55:07.151523 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:55:07.152712 [Enter `^Ec?' for help]
302 10:55:07.307935
303 10:55:07.308502
304 10:55:07.308922 F0: 102B 0000
305 10:55:07.309328
306 10:55:07.309680 F3: 1001 0000 [0200]
307 10:55:07.311197
308 10:55:07.311675 F3: 1001 0000
309 10:55:07.312113
310 10:55:07.312472 F7: 102D 0000
311 10:55:07.312825
312 10:55:07.314546 F1: 0000 0000
313 10:55:07.314993
314 10:55:07.315525 V0: 0000 0000 [0001]
315 10:55:07.315971
316 10:55:07.317804 00: 0007 8000
317 10:55:07.318295
318 10:55:07.318652 01: 0000 0000
319 10:55:07.319063
320 10:55:07.321328 BP: 0C00 0209 [0000]
321 10:55:07.321789
322 10:55:07.322183 G0: 1182 0000
323 10:55:07.322558
324 10:55:07.325238 EC: 0000 0021 [4000]
325 10:55:07.325669
326 10:55:07.326013 S7: 0000 0000 [0000]
327 10:55:07.326335
328 10:55:07.328257 CC: 0000 0000 [0001]
329 10:55:07.328687
330 10:55:07.329030 T0: 0000 0040 [010F]
331 10:55:07.329363
332 10:55:07.329672 Jump to BL
333 10:55:07.329973
334 10:55:07.355195
335 10:55:07.355737
336 10:55:07.356236
337 10:55:07.362680 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:55:07.365979 ARM64: Exception handlers installed.
339 10:55:07.369570 ARM64: Testing exception
340 10:55:07.372985 ARM64: Done test exception
341 10:55:07.379960 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:55:07.389756 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:55:07.396909 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:55:07.407420 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:55:07.413765 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:55:07.420055 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:55:07.431784 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:55:07.438812 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:55:07.458070 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:55:07.461010 WDT: Last reset was cold boot
351 10:55:07.464700 SPI1(PAD0) initialized at 2873684 Hz
352 10:55:07.467820 SPI5(PAD0) initialized at 992727 Hz
353 10:55:07.470979 VBOOT: Loading verstage.
354 10:55:07.477996 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:55:07.481173 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:55:07.484411 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:55:07.487798 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:55:07.494975 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:55:07.501911 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:55:07.513199 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 10:55:07.513639
362 10:55:07.513971
363 10:55:07.523216 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:55:07.526551 ARM64: Exception handlers installed.
365 10:55:07.529644 ARM64: Testing exception
366 10:55:07.530079 ARM64: Done test exception
367 10:55:07.536692 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:55:07.539861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:55:07.553424 Probing TPM: . done!
370 10:55:07.553852 TPM ready after 0 ms
371 10:55:07.561025 Connected to device vid:did:rid of 1ae0:0028:00
372 10:55:07.568096 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 10:55:07.628278 Initialized TPM device CR50 revision 0
374 10:55:07.639828 tlcl_send_startup: Startup return code is 0
375 10:55:07.640433 TPM: setup succeeded
376 10:55:07.651130 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:55:07.659991 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:55:07.674170 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:55:07.681198 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:55:07.685382 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:55:07.689117 in-header: 03 07 00 00 08 00 00 00
382 10:55:07.692941 in-data: aa e4 47 04 13 02 00 00
383 10:55:07.693039 Chrome EC: UHEPI supported
384 10:55:07.699592 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:55:07.702759 in-header: 03 95 00 00 08 00 00 00
386 10:55:07.706659 in-data: 18 20 20 08 00 00 00 00
387 10:55:07.706741 Phase 1
388 10:55:07.710653 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:55:07.717892 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:55:07.724985 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:55:07.728811 Recovery requested (1009000e)
392 10:55:07.736041 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:55:07.741292 tlcl_extend: response is 0
394 10:55:07.751018 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:55:07.756419 tlcl_extend: response is 0
396 10:55:07.763959 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:55:07.783445 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 10:55:07.790279 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:55:07.790659
400 10:55:07.790851
401 10:55:07.800583 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:55:07.803753 ARM64: Exception handlers installed.
403 10:55:07.806993 ARM64: Testing exception
404 10:55:07.807419 ARM64: Done test exception
405 10:55:07.829680 pmic_efuse_setting: Set efuses in 11 msecs
406 10:55:07.832659 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:55:07.839447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:55:07.842829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:55:07.849792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:55:07.853840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:55:07.857610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:55:07.864479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:55:07.868102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:55:07.871607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:55:07.875906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:55:07.882839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:55:07.887274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:55:07.890308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:55:07.893945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:55:07.901746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:55:07.905456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:55:07.912770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:55:07.920621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:55:07.923878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:55:07.931907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:55:07.935142 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:55:07.938957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:55:07.946431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:55:07.954262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:55:07.958074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:55:07.961354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:55:07.968878 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:55:07.972232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:55:07.979485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:55:07.983408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:55:07.987212 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:55:07.993774 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:55:07.997661 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:55:08.001755 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:55:08.009083 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:55:08.012240 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:55:08.020071 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:55:08.023137 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:55:08.026917 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:55:08.034182 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:55:08.037900 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:55:08.041279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:55:08.045209 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:55:08.048586 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:55:08.056242 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:55:08.060095 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:55:08.064034 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:55:08.067397 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:55:08.071142 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:55:08.074973 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:55:08.082126 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:55:08.085707 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:55:08.093441 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:55:08.101222 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:55:08.104959 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:55:08.112014 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:55:08.122465 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:55:08.126645 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:55:08.129747 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:55:08.133606 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:55:08.142775 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 10:55:08.146120 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:55:08.151280 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 10:55:08.157649 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:55:08.166863 [RTC]rtc_get_frequency_meter,154: input=15, output=757
471 10:55:08.176742 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 10:55:08.185773 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 10:55:08.195578 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 10:55:08.205010 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 10:55:08.214369 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 10:55:08.224064 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 10:55:08.227763 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 10:55:08.231813 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 10:55:08.235451 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:55:08.242943 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:55:08.246868 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:55:08.250175 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:55:08.253947 ADC[4]: Raw value=906203 ID=7
484 10:55:08.254461 ADC[3]: Raw value=213441 ID=1
485 10:55:08.257990 RAM Code: 0x71
486 10:55:08.261634 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:55:08.264961 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:55:08.276378 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:55:08.280844 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:55:08.284162 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:55:08.288048 in-header: 03 07 00 00 08 00 00 00
492 10:55:08.292739 in-data: aa e4 47 04 13 02 00 00
493 10:55:08.295898 Chrome EC: UHEPI supported
494 10:55:08.303305 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:55:08.306516 in-header: 03 95 00 00 08 00 00 00
496 10:55:08.311005 in-data: 18 20 20 08 00 00 00 00
497 10:55:08.311486 MRC: failed to locate region type 0.
498 10:55:08.317838 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:55:08.321560 DRAM-K: Running full calibration
500 10:55:08.329352 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:55:08.329785 header.status = 0x0
502 10:55:08.333333 header.version = 0x6 (expected: 0x6)
503 10:55:08.337103 header.size = 0xd00 (expected: 0xd00)
504 10:55:08.337539 header.flags = 0x0
505 10:55:08.344014 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:55:08.362613 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 10:55:08.370297 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:55:08.370728 dram_init: ddr_geometry: 2
509 10:55:08.374185 [EMI] MDL number = 2
510 10:55:08.374668 [EMI] Get MDL freq = 0
511 10:55:08.377960 dram_init: ddr_type: 0
512 10:55:08.378601 is_discrete_lpddr4: 1
513 10:55:08.382054 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:55:08.382561
515 10:55:08.383089
516 10:55:08.385914 [Bian_co] ETT version 0.0.0.1
517 10:55:08.389154 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:55:08.389587
519 10:55:08.396340 dramc_set_vcore_voltage set vcore to 650000
520 10:55:08.396763 Read voltage for 800, 4
521 10:55:08.397102 Vio18 = 0
522 10:55:08.400586 Vcore = 650000
523 10:55:08.401010 Vdram = 0
524 10:55:08.401348 Vddq = 0
525 10:55:08.401661 Vmddr = 0
526 10:55:08.404386 dram_init: config_dvfs: 1
527 10:55:08.408103 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:55:08.415754 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:55:08.419421 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 10:55:08.424011 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 10:55:08.426869 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 10:55:08.430623 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 10:55:08.431222 MEM_TYPE=3, freq_sel=18
534 10:55:08.433877 sv_algorithm_assistance_LP4_1600
535 10:55:08.440620 ============ PULL DRAM RESETB DOWN ============
536 10:55:08.443612 ========== PULL DRAM RESETB DOWN end =========
537 10:55:08.447440 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:55:08.450611 ===================================
539 10:55:08.454213 LPDDR4 DRAM CONFIGURATION
540 10:55:08.458072 ===================================
541 10:55:08.458499 EX_ROW_EN[0] = 0x0
542 10:55:08.461324 EX_ROW_EN[1] = 0x0
543 10:55:08.461747 LP4Y_EN = 0x0
544 10:55:08.465330 WORK_FSP = 0x0
545 10:55:08.465795 WL = 0x2
546 10:55:08.468587 RL = 0x2
547 10:55:08.469011 BL = 0x2
548 10:55:08.472253 RPST = 0x0
549 10:55:08.472701 RD_PRE = 0x0
550 10:55:08.476114 WR_PRE = 0x1
551 10:55:08.476537 WR_PST = 0x0
552 10:55:08.479533 DBI_WR = 0x0
553 10:55:08.480050 DBI_RD = 0x0
554 10:55:08.482849 OTF = 0x1
555 10:55:08.486297 ===================================
556 10:55:08.489716 ===================================
557 10:55:08.490158 ANA top config
558 10:55:08.492779 ===================================
559 10:55:08.496073 DLL_ASYNC_EN = 0
560 10:55:08.499394 ALL_SLAVE_EN = 1
561 10:55:08.499911 NEW_RANK_MODE = 1
562 10:55:08.502841 DLL_IDLE_MODE = 1
563 10:55:08.506216 LP45_APHY_COMB_EN = 1
564 10:55:08.509185 TX_ODT_DIS = 1
565 10:55:08.509713 NEW_8X_MODE = 1
566 10:55:08.512739 ===================================
567 10:55:08.516363 ===================================
568 10:55:08.520130 data_rate = 1600
569 10:55:08.523455 CKR = 1
570 10:55:08.526909 DQ_P2S_RATIO = 8
571 10:55:08.530241 ===================================
572 10:55:08.533260 CA_P2S_RATIO = 8
573 10:55:08.533683 DQ_CA_OPEN = 0
574 10:55:08.537058 DQ_SEMI_OPEN = 0
575 10:55:08.540020 CA_SEMI_OPEN = 0
576 10:55:08.543485 CA_FULL_RATE = 0
577 10:55:08.546574 DQ_CKDIV4_EN = 1
578 10:55:08.550337 CA_CKDIV4_EN = 1
579 10:55:08.550860 CA_PREDIV_EN = 0
580 10:55:08.553208 PH8_DLY = 0
581 10:55:08.556955 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:55:08.559861 DQ_AAMCK_DIV = 4
583 10:55:08.563552 CA_AAMCK_DIV = 4
584 10:55:08.564009 CA_ADMCK_DIV = 4
585 10:55:08.566545 DQ_TRACK_CA_EN = 0
586 10:55:08.569868 CA_PICK = 800
587 10:55:08.573828 CA_MCKIO = 800
588 10:55:08.577467 MCKIO_SEMI = 0
589 10:55:08.581287 PLL_FREQ = 3068
590 10:55:08.581806 DQ_UI_PI_RATIO = 32
591 10:55:08.585214 CA_UI_PI_RATIO = 0
592 10:55:08.588986 ===================================
593 10:55:08.592112 ===================================
594 10:55:08.592567 memory_type:LPDDR4
595 10:55:08.596067 GP_NUM : 10
596 10:55:08.599900 SRAM_EN : 1
597 10:55:08.600320 MD32_EN : 0
598 10:55:08.603646 ===================================
599 10:55:08.607589 [ANA_INIT] >>>>>>>>>>>>>>
600 10:55:08.608154 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:55:08.611414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:55:08.614691 ===================================
603 10:55:08.618409 data_rate = 1600,PCW = 0X7600
604 10:55:08.621550 ===================================
605 10:55:08.624853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:55:08.631635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:55:08.634924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:55:08.641401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:55:08.645201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:55:08.648026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:55:08.648454 [ANA_INIT] flow start
612 10:55:08.651415 [ANA_INIT] PLL >>>>>>>>
613 10:55:08.655025 [ANA_INIT] PLL <<<<<<<<
614 10:55:08.655505 [ANA_INIT] MIDPI >>>>>>>>
615 10:55:08.657874 [ANA_INIT] MIDPI <<<<<<<<
616 10:55:08.661529 [ANA_INIT] DLL >>>>>>>>
617 10:55:08.662009 [ANA_INIT] flow end
618 10:55:08.668017 ============ LP4 DIFF to SE enter ============
619 10:55:08.671682 ============ LP4 DIFF to SE exit ============
620 10:55:08.674685 [ANA_INIT] <<<<<<<<<<<<<
621 10:55:08.678032 [Flow] Enable top DCM control >>>>>
622 10:55:08.681632 [Flow] Enable top DCM control <<<<<
623 10:55:08.682201 Enable DLL master slave shuffle
624 10:55:08.687854 ==============================================================
625 10:55:08.691157 Gating Mode config
626 10:55:08.695430 ==============================================================
627 10:55:08.698605 Config description:
628 10:55:08.708474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:55:08.715555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:55:08.718835 SELPH_MODE 0: By rank 1: By Phase
631 10:55:08.724910 ==============================================================
632 10:55:08.728838 GAT_TRACK_EN = 1
633 10:55:08.731872 RX_GATING_MODE = 2
634 10:55:08.732293 RX_GATING_TRACK_MODE = 2
635 10:55:08.735481 SELPH_MODE = 1
636 10:55:08.738518 PICG_EARLY_EN = 1
637 10:55:08.741644 VALID_LAT_VALUE = 1
638 10:55:08.748952 ==============================================================
639 10:55:08.752041 Enter into Gating configuration >>>>
640 10:55:08.754893 Exit from Gating configuration <<<<
641 10:55:08.758555 Enter into DVFS_PRE_config >>>>>
642 10:55:08.768498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:55:08.771780 Exit from DVFS_PRE_config <<<<<
644 10:55:08.775266 Enter into PICG configuration >>>>
645 10:55:08.778384 Exit from PICG configuration <<<<
646 10:55:08.781984 [RX_INPUT] configuration >>>>>
647 10:55:08.785222 [RX_INPUT] configuration <<<<<
648 10:55:08.788734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:55:08.795631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:55:08.802353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:55:08.805593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:55:08.812010 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:55:08.818725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:55:08.822765 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:55:08.825852 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:55:08.832262 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:55:08.835416 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:55:08.838764 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:55:08.845526 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:55:08.846132 ===================================
661 10:55:08.848953 LPDDR4 DRAM CONFIGURATION
662 10:55:08.852200 ===================================
663 10:55:08.855516 EX_ROW_EN[0] = 0x0
664 10:55:08.856099 EX_ROW_EN[1] = 0x0
665 10:55:08.858704 LP4Y_EN = 0x0
666 10:55:08.859293 WORK_FSP = 0x0
667 10:55:08.861724 WL = 0x2
668 10:55:08.862297 RL = 0x2
669 10:55:08.865531 BL = 0x2
670 10:55:08.868787 RPST = 0x0
671 10:55:08.869283 RD_PRE = 0x0
672 10:55:08.872369 WR_PRE = 0x1
673 10:55:08.872976 WR_PST = 0x0
674 10:55:08.875146 DBI_WR = 0x0
675 10:55:08.875789 DBI_RD = 0x0
676 10:55:08.878972 OTF = 0x1
677 10:55:08.882456 ===================================
678 10:55:08.885281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:55:08.888974 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:55:08.891884 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:55:08.895293 ===================================
682 10:55:08.899004 LPDDR4 DRAM CONFIGURATION
683 10:55:08.902326 ===================================
684 10:55:08.905592 EX_ROW_EN[0] = 0x10
685 10:55:08.906107 EX_ROW_EN[1] = 0x0
686 10:55:08.908796 LP4Y_EN = 0x0
687 10:55:08.909342 WORK_FSP = 0x0
688 10:55:08.912347 WL = 0x2
689 10:55:08.912769 RL = 0x2
690 10:55:08.915266 BL = 0x2
691 10:55:08.915744 RPST = 0x0
692 10:55:08.918819 RD_PRE = 0x0
693 10:55:08.919377 WR_PRE = 0x1
694 10:55:08.922787 WR_PST = 0x0
695 10:55:08.923368 DBI_WR = 0x0
696 10:55:08.925996 DBI_RD = 0x0
697 10:55:08.926518 OTF = 0x1
698 10:55:08.928966 ===================================
699 10:55:08.935663 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:55:08.940105 nWR fixed to 40
701 10:55:08.943979 [ModeRegInit_LP4] CH0 RK0
702 10:55:08.944505 [ModeRegInit_LP4] CH0 RK1
703 10:55:08.947119 [ModeRegInit_LP4] CH1 RK0
704 10:55:08.951012 [ModeRegInit_LP4] CH1 RK1
705 10:55:08.951575 match AC timing 13
706 10:55:08.957315 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:55:08.960537 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:55:08.963757 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:55:08.970894 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:55:08.973732 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:55:08.974156 [EMI DOE] emi_dcm 0
712 10:55:08.980703 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:55:08.981225 ==
714 10:55:08.984012 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:55:08.987061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:55:08.987606 ==
717 10:55:08.994134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:55:08.997232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:55:09.007435 [CA 0] Center 36 (6~67) winsize 62
720 10:55:09.010988 [CA 1] Center 36 (6~67) winsize 62
721 10:55:09.014357 [CA 2] Center 34 (4~65) winsize 62
722 10:55:09.018195 [CA 3] Center 33 (3~64) winsize 62
723 10:55:09.020912 [CA 4] Center 33 (2~64) winsize 63
724 10:55:09.024325 [CA 5] Center 32 (2~62) winsize 61
725 10:55:09.024897
726 10:55:09.027456 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:55:09.027920
728 10:55:09.030845 [CATrainingPosCal] consider 1 rank data
729 10:55:09.034855 u2DelayCellTimex100 = 270/100 ps
730 10:55:09.037887 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 10:55:09.041107 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 10:55:09.047860 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 10:55:09.050709 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 10:55:09.054307 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 10:55:09.057356 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 10:55:09.057807
737 10:55:09.060637 CA PerBit enable=1, Macro0, CA PI delay=32
738 10:55:09.061103
739 10:55:09.064339 [CBTSetCACLKResult] CA Dly = 32
740 10:55:09.064839 CS Dly: 4 (0~35)
741 10:55:09.067539 ==
742 10:55:09.067991 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:55:09.074526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:55:09.075059 ==
745 10:55:09.077588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:55:09.084568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:55:09.094023 [CA 0] Center 36 (6~67) winsize 62
748 10:55:09.097272 [CA 1] Center 36 (6~67) winsize 62
749 10:55:09.100631 [CA 2] Center 34 (4~65) winsize 62
750 10:55:09.103708 [CA 3] Center 33 (3~64) winsize 62
751 10:55:09.107462 [CA 4] Center 32 (2~63) winsize 62
752 10:55:09.110860 [CA 5] Center 32 (2~63) winsize 62
753 10:55:09.111460
754 10:55:09.113632 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 10:55:09.114197
756 10:55:09.117405 [CATrainingPosCal] consider 2 rank data
757 10:55:09.120622 u2DelayCellTimex100 = 270/100 ps
758 10:55:09.124053 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 10:55:09.127298 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 10:55:09.133969 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 10:55:09.137884 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 10:55:09.141271 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 10:55:09.144215 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 10:55:09.144692
765 10:55:09.147833 CA PerBit enable=1, Macro0, CA PI delay=32
766 10:55:09.148409
767 10:55:09.150794 [CBTSetCACLKResult] CA Dly = 32
768 10:55:09.151266 CS Dly: 5 (0~37)
769 10:55:09.151684
770 10:55:09.153878 ----->DramcWriteLeveling(PI) begin...
771 10:55:09.154361 ==
772 10:55:09.157685 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:55:09.161580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:55:09.162143 ==
775 10:55:09.165402 Write leveling (Byte 0): 34 => 34
776 10:55:09.168994 Write leveling (Byte 1): 30 => 30
777 10:55:09.172803 DramcWriteLeveling(PI) end<-----
778 10:55:09.173286
779 10:55:09.173773 ==
780 10:55:09.175840 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:55:09.179036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:55:09.179510 ==
783 10:55:09.182319 [Gating] SW mode calibration
784 10:55:09.189131 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:55:09.196357 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:55:09.199406 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:55:09.202626 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 10:55:09.209671 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 10:55:09.212996 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:55:09.216444 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:55:09.223289 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:55:09.226525 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:55:09.229810 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:55:09.236442 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:55:09.239921 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:55:09.243181 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:55:09.246519 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:55:09.253518 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:55:09.256571 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:55:09.259892 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:55:09.266705 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:55:09.270032 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:55:09.273075 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:55:09.280164 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 10:55:09.283213 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:55:09.287006 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:55:09.293608 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:55:09.296921 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:55:09.300040 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:55:09.307473 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:55:09.310355 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:55:09.313332 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
813 10:55:09.320367 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 10:55:09.323373 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:55:09.326713 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:55:09.329822 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:55:09.336288 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:55:09.340021 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:55:09.343926 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
820 10:55:09.349813 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 0) (1 1)
821 10:55:09.353916 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 10:55:09.356977 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:55:09.363449 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:55:09.366783 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:55:09.370604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:55:09.376671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:55:09.380138 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 10:55:09.383604 0 11 8 | B1->B0 | 2929 3c3c | 0 1 | (0 0) (0 0)
829 10:55:09.390113 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 10:55:09.393651 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:55:09.396773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:55:09.403612 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:55:09.407076 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:55:09.410308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:55:09.413305 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 10:55:09.420414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 10:55:09.423434 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:55:09.427399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:55:09.433432 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:55:09.436827 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:55:09.440174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:55:09.447001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:55:09.449903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:55:09.453667 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:55:09.460000 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:55:09.463411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:55:09.467087 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:55:09.473324 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:55:09.476690 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:55:09.479994 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:55:09.487009 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:55:09.490159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:55:09.493731 Total UI for P1: 0, mck2ui 16
854 10:55:09.496923 best dqsien dly found for B0: ( 0, 14, 6)
855 10:55:09.500129 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:55:09.503379 Total UI for P1: 0, mck2ui 16
857 10:55:09.507388 best dqsien dly found for B1: ( 0, 14, 8)
858 10:55:09.511230 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 10:55:09.514432 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 10:55:09.515008
861 10:55:09.517650 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 10:55:09.520676 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:55:09.524436 [Gating] SW calibration Done
864 10:55:09.524999 ==
865 10:55:09.527754 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:55:09.530836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:55:09.531311 ==
868 10:55:09.534048 RX Vref Scan: 0
869 10:55:09.534612
870 10:55:09.537511 RX Vref 0 -> 0, step: 1
871 10:55:09.537983
872 10:55:09.538425 RX Delay -130 -> 252, step: 16
873 10:55:09.543974 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 10:55:09.547688 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 10:55:09.551075 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 10:55:09.554549 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 10:55:09.557644 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 10:55:09.564500 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 10:55:09.567560 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 10:55:09.570757 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 10:55:09.574789 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 10:55:09.577714 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 10:55:09.584250 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
884 10:55:09.587536 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 10:55:09.590582 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 10:55:09.594702 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 10:55:09.597964 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 10:55:09.604124 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 10:55:09.604649 ==
890 10:55:09.607658 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:55:09.611057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:55:09.611531 ==
893 10:55:09.611879 DQS Delay:
894 10:55:09.614256 DQS0 = 0, DQS1 = 0
895 10:55:09.614691 DQM Delay:
896 10:55:09.617553 DQM0 = 89, DQM1 = 85
897 10:55:09.618072 DQ Delay:
898 10:55:09.620535 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 10:55:09.624217 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 10:55:09.627705 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
901 10:55:09.631211 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 10:55:09.631769
903 10:55:09.632112
904 10:55:09.632429 ==
905 10:55:09.634361 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:55:09.637558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:55:09.638121 ==
908 10:55:09.638551
909 10:55:09.638874
910 10:55:09.640973 TX Vref Scan disable
911 10:55:09.643967 == TX Byte 0 ==
912 10:55:09.647748 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 10:55:09.650782 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 10:55:09.654711 == TX Byte 1 ==
915 10:55:09.658009 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 10:55:09.660903 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 10:55:09.661330 ==
918 10:55:09.664648 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:55:09.670572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:55:09.671002 ==
921 10:55:09.682546 TX Vref=22, minBit 3, minWin=27, winSum=445
922 10:55:09.686314 TX Vref=24, minBit 10, minWin=27, winSum=452
923 10:55:09.689635 TX Vref=26, minBit 7, minWin=28, winSum=457
924 10:55:09.692981 TX Vref=28, minBit 5, minWin=28, winSum=455
925 10:55:09.696273 TX Vref=30, minBit 5, minWin=28, winSum=456
926 10:55:09.699431 TX Vref=32, minBit 2, minWin=28, winSum=453
927 10:55:09.706302 [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 26
928 10:55:09.706898
929 10:55:09.709506 Final TX Range 1 Vref 26
930 10:55:09.709931
931 10:55:09.710267 ==
932 10:55:09.712598 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:55:09.716191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:55:09.716642 ==
935 10:55:09.719659
936 10:55:09.720128
937 10:55:09.720469 TX Vref Scan disable
938 10:55:09.722730 == TX Byte 0 ==
939 10:55:09.726399 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 10:55:09.729591 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 10:55:09.732946 == TX Byte 1 ==
942 10:55:09.735973 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 10:55:09.739301 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 10:55:09.743238
945 10:55:09.743711 [DATLAT]
946 10:55:09.744051 Freq=800, CH0 RK0
947 10:55:09.744368
948 10:55:09.746256 DATLAT Default: 0xa
949 10:55:09.746766 0, 0xFFFF, sum = 0
950 10:55:09.749176 1, 0xFFFF, sum = 0
951 10:55:09.749706 2, 0xFFFF, sum = 0
952 10:55:09.753200 3, 0xFFFF, sum = 0
953 10:55:09.753630 4, 0xFFFF, sum = 0
954 10:55:09.756266 5, 0xFFFF, sum = 0
955 10:55:09.759309 6, 0xFFFF, sum = 0
956 10:55:09.759816 7, 0xFFFF, sum = 0
957 10:55:09.762963 8, 0xFFFF, sum = 0
958 10:55:09.763595 9, 0x0, sum = 1
959 10:55:09.763954 10, 0x0, sum = 2
960 10:55:09.765903 11, 0x0, sum = 3
961 10:55:09.766470 12, 0x0, sum = 4
962 10:55:09.769635 best_step = 10
963 10:55:09.770057
964 10:55:09.770595 ==
965 10:55:09.773000 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:55:09.776197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:55:09.776663 ==
968 10:55:09.779265 RX Vref Scan: 1
969 10:55:09.779787
970 10:55:09.780171 Set Vref Range= 32 -> 127
971 10:55:09.780497
972 10:55:09.782992 RX Vref 32 -> 127, step: 1
973 10:55:09.783573
974 10:55:09.785888 RX Delay -95 -> 252, step: 8
975 10:55:09.786458
976 10:55:09.789284 Set Vref, RX VrefLevel [Byte0]: 32
977 10:55:09.793136 [Byte1]: 32
978 10:55:09.793590
979 10:55:09.796475 Set Vref, RX VrefLevel [Byte0]: 33
980 10:55:09.799685 [Byte1]: 33
981 10:55:09.802928
982 10:55:09.803539 Set Vref, RX VrefLevel [Byte0]: 34
983 10:55:09.806190 [Byte1]: 34
984 10:55:09.810580
985 10:55:09.811002 Set Vref, RX VrefLevel [Byte0]: 35
986 10:55:09.814315 [Byte1]: 35
987 10:55:09.818758
988 10:55:09.819179 Set Vref, RX VrefLevel [Byte0]: 36
989 10:55:09.822041 [Byte1]: 36
990 10:55:09.825832
991 10:55:09.829372 Set Vref, RX VrefLevel [Byte0]: 37
992 10:55:09.829794 [Byte1]: 37
993 10:55:09.834161
994 10:55:09.834622 Set Vref, RX VrefLevel [Byte0]: 38
995 10:55:09.837254 [Byte1]: 38
996 10:55:09.841788
997 10:55:09.842208 Set Vref, RX VrefLevel [Byte0]: 39
998 10:55:09.844835 [Byte1]: 39
999 10:55:09.849182
1000 10:55:09.849685 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:55:09.852710 [Byte1]: 40
1002 10:55:09.855987
1003 10:55:09.856448 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:55:09.859363 [Byte1]: 41
1005 10:55:09.864000
1006 10:55:09.864422 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:55:09.867112 [Byte1]: 42
1008 10:55:09.871370
1009 10:55:09.871798 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:55:09.874899 [Byte1]: 43
1011 10:55:09.879198
1012 10:55:09.879712 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:55:09.882588 [Byte1]: 44
1014 10:55:09.886964
1015 10:55:09.887615 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:55:09.890218 [Byte1]: 45
1017 10:55:09.894433
1018 10:55:09.894919 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:55:09.897420 [Byte1]: 46
1020 10:55:09.901885
1021 10:55:09.902495 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:55:09.905193 [Byte1]: 47
1023 10:55:09.909659
1024 10:55:09.910077 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:55:09.913024 [Byte1]: 48
1026 10:55:09.917538
1027 10:55:09.918047 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:55:09.920626 [Byte1]: 49
1029 10:55:09.925133
1030 10:55:09.925546 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:55:09.928271 [Byte1]: 50
1032 10:55:09.932836
1033 10:55:09.933370 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:55:09.936181 [Byte1]: 51
1035 10:55:09.940441
1036 10:55:09.940966 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:55:09.943560 [Byte1]: 52
1038 10:55:09.948045
1039 10:55:09.948564 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:55:09.950984 [Byte1]: 53
1041 10:55:09.955584
1042 10:55:09.956134 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:55:09.958357 [Byte1]: 54
1044 10:55:09.963020
1045 10:55:09.963566 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:55:09.966102 [Byte1]: 55
1047 10:55:09.970951
1048 10:55:09.971508 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:55:09.974111 [Byte1]: 56
1050 10:55:09.978194
1051 10:55:09.978717 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:55:09.981448 [Byte1]: 57
1053 10:55:09.985673
1054 10:55:09.986185 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:55:09.988799 [Byte1]: 58
1056 10:55:09.993022
1057 10:55:09.993573 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:55:09.996744 [Byte1]: 59
1059 10:55:10.001060
1060 10:55:10.001571 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:55:10.004084 [Byte1]: 60
1062 10:55:10.008634
1063 10:55:10.009149 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:55:10.011891 [Byte1]: 61
1065 10:55:10.016354
1066 10:55:10.016866 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:55:10.019455 [Byte1]: 62
1068 10:55:10.023675
1069 10:55:10.024097 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:55:10.026872 [Byte1]: 63
1071 10:55:10.031546
1072 10:55:10.032066 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:55:10.034754 [Byte1]: 64
1074 10:55:10.038666
1075 10:55:10.039119 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:55:10.042003 [Byte1]: 65
1077 10:55:10.046545
1078 10:55:10.047067 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:55:10.049677 [Byte1]: 66
1080 10:55:10.053760
1081 10:55:10.054372 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:55:10.056947 [Byte1]: 67
1083 10:55:10.061512
1084 10:55:10.062026 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:55:10.065039 [Byte1]: 68
1086 10:55:10.069730
1087 10:55:10.070242 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:55:10.072940 [Byte1]: 69
1089 10:55:10.076557
1090 10:55:10.076975 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:55:10.080539 [Byte1]: 70
1092 10:55:10.084385
1093 10:55:10.084914 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:55:10.088205 [Byte1]: 71
1095 10:55:10.092124
1096 10:55:10.092835 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:55:10.095542 [Byte1]: 72
1098 10:55:10.099707
1099 10:55:10.100137 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:55:10.102966 [Byte1]: 73
1101 10:55:10.107368
1102 10:55:10.107787 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:55:10.110783 [Byte1]: 74
1104 10:55:10.115202
1105 10:55:10.115767 Set Vref, RX VrefLevel [Byte0]: 75
1106 10:55:10.118097 [Byte1]: 75
1107 10:55:10.122571
1108 10:55:10.123104 Set Vref, RX VrefLevel [Byte0]: 76
1109 10:55:10.125682 [Byte1]: 76
1110 10:55:10.130045
1111 10:55:10.130562 Set Vref, RX VrefLevel [Byte0]: 77
1112 10:55:10.133135 [Byte1]: 77
1113 10:55:10.137669
1114 10:55:10.138154 Set Vref, RX VrefLevel [Byte0]: 78
1115 10:55:10.140629 [Byte1]: 78
1116 10:55:10.145281
1117 10:55:10.145797 Set Vref, RX VrefLevel [Byte0]: 79
1118 10:55:10.148706 [Byte1]: 79
1119 10:55:10.153017
1120 10:55:10.153532 Final RX Vref Byte 0 = 54 to rank0
1121 10:55:10.156481 Final RX Vref Byte 1 = 57 to rank0
1122 10:55:10.159274 Final RX Vref Byte 0 = 54 to rank1
1123 10:55:10.162691 Final RX Vref Byte 1 = 57 to rank1==
1124 10:55:10.165890 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 10:55:10.169624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 10:55:10.172838 ==
1127 10:55:10.173351 DQS Delay:
1128 10:55:10.173686 DQS0 = 0, DQS1 = 0
1129 10:55:10.176015 DQM Delay:
1130 10:55:10.176431 DQM0 = 91, DQM1 = 84
1131 10:55:10.179959 DQ Delay:
1132 10:55:10.183312 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1133 10:55:10.186374 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 10:55:10.186891 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1135 10:55:10.192890 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 10:55:10.193600
1137 10:55:10.193948
1138 10:55:10.199406 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1139 10:55:10.202796 CH0 RK0: MR19=606, MR18=4A41
1140 10:55:10.209660 CH0_RK0: MR19=0x606, MR18=0x4A41, DQSOSC=391, MR23=63, INC=96, DEC=64
1141 10:55:10.210176
1142 10:55:10.213293 ----->DramcWriteLeveling(PI) begin...
1143 10:55:10.213825 ==
1144 10:55:10.216145 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 10:55:10.219938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 10:55:10.220456 ==
1147 10:55:10.222867 Write leveling (Byte 0): 35 => 35
1148 10:55:10.226252 Write leveling (Byte 1): 27 => 27
1149 10:55:10.270251 DramcWriteLeveling(PI) end<-----
1150 10:55:10.270904
1151 10:55:10.271276 ==
1152 10:55:10.271702 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 10:55:10.272050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 10:55:10.272375 ==
1155 10:55:10.272691 [Gating] SW mode calibration
1156 10:55:10.273004 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 10:55:10.273651 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 10:55:10.274000 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 10:55:10.274321 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 10:55:10.274634 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1161 10:55:10.274941 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1162 10:55:10.314416 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:55:10.315130 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:55:10.315570 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:55:10.316091 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:55:10.316841 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:55:10.317211 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:55:10.317546 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:55:10.317870 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:55:10.318189 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:55:10.318505 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:55:10.358819 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:55:10.359472 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:55:10.359850 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:55:10.360196 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1176 10:55:10.360935 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 10:55:10.361393 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:55:10.361755 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:55:10.362092 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:55:10.362416 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 10:55:10.362757 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:55:10.363210 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:55:10.366361 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:55:10.370253 0 9 8 | B1->B0 | 2e2e 2e2e | 1 1 | (1 1) (1 1)
1185 10:55:10.376374 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 10:55:10.380129 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 10:55:10.383192 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 10:55:10.386731 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 10:55:10.393514 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 10:55:10.396582 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 10:55:10.400124 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
1192 10:55:10.404010 0 10 8 | B1->B0 | 2828 2525 | 0 1 | (0 1) (1 0)
1193 10:55:10.411578 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 10:55:10.414994 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 10:55:10.418914 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:55:10.422223 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:55:10.429724 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:55:10.432553 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:55:10.436192 0 11 4 | B1->B0 | 2525 2727 | 0 1 | (0 0) (0 0)
1200 10:55:10.439286 0 11 8 | B1->B0 | 3e3e 3636 | 0 0 | (0 0) (0 0)
1201 10:55:10.445707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:55:10.449331 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 10:55:10.452683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 10:55:10.459515 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 10:55:10.462709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 10:55:10.465691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 10:55:10.473038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 10:55:10.475867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 10:55:10.479542 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1210 10:55:10.485722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:55:10.489078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:55:10.493010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:55:10.499256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:55:10.503130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:55:10.506117 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:55:10.509384 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:55:10.515673 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:55:10.518900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:55:10.522735 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:55:10.529424 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:55:10.532630 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:55:10.536097 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:55:10.542637 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:55:10.545987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 10:55:10.549006 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 10:55:10.552757 Total UI for P1: 0, mck2ui 16
1227 10:55:10.556389 best dqsien dly found for B0: ( 0, 14, 8)
1228 10:55:10.559906 Total UI for P1: 0, mck2ui 16
1229 10:55:10.563002 best dqsien dly found for B1: ( 0, 14, 8)
1230 10:55:10.566656 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 10:55:10.569737 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 10:55:10.570294
1233 10:55:10.572801 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 10:55:10.579403 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 10:55:10.579867 [Gating] SW calibration Done
1236 10:55:10.580318 ==
1237 10:55:10.583121 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 10:55:10.589743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 10:55:10.590170 ==
1240 10:55:10.590503 RX Vref Scan: 0
1241 10:55:10.590836
1242 10:55:10.592613 RX Vref 0 -> 0, step: 1
1243 10:55:10.592974
1244 10:55:10.596409 RX Delay -130 -> 252, step: 16
1245 10:55:10.599565 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1246 10:55:10.602810 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1247 10:55:10.606100 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1248 10:55:10.613014 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1249 10:55:10.616221 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1250 10:55:10.619404 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1251 10:55:10.622657 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1252 10:55:10.626527 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1253 10:55:10.632815 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1254 10:55:10.636594 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1255 10:55:10.639602 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1256 10:55:10.643177 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1257 10:55:10.646399 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1258 10:55:10.653258 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1259 10:55:10.656347 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1260 10:55:10.659217 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1261 10:55:10.659716 ==
1262 10:55:10.663153 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 10:55:10.666367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 10:55:10.666786 ==
1265 10:55:10.669296 DQS Delay:
1266 10:55:10.669726 DQS0 = 0, DQS1 = 0
1267 10:55:10.672804 DQM Delay:
1268 10:55:10.673214 DQM0 = 93, DQM1 = 85
1269 10:55:10.673589 DQ Delay:
1270 10:55:10.676020 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1271 10:55:10.679291 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =93
1272 10:55:10.682610 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1273 10:55:10.686670 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1274 10:55:10.687188
1275 10:55:10.687559
1276 10:55:10.687863 ==
1277 10:55:10.689651 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 10:55:10.696156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 10:55:10.696600 ==
1280 10:55:10.696934
1281 10:55:10.697300
1282 10:55:10.697629 TX Vref Scan disable
1283 10:55:10.700379 == TX Byte 0 ==
1284 10:55:10.703684 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1285 10:55:10.706882 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1286 10:55:10.710081 == TX Byte 1 ==
1287 10:55:10.713134 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1288 10:55:10.717092 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1289 10:55:10.720383 ==
1290 10:55:10.723643 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 10:55:10.726900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 10:55:10.727360 ==
1293 10:55:10.740081 TX Vref=22, minBit 12, minWin=27, winSum=450
1294 10:55:10.743238 TX Vref=24, minBit 1, minWin=28, winSum=451
1295 10:55:10.746763 TX Vref=26, minBit 1, minWin=28, winSum=453
1296 10:55:10.750443 TX Vref=28, minBit 7, minWin=28, winSum=461
1297 10:55:10.753349 TX Vref=30, minBit 1, minWin=28, winSum=457
1298 10:55:10.760214 TX Vref=32, minBit 1, minWin=28, winSum=456
1299 10:55:10.763217 [TxChooseVref] Worse bit 7, Min win 28, Win sum 461, Final Vref 28
1300 10:55:10.763806
1301 10:55:10.767012 Final TX Range 1 Vref 28
1302 10:55:10.767468
1303 10:55:10.767800 ==
1304 10:55:10.770265 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 10:55:10.773298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 10:55:10.773710 ==
1307 10:55:10.776442
1308 10:55:10.776848
1309 10:55:10.777169 TX Vref Scan disable
1310 10:55:10.780173 == TX Byte 0 ==
1311 10:55:10.783490 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1312 10:55:10.787163 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1313 10:55:10.790489 == TX Byte 1 ==
1314 10:55:10.793635 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1315 10:55:10.796737 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1316 10:55:10.800505
1317 10:55:10.800913 [DATLAT]
1318 10:55:10.801236 Freq=800, CH0 RK1
1319 10:55:10.801563
1320 10:55:10.803634 DATLAT Default: 0xa
1321 10:55:10.804042 0, 0xFFFF, sum = 0
1322 10:55:10.807114 1, 0xFFFF, sum = 0
1323 10:55:10.807567 2, 0xFFFF, sum = 0
1324 10:55:10.810422 3, 0xFFFF, sum = 0
1325 10:55:10.810839 4, 0xFFFF, sum = 0
1326 10:55:10.813675 5, 0xFFFF, sum = 0
1327 10:55:10.816926 6, 0xFFFF, sum = 0
1328 10:55:10.817460 7, 0xFFFF, sum = 0
1329 10:55:10.820600 8, 0xFFFF, sum = 0
1330 10:55:10.821018 9, 0x0, sum = 1
1331 10:55:10.821346 10, 0x0, sum = 2
1332 10:55:10.823872 11, 0x0, sum = 3
1333 10:55:10.824292 12, 0x0, sum = 4
1334 10:55:10.827029 best_step = 10
1335 10:55:10.827485
1336 10:55:10.827824 ==
1337 10:55:10.830280 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 10:55:10.833511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 10:55:10.833945 ==
1340 10:55:10.836963 RX Vref Scan: 0
1341 10:55:10.837372
1342 10:55:10.837695 RX Vref 0 -> 0, step: 1
1343 10:55:10.838001
1344 10:55:10.839812 RX Delay -95 -> 252, step: 8
1345 10:55:10.846795 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 10:55:10.852540 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1347 10:55:10.853744 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 10:55:10.856839 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1349 10:55:10.860626 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 10:55:10.867362 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1351 10:55:10.870152 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 10:55:10.873424 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 10:55:10.877059 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 10:55:10.880378 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 10:55:10.887177 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 10:55:10.890134 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 10:55:10.893160 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1358 10:55:10.896906 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1359 10:55:10.900077 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 10:55:10.906531 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1361 10:55:10.906612 ==
1362 10:55:10.910367 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 10:55:10.913804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 10:55:10.913890 ==
1365 10:55:10.913954 DQS Delay:
1366 10:55:10.916704 DQS0 = 0, DQS1 = 0
1367 10:55:10.916789 DQM Delay:
1368 10:55:10.920218 DQM0 = 93, DQM1 = 83
1369 10:55:10.920298 DQ Delay:
1370 10:55:10.923189 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =92
1371 10:55:10.926417 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1372 10:55:10.930278 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1373 10:55:10.933516 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1374 10:55:10.933596
1375 10:55:10.933659
1376 10:55:10.940476 [DQSOSCAuto] RK1, (LSB)MR18= 0x4414, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1377 10:55:10.943668 CH0 RK1: MR19=606, MR18=4414
1378 10:55:10.950503 CH0_RK1: MR19=0x606, MR18=0x4414, DQSOSC=392, MR23=63, INC=96, DEC=64
1379 10:55:10.953597 [RxdqsGatingPostProcess] freq 800
1380 10:55:10.960697 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 10:55:10.960777 Pre-setting of DQS Precalculation
1382 10:55:10.967090 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 10:55:10.967169 ==
1384 10:55:10.970846 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 10:55:10.973740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 10:55:10.973820 ==
1387 10:55:10.980372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 10:55:10.986805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 10:55:10.994939 [CA 0] Center 36 (6~67) winsize 62
1390 10:55:10.998135 [CA 1] Center 36 (6~67) winsize 62
1391 10:55:11.001944 [CA 2] Center 35 (4~66) winsize 63
1392 10:55:11.005161 [CA 3] Center 34 (4~65) winsize 62
1393 10:55:11.008341 [CA 4] Center 34 (4~65) winsize 62
1394 10:55:11.011507 [CA 5] Center 34 (4~65) winsize 62
1395 10:55:11.011587
1396 10:55:11.015287 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 10:55:11.015378
1398 10:55:11.018498 [CATrainingPosCal] consider 1 rank data
1399 10:55:11.021549 u2DelayCellTimex100 = 270/100 ps
1400 10:55:11.025331 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 10:55:11.028245 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 10:55:11.035195 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1403 10:55:11.038422 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 10:55:11.041602 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 10:55:11.044986 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 10:55:11.045066
1407 10:55:11.048936 CA PerBit enable=1, Macro0, CA PI delay=34
1408 10:55:11.049016
1409 10:55:11.051873 [CBTSetCACLKResult] CA Dly = 34
1410 10:55:11.051979 CS Dly: 5 (0~36)
1411 10:55:11.052070 ==
1412 10:55:11.054945 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 10:55:11.061863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 10:55:11.061943 ==
1415 10:55:11.065160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 10:55:11.072097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 10:55:11.081685 [CA 0] Center 36 (6~67) winsize 62
1418 10:55:11.085245 [CA 1] Center 37 (6~68) winsize 63
1419 10:55:11.088920 [CA 2] Center 35 (4~66) winsize 63
1420 10:55:11.092580 [CA 3] Center 34 (4~65) winsize 62
1421 10:55:11.097055 [CA 4] Center 35 (5~66) winsize 62
1422 10:55:11.097135 [CA 5] Center 34 (4~65) winsize 62
1423 10:55:11.097236
1424 10:55:11.100200 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 10:55:11.104003
1426 10:55:11.107150 [CATrainingPosCal] consider 2 rank data
1427 10:55:11.107246 u2DelayCellTimex100 = 270/100 ps
1428 10:55:11.113949 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 10:55:11.117270 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 10:55:11.120464 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1431 10:55:11.123545 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 10:55:11.127261 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 10:55:11.130514 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 10:55:11.130614
1435 10:55:11.133673 CA PerBit enable=1, Macro0, CA PI delay=34
1436 10:55:11.133769
1437 10:55:11.137297 [CBTSetCACLKResult] CA Dly = 34
1438 10:55:11.140391 CS Dly: 6 (0~39)
1439 10:55:11.140469
1440 10:55:11.143551 ----->DramcWriteLeveling(PI) begin...
1441 10:55:11.143628 ==
1442 10:55:11.146858 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 10:55:11.150705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 10:55:11.150802 ==
1445 10:55:11.153819 Write leveling (Byte 0): 27 => 27
1446 10:55:11.156962 Write leveling (Byte 1): 28 => 28
1447 10:55:11.160711 DramcWriteLeveling(PI) end<-----
1448 10:55:11.160816
1449 10:55:11.160911 ==
1450 10:55:11.163811 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 10:55:11.167009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 10:55:11.167105 ==
1453 10:55:11.170235 [Gating] SW mode calibration
1454 10:55:11.177200 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 10:55:11.183667 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 10:55:11.186843 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 10:55:11.190600 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:55:11.197083 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:55:11.200164 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:55:11.203938 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:55:11.210713 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:55:11.213833 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:55:11.217349 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:55:11.220570 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:55:11.227077 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:55:11.230734 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:55:11.234086 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:55:11.240285 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:55:11.243921 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:55:11.246946 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:55:11.253528 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:55:11.257347 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:55:11.260262 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1474 10:55:11.267074 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:55:11.270329 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:55:11.273683 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:55:11.280810 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:55:11.283902 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:55:11.287061 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:55:11.293786 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:55:11.297269 0 9 4 | B1->B0 | 2323 2626 | 1 0 | (1 1) (0 0)
1482 10:55:11.300462 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1483 10:55:11.307026 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 10:55:11.310690 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 10:55:11.313696 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 10:55:11.317284 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 10:55:11.324150 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 10:55:11.327278 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1489 10:55:11.330449 0 10 4 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 1)
1490 10:55:11.337043 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1491 10:55:11.340865 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:55:11.344026 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 10:55:11.350876 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:55:11.353882 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:55:11.357111 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:55:11.364203 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1497 10:55:11.367292 0 11 4 | B1->B0 | 2727 3434 | 0 0 | (0 0) (1 1)
1498 10:55:11.370557 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (1 1) (0 0)
1499 10:55:11.377766 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 10:55:11.381127 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 10:55:11.384173 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 10:55:11.387580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 10:55:11.393863 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 10:55:11.397479 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 10:55:11.400566 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 10:55:11.407710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:55:11.410942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:55:11.413952 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:55:11.421155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:55:11.424093 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:55:11.427726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:55:11.434522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:55:11.437584 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:55:11.440754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:55:11.447859 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:55:11.450988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:55:11.454703 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:55:11.457812 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:55:11.464787 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:55:11.467977 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:55:11.471048 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1522 10:55:11.478048 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1523 10:55:11.481285 Total UI for P1: 0, mck2ui 16
1524 10:55:11.484617 best dqsien dly found for B1: ( 0, 14, 4)
1525 10:55:11.487780 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 10:55:11.491062 Total UI for P1: 0, mck2ui 16
1527 10:55:11.494873 best dqsien dly found for B0: ( 0, 14, 6)
1528 10:55:11.498106 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1529 10:55:11.501330 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1530 10:55:11.501403
1531 10:55:11.504572 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1532 10:55:11.508284 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1533 10:55:11.511298 [Gating] SW calibration Done
1534 10:55:11.511417 ==
1535 10:55:11.514811 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 10:55:11.517582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1537 10:55:11.517653 ==
1538 10:55:11.520905 RX Vref Scan: 0
1539 10:55:11.520978
1540 10:55:11.524729 RX Vref 0 -> 0, step: 1
1541 10:55:11.524809
1542 10:55:11.524873 RX Delay -130 -> 252, step: 16
1543 10:55:11.531461 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1544 10:55:11.534468 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1545 10:55:11.538171 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1546 10:55:11.541235 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1547 10:55:11.544781 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1548 10:55:11.551224 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1549 10:55:11.554495 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1550 10:55:11.558254 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1551 10:55:11.561497 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1552 10:55:11.564593 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1553 10:55:11.571570 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1554 10:55:11.574554 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1555 10:55:11.577693 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1556 10:55:11.581495 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1557 10:55:11.584765 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1558 10:55:11.591225 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1559 10:55:11.591334 ==
1560 10:55:11.594586 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 10:55:11.598342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 10:55:11.598416 ==
1563 10:55:11.598486 DQS Delay:
1564 10:55:11.601569 DQS0 = 0, DQS1 = 0
1565 10:55:11.601640 DQM Delay:
1566 10:55:11.604788 DQM0 = 93, DQM1 = 88
1567 10:55:11.604854 DQ Delay:
1568 10:55:11.607850 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1569 10:55:11.611547 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1570 10:55:11.614666 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1571 10:55:11.618258 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1572 10:55:11.618353
1573 10:55:11.618441
1574 10:55:11.618533 ==
1575 10:55:11.621416 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 10:55:11.625130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 10:55:11.628260 ==
1578 10:55:11.628331
1579 10:55:11.628391
1580 10:55:11.628448 TX Vref Scan disable
1581 10:55:11.631472 == TX Byte 0 ==
1582 10:55:11.634583 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1583 10:55:11.638156 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1584 10:55:11.641262 == TX Byte 1 ==
1585 10:55:11.645072 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1586 10:55:11.648797 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1587 10:55:11.648868 ==
1588 10:55:11.652262 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 10:55:11.655524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 10:55:11.658578 ==
1591 10:55:11.670225 TX Vref=22, minBit 0, minWin=26, winSum=436
1592 10:55:11.673400 TX Vref=24, minBit 1, minWin=27, winSum=443
1593 10:55:11.676476 TX Vref=26, minBit 1, minWin=27, winSum=444
1594 10:55:11.680157 TX Vref=28, minBit 1, minWin=27, winSum=446
1595 10:55:11.683274 TX Vref=30, minBit 0, minWin=27, winSum=449
1596 10:55:11.686504 TX Vref=32, minBit 2, minWin=26, winSum=445
1597 10:55:11.693669 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1598 10:55:11.693751
1599 10:55:11.696786 Final TX Range 1 Vref 30
1600 10:55:11.696868
1601 10:55:11.696931 ==
1602 10:55:11.699929 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 10:55:11.703685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 10:55:11.703771 ==
1605 10:55:11.703836
1606 10:55:11.703895
1607 10:55:11.706930 TX Vref Scan disable
1608 10:55:11.710240 == TX Byte 0 ==
1609 10:55:11.713297 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 10:55:11.716649 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 10:55:11.720308 == TX Byte 1 ==
1612 10:55:11.723225 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1613 10:55:11.726970 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1614 10:55:11.727086
1615 10:55:11.730251 [DATLAT]
1616 10:55:11.730332 Freq=800, CH1 RK0
1617 10:55:11.730397
1618 10:55:11.733894 DATLAT Default: 0xa
1619 10:55:11.733975 0, 0xFFFF, sum = 0
1620 10:55:11.736912 1, 0xFFFF, sum = 0
1621 10:55:11.736995 2, 0xFFFF, sum = 0
1622 10:55:11.740657 3, 0xFFFF, sum = 0
1623 10:55:11.740740 4, 0xFFFF, sum = 0
1624 10:55:11.743693 5, 0xFFFF, sum = 0
1625 10:55:11.743776 6, 0xFFFF, sum = 0
1626 10:55:11.746819 7, 0xFFFF, sum = 0
1627 10:55:11.746901 8, 0xFFFF, sum = 0
1628 10:55:11.750602 9, 0x0, sum = 1
1629 10:55:11.750685 10, 0x0, sum = 2
1630 10:55:11.753742 11, 0x0, sum = 3
1631 10:55:11.753825 12, 0x0, sum = 4
1632 10:55:11.756869 best_step = 10
1633 10:55:11.756950
1634 10:55:11.757013 ==
1635 10:55:11.760612 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 10:55:11.763628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 10:55:11.763710 ==
1638 10:55:11.767252 RX Vref Scan: 1
1639 10:55:11.767356
1640 10:55:11.767435 Set Vref Range= 32 -> 127
1641 10:55:11.767495
1642 10:55:11.770443 RX Vref 32 -> 127, step: 1
1643 10:55:11.770525
1644 10:55:11.773735 RX Delay -79 -> 252, step: 8
1645 10:55:11.773816
1646 10:55:11.776928 Set Vref, RX VrefLevel [Byte0]: 32
1647 10:55:11.780531 [Byte1]: 32
1648 10:55:11.780612
1649 10:55:11.784179 Set Vref, RX VrefLevel [Byte0]: 33
1650 10:55:11.787352 [Byte1]: 33
1651 10:55:11.787447
1652 10:55:11.790719 Set Vref, RX VrefLevel [Byte0]: 34
1653 10:55:11.793775 [Byte1]: 34
1654 10:55:11.797730
1655 10:55:11.797811 Set Vref, RX VrefLevel [Byte0]: 35
1656 10:55:11.800832 [Byte1]: 35
1657 10:55:11.805466
1658 10:55:11.805546 Set Vref, RX VrefLevel [Byte0]: 36
1659 10:55:11.808701 [Byte1]: 36
1660 10:55:11.812580
1661 10:55:11.812661 Set Vref, RX VrefLevel [Byte0]: 37
1662 10:55:11.815859 [Byte1]: 37
1663 10:55:11.820283
1664 10:55:11.820363 Set Vref, RX VrefLevel [Byte0]: 38
1665 10:55:11.824053 [Byte1]: 38
1666 10:55:11.827782
1667 10:55:11.827862 Set Vref, RX VrefLevel [Byte0]: 39
1668 10:55:11.831569 [Byte1]: 39
1669 10:55:11.835195
1670 10:55:11.835276 Set Vref, RX VrefLevel [Byte0]: 40
1671 10:55:11.838949 [Byte1]: 40
1672 10:55:11.843212
1673 10:55:11.843331 Set Vref, RX VrefLevel [Byte0]: 41
1674 10:55:11.846425 [Byte1]: 41
1675 10:55:11.850524
1676 10:55:11.850606 Set Vref, RX VrefLevel [Byte0]: 42
1677 10:55:11.853627 [Byte1]: 42
1678 10:55:11.858013
1679 10:55:11.858095 Set Vref, RX VrefLevel [Byte0]: 43
1680 10:55:11.861160 [Byte1]: 43
1681 10:55:11.865562
1682 10:55:11.865652 Set Vref, RX VrefLevel [Byte0]: 44
1683 10:55:11.868675 [Byte1]: 44
1684 10:55:11.873506
1685 10:55:11.873589 Set Vref, RX VrefLevel [Byte0]: 45
1686 10:55:11.876568 [Byte1]: 45
1687 10:55:11.880581
1688 10:55:11.880664 Set Vref, RX VrefLevel [Byte0]: 46
1689 10:55:11.884331 [Byte1]: 46
1690 10:55:11.887997
1691 10:55:11.888080 Set Vref, RX VrefLevel [Byte0]: 47
1692 10:55:11.891529 [Byte1]: 47
1693 10:55:11.895960
1694 10:55:11.896042 Set Vref, RX VrefLevel [Byte0]: 48
1695 10:55:11.899213 [Byte1]: 48
1696 10:55:11.903156
1697 10:55:11.903268 Set Vref, RX VrefLevel [Byte0]: 49
1698 10:55:11.906949 [Byte1]: 49
1699 10:55:11.910775
1700 10:55:11.910877 Set Vref, RX VrefLevel [Byte0]: 50
1701 10:55:11.914052 [Byte1]: 50
1702 10:55:11.918500
1703 10:55:11.918583 Set Vref, RX VrefLevel [Byte0]: 51
1704 10:55:11.921745 [Byte1]: 51
1705 10:55:11.926245
1706 10:55:11.926327 Set Vref, RX VrefLevel [Byte0]: 52
1707 10:55:11.929497 [Byte1]: 52
1708 10:55:11.933277
1709 10:55:11.933360 Set Vref, RX VrefLevel [Byte0]: 53
1710 10:55:11.936484 [Byte1]: 53
1711 10:55:11.940823
1712 10:55:11.940906 Set Vref, RX VrefLevel [Byte0]: 54
1713 10:55:11.944477 [Byte1]: 54
1714 10:55:11.948844
1715 10:55:11.948927 Set Vref, RX VrefLevel [Byte0]: 55
1716 10:55:11.951900 [Byte1]: 55
1717 10:55:11.956175
1718 10:55:11.956259 Set Vref, RX VrefLevel [Byte0]: 56
1719 10:55:11.959583 [Byte1]: 56
1720 10:55:11.963956
1721 10:55:11.964038 Set Vref, RX VrefLevel [Byte0]: 57
1722 10:55:11.966973 [Byte1]: 57
1723 10:55:11.970974
1724 10:55:11.971055 Set Vref, RX VrefLevel [Byte0]: 58
1725 10:55:11.974700 [Byte1]: 58
1726 10:55:11.978725
1727 10:55:11.978806 Set Vref, RX VrefLevel [Byte0]: 59
1728 10:55:11.982266 [Byte1]: 59
1729 10:55:11.986709
1730 10:55:11.986790 Set Vref, RX VrefLevel [Byte0]: 60
1731 10:55:11.989781 [Byte1]: 60
1732 10:55:11.994038
1733 10:55:11.994119 Set Vref, RX VrefLevel [Byte0]: 61
1734 10:55:11.997028 [Byte1]: 61
1735 10:55:12.001410
1736 10:55:12.001493 Set Vref, RX VrefLevel [Byte0]: 62
1737 10:55:12.004586 [Byte1]: 62
1738 10:55:12.009050
1739 10:55:12.009132 Set Vref, RX VrefLevel [Byte0]: 63
1740 10:55:12.012195 [Byte1]: 63
1741 10:55:12.016765
1742 10:55:12.016846 Set Vref, RX VrefLevel [Byte0]: 64
1743 10:55:12.019977 [Byte1]: 64
1744 10:55:12.023877
1745 10:55:12.023958 Set Vref, RX VrefLevel [Byte0]: 65
1746 10:55:12.027697 [Byte1]: 65
1747 10:55:12.031469
1748 10:55:12.031550 Set Vref, RX VrefLevel [Byte0]: 66
1749 10:55:12.034710 [Byte1]: 66
1750 10:55:12.039152
1751 10:55:12.039227 Set Vref, RX VrefLevel [Byte0]: 67
1752 10:55:12.042439 [Byte1]: 67
1753 10:55:12.046761
1754 10:55:12.046829 Set Vref, RX VrefLevel [Byte0]: 68
1755 10:55:12.049827 [Byte1]: 68
1756 10:55:12.054010
1757 10:55:12.054079 Set Vref, RX VrefLevel [Byte0]: 69
1758 10:55:12.057687 [Byte1]: 69
1759 10:55:12.061561
1760 10:55:12.061630 Set Vref, RX VrefLevel [Byte0]: 70
1761 10:55:12.065022 [Byte1]: 70
1762 10:55:12.069238
1763 10:55:12.069311 Set Vref, RX VrefLevel [Byte0]: 71
1764 10:55:12.072780 [Byte1]: 71
1765 10:55:12.077299
1766 10:55:12.077364 Set Vref, RX VrefLevel [Byte0]: 72
1767 10:55:12.080448 [Byte1]: 72
1768 10:55:12.084173
1769 10:55:12.084250 Final RX Vref Byte 0 = 60 to rank0
1770 10:55:12.087827 Final RX Vref Byte 1 = 55 to rank0
1771 10:55:12.090803 Final RX Vref Byte 0 = 60 to rank1
1772 10:55:12.094706 Final RX Vref Byte 1 = 55 to rank1==
1773 10:55:12.097809 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 10:55:12.101318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 10:55:12.104895 ==
1776 10:55:12.104968 DQS Delay:
1777 10:55:12.105030 DQS0 = 0, DQS1 = 0
1778 10:55:12.108073 DQM Delay:
1779 10:55:12.108147 DQM0 = 95, DQM1 = 89
1780 10:55:12.111194 DQ Delay:
1781 10:55:12.114329 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1782 10:55:12.117626 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1783 10:55:12.117693 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1784 10:55:12.124751 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1785 10:55:12.124818
1786 10:55:12.124877
1787 10:55:12.131271 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1788 10:55:12.134484 CH1 RK0: MR19=606, MR18=2945
1789 10:55:12.140956 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1790 10:55:12.141036
1791 10:55:12.144743 ----->DramcWriteLeveling(PI) begin...
1792 10:55:12.144815 ==
1793 10:55:12.147962 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 10:55:12.151355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 10:55:12.151450 ==
1796 10:55:12.154467 Write leveling (Byte 0): 29 => 29
1797 10:55:12.157699 Write leveling (Byte 1): 31 => 31
1798 10:55:12.161565 DramcWriteLeveling(PI) end<-----
1799 10:55:12.161646
1800 10:55:12.161709 ==
1801 10:55:12.164673 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 10:55:12.167657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 10:55:12.167731 ==
1804 10:55:12.171103 [Gating] SW mode calibration
1805 10:55:12.177708 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 10:55:12.184445 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 10:55:12.188299 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 10:55:12.191250 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1809 10:55:12.197955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 10:55:12.201134 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 10:55:12.204938 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:55:12.211496 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:55:12.214984 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:55:12.218140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:55:12.224595 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:55:12.227883 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:55:12.231213 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:55:12.235068 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:55:12.242000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:55:12.245184 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:55:12.248359 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:55:12.254834 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:55:12.258708 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1824 10:55:12.261943 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1825 10:55:12.268262 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:55:12.272040 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:55:12.275059 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:55:12.281827 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:55:12.285445 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:55:12.289020 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:55:12.291961 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:55:12.298923 0 9 4 | B1->B0 | 2828 2323 | 1 1 | (1 1) (1 1)
1833 10:55:12.301985 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1834 10:55:12.305013 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 10:55:12.311734 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 10:55:12.315496 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 10:55:12.318531 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 10:55:12.325062 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 10:55:12.328750 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1840 10:55:12.331910 0 10 4 | B1->B0 | 2929 2f2f | 0 0 | (1 0) (1 1)
1841 10:55:12.338963 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1842 10:55:12.342195 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:55:12.345466 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:55:12.351856 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:55:12.355612 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:55:12.358945 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:55:12.362138 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1848 10:55:12.368987 0 11 4 | B1->B0 | 3535 2929 | 0 1 | (0 0) (0 0)
1849 10:55:12.372150 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1850 10:55:12.375209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 10:55:12.382228 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 10:55:12.385334 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 10:55:12.388979 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 10:55:12.395617 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 10:55:12.399171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 10:55:12.402146 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 10:55:12.408918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 10:55:12.412588 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:55:12.415916 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:55:12.422098 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:55:12.425825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:55:12.429096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:55:12.432137 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:55:12.439105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:55:12.442862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:55:12.446173 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:55:12.452595 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:55:12.455902 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:55:12.459179 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:55:12.466200 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:55:12.469234 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:55:12.472533 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1873 10:55:12.478967 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 10:55:12.479049 Total UI for P1: 0, mck2ui 16
1875 10:55:12.486018 best dqsien dly found for B0: ( 0, 14, 4)
1876 10:55:12.486100 Total UI for P1: 0, mck2ui 16
1877 10:55:12.489256 best dqsien dly found for B1: ( 0, 14, 4)
1878 10:55:12.495986 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1879 10:55:12.499155 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1880 10:55:12.499252
1881 10:55:12.502643 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 10:55:12.505631 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1883 10:55:12.509093 [Gating] SW calibration Done
1884 10:55:12.509177 ==
1885 10:55:12.512652 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 10:55:12.516247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 10:55:12.516320 ==
1888 10:55:12.516384 RX Vref Scan: 0
1889 10:55:12.519223
1890 10:55:12.519317 RX Vref 0 -> 0, step: 1
1891 10:55:12.519422
1892 10:55:12.522434 RX Delay -130 -> 252, step: 16
1893 10:55:12.526187 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1894 10:55:12.529139 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1895 10:55:12.536058 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1896 10:55:12.539024 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1897 10:55:12.542240 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1898 10:55:12.546098 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1899 10:55:12.549400 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1900 10:55:12.555832 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1901 10:55:12.559115 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1902 10:55:12.562391 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1903 10:55:12.565667 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1904 10:55:12.568877 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1905 10:55:12.575642 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1906 10:55:12.578879 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1907 10:55:12.582673 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1908 10:55:12.585754 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1909 10:55:12.585851 ==
1910 10:55:12.589067 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 10:55:12.595998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 10:55:12.596072 ==
1913 10:55:12.596133 DQS Delay:
1914 10:55:12.599192 DQS0 = 0, DQS1 = 0
1915 10:55:12.599299 DQM Delay:
1916 10:55:12.599444 DQM0 = 93, DQM1 = 90
1917 10:55:12.602417 DQ Delay:
1918 10:55:12.606286 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1919 10:55:12.609456 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1920 10:55:12.612522 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1921 10:55:12.616137 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1922 10:55:12.616217
1923 10:55:12.616281
1924 10:55:12.616341 ==
1925 10:55:12.619153 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 10:55:12.622832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 10:55:12.622914 ==
1928 10:55:12.622978
1929 10:55:12.623038
1930 10:55:12.626031 TX Vref Scan disable
1931 10:55:12.626159 == TX Byte 0 ==
1932 10:55:12.632824 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1933 10:55:12.635884 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1934 10:55:12.635966 == TX Byte 1 ==
1935 10:55:12.642942 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1936 10:55:12.645979 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1937 10:55:12.646060 ==
1938 10:55:12.649059 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 10:55:12.652839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 10:55:12.652921 ==
1941 10:55:12.666467 TX Vref=22, minBit 1, minWin=27, winSum=443
1942 10:55:12.670316 TX Vref=24, minBit 1, minWin=27, winSum=446
1943 10:55:12.673708 TX Vref=26, minBit 2, minWin=27, winSum=449
1944 10:55:12.676686 TX Vref=28, minBit 2, minWin=27, winSum=449
1945 10:55:12.680453 TX Vref=30, minBit 1, minWin=27, winSum=448
1946 10:55:12.683687 TX Vref=32, minBit 0, minWin=27, winSum=448
1947 10:55:12.690058 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 26
1948 10:55:12.690140
1949 10:55:12.693270 Final TX Range 1 Vref 26
1950 10:55:12.693367
1951 10:55:12.693460 ==
1952 10:55:12.697085 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 10:55:12.700297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 10:55:12.700380 ==
1955 10:55:12.700446
1956 10:55:12.700505
1957 10:55:12.703287 TX Vref Scan disable
1958 10:55:12.707209 == TX Byte 0 ==
1959 10:55:12.710490 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1960 10:55:12.713532 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1961 10:55:12.717209 == TX Byte 1 ==
1962 10:55:12.720209 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1963 10:55:12.723729 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1964 10:55:12.723811
1965 10:55:12.727224 [DATLAT]
1966 10:55:12.727311 Freq=800, CH1 RK1
1967 10:55:12.727432
1968 10:55:12.730479 DATLAT Default: 0xa
1969 10:55:12.730588 0, 0xFFFF, sum = 0
1970 10:55:12.733585 1, 0xFFFF, sum = 0
1971 10:55:12.733684 2, 0xFFFF, sum = 0
1972 10:55:12.737120 3, 0xFFFF, sum = 0
1973 10:55:12.737215 4, 0xFFFF, sum = 0
1974 10:55:12.740184 5, 0xFFFF, sum = 0
1975 10:55:12.740257 6, 0xFFFF, sum = 0
1976 10:55:12.743892 7, 0xFFFF, sum = 0
1977 10:55:12.743988 8, 0xFFFF, sum = 0
1978 10:55:12.747118 9, 0x0, sum = 1
1979 10:55:12.747215 10, 0x0, sum = 2
1980 10:55:12.750291 11, 0x0, sum = 3
1981 10:55:12.750362 12, 0x0, sum = 4
1982 10:55:12.754003 best_step = 10
1983 10:55:12.754100
1984 10:55:12.754186 ==
1985 10:55:12.756656 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 10:55:12.760513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 10:55:12.760584 ==
1988 10:55:12.763875 RX Vref Scan: 0
1989 10:55:12.763945
1990 10:55:12.764008 RX Vref 0 -> 0, step: 1
1991 10:55:12.764094
1992 10:55:12.767084 RX Delay -63 -> 252, step: 8
1993 10:55:12.773562 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1994 10:55:12.776761 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1995 10:55:12.779893 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1996 10:55:12.783567 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1997 10:55:12.786805 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1998 10:55:12.790091 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1999 10:55:12.796551 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2000 10:55:12.799856 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2001 10:55:12.803834 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2002 10:55:12.806832 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2003 10:55:12.810072 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2004 10:55:12.813916 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2005 10:55:12.820171 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2006 10:55:12.823716 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2007 10:55:12.826666 iDelay=209, Bit 14, Center 100 (1 ~ 200) 200
2008 10:55:12.830254 iDelay=209, Bit 15, Center 100 (1 ~ 200) 200
2009 10:55:12.830329 ==
2010 10:55:12.833986 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 10:55:12.840405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 10:55:12.840474 ==
2013 10:55:12.840535 DQS Delay:
2014 10:55:12.840594 DQS0 = 0, DQS1 = 0
2015 10:55:12.843617 DQM Delay:
2016 10:55:12.843681 DQM0 = 97, DQM1 = 92
2017 10:55:12.847091 DQ Delay:
2018 10:55:12.850487 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2019 10:55:12.853688 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2020 10:55:12.857287 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2021 10:55:12.860493 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =100
2022 10:55:12.860562
2023 10:55:12.860623
2024 10:55:12.867481 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2025 10:55:12.870700 CH1 RK1: MR19=606, MR18=4711
2026 10:55:12.877152 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2027 10:55:12.880418 [RxdqsGatingPostProcess] freq 800
2028 10:55:12.884194 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 10:55:12.887297 Pre-setting of DQS Precalculation
2030 10:55:12.893700 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 10:55:12.900724 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 10:55:12.907261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 10:55:12.907392
2034 10:55:12.907458
2035 10:55:12.910378 [Calibration Summary] 1600 Mbps
2036 10:55:12.910474 CH 0, Rank 0
2037 10:55:12.914059 SW Impedance : PASS
2038 10:55:12.917226 DUTY Scan : NO K
2039 10:55:12.917299 ZQ Calibration : PASS
2040 10:55:12.920397 Jitter Meter : NO K
2041 10:55:12.924284 CBT Training : PASS
2042 10:55:12.924380 Write leveling : PASS
2043 10:55:12.927270 RX DQS gating : PASS
2044 10:55:12.927364 RX DQ/DQS(RDDQC) : PASS
2045 10:55:12.930909 TX DQ/DQS : PASS
2046 10:55:12.934012 RX DATLAT : PASS
2047 10:55:12.934081 RX DQ/DQS(Engine): PASS
2048 10:55:12.937670 TX OE : NO K
2049 10:55:12.937739 All Pass.
2050 10:55:12.937799
2051 10:55:12.940714 CH 0, Rank 1
2052 10:55:12.940779 SW Impedance : PASS
2053 10:55:12.944272 DUTY Scan : NO K
2054 10:55:12.947466 ZQ Calibration : PASS
2055 10:55:12.947535 Jitter Meter : NO K
2056 10:55:12.950999 CBT Training : PASS
2057 10:55:12.954029 Write leveling : PASS
2058 10:55:12.954124 RX DQS gating : PASS
2059 10:55:12.957938 RX DQ/DQS(RDDQC) : PASS
2060 10:55:12.958032 TX DQ/DQS : PASS
2061 10:55:12.960960 RX DATLAT : PASS
2062 10:55:12.963924 RX DQ/DQS(Engine): PASS
2063 10:55:12.964022 TX OE : NO K
2064 10:55:12.967731 All Pass.
2065 10:55:12.967803
2066 10:55:12.967866 CH 1, Rank 0
2067 10:55:12.970737 SW Impedance : PASS
2068 10:55:12.970802 DUTY Scan : NO K
2069 10:55:12.974009 ZQ Calibration : PASS
2070 10:55:12.977334 Jitter Meter : NO K
2071 10:55:12.977417 CBT Training : PASS
2072 10:55:12.981190 Write leveling : PASS
2073 10:55:12.984463 RX DQS gating : PASS
2074 10:55:12.984533 RX DQ/DQS(RDDQC) : PASS
2075 10:55:12.987484 TX DQ/DQS : PASS
2076 10:55:12.990717 RX DATLAT : PASS
2077 10:55:12.990812 RX DQ/DQS(Engine): PASS
2078 10:55:12.994007 TX OE : NO K
2079 10:55:12.994123 All Pass.
2080 10:55:12.994216
2081 10:55:12.997763 CH 1, Rank 1
2082 10:55:12.997869 SW Impedance : PASS
2083 10:55:13.000942 DUTY Scan : NO K
2084 10:55:13.004168 ZQ Calibration : PASS
2085 10:55:13.004244 Jitter Meter : NO K
2086 10:55:13.007437 CBT Training : PASS
2087 10:55:13.007511 Write leveling : PASS
2088 10:55:13.010706 RX DQS gating : PASS
2089 10:55:13.014435 RX DQ/DQS(RDDQC) : PASS
2090 10:55:13.014510 TX DQ/DQS : PASS
2091 10:55:13.017634 RX DATLAT : PASS
2092 10:55:13.020859 RX DQ/DQS(Engine): PASS
2093 10:55:13.020961 TX OE : NO K
2094 10:55:13.024027 All Pass.
2095 10:55:13.024130
2096 10:55:13.024219 DramC Write-DBI off
2097 10:55:13.027825 PER_BANK_REFRESH: Hybrid Mode
2098 10:55:13.027899 TX_TRACKING: ON
2099 10:55:13.031053 [GetDramInforAfterCalByMRR] Vendor 6.
2100 10:55:13.037924 [GetDramInforAfterCalByMRR] Revision 606.
2101 10:55:13.041172 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 10:55:13.041254 MR0 0x3b3b
2103 10:55:13.041318 MR8 0x5151
2104 10:55:13.044171 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 10:55:13.044252
2106 10:55:13.047926 MR0 0x3b3b
2107 10:55:13.048009 MR8 0x5151
2108 10:55:13.051012 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 10:55:13.051095
2110 10:55:13.060981 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 10:55:13.064227 [FAST_K] Save calibration result to emmc
2112 10:55:13.067986 [FAST_K] Save calibration result to emmc
2113 10:55:13.071117 dram_init: config_dvfs: 1
2114 10:55:13.074812 dramc_set_vcore_voltage set vcore to 662500
2115 10:55:13.078107 Read voltage for 1200, 2
2116 10:55:13.078189 Vio18 = 0
2117 10:55:13.078255 Vcore = 662500
2118 10:55:13.081283 Vdram = 0
2119 10:55:13.081365 Vddq = 0
2120 10:55:13.081429 Vmddr = 0
2121 10:55:13.087679 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 10:55:13.090952 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 10:55:13.094787 MEM_TYPE=3, freq_sel=15
2124 10:55:13.097977 sv_algorithm_assistance_LP4_1600
2125 10:55:13.101161 ============ PULL DRAM RESETB DOWN ============
2126 10:55:13.104908 ========== PULL DRAM RESETB DOWN end =========
2127 10:55:13.111299 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 10:55:13.114593 ===================================
2129 10:55:13.114675 LPDDR4 DRAM CONFIGURATION
2130 10:55:13.117799 ===================================
2131 10:55:13.121467 EX_ROW_EN[0] = 0x0
2132 10:55:13.121548 EX_ROW_EN[1] = 0x0
2133 10:55:13.124625 LP4Y_EN = 0x0
2134 10:55:13.127966 WORK_FSP = 0x0
2135 10:55:13.128049 WL = 0x4
2136 10:55:13.131181 RL = 0x4
2137 10:55:13.131287 BL = 0x2
2138 10:55:13.134422 RPST = 0x0
2139 10:55:13.134504 RD_PRE = 0x0
2140 10:55:13.137693 WR_PRE = 0x1
2141 10:55:13.137775 WR_PST = 0x0
2142 10:55:13.141434 DBI_WR = 0x0
2143 10:55:13.141516 DBI_RD = 0x0
2144 10:55:13.144397 OTF = 0x1
2145 10:55:13.148014 ===================================
2146 10:55:13.151021 ===================================
2147 10:55:13.151103 ANA top config
2148 10:55:13.154656 ===================================
2149 10:55:13.157761 DLL_ASYNC_EN = 0
2150 10:55:13.161342 ALL_SLAVE_EN = 0
2151 10:55:13.161424 NEW_RANK_MODE = 1
2152 10:55:13.164932 DLL_IDLE_MODE = 1
2153 10:55:13.167984 LP45_APHY_COMB_EN = 1
2154 10:55:13.171094 TX_ODT_DIS = 1
2155 10:55:13.171178 NEW_8X_MODE = 1
2156 10:55:13.174769 ===================================
2157 10:55:13.177865 ===================================
2158 10:55:13.181597 data_rate = 2400
2159 10:55:13.184687 CKR = 1
2160 10:55:13.187875 DQ_P2S_RATIO = 8
2161 10:55:13.191071 ===================================
2162 10:55:13.194368 CA_P2S_RATIO = 8
2163 10:55:13.197632 DQ_CA_OPEN = 0
2164 10:55:13.197714 DQ_SEMI_OPEN = 0
2165 10:55:13.201433 CA_SEMI_OPEN = 0
2166 10:55:13.204683 CA_FULL_RATE = 0
2167 10:55:13.207861 DQ_CKDIV4_EN = 0
2168 10:55:13.211105 CA_CKDIV4_EN = 0
2169 10:55:13.214989 CA_PREDIV_EN = 0
2170 10:55:13.215071 PH8_DLY = 17
2171 10:55:13.218204 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 10:55:13.221459 DQ_AAMCK_DIV = 4
2173 10:55:13.224580 CA_AAMCK_DIV = 4
2174 10:55:13.228464 CA_ADMCK_DIV = 4
2175 10:55:13.231739 DQ_TRACK_CA_EN = 0
2176 10:55:13.231821 CA_PICK = 1200
2177 10:55:13.234952 CA_MCKIO = 1200
2178 10:55:13.238346 MCKIO_SEMI = 0
2179 10:55:13.241329 PLL_FREQ = 2366
2180 10:55:13.244671 DQ_UI_PI_RATIO = 32
2181 10:55:13.248436 CA_UI_PI_RATIO = 0
2182 10:55:13.251432 ===================================
2183 10:55:13.255093 ===================================
2184 10:55:13.255175 memory_type:LPDDR4
2185 10:55:13.258100 GP_NUM : 10
2186 10:55:13.261774 SRAM_EN : 1
2187 10:55:13.261858 MD32_EN : 0
2188 10:55:13.264819 ===================================
2189 10:55:13.268591 [ANA_INIT] >>>>>>>>>>>>>>
2190 10:55:13.271653 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 10:55:13.274719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 10:55:13.278691 ===================================
2193 10:55:13.281679 data_rate = 2400,PCW = 0X5b00
2194 10:55:13.285350 ===================================
2195 10:55:13.288414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 10:55:13.291843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 10:55:13.298417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 10:55:13.301563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 10:55:13.305312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 10:55:13.308538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 10:55:13.311722 [ANA_INIT] flow start
2202 10:55:13.314988 [ANA_INIT] PLL >>>>>>>>
2203 10:55:13.315069 [ANA_INIT] PLL <<<<<<<<
2204 10:55:13.318279 [ANA_INIT] MIDPI >>>>>>>>
2205 10:55:13.322212 [ANA_INIT] MIDPI <<<<<<<<
2206 10:55:13.322292 [ANA_INIT] DLL >>>>>>>>
2207 10:55:13.325498 [ANA_INIT] DLL <<<<<<<<
2208 10:55:13.328738 [ANA_INIT] flow end
2209 10:55:13.331941 ============ LP4 DIFF to SE enter ============
2210 10:55:13.335154 ============ LP4 DIFF to SE exit ============
2211 10:55:13.338484 [ANA_INIT] <<<<<<<<<<<<<
2212 10:55:13.341707 [Flow] Enable top DCM control >>>>>
2213 10:55:13.345533 [Flow] Enable top DCM control <<<<<
2214 10:55:13.348824 Enable DLL master slave shuffle
2215 10:55:13.351913 ==============================================================
2216 10:55:13.355595 Gating Mode config
2217 10:55:13.358691 ==============================================================
2218 10:55:13.361731 Config description:
2219 10:55:13.372035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 10:55:13.378774 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 10:55:13.381892 SELPH_MODE 0: By rank 1: By Phase
2222 10:55:13.388808 ==============================================================
2223 10:55:13.391893 GAT_TRACK_EN = 1
2224 10:55:13.395633 RX_GATING_MODE = 2
2225 10:55:13.398649 RX_GATING_TRACK_MODE = 2
2226 10:55:13.401951 SELPH_MODE = 1
2227 10:55:13.405799 PICG_EARLY_EN = 1
2228 10:55:13.405882 VALID_LAT_VALUE = 1
2229 10:55:13.412129 ==============================================================
2230 10:55:13.415292 Enter into Gating configuration >>>>
2231 10:55:13.418505 Exit from Gating configuration <<<<
2232 10:55:13.422381 Enter into DVFS_PRE_config >>>>>
2233 10:55:13.432009 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 10:55:13.435723 Exit from DVFS_PRE_config <<<<<
2235 10:55:13.438941 Enter into PICG configuration >>>>
2236 10:55:13.442126 Exit from PICG configuration <<<<
2237 10:55:13.445475 [RX_INPUT] configuration >>>>>
2238 10:55:13.448696 [RX_INPUT] configuration <<<<<
2239 10:55:13.451842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 10:55:13.458998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 10:55:13.465627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 10:55:13.472474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 10:55:13.478552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 10:55:13.482163 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 10:55:13.488773 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 10:55:13.491906 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 10:55:13.495733 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 10:55:13.499185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 10:55:13.502288 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 10:55:13.508614 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 10:55:13.512379 ===================================
2252 10:55:13.515646 LPDDR4 DRAM CONFIGURATION
2253 10:55:13.518863 ===================================
2254 10:55:13.518946 EX_ROW_EN[0] = 0x0
2255 10:55:13.521978 EX_ROW_EN[1] = 0x0
2256 10:55:13.522059 LP4Y_EN = 0x0
2257 10:55:13.525866 WORK_FSP = 0x0
2258 10:55:13.525948 WL = 0x4
2259 10:55:13.529078 RL = 0x4
2260 10:55:13.529159 BL = 0x2
2261 10:55:13.532312 RPST = 0x0
2262 10:55:13.532394 RD_PRE = 0x0
2263 10:55:13.535549 WR_PRE = 0x1
2264 10:55:13.535630 WR_PST = 0x0
2265 10:55:13.538665 DBI_WR = 0x0
2266 10:55:13.538746 DBI_RD = 0x0
2267 10:55:13.542546 OTF = 0x1
2268 10:55:13.545795 ===================================
2269 10:55:13.549084 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 10:55:13.552320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 10:55:13.558898 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 10:55:13.562160 ===================================
2273 10:55:13.562242 LPDDR4 DRAM CONFIGURATION
2274 10:55:13.566050 ===================================
2275 10:55:13.569090 EX_ROW_EN[0] = 0x10
2276 10:55:13.572137 EX_ROW_EN[1] = 0x0
2277 10:55:13.572219 LP4Y_EN = 0x0
2278 10:55:13.575832 WORK_FSP = 0x0
2279 10:55:13.575913 WL = 0x4
2280 10:55:13.578954 RL = 0x4
2281 10:55:13.579035 BL = 0x2
2282 10:55:13.582157 RPST = 0x0
2283 10:55:13.582254 RD_PRE = 0x0
2284 10:55:13.585831 WR_PRE = 0x1
2285 10:55:13.585913 WR_PST = 0x0
2286 10:55:13.588843 DBI_WR = 0x0
2287 10:55:13.588924 DBI_RD = 0x0
2288 10:55:13.592354 OTF = 0x1
2289 10:55:13.595434 ===================================
2290 10:55:13.602287 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 10:55:13.602370 ==
2292 10:55:13.605424 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 10:55:13.609127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 10:55:13.609208 ==
2295 10:55:13.612193 [Duty_Offset_Calibration]
2296 10:55:13.612272 B0:2 B1:1 CA:1
2297 10:55:13.612335
2298 10:55:13.615985 [DutyScan_Calibration_Flow] k_type=0
2299 10:55:13.625765
2300 10:55:13.625844 ==CLK 0==
2301 10:55:13.628981 Final CLK duty delay cell = 0
2302 10:55:13.632139 [0] MAX Duty = 5156%(X100), DQS PI = 22
2303 10:55:13.635500 [0] MIN Duty = 4844%(X100), DQS PI = 48
2304 10:55:13.635589 [0] AVG Duty = 5000%(X100)
2305 10:55:13.638712
2306 10:55:13.638795 CH0 CLK Duty spec in!! Max-Min= 312%
2307 10:55:13.645646 [DutyScan_Calibration_Flow] ====Done====
2308 10:55:13.645726
2309 10:55:13.648865 [DutyScan_Calibration_Flow] k_type=1
2310 10:55:13.663005
2311 10:55:13.663085 ==DQS 0 ==
2312 10:55:13.666828 Final DQS duty delay cell = -4
2313 10:55:13.670055 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2314 10:55:13.673212 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2315 10:55:13.676554 [-4] AVG Duty = 4937%(X100)
2316 10:55:13.676633
2317 10:55:13.676696 ==DQS 1 ==
2318 10:55:13.680080 Final DQS duty delay cell = -4
2319 10:55:13.683180 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2320 10:55:13.686940 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2321 10:55:13.689963 [-4] AVG Duty = 4906%(X100)
2322 10:55:13.690042
2323 10:55:13.693583 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2324 10:55:13.693662
2325 10:55:13.696715 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2326 10:55:13.700074 [DutyScan_Calibration_Flow] ====Done====
2327 10:55:13.700154
2328 10:55:13.703074 [DutyScan_Calibration_Flow] k_type=3
2329 10:55:13.720621
2330 10:55:13.720707 ==DQM 0 ==
2331 10:55:13.723863 Final DQM duty delay cell = 0
2332 10:55:13.727150 [0] MAX Duty = 5156%(X100), DQS PI = 28
2333 10:55:13.730238 [0] MIN Duty = 4875%(X100), DQS PI = 58
2334 10:55:13.730318 [0] AVG Duty = 5015%(X100)
2335 10:55:13.733508
2336 10:55:13.733588 ==DQM 1 ==
2337 10:55:13.736865 Final DQM duty delay cell = 0
2338 10:55:13.740687 [0] MAX Duty = 5124%(X100), DQS PI = 60
2339 10:55:13.743839 [0] MIN Duty = 5031%(X100), DQS PI = 18
2340 10:55:13.743919 [0] AVG Duty = 5077%(X100)
2341 10:55:13.746959
2342 10:55:13.750732 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2343 10:55:13.750812
2344 10:55:13.753979 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2345 10:55:13.757180 [DutyScan_Calibration_Flow] ====Done====
2346 10:55:13.757259
2347 10:55:13.760444 [DutyScan_Calibration_Flow] k_type=2
2348 10:55:13.776925
2349 10:55:13.777005 ==DQ 0 ==
2350 10:55:13.780275 Final DQ duty delay cell = 0
2351 10:55:13.783460 [0] MAX Duty = 5031%(X100), DQS PI = 26
2352 10:55:13.787046 [0] MIN Duty = 4875%(X100), DQS PI = 0
2353 10:55:13.787126 [0] AVG Duty = 4953%(X100)
2354 10:55:13.787189
2355 10:55:13.790093 ==DQ 1 ==
2356 10:55:13.793720 Final DQ duty delay cell = 0
2357 10:55:13.796860 [0] MAX Duty = 5093%(X100), DQS PI = 24
2358 10:55:13.800510 [0] MIN Duty = 4969%(X100), DQS PI = 2
2359 10:55:13.800591 [0] AVG Duty = 5031%(X100)
2360 10:55:13.800654
2361 10:55:13.803517 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2362 10:55:13.803597
2363 10:55:13.807022 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2364 10:55:13.813906 [DutyScan_Calibration_Flow] ====Done====
2365 10:55:13.813986 ==
2366 10:55:13.817223 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 10:55:13.820366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 10:55:13.820448 ==
2369 10:55:13.823498 [Duty_Offset_Calibration]
2370 10:55:13.823577 B0:1 B1:0 CA:0
2371 10:55:13.823641
2372 10:55:13.827160 [DutyScan_Calibration_Flow] k_type=0
2373 10:55:13.836033
2374 10:55:13.836111 ==CLK 0==
2375 10:55:13.839270 Final CLK duty delay cell = -4
2376 10:55:13.842637 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2377 10:55:13.845862 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2378 10:55:13.849680 [-4] AVG Duty = 4969%(X100)
2379 10:55:13.849764
2380 10:55:13.852759 CH1 CLK Duty spec in!! Max-Min= 124%
2381 10:55:13.856054 [DutyScan_Calibration_Flow] ====Done====
2382 10:55:13.856136
2383 10:55:13.859302 [DutyScan_Calibration_Flow] k_type=1
2384 10:55:13.875938
2385 10:55:13.876019 ==DQS 0 ==
2386 10:55:13.879215 Final DQS duty delay cell = 0
2387 10:55:13.882531 [0] MAX Duty = 5094%(X100), DQS PI = 26
2388 10:55:13.886257 [0] MIN Duty = 4875%(X100), DQS PI = 0
2389 10:55:13.886368 [0] AVG Duty = 4984%(X100)
2390 10:55:13.886452
2391 10:55:13.889497 ==DQS 1 ==
2392 10:55:13.892741 Final DQS duty delay cell = 0
2393 10:55:13.896227 [0] MAX Duty = 5156%(X100), DQS PI = 18
2394 10:55:13.899357 [0] MIN Duty = 4938%(X100), DQS PI = 12
2395 10:55:13.899453 [0] AVG Duty = 5047%(X100)
2396 10:55:13.899518
2397 10:55:13.902955 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2398 10:55:13.905945
2399 10:55:13.909679 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2400 10:55:13.912715 [DutyScan_Calibration_Flow] ====Done====
2401 10:55:13.912798
2402 10:55:13.916302 [DutyScan_Calibration_Flow] k_type=3
2403 10:55:13.932523
2404 10:55:13.932604 ==DQM 0 ==
2405 10:55:13.935495 Final DQM duty delay cell = 0
2406 10:55:13.939115 [0] MAX Duty = 5156%(X100), DQS PI = 8
2407 10:55:13.942229 [0] MIN Duty = 5031%(X100), DQS PI = 0
2408 10:55:13.942319 [0] AVG Duty = 5093%(X100)
2409 10:55:13.945420
2410 10:55:13.945507 ==DQM 1 ==
2411 10:55:13.948718 Final DQM duty delay cell = 0
2412 10:55:13.952540 [0] MAX Duty = 5031%(X100), DQS PI = 16
2413 10:55:13.955641 [0] MIN Duty = 4907%(X100), DQS PI = 36
2414 10:55:13.955724 [0] AVG Duty = 4969%(X100)
2415 10:55:13.955789
2416 10:55:13.962527 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2417 10:55:13.962609
2418 10:55:13.965740 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2419 10:55:13.969548 [DutyScan_Calibration_Flow] ====Done====
2420 10:55:13.969630
2421 10:55:13.972745 [DutyScan_Calibration_Flow] k_type=2
2422 10:55:13.988260
2423 10:55:13.988342 ==DQ 0 ==
2424 10:55:13.991521 Final DQ duty delay cell = -4
2425 10:55:13.994725 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2426 10:55:13.998035 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2427 10:55:14.001807 [-4] AVG Duty = 5000%(X100)
2428 10:55:14.001890
2429 10:55:14.001955 ==DQ 1 ==
2430 10:55:14.004827 Final DQ duty delay cell = 0
2431 10:55:14.008317 [0] MAX Duty = 5125%(X100), DQS PI = 20
2432 10:55:14.011751 [0] MIN Duty = 4938%(X100), DQS PI = 34
2433 10:55:14.011826 [0] AVG Duty = 5031%(X100)
2434 10:55:14.011889
2435 10:55:14.014808 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2436 10:55:14.018471
2437 10:55:14.018567 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2438 10:55:14.025365 [DutyScan_Calibration_Flow] ====Done====
2439 10:55:14.028471 nWR fixed to 30
2440 10:55:14.028543 [ModeRegInit_LP4] CH0 RK0
2441 10:55:14.031559 [ModeRegInit_LP4] CH0 RK1
2442 10:55:14.035256 [ModeRegInit_LP4] CH1 RK0
2443 10:55:14.035388 [ModeRegInit_LP4] CH1 RK1
2444 10:55:14.038468 match AC timing 7
2445 10:55:14.042065 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 10:55:14.045050 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 10:55:14.051817 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 10:55:14.055066 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 10:55:14.061867 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 10:55:14.061966 ==
2451 10:55:14.065029 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 10:55:14.068269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 10:55:14.068343 ==
2454 10:55:14.075255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 10:55:14.078474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2456 10:55:14.088176 [CA 0] Center 39 (8~70) winsize 63
2457 10:55:14.091296 [CA 1] Center 39 (8~70) winsize 63
2458 10:55:14.095267 [CA 2] Center 35 (5~66) winsize 62
2459 10:55:14.098458 [CA 3] Center 34 (4~65) winsize 62
2460 10:55:14.101698 [CA 4] Center 33 (3~64) winsize 62
2461 10:55:14.104973 [CA 5] Center 32 (3~62) winsize 60
2462 10:55:14.105052
2463 10:55:14.108080 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2464 10:55:14.108150
2465 10:55:14.111753 [CATrainingPosCal] consider 1 rank data
2466 10:55:14.114705 u2DelayCellTimex100 = 270/100 ps
2467 10:55:14.118321 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2468 10:55:14.121272 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2469 10:55:14.128475 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2470 10:55:14.131672 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2471 10:55:14.134747 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2472 10:55:14.138548 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2473 10:55:14.138643
2474 10:55:14.141776 CA PerBit enable=1, Macro0, CA PI delay=32
2475 10:55:14.141869
2476 10:55:14.145042 [CBTSetCACLKResult] CA Dly = 32
2477 10:55:14.145111 CS Dly: 6 (0~37)
2478 10:55:14.145178 ==
2479 10:55:14.148240 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 10:55:14.155013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 10:55:14.155120 ==
2482 10:55:14.158571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 10:55:14.164837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2484 10:55:14.173850 [CA 0] Center 38 (8~69) winsize 62
2485 10:55:14.177669 [CA 1] Center 38 (8~69) winsize 62
2486 10:55:14.180983 [CA 2] Center 35 (4~66) winsize 63
2487 10:55:14.184228 [CA 3] Center 34 (4~65) winsize 62
2488 10:55:14.187355 [CA 4] Center 33 (3~64) winsize 62
2489 10:55:14.190611 [CA 5] Center 32 (3~62) winsize 60
2490 10:55:14.190722
2491 10:55:14.193806 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2492 10:55:14.193911
2493 10:55:14.197637 [CATrainingPosCal] consider 2 rank data
2494 10:55:14.200831 u2DelayCellTimex100 = 270/100 ps
2495 10:55:14.204017 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2496 10:55:14.207228 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2497 10:55:14.214074 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2498 10:55:14.217523 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2499 10:55:14.221107 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2500 10:55:14.224094 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2501 10:55:14.224165
2502 10:55:14.227910 CA PerBit enable=1, Macro0, CA PI delay=32
2503 10:55:14.227985
2504 10:55:14.230915 [CBTSetCACLKResult] CA Dly = 32
2505 10:55:14.231011 CS Dly: 6 (0~38)
2506 10:55:14.231107
2507 10:55:14.234592 ----->DramcWriteLeveling(PI) begin...
2508 10:55:14.234663 ==
2509 10:55:14.237682 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 10:55:14.244512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 10:55:14.244600 ==
2512 10:55:14.247746 Write leveling (Byte 0): 32 => 32
2513 10:55:14.250840 Write leveling (Byte 1): 31 => 31
2514 10:55:14.250913 DramcWriteLeveling(PI) end<-----
2515 10:55:14.254676
2516 10:55:14.254756 ==
2517 10:55:14.257826 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 10:55:14.261092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 10:55:14.261199 ==
2520 10:55:14.264114 [Gating] SW mode calibration
2521 10:55:14.270734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 10:55:14.274345 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 10:55:14.280837 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2524 10:55:14.284646 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2525 10:55:14.287739 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 10:55:14.294340 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 10:55:14.297666 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 10:55:14.301009 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 10:55:14.307500 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2530 10:55:14.310773 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2531 10:55:14.314094 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2532 10:55:14.321151 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 10:55:14.324127 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 10:55:14.328232 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 10:55:14.334165 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 10:55:14.337790 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 10:55:14.340842 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2538 10:55:14.344108 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2539 10:55:14.350844 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2540 10:55:14.354692 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 10:55:14.357947 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 10:55:14.364324 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 10:55:14.368205 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 10:55:14.371338 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 10:55:14.378088 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 10:55:14.381083 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 10:55:14.384710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 10:55:14.390998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 10:55:14.394438 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 10:55:14.398206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 10:55:14.404739 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:55:14.408101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:55:14.411228 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:55:14.414694 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:55:14.421092 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:55:14.424979 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:55:14.428138 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:55:14.434701 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:55:14.438364 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:55:14.441533 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:55:14.448005 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 10:55:14.451088 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2563 10:55:14.454632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 10:55:14.457842 Total UI for P1: 0, mck2ui 16
2565 10:55:14.461567 best dqsien dly found for B0: ( 1, 3, 26)
2566 10:55:14.467990 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 10:55:14.468074 Total UI for P1: 0, mck2ui 16
2568 10:55:14.471207 best dqsien dly found for B1: ( 1, 4, 0)
2569 10:55:14.478300 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2570 10:55:14.481371 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2571 10:55:14.481454
2572 10:55:14.485113 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2573 10:55:14.488129 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 10:55:14.491604 [Gating] SW calibration Done
2575 10:55:14.491686 ==
2576 10:55:14.495148 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 10:55:14.498477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 10:55:14.498560 ==
2579 10:55:14.498625 RX Vref Scan: 0
2580 10:55:14.498686
2581 10:55:14.501706 RX Vref 0 -> 0, step: 1
2582 10:55:14.501789
2583 10:55:14.504883 RX Delay -40 -> 252, step: 8
2584 10:55:14.508193 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2585 10:55:14.511530 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2586 10:55:14.518012 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2587 10:55:14.521675 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2588 10:55:14.524954 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2589 10:55:14.528149 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2590 10:55:14.532065 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2591 10:55:14.538376 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2592 10:55:14.541338 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2593 10:55:14.544778 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2594 10:55:14.548009 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2595 10:55:14.551561 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2596 10:55:14.558640 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2597 10:55:14.561800 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2598 10:55:14.564844 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2599 10:55:14.568581 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2600 10:55:14.568664 ==
2601 10:55:14.571688 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 10:55:14.574809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 10:55:14.578732 ==
2604 10:55:14.578814 DQS Delay:
2605 10:55:14.578879 DQS0 = 0, DQS1 = 0
2606 10:55:14.581982 DQM Delay:
2607 10:55:14.582064 DQM0 = 121, DQM1 = 113
2608 10:55:14.584982 DQ Delay:
2609 10:55:14.588422 DQ0 =119, DQ1 =127, DQ2 =119, DQ3 =119
2610 10:55:14.591562 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2611 10:55:14.595466 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2612 10:55:14.598465 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2613 10:55:14.598547
2614 10:55:14.598611
2615 10:55:14.598672 ==
2616 10:55:14.601930 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 10:55:14.605017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 10:55:14.605101 ==
2619 10:55:14.605167
2620 10:55:14.605227
2621 10:55:14.608935 TX Vref Scan disable
2622 10:55:14.611608 == TX Byte 0 ==
2623 10:55:14.615523 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2624 10:55:14.618730 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2625 10:55:14.621857 == TX Byte 1 ==
2626 10:55:14.625090 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2627 10:55:14.628182 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2628 10:55:14.628265 ==
2629 10:55:14.631568 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 10:55:14.635449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 10:55:14.638018 ==
2632 10:55:14.648171 TX Vref=22, minBit 0, minWin=25, winSum=412
2633 10:55:14.651742 TX Vref=24, minBit 0, minWin=25, winSum=413
2634 10:55:14.655451 TX Vref=26, minBit 0, minWin=25, winSum=418
2635 10:55:14.658543 TX Vref=28, minBit 12, minWin=25, winSum=422
2636 10:55:14.662045 TX Vref=30, minBit 1, minWin=26, winSum=428
2637 10:55:14.665019 TX Vref=32, minBit 1, minWin=26, winSum=425
2638 10:55:14.671861 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
2639 10:55:14.671945
2640 10:55:14.674934 Final TX Range 1 Vref 30
2641 10:55:14.675017
2642 10:55:14.675082 ==
2643 10:55:14.678720 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 10:55:14.681739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 10:55:14.681823 ==
2646 10:55:14.681889
2647 10:55:14.685520
2648 10:55:14.685641 TX Vref Scan disable
2649 10:55:14.688674 == TX Byte 0 ==
2650 10:55:14.691926 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2651 10:55:14.695206 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2652 10:55:14.698401 == TX Byte 1 ==
2653 10:55:14.702109 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2654 10:55:14.705377 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2655 10:55:14.705460
2656 10:55:14.708496 [DATLAT]
2657 10:55:14.708579 Freq=1200, CH0 RK0
2658 10:55:14.708645
2659 10:55:14.712078 DATLAT Default: 0xd
2660 10:55:14.712160 0, 0xFFFF, sum = 0
2661 10:55:14.714984 1, 0xFFFF, sum = 0
2662 10:55:14.715070 2, 0xFFFF, sum = 0
2663 10:55:14.718779 3, 0xFFFF, sum = 0
2664 10:55:14.718863 4, 0xFFFF, sum = 0
2665 10:55:14.722015 5, 0xFFFF, sum = 0
2666 10:55:14.722098 6, 0xFFFF, sum = 0
2667 10:55:14.725146 7, 0xFFFF, sum = 0
2668 10:55:14.725229 8, 0xFFFF, sum = 0
2669 10:55:14.728408 9, 0xFFFF, sum = 0
2670 10:55:14.728491 10, 0xFFFF, sum = 0
2671 10:55:14.732327 11, 0xFFFF, sum = 0
2672 10:55:14.732410 12, 0x0, sum = 1
2673 10:55:14.735532 13, 0x0, sum = 2
2674 10:55:14.735615 14, 0x0, sum = 3
2675 10:55:14.738763 15, 0x0, sum = 4
2676 10:55:14.738877 best_step = 13
2677 10:55:14.738942
2678 10:55:14.739003 ==
2679 10:55:14.742016 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 10:55:14.748595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 10:55:14.748678 ==
2682 10:55:14.748743 RX Vref Scan: 1
2683 10:55:14.748804
2684 10:55:14.752203 Set Vref Range= 32 -> 127
2685 10:55:14.752286
2686 10:55:14.755457 RX Vref 32 -> 127, step: 1
2687 10:55:14.755539
2688 10:55:14.758496 RX Delay -13 -> 252, step: 4
2689 10:55:14.758578
2690 10:55:14.762196 Set Vref, RX VrefLevel [Byte0]: 32
2691 10:55:14.765144 [Byte1]: 32
2692 10:55:14.765226
2693 10:55:14.768589 Set Vref, RX VrefLevel [Byte0]: 33
2694 10:55:14.772142 [Byte1]: 33
2695 10:55:14.772224
2696 10:55:14.775498 Set Vref, RX VrefLevel [Byte0]: 34
2697 10:55:14.778420 [Byte1]: 34
2698 10:55:14.782801
2699 10:55:14.782883 Set Vref, RX VrefLevel [Byte0]: 35
2700 10:55:14.785989 [Byte1]: 35
2701 10:55:14.790721
2702 10:55:14.790802 Set Vref, RX VrefLevel [Byte0]: 36
2703 10:55:14.793701 [Byte1]: 36
2704 10:55:14.798180
2705 10:55:14.798262 Set Vref, RX VrefLevel [Byte0]: 37
2706 10:55:14.801467 [Byte1]: 37
2707 10:55:14.805868
2708 10:55:14.805951 Set Vref, RX VrefLevel [Byte0]: 38
2709 10:55:14.809806 [Byte1]: 38
2710 10:55:14.814119
2711 10:55:14.814200 Set Vref, RX VrefLevel [Byte0]: 39
2712 10:55:14.817461 [Byte1]: 39
2713 10:55:14.821642
2714 10:55:14.821753 Set Vref, RX VrefLevel [Byte0]: 40
2715 10:55:14.825469 [Byte1]: 40
2716 10:55:14.829916
2717 10:55:14.829998 Set Vref, RX VrefLevel [Byte0]: 41
2718 10:55:14.833115 [Byte1]: 41
2719 10:55:14.837664
2720 10:55:14.837746 Set Vref, RX VrefLevel [Byte0]: 42
2721 10:55:14.840783 [Byte1]: 42
2722 10:55:14.845436
2723 10:55:14.845517 Set Vref, RX VrefLevel [Byte0]: 43
2724 10:55:14.848619 [Byte1]: 43
2725 10:55:14.853665
2726 10:55:14.853747 Set Vref, RX VrefLevel [Byte0]: 44
2727 10:55:14.856814 [Byte1]: 44
2728 10:55:14.861274
2729 10:55:14.861356 Set Vref, RX VrefLevel [Byte0]: 45
2730 10:55:14.864455 [Byte1]: 45
2731 10:55:14.869407
2732 10:55:14.869488 Set Vref, RX VrefLevel [Byte0]: 46
2733 10:55:14.872462 [Byte1]: 46
2734 10:55:14.877210
2735 10:55:14.877294 Set Vref, RX VrefLevel [Byte0]: 47
2736 10:55:14.880207 [Byte1]: 47
2737 10:55:14.884783
2738 10:55:14.884889 Set Vref, RX VrefLevel [Byte0]: 48
2739 10:55:14.888184 [Byte1]: 48
2740 10:55:14.893242
2741 10:55:14.893320 Set Vref, RX VrefLevel [Byte0]: 49
2742 10:55:14.896468 [Byte1]: 49
2743 10:55:14.900572
2744 10:55:14.900644 Set Vref, RX VrefLevel [Byte0]: 50
2745 10:55:14.904364 [Byte1]: 50
2746 10:55:14.908818
2747 10:55:14.908892 Set Vref, RX VrefLevel [Byte0]: 51
2748 10:55:14.912040 [Byte1]: 51
2749 10:55:14.916348
2750 10:55:14.916421 Set Vref, RX VrefLevel [Byte0]: 52
2751 10:55:14.920027 [Byte1]: 52
2752 10:55:14.924633
2753 10:55:14.924700 Set Vref, RX VrefLevel [Byte0]: 53
2754 10:55:14.927612 [Byte1]: 53
2755 10:55:14.932625
2756 10:55:14.932702 Set Vref, RX VrefLevel [Byte0]: 54
2757 10:55:14.935850 [Byte1]: 54
2758 10:55:14.940450
2759 10:55:14.940525 Set Vref, RX VrefLevel [Byte0]: 55
2760 10:55:14.943682 [Byte1]: 55
2761 10:55:14.948081
2762 10:55:14.948200 Set Vref, RX VrefLevel [Byte0]: 56
2763 10:55:14.951465 [Byte1]: 56
2764 10:55:14.955941
2765 10:55:14.956045 Set Vref, RX VrefLevel [Byte0]: 57
2766 10:55:14.959083 [Byte1]: 57
2767 10:55:14.964170
2768 10:55:14.964244 Set Vref, RX VrefLevel [Byte0]: 58
2769 10:55:14.967470 [Byte1]: 58
2770 10:55:14.971963
2771 10:55:14.972036 Set Vref, RX VrefLevel [Byte0]: 59
2772 10:55:14.975146 [Byte1]: 59
2773 10:55:14.979551
2774 10:55:14.979632 Set Vref, RX VrefLevel [Byte0]: 60
2775 10:55:14.983009 [Byte1]: 60
2776 10:55:14.987239
2777 10:55:14.987317 Set Vref, RX VrefLevel [Byte0]: 61
2778 10:55:14.990888 [Byte1]: 61
2779 10:55:14.995582
2780 10:55:14.995659 Set Vref, RX VrefLevel [Byte0]: 62
2781 10:55:14.998649 [Byte1]: 62
2782 10:55:15.003511
2783 10:55:15.003588 Set Vref, RX VrefLevel [Byte0]: 63
2784 10:55:15.006673 [Byte1]: 63
2785 10:55:15.011569
2786 10:55:15.011649 Set Vref, RX VrefLevel [Byte0]: 64
2787 10:55:15.014681 [Byte1]: 64
2788 10:55:15.019179
2789 10:55:15.019259 Set Vref, RX VrefLevel [Byte0]: 65
2790 10:55:15.022220 [Byte1]: 65
2791 10:55:15.027043
2792 10:55:15.027124 Set Vref, RX VrefLevel [Byte0]: 66
2793 10:55:15.030298 [Byte1]: 66
2794 10:55:15.035206
2795 10:55:15.035286 Set Vref, RX VrefLevel [Byte0]: 67
2796 10:55:15.038338 [Byte1]: 67
2797 10:55:15.042735
2798 10:55:15.042818 Set Vref, RX VrefLevel [Byte0]: 68
2799 10:55:15.045946 [Byte1]: 68
2800 10:55:15.050511
2801 10:55:15.050592 Set Vref, RX VrefLevel [Byte0]: 69
2802 10:55:15.053797 [Byte1]: 69
2803 10:55:15.058877
2804 10:55:15.058957 Final RX Vref Byte 0 = 55 to rank0
2805 10:55:15.062060 Final RX Vref Byte 1 = 50 to rank0
2806 10:55:15.065070 Final RX Vref Byte 0 = 55 to rank1
2807 10:55:15.068991 Final RX Vref Byte 1 = 50 to rank1==
2808 10:55:15.072207 Dram Type= 6, Freq= 0, CH_0, rank 0
2809 10:55:15.078527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2810 10:55:15.078608 ==
2811 10:55:15.078672 DQS Delay:
2812 10:55:15.078731 DQS0 = 0, DQS1 = 0
2813 10:55:15.081656 DQM Delay:
2814 10:55:15.081736 DQM0 = 120, DQM1 = 112
2815 10:55:15.085371 DQ Delay:
2816 10:55:15.088538 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
2817 10:55:15.092228 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2818 10:55:15.095253 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2819 10:55:15.098620 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2820 10:55:15.098701
2821 10:55:15.098763
2822 10:55:15.105604 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2823 10:55:15.108488 CH0 RK0: MR19=404, MR18=130C
2824 10:55:15.115485 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2825 10:55:15.115567
2826 10:55:15.119051 ----->DramcWriteLeveling(PI) begin...
2827 10:55:15.119132 ==
2828 10:55:15.122150 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 10:55:15.125124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 10:55:15.128709 ==
2831 10:55:15.128790 Write leveling (Byte 0): 32 => 32
2832 10:55:15.131907 Write leveling (Byte 1): 28 => 28
2833 10:55:15.135690 DramcWriteLeveling(PI) end<-----
2834 10:55:15.135771
2835 10:55:15.135834 ==
2836 10:55:15.138870 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 10:55:15.145091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 10:55:15.145173 ==
2839 10:55:15.145238 [Gating] SW mode calibration
2840 10:55:15.155421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2841 10:55:15.158700 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2842 10:55:15.161989 0 15 0 | B1->B0 | 3232 2f2e | 0 1 | (0 0) (0 0)
2843 10:55:15.168786 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 10:55:15.172051 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 10:55:15.175252 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 10:55:15.182418 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 10:55:15.185689 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 10:55:15.188879 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 10:55:15.195822 0 15 28 | B1->B0 | 2d2d 2c2c | 0 1 | (0 0) (1 0)
2850 10:55:15.198825 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 10:55:15.202013 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 10:55:15.209084 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 10:55:15.212084 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 10:55:15.215876 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 10:55:15.222120 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 10:55:15.225871 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
2857 10:55:15.229140 1 0 28 | B1->B0 | 3636 3838 | 0 1 | (0 0) (0 0)
2858 10:55:15.232216 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2859 10:55:15.238762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 10:55:15.242556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 10:55:15.245657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 10:55:15.252396 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 10:55:15.255680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 10:55:15.259059 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 10:55:15.265569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2866 10:55:15.268852 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2867 10:55:15.272589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:55:15.279212 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:55:15.282460 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:55:15.285633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:55:15.292201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 10:55:15.295798 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:55:15.298892 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 10:55:15.305847 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:55:15.308711 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:55:15.312261 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 10:55:15.319045 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 10:55:15.322044 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 10:55:15.325923 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 10:55:15.329101 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2881 10:55:15.335450 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2882 10:55:15.338757 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2883 10:55:15.342446 Total UI for P1: 0, mck2ui 16
2884 10:55:15.345419 best dqsien dly found for B1: ( 1, 3, 26)
2885 10:55:15.349018 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 10:55:15.352059 Total UI for P1: 0, mck2ui 16
2887 10:55:15.355873 best dqsien dly found for B0: ( 1, 4, 0)
2888 10:55:15.359038 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2889 10:55:15.362341 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2890 10:55:15.362436
2891 10:55:15.368629 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2892 10:55:15.372576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2893 10:55:15.372645 [Gating] SW calibration Done
2894 10:55:15.375546 ==
2895 10:55:15.378767 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 10:55:15.381942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 10:55:15.382035 ==
2898 10:55:15.382123 RX Vref Scan: 0
2899 10:55:15.382210
2900 10:55:15.385747 RX Vref 0 -> 0, step: 1
2901 10:55:15.385839
2902 10:55:15.388958 RX Delay -40 -> 252, step: 8
2903 10:55:15.392235 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2904 10:55:15.395433 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2905 10:55:15.399081 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2906 10:55:15.405566 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2907 10:55:15.408617 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2908 10:55:15.412493 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2909 10:55:15.415373 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2910 10:55:15.418831 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2911 10:55:15.425426 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2912 10:55:15.429063 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2913 10:55:15.432164 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2914 10:55:15.435470 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2915 10:55:15.439139 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2916 10:55:15.445547 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2917 10:55:15.448802 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2918 10:55:15.452470 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2919 10:55:15.452542 ==
2920 10:55:15.455908 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 10:55:15.458841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 10:55:15.458945 ==
2923 10:55:15.462552 DQS Delay:
2924 10:55:15.462671 DQS0 = 0, DQS1 = 0
2925 10:55:15.465736 DQM Delay:
2926 10:55:15.465839 DQM0 = 122, DQM1 = 112
2927 10:55:15.465939 DQ Delay:
2928 10:55:15.468996 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2929 10:55:15.475582 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2930 10:55:15.479431 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2931 10:55:15.482455 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2932 10:55:15.482542
2933 10:55:15.482637
2934 10:55:15.482730 ==
2935 10:55:15.485719 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 10:55:15.489054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 10:55:15.489152 ==
2938 10:55:15.489244
2939 10:55:15.489340
2940 10:55:15.492347 TX Vref Scan disable
2941 10:55:15.496199 == TX Byte 0 ==
2942 10:55:15.499315 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2943 10:55:15.502663 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2944 10:55:15.505723 == TX Byte 1 ==
2945 10:55:15.508985 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2946 10:55:15.512188 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2947 10:55:15.512261 ==
2948 10:55:15.515947 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 10:55:15.518788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 10:55:15.518880 ==
2951 10:55:15.532543 TX Vref=22, minBit 1, minWin=25, winSum=415
2952 10:55:15.535622 TX Vref=24, minBit 1, minWin=25, winSum=418
2953 10:55:15.539015 TX Vref=26, minBit 3, minWin=25, winSum=425
2954 10:55:15.542682 TX Vref=28, minBit 1, minWin=26, winSum=428
2955 10:55:15.545699 TX Vref=30, minBit 1, minWin=26, winSum=430
2956 10:55:15.549564 TX Vref=32, minBit 0, minWin=26, winSum=424
2957 10:55:15.555949 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
2958 10:55:15.556032
2959 10:55:15.559573 Final TX Range 1 Vref 30
2960 10:55:15.559656
2961 10:55:15.559720 ==
2962 10:55:15.562754 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 10:55:15.565865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 10:55:15.565950 ==
2965 10:55:15.566014
2966 10:55:15.566073
2967 10:55:15.569624 TX Vref Scan disable
2968 10:55:15.572637 == TX Byte 0 ==
2969 10:55:15.575737 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2970 10:55:15.579604 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2971 10:55:15.582707 == TX Byte 1 ==
2972 10:55:15.586435 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2973 10:55:15.589605 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2974 10:55:15.589684
2975 10:55:15.592845 [DATLAT]
2976 10:55:15.592921 Freq=1200, CH0 RK1
2977 10:55:15.592989
2978 10:55:15.596104 DATLAT Default: 0xd
2979 10:55:15.596178 0, 0xFFFF, sum = 0
2980 10:55:15.599938 1, 0xFFFF, sum = 0
2981 10:55:15.600009 2, 0xFFFF, sum = 0
2982 10:55:15.603209 3, 0xFFFF, sum = 0
2983 10:55:15.603363 4, 0xFFFF, sum = 0
2984 10:55:15.606483 5, 0xFFFF, sum = 0
2985 10:55:15.606561 6, 0xFFFF, sum = 0
2986 10:55:15.609489 7, 0xFFFF, sum = 0
2987 10:55:15.609563 8, 0xFFFF, sum = 0
2988 10:55:15.612734 9, 0xFFFF, sum = 0
2989 10:55:15.612840 10, 0xFFFF, sum = 0
2990 10:55:15.616656 11, 0xFFFF, sum = 0
2991 10:55:15.616730 12, 0x0, sum = 1
2992 10:55:15.619811 13, 0x0, sum = 2
2993 10:55:15.619888 14, 0x0, sum = 3
2994 10:55:15.623097 15, 0x0, sum = 4
2995 10:55:15.623205 best_step = 13
2996 10:55:15.623300
2997 10:55:15.623425 ==
2998 10:55:15.626153 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 10:55:15.633270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 10:55:15.633348 ==
3001 10:55:15.633411 RX Vref Scan: 0
3002 10:55:15.633469
3003 10:55:15.636246 RX Vref 0 -> 0, step: 1
3004 10:55:15.636322
3005 10:55:15.639912 RX Delay -13 -> 252, step: 4
3006 10:55:15.643034 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3007 10:55:15.646045 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3008 10:55:15.652983 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3009 10:55:15.656138 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3010 10:55:15.660024 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3011 10:55:15.663250 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3012 10:55:15.666245 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3013 10:55:15.669497 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3014 10:55:15.676502 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3015 10:55:15.679502 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3016 10:55:15.683243 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3017 10:55:15.686458 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3018 10:55:15.689558 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3019 10:55:15.696620 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3020 10:55:15.699839 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3021 10:55:15.702980 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3022 10:55:15.703078 ==
3023 10:55:15.706136 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 10:55:15.709499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 10:55:15.709601 ==
3026 10:55:15.713315 DQS Delay:
3027 10:55:15.713412 DQS0 = 0, DQS1 = 0
3028 10:55:15.716531 DQM Delay:
3029 10:55:15.716630 DQM0 = 121, DQM1 = 110
3030 10:55:15.719811 DQ Delay:
3031 10:55:15.722831 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3032 10:55:15.726164 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3033 10:55:15.729903 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3034 10:55:15.732851 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3035 10:55:15.732952
3036 10:55:15.733042
3037 10:55:15.739649 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3038 10:55:15.743178 CH0 RK1: MR19=403, MR18=11F2
3039 10:55:15.749842 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3040 10:55:15.753032 [RxdqsGatingPostProcess] freq 1200
3041 10:55:15.759869 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3042 10:55:15.759948 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 10:55:15.763146 best DQS1 dly(2T, 0.5T) = (0, 12)
3044 10:55:15.766255 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 10:55:15.770027 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3046 10:55:15.773206 best DQS0 dly(2T, 0.5T) = (0, 12)
3047 10:55:15.776379 best DQS1 dly(2T, 0.5T) = (0, 11)
3048 10:55:15.780256 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3049 10:55:15.783476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3050 10:55:15.786430 Pre-setting of DQS Precalculation
3051 10:55:15.790311 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3052 10:55:15.790392 ==
3053 10:55:15.793461 Dram Type= 6, Freq= 0, CH_1, rank 0
3054 10:55:15.799817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 10:55:15.799899 ==
3056 10:55:15.803069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3057 10:55:15.810179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3058 10:55:15.818888 [CA 0] Center 37 (7~68) winsize 62
3059 10:55:15.822096 [CA 1] Center 38 (8~68) winsize 61
3060 10:55:15.825432 [CA 2] Center 35 (5~65) winsize 61
3061 10:55:15.828558 [CA 3] Center 34 (4~64) winsize 61
3062 10:55:15.831706 [CA 4] Center 34 (4~64) winsize 61
3063 10:55:15.835686 [CA 5] Center 33 (3~63) winsize 61
3064 10:55:15.835767
3065 10:55:15.838821 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3066 10:55:15.838901
3067 10:55:15.841769 [CATrainingPosCal] consider 1 rank data
3068 10:55:15.845422 u2DelayCellTimex100 = 270/100 ps
3069 10:55:15.848603 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 10:55:15.852213 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3071 10:55:15.858818 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3072 10:55:15.861932 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3073 10:55:15.865559 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3074 10:55:15.868616 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3075 10:55:15.868697
3076 10:55:15.872318 CA PerBit enable=1, Macro0, CA PI delay=33
3077 10:55:15.872399
3078 10:55:15.875508 [CBTSetCACLKResult] CA Dly = 33
3079 10:55:15.875590 CS Dly: 8 (0~39)
3080 10:55:15.875654 ==
3081 10:55:15.878695 Dram Type= 6, Freq= 0, CH_1, rank 1
3082 10:55:15.885601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 10:55:15.885683 ==
3084 10:55:15.888896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 10:55:15.895613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3086 10:55:15.904346 [CA 0] Center 37 (7~68) winsize 62
3087 10:55:15.907545 [CA 1] Center 37 (7~68) winsize 62
3088 10:55:15.910769 [CA 2] Center 35 (5~65) winsize 61
3089 10:55:15.914652 [CA 3] Center 35 (5~65) winsize 61
3090 10:55:15.917942 [CA 4] Center 34 (4~65) winsize 62
3091 10:55:15.921134 [CA 5] Center 34 (4~64) winsize 61
3092 10:55:15.921208
3093 10:55:15.924213 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3094 10:55:15.924287
3095 10:55:15.927402 [CATrainingPosCal] consider 2 rank data
3096 10:55:15.931167 u2DelayCellTimex100 = 270/100 ps
3097 10:55:15.934294 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3098 10:55:15.937516 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3099 10:55:15.944214 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3100 10:55:15.947803 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3101 10:55:15.951058 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 10:55:15.954617 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3103 10:55:15.954701
3104 10:55:15.958215 CA PerBit enable=1, Macro0, CA PI delay=33
3105 10:55:15.958323
3106 10:55:15.961186 [CBTSetCACLKResult] CA Dly = 33
3107 10:55:15.961274 CS Dly: 9 (0~41)
3108 10:55:15.961358
3109 10:55:15.964745 ----->DramcWriteLeveling(PI) begin...
3110 10:55:15.964830 ==
3111 10:55:15.967967 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 10:55:15.974590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 10:55:15.974675 ==
3114 10:55:15.977695 Write leveling (Byte 0): 27 => 27
3115 10:55:15.980907 Write leveling (Byte 1): 28 => 28
3116 10:55:15.980991 DramcWriteLeveling(PI) end<-----
3117 10:55:15.984798
3118 10:55:15.984894 ==
3119 10:55:15.988052 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 10:55:15.991198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 10:55:15.991307 ==
3122 10:55:15.994971 [Gating] SW mode calibration
3123 10:55:16.001581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3124 10:55:16.004689 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3125 10:55:16.011761 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 10:55:16.014937 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 10:55:16.018203 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 10:55:16.024520 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 10:55:16.028211 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 10:55:16.031516 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 10:55:16.037964 0 15 24 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (0 0)
3132 10:55:16.041113 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3133 10:55:16.045090 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 10:55:16.051532 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 10:55:16.054617 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 10:55:16.057816 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 10:55:16.061618 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 10:55:16.067928 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 10:55:16.071531 1 0 24 | B1->B0 | 3434 3f3f | 0 1 | (0 0) (0 0)
3140 10:55:16.074716 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 10:55:16.081542 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 10:55:16.084620 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 10:55:16.088386 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 10:55:16.094903 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 10:55:16.098044 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 10:55:16.101828 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 10:55:16.108416 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 10:55:16.111551 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3149 10:55:16.114676 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:55:16.121462 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:55:16.124791 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:55:16.128399 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:55:16.131422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:55:16.138592 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 10:55:16.141737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:55:16.144880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:55:16.151970 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:55:16.155110 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 10:55:16.158422 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 10:55:16.164832 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 10:55:16.168384 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 10:55:16.171912 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 10:55:16.178541 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 10:55:16.181798 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3165 10:55:16.185244 Total UI for P1: 0, mck2ui 16
3166 10:55:16.188272 best dqsien dly found for B0: ( 1, 3, 24)
3167 10:55:16.192039 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 10:55:16.195215 Total UI for P1: 0, mck2ui 16
3169 10:55:16.198442 best dqsien dly found for B1: ( 1, 3, 26)
3170 10:55:16.201626 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3171 10:55:16.205411 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3172 10:55:16.205519
3173 10:55:16.208489 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3174 10:55:16.215216 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3175 10:55:16.215317 [Gating] SW calibration Done
3176 10:55:16.218224 ==
3177 10:55:16.218309 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 10:55:16.225160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 10:55:16.225253 ==
3180 10:55:16.225333 RX Vref Scan: 0
3181 10:55:16.225394
3182 10:55:16.228546 RX Vref 0 -> 0, step: 1
3183 10:55:16.228620
3184 10:55:16.231677 RX Delay -40 -> 252, step: 8
3185 10:55:16.234836 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3186 10:55:16.238670 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3187 10:55:16.241834 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3188 10:55:16.248441 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3189 10:55:16.251567 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3190 10:55:16.254846 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3191 10:55:16.258188 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3192 10:55:16.261995 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3193 10:55:16.265196 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3194 10:55:16.271767 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3195 10:55:16.275548 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3196 10:55:16.278627 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3197 10:55:16.281675 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3198 10:55:16.288253 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3199 10:55:16.291841 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3200 10:55:16.294932 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3201 10:55:16.295017 ==
3202 10:55:16.298008 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 10:55:16.301838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 10:55:16.301920 ==
3205 10:55:16.305212 DQS Delay:
3206 10:55:16.305310 DQS0 = 0, DQS1 = 0
3207 10:55:16.308301 DQM Delay:
3208 10:55:16.308376 DQM0 = 120, DQM1 = 116
3209 10:55:16.308439 DQ Delay:
3210 10:55:16.311947 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3211 10:55:16.318230 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3212 10:55:16.321390 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3213 10:55:16.324866 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3214 10:55:16.324949
3215 10:55:16.325013
3216 10:55:16.325073 ==
3217 10:55:16.328497 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 10:55:16.331698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 10:55:16.331782 ==
3220 10:55:16.331847
3221 10:55:16.331908
3222 10:55:16.334820 TX Vref Scan disable
3223 10:55:16.338001 == TX Byte 0 ==
3224 10:55:16.341679 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3225 10:55:16.344902 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3226 10:55:16.348160 == TX Byte 1 ==
3227 10:55:16.351507 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3228 10:55:16.355147 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3229 10:55:16.355230 ==
3230 10:55:16.358333 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 10:55:16.361456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 10:55:16.361540 ==
3233 10:55:16.374324 TX Vref=22, minBit 1, minWin=24, winSum=409
3234 10:55:16.378235 TX Vref=24, minBit 9, minWin=25, winSum=418
3235 10:55:16.381265 TX Vref=26, minBit 9, minWin=25, winSum=422
3236 10:55:16.384205 TX Vref=28, minBit 1, minWin=26, winSum=425
3237 10:55:16.387869 TX Vref=30, minBit 1, minWin=26, winSum=432
3238 10:55:16.394717 TX Vref=32, minBit 10, minWin=25, winSum=429
3239 10:55:16.397638 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3240 10:55:16.397721
3241 10:55:16.400806 Final TX Range 1 Vref 30
3242 10:55:16.400888
3243 10:55:16.400954 ==
3244 10:55:16.404108 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 10:55:16.407381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 10:55:16.410643 ==
3247 10:55:16.410726
3248 10:55:16.410791
3249 10:55:16.410851 TX Vref Scan disable
3250 10:55:16.414435 == TX Byte 0 ==
3251 10:55:16.417359 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3252 10:55:16.423928 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3253 10:55:16.424011 == TX Byte 1 ==
3254 10:55:16.427804 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3255 10:55:16.434058 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3256 10:55:16.434156
3257 10:55:16.434221 [DATLAT]
3258 10:55:16.434281 Freq=1200, CH1 RK0
3259 10:55:16.434340
3260 10:55:16.437584 DATLAT Default: 0xd
3261 10:55:16.437667 0, 0xFFFF, sum = 0
3262 10:55:16.440737 1, 0xFFFF, sum = 0
3263 10:55:16.440820 2, 0xFFFF, sum = 0
3264 10:55:16.444424 3, 0xFFFF, sum = 0
3265 10:55:16.447644 4, 0xFFFF, sum = 0
3266 10:55:16.447728 5, 0xFFFF, sum = 0
3267 10:55:16.450877 6, 0xFFFF, sum = 0
3268 10:55:16.450960 7, 0xFFFF, sum = 0
3269 10:55:16.454104 8, 0xFFFF, sum = 0
3270 10:55:16.454187 9, 0xFFFF, sum = 0
3271 10:55:16.457210 10, 0xFFFF, sum = 0
3272 10:55:16.457294 11, 0xFFFF, sum = 0
3273 10:55:16.460488 12, 0x0, sum = 1
3274 10:55:16.460571 13, 0x0, sum = 2
3275 10:55:16.463803 14, 0x0, sum = 3
3276 10:55:16.463889 15, 0x0, sum = 4
3277 10:55:16.463955 best_step = 13
3278 10:55:16.467705
3279 10:55:16.467787 ==
3280 10:55:16.470824 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 10:55:16.473972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 10:55:16.474055 ==
3283 10:55:16.474120 RX Vref Scan: 1
3284 10:55:16.474181
3285 10:55:16.477272 Set Vref Range= 32 -> 127
3286 10:55:16.477354
3287 10:55:16.481153 RX Vref 32 -> 127, step: 1
3288 10:55:16.481235
3289 10:55:16.483768 RX Delay -5 -> 252, step: 4
3290 10:55:16.483850
3291 10:55:16.487501 Set Vref, RX VrefLevel [Byte0]: 32
3292 10:55:16.490604 [Byte1]: 32
3293 10:55:16.490684
3294 10:55:16.494224 Set Vref, RX VrefLevel [Byte0]: 33
3295 10:55:16.497229 [Byte1]: 33
3296 10:55:16.497309
3297 10:55:16.500824 Set Vref, RX VrefLevel [Byte0]: 34
3298 10:55:16.503886 [Byte1]: 34
3299 10:55:16.508580
3300 10:55:16.508660 Set Vref, RX VrefLevel [Byte0]: 35
3301 10:55:16.511610 [Byte1]: 35
3302 10:55:16.516647
3303 10:55:16.516728 Set Vref, RX VrefLevel [Byte0]: 36
3304 10:55:16.519817 [Byte1]: 36
3305 10:55:16.524022
3306 10:55:16.524102 Set Vref, RX VrefLevel [Byte0]: 37
3307 10:55:16.527160 [Byte1]: 37
3308 10:55:16.531779
3309 10:55:16.531860 Set Vref, RX VrefLevel [Byte0]: 38
3310 10:55:16.535030 [Byte1]: 38
3311 10:55:16.539979
3312 10:55:16.540058 Set Vref, RX VrefLevel [Byte0]: 39
3313 10:55:16.542923 [Byte1]: 39
3314 10:55:16.547705
3315 10:55:16.547785 Set Vref, RX VrefLevel [Byte0]: 40
3316 10:55:16.550748 [Byte1]: 40
3317 10:55:16.555423
3318 10:55:16.558483 Set Vref, RX VrefLevel [Byte0]: 41
3319 10:55:16.561654 [Byte1]: 41
3320 10:55:16.561737
3321 10:55:16.565513 Set Vref, RX VrefLevel [Byte0]: 42
3322 10:55:16.568812 [Byte1]: 42
3323 10:55:16.568892
3324 10:55:16.572026 Set Vref, RX VrefLevel [Byte0]: 43
3325 10:55:16.575109 [Byte1]: 43
3326 10:55:16.579009
3327 10:55:16.579088 Set Vref, RX VrefLevel [Byte0]: 44
3328 10:55:16.582106 [Byte1]: 44
3329 10:55:16.586682
3330 10:55:16.586762 Set Vref, RX VrefLevel [Byte0]: 45
3331 10:55:16.589984 [Byte1]: 45
3332 10:55:16.594463
3333 10:55:16.594542 Set Vref, RX VrefLevel [Byte0]: 46
3334 10:55:16.598086 [Byte1]: 46
3335 10:55:16.602378
3336 10:55:16.602457 Set Vref, RX VrefLevel [Byte0]: 47
3337 10:55:16.605981 [Byte1]: 47
3338 10:55:16.610322
3339 10:55:16.610428 Set Vref, RX VrefLevel [Byte0]: 48
3340 10:55:16.613887 [Byte1]: 48
3341 10:55:16.618061
3342 10:55:16.618163 Set Vref, RX VrefLevel [Byte0]: 49
3343 10:55:16.621509 [Byte1]: 49
3344 10:55:16.625846
3345 10:55:16.625949 Set Vref, RX VrefLevel [Byte0]: 50
3346 10:55:16.629646 [Byte1]: 50
3347 10:55:16.633876
3348 10:55:16.633979 Set Vref, RX VrefLevel [Byte0]: 51
3349 10:55:16.637255 [Byte1]: 51
3350 10:55:16.641619
3351 10:55:16.641722 Set Vref, RX VrefLevel [Byte0]: 52
3352 10:55:16.645244 [Byte1]: 52
3353 10:55:16.649573
3354 10:55:16.649682 Set Vref, RX VrefLevel [Byte0]: 53
3355 10:55:16.653242 [Byte1]: 53
3356 10:55:16.657317
3357 10:55:16.657421 Set Vref, RX VrefLevel [Byte0]: 54
3358 10:55:16.661170 [Byte1]: 54
3359 10:55:16.665679
3360 10:55:16.665787 Set Vref, RX VrefLevel [Byte0]: 55
3361 10:55:16.668883 [Byte1]: 55
3362 10:55:16.673392
3363 10:55:16.673492 Set Vref, RX VrefLevel [Byte0]: 56
3364 10:55:16.676567 [Byte1]: 56
3365 10:55:16.681098
3366 10:55:16.681200 Set Vref, RX VrefLevel [Byte0]: 57
3367 10:55:16.684401 [Byte1]: 57
3368 10:55:16.688943
3369 10:55:16.689043 Set Vref, RX VrefLevel [Byte0]: 58
3370 10:55:16.692111 [Byte1]: 58
3371 10:55:16.696560
3372 10:55:16.696667 Set Vref, RX VrefLevel [Byte0]: 59
3373 10:55:16.700303 [Byte1]: 59
3374 10:55:16.704870
3375 10:55:16.704956 Set Vref, RX VrefLevel [Byte0]: 60
3376 10:55:16.707855 [Byte1]: 60
3377 10:55:16.712564
3378 10:55:16.712654 Set Vref, RX VrefLevel [Byte0]: 61
3379 10:55:16.716151 [Byte1]: 61
3380 10:55:16.720471
3381 10:55:16.720545 Set Vref, RX VrefLevel [Byte0]: 62
3382 10:55:16.723496 [Byte1]: 62
3383 10:55:16.728248
3384 10:55:16.728368 Set Vref, RX VrefLevel [Byte0]: 63
3385 10:55:16.731519 [Byte1]: 63
3386 10:55:16.735850
3387 10:55:16.735932 Set Vref, RX VrefLevel [Byte0]: 64
3388 10:55:16.739039 [Byte1]: 64
3389 10:55:16.744170
3390 10:55:16.744240 Set Vref, RX VrefLevel [Byte0]: 65
3391 10:55:16.747153 [Byte1]: 65
3392 10:55:16.751620
3393 10:55:16.751703 Set Vref, RX VrefLevel [Byte0]: 66
3394 10:55:16.754824 [Byte1]: 66
3395 10:55:16.759586
3396 10:55:16.759666 Set Vref, RX VrefLevel [Byte0]: 67
3397 10:55:16.762903 [Byte1]: 67
3398 10:55:16.767766
3399 10:55:16.767837 Set Vref, RX VrefLevel [Byte0]: 68
3400 10:55:16.770910 [Byte1]: 68
3401 10:55:16.775423
3402 10:55:16.775496 Final RX Vref Byte 0 = 55 to rank0
3403 10:55:16.778708 Final RX Vref Byte 1 = 52 to rank0
3404 10:55:16.781911 Final RX Vref Byte 0 = 55 to rank1
3405 10:55:16.785452 Final RX Vref Byte 1 = 52 to rank1==
3406 10:55:16.788668 Dram Type= 6, Freq= 0, CH_1, rank 0
3407 10:55:16.795111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 10:55:16.795209 ==
3409 10:55:16.795306 DQS Delay:
3410 10:55:16.795409 DQS0 = 0, DQS1 = 0
3411 10:55:16.799053 DQM Delay:
3412 10:55:16.799146 DQM0 = 120, DQM1 = 117
3413 10:55:16.801849 DQ Delay:
3414 10:55:16.805515 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3415 10:55:16.808595 DQ4 =122, DQ5 =128, DQ6 =130, DQ7 =120
3416 10:55:16.812242 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3417 10:55:16.815434 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3418 10:55:16.815516
3419 10:55:16.815580
3420 10:55:16.822026 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3421 10:55:16.825711 CH1 RK0: MR19=304, MR18=FE10
3422 10:55:16.832344 CH1_RK0: MR19=0x304, MR18=0xFE10, DQSOSC=403, MR23=63, INC=40, DEC=26
3423 10:55:16.832429
3424 10:55:16.835437 ----->DramcWriteLeveling(PI) begin...
3425 10:55:16.835519 ==
3426 10:55:16.839199 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 10:55:16.842336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 10:55:16.842418 ==
3429 10:55:16.845855 Write leveling (Byte 0): 26 => 26
3430 10:55:16.849074 Write leveling (Byte 1): 28 => 28
3431 10:55:16.852278 DramcWriteLeveling(PI) end<-----
3432 10:55:16.852359
3433 10:55:16.852423 ==
3434 10:55:16.855491 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 10:55:16.862325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 10:55:16.862422 ==
3437 10:55:16.862501 [Gating] SW mode calibration
3438 10:55:16.872296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3439 10:55:16.875453 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3440 10:55:16.879058 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 10:55:16.885506 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 10:55:16.888642 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 10:55:16.892492 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 10:55:16.899082 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 10:55:16.902446 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3446 10:55:16.905784 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 1) (0 1)
3447 10:55:16.911951 0 15 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 1)
3448 10:55:16.915595 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 10:55:16.918678 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 10:55:16.925984 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 10:55:16.929019 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 10:55:16.932311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 10:55:16.938545 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3454 10:55:16.942254 1 0 24 | B1->B0 | 4444 2727 | 0 0 | (0 0) (0 0)
3455 10:55:16.945819 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3456 10:55:16.951925 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 10:55:16.955341 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 10:55:16.958527 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 10:55:16.965453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 10:55:16.968745 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 10:55:16.971899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 10:55:16.975453 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3463 10:55:16.981757 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3464 10:55:16.985463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 10:55:16.988496 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 10:55:16.995055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 10:55:16.998934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:55:17.002211 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:55:17.008640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:55:17.011846 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:55:17.015027 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 10:55:17.021933 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 10:55:17.025208 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 10:55:17.028437 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 10:55:17.035483 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 10:55:17.038685 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 10:55:17.042091 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3478 10:55:17.048251 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3479 10:55:17.051794 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3480 10:55:17.054894 Total UI for P1: 0, mck2ui 16
3481 10:55:17.058301 best dqsien dly found for B1: ( 1, 3, 22)
3482 10:55:17.061906 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 10:55:17.064959 Total UI for P1: 0, mck2ui 16
3484 10:55:17.068424 best dqsien dly found for B0: ( 1, 3, 28)
3485 10:55:17.071866 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3486 10:55:17.075208 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3487 10:55:17.075316
3488 10:55:17.078285 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3489 10:55:17.085137 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3490 10:55:17.085220 [Gating] SW calibration Done
3491 10:55:17.088067 ==
3492 10:55:17.088149 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 10:55:17.094841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 10:55:17.094930 ==
3495 10:55:17.094995 RX Vref Scan: 0
3496 10:55:17.095059
3497 10:55:17.098491 RX Vref 0 -> 0, step: 1
3498 10:55:17.098579
3499 10:55:17.101671 RX Delay -40 -> 252, step: 8
3500 10:55:17.104841 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3501 10:55:17.108112 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3502 10:55:17.111312 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3503 10:55:17.118295 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3504 10:55:17.121563 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3505 10:55:17.124543 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3506 10:55:17.127906 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3507 10:55:17.131126 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3508 10:55:17.138183 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3509 10:55:17.141388 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3510 10:55:17.144479 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3511 10:55:17.147730 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3512 10:55:17.151521 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3513 10:55:17.158258 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3514 10:55:17.161315 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3515 10:55:17.164293 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3516 10:55:17.164362 ==
3517 10:55:17.168051 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 10:55:17.171652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 10:55:17.174615 ==
3520 10:55:17.174703 DQS Delay:
3521 10:55:17.174766 DQS0 = 0, DQS1 = 0
3522 10:55:17.178108 DQM Delay:
3523 10:55:17.178184 DQM0 = 121, DQM1 = 118
3524 10:55:17.181543 DQ Delay:
3525 10:55:17.184612 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3526 10:55:17.187819 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3527 10:55:17.191570 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3528 10:55:17.194564 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3529 10:55:17.194633
3530 10:55:17.194698
3531 10:55:17.194759 ==
3532 10:55:17.198129 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 10:55:17.201164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 10:55:17.201237 ==
3535 10:55:17.201299
3536 10:55:17.201356
3537 10:55:17.204461 TX Vref Scan disable
3538 10:55:17.207645 == TX Byte 0 ==
3539 10:55:17.211579 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3540 10:55:17.214823 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3541 10:55:17.217615 == TX Byte 1 ==
3542 10:55:17.221208 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3543 10:55:17.224488 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3544 10:55:17.224561 ==
3545 10:55:17.227969 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 10:55:17.234382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 10:55:17.234472 ==
3548 10:55:17.244984 TX Vref=22, minBit 9, minWin=25, winSum=420
3549 10:55:17.248187 TX Vref=24, minBit 10, minWin=25, winSum=423
3550 10:55:17.251271 TX Vref=26, minBit 10, minWin=25, winSum=427
3551 10:55:17.254500 TX Vref=28, minBit 9, minWin=26, winSum=433
3552 10:55:17.258576 TX Vref=30, minBit 9, minWin=26, winSum=433
3553 10:55:17.264592 TX Vref=32, minBit 9, minWin=26, winSum=433
3554 10:55:17.268269 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3555 10:55:17.268344
3556 10:55:17.271267 Final TX Range 1 Vref 28
3557 10:55:17.271394
3558 10:55:17.271456 ==
3559 10:55:17.275131 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 10:55:17.278091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 10:55:17.278167 ==
3562 10:55:17.278286
3563 10:55:17.281247
3564 10:55:17.281318 TX Vref Scan disable
3565 10:55:17.285038 == TX Byte 0 ==
3566 10:55:17.287887 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 10:55:17.291572 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 10:55:17.294460 == TX Byte 1 ==
3569 10:55:17.298211 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3570 10:55:17.301465 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3571 10:55:17.301539
3572 10:55:17.304913 [DATLAT]
3573 10:55:17.305009 Freq=1200, CH1 RK1
3574 10:55:17.305098
3575 10:55:17.308019 DATLAT Default: 0xd
3576 10:55:17.308097 0, 0xFFFF, sum = 0
3577 10:55:17.311103 1, 0xFFFF, sum = 0
3578 10:55:17.311240 2, 0xFFFF, sum = 0
3579 10:55:17.314446 3, 0xFFFF, sum = 0
3580 10:55:17.314542 4, 0xFFFF, sum = 0
3581 10:55:17.318342 5, 0xFFFF, sum = 0
3582 10:55:17.318427 6, 0xFFFF, sum = 0
3583 10:55:17.321474 7, 0xFFFF, sum = 0
3584 10:55:17.324682 8, 0xFFFF, sum = 0
3585 10:55:17.324753 9, 0xFFFF, sum = 0
3586 10:55:17.327913 10, 0xFFFF, sum = 0
3587 10:55:17.327982 11, 0xFFFF, sum = 0
3588 10:55:17.331555 12, 0x0, sum = 1
3589 10:55:17.331664 13, 0x0, sum = 2
3590 10:55:17.334573 14, 0x0, sum = 3
3591 10:55:17.334663 15, 0x0, sum = 4
3592 10:55:17.334759 best_step = 13
3593 10:55:17.334845
3594 10:55:17.337803 ==
3595 10:55:17.341130 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 10:55:17.344899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 10:55:17.344973 ==
3598 10:55:17.345061 RX Vref Scan: 0
3599 10:55:17.345167
3600 10:55:17.347912 RX Vref 0 -> 0, step: 1
3601 10:55:17.348014
3602 10:55:17.351300 RX Delay -5 -> 252, step: 4
3603 10:55:17.354571 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3604 10:55:17.358013 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3605 10:55:17.364424 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3606 10:55:17.368195 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3607 10:55:17.371192 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3608 10:55:17.374947 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3609 10:55:17.377959 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3610 10:55:17.384635 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3611 10:55:17.387710 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3612 10:55:17.391094 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3613 10:55:17.394714 iDelay=195, Bit 10, Center 118 (55 ~ 182) 128
3614 10:55:17.397759 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3615 10:55:17.404871 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3616 10:55:17.408039 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3617 10:55:17.411020 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3618 10:55:17.414586 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3619 10:55:17.414662 ==
3620 10:55:17.417802 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 10:55:17.424169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 10:55:17.424248 ==
3623 10:55:17.424312 DQS Delay:
3624 10:55:17.427951 DQS0 = 0, DQS1 = 0
3625 10:55:17.428026 DQM Delay:
3626 10:55:17.431157 DQM0 = 119, DQM1 = 118
3627 10:55:17.431264 DQ Delay:
3628 10:55:17.434335 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3629 10:55:17.438059 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3630 10:55:17.441202 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3631 10:55:17.444522 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3632 10:55:17.444596
3633 10:55:17.444657
3634 10:55:17.454876 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3635 10:55:17.454964 CH1 RK1: MR19=403, MR18=13F0
3636 10:55:17.461274 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3637 10:55:17.464536 [RxdqsGatingPostProcess] freq 1200
3638 10:55:17.471571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3639 10:55:17.474746 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 10:55:17.477757 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 10:55:17.480780 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 10:55:17.484483 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 10:55:17.487548 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 10:55:17.487622 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 10:55:17.491265 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 10:55:17.494243 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 10:55:17.497896 Pre-setting of DQS Precalculation
3648 10:55:17.504327 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3649 10:55:17.510910 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3650 10:55:17.517819 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3651 10:55:17.517900
3652 10:55:17.517964
3653 10:55:17.520420 [Calibration Summary] 2400 Mbps
3654 10:55:17.524130 CH 0, Rank 0
3655 10:55:17.524211 SW Impedance : PASS
3656 10:55:17.527288 DUTY Scan : NO K
3657 10:55:17.527407 ZQ Calibration : PASS
3658 10:55:17.530536 Jitter Meter : NO K
3659 10:55:17.534181 CBT Training : PASS
3660 10:55:17.534261 Write leveling : PASS
3661 10:55:17.537452 RX DQS gating : PASS
3662 10:55:17.541064 RX DQ/DQS(RDDQC) : PASS
3663 10:55:17.541144 TX DQ/DQS : PASS
3664 10:55:17.544227 RX DATLAT : PASS
3665 10:55:17.547419 RX DQ/DQS(Engine): PASS
3666 10:55:17.547499 TX OE : NO K
3667 10:55:17.550603 All Pass.
3668 10:55:17.550673
3669 10:55:17.550734 CH 0, Rank 1
3670 10:55:17.553855 SW Impedance : PASS
3671 10:55:17.553936 DUTY Scan : NO K
3672 10:55:17.557494 ZQ Calibration : PASS
3673 10:55:17.560773 Jitter Meter : NO K
3674 10:55:17.560853 CBT Training : PASS
3675 10:55:17.564056 Write leveling : PASS
3676 10:55:17.567314 RX DQS gating : PASS
3677 10:55:17.567416 RX DQ/DQS(RDDQC) : PASS
3678 10:55:17.571089 TX DQ/DQS : PASS
3679 10:55:17.571170 RX DATLAT : PASS
3680 10:55:17.574437 RX DQ/DQS(Engine): PASS
3681 10:55:17.577563 TX OE : NO K
3682 10:55:17.577643 All Pass.
3683 10:55:17.577707
3684 10:55:17.580745 CH 1, Rank 0
3685 10:55:17.580826 SW Impedance : PASS
3686 10:55:17.583935 DUTY Scan : NO K
3687 10:55:17.584038 ZQ Calibration : PASS
3688 10:55:17.587040 Jitter Meter : NO K
3689 10:55:17.590710 CBT Training : PASS
3690 10:55:17.590791 Write leveling : PASS
3691 10:55:17.593595 RX DQS gating : PASS
3692 10:55:17.596964 RX DQ/DQS(RDDQC) : PASS
3693 10:55:17.597045 TX DQ/DQS : PASS
3694 10:55:17.600361 RX DATLAT : PASS
3695 10:55:17.603607 RX DQ/DQS(Engine): PASS
3696 10:55:17.603689 TX OE : NO K
3697 10:55:17.607171 All Pass.
3698 10:55:17.607252
3699 10:55:17.607356 CH 1, Rank 1
3700 10:55:17.610220 SW Impedance : PASS
3701 10:55:17.610302 DUTY Scan : NO K
3702 10:55:17.613318 ZQ Calibration : PASS
3703 10:55:17.616981 Jitter Meter : NO K
3704 10:55:17.617062 CBT Training : PASS
3705 10:55:17.620201 Write leveling : PASS
3706 10:55:17.623196 RX DQS gating : PASS
3707 10:55:17.623304 RX DQ/DQS(RDDQC) : PASS
3708 10:55:17.626545 TX DQ/DQS : PASS
3709 10:55:17.630219 RX DATLAT : PASS
3710 10:55:17.630300 RX DQ/DQS(Engine): PASS
3711 10:55:17.633372 TX OE : NO K
3712 10:55:17.633454 All Pass.
3713 10:55:17.633519
3714 10:55:17.636442 DramC Write-DBI off
3715 10:55:17.640099 PER_BANK_REFRESH: Hybrid Mode
3716 10:55:17.640180 TX_TRACKING: ON
3717 10:55:17.649760 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3718 10:55:17.652986 [FAST_K] Save calibration result to emmc
3719 10:55:17.656211 dramc_set_vcore_voltage set vcore to 650000
3720 10:55:17.659903 Read voltage for 600, 5
3721 10:55:17.659985 Vio18 = 0
3722 10:55:17.660049 Vcore = 650000
3723 10:55:17.663079 Vdram = 0
3724 10:55:17.663160 Vddq = 0
3725 10:55:17.663225 Vmddr = 0
3726 10:55:17.669606 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3727 10:55:17.672867 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3728 10:55:17.676099 MEM_TYPE=3, freq_sel=19
3729 10:55:17.679451 sv_algorithm_assistance_LP4_1600
3730 10:55:17.683255 ============ PULL DRAM RESETB DOWN ============
3731 10:55:17.686531 ========== PULL DRAM RESETB DOWN end =========
3732 10:55:17.692785 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 10:55:17.696497 ===================================
3734 10:55:17.696595 LPDDR4 DRAM CONFIGURATION
3735 10:55:17.699560 ===================================
3736 10:55:17.702649 EX_ROW_EN[0] = 0x0
3737 10:55:17.706414 EX_ROW_EN[1] = 0x0
3738 10:55:17.706497 LP4Y_EN = 0x0
3739 10:55:17.709507 WORK_FSP = 0x0
3740 10:55:17.709591 WL = 0x2
3741 10:55:17.712671 RL = 0x2
3742 10:55:17.712750 BL = 0x2
3743 10:55:17.716199 RPST = 0x0
3744 10:55:17.716279 RD_PRE = 0x0
3745 10:55:17.719533 WR_PRE = 0x1
3746 10:55:17.719630 WR_PST = 0x0
3747 10:55:17.722620 DBI_WR = 0x0
3748 10:55:17.722688 DBI_RD = 0x0
3749 10:55:17.726193 OTF = 0x1
3750 10:55:17.729445 ===================================
3751 10:55:17.732551 ===================================
3752 10:55:17.732620 ANA top config
3753 10:55:17.736148 ===================================
3754 10:55:17.739520 DLL_ASYNC_EN = 0
3755 10:55:17.742557 ALL_SLAVE_EN = 1
3756 10:55:17.745789 NEW_RANK_MODE = 1
3757 10:55:17.745860 DLL_IDLE_MODE = 1
3758 10:55:17.749037 LP45_APHY_COMB_EN = 1
3759 10:55:17.752823 TX_ODT_DIS = 1
3760 10:55:17.755969 NEW_8X_MODE = 1
3761 10:55:17.759193 ===================================
3762 10:55:17.762413 ===================================
3763 10:55:17.765531 data_rate = 1200
3764 10:55:17.765612 CKR = 1
3765 10:55:17.768891 DQ_P2S_RATIO = 8
3766 10:55:17.772197 ===================================
3767 10:55:17.775890 CA_P2S_RATIO = 8
3768 10:55:17.779077 DQ_CA_OPEN = 0
3769 10:55:17.782386 DQ_SEMI_OPEN = 0
3770 10:55:17.785693 CA_SEMI_OPEN = 0
3771 10:55:17.785792 CA_FULL_RATE = 0
3772 10:55:17.788843 DQ_CKDIV4_EN = 1
3773 10:55:17.792212 CA_CKDIV4_EN = 1
3774 10:55:17.796023 CA_PREDIV_EN = 0
3775 10:55:17.798797 PH8_DLY = 0
3776 10:55:17.802620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3777 10:55:17.802700 DQ_AAMCK_DIV = 4
3778 10:55:17.805766 CA_AAMCK_DIV = 4
3779 10:55:17.808845 CA_ADMCK_DIV = 4
3780 10:55:17.812575 DQ_TRACK_CA_EN = 0
3781 10:55:17.816014 CA_PICK = 600
3782 10:55:17.819018 CA_MCKIO = 600
3783 10:55:17.822234 MCKIO_SEMI = 0
3784 10:55:17.822315 PLL_FREQ = 2288
3785 10:55:17.825822 DQ_UI_PI_RATIO = 32
3786 10:55:17.828917 CA_UI_PI_RATIO = 0
3787 10:55:17.832375 ===================================
3788 10:55:17.835627 ===================================
3789 10:55:17.838726 memory_type:LPDDR4
3790 10:55:17.838807 GP_NUM : 10
3791 10:55:17.842423 SRAM_EN : 1
3792 10:55:17.845515 MD32_EN : 0
3793 10:55:17.849307 ===================================
3794 10:55:17.849388 [ANA_INIT] >>>>>>>>>>>>>>
3795 10:55:17.852421 <<<<<< [CONFIGURE PHASE]: ANA_TX
3796 10:55:17.855621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3797 10:55:17.858931 ===================================
3798 10:55:17.862163 data_rate = 1200,PCW = 0X5800
3799 10:55:17.865256 ===================================
3800 10:55:17.868984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3801 10:55:17.875411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 10:55:17.878698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 10:55:17.885230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3804 10:55:17.889111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3805 10:55:17.892261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3806 10:55:17.892342 [ANA_INIT] flow start
3807 10:55:17.895451 [ANA_INIT] PLL >>>>>>>>
3808 10:55:17.898577 [ANA_INIT] PLL <<<<<<<<
3809 10:55:17.901919 [ANA_INIT] MIDPI >>>>>>>>
3810 10:55:17.902001 [ANA_INIT] MIDPI <<<<<<<<
3811 10:55:17.905349 [ANA_INIT] DLL >>>>>>>>
3812 10:55:17.908549 [ANA_INIT] flow end
3813 10:55:17.912284 ============ LP4 DIFF to SE enter ============
3814 10:55:17.915584 ============ LP4 DIFF to SE exit ============
3815 10:55:17.918665 [ANA_INIT] <<<<<<<<<<<<<
3816 10:55:17.921697 [Flow] Enable top DCM control >>>>>
3817 10:55:17.925234 [Flow] Enable top DCM control <<<<<
3818 10:55:17.929048 Enable DLL master slave shuffle
3819 10:55:17.932167 ==============================================================
3820 10:55:17.935348 Gating Mode config
3821 10:55:17.938290 ==============================================================
3822 10:55:17.941826 Config description:
3823 10:55:17.951758 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3824 10:55:17.958630 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3825 10:55:17.961661 SELPH_MODE 0: By rank 1: By Phase
3826 10:55:17.968665 ==============================================================
3827 10:55:17.971864 GAT_TRACK_EN = 1
3828 10:55:17.975679 RX_GATING_MODE = 2
3829 10:55:17.978707 RX_GATING_TRACK_MODE = 2
3830 10:55:17.981922 SELPH_MODE = 1
3831 10:55:17.982004 PICG_EARLY_EN = 1
3832 10:55:17.985404 VALID_LAT_VALUE = 1
3833 10:55:17.991726 ==============================================================
3834 10:55:17.995601 Enter into Gating configuration >>>>
3835 10:55:17.998724 Exit from Gating configuration <<<<
3836 10:55:18.002002 Enter into DVFS_PRE_config >>>>>
3837 10:55:18.011635 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3838 10:55:18.015266 Exit from DVFS_PRE_config <<<<<
3839 10:55:18.018264 Enter into PICG configuration >>>>
3840 10:55:18.021573 Exit from PICG configuration <<<<
3841 10:55:18.025226 [RX_INPUT] configuration >>>>>
3842 10:55:18.028286 [RX_INPUT] configuration <<<<<
3843 10:55:18.031992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3844 10:55:18.038221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3845 10:55:18.045000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 10:55:18.051803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 10:55:18.058441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 10:55:18.064948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 10:55:18.068215 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3850 10:55:18.071335 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3851 10:55:18.075095 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3852 10:55:18.078291 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3853 10:55:18.084709 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3854 10:55:18.087955 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3855 10:55:18.091188 ===================================
3856 10:55:18.095038 LPDDR4 DRAM CONFIGURATION
3857 10:55:18.098312 ===================================
3858 10:55:18.098394 EX_ROW_EN[0] = 0x0
3859 10:55:18.101475 EX_ROW_EN[1] = 0x0
3860 10:55:18.101572 LP4Y_EN = 0x0
3861 10:55:18.104763 WORK_FSP = 0x0
3862 10:55:18.104844 WL = 0x2
3863 10:55:18.107993 RL = 0x2
3864 10:55:18.108074 BL = 0x2
3865 10:55:18.111155 RPST = 0x0
3866 10:55:18.111236 RD_PRE = 0x0
3867 10:55:18.114450 WR_PRE = 0x1
3868 10:55:18.118390 WR_PST = 0x0
3869 10:55:18.118471 DBI_WR = 0x0
3870 10:55:18.121401 DBI_RD = 0x0
3871 10:55:18.121482 OTF = 0x1
3872 10:55:18.124501 ===================================
3873 10:55:18.128187 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3874 10:55:18.131235 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3875 10:55:18.138036 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 10:55:18.140957 ===================================
3877 10:55:18.144820 LPDDR4 DRAM CONFIGURATION
3878 10:55:18.147927 ===================================
3879 10:55:18.148008 EX_ROW_EN[0] = 0x10
3880 10:55:18.151095 EX_ROW_EN[1] = 0x0
3881 10:55:18.151176 LP4Y_EN = 0x0
3882 10:55:18.154795 WORK_FSP = 0x0
3883 10:55:18.154876 WL = 0x2
3884 10:55:18.157956 RL = 0x2
3885 10:55:18.158055 BL = 0x2
3886 10:55:18.161045 RPST = 0x0
3887 10:55:18.161126 RD_PRE = 0x0
3888 10:55:18.164518 WR_PRE = 0x1
3889 10:55:18.164599 WR_PST = 0x0
3890 10:55:18.168471 DBI_WR = 0x0
3891 10:55:18.168552 DBI_RD = 0x0
3892 10:55:18.171444 OTF = 0x1
3893 10:55:18.174428 ===================================
3894 10:55:18.180943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3895 10:55:18.184763 nWR fixed to 30
3896 10:55:18.188025 [ModeRegInit_LP4] CH0 RK0
3897 10:55:18.188107 [ModeRegInit_LP4] CH0 RK1
3898 10:55:18.191362 [ModeRegInit_LP4] CH1 RK0
3899 10:55:18.194599 [ModeRegInit_LP4] CH1 RK1
3900 10:55:18.194681 match AC timing 17
3901 10:55:18.201094 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3902 10:55:18.204289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3903 10:55:18.208005 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3904 10:55:18.214655 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3905 10:55:18.217719 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3906 10:55:18.217805 ==
3907 10:55:18.220930 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 10:55:18.224118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 10:55:18.224200 ==
3910 10:55:18.230890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 10:55:18.237452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3912 10:55:18.241221 [CA 0] Center 35 (5~66) winsize 62
3913 10:55:18.244174 [CA 1] Center 35 (5~66) winsize 62
3914 10:55:18.247820 [CA 2] Center 33 (3~64) winsize 62
3915 10:55:18.250945 [CA 3] Center 33 (2~64) winsize 63
3916 10:55:18.254060 [CA 4] Center 33 (2~64) winsize 63
3917 10:55:18.257429 [CA 5] Center 32 (2~63) winsize 62
3918 10:55:18.257510
3919 10:55:18.261156 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3920 10:55:18.261237
3921 10:55:18.264339 [CATrainingPosCal] consider 1 rank data
3922 10:55:18.267465 u2DelayCellTimex100 = 270/100 ps
3923 10:55:18.271200 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3924 10:55:18.274275 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3925 10:55:18.277311 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3926 10:55:18.280984 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3927 10:55:18.284081 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3928 10:55:18.287751 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3929 10:55:18.290904
3930 10:55:18.294108 CA PerBit enable=1, Macro0, CA PI delay=32
3931 10:55:18.294189
3932 10:55:18.297312 [CBTSetCACLKResult] CA Dly = 32
3933 10:55:18.297393 CS Dly: 5 (0~36)
3934 10:55:18.297457 ==
3935 10:55:18.301194 Dram Type= 6, Freq= 0, CH_0, rank 1
3936 10:55:18.304454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 10:55:18.304536 ==
3938 10:55:18.310917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 10:55:18.317321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3940 10:55:18.320613 [CA 0] Center 35 (5~66) winsize 62
3941 10:55:18.323858 [CA 1] Center 35 (5~66) winsize 62
3942 10:55:18.327590 [CA 2] Center 34 (3~65) winsize 63
3943 10:55:18.330692 [CA 3] Center 33 (3~64) winsize 62
3944 10:55:18.334495 [CA 4] Center 32 (2~63) winsize 62
3945 10:55:18.337554 [CA 5] Center 32 (2~63) winsize 62
3946 10:55:18.337635
3947 10:55:18.341020 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3948 10:55:18.341101
3949 10:55:18.344026 [CATrainingPosCal] consider 2 rank data
3950 10:55:18.347248 u2DelayCellTimex100 = 270/100 ps
3951 10:55:18.350719 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3952 10:55:18.353868 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3953 10:55:18.357547 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3954 10:55:18.360745 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3955 10:55:18.363873 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3956 10:55:18.370688 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3957 10:55:18.370857
3958 10:55:18.373871 CA PerBit enable=1, Macro0, CA PI delay=32
3959 10:55:18.373953
3960 10:55:18.377604 [CBTSetCACLKResult] CA Dly = 32
3961 10:55:18.377686 CS Dly: 5 (0~36)
3962 10:55:18.377750
3963 10:55:18.380657 ----->DramcWriteLeveling(PI) begin...
3964 10:55:18.380740 ==
3965 10:55:18.383843 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 10:55:18.386935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 10:55:18.390488 ==
3968 10:55:18.390569 Write leveling (Byte 0): 33 => 33
3969 10:55:18.393601 Write leveling (Byte 1): 30 => 30
3970 10:55:18.397472 DramcWriteLeveling(PI) end<-----
3971 10:55:18.397554
3972 10:55:18.397619 ==
3973 10:55:18.400783 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 10:55:18.407140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 10:55:18.407222 ==
3976 10:55:18.410317 [Gating] SW mode calibration
3977 10:55:18.416809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 10:55:18.419969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3979 10:55:18.426938 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 10:55:18.430193 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 10:55:18.433346 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 10:55:18.440498 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
3983 10:55:18.443468 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3984 10:55:18.447100 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 10:55:18.453815 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 10:55:18.456793 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 10:55:18.460384 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:55:18.463313 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 10:55:18.470445 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3990 10:55:18.473648 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3991 10:55:18.476669 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
3992 10:55:18.483713 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 10:55:18.486872 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 10:55:18.490019 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 10:55:18.496760 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:55:18.500362 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:55:18.503644 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 10:55:18.510081 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3999 10:55:18.513255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4000 10:55:18.516529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 10:55:18.523612 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 10:55:18.526747 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:55:18.530025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:55:18.536563 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:55:18.540229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:55:18.543537 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:55:18.550254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:55:18.553450 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:55:18.556688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:55:18.563231 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:55:18.566831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:55:18.569851 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 10:55:18.573107 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 10:55:18.580076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4015 10:55:18.583153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 10:55:18.586907 Total UI for P1: 0, mck2ui 16
4017 10:55:18.589987 best dqsien dly found for B0: ( 0, 13, 12)
4018 10:55:18.593226 Total UI for P1: 0, mck2ui 16
4019 10:55:18.596778 best dqsien dly found for B1: ( 0, 13, 14)
4020 10:55:18.599731 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4021 10:55:18.603478 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4022 10:55:18.603560
4023 10:55:18.606630 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4024 10:55:18.613554 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4025 10:55:18.613636 [Gating] SW calibration Done
4026 10:55:18.613700 ==
4027 10:55:18.616658 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 10:55:18.623242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 10:55:18.623348 ==
4030 10:55:18.623429 RX Vref Scan: 0
4031 10:55:18.623489
4032 10:55:18.626367 RX Vref 0 -> 0, step: 1
4033 10:55:18.626449
4034 10:55:18.629594 RX Delay -230 -> 252, step: 16
4035 10:55:18.633297 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4036 10:55:18.636439 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4037 10:55:18.639581 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4038 10:55:18.646640 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4039 10:55:18.649869 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4040 10:55:18.653055 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4041 10:55:18.656197 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4042 10:55:18.663168 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4043 10:55:18.666389 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4044 10:55:18.669927 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4045 10:55:18.672769 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4046 10:55:18.676310 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4047 10:55:18.683244 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4048 10:55:18.686295 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4049 10:55:18.690025 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4050 10:55:18.693074 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4051 10:55:18.696433 ==
4052 10:55:18.696503 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 10:55:18.703381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 10:55:18.703456 ==
4055 10:55:18.703518 DQS Delay:
4056 10:55:18.706320 DQS0 = 0, DQS1 = 0
4057 10:55:18.706424 DQM Delay:
4058 10:55:18.709905 DQM0 = 52, DQM1 = 46
4059 10:55:18.709982 DQ Delay:
4060 10:55:18.712850 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4061 10:55:18.716808 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4062 10:55:18.720019 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4063 10:55:18.723201 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4064 10:55:18.723295
4065 10:55:18.723411
4066 10:55:18.723469 ==
4067 10:55:18.726376 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 10:55:18.729630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 10:55:18.729701 ==
4070 10:55:18.729762
4071 10:55:18.729829
4072 10:55:18.732791 TX Vref Scan disable
4073 10:55:18.735958 == TX Byte 0 ==
4074 10:55:18.739230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4075 10:55:18.743036 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4076 10:55:18.746307 == TX Byte 1 ==
4077 10:55:18.749492 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4078 10:55:18.752763 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4079 10:55:18.752840 ==
4080 10:55:18.755962 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 10:55:18.759782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 10:55:18.762973 ==
4083 10:55:18.763044
4084 10:55:18.763111
4085 10:55:18.763170 TX Vref Scan disable
4086 10:55:18.766951 == TX Byte 0 ==
4087 10:55:18.770046 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4088 10:55:18.773114 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4089 10:55:18.776758 == TX Byte 1 ==
4090 10:55:18.779839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4091 10:55:18.786465 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4092 10:55:18.786547
4093 10:55:18.786612 [DATLAT]
4094 10:55:18.786670 Freq=600, CH0 RK0
4095 10:55:18.786727
4096 10:55:18.790188 DATLAT Default: 0x9
4097 10:55:18.790268 0, 0xFFFF, sum = 0
4098 10:55:18.793323 1, 0xFFFF, sum = 0
4099 10:55:18.793405 2, 0xFFFF, sum = 0
4100 10:55:18.797058 3, 0xFFFF, sum = 0
4101 10:55:18.797140 4, 0xFFFF, sum = 0
4102 10:55:18.800054 5, 0xFFFF, sum = 0
4103 10:55:18.803243 6, 0xFFFF, sum = 0
4104 10:55:18.803384 7, 0xFFFF, sum = 0
4105 10:55:18.803451 8, 0x0, sum = 1
4106 10:55:18.806550 9, 0x0, sum = 2
4107 10:55:18.806631 10, 0x0, sum = 3
4108 10:55:18.810212 11, 0x0, sum = 4
4109 10:55:18.810294 best_step = 9
4110 10:55:18.810358
4111 10:55:18.810417 ==
4112 10:55:18.813443 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 10:55:18.820177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 10:55:18.820258 ==
4115 10:55:18.820323 RX Vref Scan: 1
4116 10:55:18.820383
4117 10:55:18.823267 RX Vref 0 -> 0, step: 1
4118 10:55:18.823393
4119 10:55:18.826607 RX Delay -163 -> 252, step: 8
4120 10:55:18.826674
4121 10:55:18.829800 Set Vref, RX VrefLevel [Byte0]: 55
4122 10:55:18.833712 [Byte1]: 50
4123 10:55:18.833793
4124 10:55:18.836953 Final RX Vref Byte 0 = 55 to rank0
4125 10:55:18.840131 Final RX Vref Byte 1 = 50 to rank0
4126 10:55:18.843230 Final RX Vref Byte 0 = 55 to rank1
4127 10:55:18.846578 Final RX Vref Byte 1 = 50 to rank1==
4128 10:55:18.850360 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 10:55:18.853517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 10:55:18.853598 ==
4131 10:55:18.856803 DQS Delay:
4132 10:55:18.856883 DQS0 = 0, DQS1 = 0
4133 10:55:18.856947 DQM Delay:
4134 10:55:18.860012 DQM0 = 52, DQM1 = 46
4135 10:55:18.860093 DQ Delay:
4136 10:55:18.863273 DQ0 =48, DQ1 =56, DQ2 =48, DQ3 =48
4137 10:55:18.866518 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4138 10:55:18.869756 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4139 10:55:18.873604 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4140 10:55:18.873688
4141 10:55:18.873752
4142 10:55:18.883442 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4143 10:55:18.883525 CH0 RK0: MR19=808, MR18=6D60
4144 10:55:18.889684 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4145 10:55:18.889765
4146 10:55:18.893258 ----->DramcWriteLeveling(PI) begin...
4147 10:55:18.896447 ==
4148 10:55:18.896545 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 10:55:18.903201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 10:55:18.903282 ==
4151 10:55:18.906199 Write leveling (Byte 0): 35 => 35
4152 10:55:18.909951 Write leveling (Byte 1): 30 => 30
4153 10:55:18.913135 DramcWriteLeveling(PI) end<-----
4154 10:55:18.913242
4155 10:55:18.913333 ==
4156 10:55:18.916299 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 10:55:18.920004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 10:55:18.920087 ==
4159 10:55:18.923070 [Gating] SW mode calibration
4160 10:55:18.929679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4161 10:55:18.932888 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4162 10:55:18.939869 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 10:55:18.943131 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 10:55:18.946333 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 10:55:18.952808 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
4166 10:55:18.956558 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
4167 10:55:18.959879 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 10:55:18.966453 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 10:55:18.969724 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 10:55:18.973007 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 10:55:18.979230 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 10:55:18.983166 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 10:55:18.986170 0 10 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4174 10:55:18.993013 0 10 16 | B1->B0 | 4242 4141 | 0 0 | (0 0) (0 0)
4175 10:55:18.996166 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 10:55:18.999225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 10:55:19.006096 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 10:55:19.009178 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 10:55:19.012946 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 10:55:19.019166 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 10:55:19.022869 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4182 10:55:19.026009 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 10:55:19.032477 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 10:55:19.036365 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 10:55:19.039588 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 10:55:19.045965 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:55:19.049241 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:55:19.052352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:55:19.056068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:55:19.062503 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:55:19.065803 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 10:55:19.069126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 10:55:19.075677 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 10:55:19.078948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 10:55:19.082249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 10:55:19.089309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 10:55:19.092277 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 10:55:19.099091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4199 10:55:19.099200 Total UI for P1: 0, mck2ui 16
4200 10:55:19.102113 best dqsien dly found for B0: ( 0, 13, 14)
4201 10:55:19.108937 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 10:55:19.112064 Total UI for P1: 0, mck2ui 16
4203 10:55:19.115037 best dqsien dly found for B1: ( 0, 13, 16)
4204 10:55:19.118886 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4205 10:55:19.121944 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4206 10:55:19.122041
4207 10:55:19.125136 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4208 10:55:19.128348 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4209 10:55:19.131500 [Gating] SW calibration Done
4210 10:55:19.131595 ==
4211 10:55:19.135077 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 10:55:19.138137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 10:55:19.141721 ==
4214 10:55:19.141803 RX Vref Scan: 0
4215 10:55:19.141869
4216 10:55:19.144927 RX Vref 0 -> 0, step: 1
4217 10:55:19.145009
4218 10:55:19.148228 RX Delay -230 -> 252, step: 16
4219 10:55:19.151383 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4220 10:55:19.154597 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4221 10:55:19.158497 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4222 10:55:19.161649 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4223 10:55:19.168000 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4224 10:55:19.171258 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4225 10:55:19.174497 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4226 10:55:19.178384 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4227 10:55:19.181665 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4228 10:55:19.188061 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4229 10:55:19.191210 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4230 10:55:19.194413 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4231 10:55:19.198357 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4232 10:55:19.204315 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4233 10:55:19.207957 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4234 10:55:19.210942 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4235 10:55:19.211024 ==
4236 10:55:19.214548 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 10:55:19.217757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 10:55:19.217840 ==
4239 10:55:19.221517 DQS Delay:
4240 10:55:19.221599 DQS0 = 0, DQS1 = 0
4241 10:55:19.224542 DQM Delay:
4242 10:55:19.224624 DQM0 = 60, DQM1 = 48
4243 10:55:19.224689 DQ Delay:
4244 10:55:19.227666 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4245 10:55:19.230965 DQ4 =65, DQ5 =57, DQ6 =65, DQ7 =65
4246 10:55:19.234023 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4247 10:55:19.237471 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4248 10:55:19.237568
4249 10:55:19.237659
4250 10:55:19.241211 ==
4251 10:55:19.241309 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 10:55:19.247877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 10:55:19.247952 ==
4254 10:55:19.248013
4255 10:55:19.248071
4256 10:55:19.251083 TX Vref Scan disable
4257 10:55:19.251182 == TX Byte 0 ==
4258 10:55:19.254289 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4259 10:55:19.260745 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4260 10:55:19.260817 == TX Byte 1 ==
4261 10:55:19.264065 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4262 10:55:19.271096 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4263 10:55:19.271192 ==
4264 10:55:19.274292 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 10:55:19.277563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 10:55:19.277653 ==
4267 10:55:19.277714
4268 10:55:19.277774
4269 10:55:19.280710 TX Vref Scan disable
4270 10:55:19.283880 == TX Byte 0 ==
4271 10:55:19.287862 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4272 10:55:19.290887 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4273 10:55:19.294147 == TX Byte 1 ==
4274 10:55:19.297415 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4275 10:55:19.300641 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4276 10:55:19.300736
4277 10:55:19.303754 [DATLAT]
4278 10:55:19.303855 Freq=600, CH0 RK1
4279 10:55:19.303945
4280 10:55:19.307531 DATLAT Default: 0x9
4281 10:55:19.307614 0, 0xFFFF, sum = 0
4282 10:55:19.310557 1, 0xFFFF, sum = 0
4283 10:55:19.310640 2, 0xFFFF, sum = 0
4284 10:55:19.314331 3, 0xFFFF, sum = 0
4285 10:55:19.314445 4, 0xFFFF, sum = 0
4286 10:55:19.317555 5, 0xFFFF, sum = 0
4287 10:55:19.317658 6, 0xFFFF, sum = 0
4288 10:55:19.320462 7, 0xFFFF, sum = 0
4289 10:55:19.320542 8, 0x0, sum = 1
4290 10:55:19.324249 9, 0x0, sum = 2
4291 10:55:19.324348 10, 0x0, sum = 3
4292 10:55:19.327477 11, 0x0, sum = 4
4293 10:55:19.327583 best_step = 9
4294 10:55:19.327678
4295 10:55:19.327764 ==
4296 10:55:19.330449 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 10:55:19.334169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 10:55:19.337445 ==
4299 10:55:19.337543 RX Vref Scan: 0
4300 10:55:19.337635
4301 10:55:19.340796 RX Vref 0 -> 0, step: 1
4302 10:55:19.340894
4303 10:55:19.343709 RX Delay -163 -> 252, step: 8
4304 10:55:19.347226 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4305 10:55:19.350702 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4306 10:55:19.357718 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4307 10:55:19.360609 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4308 10:55:19.364309 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4309 10:55:19.367356 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4310 10:55:19.370553 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4311 10:55:19.373836 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4312 10:55:19.380372 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4313 10:55:19.383621 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4314 10:55:19.387456 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4315 10:55:19.390726 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4316 10:55:19.397242 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4317 10:55:19.400408 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4318 10:55:19.403671 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4319 10:55:19.406846 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4320 10:55:19.406944 ==
4321 10:55:19.410240 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 10:55:19.417245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 10:55:19.417327 ==
4324 10:55:19.417392 DQS Delay:
4325 10:55:19.417452 DQS0 = 0, DQS1 = 0
4326 10:55:19.420271 DQM Delay:
4327 10:55:19.420338 DQM0 = 53, DQM1 = 47
4328 10:55:19.423883 DQ Delay:
4329 10:55:19.426924 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4330 10:55:19.430030 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =64
4331 10:55:19.433678 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4332 10:55:19.436549 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4333 10:55:19.436629
4334 10:55:19.436691
4335 10:55:19.443490 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4336 10:55:19.446715 CH0 RK1: MR19=808, MR18=6323
4337 10:55:19.453515 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4338 10:55:19.456885 [RxdqsGatingPostProcess] freq 600
4339 10:55:19.460110 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4340 10:55:19.463159 Pre-setting of DQS Precalculation
4341 10:55:19.469813 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4342 10:55:19.469943 ==
4343 10:55:19.473220 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 10:55:19.476653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 10:55:19.476732 ==
4346 10:55:19.483112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4347 10:55:19.487133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4348 10:55:19.490875 [CA 0] Center 35 (5~66) winsize 62
4349 10:55:19.494081 [CA 1] Center 35 (5~66) winsize 62
4350 10:55:19.497835 [CA 2] Center 34 (4~65) winsize 62
4351 10:55:19.501127 [CA 3] Center 34 (4~65) winsize 62
4352 10:55:19.504384 [CA 4] Center 34 (4~65) winsize 62
4353 10:55:19.507503 [CA 5] Center 33 (3~64) winsize 62
4354 10:55:19.507581
4355 10:55:19.510714 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4356 10:55:19.510815
4357 10:55:19.513905 [CATrainingPosCal] consider 1 rank data
4358 10:55:19.517869 u2DelayCellTimex100 = 270/100 ps
4359 10:55:19.520817 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4360 10:55:19.524352 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4361 10:55:19.530814 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 10:55:19.534434 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 10:55:19.537564 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 10:55:19.540636 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4365 10:55:19.540730
4366 10:55:19.544234 CA PerBit enable=1, Macro0, CA PI delay=33
4367 10:55:19.544315
4368 10:55:19.547220 [CBTSetCACLKResult] CA Dly = 33
4369 10:55:19.547349 CS Dly: 5 (0~36)
4370 10:55:19.550557 ==
4371 10:55:19.554273 Dram Type= 6, Freq= 0, CH_1, rank 1
4372 10:55:19.557521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 10:55:19.557601 ==
4374 10:55:19.560595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 10:55:19.567561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 10:55:19.571168 [CA 0] Center 36 (5~67) winsize 63
4377 10:55:19.574724 [CA 1] Center 36 (5~67) winsize 63
4378 10:55:19.577890 [CA 2] Center 35 (4~66) winsize 63
4379 10:55:19.580830 [CA 3] Center 34 (4~65) winsize 62
4380 10:55:19.584665 [CA 4] Center 35 (4~66) winsize 63
4381 10:55:19.587853 [CA 5] Center 34 (3~65) winsize 63
4382 10:55:19.587929
4383 10:55:19.591189 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 10:55:19.591283
4385 10:55:19.594457 [CATrainingPosCal] consider 2 rank data
4386 10:55:19.597645 u2DelayCellTimex100 = 270/100 ps
4387 10:55:19.600845 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4388 10:55:19.607894 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 10:55:19.611106 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 10:55:19.614411 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 10:55:19.617552 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 10:55:19.620849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 10:55:19.620921
4394 10:55:19.624009 CA PerBit enable=1, Macro0, CA PI delay=33
4395 10:55:19.624079
4396 10:55:19.627748 [CBTSetCACLKResult] CA Dly = 33
4397 10:55:19.627817 CS Dly: 6 (0~38)
4398 10:55:19.630789
4399 10:55:19.633995 ----->DramcWriteLeveling(PI) begin...
4400 10:55:19.634067 ==
4401 10:55:19.637790 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 10:55:19.640555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 10:55:19.640630 ==
4404 10:55:19.644200 Write leveling (Byte 0): 28 => 28
4405 10:55:19.647360 Write leveling (Byte 1): 32 => 32
4406 10:55:19.650420 DramcWriteLeveling(PI) end<-----
4407 10:55:19.650494
4408 10:55:19.650555 ==
4409 10:55:19.653990 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 10:55:19.657126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 10:55:19.657195 ==
4412 10:55:19.660375 [Gating] SW mode calibration
4413 10:55:19.667412 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4414 10:55:19.674023 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4415 10:55:19.676868 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 10:55:19.680368 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 10:55:19.686879 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 10:55:19.690537 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 0) (0 1)
4419 10:55:19.693894 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 10:55:19.700365 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 10:55:19.703608 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 10:55:19.706709 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 10:55:19.713645 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 10:55:19.716960 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 10:55:19.720162 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 10:55:19.723351 0 10 12 | B1->B0 | 3838 3838 | 0 0 | (0 0) (0 0)
4427 10:55:19.730353 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 10:55:19.733353 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 10:55:19.737180 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 10:55:19.743508 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 10:55:19.747005 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 10:55:19.749907 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 10:55:19.756805 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 10:55:19.760397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4435 10:55:19.763414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 10:55:19.770447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 10:55:19.773070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 10:55:19.776405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:55:19.783558 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:55:19.786590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:55:19.790169 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:55:19.796810 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:55:19.799627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:55:19.803368 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:55:19.809793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 10:55:19.812906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 10:55:19.816773 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 10:55:19.823257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 10:55:19.826503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 10:55:19.829746 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4451 10:55:19.836081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 10:55:19.836163 Total UI for P1: 0, mck2ui 16
4453 10:55:19.843120 best dqsien dly found for B0: ( 0, 13, 12)
4454 10:55:19.843217 Total UI for P1: 0, mck2ui 16
4455 10:55:19.849456 best dqsien dly found for B1: ( 0, 13, 12)
4456 10:55:19.853356 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4457 10:55:19.856436 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4458 10:55:19.856547
4459 10:55:19.859951 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4460 10:55:19.862959 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4461 10:55:19.866551 [Gating] SW calibration Done
4462 10:55:19.866632 ==
4463 10:55:19.869705 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 10:55:19.872806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 10:55:19.872888 ==
4466 10:55:19.876632 RX Vref Scan: 0
4467 10:55:19.876756
4468 10:55:19.876849 RX Vref 0 -> 0, step: 1
4469 10:55:19.876931
4470 10:55:19.879973 RX Delay -230 -> 252, step: 16
4471 10:55:19.886045 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4472 10:55:19.889219 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4473 10:55:19.892523 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4474 10:55:19.896102 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4475 10:55:19.899202 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4476 10:55:19.905948 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4477 10:55:19.909243 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4478 10:55:19.912501 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4479 10:55:19.916176 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4480 10:55:19.922412 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4481 10:55:19.925725 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4482 10:55:19.929517 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4483 10:55:19.932804 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4484 10:55:19.939207 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4485 10:55:19.942251 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4486 10:55:19.946138 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4487 10:55:19.946212 ==
4488 10:55:19.949372 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 10:55:19.952553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 10:55:19.952636 ==
4491 10:55:19.955618 DQS Delay:
4492 10:55:19.955700 DQS0 = 0, DQS1 = 0
4493 10:55:19.958839 DQM Delay:
4494 10:55:19.958921 DQM0 = 49, DQM1 = 46
4495 10:55:19.958986 DQ Delay:
4496 10:55:19.962652 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4497 10:55:19.965807 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4498 10:55:19.968987 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4499 10:55:19.972647 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4500 10:55:19.972728
4501 10:55:19.972794
4502 10:55:19.975534 ==
4503 10:55:19.979159 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 10:55:19.982431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 10:55:19.982503 ==
4506 10:55:19.982565
4507 10:55:19.982626
4508 10:55:19.985527 TX Vref Scan disable
4509 10:55:19.985627 == TX Byte 0 ==
4510 10:55:19.992017 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 10:55:19.995449 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 10:55:19.995528 == TX Byte 1 ==
4513 10:55:20.002252 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4514 10:55:20.005279 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4515 10:55:20.005355 ==
4516 10:55:20.008378 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 10:55:20.012231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 10:55:20.012308 ==
4519 10:55:20.012374
4520 10:55:20.012434
4521 10:55:20.015619 TX Vref Scan disable
4522 10:55:20.018680 == TX Byte 0 ==
4523 10:55:20.021847 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 10:55:20.025789 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 10:55:20.028428 == TX Byte 1 ==
4526 10:55:20.032320 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4527 10:55:20.035480 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4528 10:55:20.035551
4529 10:55:20.038681 [DATLAT]
4530 10:55:20.038749 Freq=600, CH1 RK0
4531 10:55:20.038814
4532 10:55:20.042020 DATLAT Default: 0x9
4533 10:55:20.042094 0, 0xFFFF, sum = 0
4534 10:55:20.045218 1, 0xFFFF, sum = 0
4535 10:55:20.045290 2, 0xFFFF, sum = 0
4536 10:55:20.048935 3, 0xFFFF, sum = 0
4537 10:55:20.049007 4, 0xFFFF, sum = 0
4538 10:55:20.052104 5, 0xFFFF, sum = 0
4539 10:55:20.052174 6, 0xFFFF, sum = 0
4540 10:55:20.055222 7, 0xFFFF, sum = 0
4541 10:55:20.055330 8, 0x0, sum = 1
4542 10:55:20.058279 9, 0x0, sum = 2
4543 10:55:20.058367 10, 0x0, sum = 3
4544 10:55:20.062127 11, 0x0, sum = 4
4545 10:55:20.062203 best_step = 9
4546 10:55:20.062265
4547 10:55:20.062323 ==
4548 10:55:20.065251 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 10:55:20.068556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 10:55:20.071842 ==
4551 10:55:20.071914 RX Vref Scan: 1
4552 10:55:20.071975
4553 10:55:20.075627 RX Vref 0 -> 0, step: 1
4554 10:55:20.075697
4555 10:55:20.078577 RX Delay -163 -> 252, step: 8
4556 10:55:20.078645
4557 10:55:20.082475 Set Vref, RX VrefLevel [Byte0]: 55
4558 10:55:20.085373 [Byte1]: 52
4559 10:55:20.085473
4560 10:55:20.088420 Final RX Vref Byte 0 = 55 to rank0
4561 10:55:20.091936 Final RX Vref Byte 1 = 52 to rank0
4562 10:55:20.094873 Final RX Vref Byte 0 = 55 to rank1
4563 10:55:20.098611 Final RX Vref Byte 1 = 52 to rank1==
4564 10:55:20.101551 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 10:55:20.105434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 10:55:20.105509 ==
4567 10:55:20.105572 DQS Delay:
4568 10:55:20.108592 DQS0 = 0, DQS1 = 0
4569 10:55:20.108706 DQM Delay:
4570 10:55:20.111740 DQM0 = 47, DQM1 = 45
4571 10:55:20.111845 DQ Delay:
4572 10:55:20.115311 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4573 10:55:20.118295 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4574 10:55:20.121637 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4575 10:55:20.124846 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4576 10:55:20.124932
4577 10:55:20.124994
4578 10:55:20.135011 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4579 10:55:20.135094 CH1 RK0: MR19=808, MR18=466C
4580 10:55:20.142072 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4581 10:55:20.142150
4582 10:55:20.145293 ----->DramcWriteLeveling(PI) begin...
4583 10:55:20.145364 ==
4584 10:55:20.148421 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 10:55:20.154907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 10:55:20.154981 ==
4587 10:55:20.158147 Write leveling (Byte 0): 30 => 30
4588 10:55:20.161878 Write leveling (Byte 1): 32 => 32
4589 10:55:20.161945 DramcWriteLeveling(PI) end<-----
4590 10:55:20.162037
4591 10:55:20.165180 ==
4592 10:55:20.168256 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 10:55:20.171477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 10:55:20.171551 ==
4595 10:55:20.175205 [Gating] SW mode calibration
4596 10:55:20.181881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4597 10:55:20.184910 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4598 10:55:20.191771 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 10:55:20.194856 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 10:55:20.198595 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 10:55:20.204843 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (1 1) (0 0)
4602 10:55:20.208372 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 10:55:20.211534 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 10:55:20.218255 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 10:55:20.221953 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 10:55:20.225142 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 10:55:20.231508 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 10:55:20.234726 0 10 8 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4609 10:55:20.238671 0 10 12 | B1->B0 | 3737 3535 | 0 1 | (0 0) (0 0)
4610 10:55:20.241808 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 10:55:20.248183 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 10:55:20.251453 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 10:55:20.255055 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 10:55:20.261589 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 10:55:20.264657 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 10:55:20.268456 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4617 10:55:20.274797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4618 10:55:20.278470 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 10:55:20.281652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 10:55:20.288112 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 10:55:20.291136 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:55:20.294407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:55:20.301419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:55:20.304452 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:55:20.308199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:55:20.314407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:55:20.317968 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 10:55:20.321019 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 10:55:20.327579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 10:55:20.331308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 10:55:20.334269 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 10:55:20.340838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 10:55:20.344591 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 10:55:20.347742 Total UI for P1: 0, mck2ui 16
4635 10:55:20.350906 best dqsien dly found for B0: ( 0, 13, 10)
4636 10:55:20.354815 Total UI for P1: 0, mck2ui 16
4637 10:55:20.357991 best dqsien dly found for B1: ( 0, 13, 10)
4638 10:55:20.361200 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4639 10:55:20.364417 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4640 10:55:20.364530
4641 10:55:20.367622 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4642 10:55:20.371272 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4643 10:55:20.374516 [Gating] SW calibration Done
4644 10:55:20.374596 ==
4645 10:55:20.377677 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 10:55:20.381260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 10:55:20.381373 ==
4648 10:55:20.384659 RX Vref Scan: 0
4649 10:55:20.384773
4650 10:55:20.387866 RX Vref 0 -> 0, step: 1
4651 10:55:20.387978
4652 10:55:20.391081 RX Delay -230 -> 252, step: 16
4653 10:55:20.394228 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4654 10:55:20.397938 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4655 10:55:20.401163 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4656 10:55:20.404310 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4657 10:55:20.411214 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4658 10:55:20.414551 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4659 10:55:20.417570 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4660 10:55:20.420586 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4661 10:55:20.427557 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4662 10:55:20.430627 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4663 10:55:20.434223 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4664 10:55:20.437185 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4665 10:55:20.443812 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4666 10:55:20.447503 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4667 10:55:20.450851 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4668 10:55:20.454000 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4669 10:55:20.454110 ==
4670 10:55:20.457227 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 10:55:20.464186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 10:55:20.464297 ==
4673 10:55:20.464390 DQS Delay:
4674 10:55:20.467442 DQS0 = 0, DQS1 = 0
4675 10:55:20.467515 DQM Delay:
4676 10:55:20.467576 DQM0 = 50, DQM1 = 48
4677 10:55:20.470640 DQ Delay:
4678 10:55:20.473768 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4679 10:55:20.477100 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4680 10:55:20.480328 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4681 10:55:20.484094 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4682 10:55:20.484198
4683 10:55:20.484270
4684 10:55:20.484338 ==
4685 10:55:20.487095 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 10:55:20.490399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 10:55:20.490472 ==
4688 10:55:20.490535
4689 10:55:20.490602
4690 10:55:20.494332 TX Vref Scan disable
4691 10:55:20.494418 == TX Byte 0 ==
4692 10:55:20.500366 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4693 10:55:20.504015 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4694 10:55:20.504092 == TX Byte 1 ==
4695 10:55:20.510440 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4696 10:55:20.513747 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4697 10:55:20.513826 ==
4698 10:55:20.517448 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 10:55:20.520577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 10:55:20.520678 ==
4701 10:55:20.520747
4702 10:55:20.520820
4703 10:55:20.524304 TX Vref Scan disable
4704 10:55:20.527479 == TX Byte 0 ==
4705 10:55:20.530557 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 10:55:20.533859 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 10:55:20.537615 == TX Byte 1 ==
4708 10:55:20.540603 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4709 10:55:20.544057 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4710 10:55:20.547229
4711 10:55:20.547377 [DATLAT]
4712 10:55:20.547486 Freq=600, CH1 RK1
4713 10:55:20.547575
4714 10:55:20.550388 DATLAT Default: 0x9
4715 10:55:20.550490 0, 0xFFFF, sum = 0
4716 10:55:20.554044 1, 0xFFFF, sum = 0
4717 10:55:20.554163 2, 0xFFFF, sum = 0
4718 10:55:20.557017 3, 0xFFFF, sum = 0
4719 10:55:20.557144 4, 0xFFFF, sum = 0
4720 10:55:20.560393 5, 0xFFFF, sum = 0
4721 10:55:20.560478 6, 0xFFFF, sum = 0
4722 10:55:20.563480 7, 0xFFFF, sum = 0
4723 10:55:20.563554 8, 0x0, sum = 1
4724 10:55:20.566644 9, 0x0, sum = 2
4725 10:55:20.566737 10, 0x0, sum = 3
4726 10:55:20.570546 11, 0x0, sum = 4
4727 10:55:20.570627 best_step = 9
4728 10:55:20.570689
4729 10:55:20.570746 ==
4730 10:55:20.573650 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 10:55:20.579997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 10:55:20.580085 ==
4733 10:55:20.580156 RX Vref Scan: 0
4734 10:55:20.580216
4735 10:55:20.583755 RX Vref 0 -> 0, step: 1
4736 10:55:20.583837
4737 10:55:20.586896 RX Delay -163 -> 252, step: 8
4738 10:55:20.590073 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4739 10:55:20.597170 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4740 10:55:20.600392 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4741 10:55:20.603490 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4742 10:55:20.606477 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4743 10:55:20.609714 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4744 10:55:20.616791 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4745 10:55:20.619956 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4746 10:55:20.623187 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4747 10:55:20.626693 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4748 10:55:20.629828 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4749 10:55:20.636116 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4750 10:55:20.639934 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4751 10:55:20.643089 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4752 10:55:20.646344 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4753 10:55:20.653137 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4754 10:55:20.653216 ==
4755 10:55:20.656060 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 10:55:20.659993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 10:55:20.660080 ==
4758 10:55:20.660146 DQS Delay:
4759 10:55:20.662904 DQS0 = 0, DQS1 = 0
4760 10:55:20.662989 DQM Delay:
4761 10:55:20.665993 DQM0 = 49, DQM1 = 46
4762 10:55:20.666096 DQ Delay:
4763 10:55:20.669183 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4764 10:55:20.672511 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4765 10:55:20.675858 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4766 10:55:20.679552 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4767 10:55:20.679649
4768 10:55:20.679735
4769 10:55:20.685888 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4770 10:55:20.689699 CH1 RK1: MR19=808, MR18=6D25
4771 10:55:20.696023 CH1_RK1: MR19=0x808, MR18=0x6D25, DQSOSC=389, MR23=63, INC=173, DEC=115
4772 10:55:20.699204 [RxdqsGatingPostProcess] freq 600
4773 10:55:20.706074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 10:55:20.709805 Pre-setting of DQS Precalculation
4775 10:55:20.712748 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 10:55:20.719256 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 10:55:20.725852 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 10:55:20.725935
4779 10:55:20.725999
4780 10:55:20.729609 [Calibration Summary] 1200 Mbps
4781 10:55:20.732474 CH 0, Rank 0
4782 10:55:20.732557 SW Impedance : PASS
4783 10:55:20.736156 DUTY Scan : NO K
4784 10:55:20.739359 ZQ Calibration : PASS
4785 10:55:20.739454 Jitter Meter : NO K
4786 10:55:20.742466 CBT Training : PASS
4787 10:55:20.746141 Write leveling : PASS
4788 10:55:20.746223 RX DQS gating : PASS
4789 10:55:20.749492 RX DQ/DQS(RDDQC) : PASS
4790 10:55:20.752754 TX DQ/DQS : PASS
4791 10:55:20.752837 RX DATLAT : PASS
4792 10:55:20.755970 RX DQ/DQS(Engine): PASS
4793 10:55:20.756052 TX OE : NO K
4794 10:55:20.759045 All Pass.
4795 10:55:20.759127
4796 10:55:20.759191 CH 0, Rank 1
4797 10:55:20.762593 SW Impedance : PASS
4798 10:55:20.762676 DUTY Scan : NO K
4799 10:55:20.765692 ZQ Calibration : PASS
4800 10:55:20.769326 Jitter Meter : NO K
4801 10:55:20.769408 CBT Training : PASS
4802 10:55:20.772449 Write leveling : PASS
4803 10:55:20.775658 RX DQS gating : PASS
4804 10:55:20.775740 RX DQ/DQS(RDDQC) : PASS
4805 10:55:20.779311 TX DQ/DQS : PASS
4806 10:55:20.782554 RX DATLAT : PASS
4807 10:55:20.782636 RX DQ/DQS(Engine): PASS
4808 10:55:20.785721 TX OE : NO K
4809 10:55:20.785804 All Pass.
4810 10:55:20.785869
4811 10:55:20.788856 CH 1, Rank 0
4812 10:55:20.788938 SW Impedance : PASS
4813 10:55:20.792632 DUTY Scan : NO K
4814 10:55:20.795804 ZQ Calibration : PASS
4815 10:55:20.795888 Jitter Meter : NO K
4816 10:55:20.798964 CBT Training : PASS
4817 10:55:20.802628 Write leveling : PASS
4818 10:55:20.802711 RX DQS gating : PASS
4819 10:55:20.805966 RX DQ/DQS(RDDQC) : PASS
4820 10:55:20.806103 TX DQ/DQS : PASS
4821 10:55:20.809064 RX DATLAT : PASS
4822 10:55:20.812219 RX DQ/DQS(Engine): PASS
4823 10:55:20.812338 TX OE : NO K
4824 10:55:20.815734 All Pass.
4825 10:55:20.815813
4826 10:55:20.815878 CH 1, Rank 1
4827 10:55:20.818940 SW Impedance : PASS
4828 10:55:20.819011 DUTY Scan : NO K
4829 10:55:20.822155 ZQ Calibration : PASS
4830 10:55:20.825366 Jitter Meter : NO K
4831 10:55:20.825438 CBT Training : PASS
4832 10:55:20.829252 Write leveling : PASS
4833 10:55:20.832383 RX DQS gating : PASS
4834 10:55:20.832454 RX DQ/DQS(RDDQC) : PASS
4835 10:55:20.835480 TX DQ/DQS : PASS
4836 10:55:20.838910 RX DATLAT : PASS
4837 10:55:20.838980 RX DQ/DQS(Engine): PASS
4838 10:55:20.841932 TX OE : NO K
4839 10:55:20.842049 All Pass.
4840 10:55:20.842155
4841 10:55:20.845856 DramC Write-DBI off
4842 10:55:20.848862 PER_BANK_REFRESH: Hybrid Mode
4843 10:55:20.848934 TX_TRACKING: ON
4844 10:55:20.858882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 10:55:20.862133 [FAST_K] Save calibration result to emmc
4846 10:55:20.865173 dramc_set_vcore_voltage set vcore to 662500
4847 10:55:20.868460 Read voltage for 933, 3
4848 10:55:20.868546 Vio18 = 0
4849 10:55:20.868610 Vcore = 662500
4850 10:55:20.872049 Vdram = 0
4851 10:55:20.872121 Vddq = 0
4852 10:55:20.872190 Vmddr = 0
4853 10:55:20.878953 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 10:55:20.881994 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 10:55:20.885182 MEM_TYPE=3, freq_sel=17
4856 10:55:20.888448 sv_algorithm_assistance_LP4_1600
4857 10:55:20.891562 ============ PULL DRAM RESETB DOWN ============
4858 10:55:20.895384 ========== PULL DRAM RESETB DOWN end =========
4859 10:55:20.901570 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 10:55:20.904812 ===================================
4861 10:55:20.904893 LPDDR4 DRAM CONFIGURATION
4862 10:55:20.911888 ===================================
4863 10:55:20.911969 EX_ROW_EN[0] = 0x0
4864 10:55:20.915016 EX_ROW_EN[1] = 0x0
4865 10:55:20.915122 LP4Y_EN = 0x0
4866 10:55:20.918306 WORK_FSP = 0x0
4867 10:55:20.918437 WL = 0x3
4868 10:55:20.921440 RL = 0x3
4869 10:55:20.921527 BL = 0x2
4870 10:55:20.924531 RPST = 0x0
4871 10:55:20.924604 RD_PRE = 0x0
4872 10:55:20.927851 WR_PRE = 0x1
4873 10:55:20.927923 WR_PST = 0x0
4874 10:55:20.931600 DBI_WR = 0x0
4875 10:55:20.931669 DBI_RD = 0x0
4876 10:55:20.934846 OTF = 0x1
4877 10:55:20.938204 ===================================
4878 10:55:20.941398 ===================================
4879 10:55:20.941495 ANA top config
4880 10:55:20.944501 ===================================
4881 10:55:20.948170 DLL_ASYNC_EN = 0
4882 10:55:20.951282 ALL_SLAVE_EN = 1
4883 10:55:20.954486 NEW_RANK_MODE = 1
4884 10:55:20.954567 DLL_IDLE_MODE = 1
4885 10:55:20.958158 LP45_APHY_COMB_EN = 1
4886 10:55:20.961368 TX_ODT_DIS = 1
4887 10:55:20.964661 NEW_8X_MODE = 1
4888 10:55:20.967753 ===================================
4889 10:55:20.971497 ===================================
4890 10:55:20.974618 data_rate = 1866
4891 10:55:20.977668 CKR = 1
4892 10:55:20.977810 DQ_P2S_RATIO = 8
4893 10:55:20.981345 ===================================
4894 10:55:20.984815 CA_P2S_RATIO = 8
4895 10:55:20.987936 DQ_CA_OPEN = 0
4896 10:55:20.991150 DQ_SEMI_OPEN = 0
4897 10:55:20.994285 CA_SEMI_OPEN = 0
4898 10:55:20.994383 CA_FULL_RATE = 0
4899 10:55:20.997536 DQ_CKDIV4_EN = 1
4900 10:55:21.001295 CA_CKDIV4_EN = 1
4901 10:55:21.004406 CA_PREDIV_EN = 0
4902 10:55:21.008051 PH8_DLY = 0
4903 10:55:21.011227 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 10:55:21.011315 DQ_AAMCK_DIV = 4
4905 10:55:21.014441 CA_AAMCK_DIV = 4
4906 10:55:21.017667 CA_ADMCK_DIV = 4
4907 10:55:21.021625 DQ_TRACK_CA_EN = 0
4908 10:55:21.024709 CA_PICK = 933
4909 10:55:21.027902 CA_MCKIO = 933
4910 10:55:21.031140 MCKIO_SEMI = 0
4911 10:55:21.031225 PLL_FREQ = 3732
4912 10:55:21.034363 DQ_UI_PI_RATIO = 32
4913 10:55:21.037613 CA_UI_PI_RATIO = 0
4914 10:55:21.041514 ===================================
4915 10:55:21.044721 ===================================
4916 10:55:21.047828 memory_type:LPDDR4
4917 10:55:21.047927 GP_NUM : 10
4918 10:55:21.051449 SRAM_EN : 1
4919 10:55:21.054522 MD32_EN : 0
4920 10:55:21.057652 ===================================
4921 10:55:21.057782 [ANA_INIT] >>>>>>>>>>>>>>
4922 10:55:21.061434 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 10:55:21.064529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 10:55:21.067702 ===================================
4925 10:55:21.070839 data_rate = 1866,PCW = 0X8f00
4926 10:55:21.074723 ===================================
4927 10:55:21.077969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 10:55:21.084706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 10:55:21.087919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 10:55:21.094680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 10:55:21.097767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 10:55:21.100948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 10:55:21.101049 [ANA_INIT] flow start
4934 10:55:21.104132 [ANA_INIT] PLL >>>>>>>>
4935 10:55:21.107802 [ANA_INIT] PLL <<<<<<<<
4936 10:55:21.110897 [ANA_INIT] MIDPI >>>>>>>>
4937 10:55:21.110995 [ANA_INIT] MIDPI <<<<<<<<
4938 10:55:21.114629 [ANA_INIT] DLL >>>>>>>>
4939 10:55:21.114731 [ANA_INIT] flow end
4940 10:55:21.121014 ============ LP4 DIFF to SE enter ============
4941 10:55:21.124235 ============ LP4 DIFF to SE exit ============
4942 10:55:21.127543 [ANA_INIT] <<<<<<<<<<<<<
4943 10:55:21.131235 [Flow] Enable top DCM control >>>>>
4944 10:55:21.134368 [Flow] Enable top DCM control <<<<<
4945 10:55:21.137739 Enable DLL master slave shuffle
4946 10:55:21.140845 ==============================================================
4947 10:55:21.144057 Gating Mode config
4948 10:55:21.147949 ==============================================================
4949 10:55:21.150984 Config description:
4950 10:55:21.160947 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 10:55:21.167917 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 10:55:21.170884 SELPH_MODE 0: By rank 1: By Phase
4953 10:55:21.177561 ==============================================================
4954 10:55:21.180708 GAT_TRACK_EN = 1
4955 10:55:21.184624 RX_GATING_MODE = 2
4956 10:55:21.187713 RX_GATING_TRACK_MODE = 2
4957 10:55:21.191273 SELPH_MODE = 1
4958 10:55:21.191352 PICG_EARLY_EN = 1
4959 10:55:21.194519 VALID_LAT_VALUE = 1
4960 10:55:21.200649 ==============================================================
4961 10:55:21.204275 Enter into Gating configuration >>>>
4962 10:55:21.207443 Exit from Gating configuration <<<<
4963 10:55:21.210456 Enter into DVFS_PRE_config >>>>>
4964 10:55:21.220502 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 10:55:21.223801 Exit from DVFS_PRE_config <<<<<
4966 10:55:21.227612 Enter into PICG configuration >>>>
4967 10:55:21.230871 Exit from PICG configuration <<<<
4968 10:55:21.233982 [RX_INPUT] configuration >>>>>
4969 10:55:21.237106 [RX_INPUT] configuration <<<<<
4970 10:55:21.240359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 10:55:21.246805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 10:55:21.253404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 10:55:21.260027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 10:55:21.267183 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 10:55:21.273478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 10:55:21.277261 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 10:55:21.280212 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 10:55:21.283966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 10:55:21.290452 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 10:55:21.297008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 10:55:21.297342 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 10:55:21.300229 ===================================
4983 10:55:21.303954 LPDDR4 DRAM CONFIGURATION
4984 10:55:21.307014 ===================================
4985 10:55:21.307137 EX_ROW_EN[0] = 0x0
4986 10:55:21.310115 EX_ROW_EN[1] = 0x0
4987 10:55:21.310251 LP4Y_EN = 0x0
4988 10:55:21.313756 WORK_FSP = 0x0
4989 10:55:21.313859 WL = 0x3
4990 10:55:21.316760 RL = 0x3
4991 10:55:21.316845 BL = 0x2
4992 10:55:21.320399 RPST = 0x0
4993 10:55:21.323509 RD_PRE = 0x0
4994 10:55:21.323594 WR_PRE = 0x1
4995 10:55:21.326728 WR_PST = 0x0
4996 10:55:21.326809 DBI_WR = 0x0
4997 10:55:21.329973 DBI_RD = 0x0
4998 10:55:21.330071 OTF = 0x1
4999 10:55:21.333229 ===================================
5000 10:55:21.336381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 10:55:21.343407 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 10:55:21.346633 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 10:55:21.349843 ===================================
5004 10:55:21.353034 LPDDR4 DRAM CONFIGURATION
5005 10:55:21.356920 ===================================
5006 10:55:21.357024 EX_ROW_EN[0] = 0x10
5007 10:55:21.360154 EX_ROW_EN[1] = 0x0
5008 10:55:21.360229 LP4Y_EN = 0x0
5009 10:55:21.363178 WORK_FSP = 0x0
5010 10:55:21.363276 WL = 0x3
5011 10:55:21.366237 RL = 0x3
5012 10:55:21.366349 BL = 0x2
5013 10:55:21.369635 RPST = 0x0
5014 10:55:21.369719 RD_PRE = 0x0
5015 10:55:21.372813 WR_PRE = 0x1
5016 10:55:21.376700 WR_PST = 0x0
5017 10:55:21.376818 DBI_WR = 0x0
5018 10:55:21.379681 DBI_RD = 0x0
5019 10:55:21.379756 OTF = 0x1
5020 10:55:21.382925 ===================================
5021 10:55:21.389579 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 10:55:21.393459 nWR fixed to 30
5023 10:55:21.396628 [ModeRegInit_LP4] CH0 RK0
5024 10:55:21.396739 [ModeRegInit_LP4] CH0 RK1
5025 10:55:21.399888 [ModeRegInit_LP4] CH1 RK0
5026 10:55:21.402974 [ModeRegInit_LP4] CH1 RK1
5027 10:55:21.403078 match AC timing 9
5028 10:55:21.409835 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 10:55:21.413678 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 10:55:21.416663 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 10:55:21.423364 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 10:55:21.426307 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 10:55:21.426415 ==
5034 10:55:21.429787 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 10:55:21.433522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 10:55:21.433607 ==
5037 10:55:21.439912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 10:55:21.446361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5039 10:55:21.450135 [CA 0] Center 37 (6~68) winsize 63
5040 10:55:21.453370 [CA 1] Center 37 (7~68) winsize 62
5041 10:55:21.456622 [CA 2] Center 34 (4~65) winsize 62
5042 10:55:21.459811 [CA 3] Center 33 (3~64) winsize 62
5043 10:55:21.463034 [CA 4] Center 33 (3~64) winsize 62
5044 10:55:21.466892 [CA 5] Center 32 (2~62) winsize 61
5045 10:55:21.467048
5046 10:55:21.469920 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5047 10:55:21.470002
5048 10:55:21.473171 [CATrainingPosCal] consider 1 rank data
5049 10:55:21.476471 u2DelayCellTimex100 = 270/100 ps
5050 10:55:21.479579 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5051 10:55:21.482807 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5052 10:55:21.486476 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5053 10:55:21.489689 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5054 10:55:21.492871 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5055 10:55:21.496522 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5056 10:55:21.499565
5057 10:55:21.502690 CA PerBit enable=1, Macro0, CA PI delay=32
5058 10:55:21.502765
5059 10:55:21.505860 [CBTSetCACLKResult] CA Dly = 32
5060 10:55:21.505932 CS Dly: 5 (0~36)
5061 10:55:21.505992 ==
5062 10:55:21.509442 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 10:55:21.512617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 10:55:21.512725 ==
5065 10:55:21.519513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 10:55:21.526302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 10:55:21.529838 [CA 0] Center 37 (7~68) winsize 62
5068 10:55:21.532964 [CA 1] Center 37 (7~68) winsize 62
5069 10:55:21.535927 [CA 2] Center 34 (4~65) winsize 62
5070 10:55:21.539623 [CA 3] Center 34 (3~65) winsize 63
5071 10:55:21.542740 [CA 4] Center 33 (3~63) winsize 61
5072 10:55:21.545913 [CA 5] Center 32 (2~62) winsize 61
5073 10:55:21.545995
5074 10:55:21.549606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 10:55:21.549688
5076 10:55:21.552810 [CATrainingPosCal] consider 2 rank data
5077 10:55:21.556152 u2DelayCellTimex100 = 270/100 ps
5078 10:55:21.559527 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 10:55:21.562610 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5080 10:55:21.565839 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 10:55:21.569698 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5082 10:55:21.572836 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5083 10:55:21.579788 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5084 10:55:21.579872
5085 10:55:21.582490 CA PerBit enable=1, Macro0, CA PI delay=32
5086 10:55:21.582571
5087 10:55:21.586198 [CBTSetCACLKResult] CA Dly = 32
5088 10:55:21.586291 CS Dly: 5 (0~37)
5089 10:55:21.586388
5090 10:55:21.589312 ----->DramcWriteLeveling(PI) begin...
5091 10:55:21.589396 ==
5092 10:55:21.592416 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 10:55:21.596245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 10:55:21.599731 ==
5095 10:55:21.599814 Write leveling (Byte 0): 33 => 33
5096 10:55:21.602748 Write leveling (Byte 1): 28 => 28
5097 10:55:21.605868 DramcWriteLeveling(PI) end<-----
5098 10:55:21.605952
5099 10:55:21.606018 ==
5100 10:55:21.609571 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 10:55:21.615667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 10:55:21.615751 ==
5103 10:55:21.619196 [Gating] SW mode calibration
5104 10:55:21.626148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 10:55:21.629174 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 10:55:21.635744 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5107 10:55:21.638815 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 10:55:21.642424 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 10:55:21.649205 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 10:55:21.652470 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 10:55:21.655633 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 10:55:21.662235 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5113 10:55:21.665417 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
5114 10:55:21.668676 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
5115 10:55:21.675085 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 10:55:21.678900 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 10:55:21.681990 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 10:55:21.689009 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 10:55:21.692102 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 10:55:21.695323 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5121 10:55:21.698367 0 15 28 | B1->B0 | 2828 3b3b | 0 0 | (1 1) (0 0)
5122 10:55:21.705545 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5123 10:55:21.708599 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 10:55:21.711869 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 10:55:21.718829 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 10:55:21.721824 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 10:55:21.724965 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 10:55:21.731635 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 10:55:21.735187 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 10:55:21.738226 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 10:55:21.745020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 10:55:21.748241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 10:55:21.751856 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 10:55:21.758527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:55:21.761715 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:55:21.764918 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:55:21.771427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:55:21.774624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:55:21.778463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:55:21.784726 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 10:55:21.788519 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 10:55:21.791653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 10:55:21.798121 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 10:55:21.801254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 10:55:21.805040 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5146 10:55:21.811436 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 10:55:21.811533 Total UI for P1: 0, mck2ui 16
5148 10:55:21.818344 best dqsien dly found for B0: ( 1, 2, 28)
5149 10:55:21.818463 Total UI for P1: 0, mck2ui 16
5150 10:55:21.821259 best dqsien dly found for B1: ( 1, 2, 28)
5151 10:55:21.828021 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5152 10:55:21.831200 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5153 10:55:21.831316
5154 10:55:21.835031 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5155 10:55:21.838112 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5156 10:55:21.841138 [Gating] SW calibration Done
5157 10:55:21.841225 ==
5158 10:55:21.844673 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 10:55:21.848316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 10:55:21.848409 ==
5161 10:55:21.851259 RX Vref Scan: 0
5162 10:55:21.851383
5163 10:55:21.851479 RX Vref 0 -> 0, step: 1
5164 10:55:21.851571
5165 10:55:21.854388 RX Delay -80 -> 252, step: 8
5166 10:55:21.857788 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5167 10:55:21.864478 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5168 10:55:21.867645 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5169 10:55:21.871539 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5170 10:55:21.874665 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5171 10:55:21.877946 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5172 10:55:21.881165 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5173 10:55:21.888102 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5174 10:55:21.891455 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5175 10:55:21.894544 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5176 10:55:21.897929 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5177 10:55:21.901129 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5178 10:55:21.904455 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5179 10:55:21.911173 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5180 10:55:21.914302 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5181 10:55:21.917524 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5182 10:55:21.917633 ==
5183 10:55:21.920803 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 10:55:21.924597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 10:55:21.924697 ==
5186 10:55:21.927623 DQS Delay:
5187 10:55:21.927722 DQS0 = 0, DQS1 = 0
5188 10:55:21.927813 DQM Delay:
5189 10:55:21.931290 DQM0 = 104, DQM1 = 95
5190 10:55:21.931409 DQ Delay:
5191 10:55:21.934620 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5192 10:55:21.937805 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5193 10:55:21.940714 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =91
5194 10:55:21.944606 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5195 10:55:21.947631
5196 10:55:21.947741
5197 10:55:21.947829 ==
5198 10:55:21.950802 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 10:55:21.954440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 10:55:21.954550 ==
5201 10:55:21.954645
5202 10:55:21.954727
5203 10:55:21.957517 TX Vref Scan disable
5204 10:55:21.957612 == TX Byte 0 ==
5205 10:55:21.964330 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5206 10:55:21.967491 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5207 10:55:21.967607 == TX Byte 1 ==
5208 10:55:21.974144 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5209 10:55:21.977370 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5210 10:55:21.977517 ==
5211 10:55:21.980563 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 10:55:21.983781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 10:55:21.983906 ==
5214 10:55:21.984011
5215 10:55:21.984092
5216 10:55:21.987674 TX Vref Scan disable
5217 10:55:21.990658 == TX Byte 0 ==
5218 10:55:21.993851 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5219 10:55:21.997669 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5220 10:55:22.000911 == TX Byte 1 ==
5221 10:55:22.004212 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5222 10:55:22.007458 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5223 10:55:22.007567
5224 10:55:22.010646 [DATLAT]
5225 10:55:22.010746 Freq=933, CH0 RK0
5226 10:55:22.010834
5227 10:55:22.014065 DATLAT Default: 0xd
5228 10:55:22.014167 0, 0xFFFF, sum = 0
5229 10:55:22.017161 1, 0xFFFF, sum = 0
5230 10:55:22.017272 2, 0xFFFF, sum = 0
5231 10:55:22.020864 3, 0xFFFF, sum = 0
5232 10:55:22.020968 4, 0xFFFF, sum = 0
5233 10:55:22.024003 5, 0xFFFF, sum = 0
5234 10:55:22.024104 6, 0xFFFF, sum = 0
5235 10:55:22.027159 7, 0xFFFF, sum = 0
5236 10:55:22.027285 8, 0xFFFF, sum = 0
5237 10:55:22.030500 9, 0xFFFF, sum = 0
5238 10:55:22.030598 10, 0x0, sum = 1
5239 10:55:22.034018 11, 0x0, sum = 2
5240 10:55:22.034111 12, 0x0, sum = 3
5241 10:55:22.037264 13, 0x0, sum = 4
5242 10:55:22.037357 best_step = 11
5243 10:55:22.037424
5244 10:55:22.037485 ==
5245 10:55:22.040518 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 10:55:22.047092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 10:55:22.047213 ==
5248 10:55:22.047284 RX Vref Scan: 1
5249 10:55:22.047367
5250 10:55:22.050735 RX Vref 0 -> 0, step: 1
5251 10:55:22.050826
5252 10:55:22.053566 RX Delay -53 -> 252, step: 4
5253 10:55:22.053655
5254 10:55:22.057267 Set Vref, RX VrefLevel [Byte0]: 55
5255 10:55:22.060373 [Byte1]: 50
5256 10:55:22.060470
5257 10:55:22.063819 Final RX Vref Byte 0 = 55 to rank0
5258 10:55:22.066756 Final RX Vref Byte 1 = 50 to rank0
5259 10:55:22.070422 Final RX Vref Byte 0 = 55 to rank1
5260 10:55:22.073452 Final RX Vref Byte 1 = 50 to rank1==
5261 10:55:22.076853 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 10:55:22.080460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 10:55:22.080580 ==
5264 10:55:22.083611 DQS Delay:
5265 10:55:22.083707 DQS0 = 0, DQS1 = 0
5266 10:55:22.083775 DQM Delay:
5267 10:55:22.086868 DQM0 = 104, DQM1 = 96
5268 10:55:22.086973 DQ Delay:
5269 10:55:22.090759 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5270 10:55:22.093884 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5271 10:55:22.096863 DQ8 =84, DQ9 =84, DQ10 =98, DQ11 =90
5272 10:55:22.103910 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =104
5273 10:55:22.104032
5274 10:55:22.104099
5275 10:55:22.110393 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5276 10:55:22.113625 CH0 RK0: MR19=505, MR18=332B
5277 10:55:22.120627 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5278 10:55:22.120762
5279 10:55:22.123671 ----->DramcWriteLeveling(PI) begin...
5280 10:55:22.123764 ==
5281 10:55:22.126850 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 10:55:22.130000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 10:55:22.130092 ==
5284 10:55:22.133214 Write leveling (Byte 0): 33 => 33
5285 10:55:22.136490 Write leveling (Byte 1): 30 => 30
5286 10:55:22.140114 DramcWriteLeveling(PI) end<-----
5287 10:55:22.140217
5288 10:55:22.140282 ==
5289 10:55:22.143206 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 10:55:22.146454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 10:55:22.146545 ==
5292 10:55:22.149648 [Gating] SW mode calibration
5293 10:55:22.156676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5294 10:55:22.163232 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5295 10:55:22.166724 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5296 10:55:22.169893 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 10:55:22.176842 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 10:55:22.179896 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 10:55:22.183503 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 10:55:22.189821 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 10:55:22.193080 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5302 10:55:22.196856 0 14 28 | B1->B0 | 2a2a 2929 | 1 0 | (1 1) (1 0)
5303 10:55:22.203526 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (1 0)
5304 10:55:22.206748 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 10:55:22.209987 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 10:55:22.216493 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 10:55:22.219771 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 10:55:22.223151 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 10:55:22.230175 0 15 24 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5310 10:55:22.233120 0 15 28 | B1->B0 | 3a3a 3737 | 1 0 | (0 0) (1 1)
5311 10:55:22.236446 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5312 10:55:22.242728 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 10:55:22.246296 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 10:55:22.249564 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 10:55:22.256160 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 10:55:22.260000 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 10:55:22.263213 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 10:55:22.269825 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5319 10:55:22.272784 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 10:55:22.276246 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 10:55:22.282789 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 10:55:22.286418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 10:55:22.289411 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 10:55:22.296075 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:55:22.299769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:55:22.302887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:55:22.309121 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:55:22.312567 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:55:22.315708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:55:22.322851 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 10:55:22.326127 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 10:55:22.329406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 10:55:22.332577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 10:55:22.339533 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5335 10:55:22.342550 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 10:55:22.345885 Total UI for P1: 0, mck2ui 16
5337 10:55:22.349109 best dqsien dly found for B0: ( 1, 2, 28)
5338 10:55:22.352720 Total UI for P1: 0, mck2ui 16
5339 10:55:22.355791 best dqsien dly found for B1: ( 1, 2, 28)
5340 10:55:22.359641 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5341 10:55:22.362751 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5342 10:55:22.362877
5343 10:55:22.366115 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5344 10:55:22.369442 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5345 10:55:22.372522 [Gating] SW calibration Done
5346 10:55:22.372664 ==
5347 10:55:22.375596 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 10:55:22.382410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 10:55:22.382543 ==
5350 10:55:22.382614 RX Vref Scan: 0
5351 10:55:22.382676
5352 10:55:22.385946 RX Vref 0 -> 0, step: 1
5353 10:55:22.386039
5354 10:55:22.389016 RX Delay -80 -> 252, step: 8
5355 10:55:22.392681 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5356 10:55:22.395665 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5357 10:55:22.399454 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5358 10:55:22.402480 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5359 10:55:22.409297 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5360 10:55:22.413022 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5361 10:55:22.416170 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5362 10:55:22.419406 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5363 10:55:22.422627 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5364 10:55:22.425850 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5365 10:55:22.429159 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5366 10:55:22.435687 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5367 10:55:22.438833 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5368 10:55:22.442585 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5369 10:55:22.445663 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5370 10:55:22.449115 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5371 10:55:22.452162 ==
5372 10:55:22.455972 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 10:55:22.458944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 10:55:22.459042 ==
5375 10:55:22.459109 DQS Delay:
5376 10:55:22.462181 DQS0 = 0, DQS1 = 0
5377 10:55:22.462274 DQM Delay:
5378 10:55:22.465864 DQM0 = 104, DQM1 = 95
5379 10:55:22.465961 DQ Delay:
5380 10:55:22.469137 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5381 10:55:22.472320 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5382 10:55:22.475368 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5383 10:55:22.478456 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5384 10:55:22.478581
5385 10:55:22.478647
5386 10:55:22.478706 ==
5387 10:55:22.481925 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 10:55:22.485725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 10:55:22.488755 ==
5390 10:55:22.488870
5391 10:55:22.488954
5392 10:55:22.489037 TX Vref Scan disable
5393 10:55:22.491789 == TX Byte 0 ==
5394 10:55:22.495475 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5395 10:55:22.498544 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5396 10:55:22.502250 == TX Byte 1 ==
5397 10:55:22.505153 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5398 10:55:22.508871 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5399 10:55:22.511775 ==
5400 10:55:22.511909 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 10:55:22.518677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 10:55:22.518802 ==
5403 10:55:22.518937
5404 10:55:22.519039
5405 10:55:22.521743 TX Vref Scan disable
5406 10:55:22.521848 == TX Byte 0 ==
5407 10:55:22.528839 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5408 10:55:22.532018 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5409 10:55:22.532101 == TX Byte 1 ==
5410 10:55:22.538531 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5411 10:55:22.541857 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5412 10:55:22.541989
5413 10:55:22.542090 [DATLAT]
5414 10:55:22.545029 Freq=933, CH0 RK1
5415 10:55:22.545111
5416 10:55:22.545193 DATLAT Default: 0xb
5417 10:55:22.548198 0, 0xFFFF, sum = 0
5418 10:55:22.548283 1, 0xFFFF, sum = 0
5419 10:55:22.551966 2, 0xFFFF, sum = 0
5420 10:55:22.552069 3, 0xFFFF, sum = 0
5421 10:55:22.555082 4, 0xFFFF, sum = 0
5422 10:55:22.555162 5, 0xFFFF, sum = 0
5423 10:55:22.558158 6, 0xFFFF, sum = 0
5424 10:55:22.558241 7, 0xFFFF, sum = 0
5425 10:55:22.561915 8, 0xFFFF, sum = 0
5426 10:55:22.561996 9, 0xFFFF, sum = 0
5427 10:55:22.565019 10, 0x0, sum = 1
5428 10:55:22.565122 11, 0x0, sum = 2
5429 10:55:22.568785 12, 0x0, sum = 3
5430 10:55:22.568874 13, 0x0, sum = 4
5431 10:55:22.571938 best_step = 11
5432 10:55:22.572026
5433 10:55:22.572095 ==
5434 10:55:22.575219 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 10:55:22.578268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 10:55:22.578380 ==
5437 10:55:22.581549 RX Vref Scan: 0
5438 10:55:22.581656
5439 10:55:22.581746 RX Vref 0 -> 0, step: 1
5440 10:55:22.581836
5441 10:55:22.584917 RX Delay -45 -> 252, step: 4
5442 10:55:22.591902 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5443 10:55:22.595698 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5444 10:55:22.598777 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5445 10:55:22.601939 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5446 10:55:22.605227 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5447 10:55:22.611865 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5448 10:55:22.615273 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5449 10:55:22.618781 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5450 10:55:22.621753 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5451 10:55:22.625328 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5452 10:55:22.628786 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5453 10:55:22.635073 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5454 10:55:22.638308 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5455 10:55:22.641604 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5456 10:55:22.645420 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5457 10:55:22.648726 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5458 10:55:22.651922 ==
5459 10:55:22.655117 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 10:55:22.658310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 10:55:22.658473 ==
5462 10:55:22.658601 DQS Delay:
5463 10:55:22.662095 DQS0 = 0, DQS1 = 0
5464 10:55:22.662242 DQM Delay:
5465 10:55:22.665198 DQM0 = 104, DQM1 = 94
5466 10:55:22.665311 DQ Delay:
5467 10:55:22.668437 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5468 10:55:22.672117 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5469 10:55:22.675182 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =88
5470 10:55:22.678345 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5471 10:55:22.678458
5472 10:55:22.678553
5473 10:55:22.688452 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5474 10:55:22.688586 CH0 RK1: MR19=505, MR18=2B04
5475 10:55:22.695473 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5476 10:55:22.698573 [RxdqsGatingPostProcess] freq 933
5477 10:55:22.705011 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5478 10:55:22.708213 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 10:55:22.711433 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 10:55:22.715049 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 10:55:22.718328 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 10:55:22.721884 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 10:55:22.722020 best DQS1 dly(2T, 0.5T) = (0, 10)
5484 10:55:22.724917 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 10:55:22.728525 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5486 10:55:22.731506 Pre-setting of DQS Precalculation
5487 10:55:22.738633 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5488 10:55:22.738749 ==
5489 10:55:22.741812 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 10:55:22.745033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 10:55:22.745124 ==
5492 10:55:22.751433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5493 10:55:22.758497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5494 10:55:22.761838 [CA 0] Center 36 (6~67) winsize 62
5495 10:55:22.765028 [CA 1] Center 37 (7~68) winsize 62
5496 10:55:22.768330 [CA 2] Center 34 (4~65) winsize 62
5497 10:55:22.771420 [CA 3] Center 34 (4~65) winsize 62
5498 10:55:22.774612 [CA 4] Center 34 (4~65) winsize 62
5499 10:55:22.777741 [CA 5] Center 33 (3~64) winsize 62
5500 10:55:22.777839
5501 10:55:22.781518 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5502 10:55:22.781613
5503 10:55:22.784481 [CATrainingPosCal] consider 1 rank data
5504 10:55:22.788207 u2DelayCellTimex100 = 270/100 ps
5505 10:55:22.791240 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 10:55:22.794499 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5507 10:55:22.798226 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 10:55:22.801383 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 10:55:22.804639 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 10:55:22.807934 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5511 10:55:22.808037
5512 10:55:22.814795 CA PerBit enable=1, Macro0, CA PI delay=33
5513 10:55:22.814930
5514 10:55:22.815005 [CBTSetCACLKResult] CA Dly = 33
5515 10:55:22.818166 CS Dly: 6 (0~37)
5516 10:55:22.818261 ==
5517 10:55:22.821218 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 10:55:22.824212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 10:55:22.824306 ==
5520 10:55:22.830788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 10:55:22.837749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5522 10:55:22.840648 [CA 0] Center 37 (6~68) winsize 63
5523 10:55:22.844165 [CA 1] Center 37 (6~68) winsize 63
5524 10:55:22.847412 [CA 2] Center 35 (5~66) winsize 62
5525 10:55:22.851237 [CA 3] Center 34 (4~65) winsize 62
5526 10:55:22.854527 [CA 4] Center 34 (4~65) winsize 62
5527 10:55:22.857724 [CA 5] Center 34 (4~64) winsize 61
5528 10:55:22.857817
5529 10:55:22.860898 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5530 10:55:22.860986
5531 10:55:22.864643 [CATrainingPosCal] consider 2 rank data
5532 10:55:22.867968 u2DelayCellTimex100 = 270/100 ps
5533 10:55:22.871158 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5534 10:55:22.874476 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5535 10:55:22.877521 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5536 10:55:22.880584 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5537 10:55:22.884436 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5538 10:55:22.887472 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5539 10:55:22.887566
5540 10:55:22.894167 CA PerBit enable=1, Macro0, CA PI delay=34
5541 10:55:22.894295
5542 10:55:22.897241 [CBTSetCACLKResult] CA Dly = 34
5543 10:55:22.897336 CS Dly: 7 (0~40)
5544 10:55:22.897421
5545 10:55:22.900527 ----->DramcWriteLeveling(PI) begin...
5546 10:55:22.900620 ==
5547 10:55:22.904403 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 10:55:22.907562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 10:55:22.907680 ==
5550 10:55:22.910915 Write leveling (Byte 0): 29 => 29
5551 10:55:22.914134 Write leveling (Byte 1): 27 => 27
5552 10:55:22.917225 DramcWriteLeveling(PI) end<-----
5553 10:55:22.917327
5554 10:55:22.917402 ==
5555 10:55:22.921037 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 10:55:22.927417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 10:55:22.927523 ==
5558 10:55:22.927591 [Gating] SW mode calibration
5559 10:55:22.937094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5560 10:55:22.940852 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5561 10:55:22.943800 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 10:55:22.950390 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 10:55:22.953969 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 10:55:22.957192 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 10:55:22.964101 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 10:55:22.967305 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 10:55:22.970492 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
5568 10:55:22.977643 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5569 10:55:22.980967 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 10:55:22.984258 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 10:55:22.990404 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 10:55:22.994137 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 10:55:22.997254 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 10:55:23.004243 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 10:55:23.007519 0 15 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5576 10:55:23.010658 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5577 10:55:23.017219 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 10:55:23.020300 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 10:55:23.023661 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 10:55:23.030591 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 10:55:23.033787 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 10:55:23.036939 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 10:55:23.043882 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 10:55:23.046929 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 10:55:23.049921 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 10:55:23.056870 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 10:55:23.059879 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 10:55:23.063488 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 10:55:23.069801 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:55:23.073555 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:55:23.076758 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:55:23.083250 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:55:23.086511 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:55:23.089556 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:55:23.096439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:55:23.099604 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:55:23.103232 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 10:55:23.106331 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 10:55:23.113256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5600 10:55:23.116403 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 10:55:23.119721 Total UI for P1: 0, mck2ui 16
5602 10:55:23.122924 best dqsien dly found for B0: ( 1, 2, 24)
5603 10:55:23.126063 Total UI for P1: 0, mck2ui 16
5604 10:55:23.129965 best dqsien dly found for B1: ( 1, 2, 24)
5605 10:55:23.133135 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5606 10:55:23.136428 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5607 10:55:23.136525
5608 10:55:23.139693 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 10:55:23.146068 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 10:55:23.146174 [Gating] SW calibration Done
5611 10:55:23.146239 ==
5612 10:55:23.149775 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 10:55:23.156327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 10:55:23.156430 ==
5615 10:55:23.156498 RX Vref Scan: 0
5616 10:55:23.156560
5617 10:55:23.159359 RX Vref 0 -> 0, step: 1
5618 10:55:23.159458
5619 10:55:23.162980 RX Delay -80 -> 252, step: 8
5620 10:55:23.166393 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5621 10:55:23.169411 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5622 10:55:23.172670 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5623 10:55:23.176317 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5624 10:55:23.179536 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5625 10:55:23.185923 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5626 10:55:23.189753 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5627 10:55:23.193037 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5628 10:55:23.196113 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5629 10:55:23.199291 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5630 10:55:23.206008 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5631 10:55:23.209126 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5632 10:55:23.212363 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5633 10:55:23.216028 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5634 10:55:23.219030 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5635 10:55:23.226254 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5636 10:55:23.226359 ==
5637 10:55:23.229287 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 10:55:23.232321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 10:55:23.232417 ==
5640 10:55:23.232483 DQS Delay:
5641 10:55:23.235624 DQS0 = 0, DQS1 = 0
5642 10:55:23.235707 DQM Delay:
5643 10:55:23.238896 DQM0 = 102, DQM1 = 98
5644 10:55:23.238979 DQ Delay:
5645 10:55:23.242641 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5646 10:55:23.245940 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5647 10:55:23.249099 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5648 10:55:23.252300 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5649 10:55:23.252396
5650 10:55:23.252461
5651 10:55:23.252521 ==
5652 10:55:23.255581 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 10:55:23.262149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 10:55:23.262249 ==
5655 10:55:23.262315
5656 10:55:23.262376
5657 10:55:23.262434 TX Vref Scan disable
5658 10:55:23.265834 == TX Byte 0 ==
5659 10:55:23.268973 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5660 10:55:23.275438 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5661 10:55:23.275604 == TX Byte 1 ==
5662 10:55:23.279139 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 10:55:23.285523 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 10:55:23.285641 ==
5665 10:55:23.288763 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 10:55:23.292021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 10:55:23.292127 ==
5668 10:55:23.292194
5669 10:55:23.292255
5670 10:55:23.295900 TX Vref Scan disable
5671 10:55:23.295986 == TX Byte 0 ==
5672 10:55:23.302153 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5673 10:55:23.305446 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5674 10:55:23.305549 == TX Byte 1 ==
5675 10:55:23.312167 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 10:55:23.315863 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 10:55:23.315963
5678 10:55:23.316044 [DATLAT]
5679 10:55:23.318988 Freq=933, CH1 RK0
5680 10:55:23.319078
5681 10:55:23.319145 DATLAT Default: 0xd
5682 10:55:23.322113 0, 0xFFFF, sum = 0
5683 10:55:23.322206 1, 0xFFFF, sum = 0
5684 10:55:23.325297 2, 0xFFFF, sum = 0
5685 10:55:23.325385 3, 0xFFFF, sum = 0
5686 10:55:23.328932 4, 0xFFFF, sum = 0
5687 10:55:23.329025 5, 0xFFFF, sum = 0
5688 10:55:23.332105 6, 0xFFFF, sum = 0
5689 10:55:23.335259 7, 0xFFFF, sum = 0
5690 10:55:23.335389 8, 0xFFFF, sum = 0
5691 10:55:23.338541 9, 0xFFFF, sum = 0
5692 10:55:23.338627 10, 0x0, sum = 1
5693 10:55:23.338694 11, 0x0, sum = 2
5694 10:55:23.342411 12, 0x0, sum = 3
5695 10:55:23.342497 13, 0x0, sum = 4
5696 10:55:23.345652 best_step = 11
5697 10:55:23.345736
5698 10:55:23.345802 ==
5699 10:55:23.348765 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 10:55:23.351965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 10:55:23.352053 ==
5702 10:55:23.355204 RX Vref Scan: 1
5703 10:55:23.355288
5704 10:55:23.355398 RX Vref 0 -> 0, step: 1
5705 10:55:23.355462
5706 10:55:23.359076 RX Delay -45 -> 252, step: 4
5707 10:55:23.359219
5708 10:55:23.362182 Set Vref, RX VrefLevel [Byte0]: 55
5709 10:55:23.365247 [Byte1]: 52
5710 10:55:23.369522
5711 10:55:23.369642 Final RX Vref Byte 0 = 55 to rank0
5712 10:55:23.373245 Final RX Vref Byte 1 = 52 to rank0
5713 10:55:23.376241 Final RX Vref Byte 0 = 55 to rank1
5714 10:55:23.379869 Final RX Vref Byte 1 = 52 to rank1==
5715 10:55:23.382916 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 10:55:23.386576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 10:55:23.389787 ==
5718 10:55:23.389889 DQS Delay:
5719 10:55:23.389957 DQS0 = 0, DQS1 = 0
5720 10:55:23.392883 DQM Delay:
5721 10:55:23.392969 DQM0 = 103, DQM1 = 99
5722 10:55:23.396158 DQ Delay:
5723 10:55:23.399275 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5724 10:55:23.402550 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5725 10:55:23.406456 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5726 10:55:23.409097 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5727 10:55:23.409192
5728 10:55:23.409260
5729 10:55:23.416154 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5730 10:55:23.419363 CH1 RK0: MR19=505, MR18=152C
5731 10:55:23.425796 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5732 10:55:23.425909
5733 10:55:23.429551 ----->DramcWriteLeveling(PI) begin...
5734 10:55:23.429645 ==
5735 10:55:23.432605 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 10:55:23.435854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 10:55:23.435945 ==
5738 10:55:23.439634 Write leveling (Byte 0): 27 => 27
5739 10:55:23.442776 Write leveling (Byte 1): 28 => 28
5740 10:55:23.446018 DramcWriteLeveling(PI) end<-----
5741 10:55:23.446110
5742 10:55:23.446176 ==
5743 10:55:23.449285 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 10:55:23.453010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 10:55:23.456233 ==
5746 10:55:23.456333 [Gating] SW mode calibration
5747 10:55:23.465843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 10:55:23.469676 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 10:55:23.472664 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 10:55:23.479234 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 10:55:23.482935 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 10:55:23.485971 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 10:55:23.492597 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 10:55:23.496303 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 10:55:23.499377 0 14 24 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 0)
5756 10:55:23.505784 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5757 10:55:23.509181 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 10:55:23.512348 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 10:55:23.518933 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 10:55:23.522516 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 10:55:23.525710 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 10:55:23.532158 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5763 10:55:23.536031 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
5764 10:55:23.538975 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5765 10:55:23.546006 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 10:55:23.549154 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 10:55:23.552367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 10:55:23.558703 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 10:55:23.561920 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 10:55:23.565838 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 10:55:23.572162 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 10:55:23.575477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5773 10:55:23.579162 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 10:55:23.585850 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 10:55:23.588860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 10:55:23.591930 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 10:55:23.595538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:55:23.602289 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:55:23.605504 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:55:23.608596 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:55:23.615753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:55:23.618840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:55:23.622090 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 10:55:23.628993 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 10:55:23.631966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 10:55:23.635213 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 10:55:23.642149 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5788 10:55:23.645302 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5789 10:55:23.648257 Total UI for P1: 0, mck2ui 16
5790 10:55:23.652200 best dqsien dly found for B1: ( 1, 2, 24)
5791 10:55:23.655408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 10:55:23.658464 Total UI for P1: 0, mck2ui 16
5793 10:55:23.661637 best dqsien dly found for B0: ( 1, 2, 26)
5794 10:55:23.665433 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5795 10:55:23.668727 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5796 10:55:23.668820
5797 10:55:23.675190 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5798 10:55:23.678462 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 10:55:23.681509 [Gating] SW calibration Done
5800 10:55:23.681600 ==
5801 10:55:23.685183 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 10:55:23.688207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 10:55:23.688365 ==
5804 10:55:23.688477 RX Vref Scan: 0
5805 10:55:23.688646
5806 10:55:23.691769 RX Vref 0 -> 0, step: 1
5807 10:55:23.691897
5808 10:55:23.694992 RX Delay -80 -> 252, step: 8
5809 10:55:23.698241 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5810 10:55:23.701508 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5811 10:55:23.705021 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5812 10:55:23.711744 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5813 10:55:23.714691 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5814 10:55:23.717990 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5815 10:55:23.721291 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5816 10:55:23.725048 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5817 10:55:23.728320 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5818 10:55:23.734644 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5819 10:55:23.737753 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5820 10:55:23.740979 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5821 10:55:23.744833 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5822 10:55:23.747978 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5823 10:55:23.754921 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5824 10:55:23.758006 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5825 10:55:23.758152 ==
5826 10:55:23.761186 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 10:55:23.764529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 10:55:23.764661 ==
5829 10:55:23.767673 DQS Delay:
5830 10:55:23.767791 DQS0 = 0, DQS1 = 0
5831 10:55:23.767902 DQM Delay:
5832 10:55:23.771414 DQM0 = 103, DQM1 = 99
5833 10:55:23.771527 DQ Delay:
5834 10:55:23.774750 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5835 10:55:23.777992 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5836 10:55:23.781226 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5837 10:55:23.784487 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5838 10:55:23.784602
5839 10:55:23.784705
5840 10:55:23.784805 ==
5841 10:55:23.788119 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 10:55:23.794778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 10:55:23.794922 ==
5844 10:55:23.795033
5845 10:55:23.795125
5846 10:55:23.795228 TX Vref Scan disable
5847 10:55:23.798268 == TX Byte 0 ==
5848 10:55:23.801809 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5849 10:55:23.808004 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5850 10:55:23.808137 == TX Byte 1 ==
5851 10:55:23.811506 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5852 10:55:23.818296 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5853 10:55:23.818463 ==
5854 10:55:23.821477 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 10:55:23.824677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 10:55:23.824799 ==
5857 10:55:23.824897
5858 10:55:23.824989
5859 10:55:23.827870 TX Vref Scan disable
5860 10:55:23.828008 == TX Byte 0 ==
5861 10:55:23.834932 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5862 10:55:23.838037 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5863 10:55:23.838178 == TX Byte 1 ==
5864 10:55:23.844956 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 10:55:23.847951 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 10:55:23.848097
5867 10:55:23.848192 [DATLAT]
5868 10:55:23.851172 Freq=933, CH1 RK1
5869 10:55:23.851294
5870 10:55:23.851410 DATLAT Default: 0xb
5871 10:55:23.854353 0, 0xFFFF, sum = 0
5872 10:55:23.854469 1, 0xFFFF, sum = 0
5873 10:55:23.858244 2, 0xFFFF, sum = 0
5874 10:55:23.858373 3, 0xFFFF, sum = 0
5875 10:55:23.861300 4, 0xFFFF, sum = 0
5876 10:55:23.864275 5, 0xFFFF, sum = 0
5877 10:55:23.864402 6, 0xFFFF, sum = 0
5878 10:55:23.868003 7, 0xFFFF, sum = 0
5879 10:55:23.868121 8, 0xFFFF, sum = 0
5880 10:55:23.871077 9, 0xFFFF, sum = 0
5881 10:55:23.871215 10, 0x0, sum = 1
5882 10:55:23.874868 11, 0x0, sum = 2
5883 10:55:23.875020 12, 0x0, sum = 3
5884 10:55:23.875119 13, 0x0, sum = 4
5885 10:55:23.878018 best_step = 11
5886 10:55:23.878160
5887 10:55:23.878278 ==
5888 10:55:23.881193 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 10:55:23.884920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 10:55:23.885053 ==
5891 10:55:23.888142 RX Vref Scan: 0
5892 10:55:23.888228
5893 10:55:23.888300 RX Vref 0 -> 0, step: 1
5894 10:55:23.888362
5895 10:55:23.891149 RX Delay -45 -> 252, step: 4
5896 10:55:23.898658 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5897 10:55:23.901627 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5898 10:55:23.905274 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5899 10:55:23.908281 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5900 10:55:23.912166 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5901 10:55:23.918941 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5902 10:55:23.921984 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5903 10:55:23.925007 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5904 10:55:23.928802 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5905 10:55:23.932064 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5906 10:55:23.935180 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5907 10:55:23.941786 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5908 10:55:23.944945 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5909 10:55:23.948731 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5910 10:55:23.951851 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5911 10:55:23.958146 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5912 10:55:23.958269 ==
5913 10:55:23.962008 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 10:55:23.965211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 10:55:23.965305 ==
5916 10:55:23.965372 DQS Delay:
5917 10:55:23.968439 DQS0 = 0, DQS1 = 0
5918 10:55:23.968554 DQM Delay:
5919 10:55:23.971601 DQM0 = 104, DQM1 = 99
5920 10:55:23.971688 DQ Delay:
5921 10:55:23.975198 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5922 10:55:23.978250 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5923 10:55:23.981551 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5924 10:55:23.984821 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5925 10:55:23.984915
5926 10:55:23.984981
5927 10:55:23.994635 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5928 10:55:23.998356 CH1 RK1: MR19=504, MR18=2AFD
5929 10:55:24.001492 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5930 10:55:24.004625 [RxdqsGatingPostProcess] freq 933
5931 10:55:24.011302 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 10:55:24.014311 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 10:55:24.017963 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 10:55:24.021635 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 10:55:24.024738 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 10:55:24.027858 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 10:55:24.031468 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 10:55:24.034487 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 10:55:24.037666 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 10:55:24.037764 Pre-setting of DQS Precalculation
5941 10:55:24.044824 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 10:55:24.051276 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 10:55:24.057816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 10:55:24.057930
5945 10:55:24.058004
5946 10:55:24.061163 [Calibration Summary] 1866 Mbps
5947 10:55:24.064350 CH 0, Rank 0
5948 10:55:24.064433 SW Impedance : PASS
5949 10:55:24.067674 DUTY Scan : NO K
5950 10:55:24.071446 ZQ Calibration : PASS
5951 10:55:24.071532 Jitter Meter : NO K
5952 10:55:24.074585 CBT Training : PASS
5953 10:55:24.077736 Write leveling : PASS
5954 10:55:24.077833 RX DQS gating : PASS
5955 10:55:24.080862 RX DQ/DQS(RDDQC) : PASS
5956 10:55:24.080962 TX DQ/DQS : PASS
5957 10:55:24.084474 RX DATLAT : PASS
5958 10:55:24.087764 RX DQ/DQS(Engine): PASS
5959 10:55:24.087839 TX OE : NO K
5960 10:55:24.091001 All Pass.
5961 10:55:24.091071
5962 10:55:24.091132 CH 0, Rank 1
5963 10:55:24.094257 SW Impedance : PASS
5964 10:55:24.094329 DUTY Scan : NO K
5965 10:55:24.097457 ZQ Calibration : PASS
5966 10:55:24.100682 Jitter Meter : NO K
5967 10:55:24.100809 CBT Training : PASS
5968 10:55:24.104509 Write leveling : PASS
5969 10:55:24.107514 RX DQS gating : PASS
5970 10:55:24.107606 RX DQ/DQS(RDDQC) : PASS
5971 10:55:24.110626 TX DQ/DQS : PASS
5972 10:55:24.114282 RX DATLAT : PASS
5973 10:55:24.114374 RX DQ/DQS(Engine): PASS
5974 10:55:24.117632 TX OE : NO K
5975 10:55:24.117744 All Pass.
5976 10:55:24.117825
5977 10:55:24.120775 CH 1, Rank 0
5978 10:55:24.120887 SW Impedance : PASS
5979 10:55:24.124342 DUTY Scan : NO K
5980 10:55:24.127240 ZQ Calibration : PASS
5981 10:55:24.127337 Jitter Meter : NO K
5982 10:55:24.130835 CBT Training : PASS
5983 10:55:24.133903 Write leveling : PASS
5984 10:55:24.133988 RX DQS gating : PASS
5985 10:55:24.137457 RX DQ/DQS(RDDQC) : PASS
5986 10:55:24.137544 TX DQ/DQS : PASS
5987 10:55:24.140979 RX DATLAT : PASS
5988 10:55:24.144205 RX DQ/DQS(Engine): PASS
5989 10:55:24.144293 TX OE : NO K
5990 10:55:24.147478 All Pass.
5991 10:55:24.147562
5992 10:55:24.147627 CH 1, Rank 1
5993 10:55:24.150702 SW Impedance : PASS
5994 10:55:24.150786 DUTY Scan : NO K
5995 10:55:24.153997 ZQ Calibration : PASS
5996 10:55:24.157206 Jitter Meter : NO K
5997 10:55:24.157317 CBT Training : PASS
5998 10:55:24.160452 Write leveling : PASS
5999 10:55:24.164032 RX DQS gating : PASS
6000 10:55:24.164131 RX DQ/DQS(RDDQC) : PASS
6001 10:55:24.167685 TX DQ/DQS : PASS
6002 10:55:24.170828 RX DATLAT : PASS
6003 10:55:24.170917 RX DQ/DQS(Engine): PASS
6004 10:55:24.174038 TX OE : NO K
6005 10:55:24.174127 All Pass.
6006 10:55:24.174194
6007 10:55:24.177183 DramC Write-DBI off
6008 10:55:24.180364 PER_BANK_REFRESH: Hybrid Mode
6009 10:55:24.180470 TX_TRACKING: ON
6010 10:55:24.190781 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 10:55:24.194051 [FAST_K] Save calibration result to emmc
6012 10:55:24.197360 dramc_set_vcore_voltage set vcore to 650000
6013 10:55:24.200536 Read voltage for 400, 6
6014 10:55:24.200646 Vio18 = 0
6015 10:55:24.200714 Vcore = 650000
6016 10:55:24.203718 Vdram = 0
6017 10:55:24.203802 Vddq = 0
6018 10:55:24.203869 Vmddr = 0
6019 10:55:24.210738 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 10:55:24.213741 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 10:55:24.217472 MEM_TYPE=3, freq_sel=20
6022 10:55:24.220369 sv_algorithm_assistance_LP4_800
6023 10:55:24.223965 ============ PULL DRAM RESETB DOWN ============
6024 10:55:24.226992 ========== PULL DRAM RESETB DOWN end =========
6025 10:55:24.233781 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 10:55:24.236913 ===================================
6027 10:55:24.237031 LPDDR4 DRAM CONFIGURATION
6028 10:55:24.240518 ===================================
6029 10:55:24.243678 EX_ROW_EN[0] = 0x0
6030 10:55:24.246705 EX_ROW_EN[1] = 0x0
6031 10:55:24.246825 LP4Y_EN = 0x0
6032 10:55:24.249978 WORK_FSP = 0x0
6033 10:55:24.250063 WL = 0x2
6034 10:55:24.253738 RL = 0x2
6035 10:55:24.253824 BL = 0x2
6036 10:55:24.256917 RPST = 0x0
6037 10:55:24.257032 RD_PRE = 0x0
6038 10:55:24.260085 WR_PRE = 0x1
6039 10:55:24.260170 WR_PST = 0x0
6040 10:55:24.263211 DBI_WR = 0x0
6041 10:55:24.263323 DBI_RD = 0x0
6042 10:55:24.266432 OTF = 0x1
6043 10:55:24.269720 ===================================
6044 10:55:24.273415 ===================================
6045 10:55:24.273507 ANA top config
6046 10:55:24.276652 ===================================
6047 10:55:24.279846 DLL_ASYNC_EN = 0
6048 10:55:24.283082 ALL_SLAVE_EN = 1
6049 10:55:24.286375 NEW_RANK_MODE = 1
6050 10:55:24.286506 DLL_IDLE_MODE = 1
6051 10:55:24.289647 LP45_APHY_COMB_EN = 1
6052 10:55:24.293359 TX_ODT_DIS = 1
6053 10:55:24.296245 NEW_8X_MODE = 1
6054 10:55:24.299886 ===================================
6055 10:55:24.303084 ===================================
6056 10:55:24.306417 data_rate = 800
6057 10:55:24.306520 CKR = 1
6058 10:55:24.309699 DQ_P2S_RATIO = 4
6059 10:55:24.312864 ===================================
6060 10:55:24.316019 CA_P2S_RATIO = 4
6061 10:55:24.319817 DQ_CA_OPEN = 0
6062 10:55:24.322911 DQ_SEMI_OPEN = 1
6063 10:55:24.326014 CA_SEMI_OPEN = 1
6064 10:55:24.326143 CA_FULL_RATE = 0
6065 10:55:24.329159 DQ_CKDIV4_EN = 0
6066 10:55:24.332664 CA_CKDIV4_EN = 1
6067 10:55:24.336238 CA_PREDIV_EN = 0
6068 10:55:24.339384 PH8_DLY = 0
6069 10:55:24.342460 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 10:55:24.346090 DQ_AAMCK_DIV = 0
6071 10:55:24.346240 CA_AAMCK_DIV = 0
6072 10:55:24.349139 CA_ADMCK_DIV = 4
6073 10:55:24.352357 DQ_TRACK_CA_EN = 0
6074 10:55:24.356119 CA_PICK = 800
6075 10:55:24.359310 CA_MCKIO = 400
6076 10:55:24.362470 MCKIO_SEMI = 400
6077 10:55:24.365700 PLL_FREQ = 3016
6078 10:55:24.365807 DQ_UI_PI_RATIO = 32
6079 10:55:24.368823 CA_UI_PI_RATIO = 32
6080 10:55:24.372676 ===================================
6081 10:55:24.375776 ===================================
6082 10:55:24.378978 memory_type:LPDDR4
6083 10:55:24.382233 GP_NUM : 10
6084 10:55:24.382346 SRAM_EN : 1
6085 10:55:24.385785 MD32_EN : 0
6086 10:55:24.389084 ===================================
6087 10:55:24.392351 [ANA_INIT] >>>>>>>>>>>>>>
6088 10:55:24.392468 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 10:55:24.395580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 10:55:24.399230 ===================================
6091 10:55:24.402452 data_rate = 800,PCW = 0X7400
6092 10:55:24.405407 ===================================
6093 10:55:24.408600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 10:55:24.415860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 10:55:24.425462 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 10:55:24.432017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 10:55:24.435691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 10:55:24.438853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 10:55:24.438969 [ANA_INIT] flow start
6100 10:55:24.442464 [ANA_INIT] PLL >>>>>>>>
6101 10:55:24.445503 [ANA_INIT] PLL <<<<<<<<
6102 10:55:24.448579 [ANA_INIT] MIDPI >>>>>>>>
6103 10:55:24.448665 [ANA_INIT] MIDPI <<<<<<<<
6104 10:55:24.452185 [ANA_INIT] DLL >>>>>>>>
6105 10:55:24.452270 [ANA_INIT] flow end
6106 10:55:24.458737 ============ LP4 DIFF to SE enter ============
6107 10:55:24.461966 ============ LP4 DIFF to SE exit ============
6108 10:55:24.465198 [ANA_INIT] <<<<<<<<<<<<<
6109 10:55:24.468513 [Flow] Enable top DCM control >>>>>
6110 10:55:24.471852 [Flow] Enable top DCM control <<<<<
6111 10:55:24.474991 Enable DLL master slave shuffle
6112 10:55:24.478929 ==============================================================
6113 10:55:24.482116 Gating Mode config
6114 10:55:24.485429 ==============================================================
6115 10:55:24.488501 Config description:
6116 10:55:24.498492 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 10:55:24.505434 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 10:55:24.508558 SELPH_MODE 0: By rank 1: By Phase
6119 10:55:24.515437 ==============================================================
6120 10:55:24.518655 GAT_TRACK_EN = 0
6121 10:55:24.521841 RX_GATING_MODE = 2
6122 10:55:24.524916 RX_GATING_TRACK_MODE = 2
6123 10:55:24.528104 SELPH_MODE = 1
6124 10:55:24.531844 PICG_EARLY_EN = 1
6125 10:55:24.531944 VALID_LAT_VALUE = 1
6126 10:55:24.538568 ==============================================================
6127 10:55:24.541569 Enter into Gating configuration >>>>
6128 10:55:24.545006 Exit from Gating configuration <<<<
6129 10:55:24.548211 Enter into DVFS_PRE_config >>>>>
6130 10:55:24.558204 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 10:55:24.561841 Exit from DVFS_PRE_config <<<<<
6132 10:55:24.564870 Enter into PICG configuration >>>>
6133 10:55:24.568585 Exit from PICG configuration <<<<
6134 10:55:24.571769 [RX_INPUT] configuration >>>>>
6135 10:55:24.575172 [RX_INPUT] configuration <<<<<
6136 10:55:24.578491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 10:55:24.584704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 10:55:24.591705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 10:55:24.598269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 10:55:24.604986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 10:55:24.611201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 10:55:24.615124 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 10:55:24.618230 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 10:55:24.621449 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 10:55:24.624669 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 10:55:24.631057 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 10:55:24.634994 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 10:55:24.638209 ===================================
6149 10:55:24.641264 LPDDR4 DRAM CONFIGURATION
6150 10:55:24.644379 ===================================
6151 10:55:24.644477 EX_ROW_EN[0] = 0x0
6152 10:55:24.648176 EX_ROW_EN[1] = 0x0
6153 10:55:24.648275 LP4Y_EN = 0x0
6154 10:55:24.651132 WORK_FSP = 0x0
6155 10:55:24.651222 WL = 0x2
6156 10:55:24.654743 RL = 0x2
6157 10:55:24.654836 BL = 0x2
6158 10:55:24.657676 RPST = 0x0
6159 10:55:24.661425 RD_PRE = 0x0
6160 10:55:24.661520 WR_PRE = 0x1
6161 10:55:24.664455 WR_PST = 0x0
6162 10:55:24.664547 DBI_WR = 0x0
6163 10:55:24.667723 DBI_RD = 0x0
6164 10:55:24.667813 OTF = 0x1
6165 10:55:24.671277 ===================================
6166 10:55:24.674395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 10:55:24.681454 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 10:55:24.684590 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 10:55:24.687709 ===================================
6170 10:55:24.690950 LPDDR4 DRAM CONFIGURATION
6171 10:55:24.694777 ===================================
6172 10:55:24.694879 EX_ROW_EN[0] = 0x10
6173 10:55:24.697983 EX_ROW_EN[1] = 0x0
6174 10:55:24.698073 LP4Y_EN = 0x0
6175 10:55:24.701168 WORK_FSP = 0x0
6176 10:55:24.701257 WL = 0x2
6177 10:55:24.704292 RL = 0x2
6178 10:55:24.704381 BL = 0x2
6179 10:55:24.708109 RPST = 0x0
6180 10:55:24.708201 RD_PRE = 0x0
6181 10:55:24.711406 WR_PRE = 0x1
6182 10:55:24.711495 WR_PST = 0x0
6183 10:55:24.714271 DBI_WR = 0x0
6184 10:55:24.714359 DBI_RD = 0x0
6185 10:55:24.718155 OTF = 0x1
6186 10:55:24.721392 ===================================
6187 10:55:24.727740 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 10:55:24.730962 nWR fixed to 30
6189 10:55:24.734764 [ModeRegInit_LP4] CH0 RK0
6190 10:55:24.734888 [ModeRegInit_LP4] CH0 RK1
6191 10:55:24.737927 [ModeRegInit_LP4] CH1 RK0
6192 10:55:24.741172 [ModeRegInit_LP4] CH1 RK1
6193 10:55:24.741307 match AC timing 19
6194 10:55:24.747342 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 10:55:24.750824 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 10:55:24.754016 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 10:55:24.760779 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 10:55:24.764343 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 10:55:24.764460 ==
6200 10:55:24.767339 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 10:55:24.770904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 10:55:24.770988 ==
6203 10:55:24.777513 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 10:55:24.784093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6205 10:55:24.787931 [CA 0] Center 36 (8~64) winsize 57
6206 10:55:24.791081 [CA 1] Center 36 (8~64) winsize 57
6207 10:55:24.794493 [CA 2] Center 36 (8~64) winsize 57
6208 10:55:24.797619 [CA 3] Center 36 (8~64) winsize 57
6209 10:55:24.797735 [CA 4] Center 36 (8~64) winsize 57
6210 10:55:24.800841 [CA 5] Center 36 (8~64) winsize 57
6211 10:55:24.800932
6212 10:55:24.807830 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6213 10:55:24.807943
6214 10:55:24.811010 [CATrainingPosCal] consider 1 rank data
6215 10:55:24.814205 u2DelayCellTimex100 = 270/100 ps
6216 10:55:24.817340 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 10:55:24.820399 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 10:55:24.824064 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 10:55:24.827292 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 10:55:24.830344 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 10:55:24.834259 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 10:55:24.834372
6223 10:55:24.837481 CA PerBit enable=1, Macro0, CA PI delay=36
6224 10:55:24.837574
6225 10:55:24.840635 [CBTSetCACLKResult] CA Dly = 36
6226 10:55:24.843702 CS Dly: 1 (0~32)
6227 10:55:24.843799 ==
6228 10:55:24.846932 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 10:55:24.850122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 10:55:24.850218 ==
6231 10:55:24.856903 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 10:55:24.863616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 10:55:24.863746 [CA 0] Center 36 (8~64) winsize 57
6234 10:55:24.866689 [CA 1] Center 36 (8~64) winsize 57
6235 10:55:24.870373 [CA 2] Center 36 (8~64) winsize 57
6236 10:55:24.873484 [CA 3] Center 36 (8~64) winsize 57
6237 10:55:24.877202 [CA 4] Center 36 (8~64) winsize 57
6238 10:55:24.879910 [CA 5] Center 36 (8~64) winsize 57
6239 10:55:24.880013
6240 10:55:24.883454 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 10:55:24.883551
6242 10:55:24.886620 [CATrainingPosCal] consider 2 rank data
6243 10:55:24.889888 u2DelayCellTimex100 = 270/100 ps
6244 10:55:24.893713 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 10:55:24.900299 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 10:55:24.903621 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 10:55:24.906852 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 10:55:24.910077 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 10:55:24.913424 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:55:24.913527
6251 10:55:24.916432 CA PerBit enable=1, Macro0, CA PI delay=36
6252 10:55:24.916523
6253 10:55:24.919719 [CBTSetCACLKResult] CA Dly = 36
6254 10:55:24.919821 CS Dly: 1 (0~32)
6255 10:55:24.923597
6256 10:55:24.926746 ----->DramcWriteLeveling(PI) begin...
6257 10:55:24.926878 ==
6258 10:55:24.929861 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 10:55:24.933078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 10:55:24.933205 ==
6261 10:55:24.936768 Write leveling (Byte 0): 40 => 8
6262 10:55:24.939753 Write leveling (Byte 1): 40 => 8
6263 10:55:24.943494 DramcWriteLeveling(PI) end<-----
6264 10:55:24.943595
6265 10:55:24.943665 ==
6266 10:55:24.946715 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 10:55:24.949961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 10:55:24.950047 ==
6269 10:55:24.953197 [Gating] SW mode calibration
6270 10:55:24.960070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 10:55:24.966163 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 10:55:24.969869 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 10:55:24.972926 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 10:55:24.979585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 10:55:24.983175 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 10:55:24.986135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 10:55:24.992905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 10:55:24.996323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 10:55:24.999263 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 10:55:25.005850 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 10:55:25.005928 Total UI for P1: 0, mck2ui 16
6282 10:55:25.009777 best dqsien dly found for B0: ( 0, 14, 24)
6283 10:55:25.012975 Total UI for P1: 0, mck2ui 16
6284 10:55:25.016157 best dqsien dly found for B1: ( 0, 14, 24)
6285 10:55:25.019374 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 10:55:25.026602 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 10:55:25.026687
6288 10:55:25.029501 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 10:55:25.032710 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 10:55:25.035900 [Gating] SW calibration Done
6291 10:55:25.035985 ==
6292 10:55:25.039527 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 10:55:25.042650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 10:55:25.042760 ==
6295 10:55:25.046303 RX Vref Scan: 0
6296 10:55:25.046398
6297 10:55:25.046460 RX Vref 0 -> 0, step: 1
6298 10:55:25.046518
6299 10:55:25.049424 RX Delay -410 -> 252, step: 16
6300 10:55:25.052704 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6301 10:55:25.059214 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6302 10:55:25.063099 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6303 10:55:25.066162 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6304 10:55:25.069272 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6305 10:55:25.075917 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6306 10:55:25.079049 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6307 10:55:25.082767 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6308 10:55:25.085825 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6309 10:55:25.092523 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6310 10:55:25.096231 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6311 10:55:25.099503 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6312 10:55:25.102741 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6313 10:55:25.109098 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6314 10:55:25.112927 iDelay=230, Bit 14, Center -3 (-234 ~ 229) 464
6315 10:55:25.116259 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6316 10:55:25.116362 ==
6317 10:55:25.119513 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 10:55:25.125888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 10:55:25.125969 ==
6320 10:55:25.126031 DQS Delay:
6321 10:55:25.126090 DQS0 = 27, DQS1 = 35
6322 10:55:25.129119 DQM Delay:
6323 10:55:25.129197 DQM0 = 10, DQM1 = 13
6324 10:55:25.132215 DQ Delay:
6325 10:55:25.136086 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6326 10:55:25.136165 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6327 10:55:25.139340 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6328 10:55:25.142514 DQ12 =16, DQ13 =16, DQ14 =32, DQ15 =16
6329 10:55:25.142592
6330 10:55:25.142654
6331 10:55:25.145618 ==
6332 10:55:25.148894 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 10:55:25.152641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 10:55:25.152720 ==
6335 10:55:25.152782
6336 10:55:25.152839
6337 10:55:25.155702 TX Vref Scan disable
6338 10:55:25.155781 == TX Byte 0 ==
6339 10:55:25.158926 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 10:55:25.165803 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 10:55:25.165882 == TX Byte 1 ==
6342 10:55:25.169175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 10:55:25.175452 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 10:55:25.175531 ==
6345 10:55:25.178988 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 10:55:25.182480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 10:55:25.182560 ==
6348 10:55:25.182622
6349 10:55:25.182680
6350 10:55:25.185684 TX Vref Scan disable
6351 10:55:25.185762 == TX Byte 0 ==
6352 10:55:25.189239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 10:55:25.195899 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 10:55:25.195979 == TX Byte 1 ==
6355 10:55:25.199293 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 10:55:25.205903 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 10:55:25.205982
6358 10:55:25.206044 [DATLAT]
6359 10:55:25.206103 Freq=400, CH0 RK0
6360 10:55:25.206159
6361 10:55:25.209094 DATLAT Default: 0xf
6362 10:55:25.209173 0, 0xFFFF, sum = 0
6363 10:55:25.212580 1, 0xFFFF, sum = 0
6364 10:55:25.215757 2, 0xFFFF, sum = 0
6365 10:55:25.215837 3, 0xFFFF, sum = 0
6366 10:55:25.218973 4, 0xFFFF, sum = 0
6367 10:55:25.219079 5, 0xFFFF, sum = 0
6368 10:55:25.222129 6, 0xFFFF, sum = 0
6369 10:55:25.222217 7, 0xFFFF, sum = 0
6370 10:55:25.225869 8, 0xFFFF, sum = 0
6371 10:55:25.225949 9, 0xFFFF, sum = 0
6372 10:55:25.229080 10, 0xFFFF, sum = 0
6373 10:55:25.229160 11, 0xFFFF, sum = 0
6374 10:55:25.232282 12, 0xFFFF, sum = 0
6375 10:55:25.232365 13, 0x0, sum = 1
6376 10:55:25.235544 14, 0x0, sum = 2
6377 10:55:25.235654 15, 0x0, sum = 3
6378 10:55:25.239427 16, 0x0, sum = 4
6379 10:55:25.239592 best_step = 14
6380 10:55:25.239684
6381 10:55:25.239771 ==
6382 10:55:25.242574 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 10:55:25.245810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 10:55:25.245906 ==
6385 10:55:25.249008 RX Vref Scan: 1
6386 10:55:25.249088
6387 10:55:25.252777 RX Vref 0 -> 0, step: 1
6388 10:55:25.252857
6389 10:55:25.252919 RX Delay -311 -> 252, step: 8
6390 10:55:25.252978
6391 10:55:25.255703 Set Vref, RX VrefLevel [Byte0]: 55
6392 10:55:25.258856 [Byte1]: 50
6393 10:55:25.264165
6394 10:55:25.264243 Final RX Vref Byte 0 = 55 to rank0
6395 10:55:25.267452 Final RX Vref Byte 1 = 50 to rank0
6396 10:55:25.271218 Final RX Vref Byte 0 = 55 to rank1
6397 10:55:25.274593 Final RX Vref Byte 1 = 50 to rank1==
6398 10:55:25.277687 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 10:55:25.284028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 10:55:25.284107 ==
6401 10:55:25.284169 DQS Delay:
6402 10:55:25.287561 DQS0 = 28, DQS1 = 36
6403 10:55:25.287640 DQM Delay:
6404 10:55:25.287702 DQM0 = 11, DQM1 = 12
6405 10:55:25.291106 DQ Delay:
6406 10:55:25.294081 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6407 10:55:25.294189 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6408 10:55:25.297792 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6409 10:55:25.300629 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6410 10:55:25.300733
6411 10:55:25.304157
6412 10:55:25.310551 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6413 10:55:25.314164 CH0 RK0: MR19=C0C, MR18=C8B4
6414 10:55:25.320540 CH0_RK0: MR19=0xC0C, MR18=0xC8B4, DQSOSC=385, MR23=63, INC=398, DEC=265
6415 10:55:25.320628 ==
6416 10:55:25.324366 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 10:55:25.327590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 10:55:25.327673 ==
6419 10:55:25.330721 [Gating] SW mode calibration
6420 10:55:25.337304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 10:55:25.344215 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 10:55:25.347366 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 10:55:25.350661 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 10:55:25.353882 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 10:55:25.360655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 10:55:25.364336 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 10:55:25.367681 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 10:55:25.374419 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 10:55:25.377563 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 10:55:25.380869 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 10:55:25.384158 Total UI for P1: 0, mck2ui 16
6432 10:55:25.387443 best dqsien dly found for B0: ( 0, 14, 24)
6433 10:55:25.390495 Total UI for P1: 0, mck2ui 16
6434 10:55:25.394281 best dqsien dly found for B1: ( 0, 14, 24)
6435 10:55:25.397329 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 10:55:25.400428 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 10:55:25.404143
6438 10:55:25.407659 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 10:55:25.410710 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 10:55:25.413665 [Gating] SW calibration Done
6441 10:55:25.413747 ==
6442 10:55:25.417141 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 10:55:25.420528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 10:55:25.420662 ==
6445 10:55:25.420764 RX Vref Scan: 0
6446 10:55:25.423965
6447 10:55:25.424048 RX Vref 0 -> 0, step: 1
6448 10:55:25.424131
6449 10:55:25.427299 RX Delay -410 -> 252, step: 16
6450 10:55:25.430396 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6451 10:55:25.437012 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6452 10:55:25.440193 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6453 10:55:25.443918 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6454 10:55:25.447005 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6455 10:55:25.453565 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6456 10:55:25.457371 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6457 10:55:25.460546 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6458 10:55:25.463807 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6459 10:55:25.470665 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6460 10:55:25.473663 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6461 10:55:25.476745 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6462 10:55:25.480054 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6463 10:55:25.487317 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6464 10:55:25.490405 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6465 10:55:25.493632 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6466 10:55:25.493713 ==
6467 10:55:25.497292 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 10:55:25.500466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 10:55:25.503752 ==
6470 10:55:25.503833 DQS Delay:
6471 10:55:25.503900 DQS0 = 27, DQS1 = 35
6472 10:55:25.506873 DQM Delay:
6473 10:55:25.506954 DQM0 = 12, DQM1 = 11
6474 10:55:25.510406 DQ Delay:
6475 10:55:25.510487 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6476 10:55:25.513444 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6477 10:55:25.517059 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6478 10:55:25.520060 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6479 10:55:25.520171
6480 10:55:25.520238
6481 10:55:25.520297 ==
6482 10:55:25.523647 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 10:55:25.530421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 10:55:25.530503 ==
6485 10:55:25.530568
6486 10:55:25.530626
6487 10:55:25.530684 TX Vref Scan disable
6488 10:55:25.533402 == TX Byte 0 ==
6489 10:55:25.536665 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6490 10:55:25.540027 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6491 10:55:25.543874 == TX Byte 1 ==
6492 10:55:25.547044 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6493 10:55:25.550115 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6494 10:55:25.553178 ==
6495 10:55:25.553260 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 10:55:25.560361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 10:55:25.560470 ==
6498 10:55:25.560563
6499 10:55:25.560651
6500 10:55:25.563602 TX Vref Scan disable
6501 10:55:25.563710 == TX Byte 0 ==
6502 10:55:25.566614 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6503 10:55:25.569984 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6504 10:55:25.573865 == TX Byte 1 ==
6505 10:55:25.576816 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 10:55:25.579937 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 10:55:25.583526
6508 10:55:25.583630 [DATLAT]
6509 10:55:25.583719 Freq=400, CH0 RK1
6510 10:55:25.583806
6511 10:55:25.586757 DATLAT Default: 0xe
6512 10:55:25.586852 0, 0xFFFF, sum = 0
6513 10:55:25.589977 1, 0xFFFF, sum = 0
6514 10:55:25.590049 2, 0xFFFF, sum = 0
6515 10:55:25.593114 3, 0xFFFF, sum = 0
6516 10:55:25.593219 4, 0xFFFF, sum = 0
6517 10:55:25.596390 5, 0xFFFF, sum = 0
6518 10:55:25.596470 6, 0xFFFF, sum = 0
6519 10:55:25.600144 7, 0xFFFF, sum = 0
6520 10:55:25.603233 8, 0xFFFF, sum = 0
6521 10:55:25.603371 9, 0xFFFF, sum = 0
6522 10:55:25.606499 10, 0xFFFF, sum = 0
6523 10:55:25.606596 11, 0xFFFF, sum = 0
6524 10:55:25.609841 12, 0xFFFF, sum = 0
6525 10:55:25.609938 13, 0x0, sum = 1
6526 10:55:25.612977 14, 0x0, sum = 2
6527 10:55:25.613076 15, 0x0, sum = 3
6528 10:55:25.616655 16, 0x0, sum = 4
6529 10:55:25.616738 best_step = 14
6530 10:55:25.616801
6531 10:55:25.616858 ==
6532 10:55:25.619707 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 10:55:25.623191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 10:55:25.623296 ==
6535 10:55:25.626230 RX Vref Scan: 0
6536 10:55:25.626313
6537 10:55:25.629748 RX Vref 0 -> 0, step: 1
6538 10:55:25.629855
6539 10:55:25.629951 RX Delay -311 -> 252, step: 8
6540 10:55:25.638770 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6541 10:55:25.642019 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6542 10:55:25.645280 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6543 10:55:25.648437 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6544 10:55:25.655268 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6545 10:55:25.658519 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6546 10:55:25.661713 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6547 10:55:25.664881 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6548 10:55:25.671867 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6549 10:55:25.674972 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6550 10:55:25.678181 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6551 10:55:25.681421 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6552 10:55:25.688248 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6553 10:55:25.692100 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6554 10:55:25.695153 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6555 10:55:25.701601 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6556 10:55:25.701679 ==
6557 10:55:25.704776 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 10:55:25.708548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 10:55:25.708633 ==
6560 10:55:25.708714 DQS Delay:
6561 10:55:25.711803 DQS0 = 24, DQS1 = 32
6562 10:55:25.711884 DQM Delay:
6563 10:55:25.715156 DQM0 = 8, DQM1 = 9
6564 10:55:25.715237 DQ Delay:
6565 10:55:25.718388 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6566 10:55:25.721840 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6567 10:55:25.724943 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6568 10:55:25.727883 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6569 10:55:25.727965
6570 10:55:25.728028
6571 10:55:25.735078 [DQSOSCAuto] RK1, (LSB)MR18= 0xb555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6572 10:55:25.738064 CH0 RK1: MR19=C0C, MR18=B555
6573 10:55:25.744779 CH0_RK1: MR19=0xC0C, MR18=0xB555, DQSOSC=387, MR23=63, INC=394, DEC=262
6574 10:55:25.748137 [RxdqsGatingPostProcess] freq 400
6575 10:55:25.751342 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 10:55:25.754578 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 10:55:25.758240 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 10:55:25.761396 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 10:55:25.764607 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 10:55:25.767812 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 10:55:25.771617 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 10:55:25.774811 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 10:55:25.778031 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 10:55:25.781308 Pre-setting of DQS Precalculation
6585 10:55:25.784546 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 10:55:25.788004 ==
6587 10:55:25.788119 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 10:55:25.794620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 10:55:25.794702 ==
6590 10:55:25.797711 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 10:55:25.804826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6592 10:55:25.807999 [CA 0] Center 36 (8~64) winsize 57
6593 10:55:25.811733 [CA 1] Center 36 (8~64) winsize 57
6594 10:55:25.814907 [CA 2] Center 36 (8~64) winsize 57
6595 10:55:25.818149 [CA 3] Center 36 (8~64) winsize 57
6596 10:55:25.821459 [CA 4] Center 36 (8~64) winsize 57
6597 10:55:25.824534 [CA 5] Center 36 (8~64) winsize 57
6598 10:55:25.824623
6599 10:55:25.828122 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6600 10:55:25.828203
6601 10:55:25.831180 [CATrainingPosCal] consider 1 rank data
6602 10:55:25.834168 u2DelayCellTimex100 = 270/100 ps
6603 10:55:25.837860 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 10:55:25.841389 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 10:55:25.844433 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 10:55:25.848071 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 10:55:25.851074 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 10:55:25.857445 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 10:55:25.857526
6610 10:55:25.860777 CA PerBit enable=1, Macro0, CA PI delay=36
6611 10:55:25.860858
6612 10:55:25.864442 [CBTSetCACLKResult] CA Dly = 36
6613 10:55:25.864523 CS Dly: 1 (0~32)
6614 10:55:25.864588 ==
6615 10:55:25.867634 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 10:55:25.870735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 10:55:25.874575 ==
6618 10:55:25.877806 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 10:55:25.884186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 10:55:25.887484 [CA 0] Center 36 (8~64) winsize 57
6621 10:55:25.890719 [CA 1] Center 36 (8~64) winsize 57
6622 10:55:25.894014 [CA 2] Center 36 (8~64) winsize 57
6623 10:55:25.897614 [CA 3] Center 36 (8~64) winsize 57
6624 10:55:25.900785 [CA 4] Center 36 (8~64) winsize 57
6625 10:55:25.903800 [CA 5] Center 36 (8~64) winsize 57
6626 10:55:25.903881
6627 10:55:25.907717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 10:55:25.907798
6629 10:55:25.910820 [CATrainingPosCal] consider 2 rank data
6630 10:55:25.913859 u2DelayCellTimex100 = 270/100 ps
6631 10:55:25.917020 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 10:55:25.920872 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 10:55:25.924139 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 10:55:25.927512 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 10:55:25.930630 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 10:55:25.933814 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:55:25.933895
6638 10:55:25.937458 CA PerBit enable=1, Macro0, CA PI delay=36
6639 10:55:25.940441
6640 10:55:25.940523 [CBTSetCACLKResult] CA Dly = 36
6641 10:55:25.944063 CS Dly: 1 (0~32)
6642 10:55:25.944136
6643 10:55:25.947056 ----->DramcWriteLeveling(PI) begin...
6644 10:55:25.947160 ==
6645 10:55:25.950753 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 10:55:25.953788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 10:55:25.953867 ==
6648 10:55:25.957464 Write leveling (Byte 0): 40 => 8
6649 10:55:25.960574 Write leveling (Byte 1): 40 => 8
6650 10:55:25.963737 DramcWriteLeveling(PI) end<-----
6651 10:55:25.963817
6652 10:55:25.963880 ==
6653 10:55:25.966844 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 10:55:25.970508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 10:55:25.970589 ==
6656 10:55:25.973800 [Gating] SW mode calibration
6657 10:55:25.980154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 10:55:25.987274 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 10:55:25.990554 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 10:55:25.996994 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 10:55:26.000210 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 10:55:26.003871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 10:55:26.010759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 10:55:26.013937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 10:55:26.017025 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 10:55:26.020235 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 10:55:26.027345 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 10:55:26.030558 Total UI for P1: 0, mck2ui 16
6669 10:55:26.033881 best dqsien dly found for B0: ( 0, 14, 24)
6670 10:55:26.036943 Total UI for P1: 0, mck2ui 16
6671 10:55:26.040646 best dqsien dly found for B1: ( 0, 14, 24)
6672 10:55:26.043811 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 10:55:26.047411 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 10:55:26.047493
6675 10:55:26.050420 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 10:55:26.054036 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 10:55:26.057128 [Gating] SW calibration Done
6678 10:55:26.057211 ==
6679 10:55:26.060672 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 10:55:26.063788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 10:55:26.063871 ==
6682 10:55:26.066875 RX Vref Scan: 0
6683 10:55:26.066981
6684 10:55:26.067076 RX Vref 0 -> 0, step: 1
6685 10:55:26.070598
6686 10:55:26.070673 RX Delay -410 -> 252, step: 16
6687 10:55:26.077297 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6688 10:55:26.080512 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6689 10:55:26.083677 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6690 10:55:26.086804 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6691 10:55:26.093853 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6692 10:55:26.097125 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6693 10:55:26.100475 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6694 10:55:26.103661 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6695 10:55:26.110005 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6696 10:55:26.113648 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6697 10:55:26.116775 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6698 10:55:26.119891 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6699 10:55:26.126755 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6700 10:55:26.130049 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6701 10:55:26.133249 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6702 10:55:26.139775 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6703 10:55:26.139859 ==
6704 10:55:26.143010 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 10:55:26.146582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 10:55:26.146665 ==
6707 10:55:26.146731 DQS Delay:
6708 10:55:26.149661 DQS0 = 35, DQS1 = 35
6709 10:55:26.149743 DQM Delay:
6710 10:55:26.153344 DQM0 = 17, DQM1 = 13
6711 10:55:26.153426 DQ Delay:
6712 10:55:26.156461 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6713 10:55:26.159939 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6714 10:55:26.163533 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6715 10:55:26.166712 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6716 10:55:26.166811
6717 10:55:26.166908
6718 10:55:26.166983 ==
6719 10:55:26.169677 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 10:55:26.173463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 10:55:26.173547 ==
6722 10:55:26.173612
6723 10:55:26.173671
6724 10:55:26.176481 TX Vref Scan disable
6725 10:55:26.176563 == TX Byte 0 ==
6726 10:55:26.183463 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 10:55:26.186557 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 10:55:26.186640 == TX Byte 1 ==
6729 10:55:26.193280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 10:55:26.196642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 10:55:26.196729 ==
6732 10:55:26.199775 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 10:55:26.202991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 10:55:26.203074 ==
6735 10:55:26.203139
6736 10:55:26.203200
6737 10:55:26.206731 TX Vref Scan disable
6738 10:55:26.206813 == TX Byte 0 ==
6739 10:55:26.213102 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 10:55:26.216858 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 10:55:26.216940 == TX Byte 1 ==
6742 10:55:26.223027 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 10:55:26.226201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 10:55:26.226288
6745 10:55:26.226354 [DATLAT]
6746 10:55:26.229942 Freq=400, CH1 RK0
6747 10:55:26.230024
6748 10:55:26.230095 DATLAT Default: 0xf
6749 10:55:26.233208 0, 0xFFFF, sum = 0
6750 10:55:26.233291 1, 0xFFFF, sum = 0
6751 10:55:26.236361 2, 0xFFFF, sum = 0
6752 10:55:26.236444 3, 0xFFFF, sum = 0
6753 10:55:26.239514 4, 0xFFFF, sum = 0
6754 10:55:26.239587 5, 0xFFFF, sum = 0
6755 10:55:26.243330 6, 0xFFFF, sum = 0
6756 10:55:26.243418 7, 0xFFFF, sum = 0
6757 10:55:26.246572 8, 0xFFFF, sum = 0
6758 10:55:26.249691 9, 0xFFFF, sum = 0
6759 10:55:26.249774 10, 0xFFFF, sum = 0
6760 10:55:26.253339 11, 0xFFFF, sum = 0
6761 10:55:26.253423 12, 0xFFFF, sum = 0
6762 10:55:26.256391 13, 0x0, sum = 1
6763 10:55:26.256474 14, 0x0, sum = 2
6764 10:55:26.259882 15, 0x0, sum = 3
6765 10:55:26.259956 16, 0x0, sum = 4
6766 10:55:26.260020 best_step = 14
6767 10:55:26.260079
6768 10:55:26.262885 ==
6769 10:55:26.266531 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 10:55:26.270127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 10:55:26.270200 ==
6772 10:55:26.270262 RX Vref Scan: 1
6773 10:55:26.270321
6774 10:55:26.273210 RX Vref 0 -> 0, step: 1
6775 10:55:26.273292
6776 10:55:26.276214 RX Delay -311 -> 252, step: 8
6777 10:55:26.276296
6778 10:55:26.280101 Set Vref, RX VrefLevel [Byte0]: 55
6779 10:55:26.283068 [Byte1]: 52
6780 10:55:26.286520
6781 10:55:26.286604 Final RX Vref Byte 0 = 55 to rank0
6782 10:55:26.290054 Final RX Vref Byte 1 = 52 to rank0
6783 10:55:26.293247 Final RX Vref Byte 0 = 55 to rank1
6784 10:55:26.296418 Final RX Vref Byte 1 = 52 to rank1==
6785 10:55:26.300201 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 10:55:26.303416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 10:55:26.306605 ==
6788 10:55:26.306687 DQS Delay:
6789 10:55:26.306752 DQS0 = 28, DQS1 = 32
6790 10:55:26.309926 DQM Delay:
6791 10:55:26.310009 DQM0 = 9, DQM1 = 11
6792 10:55:26.313153 DQ Delay:
6793 10:55:26.313287 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6794 10:55:26.316485 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6795 10:55:26.320203 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6796 10:55:26.323268 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6797 10:55:26.323401
6798 10:55:26.323466
6799 10:55:26.332981 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6800 10:55:26.336270 CH1 RK0: MR19=C0C, MR18=90C8
6801 10:55:26.340156 CH1_RK0: MR19=0xC0C, MR18=0x90C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6802 10:55:26.342821 ==
6803 10:55:26.346609 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 10:55:26.349891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 10:55:26.349974 ==
6806 10:55:26.353104 [Gating] SW mode calibration
6807 10:55:26.359934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 10:55:26.363118 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 10:55:26.369632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 10:55:26.373131 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 10:55:26.376580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 10:55:26.382926 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 10:55:26.385940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 10:55:26.389741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 10:55:26.395980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 10:55:26.399267 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 10:55:26.403109 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 10:55:26.406437 Total UI for P1: 0, mck2ui 16
6819 10:55:26.409637 best dqsien dly found for B0: ( 0, 14, 24)
6820 10:55:26.412937 Total UI for P1: 0, mck2ui 16
6821 10:55:26.416124 best dqsien dly found for B1: ( 0, 14, 24)
6822 10:55:26.419917 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 10:55:26.423083 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 10:55:26.423167
6825 10:55:26.429605 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 10:55:26.433307 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 10:55:26.433390 [Gating] SW calibration Done
6828 10:55:26.436373 ==
6829 10:55:26.436456 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 10:55:26.442679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 10:55:26.442762 ==
6832 10:55:26.442827 RX Vref Scan: 0
6833 10:55:26.442889
6834 10:55:26.446590 RX Vref 0 -> 0, step: 1
6835 10:55:26.446672
6836 10:55:26.449866 RX Delay -410 -> 252, step: 16
6837 10:55:26.453076 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6838 10:55:26.456222 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6839 10:55:26.463167 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6840 10:55:26.466162 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6841 10:55:26.469229 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6842 10:55:26.472913 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6843 10:55:26.479822 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6844 10:55:26.482682 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6845 10:55:26.486492 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6846 10:55:26.489474 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6847 10:55:26.496242 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6848 10:55:26.499415 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6849 10:55:26.502446 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6850 10:55:26.506068 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6851 10:55:26.512479 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6852 10:55:26.515719 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6853 10:55:26.515834 ==
6854 10:55:26.518984 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 10:55:26.522807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 10:55:26.522925 ==
6857 10:55:26.526115 DQS Delay:
6858 10:55:26.526230 DQS0 = 27, DQS1 = 35
6859 10:55:26.529303 DQM Delay:
6860 10:55:26.529419 DQM0 = 11, DQM1 = 15
6861 10:55:26.529521 DQ Delay:
6862 10:55:26.532535 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6863 10:55:26.535753 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6864 10:55:26.539287 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6865 10:55:26.542260 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6866 10:55:26.542372
6867 10:55:26.542478
6868 10:55:26.542577 ==
6869 10:55:26.545943 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 10:55:26.552403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 10:55:26.552520 ==
6872 10:55:26.552626
6873 10:55:26.552727
6874 10:55:26.552825 TX Vref Scan disable
6875 10:55:26.555533 == TX Byte 0 ==
6876 10:55:26.558857 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6877 10:55:26.562797 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6878 10:55:26.566005 == TX Byte 1 ==
6879 10:55:26.569061 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6880 10:55:26.572222 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6881 10:55:26.572334 ==
6882 10:55:26.575829 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 10:55:26.582561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 10:55:26.582676 ==
6885 10:55:26.582783
6886 10:55:26.582885
6887 10:55:26.582984 TX Vref Scan disable
6888 10:55:26.585603 == TX Byte 0 ==
6889 10:55:26.589169 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 10:55:26.592965 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 10:55:26.596090 == TX Byte 1 ==
6892 10:55:26.599049 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 10:55:26.602170 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 10:55:26.602287
6895 10:55:26.606039 [DATLAT]
6896 10:55:26.606150 Freq=400, CH1 RK1
6897 10:55:26.606255
6898 10:55:26.609022 DATLAT Default: 0xe
6899 10:55:26.609134 0, 0xFFFF, sum = 0
6900 10:55:26.612790 1, 0xFFFF, sum = 0
6901 10:55:26.612905 2, 0xFFFF, sum = 0
6902 10:55:26.616047 3, 0xFFFF, sum = 0
6903 10:55:26.616163 4, 0xFFFF, sum = 0
6904 10:55:26.619266 5, 0xFFFF, sum = 0
6905 10:55:26.619420 6, 0xFFFF, sum = 0
6906 10:55:26.622519 7, 0xFFFF, sum = 0
6907 10:55:26.622634 8, 0xFFFF, sum = 0
6908 10:55:26.625769 9, 0xFFFF, sum = 0
6909 10:55:26.625888 10, 0xFFFF, sum = 0
6910 10:55:26.628993 11, 0xFFFF, sum = 0
6911 10:55:26.629110 12, 0xFFFF, sum = 0
6912 10:55:26.632224 13, 0x0, sum = 1
6913 10:55:26.632339 14, 0x0, sum = 2
6914 10:55:26.635546 15, 0x0, sum = 3
6915 10:55:26.635663 16, 0x0, sum = 4
6916 10:55:26.639091 best_step = 14
6917 10:55:26.639208
6918 10:55:26.639310 ==
6919 10:55:26.642117 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 10:55:26.645410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 10:55:26.645522 ==
6922 10:55:26.648940 RX Vref Scan: 0
6923 10:55:26.649054
6924 10:55:26.649160 RX Vref 0 -> 0, step: 1
6925 10:55:26.649260
6926 10:55:26.651859 RX Delay -311 -> 252, step: 8
6927 10:55:26.660070 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6928 10:55:26.663473 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6929 10:55:26.666871 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6930 10:55:26.670003 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6931 10:55:26.676708 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6932 10:55:26.680321 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6933 10:55:26.683481 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6934 10:55:26.686358 iDelay=217, Bit 7, Center -20 (-247 ~ 208) 456
6935 10:55:26.693033 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6936 10:55:26.696576 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6937 10:55:26.700467 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6938 10:55:26.703584 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6939 10:55:26.710198 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6940 10:55:26.713241 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6941 10:55:26.716913 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6942 10:55:26.720158 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6943 10:55:26.723410 ==
6944 10:55:26.726646 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 10:55:26.729927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 10:55:26.730011 ==
6947 10:55:26.730085 DQS Delay:
6948 10:55:26.733134 DQS0 = 28, DQS1 = 36
6949 10:55:26.733209 DQM Delay:
6950 10:55:26.736421 DQM0 = 10, DQM1 = 14
6951 10:55:26.736489 DQ Delay:
6952 10:55:26.739708 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6953 10:55:26.743444 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6954 10:55:26.746492 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6955 10:55:26.749714 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6956 10:55:26.749790
6957 10:55:26.749859
6958 10:55:26.756675 [DQSOSCAuto] RK1, (LSB)MR18= 0xc356, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6959 10:55:26.759812 CH1 RK1: MR19=C0C, MR18=C356
6960 10:55:26.766863 CH1_RK1: MR19=0xC0C, MR18=0xC356, DQSOSC=385, MR23=63, INC=398, DEC=265
6961 10:55:26.770015 [RxdqsGatingPostProcess] freq 400
6962 10:55:26.773318 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 10:55:26.776427 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 10:55:26.779649 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 10:55:26.783191 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 10:55:26.786749 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 10:55:26.789770 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 10:55:26.793505 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 10:55:26.796560 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 10:55:26.800068 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 10:55:26.803070 Pre-setting of DQS Precalculation
6972 10:55:26.806636 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 10:55:26.816279 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 10:55:26.822936 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 10:55:26.823047
6976 10:55:26.823140
6977 10:55:26.826772 [Calibration Summary] 800 Mbps
6978 10:55:26.826853 CH 0, Rank 0
6979 10:55:26.829872 SW Impedance : PASS
6980 10:55:26.829941 DUTY Scan : NO K
6981 10:55:26.833242 ZQ Calibration : PASS
6982 10:55:26.836535 Jitter Meter : NO K
6983 10:55:26.836609 CBT Training : PASS
6984 10:55:26.839812 Write leveling : PASS
6985 10:55:26.839886 RX DQS gating : PASS
6986 10:55:26.842965 RX DQ/DQS(RDDQC) : PASS
6987 10:55:26.846898 TX DQ/DQS : PASS
6988 10:55:26.846995 RX DATLAT : PASS
6989 10:55:26.850101 RX DQ/DQS(Engine): PASS
6990 10:55:26.853151 TX OE : NO K
6991 10:55:26.853248 All Pass.
6992 10:55:26.853343
6993 10:55:26.853429 CH 0, Rank 1
6994 10:55:26.856437 SW Impedance : PASS
6995 10:55:26.860030 DUTY Scan : NO K
6996 10:55:26.860158 ZQ Calibration : PASS
6997 10:55:26.863436 Jitter Meter : NO K
6998 10:55:26.866650 CBT Training : PASS
6999 10:55:26.866729 Write leveling : NO K
7000 10:55:26.869691 RX DQS gating : PASS
7001 10:55:26.873003 RX DQ/DQS(RDDQC) : PASS
7002 10:55:26.873090 TX DQ/DQS : PASS
7003 10:55:26.876197 RX DATLAT : PASS
7004 10:55:26.879491 RX DQ/DQS(Engine): PASS
7005 10:55:26.879566 TX OE : NO K
7006 10:55:26.882729 All Pass.
7007 10:55:26.882813
7008 10:55:26.882873 CH 1, Rank 0
7009 10:55:26.886564 SW Impedance : PASS
7010 10:55:26.886658 DUTY Scan : NO K
7011 10:55:26.889770 ZQ Calibration : PASS
7012 10:55:26.892724 Jitter Meter : NO K
7013 10:55:26.892795 CBT Training : PASS
7014 10:55:26.896087 Write leveling : PASS
7015 10:55:26.896191 RX DQS gating : PASS
7016 10:55:26.899609 RX DQ/DQS(RDDQC) : PASS
7017 10:55:26.902710 TX DQ/DQS : PASS
7018 10:55:26.902782 RX DATLAT : PASS
7019 10:55:26.906380 RX DQ/DQS(Engine): PASS
7020 10:55:26.909305 TX OE : NO K
7021 10:55:26.909380 All Pass.
7022 10:55:26.909449
7023 10:55:26.909506 CH 1, Rank 1
7024 10:55:26.912657 SW Impedance : PASS
7025 10:55:26.916286 DUTY Scan : NO K
7026 10:55:26.916361 ZQ Calibration : PASS
7027 10:55:26.919737 Jitter Meter : NO K
7028 10:55:26.922940 CBT Training : PASS
7029 10:55:26.923045 Write leveling : NO K
7030 10:55:26.925994 RX DQS gating : PASS
7031 10:55:26.929775 RX DQ/DQS(RDDQC) : PASS
7032 10:55:26.929849 TX DQ/DQS : PASS
7033 10:55:26.932840 RX DATLAT : PASS
7034 10:55:26.936039 RX DQ/DQS(Engine): PASS
7035 10:55:26.936109 TX OE : NO K
7036 10:55:26.936175 All Pass.
7037 10:55:26.939786
7038 10:55:26.939866 DramC Write-DBI off
7039 10:55:26.942968 PER_BANK_REFRESH: Hybrid Mode
7040 10:55:26.943034 TX_TRACKING: ON
7041 10:55:26.952814 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 10:55:26.955956 [FAST_K] Save calibration result to emmc
7043 10:55:26.959236 dramc_set_vcore_voltage set vcore to 725000
7044 10:55:26.962909 Read voltage for 1600, 0
7045 10:55:26.963022 Vio18 = 0
7046 10:55:26.966091 Vcore = 725000
7047 10:55:26.966194 Vdram = 0
7048 10:55:26.966283 Vddq = 0
7049 10:55:26.966368 Vmddr = 0
7050 10:55:26.972368 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 10:55:26.979281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 10:55:26.979405 MEM_TYPE=3, freq_sel=13
7053 10:55:26.982546 sv_algorithm_assistance_LP4_3733
7054 10:55:26.985856 ============ PULL DRAM RESETB DOWN ============
7055 10:55:26.992281 ========== PULL DRAM RESETB DOWN end =========
7056 10:55:26.995988 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 10:55:26.999186 ===================================
7058 10:55:27.002134 LPDDR4 DRAM CONFIGURATION
7059 10:55:27.005825 ===================================
7060 10:55:27.005901 EX_ROW_EN[0] = 0x0
7061 10:55:27.008800 EX_ROW_EN[1] = 0x0
7062 10:55:27.012448 LP4Y_EN = 0x0
7063 10:55:27.012549 WORK_FSP = 0x1
7064 10:55:27.015381 WL = 0x5
7065 10:55:27.015488 RL = 0x5
7066 10:55:27.018859 BL = 0x2
7067 10:55:27.018960 RPST = 0x0
7068 10:55:27.022331 RD_PRE = 0x0
7069 10:55:27.022442 WR_PRE = 0x1
7070 10:55:27.025240 WR_PST = 0x1
7071 10:55:27.025310 DBI_WR = 0x0
7072 10:55:27.028869 DBI_RD = 0x0
7073 10:55:27.028945 OTF = 0x1
7074 10:55:27.032356 ===================================
7075 10:55:27.035539 ===================================
7076 10:55:27.038648 ANA top config
7077 10:55:27.041811 ===================================
7078 10:55:27.041888 DLL_ASYNC_EN = 0
7079 10:55:27.045145 ALL_SLAVE_EN = 0
7080 10:55:27.048915 NEW_RANK_MODE = 1
7081 10:55:27.052056 DLL_IDLE_MODE = 1
7082 10:55:27.055266 LP45_APHY_COMB_EN = 1
7083 10:55:27.055391 TX_ODT_DIS = 0
7084 10:55:27.058497 NEW_8X_MODE = 1
7085 10:55:27.062387 ===================================
7086 10:55:27.065548 ===================================
7087 10:55:27.069122 data_rate = 3200
7088 10:55:27.072186 CKR = 1
7089 10:55:27.075481 DQ_P2S_RATIO = 8
7090 10:55:27.079063 ===================================
7091 10:55:27.079143 CA_P2S_RATIO = 8
7092 10:55:27.082158 DQ_CA_OPEN = 0
7093 10:55:27.085382 DQ_SEMI_OPEN = 0
7094 10:55:27.088619 CA_SEMI_OPEN = 0
7095 10:55:27.091920 CA_FULL_RATE = 0
7096 10:55:27.095220 DQ_CKDIV4_EN = 0
7097 10:55:27.095314 CA_CKDIV4_EN = 0
7098 10:55:27.098496 CA_PREDIV_EN = 0
7099 10:55:27.102409 PH8_DLY = 12
7100 10:55:27.105387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 10:55:27.108592 DQ_AAMCK_DIV = 4
7102 10:55:27.112430 CA_AAMCK_DIV = 4
7103 10:55:27.112510 CA_ADMCK_DIV = 4
7104 10:55:27.115304 DQ_TRACK_CA_EN = 0
7105 10:55:27.118772 CA_PICK = 1600
7106 10:55:27.121980 CA_MCKIO = 1600
7107 10:55:27.125561 MCKIO_SEMI = 0
7108 10:55:27.128502 PLL_FREQ = 3068
7109 10:55:27.132105 DQ_UI_PI_RATIO = 32
7110 10:55:27.132190 CA_UI_PI_RATIO = 0
7111 10:55:27.135031 ===================================
7112 10:55:27.138517 ===================================
7113 10:55:27.142148 memory_type:LPDDR4
7114 10:55:27.145337 GP_NUM : 10
7115 10:55:27.145446 SRAM_EN : 1
7116 10:55:27.148352 MD32_EN : 0
7117 10:55:27.152079 ===================================
7118 10:55:27.155515 [ANA_INIT] >>>>>>>>>>>>>>
7119 10:55:27.158643 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 10:55:27.161825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 10:55:27.164951 ===================================
7122 10:55:27.165035 data_rate = 3200,PCW = 0X7600
7123 10:55:27.168785 ===================================
7124 10:55:27.171963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 10:55:27.178495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 10:55:27.185440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 10:55:27.188692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 10:55:27.191977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 10:55:27.195186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 10:55:27.198418 [ANA_INIT] flow start
7131 10:55:27.201744 [ANA_INIT] PLL >>>>>>>>
7132 10:55:27.201851 [ANA_INIT] PLL <<<<<<<<
7133 10:55:27.204942 [ANA_INIT] MIDPI >>>>>>>>
7134 10:55:27.208133 [ANA_INIT] MIDPI <<<<<<<<
7135 10:55:27.208215 [ANA_INIT] DLL >>>>>>>>
7136 10:55:27.211464 [ANA_INIT] DLL <<<<<<<<
7137 10:55:27.215282 [ANA_INIT] flow end
7138 10:55:27.218209 ============ LP4 DIFF to SE enter ============
7139 10:55:27.221379 ============ LP4 DIFF to SE exit ============
7140 10:55:27.225140 [ANA_INIT] <<<<<<<<<<<<<
7141 10:55:27.228233 [Flow] Enable top DCM control >>>>>
7142 10:55:27.231792 [Flow] Enable top DCM control <<<<<
7143 10:55:27.234914 Enable DLL master slave shuffle
7144 10:55:27.238463 ==============================================================
7145 10:55:27.241246 Gating Mode config
7146 10:55:27.244724 ==============================================================
7147 10:55:27.248551 Config description:
7148 10:55:27.258178 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 10:55:27.264696 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 10:55:27.268501 SELPH_MODE 0: By rank 1: By Phase
7151 10:55:27.274922 ==============================================================
7152 10:55:27.278093 GAT_TRACK_EN = 1
7153 10:55:27.281871 RX_GATING_MODE = 2
7154 10:55:27.284872 RX_GATING_TRACK_MODE = 2
7155 10:55:27.288014 SELPH_MODE = 1
7156 10:55:27.291720 PICG_EARLY_EN = 1
7157 10:55:27.291802 VALID_LAT_VALUE = 1
7158 10:55:27.298132 ==============================================================
7159 10:55:27.301406 Enter into Gating configuration >>>>
7160 10:55:27.304580 Exit from Gating configuration <<<<
7161 10:55:27.308473 Enter into DVFS_PRE_config >>>>>
7162 10:55:27.317894 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 10:55:27.321777 Exit from DVFS_PRE_config <<<<<
7164 10:55:27.324787 Enter into PICG configuration >>>>
7165 10:55:27.327974 Exit from PICG configuration <<<<
7166 10:55:27.331192 [RX_INPUT] configuration >>>>>
7167 10:55:27.334610 [RX_INPUT] configuration <<<<<
7168 10:55:27.341139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 10:55:27.344742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 10:55:27.351346 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 10:55:27.357702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 10:55:27.364477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 10:55:27.371034 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 10:55:27.374260 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 10:55:27.377499 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 10:55:27.381427 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 10:55:27.387508 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 10:55:27.390788 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 10:55:27.394520 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 10:55:27.397583 ===================================
7181 10:55:27.400852 LPDDR4 DRAM CONFIGURATION
7182 10:55:27.404820 ===================================
7183 10:55:27.404895 EX_ROW_EN[0] = 0x0
7184 10:55:27.408016 EX_ROW_EN[1] = 0x0
7185 10:55:27.408088 LP4Y_EN = 0x0
7186 10:55:27.411242 WORK_FSP = 0x1
7187 10:55:27.411346 WL = 0x5
7188 10:55:27.414406 RL = 0x5
7189 10:55:27.414478 BL = 0x2
7190 10:55:27.417557 RPST = 0x0
7191 10:55:27.420737 RD_PRE = 0x0
7192 10:55:27.420834 WR_PRE = 0x1
7193 10:55:27.424540 WR_PST = 0x1
7194 10:55:27.424631 DBI_WR = 0x0
7195 10:55:27.427693 DBI_RD = 0x0
7196 10:55:27.427775 OTF = 0x1
7197 10:55:27.430918 ===================================
7198 10:55:27.434186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 10:55:27.441174 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 10:55:27.444189 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 10:55:27.447939 ===================================
7202 10:55:27.450983 LPDDR4 DRAM CONFIGURATION
7203 10:55:27.454609 ===================================
7204 10:55:27.454726 EX_ROW_EN[0] = 0x10
7205 10:55:27.457562 EX_ROW_EN[1] = 0x0
7206 10:55:27.457669 LP4Y_EN = 0x0
7207 10:55:27.461149 WORK_FSP = 0x1
7208 10:55:27.461256 WL = 0x5
7209 10:55:27.464110 RL = 0x5
7210 10:55:27.464183 BL = 0x2
7211 10:55:27.467274 RPST = 0x0
7212 10:55:27.467434 RD_PRE = 0x0
7213 10:55:27.470898 WR_PRE = 0x1
7214 10:55:27.474056 WR_PST = 0x1
7215 10:55:27.474138 DBI_WR = 0x0
7216 10:55:27.477296 DBI_RD = 0x0
7217 10:55:27.477394 OTF = 0x1
7218 10:55:27.480420 ===================================
7219 10:55:27.487509 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 10:55:27.487616 ==
7221 10:55:27.490510 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 10:55:27.493663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 10:55:27.493763 ==
7224 10:55:27.496893 [Duty_Offset_Calibration]
7225 10:55:27.500642 B0:2 B1:1 CA:1
7226 10:55:27.500722
7227 10:55:27.503761 [DutyScan_Calibration_Flow] k_type=0
7228 10:55:27.512129
7229 10:55:27.512208 ==CLK 0==
7230 10:55:27.515387 Final CLK duty delay cell = 0
7231 10:55:27.518496 [0] MAX Duty = 5156%(X100), DQS PI = 22
7232 10:55:27.522232 [0] MIN Duty = 4907%(X100), DQS PI = 0
7233 10:55:27.522313 [0] AVG Duty = 5031%(X100)
7234 10:55:27.522377
7235 10:55:27.525496 CH0 CLK Duty spec in!! Max-Min= 249%
7236 10:55:27.531826 [DutyScan_Calibration_Flow] ====Done====
7237 10:55:27.531906
7238 10:55:27.534926 [DutyScan_Calibration_Flow] k_type=1
7239 10:55:27.551367
7240 10:55:27.551448 ==DQS 0 ==
7241 10:55:27.554309 Final DQS duty delay cell = -4
7242 10:55:27.558142 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7243 10:55:27.561011 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7244 10:55:27.564468 [-4] AVG Duty = 4922%(X100)
7245 10:55:27.564551
7246 10:55:27.564615 ==DQS 1 ==
7247 10:55:27.567487 Final DQS duty delay cell = 0
7248 10:55:27.571458 [0] MAX Duty = 5187%(X100), DQS PI = 20
7249 10:55:27.574439 [0] MIN Duty = 5031%(X100), DQS PI = 52
7250 10:55:27.577977 [0] AVG Duty = 5109%(X100)
7251 10:55:27.578057
7252 10:55:27.581216 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7253 10:55:27.581297
7254 10:55:27.584382 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7255 10:55:27.587834 [DutyScan_Calibration_Flow] ====Done====
7256 10:55:27.587915
7257 10:55:27.591087 [DutyScan_Calibration_Flow] k_type=3
7258 10:55:27.607990
7259 10:55:27.608072 ==DQM 0 ==
7260 10:55:27.610897 Final DQM duty delay cell = 0
7261 10:55:27.614489 [0] MAX Duty = 5218%(X100), DQS PI = 32
7262 10:55:27.617671 [0] MIN Duty = 4907%(X100), DQS PI = 56
7263 10:55:27.620953 [0] AVG Duty = 5062%(X100)
7264 10:55:27.621049
7265 10:55:27.621145 ==DQM 1 ==
7266 10:55:27.624134 Final DQM duty delay cell = -4
7267 10:55:27.627906 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7268 10:55:27.631070 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7269 10:55:27.634164 [-4] AVG Duty = 4906%(X100)
7270 10:55:27.634278
7271 10:55:27.637911 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7272 10:55:27.637993
7273 10:55:27.640826 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7274 10:55:27.643971 [DutyScan_Calibration_Flow] ====Done====
7275 10:55:27.644052
7276 10:55:27.647905 [DutyScan_Calibration_Flow] k_type=2
7277 10:55:27.665168
7278 10:55:27.665251 ==DQ 0 ==
7279 10:55:27.668815 Final DQ duty delay cell = 0
7280 10:55:27.671798 [0] MAX Duty = 5062%(X100), DQS PI = 24
7281 10:55:27.675442 [0] MIN Duty = 4907%(X100), DQS PI = 0
7282 10:55:27.675550 [0] AVG Duty = 4984%(X100)
7283 10:55:27.678305
7284 10:55:27.678403 ==DQ 1 ==
7285 10:55:27.681574 Final DQ duty delay cell = 0
7286 10:55:27.685070 [0] MAX Duty = 5125%(X100), DQS PI = 6
7287 10:55:27.688387 [0] MIN Duty = 4907%(X100), DQS PI = 34
7288 10:55:27.688472 [0] AVG Duty = 5016%(X100)
7289 10:55:27.688557
7290 10:55:27.691685 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7291 10:55:27.694866
7292 10:55:27.698469 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7293 10:55:27.701695 [DutyScan_Calibration_Flow] ====Done====
7294 10:55:27.701776 ==
7295 10:55:27.704981 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 10:55:27.708213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 10:55:27.708322 ==
7298 10:55:27.711394 [Duty_Offset_Calibration]
7299 10:55:27.711474 B0:1 B1:0 CA:0
7300 10:55:27.711537
7301 10:55:27.715033 [DutyScan_Calibration_Flow] k_type=0
7302 10:55:27.724457
7303 10:55:27.724571 ==CLK 0==
7304 10:55:27.727607 Final CLK duty delay cell = -4
7305 10:55:27.731422 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7306 10:55:27.734648 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7307 10:55:27.737922 [-4] AVG Duty = 4922%(X100)
7308 10:55:27.738002
7309 10:55:27.741222 CH1 CLK Duty spec in!! Max-Min= 156%
7310 10:55:27.744876 [DutyScan_Calibration_Flow] ====Done====
7311 10:55:27.744956
7312 10:55:27.747943 [DutyScan_Calibration_Flow] k_type=1
7313 10:55:27.764623
7314 10:55:27.764703 ==DQS 0 ==
7315 10:55:27.768401 Final DQS duty delay cell = 0
7316 10:55:27.771305 [0] MAX Duty = 5094%(X100), DQS PI = 16
7317 10:55:27.774450 [0] MIN Duty = 4844%(X100), DQS PI = 48
7318 10:55:27.774527 [0] AVG Duty = 4969%(X100)
7319 10:55:27.778061
7320 10:55:27.778140 ==DQS 1 ==
7321 10:55:27.781546 Final DQS duty delay cell = 0
7322 10:55:27.784554 [0] MAX Duty = 5249%(X100), DQS PI = 18
7323 10:55:27.788220 [0] MIN Duty = 4969%(X100), DQS PI = 8
7324 10:55:27.788300 [0] AVG Duty = 5109%(X100)
7325 10:55:27.791451
7326 10:55:27.794635 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7327 10:55:27.794745
7328 10:55:27.797895 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7329 10:55:27.800944 [DutyScan_Calibration_Flow] ====Done====
7330 10:55:27.801024
7331 10:55:27.804686 [DutyScan_Calibration_Flow] k_type=3
7332 10:55:27.821275
7333 10:55:27.821355 ==DQM 0 ==
7334 10:55:27.824893 Final DQM duty delay cell = 0
7335 10:55:27.828095 [0] MAX Duty = 5218%(X100), DQS PI = 18
7336 10:55:27.831801 [0] MIN Duty = 4969%(X100), DQS PI = 48
7337 10:55:27.834759 [0] AVG Duty = 5093%(X100)
7338 10:55:27.834839
7339 10:55:27.834903 ==DQM 1 ==
7340 10:55:27.838025 Final DQM duty delay cell = 0
7341 10:55:27.841346 [0] MAX Duty = 5093%(X100), DQS PI = 18
7342 10:55:27.845075 [0] MIN Duty = 4907%(X100), DQS PI = 34
7343 10:55:27.848090 [0] AVG Duty = 5000%(X100)
7344 10:55:27.848170
7345 10:55:27.851891 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7346 10:55:27.851972
7347 10:55:27.855109 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7348 10:55:27.858395 [DutyScan_Calibration_Flow] ====Done====
7349 10:55:27.858476
7350 10:55:27.861540 [DutyScan_Calibration_Flow] k_type=2
7351 10:55:27.877454
7352 10:55:27.877534 ==DQ 0 ==
7353 10:55:27.881022 Final DQ duty delay cell = -4
7354 10:55:27.884183 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7355 10:55:27.887828 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7356 10:55:27.890787 [-4] AVG Duty = 4968%(X100)
7357 10:55:27.890867
7358 10:55:27.890929 ==DQ 1 ==
7359 10:55:27.893919 Final DQ duty delay cell = 0
7360 10:55:27.897625 [0] MAX Duty = 5124%(X100), DQS PI = 16
7361 10:55:27.900643 [0] MIN Duty = 4938%(X100), DQS PI = 10
7362 10:55:27.904422 [0] AVG Duty = 5031%(X100)
7363 10:55:27.904502
7364 10:55:27.907605 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7365 10:55:27.907685
7366 10:55:27.910863 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7367 10:55:27.914009 [DutyScan_Calibration_Flow] ====Done====
7368 10:55:27.917254 nWR fixed to 30
7369 10:55:27.920860 [ModeRegInit_LP4] CH0 RK0
7370 10:55:27.920979 [ModeRegInit_LP4] CH0 RK1
7371 10:55:27.924078 [ModeRegInit_LP4] CH1 RK0
7372 10:55:27.927159 [ModeRegInit_LP4] CH1 RK1
7373 10:55:27.927232 match AC timing 5
7374 10:55:27.933872 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 10:55:27.936950 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 10:55:27.940793 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 10:55:27.947224 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 10:55:27.950470 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 10:55:27.950556 [MiockJmeterHQA]
7380 10:55:27.950641
7381 10:55:27.953626 [DramcMiockJmeter] u1RxGatingPI = 0
7382 10:55:27.957455 0 : 4253, 4026
7383 10:55:27.957563 4 : 4363, 4137
7384 10:55:27.960558 8 : 4252, 4027
7385 10:55:27.960632 12 : 4252, 4027
7386 10:55:27.963742 16 : 4252, 4027
7387 10:55:27.963816 20 : 4252, 4027
7388 10:55:27.963878 24 : 4255, 4029
7389 10:55:27.967053 28 : 4252, 4027
7390 10:55:27.967126 32 : 4253, 4026
7391 10:55:27.970300 36 : 4365, 4140
7392 10:55:27.970372 40 : 4250, 4027
7393 10:55:27.973527 44 : 4255, 4029
7394 10:55:27.973600 48 : 4250, 4027
7395 10:55:27.973669 52 : 4363, 4137
7396 10:55:27.977250 56 : 4250, 4027
7397 10:55:27.977348 60 : 4360, 4138
7398 10:55:27.980394 64 : 4253, 4026
7399 10:55:27.980465 68 : 4249, 4027
7400 10:55:27.983541 72 : 4250, 4027
7401 10:55:27.983614 76 : 4252, 4030
7402 10:55:27.986976 80 : 4360, 4137
7403 10:55:27.987081 84 : 4250, 4026
7404 10:55:27.987170 88 : 4361, 177
7405 10:55:27.990663 92 : 4360, 0
7406 10:55:27.990747 96 : 4249, 0
7407 10:55:27.993740 100 : 4252, 0
7408 10:55:27.993817 104 : 4252, 0
7409 10:55:27.993881 108 : 4252, 0
7410 10:55:27.997079 112 : 4360, 0
7411 10:55:27.997161 116 : 4360, 0
7412 10:55:27.997226 120 : 4250, 0
7413 10:55:28.000710 124 : 4250, 0
7414 10:55:28.000792 128 : 4250, 0
7415 10:55:28.003906 132 : 4252, 0
7416 10:55:28.003988 136 : 4250, 0
7417 10:55:28.004053 140 : 4249, 0
7418 10:55:28.007092 144 : 4252, 0
7419 10:55:28.007175 148 : 4360, 0
7420 10:55:28.010237 152 : 4360, 0
7421 10:55:28.010320 156 : 4250, 0
7422 10:55:28.010386 160 : 4250, 0
7423 10:55:28.014037 164 : 4360, 0
7424 10:55:28.014119 168 : 4360, 0
7425 10:55:28.014185 172 : 4250, 0
7426 10:55:28.017164 176 : 4249, 0
7427 10:55:28.017275 180 : 4249, 0
7428 10:55:28.020296 184 : 4250, 0
7429 10:55:28.020380 188 : 4250, 0
7430 10:55:28.020445 192 : 4250, 0
7431 10:55:28.023550 196 : 4252, 0
7432 10:55:28.023633 200 : 4250, 0
7433 10:55:28.026818 204 : 4250, 1330
7434 10:55:28.026900 208 : 4250, 4000
7435 10:55:28.030530 212 : 4250, 4026
7436 10:55:28.030613 216 : 4252, 4029
7437 10:55:28.033708 220 : 4253, 4029
7438 10:55:28.033790 224 : 4250, 4027
7439 10:55:28.036737 228 : 4250, 4026
7440 10:55:28.036819 232 : 4252, 4030
7441 10:55:28.036885 236 : 4250, 4027
7442 10:55:28.040498 240 : 4360, 4137
7443 10:55:28.040580 244 : 4360, 4137
7444 10:55:28.043604 248 : 4247, 4025
7445 10:55:28.043688 252 : 4363, 4140
7446 10:55:28.046858 256 : 4360, 4137
7447 10:55:28.046941 260 : 4250, 4027
7448 10:55:28.050119 264 : 4250, 4026
7449 10:55:28.050201 268 : 4252, 4030
7450 10:55:28.053978 272 : 4249, 4027
7451 10:55:28.054061 276 : 4249, 4027
7452 10:55:28.056531 280 : 4250, 4026
7453 10:55:28.056613 284 : 4252, 4029
7454 10:55:28.060327 288 : 4249, 4027
7455 10:55:28.060409 292 : 4362, 4140
7456 10:55:28.060475 296 : 4360, 4137
7457 10:55:28.063530 300 : 4250, 4027
7458 10:55:28.063612 304 : 4363, 4140
7459 10:55:28.066790 308 : 4360, 4104
7460 10:55:28.066872 312 : 4249, 2036
7461 10:55:28.066937
7462 10:55:28.069972 MIOCK jitter meter ch=0
7463 10:55:28.070053
7464 10:55:28.073077 1T = (312-88) = 224 dly cells
7465 10:55:28.080035 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7466 10:55:28.080117 ==
7467 10:55:28.083186 Dram Type= 6, Freq= 0, CH_0, rank 0
7468 10:55:28.086435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7469 10:55:28.086520 ==
7470 10:55:28.093250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7471 10:55:28.096181 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7472 10:55:28.099786 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7473 10:55:28.106752 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7474 10:55:28.115673 [CA 0] Center 43 (12~74) winsize 63
7475 10:55:28.118668 [CA 1] Center 43 (13~74) winsize 62
7476 10:55:28.121882 [CA 2] Center 38 (9~68) winsize 60
7477 10:55:28.125107 [CA 3] Center 38 (8~68) winsize 61
7478 10:55:28.128965 [CA 4] Center 37 (7~67) winsize 61
7479 10:55:28.132130 [CA 5] Center 36 (7~65) winsize 59
7480 10:55:28.132214
7481 10:55:28.135503 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7482 10:55:28.135584
7483 10:55:28.138509 [CATrainingPosCal] consider 1 rank data
7484 10:55:28.141628 u2DelayCellTimex100 = 290/100 ps
7485 10:55:28.145245 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7486 10:55:28.152078 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7487 10:55:28.155036 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7488 10:55:28.159040 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7489 10:55:28.162190 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7490 10:55:28.165409 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7491 10:55:28.165490
7492 10:55:28.168600 CA PerBit enable=1, Macro0, CA PI delay=36
7493 10:55:28.168682
7494 10:55:28.171773 [CBTSetCACLKResult] CA Dly = 36
7495 10:55:28.175018 CS Dly: 9 (0~40)
7496 10:55:28.178902 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7497 10:55:28.181912 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7498 10:55:28.182015 ==
7499 10:55:28.184976 Dram Type= 6, Freq= 0, CH_0, rank 1
7500 10:55:28.188288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 10:55:28.188364 ==
7502 10:55:28.194866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 10:55:28.198648 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 10:55:28.204925 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 10:55:28.208433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 10:55:28.218770 [CA 0] Center 42 (12~73) winsize 62
7507 10:55:28.221805 [CA 1] Center 42 (12~73) winsize 62
7508 10:55:28.225373 [CA 2] Center 38 (8~68) winsize 61
7509 10:55:28.228481 [CA 3] Center 37 (8~67) winsize 60
7510 10:55:28.231673 [CA 4] Center 36 (6~66) winsize 61
7511 10:55:28.234985 [CA 5] Center 35 (5~65) winsize 61
7512 10:55:28.235067
7513 10:55:28.238835 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 10:55:28.238916
7515 10:55:28.242116 [CATrainingPosCal] consider 2 rank data
7516 10:55:28.245283 u2DelayCellTimex100 = 290/100 ps
7517 10:55:28.248628 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7518 10:55:28.255140 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7519 10:55:28.258194 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7520 10:55:28.262025 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7521 10:55:28.265053 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7522 10:55:28.268154 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7523 10:55:28.268227
7524 10:55:28.271521 CA PerBit enable=1, Macro0, CA PI delay=36
7525 10:55:28.271619
7526 10:55:28.275240 [CBTSetCACLKResult] CA Dly = 36
7527 10:55:28.278535 CS Dly: 10 (0~42)
7528 10:55:28.281744 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 10:55:28.284900 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 10:55:28.284996
7531 10:55:28.288276 ----->DramcWriteLeveling(PI) begin...
7532 10:55:28.288355 ==
7533 10:55:28.291495 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 10:55:28.294680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 10:55:28.298551 ==
7536 10:55:28.298650 Write leveling (Byte 0): 36 => 36
7537 10:55:28.301589 Write leveling (Byte 1): 27 => 27
7538 10:55:28.304722 DramcWriteLeveling(PI) end<-----
7539 10:55:28.304824
7540 10:55:28.304912 ==
7541 10:55:28.308508 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 10:55:28.314846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 10:55:28.314921 ==
7544 10:55:28.318397 [Gating] SW mode calibration
7545 10:55:28.324564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7546 10:55:28.328472 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7547 10:55:28.335046 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7548 10:55:28.338183 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7549 10:55:28.341473 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7550 10:55:28.348278 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7551 10:55:28.351443 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7552 10:55:28.354601 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7553 10:55:28.358219 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 10:55:28.364596 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 10:55:28.368148 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 10:55:28.371165 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7557 10:55:28.378207 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7558 10:55:28.381532 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7559 10:55:28.384668 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7560 10:55:28.391515 1 5 20 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
7561 10:55:28.394574 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7562 10:55:28.397845 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7563 10:55:28.404504 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7564 10:55:28.408130 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 10:55:28.411431 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7566 10:55:28.417831 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7567 10:55:28.420921 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
7568 10:55:28.424467 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7569 10:55:28.431040 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 10:55:28.434251 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 10:55:28.437759 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 10:55:28.444465 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 10:55:28.447675 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 10:55:28.451014 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 10:55:28.457755 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7576 10:55:28.461084 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 10:55:28.464422 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 10:55:28.471141 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 10:55:28.474168 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 10:55:28.477408 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 10:55:28.484580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 10:55:28.487763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:55:28.490955 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:55:28.497838 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:55:28.501028 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:55:28.504409 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:55:28.507618 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:55:28.514512 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:55:28.517831 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 10:55:28.521074 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 10:55:28.527921 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7592 10:55:28.531008 Total UI for P1: 0, mck2ui 16
7593 10:55:28.533931 best dqsien dly found for B0: ( 1, 9, 10)
7594 10:55:28.537518 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 10:55:28.540676 Total UI for P1: 0, mck2ui 16
7596 10:55:28.544391 best dqsien dly found for B1: ( 1, 9, 18)
7597 10:55:28.547444 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7598 10:55:28.550985 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7599 10:55:28.551063
7600 10:55:28.554027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7601 10:55:28.557342 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7602 10:55:28.560998 [Gating] SW calibration Done
7603 10:55:28.561070 ==
7604 10:55:28.564111 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 10:55:28.570938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 10:55:28.571019 ==
7607 10:55:28.571083 RX Vref Scan: 0
7608 10:55:28.571141
7609 10:55:28.573940 RX Vref 0 -> 0, step: 1
7610 10:55:28.574060
7611 10:55:28.577548 RX Delay 0 -> 252, step: 8
7612 10:55:28.580725 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7613 10:55:28.583763 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7614 10:55:28.587616 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7615 10:55:28.590248 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7616 10:55:28.597165 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7617 10:55:28.600412 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7618 10:55:28.604191 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7619 10:55:28.607434 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7620 10:55:28.610672 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7621 10:55:28.613720 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7622 10:55:28.620101 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7623 10:55:28.623401 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7624 10:55:28.627304 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7625 10:55:28.630584 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7626 10:55:28.637258 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7627 10:55:28.640425 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7628 10:55:28.640508 ==
7629 10:55:28.643449 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 10:55:28.647096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 10:55:28.647178 ==
7632 10:55:28.650038 DQS Delay:
7633 10:55:28.650154 DQS0 = 0, DQS1 = 0
7634 10:55:28.650236 DQM Delay:
7635 10:55:28.653281 DQM0 = 136, DQM1 = 130
7636 10:55:28.653363 DQ Delay:
7637 10:55:28.656863 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7638 10:55:28.659884 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7639 10:55:28.663910 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7640 10:55:28.670213 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7641 10:55:28.670296
7642 10:55:28.670360
7643 10:55:28.670420 ==
7644 10:55:28.673407 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 10:55:28.677125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 10:55:28.677211 ==
7647 10:55:28.677275
7648 10:55:28.677335
7649 10:55:28.680190 TX Vref Scan disable
7650 10:55:28.680259 == TX Byte 0 ==
7651 10:55:28.686818 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7652 10:55:28.689902 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7653 10:55:28.689983 == TX Byte 1 ==
7654 10:55:28.696370 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7655 10:55:28.700153 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7656 10:55:28.700222 ==
7657 10:55:28.703265 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 10:55:28.706970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 10:55:28.707079 ==
7660 10:55:28.721813
7661 10:55:28.724923 TX Vref early break, caculate TX vref
7662 10:55:28.728255 TX Vref=16, minBit 0, minWin=23, winSum=381
7663 10:55:28.731524 TX Vref=18, minBit 0, minWin=23, winSum=388
7664 10:55:28.734755 TX Vref=20, minBit 0, minWin=24, winSum=402
7665 10:55:28.737998 TX Vref=22, minBit 7, minWin=24, winSum=409
7666 10:55:28.741105 TX Vref=24, minBit 2, minWin=25, winSum=419
7667 10:55:28.748105 TX Vref=26, minBit 2, minWin=25, winSum=422
7668 10:55:28.751144 TX Vref=28, minBit 1, minWin=25, winSum=423
7669 10:55:28.754847 TX Vref=30, minBit 1, minWin=24, winSum=414
7670 10:55:28.757802 TX Vref=32, minBit 0, minWin=24, winSum=402
7671 10:55:28.761669 TX Vref=34, minBit 6, minWin=23, winSum=392
7672 10:55:28.768156 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
7673 10:55:28.768239
7674 10:55:28.771106 Final TX Range 0 Vref 28
7675 10:55:28.771187
7676 10:55:28.771250 ==
7677 10:55:28.774645 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 10:55:28.777862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 10:55:28.777943 ==
7680 10:55:28.778007
7681 10:55:28.778065
7682 10:55:28.781541 TX Vref Scan disable
7683 10:55:28.787816 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7684 10:55:28.787898 == TX Byte 0 ==
7685 10:55:28.791515 u2DelayCellOfst[0]=10 cells (3 PI)
7686 10:55:28.794469 u2DelayCellOfst[1]=16 cells (5 PI)
7687 10:55:28.798078 u2DelayCellOfst[2]=10 cells (3 PI)
7688 10:55:28.801410 u2DelayCellOfst[3]=6 cells (2 PI)
7689 10:55:28.804585 u2DelayCellOfst[4]=6 cells (2 PI)
7690 10:55:28.807687 u2DelayCellOfst[5]=0 cells (0 PI)
7691 10:55:28.811455 u2DelayCellOfst[6]=16 cells (5 PI)
7692 10:55:28.811535 u2DelayCellOfst[7]=16 cells (5 PI)
7693 10:55:28.818005 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7694 10:55:28.821132 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7695 10:55:28.824269 == TX Byte 1 ==
7696 10:55:28.824349 u2DelayCellOfst[8]=0 cells (0 PI)
7697 10:55:28.827539 u2DelayCellOfst[9]=0 cells (0 PI)
7698 10:55:28.831383 u2DelayCellOfst[10]=6 cells (2 PI)
7699 10:55:28.834657 u2DelayCellOfst[11]=0 cells (0 PI)
7700 10:55:28.837884 u2DelayCellOfst[12]=6 cells (2 PI)
7701 10:55:28.841036 u2DelayCellOfst[13]=6 cells (2 PI)
7702 10:55:28.844291 u2DelayCellOfst[14]=13 cells (4 PI)
7703 10:55:28.847377 u2DelayCellOfst[15]=10 cells (3 PI)
7704 10:55:28.850617 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7705 10:55:28.857605 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7706 10:55:28.857686 DramC Write-DBI on
7707 10:55:28.857750 ==
7708 10:55:28.860833 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 10:55:28.863956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 10:55:28.864037 ==
7711 10:55:28.867120
7712 10:55:28.867224
7713 10:55:28.867315 TX Vref Scan disable
7714 10:55:28.870852 == TX Byte 0 ==
7715 10:55:28.873957 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7716 10:55:28.877059 == TX Byte 1 ==
7717 10:55:28.880623 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7718 10:55:28.884186 DramC Write-DBI off
7719 10:55:28.884263
7720 10:55:28.884325 [DATLAT]
7721 10:55:28.884404 Freq=1600, CH0 RK0
7722 10:55:28.884485
7723 10:55:28.887190 DATLAT Default: 0xf
7724 10:55:28.887261 0, 0xFFFF, sum = 0
7725 10:55:28.890505 1, 0xFFFF, sum = 0
7726 10:55:28.893673 2, 0xFFFF, sum = 0
7727 10:55:28.893755 3, 0xFFFF, sum = 0
7728 10:55:28.897192 4, 0xFFFF, sum = 0
7729 10:55:28.897274 5, 0xFFFF, sum = 0
7730 10:55:28.900754 6, 0xFFFF, sum = 0
7731 10:55:28.900835 7, 0xFFFF, sum = 0
7732 10:55:28.903764 8, 0xFFFF, sum = 0
7733 10:55:28.903847 9, 0xFFFF, sum = 0
7734 10:55:28.907279 10, 0xFFFF, sum = 0
7735 10:55:28.907407 11, 0xFFFF, sum = 0
7736 10:55:28.910721 12, 0xFFFF, sum = 0
7737 10:55:28.910816 13, 0xFFFF, sum = 0
7738 10:55:28.913723 14, 0x0, sum = 1
7739 10:55:28.913805 15, 0x0, sum = 2
7740 10:55:28.916785 16, 0x0, sum = 3
7741 10:55:28.916866 17, 0x0, sum = 4
7742 10:55:28.920060 best_step = 15
7743 10:55:28.920140
7744 10:55:28.920203 ==
7745 10:55:28.923883 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 10:55:28.926848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 10:55:28.926955 ==
7748 10:55:28.930117 RX Vref Scan: 1
7749 10:55:28.930197
7750 10:55:28.930261 Set Vref Range= 24 -> 127
7751 10:55:28.930321
7752 10:55:28.933901 RX Vref 24 -> 127, step: 1
7753 10:55:28.933981
7754 10:55:28.937099 RX Delay 19 -> 252, step: 4
7755 10:55:28.937179
7756 10:55:28.940472 Set Vref, RX VrefLevel [Byte0]: 24
7757 10:55:28.943609 [Byte1]: 24
7758 10:55:28.943690
7759 10:55:28.946716 Set Vref, RX VrefLevel [Byte0]: 25
7760 10:55:28.950526 [Byte1]: 25
7761 10:55:28.953547
7762 10:55:28.953627 Set Vref, RX VrefLevel [Byte0]: 26
7763 10:55:28.956689 [Byte1]: 26
7764 10:55:28.961086
7765 10:55:28.961167 Set Vref, RX VrefLevel [Byte0]: 27
7766 10:55:28.964272 [Byte1]: 27
7767 10:55:28.968906
7768 10:55:28.968986 Set Vref, RX VrefLevel [Byte0]: 28
7769 10:55:28.972001 [Byte1]: 28
7770 10:55:28.976200
7771 10:55:28.976281 Set Vref, RX VrefLevel [Byte0]: 29
7772 10:55:28.982835 [Byte1]: 29
7773 10:55:28.982916
7774 10:55:28.985864 Set Vref, RX VrefLevel [Byte0]: 30
7775 10:55:28.989247 [Byte1]: 30
7776 10:55:28.989328
7777 10:55:28.992331 Set Vref, RX VrefLevel [Byte0]: 31
7778 10:55:28.996169 [Byte1]: 31
7779 10:55:28.996250
7780 10:55:28.999238 Set Vref, RX VrefLevel [Byte0]: 32
7781 10:55:29.002467 [Byte1]: 32
7782 10:55:29.006601
7783 10:55:29.006757 Set Vref, RX VrefLevel [Byte0]: 33
7784 10:55:29.010064 [Byte1]: 33
7785 10:55:29.014186
7786 10:55:29.014267 Set Vref, RX VrefLevel [Byte0]: 34
7787 10:55:29.017186 [Byte1]: 34
7788 10:55:29.021511
7789 10:55:29.021592 Set Vref, RX VrefLevel [Byte0]: 35
7790 10:55:29.024725 [Byte1]: 35
7791 10:55:29.029204
7792 10:55:29.029285 Set Vref, RX VrefLevel [Byte0]: 36
7793 10:55:29.032269 [Byte1]: 36
7794 10:55:29.036749
7795 10:55:29.036834 Set Vref, RX VrefLevel [Byte0]: 37
7796 10:55:29.040071 [Byte1]: 37
7797 10:55:29.043983
7798 10:55:29.044065 Set Vref, RX VrefLevel [Byte0]: 38
7799 10:55:29.047911 [Byte1]: 38
7800 10:55:29.051938
7801 10:55:29.052019 Set Vref, RX VrefLevel [Byte0]: 39
7802 10:55:29.054988 [Byte1]: 39
7803 10:55:29.059607
7804 10:55:29.059688 Set Vref, RX VrefLevel [Byte0]: 40
7805 10:55:29.062833 [Byte1]: 40
7806 10:55:29.067190
7807 10:55:29.067271 Set Vref, RX VrefLevel [Byte0]: 41
7808 10:55:29.070474 [Byte1]: 41
7809 10:55:29.074297
7810 10:55:29.074378 Set Vref, RX VrefLevel [Byte0]: 42
7811 10:55:29.078200 [Byte1]: 42
7812 10:55:29.082575
7813 10:55:29.082655 Set Vref, RX VrefLevel [Byte0]: 43
7814 10:55:29.085548 [Byte1]: 43
7815 10:55:29.089607
7816 10:55:29.089687 Set Vref, RX VrefLevel [Byte0]: 44
7817 10:55:29.093054 [Byte1]: 44
7818 10:55:29.097357
7819 10:55:29.097439 Set Vref, RX VrefLevel [Byte0]: 45
7820 10:55:29.100875 [Byte1]: 45
7821 10:55:29.104610
7822 10:55:29.104690 Set Vref, RX VrefLevel [Byte0]: 46
7823 10:55:29.108467 [Byte1]: 46
7824 10:55:29.112710
7825 10:55:29.112819 Set Vref, RX VrefLevel [Byte0]: 47
7826 10:55:29.115809 [Byte1]: 47
7827 10:55:29.120025
7828 10:55:29.120106 Set Vref, RX VrefLevel [Byte0]: 48
7829 10:55:29.122957 [Byte1]: 48
7830 10:55:29.127774
7831 10:55:29.127856 Set Vref, RX VrefLevel [Byte0]: 49
7832 10:55:29.131097 [Byte1]: 49
7833 10:55:29.135063
7834 10:55:29.135143 Set Vref, RX VrefLevel [Byte0]: 50
7835 10:55:29.138794 [Byte1]: 50
7836 10:55:29.142562
7837 10:55:29.142643 Set Vref, RX VrefLevel [Byte0]: 51
7838 10:55:29.145848 [Byte1]: 51
7839 10:55:29.150478
7840 10:55:29.150558 Set Vref, RX VrefLevel [Byte0]: 52
7841 10:55:29.153631 [Byte1]: 52
7842 10:55:29.158149
7843 10:55:29.158230 Set Vref, RX VrefLevel [Byte0]: 53
7844 10:55:29.161263 [Byte1]: 53
7845 10:55:29.165151
7846 10:55:29.165231 Set Vref, RX VrefLevel [Byte0]: 54
7847 10:55:29.168446 [Byte1]: 54
7848 10:55:29.172714
7849 10:55:29.172804 Set Vref, RX VrefLevel [Byte0]: 55
7850 10:55:29.176023 [Byte1]: 55
7851 10:55:29.180613
7852 10:55:29.180694 Set Vref, RX VrefLevel [Byte0]: 56
7853 10:55:29.183777 [Byte1]: 56
7854 10:55:29.188140
7855 10:55:29.188221 Set Vref, RX VrefLevel [Byte0]: 57
7856 10:55:29.191236 [Byte1]: 57
7857 10:55:29.195619
7858 10:55:29.195740 Set Vref, RX VrefLevel [Byte0]: 58
7859 10:55:29.199250 [Byte1]: 58
7860 10:55:29.203121
7861 10:55:29.203201 Set Vref, RX VrefLevel [Byte0]: 59
7862 10:55:29.206408 [Byte1]: 59
7863 10:55:29.210778
7864 10:55:29.210859 Set Vref, RX VrefLevel [Byte0]: 60
7865 10:55:29.213905 [Byte1]: 60
7866 10:55:29.218186
7867 10:55:29.218267 Set Vref, RX VrefLevel [Byte0]: 61
7868 10:55:29.221933 [Byte1]: 61
7869 10:55:29.226375
7870 10:55:29.226494 Set Vref, RX VrefLevel [Byte0]: 62
7871 10:55:29.229469 [Byte1]: 62
7872 10:55:29.233631
7873 10:55:29.233711 Set Vref, RX VrefLevel [Byte0]: 63
7874 10:55:29.236633 [Byte1]: 63
7875 10:55:29.240943
7876 10:55:29.241024 Set Vref, RX VrefLevel [Byte0]: 64
7877 10:55:29.244203 [Byte1]: 64
7878 10:55:29.248799
7879 10:55:29.248880 Set Vref, RX VrefLevel [Byte0]: 65
7880 10:55:29.252046 [Byte1]: 65
7881 10:55:29.256522
7882 10:55:29.256603 Set Vref, RX VrefLevel [Byte0]: 66
7883 10:55:29.259852 [Byte1]: 66
7884 10:55:29.263674
7885 10:55:29.263754 Set Vref, RX VrefLevel [Byte0]: 67
7886 10:55:29.266916 [Byte1]: 67
7887 10:55:29.271577
7888 10:55:29.271686 Set Vref, RX VrefLevel [Byte0]: 68
7889 10:55:29.274666 [Byte1]: 68
7890 10:55:29.278955
7891 10:55:29.279045 Set Vref, RX VrefLevel [Byte0]: 69
7892 10:55:29.282149 [Byte1]: 69
7893 10:55:29.286647
7894 10:55:29.286721 Set Vref, RX VrefLevel [Byte0]: 70
7895 10:55:29.289683 [Byte1]: 70
7896 10:55:29.294034
7897 10:55:29.294108 Set Vref, RX VrefLevel [Byte0]: 71
7898 10:55:29.297853 [Byte1]: 71
7899 10:55:29.301647
7900 10:55:29.301720 Set Vref, RX VrefLevel [Byte0]: 72
7901 10:55:29.305259 [Byte1]: 72
7902 10:55:29.309494
7903 10:55:29.309566 Set Vref, RX VrefLevel [Byte0]: 73
7904 10:55:29.312398 [Byte1]: 73
7905 10:55:29.316876
7906 10:55:29.316953 Set Vref, RX VrefLevel [Byte0]: 74
7907 10:55:29.319974 [Byte1]: 74
7908 10:55:29.324710
7909 10:55:29.324791 Set Vref, RX VrefLevel [Byte0]: 75
7910 10:55:29.327879 [Byte1]: 75
7911 10:55:29.331728
7912 10:55:29.331806 Set Vref, RX VrefLevel [Byte0]: 76
7913 10:55:29.335605 [Byte1]: 76
7914 10:55:29.339862
7915 10:55:29.339935 Final RX Vref Byte 0 = 55 to rank0
7916 10:55:29.342870 Final RX Vref Byte 1 = 62 to rank0
7917 10:55:29.346360 Final RX Vref Byte 0 = 55 to rank1
7918 10:55:29.349454 Final RX Vref Byte 1 = 62 to rank1==
7919 10:55:29.352726 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 10:55:29.359731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 10:55:29.359817 ==
7922 10:55:29.359882 DQS Delay:
7923 10:55:29.359941 DQS0 = 0, DQS1 = 0
7924 10:55:29.362988 DQM Delay:
7925 10:55:29.363071 DQM0 = 133, DQM1 = 128
7926 10:55:29.366147 DQ Delay:
7927 10:55:29.369241 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7928 10:55:29.372659 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7929 10:55:29.375800 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7930 10:55:29.379551 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7931 10:55:29.379623
7932 10:55:29.379683
7933 10:55:29.379740
7934 10:55:29.382918 [DramC_TX_OE_Calibration] TA2
7935 10:55:29.386037 Original DQ_B0 (3 6) =30, OEN = 27
7936 10:55:29.389272 Original DQ_B1 (3 6) =30, OEN = 27
7937 10:55:29.392435 24, 0x0, End_B0=24 End_B1=24
7938 10:55:29.392503 25, 0x0, End_B0=25 End_B1=25
7939 10:55:29.396112 26, 0x0, End_B0=26 End_B1=26
7940 10:55:29.399140 27, 0x0, End_B0=27 End_B1=27
7941 10:55:29.402402 28, 0x0, End_B0=28 End_B1=28
7942 10:55:29.405707 29, 0x0, End_B0=29 End_B1=29
7943 10:55:29.405777 30, 0x0, End_B0=30 End_B1=30
7944 10:55:29.409339 31, 0x4141, End_B0=30 End_B1=30
7945 10:55:29.412367 Byte0 end_step=30 best_step=27
7946 10:55:29.415985 Byte1 end_step=30 best_step=27
7947 10:55:29.419079 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 10:55:29.422757 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 10:55:29.422838
7950 10:55:29.422905
7951 10:55:29.429058 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7952 10:55:29.432498 CH0 RK0: MR19=303, MR18=2521
7953 10:55:29.439286 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7954 10:55:29.439415
7955 10:55:29.442383 ----->DramcWriteLeveling(PI) begin...
7956 10:55:29.442456 ==
7957 10:55:29.445690 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 10:55:29.449428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 10:55:29.449506 ==
7960 10:55:29.452535 Write leveling (Byte 0): 36 => 36
7961 10:55:29.455940 Write leveling (Byte 1): 26 => 26
7962 10:55:29.459205 DramcWriteLeveling(PI) end<-----
7963 10:55:29.459290
7964 10:55:29.459373 ==
7965 10:55:29.462330 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 10:55:29.465533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 10:55:29.465606 ==
7968 10:55:29.469410 [Gating] SW mode calibration
7969 10:55:29.475795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 10:55:29.482267 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 10:55:29.486062 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 10:55:29.489330 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7973 10:55:29.495798 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7974 10:55:29.498850 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7975 10:55:29.502568 1 4 16 | B1->B0 | 3030 3535 | 0 0 | (0 0) (0 0)
7976 10:55:29.508866 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 10:55:29.512648 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 10:55:29.515833 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7979 10:55:29.522320 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 10:55:29.525403 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7981 10:55:29.528987 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 0) (0 0)
7982 10:55:29.535494 1 5 12 | B1->B0 | 3434 3535 | 1 0 | (1 0) (0 1)
7983 10:55:29.538940 1 5 16 | B1->B0 | 2d2d 2726 | 1 1 | (1 0) (1 0)
7984 10:55:29.542048 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7985 10:55:29.548634 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7986 10:55:29.552309 1 5 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7987 10:55:29.555627 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 10:55:29.562348 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 10:55:29.565385 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7990 10:55:29.569083 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7991 10:55:29.575470 1 6 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7992 10:55:29.578562 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 10:55:29.582489 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 10:55:29.588677 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 10:55:29.591980 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 10:55:29.595915 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 10:55:29.598497 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 10:55:29.605546 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 10:55:29.608603 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8000 10:55:29.611874 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 10:55:29.618912 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 10:55:29.622221 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 10:55:29.625172 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 10:55:29.632194 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:55:29.635065 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:55:29.638235 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 10:55:29.645162 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 10:55:29.648207 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 10:55:29.651848 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 10:55:29.658406 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 10:55:29.661521 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 10:55:29.665228 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 10:55:29.671372 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 10:55:29.674572 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 10:55:29.677842 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8016 10:55:29.681561 Total UI for P1: 0, mck2ui 16
8017 10:55:29.684825 best dqsien dly found for B0: ( 1, 9, 12)
8018 10:55:29.691886 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 10:55:29.691966 Total UI for P1: 0, mck2ui 16
8020 10:55:29.698297 best dqsien dly found for B1: ( 1, 9, 14)
8021 10:55:29.701610 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8022 10:55:29.704775 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8023 10:55:29.704884
8024 10:55:29.707898 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8025 10:55:29.711861 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8026 10:55:29.714872 [Gating] SW calibration Done
8027 10:55:29.714976 ==
8028 10:55:29.718205 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 10:55:29.721479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 10:55:29.721577 ==
8031 10:55:29.724592 RX Vref Scan: 0
8032 10:55:29.724662
8033 10:55:29.724722 RX Vref 0 -> 0, step: 1
8034 10:55:29.724780
8035 10:55:29.727778 RX Delay 0 -> 252, step: 8
8036 10:55:29.731529 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8037 10:55:29.737677 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8038 10:55:29.741304 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8039 10:55:29.744862 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8040 10:55:29.748027 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8041 10:55:29.751067 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8042 10:55:29.757983 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8043 10:55:29.761492 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8044 10:55:29.764649 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8045 10:55:29.767607 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8046 10:55:29.771128 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8047 10:55:29.777846 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8048 10:55:29.780998 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8049 10:55:29.784133 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8050 10:55:29.787846 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8051 10:55:29.794492 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8052 10:55:29.794580 ==
8053 10:55:29.797476 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 10:55:29.800701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 10:55:29.800780 ==
8056 10:55:29.800844 DQS Delay:
8057 10:55:29.804597 DQS0 = 0, DQS1 = 0
8058 10:55:29.804672 DQM Delay:
8059 10:55:29.807819 DQM0 = 136, DQM1 = 128
8060 10:55:29.807892 DQ Delay:
8061 10:55:29.811047 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8062 10:55:29.814177 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8063 10:55:29.817465 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8064 10:55:29.820701 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8065 10:55:29.820773
8066 10:55:29.820844
8067 10:55:29.824028 ==
8068 10:55:29.824108 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 10:55:29.831067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 10:55:29.831150 ==
8071 10:55:29.831215
8072 10:55:29.831275
8073 10:55:29.834217 TX Vref Scan disable
8074 10:55:29.834298 == TX Byte 0 ==
8075 10:55:29.837245 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8076 10:55:29.844183 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8077 10:55:29.844258 == TX Byte 1 ==
8078 10:55:29.847197 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8079 10:55:29.853765 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8080 10:55:29.853889 ==
8081 10:55:29.857412 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 10:55:29.860569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 10:55:29.860651 ==
8084 10:55:29.875104
8085 10:55:29.878063 TX Vref early break, caculate TX vref
8086 10:55:29.881524 TX Vref=16, minBit 1, minWin=22, winSum=385
8087 10:55:29.884626 TX Vref=18, minBit 1, minWin=23, winSum=395
8088 10:55:29.888411 TX Vref=20, minBit 1, minWin=24, winSum=403
8089 10:55:29.891567 TX Vref=22, minBit 3, minWin=24, winSum=413
8090 10:55:29.894919 TX Vref=24, minBit 1, minWin=24, winSum=414
8091 10:55:29.901391 TX Vref=26, minBit 1, minWin=25, winSum=428
8092 10:55:29.904495 TX Vref=28, minBit 0, minWin=26, winSum=426
8093 10:55:29.908433 TX Vref=30, minBit 0, minWin=25, winSum=415
8094 10:55:29.911599 TX Vref=32, minBit 2, minWin=24, winSum=409
8095 10:55:29.914752 TX Vref=34, minBit 0, minWin=23, winSum=398
8096 10:55:29.921713 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8097 10:55:29.921813
8098 10:55:29.924839 Final TX Range 0 Vref 28
8099 10:55:29.924970
8100 10:55:29.925094 ==
8101 10:55:29.928055 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 10:55:29.931441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 10:55:29.931531 ==
8104 10:55:29.931597
8105 10:55:29.931667
8106 10:55:29.934598 TX Vref Scan disable
8107 10:55:29.941448 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8108 10:55:29.941536 == TX Byte 0 ==
8109 10:55:29.944590 u2DelayCellOfst[0]=10 cells (3 PI)
8110 10:55:29.947794 u2DelayCellOfst[1]=16 cells (5 PI)
8111 10:55:29.951441 u2DelayCellOfst[2]=10 cells (3 PI)
8112 10:55:29.954561 u2DelayCellOfst[3]=10 cells (3 PI)
8113 10:55:29.957706 u2DelayCellOfst[4]=6 cells (2 PI)
8114 10:55:29.961352 u2DelayCellOfst[5]=0 cells (0 PI)
8115 10:55:29.964873 u2DelayCellOfst[6]=16 cells (5 PI)
8116 10:55:29.967571 u2DelayCellOfst[7]=13 cells (4 PI)
8117 10:55:29.971377 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8118 10:55:29.974453 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8119 10:55:29.977670 == TX Byte 1 ==
8120 10:55:29.977751 u2DelayCellOfst[8]=3 cells (1 PI)
8121 10:55:29.980727 u2DelayCellOfst[9]=0 cells (0 PI)
8122 10:55:29.984351 u2DelayCellOfst[10]=6 cells (2 PI)
8123 10:55:29.987545 u2DelayCellOfst[11]=6 cells (2 PI)
8124 10:55:29.990993 u2DelayCellOfst[12]=10 cells (3 PI)
8125 10:55:29.994015 u2DelayCellOfst[13]=10 cells (3 PI)
8126 10:55:29.997636 u2DelayCellOfst[14]=13 cells (4 PI)
8127 10:55:30.000882 u2DelayCellOfst[15]=13 cells (4 PI)
8128 10:55:30.004022 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8129 10:55:30.011044 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8130 10:55:30.011153 DramC Write-DBI on
8131 10:55:30.011244 ==
8132 10:55:30.014341 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 10:55:30.017526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 10:55:30.020884 ==
8135 10:55:30.020956
8136 10:55:30.021024
8137 10:55:30.021080 TX Vref Scan disable
8138 10:55:30.024598 == TX Byte 0 ==
8139 10:55:30.027838 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8140 10:55:30.031168 == TX Byte 1 ==
8141 10:55:30.034387 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8142 10:55:30.037580 DramC Write-DBI off
8143 10:55:30.037648
8144 10:55:30.037710 [DATLAT]
8145 10:55:30.037776 Freq=1600, CH0 RK1
8146 10:55:30.037833
8147 10:55:30.041423 DATLAT Default: 0xf
8148 10:55:30.041496 0, 0xFFFF, sum = 0
8149 10:55:30.044473 1, 0xFFFF, sum = 0
8150 10:55:30.044547 2, 0xFFFF, sum = 0
8151 10:55:30.047641 3, 0xFFFF, sum = 0
8152 10:55:30.050965 4, 0xFFFF, sum = 0
8153 10:55:30.051040 5, 0xFFFF, sum = 0
8154 10:55:30.054142 6, 0xFFFF, sum = 0
8155 10:55:30.054232 7, 0xFFFF, sum = 0
8156 10:55:30.057983 8, 0xFFFF, sum = 0
8157 10:55:30.058054 9, 0xFFFF, sum = 0
8158 10:55:30.061143 10, 0xFFFF, sum = 0
8159 10:55:30.061212 11, 0xFFFF, sum = 0
8160 10:55:30.064343 12, 0xFFFF, sum = 0
8161 10:55:30.064429 13, 0xFFFF, sum = 0
8162 10:55:30.067947 14, 0x0, sum = 1
8163 10:55:30.068020 15, 0x0, sum = 2
8164 10:55:30.070890 16, 0x0, sum = 3
8165 10:55:30.070974 17, 0x0, sum = 4
8166 10:55:30.074517 best_step = 15
8167 10:55:30.074621
8168 10:55:30.074711 ==
8169 10:55:30.077630 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 10:55:30.080870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 10:55:30.080956 ==
8172 10:55:30.081017 RX Vref Scan: 0
8173 10:55:30.084128
8174 10:55:30.084215 RX Vref 0 -> 0, step: 1
8175 10:55:30.084276
8176 10:55:30.087836 RX Delay 19 -> 252, step: 4
8177 10:55:30.090975 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8178 10:55:30.097665 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8179 10:55:30.100896 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8180 10:55:30.104505 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8181 10:55:30.107926 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8182 10:55:30.111063 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8183 10:55:30.117397 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8184 10:55:30.120650 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8185 10:55:30.123938 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8186 10:55:30.127706 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8187 10:55:30.130834 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8188 10:55:30.137426 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8189 10:55:30.140704 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8190 10:55:30.144400 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8191 10:55:30.147626 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8192 10:55:30.150510 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8193 10:55:30.150593 ==
8194 10:55:30.154399 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 10:55:30.160553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 10:55:30.160636 ==
8197 10:55:30.160702 DQS Delay:
8198 10:55:30.164473 DQS0 = 0, DQS1 = 0
8199 10:55:30.164555 DQM Delay:
8200 10:55:30.167602 DQM0 = 134, DQM1 = 127
8201 10:55:30.167684 DQ Delay:
8202 10:55:30.170686 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8203 10:55:30.173948 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =142
8204 10:55:30.177544 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8205 10:55:30.180578 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8206 10:55:30.180661
8207 10:55:30.180725
8208 10:55:30.180786
8209 10:55:30.184203 [DramC_TX_OE_Calibration] TA2
8210 10:55:30.187497 Original DQ_B0 (3 6) =30, OEN = 27
8211 10:55:30.190678 Original DQ_B1 (3 6) =30, OEN = 27
8212 10:55:30.193857 24, 0x0, End_B0=24 End_B1=24
8213 10:55:30.193941 25, 0x0, End_B0=25 End_B1=25
8214 10:55:30.197023 26, 0x0, End_B0=26 End_B1=26
8215 10:55:30.200781 27, 0x0, End_B0=27 End_B1=27
8216 10:55:30.204352 28, 0x0, End_B0=28 End_B1=28
8217 10:55:30.207554 29, 0x0, End_B0=29 End_B1=29
8218 10:55:30.207637 30, 0x0, End_B0=30 End_B1=30
8219 10:55:30.210657 31, 0x4141, End_B0=30 End_B1=30
8220 10:55:30.213884 Byte0 end_step=30 best_step=27
8221 10:55:30.217361 Byte1 end_step=30 best_step=27
8222 10:55:30.220606 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 10:55:30.224282 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 10:55:30.224386
8225 10:55:30.224453
8226 10:55:30.230544 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8227 10:55:30.233719 CH0 RK1: MR19=303, MR18=1E07
8228 10:55:30.240632 CH0_RK1: MR19=0x303, MR18=0x1E07, DQSOSC=394, MR23=63, INC=23, DEC=15
8229 10:55:30.243967 [RxdqsGatingPostProcess] freq 1600
8230 10:55:30.247148 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 10:55:30.250359 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 10:55:30.254096 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 10:55:30.257397 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 10:55:30.260561 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 10:55:30.263658 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 10:55:30.267470 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 10:55:30.270705 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 10:55:30.273483 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 10:55:30.277412 Pre-setting of DQS Precalculation
8240 10:55:30.280581 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 10:55:30.280663 ==
8242 10:55:30.283778 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 10:55:30.286914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 10:55:30.290377 ==
8245 10:55:30.293458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 10:55:30.297138 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 10:55:30.303546 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 10:55:30.307381 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 10:55:30.317019 [CA 0] Center 42 (12~72) winsize 61
8250 10:55:30.320754 [CA 1] Center 42 (12~72) winsize 61
8251 10:55:30.323879 [CA 2] Center 38 (9~68) winsize 60
8252 10:55:30.327699 [CA 3] Center 38 (9~67) winsize 59
8253 10:55:30.330472 [CA 4] Center 38 (9~68) winsize 60
8254 10:55:30.333593 [CA 5] Center 37 (8~67) winsize 60
8255 10:55:30.333671
8256 10:55:30.337448 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8257 10:55:30.337520
8258 10:55:30.340545 [CATrainingPosCal] consider 1 rank data
8259 10:55:30.343869 u2DelayCellTimex100 = 290/100 ps
8260 10:55:30.346980 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8261 10:55:30.353514 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8262 10:55:30.357240 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8263 10:55:30.360472 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8264 10:55:30.363675 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8265 10:55:30.366899 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8266 10:55:30.366980
8267 10:55:30.370694 CA PerBit enable=1, Macro0, CA PI delay=37
8268 10:55:30.370770
8269 10:55:30.373842 [CBTSetCACLKResult] CA Dly = 37
8270 10:55:30.376984 CS Dly: 10 (0~41)
8271 10:55:30.380147 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 10:55:30.383980 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 10:55:30.384060 ==
8274 10:55:30.387111 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 10:55:30.390446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 10:55:30.393683 ==
8277 10:55:30.396667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 10:55:30.400177 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 10:55:30.406951 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 10:55:30.413419 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 10:55:30.420828 [CA 0] Center 42 (13~72) winsize 60
8282 10:55:30.423621 [CA 1] Center 42 (13~72) winsize 60
8283 10:55:30.427203 [CA 2] Center 39 (10~69) winsize 60
8284 10:55:30.430362 [CA 3] Center 38 (9~68) winsize 60
8285 10:55:30.434053 [CA 4] Center 39 (9~69) winsize 61
8286 10:55:30.437087 [CA 5] Center 38 (9~68) winsize 60
8287 10:55:30.437168
8288 10:55:30.440161 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 10:55:30.440243
8290 10:55:30.443815 [CATrainingPosCal] consider 2 rank data
8291 10:55:30.446859 u2DelayCellTimex100 = 290/100 ps
8292 10:55:30.450610 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8293 10:55:30.457193 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8294 10:55:30.460419 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8295 10:55:30.463533 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8296 10:55:30.466751 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8297 10:55:30.470483 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8298 10:55:30.470586
8299 10:55:30.473598 CA PerBit enable=1, Macro0, CA PI delay=38
8300 10:55:30.473685
8301 10:55:30.477040 [CBTSetCACLKResult] CA Dly = 38
8302 10:55:30.480018 CS Dly: 12 (0~45)
8303 10:55:30.483818 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 10:55:30.487025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 10:55:30.487144
8306 10:55:30.490216 ----->DramcWriteLeveling(PI) begin...
8307 10:55:30.490301 ==
8308 10:55:30.493394 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 10:55:30.496780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 10:55:30.500681 ==
8311 10:55:30.503829 Write leveling (Byte 0): 26 => 26
8312 10:55:30.503913 Write leveling (Byte 1): 29 => 29
8313 10:55:30.506930 DramcWriteLeveling(PI) end<-----
8314 10:55:30.507012
8315 10:55:30.507075 ==
8316 10:55:30.510283 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 10:55:30.517165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 10:55:30.517265 ==
8319 10:55:30.520304 [Gating] SW mode calibration
8320 10:55:30.527130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 10:55:30.530165 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 10:55:30.536705 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 10:55:30.540227 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 10:55:30.543417 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8325 10:55:30.550177 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8326 10:55:30.553194 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 10:55:30.556765 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 10:55:30.563224 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 10:55:30.566955 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 10:55:30.570152 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 10:55:30.573393 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 10:55:30.579749 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
8333 10:55:30.583452 1 5 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
8334 10:55:30.586466 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 10:55:30.593512 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 10:55:30.596807 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 10:55:30.599988 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 10:55:30.606437 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 10:55:30.610225 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 10:55:30.613453 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8341 10:55:30.619982 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 10:55:30.623052 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 10:55:30.626983 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 10:55:30.633128 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 10:55:30.636773 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 10:55:30.640330 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 10:55:30.646434 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 10:55:30.650240 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8349 10:55:30.653264 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 10:55:30.660044 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 10:55:30.662980 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 10:55:30.666382 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 10:55:30.673122 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 10:55:30.676511 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:55:30.679955 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:55:30.686335 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:55:30.689475 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:55:30.692589 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 10:55:30.699065 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 10:55:30.703000 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 10:55:30.706233 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 10:55:30.712598 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 10:55:30.715769 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 10:55:30.719073 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 10:55:30.725869 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 10:55:30.728805 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 10:55:30.732626 Total UI for P1: 0, mck2ui 16
8368 10:55:30.735836 best dqsien dly found for B0: ( 1, 9, 10)
8369 10:55:30.738834 Total UI for P1: 0, mck2ui 16
8370 10:55:30.742555 best dqsien dly found for B1: ( 1, 9, 10)
8371 10:55:30.745475 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8372 10:55:30.749023 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8373 10:55:30.749148
8374 10:55:30.752159 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 10:55:30.755438 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 10:55:30.759087 [Gating] SW calibration Done
8377 10:55:30.759215 ==
8378 10:55:30.762772 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 10:55:30.765817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 10:55:30.765947 ==
8381 10:55:30.768988 RX Vref Scan: 0
8382 10:55:30.769113
8383 10:55:30.772191 RX Vref 0 -> 0, step: 1
8384 10:55:30.772320
8385 10:55:30.772440 RX Delay 0 -> 252, step: 8
8386 10:55:30.779194 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8387 10:55:30.782308 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8388 10:55:30.785521 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8389 10:55:30.788842 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8390 10:55:30.792171 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8391 10:55:30.799003 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8392 10:55:30.802252 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 10:55:30.805520 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8394 10:55:30.808802 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8395 10:55:30.812537 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8396 10:55:30.818807 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 10:55:30.822094 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8398 10:55:30.825867 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 10:55:30.828907 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8400 10:55:30.832075 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 10:55:30.839139 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8402 10:55:30.839230 ==
8403 10:55:30.842238 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 10:55:30.845400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 10:55:30.845470 ==
8406 10:55:30.845534 DQS Delay:
8407 10:55:30.849036 DQS0 = 0, DQS1 = 0
8408 10:55:30.849114 DQM Delay:
8409 10:55:30.852031 DQM0 = 137, DQM1 = 132
8410 10:55:30.852104 DQ Delay:
8411 10:55:30.855662 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8412 10:55:30.858603 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8413 10:55:30.862439 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8414 10:55:30.865508 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8415 10:55:30.865581
8416 10:55:30.865642
8417 10:55:30.868502 ==
8418 10:55:30.872223 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 10:55:30.875377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 10:55:30.875486 ==
8421 10:55:30.875626
8422 10:55:30.875720
8423 10:55:30.878357 TX Vref Scan disable
8424 10:55:30.878426 == TX Byte 0 ==
8425 10:55:30.881698 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 10:55:30.888544 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 10:55:30.888620 == TX Byte 1 ==
8428 10:55:30.891864 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8429 10:55:30.898276 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8430 10:55:30.898378 ==
8431 10:55:30.901869 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 10:55:30.905081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 10:55:30.905159 ==
8434 10:55:30.918170
8435 10:55:30.921321 TX Vref early break, caculate TX vref
8436 10:55:30.925179 TX Vref=16, minBit 1, minWin=22, winSum=377
8437 10:55:30.928477 TX Vref=18, minBit 1, minWin=23, winSum=381
8438 10:55:30.931511 TX Vref=20, minBit 0, minWin=24, winSum=399
8439 10:55:30.934765 TX Vref=22, minBit 1, minWin=23, winSum=400
8440 10:55:30.937903 TX Vref=24, minBit 1, minWin=25, winSum=415
8441 10:55:30.944620 TX Vref=26, minBit 0, minWin=25, winSum=426
8442 10:55:30.948358 TX Vref=28, minBit 0, minWin=25, winSum=423
8443 10:55:30.951377 TX Vref=30, minBit 0, minWin=25, winSum=418
8444 10:55:30.954621 TX Vref=32, minBit 0, minWin=25, winSum=412
8445 10:55:30.958206 TX Vref=34, minBit 2, minWin=24, winSum=402
8446 10:55:30.964839 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8447 10:55:30.964942
8448 10:55:30.967913 Final TX Range 0 Vref 26
8449 10:55:30.968002
8450 10:55:30.968067 ==
8451 10:55:30.971543 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 10:55:30.974643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 10:55:30.974743 ==
8454 10:55:30.974810
8455 10:55:30.974870
8456 10:55:30.978455 TX Vref Scan disable
8457 10:55:30.985217 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8458 10:55:30.985302 == TX Byte 0 ==
8459 10:55:30.988357 u2DelayCellOfst[0]=16 cells (5 PI)
8460 10:55:30.991501 u2DelayCellOfst[1]=10 cells (3 PI)
8461 10:55:30.995364 u2DelayCellOfst[2]=0 cells (0 PI)
8462 10:55:30.998594 u2DelayCellOfst[3]=3 cells (1 PI)
8463 10:55:31.001828 u2DelayCellOfst[4]=6 cells (2 PI)
8464 10:55:31.001912 u2DelayCellOfst[5]=16 cells (5 PI)
8465 10:55:31.004800 u2DelayCellOfst[6]=16 cells (5 PI)
8466 10:55:31.008696 u2DelayCellOfst[7]=3 cells (1 PI)
8467 10:55:31.015021 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8468 10:55:31.018297 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 10:55:31.018382 == TX Byte 1 ==
8470 10:55:31.021485 u2DelayCellOfst[8]=0 cells (0 PI)
8471 10:55:31.024696 u2DelayCellOfst[9]=6 cells (2 PI)
8472 10:55:31.028549 u2DelayCellOfst[10]=13 cells (4 PI)
8473 10:55:31.031806 u2DelayCellOfst[11]=6 cells (2 PI)
8474 10:55:31.034984 u2DelayCellOfst[12]=16 cells (5 PI)
8475 10:55:31.038015 u2DelayCellOfst[13]=16 cells (5 PI)
8476 10:55:31.041380 u2DelayCellOfst[14]=16 cells (5 PI)
8477 10:55:31.044572 u2DelayCellOfst[15]=16 cells (5 PI)
8478 10:55:31.048328 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8479 10:55:31.051282 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8480 10:55:31.054467 DramC Write-DBI on
8481 10:55:31.054553 ==
8482 10:55:31.057765 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 10:55:31.061545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 10:55:31.061629 ==
8485 10:55:31.061695
8486 10:55:31.061782
8487 10:55:31.064563 TX Vref Scan disable
8488 10:55:31.068067 == TX Byte 0 ==
8489 10:55:31.071078 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8490 10:55:31.074688 == TX Byte 1 ==
8491 10:55:31.077828 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8492 10:55:31.077911 DramC Write-DBI off
8493 10:55:31.077991
8494 10:55:31.080990 [DATLAT]
8495 10:55:31.081087 Freq=1600, CH1 RK0
8496 10:55:31.081153
8497 10:55:31.084842 DATLAT Default: 0xf
8498 10:55:31.084925 0, 0xFFFF, sum = 0
8499 10:55:31.087824 1, 0xFFFF, sum = 0
8500 10:55:31.087910 2, 0xFFFF, sum = 0
8501 10:55:31.091431 3, 0xFFFF, sum = 0
8502 10:55:31.091534 4, 0xFFFF, sum = 0
8503 10:55:31.094536 5, 0xFFFF, sum = 0
8504 10:55:31.094622 6, 0xFFFF, sum = 0
8505 10:55:31.098143 7, 0xFFFF, sum = 0
8506 10:55:31.098248 8, 0xFFFF, sum = 0
8507 10:55:31.101438 9, 0xFFFF, sum = 0
8508 10:55:31.104580 10, 0xFFFF, sum = 0
8509 10:55:31.104664 11, 0xFFFF, sum = 0
8510 10:55:31.107741 12, 0xFFFF, sum = 0
8511 10:55:31.107840 13, 0xFFFF, sum = 0
8512 10:55:31.110927 14, 0x0, sum = 1
8513 10:55:31.111011 15, 0x0, sum = 2
8514 10:55:31.114730 16, 0x0, sum = 3
8515 10:55:31.114814 17, 0x0, sum = 4
8516 10:55:31.114881 best_step = 15
8517 10:55:31.114941
8518 10:55:31.118074 ==
8519 10:55:31.121226 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 10:55:31.124376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 10:55:31.124462 ==
8522 10:55:31.124527 RX Vref Scan: 1
8523 10:55:31.124593
8524 10:55:31.127620 Set Vref Range= 24 -> 127
8525 10:55:31.127707
8526 10:55:31.130829 RX Vref 24 -> 127, step: 1
8527 10:55:31.130916
8528 10:55:31.134204 RX Delay 27 -> 252, step: 4
8529 10:55:31.134288
8530 10:55:31.137419 Set Vref, RX VrefLevel [Byte0]: 24
8531 10:55:31.141162 [Byte1]: 24
8532 10:55:31.141249
8533 10:55:31.144296 Set Vref, RX VrefLevel [Byte0]: 25
8534 10:55:31.147683 [Byte1]: 25
8535 10:55:31.147767
8536 10:55:31.150880 Set Vref, RX VrefLevel [Byte0]: 26
8537 10:55:31.154068 [Byte1]: 26
8538 10:55:31.157871
8539 10:55:31.157953 Set Vref, RX VrefLevel [Byte0]: 27
8540 10:55:31.160774 [Byte1]: 27
8541 10:55:31.165256
8542 10:55:31.165336 Set Vref, RX VrefLevel [Byte0]: 28
8543 10:55:31.168519 [Byte1]: 28
8544 10:55:31.172539
8545 10:55:31.172619 Set Vref, RX VrefLevel [Byte0]: 29
8546 10:55:31.176022 [Byte1]: 29
8547 10:55:31.180400
8548 10:55:31.180490 Set Vref, RX VrefLevel [Byte0]: 30
8549 10:55:31.183692 [Byte1]: 30
8550 10:55:31.187510
8551 10:55:31.187593 Set Vref, RX VrefLevel [Byte0]: 31
8552 10:55:31.190726 [Byte1]: 31
8553 10:55:31.195062
8554 10:55:31.195153 Set Vref, RX VrefLevel [Byte0]: 32
8555 10:55:31.198490 [Byte1]: 32
8556 10:55:31.202731
8557 10:55:31.202828 Set Vref, RX VrefLevel [Byte0]: 33
8558 10:55:31.205807 [Byte1]: 33
8559 10:55:31.210115
8560 10:55:31.210212 Set Vref, RX VrefLevel [Byte0]: 34
8561 10:55:31.213738 [Byte1]: 34
8562 10:55:31.217746
8563 10:55:31.217858 Set Vref, RX VrefLevel [Byte0]: 35
8564 10:55:31.220976 [Byte1]: 35
8565 10:55:31.225186
8566 10:55:31.225283 Set Vref, RX VrefLevel [Byte0]: 36
8567 10:55:31.228418 [Byte1]: 36
8568 10:55:31.232947
8569 10:55:31.233048 Set Vref, RX VrefLevel [Byte0]: 37
8570 10:55:31.236011 [Byte1]: 37
8571 10:55:31.240583
8572 10:55:31.240681 Set Vref, RX VrefLevel [Byte0]: 38
8573 10:55:31.243742 [Byte1]: 38
8574 10:55:31.248163
8575 10:55:31.248248 Set Vref, RX VrefLevel [Byte0]: 39
8576 10:55:31.251430 [Byte1]: 39
8577 10:55:31.255225
8578 10:55:31.255310 Set Vref, RX VrefLevel [Byte0]: 40
8579 10:55:31.259216 [Byte1]: 40
8580 10:55:31.262950
8581 10:55:31.263034 Set Vref, RX VrefLevel [Byte0]: 41
8582 10:55:31.266686 [Byte1]: 41
8583 10:55:31.270345
8584 10:55:31.270432 Set Vref, RX VrefLevel [Byte0]: 42
8585 10:55:31.273599 [Byte1]: 42
8586 10:55:31.278497
8587 10:55:31.278581 Set Vref, RX VrefLevel [Byte0]: 43
8588 10:55:31.281423 [Byte1]: 43
8589 10:55:31.285685
8590 10:55:31.285796 Set Vref, RX VrefLevel [Byte0]: 44
8591 10:55:31.288744 [Byte1]: 44
8592 10:55:31.293361
8593 10:55:31.293446 Set Vref, RX VrefLevel [Byte0]: 45
8594 10:55:31.296599 [Byte1]: 45
8595 10:55:31.300454
8596 10:55:31.300533 Set Vref, RX VrefLevel [Byte0]: 46
8597 10:55:31.304238 [Byte1]: 46
8598 10:55:31.308460
8599 10:55:31.308538 Set Vref, RX VrefLevel [Byte0]: 47
8600 10:55:31.311383 [Byte1]: 47
8601 10:55:31.316141
8602 10:55:31.316219 Set Vref, RX VrefLevel [Byte0]: 48
8603 10:55:31.319223 [Byte1]: 48
8604 10:55:31.323159
8605 10:55:31.323237 Set Vref, RX VrefLevel [Byte0]: 49
8606 10:55:31.326355 [Byte1]: 49
8607 10:55:31.330942
8608 10:55:31.331029 Set Vref, RX VrefLevel [Byte0]: 50
8609 10:55:31.334120 [Byte1]: 50
8610 10:55:31.338573
8611 10:55:31.338654 Set Vref, RX VrefLevel [Byte0]: 51
8612 10:55:31.341740 [Byte1]: 51
8613 10:55:31.346076
8614 10:55:31.346152 Set Vref, RX VrefLevel [Byte0]: 52
8615 10:55:31.349087 [Byte1]: 52
8616 10:55:31.353559
8617 10:55:31.353641 Set Vref, RX VrefLevel [Byte0]: 53
8618 10:55:31.356669 [Byte1]: 53
8619 10:55:31.361143
8620 10:55:31.361229 Set Vref, RX VrefLevel [Byte0]: 54
8621 10:55:31.364386 [Byte1]: 54
8622 10:55:31.368236
8623 10:55:31.368311 Set Vref, RX VrefLevel [Byte0]: 55
8624 10:55:31.371436 [Byte1]: 55
8625 10:55:31.375734
8626 10:55:31.375814 Set Vref, RX VrefLevel [Byte0]: 56
8627 10:55:31.379439 [Byte1]: 56
8628 10:55:31.383826
8629 10:55:31.383897 Set Vref, RX VrefLevel [Byte0]: 57
8630 10:55:31.386641 [Byte1]: 57
8631 10:55:31.391020
8632 10:55:31.391100 Set Vref, RX VrefLevel [Byte0]: 58
8633 10:55:31.394784 [Byte1]: 58
8634 10:55:31.398486
8635 10:55:31.398562 Set Vref, RX VrefLevel [Byte0]: 59
8636 10:55:31.401770 [Byte1]: 59
8637 10:55:31.406107
8638 10:55:31.406193 Set Vref, RX VrefLevel [Byte0]: 60
8639 10:55:31.409360 [Byte1]: 60
8640 10:55:31.413708
8641 10:55:31.413837 Set Vref, RX VrefLevel [Byte0]: 61
8642 10:55:31.416951 [Byte1]: 61
8643 10:55:31.421139
8644 10:55:31.421257 Set Vref, RX VrefLevel [Byte0]: 62
8645 10:55:31.424592 [Byte1]: 62
8646 10:55:31.428734
8647 10:55:31.428860 Set Vref, RX VrefLevel [Byte0]: 63
8648 10:55:31.431869 [Byte1]: 63
8649 10:55:31.436334
8650 10:55:31.436420 Set Vref, RX VrefLevel [Byte0]: 64
8651 10:55:31.439514 [Byte1]: 64
8652 10:55:31.443991
8653 10:55:31.444077 Set Vref, RX VrefLevel [Byte0]: 65
8654 10:55:31.447215 [Byte1]: 65
8655 10:55:31.451620
8656 10:55:31.451705 Set Vref, RX VrefLevel [Byte0]: 66
8657 10:55:31.454726 [Byte1]: 66
8658 10:55:31.458555
8659 10:55:31.458639 Set Vref, RX VrefLevel [Byte0]: 67
8660 10:55:31.461881 [Byte1]: 67
8661 10:55:31.466320
8662 10:55:31.466404 Set Vref, RX VrefLevel [Byte0]: 68
8663 10:55:31.469583 [Byte1]: 68
8664 10:55:31.474147
8665 10:55:31.474231 Set Vref, RX VrefLevel [Byte0]: 69
8666 10:55:31.477416 [Byte1]: 69
8667 10:55:31.481631
8668 10:55:31.481716 Set Vref, RX VrefLevel [Byte0]: 70
8669 10:55:31.484822 [Byte1]: 70
8670 10:55:31.489137
8671 10:55:31.489250 Set Vref, RX VrefLevel [Byte0]: 71
8672 10:55:31.492467 [Byte1]: 71
8673 10:55:31.496276
8674 10:55:31.496389 Set Vref, RX VrefLevel [Byte0]: 72
8675 10:55:31.500185 [Byte1]: 72
8676 10:55:31.504276
8677 10:55:31.504396 Set Vref, RX VrefLevel [Byte0]: 73
8678 10:55:31.507559 [Byte1]: 73
8679 10:55:31.511489
8680 10:55:31.511620 Set Vref, RX VrefLevel [Byte0]: 74
8681 10:55:31.515208 [Byte1]: 74
8682 10:55:31.519001
8683 10:55:31.519109 Set Vref, RX VrefLevel [Byte0]: 75
8684 10:55:31.522338 [Byte1]: 75
8685 10:55:31.526652
8686 10:55:31.526765 Final RX Vref Byte 0 = 58 to rank0
8687 10:55:31.529780 Final RX Vref Byte 1 = 57 to rank0
8688 10:55:31.533431 Final RX Vref Byte 0 = 58 to rank1
8689 10:55:31.536445 Final RX Vref Byte 1 = 57 to rank1==
8690 10:55:31.539704 Dram Type= 6, Freq= 0, CH_1, rank 0
8691 10:55:31.546518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8692 10:55:31.546605 ==
8693 10:55:31.546673 DQS Delay:
8694 10:55:31.546736 DQS0 = 0, DQS1 = 0
8695 10:55:31.549772 DQM Delay:
8696 10:55:31.549855 DQM0 = 134, DQM1 = 131
8697 10:55:31.552995 DQ Delay:
8698 10:55:31.556168 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8699 10:55:31.559853 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8700 10:55:31.563183 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8701 10:55:31.566319 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8702 10:55:31.566402
8703 10:55:31.566468
8704 10:55:31.566528
8705 10:55:31.570081 [DramC_TX_OE_Calibration] TA2
8706 10:55:31.573328 Original DQ_B0 (3 6) =30, OEN = 27
8707 10:55:31.576570 Original DQ_B1 (3 6) =30, OEN = 27
8708 10:55:31.579834 24, 0x0, End_B0=24 End_B1=24
8709 10:55:31.579920 25, 0x0, End_B0=25 End_B1=25
8710 10:55:31.582988 26, 0x0, End_B0=26 End_B1=26
8711 10:55:31.586635 27, 0x0, End_B0=27 End_B1=27
8712 10:55:31.589766 28, 0x0, End_B0=28 End_B1=28
8713 10:55:31.592995 29, 0x0, End_B0=29 End_B1=29
8714 10:55:31.593081 30, 0x0, End_B0=30 End_B1=30
8715 10:55:31.596162 31, 0x5151, End_B0=30 End_B1=30
8716 10:55:31.599738 Byte0 end_step=30 best_step=27
8717 10:55:31.602697 Byte1 end_step=30 best_step=27
8718 10:55:31.606302 Byte0 TX OE(2T, 0.5T) = (3, 3)
8719 10:55:31.609466 Byte1 TX OE(2T, 0.5T) = (3, 3)
8720 10:55:31.609551
8721 10:55:31.609617
8722 10:55:31.616066 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8723 10:55:31.619362 CH1 RK0: MR19=303, MR18=1724
8724 10:55:31.626073 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8725 10:55:31.626164
8726 10:55:31.629278 ----->DramcWriteLeveling(PI) begin...
8727 10:55:31.629377 ==
8728 10:55:31.632993 Dram Type= 6, Freq= 0, CH_1, rank 1
8729 10:55:31.636105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 10:55:31.636186 ==
8731 10:55:31.639191 Write leveling (Byte 0): 25 => 25
8732 10:55:31.642830 Write leveling (Byte 1): 28 => 28
8733 10:55:31.646004 DramcWriteLeveling(PI) end<-----
8734 10:55:31.646077
8735 10:55:31.646141 ==
8736 10:55:31.649239 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 10:55:31.653064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 10:55:31.653140 ==
8739 10:55:31.656369 [Gating] SW mode calibration
8740 10:55:31.662504 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8741 10:55:31.669493 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8742 10:55:31.672734 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 10:55:31.675932 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 10:55:31.682444 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8745 10:55:31.686355 1 4 12 | B1->B0 | 3333 2c2b | 1 1 | (1 1) (0 0)
8746 10:55:31.689482 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 10:55:31.696536 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 10:55:31.699587 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 10:55:31.702731 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 10:55:31.709147 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 10:55:31.713040 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8752 10:55:31.715962 1 5 8 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
8753 10:55:31.722665 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8754 10:55:31.725773 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 10:55:31.729017 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 10:55:31.736090 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 10:55:31.739120 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 10:55:31.742844 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 10:55:31.749557 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 10:55:31.752174 1 6 8 | B1->B0 | 3b3b 2424 | 0 0 | (0 0) (0 0)
8761 10:55:31.755819 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 10:55:31.762461 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 10:55:31.765594 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 10:55:31.769212 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 10:55:31.775586 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 10:55:31.778887 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 10:55:31.782191 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8768 10:55:31.788955 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8769 10:55:31.792164 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8770 10:55:31.795504 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 10:55:31.799232 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 10:55:31.805547 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 10:55:31.809206 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 10:55:31.812392 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 10:55:31.819363 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 10:55:31.822486 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 10:55:31.826087 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 10:55:31.832360 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 10:55:31.835872 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 10:55:31.839215 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 10:55:31.845616 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 10:55:31.849145 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 10:55:31.852086 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8784 10:55:31.858978 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8785 10:55:31.862300 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8786 10:55:31.865477 Total UI for P1: 0, mck2ui 16
8787 10:55:31.869401 best dqsien dly found for B1: ( 1, 9, 6)
8788 10:55:31.872580 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 10:55:31.875853 Total UI for P1: 0, mck2ui 16
8790 10:55:31.878896 best dqsien dly found for B0: ( 1, 9, 12)
8791 10:55:31.882031 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8792 10:55:31.885425 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8793 10:55:31.885509
8794 10:55:31.888603 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8795 10:55:31.895806 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8796 10:55:31.895890 [Gating] SW calibration Done
8797 10:55:31.899024 ==
8798 10:55:31.899146 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 10:55:31.905418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 10:55:31.905505 ==
8801 10:55:31.905572 RX Vref Scan: 0
8802 10:55:31.905634
8803 10:55:31.908526 RX Vref 0 -> 0, step: 1
8804 10:55:31.908609
8805 10:55:31.912149 RX Delay 0 -> 252, step: 8
8806 10:55:31.915301 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8807 10:55:31.918572 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8808 10:55:31.921701 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8809 10:55:31.928585 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8810 10:55:31.931747 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8811 10:55:31.935353 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8812 10:55:31.938418 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8813 10:55:31.941594 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8814 10:55:31.948474 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8815 10:55:31.952119 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8816 10:55:31.954957 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8817 10:55:31.958622 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8818 10:55:31.961739 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8819 10:55:31.968410 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8820 10:55:31.972127 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8821 10:55:31.975381 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8822 10:55:31.975479 ==
8823 10:55:31.978585 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 10:55:31.981735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 10:55:31.981847 ==
8826 10:55:31.984960 DQS Delay:
8827 10:55:31.985044 DQS0 = 0, DQS1 = 0
8828 10:55:31.988186 DQM Delay:
8829 10:55:31.988298 DQM0 = 136, DQM1 = 133
8830 10:55:31.988364 DQ Delay:
8831 10:55:31.995357 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8832 10:55:31.998458 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8833 10:55:32.001690 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8834 10:55:32.004962 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8835 10:55:32.005046
8836 10:55:32.005112
8837 10:55:32.005172 ==
8838 10:55:32.008790 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 10:55:32.011905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 10:55:32.011990 ==
8841 10:55:32.012056
8842 10:55:32.012115
8843 10:55:32.014981 TX Vref Scan disable
8844 10:55:32.018683 == TX Byte 0 ==
8845 10:55:32.021916 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8846 10:55:32.025122 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8847 10:55:32.028517 == TX Byte 1 ==
8848 10:55:32.031650 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8849 10:55:32.034847 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8850 10:55:32.034931 ==
8851 10:55:32.038630 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 10:55:32.041687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 10:55:32.044935 ==
8854 10:55:32.056317
8855 10:55:32.059534 TX Vref early break, caculate TX vref
8856 10:55:32.062513 TX Vref=16, minBit 0, minWin=22, winSum=379
8857 10:55:32.066286 TX Vref=18, minBit 0, minWin=24, winSum=394
8858 10:55:32.069329 TX Vref=20, minBit 0, minWin=23, winSum=397
8859 10:55:32.072485 TX Vref=22, minBit 0, minWin=25, winSum=413
8860 10:55:32.075894 TX Vref=24, minBit 0, minWin=25, winSum=420
8861 10:55:32.083049 TX Vref=26, minBit 0, minWin=25, winSum=424
8862 10:55:32.086158 TX Vref=28, minBit 0, minWin=25, winSum=431
8863 10:55:32.089289 TX Vref=30, minBit 0, minWin=26, winSum=424
8864 10:55:32.092620 TX Vref=32, minBit 0, minWin=24, winSum=411
8865 10:55:32.095840 TX Vref=34, minBit 6, minWin=24, winSum=404
8866 10:55:32.103102 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
8867 10:55:32.103186
8868 10:55:32.106168 Final TX Range 0 Vref 30
8869 10:55:32.106253
8870 10:55:32.106319 ==
8871 10:55:32.109508 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 10:55:32.112597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 10:55:32.112688 ==
8874 10:55:32.112753
8875 10:55:32.112813
8876 10:55:32.115761 TX Vref Scan disable
8877 10:55:32.122569 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8878 10:55:32.122653 == TX Byte 0 ==
8879 10:55:32.125707 u2DelayCellOfst[0]=16 cells (5 PI)
8880 10:55:32.129058 u2DelayCellOfst[1]=13 cells (4 PI)
8881 10:55:32.132197 u2DelayCellOfst[2]=0 cells (0 PI)
8882 10:55:32.135446 u2DelayCellOfst[3]=6 cells (2 PI)
8883 10:55:32.139026 u2DelayCellOfst[4]=10 cells (3 PI)
8884 10:55:32.142172 u2DelayCellOfst[5]=16 cells (5 PI)
8885 10:55:32.145289 u2DelayCellOfst[6]=20 cells (6 PI)
8886 10:55:32.148991 u2DelayCellOfst[7]=6 cells (2 PI)
8887 10:55:32.151948 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8888 10:55:32.155624 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8889 10:55:32.158831 == TX Byte 1 ==
8890 10:55:32.158937 u2DelayCellOfst[8]=0 cells (0 PI)
8891 10:55:32.162099 u2DelayCellOfst[9]=3 cells (1 PI)
8892 10:55:32.165095 u2DelayCellOfst[10]=10 cells (3 PI)
8893 10:55:32.168768 u2DelayCellOfst[11]=3 cells (1 PI)
8894 10:55:32.171902 u2DelayCellOfst[12]=13 cells (4 PI)
8895 10:55:32.174962 u2DelayCellOfst[13]=13 cells (4 PI)
8896 10:55:32.178727 u2DelayCellOfst[14]=13 cells (4 PI)
8897 10:55:32.181766 u2DelayCellOfst[15]=16 cells (5 PI)
8898 10:55:32.185309 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8899 10:55:32.191767 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 10:55:32.191855 DramC Write-DBI on
8901 10:55:32.191921 ==
8902 10:55:32.194853 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 10:55:32.201426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 10:55:32.201510 ==
8905 10:55:32.201575
8906 10:55:32.201635
8907 10:55:32.201693 TX Vref Scan disable
8908 10:55:32.205281 == TX Byte 0 ==
8909 10:55:32.208569 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8910 10:55:32.211679 == TX Byte 1 ==
8911 10:55:32.214969 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8912 10:55:32.218827 DramC Write-DBI off
8913 10:55:32.218910
8914 10:55:32.218976 [DATLAT]
8915 10:55:32.219037 Freq=1600, CH1 RK1
8916 10:55:32.219096
8917 10:55:32.221972 DATLAT Default: 0xf
8918 10:55:32.222055 0, 0xFFFF, sum = 0
8919 10:55:32.225247 1, 0xFFFF, sum = 0
8920 10:55:32.228781 2, 0xFFFF, sum = 0
8921 10:55:32.228881 3, 0xFFFF, sum = 0
8922 10:55:32.231765 4, 0xFFFF, sum = 0
8923 10:55:32.231877 5, 0xFFFF, sum = 0
8924 10:55:32.235017 6, 0xFFFF, sum = 0
8925 10:55:32.235101 7, 0xFFFF, sum = 0
8926 10:55:32.238846 8, 0xFFFF, sum = 0
8927 10:55:32.238930 9, 0xFFFF, sum = 0
8928 10:55:32.242006 10, 0xFFFF, sum = 0
8929 10:55:32.242090 11, 0xFFFF, sum = 0
8930 10:55:32.245251 12, 0xFFFF, sum = 0
8931 10:55:32.245335 13, 0xFFFF, sum = 0
8932 10:55:32.248480 14, 0x0, sum = 1
8933 10:55:32.248563 15, 0x0, sum = 2
8934 10:55:32.251784 16, 0x0, sum = 3
8935 10:55:32.251931 17, 0x0, sum = 4
8936 10:55:32.255042 best_step = 15
8937 10:55:32.255124
8938 10:55:32.255190 ==
8939 10:55:32.258668 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 10:55:32.261828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 10:55:32.261912 ==
8942 10:55:32.265437 RX Vref Scan: 0
8943 10:55:32.265541
8944 10:55:32.265621 RX Vref 0 -> 0, step: 1
8945 10:55:32.265681
8946 10:55:32.268468 RX Delay 19 -> 252, step: 4
8947 10:55:32.271675 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8948 10:55:32.278512 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8949 10:55:32.281537 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8950 10:55:32.285262 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8951 10:55:32.288336 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8952 10:55:32.291893 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8953 10:55:32.294858 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8954 10:55:32.301567 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8955 10:55:32.304853 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8956 10:55:32.308691 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8957 10:55:32.311834 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8958 10:55:32.315094 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8959 10:55:32.321720 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8960 10:55:32.324934 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8961 10:55:32.328761 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8962 10:55:32.331899 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8963 10:55:32.331986 ==
8964 10:55:32.334934 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 10:55:32.341541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 10:55:32.341626 ==
8967 10:55:32.341693 DQS Delay:
8968 10:55:32.345412 DQS0 = 0, DQS1 = 0
8969 10:55:32.345496 DQM Delay:
8970 10:55:32.345562 DQM0 = 134, DQM1 = 130
8971 10:55:32.348623 DQ Delay:
8972 10:55:32.351909 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8973 10:55:32.355180 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8974 10:55:32.358462 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8975 10:55:32.361636 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8976 10:55:32.361719
8977 10:55:32.361784
8978 10:55:32.361845
8979 10:55:32.365298 [DramC_TX_OE_Calibration] TA2
8980 10:55:32.368356 Original DQ_B0 (3 6) =30, OEN = 27
8981 10:55:32.371439 Original DQ_B1 (3 6) =30, OEN = 27
8982 10:55:32.374914 24, 0x0, End_B0=24 End_B1=24
8983 10:55:32.374999 25, 0x0, End_B0=25 End_B1=25
8984 10:55:32.378543 26, 0x0, End_B0=26 End_B1=26
8985 10:55:32.381697 27, 0x0, End_B0=27 End_B1=27
8986 10:55:32.384919 28, 0x0, End_B0=28 End_B1=28
8987 10:55:32.388467 29, 0x0, End_B0=29 End_B1=29
8988 10:55:32.388550 30, 0x0, End_B0=30 End_B1=30
8989 10:55:32.391490 31, 0x4141, End_B0=30 End_B1=30
8990 10:55:32.395200 Byte0 end_step=30 best_step=27
8991 10:55:32.398317 Byte1 end_step=30 best_step=27
8992 10:55:32.401488 Byte0 TX OE(2T, 0.5T) = (3, 3)
8993 10:55:32.405063 Byte1 TX OE(2T, 0.5T) = (3, 3)
8994 10:55:32.405184
8995 10:55:32.405287
8996 10:55:32.411446 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8997 10:55:32.414638 CH1 RK1: MR19=303, MR18=2006
8998 10:55:32.421706 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
8999 10:55:32.425013 [RxdqsGatingPostProcess] freq 1600
9000 10:55:32.428273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9001 10:55:32.431466 best DQS0 dly(2T, 0.5T) = (1, 1)
9002 10:55:32.434797 best DQS1 dly(2T, 0.5T) = (1, 1)
9003 10:55:32.437998 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9004 10:55:32.441608 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9005 10:55:32.444691 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 10:55:32.447773 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 10:55:32.451340 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 10:55:32.455061 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 10:55:32.458305 Pre-setting of DQS Precalculation
9010 10:55:32.461612 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9011 10:55:32.468130 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9012 10:55:32.474947 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9013 10:55:32.475030
9014 10:55:32.477877
9015 10:55:32.477954 [Calibration Summary] 3200 Mbps
9016 10:55:32.481461 CH 0, Rank 0
9017 10:55:32.481541 SW Impedance : PASS
9018 10:55:32.485140 DUTY Scan : NO K
9019 10:55:32.488057 ZQ Calibration : PASS
9020 10:55:32.488131 Jitter Meter : NO K
9021 10:55:32.491699 CBT Training : PASS
9022 10:55:32.494741 Write leveling : PASS
9023 10:55:32.494818 RX DQS gating : PASS
9024 10:55:32.497878 RX DQ/DQS(RDDQC) : PASS
9025 10:55:32.501537 TX DQ/DQS : PASS
9026 10:55:32.501618 RX DATLAT : PASS
9027 10:55:32.504562 RX DQ/DQS(Engine): PASS
9028 10:55:32.504637 TX OE : PASS
9029 10:55:32.508077 All Pass.
9030 10:55:32.508170
9031 10:55:32.508266 CH 0, Rank 1
9032 10:55:32.511211 SW Impedance : PASS
9033 10:55:32.511330 DUTY Scan : NO K
9034 10:55:32.514832 ZQ Calibration : PASS
9035 10:55:32.517903 Jitter Meter : NO K
9036 10:55:32.517981 CBT Training : PASS
9037 10:55:32.521613 Write leveling : PASS
9038 10:55:32.524904 RX DQS gating : PASS
9039 10:55:32.525025 RX DQ/DQS(RDDQC) : PASS
9040 10:55:32.528141 TX DQ/DQS : PASS
9041 10:55:32.531305 RX DATLAT : PASS
9042 10:55:32.531414 RX DQ/DQS(Engine): PASS
9043 10:55:32.534555 TX OE : PASS
9044 10:55:32.534630 All Pass.
9045 10:55:32.534709
9046 10:55:32.537808 CH 1, Rank 0
9047 10:55:32.537881 SW Impedance : PASS
9048 10:55:32.541645 DUTY Scan : NO K
9049 10:55:32.544800 ZQ Calibration : PASS
9050 10:55:32.544872 Jitter Meter : NO K
9051 10:55:32.548515 CBT Training : PASS
9052 10:55:32.551533 Write leveling : PASS
9053 10:55:32.551608 RX DQS gating : PASS
9054 10:55:32.554640 RX DQ/DQS(RDDQC) : PASS
9055 10:55:32.554718 TX DQ/DQS : PASS
9056 10:55:32.558360 RX DATLAT : PASS
9057 10:55:32.561325 RX DQ/DQS(Engine): PASS
9058 10:55:32.561399 TX OE : PASS
9059 10:55:32.564606 All Pass.
9060 10:55:32.564683
9061 10:55:32.564763 CH 1, Rank 1
9062 10:55:32.567713 SW Impedance : PASS
9063 10:55:32.567790 DUTY Scan : NO K
9064 10:55:32.571559 ZQ Calibration : PASS
9065 10:55:32.574788 Jitter Meter : NO K
9066 10:55:32.574867 CBT Training : PASS
9067 10:55:32.578051 Write leveling : PASS
9068 10:55:32.581266 RX DQS gating : PASS
9069 10:55:32.581341 RX DQ/DQS(RDDQC) : PASS
9070 10:55:32.584963 TX DQ/DQS : PASS
9071 10:55:32.588156 RX DATLAT : PASS
9072 10:55:32.588231 RX DQ/DQS(Engine): PASS
9073 10:55:32.591169 TX OE : PASS
9074 10:55:32.591270 All Pass.
9075 10:55:32.591400
9076 10:55:32.594841 DramC Write-DBI on
9077 10:55:32.597792 PER_BANK_REFRESH: Hybrid Mode
9078 10:55:32.597867 TX_TRACKING: ON
9079 10:55:32.607926 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9080 10:55:32.614470 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9081 10:55:32.621123 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 10:55:32.624690 [FAST_K] Save calibration result to emmc
9083 10:55:32.627843 sync common calibartion params.
9084 10:55:32.631105 sync cbt_mode0:1, 1:1
9085 10:55:32.634321 dram_init: ddr_geometry: 2
9086 10:55:32.634400 dram_init: ddr_geometry: 2
9087 10:55:32.637553 dram_init: ddr_geometry: 2
9088 10:55:32.640943 0:dram_rank_size:100000000
9089 10:55:32.641023 1:dram_rank_size:100000000
9090 10:55:32.647925 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9091 10:55:32.651057 DFS_SHUFFLE_HW_MODE: ON
9092 10:55:32.654199 dramc_set_vcore_voltage set vcore to 725000
9093 10:55:32.657494 Read voltage for 1600, 0
9094 10:55:32.657574 Vio18 = 0
9095 10:55:32.657678 Vcore = 725000
9096 10:55:32.661414 Vdram = 0
9097 10:55:32.661524 Vddq = 0
9098 10:55:32.661631 Vmddr = 0
9099 10:55:32.664514 switch to 3200 Mbps bootup
9100 10:55:32.664613 [DramcRunTimeConfig]
9101 10:55:32.668365 PHYPLL
9102 10:55:32.668480 DPM_CONTROL_AFTERK: ON
9103 10:55:32.671426 PER_BANK_REFRESH: ON
9104 10:55:32.674408 REFRESH_OVERHEAD_REDUCTION: ON
9105 10:55:32.674508 CMD_PICG_NEW_MODE: OFF
9106 10:55:32.677702 XRTWTW_NEW_MODE: ON
9107 10:55:32.677805 XRTRTR_NEW_MODE: ON
9108 10:55:32.680902 TX_TRACKING: ON
9109 10:55:32.680975 RDSEL_TRACKING: OFF
9110 10:55:32.684256 DQS Precalculation for DVFS: ON
9111 10:55:32.687418 RX_TRACKING: OFF
9112 10:55:32.687493 HW_GATING DBG: ON
9113 10:55:32.691243 ZQCS_ENABLE_LP4: ON
9114 10:55:32.691318 RX_PICG_NEW_MODE: ON
9115 10:55:32.694425 TX_PICG_NEW_MODE: ON
9116 10:55:32.694499 ENABLE_RX_DCM_DPHY: ON
9117 10:55:32.698092 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9118 10:55:32.701137 DUMMY_READ_FOR_TRACKING: OFF
9119 10:55:32.704642 !!! SPM_CONTROL_AFTERK: OFF
9120 10:55:32.707609 !!! SPM could not control APHY
9121 10:55:32.707686 IMPEDANCE_TRACKING: ON
9122 10:55:32.711031 TEMP_SENSOR: ON
9123 10:55:32.711105 HW_SAVE_FOR_SR: OFF
9124 10:55:32.714785 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9125 10:55:32.717786 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9126 10:55:32.720830 Read ODT Tracking: ON
9127 10:55:32.724308 Refresh Rate DeBounce: ON
9128 10:55:32.724419 DFS_NO_QUEUE_FLUSH: ON
9129 10:55:32.727891 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9130 10:55:32.730940 ENABLE_DFS_RUNTIME_MRW: OFF
9131 10:55:32.734058 DDR_RESERVE_NEW_MODE: ON
9132 10:55:32.734136 MR_CBT_SWITCH_FREQ: ON
9133 10:55:32.737912 =========================
9134 10:55:32.756429 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9135 10:55:32.759623 dram_init: ddr_geometry: 2
9136 10:55:32.777753 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9137 10:55:32.781549 dram_init: dram init end (result: 0)
9138 10:55:32.788147 DRAM-K: Full calibration passed in 24455 msecs
9139 10:55:32.791278 MRC: failed to locate region type 0.
9140 10:55:32.791435 DRAM rank0 size:0x100000000,
9141 10:55:32.794541 DRAM rank1 size=0x100000000
9142 10:55:32.804507 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9143 10:55:32.811204 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9144 10:55:32.817915 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9145 10:55:32.824277 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9146 10:55:32.827926 DRAM rank0 size:0x100000000,
9147 10:55:32.830890 DRAM rank1 size=0x100000000
9148 10:55:32.831029 CBMEM:
9149 10:55:32.834029 IMD: root @ 0xfffff000 254 entries.
9150 10:55:32.837592 IMD: root @ 0xffffec00 62 entries.
9151 10:55:32.841360 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9152 10:55:32.844546 WARNING: RO_VPD is uninitialized or empty.
9153 10:55:32.850890 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9154 10:55:32.858020 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9155 10:55:32.870695 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9156 10:55:32.882024 BS: romstage times (exec / console): total (unknown) / 23983 ms
9157 10:55:32.882198
9158 10:55:32.882282
9159 10:55:32.891757 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9160 10:55:32.895609 ARM64: Exception handlers installed.
9161 10:55:32.898864 ARM64: Testing exception
9162 10:55:32.901929 ARM64: Done test exception
9163 10:55:32.902026 Enumerating buses...
9164 10:55:32.905261 Show all devs... Before device enumeration.
9165 10:55:32.908386 Root Device: enabled 1
9166 10:55:32.912118 CPU_CLUSTER: 0: enabled 1
9167 10:55:32.912221 CPU: 00: enabled 1
9168 10:55:32.915145 Compare with tree...
9169 10:55:32.915235 Root Device: enabled 1
9170 10:55:32.918734 CPU_CLUSTER: 0: enabled 1
9171 10:55:32.921868 CPU: 00: enabled 1
9172 10:55:32.921965 Root Device scanning...
9173 10:55:32.925459 scan_static_bus for Root Device
9174 10:55:32.928703 CPU_CLUSTER: 0 enabled
9175 10:55:32.931934 scan_static_bus for Root Device done
9176 10:55:32.935520 scan_bus: bus Root Device finished in 8 msecs
9177 10:55:32.935677 done
9178 10:55:32.942112 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9179 10:55:32.945175 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9180 10:55:32.952074 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9181 10:55:32.955385 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9182 10:55:32.958561 Allocating resources...
9183 10:55:32.961694 Reading resources...
9184 10:55:32.965409 Root Device read_resources bus 0 link: 0
9185 10:55:32.965508 DRAM rank0 size:0x100000000,
9186 10:55:32.968451 DRAM rank1 size=0x100000000
9187 10:55:32.971721 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9188 10:55:32.974907 CPU: 00 missing read_resources
9189 10:55:32.978580 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9190 10:55:32.984987 Root Device read_resources bus 0 link: 0 done
9191 10:55:32.985114 Done reading resources.
9192 10:55:32.991685 Show resources in subtree (Root Device)...After reading.
9193 10:55:32.994796 Root Device child on link 0 CPU_CLUSTER: 0
9194 10:55:32.998640 CPU_CLUSTER: 0 child on link 0 CPU: 00
9195 10:55:33.008226 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9196 10:55:33.008318 CPU: 00
9197 10:55:33.011528 Root Device assign_resources, bus 0 link: 0
9198 10:55:33.014671 CPU_CLUSTER: 0 missing set_resources
9199 10:55:33.021404 Root Device assign_resources, bus 0 link: 0 done
9200 10:55:33.021543 Done setting resources.
9201 10:55:33.028121 Show resources in subtree (Root Device)...After assigning values.
9202 10:55:33.031649 Root Device child on link 0 CPU_CLUSTER: 0
9203 10:55:33.034900 CPU_CLUSTER: 0 child on link 0 CPU: 00
9204 10:55:33.044540 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9205 10:55:33.044651 CPU: 00
9206 10:55:33.047982 Done allocating resources.
9207 10:55:33.051539 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9208 10:55:33.054488 Enabling resources...
9209 10:55:33.054588 done.
9210 10:55:33.061375 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9211 10:55:33.061481 Initializing devices...
9212 10:55:33.064597 Root Device init
9213 10:55:33.064678 init hardware done!
9214 10:55:33.068358 0x00000018: ctrlr->caps
9215 10:55:33.071477 52.000 MHz: ctrlr->f_max
9216 10:55:33.071554 0.400 MHz: ctrlr->f_min
9217 10:55:33.074801 0x40ff8080: ctrlr->voltages
9218 10:55:33.074907 sclk: 390625
9219 10:55:33.078015 Bus Width = 1
9220 10:55:33.078114 sclk: 390625
9221 10:55:33.081136 Bus Width = 1
9222 10:55:33.081226 Early init status = 3
9223 10:55:33.087694 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9224 10:55:33.090952 in-header: 03 fc 00 00 01 00 00 00
9225 10:55:33.091058 in-data: 00
9226 10:55:33.097790 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9227 10:55:33.100743 in-header: 03 fd 00 00 00 00 00 00
9228 10:55:33.103986 in-data:
9229 10:55:33.107215 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9230 10:55:33.111474 in-header: 03 fc 00 00 01 00 00 00
9231 10:55:33.114757 in-data: 00
9232 10:55:33.117928 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9233 10:55:33.123633 in-header: 03 fd 00 00 00 00 00 00
9234 10:55:33.126713 in-data:
9235 10:55:33.129793 [SSUSB] Setting up USB HOST controller...
9236 10:55:33.133377 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9237 10:55:33.136971 [SSUSB] phy power-on done.
9238 10:55:33.140151 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9239 10:55:33.146757 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9240 10:55:33.149741 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9241 10:55:33.156489 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9242 10:55:33.163119 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9243 10:55:33.170115 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9244 10:55:33.176429 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9245 10:55:33.182979 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9246 10:55:33.186668 SPM: binary array size = 0x9dc
9247 10:55:33.190000 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9248 10:55:33.196477 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9249 10:55:33.202973 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9250 10:55:33.209761 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9251 10:55:33.212845 configure_display: Starting display init
9252 10:55:33.246841 anx7625_power_on_init: Init interface.
9253 10:55:33.250202 anx7625_disable_pd_protocol: Disabled PD feature.
9254 10:55:33.253220 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9255 10:55:33.281668 anx7625_start_dp_work: Secure OCM version=00
9256 10:55:33.284740 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9257 10:55:33.299552 sp_tx_get_edid_block: EDID Block = 1
9258 10:55:33.402073 Extracted contents:
9259 10:55:33.405245 header: 00 ff ff ff ff ff ff 00
9260 10:55:33.408613 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9261 10:55:33.411706 version: 01 04
9262 10:55:33.415505 basic params: 95 1f 11 78 0a
9263 10:55:33.418591 chroma info: 76 90 94 55 54 90 27 21 50 54
9264 10:55:33.421764 established: 00 00 00
9265 10:55:33.428499 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9266 10:55:33.431600 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9267 10:55:33.438563 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9268 10:55:33.445221 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9269 10:55:33.451301 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9270 10:55:33.454815 extensions: 00
9271 10:55:33.454916 checksum: fb
9272 10:55:33.455011
9273 10:55:33.457982 Manufacturer: IVO Model 57d Serial Number 0
9274 10:55:33.461772 Made week 0 of 2020
9275 10:55:33.461871 EDID version: 1.4
9276 10:55:33.464910 Digital display
9277 10:55:33.468064 6 bits per primary color channel
9278 10:55:33.468162 DisplayPort interface
9279 10:55:33.471263 Maximum image size: 31 cm x 17 cm
9280 10:55:33.475056 Gamma: 220%
9281 10:55:33.475197 Check DPMS levels
9282 10:55:33.478217 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9283 10:55:33.484390 First detailed timing is preferred timing
9284 10:55:33.484496 Established timings supported:
9285 10:55:33.488066 Standard timings supported:
9286 10:55:33.491298 Detailed timings
9287 10:55:33.494509 Hex of detail: 383680a07038204018303c0035ae10000019
9288 10:55:33.497628 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9289 10:55:33.504744 0780 0798 07c8 0820 hborder 0
9290 10:55:33.507884 0438 043b 0447 0458 vborder 0
9291 10:55:33.511091 -hsync -vsync
9292 10:55:33.511192 Did detailed timing
9293 10:55:33.518052 Hex of detail: 000000000000000000000000000000000000
9294 10:55:33.518177 Manufacturer-specified data, tag 0
9295 10:55:33.524344 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9296 10:55:33.527431 ASCII string: InfoVision
9297 10:55:33.531283 Hex of detail: 000000fe00523134304e574635205248200a
9298 10:55:33.534403 ASCII string: R140NWF5 RH
9299 10:55:33.534494 Checksum
9300 10:55:33.537584 Checksum: 0xfb (valid)
9301 10:55:33.541091 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9302 10:55:33.544215 DSI data_rate: 832800000 bps
9303 10:55:33.551196 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9304 10:55:33.554426 anx7625_parse_edid: pixelclock(138800).
9305 10:55:33.558058 hactive(1920), hsync(48), hfp(24), hbp(88)
9306 10:55:33.561207 vactive(1080), vsync(12), vfp(3), vbp(17)
9307 10:55:33.564398 anx7625_dsi_config: config dsi.
9308 10:55:33.571132 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9309 10:55:33.583942 anx7625_dsi_config: success to config DSI
9310 10:55:33.587410 anx7625_dp_start: MIPI phy setup OK.
9311 10:55:33.590402 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9312 10:55:33.594029 mtk_ddp_mode_set invalid vrefresh 60
9313 10:55:33.597264 main_disp_path_setup
9314 10:55:33.597354 ovl_layer_smi_id_en
9315 10:55:33.600520 ovl_layer_smi_id_en
9316 10:55:33.600622 ccorr_config
9317 10:55:33.600709 aal_config
9318 10:55:33.603578 gamma_config
9319 10:55:33.603673 postmask_config
9320 10:55:33.607529 dither_config
9321 10:55:33.610759 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9322 10:55:33.617177 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9323 10:55:33.620435 Root Device init finished in 552 msecs
9324 10:55:33.620554 CPU_CLUSTER: 0 init
9325 10:55:33.630704 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9326 10:55:33.634022 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9327 10:55:33.637200 APU_MBOX 0x190000b0 = 0x10001
9328 10:55:33.640832 APU_MBOX 0x190001b0 = 0x10001
9329 10:55:33.643875 APU_MBOX 0x190005b0 = 0x10001
9330 10:55:33.647070 APU_MBOX 0x190006b0 = 0x10001
9331 10:55:33.650720 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9332 10:55:33.662642 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9333 10:55:33.675499 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9334 10:55:33.681896 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9335 10:55:33.693412 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9336 10:55:33.702704 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9337 10:55:33.705825 CPU_CLUSTER: 0 init finished in 81 msecs
9338 10:55:33.709103 Devices initialized
9339 10:55:33.712390 Show all devs... After init.
9340 10:55:33.712462 Root Device: enabled 1
9341 10:55:33.716188 CPU_CLUSTER: 0: enabled 1
9342 10:55:33.719392 CPU: 00: enabled 1
9343 10:55:33.722562 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9344 10:55:33.725711 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9345 10:55:33.729425 ELOG: NV offset 0x57f000 size 0x1000
9346 10:55:33.736156 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9347 10:55:33.742563 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9348 10:55:33.746338 ELOG: Event(17) added with size 13 at 2023-06-05 10:55:21 UTC
9349 10:55:33.749484 out: cmd=0x121: 03 db 21 01 00 00 00 00
9350 10:55:33.753369 in-header: 03 dc 00 00 2c 00 00 00
9351 10:55:33.766351 in-data: 83 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9352 10:55:33.773121 ELOG: Event(A1) added with size 10 at 2023-06-05 10:55:21 UTC
9353 10:55:33.779594 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9354 10:55:33.785932 ELOG: Event(A0) added with size 9 at 2023-06-05 10:55:21 UTC
9355 10:55:33.789123 elog_add_boot_reason: Logged dev mode boot
9356 10:55:33.792546 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9357 10:55:33.795813 Finalize devices...
9358 10:55:33.795905 Devices finalized
9359 10:55:33.802424 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9360 10:55:33.806066 Writing coreboot table at 0xffe64000
9361 10:55:33.809617 0. 000000000010a000-0000000000113fff: RAMSTAGE
9362 10:55:33.812635 1. 0000000040000000-00000000400fffff: RAM
9363 10:55:33.819015 2. 0000000040100000-000000004032afff: RAMSTAGE
9364 10:55:33.822948 3. 000000004032b000-00000000545fffff: RAM
9365 10:55:33.826023 4. 0000000054600000-000000005465ffff: BL31
9366 10:55:33.829174 5. 0000000054660000-00000000ffe63fff: RAM
9367 10:55:33.835543 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9368 10:55:33.839429 7. 0000000100000000-000000023fffffff: RAM
9369 10:55:33.839537 Passing 5 GPIOs to payload:
9370 10:55:33.845916 NAME | PORT | POLARITY | VALUE
9371 10:55:33.849163 EC in RW | 0x000000aa | low | undefined
9372 10:55:33.855467 EC interrupt | 0x00000005 | low | undefined
9373 10:55:33.859173 TPM interrupt | 0x000000ab | high | undefined
9374 10:55:33.862286 SD card detect | 0x00000011 | high | undefined
9375 10:55:33.869244 speaker enable | 0x00000093 | high | undefined
9376 10:55:33.872472 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9377 10:55:33.875485 in-header: 03 f9 00 00 02 00 00 00
9378 10:55:33.875563 in-data: 02 00
9379 10:55:33.878623 ADC[4]: Raw value=904726 ID=7
9380 10:55:33.882341 ADC[3]: Raw value=213810 ID=1
9381 10:55:33.885357 RAM Code: 0x71
9382 10:55:33.885455 ADC[6]: Raw value=75701 ID=0
9383 10:55:33.888980 ADC[5]: Raw value=212703 ID=1
9384 10:55:33.891947 SKU Code: 0x1
9385 10:55:33.895737 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9386 10:55:33.898947 coreboot table: 964 bytes.
9387 10:55:33.902073 IMD ROOT 0. 0xfffff000 0x00001000
9388 10:55:33.905250 IMD SMALL 1. 0xffffe000 0x00001000
9389 10:55:33.909151 RO MCACHE 2. 0xffffc000 0x00001104
9390 10:55:33.911959 CONSOLE 3. 0xfff7c000 0x00080000
9391 10:55:33.915779 FMAP 4. 0xfff7b000 0x00000452
9392 10:55:33.918823 TIME STAMP 5. 0xfff7a000 0x00000910
9393 10:55:33.922436 VBOOT WORK 6. 0xfff66000 0x00014000
9394 10:55:33.925597 RAMOOPS 7. 0xffe66000 0x00100000
9395 10:55:33.928788 COREBOOT 8. 0xffe64000 0x00002000
9396 10:55:33.928890 IMD small region:
9397 10:55:33.932044 IMD ROOT 0. 0xffffec00 0x00000400
9398 10:55:33.935723 VPD 1. 0xffffeba0 0x0000004c
9399 10:55:33.938950 MMC STATUS 2. 0xffffeb80 0x00000004
9400 10:55:33.945468 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9401 10:55:33.949282 Probing TPM: done!
9402 10:55:33.952418 Connected to device vid:did:rid of 1ae0:0028:00
9403 10:55:33.962697 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9404 10:55:33.965434 Initialized TPM device CR50 revision 0
9405 10:55:33.969046 Checking cr50 for pending updates
9406 10:55:33.972890 Reading cr50 TPM mode
9407 10:55:33.981216 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9408 10:55:33.987633 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9409 10:55:34.028182 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9410 10:55:34.031428 Checking segment from ROM address 0x40100000
9411 10:55:34.034917 Checking segment from ROM address 0x4010001c
9412 10:55:34.041144 Loading segment from ROM address 0x40100000
9413 10:55:34.041270 code (compression=0)
9414 10:55:34.051534 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9415 10:55:34.057787 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9416 10:55:34.057947 it's not compressed!
9417 10:55:34.064875 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9418 10:55:34.068183 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9419 10:55:34.088156 Loading segment from ROM address 0x4010001c
9420 10:55:34.088335 Entry Point 0x80000000
9421 10:55:34.091979 Loaded segments
9422 10:55:34.095126 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9423 10:55:34.101313 Jumping to boot code at 0x80000000(0xffe64000)
9424 10:55:34.107986 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9425 10:55:34.114788 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9426 10:55:34.123070 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9427 10:55:34.126365 Checking segment from ROM address 0x40100000
9428 10:55:34.129576 Checking segment from ROM address 0x4010001c
9429 10:55:34.136378 Loading segment from ROM address 0x40100000
9430 10:55:34.136513 code (compression=1)
9431 10:55:34.143047 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9432 10:55:34.152653 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9433 10:55:34.152762 using LZMA
9434 10:55:34.160895 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9435 10:55:34.168016 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9436 10:55:34.171170 Loading segment from ROM address 0x4010001c
9437 10:55:34.171270 Entry Point 0x54601000
9438 10:55:34.174447 Loaded segments
9439 10:55:34.177566 NOTICE: MT8192 bl31_setup
9440 10:55:34.184520 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9441 10:55:34.187815 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9442 10:55:34.191562 WARNING: region 0:
9443 10:55:34.194627 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 10:55:34.194722 WARNING: region 1:
9445 10:55:34.201773 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9446 10:55:34.204819 WARNING: region 2:
9447 10:55:34.207958 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9448 10:55:34.211571 WARNING: region 3:
9449 10:55:34.214653 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 10:55:34.217803 WARNING: region 4:
9451 10:55:34.224456 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 10:55:34.224582 WARNING: region 5:
9453 10:55:34.228311 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 10:55:34.231650 WARNING: region 6:
9455 10:55:34.234711 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 10:55:34.237881 WARNING: region 7:
9457 10:55:34.241631 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 10:55:34.247848 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9459 10:55:34.251430 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9460 10:55:34.254770 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9461 10:55:34.261851 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9462 10:55:34.265081 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9463 10:55:34.268297 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9464 10:55:34.274748 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9465 10:55:34.277982 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9466 10:55:34.281897 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9467 10:55:34.288094 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9468 10:55:34.291252 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9469 10:55:34.298128 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9470 10:55:34.301322 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9471 10:55:34.305205 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9472 10:55:34.311462 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9473 10:55:34.314443 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9474 10:55:34.317981 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9475 10:55:34.324786 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9476 10:55:34.328337 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9477 10:55:34.334866 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9478 10:55:34.338094 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9479 10:55:34.341261 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9480 10:55:34.348264 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9481 10:55:34.351478 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9482 10:55:34.358371 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9483 10:55:34.361422 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9484 10:55:34.364713 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9485 10:55:34.371775 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9486 10:55:34.374852 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9487 10:55:34.378259 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9488 10:55:34.384749 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9489 10:55:34.388641 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9490 10:55:34.391785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9491 10:55:34.397995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9492 10:55:34.401775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9493 10:55:34.404888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9494 10:55:34.408098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9495 10:55:34.415128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9496 10:55:34.418775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9497 10:55:34.421640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9498 10:55:34.425241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9499 10:55:34.431969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9500 10:55:34.434884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9501 10:55:34.438165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9502 10:55:34.442046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9503 10:55:34.448466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9504 10:55:34.451771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9505 10:55:34.455011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9506 10:55:34.462128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9507 10:55:34.464885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9508 10:55:34.468606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9509 10:55:34.474985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9510 10:55:34.478228 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9511 10:55:34.485237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9512 10:55:34.488510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9513 10:55:34.494911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9514 10:55:34.498803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9515 10:55:34.501969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9516 10:55:34.508143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9517 10:55:34.511971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9518 10:55:34.518472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9519 10:55:34.521534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9520 10:55:34.528150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9521 10:55:34.531964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9522 10:55:34.534961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9523 10:55:34.541671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9524 10:55:34.545322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9525 10:55:34.552202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9526 10:55:34.555410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9527 10:55:34.561837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9528 10:55:34.565055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9529 10:55:34.568883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9530 10:55:34.575430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9531 10:55:34.578406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9532 10:55:34.585159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9533 10:55:34.589007 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9534 10:55:34.595425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9535 10:55:34.598606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9536 10:55:34.602419 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9537 10:55:34.608830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9538 10:55:34.612389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9539 10:55:34.618666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9540 10:55:34.621856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9541 10:55:34.628752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9542 10:55:34.632419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9543 10:55:34.635430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9544 10:55:34.642090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9545 10:55:34.645747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9546 10:55:34.652631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9547 10:55:34.655658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9548 10:55:34.659462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9549 10:55:34.665915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9550 10:55:34.669090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9551 10:55:34.676212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9552 10:55:34.679765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9553 10:55:34.685746 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9554 10:55:34.689438 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9555 10:55:34.693090 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9556 10:55:34.696223 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9557 10:55:34.702595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9558 10:55:34.705922 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9559 10:55:34.709071 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9560 10:55:34.715887 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9561 10:55:34.719459 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9562 10:55:34.722614 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9563 10:55:34.729683 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9564 10:55:34.732820 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9565 10:55:34.739735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9566 10:55:34.742711 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9567 10:55:34.746226 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9568 10:55:34.752966 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9569 10:55:34.755798 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9570 10:55:34.762827 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9571 10:55:34.766010 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9572 10:55:34.769251 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9573 10:55:34.776419 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9574 10:55:34.779512 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9575 10:55:34.782787 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9576 10:55:34.789694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9577 10:55:34.792890 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9578 10:55:34.796033 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9579 10:55:34.799787 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9580 10:55:34.802868 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9581 10:55:34.809354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9582 10:55:34.812603 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9583 10:55:34.819662 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9584 10:55:34.822705 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9585 10:55:34.826422 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9586 10:55:34.832736 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9587 10:55:34.835929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9588 10:55:34.839767 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9589 10:55:34.845955 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9590 10:55:34.849672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9591 10:55:34.856441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9592 10:55:34.859351 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9593 10:55:34.862936 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9594 10:55:34.869765 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9595 10:55:34.872981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9596 10:55:34.879472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9597 10:55:34.882721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9598 10:55:34.886525 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9599 10:55:34.892856 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9600 10:55:34.896666 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9601 10:55:34.903102 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9602 10:55:34.906298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9603 10:55:34.909944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9604 10:55:34.916141 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9605 10:55:34.920030 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9606 10:55:34.923259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9607 10:55:34.929611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9608 10:55:34.933251 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9609 10:55:34.936419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9610 10:55:34.943454 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9611 10:55:34.946653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9612 10:55:34.953354 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9613 10:55:34.956530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9614 10:55:34.959541 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9615 10:55:34.966412 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9616 10:55:34.969549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9617 10:55:34.976223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9618 10:55:34.980212 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9619 10:55:34.983298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9620 10:55:34.989865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9621 10:55:34.993157 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9622 10:55:35.000172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9623 10:55:35.003491 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9624 10:55:35.006680 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9625 10:55:35.012906 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9626 10:55:35.016571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9627 10:55:35.019728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9628 10:55:35.026686 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9629 10:55:35.029897 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9630 10:55:35.036685 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9631 10:55:35.039819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9632 10:55:35.042924 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9633 10:55:35.049427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9634 10:55:35.053178 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9635 10:55:35.059291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9636 10:55:35.063052 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9637 10:55:35.066083 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9638 10:55:35.072667 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9639 10:55:35.075801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9640 10:55:35.082386 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9641 10:55:35.086196 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9642 10:55:35.089429 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9643 10:55:35.095902 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9644 10:55:35.099113 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9645 10:55:35.106098 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9646 10:55:35.109417 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9647 10:55:35.112470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9648 10:55:35.119332 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9649 10:55:35.122567 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9650 10:55:35.128839 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9651 10:55:35.132671 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9652 10:55:35.135936 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9653 10:55:35.142205 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9654 10:55:35.145718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9655 10:55:35.152720 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9656 10:55:35.155950 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9657 10:55:35.161986 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9658 10:55:35.165779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9659 10:55:35.168890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9660 10:55:35.175500 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9661 10:55:35.179171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9662 10:55:35.185156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9663 10:55:35.188860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9664 10:55:35.195294 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9665 10:55:35.198519 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9666 10:55:35.202431 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9667 10:55:35.208700 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9668 10:55:35.211966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9669 10:55:35.218907 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9670 10:55:35.222096 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9671 10:55:35.225253 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9672 10:55:35.232111 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9673 10:55:35.235303 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9674 10:55:35.241885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9675 10:55:35.245045 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9676 10:55:35.251941 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9677 10:55:35.255024 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9678 10:55:35.258282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9679 10:55:35.265305 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9680 10:55:35.268373 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9681 10:55:35.275318 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9682 10:55:35.278529 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9683 10:55:35.281658 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9684 10:55:35.288303 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9685 10:55:35.291824 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9686 10:55:35.298453 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9687 10:55:35.301787 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9688 10:55:35.304981 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9689 10:55:35.308136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9690 10:55:35.314724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9691 10:55:35.317943 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9692 10:55:35.321162 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9693 10:55:35.328075 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9694 10:55:35.331237 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9695 10:55:35.334353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9696 10:55:35.341317 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9697 10:55:35.344527 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9698 10:55:35.347788 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9699 10:55:35.354698 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9700 10:55:35.357658 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9701 10:55:35.361300 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9702 10:55:35.367615 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9703 10:55:35.370796 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9704 10:55:35.377683 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9705 10:55:35.380682 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9706 10:55:35.384231 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9707 10:55:35.390741 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9708 10:55:35.393845 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9709 10:55:35.400934 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9710 10:55:35.404345 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9711 10:55:35.407557 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9712 10:55:35.414049 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9713 10:55:35.417336 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9714 10:55:35.420533 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9715 10:55:35.427602 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9716 10:55:35.430769 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9717 10:55:35.433931 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9718 10:55:35.440337 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9719 10:55:35.444112 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9720 10:55:35.450682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9721 10:55:35.453853 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9722 10:55:35.457060 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9723 10:55:35.464050 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9724 10:55:35.467143 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9725 10:55:35.470398 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9726 10:55:35.476864 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9727 10:55:35.480670 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9728 10:55:35.483854 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9729 10:55:35.487082 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9730 10:55:35.493648 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9731 10:55:35.497435 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9732 10:55:35.500445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9733 10:55:35.503940 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9734 10:55:35.507318 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9735 10:55:35.513898 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9736 10:55:35.516973 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9737 10:55:35.520247 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9738 10:55:35.526684 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9739 10:55:35.530598 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9740 10:55:35.533785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9741 10:55:35.540595 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9742 10:55:35.543809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9743 10:55:35.550013 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9744 10:55:35.553971 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9745 10:55:35.557098 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9746 10:55:35.563268 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9747 10:55:35.567065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9748 10:55:35.573529 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9749 10:55:35.576663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9750 10:55:35.579778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9751 10:55:35.586856 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9752 10:55:35.590261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9753 10:55:35.596911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9754 10:55:35.599730 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9755 10:55:35.603543 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9756 10:55:35.609903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9757 10:55:35.613481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9758 10:55:35.619851 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9759 10:55:35.623440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9760 10:55:35.629689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9761 10:55:35.632854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9762 10:55:35.636597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9763 10:55:35.643206 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9764 10:55:35.646330 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9765 10:55:35.653204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9766 10:55:35.656194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9767 10:55:35.659320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9768 10:55:35.666341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9769 10:55:35.669593 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9770 10:55:35.676083 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9771 10:55:35.679446 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9772 10:55:35.682531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9773 10:55:35.689434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9774 10:55:35.692646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9775 10:55:35.699801 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9776 10:55:35.702875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9777 10:55:35.709546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9778 10:55:35.712630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9779 10:55:35.716161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9780 10:55:35.722381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9781 10:55:35.725846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9782 10:55:35.732390 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9783 10:55:35.735618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9784 10:55:35.739322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9785 10:55:35.745757 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9786 10:55:35.749047 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9787 10:55:35.756054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9788 10:55:35.759211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9789 10:55:35.762248 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9790 10:55:35.769303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9791 10:55:35.772402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9792 10:55:35.779014 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9793 10:55:35.782683 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9794 10:55:35.785924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9795 10:55:35.792787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9796 10:55:35.796067 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9797 10:55:35.802451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9798 10:55:35.805657 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9799 10:55:35.809052 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9800 10:55:35.815697 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9801 10:55:35.818744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9802 10:55:35.825333 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9803 10:55:35.828870 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9804 10:55:35.835130 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9805 10:55:35.838710 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9806 10:55:35.841949 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9807 10:55:35.848688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9808 10:55:35.851932 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9809 10:55:35.858377 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9810 10:55:35.861703 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9811 10:55:35.864855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9812 10:55:35.871604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9813 10:55:35.874758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9814 10:55:35.881798 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9815 10:55:35.885016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9816 10:55:35.892062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9817 10:55:35.894846 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9818 10:55:35.901466 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9819 10:55:35.904825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9820 10:55:35.908656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9821 10:55:35.915056 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9822 10:55:35.918256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9823 10:55:35.925120 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9824 10:55:35.928626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9825 10:55:35.931623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9826 10:55:35.938363 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9827 10:55:35.941989 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9828 10:55:35.948730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9829 10:55:35.951807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9830 10:55:35.958238 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9831 10:55:35.961995 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9832 10:55:35.968446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9833 10:55:35.971756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9834 10:55:35.974703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9835 10:55:35.981458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9836 10:55:35.984728 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9837 10:55:35.991787 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9838 10:55:35.995054 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9839 10:55:36.001515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9840 10:55:36.004576 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9841 10:55:36.008224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9842 10:55:36.014633 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9843 10:55:36.017787 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9844 10:55:36.024945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9845 10:55:36.027969 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9846 10:55:36.034628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9847 10:55:36.037690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9848 10:55:36.041332 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9849 10:55:36.047754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9850 10:55:36.051364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9851 10:55:36.057618 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9852 10:55:36.061236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9853 10:55:36.067824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9854 10:55:36.071049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9855 10:55:36.074914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9856 10:55:36.081079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9857 10:55:36.084769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9858 10:55:36.090990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9859 10:55:36.094925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9860 10:55:36.098000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9861 10:55:36.104450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9862 10:55:36.108168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9863 10:55:36.114347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9864 10:55:36.118021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9865 10:55:36.124526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9866 10:55:36.127772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9867 10:55:36.134275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9868 10:55:36.138046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9869 10:55:36.144686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9870 10:55:36.147717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9871 10:55:36.154281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9872 10:55:36.158057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9873 10:55:36.164263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9874 10:55:36.167883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9875 10:55:36.174350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9876 10:55:36.177532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9877 10:55:36.180732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9878 10:55:36.187515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9879 10:55:36.190613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9880 10:55:36.197398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9881 10:55:36.200641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9882 10:55:36.207151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9883 10:55:36.214258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9884 10:55:36.217465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9885 10:55:36.224197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9886 10:55:36.227534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9887 10:55:36.233911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9888 10:55:36.237025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9889 10:55:36.243900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9890 10:55:36.247459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9891 10:55:36.253840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9892 10:55:36.256910 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9893 10:55:36.257012 INFO: [APUAPC] vio 0
9894 10:55:36.264713 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9895 10:55:36.267788 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9896 10:55:36.270878 INFO: [APUAPC] D0_APC_0: 0x400510
9897 10:55:36.274804 INFO: [APUAPC] D0_APC_1: 0x0
9898 10:55:36.278067 INFO: [APUAPC] D0_APC_2: 0x1540
9899 10:55:36.281386 INFO: [APUAPC] D0_APC_3: 0x0
9900 10:55:36.284684 INFO: [APUAPC] D1_APC_0: 0xffffffff
9901 10:55:36.287840 INFO: [APUAPC] D1_APC_1: 0xffffffff
9902 10:55:36.291529 INFO: [APUAPC] D1_APC_2: 0x3fffff
9903 10:55:36.294726 INFO: [APUAPC] D1_APC_3: 0x0
9904 10:55:36.297685 INFO: [APUAPC] D2_APC_0: 0xffffffff
9905 10:55:36.301445 INFO: [APUAPC] D2_APC_1: 0xffffffff
9906 10:55:36.304612 INFO: [APUAPC] D2_APC_2: 0x3fffff
9907 10:55:36.307955 INFO: [APUAPC] D2_APC_3: 0x0
9908 10:55:36.311081 INFO: [APUAPC] D3_APC_0: 0xffffffff
9909 10:55:36.314261 INFO: [APUAPC] D3_APC_1: 0xffffffff
9910 10:55:36.318181 INFO: [APUAPC] D3_APC_2: 0x3fffff
9911 10:55:36.318279 INFO: [APUAPC] D3_APC_3: 0x0
9912 10:55:36.321445 INFO: [APUAPC] D4_APC_0: 0xffffffff
9913 10:55:36.327642 INFO: [APUAPC] D4_APC_1: 0xffffffff
9914 10:55:36.331320 INFO: [APUAPC] D4_APC_2: 0x3fffff
9915 10:55:36.331439 INFO: [APUAPC] D4_APC_3: 0x0
9916 10:55:36.334532 INFO: [APUAPC] D5_APC_0: 0xffffffff
9917 10:55:36.337762 INFO: [APUAPC] D5_APC_1: 0xffffffff
9918 10:55:36.340981 INFO: [APUAPC] D5_APC_2: 0x3fffff
9919 10:55:36.344197 INFO: [APUAPC] D5_APC_3: 0x0
9920 10:55:36.347928 INFO: [APUAPC] D6_APC_0: 0xffffffff
9921 10:55:36.351046 INFO: [APUAPC] D6_APC_1: 0xffffffff
9922 10:55:36.354634 INFO: [APUAPC] D6_APC_2: 0x3fffff
9923 10:55:36.357504 INFO: [APUAPC] D6_APC_3: 0x0
9924 10:55:36.360685 INFO: [APUAPC] D7_APC_0: 0xffffffff
9925 10:55:36.364089 INFO: [APUAPC] D7_APC_1: 0xffffffff
9926 10:55:36.367653 INFO: [APUAPC] D7_APC_2: 0x3fffff
9927 10:55:36.371020 INFO: [APUAPC] D7_APC_3: 0x0
9928 10:55:36.374171 INFO: [APUAPC] D8_APC_0: 0xffffffff
9929 10:55:36.377870 INFO: [APUAPC] D8_APC_1: 0xffffffff
9930 10:55:36.381002 INFO: [APUAPC] D8_APC_2: 0x3fffff
9931 10:55:36.384201 INFO: [APUAPC] D8_APC_3: 0x0
9932 10:55:36.387508 INFO: [APUAPC] D9_APC_0: 0xffffffff
9933 10:55:36.390734 INFO: [APUAPC] D9_APC_1: 0xffffffff
9934 10:55:36.393926 INFO: [APUAPC] D9_APC_2: 0x3fffff
9935 10:55:36.397290 INFO: [APUAPC] D9_APC_3: 0x0
9936 10:55:36.400944 INFO: [APUAPC] D10_APC_0: 0xffffffff
9937 10:55:36.404400 INFO: [APUAPC] D10_APC_1: 0xffffffff
9938 10:55:36.407462 INFO: [APUAPC] D10_APC_2: 0x3fffff
9939 10:55:36.410666 INFO: [APUAPC] D10_APC_3: 0x0
9940 10:55:36.413923 INFO: [APUAPC] D11_APC_0: 0xffffffff
9941 10:55:36.417194 INFO: [APUAPC] D11_APC_1: 0xffffffff
9942 10:55:36.420423 INFO: [APUAPC] D11_APC_2: 0x3fffff
9943 10:55:36.424355 INFO: [APUAPC] D11_APC_3: 0x0
9944 10:55:36.427515 INFO: [APUAPC] D12_APC_0: 0xffffffff
9945 10:55:36.430738 INFO: [APUAPC] D12_APC_1: 0xffffffff
9946 10:55:36.434474 INFO: [APUAPC] D12_APC_2: 0x3fffff
9947 10:55:36.437717 INFO: [APUAPC] D12_APC_3: 0x0
9948 10:55:36.440923 INFO: [APUAPC] D13_APC_0: 0xffffffff
9949 10:55:36.444273 INFO: [APUAPC] D13_APC_1: 0xffffffff
9950 10:55:36.447305 INFO: [APUAPC] D13_APC_2: 0x3fffff
9951 10:55:36.450564 INFO: [APUAPC] D13_APC_3: 0x0
9952 10:55:36.454232 INFO: [APUAPC] D14_APC_0: 0xffffffff
9953 10:55:36.457347 INFO: [APUAPC] D14_APC_1: 0xffffffff
9954 10:55:36.460983 INFO: [APUAPC] D14_APC_2: 0x3fffff
9955 10:55:36.464028 INFO: [APUAPC] D14_APC_3: 0x0
9956 10:55:36.467713 INFO: [APUAPC] D15_APC_0: 0xffffffff
9957 10:55:36.470873 INFO: [APUAPC] D15_APC_1: 0xffffffff
9958 10:55:36.474342 INFO: [APUAPC] D15_APC_2: 0x3fffff
9959 10:55:36.477193 INFO: [APUAPC] D15_APC_3: 0x0
9960 10:55:36.481055 INFO: [APUAPC] APC_CON: 0x4
9961 10:55:36.484229 INFO: [NOCDAPC] D0_APC_0: 0x0
9962 10:55:36.487450 INFO: [NOCDAPC] D0_APC_1: 0x0
9963 10:55:36.487578 INFO: [NOCDAPC] D1_APC_0: 0x0
9964 10:55:36.490732 INFO: [NOCDAPC] D1_APC_1: 0xfff
9965 10:55:36.493977 INFO: [NOCDAPC] D2_APC_0: 0x0
9966 10:55:36.497180 INFO: [NOCDAPC] D2_APC_1: 0xfff
9967 10:55:36.500442 INFO: [NOCDAPC] D3_APC_0: 0x0
9968 10:55:36.504124 INFO: [NOCDAPC] D3_APC_1: 0xfff
9969 10:55:36.507370 INFO: [NOCDAPC] D4_APC_0: 0x0
9970 10:55:36.510470 INFO: [NOCDAPC] D4_APC_1: 0xfff
9971 10:55:36.513950 INFO: [NOCDAPC] D5_APC_0: 0x0
9972 10:55:36.517590 INFO: [NOCDAPC] D5_APC_1: 0xfff
9973 10:55:36.520894 INFO: [NOCDAPC] D6_APC_0: 0x0
9974 10:55:36.521034 INFO: [NOCDAPC] D6_APC_1: 0xfff
9975 10:55:36.524103 INFO: [NOCDAPC] D7_APC_0: 0x0
9976 10:55:36.527276 INFO: [NOCDAPC] D7_APC_1: 0xfff
9977 10:55:36.530394 INFO: [NOCDAPC] D8_APC_0: 0x0
9978 10:55:36.533688 INFO: [NOCDAPC] D8_APC_1: 0xfff
9979 10:55:36.537467 INFO: [NOCDAPC] D9_APC_0: 0x0
9980 10:55:36.540507 INFO: [NOCDAPC] D9_APC_1: 0xfff
9981 10:55:36.543722 INFO: [NOCDAPC] D10_APC_0: 0x0
9982 10:55:36.547531 INFO: [NOCDAPC] D10_APC_1: 0xfff
9983 10:55:36.550826 INFO: [NOCDAPC] D11_APC_0: 0x0
9984 10:55:36.554052 INFO: [NOCDAPC] D11_APC_1: 0xfff
9985 10:55:36.557212 INFO: [NOCDAPC] D12_APC_0: 0x0
9986 10:55:36.560271 INFO: [NOCDAPC] D12_APC_1: 0xfff
9987 10:55:36.560384 INFO: [NOCDAPC] D13_APC_0: 0x0
9988 10:55:36.563944 INFO: [NOCDAPC] D13_APC_1: 0xfff
9989 10:55:36.567044 INFO: [NOCDAPC] D14_APC_0: 0x0
9990 10:55:36.570729 INFO: [NOCDAPC] D14_APC_1: 0xfff
9991 10:55:36.573727 INFO: [NOCDAPC] D15_APC_0: 0x0
9992 10:55:36.576845 INFO: [NOCDAPC] D15_APC_1: 0xfff
9993 10:55:36.580455 INFO: [NOCDAPC] APC_CON: 0x4
9994 10:55:36.584245 INFO: [APUAPC] set_apusys_apc done
9995 10:55:36.587085 INFO: [DEVAPC] devapc_init done
9996 10:55:36.590312 INFO: GICv3 without legacy support detected.
9997 10:55:36.594039 INFO: ARM GICv3 driver initialized in EL3
9998 10:55:36.600631 INFO: Maximum SPI INTID supported: 639
9999 10:55:36.603887 INFO: BL31: Initializing runtime services
10000 10:55:36.606915 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10001 10:55:36.610092 INFO: SPM: enable CPC mode
10002 10:55:36.617017 INFO: mcdi ready for mcusys-off-idle and system suspend
10003 10:55:36.620719 INFO: BL31: Preparing for EL3 exit to normal world
10004 10:55:36.623613 INFO: Entry point address = 0x80000000
10005 10:55:36.626775 INFO: SPSR = 0x8
10006 10:55:36.632495
10007 10:55:36.632635
10008 10:55:36.632743
10009 10:55:36.635692 Starting depthcharge on Spherion...
10010 10:55:36.635815
10011 10:55:36.635910 Wipe memory regions:
10012 10:55:36.636009
10013 10:55:36.636830 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10014 10:55:36.636984 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10015 10:55:36.637105 Setting prompt string to ['asurada:']
10016 10:55:36.637231 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10017 10:55:36.639462 [0x00000040000000, 0x00000054600000)
10018 10:55:36.761836
10019 10:55:36.762032 [0x00000054660000, 0x00000080000000)
10020 10:55:37.021894
10021 10:55:37.022094 [0x000000821a7280, 0x000000ffe64000)
10022 10:55:37.766660
10023 10:55:37.766855 [0x00000100000000, 0x00000240000000)
10024 10:55:39.656852
10025 10:55:39.660056 Initializing XHCI USB controller at 0x11200000.
10026 10:55:40.698445
10027 10:55:40.701301 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10028 10:55:40.701426
10029 10:55:40.701491
10030 10:55:40.701552
10031 10:55:40.701831 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10033 10:55:40.802191 asurada: tftpboot 192.168.201.1 10590987/tftp-deploy-k5gx8mcg/kernel/image.itb 10590987/tftp-deploy-k5gx8mcg/kernel/cmdline
10034 10:55:40.802373 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 10:55:40.802497 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10036 10:55:40.806338 tftpboot 192.168.201.1 10590987/tftp-deploy-k5gx8mcg/kernel/image.itp-deploy-k5gx8mcg/kernel/cmdline
10037 10:55:40.806429
10038 10:55:40.806495 Waiting for link
10039 10:55:40.967047
10040 10:55:40.967205 R8152: Initializing
10041 10:55:40.967273
10042 10:55:40.970277 Version 9 (ocp_data = 6010)
10043 10:55:40.970366
10044 10:55:40.973859 R8152: Done initializing
10045 10:55:40.973961
10046 10:55:40.974028 Adding net device
10047 10:55:42.919909
10048 10:55:42.920057 done.
10049 10:55:42.920144
10050 10:55:42.920222 MAC: 00:e0:4c:78:7a:aa
10051 10:55:42.920282
10052 10:55:42.922616 Sending DHCP discover... done.
10053 10:55:42.922687
10054 10:55:42.926398 Waiting for reply... done.
10055 10:55:42.926482
10056 10:55:42.929347 Sending DHCP request... done.
10057 10:55:42.929431
10058 10:55:42.929496 Waiting for reply... done.
10059 10:55:42.929563
10060 10:55:42.933032 My ip is 192.168.201.12
10061 10:55:42.933139
10062 10:55:42.936017 The DHCP server ip is 192.168.201.1
10063 10:55:42.936190
10064 10:55:42.939318 TFTP server IP predefined by user: 192.168.201.1
10065 10:55:42.939425
10066 10:55:42.946080 Bootfile predefined by user: 10590987/tftp-deploy-k5gx8mcg/kernel/image.itb
10067 10:55:42.946184
10068 10:55:42.949182 Sending tftp read request... done.
10069 10:55:42.949266
10070 10:55:42.952425 Waiting for the transfer...
10071 10:55:42.952511
10072 10:55:43.207767 00000000 ################################################################
10073 10:55:43.207904
10074 10:55:43.458312 00080000 ################################################################
10075 10:55:43.458491
10076 10:55:43.701886 00100000 ################################################################
10077 10:55:43.702066
10078 10:55:43.948192 00180000 ################################################################
10079 10:55:43.948347
10080 10:55:44.191280 00200000 ################################################################
10081 10:55:44.191446
10082 10:55:44.432313 00280000 ################################################################
10083 10:55:44.432461
10084 10:55:44.677201 00300000 ################################################################
10085 10:55:44.677389
10086 10:55:44.920244 00380000 ################################################################
10087 10:55:44.920435
10088 10:55:45.167336 00400000 ################################################################
10089 10:55:45.167512
10090 10:55:45.411230 00480000 ################################################################
10091 10:55:45.411409
10092 10:55:45.652830 00500000 ################################################################
10093 10:55:45.653006
10094 10:55:45.895111 00580000 ################################################################
10095 10:55:45.895260
10096 10:55:46.140916 00600000 ################################################################
10097 10:55:46.141096
10098 10:55:46.397121 00680000 ################################################################
10099 10:55:46.397290
10100 10:55:46.632303 00700000 ################################################################
10101 10:55:46.632479
10102 10:55:46.873516 00780000 ################################################################
10103 10:55:46.873742
10104 10:55:47.110289 00800000 ################################################################
10105 10:55:47.110461
10106 10:55:47.344613 00880000 ################################################################
10107 10:55:47.344767
10108 10:55:47.580188 00900000 ################################################################
10109 10:55:47.580360
10110 10:55:47.817819 00980000 ################################################################
10111 10:55:47.818008
10112 10:55:48.053031 00a00000 ################################################################
10113 10:55:48.053281
10114 10:55:48.287295 00a80000 ################################################################
10115 10:55:48.287475
10116 10:55:48.520535 00b00000 ################################################################
10117 10:55:48.520678
10118 10:55:48.755973 00b80000 ################################################################
10119 10:55:48.756136
10120 10:55:48.991028 00c00000 ################################################################
10121 10:55:48.991182
10122 10:55:49.223991 00c80000 ################################################################
10123 10:55:49.224141
10124 10:55:49.454979 00d00000 ################################################################
10125 10:55:49.455132
10126 10:55:49.689144 00d80000 ################################################################
10127 10:55:49.689288
10128 10:55:49.926883 00e00000 ################################################################
10129 10:55:49.927047
10130 10:55:50.161902 00e80000 ################################################################
10131 10:55:50.162053
10132 10:55:50.403179 00f00000 ################################################################
10133 10:55:50.403369
10134 10:55:50.645804 00f80000 ################################################################
10135 10:55:50.645941
10136 10:55:50.887845 01000000 ################################################################
10137 10:55:50.887984
10138 10:55:51.132237 01080000 ################################################################
10139 10:55:51.132378
10140 10:55:51.378567 01100000 ################################################################
10141 10:55:51.378715
10142 10:55:51.623840 01180000 ################################################################
10143 10:55:51.624018
10144 10:55:51.869648 01200000 ################################################################
10145 10:55:51.869795
10146 10:55:52.112140 01280000 ################################################################
10147 10:55:52.112288
10148 10:55:52.353603 01300000 ################################################################
10149 10:55:52.353750
10150 10:55:52.597668 01380000 ################################################################
10151 10:55:52.597829
10152 10:55:52.842014 01400000 ################################################################
10153 10:55:52.842182
10154 10:55:53.083081 01480000 ################################################################
10155 10:55:53.083240
10156 10:55:53.326626 01500000 ################################################################
10157 10:55:53.326790
10158 10:55:53.573102 01580000 ################################################################
10159 10:55:53.573245
10160 10:55:53.822284 01600000 ################################################################
10161 10:55:53.822413
10162 10:55:54.072793 01680000 ################################################################
10163 10:55:54.072939
10164 10:55:54.324726 01700000 ################################################################
10165 10:55:54.324904
10166 10:55:54.579089 01780000 ################################################################
10167 10:55:54.579230
10168 10:55:54.825853 01800000 ################################################################
10169 10:55:54.825989
10170 10:55:55.073345 01880000 ################################################################
10171 10:55:55.073513
10172 10:55:55.327266 01900000 ################################################################
10173 10:55:55.327409
10174 10:55:55.581362 01980000 ################################################################
10175 10:55:55.581527
10176 10:55:55.825502 01a00000 ################################################################
10177 10:55:55.825638
10178 10:55:56.074676 01a80000 ################################################################
10179 10:55:56.074830
10180 10:55:56.330825 01b00000 ################################################################
10181 10:55:56.330985
10182 10:55:56.583207 01b80000 ################################################################
10183 10:55:56.583357
10184 10:55:56.829197 01c00000 ################################################################
10185 10:55:56.829327
10186 10:55:57.078066 01c80000 ################################################################
10187 10:55:57.078207
10188 10:55:57.330340 01d00000 ################################################################
10189 10:55:57.330505
10190 10:55:57.576095 01d80000 ################################################################
10191 10:55:57.576250
10192 10:55:57.826334 01e00000 ################################################################
10193 10:55:57.826476
10194 10:55:58.083854 01e80000 ################################################################
10195 10:55:58.083990
10196 10:55:58.334715 01f00000 ################################################################
10197 10:55:58.334881
10198 10:55:58.583345 01f80000 ################################################################
10199 10:55:58.583487
10200 10:55:58.841537 02000000 ################################################################
10201 10:55:58.841695
10202 10:55:59.100304 02080000 ################################################################
10203 10:55:59.100450
10204 10:55:59.350229 02100000 ################################################################
10205 10:55:59.350371
10206 10:55:59.603833 02180000 ################################################################
10207 10:55:59.603973
10208 10:55:59.857568 02200000 ################################################################
10209 10:55:59.857709
10210 10:56:00.110164 02280000 ################################################################
10211 10:56:00.110336
10212 10:56:00.366588 02300000 ################################################################
10213 10:56:00.366769
10214 10:56:00.624719 02380000 ################################################################
10215 10:56:00.624888
10216 10:56:00.885851 02400000 ################################################################
10217 10:56:00.886016
10218 10:56:01.138319 02480000 ################################################################
10219 10:56:01.138458
10220 10:56:01.400026 02500000 ################################################################
10221 10:56:01.400199
10222 10:56:01.649215 02580000 ################################################################
10223 10:56:01.649389
10224 10:56:01.899268 02600000 ################################################################
10225 10:56:01.899473
10226 10:56:02.151450 02680000 ################################################################
10227 10:56:02.151615
10228 10:56:02.405663 02700000 ################################################################
10229 10:56:02.405823
10230 10:56:02.656758 02780000 ################################################################
10231 10:56:02.656892
10232 10:56:02.908708 02800000 ################################################################
10233 10:56:02.908846
10234 10:56:03.171791 02880000 ################################################################
10235 10:56:03.171940
10236 10:56:03.431885 02900000 ################################################################
10237 10:56:03.432032
10238 10:56:03.681694 02980000 ################################################################
10239 10:56:03.681875
10240 10:56:03.952289 02a00000 ################################################################
10241 10:56:03.952429
10242 10:56:04.211353 02a80000 ################################################################
10243 10:56:04.211497
10244 10:56:04.460419 02b00000 ################################################################
10245 10:56:04.460553
10246 10:56:04.721274 02b80000 ################################################################
10247 10:56:04.721405
10248 10:56:05.005079 02c00000 ################################################################
10249 10:56:05.005208
10250 10:56:05.285413 02c80000 ################################################################
10251 10:56:05.285542
10252 10:56:05.572074 02d00000 ################################################################
10253 10:56:05.572215
10254 10:56:05.832681 02d80000 ################################################################
10255 10:56:05.832820
10256 10:56:06.088339 02e00000 ################################################################
10257 10:56:06.088477
10258 10:56:06.348689 02e80000 ################################################################
10259 10:56:06.348832
10260 10:56:06.615887 02f00000 ################################################################
10261 10:56:06.616027
10262 10:56:06.832722 02f80000 ####################################################### done.
10263 10:56:06.832879
10264 10:56:06.836163 The bootfile was 50251994 bytes long.
10265 10:56:06.836240
10266 10:56:06.838745 Sending tftp read request... done.
10267 10:56:06.838821
10268 10:56:06.842183 Waiting for the transfer...
10269 10:56:06.842269
10270 10:56:06.842338 00000000 # done.
10271 10:56:06.842404
10272 10:56:06.852562 Command line loaded dynamically from TFTP file: 10590987/tftp-deploy-k5gx8mcg/kernel/cmdline
10273 10:56:06.852673
10274 10:56:06.862529 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10275 10:56:06.862664
10276 10:56:06.862785 Loading FIT.
10277 10:56:06.862885
10278 10:56:06.865533 Image ramdisk-1 has 40121099 bytes.
10279 10:56:06.865666
10280 10:56:06.869025 Image fdt-1 has 46924 bytes.
10281 10:56:06.869192
10282 10:56:06.872190 Image kernel-1 has 10081937 bytes.
10283 10:56:06.872340
10284 10:56:06.882216 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10285 10:56:06.882417
10286 10:56:06.899224 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10287 10:56:06.899795
10288 10:56:06.905940 Choosing best match conf-1 for compat google,spherion-rev2.
10289 10:56:06.906359
10290 10:56:06.913527 Connected to device vid:did:rid of 1ae0:0028:00
10291 10:56:06.921314
10292 10:56:06.925034 tpm_get_response: command 0x17b, return code 0x0
10293 10:56:06.925502
10294 10:56:06.928200 ec_init: CrosEC protocol v3 supported (256, 248)
10295 10:56:06.932105
10296 10:56:06.935320 tpm_cleanup: add release locality here.
10297 10:56:06.935768
10298 10:56:06.936106 Shutting down all USB controllers.
10299 10:56:06.938758
10300 10:56:06.939162 Removing current net device
10301 10:56:06.939594
10302 10:56:06.945529 Exiting depthcharge with code 4 at timestamp: 59586663
10303 10:56:06.946045
10304 10:56:06.948705 LZMA decompressing kernel-1 to 0x821a6718
10305 10:56:06.949114
10306 10:56:06.952123 LZMA decompressing kernel-1 to 0x40000000
10307 10:56:08.218145
10308 10:56:08.218687 jumping to kernel
10309 10:56:08.220238 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10310 10:56:08.220751 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
10311 10:56:08.221148 Setting prompt string to ['Linux version [0-9]']
10312 10:56:08.221514 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10313 10:56:08.221889 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10314 10:56:08.300140
10315 10:56:08.303248 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10316 10:56:08.306958 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10317 10:56:08.307459 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10318 10:56:08.307880 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 10:56:08.308242 Using line separator: #'\n'#
10320 10:56:08.308547 No login prompt set.
10321 10:56:08.308851 Parsing kernel messages
10322 10:56:08.309125 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 10:56:08.309654 [login-action] Waiting for messages, (timeout 00:03:54)
10324 10:56:08.325942 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1608981-arm64-gcc-10-defconfig-arm64-chromebook-p5v4z) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023
10325 10:56:08.329095 [ 0.000000] random: crng init done
10326 10:56:08.335982 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 10:56:08.339123 [ 0.000000] efi: UEFI not found.
10328 10:56:08.345505 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 10:56:08.352680 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 10:56:08.362446 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 10:56:08.372664 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 10:56:08.379141 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 10:56:08.385826 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 10:56:08.391689 [ 0.000000] NUMA: No NUMA configuration found
10335 10:56:08.398404 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 10:56:08.401579 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10337 10:56:08.405329 [ 0.000000] Zone ranges:
10338 10:56:08.411509 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 10:56:08.414918 [ 0.000000] DMA32 empty
10340 10:56:08.422157 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 10:56:08.424881 [ 0.000000] Movable zone start for each node
10342 10:56:08.427984 [ 0.000000] Early memory node ranges
10343 10:56:08.434639 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 10:56:08.441615 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 10:56:08.448532 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 10:56:08.454899 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 10:56:08.461281 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 10:56:08.468078 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 10:56:08.524307 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 10:56:08.530698 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 10:56:08.537176 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 10:56:08.540687 [ 0.000000] psci: probing for conduit method from DT.
10353 10:56:08.547434 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 10:56:08.550520 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 10:56:08.557516 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 10:56:08.560867 [ 0.000000] psci: SMC Calling Convention v1.2
10357 10:56:08.567248 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 10:56:08.570281 [ 0.000000] Detected VIPT I-cache on CPU0
10359 10:56:08.576940 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 10:56:08.583768 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 10:56:08.590485 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 10:56:08.596720 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 10:56:08.603844 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 10:56:08.610502 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 10:56:08.616773 [ 0.000000] alternatives: applying boot alternatives
10366 10:56:08.620592 [ 0.000000] Fallback order for Node 0: 0
10367 10:56:08.627078 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 10:56:08.630339 [ 0.000000] Policy zone: Normal
10369 10:56:08.643737 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10370 10:56:08.653535 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 10:56:08.666097 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 10:56:08.675977 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 10:56:08.683049 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 10:56:08.686117 <6>[ 0.000000] software IO TLB: area num 8.
10375 10:56:08.742682 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 10:56:08.892313 <6>[ 0.000000] Memory: 7933760K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419008K reserved, 32768K cma-reserved)
10377 10:56:08.898392 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 10:56:08.904963 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 10:56:08.908301 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 10:56:08.915062 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 10:56:08.921564 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 10:56:08.925085 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 10:56:08.934870 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 10:56:08.941807 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 10:56:08.948433 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 10:56:08.955197 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 10:56:08.958234 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 10:56:08.961827 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 10:56:08.967838 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 10:56:08.971732 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 10:56:08.977875 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 10:56:08.991035 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 10:56:09.004232 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 10:56:09.010867 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 10:56:09.018903 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 10:56:09.032287 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 10:56:09.038244 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 10:56:09.044790 <6>[ 0.009173] Console: colour dummy device 80x25
10399 10:56:09.054929 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 10:56:09.061210 <6>[ 0.024407] pid_max: default: 32768 minimum: 301
10401 10:56:09.064792 <6>[ 0.029280] LSM: Security Framework initializing
10402 10:56:09.071524 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 10:56:09.081610 <6>[ 0.042035] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 10:56:09.088481 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10405 10:56:09.094796 <6>[ 0.058921] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 10:56:09.101853 <6>[ 0.065298] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 10:56:09.107860 <6>[ 0.071706] rcu: Hierarchical SRCU implementation.
10408 10:56:09.111210 <6>[ 0.076750] rcu: Max phase no-delay instances is 1000.
10409 10:56:09.119383 <6>[ 0.083800] EFI services will not be available.
10410 10:56:09.122600 <6>[ 0.088763] smp: Bringing up secondary CPUs ...
10411 10:56:09.131716 <6>[ 0.093819] Detected VIPT I-cache on CPU1
10412 10:56:09.138659 <6>[ 0.093890] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10413 10:56:09.145098 <6>[ 0.093920] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10414 10:56:09.148349 <6>[ 0.094263] Detected VIPT I-cache on CPU2
10415 10:56:09.155587 <6>[ 0.094314] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10416 10:56:09.164974 <6>[ 0.094331] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10417 10:56:09.168194 <6>[ 0.094589] Detected VIPT I-cache on CPU3
10418 10:56:09.174933 <6>[ 0.094636] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10419 10:56:09.181956 <6>[ 0.094650] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10420 10:56:09.185194 <6>[ 0.094957] CPU features: detected: Spectre-v4
10421 10:56:09.191625 <6>[ 0.094963] CPU features: detected: Spectre-BHB
10422 10:56:09.194927 <6>[ 0.094969] Detected PIPT I-cache on CPU4
10423 10:56:09.201452 <6>[ 0.095026] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10424 10:56:09.207885 <6>[ 0.095042] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10425 10:56:09.214692 <6>[ 0.095335] Detected PIPT I-cache on CPU5
10426 10:56:09.221396 <6>[ 0.095398] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10427 10:56:09.228095 <6>[ 0.095414] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10428 10:56:09.231387 <6>[ 0.095697] Detected PIPT I-cache on CPU6
10429 10:56:09.237704 <6>[ 0.095762] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10430 10:56:09.243982 <6>[ 0.095778] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10431 10:56:09.250803 <6>[ 0.096077] Detected PIPT I-cache on CPU7
10432 10:56:09.257495 <6>[ 0.096144] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10433 10:56:09.263983 <6>[ 0.096160] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10434 10:56:09.267268 <6>[ 0.096206] smp: Brought up 1 node, 8 CPUs
10435 10:56:09.274261 <6>[ 0.237600] SMP: Total of 8 processors activated.
10436 10:56:09.278014 <6>[ 0.242521] CPU features: detected: 32-bit EL0 Support
10437 10:56:09.287119 <6>[ 0.247883] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10438 10:56:09.293971 <6>[ 0.256683] CPU features: detected: Common not Private translations
10439 10:56:09.300606 <6>[ 0.263198] CPU features: detected: CRC32 instructions
10440 10:56:09.304332 <6>[ 0.268582] CPU features: detected: RCpc load-acquire (LDAPR)
10441 10:56:09.310320 <6>[ 0.274579] CPU features: detected: LSE atomic instructions
10442 10:56:09.317603 <6>[ 0.280396] CPU features: detected: Privileged Access Never
10443 10:56:09.324137 <6>[ 0.286176] CPU features: detected: RAS Extension Support
10444 10:56:09.330740 <6>[ 0.291819] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10445 10:56:09.334180 <6>[ 0.299039] CPU: All CPU(s) started at EL2
10446 10:56:09.340636 <6>[ 0.303382] alternatives: applying system-wide alternatives
10447 10:56:09.349648 <6>[ 0.314092] devtmpfs: initialized
10448 10:56:09.362051 <6>[ 0.322838] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10449 10:56:09.372420 <6>[ 0.332803] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10450 10:56:09.375554 <6>[ 0.340470] pinctrl core: initialized pinctrl subsystem
10451 10:56:09.383089 <6>[ 0.347126] DMI not present or invalid.
10452 10:56:09.389627 <6>[ 0.351533] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10453 10:56:09.396350 <6>[ 0.358411] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10454 10:56:09.406315 <6>[ 0.365987] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10455 10:56:09.412793 <6>[ 0.374199] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10456 10:56:09.419317 <6>[ 0.382438] audit: initializing netlink subsys (disabled)
10457 10:56:09.426248 <5>[ 0.388133] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10458 10:56:09.432958 <6>[ 0.388838] thermal_sys: Registered thermal governor 'step_wise'
10459 10:56:09.439419 <6>[ 0.396097] thermal_sys: Registered thermal governor 'power_allocator'
10460 10:56:09.443002 <6>[ 0.402351] cpuidle: using governor menu
10461 10:56:09.449581 <6>[ 0.413305] NET: Registered PF_QIPCRTR protocol family
10462 10:56:09.456170 <6>[ 0.418782] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10463 10:56:09.463109 <6>[ 0.425880] ASID allocator initialised with 32768 entries
10464 10:56:09.466441 <6>[ 0.432439] Serial: AMBA PL011 UART driver
10465 10:56:09.476795 <4>[ 0.441079] Trying to register duplicate clock ID: 134
10466 10:56:09.530816 <6>[ 0.498134] KASLR enabled
10467 10:56:09.545311 <6>[ 0.505856] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10468 10:56:09.551947 <6>[ 0.512867] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10469 10:56:09.558307 <6>[ 0.519360] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10470 10:56:09.564816 <6>[ 0.526364] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10471 10:56:09.571688 <6>[ 0.532851] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10472 10:56:09.578275 <6>[ 0.539855] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10473 10:56:09.584623 <6>[ 0.546340] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10474 10:56:09.591170 <6>[ 0.553343] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10475 10:56:09.594455 <6>[ 0.560856] ACPI: Interpreter disabled.
10476 10:56:09.603079 <6>[ 0.567236] iommu: Default domain type: Translated
10477 10:56:09.609726 <6>[ 0.572346] iommu: DMA domain TLB invalidation policy: strict mode
10478 10:56:09.613085 <5>[ 0.578999] SCSI subsystem initialized
10479 10:56:09.619482 <6>[ 0.583162] usbcore: registered new interface driver usbfs
10480 10:56:09.626008 <6>[ 0.588895] usbcore: registered new interface driver hub
10481 10:56:09.629325 <6>[ 0.594445] usbcore: registered new device driver usb
10482 10:56:09.636393 <6>[ 0.600524] pps_core: LinuxPPS API ver. 1 registered
10483 10:56:09.646479 <6>[ 0.605717] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10484 10:56:09.649962 <6>[ 0.615057] PTP clock support registered
10485 10:56:09.652602 <6>[ 0.619296] EDAC MC: Ver: 3.0.0
10486 10:56:09.660456 <6>[ 0.624423] FPGA manager framework
10487 10:56:09.663823 <6>[ 0.628100] Advanced Linux Sound Architecture Driver Initialized.
10488 10:56:09.667132 <6>[ 0.634873] vgaarb: loaded
10489 10:56:09.673812 <6>[ 0.638041] clocksource: Switched to clocksource arch_sys_counter
10490 10:56:09.680766 <5>[ 0.644478] VFS: Disk quotas dquot_6.6.0
10491 10:56:09.686903 <6>[ 0.648664] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10492 10:56:09.690661 <6>[ 0.655851] pnp: PnP ACPI: disabled
10493 10:56:09.698354 <6>[ 0.662548] NET: Registered PF_INET protocol family
10494 10:56:09.708125 <6>[ 0.668144] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10495 10:56:09.719608 <6>[ 0.680435] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10496 10:56:09.729333 <6>[ 0.689248] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10497 10:56:09.735842 <6>[ 0.697217] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10498 10:56:09.742761 <6>[ 0.705918] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10499 10:56:09.754971 <6>[ 0.715658] TCP: Hash tables configured (established 65536 bind 65536)
10500 10:56:09.761875 <6>[ 0.722513] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 10:56:09.768404 <6>[ 0.729709] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 10:56:09.775126 <6>[ 0.737408] NET: Registered PF_UNIX/PF_LOCAL protocol family
10503 10:56:09.781560 <6>[ 0.743586] RPC: Registered named UNIX socket transport module.
10504 10:56:09.784945 <6>[ 0.749741] RPC: Registered udp transport module.
10505 10:56:09.791584 <6>[ 0.754674] RPC: Registered tcp transport module.
10506 10:56:09.797788 <6>[ 0.759606] RPC: Registered tcp NFSv4.1 backchannel transport module.
10507 10:56:09.801109 <6>[ 0.766278] PCI: CLS 0 bytes, default 64
10508 10:56:09.804167 <6>[ 0.770611] Unpacking initramfs...
10509 10:56:09.814561 <6>[ 0.774700] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10510 10:56:09.820997 <6>[ 0.783346] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10511 10:56:09.827623 <6>[ 0.792185] kvm [1]: IPA Size Limit: 40 bits
10512 10:56:09.831591 <6>[ 0.796712] kvm [1]: GICv3: no GICV resource entry
10513 10:56:09.838161 <6>[ 0.801735] kvm [1]: disabling GICv2 emulation
10514 10:56:09.844300 <6>[ 0.806426] kvm [1]: GIC system register CPU interface enabled
10515 10:56:09.848129 <6>[ 0.812586] kvm [1]: vgic interrupt IRQ18
10516 10:56:09.854393 <6>[ 0.816935] kvm [1]: VHE mode initialized successfully
10517 10:56:09.858135 <5>[ 0.823279] Initialise system trusted keyrings
10518 10:56:09.864290 <6>[ 0.828079] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10519 10:56:09.873788 <6>[ 0.838019] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10520 10:56:09.880389 <5>[ 0.844405] NFS: Registering the id_resolver key type
10521 10:56:09.883752 <5>[ 0.849708] Key type id_resolver registered
10522 10:56:09.890495 <5>[ 0.854122] Key type id_legacy registered
10523 10:56:09.897114 <6>[ 0.858397] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10524 10:56:09.903453 <6>[ 0.865320] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10525 10:56:09.910401 <6>[ 0.873038] 9p: Installing v9fs 9p2000 file system support
10526 10:56:09.947020 <5>[ 0.911234] Key type asymmetric registered
10527 10:56:09.950353 <5>[ 0.915565] Asymmetric key parser 'x509' registered
10528 10:56:09.960214 <6>[ 0.920707] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10529 10:56:09.964075 <6>[ 0.928321] io scheduler mq-deadline registered
10530 10:56:09.967028 <6>[ 0.933080] io scheduler kyber registered
10531 10:56:09.985875 <6>[ 0.949915] EINJ: ACPI disabled.
10532 10:56:10.017417 <4>[ 0.975210] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 10:56:10.028026 <4>[ 0.985832] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 10:56:10.042969 <6>[ 1.006529] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10535 10:56:10.050004 <6>[ 1.014584] printk: console [ttyS0] disabled
10536 10:56:10.078472 <6>[ 1.039229] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10537 10:56:10.084943 <6>[ 1.048708] printk: console [ttyS0] enabled
10538 10:56:10.088098 <6>[ 1.048708] printk: console [ttyS0] enabled
10539 10:56:10.094801 <6>[ 1.057601] printk: bootconsole [mtk8250] disabled
10540 10:56:10.098409 <6>[ 1.057601] printk: bootconsole [mtk8250] disabled
10541 10:56:10.104922 <6>[ 1.068855] SuperH (H)SCI(F) driver initialized
10542 10:56:10.108295 <6>[ 1.074148] msm_serial: driver initialized
10543 10:56:10.122325 <6>[ 1.083056] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10544 10:56:10.131867 <6>[ 1.091604] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10545 10:56:10.138918 <6>[ 1.100145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10546 10:56:10.148878 <6>[ 1.108772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10547 10:56:10.155455 <6>[ 1.117477] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10548 10:56:10.165691 <6>[ 1.126195] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10549 10:56:10.175307 <6>[ 1.134737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10550 10:56:10.181889 <6>[ 1.143541] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10551 10:56:10.191669 <6>[ 1.152087] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10552 10:56:10.203533 <6>[ 1.167543] loop: module loaded
10553 10:56:10.210223 <6>[ 1.173493] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10554 10:56:10.232406 <4>[ 1.196842] mtk-pmic-keys: Failed to locate of_node [id: -1]
10555 10:56:10.239247 <6>[ 1.203524] megasas: 07.719.03.00-rc1
10556 10:56:10.248718 <6>[ 1.212983] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10557 10:56:10.257428 <6>[ 1.221426] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10558 10:56:10.274071 <6>[ 1.238143] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10559 10:56:10.330730 <6>[ 1.288359] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10560 10:56:11.467563 <6>[ 2.432543] Freeing initrd memory: 39176K
10561 10:56:11.478675 <6>[ 2.443023] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10562 10:56:11.490000 <6>[ 2.454147] tun: Universal TUN/TAP device driver, 1.6
10563 10:56:11.493459 <6>[ 2.460205] thunder_xcv, ver 1.0
10564 10:56:11.496710 <6>[ 2.463712] thunder_bgx, ver 1.0
10565 10:56:11.499889 <6>[ 2.467206] nicpf, ver 1.0
10566 10:56:11.510123 <6>[ 2.471243] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10567 10:56:11.513226 <6>[ 2.478719] hns3: Copyright (c) 2017 Huawei Corporation.
10568 10:56:11.516678 <6>[ 2.484307] hclge is initializing
10569 10:56:11.523442 <6>[ 2.487888] e1000: Intel(R) PRO/1000 Network Driver
10570 10:56:11.530195 <6>[ 2.493016] e1000: Copyright (c) 1999-2006 Intel Corporation.
10571 10:56:11.533287 <6>[ 2.499032] e1000e: Intel(R) PRO/1000 Network Driver
10572 10:56:11.540313 <6>[ 2.504248] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10573 10:56:11.547048 <6>[ 2.510433] igb: Intel(R) Gigabit Ethernet Network Driver
10574 10:56:11.553388 <6>[ 2.516083] igb: Copyright (c) 2007-2014 Intel Corporation.
10575 10:56:11.559992 <6>[ 2.521920] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10576 10:56:11.566846 <6>[ 2.528437] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10577 10:56:11.570038 <6>[ 2.534902] sky2: driver version 1.30
10578 10:56:11.576845 <6>[ 2.539881] VFIO - User Level meta-driver version: 0.3
10579 10:56:11.583468 <6>[ 2.548033] usbcore: registered new interface driver usb-storage
10580 10:56:11.590187 <6>[ 2.554476] usbcore: registered new device driver onboard-usb-hub
10581 10:56:11.599167 <6>[ 2.563529] mt6397-rtc mt6359-rtc: registered as rtc0
10582 10:56:11.608830 <6>[ 2.568987] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T10:55:59 UTC (1685962559)
10583 10:56:11.612100 <6>[ 2.578580] i2c_dev: i2c /dev entries driver
10584 10:56:11.629089 <6>[ 2.590262] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10585 10:56:11.636161 <6>[ 2.600495] sdhci: Secure Digital Host Controller Interface driver
10586 10:56:11.642918 <6>[ 2.606933] sdhci: Copyright(c) Pierre Ossman
10587 10:56:11.649055 <6>[ 2.612330] Synopsys Designware Multimedia Card Interface Driver
10588 10:56:11.652633 <6>[ 2.618903] mmc0: CQHCI version 5.10
10589 10:56:11.659085 <6>[ 2.619478] sdhci-pltfm: SDHCI platform and OF driver helper
10590 10:56:11.666742 <6>[ 2.631055] ledtrig-cpu: registered to indicate activity on CPUs
10591 10:56:11.677318 <6>[ 2.638545] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10592 10:56:11.680795 <6>[ 2.645935] usbcore: registered new interface driver usbhid
10593 10:56:11.687590 <6>[ 2.651765] usbhid: USB HID core driver
10594 10:56:11.694244 <6>[ 2.656021] spi_master spi0: will run message pump with realtime priority
10595 10:56:11.738758 <6>[ 2.696537] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10596 10:56:11.757226 <6>[ 2.711444] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10597 10:56:11.760613 <6>[ 2.725037] mmc0: Command Queue Engine enabled
10598 10:56:11.767684 <6>[ 2.726305] cros-ec-spi spi0.0: Chrome EC device registered
10599 10:56:11.774125 <6>[ 2.729779] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10600 10:56:11.777377 <6>[ 2.742822] mmcblk0: mmc0:0001 DA4128 116 GiB
10601 10:56:11.788104 <6>[ 2.752583] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10602 10:56:11.798274 <6>[ 2.752707] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10603 10:56:11.804910 <6>[ 2.760014] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 10:56:11.807733 <6>[ 2.769897] NET: Registered PF_PACKET protocol family
10605 10:56:11.814841 <6>[ 2.773725] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 10:56:11.818199 <6>[ 2.778482] 9pnet: Installing 9P2000 support
10607 10:56:11.824605 <6>[ 2.784235] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10608 10:56:11.831196 <5>[ 2.788180] Key type dns_resolver registered
10609 10:56:11.834403 <6>[ 2.799701] registered taskstats version 1
10610 10:56:11.840759 <5>[ 2.804078] Loading compiled-in X.509 certificates
10611 10:56:11.876244 <4>[ 2.833854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 10:56:11.885768 <4>[ 2.844547] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 10:56:11.896466 <3>[ 2.857329] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10614 10:56:11.908546 <6>[ 2.872744] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10615 10:56:11.915134 <6>[ 2.879523] xhci-mtk 11200000.usb: xHCI Host Controller
10616 10:56:11.921892 <6>[ 2.885034] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10617 10:56:11.931661 <6>[ 2.892893] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 10:56:11.938307 <6>[ 2.902325] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10619 10:56:11.945383 <6>[ 2.908552] xhci-mtk 11200000.usb: xHCI Host Controller
10620 10:56:11.951648 <6>[ 2.914052] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10621 10:56:11.958359 <6>[ 2.921710] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10622 10:56:11.965403 <6>[ 2.929616] hub 1-0:1.0: USB hub found
10623 10:56:11.968359 <6>[ 2.933668] hub 1-0:1.0: 1 port detected
10624 10:56:11.978047 <6>[ 2.937997] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10625 10:56:11.981701 <6>[ 2.946811] hub 2-0:1.0: USB hub found
10626 10:56:11.984718 <6>[ 2.950869] hub 2-0:1.0: 1 port detected
10627 10:56:11.993784 <6>[ 2.957954] mtk-msdc 11f70000.mmc: Got CD GPIO
10628 10:56:12.014137 <6>[ 2.975588] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10629 10:56:12.021678 <6>[ 2.983740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10630 10:56:12.030874 <4>[ 2.991724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10631 10:56:12.040937 <6>[ 3.001416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10632 10:56:12.047655 <6>[ 3.009504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10633 10:56:12.057862 <6>[ 3.017571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10634 10:56:12.063951 <6>[ 3.025504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10635 10:56:12.071114 <6>[ 3.033371] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10636 10:56:12.080394 <6>[ 3.041203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10637 10:56:12.091283 <6>[ 3.051977] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10638 10:56:12.100741 <6>[ 3.060346] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10639 10:56:12.107837 <6>[ 3.068730] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10640 10:56:12.117241 <6>[ 3.077077] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10641 10:56:12.124023 <6>[ 3.085446] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10642 10:56:12.133961 <6>[ 3.093791] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10643 10:56:12.140462 <6>[ 3.102159] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10644 10:56:12.150679 <6>[ 3.110503] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10645 10:56:12.157172 <6>[ 3.118867] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10646 10:56:12.167009 <6>[ 3.127212] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10647 10:56:12.173956 <6>[ 3.135554] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10648 10:56:12.183848 <6>[ 3.143898] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10649 10:56:12.190529 <6>[ 3.152241] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10650 10:56:12.200203 <6>[ 3.160585] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10651 10:56:12.207398 <6>[ 3.168928] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10652 10:56:12.213502 <6>[ 3.177816] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10653 10:56:12.220906 <6>[ 3.185209] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10654 10:56:12.227894 <6>[ 3.192241] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10655 10:56:12.237981 <6>[ 3.199336] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10656 10:56:12.244487 <6>[ 3.206638] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10657 10:56:12.254592 <6>[ 3.213548] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10658 10:56:12.261900 <6>[ 3.222689] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10659 10:56:12.271789 <6>[ 3.231862] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10660 10:56:12.281644 <6>[ 3.241291] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10661 10:56:12.291515 <6>[ 3.250770] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10662 10:56:12.301091 <6>[ 3.260246] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10663 10:56:12.307928 <6>[ 3.269373] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10664 10:56:12.317493 <6>[ 3.278849] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10665 10:56:12.327828 <6>[ 3.287975] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10666 10:56:12.337752 <6>[ 3.297278] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10667 10:56:12.347700 <6>[ 3.307463] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10668 10:56:12.357493 <6>[ 3.318844] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10669 10:56:12.404735 <6>[ 3.366321] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10670 10:56:12.558850 <6>[ 3.523754] hub 1-1:1.0: USB hub found
10671 10:56:12.562124 <6>[ 3.528183] hub 1-1:1.0: 4 ports detected
10672 10:56:12.685296 <6>[ 3.646464] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10673 10:56:12.709055 <6>[ 3.673846] hub 2-1:1.0: USB hub found
10674 10:56:12.712306 <6>[ 3.678229] hub 2-1:1.0: 3 ports detected
10675 10:56:12.884718 <6>[ 3.846317] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10676 10:56:13.018235 <6>[ 3.982522] hub 1-1.4:1.0: USB hub found
10677 10:56:13.021016 <6>[ 3.987158] hub 1-1.4:1.0: 2 ports detected
10678 10:56:13.097137 <6>[ 4.058573] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10679 10:56:13.316673 <6>[ 4.278315] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 10:56:13.508668 <6>[ 4.470314] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 10:56:24.657333 <6>[ 15.626866] ALSA device list:
10682 10:56:24.663893 <6>[ 15.630122] No soundcards found.
10683 10:56:24.676579 <6>[ 15.642542] Freeing unused kernel memory: 8384K
10684 10:56:24.679701 <6>[ 15.647474] Run /init as init process
10685 10:56:24.709584 <6>[ 15.675914] NET: Registered PF_INET6 protocol family
10686 10:56:24.716180 <6>[ 15.682128] Segment Routing with IPv6
10687 10:56:24.719514 <6>[ 15.686057] In-situ OAM (IOAM) with IPv6
10688 10:56:24.753842 <30>[ 15.700626] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10689 10:56:24.757157 <30>[ 15.724454] systemd[1]: Detected architecture arm64.
10690 10:56:24.757242
10691 10:56:24.764260 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10692 10:56:24.764339
10693 10:56:24.779994 <30>[ 15.746411] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10694 10:56:24.933293 <30>[ 15.896387] systemd[1]: Queued start job for default target Graphical Interface.
10695 10:56:24.949569 <30>[ 15.915565] systemd[1]: Created slice system-getty.slice.
10696 10:56:24.956036 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10697 10:56:24.972633 <30>[ 15.938956] systemd[1]: Created slice system-modprobe.slice.
10698 10:56:24.979037 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10699 10:56:24.997254 <30>[ 15.963458] systemd[1]: Created slice system-serial\x2dgetty.slice.
10700 10:56:25.007387 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10701 10:56:25.020315 <30>[ 15.986810] systemd[1]: Created slice User and Session Slice.
10702 10:56:25.026948 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10703 10:56:25.047822 <30>[ 16.010879] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10704 10:56:25.054811 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10705 10:56:25.075564 <30>[ 16.038476] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10706 10:56:25.081903 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10707 10:56:25.102760 <30>[ 16.062451] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10708 10:56:25.109602 <30>[ 16.074493] systemd[1]: Reached target Local Encrypted Volumes.
10709 10:56:25.115775 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10710 10:56:25.132224 <30>[ 16.098687] systemd[1]: Reached target Paths.
10711 10:56:25.136104 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10712 10:56:25.151931 <30>[ 16.118371] systemd[1]: Reached target Remote File Systems.
10713 10:56:25.158529 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10714 10:56:25.175981 <30>[ 16.142595] systemd[1]: Reached target Slices.
10715 10:56:25.182438 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10716 10:56:25.196308 <30>[ 16.162383] systemd[1]: Reached target Swap.
10717 10:56:25.199603 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10718 10:56:25.219514 <30>[ 16.182681] systemd[1]: Listening on initctl Compatibility Named Pipe.
10719 10:56:25.225924 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10720 10:56:25.233226 <30>[ 16.197386] systemd[1]: Listening on Journal Audit Socket.
10721 10:56:25.239683 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10722 10:56:25.252307 <30>[ 16.218629] systemd[1]: Listening on Journal Socket (/dev/log).
10723 10:56:25.258593 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10724 10:56:25.277003 <30>[ 16.243123] systemd[1]: Listening on Journal Socket.
10725 10:56:25.283543 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10726 10:56:25.299743 <30>[ 16.262758] systemd[1]: Listening on Network Service Netlink Socket.
10727 10:56:25.306327 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10728 10:56:25.320762 <30>[ 16.287091] systemd[1]: Listening on udev Control Socket.
10729 10:56:25.327565 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10730 10:56:25.344725 <30>[ 16.311024] systemd[1]: Listening on udev Kernel Socket.
10731 10:56:25.351272 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10732 10:56:25.388616 <30>[ 16.354703] systemd[1]: Mounting Huge Pages File System...
10733 10:56:25.394950 Mounting [0;1;39mHuge Pages File System[0m...
10734 10:56:25.410437 <30>[ 16.376593] systemd[1]: Mounting POSIX Message Queue File System...
10735 10:56:25.416882 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10736 10:56:25.433967 <30>[ 16.400479] systemd[1]: Mounting Kernel Debug File System...
10737 10:56:25.440450 Mounting [0;1;39mKernel Debug File System[0m...
10738 10:56:25.459797 <30>[ 16.422598] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10739 10:56:25.470384 <30>[ 16.433594] systemd[1]: Starting Create list of static device nodes for the current kernel...
10740 10:56:25.476904 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10741 10:56:25.494287 <30>[ 16.460663] systemd[1]: Starting Load Kernel Module configfs...
10742 10:56:25.500641 Starting [0;1;39mLoad Kernel Module configfs[0m...
10743 10:56:25.518066 <30>[ 16.484634] systemd[1]: Starting Load Kernel Module drm...
10744 10:56:25.524983 Starting [0;1;39mLoad Kernel Module drm[0m...
10745 10:56:25.543161 <30>[ 16.506543] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10746 10:56:25.553994 <30>[ 16.520233] systemd[1]: Starting Journal Service...
10747 10:56:25.557266 Starting [0;1;39mJournal Service[0m...
10748 10:56:25.574555 <30>[ 16.541106] systemd[1]: Starting Load Kernel Modules...
10749 10:56:25.581094 Starting [0;1;39mLoad Kernel Modules[0m...
10750 10:56:25.602464 <30>[ 16.565398] systemd[1]: Starting Remount Root and Kernel File Systems...
10751 10:56:25.608868 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10752 10:56:25.626813 <30>[ 16.593055] systemd[1]: Starting Coldplug All udev Devices...
10753 10:56:25.633374 Starting [0;1;39mColdplug All udev Devices[0m...
10754 10:56:25.650937 <30>[ 16.616903] systemd[1]: Mounted Huge Pages File System.
10755 10:56:25.657355 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10756 10:56:25.672662 <30>[ 16.639022] systemd[1]: Started Journal Service.
10757 10:56:25.679012 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10758 10:56:25.693833 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10759 10:56:25.709594 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10760 10:56:25.728500 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10761 10:56:25.745580 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10762 10:56:25.761447 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10763 10:56:25.777606 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10764 10:56:25.801607 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10765 10:56:25.816229 See 'systemctl status systemd-remount-fs.service' for details.
10766 10:56:25.876360 Mounting [0;1;39mKernel Configuration File System[0m...
10767 10:56:25.898975 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10768 10:56:25.916077 <46>[ 16.879343] systemd-journald[178]: Received client request to flush runtime journal.
10769 10:56:25.925050 Starting [0;1;39mLoad/Save Random Seed[0m...
10770 10:56:25.943525 Starting [0;1;39mApply Kernel Variables[0m...
10771 10:56:25.958634 Starting [0;1;39mCreate System Users[0m...
10772 10:56:25.974280 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10773 10:56:25.996356 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10774 10:56:26.009554 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10775 10:56:26.025528 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10776 10:56:26.040856 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10777 10:56:26.057033 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10778 10:56:26.108723 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10779 10:56:26.131926 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10780 10:56:26.144098 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10781 10:56:26.160236 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10782 10:56:26.178775 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10783 10:56:26.203689 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10784 10:56:26.225320 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10785 10:56:26.244682 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10786 10:56:26.289666 Starting [0;1;39mNetwork Service[0m...
10787 10:56:26.310345 Starting [0;1;39mNetwork Time Synchronization[0m...
10788 10:56:26.329867 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10789 10:56:26.371884 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10790 10:56:26.385721 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10791 10:56:26.409534 Starting [0;1;39mNetwork Name Resolution[0m...
10792 10:56:26.424739 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10793 10:56:26.467124 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10794 10:56:26.480975 <3>[ 17.444397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 10:56:26.487935 <6>[ 17.450506] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10796 10:56:26.497810 <3>[ 17.453065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 10:56:26.504537 <6>[ 17.460517] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10798 10:56:26.514304 <3>[ 17.468213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 10:56:26.520865 <6>[ 17.468739] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10800 10:56:26.530775 <6>[ 17.477491] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10801 10:56:26.544611 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<3>[ 17.506303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 10:56:26.544696
10803 10:56:26.547710 <6>[ 17.508281] remoteproc remoteproc0: scp is available
10804 10:56:26.557604 <3>[ 17.515173] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10805 10:56:26.563998 <6>[ 17.518290] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10806 10:56:26.570690 <6>[ 17.521842] remoteproc remoteproc0: powering up scp
10807 10:56:26.577385 <3>[ 17.528594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 10:56:26.587243 <3>[ 17.528613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 10:56:26.593967 <6>[ 17.536265] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10810 10:56:26.604057 <3>[ 17.541421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 10:56:26.607154 <6>[ 17.549494] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10812 10:56:26.617253 <4>[ 17.568608] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10813 10:56:26.620417 <4>[ 17.568608] Fallback method does not support PEC.
10814 10:56:26.630393 <4>[ 17.583937] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10815 10:56:26.640268 [[0;32m OK [0m] Reached targ<4>[ 17.602607] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10816 10:56:26.647490 <3>[ 17.605361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 10:56:26.660991 et [0;1;39mSystem Time Synchron<3>[ 17.620786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 10:56:26.661075 ized[0m.
10819 10:56:26.671023 <3>[ 17.632544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 10:56:26.677324 <6>[ 17.634181] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10821 10:56:26.684046 <3>[ 17.640979] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 10:56:26.690616 <6>[ 17.643454] usbcore: registered new interface driver r8152
10823 10:56:26.697310 <6>[ 17.647973] pci_bus 0000:00: root bus resource [bus 00-ff]
10824 10:56:26.700410 <6>[ 17.648407] mc: Linux media interface: v0.10
10825 10:56:26.710660 <3>[ 17.655913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 10:56:26.717500 <3>[ 17.660157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 10:56:26.723596 <6>[ 17.662161] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10828 10:56:26.733600 <3>[ 17.667493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 10:56:26.740818 <3>[ 17.667505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 10:56:26.750637 <3>[ 17.667518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 10:56:26.757025 <3>[ 17.667526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 10:56:26.767015 <3>[ 17.668100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 10:56:26.770237 <6>[ 17.668853] videodev: Linux video capture interface: v2.00
10834 10:56:26.780187 <6>[ 17.672632] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10835 10:56:26.786700 <6>[ 17.752885] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10836 10:56:26.797067 <6>[ 17.752924] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10837 10:56:26.803428 <6>[ 17.752932] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10838 10:56:26.813072 <6>[ 17.755713] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10839 10:56:26.820408 <6>[ 17.759383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10840 10:56:26.830278 <6>[ 17.761408] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10841 10:56:26.839700 <6>[ 17.763037] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10842 10:56:26.846753 <6>[ 17.763044] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10843 10:56:26.854376 <6>[ 17.767756] remoteproc remoteproc0: remote processor scp is now up
10844 10:56:26.857624 <6>[ 17.774899] pci 0000:00:00.0: supports D1 D2
10845 10:56:26.864690 <6>[ 17.798436] usbcore: registered new interface driver cdc_ether
10846 10:56:26.871238 <6>[ 17.801720] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10847 10:56:26.880826 <6>[ 17.805387] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10848 10:56:26.888377 <6>[ 17.811204] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10849 10:56:26.891745 <6>[ 17.812518] Bluetooth: Core ver 2.22
10850 10:56:26.895514 <6>[ 17.812595] NET: Registered PF_BLUETOOTH protocol family
10851 10:56:26.902172 <6>[ 17.812598] Bluetooth: HCI device and connection manager initialized
10852 10:56:26.908570 <6>[ 17.812614] Bluetooth: HCI socket layer initialized
10853 10:56:26.912017 <6>[ 17.812620] Bluetooth: L2CAP socket layer initialized
10854 10:56:26.919319 <6>[ 17.812630] Bluetooth: SCO socket layer initialized
10855 10:56:26.925658 <6>[ 17.821318] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10856 10:56:26.932282 <6>[ 17.826019] usbcore: registered new interface driver r8153_ecm
10857 10:56:26.938948 <6>[ 17.831280] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10858 10:56:26.949586 <3>[ 17.836913] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 10:56:26.955967 <6>[ 17.843828] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10860 10:56:26.963269 <6>[ 17.844413] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10861 10:56:26.969601 <6>[ 17.844651] usbcore: registered new interface driver btusb
10862 10:56:26.979758 <4>[ 17.845207] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10863 10:56:26.986716 <3>[ 17.845223] Bluetooth: hci0: Failed to load firmware file (-2)
10864 10:56:26.989948 <3>[ 17.845227] Bluetooth: hci0: Failed to set up firmware (-2)
10865 10:56:26.999873 <4>[ 17.845231] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10866 10:56:27.013921 <6>[ 17.847126] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10867 10:56:27.020631 <6>[ 17.847333] usbcore: registered new interface driver uvcvideo
10868 10:56:27.027088 <3>[ 17.852120] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10869 10:56:27.037305 <4>[ 17.857190] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10870 10:56:27.044725 <4>[ 17.857200] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10871 10:56:27.050815 <6>[ 17.858716] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10872 10:56:27.057313 <6>[ 17.859609] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10873 10:56:27.067570 <3>[ 17.862431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 10:56:27.074681 <3>[ 17.863149] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10875 10:56:27.081394 <6>[ 17.868106] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10876 10:56:27.091562 <3>[ 17.887960] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 10:56:27.095651 <6>[ 17.890392] pci 0000:01:00.0: supports D1 D2
10878 10:56:27.102355 <6>[ 17.918211] r8152 2-1.3:1.0 eth0: v1.12.13
10879 10:56:27.108621 <6>[ 17.919635] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10880 10:56:27.115564 <3>[ 17.920033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 10:56:27.122477 <6>[ 17.939064] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10882 10:56:27.132796 <3>[ 17.940613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 10:56:27.136066 <6>[ 17.950276] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10884 10:56:27.146375 <6>[ 17.950308] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10885 10:56:27.153111 <6>[ 17.950316] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10886 10:56:27.163065 <6>[ 17.950330] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10887 10:56:27.169460 <6>[ 17.950347] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10888 10:56:27.179378 <6>[ 17.950362] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10889 10:56:27.183208 <6>[ 17.950377] pci 0000:00:00.0: PCI bridge to [bus 01]
10890 10:56:27.189752 <6>[ 17.950384] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10891 10:56:27.196150 <6>[ 17.950598] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10892 10:56:27.206017 <3>[ 17.976450] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 10:56:27.213022 <6>[ 17.986109] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10894 10:56:27.222468 <3>[ 18.014556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 10:56:27.225731 <6>[ 18.016897] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10896 10:56:27.236035 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10897 10:56:27.247707 <5>[ 18.210729] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10898 10:56:27.253967 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10899 10:56:27.267270 <5>[ 18.230376] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10900 10:56:27.273649 <4>[ 18.237476] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10901 10:56:27.280663 <6>[ 18.246375] cfg80211: failed to load regulatory.db
10902 10:56:27.287109 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10903 10:56:27.307792 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10904 10:56:27.326367 <6>[ 18.289662] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10905 10:56:27.333184 <6>[ 18.297194] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10906 10:56:27.357701 <6>[ 18.324164] mt7921e 0000:01:00.0: ASIC revision: 79610010
10907 10:56:27.462043 <4>[ 18.421872] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 10:56:27.491306 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10909 10:56:27.507832 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10910 10:56:27.527152 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10911 10:56:27.539513 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10912 10:56:27.559387 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10913 10:56:27.580858 <4>[ 18.540761] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10914 10:56:27.587392 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10915 10:56:27.594474 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10916 10:56:27.611758 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10917 10:56:27.624173 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10918 10:56:27.639775 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10919 10:56:27.659654 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10920 10:56:27.700610 <4>[ 18.660849] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10921 10:56:27.707506 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10922 10:56:27.735463 Starting [0;1;39mUser Login Management[0m...
10923 10:56:27.753820 Starting [0;1;39mPermit User Sessions[0m...
10924 10:56:27.771689 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10925 10:56:27.788314 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10926 10:56:27.809332 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10927 10:56:27.822581 <4>[ 18.782780] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 10:56:27.864574 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10929 10:56:27.883191 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10930 10:56:27.900163 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10931 10:56:27.917491 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10932 10:56:27.924430 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10933 10:56:27.947508 [[0;32m OK [<4>[ 18.908835] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 10:56:27.954022 0m] Reached target [0;1;39mGraphical Interface[0m.
10935 10:56:28.012128 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10936 10:56:28.039897 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10937 10:56:28.068812 <4>[ 19.028622] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10938 10:56:28.088554
10939 10:56:28.088641
10940 10:56:28.091668 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10941 10:56:28.091747
10942 10:56:28.094985 debian-bullseye-arm64 login: root (automatic login)
10943 10:56:28.095084
10944 10:56:28.095180
10945 10:56:28.111232 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:34:17 UTC 2023 aarch64
10946 10:56:28.111321
10947 10:56:28.118335 The programs included with the Debian GNU/Linux system are free software;
10948 10:56:28.124667 the exact distribution terms for each program are described in the
10949 10:56:28.127789 individual files in /usr/share/doc/*/copyright.
10950 10:56:28.127865
10951 10:56:28.134875 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10952 10:56:28.134952 permitted by applicable law.
10953 10:56:28.135290 Matched prompt #10: / #
10955 10:56:28.135550 Setting prompt string to ['/ #']
10956 10:56:28.135644 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10958 10:56:28.135848 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10959 10:56:28.135943 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10960 10:56:28.136017 Setting prompt string to ['/ #']
10961 10:56:28.136078 Forcing a shell prompt, looking for ['/ #']
10963 10:56:28.186277 / #
10964 10:56:28.186395 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10965 10:56:28.186490 Waiting using forced prompt support (timeout 00:02:30)
10966 10:56:28.186592 <4>[ 19.136597] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 10:56:28.191331
10968 10:56:28.191649 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10969 10:56:28.191747 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10970 10:56:28.191840 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10971 10:56:28.191937 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10972 10:56:28.192020 end: 2 depthcharge-action (duration 00:01:26) [common]
10973 10:56:28.192109 start: 3 lava-test-retry (timeout 00:08:14) [common]
10974 10:56:28.192210 start: 3.1 lava-test-shell (timeout 00:08:14) [common]
10975 10:56:28.192283 Using namespace: common
10977 10:56:28.292582 / # #
10978 10:56:28.292834 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10979 10:56:28.335517 #<4>[ 19.256692] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10980 10:56:28.335748
10981 10:56:28.336089 Using /lava-10590987
10983 10:56:28.436534 / # export SHELL=/bin/sh
10984 10:56:28.436720 export SHELL=/bin/sh<4>[ 19.376509] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 10:56:28.441539
10987 10:56:28.542051 / # . /lava-10590987/environment
10988 10:56:28.542218 . /lava-10590987/environment<4>[ 19.496198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 10:56:28.547297
10991 10:56:28.688126 / # /lava-10590987/bin/lava-test-runner /lava-10590987/0
10992 10:56:28.688261 Test shell timeout: 10s (minimum of the action and connection timeout)
10993 10:56:28.688580 <6>[ 19.590532] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10994 10:56:28.688657 <6>[ 19.598459] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10995 10:56:28.688722 /lava-10590987/bin/lava-test-runner /lava-105909<3>[ 19.617632] mt7921e 0000:01:00.0: hardware init failed
10996 10:56:28.693554 87/0
10997 10:56:28.735481 + export TESTRUN_ID=0_v4l2-compliance-uvc
10998 10:56:28.735567 + cd /lava-10590987/0/tests/0_v4l2-compliance-uvc
10999 10:56:28.735634 + cat uuid
11000 10:56:28.735695 + UUID=10590987_1.5.2.3.1
11001 10:56:28.735753 + set +x
11002 10:56:28.735813 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10590987_1.5.2.3.1>
11003 10:56:28.735870 + /usr/bin/v4l2-parser.sh -d uvcvideo
11004 10:56:28.736101 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10590987_1.5.2.3.1
11005 10:56:28.736169 Starting test lava.0_v4l2-compliance-uvc (10590987_1.5.2.3.1)
11006 10:56:28.736244 Skipping test definition patterns.
11007 10:56:28.739380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11008 10:56:28.739462 device: /dev/video0
11009 10:56:28.739697 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11011 10:56:32.807800 <4>[ 23.774757] ------------[ cut here ]------------
11012 10:56:32.814173 <4>[ 23.779697] get_vaddr_frames() cannot follow VM_IO mapping
11013 10:56:32.827547 <4>[ 23.779849] WARNING: CPU: 5 PID: 305 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11014 10:56:32.874006 <4>[ 23.797952] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common btusb mtk_vpu uvcvideo v4l2_mem2mem btintel btmtk videobuf2_dma_contig btrtl videobuf2_vmalloc btbcm r8153_ecm videobuf2_memops bluetooth videobuf2_v4l2 cdc_ether videobuf2_common usbnet ecdh_generic cros_ec_rpmsg videodev crct10dif_ce mc r8152 elan_i2c ecc elants_i2c rfkill hid_google_hammer sbs_battery pcie_mediatek_gen3 cros_ec_chardev mtk_scp mtk_rpmsg hid_vivaldi_common cros_ec_typec mtk_scp_ipi ip_tables x_tables ipv6
11015 10:56:32.880339 <4>[ 23.847339] CPU: 5 PID: 305 Comm: v4l2-compliance Not tainted 6.1.31 #1
11016 10:56:32.887177 <4>[ 23.854205] Hardware name: Google Spherion (rev0 - 3) (DT)
11017 10:56:32.893857 <4>[ 23.859941] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11018 10:56:32.899948 <4>[ 23.867154] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11019 10:56:32.907231 <4>[ 23.873251] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11020 10:56:32.910252 <4>[ 23.879347] sp : ffff8000091ab810
11021 10:56:32.916702 <4>[ 23.882911] x29: ffff8000091ab810 x28: ffffc295bdbe1000 x27: ffffc295bdbdd238
11022 10:56:32.926857 <4>[ 23.890300] x26: 0000000000000000 x25: ffffc295bdbe14c0 x24: ffff1dcb00174538
11023 10:56:32.933163 <4>[ 23.897687] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11024 10:56:32.939734 <4>[ 23.905075] x20: 00000000fffffff2 x19: ffff1dcb0ba38000 x18: fffffffffffe9520
11025 10:56:32.946591 <4>[ 23.912463] x17: 0000000000000000 x16: ffffc2962ae8bb60 x15: 0000000000000038
11026 10:56:32.956397 <4>[ 23.919850] x14: ffffc2962d5c34a8 x13: 0000000000000636 x12: 0000000000000212
11027 10:56:32.963316 <4>[ 23.927237] x11: fffffffffffe9520 x10: fffffffffffe94e8 x9 : 00000000fffff212
11028 10:56:32.969886 <4>[ 23.934625] x8 : ffffc2962d5c34a8 x7 : ffffc2962d61b4a8 x6 : 00000000000018d8
11029 10:56:32.976582 <4>[ 23.942011] x5 : ffff1dcc3ef7ba18 x4 : 00000000fffff212 x3 : ffff5b3612079000
11030 10:56:32.983605 <4>[ 23.949398] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff1dcb0ea10ec0
11031 10:56:32.986636 <4>[ 23.956785] Call trace:
11032 10:56:32.993182 <4>[ 23.959482] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11033 10:56:32.999578 <4>[ 23.965231] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11034 10:56:33.006220 <4>[ 23.971236] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11035 10:56:33.012885 <4>[ 23.977764] __prepare_userptr+0x280/0x410 [videobuf2_common]
11036 10:56:33.016677 <4>[ 23.983774] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11037 10:56:33.023035 <4>[ 23.989437] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11038 10:56:33.026292 <4>[ 23.995099] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11039 10:56:33.032920 <4>[ 23.999988] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11040 10:56:33.036194 <4>[ 24.005055] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11041 10:56:33.042753 <4>[ 24.009937] v4l_qbuf+0x48/0x60 [videodev]
11042 10:56:33.046503 <4>[ 24.014359] __video_do_ioctl+0x184/0x3d0 [videodev]
11043 10:56:33.053315 <4>[ 24.019609] video_usercopy+0x358/0x680 [videodev]
11044 10:56:33.056456 <4>[ 24.024685] video_ioctl2+0x18/0x30 [videodev]
11045 10:56:33.063338 <4>[ 24.029413] v4l2_ioctl+0x40/0x60 [videodev]
11046 10:56:33.066661 <4>[ 24.033967] __arm64_sys_ioctl+0xa8/0xf0
11047 10:56:33.069731 <4>[ 24.038148] invoke_syscall+0x48/0x114
11048 10:56:33.076121 <4>[ 24.042158] el0_svc_common.constprop.0+0x44/0xec
11049 10:56:33.079849 <4>[ 24.047118] do_el0_svc+0x2c/0xd0
11050 10:56:33.083148 <4>[ 24.050687] el0_svc+0x2c/0x84
11051 10:56:33.086416 <4>[ 24.054001] el0t_64_sync_handler+0xb8/0xc0
11052 10:56:33.089603 <4>[ 24.058439] el0t_64_sync+0x18c/0x190
11053 10:56:33.095834 <4>[ 24.062354] ---[ end trace 0000000000000000 ]---
11054 10:56:35.515167 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11055 10:56:35.525754 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11056 10:56:35.532089
11057 10:56:35.544255 Compliance test for uvcvideo device /dev/video0:
11058 10:56:35.550260
11059 10:56:35.559607 Driver Info:
11060 10:56:35.569664 Driver name : uvcvideo
11061 10:56:35.583191 Card type : HD User Facing: HD User Facing
11062 10:56:35.592158 Bus info : usb-11200000.usb-1.4.1
11063 10:56:35.598535 Driver version : 6.1.31
11064 10:56:35.609520 Capabilities : 0x84a00001
11065 10:56:35.622780 Metadata Capture
11066 10:56:35.633524 Streaming
11067 10:56:35.643418 Extended Pix Format
11068 10:56:35.653057 Device Capabilities
11069 10:56:35.662570 Device Caps : 0x04200001
11070 10:56:35.674872 Streaming
11071 10:56:35.683864 Extended Pix Format
11072 10:56:35.693603 Media Driver Info:
11073 10:56:35.702540 Driver name : uvcvideo
11074 10:56:35.716430 Model : HD User Facing: HD User Facing
11075 10:56:35.722144 Serial : 200901010001
11076 10:56:35.735704 Bus info : usb-11200000.usb-1.4.1
11077 10:56:35.741252 Media version : 6.1.31
11078 10:56:35.754376 Hardware revision: 0x00009758 (38744)
11079 10:56:35.760073 Driver version : 6.1.31
11080 10:56:35.770054 Interface Info:
11081 10:56:35.785274 <LAVA_SIGNAL_TESTSET START Interface-Info>
11082 10:56:35.785358 ID : 0x03000002
11083 10:56:35.785604 Received signal: <TESTSET> START Interface-Info
11084 10:56:35.785692 Starting test_set Interface-Info
11085 10:56:35.794518 Type : V4L Video
11086 10:56:35.804290 Entity Info:
11087 10:56:35.810080 <LAVA_SIGNAL_TESTSET STOP>
11088 10:56:35.810356 Received signal: <TESTSET> STOP
11089 10:56:35.810430 Closing test_set Interface-Info
11090 10:56:35.819316 <LAVA_SIGNAL_TESTSET START Entity-Info>
11091 10:56:35.819576 Received signal: <TESTSET> START Entity-Info
11092 10:56:35.819647 Starting test_set Entity-Info
11093 10:56:35.822511 ID : 0x00000001 (1)
11094 10:56:35.832599 Name : HD User Facing: HD User Facing
11095 10:56:35.839415 Function : V4L2 I/O
11096 10:56:35.850528 Flags : default
11097 10:56:35.860517 Pad 0x01000007 : 0: Sink
11098 10:56:35.880644 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11099 10:56:35.880732
11100 10:56:35.891538 Required ioctls:
11101 10:56:35.898660 <LAVA_SIGNAL_TESTSET STOP>
11102 10:56:35.898915 Received signal: <TESTSET> STOP
11103 10:56:35.898983 Closing test_set Entity-Info
11104 10:56:35.909096 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11105 10:56:35.909347 Received signal: <TESTSET> START Required-ioctls
11106 10:56:35.909415 Starting test_set Required-ioctls
11107 10:56:35.912248 test MC information (see 'Media Driver Info' above): OK
11108 10:56:35.936578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11109 10:56:35.936830 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11111 10:56:35.939743 test VIDIOC_QUERYCAP: OK
11112 10:56:35.958084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 10:56:35.958337 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 10:56:35.961377 test invalid ioctls: OK
11116 10:56:35.983539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11117 10:56:35.983625
11118 10:56:35.983859 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11120 10:56:35.992909 Allow for multiple opens:
11121 10:56:35.999794 <LAVA_SIGNAL_TESTSET STOP>
11122 10:56:36.000044 Received signal: <TESTSET> STOP
11123 10:56:36.000112 Closing test_set Required-ioctls
11124 10:56:36.008474 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11125 10:56:36.008734 Received signal: <TESTSET> START Allow-for-multiple-opens
11126 10:56:36.008812 Starting test_set Allow-for-multiple-opens
11127 10:56:36.011743 test second /dev/video0 open: OK
11128 10:56:36.032952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11129 10:56:36.033202 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11131 10:56:36.036274 test VIDIOC_QUERYCAP: OK
11132 10:56:36.057438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11133 10:56:36.057692 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11135 10:56:36.060485 test VIDIOC_G/S_PRIORITY: OK
11136 10:56:36.080872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11137 10:56:36.081123 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11139 10:56:36.083495 test for unlimited opens: OK
11140 10:56:36.105481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11141 10:56:36.105573
11142 10:56:36.105808 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11144 10:56:36.117142 Debug ioctls:
11145 10:56:36.124221 <LAVA_SIGNAL_TESTSET STOP>
11146 10:56:36.124475 Received signal: <TESTSET> STOP
11147 10:56:36.124550 Closing test_set Allow-for-multiple-opens
11148 10:56:36.133833 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11149 10:56:36.134084 Received signal: <TESTSET> START Debug-ioctls
11150 10:56:36.134154 Starting test_set Debug-ioctls
11151 10:56:36.137661 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11152 10:56:36.159122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11153 10:56:36.159345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11155 10:56:36.165707 test VIDIOC_LOG_STATUS: OK (Not Supported)
11156 10:56:36.184229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11157 10:56:36.184312
11158 10:56:36.184545 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11160 10:56:36.193811 Input ioctls:
11161 10:56:36.201510 <LAVA_SIGNAL_TESTSET STOP>
11162 10:56:36.201759 Received signal: <TESTSET> STOP
11163 10:56:36.201825 Closing test_set Debug-ioctls
11164 10:56:36.210686 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11165 10:56:36.210961 Received signal: <TESTSET> START Input-ioctls
11166 10:56:36.211037 Starting test_set Input-ioctls
11167 10:56:36.213895 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11168 10:56:36.238774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11169 10:56:36.239025 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11171 10:56:36.242120 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 10:56:36.261248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 10:56:36.261497 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 10:56:36.268038 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11176 10:56:36.286586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11177 10:56:36.286837 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11179 10:56:36.292891 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11180 10:56:36.311232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11181 10:56:36.311518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11183 10:56:36.314849 test VIDIOC_G/S/ENUMINPUT: OK
11184 10:56:36.336624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11185 10:56:36.336876 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11187 10:56:36.339813 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11188 10:56:36.361482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11189 10:56:36.361733 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11191 10:56:36.364576 Inputs: 1 Audio Inputs: 0 Tuners: 0
11192 10:56:36.372320
11193 10:56:36.389141 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11194 10:56:36.410230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11195 10:56:36.410488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11197 10:56:36.416483 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11198 10:56:36.433876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11199 10:56:36.434126 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11201 10:56:36.440479 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11202 10:56:36.457579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11203 10:56:36.457832 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11205 10:56:36.464046 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11206 10:56:36.481462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11207 10:56:36.481712 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11209 10:56:36.487606 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11210 10:56:36.505230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11211 10:56:36.505315
11212 10:56:36.505550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11214 10:56:36.522730 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11215 10:56:36.541741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11216 10:56:36.541993 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11218 10:56:36.548505 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11219 10:56:36.569590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11220 10:56:36.569841 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11222 10:56:36.573478 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11223 10:56:36.589995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11224 10:56:36.590248 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11226 10:56:36.592940 test VIDIOC_G/S_EDID: OK (Not Supported)
11227 10:56:36.613771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11228 10:56:36.613883
11229 10:56:36.614152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11231 10:56:36.624204 Control ioctls (Input 0):
11232 10:56:36.631527 <LAVA_SIGNAL_TESTSET STOP>
11233 10:56:36.631769 Received signal: <TESTSET> STOP
11234 10:56:36.631837 Closing test_set Input-ioctls
11235 10:56:36.641332 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11236 10:56:36.641580 Received signal: <TESTSET> START Control-ioctls-Input-0
11237 10:56:36.641675 Starting test_set Control-ioctls-Input-0
11238 10:56:36.644612 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11239 10:56:36.668489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11240 10:56:36.668572 test VIDIOC_QUERYCTRL: OK
11241 10:56:36.668807 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11243 10:56:36.689039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11244 10:56:36.689300 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11246 10:56:36.692243 test VIDIOC_G/S_CTRL: OK
11247 10:56:36.713710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11248 10:56:36.714024 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11250 10:56:36.716684 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11251 10:56:36.738715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11252 10:56:36.738991 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11254 10:56:36.745298 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11255 10:56:36.766909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11256 10:56:36.767165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11258 10:56:36.770474 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11259 10:56:36.789259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11260 10:56:36.789510 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11262 10:56:36.792247 Standard Controls: 16 Private Controls: 0
11263 10:56:36.798130
11264 10:56:36.807617 Format ioctls (Input 0):
11265 10:56:36.814399 <LAVA_SIGNAL_TESTSET STOP>
11266 10:56:36.814674 Received signal: <TESTSET> STOP
11267 10:56:36.814772 Closing test_set Control-ioctls-Input-0
11268 10:56:36.824473 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11269 10:56:36.824745 Received signal: <TESTSET> START Format-ioctls-Input-0
11270 10:56:36.824817 Starting test_set Format-ioctls-Input-0
11271 10:56:36.827696 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11272 10:56:36.851537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11273 10:56:36.851813 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11275 10:56:36.854537 test VIDIOC_G/S_PARM: OK
11276 10:56:36.871520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11277 10:56:36.871769 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11279 10:56:36.874595 test VIDIOC_G_FBUF: OK (Not Supported)
11280 10:56:36.896718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11281 10:56:36.896971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11283 10:56:36.900489 test VIDIOC_G_FMT: OK
11284 10:56:36.921370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11285 10:56:36.921645 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11287 10:56:36.924698 test VIDIOC_TRY_FMT: OK
11288 10:56:36.944844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11289 10:56:36.945098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11291 10:56:36.951392 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11292 10:56:36.955643 test VIDIOC_S_FMT: OK
11293 10:56:36.980439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11294 10:56:36.980695 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11296 10:56:36.983570 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11297 10:56:37.005135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11298 10:56:37.005398 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11300 10:56:37.008313 test Cropping: OK (Not Supported)
11301 10:56:37.029705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11302 10:56:37.029980 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11304 10:56:37.033309 test Composing: OK (Not Supported)
11305 10:56:37.054399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11306 10:56:37.054680 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11308 10:56:37.058234 test Scaling: OK (Not Supported)
11309 10:56:37.079154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11310 10:56:37.079257
11311 10:56:37.079563 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11313 10:56:37.088854 Codec ioctls (Input 0):
11314 10:56:37.095275 <LAVA_SIGNAL_TESTSET STOP>
11315 10:56:37.095570 Received signal: <TESTSET> STOP
11316 10:56:37.095639 Closing test_set Format-ioctls-Input-0
11317 10:56:37.105362 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11318 10:56:37.105636 Received signal: <TESTSET> START Codec-ioctls-Input-0
11319 10:56:37.105731 Starting test_set Codec-ioctls-Input-0
11320 10:56:37.109138 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11321 10:56:37.130749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11322 10:56:37.131015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11324 10:56:37.137244 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11325 10:56:37.153921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11326 10:56:37.154190 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11328 10:56:37.160131 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11329 10:56:37.178475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11330 10:56:37.178580
11331 10:56:37.178841 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11333 10:56:37.187167 Buffer ioctls (Input 0):
11334 10:56:37.193283 <LAVA_SIGNAL_TESTSET STOP>
11335 10:56:37.193533 Received signal: <TESTSET> STOP
11336 10:56:37.193629 Closing test_set Codec-ioctls-Input-0
11337 10:56:37.202224 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11338 10:56:37.202505 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11339 10:56:37.202591 Starting test_set Buffer-ioctls-Input-0
11340 10:56:37.206049 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11341 10:56:37.229002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11342 10:56:37.229086 test VIDIOC_EXPBUF: OK
11343 10:56:37.229323 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11345 10:56:37.250182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11346 10:56:37.250459 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11348 10:56:37.253115 test Requests: OK (Not Supported)
11349 10:56:37.276725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11350 10:56:37.276830
11351 10:56:37.277094 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11353 10:56:37.286168 Test input 0:
11354 10:56:37.296030
11355 10:56:37.306587 Streaming ioctls:
11356 10:56:37.313563 <LAVA_SIGNAL_TESTSET STOP>
11357 10:56:37.313837 Received signal: <TESTSET> STOP
11358 10:56:37.313935 Closing test_set Buffer-ioctls-Input-0
11359 10:56:37.322674 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11360 10:56:37.322947 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11361 10:56:37.323041 Starting test_set Streaming-ioctls_Test-input-0
11362 10:56:37.325770 test read/write: OK (Not Supported)
11363 10:56:37.346990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11364 10:56:37.347242 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11366 10:56:37.350303 test blocking wait: OK
11367 10:56:37.372951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11368 10:56:37.373200 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11370 10:56:37.382654 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11371 10:56:37.385768 test MMAP (no poll): FAIL
11372 10:56:37.408494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11373 10:56:37.408772 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11375 10:56:37.418217 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11376 10:56:37.418322 test MMAP (select): FAIL
11377 10:56:37.441600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11378 10:56:37.441879 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11380 10:56:37.452004 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11381 10:56:37.452110 test MMAP (epoll): FAIL
11382 10:56:37.476592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11383 10:56:37.476672
11384 10:56:37.476905 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11386 10:56:37.494068
11387 10:56:37.657679
11388 10:56:37.664815 test USERPTR (no poll): OK
11389 10:56:37.688757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11390 10:56:37.688868
11391 10:56:37.689139 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11393 10:56:37.701070
11394 10:56:37.869829
11395 10:56:37.876400 test USERPTR (select): OK
11396 10:56:37.900314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11397 10:56:37.900577 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11399 10:56:37.907000 test DMABUF: Cannot test, specify --expbuf-device
11400 10:56:37.911184
11401 10:56:37.928931 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11402 10:56:37.932088 <LAVA_TEST_RUNNER EXIT>
11403 10:56:37.932340 ok: lava_test_shell seems to have completed
11404 10:56:37.932412 Marking unfinished test run as failed
11406 10:56:37.933339 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11407 10:56:37.933481 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11408 10:56:37.933569 end: 3 lava-test-retry (duration 00:00:10) [common]
11409 10:56:37.933654 start: 4 finalize (timeout 00:08:05) [common]
11410 10:56:37.933743 start: 4.1 power-off (timeout 00:00:30) [common]
11411 10:56:37.933891 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11412 10:56:38.009737 >> Command sent successfully.
11413 10:56:38.012048 Returned 0 in 0 seconds
11414 10:56:38.112428 end: 4.1 power-off (duration 00:00:00) [common]
11416 10:56:38.112747 start: 4.2 read-feedback (timeout 00:08:04) [common]
11417 10:56:38.113006 Listened to connection for namespace 'common' for up to 1s
11418 10:56:39.113934 Finalising connection for namespace 'common'
11419 10:56:39.114128 Disconnecting from shell: Finalise
11420 10:56:39.114235 / #
11421 10:56:39.214570 end: 4.2 read-feedback (duration 00:00:01) [common]
11422 10:56:39.214769 end: 4 finalize (duration 00:00:01) [common]
11423 10:56:39.214920 Cleaning after the job
11424 10:56:39.215044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/ramdisk
11425 10:56:39.219505 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/kernel
11426 10:56:39.231089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/dtb
11427 10:56:39.231348 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10590987/tftp-deploy-k5gx8mcg/modules
11428 10:56:39.236783 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10590987
11429 10:56:39.301545 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10590987
11430 10:56:39.301718 Job finished correctly